From 0e0f828ad2af29d3d6e0ef7a0433bbf2b46af8b3 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Tue, 28 Jul 2026 18:03:24 +0200 Subject: [PATCH 1/9] Fix Phase-B capability contract --- docs/LSC1_TRANSACTION_PROTOCOL.md | 7 + docs/STATUS.md | 2 +- .../b2-capability-contract-20260728/README.md | 41 + .../SHA256SUMS | 43 + .../blake3_official.command | 1 + .../blake3_official.log | 5 + .../blake3_official.status | 2 + .../equivalence.command | 1 + .../equivalence.log | 71 + .../equivalence.status | 2 + .../equivalence_retry.command | 1 + .../equivalence_retry.log | 30021 ++++++++++++++++ .../equivalence_retry.status | 2 + .../lsc1_packet_frontend.netlist.v | 7201 ++++ .../metadata.txt | 4 + .../model.command | 1 + .../b2-capability-contract-20260728/model.log | 9 + .../model.status | 2 + .../model_final.command | 1 + .../model_final.log | 5 + .../model_final.status | 2 + .../mutation.command | 1 + .../mutation.log | 3 + .../mutation.status | 2 + .../mutation_final.command | 1 + .../mutation_final.log | 3 + .../mutation_final.status | 2 + .../netlist.command | 1 + .../netlist.log | 1328 + .../netlist.status | 2 + .../netlist_900.command | 1 + .../netlist_900.log | 22192 ++++++++++++ .../netlist_900.status | 2 + .../python_full.command | 1 + .../python_full.log | 302 + .../python_full.status | 2 + .../python_full_final.command | 1 + .../python_full_final.log | 302 + .../python_full_final.status | 2 + .../rtl.command | 1 + .../b2-capability-contract-20260728/rtl.log | 31 + .../rtl.status | 2 + .../rtl_final.command | 1 + .../rtl_final.log | 31 + .../rtl_final.status | 2 + .../b2-capability-contract-20260728/run.sh | 35 + sim/lsc1_transaction.py | 6 +- sim/test_lsc1_transaction.py | 3 +- sim/test_packet_frontend_rtl_differential.py | 6 +- test/packet_frontend/Makefile | 10 +- .../tb_lsc1_packet_frontend.sv | 8 +- 51 files changed, 61702 insertions(+), 6 deletions(-) create mode 100644 results/b2-capability-contract-20260728/README.md create mode 100644 results/b2-capability-contract-20260728/SHA256SUMS create mode 100644 results/b2-capability-contract-20260728/blake3_official.command create mode 100644 results/b2-capability-contract-20260728/blake3_official.log create mode 100644 results/b2-capability-contract-20260728/blake3_official.status create mode 100644 results/b2-capability-contract-20260728/equivalence.command create mode 100644 results/b2-capability-contract-20260728/equivalence.log create mode 100644 results/b2-capability-contract-20260728/equivalence.status create mode 100644 results/b2-capability-contract-20260728/equivalence_retry.command create mode 100644 results/b2-capability-contract-20260728/equivalence_retry.log create mode 100644 results/b2-capability-contract-20260728/equivalence_retry.status create mode 100644 results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v create mode 100644 results/b2-capability-contract-20260728/metadata.txt create mode 100644 results/b2-capability-contract-20260728/model.command create mode 100644 results/b2-capability-contract-20260728/model.log create mode 100644 results/b2-capability-contract-20260728/model.status create mode 100644 results/b2-capability-contract-20260728/model_final.command create mode 100644 results/b2-capability-contract-20260728/model_final.log create mode 100644 results/b2-capability-contract-20260728/model_final.status create mode 100644 results/b2-capability-contract-20260728/mutation.command create mode 100644 results/b2-capability-contract-20260728/mutation.log create mode 100644 results/b2-capability-contract-20260728/mutation.status create mode 100644 results/b2-capability-contract-20260728/mutation_final.command create mode 100644 results/b2-capability-contract-20260728/mutation_final.log create mode 100644 results/b2-capability-contract-20260728/mutation_final.status create mode 100644 results/b2-capability-contract-20260728/netlist.command create mode 100644 results/b2-capability-contract-20260728/netlist.log create mode 100644 results/b2-capability-contract-20260728/netlist.status create mode 100644 results/b2-capability-contract-20260728/netlist_900.command create mode 100644 results/b2-capability-contract-20260728/netlist_900.log create mode 100644 results/b2-capability-contract-20260728/netlist_900.status create mode 100644 results/b2-capability-contract-20260728/python_full.command create mode 100644 results/b2-capability-contract-20260728/python_full.log create mode 100644 results/b2-capability-contract-20260728/python_full.status create mode 100644 results/b2-capability-contract-20260728/python_full_final.command create mode 100644 results/b2-capability-contract-20260728/python_full_final.log create mode 100644 results/b2-capability-contract-20260728/python_full_final.status create mode 100644 results/b2-capability-contract-20260728/rtl.command create mode 100644 results/b2-capability-contract-20260728/rtl.log create mode 100644 results/b2-capability-contract-20260728/rtl.status create mode 100644 results/b2-capability-contract-20260728/rtl_final.command create mode 100644 results/b2-capability-contract-20260728/rtl_final.log create mode 100644 results/b2-capability-contract-20260728/rtl_final.status create mode 100755 results/b2-capability-contract-20260728/run.sh diff --git a/docs/LSC1_TRANSACTION_PROTOCOL.md b/docs/LSC1_TRANSACTION_PROTOCOL.md index be9beb3..f260320 100644 --- a/docs/LSC1_TRANSACTION_PROTOCOL.md +++ b/docs/LSC1_TRANSACTION_PROTOCOL.md @@ -494,6 +494,13 @@ See [§11](#11-service-request-and-response-contract). Device feature bits: `0` forward-only profile, `1` interpreter-compatible profile, `2` BLAKE3 service offload. +The Phase-B packet RTL advertises only `0x00000002`: +`INTERPRETER_COMPAT`. It rejects `FORWARD_ONLY` negotiation and does not +implement BLAKE3 service offload. The executable model remains the frozen +semantic oracle for the broader profile and service contract, but reports this +Phase-B device envelope so model/RTL negotiation responses agree for the +supported interpreter-compatible profile. RTL rejects `FORWARD_ONLY`. + ### 8.5 `INFO` (status query) — 20 bytes | Offset | Type | Field | diff --git a/docs/STATUS.md b/docs/STATUS.md index c47dc61..0bd57bd 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -6,7 +6,7 @@ | MinCore arithmetic seed | historical/exercised seed | existing simulation/formal suites | | v1 transaction protocol | specified and executably modelled | `docs/LSC1_TRANSACTION_PROTOCOL.md`, `sim/lsc1_transaction.py` | | Lean v1 packet/transaction foundation | protocol-sized request/response round trips, request validation precedence, current-state index-range rejection, atomic staging, abort/reset, matching retirement and exactly-once behavior proved for a pure functional model | `lean/LeanVMBMinCore/{Packet,Transaction}.lean`; byte-stream/per-opcode decoding, instruction/next-state validation, CRC-32 instantiation, service states, and RTL/oracle refinement remain open | -| v1 scalar packet executor | SET/XOR/MUL/DEREF/JUMP implemented in RTL; BLAKE3 service pending | `asic_core/rtl/lsc1_packet_frontend.sv`, RTL differential tests | +| v1 scalar packet executor | Phase-B advertises interpreter-compatible only (`0x00000002`): SET/XOR/MUL/DEREF/JUMP implemented in RTL; FORWARD_ONLY and BLAKE3 service are not advertised | `asic_core/rtl/lsc1_packet_frontend.sv`, RTL differential tests | | Host runtime, SET/XOR/MUL/DEREF/JUMP transactions | driven against the executable endpoint; frozen fixture reaches full `MATCH` | `docs/HOST_RUNTIME.md`, `host/`, `sim/test_host_runtime.py` | | Host runtime, BLAKE3 | schema/model adapter prerequisites tested; compiler/runtime and production transport remain explicit unsupported paths | `host/blake3_service.py`, `sim/test_blake3_service.py` | | lean_compiler integration | artifact exported from the frozen compiler; `hints`/`main_frame`/`witness`/`trace` are `pub(crate)` upstream | `tools/lean_compiler_export.py`, `docs/HOST_RUNTIME.md` section 4 | diff --git a/results/b2-capability-contract-20260728/README.md b/results/b2-capability-contract-20260728/README.md new file mode 100644 index 0000000..2547b9d --- /dev/null +++ b/results/b2-capability-contract-20260728/README.md @@ -0,0 +1,41 @@ +# LSC-1 Phase-B2 capability-contract evidence + +Baseline independently verified before edits: +`fda85f5efc6f5b460d72204b4d9c0d882960ec29`, tree +`df42a6211828d856e9a21ba61ecc2cd1b9dc4e71`. + +The correction narrows the Phase-B advertised device capability to +`INTERPRETER_COMPAT` (`0x00000002`), matching the packet RTL. The model retains +its broader semantic-oracle profiles, while the model/RTL differential drives +the supported Phase-B profile and the RTL bench/mutation test drives the +unadvertised `FORWARD_ONLY` rejection. + +| Check | Exit | Duration | Artifact SHA-256 | +| --- | ---: | ---: | --- | +| official BLAKE3 differential | 0 | 1426 ms | `42b629a692f30c9bfb0fcff81a5eb4631efb576c1355485035dd6d8c50131631` (`blake3_official.log`) | +| repository Python suite | 0 | 11544 ms (288 tests) | `3f3a9d48fd3bfa56895994fed2a415312f4713bb6acbe81144ec9c2ab15f8757` (`python_full_final.log`) | +| model/RTL differential | 0 | 1110 ms | `d13aeaee319cce423e3c559504b2eff9e89be80f067b0a946a7c2edea31bd59e` (`model_final.log`) | +| bounded RTL simulation | 0 | 129 ms | `881d0c9e93dd2f29354bf42351533bfe1b571eb3f4e4f0198d92dc51fe4c064f` (`rtl_final.log`) | +| mutation regression | 0 | 400 ms | `73a36fd9d3c0bd6c193ab3bcfd546574a9f3b2945298b7589aa10584725877c2` (`mutation_final.log`) | +| RTL-to-netlist synthesis (`timeout 900s`) | 0 | 447965 ms | `57b603f2145f71ea57f6830108696d4e030530235d3cecf5d7070036c3021b98` (`netlist_900.log`) | + +Rust was available through `/root/.cargo/bin` once `CARGO_HOME=/root/.cargo` +and `RUSTUP_HOME=/root/.rustup` were set; it was not available on the default +PATH. The official test is consequently an executed result, not an environment +blocker. + +Synthesis produced `lsc1_packet_frontend.netlist.v` (SHA-256 +`bea4db3161ea6fe410e47e9a8573aa07081b26666a702ee37828eae50ab3869f`). +Sequential equivalence was then attempted only against that exact netlist. The +first command failed at setup (exit 1, 2222 ms; `equivalence.log`) because the +gold RTL still contained processes/memories. The corrected command lowered +them first, but found 5039 unproven `$equiv` cells and no SAT model for the +unflattened receiver, transmitter, adapter, and field-encoder submodules. It +was stopped after 585606 ms (exit 143; `equivalence_retry.log`) rather than +claiming a proof. Thus there is no RTL/netlist equivalence result; the precise +missing repository capability is a release sequential-equivalence harness with +the required flattening/state correspondence and reset assumptions. + +Every command and status is retained beside its log. This evidence is a +committed handoff artifact, not a claim that the planned release equivalence +gate passed. diff --git a/results/b2-capability-contract-20260728/SHA256SUMS b/results/b2-capability-contract-20260728/SHA256SUMS new file mode 100644 index 0000000..7799fbf --- /dev/null +++ b/results/b2-capability-contract-20260728/SHA256SUMS @@ -0,0 +1,43 @@ +6c11a3bd4eb64e6c319620cd99d9cfbb9ae6cb7e74be09c282dd5267e15610af results/b2-capability-contract-20260728/README.md +967cd83720a145d1daba23a926a1b22eabc4e83d7b7c337cf3512f3df944c535 results/b2-capability-contract-20260728/blake3_official.command +42b629a692f30c9bfb0fcff81a5eb4631efb576c1355485035dd6d8c50131631 results/b2-capability-contract-20260728/blake3_official.log +c4c41bd36c74ae8036f7f04e842e6e165b94947210de3fbb2ff0fc6a7d212aa6 results/b2-capability-contract-20260728/blake3_official.status +8ed2f76d0f3c4e2f426b94871ba32c169b2d3db054baf69aaec18ee7c88a97d8 results/b2-capability-contract-20260728/equivalence.command +c79afc83ad60a71e82e8a7fa6b2af5d627599ff6c387452e3127ef8dc0d5c8f7 results/b2-capability-contract-20260728/equivalence.log +b55da4864ed1d5b5074f282e6bb197c72e378c1f95e3ae23067f00cf3d1071bf results/b2-capability-contract-20260728/equivalence.status +efbf348e9a19221a83c3de23fc958594ef2138f22817a951b47420d734550a59 results/b2-capability-contract-20260728/equivalence_retry.command +95562d2b0efd62f3caca735841da6ebc3f1456ee777faaabb7fd6165dd08ee61 results/b2-capability-contract-20260728/equivalence_retry.log +796e8d3bc36ff6c463f6726c0d97edcb03dad3fb8d5b5b087ee02dc9c44e391c results/b2-capability-contract-20260728/equivalence_retry.status +bea4db3161ea6fe410e47e9a8573aa07081b26666a702ee37828eae50ab3869f results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v +d4b10f492e3a5904a83de4177f5c62c655a082a2da1678656313317c04a7ea1a results/b2-capability-contract-20260728/metadata.txt +f1a875f061db0344731acf0e9ebc9cdc99a263361e487be3bc4dcc9b252d464e results/b2-capability-contract-20260728/model.command +b91294fb84265d3d8a568773e69bf4be6989b8b2495d06ea1b2b166c021228c2 results/b2-capability-contract-20260728/model.log +9320156f7729afcf7950684c435baafe45dc8515e77af2cd815ba0d9041679b2 results/b2-capability-contract-20260728/model.status +2a1fd501e41c4e8cac7e79d3cc22c212316bd0da7d37645833a4408a3ff5377e results/b2-capability-contract-20260728/model_final.command +d13aeaee319cce423e3c559504b2eff9e89be80f067b0a946a7c2edea31bd59e results/b2-capability-contract-20260728/model_final.log +26d53b8f395698095c32449712d1707c2c98b829e16fa36f012c557f78c645da results/b2-capability-contract-20260728/model_final.status +4d5f8f25d8b11fc698d4c4e75edc8e5fa76ddddda8ed6b75de580edabfa777bf results/b2-capability-contract-20260728/mutation.command +73a36fd9d3c0bd6c193ab3bcfd546574a9f3b2945298b7589aa10584725877c2 results/b2-capability-contract-20260728/mutation.log +57d257a78050bb75005d9a441af784d6d9cff1142a690a4989a7f275bf76618e results/b2-capability-contract-20260728/mutation.status +4d5f8f25d8b11fc698d4c4e75edc8e5fa76ddddda8ed6b75de580edabfa777bf results/b2-capability-contract-20260728/mutation_final.command +73a36fd9d3c0bd6c193ab3bcfd546574a9f3b2945298b7589aa10584725877c2 results/b2-capability-contract-20260728/mutation_final.log +8e76cd9739bee71cbea620307516ec37cfd2015506a62245bb8f75831b718887 results/b2-capability-contract-20260728/mutation_final.status +67eeb3e7508368a86d6be56bef6797740a87650f1feca9ea43a15f0cc612c1ec results/b2-capability-contract-20260728/netlist.command +99638ad3d2222677392e42d3a011ef253ca24376fa59f1402c40c200d84357a1 results/b2-capability-contract-20260728/netlist.log +7e6b5e7f24bd34bdc2d64ef0430123721cd458259f77e97076a7c71e0cdc6aff results/b2-capability-contract-20260728/netlist.status +5e458fe7b8a6fd2efaa0d102ef3b6761d28a45624e397ff19bbedfd61dc402a7 results/b2-capability-contract-20260728/netlist_900.command +57b603f2145f71ea57f6830108696d4e030530235d3cecf5d7070036c3021b98 results/b2-capability-contract-20260728/netlist_900.log +14ab37de2335111d8b7e7c731bb293bb6a9fea6dfa29b72f31696b9c611dd5e5 results/b2-capability-contract-20260728/netlist_900.status +c6bede227931eebaeb2cb022457155b414ff5de4642f48748e27f817a8d56c49 results/b2-capability-contract-20260728/python_full.command +498b59ec0a8d38ae9fb00b969dab98412dc9772d767c966238b5c4562c573b36 results/b2-capability-contract-20260728/python_full.log +d6f20552131049cb665bbd0449627ef0ec0d6594f1de39feae3e4e9b7ffe21f8 results/b2-capability-contract-20260728/python_full.status +3f29544634cb7c34c5681fb90cb36f818a649ae5ac8e74df372f15806081d43f results/b2-capability-contract-20260728/python_full_final.command +3f3a9d48fd3bfa56895994fed2a415312f4713bb6acbe81144ec9c2ab15f8757 results/b2-capability-contract-20260728/python_full_final.log +c0086458ffdc5a2d5f3f704c2882f7cebdc0eb6178b3bd0517ef25ce8f6083fd results/b2-capability-contract-20260728/python_full_final.status +42c1c9680f854883922eef8493abd0e7d3f7dbe293f40b5f7c639d72761a8ff2 results/b2-capability-contract-20260728/rtl.command +881d0c9e93dd2f29354bf42351533bfe1b571eb3f4e4f0198d92dc51fe4c064f results/b2-capability-contract-20260728/rtl.log +5ac891ed2dcc8e0eb2408aa15faef2b83d780baa8de02c2578b51494cff17d25 results/b2-capability-contract-20260728/rtl.status +42c1c9680f854883922eef8493abd0e7d3f7dbe293f40b5f7c639d72761a8ff2 results/b2-capability-contract-20260728/rtl_final.command +881d0c9e93dd2f29354bf42351533bfe1b571eb3f4e4f0198d92dc51fe4c064f results/b2-capability-contract-20260728/rtl_final.log +3916d13f98a1f4f76582598a2c2b98f39998cd02a9e2e117c47f5aced1b62915 results/b2-capability-contract-20260728/rtl_final.status +256ef5dd4c4cafd51370b52e2e8d02487cfea78f04304c6081a13dbc1b104787 results/b2-capability-contract-20260728/run.sh diff --git a/results/b2-capability-contract-20260728/blake3_official.command b/results/b2-capability-contract-20260728/blake3_official.command new file mode 100644 index 0000000..e05243e --- /dev/null +++ b/results/b2-capability-contract-20260728/blake3_official.command @@ -0,0 +1 @@ +timeout 300s python3 -m unittest sim.test_blake3_service.OfficialDifferentialTests diff --git a/results/b2-capability-contract-20260728/blake3_official.log b/results/b2-capability-contract-20260728/blake3_official.log new file mode 100644 index 0000000..3ef9868 --- /dev/null +++ b/results/b2-capability-contract-20260728/blake3_official.log @@ -0,0 +1,5 @@ +. +---------------------------------------------------------------------- +Ran 1 test in 1.363s + +OK diff --git a/results/b2-capability-contract-20260728/blake3_official.status b/results/b2-capability-contract-20260728/blake3_official.status new file mode 100644 index 0000000..f6419d7 --- /dev/null +++ b/results/b2-capability-contract-20260728/blake3_official.status @@ -0,0 +1,2 @@ +exit=0 +duration_ms=1426 diff --git a/results/b2-capability-contract-20260728/equivalence.command b/results/b2-capability-contract-20260728/equivalence.command new file mode 100644 index 0000000..1f08a84 --- /dev/null +++ b/results/b2-capability-contract-20260728/equivalence.command @@ -0,0 +1 @@ +timeout 900s yosys -p read_verilog\\ -sv\\ asic_core/rtl/lsc1_packet_rx.sv\\ asic_core/rtl/lsc1_packet_tx.sv\\ asic_core/rtl/gf2n_mul_bitstream.sv\\ asic_core/rtl/gf128_mul_bitstream.sv\\ asic_core/rtl/leanvm_b_stream_alu.sv\\ asic_core/rtl/lsc1_stream_adapter.sv\\ asic_core/rtl/lsc1_field_encoder.sv\\ asic_core/rtl/lsc1_packet_frontend.sv\\;\\ rename\\ lsc1_packet_frontend\\ gold\\;\\ read_verilog\\ results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v\\;\\ rename\\ lsc1_packet_frontend\\ gate\\;\\ equiv_make\\ gold\\ gate\\ equiv\\;\\ hierarchy\\ -top\\ equiv\\;\\ proc\\;\\ opt\\;\\ equiv_simple\\;\\ equiv_induct\\ -seq\\ 4\\;\\ equiv_status\\ -assert diff --git a/results/b2-capability-contract-20260728/equivalence.log b/results/b2-capability-contract-20260728/equivalence.log new file mode 100644 index 0000000..df56f99 --- /dev/null +++ b/results/b2-capability-contract-20260728/equivalence.log @@ -0,0 +1,71 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Running command `read_verilog -sv asic_core/rtl/lsc1_packet_rx.sv asic_core/rtl/lsc1_packet_tx.sv asic_core/rtl/gf2n_mul_bitstream.sv asic_core/rtl/gf128_mul_bitstream.sv asic_core/rtl/leanvm_b_stream_alu.sv asic_core/rtl/lsc1_stream_adapter.sv asic_core/rtl/lsc1_field_encoder.sv asic_core/rtl/lsc1_packet_frontend.sv; rename lsc1_packet_frontend gold; read_verilog results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v; rename lsc1_packet_frontend gate; equiv_make gold gate equiv; hierarchy -top equiv; proc; opt; equiv_simple; equiv_induct -seq 4; equiv_status -assert' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_rx.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_tx.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_tx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_tx'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: asic_core/rtl/gf2n_mul_bitstream.sv +Parsing SystemVerilog input from `asic_core/rtl/gf2n_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf2n_mul_bitstream'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: asic_core/rtl/gf128_mul_bitstream.sv +Parsing SystemVerilog input from `asic_core/rtl/gf128_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf128_mul_bitstream'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: asic_core/rtl/leanvm_b_stream_alu.sv +Parsing SystemVerilog input from `asic_core/rtl/leanvm_b_stream_alu.sv' to AST representation. +Generating RTLIL representation for module `\leanvm_b_stream_alu'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_stream_adapter.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_stream_adapter.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_stream_adapter'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_field_encoder.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_field_encoder.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_field_encoder'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_frontend.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_frontend.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Successfully finished Verilog frontend. +Renaming module \lsc1_packet_frontend to \gold. + +9. Executing Verilog-2005 frontend: results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v +Parsing Verilog input from `results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v' to AST representation. +Warning: Encountered `parallel_case' comment! Such legacy hot comments are supported by Yosys, but are not part of any formal language specification. Using the Verilog `parallel_case' attribute or the SystemVerilog `unique' or `priority' keywords is recommended! +ERROR: Gold module contains memories or processes. Run 'memory' or 'proc' respectively. diff --git a/results/b2-capability-contract-20260728/equivalence.status b/results/b2-capability-contract-20260728/equivalence.status new file mode 100644 index 0000000..d682f11 --- /dev/null +++ b/results/b2-capability-contract-20260728/equivalence.status @@ -0,0 +1,2 @@ +exit=1 +duration_ms=2222 diff --git a/results/b2-capability-contract-20260728/equivalence_retry.command b/results/b2-capability-contract-20260728/equivalence_retry.command new file mode 100644 index 0000000..4079c30 --- /dev/null +++ b/results/b2-capability-contract-20260728/equivalence_retry.command @@ -0,0 +1 @@ +timeout 900s yosys: read RTL; rename top gold; read generated netlist; rename top gate; proc; memory; opt; equiv_make gold gate equiv; hierarchy -top equiv; equiv_simple; equiv_induct -seq 4; equiv_status -assert diff --git a/results/b2-capability-contract-20260728/equivalence_retry.log b/results/b2-capability-contract-20260728/equivalence_retry.log new file mode 100644 index 0000000..0d6b7d5 --- /dev/null +++ b/results/b2-capability-contract-20260728/equivalence_retry.log @@ -0,0 +1,30021 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Running command `read_verilog -sv asic_core/rtl/lsc1_packet_rx.sv asic_core/rtl/lsc1_packet_tx.sv asic_core/rtl/gf2n_mul_bitstream.sv asic_core/rtl/gf128_mul_bitstream.sv asic_core/rtl/leanvm_b_stream_alu.sv asic_core/rtl/lsc1_stream_adapter.sv asic_core/rtl/lsc1_field_encoder.sv asic_core/rtl/lsc1_packet_frontend.sv; rename lsc1_packet_frontend gold; read_verilog results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v; rename lsc1_packet_frontend gate; proc; memory; opt; equiv_make gold gate equiv; hierarchy -top equiv; equiv_simple; equiv_induct -seq 4; equiv_status -assert' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_rx.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_tx.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_tx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_tx'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: asic_core/rtl/gf2n_mul_bitstream.sv +Parsing SystemVerilog input from `asic_core/rtl/gf2n_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf2n_mul_bitstream'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: asic_core/rtl/gf128_mul_bitstream.sv +Parsing SystemVerilog input from `asic_core/rtl/gf128_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf128_mul_bitstream'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: asic_core/rtl/leanvm_b_stream_alu.sv +Parsing SystemVerilog input from `asic_core/rtl/leanvm_b_stream_alu.sv' to AST representation. +Generating RTLIL representation for module `\leanvm_b_stream_alu'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_stream_adapter.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_stream_adapter.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_stream_adapter'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_field_encoder.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_field_encoder.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_field_encoder'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_frontend.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_frontend.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Successfully finished Verilog frontend. +Renaming module \lsc1_packet_frontend to \gold. + +9. Executing Verilog-2005 frontend: results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v +Parsing Verilog input from `results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v' to AST representation. +Warning: Encountered `parallel_case' comment! Such legacy hot comments are supported by Yosys, but are not part of any formal language specification. Using the Verilog `parallel_case' attribute or the SystemVerilog `unique' or `priority' keywords is recommended! +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Successfully finished Verilog frontend. +Renaming module \lsc1_packet_frontend to \gate. + +10. Executing PROC pass (convert processes to netlists). + +10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 10 empty switches in `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. +Cleaned up 10 empty switches. + +10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6477 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6470 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6464 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6458 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6452 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6446 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6440 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6434 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6428 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6422 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6416 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6410 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6404 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6398 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6392 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6386 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6380 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6375 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6370 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6364 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6359 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6353 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6347 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6341 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6335 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6329 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6323 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6317 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6311 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6305 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6299 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6293 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6287 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6281 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6275 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6270 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6265 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6259 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6254 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6248 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6242 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6236 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6230 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6223 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6217 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6211 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6205 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6199 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6193 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3416$3425 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3413$3424 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3410$3423 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3407$3422 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3404$3421 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3347$3393 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3344$3392 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3340$3390 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3336$3389 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3333$3388 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3330$3387 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3327$3386 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3324$3385 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3321$3384 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3318$3383 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3315$3382 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3312$3381 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3309$3380 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3306$3379 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3303$3378 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3300$3377 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3297$3376 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3294$3375 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3291$3374 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3288$3372 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3285$3370 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3282$3368 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3279$3366 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3276$3365 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3273$3364 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3270$3363 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3267$3361 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3264$3360 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3261$3358 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3258$3356 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3255$3354 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3252$3353 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3249$3352 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3246$3351 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3243$3349 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3240$3347 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3237$3345 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3234$3344 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3231$3342 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3228$3341 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3225$3339 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3222$3337 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3219$3335 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3216$3332 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3213$3330 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3210$3328 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3207$3326 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3204$3324 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3201$3322 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3197$3320 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3192$3319 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3187$3317 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3182$3316 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3178$3315 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3175$3314 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3172$3312 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3169$3311 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3166$3310 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3163$3309 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3160$3308 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3157$3307 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3154$3305 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3151$3303 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3148$3302 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3145$3301 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3142$3300 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3139$3299 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3136$3298 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3133$3296 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3130$3295 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3127$3294 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3124$3293 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3121$3292 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3118$3291 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3114$3290 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3109$3289 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3104$3288 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3100$3287 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3097$3286 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3094$3285 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3091$3284 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3088$3283 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3085$3282 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3082$3281 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3079$3280 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3076$3279 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3073$3278 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3070$3277 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3067$3276 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3064$3275 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3061$3274 in module gate. +Marked 1 switch rules as full_case in process $proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3058$3273 in module gate. +Marked 109 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855 in module gold. +Marked 5 switch rules as full_case in process $proc$asic_core/rtl/lsc1_field_encoder.sv:38$755 in module lsc1_field_encoder. +Marked 10 switch rules as full_case in process $proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671 in module lsc1_stream_adapter. +Marked 6 switch rules as full_case in process $proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646 in module lsc1_stream_adapter. +Marked 12 switch rules as full_case in process $proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615 in module leanvm_b_stream_alu. +Marked 3 switch rules as full_case in process $proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576 in module leanvm_b_stream_alu. +Marked 5 switch rules as full_case in process $proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527 in module gf2n_mul_bitstream. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:62$258 in module lsc1_packet_tx. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:44$244 in module lsc1_packet_tx. +Marked 11 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_rx.sv:62$23 in module lsc1_packet_rx. +Removed a total of 0 dead cases. + +10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 23 redundant assignments. +Promoted 399 assignments to connections. + +10.4. Executing PROC_INIT pass (extract init attributes). + +10.5. Executing PROC_ARST pass (detect async resets in processes). + +10.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6477'. + 1/1: $1\_3842_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5184$3265.$result[7:0]$6483 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6470'. + 1/1: $1\_3764_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5091$3264.$result[0:0]$6476 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6464'. + 1/1: $1\_3754_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5066$3263.$result[7:0]$6469 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6458'. + 1/1: $1\_3742_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5039$3262.$result[2:0]$6463 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6452'. + 1/1: $1\_3740_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5024$3261.$result[2:0]$6457 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6446'. + 1/1: $1\_3734_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5003$3260.$result[2:0]$6451 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6440'. + 1/1: $1\_3732_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4988$3259.$result[15:0]$6445 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6434'. + 1/1: $1\_3730_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4971$3258.$result[31:0]$6439 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6428'. + 1/1: $1\_3727_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4953$3257.$result[2047:0]$6433 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6422'. + 1/1: $1\_3725_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4938$3256.$result[7:0]$6427 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6416'. + 1/1: $1\_3721_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4921$3255.$result[7:0]$6421 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6410'. + 1/1: $1\_3717_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4904$3254.$result[7:0]$6415 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6404'. + 1/1: $1\_3653_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4827$3253.$result[7:0]$6409 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6398'. + 1/1: $1\_3652_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4805$3252.$result[0:0]$6403 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6392'. + 1/1: $1\_3647_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4785$3251.$result[0:0]$6397 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6386'. + 1/1: $1\_3646_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4771$3250.$result[0:0]$6391 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6380'. + 1/1: $1\_3642_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4754$3249.$result[0:0]$6385 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6375'. + 1/1: $1\_3634_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4731$3248.$result[7:0]$6379 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6370'. + 1/1: $1\_3626_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4708$3247.$result[3:0]$6374 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6364'. + 1/1: $1\_3611_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4672$3246.$result[3:0]$6369 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6359'. + 1/1: $1\_3608_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4640$3245.$result[0:0]$6363 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6353'. + 1/1: $1\_3607_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4626$3244.$result[0:0]$6358 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6347'. + 1/1: $1\_3599_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4605$3243.$result[3:0]$6352 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6341'. + 1/1: $1\_3592_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4577$3242.$result[0:0]$6346 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6335'. + 1/1: $1\_3588_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4554$3241.$result[6:0]$6340 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6329'. + 1/1: $1\_3559_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4506$3240.$result[2:0]$6334 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6323'. + 1/1: $1\_3550_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4478$3239.$result[5:0]$6328 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6317'. + 1/1: $1\_3542_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4455$3238.$result[4:0]$6322 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6311'. + 1/1: $1\_3536_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4434$3237.$result[0:0]$6316 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6305'. + 1/1: $1\_3533_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4418$3236.$result[127:0]$6310 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6299'. + 1/1: $1\_3473_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4344$3235.$result[7:0]$6304 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6293'. + 1/1: $1\_3472_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4322$3234.$result[0:0]$6298 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6287'. + 1/1: $1\_3470_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4305$3233.$result[0:0]$6292 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6281'. + 1/1: $1\_3469_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4291$3232.$result[0:0]$6286 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6275'. + 1/1: $1\_3467_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4276$3231.$result[0:0]$6280 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6270'. + 1/1: $1\_3460_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4254$3230.$result[7:0]$6274 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6265'. + 1/1: $1\_3458_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4237$3229.$result[3:0]$6269 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6259'. + 1/1: $1\_3444_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4202$3228.$result[3:0]$6264 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6254'. + 1/1: $1\_3435_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4164$3227.$result[0:0]$6258 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6248'. + 1/1: $1\_3434_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4150$3226.$result[0:0]$6253 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6242'. + 1/1: $1\_3425_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4128$3225.$result[3:0]$6247 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6236'. + 1/1: $1\_3418_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4100$3224.$result[0:0]$6241 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6230'. + 1/1: $1\_3412_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4075$3223.$result[6:0]$6235 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6223'. + 1/1: $1\_3378_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4020$3222.$result[7:0]$6229 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6217'. + 1/1: $1\_3363_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3992$3221.$result[2:0]$6222 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6211'. + 1/1: $1\_3354_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3964$3220.$result[5:0]$6216 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6205'. + 1/1: $1\_3346_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3941$3219.$result[4:0]$6210 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6199'. + 1/1: $1\_3338_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3918$3218.$result[0:0]$6204 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6193'. + 1/1: $1\_3335_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3900$3217.$result[127:0]$6198 +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3416$3425'. + 1/1: $0\adapter.datapath.byte_index[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3413$3424'. + 1/1: $0\adapter.datapath.state[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3410$3423'. + 1/1: $0\field_encoder.multiplier.result[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3407$3422'. + 1/1: $0\field_encoder.multiplier.datapath.state[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3404$3421'. + 1/1: $0\field_encoder.multiplier.datapath.byte_index[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3402$3420'. + 1/1: $0\write_value[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3400$3419'. + 1/1: $0\write_address[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3398$3418'. + 1/1: $0\solved_b[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3396$3417'. + 1/1: $0\solved_a[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3394$3416'. + 1/1: $0\result_value[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3392$3415'. + 1/1: $0\inv_value[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3390$3414'. + 1/1: $0\val_c[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3388$3413'. + 1/1: $0\val_b[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3386$3412'. + 1/1: $0\val_a[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3384$3411'. + 1/1: $0\pres_c[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3382$3410'. + 1/1: $0\pres_b[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3380$3409'. + 1/1: $0\pres_a[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3378$3408'. + 1/1: $0\profile[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3376$3407'. + 1/1: $0\deferred_local[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3374$3406'. + 1/1: $0\deferred_target[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3372$3405'. + 1/1: $0\next_fp_value[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3370$3404'. + 1/1: $0\next_pc_value[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3368$3403'. + 1/1: $0\proposed_fp[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3366$3402'. + 1/1: $0\proposed_pc[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3364$3401'. + 1/1: $0\addr_c[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3362$3400'. + 1/1: $0\addr_b[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3360$3399'. + 1/1: $0\addr_a[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3358$3398'. + 1/1: $0\fp[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3356$3397'. + 1/1: $0\pc[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3354$3396'. + 1/1: $0\txn_id[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3352$3395'. + 1/1: $0\n_deferred[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3350$3394'. + 1/1: $0\n_writes[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3347$3393'. + 1/1: $0\adapter.result[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3344$3392'. + 1/1: $0\receiver.frame_payload[2047:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3340$3390'. + 1/1: $0\field_encoder.multiplier.saved_operation_reg[1][0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3336$3389'. + 1/1: $0\transmitter.payload_crc_work[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3333$3388'. + 1/1: $0\transmitter.envelope_crc_work[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3330$3387'. + 1/1: $0\transmitter.saved_crc[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3327$3386'. + 1/1: $0\transmitter.saved_payload[543:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3324$3385'. + 1/1: $0\transmitter.saved_status[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3321$3384'. + 1/1: $0\transmitter.saved_length[15:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3318$3383'. + 1/1: $0\transmitter.index[15:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3315$3382'. + 1/1: $0\transmitter.active[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3312$3381'. + 1/1: $0\transmitter.payload_crc[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3309$3380'. + 1/1: $0\transmitter.done_pulse[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3306$3379'. + 1/1: $0\field_encoder.done_pulse[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3303$3378'. + 1/1: $0\field_encoder.busy[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3300$3377'. + 1/1: $0\adapter.datapath.multiplier.impl.a_shift[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3297$3376'. + 1/1: $0\adapter.datapath.multiplier.impl.accumulator[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3294$3375'. + 1/1: $0\adapter.result_index[4:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3291$3374'. + 1/1: $0\adapter.payload_index[5:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3288$3372'. + 1/1: $0\adapter.saved_b[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3285$3370'. + 1/1: $0\adapter.saved_a[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3282$3368'. + 1/1: $0\adapter.saved_operation[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3279$3366'. + 1/1: $0\adapter.fault[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3276$3365'. + 1/1: $0\adapter.done_pulse[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3273$3364'. + 1/1: $0\adapter.state[2:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3270$3363'. + 1/1: $0\done_pulse[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3267$3361'. + 1/1: $0\fault[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3264$3360'. + 1/1: $0\tx_start[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3261$3358'. + 1/1: $0\tx_status[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3258$3356'. + 1/1: $0\tx_length[15:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3255$3354'. + 1/1: $0\tx_payload[543:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3252$3353'. + 1/1: $0\capture_result_crc[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3249$3352'. + 1/1: $0\compute_state[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3246$3351'. + 1/1: $0\alu_start[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3243$3349'. + 1/1: $0\alu_operation[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3240$3347'. + 1/1: $0\alu_operand_a[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3237$3345'. + 1/1: $0\alu_operand_b[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3234$3344'. + 1/1: $0\encoder_start[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3231$3342'. + 1/1: $0\encoder_index[15:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3228$3341'. + 1/1: $0\result_pending[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3225$3339'. + 1/1: $0\staged_txn_id[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3222$3337'. + 1/1: $0\staged_next_pc[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3219$3335'. + 1/1: $0\staged_next_fp[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3216$3332'. + 1/1: $0\staged_result_crc[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3213$3330'. + 1/1: $0\state_valid[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3210$3328'. + 1/1: $0\committed_pc[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3207$3326'. + 1/1: $0\committed_fp[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3204$3324'. + 1/1: $0\retire_seq[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3201$3322'. + 1/1: $0\active_profile[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3197$3320'. + 1/1: $0\_2785_[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3192$3319'. + 1/1: $0\_2784_[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3187$3317'. + 1/1: $0\_2783_[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3182$3316'. + 1/1: $0\_2782_[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3178$3315'. + 1/1: $0\field_encoder.multiplier.datapath.scratch_byte[7:1] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3175$3314'. + 1/1: $0\field_encoder.multiplier.datapath.scratch_byte[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3172$3312'. + 1/1: $0\field_encoder.multiplier.datapath.fault[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3169$3311'. + 1/1: $0\field_encoder.multiplier.datapath.multiplier.impl.accumulator[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3166$3310'. + 1/1: $0\field_encoder.multiplier.datapath.multiplier.impl.a_shift[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3163$3309'. + 1/1: $0\field_encoder.saved_index[15:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3160$3308'. + 1/1: $0\field_encoder.multiplier.state[2:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3157$3307'. + 1/1: $0\field_encoder.multiplier.done_pulse[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3154$3305'. + 1/1: $0\field_encoder.multiplier.fault[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3151$3303'. + 1/1: $0\field_encoder.multiplier.saved_b[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3148$3302'. + 1/1: $0\field_encoder.multiplier.payload_index[5:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3145$3301'. + 1/1: $0\field_encoder.multiplier.result_index[4:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3142$3300'. + 1/1: $0\field_encoder.bit_index[3:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3139$3299'. + 1/1: $0\field_encoder.bit_index[4:4] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3136$3298'. + 1/1: $0\field_encoder.multiply_start[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3133$3296'. + 1/1: $0\adapter.datapath.fault[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3130$3295'. + 1/1: $0\adapter.datapath.scratch_byte[7:1] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3127$3294'. + 1/1: $0\adapter.datapath.scratch_byte[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3124$3293'. + 1/1: $0\field_encoder.result[127:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3121$3292'. + 1/1: $0\field_encoder.operand_b[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3118$3291'. + 1/1: $0\field_encoder.operand_b[127:1] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3114$3290'. + 1/1: $0\_2760_[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3109$3289'. + 1/1: $0\_2759_[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3104$3288'. + 1/1: $0\_2758_[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3100$3287'. + 1/1: $0\receiver.crc[31:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3097$3286'. + 1/1: $0\receiver.flags[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3094$3285'. + 1/1: $0\receiver.opcode[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3091$3284'. + 1/1: $0\receiver.version[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3088$3283'. + 1/1: $0\receiver.declared_length[15:8] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3085$3282'. + 1/1: $0\receiver.declared_length[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3082$3281'. + 1/1: $0\receiver.body_index[15:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3079$3280'. + 1/1: $0\receiver.header_index[2:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3076$3279'. + 1/1: $0\receiver.state[2:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3073$3278'. + 1/1: $0\receiver.fault_status[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3070$3277'. + 1/1: $0\receiver.fault_valid[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3067$3276'. + 1/1: $0\receiver.frame_length[15:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3064$3275'. + 1/1: $0\receiver.frame_opcode[7:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3061$3274'. + 1/1: $0\receiver.frame_valid[0:0] +Creating decoders for process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3058$3273'. + 1/1: $0\field_encoder.fault[0:0] +Creating decoders for process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + 1/3417: $68\result_bytes[215:152] [63:32] + 2/3417: $68\result_bytes[215:152] [31:0] + 3/3417: $64\result_length[31:0] + 4/3417: $67\result_bytes[279:104] [111:80] + 5/3417: $67\result_bytes[279:104] [47:40] + 6/3417: $67\result_bytes[279:104] [15:8] + 7/3417: $67\result_bytes[279:104] [143:112] + 8/3417: $63\result_length[31:0] + 9/3417: $67\result_bytes[279:104] [79:72] + 10/3417: $67\result_bytes[279:104] [71:48] + 11/3417: $67\result_bytes[279:104] [39:16] + 12/3417: $67\result_bytes[279:104] [175:144] + 13/3417: $67\result_bytes[279:104] [7:0] + 14/3417: $65\result_bytes[375:104] [175:168] + 15/3417: $66\result_bytes[375:312] [31:0] + 16/3417: $62\result_length[31:0] + 17/3417: $65\result_bytes[375:104] [207:176] + 18/3417: $61\result_length[31:0] + 19/3417: $66\result_bytes[375:312] [63:32] + 20/3417: $65\result_bytes[375:104] [167:160] + 21/3417: $65\result_bytes[375:104] [159:32] + 22/3417: $65\result_bytes[375:104] [31:0] + 23/3417: $65\result_bytes[375:104] [271:208] + 24/3417: $64\result_bytes[543:0] [375:104] + 25/3417: $64\result_bytes[543:0] [103:96] + 26/3417: $64\result_bytes[543:0] [95:64] + 27/3417: $64\result_bytes[543:0] [63:32] + 28/3417: $64\result_bytes[543:0] [31:0] + 29/3417: $64\result_bytes[543:0] [543:376] + 30/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [31:0] + 31/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [39:32] + 32/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$3159 + 33/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$3158 + 34/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$3157 + 35/3417: $29\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$3161 + 36/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [543:40] + 37/3417: $60\result_length[31:0] + 38/3417: $28\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$3155 + 39/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3154 + 40/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$3153 + 41/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$3152 + 42/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$3151 + 43/3417: $63\result_bytes[543:0] + 44/3417: $59\result_length[31:0] + 45/3417: $50\decision_deferred[0:0] + 46/3417: $49\decision_deferred[0:0] + 47/3417: $48\decision_deferred[0:0] + 48/3417: $58\decision_fault[7:0] + 49/3417: $58\decision_ok[0:0] + 50/3417: $47\decision_deferred[0:0] + 51/3417: $57\decision_fault[7:0] + 52/3417: $57\decision_ok[0:0] + 53/3417: $46\decision_deferred[0:0] + 54/3417: $45\decision_deferred[0:0] + 55/3417: $56\decision_ok[0:0] + 56/3417: $56\decision_fault[7:0] + 57/3417: $44\decision_deferred[0:0] + 58/3417: $55\decision_ok[0:0] + 59/3417: $55\decision_fault[7:0] + 60/3417: $54\decision_fault[7:0] + 61/3417: $54\decision_ok[0:0] + 62/3417: $53\decision_fault[7:0] + 63/3417: $53\decision_ok[0:0] + 64/3417: $38\addr_c[31:0] + 65/3417: $38\addr_b[31:0] + 66/3417: $42\addr_a[31:0] + 67/3417: $52\decision_fault[7:0] + 68/3417: $52\decision_ok[0:0] + 69/3417: $37\addr_c[31:0] + 70/3417: $37\addr_b[31:0] + 71/3417: $41\addr_a[31:0] + 72/3417: $43\decision_deferred[0:0] + 73/3417: $51\decision_ok[0:0] + 74/3417: $51\decision_fault[7:0] + 75/3417: $33\solved_b[127:0] + 76/3417: $33\solved_a[127:0] + 77/3417: $36\addr_c[31:0] + 78/3417: $36\addr_b[31:0] + 79/3417: $40\addr_a[31:0] + 80/3417: $31\inv_value[127:0] + 81/3417: $31\inv_present[7:0] + 82/3417: $31\val_c[127:0] + 83/3417: $31\pres_c[7:0] + 84/3417: $31\val_b[127:0] + 85/3417: $31\pres_b[7:0] + 86/3417: $31\val_a[127:0] + 87/3417: $31\pres_a[7:0] + 88/3417: $31\off_c[31:0] + 89/3417: $31\off_b[31:0] + 90/3417: $31\off_a[31:0] + 91/3417: $38\decision_detail[7:0] + 92/3417: $50\decision_fault[7:0] + 93/3417: $50\decision_ok[0:0] + 94/3417: $37\decision_detail[7:0] + 95/3417: $49\decision_fault[7:0] + 96/3417: $49\decision_ok[0:0] + 97/3417: $48\decision_fault[7:0] + 98/3417: $48\decision_ok[0:0] + 99/3417: $42\decision_deferred[0:0] + 100/3417: $47\decision_fault[7:0] + 101/3417: $47\decision_ok[0:0] + 102/3417: $41\decision_deferred[0:0] + 103/3417: $40\decision_deferred[0:0] + 104/3417: $46\decision_ok[0:0] + 105/3417: $46\decision_fault[7:0] + 106/3417: $36\decision_detail[7:0] + 107/3417: $35\decision_detail[7:0] + 108/3417: $45\decision_fault[7:0] + 109/3417: $45\decision_ok[0:0] + 110/3417: $39\decision_deferred[0:0] + 111/3417: $34\decision_detail[7:0] + 112/3417: $44\decision_fault[7:0] + 113/3417: $44\decision_ok[0:0] + 114/3417: $38\decision_deferred[0:0] + 115/3417: $43\decision_fault[7:0] + 116/3417: $43\decision_ok[0:0] + 117/3417: $37\decision_deferred[0:0] + 118/3417: $33\decision_detail[7:0] + 119/3417: $42\decision_fault[7:0] + 120/3417: $42\decision_ok[0:0] + 121/3417: $36\decision_deferred[0:0] + 122/3417: $32\decision_detail[7:0] + 123/3417: $35\addr_c[31:0] + 124/3417: $35\addr_b[31:0] + 125/3417: $39\addr_a[31:0] + 126/3417: $41\decision_fault[7:0] + 127/3417: $41\decision_ok[0:0] + 128/3417: $35\decision_deferred[0:0] + 129/3417: $31\decision_detail[7:0] + 130/3417: $34\addr_c[31:0] + 131/3417: $34\addr_b[31:0] + 132/3417: $38\addr_a[31:0] + 133/3417: $34\decision_deferred[0:0] + 134/3417: $40\decision_ok[0:0] + 135/3417: $30\decision_detail[7:0] + 136/3417: $40\decision_fault[7:0] + 137/3417: $33\addr_c[31:0] + 138/3417: $33\addr_b[31:0] + 139/3417: $37\addr_a[31:0] + 140/3417: $30\inv_value[127:0] + 141/3417: $30\inv_present[7:0] + 142/3417: $30\proposed_fp[31:0] + 143/3417: $30\proposed_pc[31:0] + 144/3417: $30\taken_proposal[7:0] + 145/3417: $30\val_c[127:0] + 146/3417: $30\pres_c[7:0] + 147/3417: $30\val_b[127:0] + 148/3417: $30\pres_b[7:0] + 149/3417: $30\val_a[127:0] + 150/3417: $30\pres_a[7:0] + 151/3417: $30\off_c[31:0] + 152/3417: $30\off_b[31:0] + 153/3417: $30\off_a[31:0] + 154/3417: $32\solved_b[127:0] + 155/3417: $32\solved_a[127:0] + 156/3417: $39\decision_fault[7:0] + 157/3417: $39\decision_ok[0:0] + 158/3417: $33\decision_deferred[0:0] + 159/3417: $38\decision_fault[7:0] + 160/3417: $38\decision_ok[0:0] + 161/3417: $32\decision_deferred[0:0] + 162/3417: $32\addr_c[31:0] + 163/3417: $32\addr_b[31:0] + 164/3417: $36\addr_a[31:0] + 165/3417: $37\decision_fault[7:0] + 166/3417: $37\decision_ok[0:0] + 167/3417: $31\decision_deferred[0:0] + 168/3417: $31\addr_c[31:0] + 169/3417: $31\addr_b[31:0] + 170/3417: $35\addr_a[31:0] + 171/3417: $36\decision_fault[7:0] + 172/3417: $36\decision_ok[0:0] + 173/3417: $30\decision_deferred[0:0] + 174/3417: $30\addr_c[31:0] + 175/3417: $30\addr_b[31:0] + 176/3417: $34\addr_a[31:0] + 177/3417: $29\decision_deferred[0:0] + 178/3417: $35\decision_ok[0:0] + 179/3417: $35\decision_fault[7:0] + 180/3417: $29\addr_c[31:0] + 181/3417: $29\addr_b[31:0] + 182/3417: $33\addr_a[31:0] + 183/3417: $29\val_c[127:0] + 184/3417: $29\pres_c[7:0] + 185/3417: $29\val_b[127:0] + 186/3417: $29\pres_b[7:0] + 187/3417: $29\base_index[31:0] + 188/3417: $29\val_a[127:0] + 189/3417: $29\pres_a[7:0] + 190/3417: $29\off_c[31:0] + 191/3417: $29\off_b[31:0] + 192/3417: $29\off_a[31:0] + 193/3417: $29\decision_detail[7:0] + 194/3417: $31\solved_b[127:0] + 195/3417: $31\solved_a[127:0] + 196/3417: $29\inv_value[127:0] + 197/3417: $29\taken_proposal[7:0] + 198/3417: $29\inv_present[7:0] + 199/3417: $29\proposed_fp[31:0] + 200/3417: $29\proposed_pc[31:0] + 201/3417: $44\n_writes[31:0] + 202/3417: $44\write_value[127:0] + 203/3417: $44\write_address[31:0] + 204/3417: $32\addr_a[31:0] + 205/3417: $34\decision_fault[7:0] + 206/3417: $34\decision_ok[0:0] + 207/3417: $43\write_value[127:0] + 208/3417: $43\write_address[31:0] + 209/3417: $31\addr_a[31:0] + 210/3417: $43\n_writes[31:0] + 211/3417: $33\decision_fault[7:0] + 212/3417: $33\decision_ok[0:0] + 213/3417: $42\write_value[127:0] + 214/3417: $42\write_address[31:0] + 215/3417: $30\addr_a[31:0] + 216/3417: $42\n_writes[31:0] + 217/3417: $32\decision_fault[7:0] + 218/3417: $32\decision_ok[0:0] + 219/3417: $41\write_value[127:0] + 220/3417: $41\write_address[31:0] + 221/3417: $29\addr_a[31:0] + 222/3417: $41\n_writes[31:0] + 223/3417: $28\addr_c[31:0] + 224/3417: $28\addr_b[31:0] + 225/3417: $28\addr_a[31:0] + 226/3417: $31\decision_ok[0:0] + 227/3417: $31\decision_fault[7:0] + 228/3417: $40\write_value[127:0] + 229/3417: $40\write_address[31:0] + 230/3417: $40\n_writes[31:0] + 231/3417: $28\val_a[127:0] + 232/3417: $28\pres_a[7:0] + 233/3417: $28\result_value[127:0] + 234/3417: $28\off_a[31:0] + 235/3417: $28\decision_deferred[0:0] + 236/3417: $28\decision_detail[7:0] + 237/3417: $30\solved_b[127:0] + 238/3417: $30\solved_a[127:0] + 239/3417: $28\inv_value[127:0] + 240/3417: $28\val_c[127:0] + 241/3417: $28\val_b[127:0] + 242/3417: $28\taken_proposal[7:0] + 243/3417: $28\inv_present[7:0] + 244/3417: $28\pres_c[7:0] + 245/3417: $28\pres_b[7:0] + 246/3417: $28\proposed_fp[31:0] + 247/3417: $28\proposed_pc[31:0] + 248/3417: $28\base_index[31:0] + 249/3417: $28\off_c[31:0] + 250/3417: $28\off_b[31:0] + 251/3417: $30\decision_fault[7:0] + 252/3417: $30\decision_ok[0:0] + 253/3417: $29\decision_fault[7:0] + 254/3417: $29\decision_ok[0:0] + 255/3417: $28\decision_fault[7:0] + 256/3417: $28\decision_ok[0:0] + 257/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [543:40] + 258/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [31:0] + 259/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [39:32] + 260/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2916 + 261/3417: $27\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2922 + 262/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2921 + 263/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2920 + 264/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2919 + 265/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2918 + 266/3417: $27\decision_deferred[0:0] + 267/3417: $27\decision_ok[0:0] + 268/3417: $27\decision_detail[7:0] + 269/3417: $27\decision_fault[7:0] + 270/3417: $39\write_value[127:0] + 271/3417: $39\write_address[31:0] + 272/3417: $62\result_bytes[543:0] + 273/3417: $29\solved_b[127:0] + 274/3417: $29\solved_a[127:0] + 275/3417: $27\result_value[127:0] + 276/3417: $27\inv_value[127:0] + 277/3417: $27\val_c[127:0] + 278/3417: $27\val_b[127:0] + 279/3417: $27\val_a[127:0] + 280/3417: $27\taken_proposal[7:0] + 281/3417: $27\inv_present[7:0] + 282/3417: $27\pres_c[7:0] + 283/3417: $27\pres_b[7:0] + 284/3417: $27\pres_a[7:0] + 285/3417: $27\profile[7:0] + 286/3417: $34\deferred_local[31:0] + 287/3417: $34\deferred_target[31:0] + 288/3417: $29\next_fp_value[31:0] + 289/3417: $29\next_pc_value[31:0] + 290/3417: $27\proposed_fp[31:0] + 291/3417: $27\proposed_pc[31:0] + 292/3417: $27\base_index[31:0] + 293/3417: $27\addr_c[31:0] + 294/3417: $27\addr_b[31:0] + 295/3417: $27\addr_a[31:0] + 296/3417: $27\off_c[31:0] + 297/3417: $27\off_b[31:0] + 298/3417: $27\off_a[31:0] + 299/3417: $27\fp[31:0] + 300/3417: $27\pc[31:0] + 301/3417: $27\txn_id[31:0] + 302/3417: $58\result_length[31:0] + 303/3417: $34\n_deferred[31:0] + 304/3417: $39\n_writes[31:0] + 305/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [543:40] + 306/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [31:0] + 307/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [39:32] + 308/3417: $26\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2915 + 309/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2914 + 310/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2913 + 311/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2912 + 312/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2911 + 313/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2910 + 314/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2909 + 315/3417: $26\decision_deferred[0:0] + 316/3417: $26\decision_ok[0:0] + 317/3417: $26\decision_detail[7:0] + 318/3417: $26\decision_fault[7:0] + 319/3417: $38\write_value[127:0] + 320/3417: $38\write_address[31:0] + 321/3417: $61\result_bytes[543:0] + 322/3417: $28\solved_b[127:0] + 323/3417: $28\solved_a[127:0] + 324/3417: $26\result_value[127:0] + 325/3417: $26\inv_value[127:0] + 326/3417: $26\val_c[127:0] + 327/3417: $26\val_b[127:0] + 328/3417: $26\val_a[127:0] + 329/3417: $26\taken_proposal[7:0] + 330/3417: $26\inv_present[7:0] + 331/3417: $26\pres_c[7:0] + 332/3417: $26\pres_b[7:0] + 333/3417: $26\pres_a[7:0] + 334/3417: $26\profile[7:0] + 335/3417: $33\deferred_local[31:0] + 336/3417: $33\deferred_target[31:0] + 337/3417: $28\next_fp_value[31:0] + 338/3417: $28\next_pc_value[31:0] + 339/3417: $26\proposed_fp[31:0] + 340/3417: $26\proposed_pc[31:0] + 341/3417: $26\base_index[31:0] + 342/3417: $26\addr_c[31:0] + 343/3417: $26\addr_b[31:0] + 344/3417: $26\addr_a[31:0] + 345/3417: $26\off_c[31:0] + 346/3417: $26\off_b[31:0] + 347/3417: $26\off_a[31:0] + 348/3417: $26\fp[31:0] + 349/3417: $26\pc[31:0] + 350/3417: $26\txn_id[31:0] + 351/3417: $57\result_length[31:0] + 352/3417: $33\n_deferred[31:0] + 353/3417: $38\n_writes[31:0] + 354/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [543:40] + 355/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [31:0] + 356/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [39:32] + 357/3417: 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$25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2859 + 377/3417: $25\decision_deferred[0:0] + 378/3417: $25\decision_ok[0:0] + 379/3417: $25\decision_detail[7:0] + 380/3417: $25\decision_fault[7:0] + 381/3417: $37\write_value[127:0] + 382/3417: $37\write_address[31:0] + 383/3417: $60\result_bytes[543:0] + 384/3417: $27\solved_b[127:0] + 385/3417: $27\solved_a[127:0] + 386/3417: $25\result_value[127:0] + 387/3417: $25\inv_value[127:0] + 388/3417: $25\val_c[127:0] + 389/3417: $25\val_b[127:0] + 390/3417: $25\val_a[127:0] + 391/3417: $25\taken_proposal[7:0] + 392/3417: $25\inv_present[7:0] + 393/3417: $25\pres_c[7:0] + 394/3417: $25\pres_b[7:0] + 395/3417: $25\pres_a[7:0] + 396/3417: $25\profile[7:0] + 397/3417: $32\deferred_local[31:0] + 398/3417: $32\deferred_target[31:0] + 399/3417: $27\next_fp_value[31:0] + 400/3417: $27\next_pc_value[31:0] + 401/3417: $25\proposed_fp[31:0] + 402/3417: $25\proposed_pc[31:0] + 403/3417: $25\base_index[31:0] + 404/3417: $25\addr_c[31:0] + 405/3417: $25\addr_b[31:0] + 406/3417: $25\addr_a[31:0] + 407/3417: $25\off_c[31:0] + 408/3417: $25\off_b[31:0] + 409/3417: $25\off_a[31:0] + 410/3417: $25\fp[31:0] + 411/3417: $25\pc[31:0] + 412/3417: $25\txn_id[31:0] + 413/3417: $56\result_length[31:0] + 414/3417: $32\n_deferred[31:0] + 415/3417: $37\n_writes[31:0] + 416/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [543:40] + 417/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [31:0] + 418/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [39:32] + 419/3417: $24\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2854 + 420/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2853 + 421/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2852 + 422/3417: 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$24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2841 + 433/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2840 + 434/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2839 + 435/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2838 + 436/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2837 + 437/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2836 + 438/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2835 + 439/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2834 + 440/3417: $24\decision_deferred[0:0] + 441/3417: $24\decision_ok[0:0] + 442/3417: $24\decision_detail[7:0] + 443/3417: $24\decision_fault[7:0] + 444/3417: $36\write_value[127:0] + 445/3417: $36\write_address[31:0] + 446/3417: $59\result_bytes[543:0] + 447/3417: $26\solved_b[127:0] + 448/3417: $26\solved_a[127:0] + 449/3417: $24\result_value[127:0] + 450/3417: $24\inv_value[127:0] + 451/3417: $24\val_c[127:0] + 452/3417: $24\val_b[127:0] + 453/3417: $24\val_a[127:0] + 454/3417: $24\taken_proposal[7:0] + 455/3417: $24\inv_present[7:0] + 456/3417: $24\pres_c[7:0] + 457/3417: $24\pres_b[7:0] + 458/3417: $24\pres_a[7:0] + 459/3417: $24\profile[7:0] + 460/3417: $31\deferred_local[31:0] + 461/3417: $31\deferred_target[31:0] + 462/3417: $26\next_fp_value[31:0] + 463/3417: $26\next_pc_value[31:0] + 464/3417: $24\proposed_fp[31:0] + 465/3417: $24\proposed_pc[31:0] + 466/3417: $24\base_index[31:0] + 467/3417: $24\addr_c[31:0] + 468/3417: $24\addr_b[31:0] + 469/3417: $24\addr_a[31:0] + 470/3417: $24\off_c[31:0] + 471/3417: $24\off_b[31:0] + 472/3417: $24\off_a[31:0] + 473/3417: $24\fp[31:0] + 474/3417: $24\pc[31:0] + 475/3417: $24\txn_id[31:0] + 476/3417: $55\result_length[31:0] + 477/3417: $31\n_deferred[31:0] + 478/3417: $36\n_writes[31:0] + 479/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [543:40] + 480/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [31:0] + 481/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [39:32] + 482/3417: $23\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2807 + 483/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2806 + 484/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2805 + 485/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2804 + 486/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2803 + 487/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2802 + 488/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2801 + 489/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2800 + 490/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2799 + 491/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2798 + 492/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2797 + 493/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2796 + 494/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2795 + 495/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2794 + 496/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2793 + 497/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2792 + 498/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2791 + 499/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2790 + 500/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2789 + 501/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2788 + 502/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2787 + 503/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2786 + 504/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2785 + 505/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2784 + 506/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2783 + 507/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2782 + 508/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2781 + 509/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2780 + 510/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2779 + 511/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2778 + 512/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2777 + 513/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2776 + 514/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2775 + 515/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2774 + 516/3417: $23\decision_deferred[0:0] + 517/3417: $23\decision_ok[0:0] + 518/3417: $23\decision_detail[7:0] + 519/3417: $23\decision_fault[7:0] + 520/3417: $35\write_value[127:0] + 521/3417: $35\write_address[31:0] + 522/3417: $58\result_bytes[543:0] + 523/3417: $25\solved_b[127:0] + 524/3417: $25\solved_a[127:0] + 525/3417: $23\result_value[127:0] + 526/3417: $23\inv_value[127:0] + 527/3417: $23\val_c[127:0] + 528/3417: $23\val_b[127:0] + 529/3417: $23\val_a[127:0] + 530/3417: $23\taken_proposal[7:0] + 531/3417: $23\inv_present[7:0] + 532/3417: $23\pres_c[7:0] + 533/3417: $23\pres_b[7:0] + 534/3417: $23\pres_a[7:0] + 535/3417: $23\profile[7:0] + 536/3417: $30\deferred_local[31:0] + 537/3417: $30\deferred_target[31:0] + 538/3417: $25\next_fp_value[31:0] + 539/3417: $25\next_pc_value[31:0] + 540/3417: $23\proposed_fp[31:0] + 541/3417: $23\proposed_pc[31:0] + 542/3417: $23\base_index[31:0] + 543/3417: $23\addr_c[31:0] + 544/3417: $23\addr_b[31:0] + 545/3417: $23\addr_a[31:0] + 546/3417: $23\off_c[31:0] + 547/3417: $23\off_b[31:0] + 548/3417: $23\off_a[31:0] + 549/3417: $23\fp[31:0] + 550/3417: $23\pc[31:0] + 551/3417: $23\txn_id[31:0] + 552/3417: $54\result_length[31:0] + 553/3417: $30\n_deferred[31:0] + 554/3417: $35\n_writes[31:0] + 555/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [543:40] + 556/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [31:0] + 557/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [39:32] + 558/3417: $22\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2749 + 559/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2748 + 560/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2747 + 561/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2746 + 562/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2745 + 563/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2744 + 564/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2743 + 565/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2742 + 566/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2741 + 567/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2740 + 568/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2739 + 569/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2738 + 570/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2737 + 571/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2736 + 572/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2735 + 573/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2734 + 574/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2733 + 575/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2732 + 576/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2731 + 577/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2730 + 578/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2729 + 579/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2728 + 580/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2727 + 581/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2726 + 582/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2725 + 583/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2724 + 584/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2723 + 585/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2722 + 586/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2721 + 587/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2720 + 588/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2719 + 589/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2718 + 590/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2717 + 591/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2716 + 592/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2715 + 593/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2714 + 594/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2713 + 595/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2712 + 596/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2711 + 597/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2710 + 598/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2709 + 599/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2708 + 600/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2707 + 601/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2706 + 602/3417: $22\decision_deferred[0:0] + 603/3417: $22\decision_ok[0:0] + 604/3417: $22\decision_detail[7:0] + 605/3417: $22\decision_fault[7:0] + 606/3417: $34\write_value[127:0] + 607/3417: $34\write_address[31:0] + 608/3417: $57\result_bytes[543:0] + 609/3417: $24\solved_b[127:0] + 610/3417: $24\solved_a[127:0] + 611/3417: $22\result_value[127:0] + 612/3417: $22\inv_value[127:0] + 613/3417: $22\val_c[127:0] + 614/3417: $22\val_b[127:0] + 615/3417: $22\val_a[127:0] + 616/3417: $22\taken_proposal[7:0] + 617/3417: $22\inv_present[7:0] + 618/3417: $22\pres_c[7:0] + 619/3417: $22\pres_b[7:0] + 620/3417: $22\pres_a[7:0] + 621/3417: $22\profile[7:0] + 622/3417: $29\deferred_local[31:0] + 623/3417: $29\deferred_target[31:0] + 624/3417: $24\next_fp_value[31:0] + 625/3417: $24\next_pc_value[31:0] + 626/3417: $22\proposed_fp[31:0] + 627/3417: $22\proposed_pc[31:0] + 628/3417: $22\base_index[31:0] + 629/3417: $22\addr_c[31:0] + 630/3417: $22\addr_b[31:0] + 631/3417: $22\addr_a[31:0] + 632/3417: $22\off_c[31:0] + 633/3417: $22\off_b[31:0] + 634/3417: $22\off_a[31:0] + 635/3417: $22\fp[31:0] + 636/3417: $22\pc[31:0] + 637/3417: $22\txn_id[31:0] + 638/3417: $53\result_length[31:0] + 639/3417: $29\n_deferred[31:0] + 640/3417: $34\n_writes[31:0] + 641/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [543:40] + 642/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [31:0] + 643/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [39:32] + 644/3417: $21\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2697 + 645/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2696 + 646/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2695 + 647/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2694 + 648/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2693 + 649/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2692 + 650/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2691 + 651/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2690 + 652/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2689 + 653/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2688 + 654/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2687 + 655/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2686 + 656/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2685 + 657/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2684 + 658/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2683 + 659/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2682 + 660/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2681 + 661/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2680 + 662/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2679 + 663/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2678 + 664/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2677 + 665/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2676 + 666/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2675 + 667/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2674 + 668/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2673 + 669/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2672 + 670/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2671 + 671/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2670 + 672/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2669 + 673/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2668 + 674/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2667 + 675/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2666 + 676/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2665 + 677/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2664 + 678/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2663 + 679/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2662 + 680/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2661 + 681/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2660 + 682/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2659 + 683/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2658 + 684/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2657 + 685/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2656 + 686/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2655 + 687/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2654 + 688/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2653 + 689/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2652 + 690/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2651 + 691/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2650 + 692/3417: $21\decision_deferred[0:0] + 693/3417: $21\decision_ok[0:0] + 694/3417: $21\decision_detail[7:0] + 695/3417: $21\decision_fault[7:0] + 696/3417: $33\write_value[127:0] + 697/3417: $33\write_address[31:0] + 698/3417: $56\result_bytes[543:0] + 699/3417: $23\solved_b[127:0] + 700/3417: $23\solved_a[127:0] + 701/3417: $21\result_value[127:0] + 702/3417: $21\inv_value[127:0] + 703/3417: $21\val_c[127:0] + 704/3417: $21\val_b[127:0] + 705/3417: $21\val_a[127:0] + 706/3417: $21\taken_proposal[7:0] + 707/3417: $21\inv_present[7:0] + 708/3417: $21\pres_c[7:0] + 709/3417: $21\pres_b[7:0] + 710/3417: $21\pres_a[7:0] + 711/3417: $21\profile[7:0] + 712/3417: $28\deferred_local[31:0] + 713/3417: $28\deferred_target[31:0] + 714/3417: $23\next_fp_value[31:0] + 715/3417: $23\next_pc_value[31:0] + 716/3417: $21\proposed_fp[31:0] + 717/3417: $21\proposed_pc[31:0] + 718/3417: $21\base_index[31:0] + 719/3417: $21\addr_c[31:0] + 720/3417: $21\addr_b[31:0] + 721/3417: $21\addr_a[31:0] + 722/3417: $21\off_c[31:0] + 723/3417: $21\off_b[31:0] + 724/3417: $21\off_a[31:0] + 725/3417: $21\fp[31:0] + 726/3417: $21\pc[31:0] + 727/3417: $21\txn_id[31:0] + 728/3417: $52\result_length[31:0] + 729/3417: $28\n_deferred[31:0] + 730/3417: $33\n_writes[31:0] + 731/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2598 [543:40] + 732/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2598 [31:0] + 733/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2598 [39:32] + 734/3417: $20\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2647 + 735/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2646 + 736/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2645 + 737/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2644 + 738/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2643 + 739/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2642 + 740/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2641 + 741/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2640 + 742/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2639 + 743/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2638 + 744/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2637 + 745/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2636 + 746/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2635 + 747/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2634 + 748/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2633 + 749/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2632 + 750/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2631 + 751/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2630 + 752/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2629 + 753/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2628 + 754/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2627 + 755/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2626 + 756/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2625 + 757/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2624 + 758/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2623 + 759/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2622 + 760/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2621 + 761/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2620 + 762/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2619 + 763/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2618 + 764/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2617 + 765/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2616 + 766/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2615 + 767/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2614 + 768/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2613 + 769/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2612 + 770/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2611 + 771/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2610 + 772/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2609 + 773/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2608 + 774/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2607 + 775/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2606 + 776/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2605 + 777/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2604 + 778/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2603 + 779/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2602 + 780/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2601 + 781/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2600 + 782/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2599 + 783/3417: $20\decision_deferred[0:0] + 784/3417: $20\decision_ok[0:0] + 785/3417: $20\decision_detail[7:0] + 786/3417: $20\decision_fault[7:0] + 787/3417: $32\write_value[127:0] + 788/3417: $32\write_address[31:0] + 789/3417: $55\result_bytes[543:0] + 790/3417: $22\solved_b[127:0] + 791/3417: $22\solved_a[127:0] + 792/3417: $20\result_value[127:0] + 793/3417: $20\inv_value[127:0] + 794/3417: $20\val_c[127:0] + 795/3417: $20\val_b[127:0] + 796/3417: $20\val_a[127:0] + 797/3417: $20\taken_proposal[7:0] + 798/3417: $20\inv_present[7:0] + 799/3417: $20\pres_c[7:0] + 800/3417: $20\pres_b[7:0] + 801/3417: $20\pres_a[7:0] + 802/3417: $20\profile[7:0] + 803/3417: $27\deferred_local[31:0] + 804/3417: $27\deferred_target[31:0] + 805/3417: $22\next_fp_value[31:0] + 806/3417: $22\next_pc_value[31:0] + 807/3417: $20\proposed_fp[31:0] + 808/3417: $20\proposed_pc[31:0] + 809/3417: $20\base_index[31:0] + 810/3417: $20\addr_c[31:0] + 811/3417: $20\addr_b[31:0] + 812/3417: $20\addr_a[31:0] + 813/3417: $20\off_c[31:0] + 814/3417: $20\off_b[31:0] + 815/3417: $20\off_a[31:0] + 816/3417: $20\fp[31:0] + 817/3417: $20\pc[31:0] + 818/3417: $20\txn_id[31:0] + 819/3417: $51\result_length[31:0] + 820/3417: $27\n_deferred[31:0] + 821/3417: $32\n_writes[31:0] + 822/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2546 [543:40] + 823/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2546 [31:0] + 824/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2546 [39:32] + 825/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2545 + 826/3417: $19\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2596 + 827/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2595 + 828/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2594 + 829/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2593 + 830/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2592 + 831/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2591 + 832/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2590 + 833/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2589 + 834/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2588 + 835/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2587 + 836/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2586 + 837/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2585 + 838/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2584 + 839/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2583 + 840/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2582 + 841/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2581 + 842/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2580 + 843/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2579 + 844/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2578 + 845/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2577 + 846/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2576 + 847/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2575 + 848/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2574 + 849/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2573 + 850/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2572 + 851/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2571 + 852/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2570 + 853/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2569 + 854/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2568 + 855/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2567 + 856/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2566 + 857/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2565 + 858/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2564 + 859/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2563 + 860/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2562 + 861/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2561 + 862/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2560 + 863/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2559 + 864/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2558 + 865/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2557 + 866/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2556 + 867/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2555 + 868/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2554 + 869/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2553 + 870/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2552 + 871/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2551 + 872/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2550 + 873/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2549 + 874/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2548 + 875/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2547 + 876/3417: $19\decision_deferred[0:0] + 877/3417: $19\decision_ok[0:0] + 878/3417: $19\decision_detail[7:0] + 879/3417: $19\decision_fault[7:0] + 880/3417: $31\write_value[127:0] + 881/3417: $31\write_address[31:0] + 882/3417: $54\result_bytes[543:0] + 883/3417: $21\solved_b[127:0] + 884/3417: $21\solved_a[127:0] + 885/3417: $19\result_value[127:0] + 886/3417: $19\inv_value[127:0] + 887/3417: $19\val_c[127:0] + 888/3417: $19\val_b[127:0] + 889/3417: $19\val_a[127:0] + 890/3417: $19\taken_proposal[7:0] + 891/3417: $19\inv_present[7:0] + 892/3417: $19\pres_c[7:0] + 893/3417: $19\pres_b[7:0] + 894/3417: $19\pres_a[7:0] + 895/3417: $19\profile[7:0] + 896/3417: $26\deferred_local[31:0] + 897/3417: $26\deferred_target[31:0] + 898/3417: $21\next_fp_value[31:0] + 899/3417: $21\next_pc_value[31:0] + 900/3417: $19\proposed_fp[31:0] + 901/3417: $19\proposed_pc[31:0] + 902/3417: $19\base_index[31:0] + 903/3417: $19\addr_c[31:0] + 904/3417: $19\addr_b[31:0] + 905/3417: $19\addr_a[31:0] + 906/3417: $19\off_c[31:0] + 907/3417: $19\off_b[31:0] + 908/3417: $19\off_a[31:0] + 909/3417: $19\fp[31:0] + 910/3417: $19\pc[31:0] + 911/3417: $19\txn_id[31:0] + 912/3417: $50\result_length[31:0] + 913/3417: $26\n_deferred[31:0] + 914/3417: $31\n_writes[31:0] + 915/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2469 [543:40] + 916/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2469 [31:0] + 917/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2469 [39:32] + 918/3417: $18\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2521 + 919/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2520 + 920/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2519 + 921/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2518 + 922/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2517 + 923/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2516 + 924/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2515 + 925/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2514 + 926/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2513 + 927/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2512 + 928/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2511 + 929/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2510 + 930/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2509 + 931/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2508 + 932/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2507 + 933/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2506 + 934/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2505 + 935/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2504 + 936/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2503 + 937/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2502 + 938/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2501 + 939/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2500 + 940/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2499 + 941/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2498 + 942/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2497 + 943/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2496 + 944/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2495 + 945/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2494 + 946/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2493 + 947/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2492 + 948/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2491 + 949/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2490 + 950/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2489 + 951/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2488 + 952/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2487 + 953/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2486 + 954/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2485 + 955/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2484 + 956/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2483 + 957/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2482 + 958/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2481 + 959/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2480 + 960/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2479 + 961/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2478 + 962/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2477 + 963/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2476 + 964/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2475 + 965/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2474 + 966/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2473 + 967/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2472 + 968/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2471 + 969/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2470 + 970/3417: $18\decision_deferred[0:0] + 971/3417: $18\decision_ok[0:0] + 972/3417: $18\decision_detail[7:0] + 973/3417: $18\decision_fault[7:0] + 974/3417: $30\write_value[127:0] + 975/3417: $30\write_address[31:0] + 976/3417: $53\result_bytes[543:0] + 977/3417: $20\solved_b[127:0] + 978/3417: $20\solved_a[127:0] + 979/3417: $18\result_value[127:0] + 980/3417: $18\inv_value[127:0] + 981/3417: $18\val_c[127:0] + 982/3417: $18\val_b[127:0] + 983/3417: $18\val_a[127:0] + 984/3417: $18\taken_proposal[7:0] + 985/3417: $18\inv_present[7:0] + 986/3417: $18\pres_c[7:0] + 987/3417: $18\pres_b[7:0] + 988/3417: $18\pres_a[7:0] + 989/3417: $18\profile[7:0] + 990/3417: $25\deferred_local[31:0] + 991/3417: $25\deferred_target[31:0] + 992/3417: $20\next_fp_value[31:0] + 993/3417: $20\next_pc_value[31:0] + 994/3417: $18\proposed_fp[31:0] + 995/3417: $18\proposed_pc[31:0] + 996/3417: $18\base_index[31:0] + 997/3417: $18\addr_c[31:0] + 998/3417: $18\addr_b[31:0] + 999/3417: $18\addr_a[31:0] + 1000/3417: $18\off_c[31:0] + 1001/3417: $18\off_b[31:0] + 1002/3417: $18\off_a[31:0] + 1003/3417: $18\fp[31:0] + 1004/3417: $18\pc[31:0] + 1005/3417: $18\txn_id[31:0] + 1006/3417: $49\result_length[31:0] + 1007/3417: $25\n_deferred[31:0] + 1008/3417: $30\n_writes[31:0] + 1009/3417: $20\retired_bytes[543:0] [127:96] + 1010/3417: $20\retired_bytes[543:0] [95:64] + 1011/3417: $20\retired_bytes[543:0] [63:32] + 1012/3417: $20\retired_bytes[543:0] [31:0] + 1013/3417: $20\retired_bytes[543:0] [543:128] + 1014/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2451 [31:0] + 1015/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2451 [39:32] + 1016/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2450 + 1017/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2449 + 1018/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2451 [543:40] + 1019/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2442 [543:40] + 1020/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2442 [31:0] + 1021/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2442 [39:32] + 1022/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2441 + 1023/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2445 + 1024/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2444 + 1025/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2443 + 1026/3417: $19\retired_bytes[543:0] + 1027/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2434 [543:40] + 1028/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2434 [31:0] + 1029/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2434 [39:32] + 1030/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2439 + 1031/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2438 + 1032/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2437 + 1033/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2436 + 1034/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2435 + 1035/3417: $18\retired_bytes[543:0] + 1036/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2379 + 1037/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2378 + 1038/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2377 + 1039/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2376 + 1040/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2375 + 1041/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2374 + 1042/3417: $17\retired_bytes[543:0] + 1043/3417: $17\txn_id[31:0] + 1044/3417: $17\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2432 + 1045/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2431 + 1046/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2430 + 1047/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2429 + 1048/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2428 + 1049/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2427 + 1050/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2426 + 1051/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2425 + 1052/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2424 + 1053/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2423 + 1054/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2422 + 1055/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2421 + 1056/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2420 + 1057/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2419 + 1058/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2418 + 1059/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2417 + 1060/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2416 + 1061/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2415 + 1062/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2414 + 1063/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2413 + 1064/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2412 + 1065/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2411 + 1066/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2410 + 1067/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2409 + 1068/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2408 + 1069/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2407 + 1070/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2406 + 1071/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2405 + 1072/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2404 + 1073/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2403 + 1074/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2402 + 1075/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2401 + 1076/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2400 + 1077/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2399 + 1078/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2398 + 1079/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2397 + 1080/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2396 + 1081/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2395 + 1082/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2394 + 1083/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2393 + 1084/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2392 + 1085/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2391 + 1086/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2390 + 1087/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2389 + 1088/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2388 + 1089/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2387 + 1090/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2386 + 1091/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2385 + 1092/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2384 + 1093/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2383 + 1094/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2382 + 1095/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2381 + 1096/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2380 + 1097/3417: $17\decision_deferred[0:0] + 1098/3417: $17\decision_ok[0:0] + 1099/3417: $17\decision_detail[7:0] + 1100/3417: $17\decision_fault[7:0] + 1101/3417: $29\write_value[127:0] + 1102/3417: $29\write_address[31:0] + 1103/3417: $52\result_bytes[543:0] + 1104/3417: $19\solved_b[127:0] + 1105/3417: $19\solved_a[127:0] + 1106/3417: $17\result_value[127:0] + 1107/3417: $17\inv_value[127:0] + 1108/3417: $17\val_c[127:0] + 1109/3417: $17\val_b[127:0] + 1110/3417: $17\val_a[127:0] + 1111/3417: $17\taken_proposal[7:0] + 1112/3417: $17\inv_present[7:0] + 1113/3417: $17\pres_c[7:0] + 1114/3417: $17\pres_b[7:0] + 1115/3417: $17\pres_a[7:0] + 1116/3417: $17\profile[7:0] + 1117/3417: $24\deferred_local[31:0] + 1118/3417: $24\deferred_target[31:0] + 1119/3417: $19\next_fp_value[31:0] + 1120/3417: $19\next_pc_value[31:0] + 1121/3417: $17\proposed_fp[31:0] + 1122/3417: $17\proposed_pc[31:0] + 1123/3417: $17\base_index[31:0] + 1124/3417: $17\addr_c[31:0] + 1125/3417: $17\addr_b[31:0] + 1126/3417: $17\addr_a[31:0] + 1127/3417: $17\off_c[31:0] + 1128/3417: $17\off_b[31:0] + 1129/3417: $17\off_a[31:0] + 1130/3417: $17\fp[31:0] + 1131/3417: $17\pc[31:0] + 1132/3417: $48\result_length[31:0] + 1133/3417: $24\n_deferred[31:0] + 1134/3417: $29\n_writes[31:0] + 1135/3417: $51\result_bytes[543:0] [111:80] + 1136/3417: $51\result_bytes[543:0] [79:48] + 1137/3417: $51\result_bytes[543:0] [47:40] + 1138/3417: $51\result_bytes[543:0] [39:32] + 1139/3417: $51\result_bytes[543:0] [31:16] + 1140/3417: $51\result_bytes[543:0] [15:8] + 1141/3417: $51\result_bytes[543:0] [7:0] + 1142/3417: $51\result_bytes[543:0] [543:112] + 1143/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2372 [31:0] + 1144/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2372 [39:32] + 1145/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2372 [543:40] + 1146/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2369 [543:40] + 1147/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2369 [31:0] + 1148/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2369 [39:32] + 1149/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2370 + 1150/3417: $50\result_bytes[543:0] + 1151/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2362 [543:40] + 1152/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2362 [31:0] + 1153/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2362 [39:32] + 1154/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2364 + 1155/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2363 + 1156/3417: $49\result_bytes[543:0] + 1157/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2358 [543:40] + 1158/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2358 [31:0] + 1159/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2358 [39:32] + 1160/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2361 + 1161/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2360 + 1162/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2359 + 1163/3417: $48\result_bytes[543:0] + 1164/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2352 [543:40] + 1165/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2352 [31:0] + 1166/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2352 [39:32] + 1167/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2356 + 1168/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2355 + 1169/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2354 + 1170/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2353 + 1171/3417: $47\result_bytes[543:0] + 1172/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2291 + 1173/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2290 + 1174/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2289 + 1175/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2288 + 1176/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2287 + 1177/3417: $46\result_bytes[543:0] + 1178/3417: $16\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2350 + 1179/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2349 + 1180/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2348 + 1181/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2347 + 1182/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2346 + 1183/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2345 + 1184/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2344 + 1185/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2343 + 1186/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2342 + 1187/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2341 + 1188/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2340 + 1189/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2339 + 1190/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2338 + 1191/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2337 + 1192/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2336 + 1193/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2335 + 1194/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2334 + 1195/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2333 + 1196/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2332 + 1197/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2331 + 1198/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2330 + 1199/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2329 + 1200/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2328 + 1201/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2327 + 1202/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2326 + 1203/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2325 + 1204/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2324 + 1205/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2323 + 1206/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2322 + 1207/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2321 + 1208/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2320 + 1209/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2319 + 1210/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2318 + 1211/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2317 + 1212/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2316 + 1213/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2315 + 1214/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2314 + 1215/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2313 + 1216/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2312 + 1217/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2311 + 1218/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2310 + 1219/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2309 + 1220/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2308 + 1221/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2307 + 1222/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2306 + 1223/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2305 + 1224/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2304 + 1225/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2303 + 1226/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2302 + 1227/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2301 + 1228/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2300 + 1229/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2299 + 1230/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2298 + 1231/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2297 + 1232/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2296 + 1233/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2295 + 1234/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2294 + 1235/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2293 + 1236/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2292 + 1237/3417: $16\decision_deferred[0:0] + 1238/3417: $16\decision_ok[0:0] + 1239/3417: $16\decision_detail[7:0] + 1240/3417: $16\decision_fault[7:0] + 1241/3417: $28\write_value[127:0] + 1242/3417: $28\write_address[31:0] + 1243/3417: $16\retired_bytes[543:0] + 1244/3417: $18\solved_b[127:0] + 1245/3417: $18\solved_a[127:0] + 1246/3417: $16\result_value[127:0] + 1247/3417: $16\inv_value[127:0] + 1248/3417: $16\val_c[127:0] + 1249/3417: $16\val_b[127:0] + 1250/3417: $16\val_a[127:0] + 1251/3417: $16\taken_proposal[7:0] + 1252/3417: $16\inv_present[7:0] + 1253/3417: $16\pres_c[7:0] + 1254/3417: $16\pres_b[7:0] + 1255/3417: $16\pres_a[7:0] + 1256/3417: $16\profile[7:0] + 1257/3417: $23\deferred_local[31:0] + 1258/3417: $23\deferred_target[31:0] + 1259/3417: $18\next_fp_value[31:0] + 1260/3417: $18\next_pc_value[31:0] + 1261/3417: $16\proposed_fp[31:0] + 1262/3417: $16\proposed_pc[31:0] + 1263/3417: $16\base_index[31:0] + 1264/3417: $16\addr_c[31:0] + 1265/3417: $16\addr_b[31:0] + 1266/3417: $16\addr_a[31:0] + 1267/3417: $16\off_c[31:0] + 1268/3417: $16\off_b[31:0] + 1269/3417: $16\off_a[31:0] + 1270/3417: $16\fp[31:0] + 1271/3417: $16\pc[31:0] + 1272/3417: $16\txn_id[31:0] + 1273/3417: $47\result_length[31:0] + 1274/3417: $23\n_deferred[31:0] + 1275/3417: $28\n_writes[31:0] + 1276/3417: $45\result_bytes[543:0] [159:152] + 1277/3417: $45\result_bytes[543:0] [151:120] + 1278/3417: $45\result_bytes[543:0] [119:88] + 1279/3417: $45\result_bytes[543:0] [87:80] + 1280/3417: $45\result_bytes[543:0] [79:48] + 1281/3417: $45\result_bytes[543:0] [47:40] + 1282/3417: $45\result_bytes[543:0] [39:8] + 1283/3417: $45\result_bytes[543:0] [7:0] + 1284/3417: $45\result_bytes[543:0] [543:160] + 1285/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2283 [31:0] + 1286/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2283 [39:32] + 1287/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2283 [543:40] + 1288/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2217 + 1289/3417: $44\result_bytes[543:0] + 1290/3417: $15\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2281 + 1291/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2280 + 1292/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2279 + 1293/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2278 + 1294/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2277 + 1295/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2276 + 1296/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2275 + 1297/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2274 + 1298/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2273 + 1299/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2272 + 1300/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2271 + 1301/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2270 + 1302/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2269 + 1303/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2268 + 1304/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2267 + 1305/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2266 + 1306/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2265 + 1307/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2264 + 1308/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2263 + 1309/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2262 + 1310/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2261 + 1311/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2260 + 1312/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2259 + 1313/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2258 + 1314/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2257 + 1315/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2256 + 1316/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2255 + 1317/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2254 + 1318/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2253 + 1319/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2252 + 1320/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2251 + 1321/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2250 + 1322/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2249 + 1323/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2248 + 1324/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2247 + 1325/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2246 + 1326/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2245 + 1327/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2244 + 1328/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2243 + 1329/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2242 + 1330/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2241 + 1331/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2240 + 1332/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2239 + 1333/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2238 + 1334/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2237 + 1335/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2236 + 1336/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2235 + 1337/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2234 + 1338/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2233 + 1339/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2232 + 1340/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2231 + 1341/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2230 + 1342/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2229 + 1343/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2228 + 1344/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2227 + 1345/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2226 + 1346/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2225 + 1347/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2224 + 1348/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2223 + 1349/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2222 + 1350/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2221 + 1351/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2220 + 1352/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2219 + 1353/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2218 + 1354/3417: $15\decision_deferred[0:0] + 1355/3417: $15\decision_ok[0:0] + 1356/3417: $15\decision_detail[7:0] + 1357/3417: $15\decision_fault[7:0] + 1358/3417: $27\write_value[127:0] + 1359/3417: $27\write_address[31:0] + 1360/3417: $15\retired_bytes[543:0] + 1361/3417: $17\solved_b[127:0] + 1362/3417: $17\solved_a[127:0] + 1363/3417: $15\result_value[127:0] + 1364/3417: $15\inv_value[127:0] + 1365/3417: $15\val_c[127:0] + 1366/3417: $15\val_b[127:0] + 1367/3417: $15\val_a[127:0] + 1368/3417: $15\taken_proposal[7:0] + 1369/3417: $15\inv_present[7:0] + 1370/3417: $15\pres_c[7:0] + 1371/3417: $15\pres_b[7:0] + 1372/3417: $15\pres_a[7:0] + 1373/3417: $15\profile[7:0] + 1374/3417: $22\deferred_local[31:0] + 1375/3417: $22\deferred_target[31:0] + 1376/3417: $17\next_fp_value[31:0] + 1377/3417: $17\next_pc_value[31:0] + 1378/3417: $15\proposed_fp[31:0] + 1379/3417: $15\proposed_pc[31:0] + 1380/3417: $15\base_index[31:0] + 1381/3417: $15\addr_c[31:0] + 1382/3417: $15\addr_b[31:0] + 1383/3417: $15\addr_a[31:0] + 1384/3417: $15\off_c[31:0] + 1385/3417: $15\off_b[31:0] + 1386/3417: $15\off_a[31:0] + 1387/3417: $15\fp[31:0] + 1388/3417: $15\pc[31:0] + 1389/3417: $15\txn_id[31:0] + 1390/3417: $46\result_length[31:0] + 1391/3417: $22\n_deferred[31:0] + 1392/3417: $27\n_writes[31:0] + 1393/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$2148 [543:40] + 1394/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$2148 [31:0] + 1395/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$2148 [39:32] + 1396/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$2147 + 1397/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$2146 + 1398/3417: $14\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2213 + 1399/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2212 + 1400/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2211 + 1401/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2210 + 1402/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2209 + 1403/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2208 + 1404/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2207 + 1405/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2206 + 1406/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2205 + 1407/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2204 + 1408/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2203 + 1409/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2202 + 1410/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2201 + 1411/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2200 + 1412/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2199 + 1413/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2198 + 1414/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2197 + 1415/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2196 + 1416/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2195 + 1417/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2194 + 1418/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2193 + 1419/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2192 + 1420/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2191 + 1421/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2190 + 1422/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2189 + 1423/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2188 + 1424/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2187 + 1425/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2186 + 1426/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2185 + 1427/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2184 + 1428/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2183 + 1429/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2182 + 1430/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2181 + 1431/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2180 + 1432/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2179 + 1433/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2178 + 1434/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2177 + 1435/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2176 + 1436/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2175 + 1437/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2174 + 1438/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2173 + 1439/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2172 + 1440/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2171 + 1441/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2170 + 1442/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2169 + 1443/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2168 + 1444/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2167 + 1445/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2166 + 1446/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2165 + 1447/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2164 + 1448/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2163 + 1449/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2162 + 1450/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2161 + 1451/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2160 + 1452/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2159 + 1453/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2158 + 1454/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2157 + 1455/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2156 + 1456/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2155 + 1457/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2154 + 1458/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2153 + 1459/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2152 + 1460/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2151 + 1461/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2150 + 1462/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2149 + 1463/3417: $14\decision_deferred[0:0] + 1464/3417: $14\decision_ok[0:0] + 1465/3417: $14\decision_detail[7:0] + 1466/3417: $14\decision_fault[7:0] + 1467/3417: $26\write_value[127:0] + 1468/3417: $26\write_address[31:0] + 1469/3417: $14\retired_bytes[543:0] + 1470/3417: $43\result_bytes[543:0] + 1471/3417: $16\solved_b[127:0] + 1472/3417: $16\solved_a[127:0] + 1473/3417: $14\result_value[127:0] + 1474/3417: $14\inv_value[127:0] + 1475/3417: $14\val_c[127:0] + 1476/3417: $14\val_b[127:0] + 1477/3417: $14\val_a[127:0] + 1478/3417: $14\taken_proposal[7:0] + 1479/3417: $14\inv_present[7:0] + 1480/3417: $14\pres_c[7:0] + 1481/3417: $14\pres_b[7:0] + 1482/3417: $14\pres_a[7:0] + 1483/3417: $14\profile[7:0] + 1484/3417: $21\deferred_local[31:0] + 1485/3417: $21\deferred_target[31:0] + 1486/3417: $16\next_fp_value[31:0] + 1487/3417: $16\next_pc_value[31:0] + 1488/3417: $14\proposed_fp[31:0] + 1489/3417: $14\proposed_pc[31:0] + 1490/3417: $14\base_index[31:0] + 1491/3417: $14\addr_c[31:0] + 1492/3417: $14\addr_b[31:0] + 1493/3417: $14\addr_a[31:0] + 1494/3417: $14\off_c[31:0] + 1495/3417: $14\off_b[31:0] + 1496/3417: $14\off_a[31:0] + 1497/3417: $14\fp[31:0] + 1498/3417: $14\pc[31:0] + 1499/3417: $14\txn_id[31:0] + 1500/3417: $45\result_length[31:0] + 1501/3417: $21\n_deferred[31:0] + 1502/3417: $26\n_writes[31:0] + 1503/3417: $13\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2145 + 1504/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2144 + 1505/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2143 + 1506/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2142 + 1507/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2141 + 1508/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2140 + 1509/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2139 + 1510/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2138 + 1511/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2137 + 1512/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2136 + 1513/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2135 + 1514/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2134 + 1515/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2133 + 1516/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2132 + 1517/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2131 + 1518/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2130 + 1519/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2129 + 1520/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2128 + 1521/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2127 + 1522/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2126 + 1523/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2125 + 1524/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2124 + 1525/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2123 + 1526/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2122 + 1527/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2121 + 1528/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2120 + 1529/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2119 + 1530/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2118 + 1531/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2117 + 1532/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2116 + 1533/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2115 + 1534/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2114 + 1535/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2113 + 1536/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2112 + 1537/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2111 + 1538/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2110 + 1539/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2109 + 1540/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2108 + 1541/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2107 + 1542/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2106 + 1543/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2105 + 1544/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2104 + 1545/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2103 + 1546/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2102 + 1547/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2101 + 1548/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2100 + 1549/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2099 + 1550/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2098 + 1551/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2097 + 1552/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2096 + 1553/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2095 + 1554/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2094 + 1555/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2093 + 1556/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2092 + 1557/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2091 + 1558/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2090 + 1559/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2089 + 1560/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2088 + 1561/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2087 + 1562/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2086 + 1563/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2085 + 1564/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2084 + 1565/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2083 + 1566/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2082 + 1567/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2081 + 1568/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$2080 + 1569/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$2079 + 1570/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$2078 + 1571/3417: $13\decision_deferred[0:0] + 1572/3417: $13\decision_ok[0:0] + 1573/3417: $13\decision_detail[7:0] + 1574/3417: $13\decision_fault[7:0] + 1575/3417: $25\write_value[127:0] + 1576/3417: $25\write_address[31:0] + 1577/3417: $13\retired_bytes[543:0] + 1578/3417: $42\result_bytes[543:0] + 1579/3417: $15\solved_b[127:0] + 1580/3417: $15\solved_a[127:0] + 1581/3417: $13\result_value[127:0] + 1582/3417: $13\inv_value[127:0] + 1583/3417: $13\val_c[127:0] + 1584/3417: $13\val_b[127:0] + 1585/3417: $13\val_a[127:0] + 1586/3417: $13\taken_proposal[7:0] + 1587/3417: $13\inv_present[7:0] + 1588/3417: $13\pres_c[7:0] + 1589/3417: $13\pres_b[7:0] + 1590/3417: $13\pres_a[7:0] + 1591/3417: $13\profile[7:0] + 1592/3417: $20\deferred_local[31:0] + 1593/3417: $20\deferred_target[31:0] + 1594/3417: $15\next_fp_value[31:0] + 1595/3417: $15\next_pc_value[31:0] + 1596/3417: $13\proposed_fp[31:0] + 1597/3417: $13\proposed_pc[31:0] + 1598/3417: $13\base_index[31:0] + 1599/3417: $13\addr_c[31:0] + 1600/3417: $13\addr_b[31:0] + 1601/3417: $13\addr_a[31:0] + 1602/3417: $13\off_c[31:0] + 1603/3417: $13\off_b[31:0] + 1604/3417: $13\off_a[31:0] + 1605/3417: $13\fp[31:0] + 1606/3417: $13\pc[31:0] + 1607/3417: $13\txn_id[31:0] + 1608/3417: $44\result_length[31:0] + 1609/3417: $20\n_deferred[31:0] + 1610/3417: $25\n_writes[31:0] + 1611/3417: $43\result_length[31:0] + 1612/3417: $41\result_bytes[215:152] [63:32] + 1613/3417: $41\result_bytes[215:152] [31:0] + 1614/3417: $40\result_bytes[279:104] [111:80] + 1615/3417: $40\result_bytes[279:104] [47:40] + 1616/3417: $40\result_bytes[279:104] [15:8] + 1617/3417: $40\result_bytes[279:104] [143:112] + 1618/3417: $42\result_length[31:0] + 1619/3417: $40\result_bytes[279:104] [79:72] + 1620/3417: $40\result_bytes[279:104] [71:48] + 1621/3417: $40\result_bytes[279:104] [39:16] + 1622/3417: $40\result_bytes[279:104] [175:144] + 1623/3417: $40\result_bytes[279:104] [7:0] + 1624/3417: $38\result_bytes[375:104] [175:168] + 1625/3417: $39\result_bytes[375:312] [63:32] + 1626/3417: $39\result_bytes[375:312] [31:0] + 1627/3417: $38\result_bytes[375:104] [207:176] + 1628/3417: $40\result_length[31:0] + 1629/3417: $41\result_length[31:0] + 1630/3417: $38\result_bytes[375:104] [167:160] + 1631/3417: $38\result_bytes[375:104] [159:32] + 1632/3417: $38\result_bytes[375:104] [31:0] + 1633/3417: $38\result_bytes[375:104] [271:208] + 1634/3417: $24\n_writes[31:0] + 1635/3417: $24\write_value[127:0] + 1636/3417: $24\write_address[31:0] + 1637/3417: $37\result_bytes[543:0] [375:104] + 1638/3417: $37\result_bytes[543:0] [103:96] + 1639/3417: $37\result_bytes[543:0] [95:64] + 1640/3417: $37\result_bytes[543:0] [63:32] + 1641/3417: $37\result_bytes[543:0] [31:0] + 1642/3417: $37\result_bytes[543:0] [543:376] + 1643/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$2073 [31:0] + 1644/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$2073 [39:32] + 1645/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$2072 + 1646/3417: $23\write_value[127:0] + 1647/3417: $23\write_address[31:0] + 1648/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$2073 [543:40] + 1649/3417: $39\result_length[31:0] + 1650/3417: $23\n_writes[31:0] + 1651/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$2066 [543:40] + 1652/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$2066 [31:0] + 1653/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$2066 [39:32] + 1654/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$2065 + 1655/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$2069 + 1656/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$2068 + 1657/3417: $13\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$2067 + 1658/3417: $22\write_value[127:0] + 1659/3417: $22\write_address[31:0] + 1660/3417: $36\result_bytes[543:0] + 1661/3417: $38\result_length[31:0] + 1662/3417: $22\n_writes[31:0] + 1663/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1996 + 1664/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1995 + 1665/3417: $12\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1994 + 1666/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1993 + 1667/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1992 + 1668/3417: $21\write_value[127:0] + 1669/3417: $21\write_address[31:0] + 1670/3417: $35\result_bytes[543:0] + 1671/3417: $37\result_length[31:0] + 1672/3417: $21\n_writes[31:0] + 1673/3417: $12\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2064 + 1674/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2063 + 1675/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2062 + 1676/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2061 + 1677/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2060 + 1678/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2059 + 1679/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2058 + 1680/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2057 + 1681/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2056 + 1682/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2055 + 1683/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2054 + 1684/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2053 + 1685/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2052 + 1686/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2051 + 1687/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2050 + 1688/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2049 + 1689/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2048 + 1690/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2047 + 1691/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2046 + 1692/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2045 + 1693/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2044 + 1694/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2043 + 1695/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2042 + 1696/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2041 + 1697/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2040 + 1698/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2039 + 1699/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2038 + 1700/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2037 + 1701/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2036 + 1702/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2035 + 1703/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2034 + 1704/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2033 + 1705/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2032 + 1706/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2031 + 1707/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2030 + 1708/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2029 + 1709/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2028 + 1710/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2027 + 1711/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2026 + 1712/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2025 + 1713/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2024 + 1714/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2023 + 1715/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2022 + 1716/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2021 + 1717/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2020 + 1718/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2019 + 1719/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2018 + 1720/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2017 + 1721/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2016 + 1722/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2015 + 1723/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2014 + 1724/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2013 + 1725/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2012 + 1726/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2011 + 1727/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2010 + 1728/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2009 + 1729/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2008 + 1730/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2007 + 1731/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2006 + 1732/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2005 + 1733/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2004 + 1734/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2003 + 1735/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2002 + 1736/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2001 + 1737/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2000 + 1738/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1999 + 1739/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1998 + 1740/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1997 + 1741/3417: $12\decision_deferred[0:0] + 1742/3417: $12\decision_ok[0:0] + 1743/3417: $12\decision_detail[7:0] + 1744/3417: $12\decision_fault[7:0] + 1745/3417: $12\retired_bytes[543:0] + 1746/3417: $14\solved_b[127:0] + 1747/3417: $14\solved_a[127:0] + 1748/3417: $12\result_value[127:0] + 1749/3417: $12\inv_value[127:0] + 1750/3417: $12\val_c[127:0] + 1751/3417: $12\val_b[127:0] + 1752/3417: $12\val_a[127:0] + 1753/3417: $12\taken_proposal[7:0] + 1754/3417: $12\inv_present[7:0] + 1755/3417: $12\pres_c[7:0] + 1756/3417: $12\pres_b[7:0] + 1757/3417: $12\pres_a[7:0] + 1758/3417: $12\profile[7:0] + 1759/3417: $19\deferred_local[31:0] + 1760/3417: $19\deferred_target[31:0] + 1761/3417: $14\next_fp_value[31:0] + 1762/3417: $14\next_pc_value[31:0] + 1763/3417: $12\proposed_fp[31:0] + 1764/3417: $12\proposed_pc[31:0] + 1765/3417: $12\base_index[31:0] + 1766/3417: $12\addr_c[31:0] + 1767/3417: $12\addr_b[31:0] + 1768/3417: $12\addr_a[31:0] + 1769/3417: $12\off_c[31:0] + 1770/3417: $12\off_b[31:0] + 1771/3417: $12\off_a[31:0] + 1772/3417: $12\fp[31:0] + 1773/3417: $12\pc[31:0] + 1774/3417: $12\txn_id[31:0] + 1775/3417: $19\n_deferred[31:0] + 1776/3417: $13\solved_a[127:0] + 1777/3417: $13\solved_b[127:0] + 1778/3417: $20\n_writes[31:0] + 1779/3417: $20\write_value[127:0] + 1780/3417: $20\write_address[31:0] + 1781/3417: $12\solved_b[127:0] + 1782/3417: $12\solved_a[127:0] + 1783/3417: $11\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1984 + 1784/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1983 + 1785/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1982 + 1786/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1981 + 1787/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1980 + 1788/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1979 + 1789/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1978 + 1790/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1977 + 1791/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1976 + 1792/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1975 + 1793/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1974 + 1794/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1973 + 1795/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1972 + 1796/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1971 + 1797/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1970 + 1798/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1969 + 1799/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1968 + 1800/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1967 + 1801/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1966 + 1802/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1965 + 1803/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1964 + 1804/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1963 + 1805/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1962 + 1806/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1961 + 1807/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1960 + 1808/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1959 + 1809/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1958 + 1810/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1957 + 1811/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1956 + 1812/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1955 + 1813/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1954 + 1814/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1953 + 1815/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1952 + 1816/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1951 + 1817/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1950 + 1818/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1949 + 1819/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1948 + 1820/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1947 + 1821/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1946 + 1822/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1945 + 1823/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1944 + 1824/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1943 + 1825/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1942 + 1826/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1941 + 1827/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1940 + 1828/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1939 + 1829/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1938 + 1830/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1937 + 1831/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1936 + 1832/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1935 + 1833/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1934 + 1834/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1933 + 1835/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1932 + 1836/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1931 + 1837/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1930 + 1838/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1929 + 1839/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1928 + 1840/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1927 + 1841/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1926 + 1842/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1925 + 1843/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1924 + 1844/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1923 + 1845/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1922 + 1846/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1921 + 1847/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1920 + 1848/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1919 + 1849/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1918 + 1850/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1917 + 1851/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1916 + 1852/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1915 + 1853/3417: $11\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1914 + 1854/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1913 + 1855/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1912 + 1856/3417: $11\decision_deferred[0:0] + 1857/3417: $11\decision_ok[0:0] + 1858/3417: $11\decision_detail[7:0] + 1859/3417: $11\decision_fault[7:0] + 1860/3417: $11\retired_bytes[543:0] + 1861/3417: $34\result_bytes[543:0] + 1862/3417: $11\result_value[127:0] + 1863/3417: $11\inv_value[127:0] + 1864/3417: $11\val_c[127:0] + 1865/3417: $11\val_b[127:0] + 1866/3417: $11\val_a[127:0] + 1867/3417: $11\taken_proposal[7:0] + 1868/3417: $11\inv_present[7:0] + 1869/3417: $11\pres_c[7:0] + 1870/3417: $11\pres_b[7:0] + 1871/3417: $11\pres_a[7:0] + 1872/3417: $11\profile[7:0] + 1873/3417: $18\deferred_local[31:0] + 1874/3417: $18\deferred_target[31:0] + 1875/3417: $13\next_fp_value[31:0] + 1876/3417: $13\next_pc_value[31:0] + 1877/3417: $11\proposed_fp[31:0] + 1878/3417: $11\proposed_pc[31:0] + 1879/3417: $11\base_index[31:0] + 1880/3417: $11\addr_c[31:0] + 1881/3417: $11\addr_b[31:0] + 1882/3417: $11\addr_a[31:0] + 1883/3417: $11\off_c[31:0] + 1884/3417: $11\off_b[31:0] + 1885/3417: $11\off_a[31:0] + 1886/3417: $11\fp[31:0] + 1887/3417: $11\pc[31:0] + 1888/3417: $11\txn_id[31:0] + 1889/3417: $36\result_length[31:0] + 1890/3417: $18\n_deferred[31:0] + 1891/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1909 [543:40] + 1892/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1909 [31:0] + 1893/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1909 [39:32] + 1894/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1908 + 1895/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1832 + 1896/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1831 + 1897/3417: $10\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1905 + 1898/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1904 + 1899/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1903 + 1900/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1902 + 1901/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1901 + 1902/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1900 + 1903/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1899 + 1904/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1898 + 1905/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1897 + 1906/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1896 + 1907/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1895 + 1908/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1894 + 1909/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1893 + 1910/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1892 + 1911/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1891 + 1912/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1890 + 1913/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1889 + 1914/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1888 + 1915/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1887 + 1916/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1886 + 1917/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1885 + 1918/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1884 + 1919/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1883 + 1920/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1882 + 1921/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1881 + 1922/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1880 + 1923/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1879 + 1924/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1878 + 1925/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1877 + 1926/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1876 + 1927/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1875 + 1928/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1874 + 1929/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1873 + 1930/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1872 + 1931/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1871 + 1932/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1870 + 1933/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1869 + 1934/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1868 + 1935/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1867 + 1936/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1866 + 1937/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1865 + 1938/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1864 + 1939/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1863 + 1940/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1862 + 1941/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1861 + 1942/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1860 + 1943/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1859 + 1944/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1858 + 1945/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1857 + 1946/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1856 + 1947/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1855 + 1948/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1854 + 1949/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1853 + 1950/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1852 + 1951/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1851 + 1952/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1850 + 1953/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1849 + 1954/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1848 + 1955/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1847 + 1956/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1846 + 1957/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1845 + 1958/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1844 + 1959/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1843 + 1960/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1842 + 1961/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1841 + 1962/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1840 + 1963/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1839 + 1964/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1838 + 1965/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1837 + 1966/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1836 + 1967/3417: $10\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1835 + 1968/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1834 + 1969/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1833 + 1970/3417: $10\decision_deferred[0:0] + 1971/3417: $10\decision_ok[0:0] + 1972/3417: $10\decision_detail[7:0] + 1973/3417: $10\decision_fault[7:0] + 1974/3417: $19\write_value[127:0] + 1975/3417: $19\write_address[31:0] + 1976/3417: $10\retired_bytes[543:0] + 1977/3417: $33\result_bytes[543:0] + 1978/3417: $11\solved_b[127:0] + 1979/3417: $11\solved_a[127:0] + 1980/3417: $10\result_value[127:0] + 1981/3417: $10\inv_value[127:0] + 1982/3417: $10\val_c[127:0] + 1983/3417: $10\val_b[127:0] + 1984/3417: $10\val_a[127:0] + 1985/3417: $10\taken_proposal[7:0] + 1986/3417: $10\inv_present[7:0] + 1987/3417: $10\pres_c[7:0] + 1988/3417: $10\pres_b[7:0] + 1989/3417: $10\pres_a[7:0] + 1990/3417: $10\profile[7:0] + 1991/3417: $17\deferred_local[31:0] + 1992/3417: $17\deferred_target[31:0] + 1993/3417: $12\next_fp_value[31:0] + 1994/3417: $12\next_pc_value[31:0] + 1995/3417: $10\proposed_fp[31:0] + 1996/3417: $10\proposed_pc[31:0] + 1997/3417: $10\base_index[31:0] + 1998/3417: $10\addr_c[31:0] + 1999/3417: $10\addr_b[31:0] + 2000/3417: $10\addr_a[31:0] + 2001/3417: $10\off_c[31:0] + 2002/3417: $10\off_b[31:0] + 2003/3417: $10\off_a[31:0] + 2004/3417: $10\fp[31:0] + 2005/3417: $10\pc[31:0] + 2006/3417: $10\txn_id[31:0] + 2007/3417: $35\result_length[31:0] + 2008/3417: $17\n_deferred[31:0] + 2009/3417: $19\n_writes[31:0] + 2010/3417: $10\solved_a[127:0] + 2011/3417: $10\solved_b[127:0] + 2012/3417: $18\n_writes[31:0] + 2013/3417: $18\write_value[127:0] + 2014/3417: $18\write_address[31:0] + 2015/3417: $9\solved_b[127:0] + 2016/3417: $9\solved_a[127:0] + 2017/3417: $9\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1825 + 2018/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1824 + 2019/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1823 + 2020/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1822 + 2021/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1821 + 2022/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1820 + 2023/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1819 + 2024/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1818 + 2025/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1817 + 2026/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1816 + 2027/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1815 + 2028/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1814 + 2029/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1813 + 2030/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1812 + 2031/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1811 + 2032/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1810 + 2033/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1809 + 2034/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1808 + 2035/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1807 + 2036/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1806 + 2037/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1805 + 2038/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1804 + 2039/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1803 + 2040/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1802 + 2041/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1801 + 2042/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1800 + 2043/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1799 + 2044/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1798 + 2045/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1797 + 2046/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1796 + 2047/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1795 + 2048/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1794 + 2049/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1793 + 2050/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1792 + 2051/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1791 + 2052/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1790 + 2053/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1789 + 2054/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1788 + 2055/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1787 + 2056/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1786 + 2057/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1785 + 2058/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1784 + 2059/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1783 + 2060/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1782 + 2061/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1781 + 2062/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1780 + 2063/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1779 + 2064/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1778 + 2065/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1777 + 2066/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1776 + 2067/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1775 + 2068/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1774 + 2069/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1773 + 2070/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1772 + 2071/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1771 + 2072/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1770 + 2073/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1769 + 2074/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1768 + 2075/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1767 + 2076/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1766 + 2077/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1765 + 2078/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1764 + 2079/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1763 + 2080/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1762 + 2081/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1761 + 2082/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1760 + 2083/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1759 + 2084/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1758 + 2085/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1757 + 2086/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1756 + 2087/3417: $9\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1755 + 2088/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1754 + 2089/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1753 + 2090/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1752 + 2091/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1751 + 2092/3417: $9\decision_deferred[0:0] + 2093/3417: $9\decision_ok[0:0] + 2094/3417: $9\decision_detail[7:0] + 2095/3417: $9\decision_fault[7:0] + 2096/3417: $9\retired_bytes[543:0] + 2097/3417: $32\result_bytes[543:0] + 2098/3417: $9\result_value[127:0] + 2099/3417: $9\inv_value[127:0] + 2100/3417: $9\val_c[127:0] + 2101/3417: $9\val_b[127:0] + 2102/3417: $9\val_a[127:0] + 2103/3417: $9\taken_proposal[7:0] + 2104/3417: $9\inv_present[7:0] + 2105/3417: $9\pres_c[7:0] + 2106/3417: $9\pres_b[7:0] + 2107/3417: $9\pres_a[7:0] + 2108/3417: $9\profile[7:0] + 2109/3417: $16\deferred_local[31:0] + 2110/3417: $16\deferred_target[31:0] + 2111/3417: $11\next_fp_value[31:0] + 2112/3417: $11\next_pc_value[31:0] + 2113/3417: $9\proposed_fp[31:0] + 2114/3417: $9\proposed_pc[31:0] + 2115/3417: $9\base_index[31:0] + 2116/3417: $9\addr_c[31:0] + 2117/3417: $9\addr_b[31:0] + 2118/3417: $9\addr_a[31:0] + 2119/3417: $9\off_c[31:0] + 2120/3417: $9\off_b[31:0] + 2121/3417: $9\off_a[31:0] + 2122/3417: $9\fp[31:0] + 2123/3417: $9\pc[31:0] + 2124/3417: $9\txn_id[31:0] + 2125/3417: $34\result_length[31:0] + 2126/3417: $16\n_deferred[31:0] + 2127/3417: $33\result_length[31:0] + 2128/3417: $31\result_bytes[279:104] [47:40] + 2129/3417: $31\result_bytes[279:104] [15:8] + 2130/3417: $31\result_bytes[279:104] [39:16] + 2131/3417: $31\result_bytes[279:104] [143:112] + 2132/3417: $31\result_bytes[279:104] [111:80] + 2133/3417: $31\result_bytes[279:104] [79:72] + 2134/3417: $31\result_bytes[279:104] [71:48] + 2135/3417: $32\result_length[31:0] + 2136/3417: $31\result_bytes[279:104] [175:144] + 2137/3417: $31\result_bytes[279:104] [7:0] + 2138/3417: $30\result_bytes[311:104] [175:168] + 2139/3417: $30\result_length[31:0] + 2140/3417: $30\result_bytes[311:104] [207:176] + 2141/3417: $30\result_bytes[311:104] [167:160] + 2142/3417: $30\result_bytes[311:104] [159:32] + 2143/3417: $30\result_bytes[311:104] [31:0] + 2144/3417: $31\result_length[31:0] + 2145/3417: $29\result_bytes[543:0] [311:104] + 2146/3417: $29\result_bytes[543:0] [103:96] + 2147/3417: $29\result_bytes[543:0] [95:64] + 2148/3417: $29\result_bytes[543:0] [63:32] + 2149/3417: $29\result_bytes[543:0] [31:0] + 2150/3417: $29\result_bytes[543:0] [543:312] + 2151/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1746 [31:0] + 2152/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1746 [39:32] + 2153/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1745 + 2154/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1746 [543:40] + 2155/3417: $29\result_length[31:0] + 2156/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1667 + 2157/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1666 + 2158/3417: $28\result_bytes[543:0] + 2159/3417: $28\result_length[31:0] + 2160/3417: $8\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1742 + 2161/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1741 + 2162/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1740 + 2163/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1739 + 2164/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1738 + 2165/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1737 + 2166/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1736 + 2167/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1735 + 2168/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1734 + 2169/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1733 + 2170/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1732 + 2171/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1731 + 2172/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1730 + 2173/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1729 + 2174/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1728 + 2175/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1727 + 2176/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1726 + 2177/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1725 + 2178/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1724 + 2179/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1723 + 2180/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1722 + 2181/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1721 + 2182/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1720 + 2183/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1719 + 2184/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1718 + 2185/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1717 + 2186/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1716 + 2187/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1715 + 2188/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1714 + 2189/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1713 + 2190/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1712 + 2191/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1711 + 2192/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1710 + 2193/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1709 + 2194/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1708 + 2195/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1707 + 2196/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1706 + 2197/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1705 + 2198/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1704 + 2199/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1703 + 2200/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1702 + 2201/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1701 + 2202/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1700 + 2203/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1699 + 2204/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1698 + 2205/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1697 + 2206/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1696 + 2207/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1695 + 2208/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1694 + 2209/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1693 + 2210/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1692 + 2211/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1691 + 2212/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1690 + 2213/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1689 + 2214/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1688 + 2215/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1687 + 2216/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1686 + 2217/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1685 + 2218/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1684 + 2219/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1683 + 2220/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1682 + 2221/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1681 + 2222/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1680 + 2223/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1679 + 2224/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1678 + 2225/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1677 + 2226/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1676 + 2227/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1675 + 2228/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1674 + 2229/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1673 + 2230/3417: $8\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1672 + 2231/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1671 + 2232/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1670 + 2233/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1669 + 2234/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1668 + 2235/3417: $8\decision_deferred[0:0] + 2236/3417: $8\decision_ok[0:0] + 2237/3417: $8\decision_detail[7:0] + 2238/3417: $8\decision_fault[7:0] + 2239/3417: $17\write_value[127:0] + 2240/3417: $17\write_address[31:0] + 2241/3417: $8\retired_bytes[543:0] + 2242/3417: $8\solved_b[127:0] + 2243/3417: $8\solved_a[127:0] + 2244/3417: $8\result_value[127:0] + 2245/3417: $8\inv_value[127:0] + 2246/3417: $8\val_c[127:0] + 2247/3417: $8\val_b[127:0] + 2248/3417: $8\val_a[127:0] + 2249/3417: $8\taken_proposal[7:0] + 2250/3417: $8\inv_present[7:0] + 2251/3417: $8\pres_c[7:0] + 2252/3417: $8\pres_b[7:0] + 2253/3417: $8\pres_a[7:0] + 2254/3417: $8\profile[7:0] + 2255/3417: $15\deferred_local[31:0] + 2256/3417: $15\deferred_target[31:0] + 2257/3417: $10\next_fp_value[31:0] + 2258/3417: $10\next_pc_value[31:0] + 2259/3417: $8\proposed_fp[31:0] + 2260/3417: $8\proposed_pc[31:0] + 2261/3417: $8\base_index[31:0] + 2262/3417: $8\addr_c[31:0] + 2263/3417: $8\addr_b[31:0] + 2264/3417: $8\addr_a[31:0] + 2265/3417: $8\off_c[31:0] + 2266/3417: $8\off_b[31:0] + 2267/3417: $8\off_a[31:0] + 2268/3417: $8\fp[31:0] + 2269/3417: $8\pc[31:0] + 2270/3417: $8\txn_id[31:0] + 2271/3417: $15\n_deferred[31:0] + 2272/3417: $17\n_writes[31:0] + 2273/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1663 [543:40] + 2274/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1663 [31:0] + 2275/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1663 [39:32] + 2276/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1662 + 2277/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1582 + 2278/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1581 + 2279/3417: $7\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1659 + 2280/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1658 + 2281/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1657 + 2282/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1656 + 2283/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1655 + 2284/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1654 + 2285/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1653 + 2286/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1652 + 2287/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1651 + 2288/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1650 + 2289/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1649 + 2290/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1648 + 2291/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1647 + 2292/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1646 + 2293/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1645 + 2294/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1644 + 2295/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1643 + 2296/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1642 + 2297/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1641 + 2298/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1640 + 2299/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1639 + 2300/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1638 + 2301/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1637 + 2302/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1636 + 2303/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1635 + 2304/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1634 + 2305/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1633 + 2306/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1632 + 2307/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1631 + 2308/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1630 + 2309/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1629 + 2310/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1628 + 2311/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1627 + 2312/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1626 + 2313/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1625 + 2314/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1624 + 2315/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1623 + 2316/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1622 + 2317/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1621 + 2318/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1620 + 2319/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1619 + 2320/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1618 + 2321/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1617 + 2322/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1616 + 2323/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1615 + 2324/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1614 + 2325/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1613 + 2326/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1612 + 2327/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1611 + 2328/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1610 + 2329/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1609 + 2330/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1608 + 2331/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1607 + 2332/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1606 + 2333/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1605 + 2334/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1604 + 2335/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1603 + 2336/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1602 + 2337/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1601 + 2338/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1600 + 2339/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1599 + 2340/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1598 + 2341/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1597 + 2342/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1596 + 2343/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1595 + 2344/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1594 + 2345/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1593 + 2346/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1592 + 2347/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1591 + 2348/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1590 + 2349/3417: $7\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1589 + 2350/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1588 + 2351/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1587 + 2352/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1586 + 2353/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1585 + 2354/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1584 + 2355/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1583 + 2356/3417: $7\decision_deferred[0:0] + 2357/3417: $7\decision_ok[0:0] + 2358/3417: $7\decision_detail[7:0] + 2359/3417: $7\decision_fault[7:0] + 2360/3417: $16\write_value[127:0] + 2361/3417: $16\write_address[31:0] + 2362/3417: $7\retired_bytes[543:0] + 2363/3417: $27\result_bytes[543:0] + 2364/3417: $7\solved_b[127:0] + 2365/3417: $7\solved_a[127:0] + 2366/3417: $7\result_value[127:0] + 2367/3417: $7\inv_value[127:0] + 2368/3417: $7\val_c[127:0] + 2369/3417: $7\val_b[127:0] + 2370/3417: $7\val_a[127:0] + 2371/3417: $7\taken_proposal[7:0] + 2372/3417: $7\inv_present[7:0] + 2373/3417: $7\pres_c[7:0] + 2374/3417: $7\pres_b[7:0] + 2375/3417: $7\pres_a[7:0] + 2376/3417: $7\profile[7:0] + 2377/3417: $14\deferred_local[31:0] + 2378/3417: $14\deferred_target[31:0] + 2379/3417: $9\next_fp_value[31:0] + 2380/3417: $9\next_pc_value[31:0] + 2381/3417: $7\proposed_fp[31:0] + 2382/3417: $7\proposed_pc[31:0] + 2383/3417: $7\base_index[31:0] + 2384/3417: $7\addr_c[31:0] + 2385/3417: $7\addr_b[31:0] + 2386/3417: $7\addr_a[31:0] + 2387/3417: $7\off_c[31:0] + 2388/3417: $7\off_b[31:0] + 2389/3417: $7\off_a[31:0] + 2390/3417: $7\fp[31:0] + 2391/3417: $7\pc[31:0] + 2392/3417: $7\txn_id[31:0] + 2393/3417: $27\result_length[31:0] + 2394/3417: $14\n_deferred[31:0] + 2395/3417: $16\n_writes[31:0] + 2396/3417: $26\result_length[31:0] + 2397/3417: $26\result_bytes[215:152] [63:32] + 2398/3417: $26\result_bytes[215:152] [31:0] + 2399/3417: $25\result_bytes[279:104] [111:80] + 2400/3417: $25\result_bytes[279:104] [47:40] + 2401/3417: $25\result_bytes[279:104] [15:8] + 2402/3417: $25\result_bytes[279:104] [143:112] + 2403/3417: $25\result_length[31:0] + 2404/3417: $25\result_bytes[279:104] [79:72] + 2405/3417: $25\result_bytes[279:104] [71:48] + 2406/3417: $25\result_bytes[279:104] [39:16] + 2407/3417: $25\result_bytes[279:104] [175:144] + 2408/3417: $25\result_bytes[279:104] [7:0] + 2409/3417: $23\result_bytes[375:104] [175:168] + 2410/3417: $24\result_bytes[375:312] [63:32] + 2411/3417: $24\result_bytes[375:312] [31:0] + 2412/3417: $23\result_bytes[375:104] [207:176] + 2413/3417: $23\result_length[31:0] + 2414/3417: $24\result_length[31:0] + 2415/3417: $23\result_bytes[375:104] [167:160] + 2416/3417: $23\result_bytes[375:104] [159:32] + 2417/3417: $23\result_bytes[375:104] [31:0] + 2418/3417: $23\result_bytes[375:104] [271:208] + 2419/3417: $22\result_bytes[543:0] [375:104] + 2420/3417: $22\result_bytes[543:0] [103:96] + 2421/3417: $22\result_bytes[543:0] [95:64] + 2422/3417: $22\result_bytes[543:0] [63:32] + 2423/3417: $22\result_bytes[543:0] [31:0] + 2424/3417: $22\result_bytes[543:0] [543:376] + 2425/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1576 [31:0] + 2426/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1576 [39:32] + 2427/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1575 + 2428/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1576 [543:40] + 2429/3417: $8\next_fp_value[31:0] + 2430/3417: $8\next_pc_value[31:0] + 2431/3417: $22\result_length[31:0] + 2432/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1571 [543:40] + 2433/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1571 [31:0] + 2434/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1571 [39:32] + 2435/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1570 + 2436/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1573 + 2437/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1572 + 2438/3417: $21\result_bytes[543:0] + 2439/3417: $7\next_fp_value[31:0] + 2440/3417: $7\next_pc_value[31:0] + 2441/3417: $21\result_length[31:0] + 2442/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1490 + 2443/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1489 + 2444/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1488 + 2445/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1487 + 2446/3417: $20\result_bytes[543:0] + 2447/3417: $6\next_fp_value[31:0] + 2448/3417: $6\next_pc_value[31:0] + 2449/3417: $20\result_length[31:0] + 2450/3417: $6\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1569 + 2451/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1568 + 2452/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1567 + 2453/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1566 + 2454/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1565 + 2455/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1564 + 2456/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1563 + 2457/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1562 + 2458/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1561 + 2459/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1560 + 2460/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1559 + 2461/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1558 + 2462/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1557 + 2463/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1556 + 2464/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1555 + 2465/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1554 + 2466/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1553 + 2467/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1552 + 2468/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1551 + 2469/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1550 + 2470/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1549 + 2471/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1548 + 2472/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1547 + 2473/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1546 + 2474/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1545 + 2475/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1544 + 2476/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1543 + 2477/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1542 + 2478/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1541 + 2479/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1540 + 2480/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1539 + 2481/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1538 + 2482/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1537 + 2483/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1536 + 2484/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1535 + 2485/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1534 + 2486/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1533 + 2487/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1532 + 2488/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1531 + 2489/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1530 + 2490/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1529 + 2491/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1528 + 2492/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1527 + 2493/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1526 + 2494/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1525 + 2495/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1524 + 2496/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1523 + 2497/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1522 + 2498/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1521 + 2499/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1520 + 2500/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1519 + 2501/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1518 + 2502/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1517 + 2503/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1516 + 2504/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1515 + 2505/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1514 + 2506/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1513 + 2507/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1512 + 2508/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1511 + 2509/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1510 + 2510/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1509 + 2511/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1508 + 2512/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1507 + 2513/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1506 + 2514/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1505 + 2515/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1504 + 2516/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1503 + 2517/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1502 + 2518/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1501 + 2519/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1500 + 2520/3417: $6\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1499 + 2521/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1498 + 2522/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1497 + 2523/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1496 + 2524/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1495 + 2525/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1494 + 2526/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1493 + 2527/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1492 + 2528/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1491 + 2529/3417: $6\decision_deferred[0:0] + 2530/3417: $6\decision_ok[0:0] + 2531/3417: $6\decision_detail[7:0] + 2532/3417: $6\decision_fault[7:0] + 2533/3417: $15\write_value[127:0] + 2534/3417: $15\write_address[31:0] + 2535/3417: $6\retired_bytes[543:0] + 2536/3417: $6\solved_b[127:0] + 2537/3417: $6\solved_a[127:0] + 2538/3417: $6\result_value[127:0] + 2539/3417: $6\inv_value[127:0] + 2540/3417: $6\val_c[127:0] + 2541/3417: $6\val_b[127:0] + 2542/3417: $6\val_a[127:0] + 2543/3417: $6\taken_proposal[7:0] + 2544/3417: $6\inv_present[7:0] + 2545/3417: $6\pres_c[7:0] + 2546/3417: $6\pres_b[7:0] + 2547/3417: $6\pres_a[7:0] + 2548/3417: $6\profile[7:0] + 2549/3417: $13\deferred_local[31:0] + 2550/3417: $13\deferred_target[31:0] + 2551/3417: $6\proposed_fp[31:0] + 2552/3417: $6\proposed_pc[31:0] + 2553/3417: $6\base_index[31:0] + 2554/3417: $6\addr_c[31:0] + 2555/3417: $6\addr_b[31:0] + 2556/3417: $6\addr_a[31:0] + 2557/3417: $6\off_c[31:0] + 2558/3417: $6\off_b[31:0] + 2559/3417: $6\off_a[31:0] + 2560/3417: $6\fp[31:0] + 2561/3417: $6\pc[31:0] + 2562/3417: $6\txn_id[31:0] + 2563/3417: $13\n_deferred[31:0] + 2564/3417: $15\n_writes[31:0] + 2565/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1484 [543:40] + 2566/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1484 [31:0] + 2567/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1484 [39:32] + 2568/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1483 + 2569/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1479 [543:40] + 2570/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1479 [31:0] + 2571/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1479 [39:32] + 2572/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1478 + 2573/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1481 + 2574/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1480 + 2575/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1394 + 2576/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1393 + 2577/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1392 + 2578/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1391 + 2579/3417: $5\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1477 + 2580/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1476 + 2581/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1475 + 2582/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1474 + 2583/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1473 + 2584/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1472 + 2585/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1471 + 2586/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1470 + 2587/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1469 + 2588/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1468 + 2589/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1467 + 2590/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1466 + 2591/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1465 + 2592/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1464 + 2593/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1463 + 2594/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1462 + 2595/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1461 + 2596/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1460 + 2597/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1459 + 2598/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1458 + 2599/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1457 + 2600/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1456 + 2601/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1455 + 2602/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1454 + 2603/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1453 + 2604/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1452 + 2605/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1451 + 2606/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1450 + 2607/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1449 + 2608/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1448 + 2609/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1447 + 2610/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1446 + 2611/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1445 + 2612/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1444 + 2613/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1443 + 2614/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1442 + 2615/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1441 + 2616/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1440 + 2617/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1439 + 2618/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1438 + 2619/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1437 + 2620/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1436 + 2621/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1435 + 2622/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1434 + 2623/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1433 + 2624/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1432 + 2625/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1431 + 2626/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1430 + 2627/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1429 + 2628/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1428 + 2629/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1427 + 2630/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1426 + 2631/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1425 + 2632/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1424 + 2633/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1423 + 2634/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1422 + 2635/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1421 + 2636/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1420 + 2637/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1419 + 2638/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1418 + 2639/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1417 + 2640/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1416 + 2641/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1415 + 2642/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1414 + 2643/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1413 + 2644/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1412 + 2645/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1411 + 2646/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1410 + 2647/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1409 + 2648/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1408 + 2649/3417: $5\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1407 + 2650/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1406 + 2651/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1405 + 2652/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1404 + 2653/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1403 + 2654/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1402 + 2655/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1401 + 2656/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1400 + 2657/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1399 + 2658/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1398 + 2659/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1397 + 2660/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1396 + 2661/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1395 + 2662/3417: $5\decision_deferred[0:0] + 2663/3417: $5\decision_ok[0:0] + 2664/3417: $5\decision_detail[7:0] + 2665/3417: $5\decision_fault[7:0] + 2666/3417: $14\write_value[127:0] + 2667/3417: $14\write_address[31:0] + 2668/3417: $5\retired_bytes[543:0] + 2669/3417: $19\result_bytes[543:0] + 2670/3417: $5\solved_b[127:0] + 2671/3417: $5\solved_a[127:0] + 2672/3417: $5\result_value[127:0] + 2673/3417: $5\inv_value[127:0] + 2674/3417: $5\val_c[127:0] + 2675/3417: $5\val_b[127:0] + 2676/3417: $5\val_a[127:0] + 2677/3417: $5\taken_proposal[7:0] + 2678/3417: $5\inv_present[7:0] + 2679/3417: $5\pres_c[7:0] + 2680/3417: $5\pres_b[7:0] + 2681/3417: $5\pres_a[7:0] + 2682/3417: $5\profile[7:0] + 2683/3417: $12\deferred_local[31:0] + 2684/3417: $12\deferred_target[31:0] + 2685/3417: $5\next_fp_value[31:0] + 2686/3417: $5\next_pc_value[31:0] + 2687/3417: $5\proposed_fp[31:0] + 2688/3417: $5\proposed_pc[31:0] + 2689/3417: $5\base_index[31:0] + 2690/3417: $5\addr_c[31:0] + 2691/3417: $5\addr_b[31:0] + 2692/3417: $5\addr_a[31:0] + 2693/3417: $5\off_c[31:0] + 2694/3417: $5\off_b[31:0] + 2695/3417: $5\off_a[31:0] + 2696/3417: $5\fp[31:0] + 2697/3417: $5\pc[31:0] + 2698/3417: $5\txn_id[31:0] + 2699/3417: $19\result_length[31:0] + 2700/3417: $12\n_deferred[31:0] + 2701/3417: $14\n_writes[31:0] + 2702/3417: $18\result_length[31:0] + 2703/3417: $18\result_bytes[215:152] [63:32] + 2704/3417: $18\result_bytes[215:152] [31:0] + 2705/3417: $17\result_bytes[279:104] [111:80] + 2706/3417: $17\result_bytes[279:104] [47:40] + 2707/3417: $17\result_bytes[279:104] [15:8] + 2708/3417: $17\result_bytes[279:104] [143:112] + 2709/3417: $17\result_length[31:0] + 2710/3417: $17\result_bytes[279:104] [79:72] + 2711/3417: $17\result_bytes[279:104] [71:48] + 2712/3417: $17\result_bytes[279:104] [39:16] + 2713/3417: $17\result_bytes[279:104] [175:144] + 2714/3417: $17\result_bytes[279:104] [7:0] + 2715/3417: $15\result_bytes[375:104] [175:168] + 2716/3417: $16\result_bytes[375:312] [63:32] + 2717/3417: $16\result_bytes[375:312] [31:0] + 2718/3417: $15\result_bytes[375:104] [207:176] + 2719/3417: $15\result_length[31:0] + 2720/3417: $16\result_length[31:0] + 2721/3417: $15\result_bytes[375:104] [167:160] + 2722/3417: $15\result_bytes[375:104] [159:32] + 2723/3417: $15\result_bytes[375:104] [31:0] + 2724/3417: $15\result_bytes[375:104] [271:208] + 2725/3417: $13\write_value[127:0] + 2726/3417: $13\write_address[31:0] + 2727/3417: $13\n_writes[31:0] + 2728/3417: $14\result_bytes[543:0] [375:104] + 2729/3417: $14\result_bytes[543:0] [103:96] + 2730/3417: $14\result_bytes[543:0] [95:64] + 2731/3417: $14\result_bytes[543:0] [63:32] + 2732/3417: $14\result_bytes[543:0] [31:0] + 2733/3417: $14\result_bytes[543:0] [543:376] + 2734/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1385 [31:0] + 2735/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1385 [39:32] + 2736/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1384 + 2737/3417: $12\write_value[127:0] + 2738/3417: $12\write_address[31:0] + 2739/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1385 [543:40] + 2740/3417: $14\result_length[31:0] + 2741/3417: $12\n_writes[31:0] + 2742/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1379 [543:40] + 2743/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1379 [31:0] + 2744/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1379 [39:32] + 2745/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$1378 + 2746/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1381 + 2747/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1380 + 2748/3417: $11\write_value[127:0] + 2749/3417: $11\write_address[31:0] + 2750/3417: $13\result_bytes[543:0] + 2751/3417: $13\result_length[31:0] + 2752/3417: $11\n_writes[31:0] + 2753/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1290 + 2754/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1289 + 2755/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1288 + 2756/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$1287 + 2757/3417: $10\write_value[127:0] + 2758/3417: $10\write_address[31:0] + 2759/3417: $12\result_bytes[543:0] + 2760/3417: $12\result_length[31:0] + 2761/3417: $10\n_writes[31:0] + 2762/3417: $4\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1377 + 2763/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1376 + 2764/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1375 + 2765/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1374 + 2766/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1373 + 2767/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1372 + 2768/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1371 + 2769/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1370 + 2770/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1369 + 2771/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1368 + 2772/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1367 + 2773/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1366 + 2774/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1365 + 2775/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1364 + 2776/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1363 + 2777/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1362 + 2778/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1361 + 2779/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1360 + 2780/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1359 + 2781/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1358 + 2782/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1357 + 2783/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1356 + 2784/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1355 + 2785/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1354 + 2786/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1353 + 2787/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1352 + 2788/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1351 + 2789/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1350 + 2790/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1349 + 2791/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1348 + 2792/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1347 + 2793/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1346 + 2794/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1345 + 2795/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1344 + 2796/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1343 + 2797/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1342 + 2798/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1341 + 2799/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1340 + 2800/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1339 + 2801/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1338 + 2802/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1337 + 2803/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1336 + 2804/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1335 + 2805/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1334 + 2806/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1333 + 2807/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1332 + 2808/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1331 + 2809/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1330 + 2810/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1329 + 2811/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1328 + 2812/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1327 + 2813/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1326 + 2814/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1325 + 2815/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1324 + 2816/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1323 + 2817/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1322 + 2818/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1321 + 2819/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1320 + 2820/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1319 + 2821/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1318 + 2822/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1317 + 2823/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1316 + 2824/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1315 + 2825/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1314 + 2826/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1313 + 2827/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1312 + 2828/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1311 + 2829/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1310 + 2830/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1309 + 2831/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1308 + 2832/3417: $4\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1307 + 2833/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1306 + 2834/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1305 + 2835/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1304 + 2836/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1303 + 2837/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1302 + 2838/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1301 + 2839/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1300 + 2840/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1299 + 2841/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1298 + 2842/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1297 + 2843/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1296 + 2844/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1295 + 2845/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1294 + 2846/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1293 + 2847/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1292 + 2848/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1291 + 2849/3417: $4\decision_deferred[0:0] + 2850/3417: $4\decision_ok[0:0] + 2851/3417: $4\decision_detail[7:0] + 2852/3417: $4\decision_fault[7:0] + 2853/3417: $4\retired_bytes[543:0] + 2854/3417: $4\solved_b[127:0] + 2855/3417: $4\solved_a[127:0] + 2856/3417: $4\result_value[127:0] + 2857/3417: $4\inv_value[127:0] + 2858/3417: $4\val_c[127:0] + 2859/3417: $4\val_b[127:0] + 2860/3417: $4\val_a[127:0] + 2861/3417: $4\taken_proposal[7:0] + 2862/3417: $4\inv_present[7:0] + 2863/3417: $4\pres_c[7:0] + 2864/3417: $4\pres_b[7:0] + 2865/3417: $4\pres_a[7:0] + 2866/3417: $4\profile[7:0] + 2867/3417: $11\deferred_local[31:0] + 2868/3417: $11\deferred_target[31:0] + 2869/3417: $4\next_fp_value[31:0] + 2870/3417: $4\next_pc_value[31:0] + 2871/3417: $4\proposed_fp[31:0] + 2872/3417: $4\proposed_pc[31:0] + 2873/3417: $4\base_index[31:0] + 2874/3417: $4\addr_c[31:0] + 2875/3417: $4\addr_b[31:0] + 2876/3417: $4\addr_a[31:0] + 2877/3417: $4\off_c[31:0] + 2878/3417: $4\off_b[31:0] + 2879/3417: $4\off_a[31:0] + 2880/3417: $4\fp[31:0] + 2881/3417: $4\pc[31:0] + 2882/3417: $4\txn_id[31:0] + 2883/3417: $11\n_deferred[31:0] + 2884/3417: $11\result_length[31:0] + 2885/3417: $11\result_bytes[215:152] [63:32] + 2886/3417: $11\result_bytes[215:152] [31:0] + 2887/3417: $10\result_bytes[279:104] [111:80] + 2888/3417: $10\result_bytes[279:104] [47:40] + 2889/3417: $10\result_bytes[279:104] [15:8] + 2890/3417: $10\result_bytes[279:104] [143:112] + 2891/3417: $10\result_length[31:0] + 2892/3417: $10\result_bytes[279:104] [79:72] + 2893/3417: $10\result_bytes[279:104] [71:48] + 2894/3417: $10\result_bytes[279:104] [39:16] + 2895/3417: $10\result_bytes[279:104] [175:144] + 2896/3417: $10\result_bytes[279:104] [7:0] + 2897/3417: $8\result_bytes[375:104] [175:168] + 2898/3417: $9\result_bytes[375:312] [63:32] + 2899/3417: $9\result_bytes[375:312] [31:0] + 2900/3417: $8\result_bytes[375:104] [207:176] + 2901/3417: $8\result_length[31:0] + 2902/3417: $9\result_length[31:0] + 2903/3417: $8\result_bytes[375:104] [167:160] + 2904/3417: $8\result_bytes[375:104] [159:32] + 2905/3417: $8\result_bytes[375:104] [31:0] + 2906/3417: $8\result_bytes[375:104] [271:208] + 2907/3417: $10\deferred_local[31:0] + 2908/3417: $10\deferred_target[31:0] + 2909/3417: $10\n_deferred[31:0] + 2910/3417: $9\write_value[127:0] + 2911/3417: $9\write_address[31:0] + 2912/3417: $9\n_writes[31:0] + 2913/3417: $9\deferred_local[31:0] + 2914/3417: $9\deferred_target[31:0] + 2915/3417: $9\n_deferred[31:0] + 2916/3417: $8\write_value[127:0] + 2917/3417: $8\write_address[31:0] + 2918/3417: $8\n_writes[31:0] + 2919/3417: $8\deferred_local[31:0] + 2920/3417: $8\deferred_target[31:0] + 2921/3417: $8\n_deferred[31:0] + 2922/3417: $7\result_bytes[543:0] [375:104] + 2923/3417: $7\result_bytes[543:0] [103:96] + 2924/3417: $7\result_bytes[543:0] [95:64] + 2925/3417: $7\result_bytes[543:0] [63:32] + 2926/3417: $7\result_bytes[543:0] [31:0] + 2927/3417: $7\result_bytes[543:0] [543:376] + 2928/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1272 [31:0] + 2929/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1272 [39:32] + 2930/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1271 + 2931/3417: $7\write_value[127:0] + 2932/3417: $7\write_address[31:0] + 2933/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1272 [543:40] + 2934/3417: $7\deferred_local[31:0] + 2935/3417: $7\deferred_target[31:0] + 2936/3417: $7\result_length[31:0] + 2937/3417: $7\n_deferred[31:0] + 2938/3417: $7\n_writes[31:0] + 2939/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1265 [543:40] + 2940/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1265 [31:0] + 2941/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1265 [39:32] + 2942/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1264 + 2943/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1267 + 2944/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1266 + 2945/3417: $6\write_value[127:0] + 2946/3417: $6\write_address[31:0] + 2947/3417: $6\result_bytes[543:0] + 2948/3417: $6\deferred_local[31:0] + 2949/3417: $6\deferred_target[31:0] + 2950/3417: $6\result_length[31:0] + 2951/3417: $6\n_deferred[31:0] + 2952/3417: $6\n_writes[31:0] + 2953/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1260 + 2954/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1259 + 2955/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1258 + 2956/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1257 + 2957/3417: $5\write_value[127:0] + 2958/3417: $5\write_address[31:0] + 2959/3417: $5\result_bytes[543:0] + 2960/3417: $5\deferred_local[31:0] + 2961/3417: $5\deferred_target[31:0] + 2962/3417: $5\result_length[31:0] + 2963/3417: $5\n_deferred[31:0] + 2964/3417: $5\n_writes[31:0] + 2965/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1251 [543:40] + 2966/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1251 [31:0] + 2967/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1251 [39:32] + 2968/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn[31:0]$1250 + 2969/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1255 + 2970/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1254 + 2971/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1253 + 2972/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1252 + 2973/3417: $4\write_value[127:0] + 2974/3417: $4\write_address[31:0] + 2975/3417: $4\result_bytes[543:0] + 2976/3417: $4\deferred_local[31:0] + 2977/3417: $4\deferred_target[31:0] + 2978/3417: $4\result_length[31:0] + 2979/3417: $4\n_deferred[31:0] + 2980/3417: $4\n_writes[31:0] + 2981/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1156 + 2982/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1155 + 2983/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1154 + 2984/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1153 + 2985/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1152 + 2986/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn[31:0]$1151 + 2987/3417: $3\write_value[127:0] + 2988/3417: $3\write_address[31:0] + 2989/3417: $3\result_bytes[543:0] + 2990/3417: $3\deferred_local[31:0] + 2991/3417: $3\deferred_target[31:0] + 2992/3417: $3\result_length[31:0] + 2993/3417: $3\n_deferred[31:0] + 2994/3417: $3\n_writes[31:0] + 2995/3417: $3\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1247 + 2996/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1246 + 2997/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1245 + 2998/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1244 + 2999/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1243 + 3000/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1242 + 3001/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1241 + 3002/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1240 + 3003/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1239 + 3004/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1238 + 3005/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1237 + 3006/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1236 + 3007/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1235 + 3008/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1234 + 3009/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1233 + 3010/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1232 + 3011/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1231 + 3012/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1230 + 3013/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1229 + 3014/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1228 + 3015/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1227 + 3016/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1226 + 3017/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1225 + 3018/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1224 + 3019/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1223 + 3020/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1222 + 3021/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1221 + 3022/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1220 + 3023/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1219 + 3024/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1218 + 3025/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1217 + 3026/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1216 + 3027/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1215 + 3028/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1214 + 3029/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1213 + 3030/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1212 + 3031/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1211 + 3032/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1210 + 3033/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1209 + 3034/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1208 + 3035/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1207 + 3036/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1206 + 3037/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1205 + 3038/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1204 + 3039/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1203 + 3040/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1202 + 3041/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1201 + 3042/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1200 + 3043/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1199 + 3044/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1198 + 3045/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1197 + 3046/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1196 + 3047/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1195 + 3048/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1194 + 3049/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1193 + 3050/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1192 + 3051/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1191 + 3052/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1190 + 3053/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1189 + 3054/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1188 + 3055/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1187 + 3056/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1186 + 3057/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1185 + 3058/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1184 + 3059/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1183 + 3060/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1182 + 3061/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1181 + 3062/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1180 + 3063/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1179 + 3064/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1178 + 3065/3417: $3\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1177 + 3066/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1176 + 3067/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1175 + 3068/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1174 + 3069/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1173 + 3070/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1172 + 3071/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1171 + 3072/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1170 + 3073/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1169 + 3074/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1168 + 3075/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1167 + 3076/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1166 + 3077/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1165 + 3078/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1164 + 3079/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1163 + 3080/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1162 + 3081/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1161 + 3082/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1160 + 3083/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1159 + 3084/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1158 + 3085/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$1157 + 3086/3417: $3\decision_deferred[0:0] + 3087/3417: $3\decision_ok[0:0] + 3088/3417: $3\decision_detail[7:0] + 3089/3417: $3\decision_fault[7:0] + 3090/3417: $3\retired_bytes[543:0] + 3091/3417: $3\solved_b[127:0] + 3092/3417: $3\solved_a[127:0] + 3093/3417: $3\result_value[127:0] + 3094/3417: $3\inv_value[127:0] + 3095/3417: $3\val_c[127:0] + 3096/3417: $3\val_b[127:0] + 3097/3417: $3\val_a[127:0] + 3098/3417: $3\taken_proposal[7:0] + 3099/3417: $3\inv_present[7:0] + 3100/3417: $3\pres_c[7:0] + 3101/3417: $3\pres_b[7:0] + 3102/3417: $3\pres_a[7:0] + 3103/3417: $3\profile[7:0] + 3104/3417: $3\next_fp_value[31:0] + 3105/3417: $3\next_pc_value[31:0] + 3106/3417: $3\proposed_fp[31:0] + 3107/3417: $3\proposed_pc[31:0] + 3108/3417: $3\base_index[31:0] + 3109/3417: $3\addr_c[31:0] + 3110/3417: $3\addr_b[31:0] + 3111/3417: $3\addr_a[31:0] + 3112/3417: $3\off_c[31:0] + 3113/3417: $3\off_b[31:0] + 3114/3417: $3\off_a[31:0] + 3115/3417: $3\fp[31:0] + 3116/3417: $3\pc[31:0] + 3117/3417: $3\txn_id[31:0] + 3118/3417: $2\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1147 + 3119/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1146 + 3120/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1145 + 3121/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1144 + 3122/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1143 + 3123/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1142 + 3124/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1141 + 3125/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1140 + 3126/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1139 + 3127/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1138 + 3128/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1137 + 3129/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1136 + 3130/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1135 + 3131/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1134 + 3132/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1133 + 3133/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1132 + 3134/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1131 + 3135/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1130 + 3136/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1129 + 3137/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1128 + 3138/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1127 + 3139/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1126 + 3140/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1125 + 3141/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1124 + 3142/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1123 + 3143/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1122 + 3144/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1121 + 3145/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1120 + 3146/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1119 + 3147/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1118 + 3148/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1117 + 3149/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1116 + 3150/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1115 + 3151/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1114 + 3152/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1113 + 3153/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1112 + 3154/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1111 + 3155/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1110 + 3156/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1109 + 3157/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1108 + 3158/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1107 + 3159/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1106 + 3160/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1105 + 3161/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1104 + 3162/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1103 + 3163/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1102 + 3164/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1101 + 3165/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1100 + 3166/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1099 + 3167/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1098 + 3168/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1097 + 3169/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1096 + 3170/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1095 + 3171/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1094 + 3172/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1093 + 3173/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1092 + 3174/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1091 + 3175/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1090 + 3176/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1089 + 3177/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1088 + 3178/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1087 + 3179/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1086 + 3180/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1085 + 3181/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1084 + 3182/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1083 + 3183/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1082 + 3184/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1081 + 3185/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1080 + 3186/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1079 + 3187/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1078 + 3188/3417: $2\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1077 + 3189/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1076 + 3190/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1075 + 3191/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1074 + 3192/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1073 + 3193/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1072 + 3194/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1071 + 3195/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1070 + 3196/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1069 + 3197/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1068 + 3198/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1067 + 3199/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1066 + 3200/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1065 + 3201/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1064 + 3202/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1063 + 3203/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1062 + 3204/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1061 + 3205/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1060 + 3206/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1059 + 3207/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1058 + 3208/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$1057 + 3209/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1056 + 3210/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1055 + 3211/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1054 + 3212/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1053 + 3213/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1052 + 3214/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn[31:0]$1051 + 3215/3417: $2\decision_deferred[0:0] + 3216/3417: $2\decision_ok[0:0] + 3217/3417: $2\decision_detail[7:0] + 3218/3417: $2\decision_fault[7:0] + 3219/3417: $2\write_value[127:0] + 3220/3417: $2\write_address[31:0] + 3221/3417: $2\retired_bytes[543:0] + 3222/3417: $2\result_bytes[543:0] + 3223/3417: $2\solved_b[127:0] + 3224/3417: $2\solved_a[127:0] + 3225/3417: $2\result_value[127:0] + 3226/3417: $2\inv_value[127:0] + 3227/3417: $2\val_c[127:0] + 3228/3417: $2\val_b[127:0] + 3229/3417: $2\val_a[127:0] + 3230/3417: $2\taken_proposal[7:0] + 3231/3417: $2\inv_present[7:0] + 3232/3417: $2\pres_c[7:0] + 3233/3417: $2\pres_b[7:0] + 3234/3417: $2\pres_a[7:0] + 3235/3417: $2\profile[7:0] + 3236/3417: $2\deferred_local[31:0] + 3237/3417: $2\deferred_target[31:0] + 3238/3417: $2\next_fp_value[31:0] + 3239/3417: $2\next_pc_value[31:0] + 3240/3417: $2\proposed_fp[31:0] + 3241/3417: $2\proposed_pc[31:0] + 3242/3417: $2\base_index[31:0] + 3243/3417: $2\addr_c[31:0] + 3244/3417: $2\addr_b[31:0] + 3245/3417: $2\addr_a[31:0] + 3246/3417: $2\off_c[31:0] + 3247/3417: $2\off_b[31:0] + 3248/3417: $2\off_a[31:0] + 3249/3417: $2\fp[31:0] + 3250/3417: $2\pc[31:0] + 3251/3417: $2\txn_id[31:0] + 3252/3417: $2\result_length[31:0] + 3253/3417: $2\n_deferred[31:0] + 3254/3417: $2\n_writes[31:0] + 3255/3417: $0\done_pulse[0:0] + 3256/3417: $0\encoder_start[0:0] + 3257/3417: $0\alu_start[0:0] + 3258/3417: $0\tx_start[0:0] + 3259/3417: $1\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1050 + 3260/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1049 + 3261/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1048 + 3262/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1047 + 3263/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1046 + 3264/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1045 + 3265/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1044 + 3266/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1043 + 3267/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1042 + 3268/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1041 + 3269/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1040 + 3270/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1039 + 3271/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1038 + 3272/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1037 + 3273/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1036 + 3274/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1035 + 3275/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1034 + 3276/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1033 + 3277/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1032 + 3278/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1031 + 3279/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1030 + 3280/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1029 + 3281/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1028 + 3282/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1027 + 3283/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1026 + 3284/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1025 + 3285/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1024 + 3286/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1023 + 3287/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1022 + 3288/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1021 + 3289/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1020 + 3290/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1019 + 3291/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1018 + 3292/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1017 + 3293/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1016 + 3294/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1015 + 3295/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1014 + 3296/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1013 + 3297/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1012 + 3298/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1011 + 3299/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1010 + 3300/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1009 + 3301/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1008 + 3302/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1007 + 3303/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1006 + 3304/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1005 + 3305/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1004 + 3306/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1003 + 3307/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1002 + 3308/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1001 + 3309/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1000 + 3310/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$999 + 3311/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$998 + 3312/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$997 + 3313/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$996 + 3314/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$995 + 3315/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$994 + 3316/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$993 + 3317/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$992 + 3318/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$991 + 3319/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$990 + 3320/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$989 + 3321/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$988 + 3322/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$987 + 3323/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$986 + 3324/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$985 + 3325/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$984 + 3326/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$983 + 3327/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$982 + 3328/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$981 + 3329/3417: $1\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$980 + 3330/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$979 + 3331/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$978 + 3332/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$977 + 3333/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$976 + 3334/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$975 + 3335/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$974 + 3336/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$973 + 3337/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$972 + 3338/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$971 + 3339/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$970 + 3340/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$969 + 3341/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$968 + 3342/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$967 + 3343/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$966 + 3344/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$965 + 3345/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$964 + 3346/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$963 + 3347/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$962 + 3348/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$961 + 3349/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$960 + 3350/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$959 + 3351/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$958 + 3352/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$957 + 3353/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$956 + 3354/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$955 + 3355/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn[31:0]$954 + 3356/3417: $1\decision_deferred[0:0] + 3357/3417: $1\decision_ok[0:0] + 3358/3417: $1\decision_detail[7:0] + 3359/3417: $1\decision_fault[7:0] + 3360/3417: $1\write_value[127:0] + 3361/3417: $1\write_address[31:0] + 3362/3417: $1\retired_bytes[543:0] + 3363/3417: $1\result_bytes[543:0] + 3364/3417: $1\solved_b[127:0] + 3365/3417: $1\solved_a[127:0] + 3366/3417: $1\result_value[127:0] + 3367/3417: $1\inv_value[127:0] + 3368/3417: $1\val_c[127:0] + 3369/3417: $1\val_b[127:0] + 3370/3417: $1\val_a[127:0] + 3371/3417: $1\taken_proposal[7:0] + 3372/3417: $1\inv_present[7:0] + 3373/3417: $1\pres_c[7:0] + 3374/3417: $1\pres_b[7:0] + 3375/3417: $1\pres_a[7:0] + 3376/3417: $1\profile[7:0] + 3377/3417: $1\deferred_local[31:0] + 3378/3417: $1\deferred_target[31:0] + 3379/3417: $1\next_fp_value[31:0] + 3380/3417: $1\next_pc_value[31:0] + 3381/3417: $1\proposed_fp[31:0] + 3382/3417: $1\proposed_pc[31:0] + 3383/3417: $1\base_index[31:0] + 3384/3417: $1\addr_c[31:0] + 3385/3417: $1\addr_b[31:0] + 3386/3417: $1\addr_a[31:0] + 3387/3417: $1\off_c[31:0] + 3388/3417: $1\off_b[31:0] + 3389/3417: $1\off_a[31:0] + 3390/3417: $1\fp[31:0] + 3391/3417: $1\pc[31:0] + 3392/3417: $1\txn_id[31:0] + 3393/3417: $1\result_length[31:0] + 3394/3417: $1\n_deferred[31:0] + 3395/3417: $1\n_writes[31:0] + 3396/3417: $0\last_fault[7:0] + 3397/3417: $0\last_status[7:0] + 3398/3417: $0\active_profile[7:0] + 3399/3417: $0\retire_seq[31:0] + 3400/3417: $0\committed_fp[31:0] + 3401/3417: $0\committed_pc[31:0] + 3402/3417: $0\state_valid[0:0] + 3403/3417: $0\staged_result_crc[31:0] + 3404/3417: $0\staged_next_fp[31:0] + 3405/3417: $0\staged_next_pc[31:0] + 3406/3417: $0\staged_txn_id[31:0] + 3407/3417: $0\result_pending[0:0] + 3408/3417: $0\encoder_index[15:0] + 3409/3417: $0\alu_operand_b[127:0] + 3410/3417: $0\alu_operand_a[127:0] + 3411/3417: $0\alu_operation[7:0] + 3412/3417: $0\compute_state[3:0] + 3413/3417: $0\capture_result_crc[0:0] + 3414/3417: $0\tx_payload[543:0] + 3415/3417: $0\tx_length[15:0] + 3416/3417: $0\tx_status[7:0] + 3417/3417: $0\fault[0:0] +Creating decoders for process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + 1/19: $3\next_accumulator[127:0] + 2/19: $3\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.$result[127:0]$767 + 3/19: $3\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.value[127:0]$768 + 4/19: $2\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.value[127:0]$765 + 5/19: $2\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.$result[127:0]$764 + 6/19: $2\next_accumulator[127:0] + 7/19: $0\multiply_start[0:0] + 8/19: $0\done_pulse[0:0] + 9/19: $1\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.value[127:0]$761 + 10/19: $1\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.$result[127:0]$760 + 11/19: $1\next_accumulator[127:0] + 12/19: $0\saved_index[15:0] + 13/19: $0\bit_index[4:0] + 14/19: $0\result[127:0] + 15/19: $0\operand_b[127:0] + 16/19: $0\operand_a[127:0] + 17/19: $0\fault[0:0] + 18/19: $0\accumulator[127:0] + 19/19: $0\busy[0:0] +Creating decoders for process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + 1/38: $6$lookahead\result$670[127:0]$738 + 2/38: $4$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638[127:0]$736 + 3/38: $4$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637[127:0]$735 + 4/38: $4$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639[31:0]$737 + 5/38: $5$lookahead\result$670[127:0]$712 + 6/38: $4$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635[127:0]$710 + 7/38: $4$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634[127:0]$709 + 8/38: $4$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636[31:0]$711 + 9/38: $4$lookahead\result$670[127:0]$703 + 10/38: $3$lookahead\result$670[127:0]$702 + 11/38: $3$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639[31:0]$701 + 12/38: $3$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638[127:0]$700 + 13/38: $3$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637[127:0]$699 + 14/38: $3$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636[31:0]$698 + 15/38: $3$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635[127:0]$697 + 16/38: $3$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634[127:0]$696 + 17/38: $2$lookahead\result$670[127:0]$693 + 18/38: $2$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639[31:0]$692 + 19/38: $2$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638[127:0]$691 + 20/38: $2$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637[127:0]$690 + 21/38: $2$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636[31:0]$689 + 22/38: $2$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635[127:0]$688 + 23/38: $2$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634[127:0]$687 + 24/38: $0\done_pulse[0:0] + 25/38: $1$lookahead\result$670[127:0]$686 + 26/38: $1$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639[31:0]$685 + 27/38: $1$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638[127:0]$684 + 28/38: $1$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637[127:0]$683 + 29/38: $1$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636[31:0]$682 + 30/38: $1$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635[127:0]$681 + 31/38: $1$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634[127:0]$680 + 32/38: $0\result_index[4:0] + 33/38: $0\payload_index[5:0] + 34/38: $0\saved_b[127:0] + 35/38: $0\saved_a[127:0] + 36/38: $0\saved_operation[7:0] + 37/38: $0\fault[0:0] + 38/38: $0\state[2:0] +Creating decoders for process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. + 1/9: $6\core_rx_data[7:0] + 2/9: $5\core_rx_data[7:0] + 3/9: $4\core_rx_data[7:0] + 4/9: $3\core_rx_data[7:0] + 5/9: $3\core_rx_valid[0:0] + 6/9: $2\core_rx_data[7:0] + 7/9: $2\core_rx_valid[0:0] + 8/9: $1\core_rx_data[7:0] + 9/9: $1\core_rx_valid[0:0] +Creating decoders for process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + 1/5: $0\scratch_byte[7:0] [7:1] + 2/5: $0\scratch_byte[7:0] [0] + 3/5: $0\byte_index[3:0] + 4/5: $0\fault[0:0] + 5/5: $0\state[3:0] +Creating decoders for process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. + 1/13: $2\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.$result[7:0]$585 + 2/13: $2\rx_ready[0:0] + 3/13: $2\tx_data[7:0] + 4/13: $2\tx_valid[0:0] + 5/13: $1\rx_ready[0:0] + 6/13: $1\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.index[3:0]$580 + 7/13: $1\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.$result[7:0]$579 + 8/13: $1\mul_result_shift[0:0] + 9/13: $1\mul_bit_value[0:0] + 10/13: $1\mul_bit_valid[0:0] + 11/13: $1\mul_a_valid[0:0] + 12/13: $1\tx_valid[0:0] + 13/13: $1\tx_data[7:0] +Creating decoders for process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + 1/30: $5\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.$result[127:0]$562 + 2/30: $5\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.carry[0:0]$564 + 3/30: $5\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.value[127:0]$563 + 4/30: $4\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.carry[0:0]$560 + 5/30: $4\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.value[127:0]$559 + 6/30: $4\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.$result[127:0]$558 + 7/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.next_value[127:0]$553 [127:120] + 8/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.next_value[127:0]$553 [119:0] + 9/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.$result[127:0]$550 + 10/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.byte_value[7:0]$552 + 11/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.value[127:0]$551 + 12/30: $3\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.carry[0:0]$556 + 13/30: $3\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.value[127:0]$555 + 14/30: $3\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.$result[127:0]$554 + 15/30: $2\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.carry[0:0]$549 + 16/30: $2\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.value[127:0]$548 + 17/30: $2\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.$result[127:0]$547 + 18/30: $2\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.next_value[127:0]$546 + 19/30: $2\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.byte_value[7:0]$545 + 20/30: $2\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.value[127:0]$544 + 21/30: $2\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.$result[127:0]$543 + 22/30: $1\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.carry[0:0]$542 + 23/30: $1\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.value[127:0]$541 + 24/30: $1\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.$result[127:0]$540 + 25/30: $1\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.next_value[127:0]$539 + 26/30: $1\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.byte_value[7:0]$538 + 27/30: $1\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.value[127:0]$537 + 28/30: $1\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.$result[127:0]$536 + 29/30: $0\accumulator[127:0] + 30/30: $0\a_shift[127:0] +Creating decoders for process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + 1/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$445 + 2/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$448 + 3/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$449 + 4/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$447 + 5/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$446 + 6/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$440 + 7/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$443 + 8/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$444 + 9/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$442 + 10/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$441 + 11/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$400 + 12/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$403 + 13/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$404 + 14/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$402 + 15/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$401 + 16/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$365 + 17/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$364 + 18/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$363 + 19/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$362 + 20/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$361 + 21/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$360 + 22/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$359 + 23/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$358 + 24/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$357 + 25/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$356 + 26/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$355 + 27/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$354 + 28/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$353 + 29/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$352 + 30/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$351 + 31/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result[31:0]$346 + 32/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index[31:0]$349 + 33/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work[31:0]$350 + 34/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data[7:0]$348 + 35/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in[31:0]$347 + 36/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$343 + 37/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$342 + 38/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$341 + 39/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$340 + 40/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$339 + 41/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$338 + 42/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$337 + 43/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$336 + 44/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$335 + 45/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$334 + 46/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$333 + 47/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$332 + 48/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$331 + 49/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$330 + 50/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$329 + 51/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work[31:0]$328 + 52/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index[31:0]$327 + 53/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data[7:0]$326 + 54/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in[31:0]$325 + 55/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result[31:0]$324 + 56/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$322 + 57/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$321 + 58/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$320 + 59/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$319 + 60/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$318 + 61/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$317 + 62/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$316 + 63/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$315 + 64/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$314 + 65/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$313 + 66/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$312 + 67/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$311 + 68/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$310 + 69/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$309 + 70/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$308 + 71/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work[31:0]$307 + 72/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index[31:0]$306 + 73/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data[7:0]$305 + 74/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in[31:0]$304 + 75/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result[31:0]$303 + 76/105: $0\done_pulse[0:0] + 77/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$300 + 78/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$299 + 79/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$298 + 80/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$297 + 81/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$296 + 82/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$295 + 83/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$294 + 84/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$293 + 85/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$292 + 86/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$291 + 87/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$290 + 88/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$289 + 89/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$288 + 90/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$287 + 91/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$286 + 92/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work[31:0]$285 + 93/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index[31:0]$284 + 94/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data[7:0]$283 + 95/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in[31:0]$282 + 96/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result[31:0]$281 + 97/105: $0\payload_crc_work[31:0] + 98/105: $0\envelope_crc_work[31:0] + 99/105: $0\saved_crc[31:0] + 100/105: $0\saved_payload[543:0] + 101/105: $0\saved_status[7:0] + 102/105: $0\saved_length[15:0] + 103/105: $0\index[15:0] + 104/105: $0\active[0:0] + 105/105: $0\payload_crc[31:0] +Creating decoders for process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:44$244'. + 1/7: $7\tx_data[7:0] + 2/7: $6\tx_data[7:0] + 3/7: $5\tx_data[7:0] + 4/7: $4\tx_data[7:0] + 5/7: $3\tx_data[7:0] + 6/7: $2\tx_data[7:0] + 7/7: $1\tx_data[7:0] +Creating decoders for process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + 1/89: $0\received_crc[31:0] [31:24] + 2/89: $0\received_crc[31:0] [23:16] + 3/89: $0\received_crc[31:0] [15:8] + 4/89: $0\received_crc[31:0] [7:0] + 5/89: $5$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$185 + 6/89: $5$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$184 + 7/89: $5$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$186 + 8/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result[31:0]$177 + 9/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index[31:0]$180 + 10/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work[31:0]$181 + 11/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data[7:0]$179 + 12/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in[31:0]$178 + 13/89: $4$lookahead\frame_payload$22[2047:0]$182 + 14/89: $4$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$176 + 15/89: $4$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$175 + 16/89: $4$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$174 + 17/89: $0\declared_length[15:0] [15:8] + 18/89: $0\declared_length[15:0] [7:0] + 19/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index[31:0]$103 + 20/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data[7:0]$102 + 21/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result[31:0]$101 + 22/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work[31:0]$85 + 23/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index[31:0]$84 + 24/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data[7:0]$83 + 25/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result[31:0]$82 + 26/89: $3$lookahead\frame_payload$22[2047:0]$99 + 27/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work[31:0]$98 + 28/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index[31:0]$97 + 29/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data[7:0]$96 + 30/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in[31:0]$95 + 31/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result[31:0]$94 + 32/89: $3$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$93 + 33/89: $3$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$92 + 34/89: $3$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$91 + 35/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.work[31:0]$90 + 36/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.bit_index[31:0]$89 + 37/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.data[7:0]$88 + 38/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.crc_in[31:0]$87 + 39/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.$result[31:0]$86 + 40/89: $2$lookahead\frame_payload$22[2047:0]$81 + 41/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work[31:0]$80 + 42/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index[31:0]$79 + 43/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data[7:0]$78 + 44/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in[31:0]$77 + 45/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result[31:0]$76 + 46/89: $2$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$75 + 47/89: $2$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$74 + 48/89: $2$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$73 + 49/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.work[31:0]$72 + 50/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.bit_index[31:0]$71 + 51/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.data[7:0]$70 + 52/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.crc_in[31:0]$69 + 53/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.$result[31:0]$68 + 54/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work[31:0]$67 + 55/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index[31:0]$66 + 56/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data[7:0]$65 + 57/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result[31:0]$64 + 58/89: $1$lookahead\frame_payload$22[2047:0]$61 + 59/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work[31:0]$60 + 60/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index[31:0]$59 + 61/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data[7:0]$58 + 62/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in[31:0]$57 + 63/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result[31:0]$56 + 64/89: $1$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$55 + 65/89: $1$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$54 + 66/89: $1$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$53 + 67/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.work[31:0]$52 + 68/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.bit_index[31:0]$51 + 69/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.data[7:0]$50 + 70/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.crc_in[31:0]$49 + 71/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.$result[31:0]$48 + 72/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work[31:0]$47 + 73/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index[31:0]$46 + 74/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data[7:0]$45 + 75/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result[31:0]$44 + 76/89: $5$lookahead\frame_payload$22[2047:0]$187 + 77/89: $0\crc[31:0] + 78/89: $0\flags[7:0] + 79/89: $0\opcode[7:0] + 80/89: $0\version[7:0] + 81/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work[31:0]$104 + 82/89: $0\body_index[15:0] + 83/89: $0\header_index[2:0] + 84/89: $0\state[2:0] + 85/89: $0\fault_status[7:0] + 86/89: $0\fault_valid[0:0] + 87/89: $0\frame_length[15:0] + 88/89: $0\frame_opcode[7:0] + 89/89: $0\frame_valid[0:0] + +10.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\gate.\_3842_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5184$3216.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6477'. +No latch inferred for signal `\gate.\_3842_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5184$3265.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6477'. +No latch inferred for signal `\gate.\_3842_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5184$3265.a' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6477'. +No latch inferred for signal `\gate.\_3842_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5184$3265.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6477'. +No latch inferred for signal `\gate.\_3842_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5184$3265.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6477'. +No latch inferred for signal `\gate.\_3764_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5091$3215.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6470'. +No latch inferred for signal `\gate.\_3764_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5091$3264.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6470'. +No latch inferred for signal `\gate.\_3764_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5091$3264.a' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6470'. +No latch inferred for signal `\gate.\_3764_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5091$3264.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6470'. +No latch inferred for signal `\gate.\_3764_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5091$3264.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6470'. +No latch inferred for signal `\gate.\_3754_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5066$3214.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6464'. +No latch inferred for signal `\gate.\_3754_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5066$3263.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6464'. +No latch inferred for signal `\gate.\_3754_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5066$3263.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6464'. +No latch inferred for signal `\gate.\_3754_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5066$3263.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6464'. +No latch inferred for signal `\gate.\_3742_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5039$3213.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6458'. +No latch inferred for signal `\gate.\_3742_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5039$3262.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6458'. +No latch inferred for signal `\gate.\_3742_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5039$3262.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6458'. +No latch inferred for signal `\gate.\_3742_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5039$3262.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6458'. +No latch inferred for signal `\gate.\_3740_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5024$3212.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6452'. +No latch inferred for signal `\gate.\_3740_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5024$3261.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6452'. +No latch inferred for signal `\gate.\_3740_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5024$3261.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6452'. +No latch inferred for signal `\gate.\_3740_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5024$3261.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6452'. +No latch inferred for signal `\gate.\_3734_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5003$3211.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6446'. +No latch inferred for signal `\gate.\_3734_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5003$3260.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6446'. +No latch inferred for signal `\gate.\_3734_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5003$3260.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6446'. +No latch inferred for signal `\gate.\_3734_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5003$3260.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6446'. +No latch inferred for signal `\gate.\_3732_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4988$3210.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6440'. +No latch inferred for signal `\gate.\_3732_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4988$3259.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6440'. +No latch inferred for signal `\gate.\_3732_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4988$3259.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6440'. +No latch inferred for signal `\gate.\_3732_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4988$3259.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6440'. +No latch inferred for signal `\gate.\_3730_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4971$3209.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6434'. +No latch inferred for signal `\gate.\_3730_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4971$3258.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6434'. +No latch inferred for signal `\gate.\_3730_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4971$3258.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6434'. +No latch inferred for signal `\gate.\_3730_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4971$3258.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6434'. +No latch inferred for signal `\gate.\_3727_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4953$3208.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6428'. +No latch inferred for signal `\gate.\_3727_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4953$3257.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6428'. +No latch inferred for signal `\gate.\_3727_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4953$3257.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6428'. +No latch inferred for signal `\gate.\_3727_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4953$3257.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6428'. +No latch inferred for signal `\gate.\_3725_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4938$3207.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6422'. +No latch inferred for signal `\gate.\_3725_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4938$3256.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6422'. +No latch inferred for signal `\gate.\_3725_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4938$3256.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6422'. +No latch inferred for signal `\gate.\_3725_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4938$3256.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6422'. +No latch inferred for signal `\gate.\_3721_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4921$3206.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6416'. +No latch inferred for signal `\gate.\_3721_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4921$3255.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6416'. +No latch inferred for signal `\gate.\_3721_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4921$3255.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6416'. +No latch inferred for signal `\gate.\_3721_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4921$3255.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6416'. +No latch inferred for signal `\gate.\_3717_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4904$3205.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6410'. +No latch inferred for signal `\gate.\_3717_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4904$3254.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6410'. +No latch inferred for signal `\gate.\_3717_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4904$3254.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6410'. +No latch inferred for signal `\gate.\_3717_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4904$3254.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6410'. +No latch inferred for signal `\gate.\_3653_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4827$3204.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6404'. +No latch inferred for signal `\gate.\_3653_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4827$3253.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6404'. +No latch inferred for signal `\gate.\_3653_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4827$3253.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6404'. +No latch inferred for signal `\gate.\_3653_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4827$3253.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6404'. +No latch inferred for signal `\gate.\_3652_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4805$3203.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6398'. +No latch inferred for signal `\gate.\_3652_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4805$3252.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6398'. +No latch inferred for signal `\gate.\_3652_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4805$3252.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6398'. +No latch inferred for signal `\gate.\_3652_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4805$3252.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6398'. +No latch inferred for signal `\gate.\_3647_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4785$3202.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6392'. +No latch inferred for signal `\gate.\_3647_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4785$3251.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6392'. +No latch inferred for signal `\gate.\_3647_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4785$3251.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6392'. +No latch inferred for signal `\gate.\_3647_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4785$3251.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6392'. +No latch inferred for signal `\gate.\_3646_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4771$3201.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6386'. +No latch inferred for signal `\gate.\_3646_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4771$3250.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6386'. +No latch inferred for signal `\gate.\_3646_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4771$3250.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6386'. +No latch inferred for signal `\gate.\_3646_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4771$3250.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6386'. +No latch inferred for signal `\gate.\_3642_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4754$3200.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6380'. +No latch inferred for signal `\gate.\_3642_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4754$3249.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6380'. +No latch inferred for signal `\gate.\_3642_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4754$3249.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6380'. +No latch inferred for signal `\gate.\_3642_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4754$3249.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6380'. +No latch inferred for signal `\gate.\_3634_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4731$3199.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6375'. +No latch inferred for signal `\gate.\_3634_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4731$3248.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6375'. +No latch inferred for signal `\gate.\_3634_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4731$3248.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6375'. +No latch inferred for signal `\gate.\_3626_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4708$3198.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6370'. +No latch inferred for signal `\gate.\_3626_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4708$3247.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6370'. +No latch inferred for signal `\gate.\_3626_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4708$3247.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6370'. +No latch inferred for signal `\gate.\_3611_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4672$3197.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6364'. +No latch inferred for signal `\gate.\_3611_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4672$3246.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6364'. +No latch inferred for signal `\gate.\_3611_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4672$3246.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6364'. +No latch inferred for signal `\gate.\_3611_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4672$3246.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6364'. +No latch inferred for signal `\gate.\_3608_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4640$3196.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6359'. +No latch inferred for signal `\gate.\_3608_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4640$3245.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6359'. +No latch inferred for signal `\gate.\_3608_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4640$3245.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6359'. +No latch inferred for signal `\gate.\_3607_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4626$3195.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6353'. +No latch inferred for signal `\gate.\_3607_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4626$3244.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6353'. +No latch inferred for signal `\gate.\_3607_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4626$3244.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6353'. +No latch inferred for signal `\gate.\_3607_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4626$3244.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6353'. +No latch inferred for signal `\gate.\_3599_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4605$3194.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6347'. +No latch inferred for signal `\gate.\_3599_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4605$3243.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6347'. +No latch inferred for signal `\gate.\_3599_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4605$3243.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6347'. +No latch inferred for signal `\gate.\_3599_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4605$3243.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6347'. +No latch inferred for signal `\gate.\_3592_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4577$3193.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6341'. +No latch inferred for signal `\gate.\_3592_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4577$3242.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6341'. +No latch inferred for signal `\gate.\_3592_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4577$3242.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6341'. +No latch inferred for signal `\gate.\_3592_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4577$3242.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6341'. +No latch inferred for signal `\gate.\_3588_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4554$3192.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6335'. +No latch inferred for signal `\gate.\_3588_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4554$3241.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6335'. +No latch inferred for signal `\gate.\_3588_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4554$3241.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6335'. +No latch inferred for signal `\gate.\_3588_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4554$3241.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6335'. +No latch inferred for signal `\gate.\_3559_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4506$3191.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6329'. +No latch inferred for signal `\gate.\_3559_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4506$3240.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6329'. +No latch inferred for signal `\gate.\_3559_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4506$3240.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6329'. +No latch inferred for signal `\gate.\_3559_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4506$3240.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6329'. +No latch inferred for signal `\gate.\_3550_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4478$3190.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6323'. +No latch inferred for signal `\gate.\_3550_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4478$3239.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6323'. +No latch inferred for signal `\gate.\_3550_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4478$3239.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6323'. +No latch inferred for signal `\gate.\_3550_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4478$3239.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6323'. +No latch inferred for signal `\gate.\_3542_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4455$3189.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6317'. +No latch inferred for signal `\gate.\_3542_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4455$3238.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6317'. +No latch inferred for signal `\gate.\_3542_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4455$3238.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6317'. +No latch inferred for signal `\gate.\_3542_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4455$3238.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6317'. +No latch inferred for signal `\gate.\_3536_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4434$3188.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6311'. +No latch inferred for signal `\gate.\_3536_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4434$3237.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6311'. +No latch inferred for signal `\gate.\_3536_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4434$3237.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6311'. +No latch inferred for signal `\gate.\_3536_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4434$3237.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6311'. +No latch inferred for signal `\gate.\_3533_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4418$3187.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6305'. +No latch inferred for signal `\gate.\_3533_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4418$3236.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6305'. +No latch inferred for signal `\gate.\_3533_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4418$3236.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6305'. +No latch inferred for signal `\gate.\_3533_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4418$3236.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6305'. +No latch inferred for signal `\gate.\_3473_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4344$3186.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6299'. +No latch inferred for signal `\gate.\_3473_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4344$3235.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6299'. +No latch inferred for signal `\gate.\_3473_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4344$3235.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6299'. +No latch inferred for signal `\gate.\_3473_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4344$3235.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6299'. +No latch inferred for signal `\gate.\_3472_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4322$3185.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6293'. +No latch inferred for signal `\gate.\_3472_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4322$3234.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6293'. +No latch inferred for signal `\gate.\_3472_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4322$3234.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6293'. +No latch inferred for signal `\gate.\_3472_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4322$3234.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6293'. +No latch inferred for signal `\gate.\_3470_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4305$3184.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6287'. +No latch inferred for signal `\gate.\_3470_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4305$3233.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6287'. +No latch inferred for signal `\gate.\_3470_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4305$3233.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6287'. +No latch inferred for signal `\gate.\_3470_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4305$3233.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6287'. +No latch inferred for signal `\gate.\_3469_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4291$3183.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6281'. +No latch inferred for signal `\gate.\_3469_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4291$3232.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6281'. +No latch inferred for signal `\gate.\_3469_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4291$3232.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6281'. +No latch inferred for signal `\gate.\_3469_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4291$3232.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6281'. +No latch inferred for signal `\gate.\_3467_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4276$3182.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6275'. +No latch inferred for signal `\gate.\_3467_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4276$3231.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6275'. +No latch inferred for signal `\gate.\_3467_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4276$3231.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6275'. +No latch inferred for signal `\gate.\_3467_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4276$3231.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6275'. +No latch inferred for signal `\gate.\_3460_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4254$3181.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6270'. +No latch inferred for signal `\gate.\_3460_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4254$3230.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6270'. +No latch inferred for signal `\gate.\_3460_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4254$3230.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6270'. +No latch inferred for signal `\gate.\_3458_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4237$3180.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6265'. +No latch inferred for signal `\gate.\_3458_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4237$3229.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6265'. +No latch inferred for signal `\gate.\_3458_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4237$3229.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6265'. +No latch inferred for signal `\gate.\_3444_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4202$3179.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6259'. +No latch inferred for signal `\gate.\_3444_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4202$3228.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6259'. +No latch inferred for signal `\gate.\_3444_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4202$3228.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6259'. +No latch inferred for signal `\gate.\_3444_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4202$3228.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6259'. +No latch inferred for signal `\gate.\_3435_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4164$3178.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6254'. +No latch inferred for signal `\gate.\_3435_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4164$3227.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6254'. +No latch inferred for signal `\gate.\_3435_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4164$3227.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6254'. +No latch inferred for signal `\gate.\_3434_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4150$3177.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6248'. +No latch inferred for signal `\gate.\_3434_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4150$3226.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6248'. +No latch inferred for signal `\gate.\_3434_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4150$3226.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6248'. +No latch inferred for signal `\gate.\_3434_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4150$3226.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6248'. +No latch inferred for signal `\gate.\_3425_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4128$3176.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6242'. +No latch inferred for signal `\gate.\_3425_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4128$3225.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6242'. +No latch inferred for signal `\gate.\_3425_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4128$3225.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6242'. +No latch inferred for signal `\gate.\_3425_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4128$3225.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6242'. +No latch inferred for signal `\gate.\_3418_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4100$3175.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6236'. +No latch inferred for signal `\gate.\_3418_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4100$3224.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6236'. +No latch inferred for signal `\gate.\_3418_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4100$3224.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6236'. +No latch inferred for signal `\gate.\_3418_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4100$3224.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6236'. +No latch inferred for signal `\gate.\_3412_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4075$3174.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6230'. +No latch inferred for signal `\gate.\_3412_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4075$3223.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6230'. +No latch inferred for signal `\gate.\_3412_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4075$3223.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6230'. +No latch inferred for signal `\gate.\_3412_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4075$3223.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6230'. +No latch inferred for signal `\gate.\_3378_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4020$3173.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6223'. +No latch inferred for signal `\gate.\_3378_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4020$3222.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6223'. +No latch inferred for signal `\gate.\_3378_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4020$3222.a' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6223'. +No latch inferred for signal `\gate.\_3378_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4020$3222.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6223'. +No latch inferred for signal `\gate.\_3378_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4020$3222.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6223'. +No latch inferred for signal `\gate.\_3363_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3992$3172.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6217'. +No latch inferred for signal `\gate.\_3363_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3992$3221.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6217'. +No latch inferred for signal `\gate.\_3363_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3992$3221.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6217'. +No latch inferred for signal `\gate.\_3363_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3992$3221.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6217'. +No latch inferred for signal `\gate.\_3354_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3964$3171.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6211'. +No latch inferred for signal `\gate.\_3354_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3964$3220.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6211'. +No latch inferred for signal `\gate.\_3354_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3964$3220.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6211'. +No latch inferred for signal `\gate.\_3354_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3964$3220.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6211'. +No latch inferred for signal `\gate.\_3346_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3941$3170.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6205'. +No latch inferred for signal `\gate.\_3346_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3941$3219.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6205'. +No latch inferred for signal `\gate.\_3346_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3941$3219.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6205'. +No latch inferred for signal `\gate.\_3346_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3941$3219.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6205'. +No latch inferred for signal `\gate.\_3338_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3918$3169.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6199'. +No latch inferred for signal `\gate.\_3338_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3918$3218.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6199'. +No latch inferred for signal `\gate.\_3338_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3918$3218.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6199'. +No latch inferred for signal `\gate.\_3338_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3918$3218.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6199'. +No latch inferred for signal `\gate.\_3335_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3900$3168.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6193'. +No latch inferred for signal `\gate.\_3335_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3900$3217.$result' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6193'. +No latch inferred for signal `\gate.\_3335_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3900$3217.b' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6193'. +No latch inferred for signal `\gate.\_3335_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3900$3217.s' from process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6193'. +No latch inferred for signal `\lsc1_stream_adapter.\core_rx_data' from process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. +No latch inferred for signal `\lsc1_stream_adapter.\core_rx_valid' from process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. +No latch inferred for signal `\leanvm_b_stream_alu.\rx_ready' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\tx_data' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\tx_valid' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_a_valid' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_valid' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_value' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_result_shift' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.$result' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.index' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\lsc1_packet_tx.\tx_data' from process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:44$244'. + +10.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\gate.\adapter.datapath.byte_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3416$3425'. + created $dff cell `$procdff$150149' with positive edge clock. +Creating register for signal `\gate.\adapter.datapath.state' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3413$3424'. + created $dff cell `$procdff$150150' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.result' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3410$3423'. + created $dff cell `$procdff$150151' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.datapath.state' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3407$3422'. + created $dff cell `$procdff$150152' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.datapath.byte_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3404$3421'. + created $dff cell `$procdff$150153' with positive edge clock. +Creating register for signal `\gate.\write_value' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3402$3420'. + created $dff cell `$procdff$150154' with positive edge clock. +Creating register for signal `\gate.\write_address' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3400$3419'. + created $dff cell `$procdff$150155' with positive edge clock. +Creating register for signal `\gate.\solved_b' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3398$3418'. + created $dff cell `$procdff$150156' with positive edge clock. +Creating register for signal `\gate.\solved_a' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3396$3417'. + created $dff cell `$procdff$150157' with positive edge clock. +Creating register for signal `\gate.\result_value' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3394$3416'. + created $dff cell `$procdff$150158' with positive edge clock. +Creating register for signal `\gate.\inv_value' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3392$3415'. + created $dff cell `$procdff$150159' with positive edge clock. +Creating register for signal `\gate.\val_c' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3390$3414'. + created $dff cell `$procdff$150160' with positive edge clock. +Creating register for signal `\gate.\val_b' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3388$3413'. + created $dff cell `$procdff$150161' with positive edge clock. +Creating register for signal `\gate.\val_a' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3386$3412'. + created $dff cell `$procdff$150162' with positive edge clock. +Creating register for signal `\gate.\pres_c' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3384$3411'. + created $dff cell `$procdff$150163' with positive edge clock. +Creating register for signal `\gate.\pres_b' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3382$3410'. + created $dff cell `$procdff$150164' with positive edge clock. +Creating register for signal `\gate.\pres_a' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3380$3409'. + created $dff cell `$procdff$150165' with positive edge clock. +Creating register for signal `\gate.\profile' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3378$3408'. + created $dff cell `$procdff$150166' with positive edge clock. +Creating register for signal `\gate.\deferred_local' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3376$3407'. + created $dff cell `$procdff$150167' with positive edge clock. +Creating register for signal `\gate.\deferred_target' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3374$3406'. + created $dff cell `$procdff$150168' with positive edge clock. +Creating register for signal `\gate.\next_fp_value' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3372$3405'. + created $dff cell `$procdff$150169' with positive edge clock. +Creating register for signal `\gate.\next_pc_value' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3370$3404'. + created $dff cell `$procdff$150170' with positive edge clock. +Creating register for signal `\gate.\proposed_fp' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3368$3403'. + created $dff cell `$procdff$150171' with positive edge clock. +Creating register for signal `\gate.\proposed_pc' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3366$3402'. + created $dff cell `$procdff$150172' with positive edge clock. +Creating register for signal `\gate.\addr_c' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3364$3401'. + created $dff cell `$procdff$150173' with positive edge clock. +Creating register for signal `\gate.\addr_b' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3362$3400'. + created $dff cell `$procdff$150174' with positive edge clock. +Creating register for signal `\gate.\addr_a' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3360$3399'. + created $dff cell `$procdff$150175' with positive edge clock. +Creating register for signal `\gate.\fp' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3358$3398'. + created $dff cell `$procdff$150176' with positive edge clock. +Creating register for signal `\gate.\pc' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3356$3397'. + created $dff cell `$procdff$150177' with positive edge clock. +Creating register for signal `\gate.\txn_id' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3354$3396'. + created $dff cell `$procdff$150178' with positive edge clock. +Creating register for signal `\gate.\n_deferred' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3352$3395'. + created $dff cell `$procdff$150179' with positive edge clock. +Creating register for signal `\gate.\n_writes' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3350$3394'. + created $dff cell `$procdff$150180' with positive edge clock. +Creating register for signal `\gate.\adapter.result' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3347$3393'. + created $dff cell `$procdff$150181' with positive edge clock. +Creating register for signal `\gate.\receiver.frame_payload' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3344$3392'. + created $dff cell `$procdff$150182' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.saved_operation_reg[1]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3340$3390'. + created $dff cell `$procdff$150183' with positive edge clock. +Creating register for signal `\gate.\transmitter.payload_crc_work' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3336$3389'. + created $dff cell `$procdff$150184' with positive edge clock. +Creating register for signal `\gate.\transmitter.envelope_crc_work' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3333$3388'. + created $dff cell `$procdff$150185' with positive edge clock. +Creating register for signal `\gate.\transmitter.saved_crc' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3330$3387'. + created $dff cell `$procdff$150186' with positive edge clock. +Creating register for signal `\gate.\transmitter.saved_payload' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3327$3386'. + created $dff cell `$procdff$150187' with positive edge clock. +Creating register for signal `\gate.\transmitter.saved_status' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3324$3385'. + created $dff cell `$procdff$150188' with positive edge clock. +Creating register for signal `\gate.\transmitter.saved_length' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3321$3384'. + created $dff cell `$procdff$150189' with positive edge clock. +Creating register for signal `\gate.\transmitter.index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3318$3383'. + created $dff cell `$procdff$150190' with positive edge clock. +Creating register for signal `\gate.\transmitter.active' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3315$3382'. + created $dff cell `$procdff$150191' with positive edge clock. +Creating register for signal `\gate.\transmitter.payload_crc' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3312$3381'. + created $dff cell `$procdff$150192' with positive edge clock. +Creating register for signal `\gate.\transmitter.done_pulse' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3309$3380'. + created $dff cell `$procdff$150193' with positive edge clock. +Creating register for signal `\gate.\field_encoder.done_pulse' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3306$3379'. + created $dff cell `$procdff$150194' with positive edge clock. +Creating register for signal `\gate.\field_encoder.busy' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3303$3378'. + created $dff cell `$procdff$150195' with positive edge clock. +Creating register for signal `\gate.\adapter.datapath.multiplier.impl.a_shift' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3300$3377'. + created $dff cell `$procdff$150196' with positive edge clock. +Creating register for signal `\gate.\adapter.datapath.multiplier.impl.accumulator' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3297$3376'. + created $dff cell `$procdff$150197' with positive edge clock. +Creating register for signal `\gate.\adapter.result_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3294$3375'. + created $dff cell `$procdff$150198' with positive edge clock. +Creating register for signal `\gate.\adapter.payload_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3291$3374'. + created $dff cell `$procdff$150199' with positive edge clock. +Creating register for signal `\gate.\adapter.saved_b' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3288$3372'. + created $dff cell `$procdff$150200' with positive edge clock. +Creating register for signal `\gate.\adapter.saved_a' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3285$3370'. + created $dff cell `$procdff$150201' with positive edge clock. +Creating register for signal `\gate.\adapter.saved_operation' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3282$3368'. + created $dff cell `$procdff$150202' with positive edge clock. +Creating register for signal `\gate.\adapter.fault' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3279$3366'. + created $dff cell `$procdff$150203' with positive edge clock. +Creating register for signal `\gate.\adapter.done_pulse' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3276$3365'. + created $dff cell `$procdff$150204' with positive edge clock. +Creating register for signal `\gate.\adapter.state' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3273$3364'. + created $dff cell `$procdff$150205' with positive edge clock. +Creating register for signal `\gate.\done_pulse' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3270$3363'. + created $dff cell `$procdff$150206' with positive edge clock. +Creating register for signal `\gate.\fault' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3267$3361'. + created $dff cell `$procdff$150207' with positive edge clock. +Creating register for signal `\gate.\tx_start' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3264$3360'. + created $dff cell `$procdff$150208' with positive edge clock. +Creating register for signal `\gate.\tx_status' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3261$3358'. + created $dff cell `$procdff$150209' with positive edge clock. +Creating register for signal `\gate.\tx_length' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3258$3356'. + created $dff cell `$procdff$150210' with positive edge clock. +Creating register for signal `\gate.\tx_payload' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3255$3354'. + created $dff cell `$procdff$150211' with positive edge clock. +Creating register for signal `\gate.\capture_result_crc' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3252$3353'. + created $dff cell `$procdff$150212' with positive edge clock. +Creating register for signal `\gate.\compute_state' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3249$3352'. + created $dff cell `$procdff$150213' with positive edge clock. +Creating register for signal `\gate.\alu_start' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3246$3351'. + created $dff cell `$procdff$150214' with positive edge clock. +Creating register for signal `\gate.\alu_operation' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3243$3349'. + created $dff cell `$procdff$150215' with positive edge clock. +Creating register for signal `\gate.\alu_operand_a' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3240$3347'. + created $dff cell `$procdff$150216' with positive edge clock. +Creating register for signal `\gate.\alu_operand_b' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3237$3345'. + created $dff cell `$procdff$150217' with positive edge clock. +Creating register for signal `\gate.\encoder_start' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3234$3344'. + created $dff cell `$procdff$150218' with positive edge clock. +Creating register for signal `\gate.\encoder_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3231$3342'. + created $dff cell `$procdff$150219' with positive edge clock. +Creating register for signal `\gate.\result_pending' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3228$3341'. + created $dff cell `$procdff$150220' with positive edge clock. +Creating register for signal `\gate.\staged_txn_id' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3225$3339'. + created $dff cell `$procdff$150221' with positive edge clock. +Creating register for signal `\gate.\staged_next_pc' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3222$3337'. + created $dff cell `$procdff$150222' with positive edge clock. +Creating register for signal `\gate.\staged_next_fp' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3219$3335'. + created $dff cell `$procdff$150223' with positive edge clock. +Creating register for signal `\gate.\staged_result_crc' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3216$3332'. + created $dff cell `$procdff$150224' with positive edge clock. +Creating register for signal `\gate.\state_valid' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3213$3330'. + created $dff cell `$procdff$150225' with positive edge clock. +Creating register for signal `\gate.\committed_pc' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3210$3328'. + created $dff cell `$procdff$150226' with positive edge clock. +Creating register for signal `\gate.\committed_fp' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3207$3326'. + created $dff cell `$procdff$150227' with positive edge clock. +Creating register for signal `\gate.\retire_seq' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3204$3324'. + created $dff cell `$procdff$150228' with positive edge clock. +Creating register for signal `\gate.\active_profile' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3201$3322'. + created $dff cell `$procdff$150229' with positive edge clock. +Creating register for signal `\gate.\_2785_' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3197$3320'. + created $dff cell `$procdff$150230' with positive edge clock. +Creating register for signal `\gate.\_2784_' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3192$3319'. + created $dff cell `$procdff$150231' with positive edge clock. +Creating register for signal `\gate.\_2783_' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3187$3317'. + created $dff cell `$procdff$150232' with positive edge clock. +Creating register for signal `\gate.\_2782_' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3182$3316'. + created $dff cell `$procdff$150233' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.datapath.scratch_byte [7:1]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3178$3315'. + created $dff cell `$procdff$150234' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.datapath.scratch_byte [0]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3175$3314'. + created $dff cell `$procdff$150235' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.datapath.fault' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3172$3312'. + created $dff cell `$procdff$150236' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.datapath.multiplier.impl.accumulator' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3169$3311'. + created $dff cell `$procdff$150237' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.datapath.multiplier.impl.a_shift' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3166$3310'. + created $dff cell `$procdff$150238' with positive edge clock. +Creating register for signal `\gate.\field_encoder.saved_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3163$3309'. + created $dff cell `$procdff$150239' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.state' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3160$3308'. + created $dff cell `$procdff$150240' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.done_pulse' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3157$3307'. + created $dff cell `$procdff$150241' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.fault' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3154$3305'. + created $dff cell `$procdff$150242' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.saved_b' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3151$3303'. + created $dff cell `$procdff$150243' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.payload_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3148$3302'. + created $dff cell `$procdff$150244' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiplier.result_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3145$3301'. + created $dff cell `$procdff$150245' with positive edge clock. +Creating register for signal `\gate.\field_encoder.bit_index [3:0]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3142$3300'. + created $dff cell `$procdff$150246' with positive edge clock. +Creating register for signal `\gate.\field_encoder.bit_index [4]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3139$3299'. + created $dff cell `$procdff$150247' with positive edge clock. +Creating register for signal `\gate.\field_encoder.multiply_start' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3136$3298'. + created $dff cell `$procdff$150248' with positive edge clock. +Creating register for signal `\gate.\adapter.datapath.fault' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3133$3296'. + created $dff cell `$procdff$150249' with positive edge clock. +Creating register for signal `\gate.\adapter.datapath.scratch_byte [7:1]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3130$3295'. + created $dff cell `$procdff$150250' with positive edge clock. +Creating register for signal `\gate.\adapter.datapath.scratch_byte [0]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3127$3294'. + created $dff cell `$procdff$150251' with positive edge clock. +Creating register for signal `\gate.\field_encoder.result' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3124$3293'. + created $dff cell `$procdff$150252' with positive edge clock. +Creating register for signal `\gate.\field_encoder.operand_b [0]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3121$3292'. + created $dff cell `$procdff$150253' with positive edge clock. +Creating register for signal `\gate.\field_encoder.operand_b [127:1]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3118$3291'. + created $dff cell `$procdff$150254' with positive edge clock. +Creating register for signal `\gate.\_2760_' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3114$3290'. + created $dff cell `$procdff$150255' with positive edge clock. +Creating register for signal `\gate.\_2759_' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3109$3289'. + created $dff cell `$procdff$150256' with positive edge clock. +Creating register for signal `\gate.\_2758_' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3104$3288'. + created $dff cell `$procdff$150257' with positive edge clock. +Creating register for signal `\gate.\receiver.crc' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3100$3287'. + created $dff cell `$procdff$150258' with positive edge clock. +Creating register for signal `\gate.\receiver.flags' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3097$3286'. + created $dff cell `$procdff$150259' with positive edge clock. +Creating register for signal `\gate.\receiver.opcode' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3094$3285'. + created $dff cell `$procdff$150260' with positive edge clock. +Creating register for signal `\gate.\receiver.version' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3091$3284'. + created $dff cell `$procdff$150261' with positive edge clock. +Creating register for signal `\gate.\receiver.declared_length [15:8]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3088$3283'. + created $dff cell `$procdff$150262' with positive edge clock. +Creating register for signal `\gate.\receiver.declared_length [7:0]' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3085$3282'. + created $dff cell `$procdff$150263' with positive edge clock. +Creating register for signal `\gate.\receiver.body_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3082$3281'. + created $dff cell `$procdff$150264' with positive edge clock. +Creating register for signal `\gate.\receiver.header_index' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3079$3280'. + created $dff cell `$procdff$150265' with positive edge clock. +Creating register for signal `\gate.\receiver.state' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3076$3279'. + created $dff cell `$procdff$150266' with positive edge clock. +Creating register for signal `\gate.\receiver.fault_status' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3073$3278'. + created $dff cell `$procdff$150267' with positive edge clock. +Creating register for signal `\gate.\receiver.fault_valid' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3070$3277'. + created $dff cell `$procdff$150268' with positive edge clock. +Creating register for signal `\gate.\receiver.frame_length' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3067$3276'. + created $dff cell `$procdff$150269' with positive edge clock. +Creating register for signal `\gate.\receiver.frame_opcode' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3064$3275'. + created $dff cell `$procdff$150270' with positive edge clock. +Creating register for signal `\gate.\receiver.frame_valid' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3061$3274'. + created $dff cell `$procdff$150271' with positive edge clock. +Creating register for signal `\gate.\field_encoder.fault' using process `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3058$3273'. + created $dff cell `$procdff$150272' with positive edge clock. +Creating register for signal `\gold.\done_pulse' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150273' with positive edge clock. +Creating register for signal `\gold.\fault' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150274' with positive edge clock. +Creating register for signal `\gold.\tx_start' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150275' with positive edge clock. +Creating register for signal `\gold.\tx_status' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150276' with positive edge clock. +Creating register for signal `\gold.\tx_length' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150277' with positive edge clock. +Creating register for signal `\gold.\tx_payload' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150278' with positive edge clock. +Creating register for signal `\gold.\capture_result_crc' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150279' with positive edge clock. +Creating register for signal `\gold.\compute_state' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150280' with positive edge clock. +Creating register for signal `\gold.\alu_start' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150281' with positive edge clock. +Creating register for signal `\gold.\alu_operation' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150282' with positive edge clock. +Creating register for signal `\gold.\alu_operand_a' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150283' with positive edge clock. +Creating register for signal `\gold.\alu_operand_b' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150284' with positive edge clock. +Creating register for signal `\gold.\encoder_start' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150285' with positive edge clock. +Creating register for signal `\gold.\encoder_index' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150286' with positive edge clock. +Creating register for signal `\gold.\result_pending' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150287' with positive edge clock. +Creating register for signal `\gold.\staged_txn_id' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150288' with positive edge clock. +Creating register for signal `\gold.\staged_next_pc' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150289' with positive edge clock. +Creating register for signal `\gold.\staged_next_fp' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150290' with positive edge clock. +Creating register for signal `\gold.\staged_result_crc' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150291' with positive edge clock. +Creating register for signal `\gold.\state_valid' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150292' with positive edge clock. +Creating register for signal `\gold.\committed_pc' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150293' with positive edge clock. +Creating register for signal `\gold.\committed_fp' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150294' with positive edge clock. +Creating register for signal `\gold.\retire_seq' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150295' with positive edge clock. +Creating register for signal `\gold.\active_profile' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150296' with positive edge clock. +Creating register for signal `\gold.\last_status' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150297' with positive edge clock. +Creating register for signal `\gold.\last_fault' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150298' with positive edge clock. +Creating register for signal `\gold.\n_writes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150299' with positive edge clock. +Creating register for signal `\gold.\n_deferred' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150300' with positive edge clock. +Creating register for signal `\gold.\result_length' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150301' with positive edge clock. +Creating register for signal `\gold.\txn_id' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150302' with positive edge clock. +Creating register for signal `\gold.\pc' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150303' with positive edge clock. +Creating register for signal `\gold.\fp' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150304' with positive edge clock. +Creating register for signal `\gold.\off_a' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150305' with positive edge clock. +Creating register for signal `\gold.\off_b' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150306' with positive edge clock. +Creating register for signal `\gold.\off_c' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150307' with positive edge clock. +Creating register for signal `\gold.\addr_a' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150308' with positive edge clock. +Creating register for signal `\gold.\addr_b' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150309' with positive edge clock. +Creating register for signal `\gold.\addr_c' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150310' with positive edge clock. +Creating register for signal `\gold.\base_index' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150311' with positive edge clock. +Creating register for signal `\gold.\proposed_pc' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150312' with positive edge clock. +Creating register for signal `\gold.\proposed_fp' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150313' with positive edge clock. +Creating register for signal `\gold.\next_pc_value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150314' with positive edge clock. +Creating register for signal `\gold.\next_fp_value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150315' with positive edge clock. +Creating register for signal `\gold.\deferred_target' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150316' with positive edge clock. +Creating register for signal `\gold.\deferred_local' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150317' with positive edge clock. +Creating register for signal `\gold.\profile' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150318' with positive edge clock. +Creating register for signal `\gold.\pres_a' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150319' with positive edge clock. +Creating register for signal `\gold.\pres_b' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150320' with positive edge clock. +Creating register for signal `\gold.\pres_c' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150321' with positive edge clock. +Creating register for signal `\gold.\inv_present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150322' with positive edge clock. +Creating register for signal `\gold.\taken_proposal' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150323' with positive edge clock. +Creating register for signal `\gold.\val_a' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150324' with positive edge clock. +Creating register for signal `\gold.\val_b' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150325' with positive edge clock. +Creating register for signal `\gold.\val_c' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150326' with positive edge clock. +Creating register for signal `\gold.\inv_value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150327' with positive edge clock. +Creating register for signal `\gold.\result_value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150328' with positive edge clock. +Creating register for signal `\gold.\solved_a' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150329' with positive edge clock. +Creating register for signal `\gold.\solved_b' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150330' with positive edge clock. +Creating register for signal `\gold.\result_bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150331' with positive edge clock. +Creating register for signal `\gold.\retired_bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150332' with positive edge clock. +Creating register for signal `\gold.\write_address' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150333' with positive edge clock. +Creating register for signal `\gold.\write_value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150334' with positive edge clock. +Creating register for signal `\gold.\decision_fault' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150335' with positive edge clock. +Creating register for signal `\gold.\decision_detail' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150336' with positive edge clock. +Creating register for signal `\gold.\decision_ok' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150337' with positive edge clock. +Creating register for signal `\gold.\decision_deferred' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150338' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150339' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150340' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150341' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150342' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150343' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150344' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150345' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150346' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150347' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150348' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150349' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150350' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150351' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150352' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150353' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150354' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150355' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150356' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150357' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150358' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150359' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150360' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150361' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150362' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150363' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150364' with positive edge clock. +Creating register for signal `\gold.\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150365' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150366' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150367' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150368' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150369' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150370' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150371' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150372' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150373' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150374' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150375' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150376' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150377' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150378' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150379' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150380' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150381' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150382' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150383' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150384' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150385' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150386' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150387' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150388' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150389' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150390' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150391' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150392' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150393' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150394' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150395' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150396' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150397' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150398' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150399' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150400' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150401' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150402' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150403' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150404' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150405' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150406' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150407' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150408' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150409' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150410' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150411' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150412' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150413' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150414' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150415' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150416' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150417' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150418' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150419' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150420' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150421' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150422' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150423' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150424' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150425' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150426' with positive edge clock. +Creating register for signal `\gold.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150427' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150428' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150429' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150430' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150431' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150432' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150433' with positive edge clock. +Creating register for signal `\gold.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150434' with positive edge clock. +Creating register for signal `\gold.\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count' using process `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$150435' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\busy' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150436' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\done_pulse' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150437' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\accumulator' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150438' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\fault' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150439' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\operand_a' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150440' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\operand_b' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150441' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\result' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150442' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\multiply_start' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150443' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\bit_index' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150444' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\saved_index' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150445' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\next_accumulator' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150446' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.$result' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150447' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.value' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$150448' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\state' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150449' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\done_pulse' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150450' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\fault' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150451' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\result' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150452' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_operation' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150453' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_a' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150454' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_b' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150455' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\payload_index' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150456' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\result_index' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150457' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150458' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150459' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150460' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150461' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150462' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150463' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$lookahead\result$670' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$150464' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\state' using process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + created $dff cell `$procdff$150465' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\fault' using process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + created $dff cell `$procdff$150466' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\byte_index' using process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + created $dff cell `$procdff$150467' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\scratch_byte' using process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + created $dff cell `$procdff$150468' with positive edge clock. +Creating register for signal `\gf2n_mul_bitstream.\a_shift' using process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + created $dff cell `$procdff$150469' with positive edge clock. +Creating register for signal `\gf2n_mul_bitstream.\accumulator' using process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + created $dff cell `$procdff$150470' with positive edge clock. +Creating register for signal `\gf2n_mul_bitstream.\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.$result' using process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + created $dff cell `$procdff$150471' with positive edge clock. +Creating register for signal `\gf2n_mul_bitstream.\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.value' using process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + created $dff cell `$procdff$150472' with positive edge clock. +Creating register for signal `\gf2n_mul_bitstream.\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.byte_value' using process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + created $dff cell `$procdff$150473' with positive edge clock. +Creating register for signal `\gf2n_mul_bitstream.\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$523.next_value' using process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + created $dff cell `$procdff$150474' with positive edge clock. +Creating register for signal `\gf2n_mul_bitstream.\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.$result' using process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + created $dff cell `$procdff$150475' with positive edge clock. +Creating register for signal `\gf2n_mul_bitstream.\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.value' using process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + created $dff cell `$procdff$150476' with positive edge clock. +Creating register for signal `\gf2n_mul_bitstream.\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$524.carry' using process `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. + created $dff cell `$procdff$150477' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\done_pulse' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150478' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150479' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\active' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150480' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150481' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_length' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150482' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_status' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150483' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_payload' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150484' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_crc' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150485' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\envelope_crc_work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150486' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc_work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150487' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150488' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150489' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150490' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150491' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150492' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150493' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150494' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150495' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150496' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150497' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150498' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150499' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150500' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150501' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150502' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150503' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150504' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150505' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150506' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$150507' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150508' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150509' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150510' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_payload' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150511' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150512' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_status' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150513' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\state' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150514' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\header_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150515' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\body_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150516' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\declared_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150517' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\version' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150518' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150519' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\flags' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150520' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150521' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\received_crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150522' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150523' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150524' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150525' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150526' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150527' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150528' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150529' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150530' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150531' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150532' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150533' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150534' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150535' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150536' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150537' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150538' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150539' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$lookahead\frame_payload$22' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$150540' with positive edge clock. + +10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6477'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6477'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6470'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6470'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6464'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6464'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6458'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6458'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6452'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6452'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6446'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6446'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6440'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6440'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6434'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6434'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6428'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6428'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6422'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6422'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6416'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6416'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6410'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6410'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6404'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6404'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6398'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6398'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6392'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6392'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6386'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6386'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6380'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6380'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6375'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6375'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6370'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6370'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6364'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6364'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6359'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6359'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6353'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6353'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6347'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6347'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6341'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6341'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6335'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6335'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6329'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6329'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6323'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6323'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6317'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6317'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6311'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6311'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6305'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6305'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6299'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6299'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6293'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6293'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6287'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6287'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6281'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6281'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6275'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6275'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6270'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6270'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6265'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6265'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6259'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6259'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6254'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6254'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6248'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6248'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6242'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6242'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6236'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6236'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6230'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6230'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6223'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6223'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6217'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6217'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6211'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6211'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6205'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6205'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6199'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6199'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6193'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:0$6193'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3416$3425'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3416$3425'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3413$3424'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3413$3424'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3410$3423'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3410$3423'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3407$3422'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3407$3422'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3404$3421'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3404$3421'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3402$3420'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3402$3420'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3400$3419'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3400$3419'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3398$3418'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3398$3418'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3396$3417'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3396$3417'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3394$3416'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3394$3416'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3392$3415'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3392$3415'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3390$3414'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3390$3414'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3388$3413'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3388$3413'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3386$3412'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3386$3412'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3384$3411'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3384$3411'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3382$3410'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3382$3410'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3380$3409'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3380$3409'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3378$3408'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3378$3408'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3376$3407'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3376$3407'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3374$3406'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3374$3406'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3372$3405'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3372$3405'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3370$3404'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3370$3404'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3368$3403'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3368$3403'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3366$3402'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3366$3402'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3364$3401'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3364$3401'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3362$3400'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3362$3400'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3360$3399'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3360$3399'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3358$3398'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3358$3398'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3356$3397'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3356$3397'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3354$3396'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3354$3396'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3352$3395'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3352$3395'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3350$3394'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3350$3394'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3347$3393'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3347$3393'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3344$3392'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3344$3392'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3340$3390'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3340$3390'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3336$3389'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3336$3389'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3333$3388'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3333$3388'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3330$3387'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3330$3387'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3327$3386'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3327$3386'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3324$3385'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3324$3385'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3321$3384'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3321$3384'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3318$3383'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3318$3383'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3315$3382'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3315$3382'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3312$3381'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3312$3381'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3309$3380'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3309$3380'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3306$3379'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3306$3379'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3303$3378'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3303$3378'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3300$3377'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3300$3377'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3297$3376'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3297$3376'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3294$3375'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3294$3375'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3291$3374'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3291$3374'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3288$3372'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3288$3372'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3285$3370'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3285$3370'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3282$3368'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3282$3368'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3279$3366'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3279$3366'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3276$3365'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3276$3365'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3273$3364'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3273$3364'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3270$3363'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3270$3363'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3267$3361'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3267$3361'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3264$3360'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3264$3360'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3261$3358'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3261$3358'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3258$3356'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3258$3356'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3255$3354'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3255$3354'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3252$3353'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3252$3353'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3249$3352'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3249$3352'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3246$3351'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3246$3351'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3243$3349'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3243$3349'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3240$3347'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3240$3347'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3237$3345'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3237$3345'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3234$3344'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3234$3344'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3231$3342'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3231$3342'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3228$3341'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3228$3341'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3225$3339'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3225$3339'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3222$3337'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3222$3337'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3219$3335'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3219$3335'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3216$3332'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3216$3332'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3213$3330'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3213$3330'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3210$3328'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3210$3328'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3207$3326'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3207$3326'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3204$3324'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3204$3324'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3201$3322'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3201$3322'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3197$3320'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3197$3320'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3192$3319'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3192$3319'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3187$3317'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3187$3317'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3182$3316'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3182$3316'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3178$3315'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3178$3315'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3175$3314'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3175$3314'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3172$3312'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3172$3312'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3169$3311'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3169$3311'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3166$3310'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3166$3310'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3163$3309'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3163$3309'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3160$3308'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3160$3308'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3157$3307'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3157$3307'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3154$3305'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3154$3305'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3151$3303'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3151$3303'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3148$3302'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3148$3302'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3145$3301'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3145$3301'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3142$3300'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3142$3300'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3139$3299'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3139$3299'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3136$3298'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3136$3298'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3133$3296'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3133$3296'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3130$3295'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3130$3295'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3127$3294'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3127$3294'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3124$3293'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3124$3293'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3121$3292'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3121$3292'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3118$3291'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3118$3291'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3114$3290'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3114$3290'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3109$3289'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3109$3289'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3104$3288'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3104$3288'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3100$3287'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3100$3287'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3097$3286'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3097$3286'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3094$3285'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3094$3285'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3091$3284'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3091$3284'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3088$3283'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3088$3283'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3085$3282'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3085$3282'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3082$3281'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3082$3281'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3079$3280'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3079$3280'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3076$3279'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3076$3279'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3073$3278'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3073$3278'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3070$3277'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3070$3277'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3067$3276'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3067$3276'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3064$3275'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3064$3275'. +Found and cleaned up 1 empty switch in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3061$3274'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3061$3274'. +Found and cleaned up 2 empty switches in `\gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3058$3273'. +Removing empty process `gate.$proc$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3058$3273'. +Found and cleaned up 110 empty switches in `\gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. +Removing empty process `gold.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. +Found and cleaned up 5 empty switches in `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. +Removing empty process `lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. +Found and cleaned up 14 empty switches in `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. +Removing empty process `lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. +Found and cleaned up 6 empty switches in `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. +Removing empty process `lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. +Found and cleaned up 23 empty switches in `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. +Removing empty process `leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. +Found and cleaned up 3 empty switches in `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +Removing empty process `leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +Found and cleaned up 7 empty switches in `\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. +Removing empty process `gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$527'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. +Removing empty process `lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:44$244'. +Removing empty process `lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:44$244'. +Found and cleaned up 14 empty switches in `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. +Removing empty process `lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. +Cleaned up 451 empty switches. + +10.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module gate. + +Optimizing module gold. + +Optimizing module lsc1_field_encoder. + +Optimizing module lsc1_stream_adapter. + +Optimizing module leanvm_b_stream_alu. + +Optimizing module gf128_mul_bitstream. +Optimizing module gf2n_mul_bitstream. + +Optimizing module lsc1_packet_tx. + +Optimizing module lsc1_packet_rx. + + +11. Executing MEMORY pass. + +11.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +11.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +11.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +11.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +11.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +11.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gate.. +Finding unused cells or wires in module \gold.. +Finding unused cells or wires in module \lsc1_field_encoder.. +Finding unused cells or wires in module \lsc1_stream_adapter.. +Finding unused cells or wires in module \leanvm_b_stream_alu.. +Finding unused cells or wires in module \gf128_mul_bitstream.. +Finding unused cells or wires in module \gf2n_mul_bitstream.. +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 27926 unused cells and 83021 unused wires. + + +11.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +11.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +11.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gate.. +Finding unused cells or wires in module \gf128_mul_bitstream.. +Finding unused cells or wires in module \gf2n_mul_bitstream.. +Finding unused cells or wires in module \gold.. +Finding unused cells or wires in module \leanvm_b_stream_alu.. +Finding unused cells or wires in module \lsc1_field_encoder.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_stream_adapter.. + +11.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +11.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +12. Executing OPT pass (performing simple optimizations). + +12.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module gate. + +Optimizing module gf128_mul_bitstream. +Optimizing module gf2n_mul_bitstream. +Optimizing module gold. +Optimizing module leanvm_b_stream_alu. +Optimizing module lsc1_field_encoder. +Optimizing module lsc1_packet_rx. + +Optimizing module lsc1_packet_tx. + +Optimizing module lsc1_stream_adapter. + + +12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gate'. + +Finding identical cells in module `\gf128_mul_bitstream'. +Finding identical cells in module `\gf2n_mul_bitstream'. +Finding identical cells in module `\gold'. + +Finding identical cells in module `\leanvm_b_stream_alu'. + +Finding identical cells in module `\lsc1_field_encoder'. +Finding identical cells in module `\lsc1_packet_rx'. + +Finding identical cells in module `\lsc1_packet_tx'. + +Finding identical cells in module `\lsc1_stream_adapter'. + +Removed a total of 378 cells. + +12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gate.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gf128_mul_bitstream.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gf2n_mul_bitstream.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gold.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port A of cell $procmux$12784: $28\decision_ok[0:0] -> 1'1 + Replacing known input bits on port A of cell $procmux$145375: \result_pending -> 1'0 + Replacing known input bits on port B of cell $procmux$145342: \result_pending -> 1'1 + Replacing known input bits on port B of cell $procmux$145339: \result_pending -> 1'0 + Replacing known input bits on port A of cell $procmux$145336: \result_pending -> 1'0 + Replacing known input bits on port A of cell $procmux$13953: $28\decision_ok[0:0] -> 1'0 + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$102401. + dead port 1/2 on $mux $procmux$102404. + dead port 1/2 on $mux $procmux$102407. + dead port 1/2 on $mux $procmux$102410. + dead port 1/2 on $mux $procmux$102413. + dead port 1/2 on $mux $procmux$102416. + dead port 1/2 on $mux $procmux$102419. + dead port 1/2 on $mux $procmux$102422. + dead port 1/2 on $mux $procmux$102425. + dead port 1/2 on $mux $procmux$102428. + dead port 1/2 on $mux $procmux$102431. + dead port 1/2 on $mux $procmux$102434. + dead port 2/2 on $mux $procmux$102437. + dead port 2/2 on $mux $procmux$102443. + dead port 1/2 on $mux $procmux$102446. + dead port 1/2 on $mux $procmux$102449. + dead port 1/2 on $mux $procmux$102452. + dead port 1/2 on $mux $procmux$102455. + dead port 1/2 on $mux $procmux$102458. + dead port 1/2 on $mux $procmux$102461. + dead port 1/2 on $mux $procmux$102464. + dead port 1/2 on $mux $procmux$102467. + dead port 1/2 on $mux $procmux$102470. + dead port 1/2 on $mux $procmux$102473. + dead port 1/2 on $mux $procmux$102476. + dead port 2/2 on $mux $procmux$102479. + dead port 2/2 on $mux $procmux$102569. + dead port 1/2 on $mux $procmux$102572. + dead port 1/2 on $mux $procmux$102575. + dead port 1/2 on $mux $procmux$102578. + dead port 1/2 on $mux $procmux$102581. + dead port 1/2 on $mux $procmux$102584. + dead port 1/2 on $mux $procmux$102587. + dead port 1/2 on $mux $procmux$102590. + dead port 1/2 on $mux $procmux$102593. + dead port 1/2 on $mux $procmux$102596. + dead port 1/2 on $mux $procmux$102599. + dead port 1/2 on $mux $procmux$102602. + dead port 2/2 on $mux $procmux$102605. + dead port 2/2 on $mux $procmux$102611. + dead port 1/2 on $mux $procmux$102614. + dead port 1/2 on $mux $procmux$102617. + dead port 1/2 on $mux $procmux$102620. + dead port 1/2 on $mux $procmux$102623. + dead port 1/2 on $mux $procmux$102626. + dead port 1/2 on $mux $procmux$102629. + dead port 1/2 on $mux $procmux$102632. + dead port 1/2 on $mux $procmux$102635. + dead port 1/2 on $mux $procmux$102638. + dead port 1/2 on $mux $procmux$102641. + dead port 1/2 on $mux $procmux$102644. + dead port 2/2 on $mux $procmux$102647. + dead port 2/2 on $mux $procmux$102653. + dead port 1/2 on $mux $procmux$102656. + dead port 1/2 on $mux $procmux$102659. + dead port 1/2 on $mux $procmux$102662. + dead port 1/2 on $mux $procmux$102665. + dead port 1/2 on $mux $procmux$102668. + dead port 1/2 on $mux $procmux$102671. + dead port 1/2 on $mux $procmux$102674. + dead port 1/2 on $mux $procmux$102677. + dead port 1/2 on $mux $procmux$102680. + dead port 1/2 on $mux $procmux$102683. + dead port 1/2 on $mux $procmux$102686. + dead port 2/2 on $mux $procmux$102689. + dead port 2/2 on $mux $procmux$102695. + dead port 1/2 on $mux $procmux$102698. + dead port 1/2 on $mux $procmux$102701. + dead port 1/2 on $mux $procmux$102704. + dead port 1/2 on $mux $procmux$102707. + dead port 1/2 on $mux $procmux$102710. + dead port 1/2 on $mux $procmux$102713. + dead port 1/2 on $mux $procmux$102716. + dead port 1/2 on $mux $procmux$102719. + dead port 1/2 on $mux $procmux$102722. + dead port 1/2 on $mux $procmux$102725. + dead port 1/2 on $mux $procmux$102728. + dead port 2/2 on $mux $procmux$102731. + dead port 2/2 on $mux $procmux$102737. + dead port 1/2 on $mux $procmux$102740. + dead port 1/2 on $mux $procmux$102743. + dead port 1/2 on $mux $procmux$102746. + dead port 1/2 on $mux $procmux$102749. + dead port 1/2 on $mux $procmux$102752. + dead port 1/2 on $mux $procmux$102755. + dead port 1/2 on $mux $procmux$102758. + dead port 1/2 on $mux $procmux$102761. + dead port 1/2 on $mux $procmux$102764. + dead port 1/2 on $mux $procmux$102767. + dead port 1/2 on $mux $procmux$102770. + dead port 2/2 on $mux $procmux$102773. + dead port 2/2 on $mux $procmux$102779. + dead port 1/2 on $mux $procmux$102782. + dead port 1/2 on $mux $procmux$102785. + dead port 1/2 on $mux $procmux$102788. + dead port 1/2 on $mux $procmux$102791. + dead port 1/2 on $mux $procmux$102794. + dead port 1/2 on $mux $procmux$102797. + dead port 1/2 on $mux $procmux$102800. + dead port 1/2 on $mux $procmux$102803. + dead port 1/2 on $mux $procmux$102806. + dead port 1/2 on $mux $procmux$102809. + dead port 1/2 on $mux $procmux$102812. + dead port 2/2 on $mux $procmux$102815. + dead port 2/2 on $mux $procmux$102821. + dead port 1/2 on $mux $procmux$102824. + dead port 1/2 on $mux $procmux$102827. + dead port 1/2 on $mux $procmux$102830. + dead port 1/2 on $mux $procmux$102833. + dead port 1/2 on $mux $procmux$102836. + dead port 1/2 on $mux $procmux$102839. + dead port 1/2 on $mux $procmux$102842. + dead port 1/2 on $mux $procmux$102845. + dead port 1/2 on $mux $procmux$102848. + dead port 1/2 on $mux $procmux$102851. + dead port 1/2 on $mux $procmux$102854. + dead port 2/2 on $mux $procmux$102857. + dead port 2/2 on $mux $procmux$102947. + dead port 1/2 on $mux $procmux$102950. + dead port 1/2 on $mux $procmux$102953. + dead port 1/2 on $mux $procmux$102956. + dead port 1/2 on $mux $procmux$102959. + dead port 1/2 on $mux $procmux$102962. + dead port 1/2 on $mux $procmux$102965. + dead port 1/2 on $mux $procmux$102968. + dead port 1/2 on $mux $procmux$102971. + dead port 1/2 on $mux $procmux$102974. + dead port 1/2 on $mux $procmux$102977. + dead port 1/2 on $mux $procmux$102980. + dead port 2/2 on $mux $procmux$102983. + dead port 2/2 on $mux $procmux$102989. + dead port 1/2 on $mux $procmux$102992. + dead port 1/2 on $mux $procmux$102995. + dead port 1/2 on $mux $procmux$102998. + dead port 1/2 on $mux $procmux$103001. + dead port 1/2 on $mux $procmux$103004. + dead port 1/2 on $mux $procmux$103007. + dead port 1/2 on $mux $procmux$103010. + dead port 1/2 on $mux $procmux$103013. + dead port 1/2 on $mux $procmux$103016. + dead port 1/2 on $mux $procmux$103019. + dead port 1/2 on $mux $procmux$103022. + dead port 2/2 on $mux $procmux$103025. + dead port 2/2 on $mux $procmux$103031. + dead port 1/2 on $mux $procmux$103034. + dead port 1/2 on $mux $procmux$103037. + dead port 1/2 on $mux $procmux$103040. + dead port 1/2 on $mux $procmux$103043. + dead port 1/2 on $mux $procmux$103046. + dead port 1/2 on $mux $procmux$103049. + dead port 1/2 on $mux $procmux$103052. + dead port 1/2 on $mux $procmux$103055. + dead port 1/2 on $mux $procmux$103058. + dead port 1/2 on $mux $procmux$103061. + dead port 1/2 on $mux $procmux$103064. + dead port 2/2 on $mux $procmux$103067. + dead port 2/2 on $mux $procmux$103073. + dead port 1/2 on $mux $procmux$103076. + dead port 1/2 on $mux $procmux$103079. + dead port 1/2 on $mux $procmux$103082. + dead port 1/2 on $mux $procmux$103085. + dead port 1/2 on $mux $procmux$103088. + dead port 1/2 on $mux $procmux$103091. + dead port 1/2 on $mux $procmux$103094. + dead port 1/2 on $mux $procmux$103097. + dead port 1/2 on $mux $procmux$103100. + dead port 1/2 on $mux $procmux$103103. + dead port 1/2 on $mux $procmux$103106. + dead port 2/2 on $mux $procmux$103109. + dead port 2/2 on $mux $procmux$103115. + dead port 1/2 on $mux $procmux$103118. + dead port 1/2 on $mux $procmux$103121. + dead port 1/2 on $mux $procmux$103124. + dead port 1/2 on $mux $procmux$103127. + dead port 1/2 on $mux $procmux$103130. + dead port 1/2 on $mux $procmux$103133. + dead port 1/2 on $mux $procmux$103136. + dead port 1/2 on $mux $procmux$103139. + dead port 1/2 on $mux $procmux$103142. + dead port 1/2 on $mux $procmux$103145. + dead port 1/2 on $mux $procmux$103148. + dead port 2/2 on $mux $procmux$103151. + dead port 2/2 on $mux $procmux$103157. + dead port 1/2 on $mux $procmux$103160. + dead port 1/2 on $mux $procmux$103163. + dead port 1/2 on $mux $procmux$103166. + dead port 1/2 on $mux $procmux$103169. + dead port 1/2 on $mux $procmux$103172. + dead port 1/2 on $mux $procmux$103175. + dead port 1/2 on $mux $procmux$103178. + dead port 1/2 on $mux $procmux$103181. + dead port 1/2 on $mux $procmux$103184. + dead port 1/2 on $mux $procmux$103187. + dead port 1/2 on $mux $procmux$103190. + dead port 2/2 on $mux $procmux$103193. + dead port 2/2 on $mux $procmux$103199. + dead port 1/2 on $mux $procmux$103202. + dead port 1/2 on $mux $procmux$103205. + dead port 1/2 on $mux $procmux$103208. + dead port 1/2 on $mux $procmux$103211. + dead port 1/2 on $mux $procmux$103214. + dead port 1/2 on $mux $procmux$103217. + dead port 1/2 on $mux $procmux$103220. + dead port 1/2 on $mux $procmux$103223. + dead port 1/2 on $mux $procmux$103226. + dead port 1/2 on $mux $procmux$103229. + dead port 1/2 on $mux $procmux$103232. + dead port 2/2 on $mux $procmux$103235. + dead port 2/2 on $mux $procmux$103241. + dead port 1/2 on $mux $procmux$103244. + dead port 1/2 on $mux $procmux$103247. + dead port 1/2 on $mux $procmux$103250. + dead port 1/2 on $mux $procmux$103253. + dead port 1/2 on $mux $procmux$103256. + dead port 1/2 on $mux $procmux$103259. + dead port 1/2 on $mux $procmux$103262. + dead port 1/2 on $mux $procmux$103265. + dead port 1/2 on $mux $procmux$103268. + dead port 1/2 on $mux $procmux$103271. + dead port 1/2 on $mux $procmux$103274. + dead port 2/2 on $mux $procmux$103277. + dead port 2/2 on $mux $procmux$103283. + dead port 1/2 on $mux $procmux$103286. + dead port 1/2 on $mux $procmux$103289. + dead port 1/2 on $mux $procmux$103292. + dead port 1/2 on $mux $procmux$103295. + dead port 1/2 on $mux $procmux$103298. + dead port 1/2 on $mux $procmux$103301. + dead port 1/2 on $mux $procmux$103304. + dead port 1/2 on $mux $procmux$103307. + dead port 1/2 on $mux $procmux$103310. + dead port 1/2 on $mux $procmux$103313. + dead port 1/2 on $mux $procmux$103316. + dead port 2/2 on $mux $procmux$103319. + dead port 2/2 on $mux $procmux$103325. + dead port 1/2 on $mux $procmux$103328. + dead port 1/2 on $mux $procmux$103331. + dead port 1/2 on $mux $procmux$103334. + dead port 1/2 on $mux $procmux$103337. + dead port 1/2 on $mux $procmux$103340. + dead port 1/2 on $mux $procmux$103343. + dead port 1/2 on $mux $procmux$103346. + dead port 1/2 on $mux $procmux$103349. + dead port 1/2 on $mux $procmux$103352. + dead port 1/2 on $mux $procmux$103355. + dead port 1/2 on $mux $procmux$103358. + dead port 2/2 on $mux $procmux$103361. + dead port 2/2 on $mux $procmux$103409. + dead port 1/2 on $mux $procmux$103412. + dead port 1/2 on $mux $procmux$103415. + dead port 1/2 on $mux $procmux$103418. + dead port 1/2 on $mux $procmux$103421. + dead port 1/2 on $mux $procmux$103424. + dead port 1/2 on $mux $procmux$103427. + dead port 1/2 on $mux $procmux$103430. + dead port 1/2 on $mux $procmux$103433. + dead port 1/2 on $mux $procmux$103436. + dead port 1/2 on $mux $procmux$103439. + dead port 1/2 on $mux $procmux$103442. + dead port 2/2 on $mux $procmux$103445. + dead port 2/2 on $mux $procmux$103451. + dead port 1/2 on $mux $procmux$103454. + dead port 1/2 on $mux $procmux$103457. + dead port 1/2 on $mux $procmux$103460. + dead port 1/2 on $mux $procmux$103463. + dead port 1/2 on $mux $procmux$103466. + dead port 1/2 on $mux $procmux$103469. + dead port 1/2 on $mux $procmux$103472. + dead port 1/2 on $mux $procmux$103475. + dead port 1/2 on $mux $procmux$103478. + dead port 1/2 on $mux $procmux$103481. + dead port 1/2 on $mux $procmux$103484. + dead port 2/2 on $mux $procmux$103487. + dead port 2/2 on $mux $procmux$103493. + dead port 1/2 on $mux $procmux$103496. + dead port 1/2 on $mux $procmux$103499. + dead port 1/2 on $mux $procmux$103502. + dead port 1/2 on $mux $procmux$103505. + dead port 1/2 on $mux $procmux$103508. + dead port 1/2 on $mux $procmux$103511. + dead port 1/2 on $mux $procmux$103514. + dead port 1/2 on $mux $procmux$103517. + dead port 1/2 on $mux $procmux$103520. + dead port 1/2 on $mux $procmux$103523. + dead port 1/2 on $mux $procmux$103526. + dead port 2/2 on $mux $procmux$103529. + dead port 2/2 on $mux $procmux$103661. + dead port 1/2 on $mux $procmux$103664. + dead port 1/2 on $mux $procmux$103667. + dead port 1/2 on $mux $procmux$103670. + dead port 1/2 on $mux $procmux$103673. + dead port 1/2 on $mux $procmux$103676. + dead port 1/2 on $mux $procmux$103679. + dead port 1/2 on $mux $procmux$103682. + dead port 1/2 on $mux $procmux$103685. + dead port 1/2 on $mux $procmux$103688. + dead port 1/2 on $mux $procmux$103691. + dead port 1/2 on $mux $procmux$103694. + dead port 2/2 on $mux $procmux$103697. + dead port 2/2 on $mux $procmux$103703. + dead port 1/2 on $mux $procmux$103706. + dead port 1/2 on $mux $procmux$103709. + dead port 1/2 on $mux $procmux$103712. + dead port 1/2 on $mux $procmux$103715. + dead port 1/2 on $mux $procmux$103718. + dead port 1/2 on $mux $procmux$103721. + dead port 1/2 on $mux $procmux$103724. + dead port 1/2 on $mux $procmux$103727. + dead port 1/2 on $mux $procmux$103730. + dead port 1/2 on $mux $procmux$103733. + dead port 1/2 on $mux $procmux$103736. + dead port 2/2 on $mux $procmux$103739. + dead port 2/2 on $mux $procmux$103745. + dead port 1/2 on $mux $procmux$103748. + dead port 1/2 on $mux $procmux$103751. + dead port 1/2 on $mux $procmux$103754. + dead port 1/2 on $mux $procmux$103757. + dead port 1/2 on $mux $procmux$103760. + dead port 1/2 on $mux $procmux$103763. + dead port 1/2 on $mux $procmux$103766. + dead port 1/2 on $mux $procmux$103769. + dead port 1/2 on $mux $procmux$103772. + dead port 1/2 on $mux $procmux$103775. + dead port 1/2 on $mux $procmux$103778. + dead port 2/2 on $mux $procmux$103781. + dead port 2/2 on $mux $procmux$103829. + dead port 1/2 on $mux $procmux$103832. + dead port 1/2 on $mux $procmux$103835. + dead port 1/2 on $mux $procmux$103838. + dead port 1/2 on $mux $procmux$103841. + dead port 1/2 on $mux $procmux$103844. + dead port 1/2 on $mux $procmux$103847. + dead port 1/2 on $mux $procmux$103850. + dead port 1/2 on $mux $procmux$103853. + dead port 1/2 on $mux $procmux$103856. + dead port 1/2 on $mux $procmux$103859. + dead port 1/2 on $mux $procmux$103862. + dead port 2/2 on $mux $procmux$103865. + dead port 2/2 on $mux $procmux$103871. + dead port 1/2 on $mux $procmux$103874. + dead port 1/2 on $mux $procmux$103877. + dead port 1/2 on $mux $procmux$103880. + dead port 1/2 on $mux $procmux$103883. + dead port 1/2 on $mux $procmux$103886. + dead port 1/2 on $mux $procmux$103889. + dead port 1/2 on $mux $procmux$103892. + dead port 1/2 on $mux $procmux$103895. + dead port 1/2 on $mux $procmux$103898. + dead port 1/2 on $mux $procmux$103901. + dead port 1/2 on $mux $procmux$103904. + dead port 2/2 on $mux $procmux$103907. + dead port 1/2 on $mux $procmux$106721. + dead port 1/2 on $mux $procmux$106724. + dead port 1/2 on $mux $procmux$106727. + dead port 1/2 on $mux $procmux$106730. + dead port 1/2 on $mux $procmux$106733. + dead port 1/2 on $mux $procmux$106736. + dead port 1/2 on $mux $procmux$106739. + dead port 1/2 on $mux $procmux$106742. + dead port 1/2 on $mux $procmux$106745. + dead port 1/2 on $mux $procmux$106748. + dead port 1/2 on $mux $procmux$106751. + dead port 2/2 on $mux $procmux$106754. + dead port 1/2 on $mux $procmux$106760. + dead port 1/2 on $mux $procmux$106763. + dead port 1/2 on $mux $procmux$106766. + dead port 1/2 on $mux $procmux$106769. + dead port 1/2 on $mux $procmux$106772. + dead port 1/2 on $mux $procmux$106775. + dead port 1/2 on $mux $procmux$106778. + dead port 1/2 on $mux $procmux$106781. + dead port 1/2 on $mux $procmux$106784. + dead port 1/2 on $mux $procmux$106787. + dead port 1/2 on $mux $procmux$106790. + dead port 2/2 on $mux $procmux$106793. + dead port 1/2 on $mux $procmux$106877. + dead port 1/2 on $mux $procmux$106880. + dead port 1/2 on $mux $procmux$106883. + dead port 1/2 on $mux $procmux$106886. + dead port 1/2 on $mux $procmux$106889. + dead port 1/2 on $mux $procmux$106892. + dead port 1/2 on $mux $procmux$106895. + dead port 1/2 on $mux $procmux$106898. + dead port 1/2 on $mux $procmux$106901. + dead port 1/2 on $mux $procmux$106904. + dead port 1/2 on $mux $procmux$106907. + dead port 2/2 on $mux $procmux$106910. + dead port 1/2 on $mux $procmux$106916. + dead port 1/2 on $mux $procmux$106919. + dead port 1/2 on $mux $procmux$106922. + dead port 1/2 on $mux $procmux$106925. + dead port 1/2 on $mux $procmux$106928. + dead port 1/2 on $mux $procmux$106931. + dead port 1/2 on $mux $procmux$106934. + dead port 1/2 on $mux $procmux$106937. + dead port 1/2 on $mux $procmux$106940. + dead port 1/2 on $mux $procmux$106943. + dead port 1/2 on $mux $procmux$106946. + dead port 2/2 on $mux $procmux$106949. + dead port 1/2 on $mux $procmux$106955. + dead port 1/2 on $mux $procmux$106958. + dead port 1/2 on $mux $procmux$106961. + dead port 1/2 on $mux $procmux$106964. + dead port 1/2 on $mux $procmux$106967. + dead port 1/2 on $mux $procmux$106970. + dead port 1/2 on $mux $procmux$106973. + dead port 1/2 on $mux $procmux$106976. + dead port 1/2 on $mux $procmux$106979. + dead port 1/2 on $mux $procmux$106982. + dead port 1/2 on $mux $procmux$106985. + dead port 2/2 on $mux $procmux$106988. + dead port 1/2 on $mux $procmux$106994. + dead port 1/2 on $mux $procmux$106997. + dead port 1/2 on $mux $procmux$107000. + dead port 1/2 on $mux $procmux$107003. + dead port 1/2 on $mux $procmux$107006. + dead port 1/2 on $mux $procmux$107009. + dead port 1/2 on $mux $procmux$107012. + dead port 1/2 on $mux $procmux$107015. + dead port 1/2 on $mux $procmux$107018. + dead port 1/2 on $mux $procmux$107021. + dead port 1/2 on $mux $procmux$107024. + dead port 2/2 on $mux $procmux$107027. + dead port 1/2 on $mux $procmux$107033. + dead port 1/2 on $mux $procmux$107036. + dead port 1/2 on $mux $procmux$107039. + dead port 1/2 on $mux $procmux$107042. + dead port 1/2 on $mux $procmux$107045. + dead port 1/2 on $mux $procmux$107048. + dead port 1/2 on $mux $procmux$107051. + dead port 1/2 on $mux $procmux$107054. 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on $mux $procmux$107135. + dead port 1/2 on $mux $procmux$107138. + dead port 1/2 on $mux $procmux$107141. + dead port 2/2 on $mux $procmux$107144. + dead port 1/2 on $mux $procmux$107228. + dead port 1/2 on $mux $procmux$107231. + dead port 1/2 on $mux $procmux$107234. + dead port 1/2 on $mux $procmux$107237. + dead port 1/2 on $mux $procmux$107240. + dead port 1/2 on $mux $procmux$107243. + dead port 1/2 on $mux $procmux$107246. + dead port 1/2 on $mux $procmux$107249. + dead port 1/2 on $mux $procmux$107252. + dead port 1/2 on $mux $procmux$107255. + dead port 1/2 on $mux $procmux$107258. + dead port 2/2 on $mux $procmux$107261. + dead port 1/2 on $mux $procmux$107267. + dead port 1/2 on $mux $procmux$107270. + dead port 1/2 on $mux $procmux$107273. + dead port 1/2 on $mux $procmux$107276. + dead port 1/2 on $mux $procmux$107279. + dead port 1/2 on $mux $procmux$107282. + dead port 1/2 on $mux $procmux$107285. + dead port 1/2 on $mux $procmux$107288. + dead port 1/2 on $mux $procmux$107291. + dead port 1/2 on $mux $procmux$107294. + dead port 1/2 on $mux $procmux$107297. + dead port 2/2 on $mux $procmux$107300. + dead port 1/2 on $mux $procmux$107306. + dead port 1/2 on $mux $procmux$107309. + dead port 1/2 on $mux $procmux$107312. + dead port 1/2 on $mux $procmux$107315. + dead port 1/2 on $mux $procmux$107318. + dead port 1/2 on $mux $procmux$107321. + dead port 1/2 on $mux $procmux$107324. + dead port 1/2 on $mux $procmux$107327. + dead port 1/2 on $mux $procmux$107330. + dead port 1/2 on $mux $procmux$107333. + dead port 1/2 on $mux $procmux$107336. + dead port 2/2 on $mux $procmux$107339. + dead port 1/2 on $mux $procmux$107345. + dead port 1/2 on $mux $procmux$107348. + dead port 1/2 on $mux $procmux$107351. + dead port 1/2 on $mux $procmux$107354. + dead port 1/2 on $mux $procmux$107357. + dead port 1/2 on $mux $procmux$107360. + dead port 1/2 on $mux $procmux$107363. + dead port 1/2 on $mux $procmux$107366. + dead port 1/2 on $mux $procmux$107369. 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on $mux $procmux$107450. + dead port 1/2 on $mux $procmux$107453. + dead port 2/2 on $mux $procmux$107456. + dead port 1/2 on $mux $procmux$107462. + dead port 1/2 on $mux $procmux$107465. + dead port 1/2 on $mux $procmux$107468. + dead port 1/2 on $mux $procmux$107471. + dead port 1/2 on $mux $procmux$107474. + dead port 1/2 on $mux $procmux$107477. + dead port 1/2 on $mux $procmux$107480. + dead port 1/2 on $mux $procmux$107483. + dead port 1/2 on $mux $procmux$107486. + dead port 1/2 on $mux $procmux$107489. + dead port 1/2 on $mux $procmux$107492. + dead port 2/2 on $mux $procmux$107495. + dead port 1/2 on $mux $procmux$107501. + dead port 1/2 on $mux $procmux$107504. + dead port 1/2 on $mux $procmux$107507. + dead port 1/2 on $mux $procmux$107510. + dead port 1/2 on $mux $procmux$107513. + dead port 1/2 on $mux $procmux$107516. + dead port 1/2 on $mux $procmux$107519. + dead port 1/2 on $mux $procmux$107522. + dead port 1/2 on $mux $procmux$107525. + dead port 1/2 on $mux $procmux$107528. + dead port 1/2 on $mux $procmux$107531. + dead port 2/2 on $mux $procmux$107534. + dead port 1/2 on $mux $procmux$107540. + dead port 1/2 on $mux $procmux$107543. + dead port 1/2 on $mux $procmux$107546. + dead port 1/2 on $mux $procmux$107549. + dead port 1/2 on $mux $procmux$107552. + dead port 1/2 on $mux $procmux$107555. + dead port 1/2 on $mux $procmux$107558. + dead port 1/2 on $mux $procmux$107561. + dead port 1/2 on $mux $procmux$107564. + dead port 1/2 on $mux $procmux$107567. + dead port 1/2 on $mux $procmux$107570. + dead port 2/2 on $mux $procmux$107573. + dead port 1/2 on $mux $procmux$107579. + dead port 1/2 on $mux $procmux$107582. + dead port 1/2 on $mux $procmux$107585. + dead port 1/2 on $mux $procmux$107588. + dead port 1/2 on $mux $procmux$107591. + dead port 1/2 on $mux $procmux$107594. + dead port 1/2 on $mux $procmux$107597. + dead port 1/2 on $mux $procmux$107600. + dead port 1/2 on $mux $procmux$107603. + dead port 1/2 on $mux $procmux$107606. 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on $mux $procmux$107726. + dead port 2/2 on $mux $procmux$107729. + dead port 1/2 on $mux $procmux$107735. + dead port 1/2 on $mux $procmux$107738. + dead port 1/2 on $mux $procmux$107741. + dead port 1/2 on $mux $procmux$107744. + dead port 1/2 on $mux $procmux$107747. + dead port 1/2 on $mux $procmux$107750. + dead port 1/2 on $mux $procmux$107753. + dead port 1/2 on $mux $procmux$107756. + dead port 1/2 on $mux $procmux$107759. + dead port 1/2 on $mux $procmux$107762. + dead port 1/2 on $mux $procmux$107765. + dead port 2/2 on $mux $procmux$107768. + dead port 1/2 on $mux $procmux$107891. + dead port 1/2 on $mux $procmux$107894. + dead port 1/2 on $mux $procmux$107897. + dead port 1/2 on $mux $procmux$107900. + dead port 1/2 on $mux $procmux$107903. + dead port 1/2 on $mux $procmux$107906. + dead port 1/2 on $mux $procmux$107909. + dead port 1/2 on $mux $procmux$107912. + dead port 1/2 on $mux $procmux$107915. + dead port 1/2 on $mux $procmux$107918. + dead port 1/2 on $mux $procmux$107921. + dead port 2/2 on $mux $procmux$107924. + dead port 1/2 on $mux $procmux$107930. + dead port 1/2 on $mux $procmux$107933. + dead port 1/2 on $mux $procmux$107936. + dead port 1/2 on $mux $procmux$107939. + dead port 1/2 on $mux $procmux$107942. + dead port 1/2 on $mux $procmux$107945. + dead port 1/2 on $mux $procmux$107948. + dead port 1/2 on $mux $procmux$107951. + dead port 1/2 on $mux $procmux$107954. + dead port 1/2 on $mux $procmux$107957. + dead port 1/2 on $mux $procmux$107960. + dead port 2/2 on $mux $procmux$107963. + dead port 1/2 on $mux $procmux$107969. + dead port 1/2 on $mux $procmux$107972. + dead port 1/2 on $mux $procmux$107975. + dead port 1/2 on $mux $procmux$107978. + dead port 1/2 on $mux $procmux$107981. + dead port 1/2 on $mux $procmux$107984. + dead port 1/2 on $mux $procmux$107987. + dead port 1/2 on $mux $procmux$107990. + dead port 1/2 on $mux $procmux$107993. + dead port 1/2 on $mux $procmux$107996. + dead port 1/2 on $mux $procmux$107999. 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on $mux $procmux$108119. + dead port 1/2 on $mux $procmux$108123. + dead port 1/2 on $mux $procmux$108126. + dead port 1/2 on $mux $procmux$108129. + dead port 1/2 on $mux $procmux$108132. + dead port 2/2 on $mux $procmux$108134. + dead port 1/2 on $mux $procmux$108137. + dead port 1/2 on $mux $procmux$108140. + dead port 1/2 on $mux $procmux$108143. + dead port 1/2 on $mux $procmux$108146. + dead port 1/2 on $mux $procmux$108149. + dead port 1/2 on $mux $procmux$108152. + dead port 1/2 on $mux $procmux$108155. + dead port 1/2 on $mux $procmux$108158. + dead port 1/2 on $mux $procmux$108161. + dead port 1/2 on $mux $procmux$108164. + dead port 2/2 on $mux $procmux$108167. + dead port 1/2 on $mux $procmux$108171. + dead port 1/2 on $mux $procmux$108174. + dead port 1/2 on $mux $procmux$108177. + dead port 1/2 on $mux $procmux$108180. + dead port 2/2 on $mux $procmux$108182. + dead port 1/2 on $mux $procmux$108185. + dead port 1/2 on $mux $procmux$108188. + dead port 1/2 on $mux $procmux$108191. + dead port 1/2 on $mux $procmux$108194. + dead port 1/2 on $mux $procmux$108197. + dead port 1/2 on $mux $procmux$108200. + dead port 1/2 on $mux $procmux$108203. + dead port 1/2 on $mux $procmux$108206. + dead port 1/2 on $mux $procmux$108209. + dead port 1/2 on $mux $procmux$108212. + dead port 2/2 on $mux $procmux$108215. + dead port 1/2 on $mux $procmux$108219. + dead port 1/2 on $mux $procmux$108222. + dead port 1/2 on $mux $procmux$108225. + dead port 1/2 on $mux $procmux$108228. + dead port 2/2 on $mux $procmux$108230. + dead port 1/2 on $mux $procmux$108233. + dead port 1/2 on $mux $procmux$108236. + dead port 1/2 on $mux $procmux$108239. + dead port 1/2 on $mux $procmux$108242. + dead port 1/2 on $mux $procmux$108245. + dead port 1/2 on $mux $procmux$108248. + dead port 1/2 on $mux $procmux$108251. + dead port 1/2 on $mux $procmux$108254. + dead port 1/2 on $mux $procmux$108257. + dead port 1/2 on $mux $procmux$108260. + dead port 2/2 on $mux $procmux$108263. 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on $mux $procmux$108344. + dead port 1/2 on $mux $procmux$108347. + dead port 1/2 on $mux $procmux$108350. + dead port 1/2 on $mux $procmux$108353. + dead port 1/2 on $mux $procmux$108356. + dead port 2/2 on $mux $procmux$108359. + dead port 1/2 on $mux $procmux$108366. + dead port 1/2 on $mux $procmux$108369. + dead port 1/2 on $mux $procmux$108372. + dead port 2/2 on $mux $procmux$108374. + dead port 1/2 on $mux $procmux$108377. + dead port 1/2 on $mux $procmux$108380. + dead port 1/2 on $mux $procmux$108383. + dead port 1/2 on $mux $procmux$108386. + dead port 1/2 on $mux $procmux$108389. + dead port 1/2 on $mux $procmux$108392. + dead port 1/2 on $mux $procmux$108395. + dead port 1/2 on $mux $procmux$108398. + dead port 1/2 on $mux $procmux$108401. + dead port 1/2 on $mux $procmux$108404. + dead port 2/2 on $mux $procmux$108407. + dead port 1/2 on $mux $procmux$108414. + dead port 1/2 on $mux $procmux$108417. + dead port 1/2 on $mux $procmux$108420. + dead port 2/2 on $mux $procmux$108422. + dead port 1/2 on $mux $procmux$108425. + dead port 1/2 on $mux $procmux$108428. + dead port 1/2 on $mux $procmux$108431. + dead port 1/2 on $mux $procmux$108434. + dead port 1/2 on $mux $procmux$108437. + dead port 1/2 on $mux $procmux$108440. + dead port 1/2 on $mux $procmux$108443. + dead port 1/2 on $mux $procmux$108446. + dead port 1/2 on $mux $procmux$108449. + dead port 1/2 on $mux $procmux$108452. + dead port 2/2 on $mux $procmux$108455. + dead port 1/2 on $mux $procmux$108462. + dead port 1/2 on $mux $procmux$108465. + dead port 1/2 on $mux $procmux$108468. + dead port 2/2 on $mux $procmux$108470. + dead port 1/2 on $mux $procmux$108473. + dead port 1/2 on $mux $procmux$108476. + dead port 1/2 on $mux $procmux$108479. + dead port 1/2 on $mux $procmux$108482. + dead port 1/2 on $mux $procmux$108485. + dead port 1/2 on $mux $procmux$108488. + dead port 1/2 on $mux $procmux$108491. + dead port 1/2 on $mux $procmux$108494. + dead port 1/2 on $mux $procmux$108497. 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on $mux $procmux$108578. + dead port 1/2 on $mux $procmux$108581. + dead port 1/2 on $mux $procmux$108584. + dead port 1/2 on $mux $procmux$108587. + dead port 1/2 on $mux $procmux$108590. + dead port 1/2 on $mux $procmux$108593. + dead port 1/2 on $mux $procmux$108596. + dead port 2/2 on $mux $procmux$108599. + dead port 1/2 on $mux $procmux$108606. + dead port 1/2 on $mux $procmux$108609. + dead port 1/2 on $mux $procmux$108612. + dead port 2/2 on $mux $procmux$108614. + dead port 1/2 on $mux $procmux$108617. + dead port 1/2 on $mux $procmux$108620. + dead port 1/2 on $mux $procmux$108623. + dead port 1/2 on $mux $procmux$108626. + dead port 1/2 on $mux $procmux$108629. + dead port 1/2 on $mux $procmux$108632. + dead port 1/2 on $mux $procmux$108635. + dead port 1/2 on $mux $procmux$108638. + dead port 1/2 on $mux $procmux$108641. + dead port 1/2 on $mux $procmux$108644. + dead port 2/2 on $mux $procmux$108647. + dead port 1/2 on $mux $procmux$108654. + dead port 1/2 on $mux $procmux$108657. + dead port 1/2 on $mux $procmux$108660. + dead port 2/2 on $mux $procmux$108662. + dead port 1/2 on $mux $procmux$108665. + dead port 1/2 on $mux $procmux$108668. + dead port 1/2 on $mux $procmux$108671. + dead port 1/2 on $mux $procmux$108674. + dead port 1/2 on $mux $procmux$108677. + dead port 1/2 on $mux $procmux$108680. + dead port 1/2 on $mux $procmux$108683. + dead port 1/2 on $mux $procmux$108686. + dead port 1/2 on $mux $procmux$108689. + dead port 1/2 on $mux $procmux$108692. + dead port 2/2 on $mux $procmux$108695. + dead port 1/2 on $mux $procmux$108702. + dead port 1/2 on $mux $procmux$108705. + dead port 1/2 on $mux $procmux$108708. + dead port 2/2 on $mux $procmux$108710. + dead port 1/2 on $mux $procmux$108713. + dead port 1/2 on $mux $procmux$108716. + dead port 1/2 on $mux $procmux$108719. + dead port 1/2 on $mux $procmux$108722. + dead port 1/2 on $mux $procmux$108725. + dead port 1/2 on $mux $procmux$108728. + dead port 1/2 on $mux $procmux$108731. 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on $mux $procmux$108809. + dead port 1/2 on $mux $procmux$108812. + dead port 1/2 on $mux $procmux$108815. + dead port 1/2 on $mux $procmux$108818. + dead port 1/2 on $mux $procmux$108821. + dead port 1/2 on $mux $procmux$108824. + dead port 1/2 on $mux $procmux$108827. + dead port 1/2 on $mux $procmux$108830. + dead port 2/2 on $mux $procmux$108833. + dead port 2/2 on $mux $procmux$108837. + dead port 1/2 on $mux $procmux$108840. + dead port 1/2 on $mux $procmux$108843. + dead port 2/2 on $mux $procmux$108845. + dead port 1/2 on $mux $procmux$108848. + dead port 1/2 on $mux $procmux$108851. + dead port 1/2 on $mux $procmux$108854. + dead port 1/2 on $mux $procmux$108857. + dead port 1/2 on $mux $procmux$108860. + dead port 1/2 on $mux $procmux$108863. + dead port 1/2 on $mux $procmux$108866. + dead port 1/2 on $mux $procmux$108869. + dead port 1/2 on $mux $procmux$108872. + dead port 1/2 on $mux $procmux$108875. + dead port 2/2 on $mux $procmux$108878. + dead port 1/2 on $mux $procmux$108885. + dead port 1/2 on $mux $procmux$108888. + dead port 2/2 on $mux $procmux$108890. + dead port 1/2 on $mux $procmux$108893. + dead port 1/2 on $mux $procmux$108896. + dead port 1/2 on $mux $procmux$108899. + dead port 1/2 on $mux $procmux$108902. + dead port 1/2 on $mux $procmux$108905. + dead port 1/2 on $mux $procmux$108908. + dead port 1/2 on $mux $procmux$108911. + dead port 1/2 on $mux $procmux$108914. + dead port 1/2 on $mux $procmux$108917. + dead port 1/2 on $mux $procmux$108920. + dead port 2/2 on $mux $procmux$108923. + dead port 1/2 on $mux $procmux$108930. + dead port 1/2 on $mux $procmux$108933. + dead port 2/2 on $mux $procmux$108935. + dead port 1/2 on $mux $procmux$108938. + dead port 1/2 on $mux $procmux$108941. + dead port 1/2 on $mux $procmux$108944. + dead port 1/2 on $mux $procmux$108947. + dead port 1/2 on $mux $procmux$108950. + dead port 1/2 on $mux $procmux$108953. + dead port 1/2 on $mux $procmux$108956. + dead port 1/2 on $mux $procmux$108959. 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on $mux $procmux$109037. + dead port 1/2 on $mux $procmux$109040. + dead port 1/2 on $mux $procmux$109043. + dead port 1/2 on $mux $procmux$109046. + dead port 1/2 on $mux $procmux$109049. + dead port 1/2 on $mux $procmux$109052. + dead port 1/2 on $mux $procmux$109055. + dead port 2/2 on $mux $procmux$109058. + dead port 1/2 on $mux $procmux$109065. + dead port 1/2 on $mux $procmux$109068. + dead port 2/2 on $mux $procmux$109070. + dead port 1/2 on $mux $procmux$109073. + dead port 1/2 on $mux $procmux$109076. + dead port 1/2 on $mux $procmux$109079. + dead port 1/2 on $mux $procmux$109082. + dead port 1/2 on $mux $procmux$109085. + dead port 1/2 on $mux $procmux$109088. + dead port 1/2 on $mux $procmux$109091. + dead port 1/2 on $mux $procmux$109094. + dead port 1/2 on $mux $procmux$109097. + dead port 1/2 on $mux $procmux$109100. + dead port 2/2 on $mux $procmux$109103. + dead port 1/2 on $mux $procmux$109110. + dead port 1/2 on $mux $procmux$109113. + dead port 2/2 on $mux $procmux$109115. + dead port 1/2 on $mux $procmux$109118. + dead port 1/2 on $mux $procmux$109121. + dead port 1/2 on $mux $procmux$109124. + dead port 1/2 on $mux $procmux$109127. + dead port 1/2 on $mux $procmux$109130. + dead port 1/2 on $mux $procmux$109133. + dead port 1/2 on $mux $procmux$109136. + dead port 1/2 on $mux $procmux$109139. + dead port 1/2 on $mux $procmux$109142. + dead port 1/2 on $mux $procmux$109145. + dead port 2/2 on $mux $procmux$109148. + dead port 1/2 on $mux $procmux$109155. + dead port 1/2 on $mux $procmux$109158. + dead port 2/2 on $mux $procmux$109160. + dead port 1/2 on $mux $procmux$109163. + dead port 1/2 on $mux $procmux$109166. + dead port 1/2 on $mux $procmux$109169. + dead port 1/2 on $mux $procmux$109172. + dead port 1/2 on $mux $procmux$109175. + dead port 1/2 on $mux $procmux$109178. + dead port 1/2 on $mux $procmux$109181. + dead port 1/2 on $mux $procmux$109184. + dead port 1/2 on $mux $procmux$109187. + dead port 1/2 on $mux $procmux$109190. + dead port 2/2 on $mux $procmux$109193. + dead port 1/2 on $mux $procmux$109245. + dead port 1/2 on $mux $procmux$109248. + dead port 2/2 on $mux $procmux$109250. + dead port 1/2 on $mux $procmux$109253. + dead port 1/2 on $mux $procmux$109256. + dead port 1/2 on $mux $procmux$109259. + dead port 1/2 on $mux $procmux$109262. + dead port 1/2 on $mux $procmux$109265. + dead port 1/2 on $mux $procmux$109268. + dead port 1/2 on $mux $procmux$109271. + dead port 1/2 on $mux $procmux$109274. + dead port 1/2 on $mux $procmux$109277. + dead port 1/2 on $mux $procmux$109280. + dead port 2/2 on $mux $procmux$109283. + dead port 1/2 on $mux $procmux$109290. + dead port 1/2 on $mux $procmux$109293. + dead port 2/2 on $mux $procmux$109295. + dead port 1/2 on $mux $procmux$109298. + dead port 1/2 on $mux $procmux$109301. + dead port 1/2 on $mux $procmux$109304. + dead port 1/2 on $mux $procmux$109307. + dead port 1/2 on $mux $procmux$109310. + dead port 1/2 on $mux $procmux$109313. + dead port 1/2 on $mux $procmux$109316. + dead port 1/2 on $mux $procmux$109319. + dead port 1/2 on $mux $procmux$109322. + dead port 1/2 on $mux $procmux$109325. + dead port 2/2 on $mux $procmux$109328. + dead port 1/2 on $mux $procmux$109713. + dead port 2/2 on $mux $procmux$109715. + dead port 1/2 on $mux $procmux$109718. + dead port 1/2 on $mux $procmux$109721. + dead port 1/2 on $mux $procmux$109724. + dead port 1/2 on $mux $procmux$109727. + dead port 1/2 on $mux $procmux$109730. + dead port 1/2 on $mux $procmux$109733. + dead port 1/2 on $mux $procmux$109736. + dead port 1/2 on $mux $procmux$109739. + dead port 1/2 on $mux $procmux$109742. + dead port 1/2 on $mux $procmux$109745. + dead port 2/2 on $mux $procmux$109748. + dead port 1/2 on $mux $procmux$109755. + dead port 2/2 on $mux $procmux$109757. + dead port 1/2 on $mux $procmux$109760. + dead port 1/2 on $mux $procmux$109763. + dead port 1/2 on $mux $procmux$109766. + dead port 1/2 on $mux $procmux$109769. + dead port 1/2 on $mux $procmux$109772. + dead port 1/2 on $mux $procmux$109775. + dead port 1/2 on $mux $procmux$109778. + dead port 1/2 on $mux $procmux$109781. + dead port 1/2 on $mux $procmux$109784. + dead port 1/2 on $mux $procmux$109787. + dead port 2/2 on $mux $procmux$109790. + dead port 1/2 on $mux $procmux$109881. + dead port 2/2 on $mux $procmux$109883. + dead port 1/2 on $mux $procmux$109886. + dead port 1/2 on $mux $procmux$109889. + dead port 1/2 on $mux $procmux$109892. + dead port 1/2 on $mux $procmux$109895. + dead port 1/2 on $mux $procmux$109898. + dead port 1/2 on $mux $procmux$109901. + dead port 1/2 on $mux $procmux$109904. + dead port 1/2 on $mux $procmux$109907. + dead port 1/2 on $mux $procmux$109910. + dead port 1/2 on $mux $procmux$109913. + dead port 2/2 on $mux $procmux$109916. + dead port 2/2 on $mux $procmux$110195. + dead port 1/2 on $mux $procmux$110198. + dead port 1/2 on $mux $procmux$110201. + dead port 1/2 on $mux $procmux$110204. + dead port 1/2 on $mux $procmux$110207. + dead port 1/2 on $mux $procmux$110210. + dead port 1/2 on $mux $procmux$110213. + dead port 1/2 on $mux $procmux$110216. + dead port 1/2 on $mux $procmux$110219. + dead port 1/2 on $mux $procmux$110222. + dead port 1/2 on $mux $procmux$110225. + dead port 2/2 on $mux $procmux$110228. + dead port 2/2 on $mux $procmux$110234. + dead port 1/2 on $mux $procmux$110237. + dead port 1/2 on $mux $procmux$110240. + dead port 1/2 on $mux $procmux$110243. + dead port 1/2 on $mux $procmux$110246. + dead port 1/2 on $mux $procmux$110249. + dead port 1/2 on $mux $procmux$110252. + dead port 1/2 on $mux $procmux$110255. + dead port 1/2 on $mux $procmux$110258. + dead port 1/2 on $mux $procmux$110261. + dead port 1/2 on $mux $procmux$110264. + dead port 2/2 on $mux $procmux$110267. + dead port 2/2 on $mux $procmux$110351. + dead port 1/2 on $mux $procmux$110354. + dead port 1/2 on $mux $procmux$110357. + dead port 1/2 on $mux $procmux$110360. + dead port 1/2 on $mux $procmux$110363. + dead port 1/2 on $mux $procmux$110366. + dead port 1/2 on $mux $procmux$110369. + dead port 1/2 on $mux $procmux$110372. + dead port 1/2 on $mux $procmux$110375. + dead port 1/2 on $mux $procmux$110378. + dead port 1/2 on $mux $procmux$110381. + dead port 2/2 on $mux $procmux$110384. + dead port 1/2 on $mux $procmux$110570. + dead port 1/2 on $mux $procmux$110573. + dead port 1/2 on $mux $procmux$110576. + dead port 1/2 on $mux $procmux$110579. + dead port 1/2 on $mux $procmux$110582. + dead port 1/2 on $mux $procmux$110585. + dead port 1/2 on $mux $procmux$110588. + dead port 1/2 on $mux $procmux$110591. + dead port 1/2 on $mux $procmux$110594. + dead port 1/2 on $mux $procmux$110597. + dead port 2/2 on $mux $procmux$110600. + dead port 1/2 on $mux $procmux$110606. + dead port 1/2 on $mux $procmux$110609. + dead port 1/2 on $mux $procmux$110612. + dead port 1/2 on $mux $procmux$110615. + dead port 1/2 on $mux $procmux$110618. + dead port 1/2 on $mux $procmux$110621. + dead port 1/2 on $mux $procmux$110624. + dead port 1/2 on $mux $procmux$110627. + dead port 1/2 on $mux $procmux$110630. + dead port 1/2 on $mux $procmux$110633. + dead port 2/2 on $mux $procmux$110636. + dead port 1/2 on $mux $procmux$110714. + dead port 1/2 on $mux $procmux$110717. + dead port 1/2 on $mux $procmux$110720. + dead port 1/2 on $mux $procmux$110723. + dead port 1/2 on $mux $procmux$110726. + dead port 1/2 on $mux $procmux$110729. + dead port 1/2 on $mux $procmux$110732. + dead port 1/2 on $mux $procmux$110735. + dead port 1/2 on $mux $procmux$110738. + dead port 1/2 on $mux $procmux$110741. + dead port 2/2 on $mux $procmux$110744. + dead port 1/2 on $mux $procmux$11284. + dead port 2/2 on $mux $procmux$11286. + dead port 1/2 on $mux $procmux$11289. + dead port 1/2 on $mux $procmux$11292. + dead port 1/2 on $mux $procmux$11295. + dead port 1/2 on $mux $procmux$11298. + dead port 1/2 on $mux $procmux$11301. + dead port 1/2 on $mux $procmux$11304. + dead port 1/2 on $mux $procmux$11307. + dead port 1/2 on $mux $procmux$11310. + dead port 1/2 on $mux $procmux$11313. + dead port 1/2 on $mux $procmux$11316. + dead port 1/2 on $mux $procmux$11319. + dead port 1/2 on $mux $procmux$11322. + dead port 1/2 on $mux $procmux$11325. + dead port 1/2 on $mux $procmux$11328. + dead port 1/2 on $mux $procmux$11331. + dead port 1/2 on $mux $procmux$11334. + dead port 1/2 on $mux $procmux$11337. + dead port 1/2 on $mux $procmux$113378. + dead port 1/2 on $mux $procmux$113381. + dead port 1/2 on $mux $procmux$113384. + dead port 1/2 on $mux $procmux$113387. + dead port 2/2 on $mux $procmux$11339. + dead port 1/2 on $mux $procmux$113390. + dead port 1/2 on $mux $procmux$113393. + dead port 1/2 on $mux $procmux$113396. + dead port 1/2 on $mux $procmux$113399. + dead port 1/2 on $mux $procmux$113402. + dead port 1/2 on $mux $procmux$113405. + dead port 2/2 on $mux $procmux$113408. + dead port 1/2 on $mux $procmux$113414. + dead port 1/2 on $mux $procmux$113417. + dead port 1/2 on $mux $procmux$11342. + dead port 1/2 on $mux $procmux$113420. + dead port 1/2 on $mux $procmux$113423. + dead port 1/2 on $mux $procmux$113426. + dead port 1/2 on $mux $procmux$113429. + dead port 1/2 on $mux $procmux$113432. + dead port 1/2 on $mux $procmux$113435. + dead port 1/2 on $mux $procmux$113438. + dead port 1/2 on $mux $procmux$113441. + dead port 2/2 on $mux $procmux$113444. + dead port 1/2 on $mux $procmux$11345. + dead port 1/2 on $mux $procmux$113450. + dead port 1/2 on $mux $procmux$113453. + dead port 1/2 on $mux $procmux$113456. + dead port 1/2 on $mux $procmux$113459. + dead port 1/2 on $mux $procmux$113462. + dead port 1/2 on $mux $procmux$113465. + dead port 1/2 on $mux $procmux$113468. + dead port 1/2 on $mux $procmux$113471. + dead port 1/2 on $mux $procmux$113474. + dead port 1/2 on $mux $procmux$113477. + dead port 1/2 on $mux $procmux$11348. + dead port 2/2 on $mux $procmux$113480. + dead port 1/2 on $mux $procmux$113486. + dead port 1/2 on $mux $procmux$113489. + dead port 1/2 on $mux $procmux$113492. + dead port 1/2 on $mux $procmux$113495. + dead port 1/2 on $mux $procmux$113498. + dead port 1/2 on $mux $procmux$113501. + dead port 1/2 on $mux $procmux$113504. + dead port 1/2 on $mux $procmux$113507. + dead port 1/2 on $mux $procmux$11351. + dead port 1/2 on $mux $procmux$113510. + dead port 1/2 on $mux $procmux$113513. + dead port 2/2 on $mux $procmux$113516. + dead port 1/2 on $mux $procmux$113522. + dead port 1/2 on $mux $procmux$113525. + dead port 1/2 on $mux $procmux$113528. + dead port 1/2 on $mux $procmux$113531. + dead port 1/2 on $mux $procmux$113534. + dead port 1/2 on $mux $procmux$113537. + dead port 1/2 on $mux $procmux$11354. + dead port 1/2 on $mux $procmux$113540. + dead port 1/2 on $mux $procmux$113543. + dead port 1/2 on $mux $procmux$113546. + dead port 1/2 on $mux $procmux$113549. + dead port 2/2 on $mux $procmux$113552. + dead port 1/2 on $mux $procmux$113558. + dead port 1/2 on $mux $procmux$113561. + dead port 1/2 on $mux $procmux$113564. + dead port 1/2 on $mux $procmux$113567. + dead port 1/2 on $mux $procmux$11357. + dead port 1/2 on $mux $procmux$113570. + dead port 1/2 on $mux $procmux$113573. + dead port 1/2 on $mux $procmux$113576. + dead port 1/2 on $mux $procmux$113579. + dead port 1/2 on $mux $procmux$113582. + dead port 1/2 on $mux $procmux$113585. + dead port 2/2 on $mux $procmux$113588. + dead port 1/2 on $mux $procmux$113594. + dead port 1/2 on $mux $procmux$113597. + dead port 1/2 on $mux $procmux$11360. + dead port 1/2 on $mux $procmux$113600. + dead port 1/2 on $mux $procmux$113603. + dead port 1/2 on $mux $procmux$113606. + dead port 1/2 on $mux $procmux$113609. + dead port 1/2 on $mux $procmux$113612. + dead port 1/2 on $mux $procmux$113615. + dead port 1/2 on $mux $procmux$113618. + dead port 1/2 on $mux $procmux$113621. + dead port 2/2 on $mux $procmux$113624. + dead port 1/2 on $mux $procmux$11363. + dead port 1/2 on $mux $procmux$11366. + dead port 1/2 on $mux $procmux$11369. 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$mux $procmux$113774. + dead port 1/2 on $mux $procmux$113777. + dead port 1/2 on $mux $procmux$113780. + dead port 1/2 on $mux $procmux$113783. + dead port 1/2 on $mux $procmux$113786. + dead port 1/2 on $mux $procmux$113789. + dead port 1/2 on $mux $procmux$113792. + dead port 1/2 on $mux $procmux$113795. + dead port 1/2 on $mux $procmux$113798. + dead port 1/2 on $mux $procmux$113801. + dead port 2/2 on $mux $procmux$113804. + dead port 1/2 on $mux $procmux$113810. + dead port 1/2 on $mux $procmux$113813. + dead port 1/2 on $mux $procmux$113816. + dead port 1/2 on $mux $procmux$113819. + dead port 2/2 on $mux $procmux$11382. + dead port 1/2 on $mux $procmux$113822. + dead port 1/2 on $mux $procmux$113825. + dead port 1/2 on $mux $procmux$113828. + dead port 1/2 on $mux $procmux$113831. + dead port 1/2 on $mux $procmux$113834. + dead port 1/2 on $mux $procmux$113837. + dead port 2/2 on $mux $procmux$113840. + dead port 1/2 on $mux $procmux$113846. + dead port 1/2 on $mux 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$procmux$11409. + dead port 1/2 on $mux $procmux$114098. + dead port 1/2 on $mux $procmux$114101. + dead port 1/2 on $mux $procmux$114104. + dead port 1/2 on $mux $procmux$114107. + dead port 1/2 on $mux $procmux$114110. + dead port 1/2 on $mux $procmux$114113. + dead port 1/2 on $mux $procmux$114116. + dead port 1/2 on $mux $procmux$114119. + dead port 1/2 on $mux $procmux$11412. + dead port 1/2 on $mux $procmux$114122. + dead port 1/2 on $mux $procmux$114125. + dead port 2/2 on $mux $procmux$114128. + dead port 1/2 on $mux $procmux$114134. + dead port 1/2 on $mux $procmux$114137. + dead port 1/2 on $mux $procmux$114140. + dead port 1/2 on $mux $procmux$114143. + dead port 1/2 on $mux $procmux$114146. + dead port 1/2 on $mux $procmux$114149. + dead port 1/2 on $mux $procmux$11415. + dead port 1/2 on $mux $procmux$114152. + dead port 1/2 on $mux $procmux$114155. + dead port 1/2 on $mux $procmux$114158. + dead port 1/2 on $mux $procmux$114161. + dead port 2/2 on $mux $procmux$114164. + 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$procmux$114335. + dead port 1/2 on $mux $procmux$114338. + dead port 1/2 on $mux $procmux$114341. + dead port 2/2 on $mux $procmux$114344. + dead port 2/2 on $mux $procmux$11435. + dead port 1/2 on $mux $procmux$114350. + dead port 1/2 on $mux $procmux$114353. + dead port 1/2 on $mux $procmux$114356. + dead port 1/2 on $mux $procmux$114359. + dead port 1/2 on $mux $procmux$114362. + dead port 1/2 on $mux $procmux$114365. + dead port 1/2 on $mux $procmux$114368. + dead port 1/2 on $mux $procmux$114371. + dead port 1/2 on $mux $procmux$114374. + dead port 1/2 on $mux $procmux$114377. + dead port 1/2 on $mux $procmux$11438. + dead port 2/2 on $mux $procmux$114380. + dead port 1/2 on $mux $procmux$114386. + dead port 1/2 on $mux $procmux$114389. + dead port 1/2 on $mux $procmux$114392. + dead port 1/2 on $mux $procmux$114395. + dead port 1/2 on $mux $procmux$114398. + dead port 1/2 on $mux $procmux$114401. + dead port 1/2 on $mux $procmux$114404. + dead port 1/2 on $mux $procmux$114407. + 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$procmux$114551. + dead port 1/2 on $mux $procmux$114554. + dead port 2/2 on $mux $procmux$114557. + dead port 1/2 on $mux $procmux$11456. + dead port 1/2 on $mux $procmux$114563. + dead port 1/2 on $mux $procmux$114566. + dead port 1/2 on $mux $procmux$114569. + dead port 1/2 on $mux $procmux$114572. + dead port 1/2 on $mux $procmux$114575. + dead port 1/2 on $mux $procmux$114578. + dead port 1/2 on $mux $procmux$114581. + dead port 1/2 on $mux $procmux$114584. + dead port 1/2 on $mux $procmux$114587. + dead port 1/2 on $mux $procmux$11459. + dead port 2/2 on $mux $procmux$114590. + dead port 1/2 on $mux $procmux$114596. + dead port 1/2 on $mux $procmux$114599. + dead port 1/2 on $mux $procmux$114602. + dead port 1/2 on $mux $procmux$114605. + dead port 1/2 on $mux $procmux$114608. + dead port 1/2 on $mux $procmux$114611. + dead port 1/2 on $mux $procmux$114614. + dead port 1/2 on $mux $procmux$114617. + dead port 1/2 on $mux $procmux$11462. + dead port 1/2 on $mux $procmux$114620. + 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$procmux$117554. + dead port 1/2 on $mux $procmux$117557. + dead port 1/2 on $mux $procmux$11756. + dead port 2/2 on $mux $procmux$117560. + dead port 1/2 on $mux $procmux$117566. + dead port 1/2 on $mux $procmux$117569. + dead port 1/2 on $mux $procmux$117572. + dead port 1/2 on $mux $procmux$117575. + dead port 1/2 on $mux $procmux$117578. + dead port 1/2 on $mux $procmux$117581. + dead port 1/2 on $mux $procmux$117584. + dead port 1/2 on $mux $procmux$117587. + dead port 1/2 on $mux $procmux$11759. + dead port 1/2 on $mux $procmux$117590. + dead port 2/2 on $mux $procmux$117593. + dead port 1/2 on $mux $procmux$117599. + dead port 1/2 on $mux $procmux$117602. + dead port 1/2 on $mux $procmux$117605. + dead port 1/2 on $mux $procmux$117608. + dead port 1/2 on $mux $procmux$117611. + dead port 1/2 on $mux $procmux$117614. + dead port 1/2 on $mux $procmux$117617. + dead port 1/2 on $mux $procmux$11762. + dead port 1/2 on $mux $procmux$117620. + dead port 1/2 on $mux $procmux$117623. + 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$mux $procmux$117701. + dead port 1/2 on $mux $procmux$117704. + dead port 1/2 on $mux $procmux$117707. + dead port 1/2 on $mux $procmux$11771. + dead port 1/2 on $mux $procmux$117710. + dead port 1/2 on $mux $procmux$117713. + dead port 1/2 on $mux $procmux$117716. + dead port 1/2 on $mux $procmux$117719. + dead port 1/2 on $mux $procmux$117722. + dead port 2/2 on $mux $procmux$117725. + dead port 1/2 on $mux $procmux$117731. + dead port 1/2 on $mux $procmux$117734. + dead port 1/2 on $mux $procmux$117737. + dead port 1/2 on $mux $procmux$11774. + dead port 1/2 on $mux $procmux$117740. + dead port 1/2 on $mux $procmux$117743. + dead port 1/2 on $mux $procmux$117746. + dead port 1/2 on $mux $procmux$117749. + dead port 1/2 on $mux $procmux$117752. + dead port 1/2 on $mux $procmux$117755. + dead port 2/2 on $mux $procmux$117758. + dead port 1/2 on $mux $procmux$117764. + dead port 1/2 on $mux $procmux$117767. + dead port 1/2 on $mux $procmux$11777. + dead port 1/2 on $mux $procmux$117770. + dead port 1/2 on $mux $procmux$117773. + dead port 1/2 on $mux $procmux$117776. + dead port 1/2 on $mux $procmux$117779. + dead port 1/2 on $mux $procmux$117782. + dead port 1/2 on $mux $procmux$117785. + dead port 1/2 on $mux $procmux$117788. + dead port 2/2 on $mux $procmux$117791. + dead port 1/2 on $mux $procmux$117797. + dead port 1/2 on $mux $procmux$11780. + dead port 1/2 on $mux $procmux$117800. + dead port 1/2 on $mux $procmux$117803. + dead port 1/2 on $mux $procmux$117806. + dead port 1/2 on $mux $procmux$117809. + dead port 1/2 on $mux $procmux$117812. + dead port 1/2 on $mux $procmux$117815. + dead port 1/2 on $mux $procmux$117818. + dead port 1/2 on $mux $procmux$117821. + dead port 2/2 on $mux $procmux$117824. + dead port 1/2 on $mux $procmux$11783. + dead port 1/2 on $mux $procmux$117830. + dead port 1/2 on $mux $procmux$117833. + dead port 1/2 on $mux $procmux$117836. + dead port 1/2 on $mux $procmux$117839. + dead port 1/2 on $mux $procmux$117842. + dead port 1/2 on $mux $procmux$117845. + dead port 1/2 on $mux $procmux$117848. + dead port 1/2 on $mux $procmux$117851. + dead port 1/2 on $mux $procmux$117854. + dead port 2/2 on $mux $procmux$117857. + dead port 2/2 on $mux $procmux$11786. + dead port 1/2 on $mux $procmux$117896. + dead port 1/2 on $mux $procmux$117899. + dead port 1/2 on $mux $procmux$117902. + dead port 1/2 on $mux $procmux$117905. + dead port 1/2 on $mux $procmux$117908. + dead port 1/2 on $mux $procmux$117911. + dead port 1/2 on $mux $procmux$117914. + dead port 1/2 on $mux $procmux$117917. + dead port 1/2 on $mux $procmux$117920. + dead port 2/2 on $mux $procmux$117923. + dead port 1/2 on $mux $procmux$117929. + dead port 1/2 on $mux $procmux$117932. + dead port 1/2 on $mux $procmux$117935. + dead port 1/2 on $mux $procmux$117938. + dead port 1/2 on $mux $procmux$117941. + dead port 1/2 on $mux $procmux$117944. + dead port 1/2 on $mux $procmux$117947. + dead port 1/2 on $mux $procmux$11795. + dead port 1/2 on $mux $procmux$117950. + dead port 1/2 on $mux $procmux$117953. + dead port 2/2 on $mux $procmux$117956. + dead port 1/2 on $mux $procmux$117962. + dead port 1/2 on $mux $procmux$117965. + dead port 1/2 on $mux $procmux$117968. + dead port 2/2 on $mux $procmux$11797. + dead port 1/2 on $mux $procmux$117971. + dead port 1/2 on $mux $procmux$117974. + dead port 1/2 on $mux $procmux$117977. + dead port 1/2 on $mux $procmux$117980. + dead port 1/2 on $mux $procmux$117983. + dead port 1/2 on $mux $procmux$117986. + dead port 2/2 on $mux $procmux$117989. + dead port 2/2 on $mux $procmux$11799. + dead port 1/2 on $mux $procmux$11802. + dead port 1/2 on $mux $procmux$11805. + dead port 1/2 on $mux $procmux$11808. + dead port 1/2 on $mux $procmux$118094. + dead port 1/2 on $mux $procmux$118097. + dead port 1/2 on $mux $procmux$118100. + dead port 1/2 on $mux $procmux$118103. + dead port 1/2 on $mux $procmux$118106. + dead port 1/2 on $mux $procmux$118109. + dead port 1/2 on $mux $procmux$11811. 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$mux $procmux$118184. + dead port 2/2 on $mux $procmux$118187. + dead port 1/2 on $mux $procmux$11820. + dead port 1/2 on $mux $procmux$118226. + dead port 1/2 on $mux $procmux$118229. + dead port 1/2 on $mux $procmux$11823. + dead port 1/2 on $mux $procmux$118232. + dead port 1/2 on $mux $procmux$118235. + dead port 1/2 on $mux $procmux$118238. + dead port 1/2 on $mux $procmux$118241. + dead port 1/2 on $mux $procmux$118244. + dead port 1/2 on $mux $procmux$118247. + dead port 1/2 on $mux $procmux$118250. + dead port 2/2 on $mux $procmux$118253. + dead port 1/2 on $mux $procmux$11826. + dead port 1/2 on $mux $procmux$11829. + dead port 1/2 on $mux $procmux$11832. + dead port 1/2 on $mux $procmux$11835. + dead port 1/2 on $mux $procmux$11838. + dead port 1/2 on $mux $procmux$11841. + dead port 1/2 on $mux $procmux$11844. + dead port 1/2 on $mux $procmux$11847. + dead port 1/2 on $mux $procmux$11850. + dead port 2/2 on $mux $procmux$11852. + dead port 1/2 on $mux $procmux$11855. + dead port 1/2 on $mux $procmux$11858. + dead port 1/2 on $mux $procmux$11861. + dead port 1/2 on $mux $procmux$11864. + dead port 1/2 on $mux $procmux$11867. + dead port 1/2 on $mux $procmux$11870. + dead port 1/2 on $mux $procmux$11873. + dead port 1/2 on $mux $procmux$11876. + dead port 1/2 on $mux $procmux$11879. + dead port 1/2 on $mux $procmux$11882. + dead port 1/2 on $mux $procmux$11885. + dead port 2/2 on $mux $procmux$11888. + dead port 1/2 on $mux $procmux$11897. + dead port 2/2 on $mux $procmux$11899. + dead port 2/2 on $mux $procmux$11901. + dead port 1/2 on $mux $procmux$11904. + dead port 1/2 on $mux $procmux$11907. + dead port 1/2 on $mux $procmux$11910. + dead port 1/2 on $mux $procmux$11913. + dead port 1/2 on $mux $procmux$11916. + dead port 1/2 on $mux $procmux$11919. + dead port 1/2 on $mux $procmux$11922. + dead port 1/2 on $mux $procmux$11925. + dead port 1/2 on $mux $procmux$11928. + dead port 1/2 on $mux $procmux$11931. + dead port 1/2 on $mux $procmux$11934. + dead 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$procmux$120974. + dead port 1/2 on $mux $procmux$120977. + dead port 1/2 on $mux $procmux$120980. + dead port 1/2 on $mux $procmux$120983. + dead port 1/2 on $mux $procmux$120986. + dead port 1/2 on $mux $procmux$120989. + dead port 1/2 on $mux $procmux$120992. + dead port 2/2 on $mux $procmux$120995. + dead port 2/2 on $mux $procmux$12100. + dead port 1/2 on $mux $procmux$121001. + dead port 1/2 on $mux $procmux$121004. + dead port 1/2 on $mux $procmux$121007. + dead port 1/2 on $mux $procmux$121010. + dead port 1/2 on $mux $procmux$121013. + dead port 1/2 on $mux $procmux$121016. + dead port 1/2 on $mux $procmux$121019. + dead port 2/2 on $mux $procmux$12102. + dead port 1/2 on $mux $procmux$121022. + dead port 2/2 on $mux $procmux$121025. + dead port 1/2 on $mux $procmux$121031. + dead port 1/2 on $mux $procmux$121034. + dead port 1/2 on $mux $procmux$121037. + dead port 1/2 on $mux $procmux$121040. + dead port 1/2 on $mux $procmux$121043. + dead port 1/2 on $mux $procmux$121046. + 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$procmux$121172. + dead port 2/2 on $mux $procmux$121175. + dead port 1/2 on $mux $procmux$121181. + dead port 1/2 on $mux $procmux$121184. + dead port 1/2 on $mux $procmux$121187. + dead port 1/2 on $mux $procmux$121190. + dead port 1/2 on $mux $procmux$121193. + dead port 1/2 on $mux $procmux$121196. + dead port 1/2 on $mux $procmux$121199. + dead port 1/2 on $mux $procmux$12120. + dead port 1/2 on $mux $procmux$121202. + dead port 2/2 on $mux $procmux$121205. + dead port 1/2 on $mux $procmux$121211. + dead port 1/2 on $mux $procmux$121214. + dead port 1/2 on $mux $procmux$121217. + dead port 1/2 on $mux $procmux$121220. + dead port 1/2 on $mux $procmux$121223. + dead port 1/2 on $mux $procmux$121226. + dead port 1/2 on $mux $procmux$121229. + dead port 1/2 on $mux $procmux$12123. + dead port 1/2 on $mux $procmux$121232. + dead port 2/2 on $mux $procmux$121235. + dead port 1/2 on $mux $procmux$121241. + dead port 1/2 on $mux $procmux$121244. + dead port 1/2 on $mux $procmux$121247. + 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$procmux$121394. + dead port 1/2 on $mux $procmux$121397. + dead port 1/2 on $mux $procmux$121400. + dead port 1/2 on $mux $procmux$121403. + dead port 1/2 on $mux $procmux$121406. + dead port 1/2 on $mux $procmux$121409. + dead port 1/2 on $mux $procmux$12141. + dead port 1/2 on $mux $procmux$121412. + dead port 2/2 on $mux $procmux$121415. + dead port 1/2 on $mux $procmux$121421. + dead port 1/2 on $mux $procmux$121424. + dead port 1/2 on $mux $procmux$121427. + dead port 1/2 on $mux $procmux$121430. + dead port 1/2 on $mux $procmux$121433. + dead port 1/2 on $mux $procmux$121436. + dead port 1/2 on $mux $procmux$121439. + dead port 1/2 on $mux $procmux$12144. + dead port 1/2 on $mux $procmux$121442. + dead port 2/2 on $mux $procmux$121445. + dead port 1/2 on $mux $procmux$12147. + dead port 1/2 on $mux $procmux$121481. + dead port 1/2 on $mux $procmux$121484. + dead port 1/2 on $mux $procmux$121487. + dead port 1/2 on $mux $procmux$121490. + dead port 1/2 on $mux $procmux$121493. + dead port 1/2 on $mux $procmux$121496. + dead port 1/2 on $mux $procmux$121499. + dead port 1/2 on $mux $procmux$12150. + dead port 1/2 on $mux $procmux$121502. + dead port 2/2 on $mux $procmux$121505. + dead port 1/2 on $mux $procmux$121511. + dead port 1/2 on $mux $procmux$121514. + dead port 1/2 on $mux $procmux$121517. + dead port 1/2 on $mux $procmux$121520. + dead port 1/2 on $mux $procmux$121523. + dead port 1/2 on $mux $procmux$121526. + dead port 1/2 on $mux $procmux$121529. + dead port 1/2 on $mux $procmux$12153. + dead port 1/2 on $mux $procmux$121532. + dead port 2/2 on $mux $procmux$121535. + dead port 1/2 on $mux $procmux$121541. + dead port 1/2 on $mux $procmux$121544. + dead port 1/2 on $mux $procmux$121547. + dead port 2/2 on $mux $procmux$12155. + dead port 1/2 on $mux $procmux$121550. + dead port 1/2 on $mux $procmux$121553. + dead port 1/2 on $mux $procmux$121556. + dead port 1/2 on $mux $procmux$121559. + dead port 1/2 on $mux $procmux$121562. + dead port 2/2 on $mux $procmux$121565. + dead port 1/2 on $mux $procmux$12158. + dead port 1/2 on $mux $procmux$12161. + dead port 1/2 on $mux $procmux$12164. + dead port 1/2 on $mux $procmux$121661. + dead port 1/2 on $mux $procmux$121664. + dead port 1/2 on $mux $procmux$121667. + dead port 1/2 on $mux $procmux$12167. + dead port 1/2 on $mux $procmux$121670. + dead port 1/2 on $mux $procmux$121673. + dead port 1/2 on $mux $procmux$121676. + dead port 1/2 on $mux $procmux$121679. + dead port 1/2 on $mux $procmux$121682. + dead port 2/2 on $mux $procmux$121685. + dead port 1/2 on $mux $procmux$121691. + dead port 1/2 on $mux $procmux$121694. + dead port 1/2 on $mux $procmux$121697. + dead port 1/2 on $mux $procmux$12170. + dead port 1/2 on $mux $procmux$121700. + dead port 1/2 on $mux $procmux$121703. + dead port 1/2 on $mux $procmux$121706. + dead port 1/2 on $mux $procmux$121709. + dead port 1/2 on $mux $procmux$121712. + dead port 2/2 on $mux $procmux$121715. + dead port 1/2 on $mux $procmux$121721. + dead port 1/2 on $mux $procmux$121724. + dead port 1/2 on $mux $procmux$121727. + dead port 1/2 on $mux $procmux$12173. + dead port 1/2 on $mux $procmux$121730. + dead port 1/2 on $mux $procmux$121733. + dead port 1/2 on $mux $procmux$121736. + dead port 1/2 on $mux $procmux$121739. + dead port 1/2 on $mux $procmux$121742. + dead port 2/2 on $mux $procmux$121745. + dead port 1/2 on $mux $procmux$12176. + dead port 1/2 on $mux $procmux$121781. + dead port 1/2 on $mux $procmux$121784. + dead port 1/2 on $mux $procmux$121787. + dead port 1/2 on $mux $procmux$12179. + dead port 1/2 on $mux $procmux$121790. + dead port 1/2 on $mux $procmux$121793. + dead port 1/2 on $mux $procmux$121796. + dead port 1/2 on $mux $procmux$121799. + dead port 1/2 on $mux $procmux$121802. + dead port 2/2 on $mux $procmux$121805. + dead port 1/2 on $mux $procmux$121811. + dead port 1/2 on $mux $procmux$121814. + dead port 1/2 on $mux $procmux$121817. + dead port 1/2 on $mux $procmux$12182. + dead port 1/2 on $mux $procmux$121820. + dead port 1/2 on $mux $procmux$121823. + dead port 1/2 on $mux $procmux$121826. + dead port 1/2 on $mux $procmux$121829. + dead port 1/2 on $mux $procmux$121832. + dead port 2/2 on $mux $procmux$121835. + dead port 2/2 on $mux $procmux$121841. + dead port 1/2 on $mux $procmux$121844. + dead port 1/2 on $mux $procmux$121847. + dead port 1/2 on $mux $procmux$12185. + dead port 1/2 on $mux $procmux$121850. + dead port 1/2 on $mux $procmux$121853. + dead port 1/2 on $mux $procmux$121856. + dead port 1/2 on $mux $procmux$121859. + dead port 1/2 on $mux $procmux$121862. + dead port 2/2 on $mux $procmux$121865. + dead port 2/2 on $mux $procmux$121871. + dead port 1/2 on $mux $procmux$121874. + dead port 1/2 on $mux $procmux$121877. + dead port 1/2 on $mux $procmux$12188. + dead port 1/2 on $mux $procmux$121880. + dead port 1/2 on $mux $procmux$121883. + dead port 1/2 on $mux $procmux$121886. + dead port 1/2 on $mux $procmux$121889. + dead port 1/2 on $mux $procmux$121892. + dead port 2/2 on $mux $procmux$121895. + dead port 1/2 on $mux $procmux$121901. + dead port 1/2 on $mux $procmux$121904. + dead port 1/2 on $mux $procmux$121907. + dead port 2/2 on $mux $procmux$12191. + dead port 1/2 on $mux $procmux$121910. + dead port 1/2 on $mux $procmux$121913. + dead port 1/2 on $mux $procmux$121916. + dead port 1/2 on $mux $procmux$121919. + dead port 2/2 on $mux $procmux$121922. + dead port 1/2 on $mux $procmux$121928. + dead port 1/2 on $mux $procmux$121931. + dead port 1/2 on $mux $procmux$121934. + dead port 1/2 on $mux $procmux$121937. + dead port 1/2 on $mux $procmux$121940. + dead port 1/2 on $mux $procmux$121943. + dead port 1/2 on $mux $procmux$121946. + dead port 2/2 on $mux $procmux$121949. + dead port 1/2 on $mux $procmux$121955. + dead port 1/2 on $mux $procmux$121958. + dead port 1/2 on $mux $procmux$121961. + dead port 1/2 on $mux $procmux$121964. + dead port 1/2 on $mux $procmux$121967. + dead port 1/2 on $mux $procmux$121970. + dead port 1/2 on $mux $procmux$121973. + dead port 2/2 on $mux $procmux$121976. + dead port 1/2 on $mux $procmux$121982. + dead port 1/2 on $mux $procmux$121985. + dead port 1/2 on $mux $procmux$121988. + dead port 2/2 on $mux $procmux$12199. + dead port 1/2 on $mux $procmux$121991. + dead port 1/2 on $mux $procmux$121994. + dead port 1/2 on $mux $procmux$121997. + dead port 1/2 on $mux $procmux$122000. + dead port 2/2 on $mux $procmux$122003. + dead port 1/2 on $mux $procmux$122009. + dead port 2/2 on $mux $procmux$12201. + dead port 1/2 on $mux $procmux$122012. + dead port 1/2 on $mux $procmux$122015. + dead port 1/2 on $mux $procmux$122018. + dead port 1/2 on $mux $procmux$122021. + dead port 1/2 on $mux $procmux$122024. + dead port 1/2 on $mux $procmux$122027. + dead port 2/2 on $mux $procmux$122030. + dead port 1/2 on $mux $procmux$12204. + dead port 1/2 on $mux $procmux$12207. + dead port 1/2 on $mux $procmux$12210. + dead port 1/2 on $mux $procmux$12213. + dead port 1/2 on $mux $procmux$12216. + dead port 1/2 on $mux $procmux$12219. + dead port 1/2 on $mux $procmux$12222. + dead port 1/2 on $mux $procmux$12225. + dead port 1/2 on $mux $procmux$12228. + dead port 1/2 on $mux $procmux$12231. + dead port 1/2 on $mux $procmux$12234. + dead port 1/2 on $mux $procmux$12237. + dead port 1/2 on $mux $procmux$12240. + dead port 1/2 on $mux $procmux$12243. + dead port 1/2 on $mux $procmux$12246. + dead port 1/2 on $mux $procmux$12249. + dead port 1/2 on $mux $procmux$12252. + dead port 2/2 on $mux $procmux$12254. + dead port 1/2 on $mux $procmux$12257. + dead port 1/2 on $mux $procmux$12260. + dead port 1/2 on $mux $procmux$12263. + dead port 1/2 on $mux $procmux$12266. + dead port 1/2 on $mux $procmux$12269. + dead port 1/2 on $mux $procmux$12272. + dead port 1/2 on $mux $procmux$12275. + dead port 1/2 on $mux $procmux$12278. + dead port 1/2 on $mux $procmux$12281. + dead port 1/2 on $mux $procmux$12284. + dead port 1/2 on $mux $procmux$12287. + dead port 2/2 on $mux $procmux$12290. + dead port 2/2 on $mux $procmux$12298. + dead port 2/2 on $mux $procmux$12300. + dead port 1/2 on $mux $procmux$12303. + dead port 1/2 on $mux $procmux$12306. + dead port 1/2 on $mux $procmux$12309. + dead port 1/2 on $mux $procmux$12312. + dead port 1/2 on $mux $procmux$12315. + dead port 1/2 on $mux $procmux$12318. + dead port 1/2 on $mux $procmux$12321. + dead port 1/2 on $mux $procmux$12324. + dead port 1/2 on $mux $procmux$12327. + dead port 1/2 on $mux $procmux$12330. + dead port 1/2 on $mux $procmux$12333. + dead port 1/2 on $mux $procmux$12336. + dead port 1/2 on $mux $procmux$12339. + dead port 1/2 on $mux $procmux$12342. + dead port 1/2 on $mux $procmux$12345. + dead port 1/2 on $mux $procmux$12348. + dead port 1/2 on $mux $procmux$12351. + dead port 2/2 on $mux $procmux$12353. + dead port 1/2 on $mux $procmux$12356. + dead port 1/2 on $mux $procmux$12359. + dead port 1/2 on $mux $procmux$12362. + dead port 1/2 on $mux $procmux$12365. + dead port 1/2 on $mux $procmux$12368. + dead port 1/2 on $mux $procmux$12371. + dead port 1/2 on $mux $procmux$12374. + dead port 1/2 on $mux $procmux$12377. + dead port 1/2 on $mux $procmux$12380. + dead port 1/2 on $mux $procmux$12383. + dead port 1/2 on $mux $procmux$12386. + dead port 2/2 on $mux $procmux$12389. + dead port 1/2 on $mux $procmux$124223. + dead port 1/2 on $mux $procmux$124226. + dead port 1/2 on $mux $procmux$124229. + dead port 1/2 on $mux $procmux$124232. + dead port 1/2 on $mux $procmux$124235. + dead port 1/2 on $mux $procmux$124238. + dead port 1/2 on $mux $procmux$124241. + dead port 2/2 on $mux $procmux$124244. + dead port 1/2 on $mux $procmux$124250. + dead port 1/2 on $mux $procmux$124253. + dead port 1/2 on $mux $procmux$124256. + dead port 1/2 on $mux $procmux$124259. + dead port 1/2 on $mux $procmux$124262. + dead port 1/2 on $mux $procmux$124265. + dead port 1/2 on $mux $procmux$124268. + dead port 2/2 on $mux $procmux$124271. + dead port 1/2 on $mux $procmux$124277. + dead port 1/2 on $mux $procmux$124280. + dead port 1/2 on $mux $procmux$124283. + dead port 1/2 on $mux $procmux$124286. + dead port 1/2 on $mux $procmux$124289. + dead port 1/2 on $mux $procmux$124292. + dead port 1/2 on $mux $procmux$124295. + dead port 2/2 on $mux $procmux$124298. + dead port 1/2 on $mux $procmux$124304. + dead port 1/2 on $mux $procmux$124307. + dead port 1/2 on $mux $procmux$124310. + dead port 1/2 on $mux $procmux$124313. + dead port 1/2 on $mux $procmux$124316. + dead port 1/2 on $mux $procmux$124319. + dead port 1/2 on $mux $procmux$124322. + dead port 2/2 on $mux $procmux$124325. + dead port 1/2 on $mux $procmux$124331. + dead port 1/2 on $mux $procmux$124334. + dead port 1/2 on $mux $procmux$124337. + dead port 1/2 on $mux $procmux$124340. + dead port 1/2 on $mux $procmux$124343. + dead port 1/2 on $mux $procmux$124346. + dead port 1/2 on $mux $procmux$124349. + dead port 2/2 on $mux $procmux$124352. + dead port 1/2 on $mux $procmux$124412. + dead port 1/2 on $mux $procmux$124415. + dead port 1/2 on $mux $procmux$124418. + dead port 1/2 on $mux $procmux$124421. + dead port 1/2 on $mux $procmux$124424. + dead port 1/2 on $mux $procmux$124427. + dead port 1/2 on $mux $procmux$124430. + dead port 2/2 on $mux $procmux$124433. + dead port 1/2 on $mux $procmux$124439. + dead port 1/2 on $mux $procmux$124442. + dead port 1/2 on $mux $procmux$124445. + dead port 1/2 on $mux $procmux$124448. + dead port 1/2 on $mux $procmux$124451. + dead port 1/2 on $mux $procmux$124454. + dead port 1/2 on $mux $procmux$124457. + dead port 2/2 on $mux $procmux$124460. + dead port 1/2 on $mux $procmux$124466. + dead port 1/2 on $mux $procmux$124469. + dead port 1/2 on $mux $procmux$124472. + dead port 1/2 on $mux $procmux$124475. + dead port 1/2 on $mux $procmux$124478. + dead port 1/2 on $mux $procmux$124481. + dead port 1/2 on $mux $procmux$124484. + dead port 2/2 on $mux $procmux$124487. + dead port 1/2 on $mux $procmux$124493. + dead port 1/2 on $mux $procmux$124496. + dead port 1/2 on $mux $procmux$124499. + dead port 1/2 on $mux $procmux$124502. + dead port 1/2 on $mux $procmux$124505. + dead port 1/2 on $mux $procmux$124508. + dead port 1/2 on $mux $procmux$124511. + dead port 2/2 on $mux $procmux$124514. + dead port 1/2 on $mux $procmux$124520. + dead port 1/2 on $mux $procmux$124523. + dead port 1/2 on $mux $procmux$124526. + dead port 1/2 on $mux $procmux$124529. + dead port 1/2 on $mux $procmux$124532. + dead port 1/2 on $mux $procmux$124535. + dead port 1/2 on $mux $procmux$124538. + dead port 2/2 on $mux $procmux$124541. + dead port 1/2 on $mux $procmux$124547. + dead port 1/2 on $mux $procmux$124550. + dead port 1/2 on $mux $procmux$124553. + dead port 1/2 on $mux $procmux$124556. + dead port 1/2 on $mux $procmux$124559. + dead port 1/2 on $mux $procmux$124562. + dead port 1/2 on $mux $procmux$124565. + dead port 2/2 on $mux $procmux$124568. + dead port 1/2 on $mux $procmux$124574. + dead port 1/2 on $mux $procmux$124577. + dead port 1/2 on $mux $procmux$124580. + dead port 1/2 on $mux $procmux$124583. + dead port 1/2 on $mux $procmux$124586. + dead port 1/2 on $mux $procmux$124589. + dead port 1/2 on $mux $procmux$124592. + dead port 2/2 on $mux $procmux$124595. + dead port 1/2 on $mux $procmux$124601. + dead port 1/2 on $mux $procmux$124604. + dead port 1/2 on $mux $procmux$124607. + dead port 1/2 on $mux $procmux$124610. + dead port 1/2 on $mux $procmux$124613. + dead port 1/2 on $mux $procmux$124616. + dead port 1/2 on $mux $procmux$124619. + dead port 2/2 on $mux $procmux$124622. + dead port 1/2 on $mux $procmux$124628. + dead port 1/2 on $mux $procmux$124631. + dead port 1/2 on $mux $procmux$124634. + dead port 1/2 on $mux $procmux$124637. + dead port 1/2 on $mux $procmux$124640. + dead port 1/2 on $mux $procmux$124643. + dead port 1/2 on $mux $procmux$124646. + dead port 2/2 on $mux $procmux$124649. + dead port 1/2 on $mux $procmux$124655. + dead port 1/2 on $mux $procmux$124658. + dead port 1/2 on $mux $procmux$124661. + dead port 1/2 on $mux $procmux$124664. + dead port 1/2 on $mux $procmux$124667. + dead port 1/2 on $mux $procmux$124670. + dead port 1/2 on $mux $procmux$124673. + dead port 2/2 on $mux $procmux$124676. + dead port 1/2 on $mux $procmux$124709. + dead port 1/2 on $mux $procmux$124712. + dead port 1/2 on $mux $procmux$124715. + dead port 1/2 on $mux $procmux$124718. + dead port 1/2 on $mux $procmux$124721. + dead port 1/2 on $mux $procmux$124724. + dead port 1/2 on $mux $procmux$124727. + dead port 2/2 on $mux $procmux$124730. + dead port 1/2 on $mux $procmux$124736. + dead port 1/2 on $mux $procmux$124739. + dead port 1/2 on $mux $procmux$124742. + dead port 1/2 on $mux $procmux$124745. + dead port 1/2 on $mux $procmux$124748. + dead port 1/2 on $mux $procmux$124751. + dead port 1/2 on $mux $procmux$124754. + dead port 2/2 on $mux $procmux$124757. + dead port 1/2 on $mux $procmux$124763. + dead port 1/2 on $mux $procmux$124766. + dead port 1/2 on $mux $procmux$124769. + dead port 1/2 on $mux $procmux$124772. + dead port 1/2 on $mux $procmux$124775. + dead port 1/2 on $mux $procmux$124778. + dead port 1/2 on $mux $procmux$124781. + dead port 2/2 on $mux $procmux$124784. + dead port 1/2 on $mux $procmux$124871. + dead port 1/2 on $mux $procmux$124874. + dead port 1/2 on $mux $procmux$124877. + dead port 1/2 on $mux $procmux$124880. + dead port 1/2 on $mux $procmux$124883. + dead port 1/2 on $mux $procmux$124886. + dead port 1/2 on $mux $procmux$124889. + dead port 2/2 on $mux $procmux$124892. + dead port 1/2 on $mux $procmux$124898. + dead port 1/2 on $mux $procmux$124901. + dead port 1/2 on $mux $procmux$124904. + dead port 1/2 on $mux $procmux$124907. + dead port 1/2 on $mux $procmux$124910. + dead port 1/2 on $mux $procmux$124913. + dead port 1/2 on $mux $procmux$124916. + dead port 2/2 on $mux $procmux$124919. + dead port 1/2 on $mux $procmux$124925. + dead port 1/2 on $mux $procmux$124928. + dead port 1/2 on $mux $procmux$124931. + dead port 1/2 on $mux $procmux$124934. + dead port 1/2 on $mux $procmux$124937. + dead port 1/2 on $mux $procmux$124940. + dead port 1/2 on $mux $procmux$124943. + dead port 2/2 on $mux $procmux$124946. + dead port 1/2 on $mux $procmux$124979. + dead port 1/2 on $mux $procmux$124982. + dead port 1/2 on $mux $procmux$124985. + dead port 1/2 on $mux $procmux$124988. + dead port 1/2 on $mux $procmux$124991. + dead port 1/2 on $mux $procmux$124994. + dead port 1/2 on $mux $procmux$124997. + dead port 2/2 on $mux $procmux$125000. + dead port 1/2 on $mux $procmux$125004. + dead port 1/2 on $mux $procmux$125007. + dead port 1/2 on $mux $procmux$125010. + dead port 2/2 on $mux $procmux$125012. + dead port 1/2 on $mux $procmux$125015. + dead port 1/2 on $mux $procmux$125018. + dead port 1/2 on $mux $procmux$125021. + dead port 1/2 on $mux $procmux$125024. + dead port 1/2 on $mux $procmux$125027. + dead port 1/2 on $mux $procmux$125030. + dead port 2/2 on $mux $procmux$125033. + dead port 1/2 on $mux $procmux$125040. + dead port 1/2 on $mux $procmux$125043. + dead port 2/2 on $mux $procmux$125045. + dead port 1/2 on $mux $procmux$125048. + dead port 1/2 on $mux $procmux$125051. + dead port 1/2 on $mux $procmux$125054. + dead port 1/2 on $mux $procmux$125057. + dead port 1/2 on $mux $procmux$125060. + dead port 1/2 on $mux $procmux$125063. + dead port 2/2 on $mux $procmux$125066. + dead port 1/2 on $mux $procmux$125073. + dead port 1/2 on $mux $procmux$125076. + dead port 2/2 on $mux $procmux$125078. + dead port 1/2 on $mux $procmux$125081. + dead port 1/2 on $mux $procmux$125084. + dead port 1/2 on $mux $procmux$125087. + dead port 1/2 on $mux $procmux$125090. + dead port 1/2 on $mux $procmux$125093. + dead port 1/2 on $mux $procmux$125096. + dead port 2/2 on $mux $procmux$125099. + dead port 1/2 on $mux $procmux$125106. + dead port 1/2 on $mux $procmux$125109. + dead port 2/2 on $mux $procmux$125111. + dead port 1/2 on $mux $procmux$125114. + dead port 1/2 on $mux $procmux$125117. + dead port 1/2 on $mux $procmux$125120. + dead port 1/2 on $mux $procmux$125123. + dead port 1/2 on $mux $procmux$125126. + dead port 1/2 on $mux $procmux$125129. + dead port 2/2 on $mux $procmux$125132. + dead port 1/2 on $mux $procmux$125139. + dead port 1/2 on $mux $procmux$125142. + dead port 2/2 on $mux $procmux$125144. + dead port 1/2 on $mux $procmux$125147. + dead port 1/2 on $mux $procmux$125150. + dead port 1/2 on $mux $procmux$125153. + dead port 1/2 on $mux $procmux$125156. + dead port 1/2 on $mux $procmux$125159. + dead port 1/2 on $mux $procmux$125162. + dead port 2/2 on $mux $procmux$125165. + dead port 1/2 on $mux $procmux$125172. + dead port 1/2 on $mux $procmux$125175. + dead port 2/2 on $mux $procmux$125177. + dead port 1/2 on $mux $procmux$125180. + dead port 1/2 on $mux $procmux$125183. + dead port 1/2 on $mux $procmux$125186. + dead port 1/2 on $mux $procmux$125189. + dead port 1/2 on $mux $procmux$125192. + dead port 1/2 on $mux $procmux$125195. + dead port 2/2 on $mux $procmux$125198. + dead port 1/2 on $mux $procmux$125205. + dead port 1/2 on $mux $procmux$125208. + dead port 2/2 on $mux $procmux$125210. + dead port 1/2 on $mux $procmux$125213. + dead port 1/2 on $mux $procmux$125216. + dead port 1/2 on $mux $procmux$125219. + dead port 1/2 on $mux $procmux$125222. + dead port 1/2 on $mux $procmux$125225. + dead port 1/2 on $mux $procmux$125228. + dead port 2/2 on $mux $procmux$125231. + dead port 1/2 on $mux $procmux$125238. + dead port 1/2 on $mux $procmux$125241. + dead port 2/2 on $mux $procmux$125243. + dead port 1/2 on $mux $procmux$125246. + dead port 1/2 on $mux $procmux$125249. + dead port 1/2 on $mux $procmux$125252. + dead port 1/2 on $mux $procmux$125255. + dead port 1/2 on $mux $procmux$125258. + dead port 1/2 on $mux $procmux$125261. + dead port 2/2 on $mux $procmux$125264. + dead port 1/2 on $mux $procmux$125271. + dead port 1/2 on $mux $procmux$125274. + dead port 2/2 on $mux $procmux$125276. + dead port 1/2 on $mux $procmux$125279. + dead port 1/2 on $mux $procmux$125282. + dead port 1/2 on $mux $procmux$125285. + dead port 1/2 on $mux $procmux$125288. + dead port 1/2 on $mux $procmux$125291. + dead port 1/2 on $mux $procmux$125294. + dead port 2/2 on $mux $procmux$125297. + dead port 1/2 on $mux $procmux$125304. + dead port 1/2 on $mux $procmux$125307. + dead port 2/2 on $mux $procmux$125309. + dead port 1/2 on $mux $procmux$125312. + dead port 1/2 on $mux $procmux$125315. + dead port 1/2 on $mux $procmux$125318. + dead port 1/2 on $mux $procmux$125321. + dead port 1/2 on $mux $procmux$125324. + dead port 1/2 on $mux $procmux$125327. + dead port 2/2 on $mux $procmux$125330. + dead port 1/2 on $mux $procmux$125337. + dead port 1/2 on $mux $procmux$125340. + dead port 2/2 on $mux $procmux$125342. + dead port 1/2 on $mux $procmux$125345. + dead port 1/2 on $mux $procmux$125348. + dead port 1/2 on $mux $procmux$125351. + dead port 1/2 on $mux $procmux$125354. + dead port 1/2 on $mux $procmux$125357. + dead port 1/2 on $mux $procmux$125360. + dead port 2/2 on $mux $procmux$125363. + dead port 1/2 on $mux $procmux$125370. + dead port 2/2 on $mux $procmux$125372. + dead port 1/2 on $mux $procmux$125375. + dead port 1/2 on $mux $procmux$125378. + dead port 1/2 on $mux $procmux$125381. + dead port 1/2 on $mux $procmux$125384. + dead port 1/2 on $mux $procmux$125387. + dead port 1/2 on $mux $procmux$125390. + dead port 2/2 on $mux $procmux$125393. + dead port 1/2 on $mux $procmux$125400. + dead port 2/2 on $mux $procmux$125402. + dead port 1/2 on $mux $procmux$125405. + dead port 1/2 on $mux $procmux$125408. + dead port 1/2 on $mux $procmux$125411. + dead port 1/2 on $mux $procmux$125414. + dead port 1/2 on $mux $procmux$125417. + dead port 1/2 on $mux $procmux$125420. + dead port 2/2 on $mux $procmux$125423. + dead port 1/2 on $mux $procmux$125430. + dead port 2/2 on $mux $procmux$125432. + dead port 1/2 on $mux $procmux$125435. + dead port 1/2 on $mux $procmux$125438. + dead port 1/2 on $mux $procmux$125441. + dead port 1/2 on $mux $procmux$125444. + dead port 1/2 on $mux $procmux$125447. + dead port 1/2 on $mux $procmux$125450. + dead port 2/2 on $mux $procmux$125453. + dead port 1/2 on $mux $procmux$125460. + dead port 2/2 on $mux $procmux$125462. + dead port 1/2 on $mux $procmux$125465. + dead port 1/2 on $mux $procmux$125468. + dead port 1/2 on $mux $procmux$125471. + dead port 1/2 on $mux $procmux$125474. + dead port 1/2 on $mux $procmux$125477. + dead port 1/2 on $mux $procmux$125480. + dead port 2/2 on $mux $procmux$125483. + dead port 1/2 on $mux $procmux$125490. + dead port 2/2 on $mux $procmux$125492. + dead port 1/2 on $mux $procmux$125495. + dead port 1/2 on $mux $procmux$125498. + dead port 1/2 on $mux $procmux$125501. + dead port 1/2 on $mux $procmux$125504. + dead port 1/2 on $mux $procmux$125507. + dead port 1/2 on $mux $procmux$125510. + dead port 2/2 on $mux $procmux$125513. + dead port 1/2 on $mux $procmux$125520. + dead port 2/2 on $mux $procmux$125522. + dead port 1/2 on $mux $procmux$125525. + dead port 1/2 on $mux $procmux$125528. + dead port 1/2 on $mux $procmux$125531. + dead port 1/2 on $mux $procmux$125534. + dead port 1/2 on $mux $procmux$125537. + dead port 1/2 on $mux $procmux$125540. + dead port 2/2 on $mux $procmux$125543. + dead port 2/2 on $mux $procmux$125547. + dead port 1/2 on $mux $procmux$125550. + dead port 2/2 on $mux $procmux$125552. + dead port 1/2 on $mux $procmux$125555. + dead port 1/2 on $mux $procmux$125558. + dead port 1/2 on $mux $procmux$125561. + dead port 1/2 on $mux $procmux$125564. + dead port 1/2 on $mux $procmux$125567. + dead port 1/2 on $mux $procmux$125570. + dead port 2/2 on $mux $procmux$125573. + dead port 2/2 on $mux $procmux$12588. + dead port 1/2 on $mux $procmux$12591. + dead port 1/2 on $mux $procmux$12594. + dead port 1/2 on $mux $procmux$12597. + dead port 1/2 on $mux $procmux$12600. + dead port 1/2 on $mux $procmux$12603. + dead port 1/2 on $mux $procmux$12606. + dead port 1/2 on $mux $procmux$12609. + dead port 1/2 on $mux $procmux$12612. + dead port 1/2 on $mux $procmux$12615. + dead port 1/2 on $mux $procmux$12618. + dead port 1/2 on $mux $procmux$12621. + dead port 1/2 on $mux $procmux$12624. + dead port 1/2 on $mux $procmux$12627. + dead port 1/2 on $mux $procmux$12630. + dead port 1/2 on $mux $procmux$12633. + dead port 1/2 on $mux $procmux$12636. + dead port 1/2 on $mux $procmux$12639. + dead port 2/2 on $mux $procmux$12641. + dead port 1/2 on $mux $procmux$12644. + dead port 1/2 on $mux $procmux$12647. + dead port 1/2 on $mux $procmux$12650. + dead port 1/2 on $mux $procmux$12653. + dead port 1/2 on $mux $procmux$12656. + dead port 1/2 on $mux $procmux$12659. + dead port 1/2 on $mux $procmux$12662. + dead port 1/2 on $mux $procmux$12665. + dead port 1/2 on $mux $procmux$12668. + dead port 1/2 on $mux $procmux$12671. + dead port 1/2 on $mux $procmux$12674. + dead port 2/2 on $mux $procmux$12677. + dead port 1/2 on $mux $procmux$12685. + dead port 1/2 on $mux $procmux$12688. + dead port 2/2 on $mux $procmux$12690. + dead port 1/2 on $mux $procmux$12693. + dead port 1/2 on $mux $procmux$12696. + dead port 1/2 on $mux $procmux$12699. + dead port 1/2 on $mux $procmux$12702. + dead port 1/2 on $mux $procmux$12705. + dead port 1/2 on $mux $procmux$12708. + dead port 1/2 on $mux $procmux$12711. + dead port 1/2 on $mux $procmux$12714. + dead port 1/2 on $mux $procmux$12717. + dead port 1/2 on $mux $procmux$12720. + dead port 1/2 on $mux $procmux$12723. + dead port 1/2 on $mux $procmux$12726. + dead port 1/2 on $mux $procmux$12729. + dead port 1/2 on $mux $procmux$12732. + dead port 1/2 on $mux $procmux$12735. + dead port 1/2 on $mux $procmux$12738. + dead port 1/2 on $mux $procmux$12741. + dead port 2/2 on $mux $procmux$12743. + dead port 1/2 on $mux $procmux$12746. + dead port 1/2 on $mux $procmux$12749. + dead port 1/2 on $mux $procmux$12752. + dead port 1/2 on $mux $procmux$12755. + dead port 1/2 on $mux $procmux$12758. + dead port 1/2 on $mux $procmux$12761. + dead port 1/2 on $mux $procmux$12764. + dead port 1/2 on $mux $procmux$12767. + dead port 1/2 on $mux $procmux$12770. + dead port 1/2 on $mux $procmux$12773. + dead port 1/2 on $mux $procmux$12776. + dead port 2/2 on $mux $procmux$12779. + dead port 1/2 on $mux $procmux$127868. + dead port 1/2 on $mux $procmux$12787. + dead port 1/2 on $mux $procmux$127871. + dead port 1/2 on $mux $procmux$127874. + dead port 1/2 on $mux $procmux$127877. + dead port 1/2 on $mux $procmux$127880. + dead port 1/2 on $mux $procmux$127883. + dead port 2/2 on $mux $procmux$127886. + dead port 1/2 on $mux $procmux$127892. + dead port 1/2 on $mux $procmux$127895. + dead port 1/2 on $mux $procmux$127898. + dead port 1/2 on $mux $procmux$12790. + dead port 1/2 on $mux $procmux$127901. + dead port 1/2 on $mux $procmux$127904. + dead port 1/2 on $mux $procmux$127907. + dead port 2/2 on $mux $procmux$127910. + dead port 2/2 on $mux $procmux$12792. + dead port 1/2 on $mux $procmux$127940. + dead port 1/2 on $mux $procmux$127943. + dead port 1/2 on $mux $procmux$127946. + dead port 1/2 on $mux $procmux$127949. + dead port 1/2 on $mux $procmux$12795. + dead port 1/2 on $mux $procmux$127952. + dead port 1/2 on $mux $procmux$127955. + dead port 2/2 on $mux $procmux$127958. + dead port 1/2 on $mux $procmux$127964. + dead port 1/2 on $mux $procmux$127967. + dead port 1/2 on $mux $procmux$127970. + dead port 1/2 on $mux $procmux$127973. + dead port 1/2 on $mux $procmux$127976. + dead port 1/2 on $mux $procmux$127979. + dead port 1/2 on $mux $procmux$12798. + dead port 2/2 on $mux $procmux$127982. + dead port 1/2 on $mux $procmux$127988. + dead port 1/2 on $mux $procmux$127991. + dead port 1/2 on $mux $procmux$127994. + dead port 1/2 on $mux $procmux$127997. + dead port 1/2 on $mux $procmux$128000. + dead port 1/2 on $mux $procmux$128003. + dead port 2/2 on $mux $procmux$128006. + dead port 1/2 on $mux $procmux$12801. + dead port 1/2 on $mux $procmux$128012. + dead port 1/2 on $mux $procmux$128015. + dead port 1/2 on $mux $procmux$128018. + dead port 1/2 on $mux $procmux$128021. + dead port 1/2 on $mux $procmux$128024. + dead port 1/2 on $mux $procmux$128027. + dead port 2/2 on $mux $procmux$128030. + dead port 1/2 on $mux $procmux$128036. + dead port 1/2 on $mux $procmux$128039. + dead port 1/2 on $mux $procmux$12804. + dead port 1/2 on $mux $procmux$128042. + dead port 1/2 on $mux $procmux$128045. + dead port 1/2 on $mux $procmux$128048. + dead port 1/2 on $mux $procmux$128051. + dead port 2/2 on $mux $procmux$128054. + dead port 1/2 on $mux $procmux$128060. + dead port 1/2 on $mux $procmux$128063. + dead port 1/2 on $mux $procmux$128066. + dead port 1/2 on $mux $procmux$128069. + dead port 1/2 on $mux $procmux$12807. + dead port 1/2 on $mux $procmux$128072. + dead port 1/2 on $mux $procmux$128075. + dead port 2/2 on $mux $procmux$128078. + dead port 1/2 on $mux $procmux$128084. + dead port 1/2 on $mux $procmux$128087. + dead port 1/2 on $mux $procmux$128090. + dead port 1/2 on $mux $procmux$128093. + dead port 1/2 on $mux $procmux$128096. + dead port 1/2 on $mux $procmux$128099. + dead port 1/2 on $mux $procmux$12810. + dead port 2/2 on $mux $procmux$128102. + dead port 1/2 on $mux $procmux$12813. + dead port 1/2 on $mux $procmux$128156. + dead port 1/2 on $mux $procmux$128159. + dead port 1/2 on $mux $procmux$12816. + dead port 1/2 on $mux $procmux$128162. + dead port 1/2 on $mux $procmux$128165. + dead port 1/2 on $mux $procmux$128168. + dead port 1/2 on $mux $procmux$128171. + dead port 2/2 on $mux $procmux$128174. + dead port 1/2 on $mux $procmux$128180. + dead port 1/2 on $mux $procmux$128183. + dead port 1/2 on $mux $procmux$128186. + dead port 1/2 on $mux $procmux$128189. + dead port 1/2 on $mux $procmux$12819. + dead port 1/2 on $mux $procmux$128192. + dead port 1/2 on $mux $procmux$128195. + dead port 2/2 on $mux $procmux$128198. + dead port 1/2 on $mux $procmux$128204. + dead port 1/2 on $mux $procmux$128207. + dead port 1/2 on $mux $procmux$128210. + dead port 1/2 on $mux $procmux$128213. + dead port 1/2 on $mux $procmux$128216. + dead port 1/2 on $mux $procmux$128219. + dead port 1/2 on $mux $procmux$12822. + dead port 2/2 on $mux $procmux$128222. + dead port 1/2 on $mux $procmux$128228. + dead port 1/2 on $mux $procmux$128231. + dead port 1/2 on $mux $procmux$128234. + dead port 1/2 on $mux $procmux$128237. + dead port 1/2 on $mux $procmux$128240. + dead port 1/2 on $mux $procmux$128243. + dead port 2/2 on $mux $procmux$128246. + dead port 1/2 on $mux $procmux$12825. + dead port 1/2 on $mux $procmux$128252. + dead port 1/2 on $mux $procmux$128255. + dead port 1/2 on $mux $procmux$128258. + dead port 1/2 on $mux $procmux$128261. + dead port 1/2 on $mux $procmux$128264. + dead port 1/2 on $mux $procmux$128267. + dead port 2/2 on $mux $procmux$128270. + dead port 1/2 on $mux $procmux$128276. + dead port 1/2 on $mux $procmux$128279. + dead port 1/2 on $mux $procmux$12828. + dead port 1/2 on $mux $procmux$128282. + dead port 1/2 on $mux $procmux$128285. + dead port 1/2 on $mux $procmux$128288. + dead port 1/2 on $mux $procmux$128291. + dead port 2/2 on $mux $procmux$128294. + dead port 1/2 on $mux $procmux$128300. + dead port 1/2 on $mux $procmux$128303. + dead port 1/2 on $mux $procmux$128306. + dead port 1/2 on $mux $procmux$128309. + dead port 1/2 on $mux $procmux$12831. + dead port 1/2 on $mux $procmux$128312. + dead port 1/2 on $mux $procmux$128315. + dead port 2/2 on $mux $procmux$128318. + dead port 1/2 on $mux $procmux$128324. + dead port 1/2 on $mux $procmux$128327. + dead port 1/2 on $mux $procmux$128330. + dead port 1/2 on $mux $procmux$128333. + dead port 1/2 on $mux $procmux$128336. + dead port 1/2 on $mux $procmux$128339. + dead port 1/2 on $mux $procmux$12834. + dead port 2/2 on $mux $procmux$128342. + dead port 1/2 on $mux $procmux$128348. + dead port 1/2 on $mux $procmux$128351. + dead port 1/2 on $mux $procmux$128354. + dead port 1/2 on $mux $procmux$128357. + dead port 1/2 on $mux $procmux$128360. + dead port 1/2 on $mux $procmux$128363. + dead port 2/2 on $mux $procmux$128366. + dead port 1/2 on $mux $procmux$12837. + dead port 1/2 on $mux $procmux$128372. + dead port 1/2 on $mux $procmux$128375. + dead port 1/2 on $mux $procmux$128378. + dead port 1/2 on $mux $procmux$128381. + dead port 1/2 on $mux $procmux$128384. + dead port 1/2 on $mux $procmux$128387. + dead port 2/2 on $mux $procmux$128390. + dead port 1/2 on $mux $procmux$12840. + dead port 1/2 on $mux $procmux$128420. + dead port 1/2 on $mux $procmux$128423. + dead port 1/2 on $mux $procmux$128426. + dead port 1/2 on $mux $procmux$128429. + dead port 1/2 on $mux $procmux$12843. + dead port 1/2 on $mux $procmux$128432. + dead port 1/2 on $mux $procmux$128435. + dead port 2/2 on $mux $procmux$128438. + dead port 1/2 on $mux $procmux$128444. + dead port 1/2 on $mux $procmux$128447. + dead port 2/2 on $mux $procmux$12845. + dead port 1/2 on $mux $procmux$128450. + dead port 1/2 on $mux $procmux$128453. + dead port 1/2 on $mux $procmux$128456. + dead port 1/2 on $mux $procmux$128459. + dead port 2/2 on $mux $procmux$128462. + dead port 1/2 on $mux $procmux$128468. + dead port 1/2 on $mux $procmux$128471. + dead port 1/2 on $mux $procmux$128474. + dead port 1/2 on $mux $procmux$128477. + dead port 1/2 on $mux $procmux$12848. + dead port 1/2 on $mux $procmux$128480. + dead port 1/2 on $mux $procmux$128483. + dead port 2/2 on $mux $procmux$128486. + dead port 1/2 on $mux $procmux$12851. + dead port 1/2 on $mux $procmux$12854. + dead port 1/2 on $mux $procmux$128564. + dead port 1/2 on $mux $procmux$128567. + dead port 1/2 on $mux $procmux$12857. + dead port 1/2 on $mux $procmux$128570. + dead port 1/2 on $mux $procmux$128573. + dead port 1/2 on $mux $procmux$128576. + dead port 1/2 on $mux $procmux$128579. + dead port 2/2 on $mux $procmux$128582. + dead port 1/2 on $mux $procmux$128588. + dead port 1/2 on $mux $procmux$128591. + dead port 1/2 on $mux $procmux$128594. + dead port 1/2 on $mux $procmux$128597. + dead port 1/2 on $mux $procmux$12860. + dead port 1/2 on $mux $procmux$128600. + dead port 1/2 on $mux $procmux$128603. + dead port 2/2 on $mux $procmux$128606. + dead port 1/2 on $mux $procmux$128612. + dead port 1/2 on $mux $procmux$128615. + dead port 1/2 on $mux $procmux$128618. + dead port 1/2 on $mux $procmux$128621. + dead port 1/2 on $mux $procmux$128624. + dead port 1/2 on $mux $procmux$128627. + dead port 1/2 on $mux $procmux$12863. + dead port 2/2 on $mux $procmux$128630. + dead port 1/2 on $mux $procmux$128636. + dead port 1/2 on $mux $procmux$128639. + dead port 1/2 on $mux $procmux$128642. + dead port 1/2 on $mux $procmux$128645. + dead port 1/2 on $mux $procmux$128648. + dead port 1/2 on $mux $procmux$128651. + dead port 2/2 on $mux $procmux$128654. + dead port 1/2 on $mux $procmux$12866. + dead port 1/2 on $mux $procmux$128660. + dead port 1/2 on $mux $procmux$128663. + dead port 1/2 on $mux $procmux$128666. + dead port 1/2 on $mux $procmux$128669. + dead port 1/2 on $mux $procmux$128672. + dead port 1/2 on $mux $procmux$128675. + dead port 2/2 on $mux $procmux$128678. + dead port 1/2 on $mux $procmux$12869. + dead port 1/2 on $mux $procmux$12872. + dead port 1/2 on $mux $procmux$12875. + dead port 1/2 on $mux $procmux$12878. + dead port 2/2 on $mux $procmux$12881. + dead port 1/2 on $mux $procmux$12889. + dead port 2/2 on $mux $procmux$12891. + dead port 1/2 on $mux $procmux$12894. + dead port 1/2 on $mux $procmux$12897. + dead port 1/2 on $mux $procmux$12900. + dead port 1/2 on $mux $procmux$12903. + dead port 1/2 on $mux $procmux$12906. + dead port 1/2 on $mux $procmux$12909. + dead port 1/2 on $mux $procmux$12912. + dead port 1/2 on $mux $procmux$12915. + dead port 1/2 on $mux $procmux$12918. + dead port 1/2 on $mux $procmux$12921. + dead port 1/2 on $mux $procmux$12924. + dead port 1/2 on $mux $procmux$12927. + dead port 1/2 on $mux $procmux$12930. + dead port 1/2 on $mux $procmux$12933. + dead port 1/2 on $mux $procmux$12936. + dead port 1/2 on $mux $procmux$12939. + dead port 1/2 on $mux $procmux$12942. + dead port 2/2 on $mux $procmux$12944. + dead port 1/2 on $mux $procmux$12947. + dead port 1/2 on $mux $procmux$12950. + dead port 1/2 on $mux $procmux$12953. + dead port 1/2 on $mux $procmux$12956. + dead port 1/2 on $mux $procmux$12959. + dead port 1/2 on $mux $procmux$12962. + dead port 1/2 on $mux $procmux$12965. + dead port 1/2 on $mux $procmux$12968. + dead port 1/2 on $mux $procmux$12971. + dead port 1/2 on $mux $procmux$12974. + dead port 1/2 on $mux $procmux$12977. + dead port 2/2 on $mux $procmux$12980. + dead port 1/2 on $mux $procmux$12988. + dead port 2/2 on $mux $procmux$12990. + dead port 1/2 on $mux $procmux$12993. + dead port 1/2 on $mux $procmux$12996. + dead port 1/2 on $mux $procmux$12999. + dead port 1/2 on $mux $procmux$13002. + dead port 1/2 on $mux $procmux$13005. + dead port 1/2 on $mux $procmux$13008. + dead port 1/2 on $mux $procmux$13011. + dead port 1/2 on $mux $procmux$13014. + dead port 1/2 on $mux $procmux$13017. + dead port 1/2 on $mux $procmux$13020. + dead port 1/2 on $mux $procmux$13023. + dead port 1/2 on $mux $procmux$13026. + dead port 1/2 on $mux $procmux$13029. + dead port 1/2 on $mux $procmux$13032. + dead port 1/2 on $mux $procmux$13035. + dead port 1/2 on $mux $procmux$13038. + dead port 1/2 on $mux $procmux$13041. + dead port 2/2 on $mux $procmux$13043. + dead port 1/2 on $mux $procmux$13046. + dead port 1/2 on $mux $procmux$13049. + dead port 1/2 on $mux $procmux$13052. + dead port 1/2 on $mux $procmux$130523. + dead port 1/2 on $mux $procmux$130526. + dead port 1/2 on $mux $procmux$130529. + dead port 1/2 on $mux $procmux$130532. + dead port 1/2 on $mux $procmux$130535. + dead port 2/2 on $mux $procmux$130538. + dead port 1/2 on $mux $procmux$130544. + dead port 1/2 on $mux $procmux$130547. + dead port 1/2 on $mux $procmux$13055. + dead port 1/2 on $mux $procmux$130550. + dead port 1/2 on $mux $procmux$130553. + dead port 1/2 on $mux $procmux$130556. + dead port 2/2 on $mux $procmux$130559. + dead port 1/2 on $mux $procmux$13058. + dead port 1/2 on $mux $procmux$130607. + dead port 1/2 on $mux $procmux$13061. + dead port 1/2 on $mux $procmux$130610. + dead port 1/2 on $mux $procmux$130613. + dead port 1/2 on $mux $procmux$130616. + dead port 1/2 on $mux $procmux$130619. + dead port 2/2 on $mux $procmux$130622. + dead port 1/2 on $mux $procmux$130628. + dead port 1/2 on $mux $procmux$130631. + dead port 1/2 on $mux $procmux$130634. + dead port 1/2 on $mux $procmux$130637. + dead port 1/2 on $mux $procmux$13064. + dead port 1/2 on $mux $procmux$130640. + dead port 2/2 on $mux $procmux$130643. + dead port 1/2 on $mux $procmux$130649. + dead port 1/2 on $mux $procmux$130652. + dead port 1/2 on $mux $procmux$130655. + dead port 1/2 on $mux $procmux$130658. + dead port 1/2 on $mux $procmux$130661. + dead port 2/2 on $mux $procmux$130664. + dead port 1/2 on $mux $procmux$13067. + dead port 1/2 on $mux $procmux$130670. + dead port 1/2 on $mux $procmux$130673. + dead port 1/2 on $mux $procmux$130676. + dead port 1/2 on $mux $procmux$130679. + dead port 1/2 on $mux $procmux$130682. + dead port 2/2 on $mux $procmux$130685. + dead port 1/2 on $mux $procmux$130691. + dead port 1/2 on $mux $procmux$130694. + dead port 1/2 on $mux $procmux$130697. + dead port 1/2 on $mux $procmux$13070. + dead port 1/2 on $mux $procmux$130700. + dead port 1/2 on $mux $procmux$130703. + dead port 2/2 on $mux $procmux$130706. + dead port 1/2 on $mux $procmux$130712. + dead port 1/2 on $mux $procmux$130715. + dead port 1/2 on $mux $procmux$130718. + dead port 1/2 on $mux $procmux$130721. + dead port 1/2 on $mux $procmux$130724. + dead port 2/2 on $mux $procmux$130727. + dead port 1/2 on $mux $procmux$13073. + dead port 1/2 on $mux $procmux$130733. + dead port 1/2 on $mux $procmux$130736. + dead port 1/2 on $mux $procmux$130739. + dead port 1/2 on $mux $procmux$130742. + dead port 1/2 on $mux $procmux$130745. + dead port 2/2 on $mux $procmux$130748. + dead port 1/2 on $mux $procmux$13076. + dead port 2/2 on $mux $procmux$13079. + dead port 1/2 on $mux $procmux$130796. + dead port 1/2 on $mux $procmux$130799. + dead port 1/2 on $mux $procmux$130802. + dead port 1/2 on $mux $procmux$130805. + dead port 1/2 on $mux $procmux$130808. + dead port 2/2 on $mux $procmux$130811. + dead port 1/2 on $mux $procmux$130817. + dead port 1/2 on $mux $procmux$130820. + dead port 1/2 on $mux $procmux$130823. + dead port 1/2 on $mux $procmux$130826. + dead port 1/2 on $mux $procmux$130829. + dead port 2/2 on $mux $procmux$130832. + dead port 1/2 on $mux $procmux$130838. + dead port 1/2 on $mux $procmux$130841. + dead port 1/2 on $mux $procmux$130844. + dead port 1/2 on $mux $procmux$130847. + dead port 1/2 on $mux $procmux$130850. + dead port 2/2 on $mux $procmux$130853. + dead port 1/2 on $mux $procmux$130859. + dead port 1/2 on $mux $procmux$130862. + dead port 1/2 on $mux $procmux$130865. + dead port 1/2 on $mux $procmux$130868. + dead port 1/2 on $mux $procmux$13087. + dead port 1/2 on $mux $procmux$130871. + dead port 2/2 on $mux $procmux$130874. + dead port 1/2 on $mux $procmux$130880. + dead port 1/2 on $mux $procmux$130883. + dead port 1/2 on $mux $procmux$130886. + dead port 1/2 on $mux $procmux$130889. + dead port 2/2 on $mux $procmux$13089. + dead port 1/2 on $mux $procmux$130892. + dead port 2/2 on $mux $procmux$130895. + dead port 1/2 on $mux $procmux$130901. + dead port 1/2 on $mux $procmux$130904. + dead port 1/2 on $mux $procmux$130907. + dead port 1/2 on $mux $procmux$130910. + dead port 1/2 on $mux $procmux$130913. + dead port 2/2 on $mux $procmux$130916. + dead port 1/2 on $mux $procmux$13092. + dead port 1/2 on $mux $procmux$130922. + dead port 1/2 on $mux $procmux$130925. + dead port 1/2 on $mux $procmux$130928. + dead port 1/2 on $mux $procmux$130931. + dead port 1/2 on $mux $procmux$130934. + dead port 2/2 on $mux $procmux$130937. + dead port 1/2 on $mux $procmux$130943. + dead port 1/2 on $mux $procmux$130946. + dead port 1/2 on $mux $procmux$130949. + dead port 1/2 on $mux $procmux$13095. + dead port 1/2 on $mux $procmux$130952. + dead port 1/2 on $mux $procmux$130955. + dead port 2/2 on $mux $procmux$130958. + dead port 1/2 on $mux $procmux$130964. + dead port 1/2 on $mux $procmux$130967. + dead port 1/2 on $mux $procmux$130970. + dead port 1/2 on $mux $procmux$130973. + dead port 1/2 on $mux $procmux$130976. + dead port 2/2 on $mux $procmux$130979. + dead port 1/2 on $mux $procmux$13098. + dead port 1/2 on $mux $procmux$130985. + dead port 1/2 on $mux $procmux$130988. + dead port 1/2 on $mux $procmux$130991. + dead port 1/2 on $mux $procmux$130994. + dead port 1/2 on $mux $procmux$130997. + dead port 2/2 on $mux $procmux$131000. + dead port 1/2 on $mux $procmux$13101. + dead port 1/2 on $mux $procmux$131027. + dead port 1/2 on $mux $procmux$131030. + dead port 1/2 on $mux $procmux$131033. + dead port 1/2 on $mux $procmux$131036. + dead port 1/2 on $mux $procmux$131039. + dead port 1/2 on $mux $procmux$13104. + dead port 2/2 on $mux $procmux$131042. + dead port 1/2 on $mux $procmux$131048. + dead port 1/2 on $mux $procmux$131051. + dead port 1/2 on $mux $procmux$131054. + dead port 1/2 on $mux $procmux$131057. + dead port 1/2 on $mux $procmux$131060. + dead port 2/2 on $mux $procmux$131063. + dead port 1/2 on $mux $procmux$131069. + dead port 1/2 on $mux $procmux$13107. + dead port 1/2 on $mux $procmux$131072. + dead port 1/2 on $mux $procmux$131075. + dead port 1/2 on $mux $procmux$131078. + dead port 1/2 on $mux $procmux$131081. + dead port 2/2 on $mux $procmux$131084. + dead port 1/2 on $mux $procmux$13110. + dead port 1/2 on $mux $procmux$13113. + dead port 1/2 on $mux $procmux$131153. + dead port 1/2 on $mux $procmux$131156. + dead port 1/2 on $mux $procmux$131159. + dead port 1/2 on $mux $procmux$13116. + dead port 1/2 on $mux $procmux$131162. + dead port 1/2 on $mux $procmux$131165. + dead port 2/2 on $mux $procmux$131168. + dead port 1/2 on $mux $procmux$131174. + dead port 1/2 on $mux $procmux$131177. + dead port 1/2 on $mux $procmux$131180. + dead port 1/2 on $mux $procmux$131183. + dead port 1/2 on $mux $procmux$131186. + dead port 2/2 on $mux $procmux$131189. + dead port 1/2 on $mux $procmux$13119. + dead port 1/2 on $mux $procmux$131195. + dead port 1/2 on $mux $procmux$131198. + dead port 1/2 on $mux $procmux$131201. + dead port 1/2 on $mux $procmux$131204. + dead port 1/2 on $mux $procmux$131207. + dead port 2/2 on $mux $procmux$131210. + dead port 1/2 on $mux $procmux$13122. + dead port 1/2 on $mux $procmux$131237. + dead port 1/2 on $mux $procmux$131240. + dead port 1/2 on $mux $procmux$131243. + dead port 1/2 on $mux $procmux$131246. + dead port 1/2 on $mux $procmux$131249. + dead port 1/2 on $mux $procmux$13125. + dead port 2/2 on $mux $procmux$131252. + dead port 1/2 on $mux $procmux$131258. + dead port 1/2 on $mux $procmux$131261. + dead port 1/2 on $mux $procmux$131264. + dead port 1/2 on $mux $procmux$131267. + dead port 1/2 on $mux $procmux$131270. + dead port 2/2 on $mux $procmux$131273. + dead port 1/2 on $mux $procmux$131277. + dead port 1/2 on $mux $procmux$13128. + dead port 1/2 on $mux $procmux$131280. + dead port 1/2 on $mux $procmux$131283. + dead port 1/2 on $mux $procmux$131286. + dead port 2/2 on $mux $procmux$131288. + dead port 1/2 on $mux $procmux$131291. + dead port 1/2 on $mux $procmux$131294. + dead port 1/2 on $mux $procmux$131297. + dead port 1/2 on $mux $procmux$131300. + dead port 2/2 on $mux $procmux$131303. + dead port 1/2 on $mux $procmux$131307. + dead port 1/2 on $mux $procmux$13131. + dead port 1/2 on $mux $procmux$131310. + dead port 1/2 on $mux $procmux$131313. + dead port 1/2 on $mux $procmux$131316. + dead port 2/2 on $mux $procmux$131318. + dead port 1/2 on $mux $procmux$131321. + dead port 1/2 on $mux $procmux$131324. + dead port 1/2 on $mux $procmux$131327. + dead port 1/2 on $mux $procmux$131330. + dead port 2/2 on $mux $procmux$131333. + dead port 1/2 on $mux $procmux$131337. + dead port 1/2 on $mux $procmux$13134. + dead port 1/2 on $mux $procmux$131340. + dead port 1/2 on $mux $procmux$131343. + dead port 1/2 on $mux $procmux$131346. + dead port 2/2 on $mux $procmux$131348. + dead port 1/2 on $mux $procmux$131351. + dead port 1/2 on $mux $procmux$131354. + dead port 1/2 on $mux $procmux$131357. + dead port 1/2 on $mux $procmux$131360. + dead port 2/2 on $mux $procmux$131363. + dead port 1/2 on $mux $procmux$13137. + dead port 1/2 on $mux $procmux$131370. + dead port 1/2 on $mux $procmux$131373. + dead port 1/2 on $mux $procmux$131376. + dead port 2/2 on $mux $procmux$131378. + dead port 1/2 on $mux $procmux$131381. + dead port 1/2 on $mux $procmux$131384. + dead port 1/2 on $mux $procmux$131387. + dead port 1/2 on $mux $procmux$131390. + dead port 2/2 on $mux $procmux$131393. + dead port 1/2 on $mux $procmux$13140. + dead port 1/2 on $mux $procmux$131400. + dead port 1/2 on $mux $procmux$131403. + dead port 1/2 on $mux $procmux$131406. + dead port 2/2 on $mux $procmux$131408. + dead port 1/2 on $mux $procmux$131411. + dead port 1/2 on $mux $procmux$131414. + dead port 1/2 on $mux $procmux$131417. + dead port 2/2 on $mux $procmux$13142. + dead port 1/2 on $mux $procmux$131420. + dead port 2/2 on $mux $procmux$131423. + dead port 1/2 on $mux $procmux$131430. + dead port 1/2 on $mux $procmux$131433. + dead port 1/2 on $mux $procmux$131436. + dead port 2/2 on $mux $procmux$131438. + dead port 1/2 on $mux $procmux$131441. + dead port 1/2 on $mux $procmux$131444. + dead port 1/2 on $mux $procmux$131447. + dead port 1/2 on $mux $procmux$13145. + dead port 1/2 on $mux $procmux$131450. + dead port 2/2 on $mux $procmux$131453. + dead port 1/2 on $mux $procmux$131460. + dead port 1/2 on $mux $procmux$131463. + dead port 1/2 on $mux $procmux$131466. + dead port 2/2 on $mux $procmux$131468. + dead port 1/2 on $mux $procmux$131471. + dead port 1/2 on $mux $procmux$131474. + dead port 1/2 on $mux $procmux$131477. + dead port 1/2 on $mux $procmux$13148. + dead port 1/2 on $mux $procmux$131480. + dead port 2/2 on $mux $procmux$131483. + dead port 1/2 on $mux $procmux$131490. + dead port 1/2 on $mux $procmux$131493. + dead port 1/2 on $mux $procmux$131496. + dead port 2/2 on $mux $procmux$131498. + dead port 1/2 on $mux $procmux$131501. + dead port 1/2 on $mux $procmux$131504. + dead port 1/2 on $mux $procmux$131507. + dead port 1/2 on $mux $procmux$13151. + dead port 1/2 on $mux $procmux$131510. + dead port 2/2 on $mux $procmux$131513. + dead port 1/2 on $mux $procmux$131520. + dead port 1/2 on $mux $procmux$131523. + dead port 1/2 on $mux $procmux$131526. + dead port 2/2 on $mux $procmux$131528. + dead port 1/2 on $mux $procmux$131531. + dead port 1/2 on $mux $procmux$131534. + dead port 1/2 on $mux $procmux$131537. + dead port 1/2 on $mux $procmux$13154. + dead port 1/2 on $mux $procmux$131540. + dead port 2/2 on $mux $procmux$131543. + dead port 1/2 on $mux $procmux$131550. + dead port 1/2 on $mux $procmux$131553. + dead port 1/2 on $mux $procmux$131556. + dead port 2/2 on $mux $procmux$131558. + dead port 1/2 on $mux $procmux$131561. + dead port 1/2 on $mux $procmux$131564. + dead port 1/2 on $mux $procmux$131567. + dead port 1/2 on $mux $procmux$13157. + dead port 1/2 on $mux $procmux$131570. + dead port 2/2 on $mux $procmux$131573. + dead port 1/2 on $mux $procmux$131580. + dead port 1/2 on $mux $procmux$131583. + dead port 1/2 on $mux $procmux$131586. + dead port 2/2 on $mux $procmux$131588. + dead port 1/2 on $mux $procmux$131591. + dead port 1/2 on $mux $procmux$131594. + dead port 1/2 on $mux $procmux$131597. + dead port 1/2 on $mux $procmux$13160. + dead port 1/2 on $mux $procmux$131600. + dead port 2/2 on $mux $procmux$131603. + dead port 1/2 on $mux $procmux$131610. + dead port 1/2 on $mux $procmux$131613. + dead port 1/2 on $mux $procmux$131616. + dead port 2/2 on $mux $procmux$131618. + dead port 1/2 on $mux $procmux$131621. + dead port 1/2 on $mux $procmux$131624. + dead port 1/2 on $mux $procmux$131627. + dead port 1/2 on $mux $procmux$13163. + dead port 1/2 on $mux $procmux$131630. + dead port 2/2 on $mux $procmux$131633. + dead port 1/2 on $mux $procmux$131640. + dead port 1/2 on $mux $procmux$131643. + dead port 1/2 on $mux $procmux$131646. + dead port 2/2 on $mux $procmux$131648. + dead port 1/2 on $mux $procmux$131651. + dead port 1/2 on $mux $procmux$131654. + dead port 1/2 on $mux $procmux$131657. + dead port 1/2 on $mux $procmux$13166. + dead port 1/2 on $mux $procmux$131660. + dead port 2/2 on $mux $procmux$131663. + dead port 1/2 on $mux $procmux$131670. + dead port 1/2 on $mux $procmux$131673. + dead port 2/2 on $mux $procmux$131675. + dead port 1/2 on $mux $procmux$131678. + dead port 1/2 on $mux $procmux$131681. + dead port 1/2 on $mux $procmux$131684. + dead port 1/2 on $mux $procmux$131687. + dead port 1/2 on $mux $procmux$13169. + dead port 2/2 on $mux $procmux$131690. + dead port 2/2 on $mux $procmux$131694. + dead port 1/2 on $mux $procmux$131697. + dead port 1/2 on $mux $procmux$131700. + dead port 2/2 on $mux $procmux$131702. + dead port 1/2 on $mux $procmux$131705. + dead port 1/2 on $mux $procmux$131708. + dead port 1/2 on $mux $procmux$131711. + dead port 1/2 on $mux $procmux$131714. + dead port 2/2 on $mux $procmux$131717. + dead port 1/2 on $mux $procmux$13172. + dead port 2/2 on $mux $procmux$131721. + dead port 1/2 on $mux $procmux$131724. + dead port 1/2 on $mux $procmux$131727. + dead port 2/2 on $mux $procmux$131729. + dead port 1/2 on $mux $procmux$131732. + dead port 1/2 on $mux $procmux$131735. + dead port 1/2 on $mux $procmux$131738. + dead port 1/2 on $mux $procmux$131741. + dead port 2/2 on $mux $procmux$131744. + dead port 1/2 on $mux $procmux$13175. + dead port 1/2 on $mux $procmux$131751. + dead port 1/2 on $mux $procmux$131754. + dead port 2/2 on $mux $procmux$131756. + dead port 1/2 on $mux $procmux$131759. + dead port 1/2 on $mux $procmux$131762. + dead port 1/2 on $mux $procmux$131765. + dead port 1/2 on $mux $procmux$131768. + dead port 2/2 on $mux $procmux$131771. + dead port 1/2 on $mux $procmux$131778. + dead port 2/2 on $mux $procmux$13178. + dead port 1/2 on $mux $procmux$131781. + dead port 2/2 on $mux $procmux$131783. + dead port 1/2 on $mux $procmux$131786. + dead port 1/2 on $mux $procmux$131789. + dead port 1/2 on $mux $procmux$131792. + dead port 1/2 on $mux $procmux$131795. + dead port 2/2 on $mux $procmux$131798. + dead port 2/2 on $mux $procmux$131802. + dead port 1/2 on $mux $procmux$131805. + dead port 1/2 on $mux $procmux$131808. + dead port 2/2 on $mux $procmux$131810. + dead port 1/2 on $mux $procmux$131813. + dead port 1/2 on $mux $procmux$131816. + dead port 1/2 on $mux $procmux$131819. + dead port 1/2 on $mux $procmux$131822. + dead port 2/2 on $mux $procmux$131825. + dead port 1/2 on $mux $procmux$131832. + dead port 1/2 on $mux $procmux$131835. + dead port 2/2 on $mux $procmux$131837. + dead port 1/2 on $mux $procmux$131840. + dead port 1/2 on $mux $procmux$131843. + dead port 1/2 on $mux $procmux$131846. + dead port 1/2 on $mux $procmux$131849. + dead port 2/2 on $mux $procmux$131852. + dead port 1/2 on $mux $procmux$131859. + dead port 1/2 on $mux $procmux$13186. + dead port 1/2 on $mux $procmux$131862. + dead port 2/2 on $mux $procmux$131864. + dead port 1/2 on $mux $procmux$131867. + dead port 1/2 on $mux $procmux$131870. + dead port 1/2 on $mux $procmux$131873. + dead port 1/2 on $mux $procmux$131876. + dead port 2/2 on $mux $procmux$131879. + dead port 2/2 on $mux $procmux$13188. + dead port 1/2 on $mux $procmux$131886. + dead port 1/2 on $mux $procmux$131889. + dead port 2/2 on $mux $procmux$131891. + dead port 1/2 on $mux $procmux$131894. + dead port 1/2 on $mux $procmux$131897. + dead port 1/2 on $mux $procmux$131900. + dead port 1/2 on $mux $procmux$131903. + dead port 2/2 on $mux $procmux$131906. + dead port 1/2 on $mux $procmux$13191. + dead port 1/2 on $mux $procmux$131913. + dead port 1/2 on $mux $procmux$131916. + dead port 2/2 on $mux $procmux$131918. + dead port 1/2 on $mux $procmux$131921. + dead port 1/2 on $mux $procmux$131924. + dead port 1/2 on $mux $procmux$131927. + dead port 1/2 on $mux $procmux$131930. + dead port 2/2 on $mux $procmux$131933. + dead port 1/2 on $mux $procmux$13194. + dead port 1/2 on $mux $procmux$13197. + dead port 1/2 on $mux $procmux$13200. + dead port 1/2 on $mux $procmux$13203. + dead port 1/2 on $mux $procmux$13206. + dead port 1/2 on $mux $procmux$13209. + dead port 1/2 on $mux $procmux$13212. + dead port 1/2 on $mux $procmux$13215. + dead port 1/2 on $mux $procmux$13218. + dead port 1/2 on $mux $procmux$132180. + dead port 2/2 on $mux $procmux$132182. + dead port 1/2 on $mux $procmux$132185. + dead port 1/2 on $mux $procmux$132188. + dead port 1/2 on $mux $procmux$132191. + dead port 1/2 on $mux $procmux$132194. + dead port 2/2 on $mux $procmux$132197. + dead port 1/2 on $mux $procmux$132204. + dead port 2/2 on $mux $procmux$132206. + dead port 1/2 on $mux $procmux$132209. + dead port 1/2 on $mux $procmux$13221. + dead port 1/2 on $mux $procmux$132212. + dead port 1/2 on $mux $procmux$132215. + dead port 1/2 on $mux $procmux$132218. + dead port 2/2 on $mux $procmux$132221. + dead port 1/2 on $mux $procmux$13224. + dead port 1/2 on $mux $procmux$13227. + dead port 1/2 on $mux $procmux$13230. + dead port 1/2 on $mux $procmux$13233. + dead port 1/2 on $mux $procmux$13236. + dead port 1/2 on $mux $procmux$13239. + dead port 2/2 on $mux $procmux$132398. + dead port 1/2 on $mux $procmux$132401. + dead port 1/2 on $mux $procmux$132404. + dead port 1/2 on $mux $procmux$132407. + dead port 2/2 on $mux $procmux$13241. + dead port 1/2 on $mux $procmux$132410. + dead port 2/2 on $mux $procmux$132413. + dead port 2/2 on $mux $procmux$132419. + dead port 1/2 on $mux $procmux$132422. + dead port 1/2 on $mux $procmux$132425. + dead port 1/2 on $mux $procmux$132428. + dead port 1/2 on $mux $procmux$132431. + dead port 2/2 on $mux $procmux$132434. + dead port 1/2 on $mux $procmux$13244. + dead port 1/2 on $mux $procmux$13247. + dead port 1/2 on $mux $procmux$13250. + dead port 1/2 on $mux $procmux$13253. + dead port 1/2 on $mux $procmux$132551. + dead port 1/2 on $mux $procmux$132554. + dead port 1/2 on $mux $procmux$132557. + dead port 1/2 on $mux $procmux$13256. + dead port 1/2 on $mux $procmux$132560. + dead port 2/2 on $mux $procmux$132563. + dead port 1/2 on $mux $procmux$132569. + dead port 1/2 on $mux $procmux$132572. + dead port 1/2 on $mux $procmux$132575. + dead port 1/2 on $mux $procmux$132578. + dead port 2/2 on $mux $procmux$132581. + dead port 1/2 on $mux $procmux$13259. + dead port 1/2 on $mux $procmux$13262. + dead port 1/2 on $mux $procmux$13265. + dead port 1/2 on $mux $procmux$13268. + dead port 1/2 on $mux $procmux$13271. + dead port 1/2 on $mux $procmux$13274. + dead port 2/2 on $mux $procmux$13277. + dead port 1/2 on $mux $procmux$13285. + dead port 2/2 on $mux $procmux$13287. + dead port 1/2 on $mux $procmux$13290. + dead port 1/2 on $mux $procmux$13293. + dead port 1/2 on $mux $procmux$13296. + dead port 1/2 on $mux $procmux$13299. + dead port 1/2 on $mux $procmux$13302. + dead port 1/2 on $mux $procmux$13305. + dead port 1/2 on $mux $procmux$13308. + dead port 1/2 on $mux $procmux$13311. + dead port 1/2 on $mux $procmux$13314. + dead port 1/2 on $mux $procmux$13317. + dead port 1/2 on $mux $procmux$13320. + dead port 1/2 on $mux $procmux$13323. + dead port 1/2 on $mux $procmux$13326. + dead port 1/2 on $mux $procmux$13329. + dead port 1/2 on $mux $procmux$13332. + dead port 1/2 on $mux $procmux$13335. + dead port 1/2 on $mux $procmux$13338. + dead port 2/2 on $mux $procmux$13340. + dead port 1/2 on $mux $procmux$13343. + dead port 1/2 on $mux $procmux$13346. + dead port 1/2 on $mux $procmux$13349. + dead port 1/2 on $mux $procmux$13352. + dead port 1/2 on $mux $procmux$13355. + dead port 1/2 on $mux $procmux$13358. + dead port 1/2 on $mux $procmux$13361. + dead port 1/2 on $mux $procmux$13364. + dead port 1/2 on $mux $procmux$13367. + dead port 1/2 on $mux $procmux$13370. + dead port 1/2 on $mux $procmux$13373. + dead port 2/2 on $mux $procmux$13376. + dead port 2/2 on $mux $procmux$13383. + dead port 1/2 on $mux $procmux$13386. + dead port 1/2 on $mux $procmux$13389. + dead port 1/2 on $mux $procmux$13392. + dead port 1/2 on $mux $procmux$13395. + dead port 1/2 on $mux $procmux$13398. + dead port 1/2 on $mux $procmux$13401. + dead port 1/2 on $mux $procmux$13404. + dead port 1/2 on $mux $procmux$13407. + dead port 1/2 on $mux $procmux$134099. + dead port 1/2 on $mux $procmux$13410. + dead port 1/2 on $mux $procmux$134102. + dead port 1/2 on $mux $procmux$134105. + dead port 1/2 on $mux $procmux$134108. + dead port 2/2 on $mux $procmux$134111. + dead port 1/2 on $mux $procmux$134117. + dead port 1/2 on $mux $procmux$134120. + dead port 1/2 on $mux $procmux$134123. + dead port 1/2 on $mux $procmux$134126. + dead port 2/2 on $mux $procmux$134129. + dead port 1/2 on $mux $procmux$13413. + dead port 1/2 on $mux $procmux$134153. + dead port 1/2 on $mux $procmux$134156. + dead port 1/2 on $mux $procmux$134159. + dead port 1/2 on $mux $procmux$13416. + dead port 1/2 on $mux $procmux$134162. + dead port 2/2 on $mux $procmux$134165. + dead port 1/2 on $mux $procmux$134171. + dead port 1/2 on $mux $procmux$134174. + dead port 1/2 on $mux $procmux$134177. + dead port 1/2 on $mux $procmux$134180. + dead port 2/2 on $mux $procmux$134183. + dead port 1/2 on $mux $procmux$134189. + dead port 1/2 on $mux $procmux$13419. + dead port 1/2 on $mux $procmux$134192. + dead port 1/2 on $mux $procmux$134195. + dead port 1/2 on $mux $procmux$134198. + dead port 2/2 on $mux $procmux$134201. + dead port 1/2 on $mux $procmux$134207. + dead port 1/2 on $mux $procmux$134210. + dead port 1/2 on $mux $procmux$134213. + dead port 1/2 on $mux $procmux$134216. + dead port 2/2 on $mux $procmux$134219. + dead port 1/2 on $mux $procmux$13422. + dead port 1/2 on $mux $procmux$134225. + dead port 1/2 on $mux $procmux$134228. + dead port 1/2 on $mux $procmux$134231. + dead port 1/2 on $mux $procmux$134234. + dead port 2/2 on $mux $procmux$134237. + dead port 1/2 on $mux $procmux$134243. + dead port 1/2 on $mux $procmux$134246. + dead port 1/2 on $mux $procmux$134249. + dead port 1/2 on $mux $procmux$13425. + dead port 1/2 on $mux $procmux$134252. + dead port 2/2 on $mux $procmux$134255. + dead port 1/2 on $mux $procmux$134261. + dead port 1/2 on $mux $procmux$134264. + dead port 1/2 on $mux $procmux$134267. + dead port 1/2 on $mux $procmux$134270. + dead port 2/2 on $mux $procmux$134273. + dead port 1/2 on $mux $procmux$13428. + dead port 1/2 on $mux $procmux$13431. + dead port 1/2 on $mux $procmux$134315. + dead port 1/2 on $mux $procmux$134318. + dead port 1/2 on $mux $procmux$134321. + dead port 1/2 on $mux $procmux$134324. + dead port 2/2 on $mux $procmux$134327. + dead port 1/2 on $mux $procmux$134333. + dead port 1/2 on $mux $procmux$134336. + dead port 1/2 on $mux $procmux$134339. + dead port 1/2 on $mux $procmux$13434. + dead port 1/2 on $mux $procmux$134342. + dead port 2/2 on $mux $procmux$134345. + dead port 1/2 on $mux $procmux$134351. + dead port 1/2 on $mux $procmux$134354. + dead port 1/2 on $mux $procmux$134357. + dead port 2/2 on $mux $procmux$13436. + dead port 1/2 on $mux $procmux$134360. + dead port 2/2 on $mux $procmux$134363. + dead port 1/2 on $mux $procmux$134369. + dead port 1/2 on $mux $procmux$134372. + dead port 1/2 on $mux $procmux$134375. + dead port 1/2 on $mux $procmux$134378. + dead port 2/2 on $mux $procmux$134381. + dead port 1/2 on $mux $procmux$134387. + dead port 1/2 on $mux $procmux$13439. + dead port 1/2 on $mux $procmux$134390. + dead port 1/2 on $mux $procmux$134393. + dead port 1/2 on $mux $procmux$134396. + dead port 2/2 on $mux $procmux$134399. + dead port 1/2 on $mux $procmux$134405. + dead port 1/2 on $mux $procmux$134408. + dead port 1/2 on $mux $procmux$134411. + dead port 1/2 on $mux $procmux$134414. + dead port 2/2 on $mux $procmux$134417. + dead port 1/2 on $mux $procmux$13442. + dead port 1/2 on $mux $procmux$134423. + dead port 1/2 on $mux $procmux$134426. + dead port 1/2 on $mux $procmux$134429. + dead port 1/2 on $mux $procmux$134432. + dead port 2/2 on $mux $procmux$134435. + dead port 1/2 on $mux $procmux$134441. + dead port 1/2 on $mux $procmux$134444. + dead port 1/2 on $mux $procmux$134447. + dead port 1/2 on $mux $procmux$13445. + dead port 1/2 on $mux $procmux$134450. + dead port 2/2 on $mux $procmux$134453. + dead port 1/2 on $mux $procmux$134477. + dead port 1/2 on $mux $procmux$13448. + dead port 1/2 on $mux $procmux$134480. + dead port 1/2 on $mux $procmux$134483. + dead port 1/2 on $mux $procmux$134486. + dead port 2/2 on $mux $procmux$134489. + dead port 1/2 on $mux $procmux$134495. + dead port 1/2 on $mux $procmux$134498. + dead port 1/2 on $mux $procmux$134501. + dead port 1/2 on $mux $procmux$134504. + dead port 2/2 on $mux $procmux$134507. + dead port 1/2 on $mux $procmux$13451. + dead port 1/2 on $mux $procmux$134513. + dead port 1/2 on $mux $procmux$134516. + dead port 1/2 on $mux $procmux$134519. + dead port 1/2 on $mux $procmux$134522. + dead port 2/2 on $mux $procmux$134525. + dead port 1/2 on $mux $procmux$13454. + dead port 1/2 on $mux $procmux$13457. + dead port 1/2 on $mux $procmux$134585. + dead port 1/2 on $mux $procmux$134588. + dead port 1/2 on $mux $procmux$134591. + dead port 1/2 on $mux $procmux$134594. + dead port 2/2 on $mux $procmux$134597. + dead port 1/2 on $mux $procmux$13460. + dead port 1/2 on $mux $procmux$134603. + dead port 1/2 on $mux $procmux$134606. + dead port 1/2 on $mux $procmux$134609. + dead port 1/2 on $mux $procmux$134612. + dead port 2/2 on $mux $procmux$134615. + dead port 1/2 on $mux $procmux$134621. + dead port 1/2 on $mux $procmux$134624. + dead port 1/2 on $mux $procmux$134627. + dead port 1/2 on $mux $procmux$13463. + dead port 1/2 on $mux $procmux$134630. + dead port 2/2 on $mux $procmux$134633. + dead port 1/2 on $mux $procmux$134639. + dead port 1/2 on $mux $procmux$134642. + dead port 1/2 on $mux $procmux$134645. + dead port 1/2 on $mux $procmux$134648. + dead port 2/2 on $mux $procmux$134651. + dead port 1/2 on $mux $procmux$134657. + dead port 1/2 on $mux $procmux$13466. + dead port 1/2 on $mux $procmux$134660. + dead port 1/2 on $mux $procmux$134663. + dead port 1/2 on $mux $procmux$134666. + dead port 2/2 on $mux $procmux$134669. + dead port 1/2 on $mux $procmux$13469. + dead port 2/2 on $mux $procmux$13472. + dead port 2/2 on $mux $procmux$13575. + dead port 1/2 on $mux $procmux$13578. + dead port 1/2 on $mux $procmux$13581. + dead port 1/2 on $mux $procmux$13584. + dead port 1/2 on $mux $procmux$13587. + dead port 1/2 on $mux $procmux$13590. + dead port 1/2 on $mux $procmux$13593. + dead port 1/2 on $mux $procmux$13596. + dead port 1/2 on $mux $procmux$13599. + dead port 1/2 on $mux $procmux$13602. + dead port 1/2 on $mux $procmux$13605. + dead port 1/2 on $mux $procmux$13608. + dead port 1/2 on $mux $procmux$13611. + dead port 1/2 on $mux $procmux$13614. + dead port 1/2 on $mux $procmux$13617. + dead port 1/2 on $mux $procmux$13620. + dead port 1/2 on $mux $procmux$13623. + dead port 1/2 on $mux $procmux$136232. + dead port 1/2 on $mux $procmux$136235. + dead port 1/2 on $mux $procmux$136238. + dead port 2/2 on $mux $procmux$136241. + dead port 1/2 on $mux $procmux$136247. + dead port 1/2 on $mux $procmux$136250. + dead port 1/2 on $mux $procmux$136253. + dead port 2/2 on $mux $procmux$136256. + dead port 1/2 on $mux $procmux$13626. + dead port 2/2 on $mux $procmux$13628. + dead port 1/2 on $mux $procmux$136292. + dead port 1/2 on $mux $procmux$136295. + dead port 1/2 on $mux $procmux$136298. + dead port 2/2 on $mux $procmux$136301. + dead port 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$procmux$136385. + dead port 1/2 on $mux $procmux$136388. + dead port 2/2 on $mux $procmux$136391. + dead port 1/2 on $mux $procmux$13640. + dead port 1/2 on $mux $procmux$136427. + dead port 1/2 on $mux $procmux$13643. + dead port 1/2 on $mux $procmux$136430. + dead port 1/2 on $mux $procmux$136433. + dead port 2/2 on $mux $procmux$136436. + dead port 1/2 on $mux $procmux$136442. + dead port 1/2 on $mux $procmux$136445. + dead port 1/2 on $mux $procmux$136448. + dead port 2/2 on $mux $procmux$136451. + dead port 1/2 on $mux $procmux$136457. + dead port 1/2 on $mux $procmux$13646. + dead port 1/2 on $mux $procmux$136460. + dead port 1/2 on $mux $procmux$136463. + dead port 2/2 on $mux $procmux$136466. + dead port 1/2 on $mux $procmux$136472. + dead port 1/2 on $mux $procmux$136475. + dead port 1/2 on $mux $procmux$136478. + dead port 2/2 on $mux $procmux$136481. + dead port 1/2 on $mux $procmux$136487. + dead port 1/2 on $mux $procmux$13649. + dead port 1/2 on $mux $procmux$136490. + dead port 1/2 on $mux $procmux$136493. + dead port 2/2 on $mux $procmux$136496. + dead port 1/2 on $mux $procmux$136502. + dead port 1/2 on $mux $procmux$136505. + dead port 1/2 on $mux $procmux$136508. + dead port 2/2 on $mux $procmux$136511. + dead port 1/2 on $mux $procmux$136517. + dead port 1/2 on $mux $procmux$13652. + dead port 1/2 on $mux $procmux$136520. + dead port 1/2 on $mux $procmux$136523. + dead port 2/2 on $mux $procmux$136526. + dead port 1/2 on $mux $procmux$136532. + dead port 1/2 on $mux $procmux$136535. + dead port 1/2 on $mux $procmux$136538. + dead port 2/2 on $mux $procmux$136541. + dead port 1/2 on $mux $procmux$136547. + dead port 1/2 on $mux $procmux$13655. + dead port 1/2 on $mux $procmux$136550. + dead port 1/2 on $mux $procmux$136553. + dead port 2/2 on $mux $procmux$136556. + dead port 1/2 on $mux $procmux$136562. + dead port 1/2 on $mux $procmux$136565. + dead port 1/2 on $mux $procmux$136568. + dead port 2/2 on $mux $procmux$136571. + dead port 1/2 on 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$procmux$136712. + dead port 1/2 on $mux $procmux$136715. + dead port 1/2 on $mux $procmux$136718. + dead port 2/2 on $mux $procmux$136721. + dead port 1/2 on $mux $procmux$13674. + dead port 1/2 on $mux $procmux$136742. + dead port 1/2 on $mux $procmux$136745. + dead port 1/2 on $mux $procmux$136748. + dead port 2/2 on $mux $procmux$136751. + dead port 1/2 on $mux $procmux$136757. + dead port 1/2 on $mux $procmux$136760. + dead port 1/2 on $mux $procmux$136763. + dead port 2/2 on $mux $procmux$136766. + dead port 1/2 on $mux $procmux$13677. + dead port 1/2 on $mux $procmux$136770. + dead port 1/2 on $mux $procmux$136773. + dead port 1/2 on $mux $procmux$136776. + dead port 1/2 on $mux $procmux$136779. + dead port 2/2 on $mux $procmux$136781. + dead port 1/2 on $mux $procmux$136784. + dead port 1/2 on $mux $procmux$136787. + dead port 2/2 on $mux $procmux$136790. + dead port 1/2 on $mux $procmux$136794. + dead port 1/2 on $mux $procmux$136797. + dead port 1/2 on $mux $procmux$13680. + dead port 1/2 on $mux $procmux$136800. + dead port 1/2 on $mux $procmux$136803. + dead port 2/2 on $mux $procmux$136805. + dead port 1/2 on $mux $procmux$136808. + dead port 1/2 on $mux $procmux$136811. + dead port 2/2 on $mux $procmux$136814. + dead port 1/2 on $mux $procmux$136818. + dead port 1/2 on $mux $procmux$136821. + dead port 1/2 on $mux $procmux$136824. + dead port 1/2 on $mux $procmux$136827. + dead port 2/2 on $mux $procmux$136829. + dead port 1/2 on $mux $procmux$13683. + dead port 1/2 on $mux $procmux$136832. + dead port 1/2 on $mux $procmux$136835. + dead port 2/2 on $mux $procmux$136838. + dead port 1/2 on $mux $procmux$136845. + dead port 1/2 on $mux $procmux$136848. + dead port 1/2 on $mux $procmux$136851. + dead port 2/2 on $mux $procmux$136853. + dead port 1/2 on $mux $procmux$136856. + dead port 1/2 on $mux $procmux$136859. + dead port 1/2 on $mux $procmux$13686. + dead port 2/2 on $mux $procmux$136862. + dead port 1/2 on $mux $procmux$136869. + dead port 1/2 on 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$procmux$136947. + dead port 2/2 on $mux $procmux$136949. + dead port 1/2 on $mux $procmux$13695. + dead port 1/2 on $mux $procmux$136952. + dead port 1/2 on $mux $procmux$136955. + dead port 2/2 on $mux $procmux$136958. + dead port 1/2 on $mux $procmux$136965. + dead port 1/2 on $mux $procmux$136968. + dead port 1/2 on $mux $procmux$136971. + dead port 2/2 on $mux $procmux$136973. + dead port 1/2 on $mux $procmux$136976. + dead port 1/2 on $mux $procmux$136979. + dead port 1/2 on $mux $procmux$13698. + dead port 2/2 on $mux $procmux$136982. + dead port 1/2 on $mux $procmux$136989. + dead port 1/2 on $mux $procmux$136992. + dead port 1/2 on $mux $procmux$136995. + dead port 2/2 on $mux $procmux$136997. + dead port 1/2 on $mux $procmux$137000. + dead port 1/2 on $mux $procmux$137003. + dead port 2/2 on $mux $procmux$137006. + dead port 1/2 on $mux $procmux$13701. + dead port 1/2 on $mux $procmux$137013. + dead port 1/2 on $mux $procmux$137016. + dead port 1/2 on $mux $procmux$137019. + dead port 2/2 on $mux $procmux$137021. + dead port 1/2 on $mux $procmux$137024. + dead port 1/2 on $mux $procmux$137027. + dead port 2/2 on $mux $procmux$137030. + dead port 1/2 on $mux $procmux$137037. + dead port 1/2 on $mux $procmux$13704. + dead port 1/2 on $mux $procmux$137040. + dead port 1/2 on $mux $procmux$137043. + dead port 2/2 on $mux $procmux$137045. + dead port 1/2 on $mux $procmux$137048. + dead port 1/2 on $mux $procmux$137051. + dead port 2/2 on $mux $procmux$137054. + dead port 1/2 on $mux $procmux$137061. + dead port 1/2 on $mux $procmux$137064. + dead port 1/2 on $mux $procmux$137067. + dead port 2/2 on $mux $procmux$137069. + dead port 1/2 on $mux $procmux$13707. + dead port 1/2 on $mux $procmux$137072. + dead port 1/2 on $mux $procmux$137075. + dead port 2/2 on $mux $procmux$137078. + dead port 1/2 on $mux $procmux$137085. + dead port 1/2 on $mux $procmux$137088. + dead port 2/2 on $mux $procmux$137090. + dead port 1/2 on $mux $procmux$137093. + dead port 1/2 on $mux $procmux$137096. + dead port 2/2 on $mux $procmux$137099. + dead port 1/2 on $mux $procmux$13710. + dead port 2/2 on $mux $procmux$137103. + dead port 1/2 on $mux $procmux$137106. + dead port 1/2 on $mux $procmux$137109. + dead port 2/2 on $mux $procmux$137111. + dead port 1/2 on $mux $procmux$137114. + dead port 1/2 on $mux $procmux$137117. + dead port 2/2 on $mux $procmux$137120. + dead port 2/2 on $mux $procmux$137124. + dead port 1/2 on $mux $procmux$137127. + dead port 1/2 on $mux $procmux$13713. + dead port 1/2 on $mux $procmux$137130. + dead port 2/2 on $mux $procmux$137132. + dead port 1/2 on $mux $procmux$137135. + dead port 1/2 on $mux $procmux$137138. + dead port 2/2 on $mux $procmux$137141. + dead port 1/2 on $mux $procmux$137148. + dead port 1/2 on $mux $procmux$137151. + dead port 2/2 on $mux $procmux$137153. + dead port 1/2 on $mux $procmux$137156. + dead port 1/2 on $mux $procmux$137159. + dead port 1/2 on $mux $procmux$13716. + dead port 2/2 on $mux $procmux$137162. + dead port 1/2 on $mux $procmux$137169. + dead port 1/2 on $mux $procmux$137172. + dead port 2/2 on $mux $procmux$137174. + dead port 1/2 on $mux $procmux$137177. + dead port 1/2 on $mux $procmux$137180. + dead port 2/2 on $mux $procmux$137183. + dead port 2/2 on $mux $procmux$137187. + dead port 1/2 on $mux $procmux$13719. + dead port 1/2 on $mux $procmux$137190. + dead port 1/2 on $mux $procmux$137193. + dead port 2/2 on $mux $procmux$137195. + dead port 1/2 on $mux $procmux$137198. + dead port 1/2 on $mux $procmux$137201. + dead port 2/2 on $mux $procmux$137204. + dead port 1/2 on $mux $procmux$137211. + dead port 1/2 on $mux $procmux$137214. + dead port 2/2 on $mux $procmux$137216. + dead port 1/2 on $mux $procmux$137219. + dead port 1/2 on $mux $procmux$13722. + dead port 1/2 on $mux $procmux$137222. + dead port 2/2 on $mux $procmux$137225. + dead port 1/2 on $mux $procmux$137232. + dead port 1/2 on $mux $procmux$137235. + dead port 2/2 on $mux $procmux$137237. + dead port 2/2 on $mux $procmux$13724. + dead port 1/2 on $mux $procmux$137240. + dead port 1/2 on $mux $procmux$137243. + dead port 2/2 on $mux $procmux$137246. + dead port 1/2 on $mux $procmux$137253. + dead port 1/2 on $mux $procmux$137256. + dead port 2/2 on $mux $procmux$137258. + dead port 1/2 on $mux $procmux$137261. + dead port 1/2 on $mux $procmux$137264. + dead port 2/2 on $mux $procmux$137267. + dead port 1/2 on $mux $procmux$13727. + dead port 1/2 on $mux $procmux$137274. + dead port 1/2 on $mux $procmux$137277. + dead port 2/2 on $mux $procmux$137279. + dead port 1/2 on $mux $procmux$137282. + dead port 1/2 on $mux $procmux$137285. + dead port 2/2 on $mux $procmux$137288. + dead port 1/2 on $mux $procmux$137295. + dead port 1/2 on $mux $procmux$137298. + dead port 1/2 on $mux $procmux$13730. + dead port 2/2 on $mux $procmux$137300. + dead port 1/2 on $mux $procmux$137303. + dead port 1/2 on $mux $procmux$137306. + dead port 2/2 on $mux $procmux$137309. + dead port 1/2 on $mux $procmux$137316. + dead port 1/2 on $mux $procmux$137319. + dead port 2/2 on $mux $procmux$137321. + dead port 1/2 on $mux $procmux$137324. + dead port 1/2 on $mux $procmux$137327. + dead port 1/2 on $mux $procmux$13733. + dead port 2/2 on $mux $procmux$137330. + dead port 1/2 on $mux $procmux$13736. + dead port 1/2 on $mux $procmux$13739. + dead port 1/2 on $mux $procmux$13742. + dead port 1/2 on $mux $procmux$13745. + dead port 1/2 on $mux $procmux$13748. + dead port 1/2 on $mux $procmux$13751. + dead port 1/2 on $mux $procmux$137520. + dead port 2/2 on $mux $procmux$137522. + dead port 1/2 on $mux $procmux$137525. + dead port 1/2 on $mux $procmux$137528. + dead port 2/2 on $mux $procmux$137531. + dead port 1/2 on $mux $procmux$137538. + dead port 1/2 on $mux $procmux$13754. + dead port 2/2 on $mux $procmux$137540. + dead port 1/2 on $mux $procmux$137543. + dead port 1/2 on $mux $procmux$137546. + dead port 2/2 on $mux $procmux$137549. + dead port 1/2 on $mux $procmux$13757. + dead port 1/2 on $mux $procmux$137592. + dead port 2/2 on $mux $procmux$137594. + dead port 1/2 on $mux $procmux$137597. + dead port 2/2 on $mux $procmux$13760. + dead port 1/2 on $mux $procmux$137600. + dead port 2/2 on $mux $procmux$137603. + dead port 2/2 on $mux $procmux$13767. + dead port 2/2 on $mux $procmux$137699. + dead port 1/2 on $mux $procmux$13770. + dead port 1/2 on $mux $procmux$137702. + dead port 1/2 on $mux $procmux$137705. + dead port 2/2 on $mux $procmux$137708. + dead port 2/2 on $mux $procmux$137714. + dead port 1/2 on $mux $procmux$137717. + dead port 1/2 on $mux $procmux$137720. + dead port 2/2 on $mux $procmux$137723. + dead port 1/2 on $mux $procmux$13773. + dead port 2/2 on $mux $procmux$137759. + dead port 1/2 on $mux $procmux$13776. + dead port 1/2 on $mux $procmux$137762. + dead port 1/2 on $mux $procmux$137765. + dead port 2/2 on $mux $procmux$137768. + dead port 1/2 on $mux $procmux$13779. + dead port 1/2 on $mux $procmux$13782. + dead port 1/2 on $mux $procmux$137822. + dead port 1/2 on $mux $procmux$137825. + dead port 2/2 on $mux $procmux$137828. + dead port 1/2 on $mux $procmux$137834. + dead port 1/2 on $mux $procmux$137837. + dead port 2/2 on $mux $procmux$137840. + dead port 1/2 on $mux $procmux$13785. + dead port 1/2 on $mux $procmux$137870. + dead port 1/2 on $mux $procmux$137873. + dead port 2/2 on $mux $procmux$137876. + dead port 1/2 on $mux $procmux$13788. + dead port 1/2 on $mux $procmux$13791. + dead port 1/2 on $mux $procmux$13794. + dead port 1/2 on $mux $procmux$13797. + dead port 1/2 on $mux $procmux$13800. + dead port 1/2 on $mux $procmux$13803. + dead port 1/2 on $mux $procmux$13806. + dead port 1/2 on $mux $procmux$13809. + dead port 1/2 on $mux $procmux$13812. + dead port 1/2 on $mux $procmux$13815. + dead port 1/2 on $mux $procmux$13818. + dead port 2/2 on $mux $procmux$13820. + dead port 1/2 on $mux $procmux$13823. + dead port 1/2 on $mux $procmux$13826. + dead port 1/2 on $mux $procmux$13829. + dead port 1/2 on $mux $procmux$13832. + dead port 1/2 on $mux $procmux$13835. + dead port 1/2 on $mux $procmux$13838. + dead port 1/2 on $mux $procmux$13841. + dead port 1/2 on $mux $procmux$13844. + dead port 1/2 on $mux $procmux$13847. + dead port 1/2 on $mux $procmux$13850. + dead port 1/2 on $mux $procmux$13853. + dead port 2/2 on $mux $procmux$13856. + dead port 1/2 on $mux $procmux$13863. + dead port 1/2 on $mux $procmux$13866. + dead port 1/2 on $mux $procmux$13869. + dead port 1/2 on $mux $procmux$13872. + dead port 1/2 on $mux $procmux$13875. + dead port 1/2 on $mux $procmux$13878. + dead port 1/2 on $mux $procmux$13881. + dead port 1/2 on $mux $procmux$13884. + dead port 1/2 on $mux $procmux$13887. + dead port 1/2 on $mux $procmux$13890. + dead port 1/2 on $mux $procmux$13893. + dead port 1/2 on $mux $procmux$13896. + dead port 1/2 on $mux $procmux$138986. + dead port 1/2 on $mux $procmux$138989. + dead port 1/2 on $mux $procmux$13899. + dead port 2/2 on $mux $procmux$138992. + dead port 1/2 on $mux $procmux$138998. + dead port 1/2 on $mux $procmux$139001. + dead port 2/2 on $mux $procmux$139004. + dead port 1/2 on $mux $procmux$139010. + dead port 1/2 on $mux $procmux$139013. + dead port 2/2 on $mux $procmux$139016. + dead port 1/2 on $mux $procmux$13902. + dead port 1/2 on $mux $procmux$139022. + dead port 1/2 on $mux $procmux$139025. + dead port 2/2 on $mux $procmux$139028. + dead port 1/2 on $mux $procmux$139034. + dead port 1/2 on $mux $procmux$139037. + dead port 2/2 on $mux $procmux$139040. + dead port 1/2 on $mux $procmux$139046. + dead port 1/2 on $mux $procmux$139049. + dead port 1/2 on $mux $procmux$13905. + dead port 2/2 on $mux $procmux$139052. + dead port 1/2 on $mux $procmux$139058. + dead port 1/2 on $mux $procmux$139061. + dead port 2/2 on $mux $procmux$139064. + dead port 1/2 on $mux $procmux$13908. + dead port 1/2 on $mux $procmux$139094. + dead port 1/2 on $mux $procmux$139097. + dead port 2/2 on $mux $procmux$139100. + dead port 1/2 on $mux $procmux$139106. + dead port 1/2 on $mux $procmux$139109. + dead port 1/2 on $mux $procmux$13911. + dead port 2/2 on $mux $procmux$139112. + dead port 1/2 on $mux $procmux$139118. + dead port 1/2 on $mux $procmux$139121. + dead port 2/2 on $mux $procmux$139124. + dead port 2/2 on $mux $procmux$13913. + dead port 1/2 on $mux $procmux$139130. + dead port 1/2 on $mux $procmux$139133. + dead port 2/2 on $mux $procmux$139136. + dead port 1/2 on $mux $procmux$139142. + dead port 1/2 on $mux $procmux$139145. + dead port 2/2 on $mux $procmux$139148. + dead port 1/2 on $mux $procmux$139154. + dead port 1/2 on $mux $procmux$139157. + dead port 1/2 on $mux $procmux$13916. + dead port 2/2 on $mux $procmux$139160. + dead port 1/2 on $mux $procmux$139166. + dead port 1/2 on $mux $procmux$139169. + dead port 2/2 on $mux $procmux$139172. + dead port 1/2 on $mux $procmux$139178. + dead port 1/2 on $mux $procmux$139181. + dead port 2/2 on $mux $procmux$139184. + dead port 1/2 on $mux $procmux$13919. + dead port 1/2 on $mux $procmux$139190. + dead port 1/2 on $mux $procmux$139193. + dead port 2/2 on $mux $procmux$139196. + dead port 1/2 on $mux $procmux$139202. + dead port 1/2 on $mux $procmux$139205. + dead port 2/2 on $mux $procmux$139208. + dead port 1/2 on $mux $procmux$13922. + dead port 1/2 on $mux $procmux$139226. + dead port 1/2 on $mux $procmux$139229. + dead port 2/2 on $mux $procmux$139232. + dead port 1/2 on $mux $procmux$139238. + dead port 1/2 on $mux $procmux$139241. + dead port 2/2 on $mux $procmux$139244. + dead port 1/2 on $mux $procmux$13925. + dead port 1/2 on $mux $procmux$139250. + dead port 1/2 on $mux $procmux$139253. + dead port 2/2 on $mux $procmux$139256. + dead port 1/2 on $mux $procmux$13928. + dead port 1/2 on $mux $procmux$139298. + dead port 1/2 on $mux $procmux$139301. + dead port 2/2 on $mux $procmux$139304. + dead port 1/2 on $mux $procmux$13931. + dead port 1/2 on $mux $procmux$139310. + dead port 1/2 on $mux $procmux$139313. + dead port 2/2 on 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$procmux$139388. + dead port 1/2 on $mux $procmux$139391. + dead port 2/2 on $mux $procmux$139394. + dead port 1/2 on $mux $procmux$139399. + dead port 1/2 on $mux $procmux$13940. + dead port 1/2 on $mux $procmux$139402. + dead port 1/2 on $mux $procmux$139405. + dead port 1/2 on $mux $procmux$139408. + dead port 2/2 on $mux $procmux$139410. + dead port 1/2 on $mux $procmux$139413. + dead port 2/2 on $mux $procmux$139415. + dead port 1/2 on $mux $procmux$139418. + dead port 2/2 on $mux $procmux$139421. + dead port 1/2 on $mux $procmux$139429. + dead port 1/2 on $mux $procmux$13943. + dead port 1/2 on $mux $procmux$139432. + dead port 1/2 on $mux $procmux$139435. + dead port 2/2 on $mux $procmux$139437. + dead port 1/2 on $mux $procmux$139440. + dead port 2/2 on $mux $procmux$139442. + dead port 1/2 on $mux $procmux$139445. + dead port 2/2 on $mux $procmux$139448. + dead port 1/2 on $mux $procmux$139456. + dead port 1/2 on $mux $procmux$139459. + dead port 1/2 on $mux $procmux$13946. + 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$procmux$139610. + dead port 1/2 on $mux $procmux$139618. + dead port 1/2 on $mux $procmux$13962. + dead port 1/2 on $mux $procmux$139621. + dead port 1/2 on $mux $procmux$139624. + dead port 2/2 on $mux $procmux$139626. + dead port 1/2 on $mux $procmux$139629. + dead port 2/2 on $mux $procmux$139631. + dead port 1/2 on $mux $procmux$139634. + dead port 2/2 on $mux $procmux$139637. + dead port 1/2 on $mux $procmux$139645. + dead port 1/2 on $mux $procmux$139648. + dead port 1/2 on $mux $procmux$13965. + dead port 1/2 on $mux $procmux$139651. + dead port 2/2 on $mux $procmux$139653. + dead port 1/2 on $mux $procmux$139656. + dead port 2/2 on $mux $procmux$139658. + dead port 1/2 on $mux $procmux$139661. + dead port 2/2 on $mux $procmux$139664. + dead port 1/2 on $mux $procmux$139672. + dead port 1/2 on $mux $procmux$139675. + dead port 1/2 on $mux $procmux$139678. + dead port 1/2 on $mux $procmux$13968. + dead port 2/2 on $mux $procmux$139680. + dead port 1/2 on $mux $procmux$139683. + dead port 2/2 on $mux $procmux$139685. + dead port 1/2 on $mux $procmux$139688. + dead port 2/2 on $mux $procmux$139691. + dead port 1/2 on $mux $procmux$139699. + dead port 1/2 on $mux $procmux$139702. + dead port 2/2 on $mux $procmux$139704. + dead port 1/2 on $mux $procmux$139707. + dead port 2/2 on $mux $procmux$139709. + dead port 1/2 on $mux $procmux$13971. + dead port 1/2 on $mux $procmux$139712. + dead port 2/2 on $mux $procmux$139715. + dead port 2/2 on $mux $procmux$139720. + dead port 1/2 on $mux $procmux$139723. + dead port 1/2 on $mux $procmux$139726. + dead port 2/2 on $mux $procmux$139728. + dead port 1/2 on $mux $procmux$139731. + dead port 2/2 on $mux $procmux$139733. + dead port 1/2 on $mux $procmux$139736. + dead port 2/2 on $mux $procmux$139739. + dead port 1/2 on $mux $procmux$13974. + dead port 2/2 on $mux $procmux$139744. + dead port 1/2 on $mux $procmux$139747. + dead port 1/2 on $mux $procmux$139750. + dead port 2/2 on $mux $procmux$139752. + dead port 1/2 on $mux $procmux$139755. + dead port 2/2 on $mux $procmux$139757. + dead port 1/2 on $mux $procmux$139760. + dead port 2/2 on $mux $procmux$139763. + dead port 1/2 on $mux $procmux$13977. + dead port 1/2 on $mux $procmux$139771. + dead port 1/2 on $mux $procmux$139774. + dead port 2/2 on $mux $procmux$139776. + dead port 1/2 on $mux $procmux$139779. + dead port 2/2 on $mux $procmux$139781. + dead port 1/2 on $mux $procmux$139784. + dead port 2/2 on $mux $procmux$139787. + dead port 1/2 on $mux $procmux$139795. + dead port 1/2 on $mux $procmux$139798. + dead port 1/2 on $mux $procmux$13980. + dead port 2/2 on $mux $procmux$139800. + dead port 1/2 on $mux $procmux$139803. + dead port 2/2 on $mux $procmux$139805. + dead port 1/2 on $mux $procmux$139808. + dead port 2/2 on $mux $procmux$139811. + dead port 2/2 on $mux $procmux$139816. + dead port 1/2 on $mux $procmux$139819. + dead port 1/2 on $mux $procmux$139822. + dead port 2/2 on $mux $procmux$139824. + dead port 1/2 on $mux $procmux$139827. + dead port 2/2 on $mux $procmux$139829. + dead port 1/2 on $mux $procmux$13983. + dead port 1/2 on $mux $procmux$139832. + dead port 2/2 on $mux $procmux$139835. + dead port 1/2 on $mux $procmux$139843. + dead port 1/2 on $mux $procmux$139846. + dead port 2/2 on $mux $procmux$139848. + dead port 1/2 on $mux $procmux$139851. + dead port 2/2 on $mux $procmux$139853. + dead port 1/2 on $mux $procmux$139856. + dead port 2/2 on $mux $procmux$139859. + dead port 1/2 on $mux $procmux$13986. + dead port 1/2 on $mux $procmux$139867. + dead port 1/2 on $mux $procmux$139870. + dead port 2/2 on $mux $procmux$139872. + dead port 1/2 on $mux $procmux$139875. + dead port 2/2 on $mux $procmux$139877. + dead port 1/2 on $mux $procmux$139880. + dead port 2/2 on $mux $procmux$139883. + dead port 1/2 on $mux $procmux$13989. + dead port 1/2 on $mux $procmux$139891. + dead port 1/2 on $mux $procmux$139894. + dead port 2/2 on $mux $procmux$139896. + dead port 1/2 on $mux $procmux$139899. + dead port 2/2 on $mux $procmux$139901. + dead port 1/2 on $mux $procmux$139904. + dead port 2/2 on $mux $procmux$139907. + dead port 1/2 on $mux $procmux$139915. + dead port 1/2 on $mux $procmux$139918. + dead port 1/2 on $mux $procmux$13992. + dead port 2/2 on $mux $procmux$139920. + dead port 1/2 on $mux $procmux$139923. + dead port 2/2 on $mux $procmux$139925. + dead port 1/2 on $mux $procmux$139928. + dead port 2/2 on $mux $procmux$139931. + dead port 1/2 on $mux $procmux$139939. + dead port 1/2 on $mux $procmux$139942. + dead port 1/2 on $mux $procmux$139945. + dead port 1/2 on $mux $procmux$139948. + dead port 1/2 on $mux $procmux$13995. + dead port 2/2 on $mux $procmux$139950. + dead port 1/2 on $mux $procmux$139953. + dead port 2/2 on $mux $procmux$139955. + dead port 1/2 on $mux $procmux$139958. + dead port 2/2 on $mux $procmux$139961. + dead port 1/2 on $mux $procmux$139969. + dead port 1/2 on $mux $procmux$139972. + dead port 1/2 on $mux $procmux$139975. + dead port 1/2 on $mux $procmux$139978. + dead port 1/2 on $mux $procmux$13998. + dead port 2/2 on $mux $procmux$139980. + dead port 1/2 on $mux $procmux$139983. + dead port 2/2 on $mux $procmux$139985. + dead port 1/2 on $mux $procmux$139988. + dead port 2/2 on $mux $procmux$139991. + dead port 1/2 on $mux $procmux$139999. + dead port 1/2 on $mux $procmux$140002. + dead port 1/2 on $mux $procmux$140005. + dead port 1/2 on $mux $procmux$140008. + dead port 1/2 on $mux $procmux$14001. + dead port 2/2 on $mux $procmux$140010. + dead port 1/2 on $mux $procmux$140013. + dead port 2/2 on $mux $procmux$140015. + dead port 1/2 on $mux $procmux$140018. + dead port 2/2 on $mux $procmux$140021. + dead port 1/2 on $mux $procmux$140029. + dead port 1/2 on $mux $procmux$140032. + dead port 1/2 on $mux $procmux$140035. + dead port 2/2 on $mux $procmux$140037. + dead port 1/2 on $mux $procmux$14004. + dead port 1/2 on $mux $procmux$140040. + dead port 2/2 on $mux $procmux$140042. + dead port 1/2 on $mux $procmux$140045. + dead port 2/2 on $mux $procmux$140048. + dead port 1/2 on $mux $procmux$140056. + dead port 1/2 on $mux $procmux$140059. + dead port 2/2 on $mux $procmux$14006. + dead port 1/2 on $mux $procmux$140062. + dead port 2/2 on $mux $procmux$140064. + dead port 1/2 on $mux $procmux$140067. + dead port 2/2 on $mux $procmux$140069. + dead port 1/2 on $mux $procmux$140072. + dead port 2/2 on $mux $procmux$140075. + dead port 1/2 on $mux $procmux$140083. + dead port 1/2 on $mux $procmux$140086. + dead port 1/2 on $mux $procmux$140089. + dead port 1/2 on $mux $procmux$14009. + dead port 2/2 on $mux $procmux$140091. + dead port 1/2 on $mux $procmux$140094. + dead port 2/2 on $mux $procmux$140096. + dead port 1/2 on $mux $procmux$140099. + dead port 2/2 on $mux $procmux$140102. + dead port 1/2 on $mux $procmux$140110. + dead port 1/2 on $mux $procmux$140113. + dead port 1/2 on $mux $procmux$140116. + dead port 2/2 on $mux $procmux$140118. + dead port 1/2 on $mux $procmux$14012. + dead port 1/2 on $mux $procmux$140121. + dead port 2/2 on $mux $procmux$140123. + dead port 1/2 on $mux $procmux$140126. + dead port 2/2 on $mux $procmux$140129. + dead port 1/2 on $mux $procmux$140137. + dead port 1/2 on $mux $procmux$140140. + dead port 1/2 on $mux $procmux$140143. + dead port 2/2 on $mux $procmux$140145. + dead port 1/2 on $mux $procmux$140148. + dead port 1/2 on $mux $procmux$14015. + dead port 2/2 on $mux $procmux$140150. + dead port 1/2 on $mux $procmux$140153. + dead port 2/2 on $mux $procmux$140156. + dead port 1/2 on $mux $procmux$140164. + dead port 1/2 on $mux $procmux$140167. + dead port 1/2 on $mux $procmux$140170. + dead port 2/2 on $mux $procmux$140172. + dead port 1/2 on $mux $procmux$140175. + dead port 2/2 on $mux $procmux$140177. + dead port 1/2 on $mux $procmux$14018. + dead port 1/2 on $mux $procmux$140180. + dead port 2/2 on $mux $procmux$140183. + dead port 1/2 on $mux $procmux$140191. + dead port 1/2 on $mux $procmux$140194. + dead port 2/2 on $mux $procmux$140196. + dead port 1/2 on $mux $procmux$140199. + dead port 2/2 on $mux $procmux$140201. + dead port 1/2 on $mux $procmux$140204. + dead port 2/2 on $mux $procmux$140207. + dead port 1/2 on $mux $procmux$14021. + dead port 1/2 on $mux $procmux$140215. + dead port 1/2 on $mux $procmux$140218. + dead port 2/2 on $mux $procmux$140220. + dead port 1/2 on $mux $procmux$140223. + dead port 2/2 on $mux $procmux$140225. + dead port 1/2 on $mux $procmux$140228. + dead port 2/2 on $mux $procmux$140231. + dead port 1/2 on $mux $procmux$14024. + dead port 1/2 on $mux $procmux$140263. + dead port 1/2 on $mux $procmux$140266. + dead port 2/2 on $mux $procmux$140268. + dead port 1/2 on $mux $procmux$14027. + dead port 1/2 on $mux $procmux$140271. + dead port 2/2 on $mux $procmux$140273. + dead port 1/2 on $mux $procmux$140276. + dead port 2/2 on $mux $procmux$140279. + dead port 1/2 on $mux $procmux$140287. + dead port 1/2 on $mux $procmux$140290. + dead port 2/2 on $mux $procmux$140292. + dead port 1/2 on $mux $procmux$140295. + dead port 2/2 on $mux $procmux$140297. + dead port 1/2 on $mux $procmux$14030. + dead port 1/2 on $mux $procmux$140300. + dead port 2/2 on $mux $procmux$140303. + dead port 1/2 on $mux $procmux$14033. + dead port 1/2 on $mux $procmux$14036. + dead port 1/2 on $mux $procmux$14039. + dead port 2/2 on $mux $procmux$14042. + dead port 1/2 on $mux $procmux$14049. + dead port 1/2 on $mux $procmux$14052. + dead port 1/2 on $mux $procmux$140524. + dead port 2/2 on $mux $procmux$140526. + dead port 1/2 on $mux $procmux$140529. + dead port 2/2 on $mux $procmux$140531. + dead port 1/2 on $mux $procmux$140534. + dead port 2/2 on $mux $procmux$140537. + dead port 1/2 on $mux $procmux$140545. + dead port 2/2 on $mux $procmux$140547. + dead port 1/2 on $mux $procmux$14055. + dead port 1/2 on $mux $procmux$140550. + dead port 2/2 on $mux $procmux$140552. + dead port 1/2 on $mux $procmux$140555. + dead port 2/2 on $mux $procmux$140558. + dead port 1/2 on $mux $procmux$14058. + dead port 1/2 on $mux $procmux$140587. + dead port 2/2 on $mux $procmux$140589. + dead port 1/2 on $mux $procmux$140592. + dead port 2/2 on $mux $procmux$140594. + dead port 1/2 on $mux $procmux$140597. + dead port 2/2 on $mux $procmux$140600. + dead port 1/2 on $mux $procmux$140608. + dead port 1/2 on $mux $procmux$14061. + dead port 2/2 on $mux $procmux$140610. + dead port 1/2 on $mux $procmux$140613. + dead port 2/2 on $mux $procmux$140615. + dead port 1/2 on $mux $procmux$140618. + dead port 2/2 on $mux $procmux$140621. + dead port 1/2 on $mux $procmux$14064. + dead port 1/2 on $mux $procmux$140650. + dead port 2/2 on $mux $procmux$140652. + dead port 1/2 on $mux $procmux$140655. + dead port 2/2 on $mux $procmux$140657. + dead port 1/2 on $mux $procmux$140660. + dead port 2/2 on $mux $procmux$140663. + dead port 1/2 on $mux $procmux$14067. + dead port 1/2 on $mux $procmux$140671. + dead port 2/2 on $mux $procmux$140673. + dead port 1/2 on $mux $procmux$140676. + dead port 2/2 on $mux $procmux$140678. + dead port 1/2 on $mux $procmux$140681. + dead port 2/2 on $mux $procmux$140684. + dead port 1/2 on $mux $procmux$14070. + dead port 1/2 on $mux $procmux$14073. + dead port 1/2 on $mux $procmux$14076. + dead port 1/2 on $mux $procmux$14079. + dead port 2/2 on $mux $procmux$140799. + dead port 1/2 on $mux $procmux$140802. + dead port 2/2 on $mux $procmux$140804. + dead port 1/2 on $mux $procmux$140807. + dead port 2/2 on $mux $procmux$140810. + dead port 2/2 on $mux $procmux$140817. + dead port 1/2 on $mux $procmux$14082. + dead port 1/2 on $mux $procmux$140820. + dead port 2/2 on $mux $procmux$140822. + dead port 1/2 on $mux $procmux$140825. + dead port 2/2 on $mux $procmux$140828. + dead port 1/2 on $mux $procmux$14085. + dead port 2/2 on $mux $procmux$140853. + dead port 1/2 on $mux $procmux$140856. + dead port 2/2 on $mux $procmux$140858. + dead port 1/2 on $mux $procmux$140861. + dead port 2/2 on $mux $procmux$140864. + dead port 2/2 on $mux $procmux$140871. + dead port 1/2 on $mux $procmux$140874. + dead port 2/2 on $mux $procmux$140876. + dead port 1/2 on $mux $procmux$140879. + dead port 1/2 on $mux $procmux$14088. + dead port 2/2 on $mux $procmux$140882. + dead port 2/2 on $mux $procmux$140907. + dead port 1/2 on $mux $procmux$14091. + dead port 1/2 on $mux $procmux$140910. + dead port 2/2 on $mux $procmux$140912. + dead port 1/2 on $mux $procmux$140915. + dead port 2/2 on $mux $procmux$140918. + dead port 2/2 on $mux $procmux$140925. + dead port 1/2 on $mux $procmux$140928. + dead port 2/2 on $mux $procmux$140930. + dead port 1/2 on $mux $procmux$140933. + dead port 2/2 on $mux $procmux$140936. + dead port 1/2 on $mux $procmux$14094. + dead port 1/2 on $mux $procmux$14097. + dead port 2/2 on $mux $procmux$14099. + dead port 1/2 on $mux $procmux$141003. + dead port 2/2 on $mux $procmux$141005. + dead port 1/2 on $mux $procmux$141008. + dead port 2/2 on $mux $procmux$141011. + dead port 1/2 on $mux $procmux$141018. + dead port 1/2 on $mux $procmux$14102. + dead port 2/2 on $mux $procmux$141020. + dead port 1/2 on $mux $procmux$141023. + dead port 2/2 on $mux $procmux$141026. + dead port 1/2 on $mux $procmux$141048. + dead port 1/2 on $mux $procmux$14105. + dead port 2/2 on $mux $procmux$141050. + dead port 1/2 on $mux $procmux$141053. + dead port 2/2 on $mux $procmux$141056. + dead port 1/2 on $mux $procmux$141063. + dead port 2/2 on $mux $procmux$141065. + dead port 1/2 on $mux $procmux$141068. + dead port 2/2 on $mux $procmux$141071. + dead port 1/2 on $mux $procmux$14108. + dead port 1/2 on $mux $procmux$141093. + dead port 2/2 on $mux $procmux$141095. + dead port 1/2 on $mux $procmux$141098. + dead port 2/2 on $mux $procmux$141101. + dead port 1/2 on $mux $procmux$141108. + dead port 1/2 on $mux $procmux$14111. + dead port 2/2 on $mux $procmux$141110. + dead port 1/2 on $mux $procmux$141113. + dead port 2/2 on $mux $procmux$141116. + dead port 1/2 on $mux $procmux$14114. + dead port 1/2 on $mux $procmux$14117. + dead port 1/2 on $mux $procmux$14120. + dead port 2/2 on $mux $procmux$141218. + dead port 1/2 on $mux $procmux$141221. + dead port 2/2 on $mux $procmux$141224. + dead port 1/2 on $mux $procmux$14123. + dead port 2/2 on $mux $procmux$141230. + dead port 1/2 on $mux $procmux$141233. + dead port 2/2 on $mux $procmux$141236. + dead port 2/2 on $mux $procmux$141254. + dead port 1/2 on $mux $procmux$141257. + dead port 1/2 on $mux $procmux$14126. + dead port 2/2 on $mux $procmux$141260. + dead port 2/2 on $mux $procmux$141266. + dead port 1/2 on $mux $procmux$141269. + dead port 2/2 on $mux $procmux$141272. + dead port 1/2 on $mux $procmux$14129. + dead port 2/2 on $mux $procmux$141290. + dead port 1/2 on $mux $procmux$141293. + dead port 2/2 on $mux $procmux$141296. + dead port 2/2 on $mux $procmux$141302. + dead port 1/2 on $mux $procmux$141305. + dead port 2/2 on $mux $procmux$141308. + dead port 1/2 on $mux $procmux$14132. + dead port 2/2 on $mux $procmux$14135. + dead port 1/2 on $mux $procmux$141368. + dead port 2/2 on $mux $procmux$141371. + dead port 1/2 on $mux $procmux$141377. + dead port 2/2 on $mux $procmux$141380. + dead port 1/2 on $mux $procmux$141395. + dead port 2/2 on $mux $procmux$141398. + dead port 1/2 on $mux $procmux$141404. + dead port 2/2 on $mux $procmux$141407. + dead port 1/2 on $mux $procmux$14142. + dead port 1/2 on $mux $procmux$141422. + dead port 2/2 on $mux $procmux$141425. + dead port 1/2 on $mux $procmux$141431. + dead port 2/2 on $mux $procmux$141434. + dead port 1/2 on $mux $procmux$14145. + dead port 1/2 on $mux $procmux$14148. + dead port 1/2 on $mux $procmux$14151. + dead port 1/2 on $mux $procmux$14154. + dead port 1/2 on $mux $procmux$14157. + dead port 1/2 on $mux $procmux$14160. + dead port 1/2 on $mux $procmux$14163. + dead port 1/2 on $mux $procmux$14166. + dead port 1/2 on $mux $procmux$14169. + dead port 1/2 on $mux $procmux$14172. + dead port 1/2 on $mux $procmux$14175. + dead port 1/2 on $mux $procmux$14178. + dead port 1/2 on $mux $procmux$14181. + dead port 1/2 on $mux $procmux$14184. + dead port 1/2 on $mux $procmux$14187. + dead port 1/2 on $mux $procmux$14190. + dead port 2/2 on $mux $procmux$14192. + dead port 1/2 on $mux $procmux$14195. + dead port 1/2 on $mux $procmux$14198. + dead port 1/2 on $mux $procmux$14201. + dead port 1/2 on $mux $procmux$14204. + dead port 1/2 on $mux $procmux$14207. + dead port 1/2 on $mux $procmux$14210. + dead port 1/2 on $mux $procmux$14213. + dead port 1/2 on $mux $procmux$14216. + dead port 1/2 on $mux $procmux$14219. + dead port 1/2 on $mux $procmux$14222. + dead port 1/2 on $mux $procmux$14225. + dead port 2/2 on $mux $procmux$14228. + dead port 1/2 on $mux $procmux$142304. + dead port 2/2 on $mux $procmux$142307. + dead port 1/2 on $mux $procmux$142313. + dead port 2/2 on $mux $procmux$142316. + dead port 1/2 on $mux $procmux$142322. + dead port 2/2 on $mux $procmux$142325. + dead port 1/2 on $mux $procmux$142331. + dead port 2/2 on $mux $procmux$142334. + dead port 1/2 on $mux $procmux$142340. + dead port 2/2 on $mux $procmux$142343. + dead port 1/2 on $mux $procmux$142349. + dead port 1/2 on $mux $procmux$14235. + dead port 2/2 on $mux $procmux$142352. + dead port 1/2 on $mux $procmux$142358. + dead port 2/2 on $mux $procmux$142361. + dead port 1/2 on $mux $procmux$14238. + dead port 1/2 on $mux $procmux$142385. + dead port 2/2 on $mux $procmux$142388. + dead port 1/2 on $mux $procmux$142394. + dead port 2/2 on $mux $procmux$142397. + dead port 1/2 on $mux $procmux$142403. + dead port 2/2 on $mux $procmux$142406. + dead port 1/2 on $mux $procmux$14241. + dead port 1/2 on $mux $procmux$142412. + dead port 2/2 on $mux $procmux$142415. + dead port 1/2 on $mux $procmux$142421. + dead port 2/2 on $mux $procmux$142424. + dead port 1/2 on $mux $procmux$142430. + dead port 2/2 on $mux $procmux$142433. + dead port 1/2 on $mux $procmux$142439. + dead port 1/2 on $mux $procmux$14244. + dead port 2/2 on $mux $procmux$142442. + dead port 1/2 on $mux $procmux$142448. + dead port 2/2 on $mux $procmux$142451. + dead port 1/2 on $mux $procmux$142466. + dead port 2/2 on $mux $procmux$142469. + dead port 1/2 on $mux $procmux$14247. + dead port 1/2 on $mux $procmux$142475. + dead port 2/2 on $mux $procmux$142478. + dead port 1/2 on $mux $procmux$142484. + dead port 2/2 on $mux $procmux$142487. + dead port 1/2 on $mux $procmux$14250. + dead port 1/2 on $mux $procmux$142520. + dead port 2/2 on $mux $procmux$142523. + dead port 1/2 on $mux $procmux$142529. + dead port 1/2 on $mux $procmux$14253. + dead port 2/2 on $mux $procmux$142532. + dead port 1/2 on $mux $procmux$142538. + dead port 2/2 on $mux $procmux$142541. + dead port 1/2 on $mux $procmux$14256. + dead port 1/2 on $mux $procmux$14259. + dead port 1/2 on $mux $procmux$14262. + dead port 1/2 on $mux $procmux$14265. + dead port 1/2 on $mux $procmux$14268. + dead port 1/2 on $mux $procmux$14271. + dead port 1/2 on $mux $procmux$14274. + dead port 1/2 on $mux $procmux$14277. + dead port 1/2 on $mux $procmux$14280. + dead port 1/2 on $mux $procmux$14283. + dead port 2/2 on $mux $procmux$14285. + dead port 1/2 on $mux $procmux$14288. + dead port 1/2 on $mux $procmux$14291. + dead port 1/2 on $mux $procmux$14294. + dead port 1/2 on $mux $procmux$14297. + dead port 1/2 on $mux $procmux$14300. + dead port 1/2 on $mux $procmux$14303. + dead port 1/2 on $mux $procmux$14306. + dead port 1/2 on $mux $procmux$14309. + dead port 1/2 on $mux $procmux$14312. + dead port 1/2 on $mux $procmux$14315. + dead port 2/2 on $mux $procmux$143153. + dead port 2/2 on $mux $procmux$143159. + dead port 2/2 on $mux $procmux$143177. + dead port 1/2 on $mux $procmux$14318. + dead port 2/2 on $mux $procmux$143183. + dead port 2/2 on $mux $procmux$143189. + dead port 2/2 on $mux $procmux$143195. + dead port 2/2 on $mux $procmux$143201. + dead port 2/2 on $mux $procmux$143207. + dead port 2/2 on $mux $procmux$14321. + dead port 2/2 on $mux $procmux$143213. + dead port 2/2 on $mux $procmux$143231. + dead port 2/2 on $mux $procmux$143237. + dead port 2/2 on $mux $procmux$143243. + dead port 2/2 on $mux $procmux$143249. + dead port 2/2 on $mux $procmux$143255. + dead port 2/2 on $mux $procmux$143261. + dead port 2/2 on $mux $procmux$143267. + dead port 2/2 on $mux $procmux$143273. + dead port 2/2 on $mux $procmux$143279. + dead port 1/2 on $mux $procmux$14328. + dead port 2/2 on $mux $procmux$143285. + dead port 2/2 on $mux $procmux$143297. + dead port 2/2 on $mux $procmux$143303. + dead port 2/2 on $mux $procmux$143309. + dead port 1/2 on $mux $procmux$14331. + dead port 2/2 on $mux $procmux$143333. + dead port 2/2 on $mux $procmux$143339. + dead port 1/2 on $mux $procmux$14334. + dead port 2/2 on $mux $procmux$143345. + dead port 2/2 on $mux $procmux$143357. + dead port 2/2 on $mux $procmux$143363. + dead port 1/2 on $mux $procmux$14337. + dead port 1/2 on $mux $procmux$14340. + dead port 1/2 on $mux $procmux$14343. + dead port 1/2 on $mux $procmux$14346. + dead port 1/2 on $mux $procmux$14349. + dead port 1/2 on $mux $procmux$14352. + dead port 1/2 on $mux $procmux$14355. + dead port 1/2 on $mux $procmux$14358. + dead port 1/2 on $mux $procmux$14361. + dead port 1/2 on $mux $procmux$14364. + dead port 1/2 on $mux $procmux$14367. + dead port 1/2 on $mux $procmux$14370. + dead port 1/2 on $mux $procmux$14373. + dead port 1/2 on $mux $procmux$14376. + dead port 2/2 on $mux $procmux$14378. + dead port 1/2 on $mux $procmux$14381. + dead port 1/2 on $mux $procmux$14384. + dead port 1/2 on $mux $procmux$14387. + dead port 1/2 on $mux $procmux$14390. + dead port 1/2 on $mux $procmux$14393. + dead port 1/2 on $mux $procmux$14396. + dead port 1/2 on $mux $procmux$14399. + dead port 1/2 on $mux $procmux$14402. + dead port 1/2 on $mux $procmux$14405. + dead port 1/2 on $mux $procmux$14408. + dead port 1/2 on $mux $procmux$14411. + dead port 2/2 on $mux $procmux$14414. + dead port 1/2 on $mux $procmux$14421. + dead port 1/2 on $mux $procmux$14424. + dead port 1/2 on $mux $procmux$14427. + dead port 1/2 on $mux $procmux$14430. + dead port 1/2 on $mux $procmux$14433. + dead port 1/2 on $mux $procmux$14436. + dead port 1/2 on $mux $procmux$14439. + dead port 1/2 on $mux $procmux$14442. + dead port 1/2 on $mux $procmux$14445. + dead port 1/2 on $mux $procmux$14448. + dead port 1/2 on $mux $procmux$14451. + dead port 1/2 on $mux $procmux$14454. + dead port 1/2 on $mux $procmux$14457. + dead port 1/2 on $mux $procmux$14460. + dead port 1/2 on $mux $procmux$14463. + dead port 1/2 on $mux $procmux$14466. + dead port 1/2 on $mux $procmux$14469. + dead port 2/2 on $mux $procmux$14471. + dead port 1/2 on $mux $procmux$14474. + dead port 1/2 on $mux $procmux$14477. + dead port 1/2 on $mux $procmux$14480. + dead port 1/2 on $mux $procmux$14483. + dead port 1/2 on $mux $procmux$14486. + dead port 1/2 on $mux $procmux$14489. + dead port 1/2 on $mux $procmux$14492. + dead port 1/2 on $mux $procmux$14495. + dead port 1/2 on $mux $procmux$14498. + dead port 1/2 on $mux $procmux$14501. + dead port 1/2 on $mux $procmux$14504. + dead port 2/2 on $mux $procmux$14507. + dead port 1/2 on $mux $procmux$14514. + dead port 1/2 on $mux $procmux$14517. + dead port 1/2 on $mux $procmux$14520. + dead port 1/2 on $mux $procmux$14523. + dead port 1/2 on $mux $procmux$14526. + dead port 1/2 on $mux $procmux$14529. + dead port 1/2 on $mux $procmux$14532. + dead port 1/2 on $mux $procmux$14535. + dead port 1/2 on $mux $procmux$14538. + dead port 1/2 on $mux $procmux$14541. + dead port 1/2 on $mux $procmux$14544. + dead port 1/2 on $mux $procmux$14547. + dead port 1/2 on $mux $procmux$14550. + dead port 1/2 on $mux $procmux$14553. + dead port 1/2 on $mux $procmux$14556. + dead port 1/2 on $mux $procmux$14559. + dead port 1/2 on $mux $procmux$14562. + dead port 2/2 on $mux $procmux$14564. + dead port 1/2 on $mux $procmux$14567. + dead port 1/2 on $mux $procmux$14570. + dead port 1/2 on $mux $procmux$14573. + dead port 1/2 on $mux $procmux$14576. + dead port 1/2 on $mux $procmux$14579. + dead port 1/2 on $mux $procmux$14582. + dead port 1/2 on $mux $procmux$14585. + dead port 1/2 on $mux $procmux$14588. + dead port 1/2 on $mux $procmux$14591. + dead port 1/2 on $mux $procmux$14594. + dead port 1/2 on $mux $procmux$14597. + dead port 2/2 on $mux $procmux$14600. + dead port 1/2 on $mux $procmux$14607. + dead port 1/2 on $mux $procmux$14610. + dead port 1/2 on $mux $procmux$14613. + dead port 1/2 on $mux $procmux$14616. + dead port 1/2 on $mux $procmux$14619. + dead port 1/2 on $mux $procmux$14622. + dead port 1/2 on $mux $procmux$14625. + dead port 1/2 on $mux $procmux$14628. + dead port 1/2 on $mux $procmux$14631. + dead port 1/2 on $mux $procmux$14634. + dead port 1/2 on $mux $procmux$14637. + dead port 1/2 on $mux $procmux$14640. + dead port 1/2 on $mux $procmux$14643. + dead port 1/2 on $mux $procmux$14646. + dead port 1/2 on $mux $procmux$14649. + dead port 1/2 on $mux $procmux$14652. + dead port 1/2 on $mux $procmux$14655. + dead port 2/2 on $mux $procmux$14657. + dead port 1/2 on $mux $procmux$14660. + dead port 1/2 on $mux $procmux$14663. + dead port 1/2 on $mux $procmux$14666. + dead port 1/2 on $mux $procmux$14669. + dead port 1/2 on $mux $procmux$14672. + dead port 1/2 on $mux $procmux$14675. + dead port 1/2 on $mux $procmux$14678. + dead port 1/2 on $mux $procmux$14681. + dead port 1/2 on $mux $procmux$14684. + dead port 1/2 on $mux $procmux$14687. + dead port 1/2 on $mux $procmux$14690. + dead port 2/2 on $mux $procmux$14693. + dead port 1/2 on $mux $procmux$14793. + dead port 1/2 on $mux $procmux$14796. + dead port 1/2 on $mux $procmux$14799. + dead port 1/2 on $mux $procmux$14802. + dead port 1/2 on $mux $procmux$14805. + dead port 1/2 on $mux $procmux$14808. + dead port 1/2 on $mux $procmux$14811. + dead port 1/2 on $mux $procmux$14814. + dead port 1/2 on $mux $procmux$14817. + dead port 1/2 on $mux $procmux$14820. + dead port 1/2 on $mux $procmux$14823. + dead port 1/2 on $mux $procmux$14826. + dead port 1/2 on $mux $procmux$14829. + dead port 1/2 on $mux $procmux$14832. + dead port 1/2 on $mux $procmux$14835. + dead port 1/2 on $mux $procmux$14838. + dead port 1/2 on $mux $procmux$14841. + dead port 2/2 on $mux $procmux$14843. + dead port 1/2 on $mux $procmux$14846. + dead port 1/2 on $mux $procmux$14849. + dead port 1/2 on $mux $procmux$14852. + dead port 1/2 on $mux $procmux$14855. + dead port 1/2 on $mux $procmux$14858. + dead port 1/2 on $mux $procmux$14861. + dead port 1/2 on $mux $procmux$14864. + dead port 1/2 on $mux $procmux$14867. + dead port 1/2 on $mux $procmux$14870. + dead port 1/2 on $mux $procmux$14873. + dead port 1/2 on $mux $procmux$14876. + dead port 2/2 on $mux $procmux$14879. + dead port 1/2 on $mux $procmux$14886. + dead port 1/2 on $mux $procmux$14889. + dead port 1/2 on $mux $procmux$14892. + dead port 1/2 on $mux $procmux$14895. + dead port 1/2 on $mux $procmux$14898. + dead port 1/2 on $mux $procmux$14901. + dead port 1/2 on $mux $procmux$14904. + dead port 1/2 on $mux $procmux$14907. + dead port 1/2 on $mux $procmux$14910. + dead port 1/2 on $mux $procmux$14913. + dead port 1/2 on $mux $procmux$14916. + dead port 1/2 on $mux $procmux$14919. + dead port 1/2 on $mux $procmux$14922. + dead port 1/2 on $mux $procmux$14925. + dead port 1/2 on $mux $procmux$14928. + dead port 1/2 on $mux $procmux$14931. + dead port 1/2 on $mux $procmux$14934. + dead port 2/2 on $mux $procmux$14936. + dead port 1/2 on $mux $procmux$14939. + dead port 1/2 on $mux $procmux$14942. + dead port 1/2 on $mux $procmux$14945. + dead port 1/2 on $mux $procmux$14948. + dead port 1/2 on $mux $procmux$14951. + dead port 1/2 on $mux $procmux$14954. + dead port 1/2 on $mux $procmux$14957. + dead port 1/2 on $mux $procmux$14960. + dead port 1/2 on $mux $procmux$14963. + dead port 1/2 on $mux $procmux$14966. + dead port 1/2 on $mux $procmux$14969. + dead port 2/2 on $mux $procmux$14972. + dead port 1/2 on $mux $procmux$14979. + dead port 1/2 on $mux $procmux$14982. + dead port 1/2 on $mux $procmux$14985. + dead port 1/2 on $mux $procmux$14988. + dead port 1/2 on $mux $procmux$14991. + dead port 1/2 on $mux $procmux$14994. + dead port 1/2 on $mux $procmux$14997. + dead port 1/2 on $mux $procmux$15000. + dead port 1/2 on $mux $procmux$15003. + dead port 1/2 on $mux $procmux$15006. + dead port 1/2 on $mux $procmux$15009. + dead port 1/2 on $mux $procmux$15012. + dead port 1/2 on $mux $procmux$15015. + dead port 1/2 on $mux $procmux$15018. + dead port 1/2 on $mux $procmux$15021. + dead port 1/2 on $mux $procmux$15024. + dead port 1/2 on $mux $procmux$15027. + dead port 2/2 on $mux $procmux$15029. + dead port 1/2 on $mux $procmux$15032. + dead port 1/2 on $mux $procmux$15035. + dead port 1/2 on $mux $procmux$15038. + dead port 1/2 on $mux $procmux$15041. + dead port 1/2 on $mux $procmux$15044. + dead port 1/2 on $mux $procmux$15047. + dead port 1/2 on $mux $procmux$15050. + dead port 1/2 on $mux $procmux$15053. + dead port 1/2 on $mux $procmux$15056. + dead port 1/2 on $mux $procmux$15059. + dead port 1/2 on $mux $procmux$15062. + dead port 2/2 on $mux $procmux$15065. + dead port 1/2 on $mux $procmux$15072. + dead port 1/2 on $mux $procmux$15075. + dead port 1/2 on $mux $procmux$15078. + dead port 1/2 on $mux $procmux$15081. + dead port 1/2 on $mux $procmux$15084. + dead port 1/2 on $mux $procmux$15087. + dead port 1/2 on $mux $procmux$15090. + dead port 1/2 on $mux $procmux$15093. + dead port 1/2 on $mux $procmux$15096. + dead port 1/2 on $mux $procmux$15099. + dead port 1/2 on $mux $procmux$15102. + dead port 1/2 on $mux $procmux$15105. + dead port 1/2 on $mux $procmux$15108. + dead port 1/2 on $mux $procmux$15111. + dead port 1/2 on $mux $procmux$15114. + dead port 1/2 on $mux $procmux$15117. + dead port 1/2 on $mux $procmux$15120. + dead port 2/2 on $mux $procmux$15122. + dead port 1/2 on $mux $procmux$15125. + dead port 1/2 on $mux $procmux$15128. + dead port 1/2 on $mux $procmux$15131. + dead port 1/2 on $mux $procmux$15134. + dead port 1/2 on $mux $procmux$15137. + dead port 1/2 on $mux $procmux$15140. + dead port 1/2 on $mux $procmux$15143. + dead port 1/2 on $mux $procmux$15146. + dead port 1/2 on $mux $procmux$15149. + dead port 1/2 on $mux $procmux$15152. + dead port 1/2 on $mux $procmux$15155. + dead port 2/2 on $mux $procmux$15158. + dead port 1/2 on $mux $procmux$15165. + dead port 1/2 on $mux $procmux$15168. + dead port 1/2 on $mux $procmux$15171. + dead port 1/2 on $mux $procmux$15174. + dead port 1/2 on $mux $procmux$15177. + dead port 1/2 on $mux $procmux$15180. + dead port 1/2 on $mux $procmux$15183. + dead port 1/2 on $mux $procmux$15186. + dead port 1/2 on $mux $procmux$15189. + dead port 1/2 on $mux $procmux$15192. + dead port 1/2 on $mux $procmux$15195. + dead port 1/2 on $mux $procmux$15198. + dead port 1/2 on $mux $procmux$15201. + dead port 1/2 on $mux $procmux$15204. + dead port 1/2 on $mux $procmux$15207. + dead port 1/2 on $mux $procmux$15210. + dead port 1/2 on $mux $procmux$15213. + dead port 2/2 on $mux $procmux$15215. + dead port 1/2 on $mux $procmux$15218. + dead port 1/2 on $mux $procmux$15221. + dead port 1/2 on $mux $procmux$15224. + dead port 1/2 on $mux $procmux$15227. + dead port 1/2 on $mux $procmux$15230. + dead port 1/2 on $mux $procmux$15233. + dead port 1/2 on $mux $procmux$15236. + dead port 1/2 on $mux $procmux$15239. + dead port 1/2 on $mux $procmux$15242. + dead port 1/2 on $mux $procmux$15245. + dead port 1/2 on $mux $procmux$15248. + dead port 2/2 on $mux $procmux$15251. + dead port 1/2 on $mux $procmux$15258. + dead port 1/2 on $mux $procmux$15261. + dead port 1/2 on $mux $procmux$15264. + dead port 1/2 on $mux $procmux$15267. + dead port 1/2 on $mux $procmux$15270. + dead port 1/2 on $mux $procmux$15273. + dead port 1/2 on $mux $procmux$15276. + dead port 1/2 on $mux $procmux$15279. + dead port 1/2 on $mux $procmux$15282. + dead port 1/2 on $mux $procmux$15285. + dead port 1/2 on $mux $procmux$15288. + dead port 1/2 on $mux $procmux$15291. + dead port 1/2 on $mux $procmux$15294. + dead port 1/2 on $mux $procmux$15297. + dead port 1/2 on $mux $procmux$15300. + dead port 1/2 on $mux $procmux$15303. + dead port 1/2 on $mux $procmux$15306. + dead port 2/2 on $mux $procmux$15308. + dead port 1/2 on $mux $procmux$15311. + dead port 1/2 on $mux $procmux$15314. + dead port 1/2 on $mux $procmux$15317. + dead port 1/2 on $mux $procmux$15320. + dead port 1/2 on $mux $procmux$15323. + dead port 1/2 on $mux $procmux$15326. + dead port 1/2 on $mux $procmux$15329. + dead port 1/2 on $mux $procmux$15332. + dead port 1/2 on $mux $procmux$15335. + dead port 1/2 on $mux $procmux$15338. + dead port 1/2 on $mux $procmux$15341. + dead port 2/2 on $mux $procmux$15344. + dead port 1/2 on $mux $procmux$15631. + dead port 1/2 on $mux $procmux$15634. + dead port 1/2 on $mux $procmux$15637. + dead port 1/2 on $mux $procmux$15640. + dead port 1/2 on $mux $procmux$15643. + dead port 1/2 on $mux $procmux$15646. + dead port 1/2 on $mux $procmux$15649. + dead port 2/2 on $mux $procmux$15651. + dead port 1/2 on $mux $procmux$15654. + dead port 1/2 on $mux $procmux$15657. + dead port 1/2 on $mux $procmux$15660. + dead port 1/2 on $mux $procmux$15663. + dead port 1/2 on $mux $procmux$15666. + dead port 1/2 on $mux $procmux$15669. + dead port 1/2 on $mux $procmux$15672. + dead port 1/2 on $mux $procmux$15675. + dead port 1/2 on $mux $procmux$15678. + dead port 1/2 on $mux $procmux$15681. + dead port 1/2 on $mux $procmux$15684. + dead port 1/2 on $mux $procmux$15687. + dead port 1/2 on $mux $procmux$15690. + dead port 1/2 on $mux $procmux$15693. + dead port 1/2 on $mux $procmux$15696. + dead port 1/2 on $mux $procmux$15699. + dead port 2/2 on $mux $procmux$15701. + dead port 1/2 on $mux $procmux$15704. + dead port 1/2 on $mux $procmux$15707. + dead port 1/2 on $mux $procmux$15710. + dead port 1/2 on $mux $procmux$15713. + dead port 1/2 on $mux $procmux$15716. + dead port 1/2 on $mux $procmux$15719. + dead port 1/2 on $mux $procmux$15722. + dead port 1/2 on $mux $procmux$15725. + dead port 1/2 on $mux $procmux$15728. + dead port 1/2 on $mux $procmux$15731. + dead port 1/2 on $mux $procmux$15734. + dead port 2/2 on $mux $procmux$15737. + dead port 1/2 on $mux $procmux$15745. + dead port 1/2 on $mux $procmux$15748. + dead port 1/2 on $mux $procmux$15751. + dead port 1/2 on $mux $procmux$15754. + dead port 1/2 on $mux $procmux$15757. + dead port 1/2 on $mux $procmux$15760. + dead port 1/2 on $mux $procmux$15763. + dead port 2/2 on $mux $procmux$15765. + dead port 1/2 on $mux $procmux$15768. + dead port 1/2 on $mux $procmux$15771. + dead port 1/2 on $mux $procmux$15774. + dead port 1/2 on $mux $procmux$15777. + dead port 1/2 on $mux $procmux$15780. + dead port 1/2 on $mux $procmux$15783. + dead port 1/2 on $mux $procmux$15786. + dead port 1/2 on $mux $procmux$15789. + dead port 1/2 on $mux $procmux$15792. + dead port 1/2 on $mux $procmux$15795. + dead port 1/2 on $mux $procmux$15798. + dead port 1/2 on $mux $procmux$15801. + dead port 1/2 on $mux $procmux$15804. + dead port 1/2 on $mux $procmux$15807. + dead port 1/2 on $mux $procmux$15810. + dead port 1/2 on $mux $procmux$15813. + dead port 2/2 on $mux $procmux$15815. + dead port 1/2 on $mux $procmux$15818. + dead port 1/2 on $mux $procmux$15821. + dead port 1/2 on $mux $procmux$15824. + dead port 1/2 on $mux $procmux$15827. + dead port 1/2 on $mux $procmux$15830. + dead port 1/2 on $mux $procmux$15833. + dead port 1/2 on $mux $procmux$15836. + dead port 1/2 on $mux $procmux$15839. + dead port 1/2 on $mux $procmux$15842. + dead port 1/2 on $mux $procmux$15845. + dead port 1/2 on $mux $procmux$15848. + dead port 2/2 on $mux $procmux$15851. + dead port 1/2 on $mux $procmux$15859. + dead port 1/2 on $mux $procmux$15862. + dead port 1/2 on $mux $procmux$15865. + dead port 1/2 on $mux $procmux$15868. + dead port 1/2 on $mux $procmux$15871. + dead port 1/2 on $mux $procmux$15874. + dead port 1/2 on $mux $procmux$15877. + dead port 2/2 on $mux $procmux$15879. + dead port 1/2 on $mux $procmux$15882. + dead port 1/2 on $mux $procmux$15885. + dead port 1/2 on $mux $procmux$15888. + dead port 1/2 on $mux $procmux$15891. + dead port 1/2 on $mux $procmux$15894. + dead port 1/2 on $mux $procmux$15897. + dead port 1/2 on $mux $procmux$15900. + dead port 1/2 on $mux $procmux$15903. + dead port 1/2 on $mux $procmux$15906. + dead port 1/2 on $mux $procmux$15909. + dead port 1/2 on $mux $procmux$15912. + dead port 1/2 on $mux $procmux$15915. + dead port 1/2 on $mux $procmux$15918. + dead port 1/2 on $mux $procmux$15921. + dead port 1/2 on $mux $procmux$15924. + dead port 1/2 on $mux $procmux$15927. + dead port 2/2 on $mux $procmux$15929. + dead port 1/2 on $mux $procmux$15932. + dead port 1/2 on $mux $procmux$15935. + dead port 1/2 on $mux $procmux$15938. + dead port 1/2 on $mux $procmux$15941. + dead port 1/2 on $mux $procmux$15944. + dead port 1/2 on $mux $procmux$15947. + dead port 1/2 on $mux $procmux$15950. + dead port 1/2 on $mux $procmux$15953. + dead port 1/2 on $mux $procmux$15956. + dead port 1/2 on $mux $procmux$15959. + dead port 1/2 on $mux $procmux$15962. + dead port 2/2 on $mux $procmux$15965. + dead port 1/2 on $mux $procmux$15973. + dead port 1/2 on $mux $procmux$15976. + dead port 1/2 on $mux $procmux$15979. + dead port 1/2 on $mux $procmux$15982. + dead port 1/2 on $mux $procmux$15985. + dead port 1/2 on $mux $procmux$15988. + dead port 2/2 on $mux $procmux$15990. + dead port 1/2 on $mux $procmux$15993. + dead port 1/2 on $mux $procmux$15996. + dead port 1/2 on $mux $procmux$15999. + dead port 1/2 on $mux $procmux$16002. + dead port 1/2 on $mux $procmux$16005. + dead port 1/2 on $mux $procmux$16008. + dead port 1/2 on $mux $procmux$16011. + dead port 1/2 on $mux $procmux$16014. + dead port 1/2 on $mux $procmux$16017. + dead port 1/2 on $mux $procmux$16020. + dead port 1/2 on $mux $procmux$16023. + dead port 1/2 on $mux $procmux$16026. + dead port 1/2 on $mux $procmux$16029. + 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dead port 2/2 on $mux $procmux$16262. + dead port 1/2 on $mux $procmux$16265. + dead port 1/2 on $mux $procmux$16268. + dead port 1/2 on $mux $procmux$16271. + dead port 1/2 on $mux $procmux$16274. + dead port 1/2 on $mux $procmux$16277. + dead port 1/2 on $mux $procmux$16280. + dead port 1/2 on $mux $procmux$16283. + dead port 1/2 on $mux $procmux$16286. + dead port 1/2 on $mux $procmux$16289. + dead port 1/2 on $mux $procmux$16292. + dead port 1/2 on $mux $procmux$16295. + dead port 2/2 on $mux $procmux$16298. + dead port 1/2 on $mux $procmux$16307. + dead port 2/2 on $mux $procmux$16309. + dead port 1/2 on $mux $procmux$16312. + dead port 1/2 on $mux $procmux$16315. + dead port 1/2 on $mux $procmux$16318. + dead port 1/2 on $mux $procmux$16321. + dead port 1/2 on $mux $procmux$16324. + dead port 2/2 on $mux $procmux$16326. + dead port 1/2 on $mux $procmux$16329. + dead port 1/2 on $mux $procmux$16332. + dead port 1/2 on $mux $procmux$16335. + dead port 1/2 on $mux $procmux$16338. + dead port 1/2 on $mux $procmux$16341. + dead port 1/2 on $mux $procmux$16344. + dead port 1/2 on $mux $procmux$16347. + dead port 1/2 on $mux $procmux$16350. + dead port 1/2 on $mux $procmux$16353. + dead port 1/2 on $mux $procmux$16356. + dead port 1/2 on $mux $procmux$16359. + dead port 1/2 on $mux $procmux$16362. + dead port 1/2 on $mux $procmux$16365. + dead port 1/2 on $mux $procmux$16368. + dead port 1/2 on $mux $procmux$16371. + dead port 1/2 on $mux $procmux$16374. + dead port 2/2 on $mux $procmux$16376. + dead port 1/2 on $mux $procmux$16379. + dead port 1/2 on $mux $procmux$16382. + dead port 1/2 on $mux $procmux$16385. + dead port 1/2 on $mux $procmux$16388. + dead port 1/2 on $mux $procmux$16391. + dead port 1/2 on $mux $procmux$16394. + dead port 1/2 on $mux $procmux$16397. + dead port 1/2 on $mux $procmux$16400. + dead port 1/2 on $mux $procmux$16403. + dead port 1/2 on $mux $procmux$16406. + dead port 1/2 on $mux $procmux$16409. + dead port 2/2 on $mux $procmux$16412. + dead port 1/2 on $mux $procmux$16421. + dead port 2/2 on $mux $procmux$16423. + dead port 1/2 on $mux $procmux$16426. + dead port 1/2 on $mux $procmux$16429. + dead port 1/2 on $mux $procmux$16432. + dead port 1/2 on $mux $procmux$16435. + dead port 1/2 on $mux $procmux$16438. + dead port 2/2 on $mux $procmux$16440. + dead port 1/2 on $mux $procmux$16443. + dead port 1/2 on $mux $procmux$16446. + dead port 1/2 on $mux $procmux$16449. + dead port 1/2 on $mux $procmux$16452. + dead port 1/2 on $mux $procmux$16455. + dead port 1/2 on $mux $procmux$16458. + dead port 1/2 on $mux $procmux$16461. + dead port 1/2 on $mux $procmux$16464. + dead port 1/2 on $mux $procmux$16467. + dead port 1/2 on $mux $procmux$16470. + dead port 1/2 on $mux $procmux$16473. + dead port 1/2 on $mux $procmux$16476. + dead port 1/2 on $mux $procmux$16479. + dead port 1/2 on $mux $procmux$16482. + dead port 1/2 on $mux $procmux$16485. + dead port 1/2 on $mux $procmux$16488. + dead port 2/2 on $mux $procmux$16490. + dead port 1/2 on $mux $procmux$16493. + dead port 1/2 on $mux $procmux$16496. + dead port 1/2 on $mux $procmux$16499. + dead port 1/2 on $mux $procmux$16502. + dead port 1/2 on $mux $procmux$16505. + dead port 1/2 on $mux $procmux$16508. + dead port 1/2 on $mux $procmux$16511. + dead port 1/2 on $mux $procmux$16514. + dead port 1/2 on $mux $procmux$16517. + dead port 1/2 on $mux $procmux$16520. + dead port 1/2 on $mux $procmux$16523. + dead port 2/2 on $mux $procmux$16526. + dead port 1/2 on $mux $procmux$16535. + dead port 2/2 on $mux $procmux$16537. + dead port 1/2 on $mux $procmux$16540. + dead port 1/2 on $mux $procmux$16543. + dead port 1/2 on $mux $procmux$16546. + dead port 1/2 on $mux $procmux$16549. + dead port 1/2 on $mux $procmux$16552. + dead port 2/2 on $mux $procmux$16554. + dead port 1/2 on $mux $procmux$16557. + dead port 1/2 on $mux $procmux$16560. + dead port 1/2 on $mux $procmux$16563. + dead port 1/2 on $mux $procmux$16566. + dead port 1/2 on $mux $procmux$16569. + dead port 1/2 on $mux $procmux$16572. + dead port 1/2 on $mux $procmux$16575. + dead port 1/2 on $mux $procmux$16578. + dead port 1/2 on $mux $procmux$16581. + dead port 1/2 on $mux $procmux$16584. + dead port 1/2 on $mux $procmux$16587. + dead port 1/2 on $mux $procmux$16590. + dead port 1/2 on $mux $procmux$16593. + dead port 1/2 on $mux $procmux$16596. + dead port 1/2 on $mux $procmux$16599. + dead port 1/2 on $mux $procmux$16602. + dead port 2/2 on $mux $procmux$16604. + dead port 1/2 on $mux $procmux$16607. + dead port 1/2 on $mux $procmux$16610. + dead port 1/2 on $mux $procmux$16613. + dead port 1/2 on $mux $procmux$16616. + dead port 1/2 on $mux $procmux$16619. + dead port 1/2 on $mux $procmux$16622. + dead port 1/2 on $mux $procmux$16625. + dead port 1/2 on $mux $procmux$16628. + dead port 1/2 on $mux $procmux$16631. + dead port 1/2 on $mux $procmux$16634. + dead port 1/2 on $mux $procmux$16637. + dead port 2/2 on $mux $procmux$16640. + dead port 2/2 on $mux $procmux$16648. + dead port 1/2 on $mux $procmux$16651. + dead port 1/2 on $mux $procmux$16654. + dead port 1/2 on $mux $procmux$16657. + dead port 1/2 on $mux $procmux$16660. + dead port 1/2 on $mux $procmux$16663. + dead port 2/2 on $mux $procmux$16665. + dead port 1/2 on $mux $procmux$16668. + dead port 1/2 on $mux $procmux$16671. + dead port 1/2 on $mux $procmux$16674. + dead port 1/2 on $mux $procmux$16677. + dead port 1/2 on $mux $procmux$16680. + dead port 1/2 on $mux $procmux$16683. + dead port 1/2 on $mux $procmux$16686. + dead port 1/2 on $mux $procmux$16689. + dead port 1/2 on $mux $procmux$16692. + dead port 1/2 on $mux $procmux$16695. + dead port 1/2 on $mux $procmux$16698. + dead port 1/2 on $mux $procmux$16701. + dead port 1/2 on $mux $procmux$16704. + dead port 1/2 on $mux $procmux$16707. + dead port 1/2 on $mux $procmux$16710. + dead port 1/2 on $mux $procmux$16713. + dead port 2/2 on $mux $procmux$16715. + dead port 1/2 on $mux $procmux$16718. + dead port 1/2 on $mux $procmux$16721. + dead port 1/2 on $mux $procmux$16724. + dead port 1/2 on $mux $procmux$16727. + dead port 1/2 on $mux $procmux$16730. + dead port 1/2 on $mux $procmux$16733. + dead port 1/2 on $mux $procmux$16736. + dead port 1/2 on $mux $procmux$16739. + dead port 1/2 on $mux $procmux$16742. + dead port 1/2 on $mux $procmux$16745. + dead port 1/2 on $mux $procmux$16748. + dead port 2/2 on $mux $procmux$16751. + dead port 2/2 on $mux $procmux$16759. + dead port 1/2 on $mux $procmux$16762. + dead port 1/2 on $mux $procmux$16765. + dead port 1/2 on $mux $procmux$16768. + dead port 1/2 on $mux $procmux$16771. + dead port 1/2 on $mux $procmux$16774. + dead port 2/2 on $mux $procmux$16776. + dead port 1/2 on $mux $procmux$16779. + dead port 1/2 on $mux $procmux$16782. + dead port 1/2 on $mux $procmux$16785. + dead port 1/2 on $mux $procmux$16788. + dead port 1/2 on $mux $procmux$16791. + dead port 1/2 on $mux $procmux$16794. + dead port 1/2 on $mux $procmux$16797. + dead port 1/2 on $mux $procmux$16800. + dead port 1/2 on $mux $procmux$16803. + dead port 1/2 on $mux $procmux$16806. + dead port 1/2 on $mux $procmux$16809. + dead port 1/2 on $mux $procmux$16812. + dead port 1/2 on $mux $procmux$16815. + dead port 1/2 on $mux $procmux$16818. + dead port 1/2 on $mux $procmux$16821. + dead port 1/2 on $mux $procmux$16824. + dead port 2/2 on $mux $procmux$16826. + dead port 1/2 on $mux $procmux$16829. + dead port 1/2 on $mux $procmux$16832. + dead port 1/2 on $mux $procmux$16835. + dead port 1/2 on $mux $procmux$16838. + dead port 1/2 on $mux $procmux$16841. + dead port 1/2 on $mux $procmux$16844. + dead port 1/2 on $mux $procmux$16847. + dead port 1/2 on $mux $procmux$16850. + dead port 1/2 on $mux $procmux$16853. + dead port 1/2 on $mux $procmux$16856. + dead port 1/2 on $mux $procmux$16859. + dead port 2/2 on $mux $procmux$16862. + dead port 2/2 on $mux $procmux$16870. + dead port 1/2 on $mux $procmux$16873. + dead port 1/2 on $mux $procmux$16876. + dead port 1/2 on $mux $procmux$16879. + dead port 1/2 on $mux $procmux$16882. + dead port 1/2 on $mux $procmux$16885. + dead port 2/2 on $mux $procmux$16887. + dead port 1/2 on $mux $procmux$16890. + dead port 1/2 on $mux $procmux$16893. + dead port 1/2 on $mux $procmux$16896. + dead port 1/2 on $mux $procmux$16899. + dead port 1/2 on $mux $procmux$16902. + dead port 1/2 on $mux $procmux$16905. + dead port 1/2 on $mux $procmux$16908. + dead port 1/2 on $mux $procmux$16911. + dead port 1/2 on $mux $procmux$16914. + dead port 1/2 on $mux $procmux$16917. + dead port 1/2 on $mux $procmux$16920. + dead port 1/2 on $mux $procmux$16923. + dead port 1/2 on $mux $procmux$16926. + dead port 1/2 on $mux $procmux$16929. + dead port 1/2 on $mux $procmux$16932. + dead port 1/2 on $mux $procmux$16935. + dead port 2/2 on $mux $procmux$16937. + dead port 1/2 on $mux $procmux$16940. + dead port 1/2 on $mux $procmux$16943. + dead port 1/2 on $mux $procmux$16946. + dead port 1/2 on $mux $procmux$16949. + dead port 1/2 on $mux $procmux$16952. + dead port 1/2 on $mux $procmux$16955. + dead port 1/2 on $mux $procmux$16958. + dead port 1/2 on $mux $procmux$16961. + dead port 1/2 on $mux $procmux$16964. + dead port 1/2 on $mux $procmux$16967. + dead port 1/2 on $mux $procmux$16970. + dead port 2/2 on $mux $procmux$16973. + dead port 1/2 on $mux $procmux$16981. + dead port 1/2 on $mux $procmux$16984. + dead port 1/2 on $mux $procmux$16987. + dead port 1/2 on $mux $procmux$16990. + dead port 1/2 on $mux $procmux$16993. + dead port 2/2 on $mux $procmux$16995. + dead port 1/2 on $mux $procmux$16998. + dead port 1/2 on $mux $procmux$17001. + dead port 1/2 on $mux $procmux$17004. + dead port 1/2 on $mux $procmux$17007. + dead port 1/2 on $mux $procmux$17010. + dead port 1/2 on $mux $procmux$17013. + dead port 1/2 on $mux $procmux$17016. + dead port 1/2 on $mux $procmux$17019. + dead port 1/2 on $mux $procmux$17022. + dead port 1/2 on $mux $procmux$17025. + dead port 1/2 on $mux $procmux$17028. + dead port 1/2 on $mux $procmux$17031. + dead port 1/2 on $mux $procmux$17034. + dead port 1/2 on $mux $procmux$17037. + dead port 1/2 on $mux $procmux$17040. + dead port 1/2 on $mux $procmux$17043. + dead port 2/2 on $mux $procmux$17045. + dead port 1/2 on $mux $procmux$17048. + dead port 1/2 on $mux $procmux$17051. + dead port 1/2 on $mux $procmux$17054. + dead port 1/2 on $mux $procmux$17057. + dead port 1/2 on $mux $procmux$17060. + dead port 1/2 on $mux $procmux$17063. + dead port 1/2 on $mux $procmux$17066. + dead port 1/2 on $mux $procmux$17069. + dead port 1/2 on $mux $procmux$17072. + dead port 1/2 on $mux $procmux$17075. + dead port 1/2 on $mux $procmux$17078. + dead port 2/2 on $mux $procmux$17081. + dead port 1/2 on $mux $procmux$17089. + dead port 1/2 on $mux $procmux$17092. + dead port 1/2 on $mux $procmux$17095. + dead port 1/2 on $mux $procmux$17098. + dead port 1/2 on $mux $procmux$17101. + dead port 2/2 on $mux $procmux$17103. + dead port 1/2 on $mux $procmux$17106. + dead port 1/2 on $mux $procmux$17109. + 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dead port 1/2 on $mux $procmux$25503. + dead port 1/2 on $mux $procmux$25506. + dead port 1/2 on $mux $procmux$25509. + dead port 1/2 on $mux $procmux$25512. + dead port 1/2 on $mux $procmux$25515. + dead port 1/2 on $mux $procmux$25518. + dead port 1/2 on $mux $procmux$25521. + dead port 2/2 on $mux $procmux$25523. + dead port 1/2 on $mux $procmux$25526. + dead port 1/2 on $mux $procmux$25529. + dead port 1/2 on $mux $procmux$25532. + dead port 1/2 on $mux $procmux$25535. + dead port 1/2 on $mux $procmux$25538. + dead port 1/2 on $mux $procmux$25541. + dead port 1/2 on $mux $procmux$25544. + dead port 1/2 on $mux $procmux$25547. + dead port 1/2 on $mux $procmux$25550. + dead port 1/2 on $mux $procmux$25553. + dead port 1/2 on $mux $procmux$25556. + dead port 2/2 on $mux $procmux$25559. + dead port 1/2 on $mux $procmux$25566. + dead port 1/2 on $mux $procmux$25569. + dead port 1/2 on $mux $procmux$25572. + dead port 1/2 on $mux $procmux$25575. + dead port 1/2 on $mux $procmux$25578. + dead port 1/2 on $mux $procmux$25581. + dead port 1/2 on $mux $procmux$25584. + dead port 1/2 on $mux $procmux$25587. + dead port 1/2 on $mux $procmux$25590. + dead port 1/2 on $mux $procmux$25593. + dead port 1/2 on $mux $procmux$25596. + dead port 1/2 on $mux $procmux$25599. + dead port 1/2 on $mux $procmux$25602. + dead port 1/2 on $mux $procmux$25605. + dead port 1/2 on $mux $procmux$25608. + dead port 2/2 on $mux $procmux$25610. + dead port 1/2 on $mux $procmux$25613. + dead port 1/2 on $mux $procmux$25616. + dead port 1/2 on $mux $procmux$25619. + dead port 1/2 on $mux $procmux$25622. + dead port 1/2 on $mux $procmux$25625. + dead port 1/2 on $mux $procmux$25628. + dead port 1/2 on $mux $procmux$25631. + dead port 1/2 on $mux $procmux$25634. + dead port 1/2 on $mux $procmux$25637. + dead port 1/2 on $mux $procmux$25640. + dead port 1/2 on $mux $procmux$25643. + dead port 2/2 on $mux $procmux$25646. + dead port 1/2 on $mux $procmux$25653. + dead port 1/2 on $mux $procmux$25656. + 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dead port 2/2 on $mux $procmux$25733. + dead port 1/2 on $mux $procmux$25914. + dead port 1/2 on $mux $procmux$25917. + dead port 1/2 on $mux $procmux$25920. + dead port 1/2 on $mux $procmux$25923. + dead port 1/2 on $mux $procmux$25926. + dead port 1/2 on $mux $procmux$25929. + dead port 1/2 on $mux $procmux$25932. + dead port 1/2 on $mux $procmux$25935. + dead port 1/2 on $mux $procmux$25938. + dead port 1/2 on $mux $procmux$25941. + dead port 1/2 on $mux $procmux$25944. + dead port 1/2 on $mux $procmux$25947. + dead port 1/2 on $mux $procmux$25950. + dead port 1/2 on $mux $procmux$25953. + dead port 1/2 on $mux $procmux$25956. + dead port 2/2 on $mux $procmux$25958. + dead port 1/2 on $mux $procmux$25961. + dead port 1/2 on $mux $procmux$25964. + dead port 1/2 on $mux $procmux$25967. + dead port 1/2 on $mux $procmux$25970. + dead port 1/2 on $mux $procmux$25973. + dead port 1/2 on $mux $procmux$25976. + dead port 1/2 on $mux $procmux$25979. + dead port 1/2 on $mux $procmux$25982. + dead port 1/2 on $mux $procmux$25985. + dead port 1/2 on $mux $procmux$25988. + dead port 1/2 on $mux $procmux$25991. + dead port 2/2 on $mux $procmux$25994. + dead port 1/2 on $mux $procmux$26001. + dead port 1/2 on $mux $procmux$26004. + dead port 1/2 on $mux $procmux$26007. + dead port 1/2 on $mux $procmux$26010. + dead port 1/2 on $mux $procmux$26013. + dead port 1/2 on $mux $procmux$26016. + dead port 1/2 on $mux $procmux$26019. + dead port 1/2 on $mux $procmux$26022. + dead port 1/2 on $mux $procmux$26025. + dead port 1/2 on $mux $procmux$26028. + dead port 1/2 on $mux $procmux$26031. + dead port 1/2 on $mux $procmux$26034. + dead port 1/2 on $mux $procmux$26037. + dead port 1/2 on $mux $procmux$26040. + dead port 1/2 on $mux $procmux$26043. + dead port 2/2 on $mux $procmux$26045. + dead port 1/2 on $mux $procmux$26048. + dead port 1/2 on $mux $procmux$26051. + dead port 1/2 on $mux $procmux$26054. + dead port 1/2 on $mux $procmux$26057. + dead port 1/2 on $mux $procmux$26060. + dead port 1/2 on $mux $procmux$26063. + dead port 1/2 on $mux $procmux$26066. + dead port 1/2 on $mux $procmux$26069. + dead port 1/2 on $mux $procmux$26072. + dead port 1/2 on $mux $procmux$26075. + dead port 1/2 on $mux $procmux$26078. + dead port 2/2 on $mux $procmux$26081. + dead port 1/2 on $mux $procmux$26089. + dead port 1/2 on $mux $procmux$26092. + dead port 1/2 on $mux $procmux$26095. + dead port 2/2 on $mux $procmux$26097. + dead port 1/2 on $mux $procmux$26100. + dead port 1/2 on $mux $procmux$26103. + dead port 1/2 on $mux $procmux$26106. + dead port 1/2 on $mux $procmux$26109. + dead port 1/2 on $mux $procmux$26112. + dead port 1/2 on $mux $procmux$26115. + dead port 1/2 on $mux $procmux$26118. + dead port 1/2 on $mux $procmux$26121. + dead port 1/2 on $mux $procmux$26124. + dead port 1/2 on $mux $procmux$26127. + dead port 1/2 on $mux $procmux$26130. + dead port 1/2 on $mux $procmux$26133. + dead port 1/2 on $mux $procmux$26136. + dead port 1/2 on $mux $procmux$26139. + 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dead port 1/2 on $mux $procmux$26473. + dead port 1/2 on $mux $procmux$26476. + dead port 2/2 on $mux $procmux$26478. + dead port 1/2 on $mux $procmux$26481. + dead port 1/2 on $mux $procmux$26484. + dead port 1/2 on $mux $procmux$26487. + dead port 1/2 on $mux $procmux$26490. + dead port 1/2 on $mux $procmux$26493. + dead port 1/2 on $mux $procmux$26496. + dead port 1/2 on $mux $procmux$26499. + dead port 1/2 on $mux $procmux$26502. + dead port 1/2 on $mux $procmux$26505. + dead port 1/2 on $mux $procmux$26508. + dead port 1/2 on $mux $procmux$26511. + dead port 1/2 on $mux $procmux$26514. + dead port 1/2 on $mux $procmux$26517. + dead port 1/2 on $mux $procmux$26520. + dead port 2/2 on $mux $procmux$26522. + dead port 1/2 on $mux $procmux$26525. + dead port 1/2 on $mux $procmux$26528. + dead port 1/2 on $mux $procmux$26531. + dead port 1/2 on $mux $procmux$26534. + dead port 1/2 on $mux $procmux$26537. + dead port 1/2 on $mux $procmux$26540. + dead port 1/2 on $mux $procmux$26543. + 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dead port 1/2 on $mux $procmux$32124. + dead port 1/2 on $mux $procmux$32127. + dead port 1/2 on $mux $procmux$32130. + dead port 1/2 on $mux $procmux$32133. + dead port 1/2 on $mux $procmux$32136. + dead port 2/2 on $mux $procmux$32138. + dead port 1/2 on $mux $procmux$32141. + dead port 1/2 on $mux $procmux$32144. + dead port 1/2 on $mux $procmux$32147. + dead port 1/2 on $mux $procmux$32150. + dead port 1/2 on $mux $procmux$32153. + dead port 1/2 on $mux $procmux$32156. + dead port 1/2 on $mux $procmux$32159. + dead port 1/2 on $mux $procmux$32162. + dead port 1/2 on $mux $procmux$32165. + dead port 1/2 on $mux $procmux$32168. + dead port 1/2 on $mux $procmux$32171. + dead port 2/2 on $mux $procmux$32174. + dead port 1/2 on $mux $procmux$32262. + dead port 1/2 on $mux $procmux$32265. + dead port 1/2 on $mux $procmux$32268. + dead port 1/2 on $mux $procmux$32271. + dead port 1/2 on $mux $procmux$32274. + dead port 1/2 on $mux $procmux$32277. + dead port 1/2 on $mux $procmux$32280. + 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dead port 1/2 on $mux $procmux$32595. + dead port 1/2 on $mux $procmux$32598. + dead port 1/2 on $mux $procmux$32601. + dead port 1/2 on $mux $procmux$32604. + dead port 1/2 on $mux $procmux$32607. + dead port 1/2 on $mux $procmux$32610. + dead port 1/2 on $mux $procmux$32613. + dead port 1/2 on $mux $procmux$32616. + dead port 1/2 on $mux $procmux$32619. + dead port 1/2 on $mux $procmux$32622. + dead port 2/2 on $mux $procmux$32624. + dead port 1/2 on $mux $procmux$32627. + dead port 1/2 on $mux $procmux$32630. + dead port 1/2 on $mux $procmux$32633. + dead port 1/2 on $mux $procmux$32636. + dead port 1/2 on $mux $procmux$32639. + dead port 1/2 on $mux $procmux$32642. + dead port 1/2 on $mux $procmux$32645. + dead port 1/2 on $mux $procmux$32648. + dead port 1/2 on $mux $procmux$32651. + dead port 1/2 on $mux $procmux$32654. + dead port 1/2 on $mux $procmux$32657. + dead port 2/2 on $mux $procmux$32660. + dead port 1/2 on $mux $procmux$32667. + dead port 1/2 on $mux $procmux$32670. + dead port 1/2 on $mux $procmux$32673. + dead port 1/2 on $mux $procmux$32676. + dead port 1/2 on $mux $procmux$32679. + dead port 1/2 on $mux $procmux$32682. + dead port 1/2 on $mux $procmux$32685. + dead port 1/2 on $mux $procmux$32688. + dead port 1/2 on $mux $procmux$32691. + dead port 1/2 on $mux $procmux$32694. + dead port 1/2 on $mux $procmux$32697. + dead port 1/2 on $mux $procmux$32700. + dead port 1/2 on $mux $procmux$32703. + dead port 2/2 on $mux $procmux$32705. + dead port 1/2 on $mux $procmux$32708. + dead port 1/2 on $mux $procmux$32711. + dead port 1/2 on $mux $procmux$32714. + dead port 1/2 on $mux $procmux$32717. + dead port 1/2 on $mux $procmux$32720. + dead port 1/2 on $mux $procmux$32723. + dead port 1/2 on $mux $procmux$32726. + dead port 1/2 on $mux $procmux$32729. + dead port 1/2 on $mux $procmux$32732. + dead port 1/2 on $mux $procmux$32735. + dead port 1/2 on $mux $procmux$32738. + dead port 2/2 on $mux $procmux$32741. + dead port 1/2 on $mux $procmux$32748. + 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dead port 1/2 on $mux $procmux$51036. + dead port 1/2 on $mux $procmux$51039. + dead port 1/2 on $mux $procmux$51042. + dead port 1/2 on $mux $procmux$51045. + dead port 1/2 on $mux $procmux$51048. + dead port 1/2 on $mux $procmux$51051. + dead port 1/2 on $mux $procmux$51054. + dead port 1/2 on $mux $procmux$51057. + dead port 1/2 on $mux $procmux$51060. + dead port 2/2 on $mux $procmux$51062. + dead port 1/2 on $mux $procmux$51065. + dead port 1/2 on $mux $procmux$51068. + dead port 1/2 on $mux $procmux$51071. + dead port 1/2 on $mux $procmux$51074. + dead port 1/2 on $mux $procmux$51077. + dead port 1/2 on $mux $procmux$51080. + dead port 1/2 on $mux $procmux$51083. + dead port 1/2 on $mux $procmux$51086. + dead port 1/2 on $mux $procmux$51089. + dead port 1/2 on $mux $procmux$51092. + dead port 1/2 on $mux $procmux$51095. + dead port 2/2 on $mux $procmux$51098. + dead port 1/2 on $mux $procmux$51105. + dead port 1/2 on $mux $procmux$51108. + dead port 1/2 on $mux $procmux$51111. + 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dead port 1/2 on $mux $procmux$51347. + dead port 1/2 on $mux $procmux$51350. + dead port 1/2 on $mux $procmux$51353. + dead port 1/2 on $mux $procmux$51356. + dead port 1/2 on $mux $procmux$51359. + dead port 1/2 on $mux $procmux$51362. + dead port 1/2 on $mux $procmux$51365. + dead port 1/2 on $mux $procmux$51368. + dead port 1/2 on $mux $procmux$51371. + dead port 2/2 on $mux $procmux$51374. + dead port 1/2 on $mux $procmux$51519. + dead port 1/2 on $mux $procmux$51522. + dead port 1/2 on $mux $procmux$51525. + dead port 1/2 on $mux $procmux$51528. + dead port 1/2 on $mux $procmux$51531. + dead port 1/2 on $mux $procmux$51534. + dead port 1/2 on $mux $procmux$51537. + dead port 1/2 on $mux $procmux$51540. + dead port 1/2 on $mux $procmux$51543. + dead port 2/2 on $mux $procmux$51545. + dead port 1/2 on $mux $procmux$51548. + dead port 1/2 on $mux $procmux$51551. + dead port 1/2 on $mux $procmux$51554. + dead port 1/2 on $mux $procmux$51557. + dead port 1/2 on $mux $procmux$51560. + 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$procmux$79358. + dead port 1/2 on $mux $procmux$7936. + dead port 1/2 on $mux $procmux$79361. + dead port 2/2 on $mux $procmux$79364. + dead port 1/2 on $mux $procmux$79371. + dead port 1/2 on $mux $procmux$79374. + dead port 1/2 on $mux $procmux$79377. + dead port 1/2 on $mux $procmux$79380. + dead port 2/2 on $mux $procmux$79382. + dead port 1/2 on $mux $procmux$79385. + dead port 1/2 on $mux $procmux$79388. + dead port 1/2 on $mux $procmux$7939. + dead port 1/2 on $mux $procmux$79391. + dead port 1/2 on $mux $procmux$79394. + dead port 1/2 on $mux $procmux$79397. + dead port 1/2 on $mux $procmux$79400. + dead port 1/2 on $mux $procmux$79403. + dead port 1/2 on $mux $procmux$79406. + dead port 1/2 on $mux $procmux$79409. + dead port 1/2 on $mux $procmux$79412. + dead port 1/2 on $mux $procmux$79415. + dead port 2/2 on $mux $procmux$79418. + dead port 1/2 on $mux $procmux$7942. + dead port 1/2 on $mux $procmux$79425. + dead port 1/2 on $mux $procmux$79428. + dead port 1/2 on $mux $procmux$79431. + dead port 1/2 on $mux $procmux$79434. + dead port 2/2 on $mux $procmux$79436. + dead port 1/2 on $mux $procmux$79439. + dead port 1/2 on $mux $procmux$79442. + dead port 1/2 on $mux $procmux$79445. + dead port 1/2 on $mux $procmux$79448. + dead port 1/2 on $mux $procmux$7945. + dead port 1/2 on $mux $procmux$79451. + dead port 1/2 on $mux $procmux$79454. + dead port 1/2 on $mux $procmux$79457. + dead port 1/2 on $mux $procmux$79460. + dead port 1/2 on $mux $procmux$79463. + dead port 1/2 on $mux $procmux$79466. + dead port 1/2 on $mux $procmux$79469. + dead port 2/2 on $mux $procmux$79472. + dead port 1/2 on $mux $procmux$79479. + dead port 1/2 on $mux $procmux$7948. + dead port 1/2 on $mux $procmux$79482. + dead port 1/2 on $mux $procmux$79485. + dead port 1/2 on $mux $procmux$79488. + dead port 2/2 on $mux $procmux$79490. + dead port 1/2 on $mux $procmux$79493. + dead port 1/2 on $mux $procmux$79496. + dead port 1/2 on $mux $procmux$79499. + dead port 1/2 on $mux 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$mux $procmux$8256. + dead port 1/2 on $mux $procmux$8259. + dead port 1/2 on $mux $procmux$8262. + dead port 1/2 on $mux $procmux$8265. + dead port 1/2 on $mux $procmux$8268. + dead port 1/2 on $mux $procmux$8271. + dead port 1/2 on $mux $procmux$8274. + dead port 1/2 on $mux $procmux$8277. + dead port 1/2 on $mux $procmux$8280. + dead port 1/2 on $mux $procmux$8283. + dead port 1/2 on $mux $procmux$8286. + dead port 1/2 on $mux $procmux$8289. + dead port 2/2 on $mux $procmux$8292. + dead port 1/2 on $mux $procmux$8299. + dead port 2/2 on $mux $procmux$8302. + dead port 1/2 on $mux $procmux$8305. + dead port 1/2 on $mux $procmux$8308. + dead port 1/2 on $mux $procmux$8311. + dead port 1/2 on $mux $procmux$8314. + dead port 1/2 on $mux $procmux$8317. + dead port 1/2 on $mux $procmux$8320. + dead port 1/2 on $mux $procmux$8323. + dead port 1/2 on $mux $procmux$8326. + dead port 1/2 on $mux $procmux$8329. + dead port 1/2 on $mux $procmux$8332. + dead port 1/2 on $mux $procmux$8335. + dead port 1/2 on $mux $procmux$8338. + dead port 1/2 on $mux $procmux$8341. + dead port 1/2 on $mux $procmux$8344. + dead port 1/2 on $mux $procmux$8347. + dead port 2/2 on $mux $procmux$8349. + dead port 1/2 on $mux $procmux$8352. + dead port 1/2 on $mux $procmux$8355. + dead port 1/2 on $mux $procmux$8358. + dead port 1/2 on $mux $procmux$8361. + dead port 1/2 on $mux $procmux$8364. + dead port 1/2 on $mux $procmux$8367. + dead port 1/2 on $mux $procmux$8370. + dead port 1/2 on $mux $procmux$8373. + dead port 1/2 on $mux $procmux$8376. + dead port 1/2 on $mux $procmux$8379. + dead port 1/2 on $mux $procmux$8382. + dead port 2/2 on $mux $procmux$8385. + dead port 1/2 on $mux $procmux$8392. + dead port 2/2 on $mux $procmux$8395. + dead port 1/2 on $mux $procmux$8398. + dead port 1/2 on $mux $procmux$8401. + dead port 1/2 on $mux $procmux$8404. + dead port 1/2 on $mux $procmux$8407. + dead port 1/2 on $mux $procmux$8410. + dead port 1/2 on $mux $procmux$8413. + dead port 1/2 on $mux $procmux$8416. + dead port 1/2 on $mux $procmux$8419. + dead port 1/2 on $mux $procmux$8422. + dead port 1/2 on $mux $procmux$8425. + dead port 1/2 on $mux $procmux$8428. + dead port 1/2 on $mux $procmux$8431. + dead port 1/2 on $mux $procmux$8434. + dead port 1/2 on $mux $procmux$8437. + dead port 1/2 on $mux $procmux$8440. + dead port 2/2 on $mux $procmux$8442. + dead port 1/2 on $mux $procmux$8445. + dead port 1/2 on $mux $procmux$8448. + dead port 1/2 on $mux $procmux$8451. + dead port 1/2 on $mux $procmux$8454. + dead port 1/2 on $mux $procmux$8457. + dead port 1/2 on $mux $procmux$8460. + dead port 1/2 on $mux $procmux$8463. + dead port 1/2 on $mux $procmux$8466. + dead port 1/2 on $mux $procmux$8469. + dead port 1/2 on $mux $procmux$8472. + dead port 1/2 on $mux $procmux$8475. + dead port 2/2 on $mux $procmux$8478. + dead port 2/2 on $mux $procmux$8485. + dead port 1/2 on $mux $procmux$8488. + dead port 1/2 on $mux $procmux$8491. + dead port 1/2 on $mux $procmux$8494. + dead port 1/2 on $mux $procmux$8497. + dead port 1/2 on $mux $procmux$8500. + dead port 1/2 on $mux $procmux$8503. + dead port 1/2 on $mux $procmux$8506. + dead port 1/2 on $mux $procmux$8509. + dead port 1/2 on $mux $procmux$8512. + dead port 1/2 on $mux $procmux$85146. + dead port 1/2 on $mux $procmux$85149. + dead port 1/2 on $mux $procmux$8515. + dead port 1/2 on $mux $procmux$85152. + dead port 2/2 on $mux $procmux$85154. + dead port 1/2 on $mux $procmux$85157. + dead port 1/2 on $mux $procmux$85160. + dead port 1/2 on $mux $procmux$85163. + dead port 1/2 on $mux $procmux$85166. + dead port 1/2 on $mux $procmux$85169. + dead port 1/2 on $mux $procmux$85172. + dead port 1/2 on $mux $procmux$85175. + dead port 1/2 on $mux $procmux$85178. + dead port 1/2 on $mux $procmux$8518. + dead port 1/2 on $mux $procmux$85181. + dead port 1/2 on $mux $procmux$85184. + dead port 1/2 on $mux $procmux$85187. + dead port 2/2 on $mux $procmux$85190. + dead port 1/2 on $mux $procmux$85197. + dead port 1/2 on $mux $procmux$85200. + dead port 1/2 on $mux $procmux$85203. + dead port 2/2 on $mux $procmux$85205. + dead port 1/2 on $mux $procmux$85208. + dead port 1/2 on $mux $procmux$8521. + dead port 1/2 on $mux $procmux$85211. + dead port 1/2 on $mux $procmux$85214. + dead port 1/2 on $mux $procmux$85217. + dead port 1/2 on $mux $procmux$85220. + dead port 1/2 on $mux $procmux$85223. + dead port 1/2 on $mux $procmux$85226. + dead port 1/2 on $mux $procmux$85229. + dead port 1/2 on $mux $procmux$85232. + dead port 1/2 on $mux $procmux$85235. + dead port 1/2 on $mux $procmux$85238. + dead port 1/2 on $mux $procmux$8524. + dead port 2/2 on $mux $procmux$85241. + dead port 1/2 on $mux $procmux$8527. + dead port 1/2 on $mux $procmux$85299. + dead port 1/2 on $mux $procmux$8530. + dead port 1/2 on $mux $procmux$85302. + dead port 1/2 on $mux $procmux$85305. + dead port 2/2 on $mux $procmux$85307. + dead port 1/2 on $mux $procmux$85310. + dead port 1/2 on $mux $procmux$85313. + dead port 1/2 on $mux $procmux$85316. + dead port 1/2 on $mux $procmux$85319. + dead port 2/2 on $mux $procmux$8532. + dead port 1/2 on $mux $procmux$85322. + dead port 1/2 on $mux $procmux$85325. + dead port 1/2 on $mux $procmux$85328. + dead port 1/2 on $mux $procmux$85331. + dead port 1/2 on $mux $procmux$85334. + dead port 1/2 on $mux $procmux$85337. + dead port 1/2 on $mux $procmux$85340. + dead port 2/2 on $mux $procmux$85343. + dead port 1/2 on $mux $procmux$8535. + dead port 1/2 on $mux $procmux$85350. + dead port 1/2 on $mux $procmux$85353. + dead port 1/2 on $mux $procmux$85356. + dead port 2/2 on $mux $procmux$85358. + dead port 1/2 on $mux $procmux$85361. + dead port 1/2 on $mux $procmux$85364. + dead port 1/2 on $mux $procmux$85367. + dead port 1/2 on $mux $procmux$85370. + dead port 1/2 on $mux $procmux$85373. + dead port 1/2 on $mux $procmux$85376. + dead port 1/2 on $mux $procmux$85379. + dead port 1/2 on $mux $procmux$8538. + dead port 1/2 on $mux $procmux$85382. + dead port 1/2 on $mux $procmux$85385. + dead port 1/2 on $mux $procmux$85388. + dead port 1/2 on $mux $procmux$85391. + dead port 2/2 on $mux $procmux$85394. + dead port 1/2 on $mux $procmux$85401. + dead port 1/2 on $mux $procmux$85404. + dead port 1/2 on $mux $procmux$85407. + dead port 2/2 on $mux $procmux$85409. + dead port 1/2 on $mux $procmux$8541. + dead port 1/2 on $mux $procmux$85412. + dead port 1/2 on $mux $procmux$85415. + dead port 1/2 on $mux $procmux$85418. + dead port 1/2 on $mux $procmux$85421. + dead port 1/2 on $mux $procmux$85424. + dead port 1/2 on $mux $procmux$85427. + dead port 1/2 on $mux $procmux$85430. + dead port 1/2 on $mux $procmux$85433. + dead port 1/2 on $mux $procmux$85436. + dead port 1/2 on $mux $procmux$85439. + dead port 1/2 on $mux $procmux$8544. + dead port 1/2 on $mux $procmux$85442. + dead port 2/2 on $mux $procmux$85445. + dead port 1/2 on $mux $procmux$85452. + dead port 1/2 on $mux $procmux$85455. + dead port 1/2 on $mux $procmux$85458. + dead port 2/2 on $mux $procmux$85460. + dead port 1/2 on $mux $procmux$85463. + dead port 1/2 on $mux $procmux$85466. + dead port 1/2 on $mux $procmux$85469. + dead port 1/2 on $mux $procmux$8547. + dead port 1/2 on $mux $procmux$85472. + dead port 1/2 on $mux $procmux$85475. + dead port 1/2 on $mux $procmux$85478. + dead port 1/2 on $mux $procmux$85481. + dead port 1/2 on $mux $procmux$85484. + dead port 1/2 on $mux $procmux$85487. + dead port 1/2 on $mux $procmux$85490. + dead port 1/2 on $mux $procmux$85493. + dead port 2/2 on $mux $procmux$85496. + dead port 1/2 on $mux $procmux$8550. + dead port 1/2 on $mux $procmux$85503. + dead port 1/2 on $mux $procmux$85506. + dead port 1/2 on $mux $procmux$85509. + dead port 2/2 on $mux $procmux$85511. + dead port 1/2 on $mux $procmux$85514. + dead port 1/2 on $mux $procmux$85517. + dead port 1/2 on $mux $procmux$85520. + dead port 1/2 on $mux $procmux$85523. + dead port 1/2 on $mux $procmux$85526. + dead port 1/2 on $mux $procmux$85529. + dead port 1/2 on $mux $procmux$8553. + dead port 1/2 on $mux $procmux$85532. + dead port 1/2 on $mux $procmux$85535. + dead port 1/2 on $mux $procmux$85538. + dead port 1/2 on $mux $procmux$85541. + dead port 1/2 on $mux $procmux$85544. + dead port 2/2 on $mux $procmux$85547. + dead port 1/2 on $mux $procmux$85554. + dead port 1/2 on $mux $procmux$85557. + dead port 1/2 on $mux $procmux$8556. + dead port 1/2 on $mux $procmux$85560. + dead port 2/2 on $mux $procmux$85562. + dead port 1/2 on $mux $procmux$85565. + dead port 1/2 on $mux $procmux$85568. + dead port 1/2 on $mux $procmux$85571. + dead port 1/2 on $mux $procmux$85574. + dead port 1/2 on $mux $procmux$85577. + dead port 1/2 on $mux $procmux$85580. + dead port 1/2 on $mux $procmux$85583. + dead port 1/2 on $mux $procmux$85586. + dead port 1/2 on $mux $procmux$85589. + dead port 1/2 on $mux $procmux$8559. + dead port 1/2 on $mux $procmux$85592. + dead port 1/2 on $mux $procmux$85595. + dead port 2/2 on $mux $procmux$85598. + dead port 1/2 on $mux $procmux$85605. + dead port 1/2 on $mux $procmux$85608. + dead port 1/2 on $mux $procmux$85611. + dead port 2/2 on $mux $procmux$85613. + dead port 1/2 on $mux $procmux$85616. + dead port 1/2 on $mux $procmux$85619. + dead port 1/2 on $mux $procmux$8562. + dead port 1/2 on $mux $procmux$85622. + dead port 1/2 on $mux $procmux$85625. + dead port 1/2 on $mux $procmux$85628. + dead port 1/2 on $mux $procmux$85631. + dead port 1/2 on $mux $procmux$85634. + dead port 1/2 on $mux $procmux$85637. + dead port 1/2 on $mux $procmux$85640. + dead port 1/2 on $mux $procmux$85643. + dead port 1/2 on $mux $procmux$85646. + dead port 2/2 on $mux $procmux$85649. + dead port 1/2 on $mux $procmux$8565. + dead port 2/2 on $mux $procmux$8568. + dead port 2/2 on $mux $procmux$8575. + dead port 1/2 on $mux $procmux$85758. + dead port 1/2 on $mux $procmux$85761. + dead port 1/2 on $mux $procmux$85764. + dead port 2/2 on $mux $procmux$85766. + dead port 1/2 on $mux $procmux$85769. + dead port 1/2 on $mux $procmux$85772. + dead port 1/2 on $mux $procmux$85775. + dead port 1/2 on $mux $procmux$85778. + dead port 2/2 on $mux $procmux$8578. + dead port 1/2 on $mux $procmux$85781. + dead port 1/2 on $mux $procmux$85784. + dead port 1/2 on $mux $procmux$85787. + dead port 1/2 on $mux $procmux$85790. + dead port 1/2 on $mux $procmux$85793. + dead port 1/2 on $mux $procmux$85796. + dead port 1/2 on $mux $procmux$85799. + dead port 2/2 on $mux $procmux$85802. + dead port 1/2 on $mux $procmux$85809. + dead port 1/2 on $mux $procmux$8581. + dead port 1/2 on $mux $procmux$85812. + dead port 1/2 on $mux $procmux$85815. + dead port 2/2 on $mux $procmux$85817. + dead port 1/2 on $mux $procmux$85820. + dead port 1/2 on $mux $procmux$85823. + dead port 1/2 on $mux $procmux$85826. + dead port 1/2 on $mux $procmux$85829. + dead port 1/2 on $mux $procmux$85832. + dead port 1/2 on $mux $procmux$85835. + dead port 1/2 on $mux $procmux$85838. + dead port 1/2 on $mux $procmux$8584. + dead port 1/2 on $mux $procmux$85841. + dead port 1/2 on $mux $procmux$85844. + dead port 1/2 on $mux $procmux$85847. + dead port 1/2 on $mux $procmux$85850. + dead port 2/2 on $mux $procmux$85853. + dead port 1/2 on $mux $procmux$85860. + dead port 1/2 on $mux $procmux$85863. + dead port 1/2 on $mux $procmux$85866. + dead port 2/2 on $mux $procmux$85868. + dead port 1/2 on $mux $procmux$8587. + dead port 1/2 on $mux $procmux$85871. + dead port 1/2 on $mux $procmux$85874. + dead port 1/2 on $mux $procmux$85877. + dead port 1/2 on $mux $procmux$85880. + dead port 1/2 on $mux $procmux$85883. + dead port 1/2 on $mux $procmux$85886. + dead port 1/2 on $mux $procmux$85889. + dead port 1/2 on $mux $procmux$85892. + dead port 1/2 on $mux $procmux$85895. + dead port 1/2 on $mux $procmux$85898. + dead port 1/2 on $mux $procmux$8590. + dead port 1/2 on $mux $procmux$85901. + dead port 2/2 on $mux $procmux$85904. + dead port 1/2 on $mux $procmux$85911. + dead port 1/2 on $mux $procmux$85914. + dead port 1/2 on $mux $procmux$85917. + dead port 2/2 on $mux $procmux$85919. + dead port 1/2 on $mux $procmux$85922. + dead port 1/2 on $mux $procmux$85925. + dead port 1/2 on $mux $procmux$85928. + dead port 1/2 on $mux $procmux$8593. + dead port 1/2 on $mux $procmux$85931. + dead port 1/2 on $mux $procmux$85934. + dead port 1/2 on $mux $procmux$85937. + dead port 1/2 on $mux $procmux$85940. + dead port 1/2 on $mux $procmux$85943. + dead port 1/2 on $mux $procmux$85946. + dead port 1/2 on $mux $procmux$85949. + dead port 1/2 on $mux $procmux$85952. + dead port 2/2 on $mux $procmux$85955. + dead port 1/2 on $mux $procmux$8596. + dead port 1/2 on $mux $procmux$85962. + dead port 1/2 on $mux $procmux$85965. + dead port 1/2 on $mux $procmux$85968. + dead port 2/2 on $mux $procmux$85970. + dead port 1/2 on $mux $procmux$85973. + dead port 1/2 on $mux $procmux$85976. + dead port 1/2 on $mux $procmux$85979. + dead port 1/2 on $mux $procmux$85982. + dead port 1/2 on $mux $procmux$85985. + dead port 1/2 on $mux $procmux$85988. + dead port 1/2 on $mux $procmux$8599. + dead port 1/2 on $mux $procmux$85991. + dead port 1/2 on $mux $procmux$85994. + dead port 1/2 on $mux $procmux$85997. + dead port 1/2 on $mux $procmux$86000. + dead port 1/2 on $mux $procmux$86003. + dead port 2/2 on $mux $procmux$86006. + dead port 1/2 on $mux $procmux$86013. + dead port 1/2 on $mux $procmux$86016. + dead port 1/2 on $mux $procmux$86019. + dead port 1/2 on $mux $procmux$8602. + dead port 2/2 on $mux $procmux$86021. + dead port 1/2 on $mux $procmux$86024. + dead port 1/2 on $mux $procmux$86027. + dead port 1/2 on $mux $procmux$86030. + dead port 1/2 on $mux $procmux$86033. + dead port 1/2 on $mux $procmux$86036. + dead port 1/2 on $mux $procmux$86039. + dead port 1/2 on $mux $procmux$86042. + dead port 1/2 on $mux $procmux$86045. + dead port 1/2 on $mux $procmux$86048. + dead port 1/2 on $mux $procmux$8605. + dead port 1/2 on $mux $procmux$86051. + dead port 1/2 on $mux $procmux$86054. + dead port 2/2 on $mux $procmux$86057. + dead port 1/2 on $mux $procmux$86064. + dead port 1/2 on $mux $procmux$86067. + dead port 1/2 on $mux $procmux$86070. + dead port 2/2 on $mux $procmux$86072. + dead port 1/2 on $mux $procmux$86075. + dead port 1/2 on $mux $procmux$86078. + dead port 1/2 on $mux $procmux$8608. + dead port 1/2 on $mux $procmux$86081. + dead port 1/2 on $mux $procmux$86084. + dead port 1/2 on $mux $procmux$86087. + dead port 1/2 on $mux $procmux$86090. + dead port 1/2 on $mux $procmux$86093. + dead port 1/2 on $mux $procmux$86096. + dead port 1/2 on $mux $procmux$86099. + dead port 1/2 on $mux $procmux$86102. + dead port 1/2 on $mux $procmux$86105. + dead port 2/2 on $mux $procmux$86108. + dead port 1/2 on $mux $procmux$8611. + dead port 1/2 on $mux $procmux$86115. + dead port 1/2 on $mux $procmux$86118. + dead port 1/2 on $mux $procmux$86121. + dead port 2/2 on $mux $procmux$86123. + dead port 1/2 on $mux $procmux$86126. + dead port 1/2 on $mux $procmux$86129. + dead port 1/2 on $mux $procmux$86132. + dead port 1/2 on $mux $procmux$86135. + dead port 1/2 on $mux $procmux$86138. + dead port 1/2 on $mux $procmux$8614. + dead port 1/2 on $mux $procmux$86141. + dead port 1/2 on $mux $procmux$86144. + dead port 1/2 on $mux $procmux$86147. + dead port 1/2 on $mux $procmux$86150. + dead port 1/2 on $mux $procmux$86153. + dead port 1/2 on $mux $procmux$86156. + dead port 2/2 on $mux $procmux$86159. + dead port 1/2 on $mux $procmux$86166. + dead port 1/2 on $mux $procmux$86169. + dead port 1/2 on $mux $procmux$8617. + dead port 1/2 on $mux $procmux$86172. + dead port 2/2 on $mux $procmux$86174. + dead port 1/2 on $mux $procmux$86177. + dead port 1/2 on $mux $procmux$86180. + dead port 1/2 on $mux $procmux$86183. + dead port 1/2 on $mux $procmux$86186. + dead port 1/2 on $mux $procmux$86189. + dead port 1/2 on $mux $procmux$86192. + dead port 1/2 on $mux $procmux$86195. + dead port 1/2 on $mux $procmux$86198. + dead port 1/2 on $mux $procmux$8620. + dead port 1/2 on $mux $procmux$86201. + dead port 1/2 on $mux $procmux$86204. + dead port 1/2 on $mux $procmux$86207. + dead port 2/2 on $mux $procmux$86210. + dead port 1/2 on $mux $procmux$86217. + dead port 1/2 on $mux $procmux$86220. + dead port 1/2 on $mux $procmux$86223. + dead port 2/2 on $mux $procmux$86225. + dead port 1/2 on $mux $procmux$86228. + dead port 1/2 on $mux $procmux$8623. + dead port 1/2 on $mux $procmux$86231. + dead port 1/2 on $mux $procmux$86234. + dead port 1/2 on $mux $procmux$86237. + dead port 1/2 on $mux $procmux$86240. + dead port 1/2 on $mux $procmux$86243. + dead port 1/2 on $mux $procmux$86246. + dead port 1/2 on $mux $procmux$86249. + dead port 2/2 on $mux $procmux$8625. + dead port 1/2 on $mux $procmux$86252. + dead port 1/2 on $mux $procmux$86255. + dead port 1/2 on $mux $procmux$86258. + dead port 2/2 on $mux $procmux$86261. + dead port 1/2 on $mux $procmux$8628. + dead port 1/2 on $mux $procmux$8631. + dead port 1/2 on $mux $procmux$86319. + dead port 1/2 on $mux $procmux$86322. + dead port 1/2 on $mux $procmux$86325. + dead port 2/2 on $mux $procmux$86327. + dead port 1/2 on $mux $procmux$86330. + dead port 1/2 on $mux $procmux$86333. + dead port 1/2 on $mux $procmux$86336. + dead port 1/2 on $mux $procmux$86339. + dead port 1/2 on $mux $procmux$8634. + dead port 1/2 on $mux $procmux$86342. + dead port 1/2 on $mux $procmux$86345. + dead port 1/2 on $mux $procmux$86348. + dead port 1/2 on $mux $procmux$86351. + dead port 1/2 on $mux $procmux$86354. + dead port 1/2 on $mux $procmux$86357. + dead port 1/2 on $mux $procmux$86360. + dead port 2/2 on $mux $procmux$86363. + dead port 1/2 on $mux $procmux$8637. + dead port 1/2 on $mux $procmux$86370. + dead port 1/2 on $mux $procmux$86373. + dead port 1/2 on $mux $procmux$86376. + dead port 2/2 on $mux $procmux$86378. + dead port 1/2 on $mux $procmux$86381. + dead port 1/2 on $mux $procmux$86384. + dead port 1/2 on $mux $procmux$86387. + dead port 1/2 on $mux $procmux$86390. + dead port 1/2 on $mux $procmux$86393. + dead port 1/2 on $mux $procmux$86396. + dead port 1/2 on $mux $procmux$86399. + dead port 1/2 on $mux $procmux$8640. + dead port 1/2 on $mux $procmux$86402. + dead port 1/2 on $mux $procmux$86405. + dead port 1/2 on $mux $procmux$86408. + dead port 1/2 on $mux $procmux$86411. + dead port 2/2 on $mux $procmux$86414. + dead port 1/2 on $mux $procmux$86421. + dead port 1/2 on $mux $procmux$86424. + dead port 1/2 on $mux $procmux$86427. + dead port 2/2 on $mux $procmux$86429. + dead port 1/2 on $mux $procmux$8643. + dead port 1/2 on $mux $procmux$86432. + dead port 1/2 on $mux $procmux$86435. + dead port 1/2 on $mux $procmux$86438. + dead port 1/2 on $mux $procmux$86441. + dead port 1/2 on $mux $procmux$86444. + dead port 1/2 on $mux $procmux$86447. + dead port 1/2 on $mux $procmux$86450. + dead port 1/2 on $mux $procmux$86453. + dead port 1/2 on $mux $procmux$86456. + dead port 1/2 on $mux $procmux$86459. + dead port 1/2 on $mux $procmux$8646. + dead port 1/2 on $mux $procmux$86462. + dead port 2/2 on $mux $procmux$86465. + dead port 1/2 on $mux $procmux$8649. + dead port 1/2 on $mux $procmux$8652. + dead port 1/2 on $mux $procmux$8655. + dead port 1/2 on $mux $procmux$8658. + dead port 2/2 on $mux $procmux$8661. + dead port 1/2 on $mux $procmux$86625. + dead port 1/2 on $mux $procmux$86628. + dead port 1/2 on $mux $procmux$86631. + dead port 2/2 on $mux $procmux$86633. + dead port 1/2 on $mux $procmux$86636. + dead port 1/2 on $mux $procmux$86639. + dead port 1/2 on $mux $procmux$86642. + dead port 1/2 on $mux $procmux$86645. + dead port 1/2 on $mux $procmux$86648. + dead port 1/2 on $mux $procmux$86651. + dead port 1/2 on $mux $procmux$86654. + dead port 1/2 on $mux $procmux$86657. + dead port 1/2 on $mux $procmux$86660. + dead port 1/2 on $mux $procmux$86663. + dead port 1/2 on $mux $procmux$86666. + dead port 2/2 on $mux $procmux$86669. + dead port 1/2 on $mux $procmux$86676. + dead port 1/2 on $mux $procmux$86679. + dead port 2/2 on $mux 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$procmux$98144. + dead port 1/2 on $mux $procmux$98147. + dead port 1/2 on $mux $procmux$98150. + dead port 1/2 on $mux $procmux$98153. + dead port 1/2 on $mux $procmux$98156. + dead port 1/2 on $mux $procmux$98159. + dead port 2/2 on $mux $procmux$98162. + dead port 1/2 on $mux $procmux$98259. + dead port 2/2 on $mux $procmux$98261. + dead port 1/2 on $mux $procmux$98264. + dead port 1/2 on $mux $procmux$98267. + dead port 1/2 on $mux $procmux$98270. + dead port 1/2 on $mux $procmux$98273. + dead port 1/2 on $mux $procmux$98276. + dead port 1/2 on $mux $procmux$98279. + dead port 1/2 on $mux $procmux$98282. + dead port 1/2 on $mux $procmux$98285. + dead port 1/2 on $mux $procmux$98288. + dead port 1/2 on $mux $procmux$98291. + dead port 1/2 on $mux $procmux$98294. + dead port 2/2 on $mux $procmux$98297. + dead port 1/2 on $mux $procmux$98304. + dead port 2/2 on $mux $procmux$98306. + dead port 1/2 on $mux $procmux$98309. + dead port 1/2 on $mux $procmux$98312. + dead port 1/2 on $mux $procmux$98315. + dead port 1/2 on $mux $procmux$98318. + dead port 1/2 on $mux $procmux$98321. + dead port 1/2 on $mux $procmux$98324. + dead port 1/2 on $mux $procmux$98327. + dead port 1/2 on $mux $procmux$98330. + dead port 1/2 on $mux $procmux$98333. + dead port 1/2 on $mux $procmux$98336. + dead port 1/2 on $mux $procmux$98339. + dead port 2/2 on $mux $procmux$98342. + dead port 1/2 on $mux $procmux$98349. + dead port 2/2 on $mux $procmux$98351. + dead port 1/2 on $mux $procmux$98354. + dead port 1/2 on $mux $procmux$98357. + dead port 1/2 on $mux $procmux$98360. + dead port 1/2 on $mux $procmux$98363. + dead port 1/2 on $mux $procmux$98366. + dead port 1/2 on $mux $procmux$98369. + dead port 1/2 on $mux $procmux$98372. + dead port 1/2 on $mux $procmux$98375. + dead port 1/2 on $mux $procmux$98378. + dead port 1/2 on $mux $procmux$98381. + dead port 1/2 on $mux $procmux$98384. + dead port 2/2 on $mux $procmux$98387. + dead port 1/2 on $mux $procmux$98394. + dead port 2/2 on $mux $procmux$98396. + dead port 1/2 on $mux $procmux$98399. + dead port 1/2 on $mux $procmux$98402. + dead port 1/2 on $mux $procmux$98405. + dead port 1/2 on $mux $procmux$98408. + dead port 1/2 on $mux $procmux$98411. + dead port 1/2 on $mux $procmux$98414. + dead port 1/2 on $mux $procmux$98417. + dead port 1/2 on $mux $procmux$98420. + dead port 1/2 on $mux $procmux$98423. + dead port 1/2 on $mux $procmux$98426. + dead port 1/2 on $mux $procmux$98429. + dead port 2/2 on $mux $procmux$98432. + dead port 1/2 on $mux $procmux$98439. + dead port 2/2 on $mux $procmux$98441. + dead port 1/2 on $mux $procmux$98444. + dead port 1/2 on $mux $procmux$98447. + dead port 1/2 on $mux $procmux$98450. + dead port 1/2 on $mux $procmux$98453. + dead port 1/2 on $mux $procmux$98456. + dead port 1/2 on $mux $procmux$98459. + dead port 1/2 on $mux $procmux$98462. + dead port 1/2 on $mux $procmux$98465. + dead port 1/2 on $mux $procmux$98468. + dead port 1/2 on $mux $procmux$98471. + dead port 1/2 on $mux $procmux$98474. + dead port 2/2 on $mux $procmux$98477. + dead port 1/2 on $mux $procmux$98484. + dead port 2/2 on $mux $procmux$98486. + dead port 1/2 on $mux $procmux$98489. + dead port 1/2 on $mux $procmux$98492. + dead port 1/2 on $mux $procmux$98495. + dead port 1/2 on $mux $procmux$98498. + dead port 1/2 on $mux $procmux$98501. + dead port 1/2 on $mux $procmux$98504. + dead port 1/2 on $mux $procmux$98507. + dead port 1/2 on $mux $procmux$98510. + dead port 1/2 on $mux $procmux$98513. + dead port 1/2 on $mux $procmux$98516. + dead port 1/2 on $mux $procmux$98519. + dead port 2/2 on $mux $procmux$98522. + dead port 1/2 on $mux $procmux$98529. + dead port 2/2 on $mux $procmux$98531. + dead port 1/2 on $mux $procmux$98534. + dead port 1/2 on $mux $procmux$98537. + dead port 1/2 on $mux $procmux$98540. + dead port 1/2 on $mux $procmux$98543. + dead port 1/2 on $mux $procmux$98546. + dead port 1/2 on $mux $procmux$98549. + dead port 1/2 on $mux $procmux$98552. + dead port 1/2 on $mux $procmux$98555. + dead port 1/2 on $mux $procmux$98558. + dead port 1/2 on $mux $procmux$98561. + dead port 1/2 on $mux $procmux$98564. + dead port 2/2 on $mux $procmux$98567. + dead port 1/2 on $mux $procmux$98574. + dead port 2/2 on $mux $procmux$98576. + dead port 1/2 on $mux $procmux$98579. + dead port 1/2 on $mux $procmux$98582. + dead port 1/2 on $mux $procmux$98585. + dead port 1/2 on $mux $procmux$98588. + dead port 1/2 on $mux $procmux$98591. + dead port 1/2 on $mux $procmux$98594. + dead port 1/2 on $mux $procmux$98597. + dead port 1/2 on $mux $procmux$98600. + dead port 1/2 on $mux $procmux$98603. + dead port 1/2 on $mux $procmux$98606. + dead port 1/2 on $mux $procmux$98609. + dead port 2/2 on $mux $procmux$98612. + dead port 1/2 on $mux $procmux$98619. + dead port 2/2 on $mux $procmux$98621. + dead port 1/2 on $mux $procmux$98624. + dead port 1/2 on $mux $procmux$98627. + dead port 1/2 on $mux $procmux$98630. + dead port 1/2 on $mux $procmux$98633. + dead port 1/2 on $mux $procmux$98636. + dead port 1/2 on $mux $procmux$98639. + dead port 1/2 on $mux $procmux$98642. + dead port 1/2 on $mux $procmux$98645. + dead port 1/2 on $mux $procmux$98648. + dead port 1/2 on $mux $procmux$98651. + dead port 1/2 on $mux $procmux$98654. + dead port 2/2 on $mux $procmux$98657. + dead port 1/2 on $mux $procmux$98664. + dead port 2/2 on $mux $procmux$98666. + dead port 1/2 on $mux $procmux$98669. + dead port 1/2 on $mux $procmux$98672. + dead port 1/2 on $mux $procmux$98675. + dead port 1/2 on $mux $procmux$98678. + dead port 1/2 on $mux $procmux$98681. + dead port 1/2 on $mux $procmux$98684. + dead port 1/2 on $mux $procmux$98687. + dead port 1/2 on $mux $procmux$98690. + dead port 1/2 on $mux $procmux$98693. + dead port 1/2 on $mux $procmux$98696. + dead port 1/2 on $mux $procmux$98699. + dead port 2/2 on $mux $procmux$98702. + dead port 1/2 on $mux $procmux$98754. + dead port 2/2 on $mux $procmux$98756. + dead port 1/2 on $mux $procmux$98759. + dead port 1/2 on $mux $procmux$98762. + dead port 1/2 on $mux $procmux$98765. + dead port 1/2 on $mux $procmux$98768. + dead port 1/2 on $mux $procmux$98771. + dead port 1/2 on $mux $procmux$98774. + dead port 1/2 on $mux $procmux$98777. + dead port 1/2 on $mux $procmux$98780. + dead port 1/2 on $mux $procmux$98783. + dead port 1/2 on $mux $procmux$98786. + dead port 1/2 on $mux $procmux$98789. + dead port 2/2 on $mux $procmux$98792. + dead port 1/2 on $mux $procmux$98799. + dead port 2/2 on $mux $procmux$98801. + dead port 1/2 on $mux $procmux$98804. + dead port 1/2 on $mux $procmux$98807. + dead port 1/2 on $mux $procmux$98810. + dead port 1/2 on $mux $procmux$98813. + dead port 1/2 on $mux $procmux$98816. + dead port 1/2 on $mux $procmux$98819. + dead port 1/2 on $mux $procmux$98822. + dead port 1/2 on $mux $procmux$98825. + dead port 1/2 on $mux $procmux$98828. + dead port 1/2 on $mux $procmux$98831. + dead port 1/2 on $mux $procmux$98834. + dead port 2/2 on $mux $procmux$98837. + dead port 1/2 on $mux $procmux$98844. + dead port 2/2 on $mux $procmux$98846. + dead port 1/2 on $mux $procmux$98849. + dead port 1/2 on $mux $procmux$98852. + dead port 1/2 on $mux $procmux$98855. + dead port 1/2 on $mux $procmux$98858. + dead port 1/2 on $mux $procmux$98861. + dead port 1/2 on $mux $procmux$98864. + dead port 1/2 on $mux $procmux$98867. + dead port 1/2 on $mux $procmux$98870. + dead port 1/2 on $mux $procmux$98873. + dead port 1/2 on $mux $procmux$98876. + dead port 1/2 on $mux $procmux$98879. + dead port 2/2 on $mux $procmux$98882. + dead port 1/2 on $mux $procmux$99024. + dead port 2/2 on $mux $procmux$99026. + dead port 1/2 on $mux $procmux$99029. + dead port 1/2 on $mux $procmux$99032. + dead port 1/2 on $mux $procmux$99035. + dead port 1/2 on $mux $procmux$99038. + dead port 1/2 on $mux $procmux$99041. + dead port 1/2 on $mux $procmux$99044. + dead port 1/2 on $mux $procmux$99047. + dead port 1/2 on $mux $procmux$99050. + dead port 1/2 on $mux $procmux$99053. + dead port 1/2 on $mux $procmux$99056. + dead port 1/2 on $mux $procmux$99059. + dead port 2/2 on $mux $procmux$99062. + dead port 1/2 on $mux $procmux$99069. + dead port 2/2 on $mux $procmux$99071. + dead port 1/2 on $mux $procmux$99074. + dead port 1/2 on $mux $procmux$99077. + dead port 1/2 on $mux $procmux$99080. + dead port 1/2 on $mux $procmux$99083. + dead port 1/2 on $mux $procmux$99086. + dead port 1/2 on $mux $procmux$99089. + dead port 1/2 on $mux $procmux$99092. + dead port 1/2 on $mux $procmux$99095. + dead port 1/2 on $mux $procmux$99098. + dead port 1/2 on $mux $procmux$99101. + dead port 1/2 on $mux $procmux$99104. + dead port 2/2 on $mux $procmux$99107. + dead port 1/2 on $mux $procmux$99114. + dead port 2/2 on $mux $procmux$99116. + dead port 1/2 on $mux $procmux$99119. + dead port 1/2 on $mux $procmux$99122. + dead port 1/2 on $mux $procmux$99125. + dead port 1/2 on $mux $procmux$99128. + dead port 1/2 on $mux $procmux$99131. + dead port 1/2 on $mux $procmux$99134. + dead port 1/2 on $mux $procmux$99137. + dead port 1/2 on $mux $procmux$99140. + dead port 1/2 on $mux $procmux$99143. + dead port 1/2 on $mux $procmux$99146. + dead port 1/2 on $mux $procmux$99149. + dead port 2/2 on $mux $procmux$99152. + dead port 1/2 on $mux $procmux$99204. + dead port 2/2 on $mux $procmux$99206. + dead port 1/2 on $mux $procmux$99209. + dead port 1/2 on $mux $procmux$99212. + dead port 1/2 on $mux $procmux$99215. + dead port 1/2 on $mux $procmux$99218. + dead port 1/2 on $mux $procmux$99221. + dead port 1/2 on $mux $procmux$99224. + dead port 1/2 on $mux $procmux$99227. + dead port 1/2 on $mux $procmux$99230. + dead port 1/2 on $mux $procmux$99233. + dead port 1/2 on $mux $procmux$99236. + dead port 1/2 on $mux $procmux$99239. + dead port 2/2 on $mux $procmux$99242. + dead port 1/2 on $mux $procmux$99249. + dead port 2/2 on $mux $procmux$99251. + dead port 1/2 on $mux $procmux$99254. + dead port 1/2 on $mux $procmux$99257. + dead port 1/2 on $mux $procmux$99260. + dead port 1/2 on $mux $procmux$99263. + dead port 1/2 on $mux $procmux$99266. + dead port 1/2 on $mux $procmux$99269. + dead port 1/2 on $mux $procmux$99272. + dead port 1/2 on $mux $procmux$99275. + dead port 1/2 on $mux $procmux$99278. + dead port 1/2 on $mux $procmux$99281. + dead port 1/2 on $mux $procmux$99284. + dead port 2/2 on $mux $procmux$99287. +Running muxtree optimizer on module \leanvm_b_stream_alu.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$147850. + dead port 2/2 on $mux $procmux$147862. + dead port 2/2 on $mux $procmux$147874. + dead port 2/2 on $mux $procmux$147886. +Running muxtree optimizer on module \lsc1_field_encoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$149397. + dead port 2/2 on $mux $procmux$149399. + dead port 1/2 on $mux $procmux$149402. + dead port 2/2 on $mux $procmux$149558. + dead port 1/2 on $mux $procmux$149561. + dead port 1/2 on $mux $procmux$149689. + dead port 2/2 on $mux $procmux$149853. + dead port 2/2 on $mux $procmux$149855. + dead port 2/2 on $mux $procmux$149857. + dead port 1/2 on $mux $procmux$149860. +Running muxtree optimizer on module \lsc1_packet_tx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$149141. + dead port 1/2 on $mux $procmux$149144. + dead port 1/2 on $mux $procmux$149147. + dead port 1/2 on $mux $procmux$149150. + dead port 1/2 on $mux $procmux$149153. + dead port 1/2 on $mux $procmux$149156. + dead port 1/2 on $mux $procmux$149162. + dead port 1/2 on $mux $procmux$149165. + dead port 1/2 on $mux $procmux$149168. + dead port 1/2 on $mux $procmux$149171. + dead port 1/2 on $mux $procmux$149174. + dead port 1/2 on $mux $procmux$149180. + dead port 1/2 on $mux $procmux$149183. + dead port 1/2 on $mux $procmux$149186. + dead port 1/2 on $mux $procmux$149189. + dead port 1/2 on $mux $procmux$149195. + dead port 1/2 on $mux $procmux$149198. + dead port 1/2 on $mux $procmux$149201. + dead port 1/2 on $mux $procmux$149207. + dead port 1/2 on $mux $procmux$149210. + dead port 1/2 on $mux $procmux$149216. +Running muxtree optimizer on module \lsc1_stream_adapter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$147126. + dead port 1/2 on $mux $procmux$147129. + dead port 2/2 on $mux $procmux$147132. + dead port 2/2 on $mux $procmux$147175. + dead port 1/2 on $mux $procmux$147178. + dead port 2/2 on $mux $procmux$147181. + dead port 2/2 on $mux $procmux$147230. + dead port 1/2 on $mux $procmux$147233. + dead port 2/2 on $mux $procmux$147236. + dead port 1/2 on $mux $procmux$147244. + dead port 2/2 on $mux $procmux$147247. + dead port 2/2 on $mux $procmux$147310. + dead port 1/3 on $pmux $procmux$147564. + dead port 2/3 on $pmux $procmux$147564. + dead port 2/2 on $mux $procmux$147567. + dead port 1/2 on $mux $procmux$147570. + dead port 1/2 on $mux $procmux$147573. + dead port 2/2 on $mux $procmux$147580. + dead port 2/2 on $mux $procmux$147582. + dead port 1/2 on $mux $procmux$147585. + dead port 1/2 on $mux $procmux$147588. + dead port 2/2 on $mux $procmux$147595. + dead port 1/2 on $mux $procmux$147598. + dead port 1/2 on $mux $procmux$147601. + dead port 1/2 on $mux $procmux$147607. + dead port 1/2 on $mux $procmux$147610. + dead port 1/2 on $mux $procmux$147616. + dead port 1/2 on $mux $procmux$147619. + dead port 1/2 on $mux $procmux$147625. + dead port 1/2 on $mux $procmux$147631. +Removed 17163 multiplexer ports. + + +12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gate. + New input vector for $reduce_or cell $reduce_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3680$3687: { \_1114_ \_1106_ \_1103_ } + New input vector for $reduce_or cell $reduce_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3634$3641: { \_0938_ \_0924_ \_0915_ } + Optimizing cells in module \gate. + Optimizing cells in module \gf128_mul_bitstream. + Optimizing cells in module \gf2n_mul_bitstream. + Optimizing cells in module \gold. + Optimizing cells in module \gold. + Optimizing cells in module \leanvm_b_stream_alu. + New ctrl vector for $pmux cell $procmux$147743: { $eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$588_Y $auto$opt_reduce.cc:134:opt_pmux$150656 } + New ctrl vector for $pmux cell $procmux$147755: { $auto$opt_reduce.cc:134:opt_pmux$150658 $eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$590_Y } + New ctrl vector for $pmux cell $procmux$147845: { $auto$opt_reduce.cc:134:opt_pmux$150660 $procmux$147847_CMP $eq$asic_core/rtl/leanvm_b_stream_alu.sv:211$608_Y } + New ctrl vector for $pmux cell $procmux$147893: { $auto$opt_reduce.cc:134:opt_pmux$150664 $eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $auto$opt_reduce.cc:134:opt_pmux$150662 } + New ctrl vector for $pmux cell $procmux$147937: { $auto$opt_reduce.cc:134:opt_pmux$150668 $eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $auto$opt_reduce.cc:134:opt_pmux$150666 } + Optimizing cells in module \leanvm_b_stream_alu. + Optimizing cells in module \lsc1_field_encoder. + Optimizing cells in module \lsc1_packet_rx. + New ctrl vector for $pmux cell $procmux$149992: { $auto$opt_reduce.cc:134:opt_pmux$150670 $procmux$149445_CMP } + Optimizing cells in module \lsc1_packet_rx. + Optimizing cells in module \lsc1_packet_tx. + Optimizing cells in module \lsc1_stream_adapter. +Performed a total of 10 changes. + +12.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gate'. + +Finding identical cells in module `\gf128_mul_bitstream'. +Finding identical cells in module `\gf2n_mul_bitstream'. +Finding identical cells in module `\gold'. + +Finding identical cells in module `\leanvm_b_stream_alu'. + +Finding identical cells in module `\lsc1_field_encoder'. +Finding identical cells in module `\lsc1_packet_rx'. + +Finding identical cells in module `\lsc1_packet_tx'. + +Finding identical cells in module `\lsc1_stream_adapter'. + +Removed a total of 134 cells. + +12.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$150272 ($dff) from module gate (D = $procmux$7257_Y, Q = \field_encoder.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150671 ($sdff) from module gate (D = 1'1, Q = \field_encoder.fault). +Adding SRST signal on $procdff$150271 ($dff) from module gate (D = \_1338_, Q = \receiver.frame_valid, rval = 1'0). +Adding SRST signal on $procdff$150270 ($dff) from module gate (D = $procmux$7249_Y, Q = \receiver.frame_opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150674 ($sdff) from module gate (D = \receiver.opcode, Q = \receiver.frame_opcode). +Adding SRST signal on $procdff$150269 ($dff) from module gate (D = $procmux$7244_Y, Q = \receiver.frame_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150676 ($sdff) from module gate (D = \receiver.declared_length, Q = \receiver.frame_length). +Adding SRST signal on $procdff$150268 ($dff) from module gate (D = \_1330_, Q = \receiver.fault_valid, rval = 1'0). +Adding SRST signal on $procdff$150267 ($dff) from module gate (D = $procmux$7236_Y, Q = \receiver.fault_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150679 ($sdff) from module gate (D = \_3754_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5066$3214.$result, Q = \receiver.fault_status). +Adding SRST signal on $procdff$150266 ($dff) from module gate (D = \_1310_, Q = \receiver.state, rval = 3'000). +Adding SRST signal on $procdff$150265 ($dff) from module gate (D = $procmux$7228_Y, Q = \receiver.header_index, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$150682 ($sdff) from module gate (D = \_3734_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5003$3211.$result, Q = \receiver.header_index). +Adding SRST signal on $procdff$150264 ($dff) from module gate (D = $procmux$7223_Y, Q = \receiver.body_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150684 ($sdff) from module gate (D = \_3732_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4988$3210.$result, Q = \receiver.body_index). +Adding SRST signal on $procdff$150263 ($dff) from module gate (D = $procmux$7218_Y, Q = \receiver.declared_length [7:0], rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150686 ($sdff) from module gate (D = \rx_data, Q = \receiver.declared_length [7:0]). +Adding SRST signal on $procdff$150262 ($dff) from module gate (D = $procmux$7213_Y, Q = \receiver.declared_length [15:8], rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150688 ($sdff) from module gate (D = \rx_data, Q = \receiver.declared_length [15:8]). +Adding SRST signal on $procdff$150261 ($dff) from module gate (D = $procmux$7208_Y, Q = \receiver.version, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150690 ($sdff) from module gate (D = \rx_data, Q = \receiver.version). +Adding SRST signal on $procdff$150260 ($dff) from module gate (D = $procmux$7203_Y, Q = \receiver.opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150692 ($sdff) from module gate (D = \rx_data, Q = \receiver.opcode). +Adding SRST signal on $procdff$150259 ($dff) from module gate (D = $procmux$7198_Y, Q = \receiver.flags, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150694 ($sdff) from module gate (D = \rx_data, Q = \receiver.flags). +Adding SRST signal on $procdff$150258 ($dff) from module gate (D = $procmux$7193_Y, Q = \receiver.crc, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$150696 ($sdff) from module gate (D = \_3730_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4971$3209.$result, Q = \receiver.crc). +Adding SRST signal on $procdff$150257 ($dff) from module gate (D = $procmux$7188_Y, Q = \_2758_, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150698 ($sdff) from module gate (D = \_3725_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4938$3207.$result, Q = \_2758_). +Adding SRST signal on $procdff$150256 ($dff) from module gate (D = $procmux$7183_Y, Q = \_2759_, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150700 ($sdff) from module gate (D = \_3721_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4921$3206.$result, Q = \_2759_). +Adding SRST signal on $procdff$150255 ($dff) from module gate (D = $procmux$7178_Y, Q = \_2760_, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150702 ($sdff) from module gate (D = \_3717_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4904$3205.$result, Q = \_2760_). +Adding SRST signal on $procdff$150254 ($dff) from module gate (D = $procmux$7173_Y, Q = \field_encoder.operand_b [127:1], rval = 127'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150704 ($sdff) from module gate (D = \_1089_ [127:1], Q = \field_encoder.operand_b [127:1]). +Adding SRST signal on $procdff$150253 ($dff) from module gate (D = $procmux$7168_Y, Q = \field_encoder.operand_b [0], rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150706 ($sdff) from module gate (D = \_1081_ [0], Q = \field_encoder.operand_b [0]). +Adding SRST signal on $procdff$150252 ($dff) from module gate (D = $procmux$7163_Y, Q = \field_encoder.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150708 ($sdff) from module gate (D = \_1089_, Q = \field_encoder.result). +Adding SRST signal on $procdff$150251 ($dff) from module gate (D = $procmux$7158_Y, Q = \adapter.datapath.scratch_byte [0], rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150710 ($sdff) from module gate (D = \_3418_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4100$3175.$result, Q = \adapter.datapath.scratch_byte [0]). +Adding SRST signal on $procdff$150250 ($dff) from module gate (D = $procmux$7153_Y, Q = \adapter.datapath.scratch_byte [7:1], rval = 7'0000000). +Adding EN signal on $auto$ff.cc:266:slice$150712 ($sdff) from module gate (D = \_3412_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4075$3174.$result, Q = \adapter.datapath.scratch_byte [7:1]). +Adding SRST signal on $procdff$150249 ($dff) from module gate (D = $procmux$7148_Y, Q = \adapter.datapath.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150714 ($sdff) from module gate (D = \_1031_, Q = \adapter.datapath.fault). +Adding SRST signal on $procdff$150248 ($dff) from module gate (D = \_1071_, Q = \field_encoder.multiply_start, rval = 1'0). +Adding SRST signal on $procdff$150247 ($dff) from module gate (D = $procmux$7140_Y, Q = \field_encoder.bit_index [4], rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150717 ($sdff) from module gate (D = \_1087_ [4], Q = \field_encoder.bit_index [4]). +Adding SRST signal on $procdff$150246 ($dff) from module gate (D = $procmux$7135_Y, Q = \field_encoder.bit_index [3:0], rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150719 ($sdff) from module gate (D = \_1077_ [3:0], Q = \field_encoder.bit_index [3:0]). +Adding SRST signal on $procdff$150245 ($dff) from module gate (D = $procmux$7130_Y, Q = \field_encoder.multiplier.result_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:266:slice$150721 ($sdff) from module gate (D = \_3542_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4455$3189.$result, Q = \field_encoder.multiplier.result_index). +Adding SRST signal on $procdff$150244 ($dff) from module gate (D = $procmux$7125_Y, Q = \field_encoder.multiplier.payload_index, rval = 6'000000). +Adding EN signal on $auto$ff.cc:266:slice$150723 ($sdff) from module gate (D = \_3550_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4478$3190.$result, Q = \field_encoder.multiplier.payload_index). +Adding SRST signal on $procdff$150243 ($dff) from module gate (D = $procmux$7120_Y, Q = \field_encoder.multiplier.saved_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150725 ($sdff) from module gate (D = \field_encoder.operand_b, Q = \field_encoder.multiplier.saved_b). +Adding SRST signal on $procdff$150242 ($dff) from module gate (D = \_1137_, Q = \field_encoder.multiplier.fault, rval = 1'0). +Adding SRST signal on $procdff$150241 ($dff) from module gate (D = \_3536_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4434$3188.$result, Q = \field_encoder.multiplier.done_pulse, rval = 1'0). +Adding SRST signal on $procdff$150240 ($dff) from module gate (D = $procmux$7109_Y, Q = \field_encoder.multiplier.state, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$150729 ($sdff) from module gate (D = \_3559_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4506$3191.$result, Q = \field_encoder.multiplier.state). +Adding SRST signal on $procdff$150239 ($dff) from module gate (D = $procmux$7104_Y, Q = \field_encoder.saved_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150731 ($sdff) from module gate (D = \encoder_index, Q = \field_encoder.saved_index). +Adding SRST signal on $procdff$150238 ($dff) from module gate (D = $procmux$7099_Y, Q = \field_encoder.multiplier.datapath.multiplier.impl.a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150733 ($sdff) from module gate (D = \_1229_, Q = \field_encoder.multiplier.datapath.multiplier.impl.a_shift). +Adding SRST signal on $procdff$150237 ($dff) from module gate (D = $procmux$7094_Y, Q = \field_encoder.multiplier.datapath.multiplier.impl.accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150735 ($sdff) from module gate (D = \_1226_, Q = \field_encoder.multiplier.datapath.multiplier.impl.accumulator). +Adding SRST signal on $procdff$150236 ($dff) from module gate (D = $procmux$7089_Y, Q = \field_encoder.multiplier.datapath.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150737 ($sdff) from module gate (D = \_1201_, Q = \field_encoder.multiplier.datapath.fault). +Adding SRST signal on $procdff$150235 ($dff) from module gate (D = $procmux$7084_Y, Q = \field_encoder.multiplier.datapath.scratch_byte [0], rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150739 ($sdff) from module gate (D = \_3592_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4577$3193.$result, Q = \field_encoder.multiplier.datapath.scratch_byte [0]). +Adding SRST signal on $procdff$150234 ($dff) from module gate (D = $procmux$7079_Y, Q = \field_encoder.multiplier.datapath.scratch_byte [7:1], rval = 7'0000000). +Adding EN signal on $auto$ff.cc:266:slice$150741 ($sdff) from module gate (D = \_3588_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4554$3192.$result, Q = \field_encoder.multiplier.datapath.scratch_byte [7:1]). +Adding SRST signal on $procdff$150233 ($dff) from module gate (D = $procmux$7074_Y, Q = \_2782_, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150743 ($sdff) from module gate (D = { \_1874_ [6:5] \_1874_ [3:2] }, Q = \_2782_). +Adding SRST signal on $procdff$150232 ($dff) from module gate (D = $procmux$7069_Y, Q = \_2783_, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150745 ($sdff) from module gate (D = { \_1875_ [7] \_1875_ [4] \_1875_ [1:0] }, Q = \_2783_). +Adding SRST signal on $procdff$150231 ($dff) from module gate (D = $procmux$7064_Y, Q = \_2784_, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150747 ($sdff) from module gate (D = { \_1923_ [6:5] \_1923_ [3:2] }, Q = \_2784_). +Adding SRST signal on $procdff$150230 ($dff) from module gate (D = $procmux$7059_Y, Q = \_2785_, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150749 ($sdff) from module gate (D = { \_1924_ [7] \_1924_ [4] \_1924_ [1:0] }, Q = \_2785_). +Adding SRST signal on $procdff$150229 ($dff) from module gate (D = $procmux$7054_Y, Q = \active_profile, rval = 8'00000001). +Adding EN signal on $auto$ff.cc:266:slice$150751 ($sdff) from module gate (D = \receiver.frame_payload [23:16], Q = \active_profile). +Adding SRST signal on $procdff$150228 ($dff) from module gate (D = $procmux$7049_Y, Q = \retire_seq, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$150753 ($sdff) from module gate (D = \_0454_, Q = \retire_seq). +Adding SRST signal on $procdff$150227 ($dff) from module gate (D = $procmux$7044_Y, Q = \committed_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$150755 ($sdff) from module gate (D = \staged_next_fp, Q = \committed_fp). +Adding SRST signal on $procdff$150226 ($dff) from module gate (D = $procmux$7039_Y, Q = \committed_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$150757 ($sdff) from module gate (D = \staged_next_pc, Q = \committed_pc). +Adding SRST signal on $procdff$150225 ($dff) from module gate (D = $procmux$7034_Y, Q = \state_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150759 ($sdff) from module gate (D = 1'1, Q = \state_valid). +Adding SRST signal on $procdff$150224 ($dff) from module gate (D = $procmux$7029_Y, Q = \staged_result_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$150761 ($sdff) from module gate (D = \_1963_, Q = \staged_result_crc). +Adding SRST signal on $procdff$150223 ($dff) from module gate (D = $procmux$7024_Y, Q = \staged_next_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$150763 ($sdff) from module gate (D = \_1999_, Q = \staged_next_fp). +Adding SRST signal on $procdff$150222 ($dff) from module gate (D = $procmux$7019_Y, Q = \staged_next_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$150765 ($sdff) from module gate (D = \_2035_, Q = \staged_next_pc). +Adding SRST signal on $procdff$150221 ($dff) from module gate (D = $procmux$7014_Y, Q = \staged_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$150767 ($sdff) from module gate (D = \_2073_, Q = \staged_txn_id). +Adding SRST signal on $procdff$150220 ($dff) from module gate (D = $procmux$7009_Y, Q = \result_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150769 ($sdff) from module gate (D = \_2112_, Q = \result_pending). +Adding SRST signal on $procdff$150219 ($dff) from module gate (D = $procmux$7004_Y, Q = \encoder_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150771 ($sdff) from module gate (D = \_2148_, Q = \encoder_index). +Adding SRST signal on $procdff$150218 ($dff) from module gate (D = \_1766_, Q = \encoder_start, rval = 1'0). +Adding SRST signal on $procdff$150217 ($dff) from module gate (D = $procmux$6996_Y, Q = \alu_operand_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150774 ($sdff) from module gate (D = \_2187_, Q = \alu_operand_b). +Adding SRST signal on $procdff$150216 ($dff) from module gate (D = $procmux$6991_Y, Q = \alu_operand_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150776 ($sdff) from module gate (D = \_2226_, Q = \alu_operand_a). +Adding SRST signal on $procdff$150215 ($dff) from module gate (D = $procmux$6986_Y, Q = \alu_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150778 ($sdff) from module gate (D = \_2265_, Q = \alu_operation). +Adding SRST signal on $procdff$150214 ($dff) from module gate (D = \_1793_, Q = \alu_start, rval = 1'0). +Adding SRST signal on $procdff$150213 ($dff) from module gate (D = $procmux$6978_Y, Q = \compute_state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150781 ($sdff) from module gate (D = \_2319_, Q = \compute_state). +Adding SRST signal on $procdff$150212 ($dff) from module gate (D = \_2358_, Q = \capture_result_crc, rval = 1'0). +Adding SRST signal on $procdff$150211 ($dff) from module gate (D = $procmux$6970_Y, Q = \tx_payload, rval = 544'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150784 ($sdff) from module gate (D = \_2409_, Q = \tx_payload). +Adding SRST signal on $procdff$150210 ($dff) from module gate (D = $procmux$6965_Y, Q = \tx_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150786 ($sdff) from module gate (D = \_2459_, Q = \tx_length). +Adding SRST signal on $procdff$150209 ($dff) from module gate (D = $procmux$6960_Y, Q = \tx_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150788 ($sdff) from module gate (D = \_2468_, Q = \tx_status). +Adding SRST signal on $procdff$150208 ($dff) from module gate (D = \_1824_, Q = \tx_start, rval = 1'0). +Adding SRST signal on $procdff$150207 ($dff) from module gate (D = $procmux$6952_Y, Q = \fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150791 ($sdff) from module gate (D = \_2519_, Q = \fault). +Adding SRST signal on $procdff$150206 ($dff) from module gate (D = \_1734_, Q = \done_pulse, rval = 1'0). +Adding SRST signal on $procdff$150205 ($dff) from module gate (D = $procmux$6944_Y, Q = \adapter.state, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$150794 ($sdff) from module gate (D = \_3363_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3992$3172.$result, Q = \adapter.state). +Adding SRST signal on $procdff$150204 ($dff) from module gate (D = \_3338_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3918$3169.$result, Q = \adapter.done_pulse, rval = 1'0). +Adding SRST signal on $procdff$150203 ($dff) from module gate (D = \_0963_, Q = \adapter.fault, rval = 1'0). +Adding SRST signal on $procdff$150202 ($dff) from module gate (D = $procmux$6933_Y, Q = \adapter.saved_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150798 ($sdff) from module gate (D = \alu_operation, Q = \adapter.saved_operation). +Adding SRST signal on $procdff$150201 ($dff) from module gate (D = $procmux$6928_Y, Q = \adapter.saved_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150800 ($sdff) from module gate (D = \alu_operand_a, Q = \adapter.saved_a). +Adding SRST signal on $procdff$150200 ($dff) from module gate (D = $procmux$6923_Y, Q = \adapter.saved_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150802 ($sdff) from module gate (D = \alu_operand_b, Q = \adapter.saved_b). +Adding SRST signal on $procdff$150199 ($dff) from module gate (D = $procmux$6918_Y, Q = \adapter.payload_index, rval = 6'000000). +Adding EN signal on $auto$ff.cc:266:slice$150804 ($sdff) from module gate (D = \_3354_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3964$3171.$result, Q = \adapter.payload_index). +Adding SRST signal on $procdff$150198 ($dff) from module gate (D = $procmux$6913_Y, Q = \adapter.result_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:266:slice$150806 ($sdff) from module gate (D = \_3346_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3941$3170.$result, Q = \adapter.result_index). +Adding SRST signal on $procdff$150197 ($dff) from module gate (D = $procmux$6908_Y, Q = \adapter.datapath.multiplier.impl.accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150808 ($sdff) from module gate (D = \_1056_, Q = \adapter.datapath.multiplier.impl.accumulator). +Adding SRST signal on $procdff$150196 ($dff) from module gate (D = $procmux$6903_Y, Q = \adapter.datapath.multiplier.impl.a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150810 ($sdff) from module gate (D = \_1059_, Q = \adapter.datapath.multiplier.impl.a_shift). +Adding SRST signal on $procdff$150195 ($dff) from module gate (D = $procmux$6898_Y, Q = \field_encoder.busy, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150812 ($sdff) from module gate (D = \_1085_, Q = \field_encoder.busy). +Adding SRST signal on $procdff$150194 ($dff) from module gate (D = \_1073_, Q = \field_encoder.done_pulse, rval = 1'0). +Adding SRST signal on $procdff$150193 ($dff) from module gate (D = \_1417_, Q = \transmitter.done_pulse, rval = 1'0). +Adding SRST signal on $procdff$150192 ($dff) from module gate (D = $procmux$6887_Y, Q = \transmitter.payload_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$150816 ($sdff) from module gate (D = \_1459_, Q = \transmitter.payload_crc). +Adding SRST signal on $procdff$150191 ($dff) from module gate (D = $procmux$6882_Y, Q = \transmitter.active, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150818 ($sdff) from module gate (D = \_1420_, Q = \transmitter.active). +Adding SRST signal on $procdff$150190 ($dff) from module gate (D = $procmux$6877_Y, Q = \transmitter.index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150820 ($sdff) from module gate (D = \_1381_, Q = \transmitter.index). +Adding SRST signal on $procdff$150189 ($dff) from module gate (D = $procmux$6872_Y, Q = \transmitter.saved_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150822 ($sdff) from module gate (D = \tx_length, Q = \transmitter.saved_length). +Adding SRST signal on $procdff$150188 ($dff) from module gate (D = $procmux$6867_Y, Q = \transmitter.saved_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$150824 ($sdff) from module gate (D = \tx_status, Q = \transmitter.saved_status). +Adding SRST signal on $procdff$150187 ($dff) from module gate (D = $procmux$6862_Y, Q = \transmitter.saved_payload, rval = 544'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150826 ($sdff) from module gate (D = \tx_payload, Q = \transmitter.saved_payload). +Adding SRST signal on $procdff$150186 ($dff) from module gate (D = $procmux$6857_Y, Q = \transmitter.saved_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$150828 ($sdff) from module gate (D = \_1415_, Q = \transmitter.saved_crc). +Adding SRST signal on $procdff$150185 ($dff) from module gate (D = $procmux$6852_Y, Q = \transmitter.envelope_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$150830 ($sdff) from module gate (D = \_1450_, Q = \transmitter.envelope_crc_work). +Adding SRST signal on $procdff$150184 ($dff) from module gate (D = $procmux$6847_Y, Q = \transmitter.payload_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$150832 ($sdff) from module gate (D = \_1458_, Q = \transmitter.payload_crc_work). +Adding SRST signal on $procdff$150183 ($dff) from module gate (D = $procmux$6842_Y, Q = \field_encoder.multiplier.saved_operation_reg[1], rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$150834 ($sdff) from module gate (D = 1'1, Q = \field_encoder.multiplier.saved_operation_reg[1]). +Adding SRST signal on $procdff$150182 ($dff) from module gate (D = $procmux$6837_Y, Q = \receiver.frame_payload, rval = 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150836 ($sdff) from module gate (D = \_3727_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4953$3208.$result, Q = \receiver.frame_payload). +Adding SRST signal on $procdff$150181 ($dff) from module gate (D = $procmux$6832_Y, Q = \adapter.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150838 ($sdff) from module gate (D = \_3335_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3900$3168.$result, Q = \adapter.result). +Adding EN signal on $procdff$150180 ($dff) from module gate (D = \_0328_, Q = \n_writes). +Adding EN signal on $procdff$150179 ($dff) from module gate (D = \_0327_, Q = \n_deferred). +Adding EN signal on $procdff$150178 ($dff) from module gate (D = \_0068_, Q = \txn_id). +Adding EN signal on $procdff$150177 ($dff) from module gate (D = \receiver.frame_payload [63:32], Q = \pc). +Adding EN signal on $procdff$150176 ($dff) from module gate (D = \receiver.frame_payload [95:64], Q = \fp). +Adding EN signal on $procdff$150175 ($dff) from module gate (D = \_0163_, Q = \addr_a). +Adding EN signal on $procdff$150174 ($dff) from module gate (D = \_0164_, Q = \addr_b). +Adding EN signal on $procdff$150173 ($dff) from module gate (D = \_0165_, Q = \addr_c). +Adding EN signal on $procdff$150172 ($dff) from module gate (D = \receiver.frame_payload [655:624], Q = \proposed_pc). +Adding EN signal on $procdff$150171 ($dff) from module gate (D = \receiver.frame_payload [687:656], Q = \proposed_fp). +Adding EN signal on $procdff$150170 ($dff) from module gate (D = \_0422_, Q = \next_pc_value). +Adding EN signal on $procdff$150169 ($dff) from module gate (D = \_0421_, Q = \next_fp_value). +Adding EN signal on $procdff$150168 ($dff) from module gate (D = \_0326_, Q = \deferred_target). +Adding EN signal on $procdff$150167 ($dff) from module gate (D = \_0325_, Q = \deferred_local). +Adding EN signal on $procdff$150166 ($dff) from module gate (D = \receiver.frame_payload [103:96], Q = \profile). +Adding EN signal on $procdff$150165 ($dff) from module gate (D = \_0174_, Q = \pres_a). +Adding EN signal on $procdff$150164 ($dff) from module gate (D = \_0192_, Q = \pres_b). +Adding EN signal on $procdff$150163 ($dff) from module gate (D = \_0193_, Q = \pres_c). +Adding EN signal on $procdff$150162 ($dff) from module gate (D = \_0178_, Q = \val_a). +Adding EN signal on $procdff$150161 ($dff) from module gate (D = \_0197_, Q = \val_b). +Adding EN signal on $procdff$150160 ($dff) from module gate (D = \_0198_, Q = \val_c). +Adding EN signal on $procdff$150159 ($dff) from module gate (D = \_0208_, Q = \inv_value). +Adding EN signal on $procdff$150158 ($dff) from module gate (D = \_0175_, Q = \result_value). +Adding EN signal on $procdff$150157 ($dff) from module gate (D = \_0449_, Q = \solved_a). +Adding EN signal on $procdff$150156 ($dff) from module gate (D = \_0450_, Q = \solved_b). +Adding EN signal on $procdff$150155 ($dff) from module gate (D = \_0329_, Q = \write_address). +Adding EN signal on $procdff$150154 ($dff) from module gate (D = \_0330_, Q = \write_value). +Adding SRST signal on $procdff$150153 ($dff) from module gate (D = $procmux$6773_Y, Q = \field_encoder.multiplier.datapath.byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150867 ($sdff) from module gate (D = \_3599_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4605$3194.$result, Q = \field_encoder.multiplier.datapath.byte_index). +Adding SRST signal on $procdff$150152 ($dff) from module gate (D = $procmux$6768_Y, Q = \field_encoder.multiplier.datapath.state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150869 ($sdff) from module gate (D = \_3611_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4672$3197.$result, Q = \field_encoder.multiplier.datapath.state). +Adding SRST signal on $procdff$150151 ($dff) from module gate (D = $procmux$6763_Y, Q = \field_encoder.multiplier.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150871 ($sdff) from module gate (D = \_3533_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4418$3187.$result, Q = \field_encoder.multiplier.result). +Adding SRST signal on $procdff$150150 ($dff) from module gate (D = $procmux$6758_Y, Q = \adapter.datapath.state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150873 ($sdff) from module gate (D = \_3444_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4202$3179.$result, Q = \adapter.datapath.state). +Adding SRST signal on $procdff$150149 ($dff) from module gate (D = $procmux$6753_Y, Q = \adapter.datapath.byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150875 ($sdff) from module gate (D = \_3425_$func$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4128$3176.$result, Q = \adapter.datapath.byte_index). +Adding SRST signal on $procdff$150470 ($dff) from module gf2n_mul_bitstream (D = $procmux$148176_Y, Q = \accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150877 ($sdff) from module gf2n_mul_bitstream (D = $procmux$148176_Y, Q = \accumulator). +Adding SRST signal on $procdff$150469 ($dff) from module gf2n_mul_bitstream (D = $procmux$148191_Y, Q = \a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$150889 ($sdff) from module gf2n_mul_bitstream (D = $procmux$148191_Y, Q = \a_shift). +Adding EN signal on $procdff$150334 ($dff) from module gold (D = $2\write_value[127:0], Q = \write_value). +Adding EN signal on $procdff$150333 ($dff) from module gold (D = $2\write_address[31:0], Q = \write_address). +Adding EN signal on $procdff$150330 ($dff) from module gold (D = $2\solved_b[127:0], Q = \solved_b). +Adding EN signal on $procdff$150329 ($dff) from module gold (D = $2\solved_a[127:0], Q = \solved_a). +Adding EN signal on $procdff$150328 ($dff) from module gold (D = $2\result_value[127:0], Q = \result_value). +Adding EN signal on $procdff$150327 ($dff) from module gold (D = $2\inv_value[127:0], Q = \inv_value). +Adding EN signal on $procdff$150326 ($dff) from module gold (D = $2\val_c[127:0], Q = \val_c). +Adding EN signal on $procdff$150325 ($dff) from module gold (D = $2\val_b[127:0], Q = \val_b). +Adding EN signal on $procdff$150324 ($dff) from module gold (D = $2\val_a[127:0], Q = \val_a). +Adding EN signal on $procdff$150321 ($dff) from module gold (D = $2\pres_c[7:0], Q = \pres_c). +Adding EN signal on $procdff$150320 ($dff) from module gold (D = $2\pres_b[7:0], Q = \pres_b). +Adding EN signal on $procdff$150319 ($dff) from module gold (D = $2\pres_a[7:0], Q = \pres_a). +Adding EN signal on $procdff$150318 ($dff) from module gold (D = $2\profile[7:0], Q = \profile). +Adding EN signal on $procdff$150317 ($dff) from module gold (D = $2\deferred_local[31:0], Q = \deferred_local). +Adding EN signal on $procdff$150316 ($dff) from module gold (D = $2\deferred_target[31:0], Q = \deferred_target). +Adding EN signal on $procdff$150315 ($dff) from module gold (D = $2\next_fp_value[31:0], Q = \next_fp_value). +Adding EN signal on $procdff$150314 ($dff) from module gold (D = $2\next_pc_value[31:0], Q = \next_pc_value). +Adding EN signal on $procdff$150313 ($dff) from module gold (D = $2\proposed_fp[31:0], Q = \proposed_fp). +Adding EN signal on $procdff$150312 ($dff) from module gold (D = $2\proposed_pc[31:0], Q = \proposed_pc). +Adding EN signal on $procdff$150310 ($dff) from module gold (D = $2\addr_c[31:0], Q = \addr_c). +Adding EN signal on $procdff$150309 ($dff) from module gold (D = $2\addr_b[31:0], Q = \addr_b). +Adding EN signal on $procdff$150308 ($dff) from module gold (D = $2\addr_a[31:0], Q = \addr_a). +Adding EN signal on $procdff$150304 ($dff) from module gold (D = $2\fp[31:0], Q = \fp). +Adding EN signal on $procdff$150303 ($dff) from module gold (D = $2\pc[31:0], Q = \pc). +Adding EN signal on $procdff$150302 ($dff) from module gold (D = $2\txn_id[31:0], Q = \txn_id). +Adding EN signal on $procdff$150300 ($dff) from module gold (D = $2\n_deferred[31:0], Q = \n_deferred). +Adding EN signal on $procdff$150299 ($dff) from module gold (D = $2\n_writes[31:0], Q = \n_writes). +Adding SRST signal on $procdff$150298 ($dff) from module gold (D = { $procmux$144385_Y [7] $procmux$144385_Y [4] $procmux$144385_Y [1:0] }, Q = { \last_fault [7] \last_fault [4] \last_fault [1:0] }, rval = 4'0000). +Adding SRST signal on $procdff$150298 ($dff) from module gold (D = { $procmux$144382_Y [6:5] $procmux$144382_Y [3:2] }, Q = { \last_fault [6:5] \last_fault [3:2] }, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$150929 ($sdff) from module gold (D = { $procmux$144382_Y [6:5] $procmux$144382_Y [3:2] }, Q = { \last_fault [6:5] \last_fault [3:2] }). +Adding EN signal on $auto$ff.cc:266:slice$150928 ($sdff) from module gold (D = { $procmux$144385_Y [7] $procmux$144385_Y [4] $procmux$144385_Y [1:0] }, Q = { \last_fault [7] \last_fault [4] \last_fault [1:0] }). +Adding SRST signal on $procdff$150297 ($dff) from module gold (D = { $procmux$144544_Y [7] $procmux$144544_Y [4] $procmux$144544_Y [1:0] }, Q = { \last_status [7] \last_status [4] \last_status [1:0] }, rval = 4'0000). +Adding SRST signal on $procdff$150297 ($dff) from module gold (D = { $procmux$144541_Y [6:5] $procmux$144541_Y [3:2] }, Q = { \last_status [6:5] \last_status [3:2] }, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$151001 ($sdff) from module gold (D = { $procmux$144541_Y [6:5] $procmux$144541_Y [3:2] }, Q = { \last_status [6:5] \last_status [3:2] }). +Adding EN signal on $auto$ff.cc:266:slice$151000 ($sdff) from module gold (D = { $procmux$144544_Y [7] $procmux$144544_Y [4] $procmux$144544_Y [1:0] }, Q = { \last_status [7] \last_status [4] \last_status [1:0] }). +Adding SRST signal on $procdff$150296 ($dff) from module gold (D = $procmux$144607_Y, Q = \active_profile, rval = 8'00000001). +Adding EN signal on $auto$ff.cc:266:slice$151036 ($sdff) from module gold (D = \frame_payload [23:16], Q = \active_profile). +Adding SRST signal on $procdff$150295 ($dff) from module gold (D = $procmux$144667_Y, Q = \retire_seq, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$151074 ($sdff) from module gold (D = $add$asic_core/rtl/lsc1_packet_frontend.sv:484$2454_Y, Q = \retire_seq). +Adding SRST signal on $procdff$150294 ($dff) from module gold (D = $procmux$144727_Y, Q = \committed_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$151110 ($sdff) from module gold (D = \staged_next_fp, Q = \committed_fp). +Adding SRST signal on $procdff$150293 ($dff) from module gold (D = $procmux$144787_Y, Q = \committed_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$151146 ($sdff) from module gold (D = \staged_next_pc, Q = \committed_pc). +Adding SRST signal on $procdff$150292 ($dff) from module gold (D = $procmux$144847_Y, Q = \state_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$151182 ($sdff) from module gold (D = 1'1, Q = \state_valid). +Adding SRST signal on $procdff$150291 ($dff) from module gold (D = $procmux$144969_Y, Q = \staged_result_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$151218 ($sdff) from module gold (D = $procmux$144966_Y, Q = \staged_result_crc). +Adding SRST signal on $procdff$150290 ($dff) from module gold (D = $procmux$145089_Y, Q = \staged_next_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$151220 ($sdff) from module gold (D = $procmux$145086_Y, Q = \staged_next_fp). +Adding SRST signal on $procdff$150289 ($dff) from module gold (D = $procmux$145209_Y, Q = \staged_next_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$151292 ($sdff) from module gold (D = $procmux$145206_Y, Q = \staged_next_pc). +Adding SRST signal on $procdff$150288 ($dff) from module gold (D = $procmux$145329_Y, Q = \staged_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$151364 ($sdff) from module gold (D = $procmux$145326_Y, Q = \staged_txn_id). +Adding SRST signal on $procdff$150287 ($dff) from module gold (D = $procmux$145454_Y, Q = \result_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$151436 ($sdff) from module gold (D = $procmux$145454_Y, Q = \result_pending). +Adding SRST signal on $procdff$150286 ($dff) from module gold (D = $procmux$145571_Y, Q = \encoder_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$151504 ($sdff) from module gold (D = $procmux$145568_Y, Q = \encoder_index). +Adding SRST signal on $procdff$150285 ($dff) from module gold (D = $procmux$143531_Y, Q = \encoder_start, rval = 1'0). +Adding SRST signal on $procdff$150284 ($dff) from module gold (D = $procmux$145712_Y, Q = \alu_operand_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$151581 ($sdff) from module gold (D = $procmux$145691_Y, Q = \alu_operand_b). +Adding SRST signal on $procdff$150283 ($dff) from module gold (D = $procmux$145853_Y, Q = \alu_operand_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$151661 ($sdff) from module gold (D = $procmux$145832_Y, Q = \alu_operand_a). +Adding SRST signal on $procdff$150282 ($dff) from module gold (D = $procmux$145994_Y, Q = \alu_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$151741 ($sdff) from module gold (D = $procmux$145973_Y, Q = \alu_operation). +Adding SRST signal on $procdff$150281 ($dff) from module gold (D = $procmux$143654_Y, Q = \alu_start, rval = 1'0). +Adding SRST signal on $procdff$150280 ($dff) from module gold (D = $procmux$146165_Y, Q = \compute_state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$151826 ($sdff) from module gold (D = $procmux$146165_Y, Q = \compute_state). +Adding SRST signal on $procdff$150279 ($dff) from module gold (D = $procmux$146287_Y, Q = \capture_result_crc, rval = 1'0). +Adding SRST signal on $procdff$150278 ($dff) from module gold (D = $procmux$146449_Y, Q = \tx_payload, rval = 544'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$151903 ($sdff) from module gold (D = $procmux$146446_Y, Q = \tx_payload). +Adding SRST signal on $procdff$150277 ($dff) from module gold (D = $procmux$146608_Y, Q = \tx_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$151925 ($sdff) from module gold (D = $procmux$146605_Y, Q = \tx_length). +Adding SRST signal on $procdff$150276 ($dff) from module gold (D = $procmux$146767_Y, Q = \tx_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$151943 ($sdff) from module gold (D = $procmux$146764_Y, Q = \tx_status). +Adding SRST signal on $procdff$150275 ($dff) from module gold (D = $procmux$143812_Y, Q = \tx_start, rval = 1'0). +Adding SRST signal on $procdff$150274 ($dff) from module gold (D = $procmux$146926_Y, Q = \fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$151966 ($sdff) from module gold (D = $procmux$146926_Y, Q = \fault). +Adding SRST signal on $procdff$150273 ($dff) from module gold (D = $procmux$143368_Y, Q = \done_pulse, rval = 1'0). +Adding SRST signal on $procdff$150468 ($dff) from module leanvm_b_stream_alu (D = { $procmux$147646_Y $procmux$147668_Y }, Q = \scratch_byte, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$151993 ($sdff) from module leanvm_b_stream_alu (D = $procmux$147668_Y, Q = \scratch_byte [0]). +Adding EN signal on $auto$ff.cc:266:slice$151993 ($sdff) from module leanvm_b_stream_alu (D = $procmux$147646_Y, Q = \scratch_byte [7:1]). +Adding SRST signal on $procdff$150467 ($dff) from module leanvm_b_stream_alu (D = $procmux$147696_Y, Q = \byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$152024 ($sdff) from module leanvm_b_stream_alu (D = $procmux$147696_Y, Q = \byte_index). +Adding SRST signal on $procdff$150466 ($dff) from module leanvm_b_stream_alu (D = $procmux$147766_Y, Q = \fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$152046 ($sdff) from module leanvm_b_stream_alu (D = $procmux$147766_Y, Q = \fault). +Adding SRST signal on $procdff$150465 ($dff) from module leanvm_b_stream_alu (D = $procmux$147774_Y, Q = \state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$152056 ($sdff) from module leanvm_b_stream_alu (D = $procmux$147774_Y, Q = \state). +Adding SRST signal on $procdff$150445 ($dff) from module lsc1_field_encoder (D = $procmux$147016_Y, Q = \saved_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152084 ($sdff) from module lsc1_field_encoder (D = \index, Q = \saved_index). +Adding SRST signal on $procdff$150444 ($dff) from module lsc1_field_encoder (D = $procmux$147031_Y [3:0], Q = \bit_index [3:0], rval = 4'0000). +Adding SRST signal on $procdff$150444 ($dff) from module lsc1_field_encoder (D = $procmux$147028_Y [4], Q = \bit_index [4], rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$152087 ($sdff) from module lsc1_field_encoder (D = $sub$asic_core/rtl/lsc1_field_encoder.sv:76$774_Y [4], Q = \bit_index [4]). +Adding EN signal on $auto$ff.cc:266:slice$152086 ($sdff) from module lsc1_field_encoder (D = $procmux$147031_Y [3:0], Q = \bit_index [3:0]). +Adding SRST signal on $procdff$150443 ($dff) from module lsc1_field_encoder (D = $procmux$146986_Y, Q = \multiply_start, rval = 1'0). +Adding SRST signal on $procdff$150442 ($dff) from module lsc1_field_encoder (D = $procmux$147046_Y, Q = \result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152107 ($sdff) from module lsc1_field_encoder (D = $ternary$asic_core/rtl/lsc1_field_encoder.sv:63$772_Y, Q = \result). +Adding SRST signal on $procdff$150441 ($dff) from module lsc1_field_encoder (D = $procmux$147061_Y [0], Q = \operand_b [0], rval = 1'0). +Adding SRST signal on $procdff$150441 ($dff) from module lsc1_field_encoder (D = $procmux$147058_Y [127:1], Q = \operand_b [127:1], rval = 127'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152116 ($sdff) from module lsc1_field_encoder (D = $ternary$asic_core/rtl/lsc1_field_encoder.sv:63$772_Y [127:1], Q = \operand_b [127:1]). +Adding EN signal on $auto$ff.cc:266:slice$152115 ($sdff) from module lsc1_field_encoder (D = $procmux$147061_Y [0], Q = \operand_b [0]). +Adding SRST signal on $procdff$150440 ($dff) from module lsc1_field_encoder (D = $procmux$147076_Y [0], Q = \operand_a [0], rval = 1'0). +Adding SRST signal on $procdff$150440 ($dff) from module lsc1_field_encoder (D = $procmux$147073_Y [127:1], Q = \operand_a [127:1], rval = 127'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152136 ($sdff) from module lsc1_field_encoder (D = $ternary$asic_core/rtl/lsc1_field_encoder.sv:63$772_Y [127:1], Q = \operand_a [127:1]). +Adding EN signal on $auto$ff.cc:266:slice$152135 ($sdff) from module lsc1_field_encoder (D = $procmux$147076_Y [0], Q = \operand_a [0]). +Adding SRST signal on $procdff$150439 ($dff) from module lsc1_field_encoder (D = $procmux$147085_Y, Q = \fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$152155 ($sdff) from module lsc1_field_encoder (D = 1'1, Q = \fault). +Adding SRST signal on $procdff$150437 ($dff) from module lsc1_field_encoder (D = $procmux$146996_Y, Q = \done_pulse, rval = 1'0). +Adding SRST signal on $procdff$150436 ($dff) from module lsc1_field_encoder (D = $procmux$147117_Y, Q = \busy, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$152166 ($sdff) from module lsc1_field_encoder (D = $procmux$147117_Y, Q = \busy). +Adding SRST signal on $procdff$150521 ($dff) from module lsc1_packet_rx (D = $procmux$149874_Y, Q = \crc, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$152174 ($sdff) from module lsc1_packet_rx (D = $procmux$149867_Y, Q = \crc). +Adding SRST signal on $procdff$150519 ($dff) from module lsc1_packet_rx (D = $procmux$149905_Y, Q = \opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$152184 ($sdff) from module lsc1_packet_rx (D = \rx_data, Q = \opcode). +Adding SRST signal on $procdff$150517 ($dff) from module lsc1_packet_rx (D = { $procmux$149448_Y $procmux$149462_Y }, Q = \declared_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152188 ($sdff) from module lsc1_packet_rx (D = \rx_data, Q = \declared_length [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$152188 ($sdff) from module lsc1_packet_rx (D = \rx_data, Q = \declared_length [7:0]). +Adding SRST signal on $procdff$150522 ($dff) from module lsc1_packet_rx (D = { $procmux$149231_Y $procmux$149247_Y $procmux$149264_Y $procmux$149282_Y }, Q = \received_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$152195 ($sdff) from module lsc1_packet_rx (D = $procmux$149228_Y, Q = \received_crc [31:24]). +Adding EN signal on $auto$ff.cc:266:slice$152195 ($sdff) from module lsc1_packet_rx (D = $procmux$149244_Y, Q = \received_crc [23:16]). +Adding EN signal on $auto$ff.cc:266:slice$152195 ($sdff) from module lsc1_packet_rx (D = $procmux$149261_Y, Q = \received_crc [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$152195 ($sdff) from module lsc1_packet_rx (D = $procmux$149279_Y, Q = \received_crc [7:0]). +Adding SRST signal on $procdff$150520 ($dff) from module lsc1_packet_rx (D = $procmux$149889_Y, Q = \flags, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$152232 ($sdff) from module lsc1_packet_rx (D = \rx_data, Q = \flags). +Adding SRST signal on $procdff$150518 ($dff) from module lsc1_packet_rx (D = $procmux$149922_Y, Q = \version, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$152236 ($sdff) from module lsc1_packet_rx (D = \rx_data, Q = \version). +Adding SRST signal on $procdff$150516 ($dff) from module lsc1_packet_rx (D = $procmux$149950_Y, Q = \body_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152240 ($sdff) from module lsc1_packet_rx (D = $procmux$149943_Y, Q = \body_index). +Adding SRST signal on $procdff$150515 ($dff) from module lsc1_packet_rx (D = $procmux$149964_Y, Q = \header_index, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$152248 ($sdff) from module lsc1_packet_rx (D = $procmux$149958_Y, Q = \header_index). +Adding SRST signal on $procdff$150514 ($dff) from module lsc1_packet_rx (D = $procmux$150003_Y, Q = \state, rval = 3'000). +Adding SRST signal on $procdff$150513 ($dff) from module lsc1_packet_rx (D = $procmux$150037_Y, Q = \fault_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$152257 ($sdff) from module lsc1_packet_rx (D = $procmux$150024_Y, Q = \fault_status). +Adding SRST signal on $procdff$150512 ($dff) from module lsc1_packet_rx (D = $procmux$150073_Y, Q = \fault_valid, rval = 1'0). +Adding SRST signal on $procdff$150511 ($dff) from module lsc1_packet_rx (D = $2$lookahead\frame_payload$22[2047:0]$81, Q = \frame_payload, rval = 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding SRST signal on $procdff$150510 ($dff) from module lsc1_packet_rx (D = $procmux$150096_Y, Q = \frame_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152277 ($sdff) from module lsc1_packet_rx (D = \declared_length, Q = \frame_length). +Adding SRST signal on $procdff$150509 ($dff) from module lsc1_packet_rx (D = $procmux$150119_Y, Q = \frame_opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$152289 ($sdff) from module lsc1_packet_rx (D = \opcode, Q = \frame_opcode). +Adding SRST signal on $procdff$150508 ($dff) from module lsc1_packet_rx (D = $procmux$150144_Y, Q = \frame_valid, rval = 1'0). +Adding SRST signal on $procdff$150478 ($dff) from module lsc1_packet_tx (D = $procmux$148966_Y, Q = \done_pulse, rval = 1'0). +Adding SRST signal on $procdff$150487 ($dff) from module lsc1_packet_tx (D = $procmux$149043_Y, Q = \payload_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$152307 ($sdff) from module lsc1_packet_tx (D = $ternary$asic_core/rtl/lsc1_packet_tx.sv:36$437_Y, Q = \payload_crc_work). +Adding SRST signal on $procdff$150486 ($dff) from module lsc1_packet_tx (D = $procmux$149055_Y, Q = \envelope_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$152313 ($sdff) from module lsc1_packet_tx (D = $ternary$asic_core/rtl/lsc1_packet_tx.sv:36$398_Y, Q = \envelope_crc_work). +Adding SRST signal on $procdff$150485 ($dff) from module lsc1_packet_tx (D = $procmux$149070_Y, Q = \saved_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$152319 ($sdff) from module lsc1_packet_tx (D = $not$asic_core/rtl/lsc1_packet_tx.sv:91$483_Y, Q = \saved_crc). +Adding SRST signal on $procdff$150484 ($dff) from module lsc1_packet_tx (D = $procmux$149079_Y, Q = \saved_payload, rval = 544'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152325 ($sdff) from module lsc1_packet_tx (D = \payload, Q = \saved_payload). +Adding SRST signal on $procdff$150483 ($dff) from module lsc1_packet_tx (D = $procmux$149085_Y, Q = \saved_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$152327 ($sdff) from module lsc1_packet_tx (D = \status, Q = \saved_status). +Adding SRST signal on $procdff$150482 ($dff) from module lsc1_packet_tx (D = $procmux$149091_Y, Q = \saved_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152329 ($sdff) from module lsc1_packet_tx (D = \payload_length, Q = \saved_length). +Adding SRST signal on $procdff$150481 ($dff) from module lsc1_packet_tx (D = $procmux$149100_Y, Q = \index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152331 ($sdff) from module lsc1_packet_tx (D = $add$asic_core/rtl/lsc1_packet_tx.sv:100$522_Y, Q = \index). +Adding SRST signal on $procdff$150480 ($dff) from module lsc1_packet_tx (D = $procmux$149115_Y, Q = \active, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$152339 ($sdff) from module lsc1_packet_tx (D = $procmux$149115_Y, Q = \active). +Adding SRST signal on $procdff$150479 ($dff) from module lsc1_packet_tx (D = $procmux$149130_Y, Q = \payload_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$152347 ($sdff) from module lsc1_packet_tx (D = $ternary$asic_core/rtl/lsc1_packet_tx.sv:92$519_Y, Q = \payload_crc). +Adding SRST signal on $procdff$150456 ($dff) from module lsc1_stream_adapter (D = $procmux$147438_Y, Q = \payload_index, rval = 6'000000). +Adding EN signal on $auto$ff.cc:266:slice$152353 ($sdff) from module lsc1_stream_adapter (D = $procmux$147438_Y, Q = \payload_index). +Adding SRST signal on $procdff$150455 ($dff) from module lsc1_stream_adapter (D = $procmux$147464_Y, Q = \saved_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152371 ($sdff) from module lsc1_stream_adapter (D = \operand_b, Q = \saved_b). +Adding SRST signal on $procdff$150454 ($dff) from module lsc1_stream_adapter (D = $procmux$147480_Y, Q = \saved_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$152377 ($sdff) from module lsc1_stream_adapter (D = \operand_a, Q = \saved_a). +Adding SRST signal on $procdff$150453 ($dff) from module lsc1_stream_adapter (D = $procmux$147496_Y, Q = \saved_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$152383 ($sdff) from module lsc1_stream_adapter (D = \operation, Q = \saved_operation). +Adding SRST signal on $procdff$150452 ($dff) from module lsc1_stream_adapter (D = $2$lookahead\result$670[127:0]$693, Q = \result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding SRST signal on $procdff$150451 ($dff) from module lsc1_stream_adapter (D = $procmux$147517_Y, Q = \fault, rval = 1'0). +Adding SRST signal on $procdff$150450 ($dff) from module lsc1_stream_adapter (D = $procmux$147355_Y, Q = \done_pulse, rval = 1'0). +Adding SRST signal on $procdff$150449 ($dff) from module lsc1_stream_adapter (D = $procmux$147529_Y, Q = \state, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$152396 ($sdff) from module lsc1_stream_adapter (D = $procmux$147529_Y, Q = \state). +Adding SRST signal on $procdff$150457 ($dff) from module lsc1_stream_adapter (D = $procmux$147407_Y, Q = \result_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:266:slice$152418 ($sdff) from module lsc1_stream_adapter (D = $procmux$147407_Y, Q = \result_index). + +12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gate.. +Finding unused cells or wires in module \gf128_mul_bitstream.. +Finding unused cells or wires in module \gf2n_mul_bitstream.. +Finding unused cells or wires in module \gold.. +Finding unused cells or wires in module \leanvm_b_stream_alu.. +Finding unused cells or wires in module \lsc1_field_encoder.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_stream_adapter.. +Removed 565 unused cells and 18239 unused wires. + + +12.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module gate. +Optimizing module gf128_mul_bitstream. +Optimizing module gf2n_mul_bitstream. + +Optimizing module gold. + +Optimizing module leanvm_b_stream_alu. + +Optimizing module lsc1_field_encoder. + +Optimizing module lsc1_packet_rx. + +Optimizing module lsc1_packet_tx. + +Optimizing module lsc1_stream_adapter. + + +12.9. Rerunning OPT passes. (Maybe there is more to do..) + +12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gate.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gf128_mul_bitstream.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gf2n_mul_bitstream.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gold.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \leanvm_b_stream_alu.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_field_encoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_packet_tx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_stream_adapter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gate. + Optimizing cells in module \gf128_mul_bitstream. + Optimizing cells in module \gf2n_mul_bitstream. + Optimizing cells in module \gold. + Optimizing cells in module \leanvm_b_stream_alu. + New ctrl vector for $pmux cell $procmux$147696: { $eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$588_Y $eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $procmux$147716_CMP $eq$asic_core/rtl/leanvm_b_stream_alu.sv:85$570_Y $auto$opt_reduce.cc:134:opt_pmux$152435 $eq$asic_core/rtl/leanvm_b_stream_alu.sv:211$607_Y } + New ctrl vector for $pmux cell $procmux$147774: { $eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$588_Y $procmux$147653_CMP $eq$asic_core/rtl/leanvm_b_stream_alu.sv:207$592_Y $eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $procmux$147716_CMP $procmux$147650_CMP $eq$asic_core/rtl/leanvm_b_stream_alu.sv:85$570_Y $auto$opt_reduce.cc:134:opt_pmux$152437 $eq$asic_core/rtl/leanvm_b_stream_alu.sv:211$607_Y $eq$asic_core/rtl/leanvm_b_stream_alu.sv:212$611_Y } + Optimizing cells in module \leanvm_b_stream_alu. + Optimizing cells in module \lsc1_field_encoder. + Optimizing cells in module \lsc1_packet_rx. + Optimizing cells in module \lsc1_packet_tx. + Optimizing cells in module \lsc1_stream_adapter. + New ctrl vector for $pmux cell $procmux$147239: { $procmux$147231_CMP $auto$opt_reduce.cc:134:opt_pmux$152439 } + Optimizing cells in module \lsc1_stream_adapter. +Performed a total of 3 changes. + +12.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gate'. +Finding identical cells in module `\gf128_mul_bitstream'. +Finding identical cells in module `\gf2n_mul_bitstream'. + +Finding identical cells in module `\gold'. + +Finding identical cells in module `\leanvm_b_stream_alu'. + +Finding identical cells in module `\lsc1_field_encoder'. + +Finding identical cells in module `\lsc1_packet_rx'. + +Finding identical cells in module `\lsc1_packet_tx'. + +Finding identical cells in module `\lsc1_stream_adapter'. + +Removed a total of 442 cells. + +12.13. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $auto$ff.cc:266:slice$150927 ($dffe) from module gold (D = $3\n_writes[31:0], Q = \n_writes). +Adding EN signal on $auto$ff.cc:266:slice$150926 ($dffe) from module gold (D = $3\n_deferred[31:0], Q = \n_deferred). +Adding EN signal on $auto$ff.cc:266:slice$150925 ($dffe) from module gold (D = $17\txn_id[31:0], Q = \txn_id). +Adding EN signal on $auto$ff.cc:266:slice$150924 ($dffe) from module gold (D = \frame_payload [63:32], Q = \pc). +Adding EN signal on $auto$ff.cc:266:slice$150923 ($dffe) from module gold (D = \frame_payload [95:64], Q = \fp). +Adding EN signal on $auto$ff.cc:266:slice$150922 ($dffe) from module gold (D = $28\addr_a[31:0], Q = \addr_a). +Adding EN signal on $auto$ff.cc:266:slice$150921 ($dffe) from module gold (D = $28\addr_b[31:0], Q = \addr_b). +Adding EN signal on $auto$ff.cc:266:slice$150920 ($dffe) from module gold (D = $28\addr_c[31:0], Q = \addr_c). +Adding EN signal on $auto$ff.cc:266:slice$150919 ($dffe) from module gold (D = \frame_payload [655:624], Q = \proposed_pc). +Adding EN signal on $auto$ff.cc:266:slice$150918 ($dffe) from module gold (D = \frame_payload [687:656], Q = \proposed_fp). +Adding EN signal on $auto$ff.cc:266:slice$150917 ($dffe) from module gold (D = $6\next_pc_value[31:0], Q = \next_pc_value). +Adding EN signal on $auto$ff.cc:266:slice$150916 ($dffe) from module gold (D = $6\next_fp_value[31:0], Q = \next_fp_value). +Adding EN signal on $auto$ff.cc:266:slice$150915 ($dffe) from module gold (D = $3\deferred_target[31:0], Q = \deferred_target). +Adding EN signal on $auto$ff.cc:266:slice$150914 ($dffe) from module gold (D = $3\deferred_local[31:0], Q = \deferred_local). +Adding EN signal on $auto$ff.cc:266:slice$150913 ($dffe) from module gold (D = \frame_payload [103:96], Q = \profile). +Adding EN signal on $auto$ff.cc:266:slice$150912 ($dffe) from module gold (D = $28\pres_a[7:0], Q = \pres_a). +Adding EN signal on $auto$ff.cc:266:slice$150911 ($dffe) from module gold (D = $29\pres_b[7:0], Q = \pres_b). +Adding EN signal on $auto$ff.cc:266:slice$150910 ($dffe) from module gold (D = $29\pres_c[7:0], Q = \pres_c). +Adding EN signal on $auto$ff.cc:266:slice$150909 ($dffe) from module gold (D = $28\val_a[127:0], Q = \val_a). +Adding EN signal on $auto$ff.cc:266:slice$150908 ($dffe) from module gold (D = $29\val_b[127:0], Q = \val_b). +Adding EN signal on $auto$ff.cc:266:slice$150907 ($dffe) from module gold (D = $29\val_c[127:0], Q = \val_c). +Adding EN signal on $auto$ff.cc:266:slice$150906 ($dffe) from module gold (D = $30\inv_value[127:0], Q = \inv_value). +Adding EN signal on $auto$ff.cc:266:slice$150905 ($dffe) from module gold (D = $28\result_value[127:0], Q = \result_value). +Adding EN signal on $auto$ff.cc:266:slice$150904 ($dffe) from module gold (D = $9\solved_a[127:0], Q = \solved_a). +Adding EN signal on $auto$ff.cc:266:slice$150903 ($dffe) from module gold (D = $9\solved_b[127:0], Q = \solved_b). +Adding EN signal on $auto$ff.cc:266:slice$150902 ($dffe) from module gold (D = $3\write_address[31:0], Q = \write_address). +Adding EN signal on $auto$ff.cc:266:slice$150901 ($dffe) from module gold (D = $3\write_value[127:0], Q = \write_value). +Adding EN signal on $auto$ff.cc:266:slice$152061 ($sdffe) from module leanvm_b_stream_alu (D = $procmux$147774_Y, Q = \state). +Adding EN signal on $auto$ff.cc:266:slice$152029 ($sdffe) from module leanvm_b_stream_alu (D = $procmux$147696_Y, Q = \byte_index). +Adding EN signal on $auto$ff.cc:266:slice$152276 ($sdff) from module lsc1_packet_rx (D = $3$lookahead\frame_payload$22[2047:0]$99, Q = \frame_payload). +Adding SRST signal on $auto$ff.cc:266:slice$152389 ($sdff) from module lsc1_stream_adapter (D = $3$lookahead\result$670[127:0]$702, Q = \result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$153994 ($sdff) from module lsc1_stream_adapter (D = $3$lookahead\result$670[127:0]$702, Q = \result). + +12.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gate.. +Finding unused cells or wires in module \gf128_mul_bitstream.. +Finding unused cells or wires in module \gf2n_mul_bitstream.. +Finding unused cells or wires in module \gold.. +Finding unused cells or wires in module \leanvm_b_stream_alu.. +Finding unused cells or wires in module \lsc1_field_encoder.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_stream_adapter.. +Removed 473 unused cells and 913 unused wires. + + +12.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module gate. +Optimizing module gf128_mul_bitstream. +Optimizing module gf2n_mul_bitstream. +Optimizing module gold. + +Optimizing module leanvm_b_stream_alu. +Optimizing module lsc1_field_encoder. +Optimizing module lsc1_packet_rx. + +Optimizing module lsc1_packet_tx. +Optimizing module lsc1_stream_adapter. + + +12.16. Rerunning OPT passes. (Maybe there is more to do..) + +12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gate.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gf128_mul_bitstream.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gf2n_mul_bitstream.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gold.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \leanvm_b_stream_alu.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_field_encoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_packet_tx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_stream_adapter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gate. + Optimizing cells in module \gf128_mul_bitstream. + Optimizing cells in module \gf2n_mul_bitstream. + Optimizing cells in module \gold. + Optimizing cells in module \leanvm_b_stream_alu. + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$153984: { $auto$opt_dff.cc:194:make_patterns_logic$153981 $auto$opt_dff.cc:194:make_patterns_logic$153979 $auto$opt_dff.cc:194:make_patterns_logic$151999 $auto$opt_dff.cc:194:make_patterns_logic$152009 $auto$opt_dff.cc:194:make_patterns_logic$152032 $auto$opt_dff.cc:194:make_patterns_logic$152034 $auto$opt_dff.cc:194:make_patterns_logic$152036 $auto$opt_dff.cc:194:make_patterns_logic$152038 $auto$opt_dff.cc:194:make_patterns_logic$152040 } + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$153977: { $auto$opt_dff.cc:194:make_patterns_logic$153974 $auto$opt_dff.cc:194:make_patterns_logic$153972 $auto$opt_dff.cc:194:make_patterns_logic$152001 $auto$opt_dff.cc:194:make_patterns_logic$152003 $auto$opt_dff.cc:194:make_patterns_logic$152032 $auto$opt_dff.cc:194:make_patterns_logic$152034 $auto$opt_dff.cc:194:make_patterns_logic$152036 $auto$opt_dff.cc:194:make_patterns_logic$152062 $auto$opt_dff.cc:194:make_patterns_logic$152070 $auto$opt_dff.cc:194:make_patterns_logic$152074 $auto$opt_dff.cc:194:make_patterns_logic$152078 $auto$opt_dff.cc:194:make_patterns_logic$152080 } + Optimizing cells in module \leanvm_b_stream_alu. + Optimizing cells in module \lsc1_field_encoder. + Optimizing cells in module \lsc1_packet_rx. + Optimizing cells in module \lsc1_packet_tx. + Optimizing cells in module \lsc1_stream_adapter. +Performed a total of 2 changes. + +12.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gate'. +Finding identical cells in module `\gf128_mul_bitstream'. +Finding identical cells in module `\gf2n_mul_bitstream'. +Finding identical cells in module `\gold'. + +Finding identical cells in module `\leanvm_b_stream_alu'. +Finding identical cells in module `\lsc1_field_encoder'. +Finding identical cells in module `\lsc1_packet_rx'. + +Finding identical cells in module `\lsc1_packet_tx'. +Finding identical cells in module `\lsc1_stream_adapter'. + +Removed a total of 749 cells. + +12.20. Executing OPT_DFF pass (perform DFF optimizations). + +12.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gate.. +Finding unused cells or wires in module \gf128_mul_bitstream.. +Finding unused cells or wires in module \gf2n_mul_bitstream.. +Finding unused cells or wires in module \gold.. +Finding unused cells or wires in module \leanvm_b_stream_alu.. +Finding unused cells or wires in module \lsc1_field_encoder.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_stream_adapter.. +Removed 2 unused cells and 751 unused wires. + + +12.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module gate. +Optimizing module gf128_mul_bitstream. +Optimizing module gf2n_mul_bitstream. +Optimizing module gold. +Optimizing module leanvm_b_stream_alu. +Optimizing module lsc1_field_encoder. +Optimizing module lsc1_packet_rx. +Optimizing module lsc1_packet_tx. +Optimizing module lsc1_stream_adapter. + +12.23. Rerunning OPT passes. (Maybe there is more to do..) + +12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gate.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gf128_mul_bitstream.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gf2n_mul_bitstream.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gold.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \leanvm_b_stream_alu.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_field_encoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_packet_tx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_stream_adapter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gate. + Optimizing cells in module \gf128_mul_bitstream. + Optimizing cells in module \gf2n_mul_bitstream. + Optimizing cells in module \gold. + Optimizing cells in module \leanvm_b_stream_alu. + Optimizing cells in module \lsc1_field_encoder. + Optimizing cells in module \lsc1_packet_rx. + Optimizing cells in module \lsc1_packet_tx. + Optimizing cells in module \lsc1_stream_adapter. +Performed a total of 0 changes. + +12.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gate'. +Finding identical cells in module `\gf128_mul_bitstream'. +Finding identical cells in module `\gf2n_mul_bitstream'. +Finding identical cells in module `\gold'. +Finding identical cells in module `\leanvm_b_stream_alu'. +Finding identical cells in module `\lsc1_field_encoder'. +Finding identical cells in module `\lsc1_packet_rx'. +Finding identical cells in module `\lsc1_packet_tx'. +Finding identical cells in module `\lsc1_stream_adapter'. +Removed a total of 0 cells. + +12.27. Executing OPT_DFF pass (perform DFF optimizations). + +12.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gate.. +Finding unused cells or wires in module \gf128_mul_bitstream.. +Finding unused cells or wires in module \gf2n_mul_bitstream.. +Finding unused cells or wires in module \gold.. +Finding unused cells or wires in module \leanvm_b_stream_alu.. +Finding unused cells or wires in module \lsc1_field_encoder.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_stream_adapter.. + +12.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module gate. +Optimizing module gf128_mul_bitstream. +Optimizing module gf2n_mul_bitstream. +Optimizing module gold. +Optimizing module leanvm_b_stream_alu. +Optimizing module lsc1_field_encoder. +Optimizing module lsc1_packet_rx. +Optimizing module lsc1_packet_tx. +Optimizing module lsc1_stream_adapter. + +12.30. Finished OPT passes. (There is nothing left to do.) + +13. Executing EQUIV_MAKE pass (creating equiv checking module). +Presumably equivalent wires: _unused_adapter_fault_gold (\alu_fault_gold), _unused_adapter_fault_gate (\adapter.fault_gate) -> _unused_adapter_fault +Presumably equivalent wires: abort_gold (\abort_gold), abort_gate (\abort_gate) -> abort +Presumably equivalent wires: active_profile_gold (\active_profile_gold), active_profile_gate (\active_profile_gate) -> active_profile +Presumably equivalent wires: addr_a_gold (\addr_a_gold), addr_a_gate (\addr_a_gate) -> addr_a +Presumably equivalent wires: addr_b_gold (\addr_b_gold), addr_b_gate (\addr_b_gate) -> addr_b +Presumably equivalent wires: addr_c_gold (\addr_c_gold), addr_c_gate (\addr_c_gate) -> addr_c +Presumably equivalent wires: alu_busy_gold (\alu_busy_gold), alu_busy_gate (\adapter.busy_gate) -> alu_busy +Presumably equivalent wires: alu_done_gold (\alu_done_gold), alu_done_gate (\adapter.done_pulse_gate) -> alu_done +Presumably equivalent wires: alu_fault_gold (\alu_fault_gold), alu_fault_gate (\adapter.fault_gate) -> alu_fault +Presumably equivalent wires: alu_operand_a_gold (\alu_operand_a_gold), alu_operand_a_gate (\alu_operand_a_gate) -> alu_operand_a +Presumably equivalent wires: alu_operand_b_gold (\alu_operand_b_gold), alu_operand_b_gate (\alu_operand_b_gate) -> alu_operand_b +Presumably equivalent wires: alu_operation_gold (\alu_operation_gold), alu_operation_gate (\alu_operation_gate) -> alu_operation +Presumably equivalent wires: alu_result_gold (\alu_result_gold), alu_result_gate (\adapter.result_gate) -> alu_result +Presumably equivalent wires: alu_start_gold (\alu_start_gold), alu_start_gate (\alu_start_gate) -> alu_start +Presumably equivalent wires: busy_gold (\busy_gold), busy_gate (\busy_gate) -> busy +Presumably equivalent wires: capture_result_crc_gold (\capture_result_crc_gold), capture_result_crc_gate (\capture_result_crc_gate) -> capture_result_crc +Presumably equivalent wires: clk_gold (\clk_gold), clk_gate (\clk_gate) -> clk +Presumably equivalent wires: committed_fp_gold (\committed_fp_gold), committed_fp_gate (\committed_fp_gate) -> committed_fp +Presumably equivalent wires: committed_pc_gold (\committed_pc_gold), committed_pc_gate (\committed_pc_gate) -> committed_pc +Presumably equivalent wires: compute_state_gold (\compute_state_gold), compute_state_gate (\compute_state_gate) -> compute_state +Presumably equivalent wires: deferred_local_gold (\deferred_local_gold), deferred_local_gate (\deferred_local_gate) -> deferred_local +Presumably equivalent wires: deferred_target_gold (\deferred_target_gold), deferred_target_gate (\deferred_target_gate) -> deferred_target +Presumably equivalent wires: done_pulse_gold (\done_pulse_gold), done_pulse_gate (\done_pulse_gate) -> done_pulse +Presumably equivalent wires: encoder_busy_gold (\encoder_busy_gold), encoder_busy_gate (\field_encoder.busy_gate) -> encoder_busy +Presumably equivalent wires: encoder_done_gold (\encoder_done_gold), encoder_done_gate (\field_encoder.done_pulse_gate) -> encoder_done +Presumably equivalent wires: encoder_fault_gold (\encoder_fault_gold), encoder_fault_gate (\field_encoder.fault_gate) -> encoder_fault +Presumably equivalent wires: encoder_index_gold (\encoder_index_gold), encoder_index_gate (\encoder_index_gate) -> encoder_index +Presumably equivalent wires: encoder_result_gold (\encoder_result_gold), encoder_result_gate (\field_encoder.result_gate) -> encoder_result +Presumably equivalent wires: encoder_start_gold (\encoder_start_gold), encoder_start_gate (\encoder_start_gate) -> encoder_start +Presumably equivalent wires: event_ready_gold (\event_ready_gold), event_ready_gate (\receiver.frame_ready_gate) -> event_ready +Presumably equivalent wires: event_valid_gold (\event_valid_gold), event_valid_gate (\event_valid_gate) -> event_valid +Presumably equivalent wires: fault_gold (\fault_gold), fault_gate (\fault_gate) -> fault +Presumably equivalent wires: fp_gold (\fp_gold), fp_gate (\fp_gate) -> fp +Presumably equivalent wires: frame_length_gold (\frame_length_gold), frame_length_gate (\receiver.frame_length_gate) -> frame_length +Presumably equivalent wires: frame_opcode_gold (\frame_opcode_gold), frame_opcode_gate (\receiver.frame_opcode_gate) -> frame_opcode +Presumably equivalent wires: frame_payload_gold (\frame_payload_gold), frame_payload_gate (\receiver.frame_payload_gate) -> frame_payload +Presumably equivalent wires: frame_valid_gold (\frame_valid_gold), frame_valid_gate (\receiver.frame_valid_gate) -> frame_valid +Presumably equivalent wires: inv_value_gold (\inv_value_gold), inv_value_gate (\inv_value_gate) -> inv_value +Presumably equivalent wires: lane_enable_gold (\lane_enable_gold), lane_enable_gate (\lane_enable_gate) -> lane_enable +Presumably equivalent wires: last_fault_gold (\last_fault_gold), last_fault_gate ({ \_2783__gate [3] \_2782__gate [3:2] \_2783__gate [2] \_2782__gate [1:0] \_2783__gate [1:0] }) -> last_fault +Presumably equivalent wires: last_status_gold (\last_status_gold), last_status_gate ({ \_2785__gate [3] \_2784__gate [3:2] \_2785__gate [2] \_2784__gate [1:0] \_2785__gate [1:0] }) -> last_status +Presumably equivalent wires: n_deferred_gold (\n_deferred_gold), n_deferred_gate (\n_deferred_gate) -> n_deferred +Presumably equivalent wires: n_writes_gold (\n_writes_gold), n_writes_gate (\n_writes_gate) -> n_writes +Presumably equivalent wires: next_fp_value_gold (\next_fp_value_gold), next_fp_value_gate (\next_fp_value_gate) -> next_fp_value +Presumably equivalent wires: next_pc_value_gold (\next_pc_value_gold), next_pc_value_gate (\next_pc_value_gate) -> next_pc_value +Presumably equivalent wires: parser_rx_ready_gold (\parser_rx_ready_gold), parser_rx_ready_gate (\receiver.rx_ready_gate) -> parser_rx_ready +Presumably equivalent wires: pc_gold (\pc_gold), pc_gate (\pc_gate) -> pc +Presumably equivalent wires: pres_a_gold (\pres_a_gold), pres_a_gate (\pres_a_gate) -> pres_a +Presumably equivalent wires: pres_b_gold (\pres_b_gold), pres_b_gate (\pres_b_gate) -> pres_b +Presumably equivalent wires: pres_c_gold (\pres_c_gold), pres_c_gate (\pres_c_gate) -> pres_c +Presumably equivalent wires: profile_gold (\profile_gold), profile_gate (\profile_gate) -> profile +Presumably equivalent wires: proposed_fp_gold (\proposed_fp_gold), proposed_fp_gate (\proposed_fp_gate) -> proposed_fp +Presumably equivalent wires: proposed_pc_gold (\proposed_pc_gold), proposed_pc_gate (\proposed_pc_gate) -> proposed_pc +Presumably equivalent wires: result_pending_gold (\result_pending_gold), result_pending_gate (\result_pending_gate) -> result_pending +Presumably equivalent wires: result_value_gold (\result_value_gold), result_value_gate (\result_value_gate) -> result_value +Presumably equivalent wires: retire_seq_gold (\retire_seq_gold), retire_seq_gate (\retire_seq_gate) -> retire_seq +Presumably equivalent wires: rst_n_gold (\rst_n_gold), rst_n_gate (\rst_n_gate) -> rst_n +Presumably equivalent wires: rx_busy_gold (\rx_busy_gold), rx_busy_gate (\receiver.busy_gate) -> rx_busy +Presumably equivalent wires: rx_data_gold (\rx_data_gold), rx_data_gate (\rx_data_gate) -> rx_data +Presumably equivalent wires: rx_fault_status_gold (\rx_fault_status_gold), rx_fault_status_gate (\receiver.fault_status_gate) -> rx_fault_status +Presumably equivalent wires: rx_fault_valid_gold (\rx_fault_valid_gold), rx_fault_valid_gate (\receiver.fault_valid_gate) -> rx_fault_valid +Presumably equivalent wires: rx_ready_gold (\rx_ready_gold), rx_ready_gate (\rx_ready_gate) -> rx_ready +Presumably equivalent wires: rx_valid_gold (\rx_valid_gold), rx_valid_gate (\rx_valid_gate) -> rx_valid +Presumably equivalent wires: solved_a_gold (\solved_a_gold), solved_a_gate (\solved_a_gate) -> solved_a +Presumably equivalent wires: solved_b_gold (\solved_b_gold), solved_b_gate (\solved_b_gate) -> solved_b +Presumably equivalent wires: staged_next_fp_gold (\staged_next_fp_gold), staged_next_fp_gate (\staged_next_fp_gate) -> staged_next_fp +Presumably equivalent wires: staged_next_pc_gold (\staged_next_pc_gold), staged_next_pc_gate (\staged_next_pc_gate) -> staged_next_pc +Presumably equivalent wires: staged_result_crc_gold (\staged_result_crc_gold), staged_result_crc_gate (\staged_result_crc_gate) -> staged_result_crc +Presumably equivalent wires: staged_txn_id_gold (\staged_txn_id_gold), staged_txn_id_gate (\staged_txn_id_gate) -> staged_txn_id +Presumably equivalent wires: state_valid_gold (\state_valid_gold), state_valid_gate (\state_valid_gate) -> state_valid +Presumably equivalent wires: tx_busy_gold (\tx_busy_gold), tx_busy_gate (\transmitter.active_gate) -> tx_busy +Presumably equivalent wires: tx_data_gold (\tx_data_gold), tx_data_gate (\transmitter.tx_data_gate) -> tx_data +Presumably equivalent wires: tx_done_gold (\tx_done_gold), tx_done_gate (\transmitter.done_pulse_gate) -> tx_done +Presumably equivalent wires: tx_length_gold (\tx_length_gold), tx_length_gate (\tx_length_gate) -> tx_length +Presumably equivalent wires: tx_payload_gold (\tx_payload_gold), tx_payload_gate (\tx_payload_gate) -> tx_payload +Presumably equivalent wires: tx_payload_crc_gold (\tx_payload_crc_gold), tx_payload_crc_gate (\transmitter.payload_crc_gate) -> tx_payload_crc +Presumably equivalent wires: tx_ready_gold (\tx_ready_gold), tx_ready_gate (\tx_ready_gate) -> tx_ready +Presumably equivalent wires: tx_start_gold (\tx_start_gold), tx_start_gate (\tx_start_gate) -> tx_start +Presumably equivalent wires: tx_status_gold (\tx_status_gold), tx_status_gate (\tx_status_gate) -> tx_status +Presumably equivalent wires: tx_valid_gold (\tx_valid_gold), tx_valid_gate (\transmitter.active_gate) -> tx_valid +Presumably equivalent wires: txn_id_gold (\txn_id_gold), txn_id_gate (\txn_id_gate) -> txn_id +Presumably equivalent wires: val_a_gold (\val_a_gold), val_a_gate (\val_a_gate) -> val_a +Presumably equivalent wires: val_b_gold (\val_b_gold), val_b_gate (\val_b_gate) -> val_b +Presumably equivalent wires: val_c_gold (\val_c_gold), val_c_gate (\val_c_gate) -> val_c +Presumably equivalent wires: write_address_gold (\write_address_gold), write_address_gate (\write_address_gate) -> write_address +Presumably equivalent wires: write_value_gold (\write_value_gold), write_value_gate (\write_value_gate) -> write_value +Changing input A of cell $add$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3052$3267_gate ($add): \retire_seq_gate -> \retire_seq +Changing input D of cell $auto$ff.cc:266:slice$150732_gate ($sdffe): \encoder_index_gate -> \encoder_index +Changing input D of cell $auto$ff.cc:266:slice$150756_gate ($sdffe): \staged_next_fp_gate -> \staged_next_fp +Changing input D of cell $auto$ff.cc:266:slice$150758_gate ($sdffe): \staged_next_pc_gate -> \staged_next_pc +Changing input D of cell $auto$ff.cc:266:slice$150799_gate ($sdffe): \alu_operation_gate -> \alu_operation +Changing input D of cell $auto$ff.cc:266:slice$150801_gate ($sdffe): \alu_operand_a_gate -> \alu_operand_a +Changing input D of cell $auto$ff.cc:266:slice$150803_gate ($sdffe): \alu_operand_b_gate -> \alu_operand_b +Changing input D of cell $auto$ff.cc:266:slice$150823_gate ($sdffe): \tx_length_gate -> \tx_length +Changing input D of cell $auto$ff.cc:266:slice$150825_gate ($sdffe): \tx_status_gate -> \tx_status +Changing input D of cell $auto$ff.cc:266:slice$150827_gate ($sdffe): \tx_payload_gate -> \tx_payload +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3833$3840_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3834$3841_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3835$3842_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3836$3843_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3837$3844_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3838$3845_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3839$3846_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3840$3847_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3841$3848_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3842$3849_gate ($eq): \compute_state_gate -> \compute_state +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3863$3870_gate ($eq): \alu_operation_gate -> \alu_operation +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3864$3871_gate ($eq): \alu_operation_gate -> \alu_operation +Changing input A of cell $eq$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3865$3872_gate ($eq): \alu_operation_gate -> \alu_operation +Changing input A of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4358$4039_gate ($logic_and): \encoder_start_gate -> \encoder_start +Changing input A of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5159$4374_gate ($logic_and): \tx_start_gate -> \tx_start +Changing input A of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5160$4375_gate ($logic_and): \transmitter.active_gate -> \tx_valid +Changing input B of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5240$4439_gate ($logic_and): \lane_enable_gate -> \lane_enable +Changing input A of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5249$4448_gate ($logic_and): \pres_c_gate -> \pres_c +Changing input A of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5251$4450_gate ($logic_and): \pres_b_gate -> \pres_b +Changing input B of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5251$4450_gate ($logic_and): \pres_c_gate -> \pres_c +Changing input A of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5253$4452_gate ($logic_and): \pres_b_gate -> \pres_b +Changing input B of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5254$4453_gate ($logic_and): \pres_c_gate -> \pres_c +Changing input B of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5256$4455_gate ($logic_and): \capture_result_crc_gate -> \capture_result_crc +Changing input A of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5259$4458_gate ($logic_and): \pres_b_gate -> \pres_b +Changing input A of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5268$4467_gate ($logic_and): \event_valid_gate -> \event_valid +Changing input A of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5287$4486_gate ($logic_and): \state_valid_gate -> \state_valid +Changing input B of cell $logic_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5313$4512_gate ($logic_and): \lane_enable_gate -> \lane_enable +Changing input A of cell $logic_not$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3831$3838_gate ($logic_not): \profile_gate -> \profile +Changing input A of cell $logic_not$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3857$3864_gate ($logic_not): \compute_state_gate -> \compute_state +Changing input A of cell $logic_not$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5161$4376_gate ($logic_not): \transmitter.active_gate -> \tx_valid +Changing input A of cell $logic_not$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5322$4521_gate ($logic_not): \pres_c_gate -> \pres_c +Changing input A of cell $logic_not$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5323$4522_gate ($logic_not): \pres_b_gate -> \pres_b +Changing input A of cell $logic_not$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5324$4523_gate ($logic_not): \pres_a_gate -> \pres_a +Changing input A of cell $logic_not$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5325$4524_gate ($logic_not): \tx_start_gate -> \tx_start +Changing input B of cell $logic_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5329$4528_gate ($logic_or): \transmitter.active_gate -> \tx_valid +Changing input B of cell $logic_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5330$4529_gate ($logic_or): \tx_start_gate -> \tx_start +Changing input B of cell $logic_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5331$4530_gate ($logic_or): \event_valid_gate -> \event_valid +Changing input B of cell $logic_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5332$4531_gate ($logic_or): \result_pending_gate -> \result_pending +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3491$3498_gate ($ne): { \receiver.fault_valid_gate \_0386__gate \_0227__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_0386__gate \_0227__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3492$3499_gate ($ne): { \receiver.fault_valid_gate \_0386__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_0386__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3493$3500_gate ($ne): { \receiver.fault_valid_gate \_1661__gate \_1513__gate \_1476__gate \_1660__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1661__gate \_1513__gate \_1476__gate \_1660__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3494$3501_gate ($ne): { \receiver.fault_valid_gate \_1587__gate \_1662__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1587__gate \_1662__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3506$3513_gate ($ne): { \receiver.fault_valid_gate \_0386__gate \_0227__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate \abort_gate } -> { \receiver.fault_valid_gate \_0386__gate \_0227__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending \abort_gate } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3507$3514_gate ($ne): { \receiver.fault_valid_gate \_0386__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate \abort_gate } -> { \receiver.fault_valid_gate \_0386__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending \abort_gate } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3508$3515_gate ($ne): { \receiver.fault_valid_gate \_1661__gate \_1513__gate \_1476__gate \_1660__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate \abort_gate } -> { \receiver.fault_valid_gate \_1661__gate \_1513__gate \_1476__gate \_1660__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending \abort_gate } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3509$3516_gate ($ne): { \receiver.fault_valid_gate \_1587__gate \_1662__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate \abort_gate } -> { \receiver.fault_valid_gate \_1587__gate \_1662__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending \abort_gate } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3521$3528_gate ($ne): { \receiver.fault_valid_gate \_0386__gate \_0227__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_0386__gate \_0227__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3522$3529_gate ($ne): { \receiver.fault_valid_gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3550$3557_gate ($ne): { \receiver.fault_valid_gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3551$3558_gate ($ne): { \receiver.fault_valid_gate \_1613__gate \_1610__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1613__gate \_1610__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3552$3559_gate ($ne): { \receiver.fault_valid_gate \_1610__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1610__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3553$3560_gate ($ne): { \receiver.fault_valid_gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3554$3561_gate ($ne): { \receiver.fault_valid_gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3555$3562_gate ($ne): { \receiver.fault_valid_gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3564$3571_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1634__gate \_1548__gate \_1568__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_0889__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1634__gate \_1548__gate \_1568__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_0889__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3565$3572_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1634__gate \_1548__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_0889__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1634__gate \_1548__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_0889__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3566$3573_gate ($ne): { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1630__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1561__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1630__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1561__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3567$3574_gate ($ne): { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1630__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1630__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3568$3575_gate ($ne): { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3569$3576_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3570$3577_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3571$3578_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3572$3579_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1548__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1548__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3573$3580_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3574$3581_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3575$3582_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3576$3583_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3577$3584_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3578$3585_gate ($ne): { \receiver.fault_valid_gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3595$3602_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1634__gate \_1548__gate \_1568__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_0889__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1634__gate \_1548__gate \_1568__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_0889__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3596$3603_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1634__gate \_1548__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_0889__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1634__gate \_1548__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_0889__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3597$3604_gate ($ne): { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1630__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1561__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1630__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1561__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3598$3605_gate ($ne): { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1630__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1630__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3599$3606_gate ($ne): { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1713__gate \_1554__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3600$3607_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1695__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3601$3608_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1475__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3602$3609_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3603$3610_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1548__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1553__gate \_1552__gate \_1548__gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3604$3611_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1627__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3605$3612_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1624__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3606$3613_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1617__gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3607$3614_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1613__gate \_1610__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1613__gate \_1610__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3608$3615_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1610__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1610__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3609$3616_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1605__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3610$3617_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1604__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3611$3618_gate ($ne): { \receiver.fault_valid_gate \_1554__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1554__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \_1504__gate \_1502__gate \_1501__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3614$3621_gate ($ne): { \_0938__gate \alu_start_gate } -> { \_0938__gate \alu_start } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3635$3642_gate ($ne): { \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \result_pending_gate } -> { \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3645$3652_gate ($ne): { \receiver.fault_valid_gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \_1507__gate \_1506__gate \_1505__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3671$3678_gate ($ne): { \receiver.fault_valid_gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1539__gate \_1534__gate \_1532__gate \_0169__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3672$3679_gate ($ne): { \receiver.fault_valid_gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1539__gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3673$3680_gate ($ne): { \receiver.fault_valid_gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1534__gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3674$3681_gate ($ne): { \receiver.fault_valid_gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending_gate } -> { \receiver.fault_valid_gate \_1532__gate \_1529__gate \_1528__gate \_1527__gate \_1526__gate \_1525__gate \_1677__gate \_1477__gate \_1591__gate \_1519__gate \_0887__gate \_0886__gate \_0885__gate \_1512__gate \_1511__gate \_1510__gate \_1509__gate \_1508__gate \result_pending } +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5412$4611_gate ($ne): \val_c_gate -> \val_c +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5413$4612_gate ($ne): \val_a_gate -> \val_a +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5414$4613_gate ($ne): \val_b_gate -> \val_b +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5414$4613_gate ($ne): \val_c_gate -> \val_c +Changing input A of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5415$4614_gate ($ne): \val_b_gate -> \val_b +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5416$4615_gate ($ne): \val_b_gate -> \val_b +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5417$4616_gate ($ne): \val_c_gate -> \val_c +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5419$4618_gate ($ne): \result_value_gate -> \result_value +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5424$4623_gate ($ne): \staged_txn_id_gate -> \staged_txn_id +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5425$4624_gate ($ne): \staged_result_crc_gate -> \staged_result_crc +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5439$4638_gate ($ne): \active_profile_gate -> \active_profile +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5440$4639_gate ($ne): \committed_pc_gate -> \committed_pc +Changing input B of cell $ne$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5441$4640_gate ($ne): \committed_fp_gate -> \committed_fp +Changing input A of cell $not$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3695$3702_gate ($not): \result_pending_gate -> \result_pending +Changing input A of cell $reduce_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3761$3768_gate ($reduce_and): { \_1512__gate \_0887__gate \_0852__gate \_0851__gate \_0850__gate \_0846__gate \_0845__gate \_0844__gate \_0843__gate \_0842__gate \_0841__gate \_0840__gate \_0839__gate \_0838__gate \_0837__gate \_0836__gate \_0834__gate \_0833__gate \result_pending_gate } -> { \_1512__gate \_0887__gate \_0852__gate \_0851__gate \_0850__gate \_0846__gate \_0845__gate \_0844__gate \_0843__gate \_0842__gate \_0841__gate \_0840__gate \_0839__gate \_0838__gate \_0837__gate \_0836__gate \_0834__gate \_0833__gate \result_pending } +Changing input A of cell $reduce_and$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3770$3777_gate ($reduce_and): { \_0938__gate \_0833__gate \alu_start_gate } -> { \_0938__gate \_0833__gate \alu_start } +Changing input A of cell $reduce_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5396$4595_gate ($reduce_or): \compute_state_gate -> \compute_state +Changing input A of cell $reduce_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5407$4606_gate ($reduce_or): \n_writes_gate -> \n_writes +Changing input A of cell $reduce_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5411$4610_gate ($reduce_or): \n_deferred_gate -> \n_deferred +Changing input A of cell $reduce_or$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6978$6177_gate ($reduce_or): \pres_a_gate -> \pres_a +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3886$3893_gate ($mux): \alu_start_gate -> \alu_start +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3923$3900_gate ($mux): \alu_start_gate -> \alu_start +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3946$3907_gate ($mux): \alu_start_gate -> \alu_start +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3966$3911_gate ($mux): \alu_start_gate -> \alu_start +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3968$3913_gate ($mux): \alu_start_gate -> \alu_start +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:4003$3928_gate ($mux): \alu_start_gate -> \alu_start +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5464$4663_gate ($mux): \addr_c_gate -> \addr_c +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5470$4669_gate ($mux): \addr_b_gate -> \addr_b +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5472$4671_gate ($mux): \addr_b_gate [23:0] -> \addr_b [23:0] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5472$4671_gate ($mux): \deferred_local_gate [31:8] -> \deferred_local [31:8] +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5473$4672_gate ($mux): \addr_a_gate [23:0] -> \addr_a [23:0] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5473$4672_gate ($mux): \deferred_target_gate [31:8] -> \deferred_target [31:8] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5474$4673_gate ($mux): \addr_c_gate -> \addr_c +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5475$4674_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5478$4677_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5483$4682_gate ($mux): { \addr_c_gate \addr_b_gate } -> { \addr_c \addr_b } +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5484$4683_gate ($mux): \n_writes_gate -> \n_writes +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5499$4698_gate ($mux): \write_value_gate -> \write_value +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5500$4699_gate ($mux): \write_address_gate -> \write_address +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5500$4699_gate ($mux): \addr_c_gate -> \addr_c +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5538$4737_gate ($mux): \solved_a_gate -> \solved_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5539$4738_gate ($mux): \solved_b_gate -> \solved_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5551$4750_gate ($mux): \deferred_target_gate [7:0] -> \deferred_target [7:0] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5552$4751_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5553$4752_gate ($mux): \deferred_local_gate [31:8] -> \deferred_local [31:8] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5557$4756_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5560$4759_gate ($mux): \write_value_gate -> \write_value +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5561$4760_gate ($mux): \write_address_gate -> \write_address +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5581$4780_gate ($mux): \write_value_gate -> \write_value +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5582$4781_gate ($mux): \write_address_gate -> \write_address +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5583$4782_gate ($mux): { \addr_c_gate \addr_b_gate } -> { \addr_c \addr_b } +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5584$4783_gate ($mux): \proposed_fp_gate -> \proposed_fp +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5585$4784_gate ($mux): \proposed_pc_gate -> \proposed_pc +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5603$4802_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5603$4802_gate ($mux): \addr_a_gate -> \addr_a +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5604$4803_gate ($mux): \addr_a_gate [31:24] -> \addr_a [31:24] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5604$4803_gate ($mux): \deferred_local_gate [7:0] -> \deferred_local [7:0] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5605$4804_gate ($mux): \deferred_target_gate [7:0] -> \deferred_target [7:0] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5606$4805_gate ($mux): \addr_b_gate -> \addr_b +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5608$4807_gate ($mux): \addr_b_gate [31:24] -> \addr_b [31:24] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5610$4809_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5615$4814_gate ($mux): { \addr_c_gate \addr_b_gate } -> { \addr_c \addr_b } +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5616$4815_gate ($mux): \write_value_gate -> \write_value +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5617$4816_gate ($mux): \write_address_gate -> \write_address +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5617$4816_gate ($mux): \addr_b_gate -> \addr_b +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5618$4817_gate ($mux): \n_writes_gate -> \n_writes +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5637$4836_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5637$4836_gate ($mux): \addr_a_gate -> \addr_a +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5638$4837_gate ($mux): \addr_a_gate [31:24] -> \addr_a [31:24] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5640$4839_gate ($mux): \addr_b_gate -> \addr_b +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5642$4841_gate ($mux): \addr_b_gate [31:24] -> \addr_b [31:24] +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5643$4842_gate ($mux): \addr_b_gate [23:0] -> \addr_b [23:0] +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5644$4843_gate ($mux): \addr_a_gate [23:0] -> \addr_a [23:0] +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5645$4844_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5649$4848_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5654$4853_gate ($mux): { \addr_c_gate \addr_b_gate } -> { \addr_c \addr_b } +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5655$4854_gate ($mux): \deferred_local_gate -> \deferred_local +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5655$4854_gate ($mux): \addr_c_gate -> \addr_c +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5656$4855_gate ($mux): \deferred_target_gate -> \deferred_target +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5656$4855_gate ($mux): \addr_b_gate -> \addr_b +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5657$4856_gate ($mux): \n_deferred_gate -> \n_deferred +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5658$4857_gate ($mux): \write_value_gate -> \write_value +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5658$4857_gate ($mux): \val_c_gate -> \val_c +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5659$4858_gate ($mux): \write_address_gate -> \write_address +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5659$4858_gate ($mux): \addr_b_gate -> \addr_b +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5660$4859_gate ($mux): \n_writes_gate -> \n_writes +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5661$4860_gate ($mux): \deferred_local_gate -> \deferred_local +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5662$4861_gate ($mux): \deferred_target_gate -> \deferred_target +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5663$4862_gate ($mux): \n_deferred_gate -> \n_deferred +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5664$4863_gate ($mux): \val_b_gate -> \val_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5665$4864_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5674$4873_gate ($mux): \deferred_local_gate -> \deferred_local +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5675$4874_gate ($mux): \deferred_target_gate -> \deferred_target +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5676$4875_gate ($mux): \n_deferred_gate -> \n_deferred +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5720$4919_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5758$4957_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5778$4977_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5811$5010_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5822$5021_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5827$5026_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5862$5061_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5873$5072_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5878$5077_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5909$5108_gate ($mux): \staged_result_crc_gate -> \staged_result_crc +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5912$5111_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5950$5149_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5965$5164_gate ($mux): \next_fp_value_gate -> \next_fp_value +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5971$5170_gate ($mux): \next_fp_value_gate -> \next_fp_value +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5976$5175_gate ($mux): \next_fp_value_gate -> \next_fp_value +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5979$5178_gate ($mux): \next_fp_value_gate -> \next_fp_value +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5986$5185_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6001$5200_gate ($mux): \next_pc_value_gate -> \next_pc_value +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6007$5206_gate ($mux): \next_pc_value_gate -> \next_pc_value +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6012$5211_gate ($mux): \next_pc_value_gate -> \next_pc_value +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6015$5214_gate ($mux): \next_pc_value_gate -> \next_pc_value +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6022$5221_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6037$5236_gate ($mux): \txn_id_gate -> \txn_id +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6043$5242_gate ($mux): \txn_id_gate -> \txn_id +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6046$5245_gate ($mux): \txn_id_gate -> \txn_id +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6050$5249_gate ($mux): \txn_id_gate -> \txn_id +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6053$5252_gate ($mux): \txn_id_gate -> \txn_id +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6060$5259_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6103$5302_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6123$5322_gate ($mux): \proposed_pc_gate [15:0] -> \proposed_pc [15:0] +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6126$5325_gate ($mux): \proposed_fp_gate [15:0] -> \proposed_fp [15:0] +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6152$5351_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6169$5368_gate ($mux): \inv_value_gate -> \inv_value +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6191$5390_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6208$5407_gate ($mux): \val_c_gate -> \val_c +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6230$5429_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6274$5473_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6305$5504_gate ($mux): \capture_result_crc_gate -> \capture_result_crc +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6308$5507_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6346$5545_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6356$5555_gate ($mux): { 416'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \staged_next_fp_gate \staged_next_pc_gate \_0454__gate \receiver.frame_payload_gate [31:0] } -> { 416'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \staged_next_fp \staged_next_pc \_0454__gate \receiver.frame_payload_gate [31:0] } +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6357$5556_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6362$5561_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6366$5565_gate ($mux): { 391'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \state_valid_gate \committed_fp_gate \committed_pc_gate \_2783__gate [3] \_2782__gate [3:2] \_2783__gate [2] \_2782__gate [1:0] \_2783__gate [1:0] \retire_seq_gate \_2785__gate [3] \_2784__gate [3:2] \_2785__gate [2] \_2784__gate [1:0] \_2785__gate [1:0] \_2729__gate \_2728__gate } -> { 391'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \state_valid \committed_fp \committed_pc \_2783__gate [3] \_2782__gate [3:2] \_2783__gate [2] \_2782__gate [1:0] \_2783__gate [1:0] \retire_seq \_2785__gate [3] \_2784__gate [3:2] \_2785__gate [2] \_2784__gate [1:0] \_2785__gate [1:0] \_2729__gate \_2728__gate } +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6370$5569_gate ($mux): { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0315__gate \_0128__gate [7:0] \next_fp_value_gate \next_pc_value_gate \txn_id_gate } -> { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0315__gate \_0128__gate [7:0] \next_fp_value \next_pc_value \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6370$5569_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6371$5570_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6374$5573_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \txn_id } +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6377$5576_gate ($mux): { 232'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0120__gate [207:176] \_0213__gate [175:168] \_0120__gate [167:160] \_0213__gate [159:0] \n_writes_gate [7:0] \next_fp_value_gate \next_pc_value_gate \txn_id_gate } -> { 232'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0120__gate [207:176] \_0213__gate [175:168] \_0120__gate [167:160] \_0213__gate [159:0] \n_writes [7:0] \next_fp_value \next_pc_value \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6377$5576_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6379$5578_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6381$5580_gate ($mux): { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0120__gate \n_writes_gate [7:0] \proposed_fp_gate \proposed_pc_gate \txn_id_gate } -> { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0120__gate \n_writes [7:0] \proposed_fp \proposed_pc \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6381$5580_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6382$5581_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6384$5583_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6385$5584_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6387$5586_gate ($mux): { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0046__gate \_0029__gate [7:0] \next_fp_value_gate \next_pc_value_gate \txn_id_gate } -> { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0046__gate \_0029__gate [7:0] \next_fp_value \next_pc_value \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6387$5586_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6388$5587_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6390$5589_gate ($mux): { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0439__gate \_0436__gate [7:0] \next_fp_value_gate \next_pc_value_gate \txn_id_gate } -> { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \_0439__gate \_0436__gate [7:0] \next_fp_value \next_pc_value \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6390$5589_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6391$5590_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6393$5592_gate ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gate } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6397$5596_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6408$5607_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6413$5612_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6425$5624_gate ($mux): \tx_length_gate -> \tx_length +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6445$5644_gate ($mux): \tx_status_gate -> \tx_status +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6456$5655_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6467$5666_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6472$5671_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6484$5683_gate ($mux): \fault_gate -> \fault +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6512$5711_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6513$5712_gate ($mux): \addr_b_gate -> \addr_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6514$5713_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6519$5718_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6520$5719_gate ($mux): \addr_b_gate -> \addr_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6521$5720_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6544$5743_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6545$5744_gate ($mux): \addr_b_gate -> \addr_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6546$5745_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6550$5749_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6551$5750_gate ($mux): \addr_b_gate -> \addr_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6552$5751_gate ($mux): \addr_a_gate -> \addr_a +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6556$5755_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6557$5756_gate ($mux): \addr_b_gate -> \addr_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6558$5757_gate ($mux): \addr_a_gate -> \addr_a +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6596$5795_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6627$5826_gate ($mux): \result_pending_gate -> \result_pending +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6656$5855_gate ($mux): \result_value_gate -> \result_value +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6667$5866_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6694$5893_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6695$5894_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6696$5895_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6697$5896_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6698$5897_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6699$5898_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6700$5899_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6701$5900_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6702$5901_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6786$5985_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6847$6046_gate ($mux): \result_pending_gate -> \result_pending +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6879$6078_gate ($mux): \result_pending_gate -> \result_pending +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6919$6118_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6920$6119_gate ($mux): \addr_b_gate -> \addr_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6921$6120_gate ($mux): \addr_a_gate -> \addr_a +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6933$6132_gate ($mux): \result_pending_gate -> \result_pending +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6963$6162_gate ($mux): \addr_c_gate -> \addr_c +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6964$6163_gate ($mux): \addr_b_gate -> \addr_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6965$6164_gate ($mux): \addr_a_gate -> \addr_a +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6982$6181_gate ($mux): \fp_gate [15:0] -> \fp [15:0] +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6983$6182_gate ($mux): \addr_b_gate -> \addr_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6983$6182_gate ($mux): \addr_a_gate -> \addr_a +Changing input A of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6984$6183_gate ($mux): \val_b_gate -> \val_b +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6984$6183_gate ($mux): \val_a_gate -> \val_a +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6986$6185_gate ($mux): \result_pending_gate -> \result_pending +Changing input B of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6987$6186_gate ($mux): \staged_txn_id_gate -> \staged_txn_id +Changing input S of cell $ternary$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:6987$6186_gate ($mux): \result_pending_gate -> \result_pending +Changing input B of cell $xor$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5215$4414_gate ($xor): \transmitter.tx_data_gate -> \tx_data +Changing input B of cell $xor$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:5216$4415_gate ($xor): \transmitter.tx_data_gate -> \tx_data +Changing input A of cell $add$results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v:3051$3266_gate ($add): \pc_gate [15:0] -> \pc [15:0] +Changing input A of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:484$2454_gold ($add): \retire_seq_gold -> \retire_seq +Changing input A of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:578$2923_gold ($add): \frame_payload_gold [63:32] -> \frame_payload [63:32] +Changing input A of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:601$2944_gold ($add): \frame_payload_gold [95:64] -> \frame_payload [95:64] +Changing input B of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:601$2944_gold ($add): \frame_payload_gold [143:112] -> \frame_payload [143:112] +Changing input A of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:634$2983_gold ($add): \frame_payload_gold [375:344] -> \frame_payload [375:344] +Changing input B of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:634$2983_gold ($add): \frame_payload_gold [175:144] -> \frame_payload [175:144] +Changing input A of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:635$2984_gold ($add): \frame_payload_gold [95:64] -> \frame_payload [95:64] +Changing input B of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:635$2984_gold ($add): \frame_payload_gold [207:176] -> \frame_payload [207:176] +Changing input A of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:671$3036_gold ($add): \frame_payload_gold [95:64] -> \frame_payload [95:64] +Changing input B of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:671$3036_gold ($add): \frame_payload_gold [175:144] -> \frame_payload [175:144] +Changing input D of cell $auto$ff.cc:266:slice$151037_gold ($sdffe): \frame_payload_gold [23:16] -> \frame_payload [23:16] +Changing input D of cell $auto$ff.cc:266:slice$151111_gold ($sdffe): \staged_next_fp_gold -> \staged_next_fp +Changing input D of cell $auto$ff.cc:266:slice$151147_gold ($sdffe): \staged_next_pc_gold -> \staged_next_pc +Changing input D of cell $auto$ff.cc:266:slice$152613_gold ($dffe): \frame_payload_gold [63:32] -> \frame_payload [63:32] +Changing input D of cell $auto$ff.cc:266:slice$152666_gold ($dffe): \frame_payload_gold [95:64] -> \frame_payload [95:64] +Changing input D of cell $auto$ff.cc:266:slice$152878_gold ($dffe): \frame_payload_gold [655:624] -> \frame_payload [655:624] +Changing input D of cell $auto$ff.cc:266:slice$152935_gold ($dffe): \frame_payload_gold [687:656] -> \frame_payload [687:656] +Changing input D of cell $auto$ff.cc:266:slice$153228_gold ($dffe): \frame_payload_gold [103:96] -> \frame_payload [103:96] +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150936_gold ($ne): { $50\decision_deferred[0:0]_gold $31\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $50\decision_deferred[0:0]_gold $31\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150938_gold ($ne): { $50\decision_deferred[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $50\decision_deferred[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150940_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:448$2371_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:445$2367_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:441$2357_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:439$2351_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:448$2371_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:445$2367_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:441$2357_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:439$2351_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150942_gold ($ne): { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:475$2448_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:471$2433_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:475$2448_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:471$2433_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150944_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:419$2282_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:419$2282_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150946_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:218$2071_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \alu_fault_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:218$2071_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \alu_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150948_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150950_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:338$1482_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:338$1482_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150952_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:324$1383_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:324$1383_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150969_gold ($ne): { $50\decision_deferred[0:0]_gold $31\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold \abort_gold } -> { $50\decision_deferred[0:0]_gold $31\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid \abort_gold } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150971_gold ($ne): { $50\decision_deferred[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold \abort_gold } -> { $50\decision_deferred[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid \abort_gold } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150973_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:448$2371_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:445$2367_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:441$2357_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:439$2351_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold \abort_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:448$2371_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:445$2367_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:441$2357_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:439$2351_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid \abort_gold } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150975_gold ($ne): { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:475$2448_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:471$2433_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold \abort_gold } -> { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:475$2448_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:471$2433_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid \abort_gold } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150977_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:419$2282_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold \abort_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:419$2282_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid \abort_gold } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150979_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:218$2071_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \alu_fault_gold \abort_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:218$2071_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \alu_fault \abort_gold } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150981_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold \abort_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault \abort_gold } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150983_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:338$1482_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold \abort_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:338$1482_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault \abort_gold } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$150985_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:324$1383_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold \abort_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:324$1383_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault \abort_gold } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151223_gold ($ne): { $50\decision_deferred[0:0]_gold $31\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $50\decision_deferred[0:0]_gold $31\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151227_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151229_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151231_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151233_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151235_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151237_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151239_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151241_gold ($ne): { $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151243_gold ($ne): { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151245_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151247_gold ($ne): { $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151249_gold ($ne): { $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151251_gold ($ne): { $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151253_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151255_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:218$2071_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \alu_fault_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:218$2071_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \alu_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151257_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \alu_fault_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \alu_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151259_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151261_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:324$1383_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:324$1383_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151263_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151265_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151461_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:471$2433_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:471$2433_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151507_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151509_gold ($ne): { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:636$3001_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:628$2981_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:636$3001_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:628$2981_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151511_gold ($ne): { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:628$2981_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:628$2981_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151513_gold ($ne): { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151515_gold ($ne): { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151517_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151547_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:338$1482_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:338$1482_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151549_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151584_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:741$3137_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:722$3101_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:508$2525_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:741$3137_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:722$3101_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:508$2525_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151586_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:741$3137_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:508$2525_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:741$3137_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:508$2525_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151588_gold ($ne): { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:683$3061_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2824_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:683$3061_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2824_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151590_gold ($ne): { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:683$3061_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:683$3061_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151592_gold ($ne): { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151594_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151596_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151598_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151600_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151602_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151604_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151606_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151608_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151610_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151612_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151614_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151616_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151618_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151620_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151622_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151624_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151626_gold ($ne): { $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151628_gold ($ne): { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151630_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151632_gold ($ne): { $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151634_gold ($ne): { $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151636_gold ($ne): { $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151638_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151833_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:741$3137_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:722$3101_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:508$2525_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:741$3137_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:722$3101_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:508$2525_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151835_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:741$3137_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:508$2525_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:741$3137_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:508$2525_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151837_gold ($ne): { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:683$3061_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2824_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:683$3061_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2824_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151839_gold ($ne): { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:683$3061_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:683$3061_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151841_gold ($ne): { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $procmux$143570_CMP_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151843_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151845_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151847_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151849_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:761$3148_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:754$3144_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3127_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151851_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:672$3054_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151853_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:665$3034_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151855_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:662$3011_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151857_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:636$3001_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:628$2981_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:636$3001_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:628$2981_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151859_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:628$2981_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:628$2981_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151861_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:625$2964_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151863_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:622$2959_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$151865_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:771$3150_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$152564_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold \result_pending_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold \result_pending } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$152994_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$152996_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$152998_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153000_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153002_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153004_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153006_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153008_gold ($ne): { $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153010_gold ($ne): { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153012_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153014_gold ($ne): { $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153016_gold ($ne): { $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153018_gold ($ne): { $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153020_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153022_gold ($ne): { $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \encoder_fault_gold } -> { $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153024_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \encoder_fault_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold \encoder_fault } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153733_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $28\decision_ok[0:0]_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153735_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:647$3003_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153737_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:608$2951_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:195:make_patterns_logic$153739_gold ($ne): { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending_gold \rx_fault_valid_gold } -> { $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:589$2933_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:549$2907_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:546$2857_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:536$2832_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:526$2772_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:522$2704_Y_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_Y_gold $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_Y_gold $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:507$2544_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:499$2468_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold \result_pending \rx_fault_valid } +Changing input A of cell $auto$opt_dff.cc:210:make_patterns_logic$151040_gold ($not): \rx_fault_valid_gold -> \rx_fault_valid +Changing input A of cell $auto$opt_dff.cc:210:make_patterns_logic$151042_gold ($not): \result_pending_gold -> \result_pending +Changing input A of cell $auto$opt_dff.cc:220:make_patterns_logic$151109_gold ($reduce_and): { $auto$rtlil.cc:2401:Not$151065_gold $auto$rtlil.cc:2401:Not$151049_gold $auto$rtlil.cc:2401:Not$151051_gold $auto$rtlil.cc:2401:Not$151053_gold $auto$rtlil.cc:2401:Not$151055_gold $auto$rtlil.cc:2401:Not$151057_gold $auto$rtlil.cc:2401:Not$151059_gold $auto$rtlil.cc:2401:Not$151061_gold $auto$rtlil.cc:2401:Not$151063_gold $auto$rtlil.cc:2401:Not$151039_gold $auto$rtlil.cc:2401:Not$151041_gold $auto$rtlil.cc:2401:Not$151045_gold $auto$rtlil.cc:2401:Not$151103_gold $auto$rtlil.cc:2401:Not$151105_gold $auto$rtlil.cc:2401:Not$151107_gold $auto$rtlil.cc:2401:Not$151047_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold \result_pending_gold } -> { $auto$rtlil.cc:2401:Not$151065_gold $auto$rtlil.cc:2401:Not$151049_gold $auto$rtlil.cc:2401:Not$151051_gold $auto$rtlil.cc:2401:Not$151053_gold $auto$rtlil.cc:2401:Not$151055_gold $auto$rtlil.cc:2401:Not$151057_gold $auto$rtlil.cc:2401:Not$151059_gold $auto$rtlil.cc:2401:Not$151061_gold $auto$rtlil.cc:2401:Not$151063_gold $auto$rtlil.cc:2401:Not$151039_gold $auto$rtlil.cc:2401:Not$151041_gold $auto$rtlil.cc:2401:Not$151045_gold $auto$rtlil.cc:2401:Not$151103_gold $auto$rtlil.cc:2401:Not$151105_gold $auto$rtlil.cc:2401:Not$151107_gold $auto$rtlil.cc:2401:Not$151047_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_Y_gold \result_pending } +Changing input A of cell $auto$opt_dff.cc:254:combine_resets$151992_gold ($reduce_or): { $auto$rtlil.cc:2401:Not$151043_gold $auto$rtlil.cc:2401:Not$151988_gold $auto$rtlil.cc:2401:Not$151990_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:471$2433_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid_gold $auto$rtlil.cc:2401:Not$150931_gold \abort_gold } -> { $auto$rtlil.cc:2401:Not$151043_gold $auto$rtlil.cc:2401:Not$151988_gold $auto$rtlil.cc:2401:Not$151990_gold $ne$asic_core/rtl/lsc1_packet_frontend.sv:471$2433_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_Y_gold $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_Y_gold $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_Y_gold \rx_fault_valid $auto$rtlil.cc:2401:Not$150931_gold \abort_gold } +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:238$1256_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:240$1261_gold ($logic_not): \profile_gold -> \profile +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:261$1282_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:318$1149_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:320$1285_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:334$1389_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:346$1485_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:357$1579_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:366$1664_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:374$1749_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:385$1829_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:396$1910_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:407$1990_gold ($eq): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:417$2214_gold ($eq): \rx_fault_status_gold -> \rx_fault_status +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:418$2216_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:438$2286_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:469$2373_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:507$2522_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:508$2525_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:509$2529_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:512$2536_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:513$2541_gold ($eq): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:71$833_gold ($logic_not): \compute_state_gold -> \compute_state +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:741$3132_gold ($logic_not): \frame_payload_gold [479:352] -> \frame_payload [479:352] +Changing input A of cell $eq$asic_core/rtl/lsc1_packet_frontend.sv:741$3135_gold ($logic_not): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input A of cell $ge$asic_core/rtl/lsc1_packet_frontend.sv:446$2366_gold ($ge): \frame_payload_gold [15:8] -> \frame_payload [15:8] +Changing input A of cell $ge$asic_core/rtl/lsc1_packet_frontend.sv:585$2929_gold ($ge): \frame_payload_gold [63:32] -> \frame_payload [63:32] +Changing input A of cell $ge$asic_core/rtl/lsc1_packet_frontend.sv:585$2930_gold ($ge): \frame_payload_gold [95:64] -> \frame_payload [95:64] +Changing input A of cell $ge$asic_core/rtl/lsc1_packet_frontend.sv:625$2960_gold ($ge): \frame_payload_gold [375:344] -> \frame_payload [375:344] +Changing input A of cell $ge$asic_core/rtl/lsc1_packet_frontend.sv:683$3059_gold ($ge): \frame_payload_gold [655:624] -> \frame_payload [655:624] +Changing input A of cell $ge$asic_core/rtl/lsc1_packet_frontend.sv:684$3060_gold ($ge): \frame_payload_gold [687:656] -> \frame_payload [687:656] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2698_gold ($gt): \frame_payload_gold [279:272] -> \frame_payload [279:272] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2750_gold ($gt): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2755_gold ($gt): \frame_payload_gold [383:376] -> \frame_payload [383:376] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2760_gold ($gt): \frame_payload_gold [519:512] -> \frame_payload [519:512] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2813_gold ($gt): \frame_payload_gold [351:344] -> \frame_payload [351:344] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2818_gold ($gt): \frame_payload_gold [487:480] -> \frame_payload [487:480] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2823_gold ($gt): \frame_payload_gold [695:688] -> \frame_payload [695:688] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:142$2894_gold ($gt): \frame_payload_gold [623:616] -> \frame_payload [623:616] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:441$2357_gold ($gt): \frame_payload_gold [23:16] -> \frame_payload [23:16] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:518$2597_gold ($gt): \frame_payload_gold [103:96] -> \frame_payload [103:96] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:594$2935_gold ($gt): \frame_payload_gold [143:112] -> \frame_payload [143:112] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:622$2955_gold ($gt): \frame_payload_gold [207:176] -> \frame_payload [207:176] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:623$2958_gold ($gt): \frame_payload_gold [175:144] -> \frame_payload [175:144] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:626$2962_gold ($gt): \frame_payload_gold [63:32] -> \frame_payload [63:32] +Changing input A of cell $gt$asic_core/rtl/lsc1_packet_frontend.sv:662$3007_gold ($gt): \frame_payload_gold [175:144] -> \frame_payload [175:144] +Changing input A of cell $le$asic_core/rtl/lsc1_packet_frontend.sv:445$2365_gold ($le): \frame_payload_gold [7:0] -> \frame_payload [7:0] +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:115$846_gold ($logic_and): \parser_rx_ready_gold -> \parser_rx_ready +Changing input B of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:115$846_gold ($logic_and): \lane_enable_gold -> \lane_enable +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:218$2071_gold ($logic_and): \pres_c_gold -> \pres_c +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:242$1268_gold ($logic_and): \pres_b_gold -> \pres_b +Changing input B of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:242$1268_gold ($logic_and): \pres_c_gold -> \pres_c +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:245$1274_gold ($logic_and): \pres_b_gold -> \pres_b +Changing input B of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:249$1276_gold ($logic_and): \pres_c_gold -> \pres_c +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:313$1148_gold ($logic_and): \tx_done_gold -> \tx_done +Changing input B of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:313$1148_gold ($logic_and): \capture_result_crc_gold -> \capture_result_crc +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:318$1150_gold ($logic_and): \encoder_done_gold -> \encoder_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:320$1286_gold ($logic_and): \encoder_done_gold -> \encoder_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:324$1383_gold ($logic_and): \pres_b_gold -> \pres_b +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:334$1390_gold ($logic_and): \encoder_done_gold -> \encoder_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:346$1486_gold ($logic_and): \encoder_done_gold -> \encoder_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:357$1580_gold ($logic_and): \alu_done_gold -> \alu_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:366$1665_gold ($logic_and): \alu_done_gold -> \alu_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:374$1750_gold ($logic_and): \alu_done_gold -> \alu_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:385$1830_gold ($logic_and): \alu_done_gold -> \alu_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:396$1911_gold ($logic_and): \alu_done_gold -> \alu_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:407$1991_gold ($logic_and): \alu_done_gold -> \alu_done +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_gold ($logic_and): \event_valid_gold -> \event_valid +Changing input B of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:414$2077_gold ($logic_and): \event_ready_gold -> \event_ready +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:583$2928_gold ($logic_and): \state_valid_gold -> \state_valid +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:598$2942_gold ($logic_and): \frame_payload_gold [279:272] -> \frame_payload [279:272] +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:696$3064_gold ($logic_and): \frame_payload_gold [695:688] -> \frame_payload [695:688] +Changing input A of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:70$836_gold ($logic_and): \event_ready_gold -> \event_ready +Changing input B of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:733$3125_gold ($logic_and): \frame_payload_gold [487:480] -> \frame_payload [487:480] +Changing input B of cell $logic_and$asic_core/rtl/lsc1_packet_frontend.sv:86$845_gold ($logic_and): \lane_enable_gold -> \lane_enable +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2699_gold ($logic_not): \frame_payload_gold [279:272] -> \frame_payload [279:272] +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2751_gold ($logic_not): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2756_gold ($logic_not): \frame_payload_gold [383:376] -> \frame_payload [383:376] +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2761_gold ($logic_not): \frame_payload_gold [519:512] -> \frame_payload [519:512] +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2814_gold ($logic_not): \frame_payload_gold [351:344] -> \frame_payload [351:344] +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2819_gold ($logic_not): \frame_payload_gold [487:480] -> \frame_payload [487:480] +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2824_gold ($logic_not): \frame_payload_gold [695:688] -> \frame_payload [695:688] +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:142$2895_gold ($logic_not): \frame_payload_gold [623:616] -> \frame_payload [623:616] +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:222$2074_gold ($logic_not): \pres_c_gold -> \pres_c +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:249$1275_gold ($logic_not): \pres_b_gold -> \pres_b +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:375$1826_gold ($logic_not): \pres_a_gold -> \pres_a +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:70$830_gold ($logic_not): \tx_busy_gold -> \tx_busy +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:70$831_gold ($logic_not): \tx_start_gold -> \tx_start +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:71$835_gold ($logic_not): \alu_busy_gold -> \alu_busy +Changing input A of cell $logic_not$asic_core/rtl/lsc1_packet_frontend.sv:71$837_gold ($logic_not): \encoder_busy_gold -> \encoder_busy +Changing input A of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:116$847_gold ($logic_or): \rx_busy_gold -> \rx_busy +Changing input B of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:116$847_gold ($logic_or): \tx_busy_gold -> \tx_busy +Changing input B of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:116$848_gold ($logic_or): \tx_start_gold -> \tx_start +Changing input B of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:116$849_gold ($logic_or): \event_valid_gold -> \event_valid +Changing input B of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:116$850_gold ($logic_or): \result_pending_gold -> \result_pending +Changing input B of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:116$853_gold ($logic_or): \alu_busy_gold -> \alu_busy +Changing input B of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:116$854_gold ($logic_or): \encoder_busy_gold -> \encoder_busy +Changing input A of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:235$1249_gold ($logic_or): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:358$1661_gold ($logic_or): \alu_fault_gold -> \alu_fault +Changing input A of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:367$1744_gold ($logic_or): \alu_fault_gold -> \alu_fault +Changing input A of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:80$839_gold ($logic_or): \frame_valid_gold -> \frame_valid +Changing input B of cell $logic_or$asic_core/rtl/lsc1_packet_frontend.sv:80$839_gold ($logic_or): \rx_fault_valid_gold -> \rx_fault_valid +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:117$851_gold ($reduce_bool): \compute_state_gold -> \compute_state +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:142$2700_gold ($reduce_bool): \frame_payload_gold [407:280] -> \frame_payload [407:280] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:142$2752_gold ($reduce_bool): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:142$2757_gold ($reduce_bool): \frame_payload_gold [511:384] -> \frame_payload [511:384] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:142$2762_gold ($reduce_bool): \frame_payload_gold [647:520] -> \frame_payload [647:520] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:142$2815_gold ($reduce_bool): \frame_payload_gold [479:352] -> \frame_payload [479:352] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:142$2820_gold ($reduce_bool): \frame_payload_gold [615:488] -> \frame_payload [615:488] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:142$2825_gold ($reduce_bool): \frame_payload_gold [823:696] -> \frame_payload [823:696] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:142$2896_gold ($reduce_bool): \frame_payload_gold [751:624] -> \frame_payload [751:624] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:169$1577_gold ($reduce_bool): \n_writes_gold -> \n_writes +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:182$1388_gold ($reduce_bool): \n_deferred_gold -> \n_deferred +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:218$2070_gold ($ne): \val_c_gold -> \val_c +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:218$2070_gold ($ne): \alu_result_gold -> \alu_result +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:235$1248_gold ($ne): \encoder_result_gold -> \encoder_result +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:235$1248_gold ($ne): \val_a_gold -> \val_a +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:242$1269_gold ($ne): \val_b_gold -> \val_b +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:242$1269_gold ($ne): \val_c_gold -> \val_c +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:324$1382_gold ($ne): \val_b_gold -> \val_b +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:324$1382_gold ($ne): \encoder_result_gold -> \encoder_result +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:338$1482_gold ($ne): \encoder_result_gold -> \encoder_result +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:338$1482_gold ($ne): \val_b_gold -> \val_b +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_gold ($ne): \encoder_result_gold -> \encoder_result +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:350$1574_gold ($ne): \val_c_gold -> \val_c +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:358$1660_gold ($ne): \alu_result_gold -> \alu_result +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:367$1743_gold ($ne): \alu_result_gold -> \alu_result +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:367$1743_gold ($ne): \result_value_gold -> \result_value +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:419$2282_gold ($reduce_bool): \frame_length_gold -> \frame_length +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:439$2351_gold ($ne): \frame_length_gold -> \frame_length +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:448$2371_gold ($ne): \frame_payload_gold [23:16] -> \frame_payload [23:16] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:471$2433_gold ($ne): \frame_length_gold -> \frame_length +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:475$2446_gold ($ne): \frame_payload_gold [31:0] -> \frame_payload [31:0] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:475$2446_gold ($ne): \staged_txn_id_gold -> \staged_txn_id +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:476$2447_gold ($ne): \frame_payload_gold [63:32] -> \frame_payload [63:32] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:476$2447_gold ($ne): \staged_result_crc_gold -> \staged_result_crc +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:499$2456_gold ($ne): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:500$2457_gold ($ne): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:501$2459_gold ($ne): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:502$2461_gold ($ne): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:503$2463_gold ($ne): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:504$2465_gold ($ne): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:505$2467_gold ($ne): \frame_opcode_gold -> \frame_opcode +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:507$2523_gold ($ne): \frame_length_gold -> \frame_length +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:508$2526_gold ($ne): \frame_length_gold -> \frame_length +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:509$2530_gold ($ne): \frame_length_gold -> \frame_length +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:512$2538_gold ($ne): \frame_length_gold -> \frame_length +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:513$2542_gold ($ne): \frame_length_gold -> \frame_length +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:520$2648_gold ($reduce_bool): \frame_payload_gold [111:104] -> \frame_payload [111:104] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:581$2924_gold ($ne): \frame_payload_gold [103:96] -> \frame_payload [103:96] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:581$2924_gold ($ne): \active_profile_gold -> \active_profile +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:583$2925_gold ($ne): \frame_payload_gold [63:32] -> \frame_payload [63:32] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:583$2925_gold ($ne): \committed_pc_gold -> \committed_pc +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:583$2926_gold ($ne): \frame_payload_gold [95:64] -> \frame_payload [95:64] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:583$2926_gold ($ne): \committed_fp_gold -> \committed_fp +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:598$2941_gold ($ne): \frame_payload_gold [407:280] -> \frame_payload [407:280] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:598$2941_gold ($ne): \frame_payload_gold [271:144] -> \frame_payload [271:144] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:636$2986_gold ($ne): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:636$2986_gold ($ne): \frame_payload_gold [383:376] -> \frame_payload [383:376] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:636$2987_gold ($ne): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:636$2987_gold ($ne): \frame_payload_gold [511:384] -> \frame_payload [511:384] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:637$2991_gold ($ne): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:637$2991_gold ($ne): \frame_payload_gold [519:512] -> \frame_payload [519:512] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:637$2992_gold ($ne): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:637$2992_gold ($ne): \frame_payload_gold [647:520] -> \frame_payload [647:520] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:638$2997_gold ($ne): \frame_payload_gold [383:376] -> \frame_payload [383:376] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:638$2997_gold ($ne): \frame_payload_gold [519:512] -> \frame_payload [519:512] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:638$2998_gold ($ne): \frame_payload_gold [511:384] -> \frame_payload [511:384] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:638$2998_gold ($ne): \frame_payload_gold [647:520] -> \frame_payload [647:520] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:672$3039_gold ($ne): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:672$3039_gold ($ne): \frame_payload_gold [351:344] -> \frame_payload [351:344] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:672$3040_gold ($ne): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:672$3040_gold ($ne): \frame_payload_gold [479:352] -> \frame_payload [479:352] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:673$3044_gold ($ne): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:673$3044_gold ($ne): \frame_payload_gold [487:480] -> \frame_payload [487:480] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:673$3045_gold ($ne): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:673$3045_gold ($ne): \frame_payload_gold [615:488] -> \frame_payload [615:488] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:674$3050_gold ($ne): \frame_payload_gold [351:344] -> \frame_payload [351:344] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:674$3050_gold ($ne): \frame_payload_gold [487:480] -> \frame_payload [487:480] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:674$3051_gold ($ne): \frame_payload_gold [479:352] -> \frame_payload [479:352] +Changing input B of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:674$3051_gold ($ne): \frame_payload_gold [615:488] -> \frame_payload [615:488] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3056_gold ($reduce_bool): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:679$3057_gold ($ne): \frame_payload_gold [623:616] -> \frame_payload [623:616] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:699$3065_gold ($reduce_bool): \frame_payload_gold [655:624] -> \frame_payload [655:624] +Changing input A of cell $ne$asic_core/rtl/lsc1_packet_frontend.sv:699$3066_gold ($reduce_bool): \frame_payload_gold [687:656] -> \frame_payload [687:656] +Changing input S of cell $procmux$102399_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$102441_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$102567_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$102609_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$103113_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$103197_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$103239_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$103869_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input A of cell $procmux$108267_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$108267_gold ($mux): \addr_a_gold -> \addr_a +Changing input A of cell $procmux$108315_gold ($mux): \addr_a_gold [31:24] -> \addr_a [31:24] +Changing input B of cell $procmux$108315_gold ($mux): \deferred_local_gold [7:0] -> \deferred_local [7:0] +Changing input B of cell $procmux$108363_gold ($mux): \deferred_target_gold [7:0] -> \deferred_target [7:0] +Changing input B of cell $procmux$108882_gold ($mux): \addr_a_gold -> \addr_a +Changing input B of cell $procmux$109152_gold ($mux): { \addr_c_gold \addr_b_gold } -> { \addr_c \addr_b } +Changing input A of cell $procmux$109197_gold ($mux): \n_writes_gold -> \n_writes +Changing input S of cell $procmux$109203_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input A of cell $procmux$109242_gold ($mux): \write_value_gold -> \write_value +Changing input B of cell $procmux$109242_gold ($mux): \alu_result_gold -> \alu_result +Changing input A of cell $procmux$109287_gold ($mux): \write_address_gold -> \write_address +Changing input B of cell $procmux$109287_gold ($mux): \addr_c_gold -> \addr_c +Changing input S of cell $procmux$110193_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input S of cell $procmux$110232_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input S of cell $procmux$110349_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input S of cell $procmux$11199_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$11238_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input B of cell $procmux$114560_gold ($mux): \alu_result_gold -> \alu_result +Changing input A of cell $procmux$121839_gold ($mux): \solved_a_gold -> \solved_a +Changing input B of cell $procmux$121839_gold ($mux): \alu_result_gold -> \alu_result +Changing input A of cell $procmux$121869_gold ($mux): \alu_result_gold -> \alu_result +Changing input B of cell $procmux$121869_gold ($mux): \solved_b_gold -> \solved_b +Changing input B of cell $procmux$121925_gold ($mux): \alu_result_gold -> \alu_result +Changing input S of cell $procmux$12408_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$12447_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$12504_gold ($mux): \result_pending_gold -> \result_pending +Changing input B of cell $procmux$125070_gold ($mux): \deferred_target_gold [7:0] -> \deferred_target [7:0] +Changing input A of cell $procmux$125103_gold ($mux): \addr_a_gold [23:0] -> \addr_a [23:0] +Changing input B of cell $procmux$125103_gold ($mux): \deferred_target_gold [31:8] -> \deferred_target [31:8] +Changing input B of cell $procmux$125136_gold ($mux): \addr_b_gold -> \addr_b +Changing input B of cell $procmux$125169_gold ($mux): \addr_a_gold -> \addr_a +Changing input B of cell $procmux$125235_gold ($mux): \deferred_local_gold [31:8] -> \deferred_local [31:8] +Changing input B of cell $procmux$125427_gold ($mux): \addr_a_gold -> \addr_a +Changing input S of cell $procmux$12543_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input B of cell $procmux$125487_gold ($mux): \write_value_gold -> \write_value +Changing input B of cell $procmux$125517_gold ($mux): \write_address_gold -> \write_address +Changing input B of cell $procmux$13084_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$13183_gold ($mux): \addr_b_gold -> \addr_b +Changing input B of cell $procmux$131856_gold ($mux): \write_value_gold -> \write_value +Changing input B of cell $procmux$131883_gold ($mux): \write_address_gold -> \write_address +Changing input B of cell $procmux$131910_gold ($mux): { \addr_c_gold \addr_b_gold } -> { \addr_c \addr_b } +Changing input A of cell $procmux$132177_gold ($mux): \proposed_fp_gold -> \proposed_fp +Changing input A of cell $procmux$132201_gold ($mux): \proposed_pc_gold -> \proposed_pc +Changing input S of cell $procmux$132396_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$132417_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input B of cell $procmux$13282_gold ($mux): \addr_a_gold -> \addr_a +Changing input S of cell $procmux$13491_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$13530_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input B of cell $procmux$13573_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$13669_gold ($mux): \addr_b_gold -> \addr_b +Changing input A of cell $procmux$136962_gold ($mux): \addr_b_gold [31:24] -> \addr_b [31:24] +Changing input A of cell $procmux$136986_gold ($mux): \addr_b_gold [23:0] -> \addr_b [23:0] +Changing input B of cell $procmux$136986_gold ($mux): \deferred_local_gold [31:8] -> \deferred_local [31:8] +Changing input B of cell $procmux$137034_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$137145_gold ($mux): \addr_a_gold -> \addr_a +Changing input B of cell $procmux$137271_gold ($mux): { \addr_c_gold \addr_b_gold } -> { \addr_c \addr_b } +Changing input A of cell $procmux$137292_gold ($mux): \write_value_gold -> \write_value +Changing input B of cell $procmux$137292_gold ($mux): \encoder_result_gold -> \encoder_result +Changing input A of cell $procmux$137313_gold ($mux): \write_address_gold -> \write_address +Changing input B of cell $procmux$137313_gold ($mux): \addr_b_gold -> \addr_b +Changing input A of cell $procmux$137334_gold ($mux): \n_writes_gold -> \n_writes +Changing input S of cell $procmux$137340_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input B of cell $procmux$13765_gold ($mux): \addr_a_gold -> \addr_a +Changing input S of cell $procmux$137697_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$137712_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$137757_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$139426_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$139426_gold ($mux): \addr_a_gold -> \addr_a +Changing input A of cell $procmux$139453_gold ($mux): \addr_a_gold [31:24] -> \addr_a [31:24] +Changing input B of cell $procmux$139507_gold ($mux): \addr_b_gold -> \addr_b +Changing input A of cell $procmux$139561_gold ($mux): \addr_b_gold [31:24] -> \addr_b [31:24] +Changing input A of cell $procmux$139588_gold ($mux): \addr_b_gold [23:0] -> \addr_b [23:0] +Changing input A of cell $procmux$139615_gold ($mux): \addr_a_gold [23:0] -> \addr_a [23:0] +Changing input B of cell $procmux$139642_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$139768_gold ($mux): \addr_a_gold -> \addr_a +Changing input B of cell $procmux$139912_gold ($mux): { \addr_c_gold \addr_b_gold } -> { \addr_c \addr_b } +Changing input A of cell $procmux$139936_gold ($mux): \deferred_local_gold -> \deferred_local +Changing input B of cell $procmux$139936_gold ($mux): \addr_c_gold -> \addr_c +Changing input A of cell $procmux$139966_gold ($mux): \deferred_target_gold -> \deferred_target +Changing input B of cell $procmux$139966_gold ($mux): \addr_b_gold -> \addr_b +Changing input A of cell $procmux$139996_gold ($mux): \n_deferred_gold -> \n_deferred +Changing input A of cell $procmux$140026_gold ($mux): \write_value_gold -> \write_value +Changing input B of cell $procmux$140026_gold ($mux): \val_c_gold -> \val_c +Changing input A of cell $procmux$140053_gold ($mux): \write_address_gold -> \write_address +Changing input B of cell $procmux$140053_gold ($mux): \addr_b_gold -> \addr_b +Changing input A of cell $procmux$140080_gold ($mux): \n_writes_gold -> \n_writes +Changing input B of cell $procmux$140107_gold ($mux): \deferred_local_gold -> \deferred_local +Changing input B of cell $procmux$140134_gold ($mux): \deferred_target_gold -> \deferred_target +Changing input B of cell $procmux$140161_gold ($mux): \n_deferred_gold -> \n_deferred +Changing input B of cell $procmux$140188_gold ($mux): \val_b_gold -> \val_b +Changing input B of cell $procmux$140212_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$140260_gold ($mux): \deferred_local_gold -> \deferred_local +Changing input B of cell $procmux$140284_gold ($mux): \deferred_target_gold -> \deferred_target +Changing input B of cell $procmux$140308_gold ($mux): \n_deferred_gold -> \n_deferred +Changing input B of cell $procmux$14139_gold ($mux): \frame_payload_gold [479:352] -> \frame_payload [479:352] +Changing input B of cell $procmux$14232_gold ($mux): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input A of cell $procmux$14325_gold ($mux): \addr_c_gold -> \addr_c +Changing input S of cell $procmux$143445_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$143484_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$143517_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$143598_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$143637_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$143687_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$143744_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$143790_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$14418_gold ($mux): \addr_b_gold -> \addr_b +Changing input S of cell $procmux$144239_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$144273_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$144288_gold ($mux): \result_pending_gold -> \result_pending +Changing input B of cell $procmux$144305_gold ($mux): \rx_fault_status_gold -> \rx_fault_status +Changing input S of cell $procmux$144305_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$144314_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input A of cell $procmux$144323_gold ($mux): \last_fault_gold -> \last_fault +Changing input S of cell $procmux$144347_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$144356_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$144365_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$144398_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$144432_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$144447_gold ($mux): \result_pending_gold -> \result_pending +Changing input B of cell $procmux$144464_gold ($mux): \rx_fault_status_gold -> \rx_fault_status +Changing input S of cell $procmux$144464_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$144473_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input A of cell $procmux$144482_gold ($mux): \last_status_gold -> \last_status +Changing input S of cell $procmux$144506_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$144524_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$144852_gold ($mux): \staged_result_crc_gold -> \staged_result_crc +Changing input B of cell $procmux$144852_gold ($mux): \tx_payload_crc_gold -> \tx_payload_crc +Changing input S of cell $procmux$144862_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$144901_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$144910_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input S of cell $procmux$144937_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$144949_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input B of cell $procmux$144976_gold ($mux): \frame_payload_gold [95:64] -> \frame_payload [95:64] +Changing input S of cell $procmux$144982_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$145021_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input A of cell $procmux$145027_gold ($mux): \next_fp_value_gold -> \next_fp_value +Changing input S of cell $procmux$145030_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input A of cell $procmux$145045_gold ($mux): \next_fp_value_gold -> \next_fp_value +Changing input A of cell $procmux$145066_gold ($mux): \next_fp_value_gold -> \next_fp_value +Changing input S of cell $procmux$145069_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$145076_gold ($mux): \next_fp_value_gold -> \next_fp_value +Changing input S of cell $procmux$145102_gold ($mux): \result_pending_gold -> \result_pending +Changing input A of cell $procmux$14511_gold ($mux): \addr_a_gold -> \addr_a +Changing input S of cell $procmux$145141_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input A of cell $procmux$145147_gold ($mux): \next_pc_value_gold -> \next_pc_value +Changing input S of cell $procmux$145150_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input A of cell $procmux$145165_gold ($mux): \next_pc_value_gold -> \next_pc_value +Changing input A of cell $procmux$145186_gold ($mux): \next_pc_value_gold -> \next_pc_value +Changing input S of cell $procmux$145189_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$145196_gold ($mux): \next_pc_value_gold -> \next_pc_value +Changing input B of cell $procmux$145216_gold ($mux): \frame_payload_gold [31:0] -> \frame_payload [31:0] +Changing input S of cell $procmux$145222_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$145261_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input A of cell $procmux$145267_gold ($mux): \txn_id_gold -> \txn_id +Changing input S of cell $procmux$145270_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input A of cell $procmux$145285_gold ($mux): \txn_id_gold -> \txn_id +Changing input A of cell $procmux$145294_gold ($mux): \txn_id_gold -> \txn_id +Changing input S of cell $procmux$145297_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$145306_gold ($mux): \txn_id_gold -> \txn_id +Changing input S of cell $procmux$145309_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$145316_gold ($mux): \txn_id_gold -> \txn_id +Changing input S of cell $procmux$145342_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$145389_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$145398_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input S of cell $procmux$145425_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$145437_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$145465_gold ($mux): \frame_payload_gold [359:344] -> \frame_payload [359:344] +Changing input S of cell $procmux$145482_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$145521_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input A of cell $procmux$145542_gold ($mux): \proposed_pc_gold [15:0] -> \proposed_pc [15:0] +Changing input A of cell $procmux$145551_gold ($mux): \proposed_fp_gold [15:0] -> \proposed_fp [15:0] +Changing input S of cell $procmux$145554_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input B of cell $procmux$145591_gold ($mux): \frame_payload_gold [479:352] -> \frame_payload [479:352] +Changing input B of cell $procmux$145594_gold ($mux): \frame_payload_gold [479:352] -> \frame_payload [479:352] +Changing input A of cell $procmux$145601_gold ($mux): \frame_payload_gold [823:696] -> \frame_payload [823:696] +Changing input S of cell $procmux$145635_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$145674_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input A of cell $procmux$145686_gold ($mux): \inv_value_gold -> \inv_value +Changing input B of cell $procmux$145727_gold ($mux): \frame_payload_gold [615:488] -> \frame_payload [615:488] +Changing input B of cell $procmux$145732_gold ($mux): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input B of cell $procmux$145735_gold ($mux): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input A of cell $procmux$145742_gold ($mux): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input S of cell $procmux$145776_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$145815_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input B of cell $procmux$145823_gold ($mux): \alu_result_gold -> \alu_result +Changing input A of cell $procmux$145827_gold ($mux): \val_c_gold -> \val_c +Changing input S of cell $procmux$145917_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$145956_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$146070_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$146109_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$146151_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$146173_gold ($mux): \capture_result_crc_gold -> \capture_result_crc +Changing input S of cell $procmux$146183_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$146222_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$146231_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input S of cell $procmux$146258_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$146270_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$146297_gold ($mux): { 504'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $28\decision_detail[7:0]_gold \frame_payload_gold [31:0] } -> { 504'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $28\decision_detail[7:0]_gold \frame_payload [31:0] } +Changing input B of cell $procmux$146297_gold ($mux): { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $65\result_bytes[375:104]_gold [271:168] 8'00000000 $65\result_bytes[375:104]_gold [159:0] $40\n_writes[31:0]_gold [7:0] \frame_payload_gold [95:64] $add$asic_core/rtl/lsc1_packet_frontend.sv:578$2923_Y_gold \frame_payload_gold [31:0] } -> { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $65\result_bytes[375:104]_gold [271:168] 8'00000000 $65\result_bytes[375:104]_gold [159:0] $40\n_writes[31:0]_gold [7:0] \frame_payload [95:64] $add$asic_core/rtl/lsc1_packet_frontend.sv:578$2923_Y_gold \frame_payload [31:0] } +Changing input B of cell $procmux$146303_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \frame_payload_gold [31:0] } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \frame_payload [31:0] } +Changing input S of cell $procmux$146303_gold ($mux): \result_pending_gold -> \result_pending +Changing input B of cell $procmux$146327_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \frame_payload_gold [31:0] } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \frame_payload [31:0] } +Changing input A of cell $procmux$146334_gold ($mux): { 416'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \staged_next_fp_gold \staged_next_pc_gold $add$asic_core/rtl/lsc1_packet_frontend.sv:484$2454_Y_gold \frame_payload_gold [31:0] } -> { 416'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \staged_next_fp \staged_next_pc $add$asic_core/rtl/lsc1_packet_frontend.sv:484$2454_Y_gold \frame_payload [31:0] } +Changing input B of cell $procmux$146334_gold ($mux): { 504'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $ternary$asic_core/rtl/lsc1_packet_frontend.sv:479$2453_Y_gold [7:0] \frame_payload_gold [31:0] } -> { 504'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $ternary$asic_core/rtl/lsc1_packet_frontend.sv:479$2453_Y_gold [7:0] \frame_payload [31:0] } +Changing input A of cell $procmux$146337_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \frame_payload_gold [31:0] } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \frame_payload [31:0] } +Changing input S of cell $procmux$146337_gold ($mux): \result_pending_gold -> \result_pending +Changing input A of cell $procmux$146346_gold ($mux): { 528'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000101001101000011001100010000000000000000000000000000001000000000000100000000000100000000 \frame_payload_gold [23:16] 8'00000001 } -> { 528'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000101001101000011001100010000000000000000000000000000001000000000000100000000000100000000 \frame_payload [23:16] 8'00000001 } +Changing input S of cell $procmux$146352_gold ($mux): \result_pending_gold -> \result_pending +Changing input A of cell $procmux$146364_gold ($mux): { 391'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \state_valid_gold \committed_fp_gold \committed_pc_gold \last_fault_gold \retire_seq_gold \last_status_gold $ternary$asic_core/rtl/lsc1_packet_frontend.sv:424$2285_Y_gold $ternary$asic_core/rtl/lsc1_packet_frontend.sv:423$2284_Y_gold } -> { 391'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \state_valid \committed_fp \committed_pc \last_fault \retire_seq \last_status $ternary$asic_core/rtl/lsc1_packet_frontend.sv:424$2285_Y_gold $ternary$asic_core/rtl/lsc1_packet_frontend.sv:423$2284_Y_gold } +Changing input S of cell $procmux$146369_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input A of cell $procmux$146375_gold ($mux): { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $38\result_bytes[375:104]_gold $24\n_writes[31:0]_gold [7:0] \next_fp_value_gold \next_pc_value_gold \txn_id_gold } -> { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $38\result_bytes[375:104]_gold $24\n_writes[31:0]_gold [7:0] \next_fp_value \next_pc_value \txn_id } +Changing input B of cell $procmux$146375_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $procmux$146378_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input S of cell $procmux$146378_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input B of cell $procmux$146387_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \txn_id } +Changing input A of cell $procmux$146396_gold ($mux): { 232'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $23\result_bytes[375:104]_gold [207:176] $30\result_bytes[311:104]_gold [175:168] $23\result_bytes[375:104]_gold [167:160] $30\result_bytes[311:104]_gold [159:0] \n_writes_gold [7:0] \next_fp_value_gold \next_pc_value_gold \txn_id_gold } -> { 232'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $23\result_bytes[375:104]_gold [207:176] $30\result_bytes[311:104]_gold [175:168] $23\result_bytes[375:104]_gold [167:160] $30\result_bytes[311:104]_gold [159:0] \n_writes [7:0] \next_fp_value \next_pc_value \txn_id } +Changing input B of cell $procmux$146396_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input B of cell $procmux$146402_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input A of cell $procmux$146408_gold ($mux): { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $23\result_bytes[375:104]_gold \n_writes_gold [7:0] \proposed_fp_gold \proposed_pc_gold \txn_id_gold } -> { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $23\result_bytes[375:104]_gold \n_writes [7:0] \proposed_fp \proposed_pc \txn_id } +Changing input B of cell $procmux$146408_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $procmux$146411_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input S of cell $procmux$146411_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input B of cell $procmux$146417_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $procmux$146420_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input S of cell $procmux$146420_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$146426_gold ($mux): { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $15\result_bytes[375:104]_gold $13\n_writes[31:0]_gold [7:0] \next_fp_value_gold \next_pc_value_gold \txn_id_gold } -> { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $15\result_bytes[375:104]_gold $13\n_writes[31:0]_gold [7:0] \next_fp_value \next_pc_value \txn_id } +Changing input B of cell $procmux$146426_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $procmux$146429_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 \txn_id } +Changing input S of cell $procmux$146429_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$146436_gold ($mux): { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $8\result_bytes[375:104]_gold $8\n_writes[31:0]_gold [7:0] \next_fp_value_gold \next_pc_value_gold \txn_id_gold } -> { 168'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $8\result_bytes[375:104]_gold $8\n_writes[31:0]_gold [7:0] \next_fp_value \next_pc_value \txn_id } +Changing input B of cell $procmux$146436_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $procmux$146439_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input B of cell $procmux$146444_gold ($mux): { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id_gold } -> { 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \txn_id } +Changing input S of cell $procmux$146462_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$146496_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$146511_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$146528_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$146537_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input A of cell $procmux$146546_gold ($mux): \tx_length_gold -> \tx_length +Changing input S of cell $procmux$146570_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$146579_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$146588_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input A of cell $procmux$146705_gold ($mux): \tx_status_gold -> \tx_status +Changing input S of cell $procmux$146780_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$146814_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$146829_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$146846_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$146855_gold ($mux): \alu_fault_gold -> \alu_fault +Changing input A of cell $procmux$146864_gold ($mux): \fault_gold -> \fault +Changing input S of cell $procmux$146888_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$146897_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input S of cell $procmux$146906_gold ($mux): \encoder_fault_gold -> \encoder_fault +Changing input B of cell $procmux$14790_gold ($mux): \frame_payload_gold [615:488] -> \frame_payload [615:488] +Changing input B of cell $procmux$14883_gold ($mux): \frame_payload_gold [487:480] -> \frame_payload [487:480] +Changing input B of cell $procmux$15069_gold ($mux): \frame_payload_gold [351:344] -> \frame_payload [351:344] +Changing input B of cell $procmux$15255_gold ($mux): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input B of cell $procmux$19018_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$19114_gold ($mux): \addr_b_gold -> \addr_b +Changing input B of cell $procmux$19210_gold ($mux): \addr_a_gold -> \addr_a +Changing input B of cell $procmux$19678_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$19771_gold ($mux): \addr_b_gold -> \addr_b +Changing input B of cell $procmux$19864_gold ($mux): \addr_a_gold -> \addr_a +Changing input B of cell $procmux$20586_gold ($mux): \frame_payload_gold [823:696] -> \frame_payload [823:696] +Changing input B of cell $procmux$21036_gold ($mux): \frame_payload_gold [615:488] -> \frame_payload [615:488] +Changing input B of cell $procmux$21126_gold ($mux): \frame_payload_gold [487:480] -> \frame_payload [487:480] +Changing input B of cell $procmux$21216_gold ($mux): \frame_payload_gold [479:352] -> \frame_payload [479:352] +Changing input B of cell $procmux$21306_gold ($mux): \frame_payload_gold [351:344] -> \frame_payload [351:344] +Changing input B of cell $procmux$21396_gold ($mux): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input B of cell $procmux$21486_gold ($mux): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input B of cell $procmux$22612_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$22708_gold ($mux): \addr_b_gold -> \addr_b +Changing input B of cell $procmux$22804_gold ($mux): \addr_a_gold -> \addr_a +Changing input B of cell $procmux$23179_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$23272_gold ($mux): \addr_b_gold -> \addr_b +Changing input B of cell $procmux$23365_gold ($mux): \addr_a_gold -> \addr_a +Changing input B of cell $procmux$23728_gold ($mux): \addr_c_gold -> \addr_c +Changing input B of cell $procmux$23818_gold ($mux): \addr_b_gold -> \addr_b +Changing input B of cell $procmux$23908_gold ($mux): \addr_a_gold -> \addr_a +Changing input B of cell $procmux$24519_gold ($mux): \frame_payload_gold [647:520] -> \frame_payload [647:520] +Changing input B of cell $procmux$24606_gold ($mux): \frame_payload_gold [519:512] -> \frame_payload [519:512] +Changing input B of cell $procmux$24693_gold ($mux): \frame_payload_gold [511:384] -> \frame_payload [511:384] +Changing input B of cell $procmux$24780_gold ($mux): \frame_payload_gold [383:376] -> \frame_payload [383:376] +Changing input B of cell $procmux$24954_gold ($mux): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input B of cell $procmux$25041_gold ($mux): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input B of cell $procmux$26182_gold ($mux): \frame_payload_gold [271:144] -> \frame_payload [271:144] +Changing input S of cell $procmux$28344_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$28383_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$28680_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$28719_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input B of cell $procmux$28761_gold ($mux): \frame_payload_gold [407:280] -> \frame_payload [407:280] +Changing input B of cell $procmux$28845_gold ($mux): \frame_payload_gold [279:272] -> \frame_payload [279:272] +Changing input A of cell $procmux$28929_gold ($mux): \result_value_gold -> \result_value +Changing input B of cell $procmux$28929_gold ($mux): \frame_payload_gold [271:144] -> \frame_payload [271:144] +Changing input S of cell $procmux$30882_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$30921_gold ($mux): \rx_fault_valid_gold -> \rx_fault_valid +Changing input S of cell $procmux$32016_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$32097_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$32259_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$32340_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$33312_gold ($mux): \result_pending_gold -> \result_pending +Changing input A of cell $procmux$33474_gold ($mux): \frame_payload_gold [95:64] -> \frame_payload [95:64] +Changing input S of cell $procmux$33474_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$33555_gold ($mux): \result_pending_gold -> \result_pending +Changing input A of cell $procmux$34527_gold ($mux): \frame_payload_gold [31:0] -> \frame_payload [31:0] +Changing input S of cell $procmux$34527_gold ($mux): \result_pending_gold -> \result_pending +Changing input S of cell $procmux$34770_gold ($mux): \result_pending_gold -> \result_pending +Changing input B of cell $procmux$82185_gold ($mux): \frame_payload_gold [31:0] -> \frame_payload [31:0] +Changing input A of cell $reduce_bool$asic_core/rtl/lsc1_packet_frontend.sv:0$3058_gold ($reduce_bool): \frame_payload_gold [623:616] -> \frame_payload [623:616] +Changing input A of cell $reduce_bool$asic_core/rtl/lsc1_packet_frontend.sv:404$1988_gold ($reduce_bool): \pres_a_gold -> \pres_a +Changing input A of cell $reduce_bool$asic_core/rtl/lsc1_packet_frontend.sv:737$3129_gold ($reduce_bool): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input B of cell $sub$asic_core/rtl/lsc1_packet_frontend.sv:594$2934_gold ($sub): \frame_payload_gold [95:64] -> \frame_payload [95:64] +Changing input B of cell $sub$asic_core/rtl/lsc1_packet_frontend.sv:623$2957_gold ($sub): \frame_payload_gold [375:344] -> \frame_payload [375:344] +Changing input A of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:261$1284_gold ($mux): \fp_gold [15:0] -> \fp [15:0] +Changing input A of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:377$1828_gold ($mux): \addr_b_gold -> \addr_b +Changing input B of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:377$1828_gold ($mux): \addr_a_gold -> \addr_a +Changing input A of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:404$1989_gold ($mux): \val_b_gold -> \val_b +Changing input B of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:404$1989_gold ($mux): \val_a_gold -> \val_a +Changing input S of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:423$2284_gold ($mux): \result_pending_gold -> \result_pending +Changing input B of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:424$2285_gold ($mux): \staged_txn_id_gold -> \staged_txn_id +Changing input S of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:424$2285_gold ($mux): \result_pending_gold -> \result_pending +Changing input B of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:714$3070_gold ($mux): { 24'000000000000000000000000 \frame_payload_gold [623:616] } -> { 24'000000000000000000000000 \frame_payload [623:616] } +Changing input B of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:715$3073_gold ($mux): \frame_payload_gold [751:624] -> \frame_payload [751:624] +Changing input A of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:737$3130_gold ($mux): \frame_payload_gold [479:352] -> \frame_payload [479:352] +Changing input B of cell $ternary$asic_core/rtl/lsc1_packet_frontend.sv:737$3130_gold ($mux): \frame_payload_gold [343:216] -> \frame_payload [343:216] +Changing input A of cell $xor$asic_core/rtl/lsc1_packet_frontend.sv:733$3126_gold ($xor): \frame_payload_gold [215:208] -> \frame_payload [215:208] +Changing input B of cell $xor$asic_core/rtl/lsc1_packet_frontend.sv:733$3126_gold ($xor): \frame_payload_gold [351:344] -> \frame_payload [351:344] +Changing input operand_a of cell adapter_gold (lsc1_stream_adapter): \alu_operand_a_gold -> \alu_operand_a +Changing input operand_b of cell adapter_gold (lsc1_stream_adapter): \alu_operand_b_gold -> \alu_operand_b +Changing input operation of cell adapter_gold (lsc1_stream_adapter): \alu_operation_gold -> \alu_operation +Changing input start of cell adapter_gold (lsc1_stream_adapter): \alu_start_gold -> \alu_start +Changing input index of cell field_encoder_gold (lsc1_field_encoder): \encoder_index_gold -> \encoder_index +Changing input start of cell field_encoder_gold (lsc1_field_encoder): \encoder_start_gold -> \encoder_start +Changing input frame_ready of cell receiver_gold (lsc1_packet_rx): \event_ready_gold -> \event_ready +Changing input payload of cell transmitter_gold (lsc1_packet_tx): \tx_payload_gold -> \tx_payload +Changing input payload_length of cell transmitter_gold (lsc1_packet_tx): \tx_length_gold -> \tx_length +Changing input start of cell transmitter_gold (lsc1_packet_tx): \tx_start_gold -> \tx_start +Changing input status of cell transmitter_gold (lsc1_packet_tx): \tx_status_gold -> \tx_status +Changing input A of cell $add$asic_core/rtl/lsc1_packet_frontend.sv:262$1283_gold ($add): \pc_gold [15:0] -> \pc [15:0] +Setting undriven nets to undef: \receiver.received_crc_gate [31:24] + +14. Executing HIERARCHY pass (managing design hierarchy). + +14.1. Analyzing design hierarchy.. +Top module: \equiv +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: \gf2n_mul_bitstream +Used module: \lsc1_field_encoder +Used module: \lsc1_packet_rx +Used module: \lsc1_packet_tx +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 + +14.2. Executing AST frontend in derive mode using pre-parsed AST for module `\gf2n_mul_bitstream'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 +Generating RTLIL representation for module `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream'. + +14.3. Analyzing design hierarchy.. +Top module: \equiv +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_field_encoder +Used module: \lsc1_packet_rx +Used module: \lsc1_packet_tx + +14.4. Analyzing design hierarchy.. +Top module: \equiv +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_field_encoder +Used module: \lsc1_packet_rx +Used module: \lsc1_packet_tx +Removing unused module `\gate'. +Removing unused module `\gf2n_mul_bitstream'. +Removing unused module `\gold'. +Removed 3 unused modules. + +15. Executing EQUIV_SIMPLE pass. +Found 5039 unproven $equiv cells (80 groups) in equiv: + Trying to prove $equiv for \rx_ready: failed. + Trying to prove $equiv for \frame_valid: failed. + Grouping SAT models for \frame_opcode: + Trying to prove $equiv for \frame_opcode [0]: failed. + Trying to prove $equiv for \frame_opcode [1]: failed. + Trying to prove $equiv for \frame_opcode [2]: failed. + Trying to prove $equiv for \frame_opcode [3]: failed. + Trying to prove $equiv for \frame_opcode [4]: failed. + Trying to prove $equiv for \frame_opcode [5]: failed. + Trying to prove $equiv for \frame_opcode [6]: failed. + Trying to prove $equiv for \frame_opcode [7]: failed. + Grouping SAT models for \frame_length: + Trying to prove $equiv for \frame_length [0]: failed. + Trying to prove $equiv for \frame_length [1]: failed. + Trying to prove $equiv for \frame_length [2]: failed. + Trying to prove $equiv for \frame_length [3]: failed. + Trying to prove $equiv for \frame_length [4]: failed. + Trying to prove $equiv for \frame_length [5]: failed. + Trying to prove $equiv for \frame_length [6]: failed. + Trying to prove $equiv for \frame_length [7]: failed. + Trying to prove $equiv for \frame_length [8]: failed. + Trying to prove $equiv for \frame_length [9]: failed. + Trying to prove $equiv for \frame_length [10]: failed. + Trying to prove $equiv for \frame_length [11]: failed. + Trying to prove $equiv for \frame_length [12]: failed. + Trying to prove $equiv for \frame_length [13]: failed. + Trying to prove $equiv for \frame_length [14]: failed. + Trying to prove $equiv for \frame_length [15]: failed. + Grouping SAT models for \frame_payload: + Trying to prove $equiv for \frame_payload [0]: failed. + Trying to prove $equiv for \frame_payload [1]: failed. + Trying to prove $equiv for \frame_payload [2]: failed. + Trying to prove $equiv for \frame_payload [3]: failed. + Trying to prove $equiv for \frame_payload [4]: failed. + Trying to prove $equiv for \frame_payload [5]: failed. + Trying to prove $equiv for \frame_payload [6]: failed. + Trying to prove $equiv for \frame_payload [7]: failed. + Trying to prove $equiv for \frame_payload [8]: failed. + Trying to prove $equiv for \frame_payload [9]: failed. + Trying to prove $equiv for \frame_payload [10]: failed. + Trying to prove $equiv for \frame_payload [11]: failed. + Trying to prove $equiv for \frame_payload [12]: failed. + Trying to prove $equiv for \frame_payload [13]: failed. + Trying to prove $equiv for \frame_payload [14]: failed. + Trying to prove $equiv for \frame_payload [15]: failed. + Trying to prove $equiv for \frame_payload [16]: failed. + Trying to prove $equiv for \frame_payload [17]: failed. + Trying to prove $equiv for \frame_payload [18]: failed. + Trying to prove $equiv for \frame_payload [19]: failed. + Trying to prove $equiv for \frame_payload [20]: failed. + Trying to prove $equiv for \frame_payload [21]: failed. + Trying to prove $equiv for \frame_payload [22]: failed. + Trying to prove $equiv for \frame_payload [23]: failed. + Trying to prove $equiv for \frame_payload [24]: failed. + Trying to prove $equiv for \frame_payload [25]: failed. + Trying to prove $equiv for \frame_payload [26]: failed. + Trying to prove $equiv for \frame_payload [27]: failed. + Trying to prove $equiv for \frame_payload [28]: failed. + Trying to prove $equiv for \frame_payload [29]: failed. + Trying to prove $equiv for \frame_payload [30]: failed. + Trying to prove $equiv for \frame_payload [31]: failed. + Trying to prove $equiv for \frame_payload [32]: failed. + Trying to prove $equiv for \frame_payload [33]: failed. + Trying to prove $equiv for \frame_payload [34]: failed. + Trying to prove $equiv for \frame_payload [35]: failed. + Trying to prove $equiv for \frame_payload [36]: failed. + Trying to prove $equiv for \frame_payload [37]: failed. + Trying to prove $equiv for \frame_payload [38]: failed. + Trying to prove $equiv for \frame_payload [39]: failed. + Trying to prove $equiv for \frame_payload [40]: failed. + Trying to prove $equiv for \frame_payload [41]: failed. + Trying to prove $equiv for \frame_payload [42]: failed. + Trying to prove $equiv for \frame_payload [43]: failed. + Trying to prove $equiv for \frame_payload [44]: failed. + Trying to prove $equiv for \frame_payload [45]: failed. + Trying to prove $equiv for \frame_payload [46]: failed. + Trying to prove $equiv for \frame_payload [47]: failed. + Trying to prove $equiv for \frame_payload [48]: failed. + Trying to prove $equiv for \frame_payload [49]: failed. + Trying to prove $equiv for \frame_payload [50]: failed. + Trying to prove $equiv for \frame_payload [51]: failed. + Trying to prove $equiv for \frame_payload [52]: failed. + Trying to prove $equiv for \frame_payload [53]: failed. + Trying to prove $equiv for \frame_payload [54]: failed. + Trying to prove $equiv for \frame_payload [55]: failed. + Trying to prove $equiv for \frame_payload [56]: failed. + Trying to prove $equiv for \frame_payload [57]: failed. + Trying to prove $equiv for \frame_payload [58]: failed. + Trying to prove $equiv for \frame_payload [59]: failed. + Trying to prove $equiv for \frame_payload [60]: failed. + Trying to prove $equiv for \frame_payload [61]: failed. + Trying to prove $equiv for \frame_payload [62]: failed. + Trying to prove $equiv for \frame_payload [63]: failed. + Trying to prove $equiv for \frame_payload [64]: failed. + Trying to prove $equiv for \frame_payload [65]: failed. + Trying to prove $equiv for \frame_payload [66]: failed. + Trying to prove $equiv for \frame_payload [67]: failed. + Trying to prove $equiv for \frame_payload [68]: failed. + Trying to prove $equiv for \frame_payload [69]: failed. + Trying to prove $equiv for \frame_payload [70]: failed. + Trying to prove $equiv for \frame_payload [71]: failed. + Trying to prove $equiv for \frame_payload [72]: failed. + Trying to prove $equiv for \frame_payload [73]: failed. + Trying to prove $equiv for \frame_payload [74]: failed. + Trying to prove $equiv for \frame_payload [75]: failed. + Trying to prove $equiv for \frame_payload [76]: failed. + Trying to prove $equiv for \frame_payload [77]: failed. + Trying to prove $equiv for \frame_payload [78]: failed. + Trying to prove $equiv for \frame_payload [79]: failed. + Trying to prove $equiv for \frame_payload [80]: failed. + Trying to prove $equiv for \frame_payload [81]: failed. + Trying to prove $equiv for \frame_payload [82]: failed. + Trying to prove $equiv for \frame_payload [83]: failed. + Trying to prove $equiv for \frame_payload [84]: failed. + Trying to prove $equiv for \frame_payload [85]: failed. + Trying to prove $equiv for \frame_payload [86]: failed. + Trying to prove $equiv for \frame_payload [87]: failed. + Trying to prove $equiv for \frame_payload [88]: failed. + Trying to prove $equiv for \frame_payload [89]: failed. + Trying to prove $equiv for \frame_payload [90]: failed. + Trying to prove $equiv for \frame_payload [91]: failed. + Trying to prove $equiv for \frame_payload [92]: failed. + Trying to prove $equiv for \frame_payload [93]: failed. + Trying to prove $equiv for \frame_payload [94]: failed. + Trying to prove $equiv for \frame_payload [95]: failed. + Trying to prove $equiv for \frame_payload [96]: failed. + Trying to prove $equiv for \frame_payload [97]: failed. + Trying to prove $equiv for \frame_payload [98]: failed. + Trying to prove $equiv for \frame_payload [99]: failed. + Trying to prove $equiv for \frame_payload [100]: failed. + Trying to prove $equiv for \frame_payload [101]: failed. + Trying to prove $equiv for \frame_payload [102]: failed. + Trying to prove $equiv for \frame_payload [103]: failed. + Trying to prove $equiv for \frame_payload [104]: failed. + Trying to prove $equiv for \frame_payload [105]: failed. + Trying to prove $equiv for \frame_payload [106]: failed. + Trying to prove $equiv for \frame_payload [107]: failed. + Trying to prove $equiv for \frame_payload [108]: failed. + Trying to prove $equiv for \frame_payload [109]: failed. + Trying to prove $equiv for \frame_payload [110]: failed. + Trying to prove $equiv for \frame_payload [111]: failed. + Trying to prove $equiv for \frame_payload [112]: failed. + Trying to prove $equiv for \frame_payload [113]: failed. + Trying to prove $equiv for \frame_payload [114]: failed. + Trying to prove $equiv for \frame_payload [115]: failed. + Trying to prove $equiv for \frame_payload [116]: failed. + Trying to prove $equiv for \frame_payload [117]: failed. + Trying to prove $equiv for \frame_payload [118]: failed. + Trying to prove $equiv for \frame_payload [119]: failed. + Trying to prove $equiv for \frame_payload [120]: failed. + Trying to prove $equiv for \frame_payload [121]: failed. + Trying to prove $equiv for \frame_payload [122]: failed. + Trying to prove $equiv for \frame_payload [123]: failed. + Trying to prove $equiv for \frame_payload [124]: failed. + Trying to prove $equiv for \frame_payload [125]: failed. + Trying to prove $equiv for \frame_payload [126]: failed. + Trying to prove $equiv for \frame_payload [127]: failed. + Trying to prove $equiv for \frame_payload [128]: failed. + Trying to prove $equiv for \frame_payload [129]: failed. + Trying to prove $equiv for \frame_payload [130]: failed. + Trying to prove $equiv for \frame_payload [131]: failed. + Trying to prove $equiv for \frame_payload [132]: failed. + Trying to prove $equiv for \frame_payload [133]: failed. + Trying to prove $equiv for \frame_payload [134]: failed. + Trying to prove $equiv for \frame_payload [135]: failed. + Trying to prove $equiv for \frame_payload [136]: failed. + Trying to prove $equiv for \frame_payload [137]: failed. + Trying to prove $equiv for \frame_payload [138]: failed. + Trying to prove $equiv for \frame_payload [139]: failed. + Trying to prove $equiv for \frame_payload [140]: failed. + Trying to prove $equiv for \frame_payload [141]: failed. + Trying to prove $equiv for \frame_payload [142]: failed. + Trying to prove $equiv for \frame_payload [143]: failed. + Trying to prove $equiv for \frame_payload [144]: failed. + Trying to prove $equiv for \frame_payload [145]: failed. + Trying to prove $equiv for \frame_payload [146]: failed. + Trying to prove $equiv for \frame_payload [147]: failed. + Trying to prove $equiv for \frame_payload [148]: failed. + Trying to prove $equiv for \frame_payload [149]: failed. + Trying to prove $equiv for \frame_payload [150]: failed. + Trying to prove $equiv for \frame_payload [151]: failed. + Trying to prove $equiv for \frame_payload [152]: failed. + Trying to prove $equiv for \frame_payload [153]: failed. + Trying to prove $equiv for \frame_payload [154]: failed. + Trying to prove $equiv for \frame_payload [155]: failed. + Trying to prove $equiv for \frame_payload [156]: failed. + Trying to prove $equiv for \frame_payload [157]: failed. + Trying to prove $equiv for \frame_payload [158]: failed. + Trying to prove $equiv for \frame_payload [159]: failed. + Trying to prove $equiv for \frame_payload [160]: failed. + Trying to prove $equiv for \frame_payload [161]: failed. + Trying to prove $equiv for \frame_payload [162]: failed. + Trying to prove $equiv for \frame_payload [163]: failed. + Trying to prove $equiv for \frame_payload [164]: failed. + Trying to prove $equiv for \frame_payload [165]: failed. + Trying to prove $equiv for \frame_payload [166]: failed. + Trying to prove $equiv for \frame_payload [167]: failed. + Trying to prove $equiv for \frame_payload [168]: failed. + Trying to prove $equiv for \frame_payload [169]: failed. + Trying to prove $equiv for \frame_payload [170]: failed. + Trying to prove $equiv for \frame_payload [171]: failed. + Trying to prove $equiv for \frame_payload [172]: failed. + Trying to prove $equiv for \frame_payload [173]: failed. + Trying to prove $equiv for \frame_payload [174]: failed. + Trying to prove $equiv for \frame_payload [175]: failed. + Trying to prove $equiv for \frame_payload [176]: failed. + Trying to prove $equiv for \frame_payload [177]: failed. + Trying to prove $equiv for \frame_payload [178]: failed. + Trying to prove $equiv for \frame_payload [179]: failed. + Trying to prove $equiv for \frame_payload [180]: failed. + Trying to prove $equiv for \frame_payload [181]: failed. + Trying to prove $equiv for \frame_payload [182]: failed. + Trying to prove $equiv for \frame_payload [183]: failed. + Trying to prove $equiv for \frame_payload [184]: failed. + Trying to prove $equiv for \frame_payload [185]: failed. + Trying to prove $equiv for \frame_payload [186]: failed. + Trying to prove $equiv for \frame_payload [187]: failed. + Trying to prove $equiv for \frame_payload [188]: failed. + Trying to prove $equiv for \frame_payload [189]: failed. + Trying to prove $equiv for \frame_payload [190]: failed. + Trying to prove $equiv for \frame_payload [191]: failed. + Trying to prove $equiv for \frame_payload [192]: failed. + Trying to prove $equiv for \frame_payload [193]: failed. + Trying to prove $equiv for \frame_payload [194]: failed. + Trying to prove $equiv for \frame_payload [195]: failed. + Trying to prove $equiv for \frame_payload [196]: failed. + Trying to prove $equiv for \frame_payload [197]: failed. + Trying to prove $equiv for \frame_payload [198]: failed. + Trying to prove $equiv for \frame_payload [199]: failed. + Trying to prove $equiv for \frame_payload [200]: failed. + Trying to prove $equiv for \frame_payload [201]: failed. + Trying to prove $equiv for \frame_payload [202]: failed. + Trying to prove $equiv for \frame_payload [203]: failed. + Trying to prove $equiv for \frame_payload [204]: failed. + Trying to prove $equiv for \frame_payload [205]: failed. + Trying to prove $equiv for \frame_payload [206]: failed. + Trying to prove $equiv for \frame_payload [207]: failed. + Trying to prove $equiv for \frame_payload [208]: failed. + Trying to prove $equiv for \frame_payload [209]: failed. + Trying to prove $equiv for \frame_payload [210]: failed. + Trying to prove $equiv for \frame_payload [211]: failed. + Trying to prove $equiv for \frame_payload [212]: failed. + Trying to prove $equiv for \frame_payload [213]: failed. + Trying to prove $equiv for \frame_payload [214]: failed. + Trying to prove $equiv for \frame_payload [215]: failed. + Trying to prove $equiv for \frame_payload [216]: failed. + Trying to prove $equiv for \frame_payload [217]: failed. + Trying to prove $equiv for \frame_payload [218]: failed. + Trying to prove $equiv for \frame_payload [219]: failed. + Trying to prove $equiv for \frame_payload [220]: failed. + Trying to prove $equiv for \frame_payload [221]: failed. + Trying to prove $equiv for \frame_payload [222]: failed. + Trying to prove $equiv for \frame_payload [223]: failed. + Trying to prove $equiv for \frame_payload [224]: failed. + Trying to prove $equiv for \frame_payload [225]: failed. + Trying to prove $equiv for \frame_payload [226]: failed. + Trying to prove $equiv for \frame_payload [227]: failed. + Trying to prove $equiv for \frame_payload [228]: failed. + Trying to prove $equiv for \frame_payload [229]: failed. + Trying to prove $equiv for \frame_payload [230]: failed. + Trying to prove $equiv for \frame_payload [231]: failed. + Trying to prove $equiv for \frame_payload [232]: failed. + Trying to prove $equiv for \frame_payload [233]: failed. + Trying to prove $equiv for \frame_payload [234]: failed. + Trying to prove $equiv for \frame_payload [235]: failed. + Trying to prove $equiv for \frame_payload [236]: failed. + Trying to prove $equiv for \frame_payload [237]: failed. + Trying to prove $equiv for \frame_payload [238]: failed. + Trying to prove $equiv for \frame_payload [239]: failed. + Trying to prove $equiv for \frame_payload [240]: failed. + Trying to prove $equiv for \frame_payload [241]: failed. + Trying to prove $equiv for \frame_payload [242]: failed. + Trying to prove $equiv for \frame_payload [243]: failed. + Trying to prove $equiv for \frame_payload [244]: failed. + Trying to prove $equiv for \frame_payload [245]: failed. + Trying to prove $equiv for \frame_payload [246]: failed. + Trying to prove $equiv for \frame_payload [247]: failed. + Trying to prove $equiv for \frame_payload [248]: failed. + Trying to prove $equiv for \frame_payload [249]: failed. + Trying to prove $equiv for \frame_payload [250]: failed. + Trying to prove $equiv for \frame_payload [251]: failed. + Trying to prove $equiv for \frame_payload [252]: failed. + Trying to prove $equiv for \frame_payload [253]: failed. + Trying to prove $equiv for \frame_payload [254]: failed. + Trying to prove $equiv for \frame_payload [255]: failed. + Trying to prove $equiv for \frame_payload [256]: failed. + Trying to prove $equiv for \frame_payload [257]: failed. + Trying to prove $equiv for \frame_payload [258]: failed. + Trying to prove $equiv for \frame_payload [259]: failed. + Trying to prove $equiv for \frame_payload [260]: failed. + Trying to prove $equiv for \frame_payload [261]: failed. + Trying to prove $equiv for \frame_payload [262]: failed. + Trying to prove $equiv for \frame_payload [263]: failed. + Trying to prove $equiv for \frame_payload [264]: failed. + Trying to prove $equiv for \frame_payload [265]: failed. + Trying to prove $equiv for \frame_payload [266]: failed. + Trying to prove $equiv for \frame_payload [267]: failed. + Trying to prove $equiv for \frame_payload [268]: failed. + Trying to prove $equiv for \frame_payload [269]: failed. + Trying to prove $equiv for \frame_payload [270]: failed. + Trying to prove $equiv for \frame_payload [271]: failed. + Trying to prove $equiv for \frame_payload [272]: failed. + Trying to prove $equiv for \frame_payload [273]: failed. + Trying to prove $equiv for \frame_payload [274]: failed. + Trying to prove $equiv for \frame_payload [275]: failed. + Trying to prove $equiv for \frame_payload [276]: failed. + Trying to prove $equiv for \frame_payload [277]: failed. + Trying to prove $equiv for \frame_payload [278]: failed. + Trying to prove $equiv for \frame_payload [279]: failed. + Trying to prove $equiv for \frame_payload [280]: failed. + Trying to prove $equiv for \frame_payload [281]: failed. + Trying to prove $equiv for \frame_payload [282]: failed. + Trying to prove $equiv for \frame_payload [283]: failed. + Trying to prove $equiv for \frame_payload [284]: failed. + Trying to prove $equiv for \frame_payload [285]: failed. + Trying to prove $equiv for \frame_payload [286]: failed. + Trying to prove $equiv for \frame_payload [287]: failed. + Trying to prove $equiv for \frame_payload [288]: failed. + Trying to prove $equiv for \frame_payload [289]: failed. + Trying to prove $equiv for \frame_payload [290]: failed. + Trying to prove $equiv for \frame_payload [291]: failed. + Trying to prove $equiv for \frame_payload [292]: failed. + Trying to prove $equiv for \frame_payload [293]: failed. + Trying to prove $equiv for \frame_payload [294]: failed. + Trying to prove $equiv for \frame_payload [295]: failed. + Trying to prove $equiv for \frame_payload [296]: failed. + Trying to prove $equiv for \frame_payload [297]: failed. + Trying to prove $equiv for \frame_payload [298]: failed. + Trying to prove $equiv for \frame_payload [299]: failed. + Trying to prove $equiv for \frame_payload [300]: failed. + Trying to prove $equiv for \frame_payload [301]: failed. + Trying to prove $equiv for \frame_payload [302]: failed. + Trying to prove $equiv for \frame_payload [303]: failed. + Trying to prove $equiv for \frame_payload [304]: failed. + Trying to prove $equiv for \frame_payload [305]: failed. + Trying to prove $equiv for \frame_payload [306]: failed. + Trying to prove $equiv for \frame_payload [307]: failed. + Trying to prove $equiv for \frame_payload [308]: failed. + Trying to prove $equiv for \frame_payload [309]: failed. + Trying to prove $equiv for \frame_payload [310]: failed. + Trying to prove $equiv for \frame_payload [311]: failed. + Trying to prove $equiv for \frame_payload [312]: failed. + Trying to prove $equiv for \frame_payload [313]: failed. + Trying to prove $equiv for \frame_payload [314]: failed. + Trying to prove $equiv for \frame_payload [315]: failed. + Trying to prove $equiv for \frame_payload [316]: failed. + Trying to prove $equiv for \frame_payload [317]: failed. + Trying to prove $equiv for \frame_payload [318]: failed. + Trying to prove $equiv for \frame_payload [319]: failed. + Trying to prove $equiv for \frame_payload [320]: failed. + Trying to prove $equiv for \frame_payload [321]: failed. + Trying to prove $equiv for \frame_payload [322]: failed. + Trying to prove $equiv for \frame_payload [323]: failed. + Trying to prove $equiv for \frame_payload [324]: failed. + Trying to prove $equiv for \frame_payload [325]: failed. + Trying to prove $equiv for \frame_payload [326]: failed. + Trying to prove $equiv for \frame_payload [327]: failed. + Trying to prove $equiv for \frame_payload [328]: failed. + Trying to prove $equiv for \frame_payload [329]: failed. + Trying to prove $equiv for \frame_payload [330]: failed. + Trying to prove $equiv for \frame_payload [331]: failed. + Trying to prove $equiv for \frame_payload [332]: failed. + Trying to prove $equiv for \frame_payload [333]: failed. + Trying to prove $equiv for \frame_payload [334]: failed. + Trying to prove $equiv for \frame_payload [335]: failed. + Trying to prove $equiv for \frame_payload [336]: failed. + Trying to prove $equiv for \frame_payload [337]: failed. + Trying to prove $equiv for \frame_payload [338]: failed. + Trying to prove $equiv for \frame_payload [339]: failed. + Trying to prove $equiv for \frame_payload [340]: failed. + Trying to prove $equiv for \frame_payload [341]: failed. + Trying to prove $equiv for \frame_payload [342]: failed. + Trying to prove $equiv for \frame_payload [343]: failed. + Trying to prove $equiv for \frame_payload [344]: failed. + Trying to prove $equiv for \frame_payload [345]: failed. + Trying to prove $equiv for \frame_payload [346]: failed. + Trying to prove $equiv for \frame_payload [347]: failed. + Trying to prove $equiv for \frame_payload [348]: failed. + Trying to prove $equiv for \frame_payload [349]: failed. + Trying to prove $equiv for \frame_payload [350]: failed. + Trying to prove $equiv for \frame_payload [351]: failed. + Trying to prove $equiv for \frame_payload [352]: failed. + Trying to prove $equiv for \frame_payload [353]: failed. + Trying to prove $equiv for \frame_payload [354]: failed. + Trying to prove $equiv for \frame_payload [355]: failed. + Trying to prove $equiv for \frame_payload [356]: failed. + Trying to prove $equiv for \frame_payload [357]: failed. + Trying to prove $equiv for \frame_payload [358]: failed. + Trying to prove $equiv for \frame_payload [359]: failed. + Trying to prove $equiv for \frame_payload [360]: failed. + Trying to prove $equiv for \frame_payload [361]: failed. + Trying to prove $equiv for \frame_payload [362]: failed. + Trying to prove $equiv for \frame_payload [363]: failed. + Trying to prove $equiv for \frame_payload [364]: failed. + Trying to prove $equiv for \frame_payload [365]: failed. + Trying to prove $equiv for \frame_payload [366]: failed. + Trying to prove $equiv for \frame_payload [367]: failed. + Trying to prove $equiv for \frame_payload [368]: failed. + Trying to prove $equiv for \frame_payload [369]: failed. + Trying to prove $equiv for \frame_payload [370]: failed. + Trying to prove $equiv for \frame_payload [371]: failed. + Trying to prove $equiv for \frame_payload [372]: failed. + Trying to prove $equiv for \frame_payload [373]: failed. + Trying to prove $equiv for \frame_payload [374]: failed. + Trying to prove $equiv for \frame_payload [375]: failed. + Trying to prove $equiv for \frame_payload [376]: failed. + Trying to prove $equiv for \frame_payload [377]: failed. + Trying to prove $equiv for \frame_payload [378]: failed. + Trying to prove $equiv for \frame_payload [379]: failed. + Trying to prove $equiv for \frame_payload [380]: failed. + Trying to prove $equiv for \frame_payload [381]: failed. + Trying to prove $equiv for \frame_payload [382]: failed. + Trying to prove $equiv for \frame_payload [383]: failed. + Trying to prove $equiv for \frame_payload [384]: failed. + Trying to prove $equiv for \frame_payload [385]: failed. + Trying to prove $equiv for \frame_payload [386]: failed. + Trying to prove $equiv for \frame_payload [387]: failed. + Trying to prove $equiv for \frame_payload [388]: failed. + Trying to prove $equiv for \frame_payload [389]: failed. + Trying to prove $equiv for \frame_payload [390]: failed. + Trying to prove $equiv for \frame_payload [391]: failed. + Trying to prove $equiv for \frame_payload [392]: failed. + Trying to prove $equiv for \frame_payload [393]: failed. + Trying to prove $equiv for \frame_payload [394]: failed. + Trying to prove $equiv for \frame_payload [395]: failed. + Trying to prove $equiv for \frame_payload [396]: failed. + Trying to prove $equiv for \frame_payload [397]: failed. + Trying to prove $equiv for \frame_payload [398]: failed. + Trying to prove $equiv for \frame_payload [399]: failed. + Trying to prove $equiv for \frame_payload [400]: failed. + Trying to prove $equiv for \frame_payload [401]: failed. + Trying to prove $equiv for \frame_payload [402]: failed. + Trying to prove $equiv for \frame_payload [403]: failed. + Trying to prove $equiv for \frame_payload [404]: failed. + Trying to prove $equiv for \frame_payload [405]: failed. + Trying to prove $equiv for \frame_payload [406]: failed. + Trying to prove $equiv for \frame_payload [407]: failed. + Trying to prove $equiv for \frame_payload [408]: failed. + Trying to prove $equiv for \frame_payload [409]: failed. + Trying to prove $equiv for \frame_payload [410]: failed. + Trying to prove $equiv for \frame_payload [411]: failed. + Trying to prove $equiv for \frame_payload [412]: failed. + Trying to prove $equiv for \frame_payload [413]: failed. + Trying to prove $equiv for \frame_payload [414]: failed. + Trying to prove $equiv for \frame_payload [415]: failed. + Trying to prove $equiv for \frame_payload [416]: failed. + Trying to prove $equiv for \frame_payload [417]: failed. + Trying to prove $equiv for \frame_payload [418]: failed. + Trying to prove $equiv for \frame_payload [419]: failed. + Trying to prove $equiv for \frame_payload [420]: failed. + Trying to prove $equiv for \frame_payload [421]: failed. + Trying to prove $equiv for \frame_payload [422]: failed. + Trying to prove $equiv for \frame_payload [423]: failed. + Trying to prove $equiv for \frame_payload [424]: failed. + Trying to prove $equiv for \frame_payload [425]: failed. + Trying to prove $equiv for \frame_payload [426]: failed. + Trying to prove $equiv for \frame_payload [427]: failed. + Trying to prove $equiv for \frame_payload [428]: failed. + Trying to prove $equiv for \frame_payload [429]: failed. + Trying to prove $equiv for \frame_payload [430]: failed. + Trying to prove $equiv for \frame_payload [431]: failed. + Trying to prove $equiv for \frame_payload [432]: failed. + Trying to prove $equiv for \frame_payload [433]: failed. + Trying to prove $equiv for \frame_payload [434]: failed. + Trying to prove $equiv for \frame_payload [435]: failed. + Trying to prove $equiv for \frame_payload [436]: failed. + Trying to prove $equiv for \frame_payload [437]: failed. + Trying to prove $equiv for \frame_payload [438]: failed. + Trying to prove $equiv for \frame_payload [439]: failed. + Trying to prove $equiv for \frame_payload [440]: failed. + Trying to prove $equiv for \frame_payload [441]: failed. + Trying to prove $equiv for \frame_payload [442]: failed. + Trying to prove $equiv for \frame_payload [443]: failed. + Trying to prove $equiv for \frame_payload [444]: failed. + Trying to prove $equiv for \frame_payload [445]: failed. + Trying to prove $equiv for \frame_payload [446]: failed. + Trying to prove $equiv for \frame_payload [447]: failed. + Trying to prove $equiv for \frame_payload [448]: failed. + Trying to prove $equiv for \frame_payload [449]: failed. + Trying to prove $equiv for \frame_payload [450]: failed. + Trying to prove $equiv for \frame_payload [451]: failed. + Trying to prove $equiv for \frame_payload [452]: failed. + Trying to prove $equiv for \frame_payload [453]: failed. + Trying to prove $equiv for \frame_payload [454]: failed. + Trying to prove $equiv for \frame_payload [455]: failed. + Trying to prove $equiv for \frame_payload [456]: failed. + Trying to prove $equiv for \frame_payload [457]: failed. + Trying to prove $equiv for \frame_payload [458]: failed. + Trying to prove $equiv for \frame_payload [459]: failed. + Trying to prove $equiv for \frame_payload [460]: failed. + Trying to prove $equiv for \frame_payload [461]: failed. + Trying to prove $equiv for \frame_payload [462]: failed. + Trying to prove $equiv for \frame_payload [463]: failed. + Trying to prove $equiv for \frame_payload [464]: failed. + Trying to prove $equiv for \frame_payload [465]: failed. + Trying to prove $equiv for \frame_payload [466]: failed. + Trying to prove $equiv for \frame_payload [467]: failed. + Trying to prove $equiv for \frame_payload [468]: failed. + Trying to prove $equiv for \frame_payload [469]: failed. + Trying to prove $equiv for \frame_payload [470]: failed. + Trying to prove $equiv for \frame_payload [471]: failed. + Trying to prove $equiv for \frame_payload [472]: failed. + Trying to prove $equiv for \frame_payload [473]: failed. + Trying to prove $equiv for \frame_payload [474]: failed. + Trying to prove $equiv for \frame_payload [475]: failed. + Trying to prove $equiv for \frame_payload [476]: failed. + Trying to prove $equiv for \frame_payload [477]: failed. + Trying to prove $equiv for \frame_payload [478]: failed. + Trying to prove $equiv for \frame_payload [479]: failed. + Trying to prove $equiv for \frame_payload [480]: failed. + Trying to prove $equiv for \frame_payload [481]: failed. + Trying to prove $equiv for \frame_payload [482]: failed. + Trying to prove $equiv for \frame_payload [483]: failed. + Trying to prove $equiv for \frame_payload [484]: failed. + Trying to prove $equiv for \frame_payload [485]: failed. + Trying to prove $equiv for \frame_payload [486]: failed. + Trying to prove $equiv for \frame_payload [487]: failed. + Trying to prove $equiv for \frame_payload [488]: failed. + Trying to prove $equiv for \frame_payload [489]: failed. + Trying to prove $equiv for \frame_payload [490]: failed. + Trying to prove $equiv for \frame_payload [491]: failed. + Trying to prove $equiv for \frame_payload [492]: failed. + Trying to prove $equiv for \frame_payload [493]: failed. + Trying to prove $equiv for \frame_payload [494]: failed. + Trying to prove $equiv for \frame_payload [495]: failed. + Trying to prove $equiv for \frame_payload [496]: failed. + Trying to prove $equiv for \frame_payload [497]: failed. + Trying to prove $equiv for \frame_payload [498]: failed. + Trying to prove $equiv for \frame_payload [499]: failed. + Trying to prove $equiv for \frame_payload [500]: failed. + Trying to prove $equiv for \frame_payload [501]: failed. + Trying to prove $equiv for \frame_payload [502]: failed. + Trying to prove $equiv for \frame_payload [503]: failed. + Trying to prove $equiv for \frame_payload [504]: failed. + Trying to prove $equiv for \frame_payload [505]: failed. + Trying to prove $equiv for \frame_payload [506]: failed. + Trying to prove $equiv for \frame_payload [507]: failed. + Trying to prove $equiv for \frame_payload [508]: failed. + Trying to prove $equiv for \frame_payload [509]: failed. + Trying to prove $equiv for \frame_payload [510]: failed. + Trying to prove $equiv for \frame_payload [511]: failed. + Trying to prove $equiv for \frame_payload [512]: failed. + Trying to prove $equiv for \frame_payload [513]: failed. + Trying to prove $equiv for \frame_payload [514]: failed. + Trying to prove $equiv for \frame_payload [515]: failed. + Trying to prove $equiv for \frame_payload [516]: failed. + Trying to prove $equiv for \frame_payload [517]: failed. + Trying to prove $equiv for \frame_payload [518]: failed. + Trying to prove $equiv for \frame_payload [519]: failed. + Trying to prove $equiv for \frame_payload [520]: failed. + Trying to prove $equiv for \frame_payload [521]: failed. + Trying to prove $equiv for \frame_payload [522]: failed. + Trying to prove $equiv for \frame_payload [523]: failed. + Trying to prove $equiv for \frame_payload [524]: failed. + Trying to prove $equiv for \frame_payload [525]: failed. + Trying to prove $equiv for \frame_payload [526]: failed. + Trying to prove $equiv for \frame_payload [527]: failed. + Trying to prove $equiv for \frame_payload [528]: failed. + Trying to prove $equiv for \frame_payload [529]: failed. + Trying to prove $equiv for \frame_payload [530]: failed. + Trying to prove $equiv for \frame_payload [531]: failed. + Trying to prove $equiv for \frame_payload [532]: failed. + Trying to prove $equiv for \frame_payload [533]: failed. + Trying to prove $equiv for \frame_payload [534]: failed. + Trying to prove $equiv for \frame_payload [535]: failed. + Trying to prove $equiv for \frame_payload [536]: failed. + Trying to prove $equiv for \frame_payload [537]: failed. + Trying to prove $equiv for \frame_payload [538]: failed. + Trying to prove $equiv for \frame_payload [539]: failed. + Trying to prove $equiv for \frame_payload [540]: failed. + Trying to prove $equiv for \frame_payload [541]: failed. + Trying to prove $equiv for \frame_payload [542]: failed. + Trying to prove $equiv for \frame_payload [543]: failed. + Trying to prove $equiv for \frame_payload [544]: failed. + Trying to prove $equiv for \frame_payload [545]: failed. + Trying to prove $equiv for \frame_payload [546]: failed. + Trying to prove $equiv for \frame_payload [547]: failed. + Trying to prove $equiv for \frame_payload [548]: failed. + Trying to prove $equiv for \frame_payload [549]: failed. + Trying to prove $equiv for \frame_payload [550]: failed. + Trying to prove $equiv for \frame_payload [551]: failed. + Trying to prove $equiv for \frame_payload [552]: failed. + Trying to prove $equiv for \frame_payload [553]: failed. + Trying to prove $equiv for \frame_payload [554]: failed. + Trying to prove $equiv for \frame_payload [555]: failed. + Trying to prove $equiv for \frame_payload [556]: failed. + Trying to prove $equiv for \frame_payload [557]: failed. + Trying to prove $equiv for \frame_payload [558]: failed. + Trying to prove $equiv for \frame_payload [559]: failed. + Trying to prove $equiv for \frame_payload [560]: failed. + Trying to prove $equiv for \frame_payload [561]: failed. + Trying to prove $equiv for \frame_payload [562]: failed. + Trying to prove $equiv for \frame_payload [563]: failed. + Trying to prove $equiv for \frame_payload [564]: failed. + Trying to prove $equiv for \frame_payload [565]: failed. + Trying to prove $equiv for \frame_payload [566]: failed. + Trying to prove $equiv for \frame_payload [567]: failed. + Trying to prove $equiv for \frame_payload [568]: failed. + Trying to prove $equiv for \frame_payload [569]: failed. + Trying to prove $equiv for \frame_payload [570]: failed. + Trying to prove $equiv for \frame_payload [571]: failed. + Trying to prove $equiv for \frame_payload [572]: failed. + Trying to prove $equiv for \frame_payload [573]: failed. + Trying to prove $equiv for \frame_payload [574]: failed. + Trying to prove $equiv for \frame_payload [575]: failed. + Trying to prove $equiv for \frame_payload [576]: failed. + Trying to prove $equiv for \frame_payload [577]: failed. + Trying to prove $equiv for \frame_payload [578]: failed. + Trying to prove $equiv for \frame_payload [579]: failed. + Trying to prove $equiv for \frame_payload [580]: failed. + Trying to prove $equiv for \frame_payload [581]: failed. + Trying to prove $equiv for \frame_payload [582]: failed. + Trying to prove $equiv for \frame_payload [583]: failed. + Trying to prove $equiv for \frame_payload [584]: failed. + Trying to prove $equiv for \frame_payload [585]: failed. + Trying to prove $equiv for \frame_payload [586]: failed. + Trying to prove $equiv for \frame_payload [587]: failed. + Trying to prove $equiv for \frame_payload [588]: failed. + Trying to prove $equiv for \frame_payload [589]: failed. + Trying to prove $equiv for \frame_payload [590]: failed. + Trying to prove $equiv for \frame_payload [591]: failed. + Trying to prove $equiv for \frame_payload [592]: failed. + Trying to prove $equiv for \frame_payload [593]: failed. + Trying to prove $equiv for \frame_payload [594]: failed. + Trying to prove $equiv for \frame_payload [595]: failed. + Trying to prove $equiv for \frame_payload [596]: failed. + Trying to prove $equiv for \frame_payload [597]: failed. + Trying to prove $equiv for \frame_payload [598]: failed. + Trying to prove $equiv for \frame_payload [599]: failed. + Trying to prove $equiv for \frame_payload [600]: failed. + Trying to prove $equiv for \frame_payload [601]: failed. + Trying to prove $equiv for \frame_payload [602]: failed. + Trying to prove $equiv for \frame_payload [603]: failed. + Trying to prove $equiv for \frame_payload [604]: failed. + Trying to prove $equiv for \frame_payload [605]: failed. + Trying to prove $equiv for \frame_payload [606]: failed. + Trying to prove $equiv for \frame_payload [607]: failed. + Trying to prove $equiv for \frame_payload [608]: failed. + Trying to prove $equiv for \frame_payload [609]: failed. + Trying to prove $equiv for \frame_payload [610]: failed. + Trying to prove $equiv for \frame_payload [611]: failed. + Trying to prove $equiv for \frame_payload [612]: failed. + Trying to prove $equiv for \frame_payload [613]: failed. + Trying to prove $equiv for \frame_payload [614]: failed. + Trying to prove $equiv for \frame_payload [615]: failed. + Trying to prove $equiv for \frame_payload [616]: failed. + Trying to prove $equiv for \frame_payload [617]: failed. + Trying to prove $equiv for \frame_payload [618]: failed. + Trying to prove $equiv for \frame_payload [619]: failed. + Trying to prove $equiv for \frame_payload [620]: failed. + Trying to prove $equiv for \frame_payload [621]: failed. + Trying to prove $equiv for \frame_payload [622]: failed. + Trying to prove $equiv for \frame_payload [623]: failed. + Trying to prove $equiv for \frame_payload [624]: failed. + Trying to prove $equiv for \frame_payload [625]: failed. + Trying to prove $equiv for \frame_payload [626]: failed. + Trying to prove $equiv for \frame_payload [627]: failed. + Trying to prove $equiv for \frame_payload [628]: failed. + Trying to prove $equiv for \frame_payload [629]: failed. + Trying to prove $equiv for \frame_payload [630]: failed. + Trying to prove $equiv for \frame_payload [631]: failed. + Trying to prove $equiv for \frame_payload [632]: failed. + Trying to prove $equiv for \frame_payload [633]: failed. + Trying to prove $equiv for \frame_payload [634]: failed. + Trying to prove $equiv for \frame_payload [635]: failed. + Trying to prove $equiv for \frame_payload [636]: failed. + Trying to prove $equiv for \frame_payload [637]: failed. + Trying to prove $equiv for \frame_payload [638]: failed. + Trying to prove $equiv for \frame_payload [639]: failed. + Trying to prove $equiv for \frame_payload [640]: failed. + Trying to prove $equiv for \frame_payload [641]: failed. + Trying to prove $equiv for \frame_payload [642]: failed. + Trying to prove $equiv for \frame_payload [643]: failed. + Trying to prove $equiv for \frame_payload [644]: failed. + Trying to prove $equiv for \frame_payload [645]: failed. + Trying to prove $equiv for \frame_payload [646]: failed. + Trying to prove $equiv for \frame_payload [647]: failed. + Trying to prove $equiv for \frame_payload [648]: failed. + Trying to prove $equiv for \frame_payload [649]: failed. + Trying to prove $equiv for \frame_payload [650]: failed. + Trying to prove $equiv for \frame_payload [651]: failed. + Trying to prove $equiv for \frame_payload [652]: failed. + Trying to prove $equiv for \frame_payload [653]: failed. + Trying to prove $equiv for \frame_payload [654]: failed. + Trying to prove $equiv for \frame_payload [655]: failed. + Trying to prove $equiv for \frame_payload [656]: failed. + Trying to prove $equiv for \frame_payload [657]: failed. + Trying to prove $equiv for \frame_payload [658]: failed. + Trying to prove $equiv for \frame_payload [659]: failed. + Trying to prove $equiv for \frame_payload [660]: failed. + Trying to prove $equiv for \frame_payload [661]: failed. + Trying to prove $equiv for \frame_payload [662]: failed. + Trying to prove $equiv for \frame_payload [663]: failed. + Trying to prove $equiv for \frame_payload [664]: failed. + Trying to prove $equiv for \frame_payload [665]: failed. + Trying to prove $equiv for \frame_payload [666]: failed. + Trying to prove $equiv for \frame_payload [667]: failed. + Trying to prove $equiv for \frame_payload [668]: failed. + Trying to prove $equiv for \frame_payload [669]: failed. + Trying to prove $equiv for \frame_payload [670]: failed. + Trying to prove $equiv for \frame_payload [671]: failed. + Trying to prove $equiv for \frame_payload [672]: failed. + Trying to prove $equiv for \frame_payload [673]: failed. + Trying to prove $equiv for \frame_payload [674]: failed. + Trying to prove $equiv for \frame_payload [675]: failed. + Trying to prove $equiv for \frame_payload [676]: failed. + Trying to prove $equiv for \frame_payload [677]: failed. + Trying to prove $equiv for \frame_payload [678]: failed. + Trying to prove $equiv for \frame_payload [679]: failed. + Trying to prove $equiv for \frame_payload [680]: failed. + Trying to prove $equiv for \frame_payload [681]: failed. + Trying to prove $equiv for \frame_payload [682]: failed. + Trying to prove $equiv for \frame_payload [683]: failed. + Trying to prove $equiv for \frame_payload [684]: failed. + Trying to prove $equiv for \frame_payload [685]: failed. + Trying to prove $equiv for \frame_payload [686]: failed. + Trying to prove $equiv for \frame_payload [687]: failed. + Trying to prove $equiv for \frame_payload [688]: failed. + Trying to prove $equiv for \frame_payload [689]: failed. + Trying to prove $equiv for \frame_payload [690]: failed. + Trying to prove $equiv for \frame_payload [691]: failed. + Trying to prove $equiv for \frame_payload [692]: failed. + Trying to prove $equiv for \frame_payload [693]: failed. + Trying to prove $equiv for \frame_payload [694]: failed. + Trying to prove $equiv for \frame_payload [695]: failed. + Trying to prove $equiv for \frame_payload [696]: failed. + Trying to prove $equiv for \frame_payload [697]: failed. + Trying to prove $equiv for \frame_payload [698]: failed. + Trying to prove $equiv for \frame_payload [699]: failed. + Trying to prove $equiv for \frame_payload [700]: failed. + Trying to prove $equiv for \frame_payload [701]: failed. + Trying to prove $equiv for \frame_payload [702]: failed. + Trying to prove $equiv for \frame_payload [703]: failed. + Trying to prove $equiv for \frame_payload [704]: failed. + Trying to prove $equiv for \frame_payload [705]: failed. + Trying to prove $equiv for \frame_payload [706]: failed. + Trying to prove $equiv for \frame_payload [707]: failed. + Trying to prove $equiv for \frame_payload [708]: failed. + Trying to prove $equiv for \frame_payload [709]: failed. + Trying to prove $equiv for \frame_payload [710]: failed. + Trying to prove $equiv for \frame_payload [711]: failed. + Trying to prove $equiv for \frame_payload [712]: failed. + Trying to prove $equiv for \frame_payload [713]: failed. + Trying to prove $equiv for \frame_payload [714]: failed. + Trying to prove $equiv for \frame_payload [715]: failed. + Trying to prove $equiv for \frame_payload [716]: failed. + Trying to prove $equiv for \frame_payload [717]: failed. + Trying to prove $equiv for \frame_payload [718]: failed. + Trying to prove $equiv for \frame_payload [719]: failed. + Trying to prove $equiv for \frame_payload [720]: failed. + Trying to prove $equiv for \frame_payload [721]: failed. + Trying to prove $equiv for \frame_payload [722]: failed. + Trying to prove $equiv for \frame_payload [723]: failed. + Trying to prove $equiv for \frame_payload [724]: failed. + Trying to prove $equiv for \frame_payload [725]: failed. + Trying to prove $equiv for \frame_payload [726]: failed. + Trying to prove $equiv for \frame_payload [727]: failed. + Trying to prove $equiv for \frame_payload [728]: failed. + Trying to prove $equiv for \frame_payload [729]: failed. + Trying to prove $equiv for \frame_payload [730]: failed. + Trying to prove $equiv for \frame_payload [731]: failed. + Trying to prove $equiv for \frame_payload [732]: failed. + Trying to prove $equiv for \frame_payload [733]: failed. + Trying to prove $equiv for \frame_payload [734]: failed. + Trying to prove $equiv for \frame_payload [735]: failed. + Trying to prove $equiv for \frame_payload [736]: failed. + Trying to prove $equiv for \frame_payload [737]: failed. + Trying to prove $equiv for \frame_payload [738]: failed. + Trying to prove $equiv for \frame_payload [739]: failed. + Trying to prove $equiv for \frame_payload [740]: failed. + Trying to prove $equiv for \frame_payload [741]: failed. + Trying to prove $equiv for \frame_payload [742]: failed. + Trying to prove $equiv for \frame_payload [743]: failed. + Trying to prove $equiv for \frame_payload [744]: failed. + Trying to prove $equiv for \frame_payload [745]: failed. + Trying to prove $equiv for \frame_payload [746]: failed. + Trying to prove $equiv for \frame_payload [747]: failed. + Trying to prove $equiv for \frame_payload [748]: failed. + Trying to prove $equiv for \frame_payload [749]: failed. + Trying to prove $equiv for \frame_payload [750]: failed. + Trying to prove $equiv for \frame_payload [751]: failed. + Trying to prove $equiv for \frame_payload [752]: failed. + Trying to prove $equiv for \frame_payload [753]: failed. + Trying to prove $equiv for \frame_payload [754]: failed. + Trying to prove $equiv for \frame_payload [755]: failed. + Trying to prove $equiv for \frame_payload [756]: failed. + Trying to prove $equiv for \frame_payload [757]: failed. + Trying to prove $equiv for \frame_payload [758]: failed. + Trying to prove $equiv for \frame_payload [759]: failed. + Trying to prove $equiv for \frame_payload [760]: failed. + Trying to prove $equiv for \frame_payload [761]: failed. + Trying to prove $equiv for \frame_payload [762]: failed. + Trying to prove $equiv for \frame_payload [763]: failed. + Trying to prove $equiv for \frame_payload [764]: failed. + Trying to prove $equiv for \frame_payload [765]: failed. + Trying to prove $equiv for \frame_payload [766]: failed. + Trying to prove $equiv for \frame_payload [767]: failed. + Trying to prove $equiv for \frame_payload [768]: failed. + Trying to prove $equiv for \frame_payload [769]: failed. + Trying to prove $equiv for \frame_payload [770]: failed. + Trying to prove $equiv for \frame_payload [771]: failed. + Trying to prove $equiv for \frame_payload [772]: failed. + Trying to prove $equiv for \frame_payload [773]: failed. + Trying to prove $equiv for \frame_payload [774]: failed. + Trying to prove $equiv for \frame_payload [775]: failed. + Trying to prove $equiv for \frame_payload [776]: failed. + Trying to prove $equiv for \frame_payload [777]: failed. + Trying to prove $equiv for \frame_payload [778]: failed. + Trying to prove $equiv for \frame_payload [779]: failed. + Trying to prove $equiv for \frame_payload [780]: failed. + Trying to prove $equiv for \frame_payload [781]: failed. + Trying to prove $equiv for \frame_payload [782]: failed. + Trying to prove $equiv for \frame_payload [783]: failed. + Trying to prove $equiv for \frame_payload [784]: failed. + Trying to prove $equiv for \frame_payload [785]: failed. + Trying to prove $equiv for \frame_payload [786]: failed. + Trying to prove $equiv for \frame_payload [787]: failed. + Trying to prove $equiv for \frame_payload [788]: failed. + Trying to prove $equiv for \frame_payload [789]: failed. + Trying to prove $equiv for \frame_payload [790]: failed. + Trying to prove $equiv for \frame_payload [791]: failed. + Trying to prove $equiv for \frame_payload [792]: failed. + Trying to prove $equiv for \frame_payload [793]: failed. + Trying to prove $equiv for \frame_payload [794]: failed. + Trying to prove $equiv for \frame_payload [795]: failed. + Trying to prove $equiv for \frame_payload [796]: failed. + Trying to prove $equiv for \frame_payload [797]: failed. + Trying to prove $equiv for \frame_payload [798]: failed. + Trying to prove $equiv for \frame_payload [799]: failed. + Trying to prove $equiv for \frame_payload [800]: failed. + Trying to prove $equiv for \frame_payload [801]: failed. + Trying to prove $equiv for \frame_payload [802]: failed. + Trying to prove $equiv for \frame_payload [803]: failed. + Trying to prove $equiv for \frame_payload [804]: failed. + Trying to prove $equiv for \frame_payload [805]: failed. + Trying to prove $equiv for \frame_payload [806]: failed. + Trying to prove $equiv for \frame_payload [807]: failed. + Trying to prove $equiv for \frame_payload [808]: failed. + Trying to prove $equiv for \frame_payload [809]: failed. + Trying to prove $equiv for \frame_payload [810]: failed. + Trying to prove $equiv for \frame_payload [811]: failed. + Trying to prove $equiv for \frame_payload [812]: failed. + Trying to prove $equiv for \frame_payload [813]: failed. + Trying to prove $equiv for \frame_payload [814]: failed. + Trying to prove $equiv for \frame_payload [815]: failed. + Trying to prove $equiv for \frame_payload [816]: failed. + Trying to prove $equiv for \frame_payload [817]: failed. + Trying to prove $equiv for \frame_payload [818]: failed. + Trying to prove $equiv for \frame_payload [819]: failed. + Trying to prove $equiv for \frame_payload [820]: failed. + Trying to prove $equiv for \frame_payload [821]: failed. + Trying to prove $equiv for \frame_payload [822]: failed. + Trying to prove $equiv for \frame_payload [823]: failed. + Trying to prove $equiv for \frame_payload [824]: failed. + Trying to prove $equiv for \frame_payload [825]: failed. + Trying to prove $equiv for \frame_payload [826]: failed. + Trying to prove $equiv for \frame_payload [827]: failed. + Trying to prove $equiv for \frame_payload [828]: failed. + Trying to prove $equiv for \frame_payload [829]: failed. + Trying to prove $equiv for \frame_payload [830]: failed. + Trying to prove $equiv for \frame_payload [831]: failed. + Trying to prove $equiv for \frame_payload [832]: failed. + Trying to prove $equiv for \frame_payload [833]: failed. + Trying to prove $equiv for \frame_payload [834]: failed. + Trying to prove $equiv for \frame_payload [835]: failed. + Trying to prove $equiv for \frame_payload [836]: failed. + Trying to prove $equiv for \frame_payload [837]: failed. + Trying to prove $equiv for \frame_payload [838]: failed. + Trying to prove $equiv for \frame_payload [839]: failed. + Trying to prove $equiv for \frame_payload [840]: failed. + Trying to prove $equiv for \frame_payload [841]: failed. + Trying to prove $equiv for \frame_payload [842]: failed. + Trying to prove $equiv for \frame_payload [843]: failed. + Trying to prove $equiv for \frame_payload [844]: failed. + Trying to prove $equiv for \frame_payload [845]: failed. + Trying to prove $equiv for \frame_payload [846]: failed. + Trying to prove $equiv for \frame_payload [847]: failed. + Trying to prove $equiv for \frame_payload [848]: failed. + Trying to prove $equiv for \frame_payload [849]: failed. + Trying to prove $equiv for \frame_payload [850]: failed. + Trying to prove $equiv for \frame_payload [851]: failed. + Trying to prove $equiv for \frame_payload [852]: failed. + Trying to prove $equiv for \frame_payload [853]: failed. + Trying to prove $equiv for \frame_payload [854]: failed. + Trying to prove $equiv for \frame_payload [855]: failed. + Trying to prove $equiv for \frame_payload [856]: failed. + Trying to prove $equiv for \frame_payload [857]: failed. + Trying to prove $equiv for \frame_payload [858]: failed. + Trying to prove $equiv for \frame_payload [859]: failed. + Trying to prove $equiv for \frame_payload [860]: failed. + Trying to prove $equiv for \frame_payload [861]: failed. + Trying to prove $equiv for \frame_payload [862]: failed. + Trying to prove $equiv for \frame_payload [863]: failed. + Trying to prove $equiv for \frame_payload [864]: failed. + Trying to prove $equiv for \frame_payload [865]: failed. + Trying to prove $equiv for \frame_payload [866]: failed. + Trying to prove $equiv for \frame_payload [867]: failed. + Trying to prove $equiv for \frame_payload [868]: failed. + Trying to prove $equiv for \frame_payload [869]: failed. + Trying to prove $equiv for \frame_payload [870]: failed. + Trying to prove $equiv for \frame_payload [871]: failed. + Trying to prove $equiv for \frame_payload [872]: failed. + Trying to prove $equiv for \frame_payload [873]: failed. + Trying to prove $equiv for \frame_payload [874]: failed. + Trying to prove $equiv for \frame_payload [875]: failed. + Trying to prove $equiv for \frame_payload [876]: failed. + Trying to prove $equiv for \frame_payload [877]: failed. + Trying to prove $equiv for \frame_payload [878]: failed. + Trying to prove $equiv for \frame_payload [879]: failed. + Trying to prove $equiv for \frame_payload [880]: failed. + Trying to prove $equiv for \frame_payload [881]: failed. + Trying to prove $equiv for \frame_payload [882]: failed. + Trying to prove $equiv for \frame_payload [883]: failed. + Trying to prove $equiv for \frame_payload [884]: failed. + Trying to prove $equiv for \frame_payload [885]: failed. + Trying to prove $equiv for \frame_payload [886]: failed. + Trying to prove $equiv for \frame_payload [887]: failed. + Trying to prove $equiv for \frame_payload [888]: failed. + Trying to prove $equiv for \frame_payload [889]: failed. + Trying to prove $equiv for \frame_payload [890]: failed. + Trying to prove $equiv for \frame_payload [891]: failed. + Trying to prove $equiv for \frame_payload [892]: failed. + Trying to prove $equiv for \frame_payload [893]: failed. + Trying to prove $equiv for \frame_payload [894]: failed. + Trying to prove $equiv for \frame_payload [895]: failed. + Trying to prove $equiv for \frame_payload [896]: failed. + Trying to prove $equiv for \frame_payload [897]: failed. + Trying to prove $equiv for \frame_payload [898]: failed. + Trying to prove $equiv for \frame_payload [899]: failed. + Trying to prove $equiv for \frame_payload [900]: failed. + Trying to prove $equiv for \frame_payload [901]: failed. + Trying to prove $equiv for \frame_payload [902]: failed. + Trying to prove $equiv for \frame_payload [903]: failed. + Trying to prove $equiv for \frame_payload [904]: failed. + Trying to prove $equiv for \frame_payload [905]: failed. + Trying to prove $equiv for \frame_payload [906]: failed. + Trying to prove $equiv for \frame_payload [907]: failed. + Trying to prove $equiv for \frame_payload [908]: failed. + Trying to prove $equiv for \frame_payload [909]: failed. + Trying to prove $equiv for \frame_payload [910]: failed. + Trying to prove $equiv for \frame_payload [911]: failed. + Trying to prove $equiv for \frame_payload [912]: failed. + Trying to prove $equiv for \frame_payload [913]: failed. + Trying to prove $equiv for \frame_payload [914]: failed. + Trying to prove $equiv for \frame_payload [915]: failed. + Trying to prove $equiv for \frame_payload [916]: failed. + Trying to prove $equiv for \frame_payload [917]: failed. + Trying to prove $equiv for \frame_payload [918]: failed. + Trying to prove $equiv for \frame_payload [919]: failed. + Trying to prove $equiv for \frame_payload [920]: failed. + Trying to prove $equiv for \frame_payload [921]: failed. + Trying to prove $equiv for \frame_payload [922]: failed. + Trying to prove $equiv for \frame_payload [923]: failed. + Trying to prove $equiv for \frame_payload [924]: failed. + Trying to prove $equiv for \frame_payload [925]: failed. + Trying to prove $equiv for \frame_payload [926]: failed. + Trying to prove $equiv for \frame_payload [927]: failed. + Trying to prove $equiv for \frame_payload [928]: failed. + Trying to prove $equiv for \frame_payload [929]: failed. + Trying to prove $equiv for \frame_payload [930]: failed. + Trying to prove $equiv for \frame_payload [931]: failed. + Trying to prove $equiv for \frame_payload [932]: failed. + Trying to prove $equiv for \frame_payload [933]: failed. + Trying to prove $equiv for \frame_payload [934]: failed. + Trying to prove $equiv for \frame_payload [935]: failed. + Trying to prove $equiv for \frame_payload [936]: failed. + Trying to prove $equiv for \frame_payload [937]: failed. + Trying to prove $equiv for \frame_payload [938]: failed. + Trying to prove $equiv for \frame_payload [939]: failed. + Trying to prove $equiv for \frame_payload [940]: failed. + Trying to prove $equiv for \frame_payload [941]: failed. + Trying to prove $equiv for \frame_payload [942]: failed. + Trying to prove $equiv for \frame_payload [943]: failed. + Trying to prove $equiv for \frame_payload [944]: failed. + Trying to prove $equiv for \frame_payload [945]: failed. + Trying to prove $equiv for \frame_payload [946]: failed. + Trying to prove $equiv for \frame_payload [947]: failed. + Trying to prove $equiv for \frame_payload [948]: failed. + Trying to prove $equiv for \frame_payload [949]: failed. + Trying to prove $equiv for \frame_payload [950]: failed. + Trying to prove $equiv for \frame_payload [951]: failed. + Trying to prove $equiv for \frame_payload [952]: failed. + Trying to prove $equiv for \frame_payload [953]: failed. + Trying to prove $equiv for \frame_payload [954]: failed. + Trying to prove $equiv for \frame_payload [955]: failed. + Trying to prove $equiv for \frame_payload [956]: failed. + Trying to prove $equiv for \frame_payload [957]: failed. + Trying to prove $equiv for \frame_payload [958]: failed. + Trying to prove $equiv for \frame_payload [959]: failed. + Trying to prove $equiv for \frame_payload [960]: failed. + Trying to prove $equiv for \frame_payload [961]: failed. + Trying to prove $equiv for \frame_payload [962]: failed. + Trying to prove $equiv for \frame_payload [963]: failed. + Trying to prove $equiv for \frame_payload [964]: failed. + Trying to prove $equiv for \frame_payload [965]: failed. + Trying to prove $equiv for \frame_payload [966]: failed. + Trying to prove $equiv for \frame_payload [967]: failed. + Trying to prove $equiv for \frame_payload [968]: failed. + Trying to prove $equiv for \frame_payload [969]: failed. + Trying to prove $equiv for \frame_payload [970]: failed. + Trying to prove $equiv for \frame_payload [971]: failed. + Trying to prove $equiv for \frame_payload [972]: failed. + Trying to prove $equiv for \frame_payload [973]: failed. + Trying to prove $equiv for \frame_payload [974]: failed. + Trying to prove $equiv for \frame_payload [975]: failed. + Trying to prove $equiv for \frame_payload [976]: failed. + Trying to prove $equiv for \frame_payload [977]: failed. + Trying to prove $equiv for \frame_payload [978]: failed. + Trying to prove $equiv for \frame_payload [979]: failed. + Trying to prove $equiv for \frame_payload [980]: failed. + Trying to prove $equiv for \frame_payload [981]: failed. + Trying to prove $equiv for \frame_payload [982]: failed. + Trying to prove $equiv for \frame_payload [983]: failed. + Trying to prove $equiv for \frame_payload [984]: failed. + Trying to prove $equiv for \frame_payload [985]: failed. + Trying to prove $equiv for \frame_payload [986]: failed. + Trying to prove $equiv for \frame_payload [987]: failed. + Trying to prove $equiv for \frame_payload [988]: failed. + Trying to prove $equiv for \frame_payload [989]: failed. + Trying to prove $equiv for \frame_payload [990]: failed. + Trying to prove $equiv for \frame_payload [991]: failed. + Trying to prove $equiv for \frame_payload [992]: failed. + Trying to prove $equiv for \frame_payload [993]: failed. + Trying to prove $equiv for \frame_payload [994]: failed. + Trying to prove $equiv for \frame_payload [995]: failed. + Trying to prove $equiv for \frame_payload [996]: failed. + Trying to prove $equiv for \frame_payload [997]: failed. + Trying to prove $equiv for \frame_payload [998]: failed. + Trying to prove $equiv for \frame_payload [999]: failed. + Trying to prove $equiv for \frame_payload [1000]: failed. + Trying to prove $equiv for \frame_payload [1001]: failed. + Trying to prove $equiv for \frame_payload [1002]: failed. + Trying to prove $equiv for \frame_payload [1003]: failed. + Trying to prove $equiv for \frame_payload [1004]: failed. + Trying to prove $equiv for \frame_payload [1005]: failed. + Trying to prove $equiv for \frame_payload [1006]: failed. + Trying to prove $equiv for \frame_payload [1007]: failed. + Trying to prove $equiv for \frame_payload [1008]: failed. + Trying to prove $equiv for \frame_payload [1009]: failed. + Trying to prove $equiv for \frame_payload [1010]: failed. + Trying to prove $equiv for \frame_payload [1011]: failed. + Trying to prove $equiv for \frame_payload [1012]: failed. + Trying to prove $equiv for \frame_payload [1013]: failed. + Trying to prove $equiv for \frame_payload [1014]: failed. + Trying to prove $equiv for \frame_payload [1015]: failed. + Trying to prove $equiv for \frame_payload [1016]: failed. + Trying to prove $equiv for \frame_payload [1017]: failed. + Trying to prove $equiv for \frame_payload [1018]: failed. + Trying to prove $equiv for \frame_payload [1019]: failed. + Trying to prove $equiv for \frame_payload [1020]: failed. + Trying to prove $equiv for \frame_payload [1021]: failed. + Trying to prove $equiv for \frame_payload [1022]: failed. + Trying to prove $equiv for \frame_payload [1023]: failed. + Trying to prove $equiv for \frame_payload [1024]: failed. + Trying to prove $equiv for \frame_payload [1025]: failed. + Trying to prove $equiv for \frame_payload [1026]: failed. + Trying to prove $equiv for \frame_payload [1027]: failed. + Trying to prove $equiv for \frame_payload [1028]: failed. + Trying to prove $equiv for \frame_payload [1029]: failed. + Trying to prove $equiv for \frame_payload [1030]: failed. + Trying to prove $equiv for \frame_payload [1031]: failed. + Trying to prove $equiv for \frame_payload [1032]: failed. + Trying to prove $equiv for \frame_payload [1033]: failed. + Trying to prove $equiv for \frame_payload [1034]: failed. + Trying to prove $equiv for \frame_payload [1035]: failed. + Trying to prove $equiv for \frame_payload [1036]: failed. + Trying to prove $equiv for \frame_payload [1037]: failed. + Trying to prove $equiv for \frame_payload [1038]: failed. + Trying to prove $equiv for \frame_payload [1039]: failed. + Trying to prove $equiv for \frame_payload [1040]: failed. + Trying to prove $equiv for \frame_payload [1041]: failed. + Trying to prove $equiv for \frame_payload [1042]: failed. + Trying to prove $equiv for \frame_payload [1043]: failed. + Trying to prove $equiv for \frame_payload [1044]: failed. + Trying to prove $equiv for \frame_payload [1045]: failed. + Trying to prove $equiv for \frame_payload [1046]: failed. + Trying to prove $equiv for \frame_payload [1047]: failed. + Trying to prove $equiv for \frame_payload [1048]: failed. + Trying to prove $equiv for \frame_payload [1049]: failed. + Trying to prove $equiv for \frame_payload [1050]: failed. + Trying to prove $equiv for \frame_payload [1051]: failed. + Trying to prove $equiv for \frame_payload [1052]: failed. + Trying to prove $equiv for \frame_payload [1053]: failed. + Trying to prove $equiv for \frame_payload [1054]: failed. + Trying to prove $equiv for \frame_payload [1055]: failed. + Trying to prove $equiv for \frame_payload [1056]: failed. + Trying to prove $equiv for \frame_payload [1057]: failed. + Trying to prove $equiv for \frame_payload [1058]: failed. + Trying to prove $equiv for \frame_payload [1059]: failed. + Trying to prove $equiv for \frame_payload [1060]: failed. + Trying to prove $equiv for \frame_payload [1061]: failed. + Trying to prove $equiv for \frame_payload [1062]: failed. + Trying to prove $equiv for \frame_payload [1063]: failed. + Trying to prove $equiv for \frame_payload [1064]: failed. + Trying to prove $equiv for \frame_payload [1065]: failed. + Trying to prove $equiv for \frame_payload [1066]: failed. + Trying to prove $equiv for \frame_payload [1067]: failed. + Trying to prove $equiv for \frame_payload [1068]: failed. + Trying to prove $equiv for \frame_payload [1069]: failed. + Trying to prove $equiv for \frame_payload [1070]: failed. + Trying to prove $equiv for \frame_payload [1071]: failed. + Trying to prove $equiv for \frame_payload [1072]: failed. + Trying to prove $equiv for \frame_payload [1073]: failed. + Trying to prove $equiv for \frame_payload [1074]: failed. + Trying to prove $equiv for \frame_payload [1075]: failed. + Trying to prove $equiv for \frame_payload [1076]: failed. + Trying to prove $equiv for \frame_payload [1077]: failed. + Trying to prove $equiv for \frame_payload [1078]: failed. + Trying to prove $equiv for \frame_payload [1079]: failed. + Trying to prove $equiv for \frame_payload [1080]: failed. + Trying to prove $equiv for \frame_payload [1081]: failed. + Trying to prove $equiv for \frame_payload [1082]: failed. + Trying to prove $equiv for \frame_payload [1083]: failed. + Trying to prove $equiv for \frame_payload [1084]: failed. + Trying to prove $equiv for \frame_payload [1085]: failed. + Trying to prove $equiv for \frame_payload [1086]: failed. + Trying to prove $equiv for \frame_payload [1087]: failed. + Trying to prove $equiv for \frame_payload [1088]: failed. + Trying to prove $equiv for \frame_payload [1089]: failed. + Trying to prove $equiv for \frame_payload [1090]: failed. + Trying to prove $equiv for \frame_payload [1091]: failed. + Trying to prove $equiv for \frame_payload [1092]: failed. + Trying to prove $equiv for \frame_payload [1093]: failed. + Trying to prove $equiv for \frame_payload [1094]: failed. + Trying to prove $equiv for \frame_payload [1095]: failed. + Trying to prove $equiv for \frame_payload [1096]: failed. + Trying to prove $equiv for \frame_payload [1097]: failed. + Trying to prove $equiv for \frame_payload [1098]: failed. + Trying to prove $equiv for \frame_payload [1099]: failed. + Trying to prove $equiv for \frame_payload [1100]: failed. + Trying to prove $equiv for \frame_payload [1101]: failed. + Trying to prove $equiv for \frame_payload [1102]: failed. + Trying to prove $equiv for \frame_payload [1103]: failed. + Trying to prove $equiv for \frame_payload [1104]: failed. + Trying to prove $equiv for \frame_payload [1105]: failed. + Trying to prove $equiv for \frame_payload [1106]: failed. + Trying to prove $equiv for \frame_payload [1107]: failed. + Trying to prove $equiv for \frame_payload [1108]: failed. + Trying to prove $equiv for \frame_payload [1109]: failed. + Trying to prove $equiv for \frame_payload [1110]: failed. + Trying to prove $equiv for \frame_payload [1111]: failed. + Trying to prove $equiv for \frame_payload [1112]: failed. + Trying to prove $equiv for \frame_payload [1113]: failed. + Trying to prove $equiv for \frame_payload [1114]: failed. + Trying to prove $equiv for \frame_payload [1115]: failed. + Trying to prove $equiv for \frame_payload [1116]: failed. + Trying to prove $equiv for \frame_payload [1117]: failed. + Trying to prove $equiv for \frame_payload [1118]: failed. + Trying to prove $equiv for \frame_payload [1119]: failed. + Trying to prove $equiv for \frame_payload [1120]: failed. + Trying to prove $equiv for \frame_payload [1121]: failed. + Trying to prove $equiv for \frame_payload [1122]: failed. + Trying to prove $equiv for \frame_payload [1123]: failed. + Trying to prove $equiv for \frame_payload [1124]: failed. + Trying to prove $equiv for \frame_payload [1125]: failed. + Trying to prove $equiv for \frame_payload [1126]: failed. + Trying to prove $equiv for \frame_payload [1127]: failed. + Trying to prove $equiv for \frame_payload [1128]: failed. + Trying to prove $equiv for \frame_payload [1129]: failed. + Trying to prove $equiv for \frame_payload [1130]: failed. + Trying to prove $equiv for \frame_payload [1131]: failed. + Trying to prove $equiv for \frame_payload [1132]: failed. + Trying to prove $equiv for \frame_payload [1133]: failed. + Trying to prove $equiv for \frame_payload [1134]: failed. + Trying to prove $equiv for \frame_payload [1135]: failed. + Trying to prove $equiv for \frame_payload [1136]: failed. + Trying to prove $equiv for \frame_payload [1137]: failed. + Trying to prove $equiv for \frame_payload [1138]: failed. + Trying to prove $equiv for \frame_payload [1139]: failed. + Trying to prove $equiv for \frame_payload [1140]: failed. + Trying to prove $equiv for \frame_payload [1141]: failed. + Trying to prove $equiv for \frame_payload [1142]: failed. + Trying to prove $equiv for \frame_payload [1143]: failed. + Trying to prove $equiv for \frame_payload [1144]: failed. + Trying to prove $equiv for \frame_payload [1145]: failed. + Trying to prove $equiv for \frame_payload [1146]: failed. + Trying to prove $equiv for \frame_payload [1147]: failed. + Trying to prove $equiv for \frame_payload [1148]: failed. + Trying to prove $equiv for \frame_payload [1149]: failed. + Trying to prove $equiv for \frame_payload [1150]: failed. + Trying to prove $equiv for \frame_payload [1151]: failed. + Trying to prove $equiv for \frame_payload [1152]: failed. + Trying to prove $equiv for \frame_payload [1153]: failed. + Trying to prove $equiv for \frame_payload [1154]: failed. + Trying to prove $equiv for \frame_payload [1155]: failed. + Trying to prove $equiv for \frame_payload [1156]: failed. + Trying to prove $equiv for \frame_payload [1157]: failed. + Trying to prove $equiv for \frame_payload [1158]: failed. + Trying to prove $equiv for \frame_payload [1159]: failed. + Trying to prove $equiv for \frame_payload [1160]: failed. + Trying to prove $equiv for \frame_payload [1161]: failed. + Trying to prove $equiv for \frame_payload [1162]: failed. + Trying to prove $equiv for \frame_payload [1163]: failed. + Trying to prove $equiv for \frame_payload [1164]: failed. + Trying to prove $equiv for \frame_payload [1165]: failed. + Trying to prove $equiv for \frame_payload [1166]: failed. + Trying to prove $equiv for \frame_payload [1167]: failed. + Trying to prove $equiv for \frame_payload [1168]: failed. + Trying to prove $equiv for \frame_payload [1169]: failed. + Trying to prove $equiv for \frame_payload [1170]: failed. + Trying to prove $equiv for \frame_payload [1171]: failed. + Trying to prove $equiv for \frame_payload [1172]: failed. + Trying to prove $equiv for \frame_payload [1173]: failed. + Trying to prove $equiv for \frame_payload [1174]: failed. + Trying to prove $equiv for \frame_payload [1175]: failed. + Trying to prove $equiv for \frame_payload [1176]: failed. + Trying to prove $equiv for \frame_payload [1177]: failed. + Trying to prove $equiv for \frame_payload [1178]: failed. + Trying to prove $equiv for \frame_payload [1179]: failed. + Trying to prove $equiv for \frame_payload [1180]: failed. + Trying to prove $equiv for \frame_payload [1181]: failed. + Trying to prove $equiv for \frame_payload [1182]: failed. + Trying to prove $equiv for \frame_payload [1183]: failed. + Trying to prove $equiv for \frame_payload [1184]: failed. + Trying to prove $equiv for \frame_payload [1185]: failed. + Trying to prove $equiv for \frame_payload [1186]: failed. + Trying to prove $equiv for \frame_payload [1187]: failed. + Trying to prove $equiv for \frame_payload [1188]: failed. + Trying to prove $equiv for \frame_payload [1189]: failed. + Trying to prove $equiv for \frame_payload [1190]: failed. + Trying to prove $equiv for \frame_payload [1191]: failed. + Trying to prove $equiv for \frame_payload [1192]: failed. + Trying to prove $equiv for \frame_payload [1193]: failed. + Trying to prove $equiv for \frame_payload [1194]: failed. + Trying to prove $equiv for \frame_payload [1195]: failed. + Trying to prove $equiv for \frame_payload [1196]: failed. + Trying to prove $equiv for \frame_payload [1197]: failed. + Trying to prove $equiv for \frame_payload [1198]: failed. + Trying to prove $equiv for \frame_payload [1199]: failed. + Trying to prove $equiv for \frame_payload [1200]: failed. + Trying to prove $equiv for \frame_payload [1201]: failed. + Trying to prove $equiv for \frame_payload [1202]: failed. + Trying to prove $equiv for \frame_payload [1203]: failed. + Trying to prove $equiv for \frame_payload [1204]: failed. + Trying to prove $equiv for \frame_payload [1205]: failed. + Trying to prove $equiv for \frame_payload [1206]: failed. + Trying to prove $equiv for \frame_payload [1207]: failed. + Trying to prove $equiv for \frame_payload [1208]: failed. + Trying to prove $equiv for \frame_payload [1209]: failed. + Trying to prove $equiv for \frame_payload [1210]: failed. + Trying to prove $equiv for \frame_payload [1211]: failed. + Trying to prove $equiv for \frame_payload [1212]: failed. + Trying to prove $equiv for \frame_payload [1213]: failed. + Trying to prove $equiv for \frame_payload [1214]: failed. + Trying to prove $equiv for \frame_payload [1215]: failed. + Trying to prove $equiv for \frame_payload [1216]: failed. + Trying to prove $equiv for \frame_payload [1217]: failed. + Trying to prove $equiv for \frame_payload [1218]: failed. + Trying to prove $equiv for \frame_payload [1219]: failed. + Trying to prove $equiv for \frame_payload [1220]: failed. + Trying to prove $equiv for \frame_payload [1221]: failed. + Trying to prove $equiv for \frame_payload [1222]: failed. + Trying to prove $equiv for \frame_payload [1223]: failed. + Trying to prove $equiv for \frame_payload [1224]: failed. + Trying to prove $equiv for \frame_payload [1225]: failed. + Trying to prove $equiv for \frame_payload [1226]: failed. + Trying to prove $equiv for \frame_payload [1227]: failed. + Trying to prove $equiv for \frame_payload [1228]: failed. + Trying to prove $equiv for \frame_payload [1229]: failed. + Trying to prove $equiv for \frame_payload [1230]: failed. + Trying to prove $equiv for \frame_payload [1231]: failed. + Trying to prove $equiv for \frame_payload [1232]: failed. + Trying to prove $equiv for \frame_payload [1233]: failed. + Trying to prove $equiv for \frame_payload [1234]: failed. + Trying to prove $equiv for \frame_payload [1235]: failed. + Trying to prove $equiv for \frame_payload [1236]: failed. + Trying to prove $equiv for \frame_payload [1237]: failed. + Trying to prove $equiv for \frame_payload [1238]: failed. + Trying to prove $equiv for \frame_payload [1239]: failed. + Trying to prove $equiv for \frame_payload [1240]: failed. + Trying to prove $equiv for \frame_payload [1241]: failed. + Trying to prove $equiv for \frame_payload [1242]: failed. + Trying to prove $equiv for \frame_payload [1243]: failed. + Trying to prove $equiv for \frame_payload [1244]: failed. + Trying to prove $equiv for \frame_payload [1245]: failed. + Trying to prove $equiv for \frame_payload [1246]: failed. + Trying to prove $equiv for \frame_payload [1247]: failed. + Trying to prove $equiv for \frame_payload [1248]: failed. + Trying to prove $equiv for \frame_payload [1249]: failed. + Trying to prove $equiv for \frame_payload [1250]: failed. + Trying to prove $equiv for \frame_payload [1251]: failed. + Trying to prove $equiv for \frame_payload [1252]: failed. + Trying to prove $equiv for \frame_payload [1253]: failed. + Trying to prove $equiv for \frame_payload [1254]: failed. + Trying to prove $equiv for \frame_payload [1255]: failed. + Trying to prove $equiv for \frame_payload [1256]: failed. + Trying to prove $equiv for \frame_payload [1257]: failed. + Trying to prove $equiv for \frame_payload [1258]: failed. + Trying to prove $equiv for \frame_payload [1259]: failed. + Trying to prove $equiv for \frame_payload [1260]: failed. + Trying to prove $equiv for \frame_payload [1261]: failed. + Trying to prove $equiv for \frame_payload [1262]: failed. + Trying to prove $equiv for \frame_payload [1263]: failed. + Trying to prove $equiv for \frame_payload [1264]: failed. + Trying to prove $equiv for \frame_payload [1265]: failed. + Trying to prove $equiv for \frame_payload [1266]: failed. + Trying to prove $equiv for \frame_payload [1267]: failed. + Trying to prove $equiv for \frame_payload [1268]: failed. + Trying to prove $equiv for \frame_payload [1269]: failed. + Trying to prove $equiv for \frame_payload [1270]: failed. + Trying to prove $equiv for \frame_payload [1271]: failed. + Trying to prove $equiv for \frame_payload [1272]: failed. + Trying to prove $equiv for \frame_payload [1273]: failed. + Trying to prove $equiv for \frame_payload [1274]: failed. + Trying to prove $equiv for \frame_payload [1275]: failed. + Trying to prove $equiv for \frame_payload [1276]: failed. + Trying to prove $equiv for \frame_payload [1277]: failed. + Trying to prove $equiv for \frame_payload [1278]: failed. + Trying to prove $equiv for \frame_payload [1279]: failed. + Trying to prove $equiv for \frame_payload [1280]: failed. + Trying to prove $equiv for \frame_payload [1281]: failed. + Trying to prove $equiv for \frame_payload [1282]: failed. + Trying to prove $equiv for \frame_payload [1283]: failed. + Trying to prove $equiv for \frame_payload [1284]: failed. + Trying to prove $equiv for \frame_payload [1285]: failed. + Trying to prove $equiv for \frame_payload [1286]: failed. + Trying to prove $equiv for \frame_payload [1287]: failed. + Trying to prove $equiv for \frame_payload [1288]: failed. + Trying to prove $equiv for \frame_payload [1289]: failed. + Trying to prove $equiv for \frame_payload [1290]: failed. + Trying to prove $equiv for \frame_payload [1291]: failed. + Trying to prove $equiv for \frame_payload [1292]: failed. + Trying to prove $equiv for \frame_payload [1293]: failed. + Trying to prove $equiv for \frame_payload [1294]: failed. + Trying to prove $equiv for \frame_payload [1295]: failed. + Trying to prove $equiv for \frame_payload [1296]: failed. + Trying to prove $equiv for \frame_payload [1297]: failed. + Trying to prove $equiv for \frame_payload [1298]: failed. + Trying to prove $equiv for \frame_payload [1299]: failed. + Trying to prove $equiv for \frame_payload [1300]: failed. + Trying to prove $equiv for \frame_payload [1301]: failed. + Trying to prove $equiv for \frame_payload [1302]: failed. + Trying to prove $equiv for \frame_payload [1303]: failed. + Trying to prove $equiv for \frame_payload [1304]: failed. + Trying to prove $equiv for \frame_payload [1305]: failed. + Trying to prove $equiv for \frame_payload [1306]: failed. + Trying to prove $equiv for \frame_payload [1307]: failed. + Trying to prove $equiv for \frame_payload [1308]: failed. + Trying to prove $equiv for \frame_payload [1309]: failed. + Trying to prove $equiv for \frame_payload [1310]: failed. + Trying to prove $equiv for \frame_payload [1311]: failed. + Trying to prove $equiv for \frame_payload [1312]: failed. + Trying to prove $equiv for \frame_payload [1313]: failed. + Trying to prove $equiv for \frame_payload [1314]: failed. + Trying to prove $equiv for \frame_payload [1315]: failed. + Trying to prove $equiv for \frame_payload [1316]: failed. + Trying to prove $equiv for \frame_payload [1317]: failed. + Trying to prove $equiv for \frame_payload [1318]: failed. + Trying to prove $equiv for \frame_payload [1319]: failed. + Trying to prove $equiv for \frame_payload [1320]: failed. + Trying to prove $equiv for \frame_payload [1321]: failed. + Trying to prove $equiv for \frame_payload [1322]: failed. + Trying to prove $equiv for \frame_payload [1323]: failed. + Trying to prove $equiv for \frame_payload [1324]: failed. + Trying to prove $equiv for \frame_payload [1325]: failed. + Trying to prove $equiv for \frame_payload [1326]: failed. + Trying to prove $equiv for \frame_payload [1327]: failed. + Trying to prove $equiv for \frame_payload [1328]: failed. + Trying to prove $equiv for \frame_payload [1329]: failed. + Trying to prove $equiv for \frame_payload [1330]: failed. + Trying to prove $equiv for \frame_payload [1331]: failed. + Trying to prove $equiv for \frame_payload [1332]: failed. + Trying to prove $equiv for \frame_payload [1333]: failed. + Trying to prove $equiv for \frame_payload [1334]: failed. + Trying to prove $equiv for \frame_payload [1335]: failed. + Trying to prove $equiv for \frame_payload [1336]: failed. + Trying to prove $equiv for \frame_payload [1337]: failed. + Trying to prove $equiv for \frame_payload [1338]: failed. + Trying to prove $equiv for \frame_payload [1339]: failed. + Trying to prove $equiv for \frame_payload [1340]: failed. + Trying to prove $equiv for \frame_payload [1341]: failed. + Trying to prove $equiv for \frame_payload [1342]: failed. + Trying to prove $equiv for \frame_payload [1343]: failed. + Trying to prove $equiv for \frame_payload [1344]: failed. + Trying to prove $equiv for \frame_payload [1345]: failed. + Trying to prove $equiv for \frame_payload [1346]: failed. + Trying to prove $equiv for \frame_payload [1347]: failed. + Trying to prove $equiv for \frame_payload [1348]: failed. + Trying to prove $equiv for \frame_payload [1349]: failed. + Trying to prove $equiv for \frame_payload [1350]: failed. + Trying to prove $equiv for \frame_payload [1351]: failed. + Trying to prove $equiv for \frame_payload [1352]: failed. + Trying to prove $equiv for \frame_payload [1353]: failed. + Trying to prove $equiv for \frame_payload [1354]: failed. + Trying to prove $equiv for \frame_payload [1355]: failed. + Trying to prove $equiv for \frame_payload [1356]: failed. + Trying to prove $equiv for \frame_payload [1357]: failed. + Trying to prove $equiv for \frame_payload [1358]: failed. + Trying to prove $equiv for \frame_payload [1359]: failed. + Trying to prove $equiv for \frame_payload [1360]: failed. + Trying to prove $equiv for \frame_payload [1361]: failed. + Trying to prove $equiv for \frame_payload [1362]: failed. + Trying to prove $equiv for \frame_payload [1363]: failed. + Trying to prove $equiv for \frame_payload [1364]: failed. + Trying to prove $equiv for \frame_payload [1365]: failed. + Trying to prove $equiv for \frame_payload [1366]: failed. + Trying to prove $equiv for \frame_payload [1367]: failed. + Trying to prove $equiv for \frame_payload [1368]: failed. + Trying to prove $equiv for \frame_payload [1369]: failed. + Trying to prove $equiv for \frame_payload [1370]: failed. + Trying to prove $equiv for \frame_payload [1371]: failed. + Trying to prove $equiv for \frame_payload [1372]: failed. + Trying to prove $equiv for \frame_payload [1373]: failed. + Trying to prove $equiv for \frame_payload [1374]: failed. + Trying to prove $equiv for \frame_payload [1375]: failed. + Trying to prove $equiv for \frame_payload [1376]: failed. + Trying to prove $equiv for \frame_payload [1377]: failed. + Trying to prove $equiv for \frame_payload [1378]: failed. + Trying to prove $equiv for \frame_payload [1379]: failed. + Trying to prove $equiv for \frame_payload [1380]: failed. + Trying to prove $equiv for \frame_payload [1381]: failed. + Trying to prove $equiv for \frame_payload [1382]: failed. + Trying to prove $equiv for \frame_payload [1383]: failed. + Trying to prove $equiv for \frame_payload [1384]: failed. + Trying to prove $equiv for \frame_payload [1385]: failed. + Trying to prove $equiv for \frame_payload [1386]: failed. + Trying to prove $equiv for \frame_payload [1387]: failed. + Trying to prove $equiv for \frame_payload [1388]: failed. + Trying to prove $equiv for \frame_payload [1389]: failed. + Trying to prove $equiv for \frame_payload [1390]: failed. + Trying to prove $equiv for \frame_payload [1391]: failed. + Trying to prove $equiv for \frame_payload [1392]: failed. + Trying to prove $equiv for \frame_payload [1393]: failed. + Trying to prove $equiv for \frame_payload [1394]: failed. + Trying to prove $equiv for \frame_payload [1395]: failed. + Trying to prove $equiv for \frame_payload [1396]: failed. + Trying to prove $equiv for \frame_payload [1397]: failed. + Trying to prove $equiv for \frame_payload [1398]: failed. + Trying to prove $equiv for \frame_payload [1399]: failed. + Trying to prove $equiv for \frame_payload [1400]: failed. + Trying to prove $equiv for \frame_payload [1401]: failed. + Trying to prove $equiv for \frame_payload [1402]: failed. + Trying to prove $equiv for \frame_payload [1403]: failed. + Trying to prove $equiv for \frame_payload [1404]: failed. + Trying to prove $equiv for \frame_payload [1405]: failed. + Trying to prove $equiv for \frame_payload [1406]: failed. + Trying to prove $equiv for \frame_payload [1407]: failed. + Trying to prove $equiv for \frame_payload [1408]: failed. + Trying to prove $equiv for \frame_payload [1409]: failed. + Trying to prove $equiv for \frame_payload [1410]: failed. + Trying to prove $equiv for \frame_payload [1411]: failed. + Trying to prove $equiv for \frame_payload [1412]: failed. + Trying to prove $equiv for \frame_payload [1413]: failed. + Trying to prove $equiv for \frame_payload [1414]: failed. + Trying to prove $equiv for \frame_payload [1415]: failed. + Trying to prove $equiv for \frame_payload [1416]: failed. + Trying to prove $equiv for \frame_payload [1417]: failed. + Trying to prove $equiv for \frame_payload [1418]: failed. + Trying to prove $equiv for \frame_payload [1419]: failed. + Trying to prove $equiv for \frame_payload [1420]: failed. + Trying to prove $equiv for \frame_payload [1421]: failed. + Trying to prove $equiv for \frame_payload [1422]: failed. + Trying to prove $equiv for \frame_payload [1423]: failed. + Trying to prove $equiv for \frame_payload [1424]: failed. + Trying to prove $equiv for \frame_payload [1425]: failed. + Trying to prove $equiv for \frame_payload [1426]: failed. + Trying to prove $equiv for \frame_payload [1427]: failed. + Trying to prove $equiv for \frame_payload [1428]: failed. + Trying to prove $equiv for \frame_payload [1429]: failed. + Trying to prove $equiv for \frame_payload [1430]: failed. + Trying to prove $equiv for \frame_payload [1431]: failed. + Trying to prove $equiv for \frame_payload [1432]: failed. + Trying to prove $equiv for \frame_payload [1433]: failed. + Trying to prove $equiv for \frame_payload [1434]: failed. + Trying to prove $equiv for \frame_payload [1435]: failed. + Trying to prove $equiv for \frame_payload [1436]: failed. + Trying to prove $equiv for \frame_payload [1437]: failed. + Trying to prove $equiv for \frame_payload [1438]: failed. + Trying to prove $equiv for \frame_payload [1439]: failed. + Trying to prove $equiv for \frame_payload [1440]: failed. + Trying to prove $equiv for \frame_payload [1441]: failed. + Trying to prove $equiv for \frame_payload [1442]: failed. + Trying to prove $equiv for \frame_payload [1443]: failed. + Trying to prove $equiv for \frame_payload [1444]: failed. + Trying to prove $equiv for \frame_payload [1445]: failed. + Trying to prove $equiv for \frame_payload [1446]: failed. + Trying to prove $equiv for \frame_payload [1447]: failed. + Trying to prove $equiv for \frame_payload [1448]: failed. + Trying to prove $equiv for \frame_payload [1449]: failed. + Trying to prove $equiv for \frame_payload [1450]: failed. + Trying to prove $equiv for \frame_payload [1451]: failed. + Trying to prove $equiv for \frame_payload [1452]: failed. + Trying to prove $equiv for \frame_payload [1453]: failed. + Trying to prove $equiv for \frame_payload [1454]: failed. + Trying to prove $equiv for \frame_payload [1455]: failed. + Trying to prove $equiv for \frame_payload [1456]: failed. + Trying to prove $equiv for \frame_payload [1457]: failed. + Trying to prove $equiv for \frame_payload [1458]: failed. + Trying to prove $equiv for \frame_payload [1459]: failed. + Trying to prove $equiv for \frame_payload [1460]: failed. + Trying to prove $equiv for \frame_payload [1461]: failed. + Trying to prove $equiv for \frame_payload [1462]: failed. + Trying to prove $equiv for \frame_payload [1463]: failed. + Trying to prove $equiv for \frame_payload [1464]: failed. + Trying to prove $equiv for \frame_payload [1465]: failed. + Trying to prove $equiv for \frame_payload [1466]: failed. + Trying to prove $equiv for \frame_payload [1467]: failed. + Trying to prove $equiv for \frame_payload [1468]: failed. + Trying to prove $equiv for \frame_payload [1469]: failed. + Trying to prove $equiv for \frame_payload [1470]: failed. + Trying to prove $equiv for \frame_payload [1471]: failed. + Trying to prove $equiv for \frame_payload [1472]: failed. + Trying to prove $equiv for \frame_payload [1473]: failed. + Trying to prove $equiv for \frame_payload [1474]: failed. + Trying to prove $equiv for \frame_payload [1475]: failed. + Trying to prove $equiv for \frame_payload [1476]: failed. + Trying to prove $equiv for \frame_payload [1477]: failed. + Trying to prove $equiv for \frame_payload [1478]: failed. + Trying to prove $equiv for \frame_payload [1479]: failed. + Trying to prove $equiv for \frame_payload [1480]: failed. + Trying to prove $equiv for \frame_payload [1481]: failed. + Trying to prove $equiv for \frame_payload [1482]: failed. + Trying to prove $equiv for \frame_payload [1483]: failed. + Trying to prove $equiv for \frame_payload [1484]: failed. + Trying to prove $equiv for \frame_payload [1485]: failed. + Trying to prove $equiv for \frame_payload [1486]: failed. + Trying to prove $equiv for \frame_payload [1487]: failed. + Trying to prove $equiv for \frame_payload [1488]: failed. + Trying to prove $equiv for \frame_payload [1489]: failed. + Trying to prove $equiv for \frame_payload [1490]: failed. + Trying to prove $equiv for \frame_payload [1491]: failed. + Trying to prove $equiv for \frame_payload [1492]: failed. + Trying to prove $equiv for \frame_payload [1493]: failed. + Trying to prove $equiv for \frame_payload [1494]: failed. + Trying to prove $equiv for \frame_payload [1495]: failed. + Trying to prove $equiv for \frame_payload [1496]: failed. + Trying to prove $equiv for \frame_payload [1497]: failed. + Trying to prove $equiv for \frame_payload [1498]: failed. + Trying to prove $equiv for \frame_payload [1499]: failed. + Trying to prove $equiv for \frame_payload [1500]: failed. + Trying to prove $equiv for \frame_payload [1501]: failed. + Trying to prove $equiv for \frame_payload [1502]: failed. + Trying to prove $equiv for \frame_payload [1503]: failed. + Trying to prove $equiv for \frame_payload [1504]: failed. + Trying to prove $equiv for \frame_payload [1505]: failed. + Trying to prove $equiv for \frame_payload [1506]: failed. + Trying to prove $equiv for \frame_payload [1507]: failed. + Trying to prove $equiv for \frame_payload [1508]: failed. + Trying to prove $equiv for \frame_payload [1509]: failed. + Trying to prove $equiv for \frame_payload [1510]: failed. + Trying to prove $equiv for \frame_payload [1511]: failed. + Trying to prove $equiv for \frame_payload [1512]: failed. + Trying to prove $equiv for \frame_payload [1513]: failed. + Trying to prove $equiv for \frame_payload [1514]: failed. + Trying to prove $equiv for \frame_payload [1515]: failed. + Trying to prove $equiv for \frame_payload [1516]: failed. + Trying to prove $equiv for \frame_payload [1517]: failed. + Trying to prove $equiv for \frame_payload [1518]: failed. + Trying to prove $equiv for \frame_payload [1519]: failed. + Trying to prove $equiv for \frame_payload [1520]: failed. + Trying to prove $equiv for \frame_payload [1521]: failed. + Trying to prove $equiv for \frame_payload [1522]: failed. + Trying to prove $equiv for \frame_payload [1523]: failed. + Trying to prove $equiv for \frame_payload [1524]: failed. + Trying to prove $equiv for \frame_payload [1525]: failed. + Trying to prove $equiv for \frame_payload [1526]: failed. + Trying to prove $equiv for \frame_payload [1527]: failed. + Trying to prove $equiv for \frame_payload [1528]: failed. + Trying to prove $equiv for \frame_payload [1529]: failed. + Trying to prove $equiv for \frame_payload [1530]: failed. + Trying to prove $equiv for \frame_payload [1531]: failed. + Trying to prove $equiv for \frame_payload [1532]: failed. + Trying to prove $equiv for \frame_payload [1533]: failed. + Trying to prove $equiv for \frame_payload [1534]: failed. + Trying to prove $equiv for \frame_payload [1535]: failed. + Trying to prove $equiv for \frame_payload [1536]: failed. + Trying to prove $equiv for \frame_payload [1537]: failed. + Trying to prove $equiv for \frame_payload [1538]: failed. + Trying to prove $equiv for \frame_payload [1539]: failed. + Trying to prove $equiv for \frame_payload [1540]: failed. + Trying to prove $equiv for \frame_payload [1541]: failed. + Trying to prove $equiv for \frame_payload [1542]: failed. + Trying to prove $equiv for \frame_payload [1543]: failed. + Trying to prove $equiv for \frame_payload [1544]: failed. + Trying to prove $equiv for \frame_payload [1545]: failed. + Trying to prove $equiv for \frame_payload [1546]: failed. + Trying to prove $equiv for \frame_payload [1547]: failed. + Trying to prove $equiv for \frame_payload [1548]: failed. + Trying to prove $equiv for \frame_payload [1549]: failed. + Trying to prove $equiv for \frame_payload [1550]: failed. + Trying to prove $equiv for \frame_payload [1551]: failed. + Trying to prove $equiv for \frame_payload [1552]: failed. + Trying to prove $equiv for \frame_payload [1553]: failed. + Trying to prove $equiv for \frame_payload [1554]: failed. + Trying to prove $equiv for \frame_payload [1555]: failed. + Trying to prove $equiv for \frame_payload [1556]: failed. + Trying to prove $equiv for \frame_payload [1557]: failed. + Trying to prove $equiv for \frame_payload [1558]: failed. + Trying to prove $equiv for \frame_payload [1559]: failed. + Trying to prove $equiv for \frame_payload [1560]: failed. + Trying to prove $equiv for \frame_payload [1561]: failed. + Trying to prove $equiv for \frame_payload [1562]: failed. + Trying to prove $equiv for \frame_payload [1563]: failed. + Trying to prove $equiv for \frame_payload [1564]: failed. + Trying to prove $equiv for \frame_payload [1565]: failed. + Trying to prove $equiv for \frame_payload [1566]: failed. + Trying to prove $equiv for \frame_payload [1567]: failed. + Trying to prove $equiv for \frame_payload [1568]: failed. + Trying to prove $equiv for \frame_payload [1569]: failed. + Trying to prove $equiv for \frame_payload [1570]: failed. + Trying to prove $equiv for \frame_payload [1571]: failed. + Trying to prove $equiv for \frame_payload [1572]: failed. + Trying to prove $equiv for \frame_payload [1573]: failed. + Trying to prove $equiv for \frame_payload [1574]: failed. + Trying to prove $equiv for \frame_payload [1575]: failed. + Trying to prove $equiv for \frame_payload [1576]: failed. + Trying to prove $equiv for \frame_payload [1577]: failed. + Trying to prove $equiv for \frame_payload [1578]: failed. + Trying to prove $equiv for \frame_payload [1579]: failed. + Trying to prove $equiv for \frame_payload [1580]: failed. + Trying to prove $equiv for \frame_payload [1581]: failed. + Trying to prove $equiv for \frame_payload [1582]: failed. + Trying to prove $equiv for \frame_payload [1583]: failed. + Trying to prove $equiv for \frame_payload [1584]: failed. + Trying to prove $equiv for \frame_payload [1585]: failed. + Trying to prove $equiv for \frame_payload [1586]: failed. + Trying to prove $equiv for \frame_payload [1587]: failed. + Trying to prove $equiv for \frame_payload [1588]: failed. + Trying to prove $equiv for \frame_payload [1589]: failed. + Trying to prove $equiv for \frame_payload [1590]: failed. + Trying to prove $equiv for \frame_payload [1591]: failed. + Trying to prove $equiv for \frame_payload [1592]: failed. + Trying to prove $equiv for \frame_payload [1593]: failed. + Trying to prove $equiv for \frame_payload [1594]: failed. + Trying to prove $equiv for \frame_payload [1595]: failed. + Trying to prove $equiv for \frame_payload [1596]: failed. + Trying to prove $equiv for \frame_payload [1597]: failed. + Trying to prove $equiv for \frame_payload [1598]: failed. + Trying to prove $equiv for \frame_payload [1599]: failed. + Trying to prove $equiv for \frame_payload [1600]: failed. + Trying to prove $equiv for \frame_payload [1601]: failed. + Trying to prove $equiv for \frame_payload [1602]: failed. + Trying to prove $equiv for \frame_payload [1603]: failed. + Trying to prove $equiv for \frame_payload [1604]: failed. + Trying to prove $equiv for \frame_payload [1605]: failed. + Trying to prove $equiv for \frame_payload [1606]: failed. + Trying to prove $equiv for \frame_payload [1607]: failed. + Trying to prove $equiv for \frame_payload [1608]: failed. + Trying to prove $equiv for \frame_payload [1609]: failed. + Trying to prove $equiv for \frame_payload [1610]: failed. + Trying to prove $equiv for \frame_payload [1611]: failed. + Trying to prove $equiv for \frame_payload [1612]: failed. + Trying to prove $equiv for \frame_payload [1613]: failed. + Trying to prove $equiv for \frame_payload [1614]: failed. + Trying to prove $equiv for \frame_payload [1615]: failed. + Trying to prove $equiv for \frame_payload [1616]: failed. + Trying to prove $equiv for \frame_payload [1617]: failed. + Trying to prove $equiv for \frame_payload [1618]: failed. + Trying to prove $equiv for \frame_payload [1619]: failed. + Trying to prove $equiv for \frame_payload [1620]: failed. + Trying to prove $equiv for \frame_payload [1621]: failed. + Trying to prove $equiv for \frame_payload [1622]: failed. + Trying to prove $equiv for \frame_payload [1623]: failed. + Trying to prove $equiv for \frame_payload [1624]: failed. + Trying to prove $equiv for \frame_payload [1625]: failed. + Trying to prove $equiv for \frame_payload [1626]: failed. + Trying to prove $equiv for \frame_payload [1627]: failed. + Trying to prove $equiv for \frame_payload [1628]: failed. + Trying to prove $equiv for \frame_payload [1629]: failed. + Trying to prove $equiv for \frame_payload [1630]: failed. + Trying to prove $equiv for \frame_payload [1631]: failed. + Trying to prove $equiv for \frame_payload [1632]: failed. + Trying to prove $equiv for \frame_payload [1633]: failed. + Trying to prove $equiv for \frame_payload [1634]: failed. + Trying to prove $equiv for \frame_payload [1635]: failed. + Trying to prove $equiv for \frame_payload [1636]: failed. + Trying to prove $equiv for \frame_payload [1637]: failed. + Trying to prove $equiv for \frame_payload [1638]: failed. + Trying to prove $equiv for \frame_payload [1639]: failed. + Trying to prove $equiv for \frame_payload [1640]: failed. + Trying to prove $equiv for \frame_payload [1641]: failed. + Trying to prove $equiv for \frame_payload [1642]: failed. + Trying to prove $equiv for \frame_payload [1643]: failed. + Trying to prove $equiv for \frame_payload [1644]: failed. + Trying to prove $equiv for \frame_payload [1645]: failed. + Trying to prove $equiv for \frame_payload [1646]: failed. + Trying to prove $equiv for \frame_payload [1647]: failed. + Trying to prove $equiv for \frame_payload [1648]: failed. + Trying to prove $equiv for \frame_payload [1649]: failed. + Trying to prove $equiv for \frame_payload [1650]: failed. + Trying to prove $equiv for \frame_payload [1651]: failed. + Trying to prove $equiv for \frame_payload [1652]: failed. + Trying to prove $equiv for \frame_payload [1653]: failed. + Trying to prove $equiv for \frame_payload [1654]: failed. + Trying to prove $equiv for \frame_payload [1655]: failed. + Trying to prove $equiv for \frame_payload [1656]: failed. + Trying to prove $equiv for \frame_payload [1657]: failed. + Trying to prove $equiv for \frame_payload [1658]: failed. + Trying to prove $equiv for \frame_payload [1659]: failed. + Trying to prove $equiv for \frame_payload [1660]: failed. + Trying to prove $equiv for \frame_payload [1661]: failed. + Trying to prove $equiv for \frame_payload [1662]: failed. + Trying to prove $equiv for \frame_payload [1663]: failed. + Trying to prove $equiv for \frame_payload [1664]: failed. + Trying to prove $equiv for \frame_payload [1665]: failed. + Trying to prove $equiv for \frame_payload [1666]: failed. + Trying to prove $equiv for \frame_payload [1667]: failed. + Trying to prove $equiv for \frame_payload [1668]: failed. + Trying to prove $equiv for \frame_payload [1669]: failed. + Trying to prove $equiv for \frame_payload [1670]: failed. + Trying to prove $equiv for \frame_payload [1671]: failed. + Trying to prove $equiv for \frame_payload [1672]: failed. + Trying to prove $equiv for \frame_payload [1673]: failed. + Trying to prove $equiv for \frame_payload [1674]: failed. + Trying to prove $equiv for \frame_payload [1675]: failed. + Trying to prove $equiv for \frame_payload [1676]: failed. + Trying to prove $equiv for \frame_payload [1677]: failed. + Trying to prove $equiv for \frame_payload [1678]: failed. + Trying to prove $equiv for \frame_payload [1679]: failed. + Trying to prove $equiv for \frame_payload [1680]: failed. + Trying to prove $equiv for \frame_payload [1681]: failed. + Trying to prove $equiv for \frame_payload [1682]: failed. + Trying to prove $equiv for \frame_payload [1683]: failed. + Trying to prove $equiv for \frame_payload [1684]: failed. + Trying to prove $equiv for \frame_payload [1685]: failed. + Trying to prove $equiv for \frame_payload [1686]: failed. + Trying to prove $equiv for \frame_payload [1687]: failed. + Trying to prove $equiv for \frame_payload [1688]: failed. + Trying to prove $equiv for \frame_payload [1689]: failed. + Trying to prove $equiv for \frame_payload [1690]: failed. + Trying to prove $equiv for \frame_payload [1691]: failed. + Trying to prove $equiv for \frame_payload [1692]: failed. + Trying to prove $equiv for \frame_payload [1693]: failed. + Trying to prove $equiv for \frame_payload [1694]: failed. + Trying to prove $equiv for \frame_payload [1695]: failed. + Trying to prove $equiv for \frame_payload [1696]: failed. + Trying to prove $equiv for \frame_payload [1697]: failed. + Trying to prove $equiv for \frame_payload [1698]: failed. + Trying to prove $equiv for \frame_payload [1699]: failed. + Trying to prove $equiv for \frame_payload [1700]: failed. + Trying to prove $equiv for \frame_payload [1701]: failed. + Trying to prove $equiv for \frame_payload [1702]: failed. + Trying to prove $equiv for \frame_payload [1703]: failed. + Trying to prove $equiv for \frame_payload [1704]: failed. + Trying to prove $equiv for \frame_payload [1705]: failed. + Trying to prove $equiv for \frame_payload [1706]: failed. + Trying to prove $equiv for \frame_payload [1707]: failed. + Trying to prove $equiv for \frame_payload [1708]: failed. + Trying to prove $equiv for \frame_payload [1709]: failed. + Trying to prove $equiv for \frame_payload [1710]: failed. + Trying to prove $equiv for \frame_payload [1711]: failed. + Trying to prove $equiv for \frame_payload [1712]: failed. + Trying to prove $equiv for \frame_payload [1713]: failed. + Trying to prove $equiv for \frame_payload [1714]: failed. + Trying to prove $equiv for \frame_payload [1715]: failed. + Trying to prove $equiv for \frame_payload [1716]: failed. + Trying to prove $equiv for \frame_payload [1717]: failed. + Trying to prove $equiv for \frame_payload [1718]: failed. + Trying to prove $equiv for \frame_payload [1719]: failed. + Trying to prove $equiv for \frame_payload [1720]: failed. + Trying to prove $equiv for \frame_payload [1721]: failed. + Trying to prove $equiv for \frame_payload [1722]: failed. + Trying to prove $equiv for \frame_payload [1723]: failed. + Trying to prove $equiv for \frame_payload [1724]: failed. + Trying to prove $equiv for \frame_payload [1725]: failed. + Trying to prove $equiv for \frame_payload [1726]: failed. + Trying to prove $equiv for \frame_payload [1727]: failed. + Trying to prove $equiv for \frame_payload [1728]: failed. + Trying to prove $equiv for \frame_payload [1729]: failed. + Trying to prove $equiv for \frame_payload [1730]: failed. + Trying to prove $equiv for \frame_payload [1731]: failed. + Trying to prove $equiv for \frame_payload [1732]: failed. + Trying to prove $equiv for \frame_payload [1733]: failed. + Trying to prove $equiv for \frame_payload [1734]: failed. + Trying to prove $equiv for \frame_payload [1735]: failed. + Trying to prove $equiv for \frame_payload [1736]: failed. + Trying to prove $equiv for \frame_payload [1737]: failed. + Trying to prove $equiv for \frame_payload [1738]: failed. + Trying to prove $equiv for \frame_payload [1739]: failed. + Trying to prove $equiv for \frame_payload [1740]: failed. + Trying to prove $equiv for \frame_payload [1741]: failed. + Trying to prove $equiv for \frame_payload [1742]: failed. + Trying to prove $equiv for \frame_payload [1743]: failed. + Trying to prove $equiv for \frame_payload [1744]: failed. + Trying to prove $equiv for \frame_payload [1745]: failed. + Trying to prove $equiv for \frame_payload [1746]: failed. + Trying to prove $equiv for \frame_payload [1747]: failed. + Trying to prove $equiv for \frame_payload [1748]: failed. + Trying to prove $equiv for \frame_payload [1749]: failed. + Trying to prove $equiv for \frame_payload [1750]: failed. + Trying to prove $equiv for \frame_payload [1751]: failed. + Trying to prove $equiv for \frame_payload [1752]: failed. + Trying to prove $equiv for \frame_payload [1753]: failed. + Trying to prove $equiv for \frame_payload [1754]: failed. + Trying to prove $equiv for \frame_payload [1755]: failed. + Trying to prove $equiv for \frame_payload [1756]: failed. + Trying to prove $equiv for \frame_payload [1757]: failed. + Trying to prove $equiv for \frame_payload [1758]: failed. + Trying to prove $equiv for \frame_payload [1759]: failed. + Trying to prove $equiv for \frame_payload [1760]: failed. + Trying to prove $equiv for \frame_payload [1761]: failed. + Trying to prove $equiv for \frame_payload [1762]: failed. + Trying to prove $equiv for \frame_payload [1763]: failed. + Trying to prove $equiv for \frame_payload [1764]: failed. + Trying to prove $equiv for \frame_payload [1765]: failed. + Trying to prove $equiv for \frame_payload [1766]: failed. + Trying to prove $equiv for \frame_payload [1767]: failed. + Trying to prove $equiv for \frame_payload [1768]: failed. + Trying to prove $equiv for \frame_payload [1769]: failed. + Trying to prove $equiv for \frame_payload [1770]: failed. + Trying to prove $equiv for \frame_payload [1771]: failed. + Trying to prove $equiv for \frame_payload [1772]: failed. + Trying to prove $equiv for \frame_payload [1773]: failed. + Trying to prove $equiv for \frame_payload [1774]: failed. + Trying to prove $equiv for \frame_payload [1775]: failed. + Trying to prove $equiv for \frame_payload [1776]: failed. + Trying to prove $equiv for \frame_payload [1777]: failed. + Trying to prove $equiv for \frame_payload [1778]: failed. + Trying to prove $equiv for \frame_payload [1779]: failed. + Trying to prove $equiv for \frame_payload [1780]: failed. + Trying to prove $equiv for \frame_payload [1781]: failed. + Trying to prove $equiv for \frame_payload [1782]: failed. + Trying to prove $equiv for \frame_payload [1783]: failed. + Trying to prove $equiv for \frame_payload [1784]: failed. + Trying to prove $equiv for \frame_payload [1785]: failed. + Trying to prove $equiv for \frame_payload [1786]: failed. + Trying to prove $equiv for \frame_payload [1787]: failed. + Trying to prove $equiv for \frame_payload [1788]: failed. + Trying to prove $equiv for \frame_payload [1789]: failed. + Trying to prove $equiv for \frame_payload [1790]: failed. + Trying to prove $equiv for \frame_payload [1791]: failed. + Trying to prove $equiv for \frame_payload [1792]: failed. + Trying to prove $equiv for \frame_payload [1793]: failed. + Trying to prove $equiv for \frame_payload [1794]: failed. + Trying to prove $equiv for \frame_payload [1795]: failed. + Trying to prove $equiv for \frame_payload [1796]: failed. + Trying to prove $equiv for \frame_payload [1797]: failed. + Trying to prove $equiv for \frame_payload [1798]: failed. + Trying to prove $equiv for \frame_payload [1799]: failed. + Trying to prove $equiv for \frame_payload [1800]: failed. + Trying to prove $equiv for \frame_payload [1801]: failed. + Trying to prove $equiv for \frame_payload [1802]: failed. + Trying to prove $equiv for \frame_payload [1803]: failed. + Trying to prove $equiv for \frame_payload [1804]: failed. + Trying to prove $equiv for \frame_payload [1805]: failed. + Trying to prove $equiv for \frame_payload [1806]: failed. + Trying to prove $equiv for \frame_payload [1807]: failed. + Trying to prove $equiv for \frame_payload [1808]: failed. + Trying to prove $equiv for \frame_payload [1809]: failed. + Trying to prove $equiv for \frame_payload [1810]: failed. + Trying to prove $equiv for \frame_payload [1811]: failed. + Trying to prove $equiv for \frame_payload [1812]: failed. + Trying to prove $equiv for \frame_payload [1813]: failed. + Trying to prove $equiv for \frame_payload [1814]: failed. + Trying to prove $equiv for \frame_payload [1815]: failed. + Trying to prove $equiv for \frame_payload [1816]: failed. + Trying to prove $equiv for \frame_payload [1817]: failed. + Trying to prove $equiv for \frame_payload [1818]: failed. + Trying to prove $equiv for \frame_payload [1819]: failed. + Trying to prove $equiv for \frame_payload [1820]: failed. + Trying to prove $equiv for \frame_payload [1821]: failed. + Trying to prove $equiv for \frame_payload [1822]: failed. + Trying to prove $equiv for \frame_payload [1823]: failed. + Trying to prove $equiv for \frame_payload [1824]: failed. + Trying to prove $equiv for \frame_payload [1825]: failed. + Trying to prove $equiv for \frame_payload [1826]: failed. + Trying to prove $equiv for \frame_payload [1827]: failed. + Trying to prove $equiv for \frame_payload [1828]: failed. + Trying to prove $equiv for \frame_payload [1829]: failed. + Trying to prove $equiv for \frame_payload [1830]: failed. + Trying to prove $equiv for \frame_payload [1831]: failed. + Trying to prove $equiv for \frame_payload [1832]: failed. + Trying to prove $equiv for \frame_payload [1833]: failed. + Trying to prove $equiv for \frame_payload [1834]: failed. + Trying to prove $equiv for \frame_payload [1835]: failed. + Trying to prove $equiv for \frame_payload [1836]: failed. + Trying to prove $equiv for \frame_payload [1837]: failed. + Trying to prove $equiv for \frame_payload [1838]: failed. + Trying to prove $equiv for \frame_payload [1839]: failed. + Trying to prove $equiv for \frame_payload [1840]: failed. + Trying to prove $equiv for \frame_payload [1841]: failed. + Trying to prove $equiv for \frame_payload [1842]: failed. + Trying to prove $equiv for \frame_payload [1843]: failed. + Trying to prove $equiv for \frame_payload [1844]: failed. + Trying to prove $equiv for \frame_payload [1845]: failed. + Trying to prove $equiv for \frame_payload [1846]: failed. + Trying to prove $equiv for \frame_payload [1847]: failed. + Trying to prove $equiv for \frame_payload [1848]: failed. + Trying to prove $equiv for \frame_payload [1849]: failed. + Trying to prove $equiv for \frame_payload [1850]: failed. + Trying to prove $equiv for \frame_payload [1851]: failed. + Trying to prove $equiv for \frame_payload [1852]: failed. + Trying to prove $equiv for \frame_payload [1853]: failed. + Trying to prove $equiv for \frame_payload [1854]: failed. + Trying to prove $equiv for \frame_payload [1855]: failed. + Trying to prove $equiv for \frame_payload [1856]: failed. + Trying to prove $equiv for \frame_payload [1857]: failed. + Trying to prove $equiv for \frame_payload [1858]: failed. + Trying to prove $equiv for \frame_payload [1859]: failed. + Trying to prove $equiv for \frame_payload [1860]: failed. + Trying to prove $equiv for \frame_payload [1861]: failed. + Trying to prove $equiv for \frame_payload [1862]: failed. + Trying to prove $equiv for \frame_payload [1863]: failed. + Trying to prove $equiv for \frame_payload [1864]: failed. + Trying to prove $equiv for \frame_payload [1865]: failed. + Trying to prove $equiv for \frame_payload [1866]: failed. + Trying to prove $equiv for \frame_payload [1867]: failed. + Trying to prove $equiv for \frame_payload [1868]: failed. + Trying to prove $equiv for \frame_payload [1869]: failed. + Trying to prove $equiv for \frame_payload [1870]: failed. + Trying to prove $equiv for \frame_payload [1871]: failed. + Trying to prove $equiv for \frame_payload [1872]: failed. + Trying to prove $equiv for \frame_payload [1873]: failed. + Trying to prove $equiv for \frame_payload [1874]: failed. + Trying to prove $equiv for \frame_payload [1875]: failed. + Trying to prove $equiv for \frame_payload [1876]: failed. + Trying to prove $equiv for \frame_payload [1877]: failed. + Trying to prove $equiv for \frame_payload [1878]: failed. + Trying to prove $equiv for \frame_payload [1879]: failed. + Trying to prove $equiv for \frame_payload [1880]: failed. + Trying to prove $equiv for \frame_payload [1881]: failed. + Trying to prove $equiv for \frame_payload [1882]: failed. + Trying to prove $equiv for \frame_payload [1883]: failed. + Trying to prove $equiv for \frame_payload [1884]: failed. + Trying to prove $equiv for \frame_payload [1885]: failed. + Trying to prove $equiv for \frame_payload [1886]: failed. + Trying to prove $equiv for \frame_payload [1887]: failed. + Trying to prove $equiv for \frame_payload [1888]: failed. + Trying to prove $equiv for \frame_payload [1889]: failed. + Trying to prove $equiv for \frame_payload [1890]: failed. + Trying to prove $equiv for \frame_payload [1891]: failed. + Trying to prove $equiv for \frame_payload [1892]: failed. + Trying to prove $equiv for \frame_payload [1893]: failed. + Trying to prove $equiv for \frame_payload [1894]: failed. + Trying to prove $equiv for \frame_payload [1895]: failed. + Trying to prove $equiv for \frame_payload [1896]: failed. + Trying to prove $equiv for \frame_payload [1897]: failed. + Trying to prove $equiv for \frame_payload [1898]: failed. + Trying to prove $equiv for \frame_payload [1899]: failed. + Trying to prove $equiv for \frame_payload [1900]: failed. + Trying to prove $equiv for \frame_payload [1901]: failed. + Trying to prove $equiv for \frame_payload [1902]: failed. + Trying to prove $equiv for \frame_payload [1903]: failed. + Trying to prove $equiv for \frame_payload [1904]: failed. + Trying to prove $equiv for \frame_payload [1905]: failed. + Trying to prove $equiv for \frame_payload [1906]: failed. + Trying to prove $equiv for \frame_payload [1907]: failed. + Trying to prove $equiv for \frame_payload [1908]: failed. + Trying to prove $equiv for \frame_payload [1909]: failed. + Trying to prove $equiv for \frame_payload [1910]: failed. + Trying to prove $equiv for \frame_payload [1911]: failed. + Trying to prove $equiv for \frame_payload [1912]: failed. + Trying to prove $equiv for \frame_payload [1913]: failed. + Trying to prove $equiv for \frame_payload [1914]: failed. + Trying to prove $equiv for \frame_payload [1915]: failed. + Trying to prove $equiv for \frame_payload [1916]: failed. + Trying to prove $equiv for \frame_payload [1917]: failed. + Trying to prove $equiv for \frame_payload [1918]: failed. + Trying to prove $equiv for \frame_payload [1919]: failed. + Trying to prove $equiv for \frame_payload [1920]: failed. + Trying to prove $equiv for \frame_payload [1921]: failed. + Trying to prove $equiv for \frame_payload [1922]: failed. + Trying to prove $equiv for \frame_payload [1923]: failed. + Trying to prove $equiv for \frame_payload [1924]: failed. + Trying to prove $equiv for \frame_payload [1925]: failed. + Trying to prove $equiv for \frame_payload [1926]: failed. + Trying to prove $equiv for \frame_payload [1927]: failed. + Trying to prove $equiv for \frame_payload [1928]: failed. + Trying to prove $equiv for \frame_payload [1929]: failed. + Trying to prove $equiv for \frame_payload [1930]: failed. + Trying to prove $equiv for \frame_payload [1931]: failed. + Trying to prove $equiv for \frame_payload [1932]: failed. + Trying to prove $equiv for \frame_payload [1933]: failed. + Trying to prove $equiv for \frame_payload [1934]: failed. + Trying to prove $equiv for \frame_payload [1935]: failed. + Trying to prove $equiv for \frame_payload [1936]: failed. + Trying to prove $equiv for \frame_payload [1937]: failed. + Trying to prove $equiv for \frame_payload [1938]: failed. + Trying to prove $equiv for \frame_payload [1939]: failed. + Trying to prove $equiv for \frame_payload [1940]: failed. + Trying to prove $equiv for \frame_payload [1941]: failed. + Trying to prove $equiv for \frame_payload [1942]: failed. + Trying to prove $equiv for \frame_payload [1943]: failed. + Trying to prove $equiv for \frame_payload [1944]: failed. + Trying to prove $equiv for \frame_payload [1945]: failed. + Trying to prove $equiv for \frame_payload [1946]: failed. + Trying to prove $equiv for \frame_payload [1947]: failed. + Trying to prove $equiv for \frame_payload [1948]: failed. + Trying to prove $equiv for \frame_payload [1949]: failed. + Trying to prove $equiv for \frame_payload [1950]: failed. + Trying to prove $equiv for \frame_payload [1951]: failed. + Trying to prove $equiv for \frame_payload [1952]: failed. + Trying to prove $equiv for \frame_payload [1953]: failed. + Trying to prove $equiv for \frame_payload [1954]: failed. + Trying to prove $equiv for \frame_payload [1955]: failed. + Trying to prove $equiv for \frame_payload [1956]: failed. + Trying to prove $equiv for \frame_payload [1957]: failed. + Trying to prove $equiv for \frame_payload [1958]: failed. + Trying to prove $equiv for \frame_payload [1959]: failed. + Trying to prove $equiv for \frame_payload [1960]: failed. + Trying to prove $equiv for \frame_payload [1961]: failed. + Trying to prove $equiv for \frame_payload [1962]: failed. + Trying to prove $equiv for \frame_payload [1963]: failed. + Trying to prove $equiv for \frame_payload [1964]: failed. + Trying to prove $equiv for \frame_payload [1965]: failed. + Trying to prove $equiv for \frame_payload [1966]: failed. + Trying to prove $equiv for \frame_payload [1967]: failed. + Trying to prove $equiv for \frame_payload [1968]: failed. + Trying to prove $equiv for \frame_payload [1969]: failed. + Trying to prove $equiv for \frame_payload [1970]: failed. + Trying to prove $equiv for \frame_payload [1971]: failed. + Trying to prove $equiv for \frame_payload [1972]: failed. + Trying to prove $equiv for \frame_payload [1973]: failed. + Trying to prove $equiv for \frame_payload [1974]: failed. + Trying to prove $equiv for \frame_payload [1975]: failed. + Trying to prove $equiv for \frame_payload [1976]: failed. + Trying to prove $equiv for \frame_payload [1977]: failed. + Trying to prove $equiv for \frame_payload [1978]: failed. + Trying to prove $equiv for \frame_payload [1979]: failed. + Trying to prove $equiv for \frame_payload [1980]: failed. + Trying to prove $equiv for \frame_payload [1981]: failed. + Trying to prove $equiv for \frame_payload [1982]: failed. + Trying to prove $equiv for \frame_payload [1983]: failed. + Trying to prove $equiv for \frame_payload [1984]: failed. + Trying to prove $equiv for \frame_payload [1985]: failed. + Trying to prove $equiv for \frame_payload [1986]: failed. + Trying to prove $equiv for \frame_payload [1987]: failed. + Trying to prove $equiv for \frame_payload [1988]: failed. + Trying to prove $equiv for \frame_payload [1989]: failed. + Trying to prove $equiv for \frame_payload [1990]: failed. + Trying to prove $equiv for \frame_payload [1991]: failed. + Trying to prove $equiv for \frame_payload [1992]: failed. + Trying to prove $equiv for \frame_payload [1993]: failed. + Trying to prove $equiv for \frame_payload [1994]: failed. + Trying to prove $equiv for \frame_payload [1995]: failed. + Trying to prove $equiv for \frame_payload [1996]: failed. + Trying to prove $equiv for \frame_payload [1997]: failed. + Trying to prove $equiv for \frame_payload [1998]: failed. + Trying to prove $equiv for \frame_payload [1999]: failed. + Trying to prove $equiv for \frame_payload [2000]: failed. + Trying to prove $equiv for \frame_payload [2001]: failed. + Trying to prove $equiv for \frame_payload [2002]: failed. + Trying to prove $equiv for \frame_payload [2003]: failed. + Trying to prove $equiv for \frame_payload [2004]: failed. + Trying to prove $equiv for \frame_payload [2005]: failed. + Trying to prove $equiv for \frame_payload [2006]: failed. + Trying to prove $equiv for \frame_payload [2007]: failed. + Trying to prove $equiv for \frame_payload [2008]: failed. + Trying to prove $equiv for \frame_payload [2009]: failed. + Trying to prove $equiv for \frame_payload [2010]: failed. + Trying to prove $equiv for \frame_payload [2011]: failed. + Trying to prove $equiv for \frame_payload [2012]: failed. + Trying to prove $equiv for \frame_payload [2013]: failed. + Trying to prove $equiv for \frame_payload [2014]: failed. + Trying to prove $equiv for \frame_payload [2015]: failed. + Trying to prove $equiv for \frame_payload [2016]: failed. + Trying to prove $equiv for \frame_payload [2017]: failed. + Trying to prove $equiv for \frame_payload [2018]: failed. + Trying to prove $equiv for \frame_payload [2019]: failed. + Trying to prove $equiv for \frame_payload [2020]: failed. + Trying to prove $equiv for \frame_payload [2021]: failed. + Trying to prove $equiv for \frame_payload [2022]: failed. + Trying to prove $equiv for \frame_payload [2023]: failed. + Trying to prove $equiv for \frame_payload [2024]: failed. + Trying to prove $equiv for \frame_payload [2025]: failed. + Trying to prove $equiv for \frame_payload [2026]: failed. + Trying to prove $equiv for \frame_payload [2027]: failed. + Trying to prove $equiv for \frame_payload [2028]: failed. + Trying to prove $equiv for \frame_payload [2029]: failed. + Trying to prove $equiv for \frame_payload [2030]: failed. + Trying to prove $equiv for \frame_payload [2031]: failed. + Trying to prove $equiv for \frame_payload [2032]: failed. + Trying to prove $equiv for \frame_payload [2033]: failed. + Trying to prove $equiv for \frame_payload [2034]: failed. + Trying to prove $equiv for \frame_payload [2035]: failed. + Trying to prove $equiv for \frame_payload [2036]: failed. + Trying to prove $equiv for \frame_payload [2037]: failed. + Trying to prove $equiv for \frame_payload [2038]: failed. + Trying to prove $equiv for \frame_payload [2039]: failed. + Trying to prove $equiv for \frame_payload [2040]: failed. + Trying to prove $equiv for \frame_payload [2041]: failed. + Trying to prove $equiv for \frame_payload [2042]: failed. + Trying to prove $equiv for \frame_payload [2043]: failed. + Trying to prove $equiv for \frame_payload [2044]: failed. + Trying to prove $equiv for \frame_payload [2045]: failed. + Trying to prove $equiv for \frame_payload [2046]: failed. + Trying to prove $equiv for \frame_payload [2047]: failed. + Trying to prove $equiv for \busy: failed. + Trying to prove $equiv for \done_pulse: failed. + Grouping SAT models for \tx_data: + Trying to prove $equiv for \tx_data [0]: failed. + Trying to prove $equiv for \tx_data [1]: failed. + Trying to prove $equiv for \tx_data [2]: failed. + Trying to prove $equiv for \tx_data [3]: failed. + Trying to prove $equiv for \tx_data [4]: failed. + Trying to prove $equiv for \tx_data [5]: failed. + Trying to prove $equiv for \tx_data [6]: failed. + Trying to prove $equiv for \tx_data [7]: failed. + Trying to prove $equiv for \tx_valid: failed. + Trying to prove $equiv for \fault: failed. + Trying to prove $equiv for \rx_fault_valid: failed. + Trying to prove $equiv for \parser_rx_ready: failed. + Trying to prove $equiv for \rx_busy: failed. + Grouping SAT models for \rx_fault_status: + Trying to prove $equiv for \rx_fault_status [0]: failed. + Trying to prove $equiv for \rx_fault_status [1]: failed. + Trying to prove $equiv for \rx_fault_status [2]: failed. + Trying to prove $equiv for \rx_fault_status [3]: failed. + Trying to prove $equiv for \rx_fault_status [4]: failed. + Trying to prove $equiv for \rx_fault_status [5]: failed. + Trying to prove $equiv for \rx_fault_status [6]: failed. + Trying to prove $equiv for \rx_fault_status [7]: failed. + Trying to prove $equiv for \tx_busy: failed. + Trying to prove $equiv for \tx_done: failed. + Grouping SAT models for \tx_payload_crc: + Trying to prove $equiv for \tx_payload_crc [0]: failed. + Trying to prove $equiv for \tx_payload_crc [1]: failed. + Trying to prove $equiv for \tx_payload_crc [2]: failed. + Trying to prove $equiv for \tx_payload_crc [3]: failed. + Trying to prove $equiv for \tx_payload_crc [4]: failed. + Trying to prove $equiv for \tx_payload_crc [5]: failed. + Trying to prove $equiv for \tx_payload_crc [6]: failed. + Trying to prove $equiv for \tx_payload_crc [7]: failed. + Trying to prove $equiv for \tx_payload_crc [8]: failed. + Trying to prove $equiv for \tx_payload_crc [9]: failed. + Trying to prove $equiv for \tx_payload_crc [10]: failed. + Trying to prove $equiv for \tx_payload_crc [11]: failed. + Trying to prove $equiv for \tx_payload_crc [12]: failed. + Trying to prove $equiv for \tx_payload_crc [13]: failed. + Trying to prove $equiv for \tx_payload_crc [14]: failed. + Trying to prove $equiv for \tx_payload_crc [15]: failed. + Trying to prove $equiv for \tx_payload_crc [16]: failed. + Trying to prove $equiv for \tx_payload_crc [17]: failed. + Trying to prove $equiv for \tx_payload_crc [18]: failed. + Trying to prove $equiv for \tx_payload_crc [19]: failed. + Trying to prove $equiv for \tx_payload_crc [20]: failed. + Trying to prove $equiv for \tx_payload_crc [21]: failed. + Trying to prove $equiv for \tx_payload_crc [22]: failed. + Trying to prove $equiv for \tx_payload_crc [23]: failed. + Trying to prove $equiv for \tx_payload_crc [24]: failed. + Trying to prove $equiv for \tx_payload_crc [25]: failed. + Trying to prove $equiv for \tx_payload_crc [26]: failed. + Trying to prove $equiv for \tx_payload_crc [27]: failed. + Trying to prove $equiv for \tx_payload_crc [28]: failed. + Trying to prove $equiv for \tx_payload_crc [29]: failed. + Trying to prove $equiv for \tx_payload_crc [30]: failed. + Trying to prove $equiv for \tx_payload_crc [31]: failed. + Trying to prove $equiv for \tx_start: failed. + Grouping SAT models for \tx_status: + Trying to prove $equiv for \tx_status [0]: failed. + Trying to prove $equiv for \tx_status [1]: failed. + Trying to prove $equiv for \tx_status [2]: failed. + Trying to prove $equiv for \tx_status [3]: failed. + Trying to prove $equiv for \tx_status [4]: failed. + Trying to prove $equiv for \tx_status [5]: failed. + Trying to prove $equiv for \tx_status [6]: failed. + Trying to prove $equiv for \tx_status [7]: failed. + Grouping SAT models for \tx_length: + Trying to prove $equiv for \tx_length [0]: failed. + Trying to prove $equiv for \tx_length [1]: failed. + Trying to prove $equiv for \tx_length [2]: failed. + Trying to prove $equiv for \tx_length [3]: failed. + Trying to prove $equiv for \tx_length [4]: failed. + Trying to prove $equiv for \tx_length [5]: failed. + Trying to prove $equiv for \tx_length [6]: failed. + Trying to prove $equiv for \tx_length [7]: failed. + Trying to prove $equiv for \tx_length [8]: failed. + Trying to prove $equiv for \tx_length [9]: failed. + Trying to prove $equiv for \tx_length [10]: failed. + Trying to prove $equiv for \tx_length [11]: failed. + Trying to prove $equiv for \tx_length [12]: failed. + Trying to prove $equiv for \tx_length [13]: failed. + Trying to prove $equiv for \tx_length [14]: failed. + Trying to prove $equiv for \tx_length [15]: failed. + Grouping SAT models for \tx_payload: + Trying to prove $equiv for \tx_payload [0]: failed. + Trying to prove $equiv for \tx_payload [1]: failed. + Trying to prove $equiv for \tx_payload [2]: failed. + Trying to prove $equiv for \tx_payload [3]: failed. + Trying to prove $equiv for \tx_payload [4]: failed. + Trying to prove $equiv for \tx_payload [5]: failed. + Trying to prove $equiv for \tx_payload [6]: failed. + Trying to prove $equiv for \tx_payload [7]: failed. + Trying to prove $equiv for \tx_payload [8]: failed. + Trying to prove $equiv for \tx_payload [9]: failed. + Trying to prove $equiv for \tx_payload [10]: failed. + Trying to prove $equiv for \tx_payload [11]: failed. + Trying to prove $equiv for \tx_payload [12]: failed. + Trying to prove $equiv for \tx_payload [13]: failed. + Trying to prove $equiv for \tx_payload [14]: failed. + Trying to prove $equiv for \tx_payload [15]: failed. + Trying to prove $equiv for \tx_payload [16]: failed. + Trying to prove $equiv for \tx_payload [17]: failed. + Trying to prove $equiv for \tx_payload [18]: failed. + Trying to prove $equiv for \tx_payload [19]: failed. + Trying to prove $equiv for \tx_payload [20]: failed. + Trying to prove $equiv for \tx_payload [21]: failed. + Trying to prove $equiv for \tx_payload [22]: failed. + Trying to prove $equiv for \tx_payload [23]: failed. + Trying to prove $equiv for \tx_payload [24]: failed. + Trying to prove $equiv for \tx_payload [25]: failed. + Trying to prove $equiv for \tx_payload [26]: failed. + Trying to prove $equiv for \tx_payload [27]: failed. + Trying to prove $equiv for \tx_payload [28]: failed. + Trying to prove $equiv for \tx_payload [29]: failed. + Trying to prove $equiv for \tx_payload [30]: failed. + Trying to prove $equiv for \tx_payload [31]: failed. + Trying to prove $equiv for \tx_payload [32]: failed. + Trying to prove $equiv for \tx_payload [33]: failed. + Trying to prove $equiv for \tx_payload [34]: failed. + Trying to prove $equiv for \tx_payload [35]: failed. + Trying to prove $equiv for \tx_payload [36]: failed. + Trying to prove $equiv for \tx_payload [37]: failed. + Trying to prove $equiv for \tx_payload [38]: failed. + Trying to prove $equiv for \tx_payload [39]: failed. + Trying to prove $equiv for \tx_payload [40]: failed. + Trying to prove $equiv for \tx_payload [41]: failed. + Trying to prove $equiv for \tx_payload [42]: failed. + Trying to prove $equiv for \tx_payload [43]: failed. + Trying to prove $equiv for \tx_payload [44]: failed. + Trying to prove $equiv for \tx_payload [45]: failed. + Trying to prove $equiv for \tx_payload [46]: failed. + Trying to prove $equiv for \tx_payload [47]: failed. + Trying to prove $equiv for \tx_payload [48]: failed. + Trying to prove $equiv for \tx_payload [49]: failed. + Trying to prove $equiv for \tx_payload [50]: failed. + Trying to prove $equiv for \tx_payload [51]: failed. + Trying to prove $equiv for \tx_payload [52]: failed. + Trying to prove $equiv for \tx_payload [53]: failed. + Trying to prove $equiv for \tx_payload [54]: failed. + Trying to prove $equiv for \tx_payload [55]: failed. + Trying to prove $equiv for \tx_payload [56]: failed. + Trying to prove $equiv for \tx_payload [57]: failed. + Trying to prove $equiv for \tx_payload [58]: failed. + Trying to prove $equiv for \tx_payload [59]: failed. + Trying to prove $equiv for \tx_payload [60]: failed. + Trying to prove $equiv for \tx_payload [61]: failed. + Trying to prove $equiv for \tx_payload [62]: failed. + Trying to prove $equiv for \tx_payload [63]: failed. + Trying to prove $equiv for \tx_payload [64]: failed. + Trying to prove $equiv for \tx_payload [65]: failed. + Trying to prove $equiv for \tx_payload [66]: failed. + Trying to prove $equiv for \tx_payload [67]: failed. + Trying to prove $equiv for \tx_payload [68]: failed. + Trying to prove $equiv for \tx_payload [69]: failed. + Trying to prove $equiv for \tx_payload [70]: failed. + Trying to prove $equiv for \tx_payload [71]: failed. + Trying to prove $equiv for \tx_payload [72]: failed. + Trying to prove $equiv for \tx_payload [73]: failed. + Trying to prove $equiv for \tx_payload [74]: failed. + Trying to prove $equiv for \tx_payload [75]: failed. + Trying to prove $equiv for \tx_payload [76]: failed. + Trying to prove $equiv for \tx_payload [77]: failed. + Trying to prove $equiv for \tx_payload [78]: failed. + Trying to prove $equiv for \tx_payload [79]: failed. + Trying to prove $equiv for \tx_payload [80]: failed. + Trying to prove $equiv for \tx_payload [81]: failed. + Trying to prove $equiv for \tx_payload [82]: failed. + Trying to prove $equiv for \tx_payload [83]: failed. + Trying to prove $equiv for \tx_payload [84]: failed. + Trying to prove $equiv for \tx_payload [85]: failed. + Trying to prove $equiv for \tx_payload [86]: failed. + Trying to prove $equiv for \tx_payload [87]: failed. + Trying to prove $equiv for \tx_payload [88]: failed. + Trying to prove $equiv for \tx_payload [89]: failed. + Trying to prove $equiv for \tx_payload [90]: failed. + Trying to prove $equiv for \tx_payload [91]: failed. + Trying to prove $equiv for \tx_payload [92]: failed. + Trying to prove $equiv for \tx_payload [93]: failed. + Trying to prove $equiv for \tx_payload [94]: failed. + Trying to prove $equiv for \tx_payload [95]: failed. + Trying to prove $equiv for \tx_payload [96]: failed. + Trying to prove $equiv for \tx_payload [97]: failed. + Trying to prove $equiv for \tx_payload [98]: failed. + Trying to prove $equiv for \tx_payload [99]: failed. + Trying to prove $equiv for \tx_payload [100]: failed. + Trying to prove $equiv for \tx_payload [101]: failed. + Trying to prove $equiv for \tx_payload [102]: failed. + Trying to prove $equiv for \tx_payload [103]: failed. + Trying to prove $equiv for \tx_payload [104]: failed. + Trying to prove $equiv for \tx_payload [105]: failed. + Trying to prove $equiv for \tx_payload [106]: failed. + Trying to prove $equiv for \tx_payload [107]: failed. + Trying to prove $equiv for \tx_payload [108]: failed. + Trying to prove $equiv for \tx_payload [109]: failed. + Trying to prove $equiv for \tx_payload [110]: failed. + Trying to prove $equiv for \tx_payload [111]: failed. + Trying to prove $equiv for \tx_payload [112]: failed. + Trying to prove $equiv for \tx_payload [113]: failed. + Trying to prove $equiv for \tx_payload [114]: failed. + Trying to prove $equiv for \tx_payload [115]: failed. + Trying to prove $equiv for \tx_payload [116]: failed. + Trying to prove $equiv for \tx_payload [117]: failed. + Trying to prove $equiv for \tx_payload [118]: failed. + Trying to prove $equiv for \tx_payload [119]: failed. + Trying to prove $equiv for \tx_payload [120]: failed. + Trying to prove $equiv for \tx_payload [121]: failed. + Trying to prove $equiv for \tx_payload [122]: failed. + Trying to prove $equiv for \tx_payload [123]: failed. + Trying to prove $equiv for \tx_payload [124]: failed. + Trying to prove $equiv for \tx_payload [125]: failed. + Trying to prove $equiv for \tx_payload [126]: failed. + Trying to prove $equiv for \tx_payload [127]: failed. + Trying to prove $equiv for \tx_payload [128]: failed. + Trying to prove $equiv for \tx_payload [129]: failed. + Trying to prove $equiv for \tx_payload [130]: failed. + Trying to prove $equiv for \tx_payload [131]: failed. + Trying to prove $equiv for \tx_payload [132]: failed. + Trying to prove $equiv for \tx_payload [133]: failed. + Trying to prove $equiv for \tx_payload [134]: failed. + Trying to prove $equiv for \tx_payload [135]: failed. + Trying to prove $equiv for \tx_payload [136]: failed. + Trying to prove $equiv for \tx_payload [137]: failed. + Trying to prove $equiv for \tx_payload [138]: failed. + Trying to prove $equiv for \tx_payload [139]: failed. + Trying to prove $equiv for \tx_payload [140]: failed. + Trying to prove $equiv for \tx_payload [141]: failed. + Trying to prove $equiv for \tx_payload [142]: failed. + Trying to prove $equiv for \tx_payload [143]: failed. + Trying to prove $equiv for \tx_payload [144]: failed. + Trying to prove $equiv for \tx_payload [145]: failed. + Trying to prove $equiv for \tx_payload [146]: failed. + Trying to prove $equiv for \tx_payload [147]: failed. + Trying to prove $equiv for \tx_payload [148]: failed. + Trying to prove $equiv for \tx_payload [149]: failed. + Trying to prove $equiv for \tx_payload [150]: failed. + Trying to prove $equiv for \tx_payload [151]: failed. + Trying to prove $equiv for \tx_payload [152]: failed. + Trying to prove $equiv for \tx_payload [153]: failed. + Trying to prove $equiv for \tx_payload [154]: failed. + Trying to prove $equiv for \tx_payload [155]: failed. + Trying to prove $equiv for \tx_payload [156]: failed. + Trying to prove $equiv for \tx_payload [157]: failed. + Trying to prove $equiv for \tx_payload [158]: failed. + Trying to prove $equiv for \tx_payload [159]: failed. + Trying to prove $equiv for \tx_payload [160]: failed. + Trying to prove $equiv for \tx_payload [161]: failed. + Trying to prove $equiv for \tx_payload [162]: failed. + Trying to prove $equiv for \tx_payload [163]: failed. + Trying to prove $equiv for \tx_payload [164]: failed. + Trying to prove $equiv for \tx_payload [165]: failed. + Trying to prove $equiv for \tx_payload [166]: failed. + Trying to prove $equiv for \tx_payload [167]: failed. + Trying to prove $equiv for \tx_payload [168]: failed. + Trying to prove $equiv for \tx_payload [169]: failed. + Trying to prove $equiv for \tx_payload [170]: failed. + Trying to prove $equiv for \tx_payload [171]: failed. + Trying to prove $equiv for \tx_payload [172]: failed. + Trying to prove $equiv for \tx_payload [173]: failed. + Trying to prove $equiv for \tx_payload [174]: failed. + Trying to prove $equiv for \tx_payload [175]: failed. + Trying to prove $equiv for \tx_payload [176]: failed. + Trying to prove $equiv for \tx_payload [177]: failed. + Trying to prove $equiv for \tx_payload [178]: failed. + Trying to prove $equiv for \tx_payload [179]: failed. + Trying to prove $equiv for \tx_payload [180]: failed. + Trying to prove $equiv for \tx_payload [181]: failed. + Trying to prove $equiv for \tx_payload [182]: failed. + Trying to prove $equiv for \tx_payload [183]: failed. + Trying to prove $equiv for \tx_payload [184]: failed. + Trying to prove $equiv for \tx_payload [185]: failed. + Trying to prove $equiv for \tx_payload [186]: failed. + Trying to prove $equiv for \tx_payload [187]: failed. + Trying to prove $equiv for \tx_payload [188]: failed. + Trying to prove $equiv for \tx_payload [189]: failed. + Trying to prove $equiv for \tx_payload [190]: failed. + Trying to prove $equiv for \tx_payload [191]: failed. + Trying to prove $equiv for \tx_payload [192]: failed. + Trying to prove $equiv for \tx_payload [193]: failed. + Trying to prove $equiv for \tx_payload [194]: failed. + Trying to prove $equiv for \tx_payload [195]: failed. + Trying to prove $equiv for \tx_payload [196]: failed. + Trying to prove $equiv for \tx_payload [197]: failed. + Trying to prove $equiv for \tx_payload [198]: failed. + Trying to prove $equiv for \tx_payload [199]: failed. + Trying to prove $equiv for \tx_payload [200]: failed. + Trying to prove $equiv for \tx_payload [201]: failed. + Trying to prove $equiv for \tx_payload [202]: failed. + Trying to prove $equiv for \tx_payload [203]: failed. + Trying to prove $equiv for \tx_payload [204]: failed. + Trying to prove $equiv for \tx_payload [205]: failed. + Trying to prove $equiv for \tx_payload [206]: failed. + Trying to prove $equiv for \tx_payload [207]: failed. + Trying to prove $equiv for \tx_payload [208]: failed. + Trying to prove $equiv for \tx_payload [209]: failed. + Trying to prove $equiv for \tx_payload [210]: failed. + Trying to prove $equiv for \tx_payload [211]: failed. + Trying to prove $equiv for \tx_payload [212]: failed. + Trying to prove $equiv for \tx_payload [213]: failed. + Trying to prove $equiv for \tx_payload [214]: failed. + Trying to prove $equiv for \tx_payload [215]: failed. + Trying to prove $equiv for \tx_payload [216]: failed. + Trying to prove $equiv for \tx_payload [217]: failed. + Trying to prove $equiv for \tx_payload [218]: failed. + Trying to prove $equiv for \tx_payload [219]: failed. + Trying to prove $equiv for \tx_payload [220]: failed. + Trying to prove $equiv for \tx_payload [221]: failed. + Trying to prove $equiv for \tx_payload [222]: failed. + Trying to prove $equiv for \tx_payload [223]: failed. + Trying to prove $equiv for \tx_payload [224]: failed. + Trying to prove $equiv for \tx_payload [225]: failed. + Trying to prove $equiv for \tx_payload [226]: failed. + Trying to prove $equiv for \tx_payload [227]: failed. + Trying to prove $equiv for \tx_payload [228]: failed. + Trying to prove $equiv for \tx_payload [229]: failed. + Trying to prove $equiv for \tx_payload [230]: failed. + Trying to prove $equiv for \tx_payload [231]: failed. + Trying to prove $equiv for \tx_payload [232]: failed. + Trying to prove $equiv for \tx_payload [233]: failed. + Trying to prove $equiv for \tx_payload [234]: failed. + Trying to prove $equiv for \tx_payload [235]: failed. + Trying to prove $equiv for \tx_payload [236]: failed. + Trying to prove $equiv for \tx_payload [237]: failed. + Trying to prove $equiv for \tx_payload [238]: failed. + Trying to prove $equiv for \tx_payload [239]: failed. + Trying to prove $equiv for \tx_payload [240]: failed. + Trying to prove $equiv for \tx_payload [241]: failed. + Trying to prove $equiv for \tx_payload [242]: failed. + Trying to prove $equiv for \tx_payload [243]: failed. + Trying to prove $equiv for \tx_payload [244]: failed. + Trying to prove $equiv for \tx_payload [245]: failed. + Trying to prove $equiv for \tx_payload [246]: failed. + Trying to prove $equiv for \tx_payload [247]: failed. + Trying to prove $equiv for \tx_payload [248]: failed. + Trying to prove $equiv for \tx_payload [249]: failed. + Trying to prove $equiv for \tx_payload [250]: failed. + Trying to prove $equiv for \tx_payload [251]: failed. + Trying to prove $equiv for \tx_payload [252]: failed. + Trying to prove $equiv for \tx_payload [253]: failed. + Trying to prove $equiv for \tx_payload [254]: failed. + Trying to prove $equiv for \tx_payload [255]: failed. + Trying to prove $equiv for \tx_payload [256]: failed. + Trying to prove $equiv for \tx_payload [257]: failed. + Trying to prove $equiv for \tx_payload [258]: failed. + Trying to prove $equiv for \tx_payload [259]: failed. + Trying to prove $equiv for \tx_payload [260]: failed. + Trying to prove $equiv for \tx_payload [261]: failed. + Trying to prove $equiv for \tx_payload [262]: failed. + Trying to prove $equiv for \tx_payload [263]: failed. + Trying to prove $equiv for \tx_payload [264]: failed. + Trying to prove $equiv for \tx_payload [265]: failed. + Trying to prove $equiv for \tx_payload [266]: failed. + Trying to prove $equiv for \tx_payload [267]: failed. + Trying to prove $equiv for \tx_payload [268]: failed. + Trying to prove $equiv for \tx_payload [269]: failed. + Trying to prove $equiv for \tx_payload [270]: failed. + Trying to prove $equiv for \tx_payload [271]: failed. + Trying to prove $equiv for \tx_payload [272]: failed. + Trying to prove $equiv for \tx_payload [273]: failed. + Trying to prove $equiv for \tx_payload [274]: failed. + Trying to prove $equiv for \tx_payload [275]: failed. + Trying to prove $equiv for \tx_payload [276]: failed. + Trying to prove $equiv for \tx_payload [277]: failed. + Trying to prove $equiv for \tx_payload [278]: failed. + Trying to prove $equiv for \tx_payload [279]: failed. + Trying to prove $equiv for \tx_payload [280]: failed. + Trying to prove $equiv for \tx_payload [281]: failed. + Trying to prove $equiv for \tx_payload [282]: failed. + Trying to prove $equiv for \tx_payload [283]: failed. + Trying to prove $equiv for \tx_payload [284]: failed. + Trying to prove $equiv for \tx_payload [285]: failed. + Trying to prove $equiv for \tx_payload [286]: failed. + Trying to prove $equiv for \tx_payload [287]: failed. + Trying to prove $equiv for \tx_payload [288]: failed. + Trying to prove $equiv for \tx_payload [289]: failed. + Trying to prove $equiv for \tx_payload [290]: failed. + Trying to prove $equiv for \tx_payload [291]: failed. + Trying to prove $equiv for \tx_payload [292]: failed. + Trying to prove $equiv for \tx_payload [293]: failed. + Trying to prove $equiv for \tx_payload [294]: failed. + Trying to prove $equiv for \tx_payload [295]: failed. + Trying to prove $equiv for \tx_payload [296]: failed. + Trying to prove $equiv for \tx_payload [297]: failed. + Trying to prove $equiv for \tx_payload [298]: failed. + Trying to prove $equiv for \tx_payload [299]: failed. + Trying to prove $equiv for \tx_payload [300]: failed. + Trying to prove $equiv for \tx_payload [301]: failed. + Trying to prove $equiv for \tx_payload [302]: failed. + Trying to prove $equiv for \tx_payload [303]: failed. + Trying to prove $equiv for \tx_payload [304]: failed. + Trying to prove $equiv for \tx_payload [305]: failed. + Trying to prove $equiv for \tx_payload [306]: failed. + Trying to prove $equiv for \tx_payload [307]: failed. + Trying to prove $equiv for \tx_payload [308]: failed. + Trying to prove $equiv for \tx_payload [309]: failed. + Trying to prove $equiv for \tx_payload [310]: failed. + Trying to prove $equiv for \tx_payload [311]: failed. + Trying to prove $equiv for \tx_payload [312]: failed. + Trying to prove $equiv for \tx_payload [313]: failed. + Trying to prove $equiv for \tx_payload [314]: failed. + Trying to prove $equiv for \tx_payload [315]: failed. + Trying to prove $equiv for \tx_payload [316]: failed. + Trying to prove $equiv for \tx_payload [317]: failed. + Trying to prove $equiv for \tx_payload [318]: failed. + Trying to prove $equiv for \tx_payload [319]: failed. + Trying to prove $equiv for \tx_payload [320]: failed. + Trying to prove $equiv for \tx_payload [321]: failed. + Trying to prove $equiv for \tx_payload [322]: failed. + Trying to prove $equiv for \tx_payload [323]: failed. + Trying to prove $equiv for \tx_payload [324]: failed. + Trying to prove $equiv for \tx_payload [325]: failed. + Trying to prove $equiv for \tx_payload [326]: failed. + Trying to prove $equiv for \tx_payload [327]: failed. + Trying to prove $equiv for \tx_payload [328]: failed. + Trying to prove $equiv for \tx_payload [329]: failed. + Trying to prove $equiv for \tx_payload [330]: failed. + Trying to prove $equiv for \tx_payload [331]: failed. + Trying to prove $equiv for \tx_payload [332]: failed. + Trying to prove $equiv for \tx_payload [333]: failed. + Trying to prove $equiv for \tx_payload [334]: failed. + Trying to prove $equiv for \tx_payload [335]: failed. + Trying to prove $equiv for \tx_payload [336]: failed. + Trying to prove $equiv for \tx_payload [337]: failed. + Trying to prove $equiv for \tx_payload [338]: failed. + Trying to prove $equiv for \tx_payload [339]: failed. + Trying to prove $equiv for \tx_payload [340]: failed. + Trying to prove $equiv for \tx_payload [341]: failed. + Trying to prove $equiv for \tx_payload [342]: failed. + Trying to prove $equiv for \tx_payload [343]: failed. + Trying to prove $equiv for \tx_payload [344]: failed. + Trying to prove $equiv for \tx_payload [345]: failed. + Trying to prove $equiv for \tx_payload [346]: failed. + Trying to prove $equiv for \tx_payload [347]: failed. + Trying to prove $equiv for \tx_payload [348]: failed. + Trying to prove $equiv for \tx_payload [349]: failed. + Trying to prove $equiv for \tx_payload [350]: failed. + Trying to prove $equiv for \tx_payload [351]: failed. + Trying to prove $equiv for \tx_payload [352]: failed. + Trying to prove $equiv for \tx_payload [353]: failed. + Trying to prove $equiv for \tx_payload [354]: failed. + Trying to prove $equiv for \tx_payload [355]: failed. + Trying to prove $equiv for \tx_payload [356]: failed. + Trying to prove $equiv for \tx_payload [357]: failed. + Trying to prove $equiv for \tx_payload [358]: failed. + Trying to prove $equiv for \tx_payload [359]: failed. + Trying to prove $equiv for \tx_payload [360]: failed. + Trying to prove $equiv for \tx_payload [361]: failed. + Trying to prove $equiv for \tx_payload [362]: failed. + Trying to prove $equiv for \tx_payload [363]: failed. + Trying to prove $equiv for \tx_payload [364]: failed. + Trying to prove $equiv for \tx_payload [365]: failed. + Trying to prove $equiv for \tx_payload [366]: failed. + Trying to prove $equiv for \tx_payload [367]: failed. + Trying to prove $equiv for \tx_payload [368]: failed. + Trying to prove $equiv for \tx_payload [369]: failed. + Trying to prove $equiv for \tx_payload [370]: failed. + Trying to prove $equiv for \tx_payload [371]: failed. + Trying to prove $equiv for \tx_payload [372]: failed. + Trying to prove $equiv for \tx_payload [373]: failed. + Trying to prove $equiv for \tx_payload [374]: failed. + Trying to prove $equiv for \tx_payload [375]: failed. + Trying to prove $equiv for \tx_payload [376]: failed. + Trying to prove $equiv for \tx_payload [377]: failed. + Trying to prove $equiv for \tx_payload [378]: failed. + Trying to prove $equiv for \tx_payload [379]: failed. + Trying to prove $equiv for \tx_payload [380]: failed. + Trying to prove $equiv for \tx_payload [381]: failed. + Trying to prove $equiv for \tx_payload [382]: failed. + Trying to prove $equiv for \tx_payload [383]: failed. + Trying to prove $equiv for \tx_payload [384]: failed. + Trying to prove $equiv for \tx_payload [385]: failed. + Trying to prove $equiv for \tx_payload [386]: failed. + Trying to prove $equiv for \tx_payload [387]: failed. + Trying to prove $equiv for \tx_payload [388]: failed. + Trying to prove $equiv for \tx_payload [389]: failed. + Trying to prove $equiv for \tx_payload [390]: failed. + Trying to prove $equiv for \tx_payload [391]: failed. + Trying to prove $equiv for \tx_payload [392]: failed. + Trying to prove $equiv for \tx_payload [393]: failed. + Trying to prove $equiv for \tx_payload [394]: failed. + Trying to prove $equiv for \tx_payload [395]: failed. + Trying to prove $equiv for \tx_payload [396]: failed. + Trying to prove $equiv for \tx_payload [397]: failed. + Trying to prove $equiv for \tx_payload [398]: failed. + Trying to prove $equiv for \tx_payload [399]: failed. + Trying to prove $equiv for \tx_payload [400]: failed. + Trying to prove $equiv for \tx_payload [401]: failed. + Trying to prove $equiv for \tx_payload [402]: failed. + Trying to prove $equiv for \tx_payload [403]: failed. + Trying to prove $equiv for \tx_payload [404]: failed. + Trying to prove $equiv for \tx_payload [405]: failed. + Trying to prove $equiv for \tx_payload [406]: failed. + Trying to prove $equiv for \tx_payload [407]: failed. + Trying to prove $equiv for \tx_payload [408]: failed. + Trying to prove $equiv for \tx_payload [409]: failed. + Trying to prove $equiv for \tx_payload [410]: failed. + Trying to prove $equiv for \tx_payload [411]: failed. + Trying to prove $equiv for \tx_payload [412]: failed. + Trying to prove $equiv for \tx_payload [413]: failed. + Trying to prove $equiv for \tx_payload [414]: failed. + Trying to prove $equiv for \tx_payload [415]: failed. + Trying to prove $equiv for \tx_payload [416]: failed. + Trying to prove $equiv for \tx_payload [417]: failed. + Trying to prove $equiv for \tx_payload [418]: failed. + Trying to prove $equiv for \tx_payload [419]: failed. + Trying to prove $equiv for \tx_payload [420]: failed. + Trying to prove $equiv for \tx_payload [421]: failed. + Trying to prove $equiv for \tx_payload [422]: failed. + Trying to prove $equiv for \tx_payload [423]: failed. + Trying to prove $equiv for \tx_payload [424]: failed. + Trying to prove $equiv for \tx_payload [425]: failed. + Trying to prove $equiv for \tx_payload [426]: failed. + Trying to prove $equiv for \tx_payload [427]: failed. + Trying to prove $equiv for \tx_payload [428]: failed. + Trying to prove $equiv for \tx_payload [429]: failed. + Trying to prove $equiv for \tx_payload [430]: failed. + Trying to prove $equiv for \tx_payload [431]: failed. + Trying to prove $equiv for \tx_payload [432]: failed. + Trying to prove $equiv for \tx_payload [433]: failed. + Trying to prove $equiv for \tx_payload [434]: failed. + Trying to prove $equiv for \tx_payload [435]: failed. + Trying to prove $equiv for \tx_payload [436]: failed. + Trying to prove $equiv for \tx_payload [437]: failed. + Trying to prove $equiv for \tx_payload [438]: failed. + Trying to prove $equiv for \tx_payload [439]: failed. + Trying to prove $equiv for \tx_payload [440]: failed. + Trying to prove $equiv for \tx_payload [441]: failed. + Trying to prove $equiv for \tx_payload [442]: failed. + Trying to prove $equiv for \tx_payload [443]: failed. + Trying to prove $equiv for \tx_payload [444]: failed. + Trying to prove $equiv for \tx_payload [445]: failed. + Trying to prove $equiv for \tx_payload [446]: failed. + Trying to prove $equiv for \tx_payload [447]: failed. + Trying to prove $equiv for \tx_payload [448]: failed. + Trying to prove $equiv for \tx_payload [449]: failed. + Trying to prove $equiv for \tx_payload [450]: failed. + Trying to prove $equiv for \tx_payload [451]: failed. + Trying to prove $equiv for \tx_payload [452]: failed. + Trying to prove $equiv for \tx_payload [453]: failed. + Trying to prove $equiv for \tx_payload [454]: failed. + Trying to prove $equiv for \tx_payload [455]: failed. + Trying to prove $equiv for \tx_payload [456]: failed. + Trying to prove $equiv for \tx_payload [457]: failed. + Trying to prove $equiv for \tx_payload [458]: failed. + Trying to prove $equiv for \tx_payload [459]: failed. + Trying to prove $equiv for \tx_payload [460]: failed. + Trying to prove $equiv for \tx_payload [461]: failed. + Trying to prove $equiv for \tx_payload [462]: failed. + Trying to prove $equiv for \tx_payload [463]: failed. + Trying to prove $equiv for \tx_payload [464]: failed. + Trying to prove $equiv for \tx_payload [465]: failed. + Trying to prove $equiv for \tx_payload [466]: failed. + Trying to prove $equiv for \tx_payload [467]: failed. + Trying to prove $equiv for \tx_payload [468]: failed. + Trying to prove $equiv for \tx_payload [469]: failed. + Trying to prove $equiv for \tx_payload [470]: failed. + Trying to prove $equiv for \tx_payload [471]: failed. + Trying to prove $equiv for \tx_payload [472]: failed. + Trying to prove $equiv for \tx_payload [473]: failed. + Trying to prove $equiv for \tx_payload [474]: failed. + Trying to prove $equiv for \tx_payload [475]: failed. + Trying to prove $equiv for \tx_payload [476]: failed. + Trying to prove $equiv for \tx_payload [477]: failed. + Trying to prove $equiv for \tx_payload [478]: failed. + Trying to prove $equiv for \tx_payload [479]: failed. + Trying to prove $equiv for \tx_payload [480]: failed. + Trying to prove $equiv for \tx_payload [481]: failed. + Trying to prove $equiv for \tx_payload [482]: failed. + Trying to prove $equiv for \tx_payload [483]: failed. + Trying to prove $equiv for \tx_payload [484]: failed. + Trying to prove $equiv for \tx_payload [485]: failed. + Trying to prove $equiv for \tx_payload [486]: failed. + Trying to prove $equiv for \tx_payload [487]: failed. + Trying to prove $equiv for \tx_payload [488]: failed. + Trying to prove $equiv for \tx_payload [489]: failed. + Trying to prove $equiv for \tx_payload [490]: failed. + Trying to prove $equiv for \tx_payload [491]: failed. + Trying to prove $equiv for \tx_payload [492]: failed. + Trying to prove $equiv for \tx_payload [493]: failed. + Trying to prove $equiv for \tx_payload [494]: failed. + Trying to prove $equiv for \tx_payload [495]: failed. + Trying to prove $equiv for \tx_payload [496]: failed. + Trying to prove $equiv for \tx_payload [497]: failed. + Trying to prove $equiv for \tx_payload [498]: failed. + Trying to prove $equiv for \tx_payload [499]: failed. + Trying to prove $equiv for \tx_payload [500]: failed. + Trying to prove $equiv for \tx_payload [501]: failed. + Trying to prove $equiv for \tx_payload [502]: failed. + Trying to prove $equiv for \tx_payload [503]: failed. + Trying to prove $equiv for \tx_payload [504]: failed. + Trying to prove $equiv for \tx_payload [505]: failed. + Trying to prove $equiv for \tx_payload [506]: failed. + Trying to prove $equiv for \tx_payload [507]: failed. + Trying to prove $equiv for \tx_payload [508]: failed. + Trying to prove $equiv for \tx_payload [509]: failed. + Trying to prove $equiv for \tx_payload [510]: failed. + Trying to prove $equiv for \tx_payload [511]: failed. + Trying to prove $equiv for \tx_payload [512]: failed. + Trying to prove $equiv for \tx_payload [513]: failed. + Trying to prove $equiv for \tx_payload [514]: failed. + Trying to prove $equiv for \tx_payload [515]: failed. + Trying to prove $equiv for \tx_payload [516]: failed. + Trying to prove $equiv for \tx_payload [517]: failed. + Trying to prove $equiv for \tx_payload [518]: failed. + Trying to prove $equiv for \tx_payload [519]: failed. + Trying to prove $equiv for \tx_payload [520]: failed. + Trying to prove $equiv for \tx_payload [521]: failed. + Trying to prove $equiv for \tx_payload [522]: failed. + Trying to prove $equiv for \tx_payload [523]: failed. + Trying to prove $equiv for \tx_payload [524]: failed. + Trying to prove $equiv for \tx_payload [525]: failed. + Trying to prove $equiv for \tx_payload [526]: failed. + Trying to prove $equiv for \tx_payload [527]: failed. + Trying to prove $equiv for \tx_payload [528]: failed. + Trying to prove $equiv for \tx_payload [529]: failed. + Trying to prove $equiv for \tx_payload [530]: failed. + Trying to prove $equiv for \tx_payload [531]: failed. + Trying to prove $equiv for \tx_payload [532]: failed. + Trying to prove $equiv for \tx_payload [533]: failed. + Trying to prove $equiv for \tx_payload [534]: failed. + Trying to prove $equiv for \tx_payload [535]: failed. + Trying to prove $equiv for \tx_payload [536]: failed. + Trying to prove $equiv for \tx_payload [537]: failed. + Trying to prove $equiv for \tx_payload [538]: failed. + Trying to prove $equiv for \tx_payload [539]: failed. + Trying to prove $equiv for \tx_payload [540]: failed. + Trying to prove $equiv for \tx_payload [541]: failed. + Trying to prove $equiv for \tx_payload [542]: failed. + Trying to prove $equiv for \tx_payload [543]: failed. + Trying to prove $equiv for \capture_result_crc: failed. + Grouping SAT models for \compute_state: + Trying to prove $equiv for \compute_state [0]: failed. + Trying to prove $equiv for \compute_state [1]: failed. + Trying to prove $equiv for \compute_state [2]: failed. + Trying to prove $equiv for \compute_state [3]: failed. + Trying to prove $equiv for \alu_start: failed. + Grouping SAT models for \alu_operation: + Trying to prove $equiv for \alu_operation [0]: failed. + Trying to prove $equiv for \alu_operation [1]: failed. + Trying to prove $equiv for \alu_operation [2]: failed. + Trying to prove $equiv for \alu_operation [3]: failed. + Trying to prove $equiv for \alu_operation [4]: failed. + Trying to prove $equiv for \alu_operation [5]: failed. + Trying to prove $equiv for \alu_operation [6]: failed. + Trying to prove $equiv for \alu_operation [7]: failed. + Grouping SAT models for \alu_operand_a: + Trying to prove $equiv for \alu_operand_a [0]: failed. + Trying to prove $equiv for \alu_operand_a [1]: failed. + Trying to prove $equiv for \alu_operand_a [2]: failed. + Trying to prove $equiv for \alu_operand_a [3]: failed. + Trying to prove $equiv for \alu_operand_a [4]: failed. + Trying to prove $equiv for \alu_operand_a [5]: failed. + Trying to prove $equiv for \alu_operand_a [6]: failed. + Trying to prove $equiv for \alu_operand_a [7]: failed. + Trying to prove $equiv for \alu_operand_a [8]: failed. + Trying to prove $equiv for \alu_operand_a [9]: failed. + Trying to prove $equiv for \alu_operand_a [10]: failed. + Trying to prove $equiv for \alu_operand_a [11]: failed. + Trying to prove $equiv for \alu_operand_a [12]: failed. + Trying to prove $equiv for \alu_operand_a [13]: failed. + Trying to prove $equiv for \alu_operand_a [14]: failed. + Trying to prove $equiv for \alu_operand_a [15]: failed. + Trying to prove $equiv for \alu_operand_a [16]: failed. + Trying to prove $equiv for \alu_operand_a [17]: failed. + Trying to prove $equiv for \alu_operand_a [18]: failed. + Trying to prove $equiv for \alu_operand_a [19]: failed. + Trying to prove $equiv for \alu_operand_a [20]: failed. + Trying to prove $equiv for \alu_operand_a [21]: failed. + Trying to prove $equiv for \alu_operand_a [22]: failed. + Trying to prove $equiv for \alu_operand_a [23]: failed. + Trying to prove $equiv for \alu_operand_a [24]: failed. + Trying to prove $equiv for \alu_operand_a [25]: failed. + Trying to prove $equiv for \alu_operand_a [26]: failed. + Trying to prove $equiv for \alu_operand_a [27]: failed. + Trying to prove $equiv for \alu_operand_a [28]: failed. + Trying to prove $equiv for \alu_operand_a [29]: failed. + Trying to prove $equiv for \alu_operand_a [30]: failed. + Trying to prove $equiv for \alu_operand_a [31]: failed. + Trying to prove $equiv for \alu_operand_a [32]: failed. + Trying to prove $equiv for \alu_operand_a [33]: failed. + Trying to prove $equiv for \alu_operand_a [34]: failed. + Trying to prove $equiv for \alu_operand_a [35]: failed. + Trying to prove $equiv for \alu_operand_a [36]: failed. + Trying to prove $equiv for \alu_operand_a [37]: failed. + Trying to prove $equiv for \alu_operand_a [38]: failed. + Trying to prove $equiv for \alu_operand_a [39]: failed. + Trying to prove $equiv for \alu_operand_a [40]: failed. + Trying to prove $equiv for \alu_operand_a [41]: failed. + Trying to prove $equiv for \alu_operand_a [42]: failed. + Trying to prove $equiv for \alu_operand_a [43]: failed. + Trying to prove $equiv for \alu_operand_a [44]: failed. + Trying to prove $equiv for \alu_operand_a [45]: failed. + Trying to prove $equiv for \alu_operand_a [46]: failed. + Trying to prove $equiv for \alu_operand_a [47]: failed. + Trying to prove $equiv for \alu_operand_a [48]: failed. + Trying to prove $equiv for \alu_operand_a [49]: failed. + Trying to prove $equiv for \alu_operand_a [50]: failed. + Trying to prove $equiv for \alu_operand_a [51]: failed. + Trying to prove $equiv for \alu_operand_a [52]: failed. + Trying to prove $equiv for \alu_operand_a [53]: failed. + Trying to prove $equiv for \alu_operand_a [54]: failed. + Trying to prove $equiv for \alu_operand_a [55]: failed. + Trying to prove $equiv for \alu_operand_a [56]: failed. + Trying to prove $equiv for \alu_operand_a [57]: failed. + Trying to prove $equiv for \alu_operand_a [58]: failed. + Trying to prove $equiv for \alu_operand_a [59]: failed. + Trying to prove $equiv for \alu_operand_a [60]: failed. + Trying to prove $equiv for \alu_operand_a [61]: failed. + Trying to prove $equiv for \alu_operand_a [62]: failed. + Trying to prove $equiv for \alu_operand_a [63]: failed. + Trying to prove $equiv for \alu_operand_a [64]: failed. + Trying to prove $equiv for \alu_operand_a [65]: failed. + Trying to prove $equiv for \alu_operand_a [66]: failed. + Trying to prove $equiv for \alu_operand_a [67]: failed. + Trying to prove $equiv for \alu_operand_a [68]: failed. + Trying to prove $equiv for \alu_operand_a [69]: failed. + Trying to prove $equiv for \alu_operand_a [70]: failed. + Trying to prove $equiv for \alu_operand_a [71]: failed. + Trying to prove $equiv for \alu_operand_a [72]: failed. + Trying to prove $equiv for \alu_operand_a [73]: failed. + Trying to prove $equiv for \alu_operand_a [74]: failed. + Trying to prove $equiv for \alu_operand_a [75]: failed. + Trying to prove $equiv for \alu_operand_a [76]: failed. + Trying to prove $equiv for \alu_operand_a [77]: failed. + Trying to prove $equiv for \alu_operand_a [78]: failed. + Trying to prove $equiv for \alu_operand_a [79]: failed. + Trying to prove $equiv for \alu_operand_a [80]: failed. + Trying to prove $equiv for \alu_operand_a [81]: failed. + Trying to prove $equiv for \alu_operand_a [82]: failed. + Trying to prove $equiv for \alu_operand_a [83]: failed. + Trying to prove $equiv for \alu_operand_a [84]: failed. + Trying to prove $equiv for \alu_operand_a [85]: failed. + Trying to prove $equiv for \alu_operand_a [86]: failed. + Trying to prove $equiv for \alu_operand_a [87]: failed. + Trying to prove $equiv for \alu_operand_a [88]: failed. + Trying to prove $equiv for \alu_operand_a [89]: failed. + Trying to prove $equiv for \alu_operand_a [90]: failed. + Trying to prove $equiv for \alu_operand_a [91]: failed. + Trying to prove $equiv for \alu_operand_a [92]: failed. + Trying to prove $equiv for \alu_operand_a [93]: failed. + Trying to prove $equiv for \alu_operand_a [94]: failed. + Trying to prove $equiv for \alu_operand_a [95]: failed. + Trying to prove $equiv for \alu_operand_a [96]: failed. + Trying to prove $equiv for \alu_operand_a [97]: failed. + Trying to prove $equiv for \alu_operand_a [98]: failed. + Trying to prove $equiv for \alu_operand_a [99]: failed. + Trying to prove $equiv for \alu_operand_a [100]: failed. + Trying to prove $equiv for \alu_operand_a [101]: failed. + Trying to prove $equiv for \alu_operand_a [102]: failed. + Trying to prove $equiv for \alu_operand_a [103]: failed. + Trying to prove $equiv for \alu_operand_a [104]: failed. + Trying to prove $equiv for \alu_operand_a [105]: failed. + Trying to prove $equiv for \alu_operand_a [106]: failed. + Trying to prove $equiv for \alu_operand_a [107]: failed. + Trying to prove $equiv for \alu_operand_a [108]: failed. + Trying to prove $equiv for \alu_operand_a [109]: failed. + Trying to prove $equiv for \alu_operand_a [110]: failed. + Trying to prove $equiv for \alu_operand_a [111]: failed. + Trying to prove $equiv for \alu_operand_a [112]: failed. + Trying to prove $equiv for \alu_operand_a [113]: failed. + Trying to prove $equiv for \alu_operand_a [114]: failed. + Trying to prove $equiv for \alu_operand_a [115]: failed. + Trying to prove $equiv for \alu_operand_a [116]: failed. + Trying to prove $equiv for \alu_operand_a [117]: failed. + Trying to prove $equiv for \alu_operand_a [118]: failed. + Trying to prove $equiv for \alu_operand_a [119]: failed. + Trying to prove $equiv for \alu_operand_a [120]: failed. + Trying to prove $equiv for \alu_operand_a [121]: failed. + Trying to prove $equiv for \alu_operand_a [122]: failed. + Trying to prove $equiv for \alu_operand_a [123]: failed. + Trying to prove $equiv for \alu_operand_a [124]: failed. + Trying to prove $equiv for \alu_operand_a [125]: failed. + Trying to prove $equiv for \alu_operand_a [126]: failed. + Trying to prove $equiv for \alu_operand_a [127]: failed. + Grouping SAT models for \alu_operand_b: + Trying to prove $equiv for \alu_operand_b [0]: failed. + Trying to prove $equiv for \alu_operand_b [1]: failed. + Trying to prove $equiv for \alu_operand_b [2]: failed. + Trying to prove $equiv for \alu_operand_b [3]: failed. + Trying to prove $equiv for \alu_operand_b [4]: failed. + Trying to prove $equiv for \alu_operand_b [5]: failed. + Trying to prove $equiv for \alu_operand_b [6]: failed. + Trying to prove $equiv for \alu_operand_b [7]: failed. + Trying to prove $equiv for \alu_operand_b [8]: failed. + Trying to prove $equiv for \alu_operand_b [9]: failed. + Trying to prove $equiv for \alu_operand_b [10]: failed. + Trying to prove $equiv for \alu_operand_b [11]: failed. + Trying to prove $equiv for \alu_operand_b [12]: failed. + Trying to prove $equiv for \alu_operand_b [13]: failed. + Trying to prove $equiv for \alu_operand_b [14]: failed. + Trying to prove $equiv for \alu_operand_b [15]: failed. + Trying to prove $equiv for \alu_operand_b [16]: failed. + Trying to prove $equiv for \alu_operand_b [17]: failed. + Trying to prove $equiv for \alu_operand_b [18]: failed. + Trying to prove $equiv for \alu_operand_b [19]: failed. + Trying to prove $equiv for \alu_operand_b [20]: failed. + Trying to prove $equiv for \alu_operand_b [21]: failed. + Trying to prove $equiv for \alu_operand_b [22]: failed. + Trying to prove $equiv for \alu_operand_b [23]: failed. + Trying to prove $equiv for \alu_operand_b [24]: failed. + Trying to prove $equiv for \alu_operand_b [25]: failed. + Trying to prove $equiv for \alu_operand_b [26]: failed. + Trying to prove $equiv for \alu_operand_b [27]: failed. + Trying to prove $equiv for \alu_operand_b [28]: failed. + Trying to prove $equiv for \alu_operand_b [29]: failed. + Trying to prove $equiv for \alu_operand_b [30]: failed. + Trying to prove $equiv for \alu_operand_b [31]: failed. + Trying to prove $equiv for \alu_operand_b [32]: failed. + Trying to prove $equiv for \alu_operand_b [33]: failed. + Trying to prove $equiv for \alu_operand_b [34]: failed. + Trying to prove $equiv for \alu_operand_b [35]: failed. + Trying to prove $equiv for \alu_operand_b [36]: failed. + Trying to prove $equiv for \alu_operand_b [37]: failed. + Trying to prove $equiv for \alu_operand_b [38]: failed. + Trying to prove $equiv for \alu_operand_b [39]: failed. + Trying to prove $equiv for \alu_operand_b [40]: failed. + Trying to prove $equiv for \alu_operand_b [41]: failed. + Trying to prove $equiv for \alu_operand_b [42]: failed. + Trying to prove $equiv for \alu_operand_b [43]: failed. + Trying to prove $equiv for \alu_operand_b [44]: failed. + Trying to prove $equiv for \alu_operand_b [45]: failed. + Trying to prove $equiv for \alu_operand_b [46]: failed. + Trying to prove $equiv for \alu_operand_b [47]: failed. + Trying to prove $equiv for \alu_operand_b [48]: failed. + Trying to prove $equiv for \alu_operand_b [49]: failed. + Trying to prove $equiv for \alu_operand_b [50]: failed. + Trying to prove $equiv for \alu_operand_b [51]: failed. + Trying to prove $equiv for \alu_operand_b [52]: failed. + Trying to prove $equiv for \alu_operand_b [53]: failed. + Trying to prove $equiv for \alu_operand_b [54]: failed. + Trying to prove $equiv for \alu_operand_b [55]: failed. + Trying to prove $equiv for \alu_operand_b [56]: failed. + Trying to prove $equiv for \alu_operand_b [57]: failed. + Trying to prove $equiv for \alu_operand_b [58]: failed. + Trying to prove $equiv for \alu_operand_b [59]: failed. + Trying to prove $equiv for \alu_operand_b [60]: failed. + Trying to prove $equiv for \alu_operand_b [61]: failed. + Trying to prove $equiv for \alu_operand_b [62]: failed. + Trying to prove $equiv for \alu_operand_b [63]: failed. + Trying to prove $equiv for \alu_operand_b [64]: failed. + Trying to prove $equiv for \alu_operand_b [65]: failed. + Trying to prove $equiv for \alu_operand_b [66]: failed. + Trying to prove $equiv for \alu_operand_b [67]: failed. + Trying to prove $equiv for \alu_operand_b [68]: failed. + Trying to prove $equiv for \alu_operand_b [69]: failed. + Trying to prove $equiv for \alu_operand_b [70]: failed. + Trying to prove $equiv for \alu_operand_b [71]: failed. + Trying to prove $equiv for \alu_operand_b [72]: failed. + Trying to prove $equiv for \alu_operand_b [73]: failed. + Trying to prove $equiv for \alu_operand_b [74]: failed. + Trying to prove $equiv for \alu_operand_b [75]: failed. + Trying to prove $equiv for \alu_operand_b [76]: failed. + Trying to prove $equiv for \alu_operand_b [77]: failed. + Trying to prove $equiv for \alu_operand_b [78]: failed. + Trying to prove $equiv for \alu_operand_b [79]: failed. + Trying to prove $equiv for \alu_operand_b [80]: failed. + Trying to prove $equiv for \alu_operand_b [81]: failed. + Trying to prove $equiv for \alu_operand_b [82]: failed. + Trying to prove $equiv for \alu_operand_b [83]: failed. + Trying to prove $equiv for \alu_operand_b [84]: failed. + Trying to prove $equiv for \alu_operand_b [85]: failed. + Trying to prove $equiv for \alu_operand_b [86]: failed. + Trying to prove $equiv for \alu_operand_b [87]: failed. + Trying to prove $equiv for \alu_operand_b [88]: failed. + Trying to prove $equiv for \alu_operand_b [89]: failed. + Trying to prove $equiv for \alu_operand_b [90]: failed. + Trying to prove $equiv for \alu_operand_b [91]: failed. + Trying to prove $equiv for \alu_operand_b [92]: failed. + Trying to prove $equiv for \alu_operand_b [93]: failed. + Trying to prove $equiv for \alu_operand_b [94]: failed. + Trying to prove $equiv for \alu_operand_b [95]: failed. + Trying to prove $equiv for \alu_operand_b [96]: failed. + Trying to prove $equiv for \alu_operand_b [97]: failed. + Trying to prove $equiv for \alu_operand_b [98]: failed. + Trying to prove $equiv for \alu_operand_b [99]: failed. + Trying to prove $equiv for \alu_operand_b [100]: failed. + Trying to prove $equiv for \alu_operand_b [101]: failed. + Trying to prove $equiv for \alu_operand_b [102]: failed. + Trying to prove $equiv for \alu_operand_b [103]: failed. + Trying to prove $equiv for \alu_operand_b [104]: failed. + Trying to prove $equiv for \alu_operand_b [105]: failed. + Trying to prove $equiv for \alu_operand_b [106]: failed. + Trying to prove $equiv for \alu_operand_b [107]: failed. + Trying to prove $equiv for \alu_operand_b [108]: failed. + Trying to prove $equiv for \alu_operand_b [109]: failed. + Trying to prove $equiv for \alu_operand_b [110]: failed. + Trying to prove $equiv for \alu_operand_b [111]: failed. + Trying to prove $equiv for \alu_operand_b [112]: failed. + Trying to prove $equiv for \alu_operand_b [113]: failed. + Trying to prove $equiv for \alu_operand_b [114]: failed. + Trying to prove $equiv for \alu_operand_b [115]: failed. + Trying to prove $equiv for \alu_operand_b [116]: failed. + Trying to prove $equiv for \alu_operand_b [117]: failed. + Trying to prove $equiv for \alu_operand_b [118]: failed. + Trying to prove $equiv for \alu_operand_b [119]: failed. + Trying to prove $equiv for \alu_operand_b [120]: failed. + Trying to prove $equiv for \alu_operand_b [121]: failed. + Trying to prove $equiv for \alu_operand_b [122]: failed. + Trying to prove $equiv for \alu_operand_b [123]: failed. + Trying to prove $equiv for \alu_operand_b [124]: failed. + Trying to prove $equiv for \alu_operand_b [125]: failed. + Trying to prove $equiv for \alu_operand_b [126]: failed. + Trying to prove $equiv for \alu_operand_b [127]: failed. + Trying to prove $equiv for \alu_busy: failed. + Trying to prove $equiv for \alu_done: failed. + Trying to prove $equiv for \alu_fault: failed. + Grouping SAT models for \alu_result: + Trying to prove $equiv for \alu_result [0]: failed. + Trying to prove $equiv for \alu_result [1]: failed. + Trying to prove $equiv for \alu_result [2]: failed. + Trying to prove $equiv for \alu_result [3]: failed. + Trying to prove $equiv for \alu_result [4]: failed. + Trying to prove $equiv for \alu_result [5]: failed. + Trying to prove $equiv for \alu_result [6]: failed. + Trying to prove $equiv for \alu_result [7]: failed. + Trying to prove $equiv for \alu_result [8]: failed. + Trying to prove $equiv for \alu_result [9]: failed. + Trying to prove $equiv for \alu_result [10]: failed. + Trying to prove $equiv for \alu_result [11]: failed. + Trying to prove $equiv for \alu_result [12]: failed. + Trying to prove $equiv for \alu_result [13]: failed. + Trying to prove $equiv for \alu_result [14]: failed. + Trying to prove $equiv for \alu_result [15]: failed. + Trying to prove $equiv for \alu_result [16]: failed. + Trying to prove $equiv for \alu_result [17]: failed. + Trying to prove $equiv for \alu_result [18]: failed. + Trying to prove $equiv for \alu_result [19]: failed. + Trying to prove $equiv for \alu_result [20]: failed. + Trying to prove $equiv for \alu_result [21]: failed. + Trying to prove $equiv for \alu_result [22]: failed. + Trying to prove $equiv for \alu_result [23]: failed. + Trying to prove $equiv for \alu_result [24]: failed. + Trying to prove $equiv for \alu_result [25]: failed. + Trying to prove $equiv for \alu_result [26]: failed. + Trying to prove $equiv for \alu_result [27]: failed. + Trying to prove $equiv for \alu_result [28]: failed. + Trying to prove $equiv for \alu_result [29]: failed. + Trying to prove $equiv for \alu_result [30]: failed. + Trying to prove $equiv for \alu_result [31]: failed. + Trying to prove $equiv for \alu_result [32]: failed. + Trying to prove $equiv for \alu_result [33]: failed. + Trying to prove $equiv for \alu_result [34]: failed. + Trying to prove $equiv for \alu_result [35]: failed. + Trying to prove $equiv for \alu_result [36]: failed. + Trying to prove $equiv for \alu_result [37]: failed. + Trying to prove $equiv for \alu_result [38]: failed. + Trying to prove $equiv for \alu_result [39]: failed. + Trying to prove $equiv for \alu_result [40]: failed. + Trying to prove $equiv for \alu_result [41]: failed. + Trying to prove $equiv for \alu_result [42]: failed. + Trying to prove $equiv for \alu_result [43]: failed. + Trying to prove $equiv for \alu_result [44]: failed. + Trying to prove $equiv for \alu_result [45]: failed. + Trying to prove $equiv for \alu_result [46]: failed. + Trying to prove $equiv for \alu_result [47]: failed. + Trying to prove $equiv for \alu_result [48]: failed. + Trying to prove $equiv for \alu_result [49]: failed. + Trying to prove $equiv for \alu_result [50]: failed. + Trying to prove $equiv for \alu_result [51]: failed. + Trying to prove $equiv for \alu_result [52]: failed. + Trying to prove $equiv for \alu_result [53]: failed. + Trying to prove $equiv for \alu_result [54]: failed. + Trying to prove $equiv for \alu_result [55]: failed. + Trying to prove $equiv for \alu_result [56]: failed. + Trying to prove $equiv for \alu_result [57]: failed. + Trying to prove $equiv for \alu_result [58]: failed. + Trying to prove $equiv for \alu_result [59]: failed. + Trying to prove $equiv for \alu_result [60]: failed. + Trying to prove $equiv for \alu_result [61]: failed. + Trying to prove $equiv for \alu_result [62]: failed. + Trying to prove $equiv for \alu_result [63]: failed. + Trying to prove $equiv for \alu_result [64]: failed. + Trying to prove $equiv for \alu_result [65]: failed. + Trying to prove $equiv for \alu_result [66]: failed. + Trying to prove $equiv for \alu_result [67]: failed. + Trying to prove $equiv for \alu_result [68]: failed. + Trying to prove $equiv for \alu_result [69]: failed. + Trying to prove $equiv for \alu_result [70]: failed. + Trying to prove $equiv for \alu_result [71]: failed. + Trying to prove $equiv for \alu_result [72]: failed. + Trying to prove $equiv for \alu_result [73]: failed. + Trying to prove $equiv for \alu_result [74]: failed. + Trying to prove $equiv for \alu_result [75]: failed. + Trying to prove $equiv for \alu_result [76]: failed. + Trying to prove $equiv for \alu_result [77]: failed. + Trying to prove $equiv for \alu_result [78]: failed. + Trying to prove $equiv for \alu_result [79]: failed. + Trying to prove $equiv for \alu_result [80]: failed. + Trying to prove $equiv for \alu_result [81]: failed. + Trying to prove $equiv for \alu_result [82]: failed. + Trying to prove $equiv for \alu_result [83]: failed. + Trying to prove $equiv for \alu_result [84]: failed. + Trying to prove $equiv for \alu_result [85]: failed. + Trying to prove $equiv for \alu_result [86]: failed. + Trying to prove $equiv for \alu_result [87]: failed. + Trying to prove $equiv for \alu_result [88]: failed. + Trying to prove $equiv for \alu_result [89]: failed. + Trying to prove $equiv for \alu_result [90]: failed. + Trying to prove $equiv for \alu_result [91]: failed. + Trying to prove $equiv for \alu_result [92]: failed. + Trying to prove $equiv for \alu_result [93]: failed. + Trying to prove $equiv for \alu_result [94]: failed. + Trying to prove $equiv for \alu_result [95]: failed. + Trying to prove $equiv for \alu_result [96]: failed. + Trying to prove $equiv for \alu_result [97]: failed. + Trying to prove $equiv for \alu_result [98]: failed. + Trying to prove $equiv for \alu_result [99]: failed. + Trying to prove $equiv for \alu_result [100]: failed. + Trying to prove $equiv for \alu_result [101]: failed. + Trying to prove $equiv for \alu_result [102]: failed. + Trying to prove $equiv for \alu_result [103]: failed. + Trying to prove $equiv for \alu_result [104]: failed. + Trying to prove $equiv for \alu_result [105]: failed. + Trying to prove $equiv for \alu_result [106]: failed. + Trying to prove $equiv for \alu_result [107]: failed. + Trying to prove $equiv for \alu_result [108]: failed. + Trying to prove $equiv for \alu_result [109]: failed. + Trying to prove $equiv for \alu_result [110]: failed. + Trying to prove $equiv for \alu_result [111]: failed. + Trying to prove $equiv for \alu_result [112]: failed. + Trying to prove $equiv for \alu_result [113]: failed. + Trying to prove $equiv for \alu_result [114]: failed. + Trying to prove $equiv for \alu_result [115]: failed. + Trying to prove $equiv for \alu_result [116]: failed. + Trying to prove $equiv for \alu_result [117]: failed. + Trying to prove $equiv for \alu_result [118]: failed. + Trying to prove $equiv for \alu_result [119]: failed. + Trying to prove $equiv for \alu_result [120]: failed. + Trying to prove $equiv for \alu_result [121]: failed. + Trying to prove $equiv for \alu_result [122]: failed. + Trying to prove $equiv for \alu_result [123]: failed. + Trying to prove $equiv for \alu_result [124]: failed. + Trying to prove $equiv for \alu_result [125]: failed. + Trying to prove $equiv for \alu_result [126]: failed. + Trying to prove $equiv for \alu_result [127]: failed. + Trying to prove $equiv for \encoder_start: failed. + Grouping SAT models for \encoder_index: + Trying to prove $equiv for \encoder_index [0]: failed. + Trying to prove $equiv for \encoder_index [1]: failed. + Trying to prove $equiv for \encoder_index [2]: failed. + Trying to prove $equiv for \encoder_index [3]: failed. + Trying to prove $equiv for \encoder_index [4]: failed. + Trying to prove $equiv for \encoder_index [5]: failed. + Trying to prove $equiv for \encoder_index [6]: failed. + Trying to prove $equiv for \encoder_index [7]: failed. + Trying to prove $equiv for \encoder_index [8]: failed. + Trying to prove $equiv for \encoder_index [9]: failed. + Trying to prove $equiv for \encoder_index [10]: failed. + Trying to prove $equiv for \encoder_index [11]: failed. + Trying to prove $equiv for \encoder_index [12]: failed. + Trying to prove $equiv for \encoder_index [13]: failed. + Trying to prove $equiv for \encoder_index [14]: failed. + Trying to prove $equiv for \encoder_index [15]: failed. + Trying to prove $equiv for \encoder_busy: failed. + Trying to prove $equiv for \encoder_done: failed. + Trying to prove $equiv for \encoder_fault: failed. + Grouping SAT models for \encoder_result: + Trying to prove $equiv for \encoder_result [0]: failed. + Trying to prove $equiv for \encoder_result [1]: failed. + Trying to prove $equiv for \encoder_result [2]: failed. + Trying to prove $equiv for \encoder_result [3]: failed. + Trying to prove $equiv for \encoder_result [4]: failed. + Trying to prove $equiv for \encoder_result [5]: failed. + Trying to prove $equiv for \encoder_result [6]: failed. + Trying to prove $equiv for \encoder_result [7]: failed. + Trying to prove $equiv for \encoder_result [8]: failed. + Trying to prove $equiv for \encoder_result [9]: failed. + Trying to prove $equiv for \encoder_result [10]: failed. + Trying to prove $equiv for \encoder_result [11]: failed. + Trying to prove $equiv for \encoder_result [12]: failed. + Trying to prove $equiv for \encoder_result [13]: failed. + Trying to prove $equiv for \encoder_result [14]: failed. + Trying to prove $equiv for \encoder_result [15]: failed. + Trying to prove $equiv for \encoder_result [16]: failed. + Trying to prove $equiv for \encoder_result [17]: failed. + Trying to prove $equiv for \encoder_result [18]: failed. + Trying to prove $equiv for \encoder_result [19]: failed. + Trying to prove $equiv for \encoder_result [20]: failed. + Trying to prove $equiv for \encoder_result [21]: failed. + Trying to prove $equiv for \encoder_result [22]: failed. + Trying to prove $equiv for \encoder_result [23]: failed. + Trying to prove $equiv for \encoder_result [24]: failed. + Trying to prove $equiv for \encoder_result [25]: failed. + Trying to prove $equiv for \encoder_result [26]: failed. + Trying to prove $equiv for \encoder_result [27]: failed. + Trying to prove $equiv for \encoder_result [28]: failed. + Trying to prove $equiv for \encoder_result [29]: failed. + Trying to prove $equiv for \encoder_result [30]: failed. + Trying to prove $equiv for \encoder_result [31]: failed. + Trying to prove $equiv for \encoder_result [32]: failed. + Trying to prove $equiv for \encoder_result [33]: failed. + Trying to prove $equiv for \encoder_result [34]: failed. + Trying to prove $equiv for \encoder_result [35]: failed. + Trying to prove $equiv for \encoder_result [36]: failed. + Trying to prove $equiv for \encoder_result [37]: failed. + Trying to prove $equiv for \encoder_result [38]: failed. + Trying to prove $equiv for \encoder_result [39]: failed. + Trying to prove $equiv for \encoder_result [40]: failed. + Trying to prove $equiv for \encoder_result [41]: failed. + Trying to prove $equiv for \encoder_result [42]: failed. + Trying to prove $equiv for \encoder_result [43]: failed. + Trying to prove $equiv for \encoder_result [44]: failed. + Trying to prove $equiv for \encoder_result [45]: failed. + Trying to prove $equiv for \encoder_result [46]: failed. + Trying to prove $equiv for \encoder_result [47]: failed. + Trying to prove $equiv for \encoder_result [48]: failed. + Trying to prove $equiv for \encoder_result [49]: failed. + Trying to prove $equiv for \encoder_result [50]: failed. + Trying to prove $equiv for \encoder_result [51]: failed. + Trying to prove $equiv for \encoder_result [52]: failed. + Trying to prove $equiv for \encoder_result [53]: failed. + Trying to prove $equiv for \encoder_result [54]: failed. + Trying to prove $equiv for \encoder_result [55]: failed. + Trying to prove $equiv for \encoder_result [56]: failed. + Trying to prove $equiv for \encoder_result [57]: failed. + Trying to prove $equiv for \encoder_result [58]: failed. + Trying to prove $equiv for \encoder_result [59]: failed. + Trying to prove $equiv for \encoder_result [60]: failed. + Trying to prove $equiv for \encoder_result [61]: failed. + Trying to prove $equiv for \encoder_result [62]: failed. + Trying to prove $equiv for \encoder_result [63]: failed. + Trying to prove $equiv for \encoder_result [64]: failed. + Trying to prove $equiv for \encoder_result [65]: failed. + Trying to prove $equiv for \encoder_result [66]: failed. + Trying to prove $equiv for \encoder_result [67]: failed. + Trying to prove $equiv for \encoder_result [68]: failed. + Trying to prove $equiv for \encoder_result [69]: failed. + Trying to prove $equiv for \encoder_result [70]: failed. + Trying to prove $equiv for \encoder_result [71]: failed. + Trying to prove $equiv for \encoder_result [72]: failed. + Trying to prove $equiv for \encoder_result [73]: failed. + Trying to prove $equiv for \encoder_result [74]: failed. + Trying to prove $equiv for \encoder_result [75]: failed. + Trying to prove $equiv for \encoder_result [76]: failed. + Trying to prove $equiv for \encoder_result [77]: failed. + Trying to prove $equiv for \encoder_result [78]: failed. + Trying to prove $equiv for \encoder_result [79]: failed. + Trying to prove $equiv for \encoder_result [80]: failed. + Trying to prove $equiv for \encoder_result [81]: failed. + Trying to prove $equiv for \encoder_result [82]: failed. + Trying to prove $equiv for \encoder_result [83]: failed. + Trying to prove $equiv for \encoder_result [84]: failed. + Trying to prove $equiv for \encoder_result [85]: failed. + Trying to prove $equiv for \encoder_result [86]: failed. + Trying to prove $equiv for \encoder_result [87]: failed. + Trying to prove $equiv for \encoder_result [88]: failed. + Trying to prove $equiv for \encoder_result [89]: failed. + Trying to prove $equiv for \encoder_result [90]: failed. + Trying to prove $equiv for \encoder_result [91]: failed. + Trying to prove $equiv for \encoder_result [92]: failed. + Trying to prove $equiv for \encoder_result [93]: failed. + Trying to prove $equiv for \encoder_result [94]: failed. + Trying to prove $equiv for \encoder_result [95]: failed. + Trying to prove $equiv for \encoder_result [96]: failed. + Trying to prove $equiv for \encoder_result [97]: failed. + Trying to prove $equiv for \encoder_result [98]: failed. + Trying to prove $equiv for \encoder_result [99]: failed. + Trying to prove $equiv for \encoder_result [100]: failed. + Trying to prove $equiv for \encoder_result [101]: failed. + Trying to prove $equiv for \encoder_result [102]: failed. + Trying to prove $equiv for \encoder_result [103]: failed. + Trying to prove $equiv for \encoder_result [104]: failed. + Trying to prove $equiv for \encoder_result [105]: failed. + Trying to prove $equiv for \encoder_result [106]: failed. + Trying to prove $equiv for \encoder_result [107]: failed. + Trying to prove $equiv for \encoder_result [108]: failed. + Trying to prove $equiv for \encoder_result [109]: failed. + Trying to prove $equiv for \encoder_result [110]: failed. + Trying to prove $equiv for \encoder_result [111]: failed. + Trying to prove $equiv for \encoder_result [112]: failed. + Trying to prove $equiv for \encoder_result [113]: failed. + Trying to prove $equiv for \encoder_result [114]: failed. + Trying to prove $equiv for \encoder_result [115]: failed. + Trying to prove $equiv for \encoder_result [116]: failed. + Trying to prove $equiv for \encoder_result [117]: failed. + Trying to prove $equiv for \encoder_result [118]: failed. + Trying to prove $equiv for \encoder_result [119]: failed. + Trying to prove $equiv for \encoder_result [120]: failed. + Trying to prove $equiv for \encoder_result [121]: failed. + Trying to prove $equiv for \encoder_result [122]: failed. + Trying to prove $equiv for \encoder_result [123]: failed. + Trying to prove $equiv for \encoder_result [124]: failed. + Trying to prove $equiv for \encoder_result [125]: failed. + Trying to prove $equiv for \encoder_result [126]: failed. + Trying to prove $equiv for \encoder_result [127]: failed. + Trying to prove $equiv for \lane_enable: failed. + Trying to prove $equiv for \result_pending: failed. + Grouping SAT models for \staged_txn_id: + Trying to prove $equiv for \staged_txn_id [0]: failed. + Trying to prove $equiv for \staged_txn_id [1]: failed. + Trying to prove $equiv for \staged_txn_id [2]: failed. + Trying to prove $equiv for \staged_txn_id [3]: failed. + Trying to prove $equiv for \staged_txn_id [4]: failed. + Trying to prove $equiv for \staged_txn_id [5]: failed. + Trying to prove $equiv for \staged_txn_id [6]: failed. + Trying to prove $equiv for \staged_txn_id [7]: failed. + Trying to prove $equiv for \staged_txn_id [8]: failed. + Trying to prove $equiv for \staged_txn_id [9]: failed. + Trying to prove $equiv for \staged_txn_id [10]: failed. + Trying to prove $equiv for \staged_txn_id [11]: failed. + Trying to prove $equiv for \staged_txn_id [12]: failed. + Trying to prove $equiv for \staged_txn_id [13]: failed. + Trying to prove $equiv for \staged_txn_id [14]: failed. + Trying to prove $equiv for \staged_txn_id [15]: failed. + Trying to prove $equiv for \staged_txn_id [16]: failed. + Trying to prove $equiv for \staged_txn_id [17]: failed. + Trying to prove $equiv for \staged_txn_id [18]: failed. + Trying to prove $equiv for \staged_txn_id [19]: failed. + Trying to prove $equiv for \staged_txn_id [20]: failed. + Trying to prove $equiv for \staged_txn_id [21]: failed. + Trying to prove $equiv for \staged_txn_id [22]: failed. + Trying to prove $equiv for \staged_txn_id [23]: failed. + Trying to prove $equiv for \staged_txn_id [24]: failed. + Trying to prove $equiv for \staged_txn_id [25]: failed. + Trying to prove $equiv for \staged_txn_id [26]: failed. + Trying to prove $equiv for \staged_txn_id [27]: failed. + Trying to prove $equiv for \staged_txn_id [28]: failed. + Trying to prove $equiv for \staged_txn_id [29]: failed. + Trying to prove $equiv for \staged_txn_id [30]: failed. + Trying to prove $equiv for \staged_txn_id [31]: failed. + Grouping SAT models for \staged_next_pc: + Trying to prove $equiv for \staged_next_pc [0]: failed. + Trying to prove $equiv for \staged_next_pc [1]: failed. + Trying to prove $equiv for \staged_next_pc [2]: failed. + Trying to prove $equiv for \staged_next_pc [3]: failed. + Trying to prove $equiv for \staged_next_pc [4]: failed. + Trying to prove $equiv for \staged_next_pc [5]: failed. + Trying to prove $equiv for \staged_next_pc [6]: failed. + Trying to prove $equiv for \staged_next_pc [7]: failed. + Trying to prove $equiv for \staged_next_pc [8]: failed. + Trying to prove $equiv for \staged_next_pc [9]: failed. + Trying to prove $equiv for \staged_next_pc [10]: failed. + Trying to prove $equiv for \staged_next_pc [11]: failed. + Trying to prove $equiv for \staged_next_pc [12]: failed. + Trying to prove $equiv for \staged_next_pc [13]: failed. + Trying to prove $equiv for \staged_next_pc [14]: failed. + Trying to prove $equiv for \staged_next_pc [15]: failed. + Trying to prove $equiv for \staged_next_pc [16]: failed. + Trying to prove $equiv for \staged_next_pc [17]: failed. + Trying to prove $equiv for \staged_next_pc [18]: failed. + Trying to prove $equiv for \staged_next_pc [19]: failed. + Trying to prove $equiv for \staged_next_pc [20]: failed. + Trying to prove $equiv for \staged_next_pc [21]: failed. + Trying to prove $equiv for \staged_next_pc [22]: failed. + Trying to prove $equiv for \staged_next_pc [23]: failed. + Trying to prove $equiv for \staged_next_pc [24]: failed. + Trying to prove $equiv for \staged_next_pc [25]: failed. + Trying to prove $equiv for \staged_next_pc [26]: failed. + Trying to prove $equiv for \staged_next_pc [27]: failed. + Trying to prove $equiv for \staged_next_pc [28]: failed. + Trying to prove $equiv for \staged_next_pc [29]: failed. + Trying to prove $equiv for \staged_next_pc [30]: failed. + Trying to prove $equiv for \staged_next_pc [31]: failed. + Grouping SAT models for \staged_next_fp: + Trying to prove $equiv for \staged_next_fp [0]: failed. + Trying to prove $equiv for \staged_next_fp [1]: failed. + Trying to prove $equiv for \staged_next_fp [2]: failed. + Trying to prove $equiv for \staged_next_fp [3]: failed. + Trying to prove $equiv for \staged_next_fp [4]: failed. + Trying to prove $equiv for \staged_next_fp [5]: failed. + Trying to prove $equiv for \staged_next_fp [6]: failed. + Trying to prove $equiv for \staged_next_fp [7]: failed. + Trying to prove $equiv for \staged_next_fp [8]: failed. + Trying to prove $equiv for \staged_next_fp [9]: failed. + Trying to prove $equiv for \staged_next_fp [10]: failed. + Trying to prove $equiv for \staged_next_fp [11]: failed. + Trying to prove $equiv for \staged_next_fp [12]: failed. + Trying to prove $equiv for \staged_next_fp [13]: failed. + Trying to prove $equiv for \staged_next_fp [14]: failed. + Trying to prove $equiv for \staged_next_fp [15]: failed. + Trying to prove $equiv for \staged_next_fp [16]: failed. + Trying to prove $equiv for \staged_next_fp [17]: failed. + Trying to prove $equiv for \staged_next_fp [18]: failed. + Trying to prove $equiv for \staged_next_fp [19]: failed. + Trying to prove $equiv for \staged_next_fp [20]: failed. + Trying to prove $equiv for \staged_next_fp [21]: failed. + Trying to prove $equiv for \staged_next_fp [22]: failed. + Trying to prove $equiv for \staged_next_fp [23]: failed. + Trying to prove $equiv for \staged_next_fp [24]: failed. + Trying to prove $equiv for \staged_next_fp [25]: failed. + Trying to prove $equiv for \staged_next_fp [26]: failed. + Trying to prove $equiv for \staged_next_fp [27]: failed. + Trying to prove $equiv for \staged_next_fp [28]: failed. + Trying to prove $equiv for \staged_next_fp [29]: failed. + Trying to prove $equiv for \staged_next_fp [30]: failed. + Trying to prove $equiv for \staged_next_fp [31]: failed. + Grouping SAT models for \staged_result_crc: + Trying to prove $equiv for \staged_result_crc [0]: failed. + Trying to prove $equiv for \staged_result_crc [1]: failed. + Trying to prove $equiv for \staged_result_crc [2]: failed. + Trying to prove $equiv for \staged_result_crc [3]: failed. + Trying to prove $equiv for \staged_result_crc [4]: failed. + Trying to prove $equiv for \staged_result_crc [5]: failed. + Trying to prove $equiv for \staged_result_crc [6]: failed. + Trying to prove $equiv for \staged_result_crc [7]: failed. + Trying to prove $equiv for \staged_result_crc [8]: failed. + Trying to prove $equiv for \staged_result_crc [9]: failed. + Trying to prove $equiv for \staged_result_crc [10]: failed. + Trying to prove $equiv for \staged_result_crc [11]: failed. + Trying to prove $equiv for \staged_result_crc [12]: failed. + Trying to prove $equiv for \staged_result_crc [13]: failed. + Trying to prove $equiv for \staged_result_crc [14]: failed. + Trying to prove $equiv for \staged_result_crc [15]: failed. + Trying to prove $equiv for \staged_result_crc [16]: failed. + Trying to prove $equiv for \staged_result_crc [17]: failed. + Trying to prove $equiv for \staged_result_crc [18]: failed. + Trying to prove $equiv for \staged_result_crc [19]: failed. + Trying to prove $equiv for \staged_result_crc [20]: failed. + Trying to prove $equiv for \staged_result_crc [21]: failed. + Trying to prove $equiv for \staged_result_crc [22]: failed. + Trying to prove $equiv for \staged_result_crc [23]: failed. + Trying to prove $equiv for \staged_result_crc [24]: failed. + Trying to prove $equiv for \staged_result_crc [25]: failed. + Trying to prove $equiv for \staged_result_crc [26]: failed. + Trying to prove $equiv for \staged_result_crc [27]: failed. + Trying to prove $equiv for \staged_result_crc [28]: failed. + Trying to prove $equiv for \staged_result_crc [29]: failed. + Trying to prove $equiv for \staged_result_crc [30]: failed. + Trying to prove $equiv for \staged_result_crc [31]: failed. + Trying to prove $equiv for \state_valid: failed. + Grouping SAT models for \committed_pc: + Trying to prove $equiv for \committed_pc [0]: failed. + Trying to prove $equiv for \committed_pc [1]: failed. + Trying to prove $equiv for \committed_pc [2]: failed. + Trying to prove $equiv for \committed_pc [3]: failed. + Trying to prove $equiv for \committed_pc [4]: failed. + Trying to prove $equiv for \committed_pc [5]: failed. + Trying to prove $equiv for \committed_pc [6]: failed. + Trying to prove $equiv for \committed_pc [7]: failed. + Trying to prove $equiv for \committed_pc [8]: failed. + Trying to prove $equiv for \committed_pc [9]: failed. + Trying to prove $equiv for \committed_pc [10]: failed. + Trying to prove $equiv for \committed_pc [11]: failed. + Trying to prove $equiv for \committed_pc [12]: failed. + Trying to prove $equiv for \committed_pc [13]: failed. + Trying to prove $equiv for \committed_pc [14]: failed. + Trying to prove $equiv for \committed_pc [15]: failed. + Trying to prove $equiv for \committed_pc [16]: failed. + Trying to prove $equiv for \committed_pc [17]: failed. + Trying to prove $equiv for \committed_pc [18]: failed. + Trying to prove $equiv for \committed_pc [19]: failed. + Trying to prove $equiv for \committed_pc [20]: failed. + Trying to prove $equiv for \committed_pc [21]: failed. + Trying to prove $equiv for \committed_pc [22]: failed. + Trying to prove $equiv for \committed_pc [23]: failed. + Trying to prove $equiv for \committed_pc [24]: failed. + Trying to prove $equiv for \committed_pc [25]: failed. + Trying to prove $equiv for \committed_pc [26]: failed. + Trying to prove $equiv for \committed_pc [27]: failed. + Trying to prove $equiv for \committed_pc [28]: failed. + Trying to prove $equiv for \committed_pc [29]: failed. + Trying to prove $equiv for \committed_pc [30]: failed. + Trying to prove $equiv for \committed_pc [31]: failed. + Grouping SAT models for \committed_fp: + Trying to prove $equiv for \committed_fp [0]: failed. + Trying to prove $equiv for \committed_fp [1]: failed. + Trying to prove $equiv for \committed_fp [2]: failed. + Trying to prove $equiv for \committed_fp [3]: failed. + Trying to prove $equiv for \committed_fp [4]: failed. + Trying to prove $equiv for \committed_fp [5]: failed. + Trying to prove $equiv for \committed_fp [6]: failed. + Trying to prove $equiv for \committed_fp [7]: failed. + Trying to prove $equiv for \committed_fp [8]: failed. + Trying to prove $equiv for \committed_fp [9]: failed. + Trying to prove $equiv for \committed_fp [10]: failed. + Trying to prove $equiv for \committed_fp [11]: failed. + Trying to prove $equiv for \committed_fp [12]: failed. + Trying to prove $equiv for \committed_fp [13]: failed. + Trying to prove $equiv for \committed_fp [14]: failed. + Trying to prove $equiv for \committed_fp [15]: failed. + Trying to prove $equiv for \committed_fp [16]: failed. + Trying to prove $equiv for \committed_fp [17]: failed. + Trying to prove $equiv for \committed_fp [18]: failed. + Trying to prove $equiv for \committed_fp [19]: failed. + Trying to prove $equiv for \committed_fp [20]: failed. + Trying to prove $equiv for \committed_fp [21]: failed. + Trying to prove $equiv for \committed_fp [22]: failed. + Trying to prove $equiv for \committed_fp [23]: failed. + Trying to prove $equiv for \committed_fp [24]: failed. + Trying to prove $equiv for \committed_fp [25]: failed. + Trying to prove $equiv for \committed_fp [26]: failed. + Trying to prove $equiv for \committed_fp [27]: failed. + Trying to prove $equiv for \committed_fp [28]: failed. + Trying to prove $equiv for \committed_fp [29]: failed. + Trying to prove $equiv for \committed_fp [30]: failed. + Trying to prove $equiv for \committed_fp [31]: failed. + Grouping SAT models for \retire_seq: + Trying to prove $equiv for \retire_seq [0]: failed. + Trying to prove $equiv for \retire_seq [1]: failed. + Trying to prove $equiv for \retire_seq [2]: failed. + Trying to prove $equiv for \retire_seq [3]: failed. + Trying to prove $equiv for \retire_seq [4]: failed. + Trying to prove $equiv for \retire_seq [5]: failed. + Trying to prove $equiv for \retire_seq [6]: failed. + Trying to prove $equiv for \retire_seq [7]: failed. + Trying to prove $equiv for \retire_seq [8]: failed. + Trying to prove $equiv for \retire_seq [9]: failed. + Trying to prove $equiv for \retire_seq [10]: failed. + Trying to prove $equiv for \retire_seq [11]: failed. + Trying to prove $equiv for \retire_seq [12]: failed. + Trying to prove $equiv for \retire_seq [13]: failed. + Trying to prove $equiv for \retire_seq [14]: failed. + Trying to prove $equiv for \retire_seq [15]: failed. + Trying to prove $equiv for \retire_seq [16]: failed. + Trying to prove $equiv for \retire_seq [17]: failed. + Trying to prove $equiv for \retire_seq [18]: failed. + Trying to prove $equiv for \retire_seq [19]: failed. + Trying to prove $equiv for \retire_seq [20]: failed. + Trying to prove $equiv for \retire_seq [21]: failed. + Trying to prove $equiv for \retire_seq [22]: failed. + Trying to prove $equiv for \retire_seq [23]: failed. + Trying to prove $equiv for \retire_seq [24]: failed. + Trying to prove $equiv for \retire_seq [25]: failed. + Trying to prove $equiv for \retire_seq [26]: failed. + Trying to prove $equiv for \retire_seq [27]: failed. + Trying to prove $equiv for \retire_seq [28]: failed. + Trying to prove $equiv for \retire_seq [29]: failed. + Trying to prove $equiv for \retire_seq [30]: failed. + Trying to prove $equiv for \retire_seq [31]: failed. + Grouping SAT models for \active_profile: + Trying to prove $equiv for \active_profile [0]: failed. + Trying to prove $equiv for \active_profile [1]: failed. + Trying to prove $equiv for \active_profile [2]: failed. + Trying to prove $equiv for \active_profile [3]: failed. + Trying to prove $equiv for \active_profile [4]: failed. + Trying to prove $equiv for \active_profile [5]: failed. + Trying to prove $equiv for \active_profile [6]: failed. + Trying to prove $equiv for \active_profile [7]: failed. + Grouping SAT models for \last_status: + Trying to prove $equiv for \last_status [0]: failed. + Trying to prove $equiv for \last_status [1]: failed. + Trying to prove $equiv for \last_status [2]: failed. + Trying to prove $equiv for \last_status [3]: failed. + Trying to prove $equiv for \last_status [4]: failed. + Trying to prove $equiv for \last_status [5]: failed. + Trying to prove $equiv for \last_status [6]: failed. + Trying to prove $equiv for \last_status [7]: failed. + Grouping SAT models for \last_fault: + Trying to prove $equiv for \last_fault [0]: failed. + Trying to prove $equiv for \last_fault [1]: failed. + Trying to prove $equiv for \last_fault [2]: failed. + Trying to prove $equiv for \last_fault [3]: failed. + Trying to prove $equiv for \last_fault [4]: failed. + Trying to prove $equiv for \last_fault [5]: failed. + Trying to prove $equiv for \last_fault [6]: failed. + Trying to prove $equiv for \last_fault [7]: failed. + Trying to prove $equiv for \event_valid: failed. + Trying to prove $equiv for \event_ready: failed. + Grouping SAT models for \n_writes: + Trying to prove $equiv for \n_writes [0]: failed. + Trying to prove $equiv for \n_writes [1]: failed. + Trying to prove $equiv for \n_writes [2]: failed. + Trying to prove $equiv for \n_writes [3]: failed. + Trying to prove $equiv for \n_writes [4]: failed. + Trying to prove $equiv for \n_writes [5]: failed. + Trying to prove $equiv for \n_writes [6]: failed. + Trying to prove $equiv for \n_writes [7]: failed. + Trying to prove $equiv for \n_writes [8]: failed. + Trying to prove $equiv for \n_writes [9]: failed. + Trying to prove $equiv for \n_writes [10]: failed. + Trying to prove $equiv for \n_writes [11]: failed. + Trying to prove $equiv for \n_writes [12]: failed. + Trying to prove $equiv for \n_writes [13]: failed. + Trying to prove $equiv for \n_writes [14]: failed. + Trying to prove $equiv for \n_writes [15]: failed. + Trying to prove $equiv for \n_writes [16]: failed. + Trying to prove $equiv for \n_writes [17]: failed. + Trying to prove $equiv for \n_writes [18]: failed. + Trying to prove $equiv for \n_writes [19]: failed. + Trying to prove $equiv for \n_writes [20]: failed. + Trying to prove $equiv for \n_writes [21]: failed. + Trying to prove $equiv for \n_writes [22]: failed. + Trying to prove $equiv for \n_writes [23]: failed. + Trying to prove $equiv for \n_writes [24]: failed. + Trying to prove $equiv for \n_writes [25]: failed. + Trying to prove $equiv for \n_writes [26]: failed. + Trying to prove $equiv for \n_writes [27]: failed. + Trying to prove $equiv for \n_writes [28]: failed. + Trying to prove $equiv for \n_writes [29]: failed. + Trying to prove $equiv for \n_writes [30]: failed. + Trying to prove $equiv for \n_writes [31]: failed. + Grouping SAT models for \n_deferred: + Trying to prove $equiv for \n_deferred [0]: failed. + Trying to prove $equiv for \n_deferred [1]: failed. + Trying to prove $equiv for \n_deferred [2]: failed. + Trying to prove $equiv for \n_deferred [3]: failed. + Trying to prove $equiv for \n_deferred [4]: failed. + Trying to prove $equiv for \n_deferred [5]: failed. + Trying to prove $equiv for \n_deferred [6]: failed. + Trying to prove $equiv for \n_deferred [7]: failed. + Trying to prove $equiv for \n_deferred [8]: failed. + Trying to prove $equiv for \n_deferred [9]: failed. + Trying to prove $equiv for \n_deferred [10]: failed. + Trying to prove $equiv for \n_deferred [11]: failed. + Trying to prove $equiv for \n_deferred [12]: failed. + Trying to prove $equiv for \n_deferred [13]: failed. + Trying to prove $equiv for \n_deferred [14]: failed. + Trying to prove $equiv for \n_deferred [15]: failed. + Trying to prove $equiv for \n_deferred [16]: failed. + Trying to prove $equiv for \n_deferred [17]: failed. + Trying to prove $equiv for \n_deferred [18]: failed. + Trying to prove $equiv for \n_deferred [19]: failed. + Trying to prove $equiv for \n_deferred [20]: failed. + Trying to prove $equiv for \n_deferred [21]: failed. + Trying to prove $equiv for \n_deferred [22]: failed. + Trying to prove $equiv for \n_deferred [23]: failed. + Trying to prove $equiv for \n_deferred [24]: failed. + Trying to prove $equiv for \n_deferred [25]: failed. + Trying to prove $equiv for \n_deferred [26]: failed. + Trying to prove $equiv for \n_deferred [27]: failed. + Trying to prove $equiv for \n_deferred [28]: failed. + Trying to prove $equiv for \n_deferred [29]: failed. + Trying to prove $equiv for \n_deferred [30]: failed. + Trying to prove $equiv for \n_deferred [31]: failed. + Grouping SAT models for \txn_id: + Trying to prove $equiv for \txn_id [0]: failed. + Trying to prove $equiv for \txn_id [1]: failed. + Trying to prove $equiv for \txn_id [2]: failed. + Trying to prove $equiv for \txn_id [3]: failed. + Trying to prove $equiv for \txn_id [4]: failed. + Trying to prove $equiv for \txn_id [5]: failed. + Trying to prove $equiv for \txn_id [6]: failed. + Trying to prove $equiv for \txn_id [7]: failed. + Trying to prove $equiv for \txn_id [8]: failed. + Trying to prove $equiv for \txn_id [9]: failed. + Trying to prove $equiv for \txn_id [10]: failed. + Trying to prove $equiv for \txn_id [11]: failed. + Trying to prove $equiv for \txn_id [12]: failed. + Trying to prove $equiv for \txn_id [13]: failed. + Trying to prove $equiv for \txn_id [14]: failed. + Trying to prove $equiv for \txn_id [15]: failed. + Trying to prove $equiv for \txn_id [16]: failed. + Trying to prove $equiv for \txn_id [17]: failed. + Trying to prove $equiv for \txn_id [18]: failed. + Trying to prove $equiv for \txn_id [19]: failed. + Trying to prove $equiv for \txn_id [20]: failed. + Trying to prove $equiv for \txn_id [21]: failed. + Trying to prove $equiv for \txn_id [22]: failed. + Trying to prove $equiv for \txn_id [23]: failed. + Trying to prove $equiv for \txn_id [24]: failed. + Trying to prove $equiv for \txn_id [25]: failed. + Trying to prove $equiv for \txn_id [26]: failed. + Trying to prove $equiv for \txn_id [27]: failed. + Trying to prove $equiv for \txn_id [28]: failed. + Trying to prove $equiv for \txn_id [29]: failed. + Trying to prove $equiv for \txn_id [30]: failed. + Trying to prove $equiv for \txn_id [31]: failed. + Grouping SAT models for \pc: + Trying to prove $equiv for \pc [0]: failed. + Trying to prove $equiv for \pc [1]: failed. + Trying to prove $equiv for \pc [2]: failed. + Trying to prove $equiv for \pc [3]: failed. + Trying to prove $equiv for \pc [4]: failed. + Trying to prove $equiv for \pc [5]: failed. + Trying to prove $equiv for \pc [6]: failed. + Trying to prove $equiv for \pc [7]: failed. + Trying to prove $equiv for \pc [8]: failed. + Trying to prove $equiv for \pc [9]: failed. + Trying to prove $equiv for \pc [10]: failed. + Trying to prove $equiv for \pc [11]: failed. + Trying to prove $equiv for \pc [12]: failed. + Trying to prove $equiv for \pc [13]: failed. + Trying to prove $equiv for \pc [14]: failed. + Trying to prove $equiv for \pc [15]: failed. + Trying to prove $equiv for \pc [16]: failed. + Trying to prove $equiv for \pc [17]: failed. + Trying to prove $equiv for \pc [18]: failed. + Trying to prove $equiv for \pc [19]: failed. + Trying to prove $equiv for \pc [20]: failed. + Trying to prove $equiv for \pc [21]: failed. + Trying to prove $equiv for \pc [22]: failed. + Trying to prove $equiv for \pc [23]: failed. + Trying to prove $equiv for \pc [24]: failed. + Trying to prove $equiv for \pc [25]: failed. + Trying to prove $equiv for \pc [26]: failed. + Trying to prove $equiv for \pc [27]: failed. + Trying to prove $equiv for \pc [28]: failed. + Trying to prove $equiv for \pc [29]: failed. + Trying to prove $equiv for \pc [30]: failed. + Trying to prove $equiv for \pc [31]: failed. + Grouping SAT models for \fp: + Trying to prove $equiv for \fp [0]: failed. + Trying to prove $equiv for \fp [1]: failed. + Trying to prove $equiv for \fp [2]: failed. + Trying to prove $equiv for \fp [3]: failed. + Trying to prove $equiv for \fp [4]: failed. + Trying to prove $equiv for \fp [5]: failed. + Trying to prove $equiv for \fp [6]: failed. + Trying to prove $equiv for \fp [7]: failed. + Trying to prove $equiv for \fp [8]: failed. + Trying to prove $equiv for \fp [9]: failed. + Trying to prove $equiv for \fp [10]: failed. + Trying to prove $equiv for \fp [11]: failed. + Trying to prove $equiv for \fp [12]: failed. + Trying to prove $equiv for \fp [13]: failed. + Trying to prove $equiv for \fp [14]: failed. + Trying to prove $equiv for \fp [15]: failed. + Trying to prove $equiv for \fp [16]: failed. + Trying to prove $equiv for \fp [17]: failed. + Trying to prove $equiv for \fp [18]: failed. + Trying to prove $equiv for \fp [19]: failed. + Trying to prove $equiv for \fp [20]: failed. + Trying to prove $equiv for \fp [21]: failed. + Trying to prove $equiv for \fp [22]: failed. + Trying to prove $equiv for \fp [23]: failed. + Trying to prove $equiv for \fp [24]: failed. + Trying to prove $equiv for \fp [25]: failed. + Trying to prove $equiv for \fp [26]: failed. + Trying to prove $equiv for \fp [27]: failed. + Trying to prove $equiv for \fp [28]: failed. + Trying to prove $equiv for \fp [29]: failed. + Trying to prove $equiv for \fp [30]: failed. + Trying to prove $equiv for \fp [31]: failed. + Grouping SAT models for \addr_a: + Trying to prove $equiv for \addr_a [0]: failed. + Trying to prove $equiv for \addr_a [1]: failed. + Trying to prove $equiv for \addr_a [2]: failed. + Trying to prove $equiv for \addr_a [3]: failed. + Trying to prove $equiv for \addr_a [4]: failed. + Trying to prove $equiv for \addr_a [5]: failed. + Trying to prove $equiv for \addr_a [6]: failed. + Trying to prove $equiv for \addr_a [7]: failed. + Trying to prove $equiv for \addr_a [8]: failed. + Trying to prove $equiv for \addr_a [9]: failed. + Trying to prove $equiv for \addr_a [10]: failed. + Trying to prove $equiv for \addr_a [11]: failed. + Trying to prove $equiv for \addr_a [12]: failed. + Trying to prove $equiv for \addr_a [13]: failed. + Trying to prove $equiv for \addr_a [14]: failed. + Trying to prove $equiv for \addr_a [15]: failed. + Trying to prove $equiv for \addr_a [16]: failed. + Trying to prove $equiv for \addr_a [17]: failed. + Trying to prove $equiv for \addr_a [18]: failed. + Trying to prove $equiv for \addr_a [19]: failed. + Trying to prove $equiv for \addr_a [20]: failed. + Trying to prove $equiv for \addr_a [21]: failed. + Trying to prove $equiv for \addr_a [22]: failed. + Trying to prove $equiv for \addr_a [23]: failed. + Trying to prove $equiv for \addr_a [24]: failed. + Trying to prove $equiv for \addr_a [25]: failed. + Trying to prove $equiv for \addr_a [26]: failed. + Trying to prove $equiv for \addr_a [27]: failed. + Trying to prove $equiv for \addr_a [28]: failed. + Trying to prove $equiv for \addr_a [29]: failed. + Trying to prove $equiv for \addr_a [30]: failed. + Trying to prove $equiv for \addr_a [31]: failed. + Grouping SAT models for \addr_b: + Trying to prove $equiv for \addr_b [0]: failed. + Trying to prove $equiv for \addr_b [1]: failed. + Trying to prove $equiv for \addr_b [2]: failed. + Trying to prove $equiv for \addr_b [3]: failed. + Trying to prove $equiv for \addr_b [4]: failed. + Trying to prove $equiv for \addr_b [5]: failed. + Trying to prove $equiv for \addr_b [6]: failed. + Trying to prove $equiv for \addr_b [7]: failed. + Trying to prove $equiv for \addr_b [8]: failed. + Trying to prove $equiv for \addr_b [9]: failed. + Trying to prove $equiv for \addr_b [10]: failed. + Trying to prove $equiv for \addr_b [11]: failed. + Trying to prove $equiv for \addr_b [12]: failed. + Trying to prove $equiv for \addr_b [13]: failed. + Trying to prove $equiv for \addr_b [14]: failed. + Trying to prove $equiv for \addr_b [15]: failed. + Trying to prove $equiv for \addr_b [16]: failed. + Trying to prove $equiv for \addr_b [17]: failed. + Trying to prove $equiv for \addr_b [18]: failed. + Trying to prove $equiv for \addr_b [19]: failed. + Trying to prove $equiv for \addr_b [20]: failed. + Trying to prove $equiv for \addr_b [21]: failed. + Trying to prove $equiv for \addr_b [22]: failed. + Trying to prove $equiv for \addr_b [23]: failed. + Trying to prove $equiv for \addr_b [24]: failed. + Trying to prove $equiv for \addr_b [25]: failed. + Trying to prove $equiv for \addr_b [26]: failed. + Trying to prove $equiv for \addr_b [27]: failed. + Trying to prove $equiv for \addr_b [28]: failed. + Trying to prove $equiv for \addr_b [29]: failed. + Trying to prove $equiv for \addr_b [30]: failed. + Trying to prove $equiv for \addr_b [31]: failed. + Grouping SAT models for \addr_c: + Trying to prove $equiv for \addr_c [0]: failed. + Trying to prove $equiv for \addr_c [1]: failed. + Trying to prove $equiv for \addr_c [2]: failed. + Trying to prove $equiv for \addr_c [3]: failed. + Trying to prove $equiv for \addr_c [4]: failed. + Trying to prove $equiv for \addr_c [5]: failed. + Trying to prove $equiv for \addr_c [6]: failed. + Trying to prove $equiv for \addr_c [7]: failed. + Trying to prove $equiv for \addr_c [8]: failed. + Trying to prove $equiv for \addr_c [9]: failed. + Trying to prove $equiv for \addr_c [10]: failed. + Trying to prove $equiv for \addr_c [11]: failed. + Trying to prove $equiv for \addr_c [12]: failed. + Trying to prove $equiv for \addr_c [13]: failed. + Trying to prove $equiv for \addr_c [14]: failed. + Trying to prove $equiv for \addr_c [15]: failed. + Trying to prove $equiv for \addr_c [16]: failed. + Trying to prove $equiv for \addr_c [17]: failed. + Trying to prove $equiv for \addr_c [18]: failed. + Trying to prove $equiv for \addr_c [19]: failed. + Trying to prove $equiv for \addr_c [20]: failed. + Trying to prove $equiv for \addr_c [21]: failed. + Trying to prove $equiv for \addr_c [22]: failed. + Trying to prove $equiv for \addr_c [23]: failed. + Trying to prove $equiv for \addr_c [24]: failed. + Trying to prove $equiv for \addr_c [25]: failed. + Trying to prove $equiv for \addr_c [26]: failed. + Trying to prove $equiv for \addr_c [27]: failed. + Trying to prove $equiv for \addr_c [28]: failed. + Trying to prove $equiv for \addr_c [29]: failed. + Trying to prove $equiv for \addr_c [30]: failed. + Trying to prove $equiv for \addr_c [31]: failed. + Grouping SAT models for \proposed_pc: + Trying to prove $equiv for \proposed_pc [0]: failed. + Trying to prove $equiv for \proposed_pc [1]: failed. + Trying to prove $equiv for \proposed_pc [2]: failed. + Trying to prove $equiv for \proposed_pc [3]: failed. + Trying to prove $equiv for \proposed_pc [4]: failed. + Trying to prove $equiv for \proposed_pc [5]: failed. + Trying to prove $equiv for \proposed_pc [6]: failed. + Trying to prove $equiv for \proposed_pc [7]: failed. + Trying to prove $equiv for \proposed_pc [8]: failed. + Trying to prove $equiv for \proposed_pc [9]: failed. + Trying to prove $equiv for \proposed_pc [10]: failed. + Trying to prove $equiv for \proposed_pc [11]: failed. + Trying to prove $equiv for \proposed_pc [12]: failed. + Trying to prove $equiv for \proposed_pc [13]: failed. + Trying to prove $equiv for \proposed_pc [14]: failed. + Trying to prove $equiv for \proposed_pc [15]: failed. + Trying to prove $equiv for \proposed_pc [16]: failed. + Trying to prove $equiv for \proposed_pc [17]: failed. + Trying to prove $equiv for \proposed_pc [18]: failed. + Trying to prove $equiv for \proposed_pc [19]: failed. + Trying to prove $equiv for \proposed_pc [20]: failed. + Trying to prove $equiv for \proposed_pc [21]: failed. + Trying to prove $equiv for \proposed_pc [22]: failed. + Trying to prove $equiv for \proposed_pc [23]: failed. + Trying to prove $equiv for \proposed_pc [24]: failed. + Trying to prove $equiv for \proposed_pc [25]: failed. + Trying to prove $equiv for \proposed_pc [26]: failed. + Trying to prove $equiv for \proposed_pc [27]: failed. + Trying to prove $equiv for \proposed_pc [28]: failed. + Trying to prove $equiv for \proposed_pc [29]: failed. + Trying to prove $equiv for \proposed_pc [30]: failed. + Trying to prove $equiv for \proposed_pc [31]: failed. + Grouping SAT models for \proposed_fp: + Trying to prove $equiv for \proposed_fp [0]: failed. + Trying to prove $equiv for \proposed_fp [1]: failed. + Trying to prove $equiv for \proposed_fp [2]: failed. + Trying to prove $equiv for \proposed_fp [3]: failed. + Trying to prove $equiv for \proposed_fp [4]: failed. + Trying to prove $equiv for \proposed_fp [5]: failed. + Trying to prove $equiv for \proposed_fp [6]: failed. + Trying to prove $equiv for \proposed_fp [7]: failed. + Trying to prove $equiv for \proposed_fp [8]: failed. + Trying to prove $equiv for \proposed_fp [9]: failed. + Trying to prove $equiv for \proposed_fp [10]: failed. + Trying to prove $equiv for \proposed_fp [11]: failed. + Trying to prove $equiv for \proposed_fp [12]: failed. + Trying to prove $equiv for \proposed_fp [13]: failed. + Trying to prove $equiv for \proposed_fp [14]: failed. + Trying to prove $equiv for \proposed_fp [15]: failed. + Trying to prove $equiv for \proposed_fp [16]: failed. + Trying to prove $equiv for \proposed_fp [17]: failed. + Trying to prove $equiv for \proposed_fp [18]: failed. + Trying to prove $equiv for \proposed_fp [19]: failed. + Trying to prove $equiv for \proposed_fp [20]: failed. + Trying to prove $equiv for \proposed_fp [21]: failed. + Trying to prove $equiv for \proposed_fp [22]: failed. + Trying to prove $equiv for \proposed_fp [23]: failed. + Trying to prove $equiv for \proposed_fp [24]: failed. + Trying to prove $equiv for \proposed_fp [25]: failed. + Trying to prove $equiv for \proposed_fp [26]: failed. + Trying to prove $equiv for \proposed_fp [27]: failed. + Trying to prove $equiv for \proposed_fp [28]: failed. + Trying to prove $equiv for \proposed_fp [29]: failed. + Trying to prove $equiv for \proposed_fp [30]: failed. + Trying to prove $equiv for \proposed_fp [31]: failed. + Grouping SAT models for \next_pc_value: + Trying to prove $equiv for \next_pc_value [0]: failed. + Trying to prove $equiv for \next_pc_value [1]: failed. + Trying to prove $equiv for \next_pc_value [2]: failed. + Trying to prove $equiv for \next_pc_value [3]: failed. + Trying to prove $equiv for \next_pc_value [4]: failed. + Trying to prove $equiv for \next_pc_value [5]: failed. + Trying to prove $equiv for \next_pc_value [6]: failed. + Trying to prove $equiv for \next_pc_value [7]: failed. + Trying to prove $equiv for \next_pc_value [8]: failed. + Trying to prove $equiv for \next_pc_value [9]: failed. + Trying to prove $equiv for \next_pc_value [10]: failed. + Trying to prove $equiv for \next_pc_value [11]: failed. + Trying to prove $equiv for \next_pc_value [12]: failed. + Trying to prove $equiv for \next_pc_value [13]: failed. + Trying to prove $equiv for \next_pc_value [14]: failed. + Trying to prove $equiv for \next_pc_value [15]: failed. + Trying to prove $equiv for \next_pc_value [16]: failed. + Trying to prove $equiv for \next_pc_value [17]: failed. + Trying to prove $equiv for \next_pc_value [18]: failed. + Trying to prove $equiv for \next_pc_value [19]: failed. + Trying to prove $equiv for \next_pc_value [20]: failed. + Trying to prove $equiv for \next_pc_value [21]: failed. + Trying to prove $equiv for \next_pc_value [22]: failed. + Trying to prove $equiv for \next_pc_value [23]: failed. + Trying to prove $equiv for \next_pc_value [24]: failed. + Trying to prove $equiv for \next_pc_value [25]: failed. + Trying to prove $equiv for \next_pc_value [26]: failed. + Trying to prove $equiv for \next_pc_value [27]: failed. + Trying to prove $equiv for \next_pc_value [28]: failed. + Trying to prove $equiv for \next_pc_value [29]: failed. + Trying to prove $equiv for \next_pc_value [30]: failed. + Trying to prove $equiv for \next_pc_value [31]: failed. + Grouping SAT models for \next_fp_value: + Trying to prove $equiv for \next_fp_value [0]: failed. + Trying to prove $equiv for \next_fp_value [1]: failed. + Trying to prove $equiv for \next_fp_value [2]: failed. + Trying to prove $equiv for \next_fp_value [3]: failed. + Trying to prove $equiv for \next_fp_value [4]: failed. + Trying to prove $equiv for \next_fp_value [5]: failed. + Trying to prove $equiv for \next_fp_value [6]: failed. + Trying to prove $equiv for \next_fp_value [7]: failed. + Trying to prove $equiv for \next_fp_value [8]: failed. + Trying to prove $equiv for \next_fp_value [9]: failed. + Trying to prove $equiv for \next_fp_value [10]: failed. + Trying to prove $equiv for \next_fp_value [11]: failed. + Trying to prove $equiv for \next_fp_value [12]: failed. + Trying to prove $equiv for \next_fp_value [13]: failed. + Trying to prove $equiv for \next_fp_value [14]: failed. + Trying to prove $equiv for \next_fp_value [15]: failed. + Trying to prove $equiv for \next_fp_value [16]: failed. + Trying to prove $equiv for \next_fp_value [17]: failed. + Trying to prove $equiv for \next_fp_value [18]: failed. + Trying to prove $equiv for \next_fp_value [19]: failed. + Trying to prove $equiv for \next_fp_value [20]: failed. + Trying to prove $equiv for \next_fp_value [21]: failed. + Trying to prove $equiv for \next_fp_value [22]: failed. + Trying to prove $equiv for \next_fp_value [23]: failed. + Trying to prove $equiv for \next_fp_value [24]: failed. + Trying to prove $equiv for \next_fp_value [25]: failed. + Trying to prove $equiv for \next_fp_value [26]: failed. + Trying to prove $equiv for \next_fp_value [27]: failed. + Trying to prove $equiv for \next_fp_value [28]: failed. + Trying to prove $equiv for \next_fp_value [29]: failed. + Trying to prove $equiv for \next_fp_value [30]: failed. + Trying to prove $equiv for \next_fp_value [31]: failed. + Grouping SAT models for \deferred_target: + Trying to prove $equiv for \deferred_target [0]: failed. + Trying to prove $equiv for \deferred_target [1]: failed. + Trying to prove $equiv for \deferred_target [2]: failed. + Trying to prove $equiv for \deferred_target [3]: failed. + Trying to prove $equiv for \deferred_target [4]: failed. + Trying to prove $equiv for \deferred_target [5]: failed. + Trying to prove $equiv for \deferred_target [6]: failed. + Trying to prove $equiv for \deferred_target [7]: failed. + Trying to prove $equiv for \deferred_target [8]: failed. + Trying to prove $equiv for \deferred_target [9]: failed. + Trying to prove $equiv for \deferred_target [10]: failed. + Trying to prove $equiv for \deferred_target [11]: failed. + Trying to prove $equiv for \deferred_target [12]: failed. + Trying to prove $equiv for \deferred_target [13]: failed. + Trying to prove $equiv for \deferred_target [14]: failed. + Trying to prove $equiv for \deferred_target [15]: failed. + Trying to prove $equiv for \deferred_target [16]: failed. + Trying to prove $equiv for \deferred_target [17]: failed. + Trying to prove $equiv for \deferred_target [18]: failed. + Trying to prove $equiv for \deferred_target [19]: failed. + Trying to prove $equiv for \deferred_target [20]: failed. + Trying to prove $equiv for \deferred_target [21]: failed. + Trying to prove $equiv for \deferred_target [22]: failed. + Trying to prove $equiv for \deferred_target [23]: failed. + Trying to prove $equiv for \deferred_target [24]: failed. + Trying to prove $equiv for \deferred_target [25]: failed. + Trying to prove $equiv for \deferred_target [26]: failed. + Trying to prove $equiv for \deferred_target [27]: failed. + Trying to prove $equiv for \deferred_target [28]: failed. + Trying to prove $equiv for \deferred_target [29]: failed. + Trying to prove $equiv for \deferred_target [30]: failed. + Trying to prove $equiv for \deferred_target [31]: failed. + Grouping SAT models for \deferred_local: + Trying to prove $equiv for \deferred_local [0]: failed. + Trying to prove $equiv for \deferred_local [1]: failed. + Trying to prove $equiv for \deferred_local [2]: failed. + Trying to prove $equiv for \deferred_local [3]: failed. + Trying to prove $equiv for \deferred_local [4]: failed. + Trying to prove $equiv for \deferred_local [5]: failed. + Trying to prove $equiv for \deferred_local [6]: failed. + Trying to prove $equiv for \deferred_local [7]: failed. + Trying to prove $equiv for \deferred_local [8]: failed. + Trying to prove $equiv for \deferred_local [9]: failed. + Trying to prove $equiv for \deferred_local [10]: failed. + Trying to prove $equiv for \deferred_local [11]: failed. + Trying to prove $equiv for \deferred_local [12]: failed. + Trying to prove $equiv for \deferred_local [13]: failed. + Trying to prove $equiv for \deferred_local [14]: failed. + Trying to prove $equiv for \deferred_local [15]: failed. + Trying to prove $equiv for \deferred_local [16]: failed. + Trying to prove $equiv for \deferred_local [17]: failed. + Trying to prove $equiv for \deferred_local [18]: failed. + Trying to prove $equiv for \deferred_local [19]: failed. + Trying to prove $equiv for \deferred_local [20]: failed. + Trying to prove $equiv for \deferred_local [21]: failed. + Trying to prove $equiv for \deferred_local [22]: failed. + Trying to prove $equiv for \deferred_local [23]: failed. + Trying to prove $equiv for \deferred_local [24]: failed. + Trying to prove $equiv for \deferred_local [25]: failed. + Trying to prove $equiv for \deferred_local [26]: failed. + Trying to prove $equiv for \deferred_local [27]: failed. + Trying to prove $equiv for \deferred_local [28]: failed. + Trying to prove $equiv for \deferred_local [29]: failed. + Trying to prove $equiv for \deferred_local [30]: failed. + Trying to prove $equiv for \deferred_local [31]: failed. + Grouping SAT models for \profile: + Trying to prove $equiv for \profile [0]: failed. + Trying to prove $equiv for \profile [1]: failed. + Trying to prove $equiv for \profile [2]: failed. + Trying to prove $equiv for \profile [3]: failed. + Trying to prove $equiv for \profile [4]: failed. + Trying to prove $equiv for \profile [5]: failed. + Trying to prove $equiv for \profile [6]: failed. + Trying to prove $equiv for \profile [7]: failed. + Grouping SAT models for \pres_a: + Trying to prove $equiv for \pres_a [0]: failed. + Trying to prove $equiv for \pres_a [1]: failed. + Trying to prove $equiv for \pres_a [2]: failed. + Trying to prove $equiv for \pres_a [3]: failed. + Trying to prove $equiv for \pres_a [4]: failed. + Trying to prove $equiv for \pres_a [5]: failed. + Trying to prove $equiv for \pres_a [6]: failed. + Trying to prove $equiv for \pres_a [7]: failed. + Grouping SAT models for \pres_b: + Trying to prove $equiv for \pres_b [0]: failed. + Trying to prove $equiv for \pres_b [1]: failed. + Trying to prove $equiv for \pres_b [2]: failed. + Trying to prove $equiv for \pres_b [3]: failed. + Trying to prove $equiv for \pres_b [4]: failed. + Trying to prove $equiv for \pres_b [5]: failed. + Trying to prove $equiv for \pres_b [6]: failed. + Trying to prove $equiv for \pres_b [7]: failed. + Grouping SAT models for \pres_c: + Trying to prove $equiv for \pres_c [0]: failed. + Trying to prove $equiv for \pres_c [1]: failed. + Trying to prove $equiv for \pres_c [2]: failed. + Trying to prove $equiv for \pres_c [3]: failed. + Trying to prove $equiv for \pres_c [4]: failed. + Trying to prove $equiv for \pres_c [5]: failed. + Trying to prove $equiv for \pres_c [6]: failed. + Trying to prove $equiv for \pres_c [7]: failed. + Grouping SAT models for \val_a: + Trying to prove $equiv for \val_a [0]: failed. + Trying to prove $equiv for \val_a [1]: failed. + Trying to prove $equiv for \val_a [2]: failed. + Trying to prove $equiv for \val_a [3]: failed. + Trying to prove $equiv for \val_a [4]: failed. + Trying to prove $equiv for \val_a [5]: failed. + Trying to prove $equiv for \val_a [6]: failed. + Trying to prove $equiv for \val_a [7]: failed. + Trying to prove $equiv for \val_a [8]: failed. + Trying to prove $equiv for \val_a [9]: failed. + Trying to prove $equiv for \val_a [10]: failed. + Trying to prove $equiv for \val_a [11]: failed. + Trying to prove $equiv for \val_a [12]: failed. + Trying to prove $equiv for \val_a [13]: failed. + Trying to prove $equiv for \val_a [14]: failed. + Trying to prove $equiv for \val_a [15]: failed. + Trying to prove $equiv for \val_a [16]: failed. + Trying to prove $equiv for \val_a [17]: failed. + Trying to prove $equiv for \val_a [18]: failed. + Trying to prove $equiv for \val_a [19]: failed. + Trying to prove $equiv for \val_a [20]: failed. + Trying to prove $equiv for \val_a [21]: failed. + Trying to prove $equiv for \val_a [22]: failed. + Trying to prove $equiv for \val_a [23]: failed. + Trying to prove $equiv for \val_a [24]: failed. + Trying to prove $equiv for \val_a [25]: failed. + Trying to prove $equiv for \val_a [26]: failed. + Trying to prove $equiv for \val_a [27]: failed. + Trying to prove $equiv for \val_a [28]: failed. + Trying to prove $equiv for \val_a [29]: failed. + Trying to prove $equiv for \val_a [30]: failed. + Trying to prove $equiv for \val_a [31]: failed. + Trying to prove $equiv for \val_a [32]: failed. + Trying to prove $equiv for \val_a [33]: failed. + Trying to prove $equiv for \val_a [34]: failed. + Trying to prove $equiv for \val_a [35]: failed. + Trying to prove $equiv for \val_a [36]: failed. + Trying to prove $equiv for \val_a [37]: failed. + Trying to prove $equiv for \val_a [38]: failed. + Trying to prove $equiv for \val_a [39]: failed. + Trying to prove $equiv for \val_a [40]: failed. + Trying to prove $equiv for \val_a [41]: failed. + Trying to prove $equiv for \val_a [42]: failed. + Trying to prove $equiv for \val_a [43]: failed. + Trying to prove $equiv for \val_a [44]: failed. + Trying to prove $equiv for \val_a [45]: failed. + Trying to prove $equiv for \val_a [46]: failed. + Trying to prove $equiv for \val_a [47]: failed. + Trying to prove $equiv for \val_a [48]: failed. + Trying to prove $equiv for \val_a [49]: failed. + Trying to prove $equiv for \val_a [50]: failed. + Trying to prove $equiv for \val_a [51]: failed. + Trying to prove $equiv for \val_a [52]: failed. + Trying to prove $equiv for \val_a [53]: failed. + Trying to prove $equiv for \val_a [54]: failed. + Trying to prove $equiv for \val_a [55]: failed. + Trying to prove $equiv for \val_a [56]: failed. + Trying to prove $equiv for \val_a [57]: failed. + Trying to prove $equiv for \val_a [58]: failed. + Trying to prove $equiv for \val_a [59]: failed. + Trying to prove $equiv for \val_a [60]: failed. + Trying to prove $equiv for \val_a [61]: failed. + Trying to prove $equiv for \val_a [62]: failed. + Trying to prove $equiv for \val_a [63]: failed. + Trying to prove $equiv for \val_a [64]: failed. + Trying to prove $equiv for \val_a [65]: failed. + Trying to prove $equiv for \val_a [66]: failed. + Trying to prove $equiv for \val_a [67]: failed. + Trying to prove $equiv for \val_a [68]: failed. + Trying to prove $equiv for \val_a [69]: failed. + Trying to prove $equiv for \val_a [70]: failed. + Trying to prove $equiv for \val_a [71]: failed. + Trying to prove $equiv for \val_a [72]: failed. + Trying to prove $equiv for \val_a [73]: failed. + Trying to prove $equiv for \val_a [74]: failed. + Trying to prove $equiv for \val_a [75]: failed. + Trying to prove $equiv for \val_a [76]: failed. + Trying to prove $equiv for \val_a [77]: failed. + Trying to prove $equiv for \val_a [78]: failed. + Trying to prove $equiv for \val_a [79]: failed. + Trying to prove $equiv for \val_a [80]: failed. + Trying to prove $equiv for \val_a [81]: failed. + Trying to prove $equiv for \val_a [82]: failed. + Trying to prove $equiv for \val_a [83]: failed. + Trying to prove $equiv for \val_a [84]: failed. + Trying to prove $equiv for \val_a [85]: failed. + Trying to prove $equiv for \val_a [86]: failed. + Trying to prove $equiv for \val_a [87]: failed. + Trying to prove $equiv for \val_a [88]: failed. + Trying to prove $equiv for \val_a [89]: failed. + Trying to prove $equiv for \val_a [90]: failed. + Trying to prove $equiv for \val_a [91]: failed. + Trying to prove $equiv for \val_a [92]: failed. + Trying to prove $equiv for \val_a [93]: failed. + Trying to prove $equiv for \val_a [94]: failed. + Trying to prove $equiv for \val_a [95]: failed. + Trying to prove $equiv for \val_a [96]: failed. + Trying to prove $equiv for \val_a [97]: failed. + Trying to prove $equiv for \val_a [98]: failed. + Trying to prove $equiv for \val_a [99]: failed. + Trying to prove $equiv for \val_a [100]: failed. + Trying to prove $equiv for \val_a [101]: failed. + Trying to prove $equiv for \val_a [102]: failed. + Trying to prove $equiv for \val_a [103]: failed. + Trying to prove $equiv for \val_a [104]: failed. + Trying to prove $equiv for \val_a [105]: failed. + Trying to prove $equiv for \val_a [106]: failed. + Trying to prove $equiv for \val_a [107]: failed. + Trying to prove $equiv for \val_a [108]: failed. + Trying to prove $equiv for \val_a [109]: failed. + Trying to prove $equiv for \val_a [110]: failed. + Trying to prove $equiv for \val_a [111]: failed. + Trying to prove $equiv for \val_a [112]: failed. + Trying to prove $equiv for \val_a [113]: failed. + Trying to prove $equiv for \val_a [114]: failed. + Trying to prove $equiv for \val_a [115]: failed. + Trying to prove $equiv for \val_a [116]: failed. + Trying to prove $equiv for \val_a [117]: failed. + Trying to prove $equiv for \val_a [118]: failed. + Trying to prove $equiv for \val_a [119]: failed. + Trying to prove $equiv for \val_a [120]: failed. + Trying to prove $equiv for \val_a [121]: failed. + Trying to prove $equiv for \val_a [122]: failed. + Trying to prove $equiv for \val_a [123]: failed. + Trying to prove $equiv for \val_a [124]: failed. + Trying to prove $equiv for \val_a [125]: failed. + Trying to prove $equiv for \val_a [126]: failed. + Trying to prove $equiv for \val_a [127]: failed. + Grouping SAT models for \val_b: + Trying to prove $equiv for \val_b [0]: failed. + Trying to prove $equiv for \val_b [1]: failed. + Trying to prove $equiv for \val_b [2]: failed. + Trying to prove $equiv for \val_b [3]: failed. + Trying to prove $equiv for \val_b [4]: failed. + Trying to prove $equiv for \val_b [5]: failed. + Trying to prove $equiv for \val_b [6]: failed. + Trying to prove $equiv for \val_b [7]: failed. + Trying to prove $equiv for \val_b [8]: failed. + Trying to prove $equiv for \val_b [9]: failed. + Trying to prove $equiv for \val_b [10]: failed. + Trying to prove $equiv for \val_b [11]: failed. + Trying to prove $equiv for \val_b [12]: failed. + Trying to prove $equiv for \val_b [13]: failed. + Trying to prove $equiv for \val_b [14]: failed. + Trying to prove $equiv for \val_b [15]: failed. + Trying to prove $equiv for \val_b [16]: failed. + Trying to prove $equiv for \val_b [17]: failed. + Trying to prove $equiv for \val_b [18]: failed. + Trying to prove $equiv for \val_b [19]: failed. + Trying to prove $equiv for \val_b [20]: failed. + Trying to prove $equiv for \val_b [21]: failed. + Trying to prove $equiv for \val_b [22]: failed. + Trying to prove $equiv for \val_b [23]: failed. + Trying to prove $equiv for \val_b [24]: failed. + Trying to prove $equiv for \val_b [25]: failed. + Trying to prove $equiv for \val_b [26]: failed. + Trying to prove $equiv for \val_b [27]: failed. + Trying to prove $equiv for \val_b [28]: failed. + Trying to prove $equiv for \val_b [29]: failed. + Trying to prove $equiv for \val_b [30]: failed. + Trying to prove $equiv for \val_b [31]: failed. + Trying to prove $equiv for \val_b [32]: failed. + Trying to prove $equiv for \val_b [33]: failed. + Trying to prove $equiv for \val_b [34]: failed. + Trying to prove $equiv for \val_b [35]: failed. + Trying to prove $equiv for \val_b [36]: failed. + Trying to prove $equiv for \val_b [37]: failed. + Trying to prove $equiv for \val_b [38]: failed. + Trying to prove $equiv for \val_b [39]: failed. + Trying to prove $equiv for \val_b [40]: failed. + Trying to prove $equiv for \val_b [41]: failed. + Trying to prove $equiv for \val_b [42]: failed. + Trying to prove $equiv for \val_b [43]: failed. + Trying to prove $equiv for \val_b [44]: failed. + Trying to prove $equiv for \val_b [45]: failed. + Trying to prove $equiv for \val_b [46]: failed. + Trying to prove $equiv for \val_b [47]: failed. + Trying to prove $equiv for \val_b [48]: failed. + Trying to prove $equiv for \val_b [49]: failed. + Trying to prove $equiv for \val_b [50]: failed. + Trying to prove $equiv for \val_b [51]: failed. + Trying to prove $equiv for \val_b [52]: failed. + Trying to prove $equiv for \val_b [53]: failed. + Trying to prove $equiv for \val_b [54]: failed. + Trying to prove $equiv for \val_b [55]: failed. + Trying to prove $equiv for \val_b [56]: failed. + Trying to prove $equiv for \val_b [57]: failed. + Trying to prove $equiv for \val_b [58]: failed. + Trying to prove $equiv for \val_b [59]: failed. + Trying to prove $equiv for \val_b [60]: failed. + Trying to prove $equiv for \val_b [61]: failed. + Trying to prove $equiv for \val_b [62]: failed. + Trying to prove $equiv for \val_b [63]: failed. + Trying to prove $equiv for \val_b [64]: failed. + Trying to prove $equiv for \val_b [65]: failed. + Trying to prove $equiv for \val_b [66]: failed. + Trying to prove $equiv for \val_b [67]: failed. + Trying to prove $equiv for \val_b [68]: failed. + Trying to prove $equiv for \val_b [69]: failed. + Trying to prove $equiv for \val_b [70]: failed. + Trying to prove $equiv for \val_b [71]: failed. + Trying to prove $equiv for \val_b [72]: failed. + Trying to prove $equiv for \val_b [73]: failed. + Trying to prove $equiv for \val_b [74]: failed. + Trying to prove $equiv for \val_b [75]: failed. + Trying to prove $equiv for \val_b [76]: failed. + Trying to prove $equiv for \val_b [77]: failed. + Trying to prove $equiv for \val_b [78]: failed. + Trying to prove $equiv for \val_b [79]: failed. + Trying to prove $equiv for \val_b [80]: failed. + Trying to prove $equiv for \val_b [81]: failed. + Trying to prove $equiv for \val_b [82]: failed. + Trying to prove $equiv for \val_b [83]: failed. + Trying to prove $equiv for \val_b [84]: failed. + Trying to prove $equiv for \val_b [85]: failed. + Trying to prove $equiv for \val_b [86]: failed. + Trying to prove $equiv for \val_b [87]: failed. + Trying to prove $equiv for \val_b [88]: failed. + Trying to prove $equiv for \val_b [89]: failed. + Trying to prove $equiv for \val_b [90]: failed. + Trying to prove $equiv for \val_b [91]: failed. + Trying to prove $equiv for \val_b [92]: failed. + Trying to prove $equiv for \val_b [93]: failed. + Trying to prove $equiv for \val_b [94]: failed. + Trying to prove $equiv for \val_b [95]: failed. + Trying to prove $equiv for \val_b [96]: failed. + Trying to prove $equiv for \val_b [97]: failed. + Trying to prove $equiv for \val_b [98]: failed. + Trying to prove $equiv for \val_b [99]: failed. + Trying to prove $equiv for \val_b [100]: failed. + Trying to prove $equiv for \val_b [101]: failed. + Trying to prove $equiv for \val_b [102]: failed. + Trying to prove $equiv for \val_b [103]: failed. + Trying to prove $equiv for \val_b [104]: failed. + Trying to prove $equiv for \val_b [105]: failed. + Trying to prove $equiv for \val_b [106]: failed. + Trying to prove $equiv for \val_b [107]: failed. + Trying to prove $equiv for \val_b [108]: failed. + Trying to prove $equiv for \val_b [109]: failed. + Trying to prove $equiv for \val_b [110]: failed. + Trying to prove $equiv for \val_b [111]: failed. + Trying to prove $equiv for \val_b [112]: failed. + Trying to prove $equiv for \val_b [113]: failed. + Trying to prove $equiv for \val_b [114]: failed. + Trying to prove $equiv for \val_b [115]: failed. + Trying to prove $equiv for \val_b [116]: failed. + Trying to prove $equiv for \val_b [117]: failed. + Trying to prove $equiv for \val_b [118]: failed. + Trying to prove $equiv for \val_b [119]: failed. + Trying to prove $equiv for \val_b [120]: failed. + Trying to prove $equiv for \val_b [121]: failed. + Trying to prove $equiv for \val_b [122]: failed. + Trying to prove $equiv for \val_b [123]: failed. + Trying to prove $equiv for \val_b [124]: failed. + Trying to prove $equiv for \val_b [125]: failed. + Trying to prove $equiv for \val_b [126]: failed. + Trying to prove $equiv for \val_b [127]: failed. + Grouping SAT models for \val_c: + Trying to prove $equiv for \val_c [0]: failed. + Trying to prove $equiv for \val_c [1]: failed. + Trying to prove $equiv for \val_c [2]: failed. + Trying to prove $equiv for \val_c [3]: failed. + Trying to prove $equiv for \val_c [4]: failed. + Trying to prove $equiv for \val_c [5]: failed. + Trying to prove $equiv for \val_c [6]: failed. + Trying to prove $equiv for \val_c [7]: failed. + Trying to prove $equiv for \val_c [8]: failed. + Trying to prove $equiv for \val_c [9]: failed. + Trying to prove $equiv for \val_c [10]: failed. + Trying to prove $equiv for \val_c [11]: failed. + Trying to prove $equiv for \val_c [12]: failed. + Trying to prove $equiv for \val_c [13]: failed. + Trying to prove $equiv for \val_c [14]: failed. + Trying to prove $equiv for \val_c [15]: failed. + Trying to prove $equiv for \val_c [16]: failed. + Trying to prove $equiv for \val_c [17]: failed. + Trying to prove $equiv for \val_c [18]: failed. + Trying to prove $equiv for \val_c [19]: failed. + Trying to prove $equiv for \val_c [20]: failed. + Trying to prove $equiv for \val_c [21]: failed. + Trying to prove $equiv for \val_c [22]: failed. + Trying to prove $equiv for \val_c [23]: failed. + Trying to prove $equiv for \val_c [24]: failed. + Trying to prove $equiv for \val_c [25]: failed. + Trying to prove $equiv for \val_c [26]: failed. + Trying to prove $equiv for \val_c [27]: failed. + Trying to prove $equiv for \val_c [28]: failed. + Trying to prove $equiv for \val_c [29]: failed. + Trying to prove $equiv for \val_c [30]: failed. + Trying to prove $equiv for \val_c [31]: failed. + Trying to prove $equiv for \val_c [32]: failed. + Trying to prove $equiv for \val_c [33]: failed. + Trying to prove $equiv for \val_c [34]: failed. + Trying to prove $equiv for \val_c [35]: failed. + Trying to prove $equiv for \val_c [36]: failed. + Trying to prove $equiv for \val_c [37]: failed. + Trying to prove $equiv for \val_c [38]: failed. + Trying to prove $equiv for \val_c [39]: failed. + Trying to prove $equiv for \val_c [40]: failed. + Trying to prove $equiv for \val_c [41]: failed. + Trying to prove $equiv for \val_c [42]: failed. + Trying to prove $equiv for \val_c [43]: failed. + Trying to prove $equiv for \val_c [44]: failed. + Trying to prove $equiv for \val_c [45]: failed. + Trying to prove $equiv for \val_c [46]: failed. + Trying to prove $equiv for \val_c [47]: failed. + Trying to prove $equiv for \val_c [48]: failed. + Trying to prove $equiv for \val_c [49]: failed. + Trying to prove $equiv for \val_c [50]: failed. + Trying to prove $equiv for \val_c [51]: failed. + Trying to prove $equiv for \val_c [52]: failed. + Trying to prove $equiv for \val_c [53]: failed. + Trying to prove $equiv for \val_c [54]: failed. + Trying to prove $equiv for \val_c [55]: failed. + Trying to prove $equiv for \val_c [56]: failed. + Trying to prove $equiv for \val_c [57]: failed. + Trying to prove $equiv for \val_c [58]: failed. + Trying to prove $equiv for \val_c [59]: failed. + Trying to prove $equiv for \val_c [60]: failed. + Trying to prove $equiv for \val_c [61]: failed. + Trying to prove $equiv for \val_c [62]: failed. + Trying to prove $equiv for \val_c [63]: failed. + Trying to prove $equiv for \val_c [64]: failed. + Trying to prove $equiv for \val_c [65]: failed. + Trying to prove $equiv for \val_c [66]: failed. + Trying to prove $equiv for \val_c [67]: failed. + Trying to prove $equiv for \val_c [68]: failed. + Trying to prove $equiv for \val_c [69]: failed. + Trying to prove $equiv for \val_c [70]: failed. + Trying to prove $equiv for \val_c [71]: failed. + Trying to prove $equiv for \val_c [72]: failed. + Trying to prove $equiv for \val_c [73]: failed. + Trying to prove $equiv for \val_c [74]: failed. + Trying to prove $equiv for \val_c [75]: failed. + Trying to prove $equiv for \val_c [76]: failed. + Trying to prove $equiv for \val_c [77]: failed. + Trying to prove $equiv for \val_c [78]: failed. + Trying to prove $equiv for \val_c [79]: failed. + Trying to prove $equiv for \val_c [80]: failed. + Trying to prove $equiv for \val_c [81]: failed. + Trying to prove $equiv for \val_c [82]: failed. + Trying to prove $equiv for \val_c [83]: failed. + Trying to prove $equiv for \val_c [84]: failed. + Trying to prove $equiv for \val_c [85]: failed. + Trying to prove $equiv for \val_c [86]: failed. + Trying to prove $equiv for \val_c [87]: failed. + Trying to prove $equiv for \val_c [88]: failed. + Trying to prove $equiv for \val_c [89]: failed. + Trying to prove $equiv for \val_c [90]: failed. + Trying to prove $equiv for \val_c [91]: failed. + Trying to prove $equiv for \val_c [92]: failed. + Trying to prove $equiv for \val_c [93]: failed. + Trying to prove $equiv for \val_c [94]: failed. + Trying to prove $equiv for \val_c [95]: failed. + Trying to prove $equiv for \val_c [96]: failed. + Trying to prove $equiv for \val_c [97]: failed. + Trying to prove $equiv for \val_c [98]: failed. + Trying to prove $equiv for \val_c [99]: failed. + Trying to prove $equiv for \val_c [100]: failed. + Trying to prove $equiv for \val_c [101]: failed. + Trying to prove $equiv for \val_c [102]: failed. + Trying to prove $equiv for \val_c [103]: failed. + Trying to prove $equiv for \val_c [104]: failed. + Trying to prove $equiv for \val_c [105]: failed. + Trying to prove $equiv for \val_c [106]: failed. + Trying to prove $equiv for \val_c [107]: failed. + Trying to prove $equiv for \val_c [108]: failed. + Trying to prove $equiv for \val_c [109]: failed. + Trying to prove $equiv for \val_c [110]: failed. + Trying to prove $equiv for \val_c [111]: failed. + Trying to prove $equiv for \val_c [112]: failed. + Trying to prove $equiv for \val_c [113]: failed. + Trying to prove $equiv for \val_c [114]: failed. + Trying to prove $equiv for \val_c [115]: failed. + Trying to prove $equiv for \val_c [116]: failed. + Trying to prove $equiv for \val_c [117]: failed. + Trying to prove $equiv for \val_c [118]: failed. + Trying to prove $equiv for \val_c [119]: failed. + Trying to prove $equiv for \val_c [120]: failed. + Trying to prove $equiv for \val_c [121]: failed. + Trying to prove $equiv for \val_c [122]: failed. + Trying to prove $equiv for \val_c [123]: failed. + Trying to prove $equiv for \val_c [124]: failed. + Trying to prove $equiv for \val_c [125]: failed. + Trying to prove $equiv for \val_c [126]: failed. + Trying to prove $equiv for \val_c [127]: failed. + Grouping SAT models for \inv_value: + Trying to prove $equiv for \inv_value [0]: failed. + Trying to prove $equiv for \inv_value [1]: failed. + Trying to prove $equiv for \inv_value [2]: failed. + Trying to prove $equiv for \inv_value [3]: failed. + Trying to prove $equiv for \inv_value [4]: failed. + Trying to prove $equiv for \inv_value [5]: failed. + Trying to prove $equiv for \inv_value [6]: failed. + Trying to prove $equiv for \inv_value [7]: failed. + Trying to prove $equiv for \inv_value [8]: failed. + Trying to prove $equiv for \inv_value [9]: failed. + Trying to prove $equiv for \inv_value [10]: failed. + Trying to prove $equiv for \inv_value [11]: failed. + Trying to prove $equiv for \inv_value [12]: failed. + Trying to prove $equiv for \inv_value [13]: failed. + Trying to prove $equiv for \inv_value [14]: failed. + Trying to prove $equiv for \inv_value [15]: failed. + Trying to prove $equiv for \inv_value [16]: failed. + Trying to prove $equiv for \inv_value [17]: failed. + Trying to prove $equiv for \inv_value [18]: failed. + Trying to prove $equiv for \inv_value [19]: failed. + Trying to prove $equiv for \inv_value [20]: failed. + Trying to prove $equiv for \inv_value [21]: failed. + Trying to prove $equiv for \inv_value [22]: failed. + Trying to prove $equiv for \inv_value [23]: failed. + Trying to prove $equiv for \inv_value [24]: failed. + Trying to prove $equiv for \inv_value [25]: failed. + Trying to prove $equiv for \inv_value [26]: failed. + Trying to prove $equiv for \inv_value [27]: failed. + Trying to prove $equiv for \inv_value [28]: failed. + Trying to prove $equiv for \inv_value [29]: failed. + Trying to prove $equiv for \inv_value [30]: failed. + Trying to prove $equiv for \inv_value [31]: failed. + Trying to prove $equiv for \inv_value [32]: failed. + Trying to prove $equiv for \inv_value [33]: failed. + Trying to prove $equiv for \inv_value [34]: failed. + Trying to prove $equiv for \inv_value [35]: failed. + Trying to prove $equiv for \inv_value [36]: failed. + Trying to prove $equiv for \inv_value [37]: failed. + Trying to prove $equiv for \inv_value [38]: failed. + Trying to prove $equiv for \inv_value [39]: failed. + Trying to prove $equiv for \inv_value [40]: failed. + Trying to prove $equiv for \inv_value [41]: failed. + Trying to prove $equiv for \inv_value [42]: failed. + Trying to prove $equiv for \inv_value [43]: failed. + Trying to prove $equiv for \inv_value [44]: failed. + Trying to prove $equiv for \inv_value [45]: failed. + Trying to prove $equiv for \inv_value [46]: failed. + Trying to prove $equiv for \inv_value [47]: failed. + Trying to prove $equiv for \inv_value [48]: failed. + Trying to prove $equiv for \inv_value [49]: failed. + Trying to prove $equiv for \inv_value [50]: failed. + Trying to prove $equiv for \inv_value [51]: failed. + Trying to prove $equiv for \inv_value [52]: failed. + Trying to prove $equiv for \inv_value [53]: failed. + Trying to prove $equiv for \inv_value [54]: failed. + Trying to prove $equiv for \inv_value [55]: failed. + Trying to prove $equiv for \inv_value [56]: failed. + Trying to prove $equiv for \inv_value [57]: failed. + Trying to prove $equiv for \inv_value [58]: failed. + Trying to prove $equiv for \inv_value [59]: failed. + Trying to prove $equiv for \inv_value [60]: failed. + Trying to prove $equiv for \inv_value [61]: failed. + Trying to prove $equiv for \inv_value [62]: failed. + Trying to prove $equiv for \inv_value [63]: failed. + Trying to prove $equiv for \inv_value [64]: failed. + Trying to prove $equiv for \inv_value [65]: failed. + Trying to prove $equiv for \inv_value [66]: failed. + Trying to prove $equiv for \inv_value [67]: failed. + Trying to prove $equiv for \inv_value [68]: failed. + Trying to prove $equiv for \inv_value [69]: failed. + Trying to prove $equiv for \inv_value [70]: failed. + Trying to prove $equiv for \inv_value [71]: failed. + Trying to prove $equiv for \inv_value [72]: failed. + Trying to prove $equiv for \inv_value [73]: failed. + Trying to prove $equiv for \inv_value [74]: failed. + Trying to prove $equiv for \inv_value [75]: failed. + Trying to prove $equiv for \inv_value [76]: failed. + Trying to prove $equiv for \inv_value [77]: failed. + Trying to prove $equiv for \inv_value [78]: failed. + Trying to prove $equiv for \inv_value [79]: failed. + Trying to prove $equiv for \inv_value [80]: failed. + Trying to prove $equiv for \inv_value [81]: failed. + Trying to prove $equiv for \inv_value [82]: failed. + Trying to prove $equiv for \inv_value [83]: failed. + Trying to prove $equiv for \inv_value [84]: failed. + Trying to prove $equiv for \inv_value [85]: failed. + Trying to prove $equiv for \inv_value [86]: failed. + Trying to prove $equiv for \inv_value [87]: failed. + Trying to prove $equiv for \inv_value [88]: failed. + Trying to prove $equiv for \inv_value [89]: failed. + Trying to prove $equiv for \inv_value [90]: failed. + Trying to prove $equiv for \inv_value [91]: failed. + Trying to prove $equiv for \inv_value [92]: failed. + Trying to prove $equiv for \inv_value [93]: failed. + Trying to prove $equiv for \inv_value [94]: failed. + Trying to prove $equiv for \inv_value [95]: failed. + Trying to prove $equiv for \inv_value [96]: failed. + Trying to prove $equiv for \inv_value [97]: failed. + Trying to prove $equiv for \inv_value [98]: failed. + Trying to prove $equiv for \inv_value [99]: failed. + Trying to prove $equiv for \inv_value [100]: failed. + Trying to prove $equiv for \inv_value [101]: failed. + Trying to prove $equiv for \inv_value [102]: failed. + Trying to prove $equiv for \inv_value [103]: failed. + Trying to prove $equiv for \inv_value [104]: failed. + Trying to prove $equiv for \inv_value [105]: failed. + Trying to prove $equiv for \inv_value [106]: failed. + Trying to prove $equiv for \inv_value [107]: failed. + Trying to prove $equiv for \inv_value [108]: failed. + Trying to prove $equiv for \inv_value [109]: failed. + Trying to prove $equiv for \inv_value [110]: failed. + Trying to prove $equiv for \inv_value [111]: failed. + Trying to prove $equiv for \inv_value [112]: failed. + Trying to prove $equiv for \inv_value [113]: failed. + Trying to prove $equiv for \inv_value [114]: failed. + Trying to prove $equiv for \inv_value [115]: failed. + Trying to prove $equiv for \inv_value [116]: failed. + Trying to prove $equiv for \inv_value [117]: failed. + Trying to prove $equiv for \inv_value [118]: failed. + Trying to prove $equiv for \inv_value [119]: failed. + Trying to prove $equiv for \inv_value [120]: failed. + Trying to prove $equiv for \inv_value [121]: failed. + Trying to prove $equiv for \inv_value [122]: failed. + Trying to prove $equiv for \inv_value [123]: failed. + Trying to prove $equiv for \inv_value [124]: failed. + Trying to prove $equiv for \inv_value [125]: failed. + Trying to prove $equiv for \inv_value [126]: failed. + Trying to prove $equiv for \inv_value [127]: failed. + Grouping SAT models for \result_value: + Trying to prove $equiv for \result_value [0]: failed. + Trying to prove $equiv for \result_value [1]: failed. + Trying to prove $equiv for \result_value [2]: failed. + Trying to prove $equiv for \result_value [3]: failed. + Trying to prove $equiv for \result_value [4]: failed. + Trying to prove $equiv for \result_value [5]: failed. + Trying to prove $equiv for \result_value [6]: failed. + Trying to prove $equiv for \result_value [7]: failed. + Trying to prove $equiv for \result_value [8]: failed. + Trying to prove $equiv for \result_value [9]: failed. + Trying to prove $equiv for \result_value [10]: failed. + Trying to prove $equiv for \result_value [11]: failed. + Trying to prove $equiv for \result_value [12]: failed. + Trying to prove $equiv for \result_value [13]: failed. + Trying to prove $equiv for \result_value [14]: failed. + Trying to prove $equiv for \result_value [15]: failed. + Trying to prove $equiv for \result_value [16]: failed. + Trying to prove $equiv for \result_value [17]: failed. + Trying to prove $equiv for \result_value [18]: failed. + Trying to prove $equiv for \result_value [19]: failed. + Trying to prove $equiv for \result_value [20]: failed. + Trying to prove $equiv for \result_value [21]: failed. + Trying to prove $equiv for \result_value [22]: failed. + Trying to prove $equiv for \result_value [23]: failed. + Trying to prove $equiv for \result_value [24]: failed. + Trying to prove $equiv for \result_value [25]: failed. + Trying to prove $equiv for \result_value [26]: failed. + Trying to prove $equiv for \result_value [27]: failed. + Trying to prove $equiv for \result_value [28]: failed. + Trying to prove $equiv for \result_value [29]: failed. + Trying to prove $equiv for \result_value [30]: failed. + Trying to prove $equiv for \result_value [31]: failed. + Trying to prove $equiv for \result_value [32]: failed. + Trying to prove $equiv for \result_value [33]: failed. + Trying to prove $equiv for \result_value [34]: failed. + Trying to prove $equiv for \result_value [35]: failed. + Trying to prove $equiv for \result_value [36]: failed. + Trying to prove $equiv for \result_value [37]: failed. + Trying to prove $equiv for \result_value [38]: failed. + Trying to prove $equiv for \result_value [39]: failed. + Trying to prove $equiv for \result_value [40]: failed. + Trying to prove $equiv for \result_value [41]: failed. + Trying to prove $equiv for \result_value [42]: failed. + Trying to prove $equiv for \result_value [43]: failed. + Trying to prove $equiv for \result_value [44]: failed. + Trying to prove $equiv for \result_value [45]: failed. + Trying to prove $equiv for \result_value [46]: failed. + Trying to prove $equiv for \result_value [47]: failed. + Trying to prove $equiv for \result_value [48]: failed. + Trying to prove $equiv for \result_value [49]: failed. + Trying to prove $equiv for \result_value [50]: failed. + Trying to prove $equiv for \result_value [51]: failed. + Trying to prove $equiv for \result_value [52]: failed. + Trying to prove $equiv for \result_value [53]: failed. + Trying to prove $equiv for \result_value [54]: failed. + Trying to prove $equiv for \result_value [55]: failed. + Trying to prove $equiv for \result_value [56]: failed. + Trying to prove $equiv for \result_value [57]: failed. + Trying to prove $equiv for \result_value [58]: failed. + Trying to prove $equiv for \result_value [59]: failed. + Trying to prove $equiv for \result_value [60]: failed. + Trying to prove $equiv for \result_value [61]: failed. + Trying to prove $equiv for \result_value [62]: failed. + Trying to prove $equiv for \result_value [63]: failed. + Trying to prove $equiv for \result_value [64]: failed. + Trying to prove $equiv for \result_value [65]: failed. + Trying to prove $equiv for \result_value [66]: failed. + Trying to prove $equiv for \result_value [67]: failed. + Trying to prove $equiv for \result_value [68]: failed. + Trying to prove $equiv for \result_value [69]: failed. + Trying to prove $equiv for \result_value [70]: failed. + Trying to prove $equiv for \result_value [71]: failed. + Trying to prove $equiv for \result_value [72]: failed. + Trying to prove $equiv for \result_value [73]: failed. + Trying to prove $equiv for \result_value [74]: failed. + Trying to prove $equiv for \result_value [75]: failed. + Trying to prove $equiv for \result_value [76]: failed. + Trying to prove $equiv for \result_value [77]: failed. + Trying to prove $equiv for \result_value [78]: failed. + Trying to prove $equiv for \result_value [79]: failed. + Trying to prove $equiv for \result_value [80]: failed. + Trying to prove $equiv for \result_value [81]: failed. + Trying to prove $equiv for \result_value [82]: failed. + Trying to prove $equiv for \result_value [83]: failed. + Trying to prove $equiv for \result_value [84]: failed. + Trying to prove $equiv for \result_value [85]: failed. + Trying to prove $equiv for \result_value [86]: failed. + Trying to prove $equiv for \result_value [87]: failed. + Trying to prove $equiv for \result_value [88]: failed. + Trying to prove $equiv for \result_value [89]: failed. + Trying to prove $equiv for \result_value [90]: failed. + Trying to prove $equiv for \result_value [91]: failed. + Trying to prove $equiv for \result_value [92]: failed. + Trying to prove $equiv for \result_value [93]: failed. + Trying to prove $equiv for \result_value [94]: failed. + Trying to prove $equiv for \result_value [95]: failed. + Trying to prove $equiv for \result_value [96]: failed. + Trying to prove $equiv for \result_value [97]: failed. + Trying to prove $equiv for \result_value [98]: failed. + Trying to prove $equiv for \result_value [99]: failed. + Trying to prove $equiv for \result_value [100]: failed. + Trying to prove $equiv for \result_value [101]: failed. + Trying to prove $equiv for \result_value [102]: failed. + Trying to prove $equiv for \result_value [103]: failed. + Trying to prove $equiv for \result_value [104]: failed. + Trying to prove $equiv for \result_value [105]: failed. + Trying to prove $equiv for \result_value [106]: failed. + Trying to prove $equiv for \result_value [107]: failed. + Trying to prove $equiv for \result_value [108]: failed. + Trying to prove $equiv for \result_value [109]: failed. + Trying to prove $equiv for \result_value [110]: failed. + Trying to prove $equiv for \result_value [111]: failed. + Trying to prove $equiv for \result_value [112]: failed. + Trying to prove $equiv for \result_value [113]: failed. + Trying to prove $equiv for \result_value [114]: failed. + Trying to prove $equiv for \result_value [115]: failed. + Trying to prove $equiv for \result_value [116]: failed. + Trying to prove $equiv for \result_value [117]: failed. + Trying to prove $equiv for \result_value [118]: failed. + Trying to prove $equiv for \result_value [119]: failed. + Trying to prove $equiv for \result_value [120]: failed. + Trying to prove $equiv for \result_value [121]: failed. + Trying to prove $equiv for \result_value [122]: failed. + Trying to prove $equiv for \result_value [123]: failed. + Trying to prove $equiv for \result_value [124]: failed. + Trying to prove $equiv for \result_value [125]: failed. + Trying to prove $equiv for \result_value [126]: failed. + Trying to prove $equiv for \result_value [127]: failed. + Grouping SAT models for \solved_a: + Trying to prove $equiv for \solved_a [0]: failed. + Trying to prove $equiv for \solved_a [1]: failed. + Trying to prove $equiv for \solved_a [2]: failed. + Trying to prove $equiv for \solved_a [3]: failed. + Trying to prove $equiv for \solved_a [4]: failed. + Trying to prove $equiv for \solved_a [5]: failed. + Trying to prove $equiv for \solved_a [6]: failed. + Trying to prove $equiv for \solved_a [7]: failed. + Trying to prove $equiv for \solved_a [8]: failed. + Trying to prove $equiv for \solved_a [9]: failed. + Trying to prove $equiv for \solved_a [10]: failed. + Trying to prove $equiv for \solved_a [11]: failed. + Trying to prove $equiv for \solved_a [12]: failed. + Trying to prove $equiv for \solved_a [13]: failed. + Trying to prove $equiv for \solved_a [14]: failed. + Trying to prove $equiv for \solved_a [15]: failed. + Trying to prove $equiv for \solved_a [16]: failed. + Trying to prove $equiv for \solved_a [17]: failed. + Trying to prove $equiv for \solved_a [18]: failed. + Trying to prove $equiv for \solved_a [19]: failed. + Trying to prove $equiv for \solved_a [20]: failed. + Trying to prove $equiv for \solved_a [21]: failed. + Trying to prove $equiv for \solved_a [22]: failed. + Trying to prove $equiv for \solved_a [23]: failed. + Trying to prove $equiv for \solved_a [24]: failed. + Trying to prove $equiv for \solved_a [25]: failed. + Trying to prove $equiv for \solved_a [26]: failed. + Trying to prove $equiv for \solved_a [27]: failed. + Trying to prove $equiv for \solved_a [28]: failed. + Trying to prove $equiv for \solved_a [29]: failed. + Trying to prove $equiv for \solved_a [30]: failed. + Trying to prove $equiv for \solved_a [31]: failed. + Trying to prove $equiv for \solved_a [32]: failed. + Trying to prove $equiv for \solved_a [33]: failed. + Trying to prove $equiv for \solved_a [34]: failed. + Trying to prove $equiv for \solved_a [35]: failed. + Trying to prove $equiv for \solved_a [36]: failed. + Trying to prove $equiv for \solved_a [37]: failed. + Trying to prove $equiv for \solved_a [38]: failed. + Trying to prove $equiv for \solved_a [39]: failed. + Trying to prove $equiv for \solved_a [40]: failed. + Trying to prove $equiv for \solved_a [41]: failed. + Trying to prove $equiv for \solved_a [42]: failed. + Trying to prove $equiv for \solved_a [43]: failed. + Trying to prove $equiv for \solved_a [44]: failed. + Trying to prove $equiv for \solved_a [45]: failed. + Trying to prove $equiv for \solved_a [46]: failed. + Trying to prove $equiv for \solved_a [47]: failed. + Trying to prove $equiv for \solved_a [48]: failed. + Trying to prove $equiv for \solved_a [49]: failed. + Trying to prove $equiv for \solved_a [50]: failed. + Trying to prove $equiv for \solved_a [51]: failed. + Trying to prove $equiv for \solved_a [52]: failed. + Trying to prove $equiv for \solved_a [53]: failed. + Trying to prove $equiv for \solved_a [54]: failed. + Trying to prove $equiv for \solved_a [55]: failed. + Trying to prove $equiv for \solved_a [56]: failed. + Trying to prove $equiv for \solved_a [57]: failed. + Trying to prove $equiv for \solved_a [58]: failed. + Trying to prove $equiv for \solved_a [59]: failed. + Trying to prove $equiv for \solved_a [60]: failed. + Trying to prove $equiv for \solved_a [61]: failed. + Trying to prove $equiv for \solved_a [62]: failed. + Trying to prove $equiv for \solved_a [63]: failed. + Trying to prove $equiv for \solved_a [64]: failed. + Trying to prove $equiv for \solved_a [65]: failed. + Trying to prove $equiv for \solved_a [66]: failed. + Trying to prove $equiv for \solved_a [67]: failed. + Trying to prove $equiv for \solved_a [68]: failed. + Trying to prove $equiv for \solved_a [69]: failed. + Trying to prove $equiv for \solved_a [70]: failed. + Trying to prove $equiv for \solved_a [71]: failed. + Trying to prove $equiv for \solved_a [72]: failed. + Trying to prove $equiv for \solved_a [73]: failed. + Trying to prove $equiv for \solved_a [74]: failed. + Trying to prove $equiv for \solved_a [75]: failed. + Trying to prove $equiv for \solved_a [76]: failed. + Trying to prove $equiv for \solved_a [77]: failed. + Trying to prove $equiv for \solved_a [78]: failed. + Trying to prove $equiv for \solved_a [79]: failed. + Trying to prove $equiv for \solved_a [80]: failed. + Trying to prove $equiv for \solved_a [81]: failed. + Trying to prove $equiv for \solved_a [82]: failed. + Trying to prove $equiv for \solved_a [83]: failed. + Trying to prove $equiv for \solved_a [84]: failed. + Trying to prove $equiv for \solved_a [85]: failed. + Trying to prove $equiv for \solved_a [86]: failed. + Trying to prove $equiv for \solved_a [87]: failed. + Trying to prove $equiv for \solved_a [88]: failed. + Trying to prove $equiv for \solved_a [89]: failed. + Trying to prove $equiv for \solved_a [90]: failed. + Trying to prove $equiv for \solved_a [91]: failed. + Trying to prove $equiv for \solved_a [92]: failed. + Trying to prove $equiv for \solved_a [93]: failed. + Trying to prove $equiv for \solved_a [94]: failed. + Trying to prove $equiv for \solved_a [95]: failed. + Trying to prove $equiv for \solved_a [96]: failed. + Trying to prove $equiv for \solved_a [97]: failed. + Trying to prove $equiv for \solved_a [98]: failed. + Trying to prove $equiv for \solved_a [99]: failed. + Trying to prove $equiv for \solved_a [100]: failed. + Trying to prove $equiv for \solved_a [101]: failed. + Trying to prove $equiv for \solved_a [102]: failed. + Trying to prove $equiv for \solved_a [103]: failed. + Trying to prove $equiv for \solved_a [104]: failed. + Trying to prove $equiv for \solved_a [105]: failed. + Trying to prove $equiv for \solved_a [106]: failed. + Trying to prove $equiv for \solved_a [107]: failed. + Trying to prove $equiv for \solved_a [108]: failed. + Trying to prove $equiv for \solved_a [109]: failed. + Trying to prove $equiv for \solved_a [110]: failed. + Trying to prove $equiv for \solved_a [111]: failed. + Trying to prove $equiv for \solved_a [112]: failed. + Trying to prove $equiv for \solved_a [113]: failed. + Trying to prove $equiv for \solved_a [114]: failed. + Trying to prove $equiv for \solved_a [115]: failed. + Trying to prove $equiv for \solved_a [116]: failed. + Trying to prove $equiv for \solved_a [117]: failed. + Trying to prove $equiv for \solved_a [118]: failed. + Trying to prove $equiv for \solved_a [119]: failed. + Trying to prove $equiv for \solved_a [120]: failed. + Trying to prove $equiv for \solved_a [121]: failed. + Trying to prove $equiv for \solved_a [122]: failed. + Trying to prove $equiv for \solved_a [123]: failed. + Trying to prove $equiv for \solved_a [124]: failed. + Trying to prove $equiv for \solved_a [125]: failed. + Trying to prove $equiv for \solved_a [126]: failed. + Trying to prove $equiv for \solved_a [127]: failed. + Grouping SAT models for \solved_b: + Trying to prove $equiv for \solved_b [0]: failed. + Trying to prove $equiv for \solved_b [1]: failed. + Trying to prove $equiv for \solved_b [2]: failed. + Trying to prove $equiv for \solved_b [3]: failed. + Trying to prove $equiv for \solved_b [4]: failed. + Trying to prove $equiv for \solved_b [5]: failed. + Trying to prove $equiv for \solved_b [6]: failed. + Trying to prove $equiv for \solved_b [7]: failed. + Trying to prove $equiv for \solved_b [8]: failed. + Trying to prove $equiv for \solved_b [9]: failed. + Trying to prove $equiv for \solved_b [10]: failed. + Trying to prove $equiv for \solved_b [11]: failed. + Trying to prove $equiv for \solved_b [12]: failed. + Trying to prove $equiv for \solved_b [13]: failed. + Trying to prove $equiv for \solved_b [14]: failed. + Trying to prove $equiv for \solved_b [15]: failed. + Trying to prove $equiv for \solved_b [16]: failed. + Trying to prove $equiv for \solved_b [17]: failed. + Trying to prove $equiv for \solved_b [18]: failed. + Trying to prove $equiv for \solved_b [19]: failed. + Trying to prove $equiv for \solved_b [20]: failed. + Trying to prove $equiv for \solved_b [21]: failed. + Trying to prove $equiv for \solved_b [22]: failed. + Trying to prove $equiv for \solved_b [23]: failed. + Trying to prove $equiv for \solved_b [24]: failed. + Trying to prove $equiv for \solved_b [25]: failed. + Trying to prove $equiv for \solved_b [26]: failed. + Trying to prove $equiv for \solved_b [27]: failed. + Trying to prove $equiv for \solved_b [28]: failed. + Trying to prove $equiv for \solved_b [29]: failed. + Trying to prove $equiv for \solved_b [30]: failed. + Trying to prove $equiv for \solved_b [31]: failed. + Trying to prove $equiv for \solved_b [32]: failed. + Trying to prove $equiv for \solved_b [33]: failed. + Trying to prove $equiv for \solved_b [34]: failed. + Trying to prove $equiv for \solved_b [35]: failed. + Trying to prove $equiv for \solved_b [36]: failed. + Trying to prove $equiv for \solved_b [37]: failed. + Trying to prove $equiv for \solved_b [38]: failed. + Trying to prove $equiv for \solved_b [39]: failed. + Trying to prove $equiv for \solved_b [40]: failed. + Trying to prove $equiv for \solved_b [41]: failed. + Trying to prove $equiv for \solved_b [42]: failed. + Trying to prove $equiv for \solved_b [43]: failed. + Trying to prove $equiv for \solved_b [44]: failed. + Trying to prove $equiv for \solved_b [45]: failed. + Trying to prove $equiv for \solved_b [46]: failed. + Trying to prove $equiv for \solved_b [47]: failed. + Trying to prove $equiv for \solved_b [48]: failed. + Trying to prove $equiv for \solved_b [49]: failed. + Trying to prove $equiv for \solved_b [50]: failed. + Trying to prove $equiv for \solved_b [51]: failed. + Trying to prove $equiv for \solved_b [52]: failed. + Trying to prove $equiv for \solved_b [53]: failed. + Trying to prove $equiv for \solved_b [54]: failed. + Trying to prove $equiv for \solved_b [55]: failed. + Trying to prove $equiv for \solved_b [56]: failed. + Trying to prove $equiv for \solved_b [57]: failed. + Trying to prove $equiv for \solved_b [58]: failed. + Trying to prove $equiv for \solved_b [59]: failed. + Trying to prove $equiv for \solved_b [60]: failed. + Trying to prove $equiv for \solved_b [61]: failed. + Trying to prove $equiv for \solved_b [62]: failed. + Trying to prove $equiv for \solved_b [63]: failed. + Trying to prove $equiv for \solved_b [64]: failed. + Trying to prove $equiv for \solved_b [65]: failed. + Trying to prove $equiv for \solved_b [66]: failed. + Trying to prove $equiv for \solved_b [67]: failed. + Trying to prove $equiv for \solved_b [68]: failed. + Trying to prove $equiv for \solved_b [69]: failed. + Trying to prove $equiv for \solved_b [70]: failed. + Trying to prove $equiv for \solved_b [71]: failed. + Trying to prove $equiv for \solved_b [72]: failed. + Trying to prove $equiv for \solved_b [73]: failed. + Trying to prove $equiv for \solved_b [74]: failed. + Trying to prove $equiv for \solved_b [75]: failed. + Trying to prove $equiv for \solved_b [76]: failed. + Trying to prove $equiv for \solved_b [77]: failed. + Trying to prove $equiv for \solved_b [78]: failed. + Trying to prove $equiv for \solved_b [79]: failed. + Trying to prove $equiv for \solved_b [80]: failed. + Trying to prove $equiv for \solved_b [81]: failed. + Trying to prove $equiv for \solved_b [82]: failed. + Trying to prove $equiv for \solved_b [83]: failed. + Trying to prove $equiv for \solved_b [84]: failed. + Trying to prove $equiv for \solved_b [85]: failed. + Trying to prove $equiv for \solved_b [86]: failed. + Trying to prove $equiv for \solved_b [87]: failed. + Trying to prove $equiv for \solved_b [88]: failed. + Trying to prove $equiv for \solved_b [89]: failed. + Trying to prove $equiv for \solved_b [90]: failed. + Trying to prove $equiv for \solved_b [91]: failed. + Trying to prove $equiv for \solved_b [92]: failed. + Trying to prove $equiv for \solved_b [93]: failed. + Trying to prove $equiv for \solved_b [94]: failed. + Trying to prove $equiv for \solved_b [95]: failed. + Trying to prove $equiv for \solved_b [96]: failed. + Trying to prove $equiv for \solved_b [97]: failed. + Trying to prove $equiv for \solved_b [98]: failed. + Trying to prove $equiv for \solved_b [99]: failed. + Trying to prove $equiv for \solved_b [100]: failed. + Trying to prove $equiv for \solved_b [101]: failed. + Trying to prove $equiv for \solved_b [102]: failed. + Trying to prove $equiv for \solved_b [103]: failed. + Trying to prove $equiv for \solved_b [104]: failed. + Trying to prove $equiv for \solved_b [105]: failed. + Trying to prove $equiv for \solved_b [106]: failed. + Trying to prove $equiv for \solved_b [107]: failed. + Trying to prove $equiv for \solved_b [108]: failed. + Trying to prove $equiv for \solved_b [109]: failed. + Trying to prove $equiv for \solved_b [110]: failed. + Trying to prove $equiv for \solved_b [111]: failed. + Trying to prove $equiv for \solved_b [112]: failed. + Trying to prove $equiv for \solved_b [113]: failed. + Trying to prove $equiv for \solved_b [114]: failed. + Trying to prove $equiv for \solved_b [115]: failed. + Trying to prove $equiv for \solved_b [116]: failed. + Trying to prove $equiv for \solved_b [117]: failed. + Trying to prove $equiv for \solved_b [118]: failed. + Trying to prove $equiv for \solved_b [119]: failed. + Trying to prove $equiv for \solved_b [120]: failed. + Trying to prove $equiv for \solved_b [121]: failed. + Trying to prove $equiv for \solved_b [122]: failed. + Trying to prove $equiv for \solved_b [123]: failed. + Trying to prove $equiv for \solved_b [124]: failed. + Trying to prove $equiv for \solved_b [125]: failed. + Trying to prove $equiv for \solved_b [126]: failed. + Trying to prove $equiv for \solved_b [127]: failed. + Grouping SAT models for \write_address: + Trying to prove $equiv for \write_address [0]: failed. + Trying to prove $equiv for \write_address [1]: failed. + Trying to prove $equiv for \write_address [2]: failed. + Trying to prove $equiv for \write_address [3]: failed. + Trying to prove $equiv for \write_address [4]: failed. + Trying to prove $equiv for \write_address [5]: failed. + Trying to prove $equiv for \write_address [6]: failed. + Trying to prove $equiv for \write_address [7]: failed. + Trying to prove $equiv for \write_address [8]: failed. + Trying to prove $equiv for \write_address [9]: failed. + Trying to prove $equiv for \write_address [10]: failed. + Trying to prove $equiv for \write_address [11]: failed. + Trying to prove $equiv for \write_address [12]: failed. + Trying to prove $equiv for \write_address [13]: failed. + Trying to prove $equiv for \write_address [14]: failed. + Trying to prove $equiv for \write_address [15]: failed. + Trying to prove $equiv for \write_address [16]: failed. + Trying to prove $equiv for \write_address [17]: failed. + Trying to prove $equiv for \write_address [18]: failed. + Trying to prove $equiv for \write_address [19]: failed. + Trying to prove $equiv for \write_address [20]: failed. + Trying to prove $equiv for \write_address [21]: failed. + Trying to prove $equiv for \write_address [22]: failed. + Trying to prove $equiv for \write_address [23]: failed. + Trying to prove $equiv for \write_address [24]: failed. + Trying to prove $equiv for \write_address [25]: failed. + Trying to prove $equiv for \write_address [26]: failed. + Trying to prove $equiv for \write_address [27]: failed. + Trying to prove $equiv for \write_address [28]: failed. + Trying to prove $equiv for \write_address [29]: failed. + Trying to prove $equiv for \write_address [30]: failed. + Trying to prove $equiv for \write_address [31]: failed. + Grouping SAT models for \write_value: + Trying to prove $equiv for \write_value [0]: failed. + Trying to prove $equiv for \write_value [1]: failed. + Trying to prove $equiv for \write_value [2]: failed. + Trying to prove $equiv for \write_value [3]: failed. + Trying to prove $equiv for \write_value [4]: failed. + Trying to prove $equiv for \write_value [5]: failed. + Trying to prove $equiv for \write_value [6]: failed. + Trying to prove $equiv for \write_value [7]: failed. + Trying to prove $equiv for \write_value [8]: failed. + Trying to prove $equiv for \write_value [9]: failed. + Trying to prove $equiv for \write_value [10]: failed. + Trying to prove $equiv for \write_value [11]: failed. + Trying to prove $equiv for \write_value [12]: failed. + Trying to prove $equiv for \write_value [13]: failed. + Trying to prove $equiv for \write_value [14]: failed. + Trying to prove $equiv for \write_value [15]: failed. + Trying to prove $equiv for \write_value [16]: failed. + Trying to prove $equiv for \write_value [17]: failed. + Trying to prove $equiv for \write_value [18]: failed. + Trying to prove $equiv for \write_value [19]: failed. + Trying to prove $equiv for \write_value [20]: failed. + Trying to prove $equiv for \write_value [21]: failed. + Trying to prove $equiv for \write_value [22]: failed. + Trying to prove $equiv for \write_value [23]: failed. + Trying to prove $equiv for \write_value [24]: failed. + Trying to prove $equiv for \write_value [25]: failed. + Trying to prove $equiv for \write_value [26]: failed. + Trying to prove $equiv for \write_value [27]: failed. + Trying to prove $equiv for \write_value [28]: failed. + Trying to prove $equiv for \write_value [29]: failed. + Trying to prove $equiv for \write_value [30]: failed. + Trying to prove $equiv for \write_value [31]: failed. + Trying to prove $equiv for \write_value [32]: failed. + Trying to prove $equiv for \write_value [33]: failed. + Trying to prove $equiv for \write_value [34]: failed. + Trying to prove $equiv for \write_value [35]: failed. + Trying to prove $equiv for \write_value [36]: failed. + Trying to prove $equiv for \write_value [37]: failed. + Trying to prove $equiv for \write_value [38]: failed. + Trying to prove $equiv for \write_value [39]: failed. + Trying to prove $equiv for \write_value [40]: failed. + Trying to prove $equiv for \write_value [41]: failed. + Trying to prove $equiv for \write_value [42]: failed. + Trying to prove $equiv for \write_value [43]: failed. + Trying to prove $equiv for \write_value [44]: failed. + Trying to prove $equiv for \write_value [45]: failed. + Trying to prove $equiv for \write_value [46]: failed. + Trying to prove $equiv for \write_value [47]: failed. + Trying to prove $equiv for \write_value [48]: failed. + Trying to prove $equiv for \write_value [49]: failed. + Trying to prove $equiv for \write_value [50]: failed. + Trying to prove $equiv for \write_value [51]: failed. + Trying to prove $equiv for \write_value [52]: failed. + Trying to prove $equiv for \write_value [53]: failed. + Trying to prove $equiv for \write_value [54]: failed. + Trying to prove $equiv for \write_value [55]: failed. + Trying to prove $equiv for \write_value [56]: failed. + Trying to prove $equiv for \write_value [57]: failed. + Trying to prove $equiv for \write_value [58]: failed. + Trying to prove $equiv for \write_value [59]: failed. + Trying to prove $equiv for \write_value [60]: failed. + Trying to prove $equiv for \write_value [61]: failed. + Trying to prove $equiv for \write_value [62]: failed. + Trying to prove $equiv for \write_value [63]: failed. + Trying to prove $equiv for \write_value [64]: failed. + Trying to prove $equiv for \write_value [65]: failed. + Trying to prove $equiv for \write_value [66]: failed. + Trying to prove $equiv for \write_value [67]: failed. + Trying to prove $equiv for \write_value [68]: failed. + Trying to prove $equiv for \write_value [69]: failed. + Trying to prove $equiv for \write_value [70]: failed. + Trying to prove $equiv for \write_value [71]: failed. + Trying to prove $equiv for \write_value [72]: failed. + Trying to prove $equiv for \write_value [73]: failed. + Trying to prove $equiv for \write_value [74]: failed. + Trying to prove $equiv for \write_value [75]: failed. + Trying to prove $equiv for \write_value [76]: failed. + Trying to prove $equiv for \write_value [77]: failed. + Trying to prove $equiv for \write_value [78]: failed. + Trying to prove $equiv for \write_value [79]: failed. + Trying to prove $equiv for \write_value [80]: failed. + Trying to prove $equiv for \write_value [81]: failed. + Trying to prove $equiv for \write_value [82]: failed. + Trying to prove $equiv for \write_value [83]: failed. + Trying to prove $equiv for \write_value [84]: failed. + Trying to prove $equiv for \write_value [85]: failed. + Trying to prove $equiv for \write_value [86]: failed. + Trying to prove $equiv for \write_value [87]: failed. + Trying to prove $equiv for \write_value [88]: failed. + Trying to prove $equiv for \write_value [89]: failed. + Trying to prove $equiv for \write_value [90]: failed. + Trying to prove $equiv for \write_value [91]: failed. + Trying to prove $equiv for \write_value [92]: failed. + Trying to prove $equiv for \write_value [93]: failed. + Trying to prove $equiv for \write_value [94]: failed. + Trying to prove $equiv for \write_value [95]: failed. + Trying to prove $equiv for \write_value [96]: failed. + Trying to prove $equiv for \write_value [97]: failed. + Trying to prove $equiv for \write_value [98]: failed. + Trying to prove $equiv for \write_value [99]: failed. + Trying to prove $equiv for \write_value [100]: failed. + Trying to prove $equiv for \write_value [101]: failed. + Trying to prove $equiv for \write_value [102]: failed. + Trying to prove $equiv for \write_value [103]: failed. + Trying to prove $equiv for \write_value [104]: failed. + Trying to prove $equiv for \write_value [105]: failed. + Trying to prove $equiv for \write_value [106]: failed. + Trying to prove $equiv for \write_value [107]: failed. + Trying to prove $equiv for \write_value [108]: failed. + Trying to prove $equiv for \write_value [109]: failed. + Trying to prove $equiv for \write_value [110]: failed. + Trying to prove $equiv for \write_value [111]: failed. + Trying to prove $equiv for \write_value [112]: failed. + Trying to prove $equiv for \write_value [113]: failed. + Trying to prove $equiv for \write_value [114]: failed. + Trying to prove $equiv for \write_value [115]: failed. + Trying to prove $equiv for \write_value [116]: failed. + Trying to prove $equiv for \write_value [117]: failed. + Trying to prove $equiv for \write_value [118]: failed. + Trying to prove $equiv for \write_value [119]: failed. + Trying to prove $equiv for \write_value [120]: failed. + Trying to prove $equiv for \write_value [121]: failed. + Trying to prove $equiv for \write_value [122]: failed. + Trying to prove $equiv for \write_value [123]: failed. + Trying to prove $equiv for \write_value [124]: failed. + Trying to prove $equiv for \write_value [125]: failed. + Trying to prove $equiv for \write_value [126]: failed. + Trying to prove $equiv for \write_value [127]: failed. + Trying to prove $equiv for \_unused_adapter_fault: failed. +Proved 0 previously unproven $equiv cells. + +16. Executing EQUIV_INDUCT pass. +No selected unproven $equiv cells found in gf128_mul_bitstream. +Found 5039 unproven $equiv cells in module equiv: +Warning: No SAT model available for cell adapter_gold (lsc1_stream_adapter). +Warning: No SAT model available for cell field_encoder_gold (lsc1_field_encoder). +Warning: No SAT model available for cell receiver_gold (lsc1_packet_rx). +Warning: No SAT model available for cell transmitter_gold (lsc1_packet_tx). diff --git a/results/b2-capability-contract-20260728/equivalence_retry.status b/results/b2-capability-contract-20260728/equivalence_retry.status new file mode 100644 index 0000000..99875bd --- /dev/null +++ b/results/b2-capability-contract-20260728/equivalence_retry.status @@ -0,0 +1,2 @@ +exit=143 +duration_ms=585606 diff --git a/results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v b/results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v new file mode 100644 index 0000000..5ac0388 --- /dev/null +++ b/results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v @@ -0,0 +1,7201 @@ +/* Generated by Yosys 0.33 (git sha1 2584903a060) */ + +module lsc1_packet_frontend(clk, rst_n, abort, rx_data, rx_valid, rx_ready, tx_data, tx_valid, tx_ready, busy, fault, done_pulse); + wire [31:0] _0000_; + wire [31:0] _0001_; + wire [31:0] _0002_; + wire [31:0] _0003_; + wire [31:0] _0004_; + wire [31:0] _0005_; + wire [175:0] _0006_; + wire [31:0] _0007_; + wire [127:0] _0008_; + wire [127:0] _0009_; + wire [31:0] _0010_; + wire [127:0] _0011_; + wire [31:0] _0012_; + wire [31:0] _0013_; + wire [31:0] _0014_; + wire [31:0] _0015_; + wire [127:0] _0016_; + wire [127:0] _0017_; + wire [31:0] _0018_; + wire [127:0] _0019_; + wire [31:0] _0020_; + wire [31:0] _0021_; + wire [31:0] _0022_; + wire [31:0] _0023_; + wire [127:0] _0024_; + wire [127:0] _0025_; + wire [31:0] _0026_; + wire [127:0] _0027_; + wire [31:0] _0028_; + wire [31:0] _0029_; + wire [31:0] _0030_; + wire [31:0] _0031_; + wire [31:0] _0032_; + wire [127:0] _0033_; + wire [31:0] _0034_; + wire [31:0] _0035_; + wire [31:0] _0036_; + wire [31:0] _0037_; + wire [127:0] _0038_; + wire [127:0] _0039_; + wire [31:0] _0040_; + wire [127:0] _0041_; + wire [31:0] _0042_; + wire [31:0] _0043_; + wire [31:0] _0044_; + wire [31:0] _0045_; + wire [271:0] _0046_; + wire [31:0] _0047_; + wire [127:0] _0048_; + wire [127:0] _0049_; + wire [31:0] _0050_; + wire [127:0] _0051_; + wire [31:0] _0052_; + wire [31:0] _0053_; + wire [31:0] _0054_; + wire [31:0] _0055_; + wire [127:0] _0056_; + wire [127:0] _0057_; + wire [31:0] _0058_; + wire [127:0] _0059_; + wire [31:0] _0060_; + wire [31:0] _0061_; + wire [31:0] _0062_; + wire [31:0] _0063_; + wire [175:0] _0064_; + wire [31:0] _0065_; + wire [127:0] _0066_; + wire [127:0] _0067_; + wire [31:0] _0068_; + wire [31:0] _0069_; + wire [127:0] _0070_; + wire [31:0] _0071_; + wire [31:0] _0072_; + wire [31:0] _0073_; + wire [31:0] _0074_; + wire [127:0] _0075_; + wire [127:0] _0076_; + wire [31:0] _0077_; + wire [31:0] _0078_; + wire [127:0] _0079_; + wire [31:0] _0080_; + wire [31:0] _0081_; + wire [31:0] _0082_; + wire [31:0] _0083_; + wire [127:0] _0084_; + wire [127:0] _0085_; + wire [31:0] _0086_; + wire [31:0] _0087_; + wire [127:0] _0088_; + wire [31:0] _0089_; + wire [31:0] _0090_; + wire [31:0] _0091_; + wire [31:0] _0092_; + wire [127:0] _0093_; + wire [127:0] _0094_; + wire [31:0] _0095_; + wire [31:0] _0096_; + wire [127:0] _0097_; + wire [31:0] _0098_; + wire [31:0] _0099_; + wire [31:0] _0100_; + wire [31:0] _0101_; + wire [127:0] _0102_; + wire [127:0] _0103_; + wire [31:0] _0104_; + wire [31:0] _0105_; + wire [127:0] _0106_; + wire [31:0] _0107_; + wire [31:0] _0108_; + wire [31:0] _0109_; + wire [31:0] _0110_; + wire [127:0] _0111_; + wire [127:0] _0112_; + wire [31:0] _0113_; + wire [31:0] _0114_; + wire [127:0] _0115_; + wire [31:0] _0116_; + wire [31:0] _0117_; + wire [31:0] _0118_; + wire [31:0] _0119_; + wire [271:0] _0120_; + wire [31:0] _0121_; + wire [127:0] _0122_; + wire [127:0] _0123_; + wire [31:0] _0124_; + wire [31:0] _0125_; + wire [127:0] _0126_; + wire [31:0] _0127_; + wire [31:0] _0128_; + wire [31:0] _0129_; + wire [31:0] _0130_; + wire [127:0] _0131_; + wire [127:0] _0132_; + wire [31:0] _0133_; + wire [31:0] _0134_; + wire [127:0] _0135_; + wire [31:0] _0136_; + wire [31:0] _0137_; + wire [31:0] _0138_; + wire [31:0] _0139_; + wire [127:0] _0140_; + wire [127:0] _0141_; + wire [31:0] _0142_; + wire [31:0] _0143_; + wire [127:0] _0144_; + wire [31:0] _0145_; + wire [31:0] _0146_; + wire [31:0] _0147_; + wire [31:0] _0148_; + wire [127:0] _0149_; + wire [127:0] _0150_; + wire [31:0] _0151_; + wire [31:0] _0152_; + wire [127:0] _0153_; + wire [31:0] _0154_; + wire [31:0] _0155_; + wire [31:0] _0156_; + wire [31:0] _0157_; + wire [127:0] _0158_; + wire [127:0] _0159_; + wire [31:0] _0160_; + wire [31:0] _0161_; + wire [127:0] _0162_; + wire [31:0] _0163_; + wire [31:0] _0164_; + wire [31:0] _0165_; + wire _0166_; + wire [7:0] _0167_; + wire [7:0] _0168_; + wire _0169_; + wire [31:0] _0170_; + wire [31:0] _0171_; + wire [31:0] _0172_; + wire [31:0] _0173_; + wire [7:0] _0174_; + wire [127:0] _0175_; + wire [127:0] _0176_; + wire [127:0] _0177_; + wire [127:0] _0178_; + wire [31:0] _0179_; + wire [127:0] _0180_; + wire [31:0] _0181_; + wire [31:0] _0182_; + wire _0183_; + wire [7:0] _0184_; + wire [7:0] _0185_; + wire _0186_; + wire [31:0] _0187_; + wire [31:0] _0188_; + wire [31:0] _0189_; + wire [31:0] _0190_; + wire [7:0] _0191_; + wire [7:0] _0192_; + wire [7:0] _0193_; + wire [127:0] _0194_; + wire [127:0] _0195_; + wire [127:0] _0196_; + wire [127:0] _0197_; + wire [127:0] _0198_; + wire [31:0] _0199_; + wire [127:0] _0200_; + wire [31:0] _0201_; + wire [31:0] _0202_; + wire _0203_; + wire [7:0] _0204_; + wire [7:0] _0205_; + wire _0206_; + wire [31:0] _0207_; + wire [127:0] _0208_; + wire [31:0] _0209_; + wire [7:0] _0210_; + wire [7:0] _0211_; + wire [7:0] _0212_; + wire [207:0] _0213_; + wire [31:0] _0214_; + wire [127:0] _0215_; + wire [127:0] _0216_; + wire [127:0] _0217_; + wire [127:0] _0218_; + wire [127:0] _0219_; + wire [31:0] _0220_; + wire [127:0] _0221_; + wire [31:0] _0222_; + wire [31:0] _0223_; + wire _0224_; + wire [7:0] _0225_; + wire [7:0] _0226_; + wire _0227_; + wire [31:0] _0228_; + wire [127:0] _0229_; + wire [31:0] _0230_; + wire [7:0] _0231_; + wire [7:0] _0232_; + wire [7:0] _0233_; + wire [175:0] _0234_; + wire [127:0] _0235_; + wire [127:0] _0236_; + wire [127:0] _0237_; + wire [127:0] _0238_; + wire [127:0] _0239_; + wire [31:0] _0240_; + wire [127:0] _0241_; + wire [31:0] _0242_; + wire [31:0] _0243_; + wire _0244_; + wire [7:0] _0245_; + wire [7:0] _0246_; + wire _0247_; + wire [31:0] _0248_; + wire [31:0] _0249_; + wire [31:0] _0250_; + wire [127:0] _0251_; + wire [127:0] _0252_; + wire [31:0] _0253_; + wire [127:0] _0254_; + wire [31:0] _0255_; + wire [31:0] _0256_; + wire [31:0] _0257_; + wire _0258_; + wire [7:0] _0259_; + wire [7:0] _0260_; + wire _0261_; + wire [31:0] _0262_; + wire [31:0] _0263_; + wire [31:0] _0264_; + wire [127:0] _0265_; + wire [31:0] _0266_; + wire [31:0] _0267_; + wire [31:0] _0268_; + wire _0269_; + wire [7:0] _0270_; + wire [7:0] _0271_; + wire _0272_; + wire [31:0] _0273_; + wire [31:0] _0274_; + wire [31:0] _0275_; + wire [127:0] _0276_; + wire [31:0] _0277_; + wire [31:0] _0278_; + wire [31:0] _0279_; + wire _0280_; + wire [7:0] _0281_; + wire [7:0] _0282_; + wire _0283_; + wire [31:0] _0284_; + wire [31:0] _0285_; + wire [127:0] _0286_; + wire [31:0] _0287_; + wire [31:0] _0288_; + wire [31:0] _0289_; + wire _0290_; + wire [7:0] _0291_; + wire [7:0] _0292_; + wire _0293_; + wire [31:0] _0294_; + wire [31:0] _0295_; + wire [127:0] _0296_; + wire [31:0] _0297_; + wire [31:0] _0298_; + wire [31:0] _0299_; + wire _0300_; + wire [7:0] _0301_; + wire [7:0] _0302_; + wire _0303_; + wire [31:0] _0304_; + wire [31:0] _0305_; + wire [127:0] _0306_; + wire [31:0] _0307_; + wire [31:0] _0308_; + wire [31:0] _0309_; + wire _0310_; + wire [7:0] _0311_; + wire [7:0] _0312_; + wire _0313_; + wire [31:0] _0314_; + wire [271:0] _0315_; + wire [31:0] _0316_; + wire [127:0] _0317_; + wire [31:0] _0318_; + wire _0319_; + wire [7:0] _0320_; + wire _0321_; + wire [31:0] _0322_; + wire [31:0] _0323_; + wire [127:0] _0324_; + wire [31:0] _0325_; + wire [31:0] _0326_; + wire [31:0] _0327_; + wire [31:0] _0328_; + wire [31:0] _0329_; + wire [127:0] _0330_; + wire [31:0] _0331_; + wire _0332_; + wire [7:0] _0333_; + wire _0334_; + wire [31:0] _0335_; + wire [31:0] _0336_; + wire [31:0] _0337_; + wire [127:0] _0338_; + wire [31:0] _0339_; + wire _0340_; + wire [7:0] _0341_; + wire _0342_; + wire [31:0] _0343_; + wire [31:0] _0344_; + wire [127:0] _0345_; + wire [31:0] _0346_; + wire _0347_; + wire [7:0] _0348_; + wire _0349_; + wire [31:0] _0350_; + wire [31:0] _0351_; + wire [127:0] _0352_; + wire _0353_; + wire [7:0] _0354_; + wire _0355_; + wire [31:0] _0356_; + wire [31:0] _0357_; + wire [127:0] _0358_; + wire _0359_; + wire [7:0] _0360_; + wire _0361_; + wire [31:0] _0362_; + wire [31:0] _0363_; + wire [127:0] _0364_; + wire _0365_; + wire [7:0] _0366_; + wire _0367_; + wire _0368_; + wire [7:0] _0369_; + wire _0370_; + wire _0371_; + wire [7:0] _0372_; + wire _0373_; + wire _0374_; + wire [7:0] _0375_; + wire _0376_; + wire _0377_; + wire [7:0] _0378_; + wire _0379_; + wire [31:0] _0380_; + wire [31:0] _0381_; + wire [31:0] _0382_; + wire [31:0] _0383_; + wire [31:0] _0384_; + wire [127:0] _0385_; + wire _0386_; + wire [7:0] _0387_; + wire _0388_; + wire [7:0] _0389_; + wire _0390_; + wire [7:0] _0391_; + wire _0392_; + wire [7:0] _0393_; + wire _0394_; + wire [7:0] _0395_; + wire _0396_; + wire [7:0] _0397_; + wire _0398_; + wire [7:0] _0399_; + wire _0400_; + wire [7:0] _0401_; + wire _0402_; + wire [7:0] _0403_; + wire _0404_; + wire [31:0] _0405_; + wire [31:0] _0406_; + wire [31:0] _0407_; + wire [31:0] _0408_; + wire [31:0] _0409_; + wire [127:0] _0410_; + wire [31:0] _0411_; + wire [31:0] _0412_; + wire [31:0] _0413_; + wire [271:0] _0414_; + wire [63:0] _0415_; + wire [175:0] _0416_; + wire [31:0] _0417_; + wire [31:0] _0418_; + wire [31:0] _0419_; + wire [31:0] _0420_; + wire [31:0] _0421_; + wire [31:0] _0422_; + wire [31:0] _0423_; + wire [127:0] _0424_; + wire [31:0] _0425_; + wire [31:0] _0426_; + wire [31:0] _0427_; + wire [31:0] _0428_; + wire [31:0] _0429_; + wire [31:0] _0430_; + wire [31:0] _0431_; + wire [127:0] _0432_; + wire [31:0] _0433_; + wire [31:0] _0434_; + wire [31:0] _0435_; + wire [31:0] _0436_; + wire [31:0] _0437_; + wire [31:0] _0438_; + wire [271:0] _0439_; + wire [31:0] _0440_; + wire [31:0] _0441_; + wire [127:0] _0442_; + wire [31:0] _0443_; + wire [31:0] _0444_; + wire [31:0] _0445_; + wire [31:0] _0446_; + wire [31:0] _0447_; + wire [31:0] _0448_; + wire [127:0] _0449_; + wire [127:0] _0450_; + wire [31:0] _0451_; + wire [127:0] _0452_; + wire [15:0] _0453_; + wire [31:0] _0454_; + wire [31:0] _0455_; + wire [31:0] _0456_; + wire [31:0] _0457_; + wire [31:0] _0458_; + wire [31:0] _0459_; + wire _0460_; + wire _0461_; + wire _0462_; + wire _0463_; + wire _0464_; + wire _0465_; + wire _0466_; + wire _0467_; + wire _0468_; + wire _0469_; + wire _0470_; + wire _0471_; + wire _0472_; + wire _0473_; + wire _0474_; + wire _0475_; + wire _0476_; + wire _0477_; + wire _0478_; + wire _0479_; + wire _0480_; + wire _0481_; + wire _0482_; + wire _0483_; + wire _0484_; + wire _0485_; + wire _0486_; + wire _0487_; + wire _0488_; + wire _0489_; + wire _0490_; + wire _0491_; + wire _0492_; + wire _0493_; + wire _0494_; + wire _0495_; + wire _0496_; + wire _0497_; + wire _0498_; + wire _0499_; + wire _0500_; + wire _0501_; + wire _0502_; + wire _0503_; + wire _0504_; + wire _0505_; + wire _0506_; + wire _0507_; + wire _0508_; + wire _0509_; + wire _0510_; + wire _0511_; + wire _0512_; + wire _0513_; + wire _0514_; + wire _0515_; + wire _0516_; + wire _0517_; + wire _0518_; + wire _0519_; + wire _0520_; + wire _0521_; + wire _0522_; + wire _0523_; + wire _0524_; + wire _0525_; + wire _0526_; + wire _0527_; + wire _0528_; + wire _0529_; + wire _0530_; + wire _0531_; + wire _0532_; + wire _0533_; + wire _0534_; + wire _0535_; + wire _0536_; + wire _0537_; + wire _0538_; + wire _0539_; + wire _0540_; + wire _0541_; + wire _0542_; + wire _0543_; + wire _0544_; + wire _0545_; + wire _0546_; + wire _0547_; + wire _0548_; + wire _0549_; + wire _0550_; + wire _0551_; + wire _0552_; + wire _0553_; + wire _0554_; + wire _0555_; + wire _0556_; + wire _0557_; + wire _0558_; + wire _0559_; + wire _0560_; + wire _0561_; + wire _0562_; + wire _0563_; + wire _0564_; + wire _0565_; + wire _0566_; + wire _0567_; + wire _0568_; + wire _0569_; + wire _0570_; + wire _0571_; + wire _0572_; + wire _0573_; + wire _0574_; + wire _0575_; + wire _0576_; + wire _0577_; + wire _0578_; + wire _0579_; + wire _0580_; + wire _0581_; + wire _0582_; + wire _0583_; + wire _0584_; + wire _0585_; + wire _0586_; + wire _0587_; + wire _0588_; + wire _0589_; + wire _0590_; + wire _0591_; + wire _0592_; + wire _0593_; + wire _0594_; + wire _0595_; + wire _0596_; + wire _0597_; + wire _0598_; + wire _0599_; + wire _0600_; + wire _0601_; + wire _0602_; + wire _0603_; + wire _0604_; + wire _0605_; + wire _0606_; + wire _0607_; + wire _0608_; + wire _0609_; + wire _0610_; + wire _0611_; + wire _0612_; + wire _0613_; + wire _0614_; + wire _0615_; + wire _0616_; + wire _0617_; + wire _0618_; + wire _0619_; + wire _0620_; + wire _0621_; + wire _0622_; + wire _0623_; + wire _0624_; + wire _0625_; + wire _0626_; + wire _0627_; + wire _0628_; + wire _0629_; + wire _0630_; + wire _0631_; + wire _0632_; + wire _0633_; + wire _0634_; + wire _0635_; + wire _0636_; + wire _0637_; + wire _0638_; + wire _0639_; + wire _0640_; + wire _0641_; + wire _0642_; + wire _0643_; + wire _0644_; + wire _0645_; + wire _0646_; + wire _0647_; + wire _0648_; + wire _0649_; + wire _0650_; + wire _0651_; + wire _0652_; + wire _0653_; + wire _0654_; + wire _0655_; + wire _0656_; + wire _0657_; + wire _0658_; + wire _0659_; + wire _0660_; + wire _0661_; + wire _0662_; + wire _0663_; + wire _0664_; + wire _0665_; + wire _0666_; + wire _0667_; + wire _0668_; + wire _0669_; + wire _0670_; + wire _0671_; + wire _0672_; + wire _0673_; + wire _0674_; + wire _0675_; + wire _0676_; + wire _0677_; + wire _0678_; + wire _0679_; + wire _0680_; + wire _0681_; + wire _0682_; + wire _0683_; + wire _0684_; + wire _0685_; + wire _0686_; + wire _0687_; + wire _0688_; + wire _0689_; + wire _0690_; + wire _0691_; + wire _0692_; + wire _0693_; + wire _0694_; + wire _0695_; + wire _0696_; + wire _0697_; + wire _0698_; + wire _0699_; + wire _0700_; + wire _0701_; + wire _0702_; + wire _0703_; + wire _0704_; + wire _0705_; + wire _0706_; + wire _0707_; + wire _0708_; + wire _0709_; + wire _0710_; + wire _0711_; + wire _0712_; + wire _0713_; + wire _0714_; + wire _0715_; + wire _0716_; + wire _0717_; + wire _0718_; + wire _0719_; + wire _0720_; + wire _0721_; + wire _0722_; + wire _0723_; + wire _0724_; + wire _0725_; + wire _0726_; + wire _0727_; + wire _0728_; + wire _0729_; + wire _0730_; + wire _0731_; + wire _0732_; + wire _0733_; + wire _0734_; + wire _0735_; + wire _0736_; + wire _0737_; + wire _0738_; + wire _0739_; + wire _0740_; + wire _0741_; + wire _0742_; + wire _0743_; + wire _0744_; + wire _0745_; + wire _0746_; + wire _0747_; + wire _0748_; + wire _0749_; + wire _0750_; + wire _0751_; + wire _0752_; + wire _0753_; + wire _0754_; + wire _0755_; + wire _0756_; + wire _0757_; + wire _0758_; + wire _0759_; + wire _0760_; + wire _0761_; + wire _0762_; + wire _0763_; + wire _0764_; + wire _0765_; + wire _0766_; + wire _0767_; + wire _0768_; + wire _0769_; + wire _0770_; + wire _0771_; + wire _0772_; + wire _0773_; + wire _0774_; + wire _0775_; + wire _0776_; + wire _0777_; + wire _0778_; + wire _0779_; + wire _0780_; + wire _0781_; + wire _0782_; + wire _0783_; + wire _0784_; + wire _0785_; + wire _0786_; + wire _0787_; + wire _0788_; + wire _0789_; + wire _0790_; + wire _0791_; + wire _0792_; + wire _0793_; + wire _0794_; + wire _0795_; + wire _0796_; + wire _0797_; + wire _0798_; + wire _0799_; + wire _0800_; + wire _0801_; + wire _0802_; + wire _0803_; + wire _0804_; + wire _0805_; + wire _0806_; + wire _0807_; + wire _0808_; + wire _0809_; + wire _0810_; + wire _0811_; + wire _0812_; + wire _0813_; + wire _0814_; + wire _0815_; + wire _0816_; + wire _0817_; + wire _0818_; + wire _0819_; + wire _0820_; + wire _0821_; + wire _0822_; + wire _0823_; + wire _0824_; + wire _0825_; + wire _0826_; + wire _0827_; + wire _0828_; + wire _0829_; + wire _0830_; + wire _0831_; + wire _0832_; + wire _0833_; + wire _0834_; + wire _0835_; + wire _0836_; + wire _0837_; + wire _0838_; + wire _0839_; + wire _0840_; + wire _0841_; + wire _0842_; + wire _0843_; + wire _0844_; + wire _0845_; + wire _0846_; + wire _0847_; + wire _0848_; + wire _0849_; + wire _0850_; + wire _0851_; + wire _0852_; + wire _0853_; + wire _0854_; + wire _0855_; + wire _0856_; + wire _0857_; + wire _0858_; + wire _0859_; + wire _0860_; + wire _0861_; + wire _0862_; + wire _0863_; + wire _0864_; + wire _0865_; + wire _0866_; + wire _0867_; + wire _0868_; + wire _0869_; + wire _0870_; + wire _0871_; + wire _0872_; + wire _0873_; + wire _0874_; + wire _0875_; + wire _0876_; + wire _0877_; + wire _0878_; + wire _0879_; + wire _0880_; + wire _0881_; + wire _0882_; + wire _0883_; + wire _0884_; + wire _0885_; + wire _0886_; + wire _0887_; + wire _0888_; + wire _0889_; + wire _0890_; + wire _0891_; + wire _0892_; + wire _0893_; + wire _0894_; + wire _0895_; + wire _0896_; + wire _0897_; + wire _0898_; + wire _0899_; + wire _0900_; + wire [7:0] _0901_; + wire _0902_; + wire [127:0] _0903_; + wire [7:0] _0904_; + wire _0905_; + wire [127:0] _0906_; + wire [7:0] _0907_; + wire [127:0] _0908_; + wire [7:0] _0909_; + wire [7:0] _0910_; + wire [31:0] _0911_; + wire [4:0] _0912_; + wire [5:0] _0913_; + wire [127:0] _0914_; + wire _0915_; + wire _0916_; + wire _0917_; + wire _0918_; + wire _0919_; + wire _0920_; + wire _0921_; + wire _0922_; + wire _0923_; + wire _0924_; + wire _0925_; + wire _0926_; + wire _0927_; + wire _0928_; + wire _0929_; + wire _0930_; + wire _0931_; + wire _0932_; + wire _0933_; + wire _0934_; + wire [32:0] _0935_; + wire [127:0] _0936_; + wire [127:0] _0937_; + wire _0938_; + wire _0939_; + wire _0940_; + wire _0941_; + wire _0942_; + wire _0943_; + wire _0944_; + wire _0945_; + wire _0946_; + wire [4:0] _0947_; + wire [4:0] _0948_; + wire [4:0] _0949_; + wire [4:0] _0950_; + wire [4:0] _0951_; + wire [4:0] _0952_; + wire [4:0] _0953_; + wire [4:0] _0954_; + wire [5:0] _0955_; + wire [5:0] _0956_; + wire [5:0] _0957_; + wire [5:0] _0958_; + wire [5:0] _0959_; + wire _0960_; + wire _0961_; + wire _0962_; + wire _0963_; + wire [2:0] _0964_; + wire [2:0] _0965_; + wire [2:0] _0966_; + wire [2:0] _0967_; + wire [2:0] _0968_; + wire [2:0] _0969_; + wire [2:0] _0970_; + wire [2:0] _0971_; + wire [2:0] _0972_; + wire [2:0] _0973_; + wire _0974_; + wire [127:0] _0975_; + wire [127:0] _0976_; + wire [7:0] _0977_; + wire [7:0] _0978_; + wire [7:0] _0979_; + wire [7:0] _0980_; + wire [31:0] _0981_; + wire _0982_; + wire [7:0] _0983_; + wire [7:0] _0984_; + wire _0985_; + wire [3:0] _0986_; + wire _0987_; + wire _0988_; + wire _0989_; + wire _0990_; + wire _0991_; + wire _0992_; + wire _0993_; + wire _0994_; + wire _0995_; + wire _0996_; + wire _0997_; + wire _0998_; + wire _0999_; + wire [6:0] _1000_; + wire [6:0] _1001_; + wire [6:0] _1002_; + wire _1003_; + wire [6:0] _1004_; + wire _1005_; + wire _1006_; + wire _1007_; + wire _1008_; + wire _1009_; + wire _1010_; + wire _1011_; + wire [3:0] _1012_; + wire [3:0] _1013_; + wire [3:0] _1014_; + wire [3:0] _1015_; + wire [3:0] _1016_; + wire [3:0] _1017_; + wire [3:0] _1018_; + wire [3:0] _1019_; + wire _1020_; + wire [3:0] _1021_; + wire [3:0] _1022_; + wire _1023_; + wire _1024_; + wire _1025_; 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_1078_; + wire [127:0] _1079_; + wire [127:0] _1080_; + wire [127:0] _1081_; + wire _1082_; + wire _1083_; + wire _1084_; + wire _1085_; + wire _1086_; + wire [4:0] _1087_; + wire [127:0] _1088_; + wire [127:0] _1089_; + wire [127:0] _1090_; + wire [7:0] _1091_; + wire _1092_; + wire [127:0] _1093_; + wire [7:0] _1094_; + wire _1095_; + wire [127:0] _1096_; + wire [7:0] _1097_; + wire [127:0] _1098_; + wire [31:0] _1099_; + wire [4:0] _1100_; + wire [5:0] _1101_; + wire [127:0] _1102_; + wire _1103_; + wire _1104_; + wire _1105_; + wire _1106_; + wire _1107_; + wire _1108_; + wire _1109_; + wire _1110_; + wire [32:0] _1111_; + wire [127:0] _1112_; + wire [127:0] _1113_; + wire _1114_; + wire _1115_; + wire _1116_; + wire _1117_; + wire _1118_; + wire _1119_; + wire _1120_; + wire [4:0] _1121_; + wire [4:0] _1122_; + wire [4:0] _1123_; + wire [4:0] _1124_; + wire [4:0] _1125_; + wire [4:0] _1126_; + wire [4:0] _1127_; + wire [4:0] _1128_; + wire [5:0] _1129_; + wire [5:0] _1130_; + wire [5:0] _1131_; + wire [5:0] _1132_; + wire [5:0] _1133_; + wire _1134_; + wire _1135_; + wire _1136_; + wire _1137_; + wire [2:0] _1138_; + wire [2:0] _1139_; + wire [2:0] _1140_; + wire [2:0] _1141_; + wire [2:0] _1142_; + wire [2:0] _1143_; + wire [2:0] _1144_; + wire [2:0] _1145_; + wire [2:0] _1146_; + wire [127:0] _1147_; + wire [127:0] _1148_; + wire [7:0] _1149_; + wire [7:0] _1150_; + wire [31:0] _1151_; + wire _1152_; + wire [7:0] _1153_; + wire [7:0] _1154_; + wire _1155_; + wire [3:0] _1156_; + wire _1157_; + wire _1158_; + wire _1159_; + wire _1160_; + wire _1161_; + wire _1162_; + wire _1163_; + wire _1164_; + wire _1165_; + wire _1166_; + wire _1167_; + wire _1168_; + wire _1169_; + wire [6:0] _1170_; + wire [6:0] _1171_; + wire [6:0] _1172_; + wire _1173_; + wire [6:0] _1174_; + wire _1175_; + wire _1176_; + wire _1177_; + wire _1178_; + wire _1179_; + wire _1180_; + wire _1181_; + wire [3:0] _1182_; + wire [3:0] _1183_; + wire [3:0] _1184_; + wire [3:0] _1185_; + wire [3:0] _1186_; + wire [3:0] _1187_; + wire [3:0] _1188_; + wire [3:0] _1189_; + wire _1190_; + wire [3:0] _1191_; + wire [3:0] _1192_; + wire _1193_; + wire _1194_; + wire _1195_; + wire _1196_; + wire _1197_; + wire _1198_; + wire _1199_; + wire _1200_; + wire _1201_; + wire [3:0] _1202_; + wire [3:0] _1203_; + wire [3:0] _1204_; + wire [3:0] _1205_; + wire [3:0] _1206_; + wire [3:0] _1207_; + wire [3:0] _1208_; + wire [3:0] _1209_; + wire [3:0] _1210_; + wire [3:0] _1211_; + wire [3:0] _1212_; + wire [3:0] _1213_; + wire [3:0] _1214_; + wire [3:0] _1215_; + wire [3:0] _1216_; + wire [3:0] _1217_; + wire [3:0] _1218_; + wire _1219_; + wire _1220_; + wire _1221_; + wire [7:0] _1222_; + wire [127:0] _1223_; + wire [127:0] _1224_; + wire [127:0] _1225_; + wire [127:0] _1226_; + wire [127:0] _1227_; + wire [127:0] _1228_; + wire [127:0] _1229_; + wire [127:0] _1230_; + wire [127:0] _1231_; + wire [2047:0] _1232_; + wire [2047:0] _1233_; + wire [2047:0] _1234_; + wire [2:0] _1235_; + wire [15:0] _1236_; + wire [2047:0] _1237_; + wire [31:0] _1238_; + wire [13:0] _1239_; + wire [13:0] _1240_; + wire [13:0] _1241_; + wire [13:0] _1242_; + wire [13:0] _1243_; + wire [13:0] _1244_; + wire [13:0] _1245_; + wire [13:0] _1246_; + wire [13:0] _1247_; + wire [13:0] _1248_; + wire [13:0] _1249_; + wire [13:0] _1250_; + wire [13:0] _1251_; + wire [13:0] _1252_; + wire [13:0] _1253_; + wire [13:0] _1254_; + wire _1255_; + wire _1256_; + wire _1257_; + wire _1258_; + wire _1259_; + wire _1260_; + wire _1261_; + wire _1262_; + wire _1263_; + wire _1264_; + wire _1265_; + wire _1266_; + wire _1267_; + wire _1268_; + wire _1269_; + wire [32:0] _1270_; + wire [2047:0] _1271_; + wire [31:0] _1272_; + wire [2047:0] _1273_; + wire _1274_; + wire _1275_; + wire _1276_; + wire [7:0] _1277_; + wire _1278_; + wire [7:0] _1279_; + wire [7:0] _1280_; + wire [7:0] _1281_; + wire _1282_; + wire [7:0] _1283_; + wire [7:0] _1284_; + wire [7:0] _1285_; + wire _1286_; + wire [7:0] _1287_; + wire [7:0] _1288_; + wire _1289_; + wire _1290_; + wire _1291_; + wire [31:0] _1292_; + wire [31:0] _1293_; + wire [31:0] _1294_; + wire _1295_; + wire _1296_; + wire _1297_; + wire [15:0] _1298_; + wire [15:0] _1299_; + wire [2:0] _1300_; + wire [2:0] _1301_; + wire [2:0] _1302_; + wire [2:0] _1303_; + wire [2:0] _1304_; + wire [2:0] _1305_; + wire [2:0] _1306_; + wire [2:0] _1307_; + wire [2:0] _1308_; + wire [2:0] _1309_; + wire [2:0] _1310_; + wire [7:0] _1311_; + wire [7:0] _1312_; + wire [7:0] _1313_; + wire [7:0] _1314_; + wire [7:0] _1315_; + wire [7:0] _1316_; + wire [7:0] _1317_; + wire [7:0] _1318_; + wire [7:0] _1319_; + wire _1320_; + wire _1321_; + wire _1322_; + wire _1323_; + wire _1324_; + wire _1325_; + wire _1326_; + wire _1327_; + wire _1328_; + wire _1329_; + wire _1330_; + wire _1331_; + wire _1332_; + wire _1333_; + wire _1334_; + wire _1335_; + wire _1336_; + wire _1337_; + wire _1338_; + wire [2047:0] _1339_; + wire [2047:0] _1340_; + wire [31:0] _1341_; + wire [31:0] _1342_; + wire [31:0] _1343_; + wire [31:0] _1344_; + wire [31:0] _1345_; + wire [31:0] _1346_; + wire [31:0] _1347_; + wire [31:0] _1348_; + wire [31:0] _1349_; + wire [31:0] _1350_; + wire [31:0] _1351_; + wire [31:0] _1352_; + wire [31:0] _1353_; + wire [31:0] _1354_; + wire [31:0] _1355_; + wire [31:0] _1356_; + wire [31:0] _1357_; + wire [31:0] _1358_; + wire [31:0] _1359_; + wire [31:0] _1360_; + wire [31:0] _1361_; + wire [31:0] _1362_; + wire [31:0] _1363_; + wire [31:0] _1364_; + wire [31:0] _1365_; + wire [31:0] _1366_; + wire [31:0] _1367_; + wire [31:0] _1368_; + wire [31:0] _1369_; + wire [31:0] _1370_; + wire [31:0] _1371_; + wire [31:0] _1372_; + wire [31:0] _1373_; + wire [7:0] _1374_; + wire [7:0] _1375_; + wire [7:0] _1376_; + wire [7:0] _1377_; + wire [7:0] _1378_; + wire [7:0] _1379_; + wire [31:0] _1380_; + wire [15:0] _1381_; + wire [31:0] _1382_; + wire [31:0] _1383_; + wire [31:0] _1384_; + wire [13:0] _1385_; + wire [13:0] _1386_; + wire [13:0] _1387_; + wire [13:0] _1388_; + wire [13:0] _1389_; + wire [13:0] _1390_; + wire [13:0] _1391_; + wire [13:0] _1392_; + wire [13:0] _1393_; + wire [13:0] _1394_; + wire [13:0] _1395_; + wire [13:0] _1396_; + wire [13:0] _1397_; + wire [13:0] _1398_; + wire [13:0] _1399_; + wire [13:0] _1400_; + wire _1401_; + wire _1402_; + wire _1403_; + wire _1404_; + wire _1405_; + wire _1406_; + wire _1407_; + wire _1408_; + wire _1409_; + wire _1410_; + wire _1411_; + wire _1412_; + wire _1413_; + wire _1414_; + wire [31:0] _1415_; + wire [31:0] _1416_; + wire _1417_; + wire _1418_; + wire _1419_; + wire _1420_; + wire _1421_; + wire _1422_; + wire _1423_; + wire [7:0] _1424_; + wire [31:0] _1425_; + wire [31:0] _1426_; + wire [31:0] _1427_; + wire [31:0] _1428_; + wire [31:0] _1429_; + wire [31:0] _1430_; + wire [31:0] _1431_; + wire [31:0] _1432_; + wire [31:0] _1433_; + wire [31:0] _1434_; + wire [31:0] _1435_; + wire [31:0] _1436_; + wire [31:0] _1437_; + wire [31:0] _1438_; + wire [31:0] _1439_; + wire [31:0] _1440_; + wire [31:0] _1441_; + wire [31:0] _1442_; + wire [31:0] _1443_; + wire [31:0] _1444_; + wire [31:0] _1445_; + wire [31:0] _1446_; + wire [31:0] _1447_; + wire [31:0] _1448_; + wire [31:0] _1449_; + wire [31:0] _1450_; + wire [31:0] _1451_; + wire [31:0] _1452_; + wire [31:0] _1453_; + wire [31:0] _1454_; + wire [31:0] _1455_; + wire [31:0] _1456_; + wire [31:0] _1457_; + wire [31:0] _1458_; + wire [31:0] _1459_; + wire [31:0] _1460_; + wire [31:0] _1461_; + wire _1462_; + wire _1463_; + wire _1464_; + wire _1465_; + wire _1466_; + wire _1467_; + wire _1468_; + wire _1469_; + wire _1470_; + wire _1471_; + wire _1472_; + wire _1473_; + wire _1474_; + wire _1475_; + wire _1476_; + wire _1477_; + wire _1478_; + wire _1479_; + wire _1480_; + wire _1481_; + wire _1482_; + wire _1483_; + wire _1484_; + wire _1485_; + wire _1486_; + wire _1487_; + wire _1488_; + wire _1489_; + wire _1490_; + wire _1491_; + wire _1492_; + wire _1493_; + wire _1494_; + wire _1495_; + wire _1496_; + wire _1497_; + wire _1498_; + wire _1499_; + wire _1500_; + wire _1501_; + wire _1502_; + wire _1503_; + wire _1504_; + wire _1505_; + wire _1506_; + wire _1507_; + wire _1508_; + wire _1509_; + wire _1510_; + wire _1511_; + wire _1512_; + wire _1513_; + wire _1514_; + wire _1515_; + wire _1516_; + wire _1517_; + wire _1518_; + wire _1519_; + wire _1520_; + wire _1521_; + wire _1522_; + wire _1523_; + wire _1524_; + wire _1525_; + wire _1526_; + wire _1527_; + wire _1528_; + wire _1529_; + wire _1530_; + wire _1531_; + wire _1532_; + wire _1533_; + wire _1534_; + wire _1535_; + wire _1536_; + wire _1537_; + wire _1538_; + wire _1539_; + wire _1540_; + wire _1541_; + wire _1542_; + wire _1543_; + wire _1544_; + wire _1545_; + wire _1546_; + wire _1547_; + wire _1548_; + wire _1549_; + wire _1550_; + wire _1551_; + wire _1552_; + wire _1553_; + wire _1554_; + wire _1555_; + wire _1556_; + wire _1557_; + wire _1558_; + wire _1559_; + wire _1560_; + wire _1561_; + wire _1562_; + wire _1563_; + wire _1564_; + wire _1565_; + wire _1566_; + wire _1567_; + wire _1568_; + wire _1569_; + wire _1570_; + wire _1571_; + wire _1572_; + wire _1573_; + wire _1574_; + wire _1575_; + wire _1576_; + wire _1577_; + wire _1578_; + wire _1579_; + wire _1580_; + wire _1581_; + wire _1582_; + wire _1583_; + wire _1584_; + wire _1585_; + wire _1586_; + wire _1587_; + wire _1588_; + wire _1589_; + wire _1590_; + wire _1591_; + wire _1592_; + wire _1593_; + wire _1594_; + wire _1595_; + wire _1596_; + wire _1597_; + wire _1598_; + wire _1599_; + wire _1600_; + wire _1601_; + wire _1602_; + wire _1603_; + wire _1604_; + wire _1605_; + wire _1606_; + wire _1607_; + wire _1608_; + wire _1609_; + wire _1610_; + wire _1611_; + wire _1612_; + wire _1613_; + wire _1614_; + wire _1615_; + wire _1616_; + wire _1617_; + wire _1618_; + wire _1619_; + wire _1620_; + wire _1621_; + wire _1622_; + wire _1623_; + wire _1624_; + wire _1625_; + wire _1626_; + wire _1627_; + wire _1628_; + wire _1629_; + wire _1630_; + wire _1631_; + wire _1632_; + wire _1633_; + wire _1634_; + wire _1635_; + wire _1636_; + wire _1637_; + wire _1638_; + wire _1639_; + wire _1640_; + wire _1641_; + wire _1642_; + wire _1643_; + wire _1644_; + wire _1645_; + wire _1646_; + wire _1647_; + wire _1648_; + wire _1649_; + wire _1650_; + wire _1651_; + wire _1652_; + wire _1653_; + wire _1654_; + wire _1655_; + wire _1656_; + wire _1657_; + wire _1658_; + wire _1659_; + wire _1660_; + wire _1661_; + wire _1662_; + wire _1663_; + wire _1664_; + wire _1665_; + wire _1666_; + wire _1667_; + wire _1668_; + wire _1669_; + wire _1670_; + wire _1671_; + wire _1672_; + wire _1673_; + wire _1674_; + wire _1675_; + wire _1676_; + wire _1677_; + wire _1678_; + wire _1679_; + wire _1680_; + wire _1681_; + wire _1682_; + wire _1683_; + wire _1684_; + wire _1685_; + wire _1686_; + wire _1687_; + wire _1688_; + wire _1689_; + wire _1690_; + wire _1691_; + wire _1692_; + wire _1693_; + wire [7:0] _1694_; + wire _1695_; + wire _1696_; + wire _1697_; + wire _1698_; + wire [31:0] _1699_; + wire [31:0] _1700_; + wire [31:0] _1701_; + wire [31:0] _1702_; + wire [31:0] _1703_; + wire [31:0] _1704_; + wire [31:0] _1705_; + wire [31:0] _1706_; + wire [31:0] _1707_; + wire [31:0] _1708_; + wire [31:0] _1709_; + wire [31:0] _1710_; + wire [31:0] _1711_; + wire [31:0] _1712_; + wire _1713_; + wire [31:0] _1714_; + wire [31:0] _1715_; + wire [31:0] _1716_; + wire [31:0] _1717_; + wire [31:0] _1718_; + wire [31:0] _1719_; + wire [31:0] _1720_; + wire [31:0] _1721_; + wire [31:0] _1722_; + wire [31:0] _1723_; + wire [31:0] _1724_; + wire [31:0] _1725_; + wire [31:0] _1726_; + wire [31:0] _1727_; + wire [31:0] _1728_; + wire [31:0] _1729_; + wire [31:0] _1730_; + wire [31:0] _1731_; + wire [31:0] _1732_; + wire [31:0] _1733_; + wire _1734_; + wire _1735_; + wire _1736_; + wire _1737_; + wire _1738_; + wire _1739_; + wire _1740_; + wire _1741_; + wire _1742_; + wire _1743_; + wire _1744_; + wire _1745_; + wire _1746_; + wire _1747_; + wire _1748_; + wire _1749_; + wire _1750_; + wire _1751_; + wire _1752_; + wire _1753_; + wire _1754_; + wire _1755_; + wire _1756_; + wire _1757_; + wire _1758_; + wire _1759_; + wire _1760_; + wire _1761_; + wire _1762_; + wire _1763_; + wire _1764_; + wire _1765_; + wire _1766_; + wire _1767_; + wire _1768_; + wire _1769_; + wire _1770_; + wire _1771_; + wire _1772_; + wire _1773_; + wire _1774_; + wire _1775_; + wire _1776_; + wire _1777_; + wire _1778_; + wire _1779_; + wire _1780_; + wire _1781_; + wire _1782_; + wire _1783_; + wire _1784_; + wire _1785_; + wire _1786_; + wire _1787_; + wire _1788_; + wire _1789_; + wire _1790_; + wire _1791_; + wire _1792_; + wire _1793_; + wire _1794_; + wire _1795_; + wire _1796_; + wire _1797_; + wire _1798_; + wire _1799_; + wire _1800_; + wire _1801_; + wire _1802_; + wire _1803_; + wire _1804_; + wire _1805_; + wire _1806_; + wire _1807_; + wire _1808_; + wire _1809_; + wire _1810_; + wire _1811_; + wire _1812_; + wire _1813_; + wire _1814_; + wire _1815_; + wire _1816_; + wire _1817_; + wire _1818_; + wire _1819_; + wire _1820_; + wire _1821_; + wire _1822_; + wire _1823_; + wire _1824_; + wire [7:0] _1825_; + wire [7:0] _1826_; + wire [7:0] _1827_; + wire [7:0] _1828_; + wire [7:0] _1829_; + wire [7:0] _1830_; + wire [7:0] _1831_; + wire [7:0] _1832_; + wire [7:0] _1833_; + wire [7:0] _1834_; + wire [7:0] _1835_; + wire [7:0] _1836_; + wire [7:0] _1837_; + wire [7:0] _1838_; + wire [7:0] _1839_; + wire [7:0] _1840_; + wire [7:0] _1841_; + wire [7:0] _1842_; + wire [7:0] _1843_; + wire [7:0] _1844_; + wire [7:0] _1845_; + wire [7:0] _1846_; + wire [7:0] _1847_; + wire [7:0] _1848_; + wire [7:0] _1849_; + wire [7:0] _1850_; + wire [7:0] _1851_; + wire [7:0] _1852_; + wire [7:0] _1853_; + wire [7:0] _1854_; + wire [7:0] _1855_; + wire [7:0] _1856_; + wire [7:0] _1857_; + wire [7:0] _1858_; + wire [7:0] _1859_; + wire [7:0] _1860_; + wire [7:0] _1861_; + wire [7:0] _1862_; + wire [7:0] _1863_; + wire [7:0] _1864_; + wire [7:0] _1865_; + wire [7:0] _1866_; + wire [7:0] _1867_; + wire [7:0] _1868_; + wire [7:0] _1869_; + wire [7:0] _1870_; + wire [7:0] _1871_; + wire [7:0] _1872_; + wire [7:0] _1873_; + wire [7:0] _1874_; + wire [7:0] _1875_; + wire [7:0] _1876_; + wire [7:0] _1877_; + wire [7:0] _1878_; + wire [7:0] _1879_; + wire [7:0] _1880_; + wire [7:0] _1881_; + wire [7:0] _1882_; + wire [7:0] _1883_; + wire [7:0] _1884_; + wire [7:0] _1885_; + wire [7:0] _1886_; + wire [7:0] _1887_; + wire [7:0] _1888_; + wire [7:0] _1889_; + wire [7:0] _1890_; + wire [7:0] _1891_; + wire [7:0] _1892_; + wire [7:0] _1893_; + wire [7:0] _1894_; + wire [7:0] _1895_; + wire [7:0] _1896_; + wire [7:0] _1897_; + wire [7:0] _1898_; + wire [7:0] _1899_; + wire [7:0] _1900_; + wire [7:0] _1901_; + wire [7:0] _1902_; + wire [7:0] _1903_; + wire [7:0] _1904_; + wire [7:0] _1905_; + wire [7:0] _1906_; + wire [7:0] _1907_; + wire [7:0] _1908_; + wire [7:0] _1909_; + wire [7:0] _1910_; + wire [7:0] _1911_; + wire [7:0] _1912_; + wire [7:0] _1913_; + wire [7:0] _1914_; + wire [7:0] _1915_; + wire [7:0] _1916_; + wire [7:0] _1917_; + wire [7:0] _1918_; + wire [7:0] _1919_; + wire [7:0] _1920_; + wire [7:0] _1921_; + wire [7:0] _1922_; + wire [7:0] _1923_; + wire [7:0] _1924_; + wire [31:0] _1925_; + wire [31:0] _1926_; + wire [31:0] _1927_; + wire [31:0] _1928_; + wire [31:0] _1929_; + wire [31:0] _1930_; + wire [31:0] _1931_; + wire [31:0] _1932_; + wire [31:0] _1933_; + wire [31:0] _1934_; + wire [31:0] _1935_; + wire [31:0] _1936_; + wire [31:0] _1937_; + wire [31:0] _1938_; + wire [31:0] _1939_; + wire [31:0] _1940_; + wire [31:0] _1941_; + wire [31:0] _1942_; + wire [31:0] _1943_; + wire [31:0] _1944_; + wire [31:0] _1945_; + wire [31:0] _1946_; + wire [31:0] _1947_; + wire [31:0] _1948_; + wire [31:0] _1949_; + wire [31:0] _1950_; + wire [31:0] _1951_; + wire [31:0] _1952_; + wire [31:0] _1953_; + wire [31:0] _1954_; + wire [31:0] _1955_; + wire [31:0] _1956_; + wire [31:0] _1957_; + wire [31:0] _1958_; + wire [31:0] _1959_; + wire [31:0] _1960_; + wire [31:0] _1961_; + wire [31:0] _1962_; + wire [31:0] _1963_; + wire [31:0] _1964_; + wire [31:0] _1965_; + wire [31:0] _1966_; + wire [31:0] _1967_; + wire [31:0] _1968_; + wire [31:0] _1969_; + wire [31:0] _1970_; + wire [31:0] _1971_; + wire [31:0] _1972_; + wire [31:0] _1973_; + wire [31:0] _1974_; + wire [31:0] _1975_; + wire [31:0] _1976_; + wire [31:0] _1977_; + wire [31:0] _1978_; + wire [31:0] _1979_; + wire [31:0] _1980_; + wire [31:0] _1981_; + wire [31:0] _1982_; + wire [31:0] _1983_; + wire [31:0] _1984_; + wire [31:0] _1985_; + wire [31:0] _1986_; + wire [31:0] _1987_; + wire [31:0] _1988_; + wire [31:0] _1989_; + wire [31:0] _1990_; + wire [31:0] _1991_; + wire [31:0] _1992_; + wire [31:0] _1993_; + wire [31:0] _1994_; + wire [31:0] _1995_; + wire [31:0] _1996_; + wire [31:0] _1997_; + wire [31:0] _1998_; + wire [31:0] _1999_; + wire [31:0] _2000_; + wire [31:0] _2001_; + wire [31:0] _2002_; + wire [31:0] _2003_; + wire [31:0] _2004_; + wire [31:0] _2005_; + wire [31:0] _2006_; + wire [31:0] _2007_; + wire [31:0] _2008_; + wire [31:0] _2009_; + wire [31:0] _2010_; + wire [31:0] _2011_; + wire [31:0] _2012_; + wire [31:0] _2013_; + wire [31:0] _2014_; + wire [31:0] _2015_; + wire [31:0] _2016_; + wire [31:0] _2017_; + wire [31:0] _2018_; + wire [31:0] _2019_; + wire [31:0] _2020_; + wire [31:0] _2021_; + wire [31:0] _2022_; + wire [31:0] _2023_; + wire [31:0] _2024_; + wire [31:0] _2025_; + wire [31:0] _2026_; + wire [31:0] _2027_; + wire [31:0] _2028_; + wire [31:0] _2029_; + wire [31:0] _2030_; + wire [31:0] _2031_; + wire [31:0] _2032_; + wire [31:0] _2033_; + wire [31:0] _2034_; + wire [31:0] _2035_; + wire [31:0] _2036_; + wire [31:0] _2037_; + wire [31:0] _2038_; + wire [31:0] _2039_; + wire [31:0] _2040_; + wire [31:0] _2041_; + wire [31:0] _2042_; + wire [31:0] _2043_; + wire [31:0] _2044_; + wire [31:0] _2045_; + wire [31:0] _2046_; + wire [31:0] _2047_; + wire [31:0] _2048_; + wire [31:0] _2049_; + wire [31:0] _2050_; + wire [31:0] _2051_; + wire [31:0] _2052_; + wire [31:0] _2053_; + wire [31:0] _2054_; + wire [31:0] _2055_; + wire [31:0] _2056_; + wire [31:0] _2057_; + wire [31:0] _2058_; + wire [31:0] _2059_; + wire [31:0] _2060_; + wire [31:0] _2061_; + wire [31:0] _2062_; + wire [31:0] _2063_; + wire [31:0] _2064_; + wire [31:0] _2065_; + wire [31:0] _2066_; + wire [31:0] _2067_; + wire [31:0] _2068_; + wire [31:0] _2069_; + wire [31:0] _2070_; + wire [31:0] _2071_; + wire [31:0] _2072_; + wire [31:0] _2073_; + wire _2074_; + wire _2075_; + wire _2076_; + wire _2077_; + wire _2078_; + wire _2079_; + wire _2080_; + wire _2081_; + wire _2082_; + wire _2083_; + wire _2084_; + wire _2085_; + wire _2086_; + wire _2087_; + wire _2088_; + wire _2089_; + wire _2090_; + wire _2091_; + wire _2092_; + wire _2093_; + wire _2094_; + wire _2095_; + wire _2096_; + wire _2097_; + wire _2098_; + wire _2099_; + wire _2100_; + wire _2101_; + wire _2102_; + wire _2103_; + wire _2104_; + wire _2105_; + wire _2106_; + wire _2107_; + wire _2108_; + wire _2109_; + wire _2110_; + wire _2111_; + wire _2112_; + wire [15:0] _2113_; + wire [15:0] _2114_; + wire [15:0] _2115_; + wire [15:0] _2116_; + wire [15:0] _2117_; + wire [15:0] _2118_; + wire [15:0] _2119_; + wire [15:0] _2120_; + wire [15:0] _2121_; + wire [15:0] _2122_; + wire [15:0] _2123_; + wire [15:0] _2124_; + wire [15:0] _2125_; + wire [15:0] _2126_; + wire [15:0] _2127_; + wire [15:0] _2128_; + wire [15:0] _2129_; + wire [15:0] _2130_; + wire [15:0] _2131_; + wire [15:0] _2132_; + wire [15:0] _2133_; + wire [15:0] _2134_; + wire [15:0] _2135_; + wire [15:0] _2136_; + wire [15:0] _2137_; + wire [15:0] _2138_; + wire [15:0] _2139_; + wire [15:0] _2140_; + wire [15:0] _2141_; + wire [15:0] _2142_; + wire [15:0] _2143_; + wire [15:0] _2144_; + wire [15:0] _2145_; + wire [15:0] _2146_; + wire [15:0] _2147_; + wire [15:0] _2148_; + wire [127:0] _2149_; + wire [127:0] _2150_; + wire [127:0] _2151_; + wire [127:0] _2152_; + wire [127:0] _2153_; + wire [127:0] _2154_; + wire [127:0] _2155_; + wire [127:0] _2156_; + wire [127:0] _2157_; + wire [127:0] _2158_; + wire [127:0] _2159_; + wire [127:0] _2160_; + wire [127:0] _2161_; + wire [127:0] _2162_; + wire [127:0] _2163_; + wire [127:0] _2164_; + wire [127:0] _2165_; + wire [127:0] _2166_; + wire [127:0] _2167_; + wire [127:0] _2168_; + wire [127:0] _2169_; + wire [127:0] _2170_; + wire [127:0] _2171_; + wire [127:0] _2172_; + wire [127:0] _2173_; + wire [127:0] _2174_; + wire [127:0] _2175_; + wire [127:0] _2176_; + wire [127:0] _2177_; + wire [127:0] _2178_; + wire [127:0] _2179_; + wire [127:0] _2180_; + wire [127:0] _2181_; + wire [127:0] _2182_; + wire [127:0] _2183_; + wire [127:0] _2184_; + wire [127:0] _2185_; + wire [127:0] _2186_; + wire [127:0] _2187_; + wire [127:0] _2188_; + wire [127:0] _2189_; + wire [127:0] _2190_; + wire [127:0] _2191_; + wire [127:0] _2192_; + wire [127:0] _2193_; + wire [127:0] _2194_; + wire [127:0] _2195_; + wire [127:0] _2196_; + wire [127:0] _2197_; + wire [127:0] _2198_; + wire [127:0] _2199_; + wire [127:0] _2200_; + wire [127:0] _2201_; + wire [127:0] _2202_; + wire [127:0] _2203_; + wire [127:0] _2204_; + wire [127:0] _2205_; + wire [127:0] _2206_; + wire [127:0] _2207_; + wire [127:0] _2208_; + wire [127:0] _2209_; + wire [127:0] _2210_; + wire [127:0] _2211_; + wire [127:0] _2212_; + wire [127:0] _2213_; + wire [127:0] _2214_; + wire [127:0] _2215_; + wire [127:0] _2216_; + wire [127:0] _2217_; + wire [127:0] _2218_; + wire [127:0] _2219_; + wire [127:0] _2220_; + wire [127:0] _2221_; + wire [127:0] _2222_; + wire [127:0] _2223_; + wire [127:0] _2224_; + wire [127:0] _2225_; + wire [127:0] _2226_; + wire [7:0] _2227_; + wire [7:0] _2228_; + wire [7:0] _2229_; + wire [7:0] _2230_; + wire [7:0] _2231_; + wire [7:0] _2232_; + wire [7:0] _2233_; + wire [7:0] _2234_; + wire [7:0] _2235_; + wire [7:0] _2236_; + wire [7:0] _2237_; + wire [7:0] _2238_; + wire [7:0] _2239_; + wire [7:0] _2240_; + wire [7:0] _2241_; + wire [7:0] _2242_; + wire [7:0] _2243_; + wire [7:0] _2244_; + wire [7:0] _2245_; + wire [7:0] _2246_; + wire [7:0] _2247_; + wire [7:0] _2248_; + wire [7:0] _2249_; + wire [7:0] _2250_; + wire [7:0] _2251_; + wire [7:0] _2252_; + wire [7:0] _2253_; + wire [7:0] _2254_; + wire [7:0] _2255_; + wire [7:0] _2256_; + wire [7:0] _2257_; + wire [7:0] _2258_; + wire [7:0] _2259_; + wire [7:0] _2260_; + wire [7:0] _2261_; + wire [7:0] _2262_; + wire [7:0] _2263_; + wire [7:0] _2264_; + wire [7:0] _2265_; + wire [3:0] _2266_; + wire [3:0] _2267_; + wire [3:0] _2268_; + wire [3:0] _2269_; + wire [3:0] _2270_; + wire [3:0] _2271_; + wire [3:0] _2272_; + wire [3:0] _2273_; + wire [3:0] _2274_; + wire [3:0] _2275_; + wire [3:0] _2276_; + wire [3:0] _2277_; + wire [3:0] _2278_; + wire [3:0] _2279_; + wire [3:0] _2280_; + wire [3:0] _2281_; + wire [3:0] _2282_; + wire [3:0] _2283_; + wire [3:0] _2284_; + wire [3:0] _2285_; + wire [3:0] _2286_; + wire [3:0] _2287_; + wire [3:0] _2288_; + wire [3:0] _2289_; + wire [3:0] _2290_; + wire [3:0] _2291_; + wire [3:0] _2292_; + wire [3:0] _2293_; + wire [3:0] _2294_; + wire [3:0] _2295_; + wire [3:0] _2296_; + wire [3:0] _2297_; + wire [3:0] _2298_; + wire [3:0] _2299_; + wire [3:0] _2300_; + wire [3:0] _2301_; + wire [3:0] _2302_; + wire [3:0] _2303_; + wire [3:0] _2304_; + wire [3:0] _2305_; + wire [3:0] _2306_; + wire [3:0] _2307_; + wire [3:0] _2308_; + wire [3:0] _2309_; + wire [3:0] _2310_; + wire [3:0] _2311_; + wire [3:0] _2312_; + wire [3:0] _2313_; + wire [3:0] _2314_; + wire [3:0] _2315_; + wire [3:0] _2316_; + wire [3:0] _2317_; + wire [3:0] _2318_; + wire [3:0] _2319_; + wire _2320_; + wire _2321_; + wire _2322_; + wire _2323_; + wire _2324_; + wire _2325_; + wire _2326_; + wire _2327_; + wire _2328_; + wire _2329_; + wire _2330_; + wire _2331_; + wire _2332_; + wire _2333_; + wire _2334_; + wire _2335_; + wire _2336_; + wire _2337_; + wire _2338_; + wire _2339_; + wire _2340_; + wire _2341_; + wire _2342_; + wire _2343_; + wire _2344_; + wire _2345_; + wire _2346_; + wire _2347_; + wire _2348_; + wire _2349_; + wire _2350_; + wire _2351_; + wire _2352_; + wire _2353_; + wire _2354_; + wire _2355_; + wire _2356_; + wire _2357_; + wire _2358_; + wire [543:0] _2359_; + wire [543:0] _2360_; + wire [543:0] _2361_; + wire [543:0] _2362_; + wire [543:0] _2363_; + wire [543:0] _2364_; + wire [543:0] _2365_; + wire [543:0] _2366_; + wire [543:0] _2367_; + wire [543:0] _2368_; + wire [543:0] _2369_; + wire [543:0] _2370_; + wire [543:0] _2371_; + wire [543:0] _2372_; + wire [543:0] _2373_; + wire [543:0] _2374_; + wire [543:0] _2375_; + wire [543:0] _2376_; + wire [543:0] _2377_; + wire [543:0] _2378_; + wire [543:0] _2379_; + wire [543:0] _2380_; + wire [543:0] _2381_; + wire [543:0] _2382_; + wire [543:0] _2383_; + wire [543:0] _2384_; + wire [543:0] _2385_; + wire [543:0] _2386_; + wire [543:0] _2387_; + wire [543:0] _2388_; + wire [543:0] _2389_; + wire [543:0] _2390_; + wire [543:0] _2391_; + wire [543:0] _2392_; + wire [543:0] _2393_; + wire [543:0] _2394_; + wire [543:0] _2395_; + wire [543:0] _2396_; + wire [543:0] _2397_; + wire [543:0] _2398_; + wire [543:0] _2399_; + wire [543:0] _2400_; + wire [543:0] _2401_; + wire [543:0] _2402_; + wire [543:0] _2403_; + wire [543:0] _2404_; + wire [543:0] _2405_; + wire [543:0] _2406_; + wire [543:0] _2407_; + wire [543:0] _2408_; + wire [543:0] _2409_; + wire [15:0] _2410_; + wire [15:0] _2411_; + wire [15:0] _2412_; + wire [15:0] _2413_; + wire [15:0] _2414_; + wire [15:0] _2415_; + wire [15:0] _2416_; + wire [15:0] _2417_; + wire [15:0] _2418_; + wire [15:0] _2419_; + wire [15:0] _2420_; + wire [15:0] _2421_; + wire [15:0] _2422_; + wire [15:0] _2423_; + wire [15:0] _2424_; + wire [15:0] _2425_; + wire [15:0] _2426_; + wire [15:0] _2427_; + wire [15:0] _2428_; + wire [15:0] _2429_; + wire [15:0] _2430_; + wire [15:0] _2431_; + wire [15:0] _2432_; + wire [15:0] _2433_; + wire [15:0] _2434_; + wire [15:0] _2435_; + wire [15:0] _2436_; + wire [15:0] _2437_; + wire [15:0] _2438_; + wire [15:0] _2439_; + wire [15:0] _2440_; + wire [15:0] _2441_; + wire [15:0] _2442_; + wire [15:0] _2443_; + wire [15:0] _2444_; + wire [15:0] _2445_; + wire [15:0] _2446_; + wire [15:0] _2447_; + wire [15:0] _2448_; + wire [15:0] _2449_; + wire [15:0] _2450_; + wire [15:0] _2451_; + wire [15:0] _2452_; + wire [15:0] _2453_; + wire [15:0] _2454_; + wire [15:0] _2455_; + wire [15:0] _2456_; + wire [15:0] _2457_; + wire [15:0] _2458_; + wire [15:0] _2459_; + wire [7:0] _2460_; + wire [7:0] _2461_; + wire [7:0] _2462_; + wire [7:0] _2463_; + wire [7:0] _2464_; + wire [7:0] _2465_; + wire [7:0] _2466_; + wire [7:0] _2467_; + wire [7:0] _2468_; + wire _2469_; + wire _2470_; + wire _2471_; + wire _2472_; + wire _2473_; + wire _2474_; + wire _2475_; + wire _2476_; + wire _2477_; + wire _2478_; + wire _2479_; + wire _2480_; + wire _2481_; + wire _2482_; + wire _2483_; + wire _2484_; + wire _2485_; + wire _2486_; + wire _2487_; + wire _2488_; + wire _2489_; + wire _2490_; + wire _2491_; + wire _2492_; + wire _2493_; + wire _2494_; + wire _2495_; + wire _2496_; + wire _2497_; + wire _2498_; + wire _2499_; + wire _2500_; + wire _2501_; + wire _2502_; + wire _2503_; + wire _2504_; + wire _2505_; + wire _2506_; + wire _2507_; + wire _2508_; + wire _2509_; + wire _2510_; + wire _2511_; + wire _2512_; + wire _2513_; + wire _2514_; + wire _2515_; + wire _2516_; + wire _2517_; + wire _2518_; + wire _2519_; + wire _2520_; + wire _2521_; + wire _2522_; + wire _2523_; + wire _2524_; + wire _2525_; + wire _2526_; + wire _2527_; + wire _2528_; + wire _2529_; + wire _2530_; + wire _2531_; + wire _2532_; + wire _2533_; + wire _2534_; + wire _2535_; + wire _2536_; + wire _2537_; + wire _2538_; + wire _2539_; + wire _2540_; + wire _2541_; + wire _2542_; + wire _2543_; + wire _2544_; + wire _2545_; + wire _2546_; + wire [31:0] _2547_; + wire [31:0] _2548_; + wire [31:0] _2549_; + wire [31:0] _2550_; + wire [31:0] _2551_; + wire [31:0] _2552_; + wire [31:0] _2553_; + wire [31:0] _2554_; + wire [31:0] _2555_; + wire [31:0] _2556_; + wire [31:0] _2557_; + wire [31:0] _2558_; + wire [31:0] _2559_; + wire [31:0] _2560_; + wire [31:0] _2561_; + wire [31:0] _2562_; + wire [31:0] _2563_; + wire [31:0] _2564_; + wire [31:0] _2565_; + wire [31:0] _2566_; + wire [31:0] _2567_; + wire [31:0] _2568_; + wire [31:0] _2569_; + wire [31:0] _2570_; + wire [31:0] _2571_; + wire [31:0] _2572_; + wire [31:0] _2573_; + wire _2574_; + wire _2575_; + wire _2576_; + wire _2577_; + wire _2578_; + wire _2579_; + wire _2580_; + wire _2581_; + wire _2582_; + wire _2583_; + wire _2584_; + wire _2585_; + wire _2586_; + wire _2587_; + wire _2588_; + wire _2589_; + wire _2590_; + wire _2591_; + wire _2592_; + wire _2593_; + wire _2594_; + wire _2595_; + wire _2596_; + wire _2597_; + wire _2598_; + wire _2599_; + wire _2600_; + wire _2601_; + wire _2602_; + wire _2603_; + wire _2604_; + wire _2605_; + wire _2606_; + wire _2607_; + wire _2608_; + wire _2609_; + wire _2610_; + wire _2611_; + wire _2612_; + wire _2613_; + wire _2614_; + wire _2615_; + wire _2616_; + wire _2617_; + wire _2618_; + wire _2619_; + wire _2620_; + wire _2621_; + wire _2622_; + wire _2623_; + wire _2624_; + wire _2625_; + wire _2626_; + wire _2627_; + wire _2628_; + wire _2629_; + wire _2630_; + wire _2631_; + wire _2632_; + wire _2633_; + wire _2634_; + wire _2635_; + wire _2636_; + wire _2637_; + wire _2638_; + wire _2639_; + wire _2640_; + wire _2641_; + wire _2642_; + wire _2643_; + wire _2644_; + wire _2645_; + wire _2646_; + wire _2647_; + wire _2648_; + wire _2649_; + wire _2650_; + wire _2651_; + wire _2652_; + wire _2653_; + wire _2654_; + wire _2655_; + wire _2656_; + wire _2657_; + wire _2658_; + wire _2659_; + wire _2660_; + wire _2661_; + wire _2662_; + wire _2663_; + wire _2664_; + wire _2665_; + wire _2666_; + wire _2667_; + wire _2668_; + wire _2669_; + wire _2670_; + wire _2671_; + wire _2672_; + wire _2673_; + wire _2674_; + wire _2675_; + wire _2676_; + wire _2677_; + wire _2678_; + wire _2679_; + wire _2680_; + wire _2681_; + wire _2682_; + wire _2683_; + wire _2684_; + wire _2685_; + wire _2686_; + wire _2687_; + wire _2688_; + wire _2689_; + wire _2690_; + wire _2691_; + wire _2692_; + wire _2693_; + wire _2694_; + wire _2695_; + wire _2696_; + wire _2697_; + wire _2698_; + wire _2699_; + wire _2700_; + wire _2701_; + wire _2702_; + wire _2703_; + wire _2704_; + wire _2705_; + wire _2706_; + wire _2707_; + wire _2708_; + wire _2709_; + wire _2710_; + wire _2711_; + wire _2712_; + wire _2713_; + wire _2714_; + wire _2715_; + wire _2716_; + wire _2717_; + wire _2718_; + wire _2719_; + wire _2720_; + wire _2721_; + wire [31:0] _2722_; + wire [31:0] _2723_; + wire [15:0] _2724_; + wire [31:0] _2725_; + wire [127:0] _2726_; + wire [31:0] _2727_; + wire [7:0] _2728_; + wire [31:0] _2729_; + wire [31:0] _2730_; + wire [31:0] _2731_; + wire [127:0] _2732_; + wire [127:0] _2733_; + wire [31:0] _2734_; + wire [7:0] _2735_; + wire _unused_adapter_fault; + input abort; + wire abort; + reg [7:0] active_profile; + wire \adapter._unused ; + wire \adapter.abort ; + wire \adapter.busy ; + wire \adapter.clk ; + wire \adapter.core_fault ; + wire [7:0] \adapter.core_rx_data ; + wire \adapter.core_rx_fire ; + wire \adapter.core_rx_ready ; + wire \adapter.core_rx_valid ; + wire [7:0] \adapter.core_tx_data ; + wire \adapter.core_tx_fire ; + wire \adapter.core_tx_ready ; + wire \adapter.core_tx_valid ; + wire \adapter.datapath.abort ; + reg [3:0] \adapter.datapath.byte_index ; + wire \adapter.datapath.clk ; + reg \adapter.datapath.fault ; + wire \adapter.datapath.mul_a_valid ; + wire \adapter.datapath.mul_bit_last ; + wire \adapter.datapath.mul_bit_valid ; + wire \adapter.datapath.mul_bit_value ; + wire [7:0] \adapter.datapath.mul_result_byte ; + wire \adapter.datapath.mul_result_shift ; + wire \adapter.datapath.mul_tail_last ; + wire [7:0] \adapter.datapath.multiplier.a_byte ; + wire \adapter.datapath.multiplier.a_last ; + wire \adapter.datapath.multiplier.a_valid ; + wire \adapter.datapath.multiplier.abort ; + wire \adapter.datapath.multiplier.bit_last ; + wire \adapter.datapath.multiplier.bit_valid ; + wire \adapter.datapath.multiplier.bit_value ; + wire \adapter.datapath.multiplier.clk ; + wire [7:0] \adapter.datapath.multiplier.impl.a_byte ; + wire \adapter.datapath.multiplier.impl.a_last ; + reg [127:0] \adapter.datapath.multiplier.impl.a_shift ; + wire \adapter.datapath.multiplier.impl.a_valid ; + wire \adapter.datapath.multiplier.impl.abort ; + reg [127:0] \adapter.datapath.multiplier.impl.accumulator ; + wire [127:0] \adapter.datapath.multiplier.impl.accumulator_next ; + wire \adapter.datapath.multiplier.impl.bit_last ; + wire \adapter.datapath.multiplier.impl.bit_valid ; + wire \adapter.datapath.multiplier.impl.bit_value ; + wire \adapter.datapath.multiplier.impl.clk ; + wire [7:0] \adapter.datapath.multiplier.impl.result_byte ; + wire \adapter.datapath.multiplier.impl.result_shift ; + wire \adapter.datapath.multiplier.impl.rst_n ; + wire [127:0] \adapter.datapath.multiplier.impl.selected ; + wire [7:0] \adapter.datapath.multiplier.result_byte ; + wire \adapter.datapath.multiplier.result_shift ; + wire \adapter.datapath.multiplier.rst_n ; + wire \adapter.datapath.rst_n ; + wire [7:0] \adapter.datapath.rx_data ; + wire \adapter.datapath.rx_fire ; + wire \adapter.datapath.rx_ready ; + wire \adapter.datapath.rx_valid ; + reg [7:0] \adapter.datapath.scratch_byte ; + reg [3:0] \adapter.datapath.state ; + wire [3:0] \adapter.datapath.status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.index ; + wire [7:0] \adapter.datapath.tx_data ; + wire \adapter.datapath.tx_fire ; + wire \adapter.datapath.tx_ready ; + wire \adapter.datapath.tx_valid ; + reg \adapter.done_pulse ; + reg \adapter.fault ; + wire [127:0] \adapter.operand_a ; + wire [127:0] \adapter.operand_b ; + wire [7:0] \adapter.operation ; + reg [5:0] \adapter.payload_index ; + reg [127:0] \adapter.result ; + reg [4:0] \adapter.result_index ; + wire \adapter.rst_n ; + reg [127:0] \adapter.saved_a ; + reg [127:0] \adapter.saved_b ; + reg [7:0] \adapter.saved_operation ; + wire \adapter.start ; + reg [2:0] \adapter.state ; + reg [31:0] addr_a; + reg [31:0] addr_b; + reg [31:0] addr_c; + wire alu_busy; + wire alu_done; + wire alu_fault; + reg [127:0] alu_operand_a; + reg [127:0] alu_operand_b; + reg [7:0] alu_operation; + wire [127:0] alu_result; + reg alu_start; + output busy; + wire busy; + reg capture_result_crc; + input clk; + wire clk; + reg [31:0] committed_fp; + reg [31:0] committed_pc; + reg [3:0] compute_state; + reg [31:0] deferred_local; + reg [31:0] deferred_target; + output done_pulse; + reg done_pulse; + wire encoder_busy; + wire encoder_done; + wire encoder_fault; + reg [15:0] encoder_index; + wire [127:0] encoder_result; + reg encoder_start; + wire event_ready; + wire event_valid; + output fault; + reg fault; + wire \field_encoder.abort ; + reg [4:0] \field_encoder.bit_index ; + reg \field_encoder.busy ; + wire \field_encoder.clk ; + reg \field_encoder.done_pulse ; + reg \field_encoder.fault ; + wire [15:0] \field_encoder.index ; + wire \field_encoder.multiplier._unused ; + wire \field_encoder.multiplier.abort ; + wire \field_encoder.multiplier.clk ; + wire \field_encoder.multiplier.core_fault ; + wire [7:0] \field_encoder.multiplier.core_rx_data ; + wire \field_encoder.multiplier.core_rx_fire ; + wire \field_encoder.multiplier.core_rx_ready ; + wire \field_encoder.multiplier.core_rx_valid ; + wire [7:0] \field_encoder.multiplier.core_tx_data ; + wire \field_encoder.multiplier.core_tx_fire ; + wire \field_encoder.multiplier.core_tx_ready ; + wire \field_encoder.multiplier.core_tx_valid ; + wire \field_encoder.multiplier.datapath.abort ; + reg [3:0] \field_encoder.multiplier.datapath.byte_index ; + wire \field_encoder.multiplier.datapath.clk ; + reg \field_encoder.multiplier.datapath.fault ; + wire \field_encoder.multiplier.datapath.mul_a_valid ; + wire \field_encoder.multiplier.datapath.mul_bit_last ; + wire \field_encoder.multiplier.datapath.mul_bit_valid ; + wire \field_encoder.multiplier.datapath.mul_bit_value ; + wire [7:0] \field_encoder.multiplier.datapath.mul_result_byte ; + wire \field_encoder.multiplier.datapath.mul_result_shift ; + wire \field_encoder.multiplier.datapath.mul_tail_last ; + wire [7:0] \field_encoder.multiplier.datapath.multiplier.a_byte ; + wire \field_encoder.multiplier.datapath.multiplier.a_last ; + wire \field_encoder.multiplier.datapath.multiplier.a_valid ; + wire \field_encoder.multiplier.datapath.multiplier.abort ; + wire \field_encoder.multiplier.datapath.multiplier.bit_last ; + wire \field_encoder.multiplier.datapath.multiplier.bit_valid ; + wire \field_encoder.multiplier.datapath.multiplier.bit_value ; + wire \field_encoder.multiplier.datapath.multiplier.clk ; + wire [7:0] \field_encoder.multiplier.datapath.multiplier.impl.a_byte ; + wire \field_encoder.multiplier.datapath.multiplier.impl.a_last ; + reg [127:0] \field_encoder.multiplier.datapath.multiplier.impl.a_shift ; + wire \field_encoder.multiplier.datapath.multiplier.impl.a_valid ; + wire \field_encoder.multiplier.datapath.multiplier.impl.abort ; + reg [127:0] \field_encoder.multiplier.datapath.multiplier.impl.accumulator ; + wire [127:0] \field_encoder.multiplier.datapath.multiplier.impl.accumulator_next ; + wire \field_encoder.multiplier.datapath.multiplier.impl.bit_last ; + wire \field_encoder.multiplier.datapath.multiplier.impl.bit_valid ; + wire \field_encoder.multiplier.datapath.multiplier.impl.bit_value ; + wire \field_encoder.multiplier.datapath.multiplier.impl.clk ; + wire [7:0] \field_encoder.multiplier.datapath.multiplier.impl.result_byte ; + wire \field_encoder.multiplier.datapath.multiplier.impl.result_shift ; + wire \field_encoder.multiplier.datapath.multiplier.impl.rst_n ; + wire [127:0] \field_encoder.multiplier.datapath.multiplier.impl.selected ; + wire [7:0] \field_encoder.multiplier.datapath.multiplier.result_byte ; + wire \field_encoder.multiplier.datapath.multiplier.result_shift ; + wire \field_encoder.multiplier.datapath.multiplier.rst_n ; + wire \field_encoder.multiplier.datapath.rst_n ; + wire [7:0] \field_encoder.multiplier.datapath.rx_data ; + wire \field_encoder.multiplier.datapath.rx_fire ; + wire \field_encoder.multiplier.datapath.rx_ready ; + wire \field_encoder.multiplier.datapath.rx_valid ; + reg [7:0] \field_encoder.multiplier.datapath.scratch_byte ; + reg [3:0] \field_encoder.multiplier.datapath.state ; + wire [3:0] \field_encoder.multiplier.datapath.status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.index ; + wire [7:0] \field_encoder.multiplier.datapath.tx_data ; + wire \field_encoder.multiplier.datapath.tx_fire ; + wire \field_encoder.multiplier.datapath.tx_ready ; + wire \field_encoder.multiplier.datapath.tx_valid ; + reg \field_encoder.multiplier.done_pulse ; + reg \field_encoder.multiplier.fault ; + wire [127:0] \field_encoder.multiplier.operand_a ; + wire [127:0] \field_encoder.multiplier.operand_b ; + wire [7:0] \field_encoder.multiplier.operation ; + reg [5:0] \field_encoder.multiplier.payload_index ; + reg [127:0] \field_encoder.multiplier.result ; + reg [4:0] \field_encoder.multiplier.result_index ; + wire \field_encoder.multiplier.rst_n ; + wire [127:0] \field_encoder.multiplier.saved_a ; + reg [127:0] \field_encoder.multiplier.saved_b ; + wire [7:0] \field_encoder.multiplier.saved_operation ; + wire \field_encoder.multiplier.start ; + reg [2:0] \field_encoder.multiplier.state ; + wire \field_encoder.multiply_done ; + wire \field_encoder.multiply_fault ; + wire [127:0] \field_encoder.multiply_result ; + reg \field_encoder.multiply_start ; + wire [127:0] \field_encoder.operand_a ; + reg [127:0] \field_encoder.operand_b ; + reg [127:0] \field_encoder.result ; + wire \field_encoder.rst_n ; + reg [15:0] \field_encoder.saved_index ; + wire \field_encoder.start ; + reg [31:0] fp; + wire [15:0] frame_length; + wire [7:0] frame_opcode; + wire [2047:0] frame_payload; + wire frame_valid; + reg [127:0] inv_value; + wire lane_enable; + wire [7:0] last_fault; + wire [7:0] last_status; + reg [31:0] n_deferred; + reg [31:0] n_writes; + reg [31:0] next_fp_value; + reg [31:0] next_pc_value; + wire parser_rx_ready; + reg [31:0] pc; + reg [7:0] pres_a; + reg [7:0] pres_b; + reg [7:0] pres_c; + reg [7:0] profile; + reg [31:0] proposed_fp; + reg [31:0] proposed_pc; + wire \receiver.abort ; + reg [15:0] \receiver.body_index ; + wire \receiver.busy ; + wire \receiver.clk ; + reg [31:0] \receiver.crc ; + reg [15:0] \receiver.declared_length ; + reg [7:0] \receiver.fault_status ; + reg \receiver.fault_valid ; + reg [7:0] \receiver.flags ; + reg [15:0] \receiver.frame_length ; + reg [7:0] \receiver.frame_opcode ; + reg [2047:0] \receiver.frame_payload ; + wire \receiver.frame_ready ; + reg \receiver.frame_valid ; + reg [2:0] \receiver.header_index ; + reg [7:0] \receiver.opcode ; + wire [31:0] \receiver.received_crc ; + wire \receiver.rst_n ; + wire [7:0] \receiver.rx_data ; + wire \receiver.rx_fire ; + wire \receiver.rx_ready ; + wire \receiver.rx_valid ; + reg [2:0] \receiver.state ; + reg [7:0] \receiver.version ; + reg result_pending; + reg [127:0] result_value; + reg [31:0] retire_seq; + input rst_n; + wire rst_n; + wire rx_busy; + input [7:0] rx_data; + wire [7:0] rx_data; + wire [7:0] rx_fault_status; + wire rx_fault_valid; + output rx_ready; + wire rx_ready; + input rx_valid; + wire rx_valid; + reg [127:0] solved_a; + reg [127:0] solved_b; + reg [31:0] staged_next_fp; + reg [31:0] staged_next_pc; + reg [31:0] staged_result_crc; + reg [31:0] staged_txn_id; + reg state_valid; + wire \transmitter.abort ; + reg \transmitter.active ; + wire \transmitter.busy ; + wire \transmitter.clk ; + reg \transmitter.done_pulse ; + reg [31:0] \transmitter.envelope_crc_work ; + reg [15:0] \transmitter.index ; + wire [543:0] \transmitter.payload ; + reg [31:0] \transmitter.payload_crc ; + reg [31:0] \transmitter.payload_crc_work ; + wire [15:0] \transmitter.payload_length ; + wire \transmitter.rst_n ; + reg [31:0] \transmitter.saved_crc ; + reg [15:0] \transmitter.saved_length ; + reg [543:0] \transmitter.saved_payload ; + reg [7:0] \transmitter.saved_status ; + wire \transmitter.start ; + wire [7:0] \transmitter.status ; + wire [7:0] \transmitter.tx_data ; + wire \transmitter.tx_ready ; + wire \transmitter.tx_valid ; + wire tx_busy; + output [7:0] tx_data; + wire [7:0] tx_data; + wire tx_done; + reg [15:0] tx_length; + reg [543:0] tx_payload; + wire [31:0] tx_payload_crc; + input tx_ready; + wire tx_ready; + reg tx_start; + reg [7:0] tx_status; + output tx_valid; + wire tx_valid; + reg [31:0] txn_id; + reg [127:0] val_a; + reg [127:0] val_b; + reg [127:0] val_c; + reg [31:0] write_address; + reg [127:0] write_value; + assign _0453_ = pc[15:0] + 16'h0002; + assign _0454_ = retire_seq + 1'h1; + assign _0455_ = \receiver.frame_payload [63:32] + 1'h1; + assign _0456_ = \receiver.frame_payload [95:64] + \receiver.frame_payload [143:112]; + assign _0457_ = \receiver.frame_payload [375:344] + \receiver.frame_payload [175:144]; + assign _0458_ = \receiver.frame_payload [95:64] + \receiver.frame_payload [207:176]; + assign _0459_ = \receiver.frame_payload [95:64] + \receiver.frame_payload [175:144]; + always @(posedge clk) + if (_0799_) \field_encoder.fault <= 1'h0; + else if (_0727_) \field_encoder.fault <= 1'h1; + always @(posedge clk) + if (_1067_) \receiver.frame_valid <= 1'h0; + else \receiver.frame_valid <= _1338_; + always @(posedge clk) + if (_1067_) \receiver.frame_opcode <= 8'h00; + else if (_0730_) \receiver.frame_opcode <= \receiver.opcode ; + always @(posedge clk) + if (_1067_) \receiver.frame_length <= 16'h0000; + else if (_0730_) \receiver.frame_length <= \receiver.declared_length ; + always @(posedge clk) + if (_1067_) \receiver.fault_valid <= 1'h0; + else \receiver.fault_valid <= _1330_; + always @(posedge clk) + if (_1067_) \receiver.fault_status <= 8'h00; + else if (_0731_) \receiver.fault_status <= _1316_; + always @(posedge clk) + if (_1067_) \receiver.state <= 3'h0; + else \receiver.state <= _1310_; + always @(posedge clk) + if (_1067_) \receiver.header_index <= 3'h0; + else if (_0732_) \receiver.header_index <= _1300_; + always @(posedge clk) + if (_1067_) \receiver.body_index <= 16'h0000; + else if (_0733_) \receiver.body_index <= _1298_; + always @(posedge clk) + if (_1067_) \receiver.declared_length [7:0] <= 8'h00; + else if (_0734_) \receiver.declared_length [7:0] <= rx_data; + always @(posedge clk) + if (_1067_) \receiver.declared_length [15:8] <= 8'h00; + else if (_0735_) \receiver.declared_length [15:8] <= rx_data; + always @(posedge clk) + if (_1067_) \receiver.version <= 8'h00; + else if (_0736_) \receiver.version <= rx_data; + always @(posedge clk) + if (_1067_) \receiver.opcode <= 8'h00; + else if (_0737_) \receiver.opcode <= rx_data; + always @(posedge clk) + if (_1067_) \receiver.flags <= 8'h00; + else if (_0738_) \receiver.flags <= rx_data; + always @(posedge clk) + if (_1067_) \receiver.crc <= 32'd4294967295; + else if (_0739_) \receiver.crc <= _1293_; + reg [7:0] _2758_; + always @(posedge clk) + if (_1067_) _2758_ <= 8'h00; + else if (_0740_) _2758_ <= _1288_; + assign \receiver.received_crc [7:0] = _2758_; + reg [7:0] _2759_; + always @(posedge clk) + if (_1067_) _2759_ <= 8'h00; + else if (_0741_) _2759_ <= _1284_; + assign \receiver.received_crc [15:8] = _2759_; + reg [7:0] _2760_; + always @(posedge clk) + if (_1067_) _2760_ <= 8'h00; + else if (_0742_) _2760_ <= _1280_; + assign \receiver.received_crc [23:16] = _2760_; + always @(posedge clk) + if (_0799_) \field_encoder.operand_b [127:1] <= 127'h00000000000000000000000000000000; + else if (_0728_) \field_encoder.operand_b [127:1] <= _1089_[127:1]; + always @(posedge clk) + if (_1067_) \field_encoder.operand_b [0] <= 1'h0; + else if (_0729_) \field_encoder.operand_b [0] <= _1081_[0]; + always @(posedge clk) + if (_1067_) \field_encoder.result <= 128'h00000000000000000000000000000000; + else if (_0743_) \field_encoder.result <= _1089_; + always @(posedge clk) + if (_0800_) \adapter.datapath.scratch_byte [0] <= 1'h0; + else if (_0744_) \adapter.datapath.scratch_byte [0] <= _1007_; + always @(posedge clk) + if (_0800_) \adapter.datapath.scratch_byte [7:1] <= 7'h00; + else if (_0745_) \adapter.datapath.scratch_byte [7:1] <= _1001_; + always @(posedge clk) + if (!rst_n) \adapter.datapath.fault <= 1'h0; + else if (_0746_) \adapter.datapath.fault <= _1031_; + always @(posedge clk) + if (_1067_) \field_encoder.multiply_start <= 1'h0; + else \field_encoder.multiply_start <= _1071_; + always @(posedge clk) + if (_0799_) \field_encoder.bit_index [4] <= 1'h0; + else if (_0728_) \field_encoder.bit_index [4] <= _1087_[4]; + always @(posedge clk) + if (_1067_) \field_encoder.bit_index [3:0] <= 4'h0; + else if (_0729_) \field_encoder.bit_index [3:0] <= _1077_[3:0]; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.result_index <= 5'h00; + else if (_0747_) \field_encoder.multiplier.result_index <= _1123_; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.payload_index <= 6'h00; + else if (_0748_) \field_encoder.multiplier.payload_index <= _1131_; + always @(posedge clk) + if (!rst_n) \field_encoder.multiplier.saved_b <= 128'h00000000000000000000000000000000; + else if (_0749_) \field_encoder.multiplier.saved_b <= \field_encoder.operand_b ; + always @(posedge clk) + if (!rst_n) \field_encoder.multiplier.fault <= 1'h0; + else \field_encoder.multiplier.fault <= _1137_; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.done_pulse <= 1'h0; + else \field_encoder.multiplier.done_pulse <= _1117_; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.state <= 3'h0; + else if (_0750_) \field_encoder.multiplier.state <= _1140_; + always @(posedge clk) + if (_1067_) \field_encoder.saved_index <= 16'h0000; + else if (_1063_) \field_encoder.saved_index <= encoder_index; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.datapath.multiplier.impl.a_shift <= 128'h00000000000000000000000000000000; + else if (_0751_) \field_encoder.multiplier.datapath.multiplier.impl.a_shift <= _1229_; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.datapath.multiplier.impl.accumulator <= 128'h00000000000000000000000000000000; + else if (_0752_) \field_encoder.multiplier.datapath.multiplier.impl.accumulator <= _1226_; + always @(posedge clk) + if (!rst_n) \field_encoder.multiplier.datapath.fault <= 1'h0; + else if (_0753_) \field_encoder.multiplier.datapath.fault <= _1201_; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.datapath.scratch_byte [0] <= 1'h0; + else if (_0754_) \field_encoder.multiplier.datapath.scratch_byte [0] <= _1177_; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.datapath.scratch_byte [7:1] <= 7'h00; + else if (_0755_) \field_encoder.multiplier.datapath.scratch_byte [7:1] <= _1171_; + reg [3:0] _2782_; + always @(posedge clk) + if (_0800_) _2782_ <= 4'h0; + else if (_0756_) _2782_ <= { _1874_[6:5], _1874_[3:2] }; + assign { last_fault[6:5], last_fault[3:2] } = _2782_; + reg [3:0] _2783_; + always @(posedge clk) + if (!rst_n) _2783_ <= 4'h0; + else if (_0757_) _2783_ <= { _1875_[7], _1875_[4], _1875_[1:0] }; + assign { last_fault[7], last_fault[4], last_fault[1:0] } = _2783_; + reg [3:0] _2784_; + always @(posedge clk) + if (_0800_) _2784_ <= 4'h0; + else if (_0758_) _2784_ <= { _1923_[6:5], _1923_[3:2] }; + assign { last_status[6:5], last_status[3:2] } = _2784_; + reg [3:0] _2785_; + always @(posedge clk) + if (!rst_n) _2785_ <= 4'h0; + else if (_0759_) _2785_ <= { _1924_[7], _1924_[4], _1924_[1:0] }; + assign { last_status[7], last_status[4], last_status[1:0] } = _2785_; + always @(posedge clk) + if (!rst_n) active_profile <= 8'h01; + else if (_0760_) active_profile <= \receiver.frame_payload [23:16]; + always @(posedge clk) + if (!rst_n) retire_seq <= 32'd0; + else if (_0761_) retire_seq <= _0454_; + always @(posedge clk) + if (!rst_n) committed_fp <= 32'd0; + else if (_0761_) committed_fp <= staged_next_fp; + always @(posedge clk) + if (!rst_n) committed_pc <= 32'd0; + else if (_0761_) committed_pc <= staged_next_pc; + always @(posedge clk) + if (!rst_n) state_valid <= 1'h0; + else if (_0761_) state_valid <= 1'h1; + always @(posedge clk) + if (!rst_n) staged_result_crc <= 32'd0; + else if (!abort) staged_result_crc <= _1963_; + always @(posedge clk) + if (!rst_n) staged_next_fp <= 32'd0; + else if (_0762_) staged_next_fp <= _1999_; + always @(posedge clk) + if (!rst_n) staged_next_pc <= 32'd0; + else if (_0762_) staged_next_pc <= _2035_; + always @(posedge clk) + if (!rst_n) staged_txn_id <= 32'd0; + else if (_0762_) staged_txn_id <= _2073_; + always @(posedge clk) + if (_0800_) result_pending <= 1'h0; + else if (_0763_) result_pending <= _2112_; + always @(posedge clk) + if (!rst_n) encoder_index <= 16'h0000; + else if (_0764_) encoder_index <= _2148_; + always @(posedge clk) + if (_0800_) encoder_start <= 1'h0; + else encoder_start <= _1766_; + always @(posedge clk) + if (!rst_n) alu_operand_b <= 128'h00000000000000000000000000000000; + else if (_0765_) alu_operand_b <= _2187_; + always @(posedge clk) + if (!rst_n) alu_operand_a <= 128'h00000000000000000000000000000000; + else if (_0765_) alu_operand_a <= _2226_; + always @(posedge clk) + if (!rst_n) alu_operation <= 8'h00; + else if (_0765_) alu_operation <= _2265_; + always @(posedge clk) + if (_0801_) alu_start <= 1'h0; + else alu_start <= _1793_; + always @(posedge clk) + if (_0800_) compute_state <= 4'h0; + else if (_0766_) compute_state <= _2319_; + always @(posedge clk) + if (_0800_) capture_result_crc <= 1'h0; + else capture_result_crc <= _2358_; + always @(posedge clk) + if (!rst_n) tx_payload <= 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + else if (_0767_) tx_payload <= _2409_; + always @(posedge clk) + if (!rst_n) tx_length <= 16'h0000; + else if (_0768_) tx_length <= _2459_; + always @(posedge clk) + if (!rst_n) tx_status <= 8'h00; + else if (_0768_) tx_status <= _2468_; + always @(posedge clk) + if (_0800_) tx_start <= 1'h0; + else tx_start <= _1824_; + always @(posedge clk) + if (!rst_n) fault <= 1'h0; + else if (_0759_) fault <= _2519_; + always @(posedge clk) + if (_0802_) done_pulse <= 1'h0; + else done_pulse <= _1734_; + always @(posedge clk) + if (_0800_) \adapter.state <= 3'h0; + else if (_0769_) \adapter.state <= _0966_; + always @(posedge clk) + if (_0800_) \adapter.done_pulse <= 1'h0; + else \adapter.done_pulse <= _0941_; + always @(posedge clk) + if (!rst_n) \adapter.fault <= 1'h0; + else \adapter.fault <= _0963_; + always @(posedge clk) + if (!rst_n) \adapter.saved_operation <= 8'h00; + else if (_0770_) \adapter.saved_operation <= alu_operation; + always @(posedge clk) + if (!rst_n) \adapter.saved_a <= 128'h00000000000000000000000000000000; + else if (_0770_) \adapter.saved_a <= alu_operand_a; + always @(posedge clk) + if (!rst_n) \adapter.saved_b <= 128'h00000000000000000000000000000000; + else if (_0770_) \adapter.saved_b <= alu_operand_b; + always @(posedge clk) + if (_0800_) \adapter.payload_index <= 6'h00; + else if (_0771_) \adapter.payload_index <= _0957_; + always @(posedge clk) + if (_0800_) \adapter.result_index <= 5'h00; + else if (_0772_) \adapter.result_index <= _0949_; + always @(posedge clk) + if (_0800_) \adapter.datapath.multiplier.impl.accumulator <= 128'h00000000000000000000000000000000; + else if (_0773_) \adapter.datapath.multiplier.impl.accumulator <= _1056_; + always @(posedge clk) + if (_0800_) \adapter.datapath.multiplier.impl.a_shift <= 128'h00000000000000000000000000000000; + else if (_0774_) \adapter.datapath.multiplier.impl.a_shift <= _1059_; + always @(posedge clk) + if (_1067_) \field_encoder.busy <= 1'h0; + else if (_0775_) \field_encoder.busy <= _1085_; + always @(posedge clk) + if (_0803_) \field_encoder.done_pulse <= 1'h0; + else \field_encoder.done_pulse <= _1073_; + always @(posedge clk) + if (_0804_) \transmitter.done_pulse <= 1'h0; + else \transmitter.done_pulse <= _1417_; + always @(posedge clk) + if (_1067_) \transmitter.payload_crc <= 32'd0; + else if (_0776_) \transmitter.payload_crc <= _1459_; + always @(posedge clk) + if (_1067_) \transmitter.active <= 1'h0; + else if (_0777_) \transmitter.active <= _1420_; + always @(posedge clk) + if (_0805_) \transmitter.index <= 16'h0000; + else if (_0778_) \transmitter.index <= _1381_; + always @(posedge clk) + if (_1067_) \transmitter.saved_length <= 16'h0000; + else if (_1411_) \transmitter.saved_length <= tx_length; + always @(posedge clk) + if (_1067_) \transmitter.saved_status <= 8'h00; + else if (_1411_) \transmitter.saved_status <= tx_status; + always @(posedge clk) + if (_1067_) \transmitter.saved_payload <= 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + else if (_1411_) \transmitter.saved_payload <= tx_payload; + always @(posedge clk) + if (_0805_) \transmitter.saved_crc <= 32'd0; + else if (_0779_) \transmitter.saved_crc <= _1415_; + always @(posedge clk) + if (_0805_) \transmitter.envelope_crc_work <= 32'd4294967295; + else if (_0780_) \transmitter.envelope_crc_work <= _1450_; + always @(posedge clk) + if (_0805_) \transmitter.payload_crc_work <= 32'd4294967295; + else if (_0781_) \transmitter.payload_crc_work <= _1458_; + reg \field_encoder.multiplier.saved_operation_reg[1] ; + always @(posedge clk) + if (!rst_n) \field_encoder.multiplier.saved_operation_reg[1] <= 1'h0; + else if (_0749_) \field_encoder.multiplier.saved_operation_reg[1] <= 1'h1; + assign \field_encoder.multiplier.saved_operation [1] = \field_encoder.multiplier.saved_operation_reg[1] ; + always @(posedge clk) + if (_1067_) \receiver.frame_payload <= 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + else if (_0782_) \receiver.frame_payload <= _1232_; + always @(posedge clk) + if (_0800_) \adapter.result <= 128'h00000000000000000000000000000000; + else if (_0783_) \adapter.result <= _0903_; + always @(posedge clk) + if (_0784_) n_writes <= _0328_; + always @(posedge clk) + if (_0785_) n_deferred <= _0327_; + always @(posedge clk) + if (_0786_) txn_id <= _0068_; + always @(posedge clk) + if (_0787_) pc <= \receiver.frame_payload [63:32]; + always @(posedge clk) + if (_0787_) fp <= \receiver.frame_payload [95:64]; + always @(posedge clk) + if (_0787_) addr_a <= _0163_; + always @(posedge clk) + if (_0787_) addr_b <= _0164_; + always @(posedge clk) + if (_0787_) addr_c <= _0165_; + always @(posedge clk) + if (_0788_) proposed_pc <= \receiver.frame_payload [655:624]; + always @(posedge clk) + if (_0788_) proposed_fp <= \receiver.frame_payload [687:656]; + always @(posedge clk) + if (_0789_) next_pc_value <= _0422_; + always @(posedge clk) + if (_0789_) next_fp_value <= _0421_; + always @(posedge clk) + if (_0785_) deferred_target <= _0326_; + always @(posedge clk) + if (_0785_) deferred_local <= _0325_; + always @(posedge clk) + if (_0787_) profile <= \receiver.frame_payload [103:96]; + always @(posedge clk) + if (_0790_) pres_a <= _0174_; + always @(posedge clk) + if (_0791_) pres_b <= _0192_; + always @(posedge clk) + if (_0791_) pres_c <= _0193_; + always @(posedge clk) + if (_0790_) val_a <= _0178_; + always @(posedge clk) + if (_0791_) val_b <= _0197_; + always @(posedge clk) + if (_0791_) val_c <= _0198_; + always @(posedge clk) + if (_0792_) inv_value <= _0208_; + always @(posedge clk) + if (_0787_) result_value <= _0175_; + always @(posedge clk) + if (_0793_) solved_a <= _0449_; + always @(posedge clk) + if (_0793_) solved_b <= _0450_; + always @(posedge clk) + if (_0784_) write_address <= _0329_; + always @(posedge clk) + if (_0784_) write_value <= _0330_; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.datapath.byte_index <= 4'h0; + else if (_0794_) \field_encoder.multiplier.datapath.byte_index <= _1184_; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.datapath.state <= 4'h0; + else if (_0795_) \field_encoder.multiplier.datapath.state <= _1203_; + always @(posedge clk) + if (_0800_) \field_encoder.multiplier.result <= 128'h00000000000000000000000000000000; + else if (_0796_) \field_encoder.multiplier.result <= _1093_; + always @(posedge clk) + if (_0800_) \adapter.datapath.state <= 4'h0; + else if (_0797_) \adapter.datapath.state <= _1033_; + always @(posedge clk) + if (_0800_) \adapter.datapath.byte_index <= 4'h0; + else if (_0798_) \adapter.datapath.byte_index <= _1014_; + assign _0460_ = | { _1063_, _1064_ }; + assign _0461_ = { \field_encoder.multiplier.fault , _1062_, _1063_, _1064_ } != 4'h5; + assign _0462_ = { \field_encoder.multiplier.fault , _1063_, _1064_ } != 3'h5; + assign _0463_ = | { _1290_, _1276_, _1275_ }; + assign _0464_ = { _1262_, _1274_, _1275_ } != 3'h1; + assign _0465_ = { _1262_, _1264_, _1265_, _1266_, _1274_, _1275_ } != 6'h03; + assign _0466_ = { _1262_, _1275_ } != 2'h3; + assign _0467_ = { _1269_, _1276_ } != 2'h1; + assign _0468_ = { _1289_, _1290_ } != 2'h1; + assign _0469_ = { _1255_, _1289_, _1290_ } != 3'h3; + assign _0470_ = | { _1290_, _1276_ }; + assign _0471_ = { _1269_, _1276_ } != 2'h3; + assign _0472_ = { _1262_, _1275_ } != 2'h1; + assign _0473_ = | { _1276_, _1275_ }; + assign _0474_ = { _1262_, _1286_, _1275_ } != 3'h1; + assign _0475_ = { _1262_, _1282_, _1275_ } != 3'h1; + assign _0476_ = { _1262_, _1278_, _1275_ } != 3'h1; + assign _0477_ = { _0991_, \adapter.datapath.multiplier.impl.a_last , \adapter.core_rx_fire } != 3'h4; + assign _0478_ = { _1003_, \adapter.core_rx_fire } != 2'h2; + assign _0479_ = { _1005_, \adapter.core_rx_fire } != 2'h2; + assign _0480_ = { _0991_, \adapter.datapath.multiplier.impl.a_last } != 2'h3; + assign _0481_ = | { _1005_, _1003_, _0996_, _0991_, _0987_ }; + assign _0482_ = { \adapter.datapath.mul_tail_last , _0996_ } != 2'h3; + assign _0483_ = | { _1005_, _1003_, _0996_, _0987_ }; + assign _0484_ = { _0993_, \adapter.core_tx_fire } != 2'h2; + assign _0485_ = { _0994_, _0993_, \adapter.core_tx_fire } != 3'h7; + assign _0486_ = { _1020_, \adapter.core_rx_fire } != 2'h2; + assign _0487_ = | { _1020_, _0996_, _0993_, _0992_, _0991_, _0990_, _0989_, _0987_ }; + assign _0488_ = { \adapter.datapath.mul_tail_last , _0996_ } != 2'h1; + assign _0489_ = { _0987_, \adapter.core_rx_fire , _0818_, abort } != 4'he; + assign _0490_ = { _0817_, abort } != 2'h2; + assign _0491_ = { _0987_, \adapter.core_rx_fire , abort } != 3'h4; + assign _0492_ = { _0989_, \adapter.core_tx_fire } != 2'h2; + assign _0493_ = { _0994_, _0993_, \adapter.core_tx_fire } != 3'h3; + assign _0494_ = { _0987_, \adapter.core_rx_fire } != 2'h2; + assign _0495_ = { _1020_, \adapter.datapath.multiplier.impl.a_last , \adapter.core_rx_fire } != 3'h5; + assign _0496_ = { _0991_, \adapter.datapath.multiplier.impl.a_last } != 2'h2; + assign _0497_ = { _1114_, \field_encoder.multiply_start } != 2'h2; + assign _0498_ = { _1103_, \field_encoder.multiplier.core_tx_fire } != 2'h2; + assign _0499_ = { _1105_, _1103_, \field_encoder.multiplier.core_tx_fire } != 3'h7; + assign _0500_ = | { _1114_, _1106_, _1103_ }; + assign _0501_ = { _1106_, \field_encoder.multiplier.core_rx_fire } != 2'h2; + assign _0502_ = { _1108_, \field_encoder.multiplier.core_rx_fire } != 2'h2; + assign _0503_ = { _1104_, _1106_, \field_encoder.multiplier.core_rx_fire } != 3'h7; + assign _0504_ = | { _1114_, _1108_, _1106_ }; + assign _0505_ = { _1105_, _1103_, \field_encoder.multiplier.core_tx_fire } != 3'h3; + assign _0506_ = { _1107_, \field_encoder.multiplier.core_rx_fire } != 2'h2; + assign _0507_ = { _1104_, _1106_, \field_encoder.multiplier.core_rx_fire } != 3'h3; + assign _0508_ = | { \field_encoder.multiplier.datapath.mul_a_valid , \field_encoder.multiplier.datapath.mul_bit_valid }; + assign _0509_ = { \field_encoder.multiplier.datapath.mul_a_valid , \field_encoder.multiplier.datapath.mul_bit_last , \field_encoder.multiplier.datapath.mul_bit_valid } != 3'h3; + assign _0510_ = | { \field_encoder.multiplier.datapath.mul_a_valid , \field_encoder.multiplier.datapath.mul_bit_valid , \field_encoder.multiplier.datapath.mul_result_shift }; + assign _0511_ = { \field_encoder.multiplier.datapath.multiplier.impl.a_last , \field_encoder.multiplier.datapath.mul_a_valid } != 2'h1; + assign _0512_ = { _1159_, \field_encoder.multiplier.core_tx_fire } != 2'h2; + assign _0513_ = { _1163_, \field_encoder.multiplier.core_tx_fire } != 2'h2; + assign _0514_ = { _1164_, _1163_, \field_encoder.multiplier.core_tx_fire } != 3'h3; + assign _0515_ = { _1190_, \field_encoder.multiplier.core_rx_fire } != 2'h2; + assign _0516_ = { _1173_, \field_encoder.multiplier.core_rx_fire } != 2'h2; + assign _0517_ = { _1157_, \field_encoder.multiplier.core_rx_fire } != 2'h2; + assign _0518_ = { _1175_, \field_encoder.multiplier.core_rx_fire } != 2'h2; + assign _0519_ = { \field_encoder.multiplier.datapath.multiplier.impl.a_last , _1190_, \field_encoder.multiplier.core_rx_fire } != 3'h3; + assign _0520_ = { _1166_, \field_encoder.multiplier.datapath.mul_tail_last } != 2'h2; + assign _0521_ = { \field_encoder.multiplier.datapath.multiplier.impl.a_last , _1161_ } != 2'h1; + assign _0522_ = { _1157_, \field_encoder.multiplier.core_rx_fire , _0806_, abort } != 4'he; + assign _0523_ = { _0807_, abort } != 2'h2; + assign _0524_ = { _1157_, \field_encoder.multiplier.core_rx_fire , abort } != 3'h4; + assign _0525_ = { _1164_, _1163_, \field_encoder.multiplier.core_tx_fire } != 3'h7; + assign _0526_ = { \field_encoder.multiplier.datapath.multiplier.impl.a_last , _1161_, \field_encoder.multiplier.core_rx_fire } != 3'h2; + assign _0527_ = | { _1157_, _1166_, _1190_, _1163_, _1162_, _1161_, _1160_, _1159_ }; + assign _0528_ = { \field_encoder.multiplier.datapath.multiplier.impl.a_last , _1161_ } != 2'h3; + assign _0529_ = { _1166_, \field_encoder.multiplier.datapath.mul_tail_last } != 2'h3; + assign _0530_ = | { _1175_, _1157_, _1166_, _1173_, _1161_ }; + assign _0531_ = | { _1175_, _1157_, _1166_, _1173_ }; + assign _0532_ = { \receiver.fault_valid , _0386_, _0227_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 27'h1000800; + assign _0533_ = { \receiver.fault_valid , _0386_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 26'h1000800; + assign _0534_ = { \receiver.fault_valid , _1661_, _1513_, _1476_, _1660_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 19'h12800; + assign _0535_ = { \receiver.fault_valid , _1587_, _1662_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 18'h04801; + assign _0536_ = | { _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ }; + assign _0537_ = { \receiver.fault_valid , _1659_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 14'h0c00; + assign _0538_ = { \adapter.fault , _1493_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 12'h200; + assign _0539_ = { _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 9'h100; + assign _0540_ = { _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 7'h40; + assign _0541_ = { _1586_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 7'h20; + assign _0542_ = { \field_encoder.fault , _1656_, _1505_, _1504_, _1502_, _1501_ } != 6'h08; + assign _0543_ = { \field_encoder.fault , _1655_, _1504_, _1502_, _1501_ } != 5'h04; + assign _0544_ = { \field_encoder.fault , _1503_, _1502_, _1501_ } != 4'h2; + assign _0545_ = { _0871_, _1584_, _1501_ } != 3'h1; + assign _0546_ = { _1496_, _1494_, _0871_, _1584_, _1501_ } != 5'h05; + assign _0547_ = { \receiver.fault_valid , _0386_, _0227_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending, abort } != 28'h2001000; + assign _0548_ = { \receiver.fault_valid , _0386_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending, abort } != 27'h2001000; + assign _0549_ = { \receiver.fault_valid , _1661_, _1513_, _1476_, _1660_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending, abort } != 20'h25000; + assign _0550_ = { \receiver.fault_valid , _1587_, _1662_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending, abort } != 19'h09002; + assign _0551_ = | { _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, abort }; + assign _0552_ = { \receiver.fault_valid , _1659_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, abort } != 15'h1800; + assign _0553_ = { \adapter.fault , _1493_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, abort } != 13'h0400; + assign _0554_ = { _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, abort } != 10'h200; + assign _0555_ = { _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, abort } != 8'h80; + assign _0556_ = { _1586_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, abort } != 8'h40; + assign _0557_ = { \field_encoder.fault , _1656_, _1505_, _1504_, _1502_, _1501_, abort } != 7'h10; + assign _0558_ = { \field_encoder.fault , _1655_, _1504_, _1502_, _1501_, abort } != 6'h08; + assign _0559_ = { \field_encoder.fault , _1503_, _1502_, _1501_, abort } != 5'h04; + assign _0560_ = { _0871_, _1584_, _1501_, abort } != 4'h2; + assign _0561_ = { _1496_, _1494_, _0871_, _1584_, _1501_, abort } != 6'h0a; + assign _0562_ = { \receiver.fault_valid , _0386_, _0227_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 27'h0000800; + assign _0563_ = { \receiver.fault_valid , _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 25'h0000801; + assign _0564_ = { \receiver.fault_valid , _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 24'h400400; + assign _0565_ = { \receiver.fault_valid , _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 23'h200400; + assign _0566_ = { \receiver.fault_valid , _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 22'h100400; + assign _0567_ = { \receiver.fault_valid , _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 21'h080400; + assign _0568_ = { \receiver.fault_valid , _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 20'h40400; + assign _0569_ = { \receiver.fault_valid , _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 19'h20400; + assign _0570_ = { \receiver.fault_valid , _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 18'h10400; + assign _0571_ = { \receiver.fault_valid , _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 17'h08400; + assign _0572_ = { \receiver.fault_valid , _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 16'h4400; + assign _0573_ = { \receiver.fault_valid , _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 15'h2400; + assign _0574_ = { \receiver.fault_valid , _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 14'h1400; + assign _0575_ = { \receiver.fault_valid , _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 13'h0c00; + assign _0576_ = { \receiver.fault_valid , _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 12'hc00; + assign _0577_ = { \adapter.fault , _1493_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 12'h600; + assign _0578_ = { \adapter.fault , _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 11'h600; + assign _0579_ = { _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 8'h80; + assign _0580_ = { _1586_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 7'h60; + assign _0581_ = { _1506_, _1505_, _1504_, _1502_, _1501_ } != 5'h10; + assign _0582_ = { \field_encoder.fault , _1656_, _1505_, _1504_, _1502_, _1501_ } != 6'h18; + assign _0583_ = { \field_encoder.fault , _1505_, _1504_, _1502_, _1501_ } != 5'h18; + assign _0584_ = { _1504_, _1502_, _1501_ } != 3'h4; + assign _0585_ = { \field_encoder.fault , _1503_, _1502_, _1501_ } != 4'h6; + assign _0586_ = { \field_encoder.fault , _1502_, _1501_ } != 3'h6; + assign _0587_ = { _1496_, _1494_, _0871_, _1584_, _1501_ } != 5'h15; + assign _0588_ = { _1494_, _0871_, _1584_, _1501_ } != 4'hd; + assign _0589_ = { _1584_, _1501_ } != 2'h3; + assign _0590_ = { \receiver.fault_valid , _1662_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 16'h6400; + assign _0591_ = { \receiver.fault_valid , _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 27'h0000800; + assign _0592_ = { \receiver.fault_valid , _1613_, _1610_, _1605_, _1604_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 31'h22000800; + assign _0593_ = { \receiver.fault_valid , _1610_, _1605_, _1604_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 30'h12000800; + assign _0594_ = { \receiver.fault_valid , _1605_, _1604_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 29'h0a000800; + assign _0595_ = { \receiver.fault_valid , _1604_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 28'h6000800; + assign _0596_ = { \receiver.fault_valid , _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 26'h1000800; + assign _0597_ = { _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 10'h200; + assign _0598_ = { _1507_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 6'h20; + assign _0599_ = { _1585_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 6'h30; + assign _0600_ = { _1505_, _1504_, _1502_, _1501_ } != 4'h8; + assign _0601_ = { \field_encoder.fault , _1655_, _1504_, _1502_, _1501_ } != 5'h0c; + assign _0602_ = { \field_encoder.fault , _1504_, _1502_, _1501_ } != 4'hc; + assign _0603_ = { _1502_, _1501_ } != 2'h2; + assign _0604_ = { _0871_, _1584_, _1501_ } != 3'h5; + assign _0605_ = { \receiver.fault_valid , _1554_, _1553_, _1552_, _1634_, _1548_, _1568_, _1539_, _1534_, _1532_, _0169_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _0889_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 30'h01880020; + assign _0606_ = { \receiver.fault_valid , _1554_, _1553_, _1552_, _1634_, _1548_, _1539_, _1534_, _1532_, _0169_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _0889_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 29'h01880020; + assign _0607_ = { \receiver.fault_valid , _1713_, _1554_, _1630_, _1695_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1561_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 31'h20408020; + assign _0608_ = { \receiver.fault_valid , _1713_, _1554_, _1630_, _1695_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 30'h14200020; + assign _0609_ = { \receiver.fault_valid , _1713_, _1554_, _1695_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 29'h00200020; + assign _0610_ = { \receiver.fault_valid , _1554_, _1695_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 28'h2200020; + assign _0611_ = { \receiver.fault_valid , _1554_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 27'h0220020; + assign _0612_ = { \receiver.fault_valid , _1554_, _1539_, _1534_, _1532_, _0169_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 24'h000020; + assign _0613_ = { \receiver.fault_valid , _1554_, _1553_, _1552_, _1548_, _1539_, _1534_, _1532_, _0169_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 27'h0040020; + assign _0614_ = { \receiver.fault_valid , _1554_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 26'h0900020; + assign _0615_ = { \receiver.fault_valid , _1554_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 25'h0500020; + assign _0616_ = { \receiver.fault_valid , _1554_, _1617_, _1539_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 24'h300020; + assign _0617_ = { \receiver.fault_valid , _1554_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 22'h080020; + assign _0618_ = { \receiver.fault_valid , _1554_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 21'h040020; + assign _0619_ = { \receiver.fault_valid , _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 19'h00021; + assign _0620_ = { _1509_, _1508_, _1585_ } != 3'h5; + assign _0621_ = | { _1512_, _1511_, _1510_, _1509_, _1508_ }; + assign _0622_ = { \receiver.fault_valid , _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 18'h10010; + assign _0623_ = { \receiver.fault_valid , _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 17'h08010; + assign _0624_ = { \receiver.fault_valid , _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 16'h4010; + assign _0625_ = { \receiver.fault_valid , _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 15'h2010; + assign _0626_ = { \receiver.fault_valid , _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 14'h1010; + assign _0627_ = { \receiver.fault_valid , _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 13'h0810; + assign _0628_ = { \receiver.fault_valid , _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 12'h410; + assign _0629_ = { \receiver.fault_valid , _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 11'h210; + assign _0630_ = { \receiver.fault_valid , _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 10'h110; + assign _0631_ = { \receiver.fault_valid , _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 9'h090; + assign _0632_ = { \receiver.fault_valid , _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 8'h50; + assign _0633_ = { \receiver.fault_valid , _0885_, _1512_, _1511_, _1510_, _1509_, _1508_ } != 7'h30; + assign _0634_ = { \receiver.fault_valid , _1512_, _1511_, _1510_, _1509_, _1508_ } != 6'h30; + assign _0635_ = { _1511_, _1510_, _1509_, _1508_ } != 4'h8; + assign _0636_ = { \receiver.fault_valid , _1554_, _1553_, _1552_, _1634_, _1548_, _1568_, _1539_, _1534_, _1532_, _0169_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _0889_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 36'h062000800; + assign _0637_ = { \receiver.fault_valid , _1554_, _1553_, _1552_, _1634_, _1548_, _1539_, _1534_, _1532_, _0169_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _0889_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 35'h062000800; + assign _0638_ = { \receiver.fault_valid , _1713_, _1554_, _1630_, _1695_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1561_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 37'h0810200800; + assign _0639_ = { \receiver.fault_valid , _1713_, _1554_, _1630_, _1695_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 36'h508000800; + assign _0640_ = { \receiver.fault_valid , _1713_, _1554_, _1695_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 35'h008000800; + assign _0641_ = { \receiver.fault_valid , _1554_, _1695_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 34'h088000800; + assign _0642_ = { \receiver.fault_valid , _1554_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1475_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 33'h008800800; + assign _0643_ = { \receiver.fault_valid , _1554_, _1539_, _1534_, _1532_, _0169_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 30'h00000800; + assign _0644_ = { \receiver.fault_valid , _1554_, _1553_, _1552_, _1548_, _1539_, _1534_, _1532_, _0169_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 33'h001000800; + assign _0645_ = { \receiver.fault_valid , _1554_, _1627_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 32'd603981824; + assign _0646_ = { \receiver.fault_valid , _1554_, _1624_, _1617_, _1539_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 31'h14000800; + assign _0647_ = { \receiver.fault_valid , _1554_, _1617_, _1539_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 30'h0c000800; + assign _0648_ = { \receiver.fault_valid , _1554_, _1613_, _1610_, _1605_, _1604_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 32'd570427392; + assign _0649_ = { \receiver.fault_valid , _1554_, _1610_, _1605_, _1604_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 31'h12000800; + assign _0650_ = { \receiver.fault_valid , _1554_, _1605_, _1604_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 30'h0a000800; + assign _0651_ = { \receiver.fault_valid , _1554_, _1604_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 29'h06000800; + assign _0652_ = { \receiver.fault_valid , _1554_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, result_pending } != 27'h1000800; + assign _0653_ = { _1509_, _1508_, _1507_, _1585_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 9'h100; + assign _0654_ = { _1585_, _1506_, _1505_, _1504_, _1502_, _1501_ } != 6'h10; + assign _0655_ = { _0938_, alu_start } != 2'h2; + assign _0656_ = { _0915_, \adapter.core_tx_fire } != 2'h2; + assign _0657_ = { _0923_, _0915_, \adapter.core_tx_fire } != 3'h3; + assign _0658_ = { _0925_, \adapter.core_rx_fire } != 2'h2; + assign _0659_ = { _0926_, \adapter.core_rx_fire } != 2'h2; + assign _0660_ = { _0924_, \adapter.core_rx_fire } != 2'h2; + assign _0661_ = { _0932_, _0924_, \adapter.core_rx_fire } != 3'h3; + assign _0662_ = { _0932_, _0924_, \adapter.core_rx_fire } != 3'h7; + assign _0663_ = | { _0924_, _0926_, _0938_ }; + assign _0664_ = { _0923_, _0915_, \adapter.core_tx_fire } != 3'h7; + assign _0665_ = | { _0915_, _0924_, _0938_ }; + assign _0666_ = { \adapter.datapath.mul_a_valid , \adapter.datapath.multiplier.impl.a_last } != 2'h2; + assign _0667_ = | { \adapter.datapath.mul_result_shift , \adapter.datapath.mul_bit_valid , \adapter.datapath.mul_a_valid }; + assign _0668_ = { \adapter.datapath.mul_bit_valid , \adapter.datapath.mul_bit_last , \adapter.datapath.mul_a_valid } != 3'h6; + assign _0669_ = | { \adapter.datapath.mul_bit_valid , \adapter.datapath.mul_a_valid }; + assign _0670_ = { \field_encoder.multiplier.fault , _1062_, _1063_, _1064_ } != 4'h1; + assign _0671_ = | { _1411_, _1412_ }; + assign _0672_ = { _1408_, _1411_, _1412_ } != 3'h1; + assign _0673_ = { _1262_, _1263_, _1275_ } != 3'h5; + assign _0674_ = { _0819_, \adapter.core_tx_fire } != 2'h2; + assign _0675_ = | { _0819_, _0938_ }; + assign _0676_ = { _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, result_pending } != 11'h001; + assign _0677_ = { _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_ } != 10'h200; + assign _0678_ = { _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_ } != 9'h100; + assign _0679_ = { _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_ } != 8'h80; + assign _0680_ = { _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_ } != 7'h40; + assign _0681_ = { _1525_, _1677_, _1477_, _1591_, _1519_, _0887_ } != 6'h20; + assign _0682_ = { _1677_, _1477_, _1591_, _1519_, _0887_ } != 5'h10; + assign _0683_ = { _1477_, _1591_, _1519_, _0887_ } != 4'h8; + assign _0684_ = { _1591_, _1519_, _0887_ } != 3'h4; + assign _0685_ = { _1519_, _0887_ } != 2'h2; + assign _0686_ = { \receiver.fault_valid , _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, result_pending } != 22'h000101; + assign _0687_ = | { _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ }; + assign _0688_ = { \receiver.fault_valid , _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 21'h080080; + assign _0689_ = { \receiver.fault_valid , _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 20'h40080; + assign _0690_ = { \receiver.fault_valid , _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 19'h20080; + assign _0691_ = { \receiver.fault_valid , _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 18'h10080; + assign _0692_ = { \receiver.fault_valid , _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 17'h08080; + assign _0693_ = { \receiver.fault_valid , _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 16'h4080; + assign _0694_ = { \receiver.fault_valid , _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 15'h2080; + assign _0695_ = { \receiver.fault_valid , _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 14'h1080; + assign _0696_ = { \receiver.fault_valid , _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 13'h0880; + assign _0697_ = { \receiver.fault_valid , _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 12'h480; + assign _0698_ = { \receiver.fault_valid , _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 11'h280; + assign _0699_ = { \receiver.fault_valid , _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 10'h180; + assign _0700_ = { \receiver.fault_valid , _1512_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 9'h180; + assign _0701_ = { _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 7'h40; + assign _0702_ = { _1510_, _1509_, _1508_, _1507_, _1506_, _1505_ } != 6'h20; + assign _0703_ = { _1509_, _1508_, _1507_, _1506_, _1505_ } != 5'h10; + assign _0704_ = { _1508_, _1507_, _1506_, _1505_ } != 4'h8; + assign _0705_ = { _1507_, _1506_, _1505_ } != 3'h4; + assign _0706_ = { _1506_, _1505_ } != 2'h2; + assign _0707_ = { \field_encoder.fault , _1656_, _1505_ } != 3'h3; + assign _0708_ = { \field_encoder.fault , _1505_ } != 2'h3; + assign _0709_ = | { _1539_, _1534_, _1532_, _0169_ }; + assign _0710_ = | { _1539_, _1534_, _0169_ }; + assign _0711_ = | { _1539_, _0169_ }; + assign _0712_ = { \receiver.fault_valid , _1539_, _1534_, _1532_, _0169_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 23'h000020; + assign _0713_ = { \receiver.fault_valid , _1539_, _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 22'h100020; + assign _0714_ = { \receiver.fault_valid , _1534_, _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 21'h080020; + assign _0715_ = { \receiver.fault_valid , _1532_, _1529_, _1528_, _1527_, _1526_, _1525_, _1677_, _1477_, _1591_, _1519_, _0887_, _0886_, _0885_, _1512_, _1511_, _1510_, _1509_, _1508_, result_pending } != 20'h40020; + assign _0716_ = { _1509_, _1508_ } != 2'h2; + assign _0717_ = { \field_encoder.multiplier.core_tx_fire , \field_encoder.multiplier.datapath.multiplier.impl.a_last , _0823_ } != 3'h7; + assign _0718_ = { \field_encoder.multiplier.core_tx_fire , _0823_ } != 2'h1; + assign _0719_ = { \field_encoder.multiplier.core_tx_fire , _0824_, \field_encoder.multiplier.datapath.multiplier.impl.a_last } != 3'h6; + assign _0720_ = { \field_encoder.multiplier.core_tx_fire , _0824_ } != 2'h1; + assign _0721_ = | { _1114_, _0822_ }; + assign _0722_ = { \field_encoder.multiplier.core_tx_fire , _0822_ } != 2'h1; + assign _0723_ = { _0821_, \adapter.core_tx_fire } != 2'h2; + assign _0724_ = { _0821_, \adapter.datapath.multiplier.impl.a_last , \adapter.core_tx_fire } != 3'h5; + assign _0725_ = { _0820_, \adapter.core_tx_fire } != 2'h2; + assign _0726_ = { _0820_, \adapter.datapath.multiplier.impl.a_last , \adapter.core_tx_fire } != 3'h7; + assign _0825_ = ~ \field_encoder.multiplier.fault ; + assign _0826_ = ~ _1062_; + assign _0827_ = ~ _1266_; + assign _0828_ = ~ _1265_; + assign _0829_ = ~ _1264_; + assign _0830_ = ~ _1262_; + assign _0831_ = ~ _1063_; + assign _0833_ = ~ abort; + assign _0834_ = ~ \receiver.fault_valid ; + assign _0835_ = ~ result_pending; + assign _0836_ = ~ _1501_; + assign _0837_ = ~ _1502_; + assign _0838_ = ~ _1504_; + assign _0839_ = ~ _1505_; + assign _0840_ = ~ _1506_; + assign _0841_ = ~ _1507_; + assign _0842_ = ~ _1508_; + assign _0843_ = ~ _1509_; + assign _0844_ = ~ _1510_; + assign _0845_ = ~ _1511_; + assign _0846_ = ~ _0885_; + assign _0847_ = ~ _1660_; + assign _0848_ = ~ _1476_; + assign _0849_ = ~ _1661_; + assign _0850_ = ~ _0886_; + assign _0851_ = ~ _1662_; + assign _0852_ = ~ _1587_; + assign _0857_ = ~ _1411_; + assign _0858_ = ~ _1408_; + assign _0854_ = ~ _0887_; + assign _0859_ = ~ _1519_; + assign _0860_ = ~ _1591_; + assign _0861_ = ~ _1477_; + assign _0862_ = ~ _1677_; + assign _0863_ = ~ _1525_; + assign _0864_ = ~ _1526_; + assign _0865_ = ~ _1527_; + assign _0866_ = ~ _1528_; + assign _0867_ = ~ _1529_; + assign _0868_ = ~ _1532_; + assign _0869_ = ~ _1534_; + assign _0727_ = & { \field_encoder.multiplier.fault , _1064_ }; + assign _0728_ = & { _0826_, _0825_, _1064_ }; + assign _0729_ = & { _0461_, _0462_, _0460_ }; + assign _0730_ = & { _0829_, _0827_, _0830_, _1274_, _1275_, \receiver.rx_fire , _0828_ }; + assign _0731_ = & { \receiver.rx_fire , _0463_, _0467_, _0468_, _0469_, _0464_, _0465_, _0466_ }; + assign _0732_ = & { \receiver.rx_fire , _0470_, _0471_ }; + assign _0733_ = & { \receiver.rx_fire , _0463_, _0468_ }; + assign _0734_ = & { _1290_, _1291_, \receiver.rx_fire }; + assign _0735_ = & { _1289_, _1290_, \receiver.rx_fire }; + assign _0736_ = & { _1290_, _1297_, \receiver.rx_fire }; + assign _0737_ = & { _1290_, _1296_, \receiver.rx_fire }; + assign _0738_ = & { _1290_, _1295_, \receiver.rx_fire }; + assign _0739_ = & { \receiver.rx_fire , _0463_, _0471_, _0472_ }; + assign _0740_ = & { \receiver.rx_fire , _0473_, _0474_, _0466_ }; + assign _0741_ = & { \receiver.rx_fire , _0473_, _0475_, _0466_ }; + assign _0742_ = & { \receiver.rx_fire , _0473_, _0476_, _0466_ }; + assign _0743_ = & { _0825_, _1062_, _1064_, _0831_ }; + assign _0744_ = & { _0477_, _0478_, _0479_, _0480_, _0481_, _0482_ }; + assign _0745_ = & { _0478_, _0479_, _0482_, _0483_ }; + assign _0746_ = & { _0489_, _0490_, _0491_ }; + assign _0747_ = & { _0498_, _0499_, _0500_, _0497_ }; + assign _0748_ = & { _0501_, _0502_, _0504_, _0497_, _0503_ }; + assign _0749_ = & { _1114_, \field_encoder.multiply_start , _0833_ }; + assign _0750_ = & { _0498_, _0501_, _0502_, _0505_, _0506_, _0507_, _0497_ }; + assign _0751_ = & { _0508_, _0509_ }; + assign _0752_ = & { _0510_, _0511_ }; + assign _0753_ = & { _0522_, _0523_, _0524_ }; + assign _0754_ = & { _0516_, _0518_, _0526_, _0529_, _0530_, _0528_ }; + assign _0755_ = & { _0516_, _0518_, _0529_, _0531_ }; + assign _0756_ = & { _0532_, _0534_, _0535_, _0536_, _0537_, _0539_, _0540_, _0541_, _0542_, _0544_, _0545_, _0546_, _0533_, _0538_, _0543_ }; + assign _0757_ = & { _0547_, _0548_, _0549_, _0550_, _0551_, _0552_, _0553_, _0554_, _0555_, _0557_, _0558_, _0559_, _0560_, _0556_, _0561_ }; + assign _0758_ = & { _0536_, _0539_, _0540_, _0545_, _0533_, _0543_ }; + assign _0759_ = & { _0548_, _0551_, _0554_, _0555_, _0558_, _0560_ }; + assign _0760_ = & { _0833_, _0834_, _0835_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0842_, _0843_, _0844_, _0845_, _0846_, _0847_, _0848_, _0849_, _1513_, _0886_, _1512_ }; + assign _0761_ = & { _0833_, _0834_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0842_, _0843_, _0844_, _0845_, _0846_, _0850_, _0851_, _0852_, _0887_, _1512_, result_pending }; + assign _0762_ = & { _0833_, _0536_, _0539_, _0540_, _0545_, _0562_, _0563_, _0564_, _0565_, _0566_, _0567_, _0568_, _0569_, _0570_, _0571_, _0572_, _0573_, _0574_, _0575_, _0576_, _0577_, _0578_, _0579_, _0580_, _0581_, _0582_, _0583_, _0584_, _0585_, _0586_, _0587_, _0588_, _0589_, _0533_ }; + assign _0763_ = & { _0536_, _0539_, _0540_, _0545_, _0564_, _0565_, _0566_, _0567_, _0568_, _0569_, _0570_, _0571_, _0572_, _0574_, _0575_, _0576_, _0577_, _0578_, _0579_, _0580_, _0581_, _0582_, _0583_, _0584_, _0585_, _0586_, _0587_, _0588_, _0589_, _0590_ }; + assign _0764_ = & { _0833_, _0536_, _0539_, _0540_, _0563_, _0564_, _0565_, _0566_, _0567_, _0568_, _0569_, _0570_, _0571_, _0572_, _0573_, _0574_, _0575_, _0576_, _0579_, _0589_, _0591_, _0592_, _0593_, _0594_, _0595_, _0597_, _0596_, _0598_, _0599_, _0600_, _0601_, _0602_, _0603_, _0604_ }; + assign _0765_ = & { _0833_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0605_, _0606_, _0607_, _0608_, _0609_, _0610_, _0611_, _0612_, _0613_, _0614_, _0615_, _0616_, _0617_, _0618_, _0619_, _0620_, _0621_, _0622_, _0623_, _0624_, _0625_, _0626_, _0627_, _0628_, _0629_, _0630_, _0631_, _0632_, _0633_, _0634_, _0635_ }; + assign _0766_ = & { _0536_, _0563_, _0564_, _0565_, _0566_, _0567_, _0568_, _0569_, _0570_, _0571_, _0572_, _0573_, _0574_, _0575_, _0576_, _0636_, _0637_, _0638_, _0640_, _0641_, _0642_, _0643_, _0645_, _0646_, _0647_, _0648_, _0650_, _0651_, _0652_, _0639_, _0644_, _0649_ }; + assign _0767_ = & { _0833_, _0536_, _0539_, _0540_, _0545_, _0653_, _0654_, _0533_, _0543_ }; + assign _0768_ = & { _0833_, _0536_, _0539_, _0540_, _0545_, _0533_, _0543_ }; + assign _0769_ = & { _0655_, _0656_, _0657_, _0660_, _0661_, _0658_, _0659_ }; + assign _0770_ = & { _0938_, _0833_, alu_start }; + assign _0771_ = & { _0655_, _0660_, _0662_, _0663_, _0659_ }; + assign _0772_ = & { _0655_, _0656_, _0664_, _0665_ }; + assign _0773_ = & { _0666_, _0667_ }; + assign _0774_ = & { _0668_, _0669_ }; + assign _0775_ = & { _0460_, _0670_ }; + assign _0776_ = & { _0857_, _1406_, _1410_, _1412_ }; + assign _0777_ = & { _0671_, _0672_ }; + assign _0778_ = & { _0858_, _1412_ }; + assign _0779_ = & { _1406_, _1410_, _1412_ }; + assign _0780_ = & { _1410_, _1412_ }; + assign _0781_ = & { _1409_, _1410_, _1412_ }; + assign _0782_ = & { \receiver.rx_fire , _0673_, _0473_, _0472_ }; + assign _0783_ = & { _0674_, _0675_, _0655_ }; + assign _0784_ = & { _0833_, _0536_, _0545_, _0563_, _0564_, _0565_, _0566_, _0567_, _0568_, _0569_, _0570_, _0571_, _0572_, _0573_, _0574_, _0575_, _0576_, _0577_, _0578_, _0579_, _0581_, _0584_, _0585_, _0586_, _0587_, _0588_, _0589_, _0598_, _0600_, rst_n }; + assign _0785_ = & { _0833_, _0536_, _0539_, _0540_, _0545_, _0563_, _0564_, _0565_, _0566_, _0567_, _0568_, _0569_, _0570_, _0571_, _0572_, _0573_, _0574_, _0575_, _0576_, _0579_, _0581_, _0584_, _0587_, _0588_, _0589_, _0597_, _0598_, _0600_, _0603_, rst_n }; + assign _0786_ = & { _0833_, _0685_, _0684_, _0683_, _0682_, _0681_, _0680_, _0679_, _0678_, _0677_, _0676_, _0834_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0842_, _0843_, _0844_, _0845_, _0846_, _0850_, _1512_, rst_n }; + assign _0787_ = & { _0833_, _0867_, _0866_, _0865_, _0864_, _0862_, _0861_, _0860_, _0859_, _0834_, _0835_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0842_, _0843_, _0844_, _0845_, _0846_, _0850_, _0863_, _0854_, _1512_, rst_n }; + assign _0788_ = & { _0869_, _0868_, _0833_, _0867_, _0866_, _0865_, _0864_, _0862_, _0861_, _0860_, _0859_, _0834_, _0835_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0842_, _0843_, _0844_, _0845_, _0846_, _0850_, _0863_, _0854_, _1539_, _1512_, rst_n }; + assign _0789_ = & { _0708_, _0707_, _0706_, _0705_, _0704_, _0703_, _0702_, _0701_, _0700_, _0699_, _0698_, _0697_, _0696_, _0695_, _0694_, _0693_, _0692_, _0691_, _0690_, _0689_, _0688_, _0687_, _0686_, _0833_, _0836_, _0837_, _0838_, rst_n }; + assign _0790_ = & { _0709_, _0833_, _0867_, _0866_, _0865_, _0864_, _0862_, _0861_, _0860_, _0859_, _0834_, _0835_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0842_, _0843_, _0844_, _0845_, _0846_, _0850_, _0863_, _0854_, _1512_, rst_n }; + assign _0791_ = & { _0710_, _0868_, _0833_, _0867_, _0866_, _0865_, _0864_, _0862_, _0861_, _0860_, _0859_, _0834_, _0835_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0842_, _0843_, _0844_, _0845_, _0846_, _0850_, _0863_, _0854_, _1512_, rst_n }; + assign _0792_ = & { _0711_, _0869_, _0868_, _0833_, _0867_, _0866_, _0865_, _0864_, _0862_, _0861_, _0860_, _0859_, _0834_, _0835_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0842_, _0843_, _0844_, _0845_, _0846_, _0850_, _0863_, _0854_, _1512_, rst_n }; + assign _0793_ = & { _0833_, _0836_, _0837_, _0838_, _0839_, _0840_, _0841_, _0619_, _0621_, _0622_, _0623_, _0624_, _0625_, _0626_, _0627_, _0628_, _0629_, _0630_, _0631_, _0632_, _0633_, _0634_, _0635_, _0716_, _0713_, _0714_, _0715_, _0712_, rst_n }; + assign _0794_ = & { _0513_, _0515_, _0520_, _0525_, _0526_, _0527_, _0718_, _0717_, _0528_ }; + assign _0795_ = & { _0512_, _0513_, _0514_, _0515_, _0516_, _0517_, _0518_, _0519_, _0520_, _0521_, _0720_, _0719_ }; + assign _0796_ = & { _0722_, _0721_, _0497_ }; + assign _0797_ = & { _0478_, _0479_, _0484_, _0486_, _0492_, _0494_, _0495_, _0496_, _0724_, _0723_, _0488_, _0493_ }; + assign _0798_ = & { _0477_, _0480_, _0484_, _0485_, _0486_, _0726_, _0725_, _0487_, _0488_ }; + assign _0832_ = ~ rst_n; + assign _0853_ = ~ _1512_; + assign _0855_ = ~ _1064_; + assign _0856_ = ~ _1412_; + assign _0799_ = | { _1063_, _1067_ }; + assign _0800_ = | { _0832_, abort }; + assign _0801_ = | { _0832_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, abort }; + assign _0802_ = | { \receiver.fault_valid , _0832_, _0853_, _0835_, _0854_, _1662_, _0886_, _0885_, _1511_, _1510_, _1509_, _1508_, _1507_, _1506_, _1505_, _1504_, _1502_, _1501_, abort }; + assign _0803_ = | { _1063_, _1067_, _0855_ }; + assign _0804_ = | { _1067_, _0856_, _1411_ }; + assign _0805_ = | { _1067_, _1411_ }; + assign _0806_ = | { _1195_, _1196_, _1197_, _1198_, _1199_ }; + assign _0807_ = | { _1166_, _1159_, _1173_, _1175_, _1190_, _1160_, _1161_, _1162_, _1163_, _1165_ }; + assign _0808_ = | { _1051_, _1050_ }; + assign _0809_ = | { _1162_, _1163_, _1165_ }; + assign _0811_ = | { _1020_, _1005_, _1003_, _0987_ }; + assign _0813_ = | { _0995_, _0993_, _0992_ }; + assign _0812_ = | { _0990_, _0989_ }; + assign _0814_ = | { _1157_, _1173_, _1175_, _1190_ }; + assign _0810_ = | { _1159_, _1160_ }; + assign _0815_ = | { _1220_, _1221_ }; + assign _0816_ = | { _1291_, _1295_, _1296_, _1297_ }; + assign _0817_ = | { _1020_, _1005_, _1003_, _0996_, _0995_, _0993_, _0992_, _0991_, _0990_, _0989_ }; + assign _0818_ = | { _1029_, _1028_, _1027_, _1026_, _1025_ }; + assign _0819_ = | { _0915_, _0924_ }; + assign _0820_ = | { _0992_, _0990_, _0989_ }; + assign _0821_ = | { _0992_, _0990_ }; + assign _0822_ = | { _1106_, _1103_ }; + assign _0823_ = | { _1159_, _1160_, _1162_ }; + assign _0824_ = | { _1160_, _1162_ }; + assign _0870_ = _0416_[15:8] == 8'h03; + assign _0871_ = \receiver.frame_opcode == 8'h04; + assign _0872_ = ! profile; + assign _0873_ = \receiver.frame_opcode == 8'h05; + assign _0874_ = compute_state == 4'h6; + assign _0875_ = compute_state == 4'h7; + assign _0876_ = compute_state == 4'h9; + assign _0877_ = compute_state == 4'ha; + assign _0878_ = compute_state == 4'h8; + assign _0879_ = compute_state == 4'h4; + assign _0880_ = compute_state == 4'h5; + assign _0881_ = compute_state == 4'h1; + assign _0882_ = compute_state == 4'h2; + assign _0883_ = compute_state == 4'h3; + assign _0884_ = \receiver.fault_status == 8'h83; + assign _0885_ = \receiver.frame_opcode == 8'h13; + assign _0886_ = \receiver.frame_opcode == 8'h10; + assign _0887_ = \receiver.frame_opcode == 8'h12; + assign _0888_ = \receiver.frame_opcode == 8'h03; + assign _0889_ = \receiver.frame_opcode == 8'h01; + assign _0890_ = \receiver.frame_opcode == 8'h02; + assign _0891_ = \receiver.frame_opcode == 8'h06; + assign _0892_ = \receiver.frame_opcode == 8'h07; + assign _0893_ = _0456_ == _0457_; + assign _0894_ = _0456_ == _0458_; + assign _0895_ = _0457_ == _0458_; + assign _0896_ = _0456_ == _0459_; + assign _0897_ = _0459_ == _0458_; + assign _0898_ = ! compute_state; + assign _0899_ = ! \receiver.frame_payload [479:352]; + assign _0900_ = ! \receiver.frame_payload [343:216]; + assign _0913_ = \adapter.payload_index + 1'h1; + assign _0912_ = \adapter.result_index + 1'h1; + assign _0914_ = \adapter.result & _0936_; + assign _0916_ = alu_operation == 8'h01; + assign _0917_ = alu_operation == 8'h02; + assign _0918_ = alu_operation == 8'h03; + assign _0920_ = \adapter.payload_index == 6'h0f; + assign _0921_ = \adapter.payload_index == 6'h1f; + assign _0922_ = \adapter.saved_operation == 8'h02; + assign _0923_ = \adapter.result_index == 5'h0f; + assign _0927_ = _0915_ && \adapter.datapath.fault ; + assign _0928_ = _0919_ && _0920_; + assign _0929_ = _0934_ && _0921_; + assign \adapter.core_rx_fire = \adapter.core_rx_valid && \adapter.core_rx_ready ; + assign \adapter.core_tx_fire = \adapter.core_tx_valid && \adapter.core_tx_ready ; + assign _0930_ = _0916_ || _0917_; + assign _0931_ = _0930_ || _0918_; + assign _0932_ = _0928_ || _0929_; + assign \adapter.core_tx_ready = _0924_ || _0915_; + assign _0933_ = \adapter.payload_index < 32'd16; + assign _0934_ = \adapter.saved_operation != 8'h03; + assign \adapter.busy = | \adapter.state ; + assign _0935_ = - $signed({ 25'h0000000, \adapter.result_index , 3'h0 }); + assign _0936_ = ~ _0975_; + assign _0937_ = _0914_ | _0976_; + assign _0908_ = \adapter.core_tx_fire ? _0937_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _0906_ = alu_start ? 128'h00000000000000000000000000000000 : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + function [127:0] _3335_; + input [127:0] a; + input [255:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3335_ = b[127:0]; + 2'b1?: + _3335_ = b[255:128]; + default: + _3335_ = a; + endcase + endfunction + assign _0903_ = _3335_(128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _0906_, _0908_ }, { _0938_, _0819_ }); + assign _0939_ = _0923_ ? 1'h1 : 1'h0; + assign _0940_ = \adapter.core_tx_fire ? _0939_ : 1'h0; + function [0:0] _3338_; + input [0:0] a; + input [2:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3338_ = b[0:0]; + 3'b?1?: + _3338_ = b[1:1]; + 3'b1??: + _3338_ = b[2:2]; + default: + _3338_ = a; + endcase + endfunction + assign _0941_ = _3338_(1'h0, { _0946_, _0944_, _0940_ }, { _0938_, _0924_, _0915_ }); + assign _0942_ = _0922_ ? 1'h0 : 1'h1; + assign _0943_ = _0932_ ? _0942_ : 1'h0; + assign _0944_ = \adapter.core_rx_fire ? _0943_ : 1'h0; + assign _0945_ = _0931_ ? 1'h0 : 1'h1; + assign _0946_ = alu_start ? _0945_ : 1'h0; + assign _0947_ = _0923_ ? 5'hxx : _0912_; + assign _0948_ = \adapter.core_tx_fire ? _0947_ : 5'hxx; + function [4:0] _3346_; + input [4:0] a; + input [14:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3346_ = b[4:0]; + 3'b?1?: + _3346_ = b[9:5]; + 3'b1??: + _3346_ = b[14:10]; + default: + _3346_ = a; + endcase + endfunction + assign _0949_ = _3346_(5'hxx, { _0954_, _0953_, _0948_ }, { _0938_, _0924_, _0915_ }); + assign _0950_ = \adapter.core_tx_fire ? _0912_ : \adapter.result_index ; + assign _0951_ = _0922_ ? 5'h00 : _0950_; + assign _0952_ = _0932_ ? _0951_ : _0950_; + assign _0953_ = \adapter.core_rx_fire ? _0952_ : _0950_; + assign _0954_ = alu_start ? 5'h00 : 5'hxx; + assign _0955_ = _0932_ ? 6'hxx : _0913_; + assign _0956_ = \adapter.core_rx_fire ? _0955_ : 6'hxx; + function [5:0] _3354_; + input [5:0] a; + input [17:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3354_ = b[5:0]; + 3'b?1?: + _3354_ = b[11:6]; + 3'b1??: + _3354_ = b[17:12]; + default: + _3354_ = a; + endcase + endfunction + assign _0957_ = _3354_(6'hxx, { _0959_, _0958_, _0956_ }, { _0938_, _0926_, _0924_ }); + assign _0958_ = \adapter.core_rx_fire ? 6'h00 : 6'hxx; + assign _0959_ = alu_start ? 6'h00 : 6'hxx; + assign _0960_ = _0927_ ? 1'h1 : \adapter.fault ; + assign _0961_ = alu_start ? _0945_ : _0960_; + assign _0962_ = _0938_ ? _0961_ : _0960_; + assign _0963_ = abort ? 1'h1 : _0962_; + assign _0964_ = _0923_ ? 3'h0 : 3'hx; + assign _0965_ = \adapter.core_tx_fire ? _0964_ : 3'hx; + function [2:0] _3363_; + input [2:0] a; + input [14:0] b; + input [4:0] s; + casez (s) // synopsys parallel_case + 5'b????1: + _3363_ = b[2:0]; + 5'b???1?: + _3363_ = b[5:3]; + 5'b??1??: + _3363_ = b[8:6]; + 5'b?1???: + _3363_ = b[11:9]; + 5'b1????: + _3363_ = b[14:12]; + default: + _3363_ = a; + endcase + endfunction + assign _0966_ = _3363_(3'h0, { _0973_, _0971_, _0970_, _0969_, _0965_ }, { _0938_, _0925_, _0926_, _0924_, _0915_ }); + assign _0915_ = \adapter.state == 3'h4; + assign _0967_ = _0922_ ? 3'h4 : 3'h0; + assign _0968_ = _0932_ ? _0967_ : 3'hx; + assign _0969_ = \adapter.core_rx_fire ? _0968_ : 3'hx; + assign _0924_ = \adapter.state == 3'h3; + assign _0970_ = \adapter.core_rx_fire ? 3'h3 : 3'hx; + assign _0926_ = \adapter.state == 3'h2; + assign _0971_ = \adapter.core_rx_fire ? 3'h2 : 3'hx; + assign _0925_ = \adapter.state == 3'h1; + assign _0972_ = _0931_ ? 3'h1 : 3'h0; + assign _0973_ = alu_start ? _0972_ : 3'hx; + assign _0938_ = ! \adapter.state ; + assign _0910_ = _0933_ ? _0977_ : _0980_; + assign _0909_ = \adapter.payload_index [0] ? _0979_ : _0978_; + function [7:0] _3378_; + input [7:0] a; + input [15:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3378_ = b[7:0]; + 2'b1?: + _3378_ = b[15:8]; + default: + _3378_ = a; + endcase + endfunction + assign _0907_ = _3378_(_0910_, { _0977_, _0909_ }, { _0919_, _0974_ }); + assign _0974_ = \adapter.saved_operation == 8'h01; + assign _0919_ = \adapter.saved_operation == 8'h03; + assign _0904_ = _0924_ ? _0907_ : 8'h00; + assign _0905_ = _0924_ ? 1'h1 : 1'h0; + assign _0901_ = _0926_ ? \adapter.saved_operation : _0904_; + assign _0902_ = _0926_ ? 1'h1 : _0905_; + assign \adapter.core_rx_data = _0925_ ? 8'h7d : _0901_; + assign \adapter.core_rx_valid = _0925_ ? 1'h1 : _0902_; + assign _0976_ = $signed(_0935_) < 0 ? \adapter.core_tx_data << - _0935_ : \adapter.core_tx_data >> _0935_; + assign _0975_ = $signed(_0935_) < 0 ? 8'hff << - _0935_ : 8'hff >> _0935_; + wire [127:0] _5651_ = \adapter.saved_a ; + assign _0977_ = _5651_[$signed({ 23'h000000, \adapter.payload_index , 3'h0 }) +: 8]; + wire [127:0] _5652_ = \adapter.saved_a ; + assign _0978_ = _5652_[$signed({ 24'h000000, \adapter.payload_index [5:1], 3'h0 }) +: 8]; + wire [127:0] _5653_ = \adapter.saved_b ; + assign _0979_ = _5653_[$signed({ 24'h000000, \adapter.payload_index [5:1], 3'h0 }) +: 8]; + wire [127:0] _5654_ = \adapter.saved_b ; + assign _0980_ = _5654_[$signed({ _0911_[31:3], 3'h0 }) +: 8]; + assign { _0981_[31:29], _0911_[31:3] } = \adapter.payload_index - 32'd16; + assign _0986_ = \adapter.datapath.byte_index + 1'h1; + assign \adapter.datapath.multiplier.impl.a_last = \adapter.datapath.byte_index == 4'hf; + assign _0987_ = ! \adapter.datapath.state ; + assign _0988_ = \adapter.core_rx_data == 8'h7d; + assign _0989_ = \adapter.datapath.state == 4'h2; + assign _0990_ = \adapter.datapath.state == 4'h3; + assign _0991_ = \adapter.datapath.state == 4'h4; + assign _0992_ = \adapter.datapath.state == 4'h8; + assign _0993_ = \adapter.datapath.state == 4'h9; + assign _0994_ = \adapter.datapath.byte_index == 4'h3; + assign _0995_ = \adapter.datapath.state == 4'ha; + assign \adapter.datapath.mul_tail_last = \adapter.datapath.scratch_byte [7:1] == 7'h01; + assign _0996_ = \adapter.datapath.state == 4'h7; + assign _0997_ = _0996_ && \adapter.datapath.multiplier.impl.a_last ; + assign \adapter.datapath.mul_bit_last = _0997_ && \adapter.datapath.mul_tail_last ; + assign _0998_ = \adapter.datapath.scratch_byte [0] || _0999_; + assign _0999_ = | \adapter.core_rx_data ; + assign _1000_ = \adapter.datapath.mul_tail_last ? 7'hxx : { 1'h0, \adapter.datapath.scratch_byte [7:2] }; + function [6:0] _3412_; + input [6:0] a; + input [27:0] b; + input [3:0] s; + casez (s) // synopsys parallel_case + 4'b???1: + _3412_ = b[6:0]; + 4'b??1?: + _3412_ = b[13:7]; + 4'b?1??: + _3412_ = b[20:14]; + 4'b1???: + _3412_ = b[27:21]; + default: + _3412_ = a; + endcase + endfunction + assign _1001_ = _3412_(7'hxx, { 7'h00, _1004_, _1002_, _1000_ }, { _0987_, _1005_, _1003_, _0996_ }); + assign _1002_ = \adapter.core_rx_fire ? { 1'h1, \adapter.core_rx_data [7:2] } : 7'hxx; + assign _1003_ = \adapter.datapath.state == 4'h6; + assign _1004_ = \adapter.core_rx_fire ? \adapter.core_rx_data [7:1] : 7'hxx; + assign _1005_ = \adapter.datapath.state == 4'h1; + assign _1006_ = \adapter.datapath.mul_tail_last ? 1'hx : \adapter.datapath.scratch_byte [1]; + function [0:0] _3418_; + input [0:0] a; + input [4:0] b; + input [4:0] s; + casez (s) // synopsys parallel_case + 5'b????1: + _3418_ = b[0:0]; + 5'b???1?: + _3418_ = b[1:1]; + 5'b??1??: + _3418_ = b[2:2]; + 5'b?1???: + _3418_ = b[3:3]; + 5'b1????: + _3418_ = b[4:4]; + default: + _3418_ = a; + endcase + endfunction + assign _1007_ = _3418_(1'hx, { 1'h0, _1011_, _1010_, _1008_, _1006_ }, { _0987_, _1005_, _0991_, _1003_, _0996_ }); + assign _1008_ = \adapter.core_rx_fire ? \adapter.core_rx_data [1] : 1'hx; + assign _1009_ = \adapter.core_rx_fire ? _0998_ : 1'hx; + assign _1010_ = \adapter.datapath.multiplier.impl.a_last ? 1'hx : _1009_; + assign _1011_ = \adapter.core_rx_fire ? \adapter.core_rx_data [0] : 1'hx; + assign _1012_ = _0994_ ? 4'hx : _0986_; + assign _1013_ = \adapter.core_tx_fire ? _1012_ : 4'hx; + function [3:0] _3425_; + input [3:0] a; + input [23:0] b; + input [5:0] s; + casez (s) // synopsys parallel_case + 6'b?????1: + _3425_ = b[3:0]; + 6'b????1?: + _3425_ = b[7:4]; + 6'b???1??: + _3425_ = b[11:8]; + 6'b??1???: + _3425_ = b[15:12]; + 6'b?1????: + _3425_ = b[19:16]; + 6'b1?????: + _3425_ = b[23:20]; + default: + _3425_ = a; + endcase + endfunction + assign _1014_ = _3425_(4'hx, { 4'h0, _1022_, _1019_, _1018_, _1016_, _1013_ }, { _0987_, _0991_, _1020_, _0996_, _0820_, _0993_ }); + assign _1015_ = \adapter.datapath.multiplier.impl.a_last ? 4'hx : _0986_; + assign _1016_ = \adapter.core_tx_fire ? _1015_ : 4'hx; + assign _1017_ = \adapter.datapath.multiplier.impl.a_last ? 4'h0 : _0986_; + assign _1018_ = \adapter.datapath.mul_tail_last ? _1017_ : 4'hx; + assign _1019_ = \adapter.core_rx_fire ? _1017_ : 4'hx; + assign _1020_ = \adapter.datapath.state == 4'h5; + assign _1021_ = \adapter.core_rx_fire ? _0986_ : 4'hx; + assign _1022_ = \adapter.datapath.multiplier.impl.a_last ? 4'hx : _1021_; + function [0:0] _3434_; + input [0:0] a; + input [1:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3434_ = b[0:0]; + 2'b1?: + _3434_ = b[1:1]; + default: + _3434_ = a; + endcase + endfunction + assign _1023_ = _3434_(1'h1, { _1030_, 1'hx }, { _0987_, _0817_ }); + function [0:0] _3435_; + input [0:0] a; + input [1:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3435_ = b[0:0]; + 2'b1?: + _3435_ = b[1:1]; + default: + _3435_ = a; + endcase + endfunction + assign _1024_ = _3435_(1'h1, 2'bx0, { _0818_, _0988_ }); + assign _1025_ = \adapter.core_rx_data == 8'h7e; + assign _1026_ = \adapter.core_rx_data == 8'h04; + assign _1027_ = \adapter.core_rx_data == 8'h03; + assign _1028_ = \adapter.core_rx_data == 8'h02; + assign _1029_ = \adapter.core_rx_data == 8'h01; + assign _1030_ = \adapter.core_rx_fire ? _1024_ : 1'hx; + assign _1031_ = abort ? 1'h1 : _1023_; + assign _1032_ = \adapter.core_tx_fire ? 4'h0 : \adapter.datapath.state ; + function [3:0] _3444_; + input [3:0] a; + input [39:0] b; + input [9:0] s; + casez (s) // synopsys parallel_case + 10'b?????????1: + _3444_ = b[3:0]; + 10'b????????1?: + _3444_ = b[7:4]; + 10'b???????1??: + _3444_ = b[11:8]; + 10'b??????1???: + _3444_ = b[15:12]; + 10'b?????1????: + _3444_ = b[19:16]; + 10'b????1?????: + _3444_ = b[23:20]; + 10'b???1??????: + _3444_ = b[27:24]; + 10'b??1???????: + _3444_ = b[31:28]; + 10'b?1????????: + _3444_ = b[35:32]; + 10'b1?????????: + _3444_ = b[39:36]; + default: + _3444_ = a; + endcase + endfunction + assign _1033_ = _3444_(4'ha, { _1048_, _1046_, _1045_, _1043_, _1042_, _1040_, _1039_, _1037_, _1035_, _1032_ }, { _0987_, _1005_, _0989_, _0991_, _1020_, _1003_, _0996_, _0821_, _0993_, _0995_ }); + assign _1034_ = _0994_ ? 4'h0 : 4'hx; + assign _1035_ = \adapter.core_tx_fire ? _1034_ : 4'hx; + assign _1036_ = \adapter.datapath.multiplier.impl.a_last ? 4'h0 : 4'hx; + assign _1037_ = \adapter.core_tx_fire ? _1036_ : 4'hx; + assign _1038_ = \adapter.datapath.multiplier.impl.a_last ? 4'h8 : 4'h6; + assign _1039_ = \adapter.datapath.mul_tail_last ? _1038_ : 4'hx; + assign _1040_ = \adapter.core_rx_fire ? 4'h7 : 4'hx; + assign _1041_ = \adapter.datapath.multiplier.impl.a_last ? 4'h6 : 4'hx; + assign _1042_ = \adapter.core_rx_fire ? _1041_ : 4'hx; + assign _1043_ = \adapter.datapath.multiplier.impl.a_last ? _1032_ : 4'hx; + assign _1044_ = \adapter.datapath.multiplier.impl.a_last ? 4'h0 : 4'h1; + assign _1045_ = \adapter.core_tx_fire ? _1044_ : 4'hx; + assign _1046_ = \adapter.core_rx_fire ? 4'h2 : 4'hx; + function [3:0] _3458_; + input [3:0] a; + input [23:0] b; + input [5:0] s; + casez (s) // synopsys parallel_case + 6'b?????1: + _3458_ = b[3:0]; + 6'b????1?: + _3458_ = b[7:4]; + 6'b???1??: + _3458_ = b[11:8]; + 6'b??1???: + _3458_ = b[15:12]; + 6'b?1????: + _3458_ = b[19:16]; + 6'b1?????: + _3458_ = b[23:20]; + default: + _3458_ = a; + endcase + endfunction + assign _1047_ = _3458_(4'ha, 24'h153490, { _1029_, _1028_, _1027_, _1026_, _1025_, _0988_ }); + assign _1048_ = \adapter.core_rx_fire ? _1047_ : 4'hx; + function [7:0] _3460_; + input [7:0] a; + input [23:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3460_ = b[7:0]; + 3'b?1?: + _3460_ = b[15:8]; + 3'b1??: + _3460_ = b[23:16]; + default: + _3460_ = a; + endcase + endfunction + assign _0983_ = _3460_(8'h00, 24'h010f08, { _0808_, _1049_, _0994_ }); + assign _1049_ = \adapter.datapath.byte_index == 4'h2; + assign _1050_ = \adapter.datapath.byte_index == 4'h1; + assign _1051_ = ! \adapter.datapath.byte_index ; + assign _0982_ = \adapter.datapath.multiplier.impl.a_last ? \adapter.core_tx_ready : 1'h1; + assign _0984_ = \adapter.datapath.multiplier.impl.a_last ? { 7'h00, _0998_ } : 8'h00; + assign _0985_ = \adapter.datapath.multiplier.impl.a_last ? \adapter.core_rx_valid : 1'h0; + function [0:0] _3467_; + input [0:0] a; + input [2:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3467_ = b[0:0]; + 3'b?1?: + _3467_ = b[1:1]; + 3'b1??: + _3467_ = b[2:2]; + default: + _3467_ = a; + endcase + endfunction + assign \adapter.core_rx_ready = _3467_(1'h0, { \adapter.core_tx_ready , _0982_, 1'h1 }, { _0812_, _0991_, _0811_ }); + assign \adapter.datapath.mul_result_shift = _0992_ ? \adapter.core_tx_ready : 1'h0; + function [0:0] _3469_; + input [0:0] a; + input [1:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3469_ = b[0:0]; + 2'b1?: + _3469_ = b[1:1]; + default: + _3469_ = a; + endcase + endfunction + assign \adapter.datapath.mul_bit_value = _3469_(1'h0, { \adapter.core_rx_data [0], \adapter.datapath.scratch_byte [0] }, { _1003_, _0996_ }); + function [0:0] _3470_; + input [0:0] a; + input [1:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3470_ = b[0:0]; + 2'b1?: + _3470_ = b[1:1]; + default: + _3470_ = a; + endcase + endfunction + assign \adapter.datapath.mul_bit_valid = _3470_(1'h0, { \adapter.core_rx_valid , 1'h1 }, { _1003_, _0996_ }); + assign \adapter.datapath.mul_a_valid = _1020_ ? \adapter.core_rx_valid : 1'h0; + function [0:0] _3472_; + input [0:0] a; + input [2:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3472_ = b[0:0]; + 3'b?1?: + _3472_ = b[1:1]; + 3'b1??: + _3472_ = b[2:2]; + default: + _3472_ = a; + endcase + endfunction + assign \adapter.core_tx_valid = _3472_(1'h0, { \adapter.core_rx_valid , _0985_, 1'h1 }, { _0812_, _0991_, _0813_ }); + function [7:0] _3473_; + input [7:0] a; + input [47:0] b; + input [5:0] s; + casez (s) // synopsys parallel_case + 6'b?????1: + _3473_ = b[7:0]; + 6'b????1?: + _3473_ = b[15:8]; + 6'b???1??: + _3473_ = b[23:16]; + 6'b??1???: + _3473_ = b[31:24]; + 6'b?1????: + _3473_ = b[39:32]; + 6'b1?????: + _3473_ = b[47:40]; + default: + _3473_ = a; + endcase + endfunction + assign \adapter.core_tx_data = _3473_(8'h00, { _1052_, \adapter.core_rx_data , _0984_, \adapter.datapath.multiplier.impl.accumulator [7:0], _0983_, 8'he0 }, { _0989_, _0990_, _0991_, _0992_, _0993_, _0995_ }); + assign _1052_ = \adapter.datapath.scratch_byte ^ \adapter.core_rx_data ; + assign _1053_ = \adapter.datapath.mul_result_shift ? { 8'h00, \adapter.datapath.multiplier.impl.accumulator [127:8] } : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _1054_ = \adapter.datapath.mul_bit_valid ? \adapter.datapath.multiplier.impl.accumulator_next : _1053_; + assign _1055_ = \adapter.datapath.multiplier.impl.a_last ? 128'h00000000000000000000000000000000 : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _1056_ = \adapter.datapath.mul_a_valid ? _1055_ : _1054_; + assign _1057_ = \adapter.datapath.mul_bit_last ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _1061_; + assign _1058_ = \adapter.datapath.mul_bit_valid ? _1057_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _1059_ = \adapter.datapath.mul_a_valid ? { \adapter.core_rx_data , \adapter.datapath.multiplier.impl.a_shift [127:8] } : _1058_; + assign \adapter.datapath.multiplier.impl.selected = \adapter.datapath.mul_bit_value ? \adapter.datapath.multiplier.impl.a_shift : 128'h00000000000000000000000000000000; + assign _1060_ = \adapter.datapath.multiplier.impl.a_shift [127] ? 128'h00000000000000000000000000000087 : 128'h00000000000000000000000000000000; + assign \adapter.datapath.multiplier.impl.accumulator_next = \adapter.datapath.multiplier.impl.accumulator ^ \adapter.datapath.multiplier.impl.selected ; + assign _1061_ = { \adapter.datapath.multiplier.impl.a_shift [126:0], 1'h0 } ^ _1060_; + assign _1062_ = ! \field_encoder.bit_index ; + assign _1063_ = encoder_start && _1066_; + assign _1064_ = \field_encoder.busy && \field_encoder.multiplier.done_pulse ; + assign _1065_ = ! rst_n; + assign _1066_ = ! \field_encoder.busy ; + assign _1067_ = _1065_ || abort; + assign _1068_ = _1062_ ? 1'h0 : 1'h1; + assign _1069_ = \field_encoder.multiplier.fault ? 1'h0 : _1068_; + assign _1070_ = _1064_ ? _1069_ : 1'h0; + assign _1071_ = _1063_ ? 1'h1 : _1070_; + assign _1072_ = _1062_ ? 1'h1 : 1'h0; + assign _1073_ = \field_encoder.multiplier.fault ? 1'h1 : _1072_; + assign _1074_ = _1062_ ? { \field_encoder.bit_index [4], 4'hx } : _1087_; + assign _1075_ = \field_encoder.multiplier.fault ? { \field_encoder.bit_index [4], 4'hx } : _1074_; + assign _1076_ = _1064_ ? _1075_ : { \field_encoder.bit_index [4], 4'hx }; + assign _1077_ = _1063_ ? 5'h0f : _1076_; + assign _1078_ = _1062_ ? { \field_encoder.operand_b [127:1], 1'hx } : _1089_; + assign _1079_ = \field_encoder.multiplier.fault ? { \field_encoder.operand_b [127:1], 1'hx } : _1078_; + assign _1080_ = _1064_ ? _1079_ : { \field_encoder.operand_b [127:1], 1'hx }; + assign _1081_ = _1063_ ? 128'h00000000000000000000000000000001 : _1080_; + assign _1082_ = _1062_ ? 1'h0 : 1'hx; + assign _1083_ = \field_encoder.multiplier.fault ? 1'h0 : _1082_; + assign _1084_ = _1064_ ? _1083_ : 1'hx; + assign _1085_ = _1063_ ? 1'h1 : _1084_; + wire [15:0] _5655_ = \field_encoder.saved_index ; + assign _1086_ = _5655_[\field_encoder.bit_index +: 1]; + assign _1087_ = \field_encoder.bit_index - 1'h1; + assign _1088_ = \field_encoder.multiplier.result [127] ? 128'h00000000000000000000000000000087 : 128'h00000000000000000000000000000000; + assign _1089_ = _1086_ ? _1090_ : \field_encoder.multiplier.result ; + assign _1090_ = { \field_encoder.multiplier.result [126:0], 1'h0 } ^ _1088_; + assign _1100_ = \field_encoder.multiplier.result_index + 1'h1; + assign _1101_ = \field_encoder.multiplier.payload_index + 1'h1; + assign _1102_ = \field_encoder.multiplier.result & _1112_; + assign _1103_ = \field_encoder.multiplier.state == 3'h4; + assign _1104_ = \field_encoder.multiplier.payload_index == 6'h1f; + assign _1105_ = \field_encoder.multiplier.result_index == 5'h0f; + assign _1106_ = \field_encoder.multiplier.state == 3'h3; + assign _1107_ = \field_encoder.multiplier.state == 3'h1; + assign _1108_ = \field_encoder.multiplier.state == 3'h2; + assign _1109_ = _1103_ && \field_encoder.multiplier.datapath.fault ; + assign \field_encoder.multiplier.core_tx_ready = _1106_ || _1103_; + assign _1110_ = \field_encoder.multiplier.payload_index < 32'd16; + assign _1111_ = - $signed({ 25'h0000000, \field_encoder.multiplier.result_index , 3'h0 }); + assign _1112_ = ~ _1147_; + assign _1113_ = _1102_ | _1148_; + assign _1098_ = \field_encoder.multiplier.core_tx_fire ? _1113_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _1096_ = \field_encoder.multiply_start ? 128'h00000000000000000000000000000000 : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _1114_ = ! \field_encoder.multiplier.state ; + function [127:0] _3533_; + input [127:0] a; + input [255:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3533_ = b[127:0]; + 2'b1?: + _3533_ = b[255:128]; + default: + _3533_ = a; + endcase + endfunction + assign _1093_ = _3533_(128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _1096_, _1098_ }, { _1114_, _0822_ }); + assign _1115_ = _1105_ ? 1'h1 : 1'h0; + assign _1116_ = \field_encoder.multiplier.core_tx_fire ? _1115_ : 1'h0; + function [0:0] _3536_; + input [0:0] a; + input [1:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3536_ = b[0:0]; + 2'b1?: + _3536_ = b[1:1]; + default: + _3536_ = a; + endcase + endfunction + assign _1117_ = _3536_(1'h0, { _1120_, _1116_ }, { _1106_, _1103_ }); + assign _1118_ = \field_encoder.multiplier.saved_operation [1] ? 1'h0 : 1'h1; + assign _1119_ = _1104_ ? _1118_ : 1'h0; + assign _1120_ = \field_encoder.multiplier.core_rx_fire ? _1119_ : 1'h0; + assign _1121_ = _1105_ ? 5'hxx : _1100_; + assign _1122_ = \field_encoder.multiplier.core_tx_fire ? _1121_ : 5'hxx; + function [4:0] _3542_; + input [4:0] a; + input [14:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3542_ = b[4:0]; + 3'b?1?: + _3542_ = b[9:5]; + 3'b1??: + _3542_ = b[14:10]; + default: + _3542_ = a; + endcase + endfunction + assign _1123_ = _3542_(5'hxx, { _1128_, _1127_, _1122_ }, { _1114_, _1106_, _1103_ }); + assign _1124_ = \field_encoder.multiplier.core_tx_fire ? _1100_ : \field_encoder.multiplier.result_index ; + assign _1125_ = \field_encoder.multiplier.saved_operation [1] ? 5'h00 : _1124_; + assign _1126_ = _1104_ ? _1125_ : _1124_; + assign _1127_ = \field_encoder.multiplier.core_rx_fire ? _1126_ : _1124_; + assign _1128_ = \field_encoder.multiply_start ? 5'h00 : 5'hxx; + assign _1129_ = _1104_ ? 6'hxx : _1101_; + assign _1130_ = \field_encoder.multiplier.core_rx_fire ? _1129_ : 6'hxx; + function [5:0] _3550_; + input [5:0] a; + input [17:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3550_ = b[5:0]; + 3'b?1?: + _3550_ = b[11:6]; + 3'b1??: + _3550_ = b[17:12]; + default: + _3550_ = a; + endcase + endfunction + assign _1131_ = _3550_(6'hxx, { _1133_, _1132_, _1130_ }, { _1114_, _1108_, _1106_ }); + assign _1132_ = \field_encoder.multiplier.core_rx_fire ? 6'h00 : 6'hxx; + assign _1133_ = \field_encoder.multiply_start ? 6'h00 : 6'hxx; + assign _1134_ = _1109_ ? 1'h1 : \field_encoder.multiplier.fault ; + assign _1135_ = \field_encoder.multiply_start ? 1'h0 : _1134_; + assign _1136_ = _1114_ ? _1135_ : _1134_; + assign _1137_ = abort ? 1'h1 : _1136_; + assign _1138_ = _1105_ ? 3'h0 : 3'hx; + assign _1139_ = \field_encoder.multiplier.core_tx_fire ? _1138_ : 3'hx; + function [2:0] _3559_; + input [2:0] a; + input [14:0] b; + input [4:0] s; + casez (s) // synopsys parallel_case + 5'b????1: + _3559_ = b[2:0]; + 5'b???1?: + _3559_ = b[5:3]; + 5'b??1??: + _3559_ = b[8:6]; + 5'b?1???: + _3559_ = b[11:9]; + 5'b1????: + _3559_ = b[14:12]; + default: + _3559_ = a; + endcase + endfunction + assign _1140_ = _3559_(3'h0, { _1146_, _1145_, _1144_, _1143_, _1139_ }, { _1114_, _1107_, _1108_, _1106_, _1103_ }); + assign _1141_ = \field_encoder.multiplier.saved_operation [1] ? 3'h4 : 3'h0; + assign _1142_ = _1104_ ? _1141_ : 3'hx; + assign _1143_ = \field_encoder.multiplier.core_rx_fire ? _1142_ : 3'hx; + assign _1144_ = \field_encoder.multiplier.core_rx_fire ? 3'h3 : 3'hx; + assign _1145_ = \field_encoder.multiplier.core_rx_fire ? 3'h2 : 3'hx; + assign _1146_ = \field_encoder.multiply_start ? 3'h1 : 3'hx; + assign _1097_ = _1110_ ? _1149_ : _1150_; + assign _1094_ = _1106_ ? _1097_ : 8'h00; + assign _1095_ = _1106_ ? 1'h1 : 1'h0; + assign _1091_ = _1108_ ? { 6'h00, \field_encoder.multiplier.saved_operation [1], 1'h0 } : _1094_; + assign _1092_ = _1108_ ? 1'h1 : _1095_; + assign \field_encoder.multiplier.core_rx_data = _1107_ ? 8'h7d : _1091_; + assign \field_encoder.multiplier.core_rx_valid = _1107_ ? 1'h1 : _1092_; + assign _1147_ = $signed(_1111_) < 0 ? 8'hff << - _1111_ : 8'hff >> _1111_; + assign _1148_ = $signed(_1111_) < 0 ? \field_encoder.multiplier.core_tx_data << - _1111_ : \field_encoder.multiplier.core_tx_data >> _1111_; + wire [127:0] _5656_ = \field_encoder.multiplier.saved_b ; + assign _1149_ = _5656_[$signed({ 23'h000000, \field_encoder.multiplier.payload_index , 3'h0 }) +: 8]; + wire [127:0] _5657_ = \field_encoder.multiplier.saved_b ; + assign _1150_ = _5657_[$signed({ _1099_[31:3], 3'h0 }) +: 8]; + assign { _1151_[31:29], _1099_[31:3] } = \field_encoder.multiplier.payload_index - 32'd16; + assign _1156_ = \field_encoder.multiplier.datapath.byte_index + 1'h1; + assign \field_encoder.multiplier.datapath.mul_tail_last = \field_encoder.multiplier.datapath.scratch_byte [7:1] == 7'h01; + assign \field_encoder.multiplier.datapath.multiplier.impl.a_last = \field_encoder.multiplier.datapath.byte_index == 4'hf; + assign \field_encoder.multiplier.core_rx_fire = \field_encoder.multiplier.core_rx_valid && \field_encoder.multiplier.datapath.rx_ready ; + assign \field_encoder.multiplier.core_tx_fire = \field_encoder.multiplier.datapath.tx_valid && \field_encoder.multiplier.core_tx_ready ; + assign _1167_ = _1166_ && \field_encoder.multiplier.datapath.multiplier.impl.a_last ; + assign \field_encoder.multiplier.datapath.mul_bit_last = _1167_ && \field_encoder.multiplier.datapath.mul_tail_last ; + assign _1168_ = \field_encoder.multiplier.datapath.scratch_byte [0] || _1169_; + assign _1169_ = | \field_encoder.multiplier.core_rx_data ; + assign _1170_ = \field_encoder.multiplier.datapath.mul_tail_last ? 7'hxx : { 1'h0, \field_encoder.multiplier.datapath.scratch_byte [7:2] }; + function [6:0] _3588_; + input [6:0] a; + input [27:0] b; + input [3:0] s; + casez (s) // synopsys parallel_case + 4'b???1: + _3588_ = b[6:0]; + 4'b??1?: + _3588_ = b[13:7]; + 4'b?1??: + _3588_ = b[20:14]; + 4'b1???: + _3588_ = b[27:21]; + default: + _3588_ = a; + endcase + endfunction + assign _1171_ = _3588_(7'hxx, { 7'h00, _1174_, _1172_, _1170_ }, { _1157_, _1175_, _1173_, _1166_ }); + assign _1172_ = \field_encoder.multiplier.core_rx_fire ? { 1'h1, \field_encoder.multiplier.core_rx_data [7:2] } : 7'hxx; + assign _1174_ = \field_encoder.multiplier.core_rx_fire ? \field_encoder.multiplier.core_rx_data [7:1] : 7'hxx; + assign _1176_ = \field_encoder.multiplier.datapath.mul_tail_last ? 1'hx : \field_encoder.multiplier.datapath.scratch_byte [1]; + function [0:0] _3592_; + input [0:0] a; + input [4:0] b; + input [4:0] s; + casez (s) // synopsys parallel_case + 5'b????1: + _3592_ = b[0:0]; + 5'b???1?: + _3592_ = b[1:1]; + 5'b??1??: + _3592_ = b[2:2]; + 5'b?1???: + _3592_ = b[3:3]; + 5'b1????: + _3592_ = b[4:4]; + default: + _3592_ = a; + endcase + endfunction + assign _1177_ = _3592_(1'hx, { 1'h0, _1181_, _1180_, _1178_, _1176_ }, { _1157_, _1175_, _1161_, _1173_, _1166_ }); + assign _1178_ = \field_encoder.multiplier.core_rx_fire ? \field_encoder.multiplier.core_rx_data [1] : 1'hx; + assign _1179_ = \field_encoder.multiplier.core_rx_fire ? _1168_ : 1'hx; + assign _1180_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? 1'hx : _1179_; + assign _1181_ = \field_encoder.multiplier.core_rx_fire ? \field_encoder.multiplier.core_rx_data [0] : 1'hx; + assign _1182_ = _1164_ ? 4'hx : _1156_; + assign _1183_ = \field_encoder.multiplier.core_tx_fire ? _1182_ : 4'hx; + function [3:0] _3599_; + input [3:0] a; + input [23:0] b; + input [5:0] s; + casez (s) // synopsys parallel_case + 6'b?????1: + _3599_ = b[3:0]; + 6'b????1?: + _3599_ = b[7:4]; + 6'b???1??: + _3599_ = b[11:8]; + 6'b??1???: + _3599_ = b[15:12]; + 6'b?1????: + _3599_ = b[19:16]; + 6'b1?????: + _3599_ = b[23:20]; + default: + _3599_ = a; + endcase + endfunction + assign _1184_ = _3599_(4'hx, { 4'h0, _1192_, _1189_, _1188_, _1186_, _1183_ }, { _1157_, _1161_, _1190_, _1166_, _0823_, _1163_ }); + assign _1188_ = \field_encoder.multiplier.datapath.mul_tail_last ? _1187_ : 4'hx; + assign _1187_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? 4'h0 : _1156_; + assign _1189_ = \field_encoder.multiplier.core_rx_fire ? _1187_ : 4'hx; + assign _1191_ = \field_encoder.multiplier.core_rx_fire ? _1156_ : 4'hx; + assign _1192_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? 4'hx : _1191_; + assign _1185_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? 4'hx : _1156_; + assign _1186_ = \field_encoder.multiplier.core_tx_fire ? _1185_ : 4'hx; + function [0:0] _3607_; + input [0:0] a; + input [1:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3607_ = b[0:0]; + 2'b1?: + _3607_ = b[1:1]; + default: + _3607_ = a; + endcase + endfunction + assign _1193_ = _3607_(1'h1, { _1200_, 1'hx }, { _1157_, _0807_ }); + function [0:0] _3608_; + input [0:0] a; + input [1:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3608_ = b[0:0]; + 2'b1?: + _3608_ = b[1:1]; + default: + _3608_ = a; + endcase + endfunction + assign _1194_ = _3608_(1'h1, 2'bx0, { _0806_, _1158_ }); + assign _1200_ = \field_encoder.multiplier.core_rx_fire ? _1194_ : 1'hx; + assign _1201_ = abort ? 1'h1 : _1193_; + function [3:0] _3611_; + input [3:0] a; + input [39:0] b; + input [9:0] s; + casez (s) // synopsys parallel_case + 10'b?????????1: + _3611_ = b[3:0]; + 10'b????????1?: + _3611_ = b[7:4]; + 10'b???????1??: + _3611_ = b[11:8]; + 10'b??????1???: + _3611_ = b[15:12]; + 10'b?????1????: + _3611_ = b[19:16]; + 10'b????1?????: + _3611_ = b[23:20]; + 10'b???1??????: + _3611_ = b[27:24]; + 10'b??1???????: + _3611_ = b[31:28]; + 10'b?1????????: + _3611_ = b[35:32]; + 10'b1?????????: + _3611_ = b[39:36]; + default: + _3611_ = a; + endcase + endfunction + assign _1203_ = _3611_(4'ha, { _1218_, _1216_, _1215_, _1213_, _1212_, _1210_, _1209_, _1207_, _1205_, _1202_ }, { _1157_, _1175_, _1159_, _1161_, _1190_, _1173_, _1166_, _0824_, _1163_, _1165_ }); + assign _1204_ = _1164_ ? 4'h0 : 4'hx; + assign _1205_ = \field_encoder.multiplier.core_tx_fire ? _1204_ : 4'hx; + assign _1208_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? 4'h8 : 4'h6; + assign _1209_ = \field_encoder.multiplier.datapath.mul_tail_last ? _1208_ : 4'hx; + assign _1210_ = \field_encoder.multiplier.core_rx_fire ? 4'h7 : 4'hx; + assign _1211_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? 4'h6 : 4'hx; + assign _1212_ = \field_encoder.multiplier.core_rx_fire ? _1211_ : 4'hx; + assign _1202_ = \field_encoder.multiplier.core_tx_fire ? 4'h0 : \field_encoder.multiplier.datapath.state ; + assign _1213_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? _1202_ : 4'hx; + assign _1206_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? 4'h0 : 4'hx; + assign _1207_ = \field_encoder.multiplier.core_tx_fire ? _1206_ : 4'hx; + assign _1214_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? 4'h0 : 4'h1; + assign _1215_ = \field_encoder.multiplier.core_tx_fire ? _1214_ : 4'hx; + assign _1216_ = \field_encoder.multiplier.core_rx_fire ? 4'h2 : 4'hx; + function [3:0] _3626_; + input [3:0] a; + input [23:0] b; + input [5:0] s; + casez (s) // synopsys parallel_case + 6'b?????1: + _3626_ = b[3:0]; + 6'b????1?: + _3626_ = b[7:4]; + 6'b???1??: + _3626_ = b[11:8]; + 6'b??1???: + _3626_ = b[15:12]; + 6'b?1????: + _3626_ = b[19:16]; + 6'b1?????: + _3626_ = b[23:20]; + default: + _3626_ = a; + endcase + endfunction + assign _1217_ = _3626_(4'ha, 24'h153490, { _1199_, _1198_, _1197_, _1196_, _1195_, _1158_ }); + assign _1158_ = \field_encoder.multiplier.core_rx_data == 8'h7d; + assign _1195_ = \field_encoder.multiplier.core_rx_data == 8'h7e; + assign _1196_ = \field_encoder.multiplier.core_rx_data == 8'h04; + assign _1197_ = \field_encoder.multiplier.core_rx_data == 8'h03; + assign _1198_ = \field_encoder.multiplier.core_rx_data == 8'h02; + assign _1199_ = \field_encoder.multiplier.core_rx_data == 8'h01; + assign _1218_ = \field_encoder.multiplier.core_rx_fire ? _1217_ : 4'hx; + function [7:0] _3634_; + input [7:0] a; + input [23:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3634_ = b[7:0]; + 3'b?1?: + _3634_ = b[15:8]; + 3'b1??: + _3634_ = b[23:16]; + default: + _3634_ = a; + endcase + endfunction + assign _1153_ = _3634_(8'h00, 24'h010f08, { _0815_, _1219_, _1164_ }); + assign _1164_ = \field_encoder.multiplier.datapath.byte_index == 4'h3; + assign _1219_ = \field_encoder.multiplier.datapath.byte_index == 4'h2; + assign _1220_ = \field_encoder.multiplier.datapath.byte_index == 4'h1; + assign _1221_ = ! \field_encoder.multiplier.datapath.byte_index ; + assign _1152_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? \field_encoder.multiplier.core_tx_ready : 1'h1; + assign _1154_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? { 7'h00, _1168_ } : 8'h00; + assign _1155_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? \field_encoder.multiplier.core_rx_valid : 1'h0; + function [0:0] _3642_; + input [0:0] a; + input [2:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3642_ = b[0:0]; + 3'b?1?: + _3642_ = b[1:1]; + 3'b1??: + _3642_ = b[2:2]; + default: + _3642_ = a; + endcase + endfunction + assign \field_encoder.multiplier.datapath.rx_ready = _3642_(1'h0, { \field_encoder.multiplier.core_tx_ready , _1152_, 1'h1 }, { _0810_, _1161_, _0814_ }); + assign _1175_ = \field_encoder.multiplier.datapath.state == 4'h1; + assign _1157_ = ! \field_encoder.multiplier.datapath.state ; + assign \field_encoder.multiplier.datapath.mul_result_shift = _1162_ ? \field_encoder.multiplier.core_tx_ready : 1'h0; + function [0:0] _3646_; + input [0:0] a; + input [1:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3646_ = b[0:0]; + 2'b1?: + _3646_ = b[1:1]; + default: + _3646_ = a; + endcase + endfunction + assign \field_encoder.multiplier.datapath.mul_bit_value = _3646_(1'h0, { \field_encoder.multiplier.core_rx_data [0], \field_encoder.multiplier.datapath.scratch_byte [0] }, { _1173_, _1166_ }); + function [0:0] _3647_; + input [0:0] a; + input [1:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3647_ = b[0:0]; + 2'b1?: + _3647_ = b[1:1]; + default: + _3647_ = a; + endcase + endfunction + assign \field_encoder.multiplier.datapath.mul_bit_valid = _3647_(1'h0, { \field_encoder.multiplier.core_rx_valid , 1'h1 }, { _1173_, _1166_ }); + assign _1166_ = \field_encoder.multiplier.datapath.state == 4'h7; + assign _1173_ = \field_encoder.multiplier.datapath.state == 4'h6; + assign \field_encoder.multiplier.datapath.mul_a_valid = _1190_ ? \field_encoder.multiplier.core_rx_valid : 1'h0; + assign _1190_ = \field_encoder.multiplier.datapath.state == 4'h5; + function [0:0] _3652_; + input [0:0] a; + input [2:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3652_ = b[0:0]; + 3'b?1?: + _3652_ = b[1:1]; + 3'b1??: + _3652_ = b[2:2]; + default: + _3652_ = a; + endcase + endfunction + assign \field_encoder.multiplier.datapath.tx_valid = _3652_(1'h0, { \field_encoder.multiplier.core_rx_valid , _1155_, 1'h1 }, { _0810_, _1161_, _0809_ }); + function [7:0] _3653_; + input [7:0] a; + input [47:0] b; + input [5:0] s; + casez (s) // synopsys parallel_case + 6'b?????1: + _3653_ = b[7:0]; + 6'b????1?: + _3653_ = b[15:8]; + 6'b???1??: + _3653_ = b[23:16]; + 6'b??1???: + _3653_ = b[31:24]; + 6'b?1????: + _3653_ = b[39:32]; + 6'b1?????: + _3653_ = b[47:40]; + default: + _3653_ = a; + endcase + endfunction + assign \field_encoder.multiplier.core_tx_data = _3653_(8'h00, { _1222_, \field_encoder.multiplier.core_rx_data , _1154_, \field_encoder.multiplier.datapath.multiplier.impl.accumulator [7:0], _1153_, 8'he0 }, { _1159_, _1160_, _1161_, _1162_, _1163_, _1165_ }); + assign _1165_ = \field_encoder.multiplier.datapath.state == 4'ha; + assign _1163_ = \field_encoder.multiplier.datapath.state == 4'h9; + assign _1162_ = \field_encoder.multiplier.datapath.state == 4'h8; + assign _1161_ = \field_encoder.multiplier.datapath.state == 4'h4; + assign _1160_ = \field_encoder.multiplier.datapath.state == 4'h3; + assign _1159_ = \field_encoder.multiplier.datapath.state == 4'h2; + assign _1222_ = \field_encoder.multiplier.datapath.scratch_byte ^ \field_encoder.multiplier.core_rx_data ; + assign _1223_ = \field_encoder.multiplier.datapath.mul_result_shift ? { 8'h00, \field_encoder.multiplier.datapath.multiplier.impl.accumulator [127:8] } : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _1224_ = \field_encoder.multiplier.datapath.mul_bit_valid ? \field_encoder.multiplier.datapath.multiplier.impl.accumulator_next : _1223_; + assign _1225_ = \field_encoder.multiplier.datapath.multiplier.impl.a_last ? 128'h00000000000000000000000000000000 : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _1226_ = \field_encoder.multiplier.datapath.mul_a_valid ? _1225_ : _1224_; + assign _1227_ = \field_encoder.multiplier.datapath.mul_bit_last ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _1231_; + assign _1228_ = \field_encoder.multiplier.datapath.mul_bit_valid ? _1227_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _1229_ = \field_encoder.multiplier.datapath.mul_a_valid ? { \field_encoder.multiplier.core_rx_data , \field_encoder.multiplier.datapath.multiplier.impl.a_shift [127:8] } : _1228_; + assign \field_encoder.multiplier.datapath.multiplier.impl.selected = \field_encoder.multiplier.datapath.mul_bit_value ? \field_encoder.multiplier.datapath.multiplier.impl.a_shift : 128'h00000000000000000000000000000000; + assign _1230_ = \field_encoder.multiplier.datapath.multiplier.impl.a_shift [127] ? 128'h00000000000000000000000000000087 : 128'h00000000000000000000000000000000; + assign \field_encoder.multiplier.datapath.multiplier.impl.accumulator_next = \field_encoder.multiplier.datapath.multiplier.impl.accumulator ^ \field_encoder.multiplier.datapath.multiplier.impl.selected ; + assign _1231_ = { \field_encoder.multiplier.datapath.multiplier.impl.a_shift [126:0], 1'h0 } ^ _1230_; + assign _1235_ = \receiver.header_index + 1'h1; + assign _1236_ = \receiver.body_index + 1'h1; + assign _1237_ = \receiver.frame_payload & _1271_; + assign _1238_ = ~ { 24'h000000, rx_data }; + assign _1239_ = ~ { 1'h0, _1238_[31:30], _1238_[28:27], _1238_[25:24], _1238_[22:20], _1238_[16], _1238_[10:9], _1238_[6] }; + assign _1240_ = ~ { 1'h0, _1341_[30:29], _1341_[27:26], _1341_[24:23], _1341_[21:19], _1341_[15], _1341_[9:8], _1341_[5] }; + assign _1241_ = ~ { 1'h0, _1342_[30:29], _1342_[27:26], _1342_[24:23], _1342_[21:19], _1342_[15], _1342_[9:8], _1342_[5] }; + assign _1242_ = ~ { 1'h0, _1343_[30:29], _1343_[27:26], _1343_[24:23], _1343_[21:19], _1343_[15], _1343_[9:8], _1343_[5] }; + assign _1243_ = ~ { 1'h0, _1344_[30:29], _1344_[27:26], _1344_[24:23], _1344_[21:19], _1344_[15], _1344_[9:8], _1344_[5] }; + assign _1244_ = ~ { 1'h0, _1345_[30:29], _1345_[27:26], _1345_[24:23], _1345_[21:19], _1345_[15], _1345_[9:8], _1345_[5] }; + assign _1245_ = ~ { 1'h0, _1346_[30:29], _1346_[27:26], _1346_[24:23], _1346_[21:19], _1346_[15], _1346_[9:8], _1346_[5] }; + assign _1246_ = ~ { 1'h0, _1347_[30:29], _1347_[27:26], _1347_[24:23], _1347_[21:19], _1347_[15], _1347_[9:8], _1347_[5] }; + assign _1247_ = ~ { 1'h0, _1348_[30:29], _1348_[27:26], _1348_[24:23], _1348_[21:19], _1348_[15], _1348_[9:8], _1348_[5] }; + assign _1248_ = ~ { 1'h0, _1349_[30:29], _1349_[27:26], _1349_[24:23], _1349_[21:19], _1349_[15], _1349_[9:8], _1349_[5] }; + assign _1249_ = ~ { 1'h0, _1350_[30:29], _1350_[27:26], _1350_[24:23], _1350_[21:19], _1350_[15], _1350_[9:8], _1350_[5] }; + assign _1250_ = ~ { 1'h0, _1351_[30:29], _1351_[27:26], _1351_[24:23], _1351_[21:19], _1351_[15], _1351_[9:8], _1351_[5] }; + assign _1251_ = ~ { 1'h0, _1352_[30:29], _1352_[27:26], _1352_[24:23], _1352_[21:19], _1352_[15], _1352_[9:8], _1352_[5] }; + assign _1252_ = ~ { 1'h0, _1353_[30:29], _1353_[27:26], _1353_[24:23], _1353_[21:19], _1353_[15], _1353_[9:8], _1353_[5] }; + assign _1253_ = ~ { 1'h0, _1354_[30:29], _1354_[27:26], _1354_[24:23], _1354_[21:19], _1354_[15], _1354_[9:8], _1354_[5] }; + assign _1254_ = ~ { 1'h0, _1355_[30:29], _1355_[27:26], _1355_[24:23], _1355_[21:19], _1355_[15], _1355_[9:8], _1355_[5] }; + assign _1255_ = { rx_data, \receiver.declared_length [7:0] } > 16'h0100; + assign _1256_ = _1268_ && _1259_; + assign \receiver.rx_ready = _1256_ && _1260_; + assign \receiver.rx_fire = \receiver.rx_valid && \receiver.rx_ready ; + assign _1257_ = \receiver.frame_valid && \receiver.frame_ready ; + assign _1258_ = \receiver.fault_valid && \receiver.frame_ready ; + assign _1259_ = ! \receiver.frame_valid ; + assign _1260_ = ! \receiver.fault_valid ; + assign _1261_ = _1267_ || \receiver.frame_valid ; + assign \receiver.busy = _1261_ || \receiver.fault_valid ; + assign _1262_ = \receiver.body_index < \receiver.declared_length ; + assign _1263_ = \receiver.body_index < 16'h0100; + assign _1264_ = { rx_data, \receiver.received_crc [23:0] } != _1272_; + assign _1265_ = \receiver.version != 8'h01; + assign _1266_ = | \receiver.flags ; + assign _1267_ = | \receiver.state ; + assign _1268_ = \receiver.state != 3'h3; + assign _1269_ = rx_data != 8'ha1; + assign _1270_ = - $signed({ 14'h0000, \receiver.body_index , 3'h0 }); + assign _1271_ = ~ _1339_; + assign _1272_ = ~ \receiver.crc ; + assign _1273_ = _1237_ | _1340_; + assign _1277_ = _1278_ ? rx_data : 8'hxx; + assign _1278_ = _1356_ == 32'd2; + assign _1279_ = _1262_ ? 8'hxx : _1277_; + function [7:0] _3717_; + input [7:0] a; + input [15:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3717_ = b[7:0]; + 2'b1?: + _3717_ = b[15:8]; + default: + _3717_ = a; + endcase + endfunction + assign _1280_ = _3717_(8'hxx, { 8'h00, _1279_ }, { _1276_, _1275_ }); + assign _1281_ = _1282_ ? rx_data : 8'hxx; + assign _1282_ = _1356_ == 32'd1; + assign _1283_ = _1262_ ? 8'hxx : _1281_; + function [7:0] _3721_; + input [7:0] a; + input [15:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3721_ = b[7:0]; + 2'b1?: + _3721_ = b[15:8]; + default: + _3721_ = a; + endcase + endfunction + assign _1284_ = _3721_(8'hxx, { 8'h00, _1283_ }, { _1276_, _1275_ }); + assign _1285_ = _1286_ ? rx_data : 8'hxx; + assign _1286_ = ! _1356_; + assign _1287_ = _1262_ ? 8'hxx : _1285_; + function [7:0] _3725_; + input [7:0] a; + input [15:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3725_ = b[7:0]; + 2'b1?: + _3725_ = b[15:8]; + default: + _3725_ = a; + endcase + endfunction + assign _1288_ = _3725_(8'hxx, { 8'h00, _1287_ }, { _1276_, _1275_ }); + assign _1233_ = _1262_ ? _1234_ : 2048'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + function [2047:0] _3727_; + input [2047:0] a; + input [4095:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3727_ = b[2047:0]; + 2'b1?: + _3727_ = b[4095:2048]; + default: + _3727_ = a; + endcase + endfunction + assign _1232_ = _3727_(2048'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, _1233_ }, { _1276_, _1275_ }); + assign _1234_ = _1263_ ? _1273_ : 2048'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _1292_ = _1262_ ? _1372_ : 32'hxxxxxxxx; + function [31:0] _3730_; + input [31:0] a; + input [95:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3730_ = b[31:0]; + 3'b?1?: + _3730_ = b[63:32]; + 3'b1??: + _3730_ = b[95:64]; + default: + _3730_ = a; + endcase + endfunction + assign _1293_ = _3730_(32'hxxxxxxxx, { _1294_, _1372_, _1292_ }, { _1276_, _1290_, _1275_ }); + assign _1294_ = _1269_ ? 32'hxxxxxxxx : _1364_; + function [15:0] _3732_; + input [15:0] a; + input [47:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3732_ = b[15:0]; + 3'b?1?: + _3732_ = b[31:16]; + 3'b1??: + _3732_ = b[47:32]; + default: + _3732_ = a; + endcase + endfunction + assign _1298_ = _3732_(16'hxxxx, { 16'h0000, _1299_, _1236_ }, { _1276_, _1290_, _1275_ }); + assign _1299_ = _1289_ ? 16'h0000 : 16'hxxxx; + function [2:0] _3734_; + input [2:0] a; + input [5:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3734_ = b[2:0]; + 2'b1?: + _3734_ = b[5:3]; + default: + _3734_ = a; + endcase + endfunction + assign _1300_ = _3734_(3'hx, { _1301_, _1235_ }, { _1276_, _1290_ }); + assign _1301_ = _1269_ ? 3'hx : 3'h0; + assign _1302_ = _1257_ ? 3'h0 : \receiver.state ; + assign _1303_ = _1258_ ? 3'h0 : _1302_; + assign _1304_ = _1274_ ? 3'h3 : _1303_; + assign _1305_ = _1262_ ? _1303_ : _1304_; + function [2:0] _3740_; + input [2:0] a; + input [8:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3740_ = b[2:0]; + 3'b?1?: + _3740_ = b[5:3]; + 3'b1??: + _3740_ = b[8:6]; + default: + _3740_ = a; + endcase + endfunction + assign _1306_ = _3740_(3'h0, { _1309_, _1308_, _1305_ }, { _1276_, _1290_, _1275_ }); + assign _1307_ = _1255_ ? 3'h3 : 3'h2; + function [2:0] _3742_; + input [2:0] a; + input [5:0] b; + input [1:0] s; + casez (s) // synopsys parallel_case + 2'b?1: + _3742_ = b[2:0]; + 2'b1?: + _3742_ = b[5:3]; + default: + _3742_ = a; + endcase + endfunction + assign _1308_ = _3742_(3'h0, { _1303_, _1307_ }, { _0816_, _1289_ }); + assign _1291_ = \receiver.header_index == 3'h3; + assign _1295_ = \receiver.header_index == 3'h2; + assign _1296_ = \receiver.header_index == 3'h1; + assign _1297_ = ! \receiver.header_index ; + assign _1309_ = _1269_ ? 3'h3 : 3'h1; + assign _1310_ = \receiver.rx_fire ? _1306_ : _1303_; + assign _1311_ = _1266_ ? 8'h85 : 8'hxx; + assign _1312_ = _1265_ ? 8'h81 : _1311_; + assign _1313_ = _1264_ ? 8'h84 : _1312_; + assign _1314_ = _1274_ ? _1313_ : 8'hxx; + assign _1315_ = _1262_ ? 8'hxx : _1314_; + function [7:0] _3754_; + input [7:0] a; + input [23:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3754_ = b[7:0]; + 3'b?1?: + _3754_ = b[15:8]; + 3'b1??: + _3754_ = b[23:16]; + default: + _3754_ = a; + endcase + endfunction + assign _1316_ = _3754_(8'hxx, { _1319_, _1318_, _1315_ }, { _1276_, _1290_, _1275_ }); + assign _1317_ = _1255_ ? 8'h83 : 8'hxx; + assign _1318_ = _1289_ ? _1317_ : 8'hxx; + assign _1319_ = _1269_ ? 8'h80 : 8'hxx; + assign _1320_ = _1258_ ? 1'h0 : \receiver.fault_valid ; + assign _1321_ = _1266_ ? 1'h1 : _1320_; + assign _1322_ = _1265_ ? 1'h1 : _1321_; + assign _1323_ = _1264_ ? 1'h1 : _1322_; + assign _1324_ = _1274_ ? _1323_ : _1320_; + assign _1325_ = _1262_ ? _1320_ : _1324_; + function [0:0] _3764_; + input [0:0] a; + input [2:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3764_ = b[0:0]; + 3'b?1?: + _3764_ = b[1:1]; + 3'b1??: + _3764_ = b[2:2]; + default: + _3764_ = a; + endcase + endfunction + assign _1326_ = _3764_(_1320_, { _1329_, _1328_, _1325_ }, { _1276_, _1290_, _1275_ }); + assign _1327_ = _1255_ ? 1'h1 : _1320_; + assign _1328_ = _1289_ ? _1327_ : _1320_; + assign _1289_ = \receiver.header_index == 3'h4; + assign _1290_ = \receiver.state == 3'h1; + assign _1329_ = _1269_ ? 1'h1 : _1320_; + assign _1276_ = ! \receiver.state ; + assign _1330_ = \receiver.rx_fire ? _1326_ : _1320_; + assign _1331_ = _1257_ ? 1'h0 : \receiver.frame_valid ; + assign _1332_ = _1266_ ? _1331_ : 1'h1; + assign _1333_ = _1265_ ? _1331_ : _1332_; + assign _1334_ = _1264_ ? _1331_ : _1333_; + assign _1335_ = _1274_ ? _1334_ : _1331_; + assign _1274_ = _1356_ == 32'd3; + assign _1336_ = _1262_ ? _1331_ : _1335_; + assign _1337_ = _1275_ ? _1336_ : _1331_; + assign _1275_ = \receiver.state == 3'h2; + assign _1338_ = \receiver.rx_fire ? _1337_ : _1331_; + assign _1339_ = $signed(_1270_) < 0 ? 8'hff << - _1270_ : 8'hff >> _1270_; + assign _1340_ = $signed(_1270_) < 0 ? rx_data << - _1270_ : rx_data >> _1270_; + assign _1356_ = \receiver.body_index - \receiver.declared_length ; + assign { _1341_[30:0], _1357_[0] } = _1238_[0] ? { _1239_[13:11], _1238_[29], _1239_[10:9], _1238_[26], _1239_[8:7], _1238_[23], _1239_[6:4], _1238_[19:17], _1239_[3], _1238_[15:11], _1239_[2:1], _1238_[8:7], _1239_[0], _1238_[5:1] } : { 1'h0, _1238_[31:1] }; + assign { _1342_[30:0], _1358_[0] } = _1357_[0] ? { _1240_[13:11], _1341_[28], _1240_[10:9], _1341_[25], _1240_[8:7], _1341_[22], _1240_[6:4], _1341_[18:16], _1240_[3], _1341_[14:10], _1240_[2:1], _1341_[7:6], _1240_[0], _1341_[4:0] } : { 1'h0, _1341_[30:0] }; + assign { _1343_[30:0], _1359_[0] } = _1358_[0] ? { _1241_[13:11], _1342_[28], _1241_[10:9], _1342_[25], _1241_[8:7], _1342_[22], _1241_[6:4], _1342_[18:16], _1241_[3], _1342_[14:10], _1241_[2:1], _1342_[7:6], _1241_[0], _1342_[4:0] } : { 1'h0, _1342_[30:0] }; + assign { _1344_[30:0], _1360_[0] } = _1359_[0] ? { _1242_[13:11], _1343_[28], _1242_[10:9], _1343_[25], _1242_[8:7], _1343_[22], _1242_[6:4], _1343_[18:16], _1242_[3], _1343_[14:10], _1242_[2:1], _1343_[7:6], _1242_[0], _1343_[4:0] } : { 1'h0, _1343_[30:0] }; + assign { _1345_[30:0], _1361_[0] } = _1360_[0] ? { _1243_[13:11], _1344_[28], _1243_[10:9], _1344_[25], _1243_[8:7], _1344_[22], _1243_[6:4], _1344_[18:16], _1243_[3], _1344_[14:10], _1243_[2:1], _1344_[7:6], _1243_[0], _1344_[4:0] } : { 1'h0, _1344_[30:0] }; + assign { _1346_[30:0], _1362_[0] } = _1361_[0] ? { _1244_[13:11], _1345_[28], _1244_[10:9], _1345_[25], _1244_[8:7], _1345_[22], _1244_[6:4], _1345_[18:16], _1244_[3], _1345_[14:10], _1244_[2:1], _1345_[7:6], _1244_[0], _1345_[4:0] } : { 1'h0, _1345_[30:0] }; + assign { _1347_[30:0], _1363_[0] } = _1362_[0] ? { _1245_[13:11], _1346_[28], _1245_[10:9], _1346_[25], _1245_[8:7], _1346_[22], _1245_[6:4], _1346_[18:16], _1245_[3], _1346_[14:10], _1245_[2:1], _1346_[7:6], _1245_[0], _1346_[4:0] } : { 1'h0, _1346_[30:0] }; + assign _1364_ = _1363_[0] ? { _1246_[13:11], _1347_[28], _1246_[10:9], _1347_[25], _1246_[8:7], _1347_[22], _1246_[6:4], _1347_[18:16], _1246_[3], _1347_[14:10], _1246_[2:1], _1347_[7:6], _1246_[0], _1347_[4:0] } : { 1'h0, _1347_[30:0] }; + assign { _1349_[30:0], _1365_[0] } = _1373_[0] ? { _1247_[13:11], _1348_[28], _1247_[10:9], _1348_[25], _1247_[8:7], _1348_[22], _1247_[6:4], _1348_[18:16], _1247_[3], _1348_[14:10], _1247_[2:1], _1348_[7:6], _1247_[0], _1348_[4:0] } : { 1'h0, _1348_[30:0] }; + assign { _1350_[30:0], _1366_[0] } = _1365_[0] ? { _1248_[13:11], _1349_[28], _1248_[10:9], _1349_[25], _1248_[8:7], _1349_[22], _1248_[6:4], _1349_[18:16], _1248_[3], _1349_[14:10], _1248_[2:1], _1349_[7:6], _1248_[0], _1349_[4:0] } : { 1'h0, _1349_[30:0] }; + assign { _1351_[30:0], _1367_[0] } = _1366_[0] ? { _1249_[13:11], _1350_[28], _1249_[10:9], _1350_[25], _1249_[8:7], _1350_[22], _1249_[6:4], _1350_[18:16], _1249_[3], _1350_[14:10], _1249_[2:1], _1350_[7:6], _1249_[0], _1350_[4:0] } : { 1'h0, _1350_[30:0] }; + assign { _1352_[30:0], _1368_[0] } = _1367_[0] ? { _1250_[13:11], _1351_[28], _1250_[10:9], _1351_[25], _1250_[8:7], _1351_[22], _1250_[6:4], _1351_[18:16], _1250_[3], _1351_[14:10], _1250_[2:1], _1351_[7:6], _1250_[0], _1351_[4:0] } : { 1'h0, _1351_[30:0] }; + assign { _1353_[30:0], _1369_[0] } = _1368_[0] ? { _1251_[13:11], _1352_[28], _1251_[10:9], _1352_[25], _1251_[8:7], _1352_[22], _1251_[6:4], _1352_[18:16], _1251_[3], _1352_[14:10], _1251_[2:1], _1352_[7:6], _1251_[0], _1352_[4:0] } : { 1'h0, _1352_[30:0] }; + assign { _1354_[30:0], _1370_[0] } = _1369_[0] ? { _1252_[13:11], _1353_[28], _1252_[10:9], _1353_[25], _1252_[8:7], _1353_[22], _1252_[6:4], _1353_[18:16], _1252_[3], _1353_[14:10], _1252_[2:1], _1353_[7:6], _1252_[0], _1353_[4:0] } : { 1'h0, _1353_[30:0] }; + assign { _1355_[30:0], _1371_[0] } = _1370_[0] ? { _1253_[13:11], _1354_[28], _1253_[10:9], _1354_[25], _1253_[8:7], _1354_[22], _1253_[6:4], _1354_[18:16], _1253_[3], _1354_[14:10], _1253_[2:1], _1354_[7:6], _1253_[0], _1354_[4:0] } : { 1'h0, _1354_[30:0] }; + assign _1372_ = _1371_[0] ? { _1254_[13:11], _1355_[28], _1254_[10:9], _1355_[25], _1254_[8:7], _1355_[22], _1254_[6:4], _1355_[18:16], _1254_[3], _1355_[14:10], _1254_[2:1], _1355_[7:6], _1254_[0], _1355_[4:0] } : { 1'h0, _1355_[30:0] }; + assign { _1348_[30:0], _1373_[0] } = \receiver.crc ^ rx_data; + assign _1381_ = \transmitter.index + 1'h1; + assign _1382_ = 32'd5 + \transmitter.saved_length ; + assign _1383_ = \transmitter.saved_length + 32'd4; + assign _1384_ = \transmitter.saved_length + 32'd8; + assign _1385_ = ~ { 1'h0, _1425_[30:29], _1425_[27:26], _1425_[24:23], _1425_[21:19], _1425_[15], _1425_[9:8], _1425_[5] }; + assign _1386_ = ~ { 1'h0, _1426_[30:29], _1426_[27:26], _1426_[24:23], _1426_[21:19], _1426_[15], _1426_[9:8], _1426_[5] }; + assign _1387_ = ~ { 1'h0, _1427_[30:29], _1427_[27:26], _1427_[24:23], _1427_[21:19], _1427_[15], _1427_[9:8], _1427_[5] }; + assign _1388_ = ~ { 1'h0, _1428_[30:29], _1428_[27:26], _1428_[24:23], _1428_[21:19], _1428_[15], _1428_[9:8], _1428_[5] }; + assign _1389_ = ~ { 1'h0, _1429_[30:29], _1429_[27:26], _1429_[24:23], _1429_[21:19], _1429_[15], _1429_[9:8], _1429_[5] }; + assign _1390_ = ~ { 1'h0, _1430_[30:29], _1430_[27:26], _1430_[24:23], _1430_[21:19], _1430_[15], _1430_[9:8], _1430_[5] }; + assign _1391_ = ~ { 1'h0, _1431_[30:29], _1431_[27:26], _1431_[24:23], _1431_[21:19], _1431_[15], _1431_[9:8], _1431_[5] }; + assign _1392_ = ~ { 1'h0, _1432_[30:29], _1432_[27:26], _1432_[24:23], _1432_[21:19], _1432_[15], _1432_[9:8], _1432_[5] }; + assign _1393_ = ~ { 1'h0, _1433_[30:29], _1433_[27:26], _1433_[24:23], _1433_[21:19], _1433_[15], _1433_[9:8], _1433_[5] }; + assign _1394_ = ~ { 1'h0, _1434_[30:29], _1434_[27:26], _1434_[24:23], _1434_[21:19], _1434_[15], _1434_[9:8], _1434_[5] }; + assign _1395_ = ~ { 1'h0, _1435_[30:29], _1435_[27:26], _1435_[24:23], _1435_[21:19], _1435_[15], _1435_[9:8], _1435_[5] }; + assign _1396_ = ~ { 1'h0, _1436_[30:29], _1436_[27:26], _1436_[24:23], _1436_[21:19], _1436_[15], _1436_[9:8], _1436_[5] }; + assign _1397_ = ~ { 1'h0, _1437_[30:29], _1437_[27:26], _1437_[24:23], _1437_[21:19], _1437_[15], _1437_[9:8], _1437_[5] }; + assign _1398_ = ~ { 1'h0, _1438_[30:29], _1438_[27:26], _1438_[24:23], _1438_[21:19], _1438_[15], _1438_[9:8], _1438_[5] }; + assign _1399_ = ~ { 1'h0, _1439_[30:29], _1439_[27:26], _1439_[24:23], _1439_[21:19], _1439_[15], _1439_[9:8], _1439_[5] }; + assign _1400_ = ~ { 1'h0, _1440_[30:29], _1440_[27:26], _1440_[24:23], _1440_[21:19], _1440_[15], _1440_[9:8], _1440_[5] }; + assign _1401_ = ! \transmitter.index ; + assign _1402_ = \transmitter.index == 16'h0001; + assign _1403_ = \transmitter.index == 16'h0002; + assign _1404_ = \transmitter.index == 16'h0003; + assign _1405_ = \transmitter.index == 16'h0004; + assign _1406_ = \transmitter.index == _1383_; + assign _1407_ = ! \transmitter.saved_length ; + assign _1408_ = \transmitter.index == _1384_; + assign _1409_ = \transmitter.index >= 32'd5; + assign _1410_ = \transmitter.index <= _1383_; + assign _1411_ = tx_start && _1413_; + assign _1412_ = \transmitter.active && tx_ready; + assign _1413_ = ! \transmitter.active ; + assign _1414_ = \transmitter.index < _1382_; + assign _1415_ = ~ _1450_; + assign _1416_ = ~ _1458_; + assign _1417_ = _1408_ ? 1'h1 : 1'h0; + assign _1418_ = _1408_ ? 1'h0 : 1'hx; + assign _1419_ = _1412_ ? _1418_ : 1'hx; + assign _1420_ = _1411_ ? 1'h1 : _1419_; + function [7:0] _3842_; + input [7:0] a; + input [23:0] b; + input [2:0] s; + casez (s) // synopsys parallel_case + 3'b??1: + _3842_ = b[7:0]; + 3'b?1?: + _3842_ = b[15:8]; + 3'b1??: + _3842_ = b[23:16]; + default: + _3842_ = a; + endcase + endfunction + assign _1379_ = _3842_(\transmitter.saved_crc [31:24], { \transmitter.saved_crc [7:0], \transmitter.saved_crc [15:8], \transmitter.saved_crc [23:16] }, { _1423_, _1422_, _1421_ }); + assign _1421_ = _1442_ == 32'd2; + assign _1422_ = _1442_ == 32'd1; + assign _1423_ = ! _1442_; + assign _1378_ = _1414_ ? _1424_ : _1379_; + assign _1377_ = _1405_ ? \transmitter.saved_length [15:8] : _1378_; + assign _1376_ = _1404_ ? \transmitter.saved_length [7:0] : _1377_; + assign _1375_ = _1403_ ? \transmitter.saved_status : _1376_; + assign _1374_ = _1402_ ? 8'h01 : _1375_; + assign \transmitter.tx_data = _1401_ ? 8'h5a : _1374_; + wire [543:0] _5658_ = \transmitter.saved_payload ; + assign _1424_ = _5658_[$signed({ _1380_[31:3], 3'h0 }) +: 8]; + assign { _1441_[31:29], _1380_[31:3] } = \transmitter.index - 32'd5; + assign _1442_ = { _1441_[31:29], _1380_[31:3] } - \transmitter.saved_length ; + assign { _1427_[30:0], _1444_[0] } = _1443_[0] ? { _1386_[13:11], _1426_[28], _1386_[10:9], _1426_[25], _1386_[8:7], _1426_[22], _1386_[6:4], _1426_[18:16], _1386_[3], _1426_[14:10], _1386_[2:1], _1426_[7:6], _1386_[0], _1426_[4:0] } : { 1'h0, _1426_[30:0] }; + assign { _1428_[30:0], _1445_[0] } = _1444_[0] ? { _1387_[13:11], _1427_[28], _1387_[10:9], _1427_[25], _1387_[8:7], _1427_[22], _1387_[6:4], _1427_[18:16], _1387_[3], _1427_[14:10], _1387_[2:1], _1427_[7:6], _1387_[0], _1427_[4:0] } : { 1'h0, _1427_[30:0] }; + assign { _1429_[30:0], _1446_[0] } = _1445_[0] ? { _1388_[13:11], _1428_[28], _1388_[10:9], _1428_[25], _1388_[8:7], _1428_[22], _1388_[6:4], _1428_[18:16], _1388_[3], _1428_[14:10], _1388_[2:1], _1428_[7:6], _1388_[0], _1428_[4:0] } : { 1'h0, _1428_[30:0] }; + assign { _1430_[30:0], _1447_[0] } = _1446_[0] ? { _1389_[13:11], _1429_[28], _1389_[10:9], _1429_[25], _1389_[8:7], _1429_[22], _1389_[6:4], _1429_[18:16], _1389_[3], _1429_[14:10], _1389_[2:1], _1429_[7:6], _1389_[0], _1429_[4:0] } : { 1'h0, _1429_[30:0] }; + assign { _1431_[30:0], _1448_[0] } = _1447_[0] ? { _1390_[13:11], _1430_[28], _1390_[10:9], _1430_[25], _1390_[8:7], _1430_[22], _1390_[6:4], _1430_[18:16], _1390_[3], _1430_[14:10], _1390_[2:1], _1430_[7:6], _1390_[0], _1430_[4:0] } : { 1'h0, _1430_[30:0] }; + assign { _1432_[30:0], _1449_[0] } = _1448_[0] ? { _1391_[13:11], _1431_[28], _1391_[10:9], _1431_[25], _1391_[8:7], _1431_[22], _1391_[6:4], _1431_[18:16], _1391_[3], _1431_[14:10], _1391_[2:1], _1431_[7:6], _1391_[0], _1431_[4:0] } : { 1'h0, _1431_[30:0] }; + assign { _1434_[30:0], _1451_[0] } = _1461_[0] ? { _1393_[13:11], _1433_[28], _1393_[10:9], _1433_[25], _1393_[8:7], _1433_[22], _1393_[6:4], _1433_[18:16], _1393_[3], _1433_[14:10], _1393_[2:1], _1433_[7:6], _1393_[0], _1433_[4:0] } : { 1'h0, _1433_[30:0] }; + assign { _1435_[30:0], _1452_[0] } = _1451_[0] ? { _1394_[13:11], _1434_[28], _1394_[10:9], _1434_[25], _1394_[8:7], _1434_[22], _1394_[6:4], _1434_[18:16], _1394_[3], _1434_[14:10], _1394_[2:1], _1434_[7:6], _1394_[0], _1434_[4:0] } : { 1'h0, _1434_[30:0] }; + assign { _1436_[30:0], _1453_[0] } = _1452_[0] ? { _1395_[13:11], _1435_[28], _1395_[10:9], _1435_[25], _1395_[8:7], _1435_[22], _1395_[6:4], _1435_[18:16], _1395_[3], _1435_[14:10], _1395_[2:1], _1435_[7:6], _1395_[0], _1435_[4:0] } : { 1'h0, _1435_[30:0] }; + assign { _1437_[30:0], _1454_[0] } = _1453_[0] ? { _1396_[13:11], _1436_[28], _1396_[10:9], _1436_[25], _1396_[8:7], _1436_[22], _1396_[6:4], _1436_[18:16], _1396_[3], _1436_[14:10], _1396_[2:1], _1436_[7:6], _1396_[0], _1436_[4:0] } : { 1'h0, _1436_[30:0] }; + assign { _1426_[30:0], _1443_[0] } = _1460_[0] ? { _1385_[13:11], _1425_[28], _1385_[10:9], _1425_[25], _1385_[8:7], _1425_[22], _1385_[6:4], _1425_[18:16], _1385_[3], _1425_[14:10], _1385_[2:1], _1425_[7:6], _1385_[0], _1425_[4:0] } : { 1'h0, _1425_[30:0] }; + assign _1450_ = _1449_[0] ? { _1392_[13:11], _1432_[28], _1392_[10:9], _1432_[25], _1392_[8:7], _1432_[22], _1392_[6:4], _1432_[18:16], _1392_[3], _1432_[14:10], _1392_[2:1], _1432_[7:6], _1392_[0], _1432_[4:0] } : { 1'h0, _1432_[30:0] }; + assign { _1438_[30:0], _1455_[0] } = _1454_[0] ? { _1397_[13:11], _1437_[28], _1397_[10:9], _1437_[25], _1397_[8:7], _1437_[22], _1397_[6:4], _1437_[18:16], _1397_[3], _1437_[14:10], _1397_[2:1], _1437_[7:6], _1397_[0], _1437_[4:0] } : { 1'h0, _1437_[30:0] }; + assign { _1439_[30:0], _1456_[0] } = _1455_[0] ? { _1398_[13:11], _1438_[28], _1398_[10:9], _1438_[25], _1398_[8:7], _1438_[22], _1398_[6:4], _1438_[18:16], _1398_[3], _1438_[14:10], _1398_[2:1], _1438_[7:6], _1398_[0], _1438_[4:0] } : { 1'h0, _1438_[30:0] }; + assign { _1440_[30:0], _1457_[0] } = _1456_[0] ? { _1399_[13:11], _1439_[28], _1399_[10:9], _1439_[25], _1399_[8:7], _1439_[22], _1399_[6:4], _1439_[18:16], _1399_[3], _1439_[14:10], _1399_[2:1], _1439_[7:6], _1399_[0], _1439_[4:0] } : { 1'h0, _1439_[30:0] }; + assign _1458_ = _1457_[0] ? { _1400_[13:11], _1440_[28], _1400_[10:9], _1440_[25], _1400_[8:7], _1440_[22], _1400_[6:4], _1440_[18:16], _1400_[3], _1440_[14:10], _1400_[2:1], _1440_[7:6], _1400_[0], _1440_[4:0] } : { 1'h0, _1440_[30:0] }; + assign _1459_ = _1407_ ? 32'd0 : _1416_; + assign { _1433_[30:0], _1461_[0] } = \transmitter.payload_crc_work ^ \transmitter.tx_data ; + assign { _1425_[30:0], _1460_[0] } = \transmitter.envelope_crc_work ^ \transmitter.tx_data ; + assign _1462_ = \receiver.frame_payload [15:8] >= 32'd1; + assign _1463_ = \receiver.frame_payload [63:32] >= 32'd65536; + assign _1464_ = \receiver.frame_payload [95:64] >= 32'd65536; + assign _1465_ = \receiver.frame_payload [375:344] >= 32'd65536; + assign _1466_ = \receiver.frame_payload [655:624] >= 32'd65536; + assign _1467_ = \receiver.frame_payload [687:656] >= 32'd65536; + assign _1468_ = \receiver.frame_payload [279:272] > 32'd1; + assign _1469_ = \receiver.frame_payload [215:208] > 32'd1; + assign _1470_ = \receiver.frame_payload [383:376] > 32'd1; + assign _1471_ = \receiver.frame_payload [519:512] > 32'd1; + assign _1472_ = \receiver.frame_payload [351:344] > 32'd1; + assign _1473_ = \receiver.frame_payload [487:480] > 32'd1; + assign _1474_ = \receiver.frame_payload [695:688] > 32'd1; + assign _1475_ = \receiver.frame_payload [623:616] > 32'd1; + assign _1476_ = \receiver.frame_payload [23:16] > 32'd1; + assign _1477_ = \receiver.frame_payload [103:96] > 32'd1; + assign _1478_ = \receiver.frame_payload [143:112] > _2722_; + assign _1479_ = \receiver.frame_payload [207:176] > _2722_; + assign _1480_ = \receiver.frame_payload [175:144] > _2723_; + assign _1481_ = \receiver.frame_payload [63:32] > 32'd65533; + assign _1482_ = \receiver.frame_payload [175:144] > _2722_; + assign _1483_ = _2731_[7:0] > 32'd1; + assign _1484_ = \receiver.frame_payload [7:0] <= 32'd1; + assign rx_ready = \receiver.rx_ready && lane_enable; + assign _1485_ = _1555_ && _1636_; + assign _1486_ = _1556_ && _1637_; + assign _1487_ = _1557_ && _1638_; + assign _1488_ = _1558_ && _1639_; + assign _1489_ = _1559_ && _1640_; + assign _1490_ = _1560_ && _1641_; + assign _1491_ = _1561_ && _1642_; + assign _1492_ = _1562_ && _1643_; + assign _1493_ = pres_c && _1651_; + assign _1494_ = _0872_ && _1563_; + assign _1495_ = pres_b && pres_c; + assign _1496_ = _1495_ && _1653_; + assign _1497_ = pres_b && _1563_; + assign _1498_ = _1564_ && pres_c; + assign _1499_ = _1564_ && _1563_; + assign _1500_ = \transmitter.done_pulse && capture_result_crc; + assign _1501_ = \field_encoder.done_pulse && _0874_; + assign _1502_ = \field_encoder.done_pulse && _0875_; + assign _1503_ = pres_b && _1654_; + assign _1504_ = \field_encoder.done_pulse && _0876_; + assign _1505_ = \field_encoder.done_pulse && _0877_; + assign _1506_ = \adapter.done_pulse && _0878_; + assign _1507_ = \adapter.done_pulse && _0879_; + assign _1508_ = \adapter.done_pulse && _0880_; + assign _1509_ = \adapter.done_pulse && _0881_; + assign _1510_ = \adapter.done_pulse && _0882_; + assign _1511_ = \adapter.done_pulse && _0883_; + assign _1512_ = event_valid && \receiver.frame_ready ; + assign _1513_ = _1484_ && _1462_; + assign _1514_ = _1665_ && _1666_; + assign _1515_ = _1514_ && _1667_; + assign _1516_ = _1515_ && _1668_; + assign _1517_ = _1516_ && _1669_; + assign _1518_ = _1517_ && _1670_; + assign _1519_ = _1518_ && _1671_; + assign _1520_ = _0888_ && _1672_; + assign _1521_ = _0889_ && _1673_; + assign _1522_ = _0890_ && _1674_; + assign _1523_ = _1593_ && _1675_; + assign _1524_ = _0892_ && _1676_; + assign _1525_ = _0888_ && _1576_; + assign _1526_ = _1593_ && _1595_; + assign _1527_ = _0892_ && _1598_; + assign _1528_ = _0892_ && _1475_; + assign _1529_ = _1599_ && _1600_; + assign _1530_ = _0890_ && _1583_; + assign _1531_ = state_valid && _1601_; + assign _1532_ = _0169_ && _0888_; + assign _1533_ = \receiver.frame_payload [279:272] && _1681_; + assign _1534_ = _0169_ && _1593_; + assign _1535_ = _0873_ && _1481_; + assign _1536_ = _0893_ && _1611_; + assign _1537_ = _0894_ && _1614_; + assign _1538_ = _0895_ && _1615_; + assign _1539_ = _0169_ && _0892_; + assign _1540_ = _0896_ && _1625_; + assign _1541_ = _0894_ && _1628_; + assign _1542_ = _0897_ && _1629_; + assign _1543_ = \receiver.frame_payload [695:688] && _1642_; + assign _1544_ = _1413_ && _1566_; + assign \receiver.frame_ready = _1544_ && _0898_; + assign _1545_ = \receiver.frame_ready && _1567_; + assign lane_enable = _1545_ && _1066_; + assign _1546_ = _1568_ && _1698_; + assign _1547_ = _0392_ && \receiver.frame_payload [487:480]; + assign _1548_ = _1547_ && _2735_; + assign _1549_ = _1556_ && _0899_; + assign _1550_ = _1559_ && _0900_; + assign _1551_ = _0398_ && _1569_; + assign _1552_ = _1551_ && _0890_; + assign _1553_ = _1551_ && _0889_; + assign _1554_ = _0227_ && _0888_; + assign \receiver.rx_valid = rx_valid && lane_enable; + assign _1555_ = ! \receiver.frame_payload [279:272]; + assign _1556_ = ! \receiver.frame_payload [215:208]; + assign _1557_ = ! \receiver.frame_payload [383:376]; + assign _1558_ = ! \receiver.frame_payload [519:512]; + assign _1559_ = ! \receiver.frame_payload [351:344]; + assign _1560_ = ! \receiver.frame_payload [487:480]; + assign _1561_ = ! \receiver.frame_payload [695:688]; + assign _1562_ = ! \receiver.frame_payload [623:616]; + assign _1563_ = ! pres_c; + assign _1564_ = ! pres_b; + assign _1565_ = ! pres_a; + assign _1566_ = ! tx_start; + assign _1567_ = ! \adapter.busy ; + assign _1568_ = ! _2731_[7:0]; + assign _1569_ = ! _0359_; + assign _1570_ = \receiver.busy || \transmitter.active ; + assign _1571_ = _1570_ || tx_start; + assign _1572_ = _1571_ || event_valid; + assign _1573_ = _1572_ || result_pending; + assign _1574_ = _1573_ || _1635_; + assign _1575_ = _1574_ || \adapter.busy ; + assign busy = _1575_ || \field_encoder.busy ; + assign _1576_ = _1468_ || _1485_; + assign _1577_ = _1469_ || _1486_; + assign _1578_ = _1470_ || _1487_; + assign _1579_ = _1471_ || _1488_; + assign _1580_ = _1472_ || _1489_; + assign _1581_ = _1473_ || _1490_; + assign _1582_ = _1474_ || _1491_; + assign _1583_ = _1475_ || _1492_; + assign _1584_ = \field_encoder.fault || _1652_; + assign _1585_ = \adapter.fault || _1657_; + assign _1586_ = \adapter.fault || _1658_; + assign _1587_ = _1663_ || _1664_; + assign _1588_ = _1520_ || _1521_; + assign _1589_ = _1588_ || _1522_; + assign _1590_ = _1589_ || _1523_; + assign _1591_ = _1590_ || _1524_; + assign _1592_ = _0871_ || _0873_; + assign _1593_ = _1592_ || _0891_; + assign _1594_ = _1577_ || _1578_; + assign _1595_ = _1594_ || _1579_; + assign _1596_ = _1577_ || _1580_; + assign _1597_ = _1596_ || _1581_; + assign _1598_ = _1597_ || _1582_; + assign _1599_ = _0889_ || _0890_; + assign _1600_ = _1597_ || _1530_; + assign _1601_ = _1679_ || _1680_; + assign _1602_ = _1463_ || _1464_; + assign _1603_ = _1478_ || _1479_; + assign _1604_ = _1603_ || _1480_; + assign _1605_ = _1465_ || _1535_; + assign _1606_ = _1469_ || _1470_; + assign _1607_ = _1606_ || _1471_; + assign _1608_ = _1607_ || _1486_; + assign _1609_ = _1608_ || _1487_; + assign _1610_ = _1609_ || _1488_; + assign _1611_ = _1682_ || _1683_; + assign _1612_ = _1536_ || _1537_; + assign _1613_ = _1612_ || _1538_; + assign _1614_ = _1684_ || _1685_; + assign _1615_ = _1686_ || _1687_; + assign _1616_ = _1478_ || _1482_; + assign _1617_ = _1616_ || _1479_; + assign _1618_ = _1469_ || _1472_; + assign _1619_ = _1618_ || _1473_; + assign _1620_ = _1619_ || _1486_; + assign _1621_ = _1620_ || _1489_; + assign _1622_ = _1621_ || _1490_; + assign _1623_ = _1622_ || _1474_; + assign _1624_ = _1623_ || _1491_; + assign _1625_ = _1688_ || _1689_; + assign _1626_ = _1540_ || _1541_; + assign _1627_ = _1626_ || _1542_; + assign _1628_ = _1690_ || _1691_; + assign _1629_ = _1692_ || _1693_; + assign _1630_ = _1466_ || _1467_; + assign _1631_ = _1696_ || _1697_; + assign _1632_ = _1622_ || _1483_; + assign _1633_ = _1632_ || _1546_; + assign _1634_ = _1549_ || _1550_; + assign event_valid = \receiver.frame_valid || \receiver.fault_valid ; + assign _1635_ = | compute_state; + assign _1636_ = | \receiver.frame_payload [407:280]; + assign _1637_ = | \receiver.frame_payload [343:216]; + assign _1638_ = | \receiver.frame_payload [511:384]; + assign _1639_ = | \receiver.frame_payload [647:520]; + assign _1640_ = | \receiver.frame_payload [479:352]; + assign _1641_ = | \receiver.frame_payload [615:488]; + assign _1642_ = | \receiver.frame_payload [823:696]; + assign _1643_ = | \receiver.frame_payload [751:624]; + assign _1644_ = | $signed(_0436_); + assign _1645_ = | $signed(_0029_); + assign _1646_ = | $signed(n_writes); + assign _1647_ = | $signed(_0128_); + assign _1648_ = | $signed(_0335_); + assign _1649_ = | $signed(_0435_); + assign _1650_ = | $signed(n_deferred); + assign _1651_ = val_c != \adapter.result ; + assign _1652_ = \field_encoder.result != val_a; + assign _1653_ = val_b != val_c; + assign _1654_ = val_b != \field_encoder.result ; + assign _1655_ = \field_encoder.result != val_b; + assign _1656_ = \field_encoder.result != val_c; + assign _1657_ = \adapter.result != 128'h00000000000000000000000000000001; + assign _1658_ = \adapter.result != result_value; + assign _1659_ = | \receiver.frame_length ; + assign _1660_ = \receiver.frame_length != 16'h0007; + assign _1661_ = \receiver.frame_payload [23:16] != 8'h01; + assign _1662_ = \receiver.frame_length != 16'h0008; + assign _1663_ = \receiver.frame_payload [31:0] != staged_txn_id; + assign _1664_ = \receiver.frame_payload [63:32] != staged_result_crc; + assign _1665_ = \receiver.frame_opcode != 8'h01; + assign _1666_ = \receiver.frame_opcode != 8'h02; + assign _1667_ = \receiver.frame_opcode != 8'h03; + assign _1668_ = \receiver.frame_opcode != 8'h04; + assign _1669_ = \receiver.frame_opcode != 8'h05; + assign _1670_ = \receiver.frame_opcode != 8'h06; + assign _1671_ = \receiver.frame_opcode != 8'h07; + assign _1672_ = \receiver.frame_length != 16'h0033; + assign _1673_ = \receiver.frame_length != 16'h004d; + assign _1674_ = \receiver.frame_length != 16'h005e; + assign _1675_ = \receiver.frame_length != 16'h0051; + assign _1676_ = \receiver.frame_length != 16'h0067; + assign _1677_ = | \receiver.frame_payload [111:104]; + assign _1678_ = \receiver.frame_payload [103:96] != active_profile; + assign _1679_ = \receiver.frame_payload [63:32] != committed_pc; + assign _1680_ = \receiver.frame_payload [95:64] != committed_fp; + assign _1681_ = \receiver.frame_payload [407:280] != \receiver.frame_payload [271:144]; + assign _1682_ = \receiver.frame_payload [215:208] != \receiver.frame_payload [383:376]; + assign _1683_ = \receiver.frame_payload [343:216] != \receiver.frame_payload [511:384]; + assign _1684_ = \receiver.frame_payload [215:208] != \receiver.frame_payload [519:512]; + assign _1685_ = \receiver.frame_payload [343:216] != \receiver.frame_payload [647:520]; + assign _1686_ = \receiver.frame_payload [383:376] != \receiver.frame_payload [519:512]; + assign _1687_ = \receiver.frame_payload [511:384] != \receiver.frame_payload [647:520]; + assign _1688_ = \receiver.frame_payload [215:208] != \receiver.frame_payload [351:344]; + assign _1689_ = \receiver.frame_payload [343:216] != \receiver.frame_payload [479:352]; + assign _1690_ = \receiver.frame_payload [215:208] != \receiver.frame_payload [487:480]; + assign _1691_ = \receiver.frame_payload [343:216] != \receiver.frame_payload [615:488]; + assign _1692_ = \receiver.frame_payload [351:344] != \receiver.frame_payload [487:480]; + assign _1693_ = \receiver.frame_payload [479:352] != \receiver.frame_payload [615:488]; + assign _1694_ = | \receiver.frame_payload [343:216]; + assign _1695_ = \receiver.frame_payload [623:616] != _1694_; + assign _1696_ = | \receiver.frame_payload [655:624]; + assign _1697_ = | \receiver.frame_payload [687:656]; + assign _1698_ = | _2732_; + assign _0238_ = _0169_ ? \receiver.frame_payload [479:352] : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _0237_ = _0169_ ? \receiver.frame_payload [343:216] : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _0144_ = _1512_ ? _0153_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _0143_ = _1512_ ? _0152_ : 32'hxxxxxxxx; + assign _0289_ = _0169_ ? _0299_ : addr_c; + assign _0049_ = _1512_ ? _0057_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _0048_ = _1512_ ? _0056_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _0089_ = _1512_ ? _0098_ : 32'hxxxxxxxx; + assign _0044_ = _1512_ ? _0054_ : 32'hxxxxxxxx; + assign _0045_ = _1512_ ? _0055_ : 32'hxxxxxxxx; + assign _0288_ = _0169_ ? _0298_ : addr_b; + assign _0137_ = _1512_ ? _0146_ : 32'hxxxxxxxx; + assign _0064_[71:48] = _1650_ ? deferred_local[31:8] : addr_b[23:0]; + assign _0064_[39:16] = _1650_ ? deferred_target[31:8] : addr_a[23:0]; + assign _0064_[175:144] = _1650_ ? addr_c : 32'd0; + assign _0331_ = _0169_ ? _0339_ : addr_a; + assign _0064_[7:0] = _1650_ ? 8'h01 : 8'h00; + assign _0315_[175:168] = _1647_ ? 8'h03 : _0064_[175:168]; + assign _0315_[207:176] = _1647_ ? addr_a : 32'd0; + assign _0336_ = _1647_ ? 32'd47 : _0065_; + assign _0315_[167:160] = _1647_ ? 8'h00 : _0064_[167:160]; + assign _0315_[159:32] = _1647_ ? _0135_ : _0064_[159:32]; + assign _0315_[31:0] = _1647_ ? _0134_ : _0064_[31:0]; + assign _0315_[271:208] = _1647_ ? { addr_c, addr_b } : 64'h0000000000000000; + assign _1699_ = _1563_ ? 32'd1 : n_writes; + assign _1700_ = _1493_ ? 32'hxxxxxxxx : _1699_; + assign _1701_ = \adapter.fault ? 32'hxxxxxxxx : _1700_; + assign _1702_ = _1511_ ? _1701_ : 32'hxxxxxxxx; + assign _1703_ = _1510_ ? 32'hxxxxxxxx : _1702_; + assign _1704_ = _1509_ ? 32'hxxxxxxxx : _1703_; + assign _1705_ = _1508_ ? 32'hxxxxxxxx : _1704_; + assign _1706_ = _1507_ ? 32'hxxxxxxxx : _1705_; + assign _1707_ = _1506_ ? 32'hxxxxxxxx : _1706_; + assign _1708_ = _1505_ ? 32'hxxxxxxxx : _1707_; + assign _1709_ = _1504_ ? 32'hxxxxxxxx : _1708_; + assign _1710_ = _1502_ ? 32'hxxxxxxxx : _1709_; + assign _1711_ = _1501_ ? 32'hxxxxxxxx : _1710_; + assign _1712_ = abort ? 32'hxxxxxxxx : _1711_; + assign _0128_ = rst_n ? _1712_ : 32'hxxxxxxxx; + assign _0135_ = _1563_ ? \adapter.result : write_value; + assign _0134_ = _1563_ ? addr_c : write_address; + assign _0229_ = _0169_ ? _2732_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _0126_ = _1493_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0135_; + assign _0125_ = _1493_ ? 32'hxxxxxxxx : _0134_; + assign _0117_ = _1493_ ? 32'hxxxxxxxx : _0128_; + assign _0115_ = \adapter.fault ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0126_; + assign _0114_ = \adapter.fault ? 32'hxxxxxxxx : _0125_; + assign _0108_ = \adapter.fault ? 32'hxxxxxxxx : _0117_; + assign _0106_ = _1511_ ? _0115_ : _0144_; + assign _0105_ = _1511_ ? _0114_ : _0143_; + assign _0099_ = _1511_ ? _0108_ : _0137_; + assign _0239_ = _0169_ ? \receiver.frame_payload [615:488] : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _0233_ = _0169_ ? \receiver.frame_payload [487:480] : 8'hxx; + assign _0039_ = _1511_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0049_; + assign _0038_ = _1511_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0048_; + assign _0080_ = _1511_ ? 32'hxxxxxxxx : _0089_; + assign _0036_ = _1511_ ? 32'hxxxxxxxx : _0044_; + assign _0037_ = _1511_ ? 32'hxxxxxxxx : _0045_; + assign _0232_ = _0169_ ? \receiver.frame_payload [351:344] : 8'hxx; + assign _0090_ = _1510_ ? 32'd1 : _0099_; + assign _0097_ = _1510_ ? \adapter.result : _0106_; + assign _0096_ = _1510_ ? _2725_ : _0105_; + assign _0025_ = _1510_ ? _0009_ : _0039_; + assign _0024_ = _1510_ ? _0008_ : _0038_; + assign _0231_ = _0169_ ? \receiver.frame_payload [215:208] : 8'hxx; + assign _0071_ = _1510_ ? 32'hxxxxxxxx : _0080_; + assign _0030_ = _1510_ ? 32'hxxxxxxxx : _0036_; + assign _0031_ = _1510_ ? 32'hxxxxxxxx : _0037_; + assign _0311_ = _1631_ ? 8'h02 : 8'h00; + assign _0088_ = _1509_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0097_; + assign _0087_ = _1509_ ? 32'hxxxxxxxx : _0096_; + assign _0017_ = _1509_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0025_; + assign _0016_ = _1509_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0024_; + assign _0387_ = _1631_ ? 8'h8f : _0168_; + assign _0060_ = _1509_ ? 32'hxxxxxxxx : _0071_; + assign _0022_ = _1509_ ? 32'hxxxxxxxx : _0030_; + assign _0023_ = _1509_ ? 32'hxxxxxxxx : _0031_; + assign _0081_ = _1509_ ? 32'hxxxxxxxx : _0090_; + assign _0008_ = _1565_ ? \adapter.result : solved_a; + assign _0009_ = _1565_ ? solved_b : \adapter.result ; + assign _0072_ = _1508_ ? 32'd1 : _0081_; + assign _0079_ = _1508_ ? \adapter.result : _0088_; + assign _0078_ = _1508_ ? _2725_ : _0087_; + assign _0450_ = _1508_ ? _0009_ : _0017_; + assign _0449_ = _1508_ ? _0008_ : _0016_; + assign _0388_ = _1631_ ? 1'h0 : _0169_; + assign _0301_ = _1543_ ? 8'h03 : _0311_; + assign _0378_ = _1543_ ? 8'h8b : _0387_; + assign _0052_ = _1508_ ? 32'hxxxxxxxx : _0060_; + assign _0014_ = _1508_ ? 32'hxxxxxxxx : _0022_; + assign _0015_ = _1508_ ? 32'hxxxxxxxx : _0023_; + assign _0234_[15:8] = _1650_ ? deferred_target[7:0] : 8'h01; + assign _0234_[111:80] = _1650_ ? addr_a : 32'd0; + assign _0234_[71:48] = _1650_ ? deferred_local[31:8] : 24'h000000; + assign _0250_ = _1650_ ? 32'd35 : 32'd19; + assign _0213_[175:168] = _1646_ ? 8'h01 : _0064_[175:168]; + assign _0214_ = _1646_ ? 32'd39 : _0250_; + assign _0120_[207:176] = _1646_ ? addr_a : 32'd0; + assign _0120_[167:160] = _1646_ ? 8'h00 : _0064_[167:160]; + assign _0379_ = _1543_ ? 1'h0 : _0388_; + assign _0213_[159:32] = _1646_ ? write_value : { _0064_[159:112], _0234_[111:80], _0064_[7:0], _0234_[71:48], _0064_[47:32] }; + assign _0213_[31:0] = _1646_ ? write_address : { _0064_[31:16], _0234_[15:8], _0064_[7:0] }; + assign _0375_ = _1561_ ? 8'h8b : _0168_; + assign _0376_ = _1561_ ? 1'h0 : _0169_; + assign _0070_ = _1507_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0079_; + assign _0069_ = _1507_ ? 32'hxxxxxxxx : _0078_; + assign _0042_ = _1507_ ? 32'hxxxxxxxx : _0052_; + assign _0004_ = _1507_ ? 32'hxxxxxxxx : _0014_; + assign _0005_ = _1507_ ? 32'hxxxxxxxx : _0015_; + assign _0061_ = _1507_ ? 32'hxxxxxxxx : _0072_; + assign _0347_ = _1561_ ? 1'h0 : 1'h1; + assign _0372_ = _1630_ ? 8'h95 : _0375_; + assign _0059_ = _1506_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0070_; + assign _0058_ = _1506_ ? 32'hxxxxxxxx : _0069_; + assign _0034_ = _1506_ ? 32'hxxxxxxxx : _0042_; + assign _0447_ = _1506_ ? 32'hxxxxxxxx : _0004_; + assign _0448_ = _1506_ ? 32'hxxxxxxxx : _0005_; + assign _0373_ = _1630_ ? 1'h0 : _0376_; + assign _0053_ = _1506_ ? 32'hxxxxxxxx : _0061_; + assign _0120_[175:168] = _1646_ ? 8'h03 : _0064_[175:168]; + assign _0121_ = _1646_ ? 32'd47 : _0065_; + assign _0120_[159:32] = _1646_ ? write_value : _0064_[159:32]; + assign _0120_[31:0] = _1646_ ? write_address : _0064_[31:0]; + assign _0120_[271:208] = _1646_ ? { addr_c, addr_b } : 64'h0000000000000000; + assign _0437_ = _1656_ ? 32'hxxxxxxxx : proposed_fp; + assign _0438_ = _1656_ ? 32'hxxxxxxxx : proposed_pc; + assign _0340_ = _1630_ ? 1'h0 : _0347_; + assign _0429_ = \field_encoder.fault ? 32'hxxxxxxxx : _0437_; + assign _0430_ = \field_encoder.fault ? 32'hxxxxxxxx : _0438_; + assign _0421_ = _1505_ ? _0429_ : _0447_; + assign _0422_ = _1505_ ? _0430_ : _0448_; + assign _0332_ = _1713_ ? _0340_ : 1'h0; + assign _0051_ = _1505_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0059_; + assign _0050_ = _1505_ ? 32'hxxxxxxxx : _0058_; + assign _0028_ = _1505_ ? 32'hxxxxxxxx : _0034_; + assign _0370_ = _1713_ ? _0373_ : _0379_; + assign _0043_ = _1505_ ? 32'hxxxxxxxx : _0053_; + assign _0369_ = _1713_ ? _0372_ : _0378_; + assign _0041_ = _1504_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0051_; + assign _0040_ = _1504_ ? 32'hxxxxxxxx : _0050_; + assign _0020_ = _1504_ ? 32'hxxxxxxxx : _0028_; + assign _0291_ = _1713_ ? 8'h00 : _0301_; + assign _0035_ = _1504_ ? 32'hxxxxxxxx : _0043_; + assign _0064_[111:80] = _1650_ ? addr_a : addr_c; + assign _0064_[47:40] = _1650_ ? deferred_local[7:0] : addr_a[31:24]; + assign _0064_[15:8] = _1650_ ? deferred_target[7:0] : 8'h03; + assign _0064_[143:112] = _1650_ ? addr_b : 32'd0; + assign _0065_ = _1650_ ? 32'd35 : 32'd27; + assign _0064_[79:72] = _1650_ ? 8'h03 : addr_b[31:24]; + assign _0046_[175:168] = _1645_ ? 8'h03 : _0064_[175:168]; + assign _0046_[207:176] = _1645_ ? addr_a : 32'd0; + assign _0047_ = _1645_ ? 32'd47 : _0065_; + assign _0046_[167:160] = _1645_ ? 8'h00 : _0064_[167:160]; + assign _0046_[159:32] = _1645_ ? _0033_ : _0064_[159:32]; + assign _0046_[31:0] = _1645_ ? _0032_ : _0064_[31:0]; + assign _0046_[271:208] = _1645_ ? { addr_c, addr_b } : 64'h0000000000000000; + assign _0033_ = _1564_ ? \field_encoder.result : write_value; + assign _0032_ = _1564_ ? addr_b : write_address; + assign _1714_ = _1564_ ? 32'd1 : n_writes; + assign _1715_ = _1503_ ? 32'hxxxxxxxx : _1714_; + assign _1716_ = \field_encoder.fault ? 32'hxxxxxxxx : _1715_; + assign _1717_ = _1502_ ? _1716_ : 32'hxxxxxxxx; + assign _1718_ = _1501_ ? 32'hxxxxxxxx : _1717_; + assign _1719_ = abort ? 32'hxxxxxxxx : _1718_; + assign _0029_ = rst_n ? _1719_ : 32'hxxxxxxxx; + assign _0027_ = _1503_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0033_; + assign _0026_ = _1503_ ? 32'hxxxxxxxx : _0032_; + assign _0021_ = _1503_ ? 32'hxxxxxxxx : _0029_; + assign _0281_ = _1695_ ? 8'h01 : _0291_; + assign _0019_ = \field_encoder.fault ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0027_; + assign _0018_ = \field_encoder.fault ? 32'hxxxxxxxx : _0026_; + assign _0013_ = \field_encoder.fault ? 32'hxxxxxxxx : _0021_; + assign _0011_ = _1502_ ? _0019_ : _0041_; + assign _0010_ = _1502_ ? _0018_ : _0040_; + assign _0003_ = _1502_ ? _0013_ : _0035_; + assign _0366_ = _1695_ ? 8'h8f : _0369_; + assign _0012_ = _1502_ ? 32'hxxxxxxxx : _0020_; + assign _0006_[111:80] = _1649_ ? addr_a : addr_c; + assign _0006_[47:40] = _1649_ ? _0433_[7:0] : addr_a[31:24]; + assign _0006_[15:8] = _1649_ ? _0434_[7:0] : 8'h03; + assign _0006_[143:112] = _1649_ ? addr_b : 32'd0; + assign _0007_ = _1649_ ? 32'd35 : 32'd27; + assign _0006_[79:72] = _1649_ ? 8'h03 : addr_b[31:24]; + assign _0006_[71:48] = _1649_ ? _0433_[31:8] : addr_b[23:0]; + assign _0006_[39:16] = _1649_ ? _0434_[31:8] : addr_a[23:0]; + assign _0006_[175:144] = _1649_ ? addr_c : 32'd0; + assign _0006_[7:0] = _1649_ ? 8'h01 : 8'h00; + assign _0439_[175:168] = _1644_ ? 8'h03 : _0006_[175:168]; + assign _0367_ = _1695_ ? 1'h0 : _0370_; + assign _0439_[207:176] = _1644_ ? addr_a : 32'd0; + assign _0440_ = _1644_ ? 32'd47 : _0007_; + assign _0439_[167:160] = _1644_ ? 8'h00 : _0006_[167:160]; + assign _0439_[159:32] = _1644_ ? _0442_ : _0006_[159:32]; + assign _0439_[31:0] = _1644_ ? _0441_ : _0006_[31:0]; + assign _0439_[271:208] = _1644_ ? { addr_c, addr_b } : 64'h0000000000000000; + assign _0000_ = _1499_ ? addr_c : deferred_local; + assign _0001_ = _1499_ ? addr_b : deferred_target; + assign _0002_ = _1499_ ? 32'd1 : n_deferred; + assign _0452_ = _1498_ ? val_c : write_value; + assign _0451_ = _1498_ ? addr_b : write_address; + assign _0446_ = _1498_ ? 32'd1 : n_writes; + assign _0443_ = _1498_ ? deferred_local : _0000_; + assign _0444_ = _1498_ ? deferred_target : _0001_; + assign _0445_ = _1498_ ? n_deferred : _0002_; + assign _0442_ = _1497_ ? val_b : _0452_; + assign _0441_ = _1497_ ? addr_c : _0451_; + assign _1720_ = _1497_ ? 32'd1 : _0446_; + assign _1721_ = _1496_ ? 32'hxxxxxxxx : _1720_; + assign _1722_ = _1494_ ? 32'hxxxxxxxx : _1721_; + assign _1723_ = _0871_ ? _1722_ : 32'hxxxxxxxx; + assign _1724_ = _1584_ ? 32'hxxxxxxxx : _1723_; + assign _1725_ = _1501_ ? _1724_ : 32'hxxxxxxxx; + assign _1726_ = abort ? 32'hxxxxxxxx : _1725_; + assign _0436_ = rst_n ? _1726_ : 32'hxxxxxxxx; + assign _0433_ = _1497_ ? deferred_local : _0443_; + assign _0434_ = _1497_ ? deferred_target : _0444_; + assign _1727_ = _1497_ ? n_deferred : _0445_; + assign _1728_ = _1496_ ? 32'hxxxxxxxx : _1727_; + assign _1729_ = _1494_ ? 32'hxxxxxxxx : _1728_; + assign _1730_ = _0871_ ? _1729_ : 32'hxxxxxxxx; + assign _1731_ = _1584_ ? 32'hxxxxxxxx : _1730_; + assign _1732_ = _1501_ ? _1731_ : 32'hxxxxxxxx; + assign _1733_ = abort ? 32'hxxxxxxxx : _1732_; + assign _0435_ = rst_n ? _1733_ : 32'hxxxxxxxx; + assign _0432_ = _1496_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0442_; + assign _0431_ = _1496_ ? 32'hxxxxxxxx : _0441_; + assign _0425_ = _1496_ ? 32'hxxxxxxxx : _0433_; + assign _0426_ = _1496_ ? 32'hxxxxxxxx : _0434_; + assign _0427_ = _1496_ ? 32'hxxxxxxxx : _0435_; + assign _0428_ = _1496_ ? 32'hxxxxxxxx : _0436_; + assign _0424_ = _1494_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0432_; + assign _0319_ = _1695_ ? 1'h0 : _0332_; + assign _0423_ = _1494_ ? 32'hxxxxxxxx : _0431_; + assign _0417_ = _1494_ ? 32'hxxxxxxxx : _0425_; + assign _0418_ = _1494_ ? 32'hxxxxxxxx : _0426_; + assign _0419_ = _1494_ ? 32'hxxxxxxxx : _0427_; + assign _0420_ = _1494_ ? 32'hxxxxxxxx : _0428_; + assign _0410_ = _0871_ ? _0424_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _0409_ = _0871_ ? _0423_ : 32'hxxxxxxxx; + assign _0405_ = _0871_ ? _0417_ : 32'hxxxxxxxx; + assign _0406_ = _0871_ ? _0418_ : 32'hxxxxxxxx; + assign _0407_ = _0871_ ? _0419_ : 32'hxxxxxxxx; + assign _0408_ = _0871_ ? _0420_ : 32'hxxxxxxxx; + assign _0385_ = _1584_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0410_; + assign _0384_ = _1584_ ? 32'hxxxxxxxx : _0409_; + assign _0380_ = _1584_ ? 32'hxxxxxxxx : _0405_; + assign _0381_ = _1584_ ? 32'hxxxxxxxx : _0406_; + assign _0382_ = _1584_ ? 32'hxxxxxxxx : _0407_; + assign _0383_ = _1584_ ? 32'hxxxxxxxx : _0408_; + assign _0330_ = _1501_ ? _0385_ : _0011_; + assign _0329_ = _1501_ ? _0384_ : _0010_; + assign _0325_ = _1501_ ? _0380_ : _0012_; + assign _0326_ = _1501_ ? _0381_ : _0012_; + assign _0327_ = _1501_ ? _0382_ : _0012_; + assign _0328_ = _1501_ ? _0383_ : _0003_; + assign _0270_ = _1475_ ? 8'h03 : _0281_; + assign _0360_ = _1475_ ? 8'h8f : _0366_; + assign _1734_ = _1587_ ? 1'h0 : 1'h1; + assign _1735_ = _1534_ ? _0203_ : 1'h0; + assign _1736_ = _1532_ ? 1'h0 : _1735_; + assign _1737_ = result_pending ? 1'h0 : _1736_; + assign _1738_ = _1529_ ? 1'h0 : _1737_; + assign _1739_ = _1528_ ? 1'h0 : _1738_; + assign _1740_ = _1527_ ? 1'h0 : _1739_; + assign _1741_ = _1526_ ? 1'h0 : _1740_; + assign _1742_ = _1525_ ? 1'h0 : _1741_; + assign _1743_ = _1677_ ? 1'h0 : _1742_; + assign _1744_ = _1477_ ? 1'h0 : _1743_; + assign _1745_ = _1591_ ? 1'h0 : _1744_; + assign _1746_ = _1519_ ? 1'h0 : _1745_; + assign _1747_ = _0887_ ? 1'h0 : _1746_; + assign _1748_ = _0886_ ? 1'h0 : _1747_; + assign _1749_ = _0885_ ? 1'h0 : _1748_; + assign _1750_ = \receiver.fault_valid ? 1'h0 : _1749_; + assign _1751_ = _1512_ ? _1750_ : 1'h0; + assign _1752_ = _1511_ ? 1'h0 : _1751_; + assign _1753_ = _1510_ ? 1'h0 : _1752_; + assign _1754_ = _1509_ ? 1'h0 : _1753_; + assign _1755_ = _1508_ ? 1'h0 : _1754_; + assign _1756_ = _1507_ ? 1'h0 : _1755_; + assign _1757_ = _1585_ ? 1'h0 : 1'h1; + assign _1758_ = _1506_ ? _1757_ : _1756_; + assign _1759_ = _1505_ ? 1'h0 : _1758_; + assign _1760_ = _1655_ ? 1'h0 : 1'h1; + assign _1761_ = \field_encoder.fault ? 1'h0 : _1760_; + assign _1762_ = _1504_ ? _1761_ : _1759_; + assign _1763_ = _1502_ ? 1'h0 : _1762_; + assign _1764_ = _0871_ ? 1'h0 : 1'h1; + assign _1765_ = _1584_ ? 1'h0 : _1764_; + assign _1766_ = _1501_ ? _1765_ : _1763_; + assign _1768_ = _1553_ ? 1'h1 : _1767_; + assign _1769_ = _1552_ ? 1'h1 : _1768_; + assign _1770_ = _0169_ ? _1769_ : 1'h0; + assign _0310_ = _1475_ ? 1'h0 : _0319_; + assign _1771_ = _1539_ ? _0280_ : _1770_; + assign _1772_ = _1534_ ? 1'h0 : _1771_; + assign _1773_ = _1532_ ? 1'h0 : _1772_; + assign _1774_ = _1554_ ? 1'h1 : _1773_; + assign _1775_ = result_pending ? 1'h0 : _1774_; + assign _1776_ = _1529_ ? 1'h0 : _1775_; + assign _1777_ = _1528_ ? 1'h0 : _1776_; + assign _1778_ = _1527_ ? 1'h0 : _1777_; + assign _1779_ = _1526_ ? 1'h0 : _1778_; + assign _1780_ = _1525_ ? 1'h0 : _1779_; + assign _1781_ = _1677_ ? 1'h0 : _1780_; + assign _1782_ = _1477_ ? 1'h0 : _1781_; + assign _1783_ = _1591_ ? 1'h0 : _1782_; + assign _1784_ = _1519_ ? 1'h0 : _1783_; + assign _1785_ = _0887_ ? 1'h0 : _1784_; + assign _1786_ = _0886_ ? 1'h0 : _1785_; + assign _1787_ = _0885_ ? 1'h0 : _1786_; + assign _1788_ = \receiver.fault_valid ? 1'h0 : _1787_; + assign _1789_ = _1512_ ? _1788_ : 1'h0; + assign _1790_ = _1511_ ? 1'h0 : _1789_; + assign _1791_ = _1510_ ? 1'h1 : _1790_; + assign _1792_ = _1509_ ? _1757_ : _1791_; + assign _1793_ = _1508_ ? 1'h1 : _1792_; + assign _1794_ = _0386_ ? 1'h0 : 1'h1; + assign _1795_ = result_pending ? 1'h1 : _1794_; + assign _1796_ = _1529_ ? 1'h1 : _1795_; + assign _1797_ = _1528_ ? 1'h1 : _1796_; + assign _1798_ = _1527_ ? 1'h1 : _1797_; + assign _1799_ = _1526_ ? 1'h1 : _1798_; + assign _1800_ = _1525_ ? 1'h1 : _1799_; + assign _1801_ = _1677_ ? 1'h1 : _1800_; + assign _1802_ = _1477_ ? 1'h1 : _1801_; + assign _1803_ = _1591_ ? 1'h1 : _1802_; + assign _1804_ = _1519_ ? 1'h1 : _1803_; + assign _1805_ = _0887_ ? 1'h1 : _1804_; + assign _1806_ = _0886_ ? 1'h1 : _1805_; + assign _1807_ = _0885_ ? 1'h1 : _1806_; + assign _1808_ = \receiver.fault_valid ? 1'h1 : _1807_; + assign _1809_ = _1512_ ? _1808_ : 1'h0; + assign _1810_ = _1511_ ? 1'h1 : _1809_; + assign _1811_ = _1510_ ? 1'h0 : _1810_; + assign _1812_ = _1585_ ? 1'h1 : 1'h0; + assign _1813_ = _1509_ ? _1812_ : _1811_; + assign _1814_ = _1508_ ? 1'h0 : _1813_; + assign _1815_ = _1507_ ? 1'h1 : _1814_; + assign _1816_ = _1506_ ? _1812_ : _1815_; + assign _1817_ = _1505_ ? 1'h1 : _1816_; + assign _1818_ = _1655_ ? 1'h1 : 1'h0; + assign _1819_ = \field_encoder.fault ? 1'h1 : _1818_; + assign _1820_ = _1504_ ? _1819_ : _1817_; + assign _1821_ = _1502_ ? 1'h1 : _1820_; + assign _1822_ = _0871_ ? 1'h1 : 1'h0; + assign _1823_ = _1584_ ? 1'h1 : _1822_; + assign _1824_ = _1501_ ? _1823_ : _1821_; + assign _0361_ = _1475_ ? 1'h0 : _0367_; + assign _1825_ = _0227_ ? 8'hxx : _0226_; + assign _1826_ = _0386_ ? 8'hxx : _1825_; + assign _1827_ = result_pending ? 8'h87 : _1826_; + assign _1828_ = _1529_ ? 8'h88 : _1827_; + assign _1829_ = _1528_ ? 8'h8f : _1828_; + assign _1830_ = _1527_ ? 8'h88 : _1829_; + assign _1831_ = _1526_ ? 8'h88 : _1830_; + assign _1832_ = _1525_ ? 8'h88 : _1831_; + assign _1833_ = _1677_ ? 8'h85 : _1832_; + assign _1834_ = _1477_ ? 8'h86 : _1833_; + assign _1835_ = _1591_ ? 8'h83 : _1834_; + assign _1836_ = _1519_ ? 8'h82 : _1835_; + assign _1837_ = _1587_ ? 8'h92 : 8'hxx; + assign _1838_ = result_pending ? _1837_ : 8'h87; + assign _1839_ = _1662_ ? 8'h83 : _1838_; + assign _1840_ = _0887_ ? _1839_ : _1836_; + assign _1841_ = _1661_ ? 8'h86 : 8'hxx; + assign _1842_ = _1513_ ? _1841_ : 8'h81; + assign _1843_ = result_pending ? 8'h87 : _1842_; + assign _1844_ = _1476_ ? 8'h86 : _1843_; + assign _1845_ = _1660_ ? 8'h83 : _1844_; + assign _1846_ = _0886_ ? _1845_ : _1840_; + assign _1847_ = _1659_ ? 8'h83 : 8'hxx; + assign _1848_ = _0885_ ? _1847_ : _1846_; + assign _1849_ = \receiver.fault_valid ? \receiver.fault_status : _1848_; + assign _1850_ = _1512_ ? _1849_ : 8'hxx; + assign _1851_ = _1493_ ? 8'h8c : 8'hxx; + assign _1852_ = \adapter.fault ? 8'h87 : _1851_; + assign _1853_ = _1511_ ? _1852_ : _1850_; + assign _1854_ = _1510_ ? 8'hxx : _1853_; + assign _1855_ = _1585_ ? 8'h8b : last_fault; + assign _1856_ = _1509_ ? _1855_ : _1854_; + assign _1857_ = _1508_ ? 8'hxx : _1856_; + assign _1858_ = _1586_ ? 8'h87 : 8'hxx; + assign _1859_ = _1507_ ? _1858_ : _1857_; + assign _1860_ = _1506_ ? _1855_ : _1859_; + assign _1861_ = _1656_ ? 8'h8a : 8'hxx; + assign _1862_ = \field_encoder.fault ? 8'h87 : _1861_; + assign _1863_ = _1505_ ? _1862_ : _1860_; + assign _1864_ = _1655_ ? 8'h8a : 8'hxx; + assign _1865_ = \field_encoder.fault ? 8'h87 : _1864_; + assign _1866_ = _1504_ ? _1865_ : _1863_; + assign _1867_ = _1503_ ? 8'h8c : 8'hxx; + assign _1868_ = \field_encoder.fault ? 8'h87 : _1867_; + assign _1869_ = _1502_ ? _1868_ : _1866_; + assign _1870_ = _1496_ ? 8'h8d : 8'hxx; + assign _1871_ = _1494_ ? 8'h90 : _1870_; + assign _1872_ = _0871_ ? _1871_ : 8'hxx; + assign _1873_ = _1584_ ? 8'h8a : _1872_; + assign _1874_ = _1501_ ? _1873_ : _1869_; + assign _1875_ = abort ? 8'h93 : _1874_; + assign _1876_ = _0227_ ? 8'h00 : _0226_; + assign _1877_ = _0386_ ? 8'hxx : _1876_; + assign _1878_ = result_pending ? 8'h87 : _1877_; + assign _1879_ = _1529_ ? 8'h88 : _1878_; + assign _1880_ = _1528_ ? 8'h8f : _1879_; + assign _1881_ = _1527_ ? 8'h88 : _1880_; + assign _1882_ = _1526_ ? 8'h88 : _1881_; + assign _1883_ = _1525_ ? 8'h88 : _1882_; + assign _1884_ = _1677_ ? 8'h85 : _1883_; + assign _1885_ = _1477_ ? 8'h86 : _1884_; + assign _1886_ = _1591_ ? 8'h83 : _1885_; + assign _1887_ = _1519_ ? 8'h82 : _1886_; + assign _1888_ = _1587_ ? 8'h92 : 8'h02; + assign _1889_ = result_pending ? _1888_ : 8'h87; + assign _1890_ = _1662_ ? 8'h83 : _1889_; + assign _1891_ = _0887_ ? _1890_ : _1887_; + assign _1892_ = _1661_ ? 8'h86 : 8'h00; + assign _1893_ = _1513_ ? _1892_ : 8'h81; + assign _1894_ = result_pending ? 8'h87 : _1893_; + assign _1895_ = _1476_ ? 8'h86 : _1894_; + assign _1896_ = _1660_ ? 8'h83 : _1895_; + assign _1897_ = _0886_ ? _1896_ : _1891_; + assign _1898_ = _1659_ ? 8'h83 : 8'h03; + assign _1899_ = _0885_ ? _1898_ : _1897_; + assign _1900_ = \receiver.fault_valid ? \receiver.fault_status : _1899_; + assign _1901_ = _1512_ ? _1900_ : 8'hxx; + assign _1902_ = _1493_ ? 8'h8c : 8'h00; + assign _1903_ = \adapter.fault ? 8'h87 : _1902_; + assign _1904_ = _1511_ ? _1903_ : _1901_; + assign _1905_ = _1510_ ? 8'hxx : _1904_; + assign _1906_ = _1585_ ? 8'h8b : last_status; + assign _1907_ = _1509_ ? _1906_ : _1905_; + assign _1908_ = _1508_ ? 8'hxx : _1907_; + assign _1909_ = _1586_ ? 8'h87 : 8'h00; + assign _1910_ = _1507_ ? _1909_ : _1908_; + assign _1911_ = _1506_ ? _1906_ : _1910_; + assign _1912_ = _1656_ ? 8'h8a : 8'h00; + assign _1913_ = \field_encoder.fault ? 8'h87 : _1912_; + assign _1914_ = _1505_ ? _1913_ : _1911_; + assign _1915_ = _1504_ ? _1865_ : _1914_; + assign _1916_ = _1503_ ? 8'h8c : 8'h00; + assign _1917_ = \field_encoder.fault ? 8'h87 : _1916_; + assign _1918_ = _1502_ ? _1917_ : _1915_; + assign _1919_ = _1496_ ? 8'h8d : 8'h00; + assign _1920_ = _1494_ ? 8'h90 : _1919_; + assign _1921_ = _0871_ ? _1920_ : 8'hxx; + assign _1922_ = _1584_ ? 8'h8a : _1921_; + assign _1923_ = _1501_ ? _1922_ : _1918_; + assign _1924_ = abort ? 8'h93 : _1923_; + assign _1925_ = _1500_ ? \transmitter.payload_crc : staged_result_crc; + assign _1926_ = _0227_ ? 32'd0 : _1925_; + assign _1927_ = _0386_ ? _1925_ : _1926_; + assign _1928_ = result_pending ? _1925_ : _1927_; + assign _1929_ = _1529_ ? _1925_ : _1928_; + assign _1930_ = _1528_ ? _1925_ : _1929_; + assign _1931_ = _1527_ ? _1925_ : _1930_; + assign _1932_ = _1526_ ? _1925_ : _1931_; + assign _1933_ = _1525_ ? _1925_ : _1932_; + assign _1934_ = _1677_ ? _1925_ : _1933_; + assign _1935_ = _1477_ ? _1925_ : _1934_; + assign _1936_ = _1591_ ? _1925_ : _1935_; + assign _1937_ = _1519_ ? _1925_ : _1936_; + assign _1938_ = _0887_ ? _1925_ : _1937_; + assign _1939_ = _0886_ ? _1925_ : _1938_; + assign _1940_ = _0885_ ? _1925_ : _1939_; + assign _1941_ = \receiver.fault_valid ? _1925_ : _1940_; + assign _1942_ = _1512_ ? _1941_ : _1925_; + assign _1943_ = _1493_ ? _1925_ : 32'd0; + assign _1944_ = \adapter.fault ? _1925_ : _1943_; + assign _1945_ = _1511_ ? _1944_ : _1942_; + assign _1946_ = _1510_ ? _1925_ : _1945_; + assign _1947_ = _1509_ ? _1925_ : _1946_; + assign _1948_ = _1508_ ? _1925_ : _1947_; + assign _1949_ = _1586_ ? _1925_ : 32'd0; + assign _1950_ = _1507_ ? _1949_ : _1948_; + assign _1951_ = _1506_ ? _1925_ : _1950_; + assign _1952_ = _1656_ ? _1925_ : 32'd0; + assign _1953_ = \field_encoder.fault ? _1925_ : _1952_; + assign _1954_ = _1505_ ? _1953_ : _1951_; + assign _1955_ = _1504_ ? _1925_ : _1954_; + assign _1956_ = _1503_ ? _1925_ : 32'd0; + assign _1957_ = \field_encoder.fault ? _1925_ : _1956_; + assign _1958_ = _1502_ ? _1957_ : _1955_; + assign _1959_ = _1496_ ? _1925_ : 32'd0; + assign _1960_ = _1494_ ? _1925_ : _1959_; + assign _1961_ = _0871_ ? _1960_ : _1925_; + assign _1962_ = _1584_ ? _1925_ : _1961_; + assign _1963_ = _1501_ ? _1962_ : _1958_; + assign _1964_ = _0227_ ? \receiver.frame_payload [95:64] : 32'hxxxxxxxx; + assign _1965_ = _0386_ ? 32'hxxxxxxxx : _1964_; + assign _1966_ = result_pending ? 32'hxxxxxxxx : _1965_; + assign _1967_ = _1529_ ? 32'hxxxxxxxx : _1966_; + assign _1968_ = _1528_ ? 32'hxxxxxxxx : _1967_; + assign _1969_ = _1527_ ? 32'hxxxxxxxx : _1968_; + assign _1970_ = _1526_ ? 32'hxxxxxxxx : _1969_; + assign _1971_ = _1525_ ? 32'hxxxxxxxx : _1970_; + assign _1972_ = _1677_ ? 32'hxxxxxxxx : _1971_; + assign _1973_ = _1477_ ? 32'hxxxxxxxx : _1972_; + assign _1974_ = _1591_ ? 32'hxxxxxxxx : _1973_; + assign _1975_ = _1519_ ? 32'hxxxxxxxx : _1974_; + assign _1976_ = _0887_ ? 32'hxxxxxxxx : _1975_; + assign _1977_ = _0886_ ? 32'hxxxxxxxx : _1976_; + assign _1978_ = _0885_ ? 32'hxxxxxxxx : _1977_; + assign _1979_ = \receiver.fault_valid ? 32'hxxxxxxxx : _1978_; + assign _1980_ = _1512_ ? _1979_ : 32'hxxxxxxxx; + assign _1981_ = _1493_ ? 32'hxxxxxxxx : next_fp_value; + assign _1982_ = \adapter.fault ? 32'hxxxxxxxx : _1981_; + assign _1983_ = _1511_ ? _1982_ : _1980_; + assign _1984_ = _1510_ ? 32'hxxxxxxxx : _1983_; + assign _1985_ = _1509_ ? 32'hxxxxxxxx : _1984_; + assign _1986_ = _1508_ ? 32'hxxxxxxxx : _1985_; + assign _1987_ = _1586_ ? 32'hxxxxxxxx : next_fp_value; + assign _1988_ = _1507_ ? _1987_ : _1986_; + assign _1989_ = _1506_ ? 32'hxxxxxxxx : _1988_; + assign _1990_ = _1505_ ? _0429_ : _1989_; + assign _1991_ = _1504_ ? 32'hxxxxxxxx : _1990_; + assign _1992_ = _1503_ ? 32'hxxxxxxxx : next_fp_value; + assign _1993_ = \field_encoder.fault ? 32'hxxxxxxxx : _1992_; + assign _1994_ = _1502_ ? _1993_ : _1991_; + assign _1995_ = _1496_ ? 32'hxxxxxxxx : next_fp_value; + assign _1996_ = _1494_ ? 32'hxxxxxxxx : _1995_; + assign _1997_ = _0871_ ? _1996_ : 32'hxxxxxxxx; + assign _1998_ = _1584_ ? 32'hxxxxxxxx : _1997_; + assign _1999_ = _1501_ ? _1998_ : _1994_; + assign _2000_ = _0227_ ? _0455_ : 32'hxxxxxxxx; + assign _2001_ = _0386_ ? 32'hxxxxxxxx : _2000_; + assign _2002_ = result_pending ? 32'hxxxxxxxx : _2001_; + assign _2003_ = _1529_ ? 32'hxxxxxxxx : _2002_; + assign _2004_ = _1528_ ? 32'hxxxxxxxx : _2003_; + assign _2005_ = _1527_ ? 32'hxxxxxxxx : _2004_; + assign _2006_ = _1526_ ? 32'hxxxxxxxx : _2005_; + assign _2007_ = _1525_ ? 32'hxxxxxxxx : _2006_; + assign _2008_ = _1677_ ? 32'hxxxxxxxx : _2007_; + assign _2009_ = _1477_ ? 32'hxxxxxxxx : _2008_; + assign _2010_ = _1591_ ? 32'hxxxxxxxx : _2009_; + assign _2011_ = _1519_ ? 32'hxxxxxxxx : _2010_; + assign _2012_ = _0887_ ? 32'hxxxxxxxx : _2011_; + assign _2013_ = _0886_ ? 32'hxxxxxxxx : _2012_; + assign _2014_ = _0885_ ? 32'hxxxxxxxx : _2013_; + assign _2015_ = \receiver.fault_valid ? 32'hxxxxxxxx : _2014_; + assign _2016_ = _1512_ ? _2015_ : 32'hxxxxxxxx; + assign _2017_ = _1493_ ? 32'hxxxxxxxx : next_pc_value; + assign _2018_ = \adapter.fault ? 32'hxxxxxxxx : _2017_; + assign _2019_ = _1511_ ? _2018_ : _2016_; + assign _2020_ = _1510_ ? 32'hxxxxxxxx : _2019_; + assign _2021_ = _1509_ ? 32'hxxxxxxxx : _2020_; + assign _2022_ = _1508_ ? 32'hxxxxxxxx : _2021_; + assign _2023_ = _1586_ ? 32'hxxxxxxxx : next_pc_value; + assign _2024_ = _1507_ ? _2023_ : _2022_; + assign _2025_ = _1506_ ? 32'hxxxxxxxx : _2024_; + assign _2026_ = _1505_ ? _0430_ : _2025_; + assign _2027_ = _1504_ ? 32'hxxxxxxxx : _2026_; + assign _2028_ = _1503_ ? 32'hxxxxxxxx : next_pc_value; + assign _2029_ = \field_encoder.fault ? 32'hxxxxxxxx : _2028_; + assign _2030_ = _1502_ ? _2029_ : _2027_; + assign _2031_ = _1496_ ? 32'hxxxxxxxx : next_pc_value; + assign _2032_ = _1494_ ? 32'hxxxxxxxx : _2031_; + assign _2033_ = _0871_ ? _2032_ : 32'hxxxxxxxx; + assign _2034_ = _1584_ ? 32'hxxxxxxxx : _2033_; + assign _2035_ = _1501_ ? _2034_ : _2030_; + assign _2036_ = _0227_ ? \receiver.frame_payload [31:0] : 32'hxxxxxxxx; + assign _2037_ = _0386_ ? 32'hxxxxxxxx : _2036_; + assign _2038_ = result_pending ? 32'hxxxxxxxx : _2037_; + assign _2039_ = _1529_ ? 32'hxxxxxxxx : _2038_; + assign _2040_ = _1528_ ? 32'hxxxxxxxx : _2039_; + assign _2041_ = _1527_ ? 32'hxxxxxxxx : _2040_; + assign _2042_ = _1526_ ? 32'hxxxxxxxx : _2041_; + assign _2043_ = _1525_ ? 32'hxxxxxxxx : _2042_; + assign _2044_ = _1677_ ? 32'hxxxxxxxx : _2043_; + assign _2045_ = _1477_ ? 32'hxxxxxxxx : _2044_; + assign _2046_ = _1591_ ? 32'hxxxxxxxx : _2045_; + assign _2047_ = _1519_ ? 32'hxxxxxxxx : _2046_; + assign _2048_ = _0887_ ? 32'hxxxxxxxx : _2047_; + assign _2049_ = _0886_ ? 32'hxxxxxxxx : _2048_; + assign _2050_ = _0885_ ? 32'hxxxxxxxx : _2049_; + assign _2051_ = \receiver.fault_valid ? 32'hxxxxxxxx : _2050_; + assign _2052_ = _1512_ ? _2051_ : 32'hxxxxxxxx; + assign _2053_ = _1493_ ? 32'hxxxxxxxx : txn_id; + assign _2054_ = \adapter.fault ? 32'hxxxxxxxx : _2053_; + assign _2055_ = _1511_ ? _2054_ : _2052_; + assign _2056_ = _1510_ ? 32'hxxxxxxxx : _2055_; + assign _2057_ = _1509_ ? 32'hxxxxxxxx : _2056_; + assign _2058_ = _1508_ ? 32'hxxxxxxxx : _2057_; + assign _2059_ = _1586_ ? 32'hxxxxxxxx : txn_id; + assign _2060_ = _1507_ ? _2059_ : _2058_; + assign _2061_ = _1506_ ? 32'hxxxxxxxx : _2060_; + assign _2062_ = _1656_ ? 32'hxxxxxxxx : txn_id; + assign _2063_ = \field_encoder.fault ? 32'hxxxxxxxx : _2062_; + assign _2064_ = _1505_ ? _2063_ : _2061_; + assign _2065_ = _1504_ ? 32'hxxxxxxxx : _2064_; + assign _2066_ = _1503_ ? 32'hxxxxxxxx : txn_id; + assign _2067_ = \field_encoder.fault ? 32'hxxxxxxxx : _2066_; + assign _2068_ = _1502_ ? _2067_ : _2065_; + assign _2069_ = _1496_ ? 32'hxxxxxxxx : txn_id; + assign _2070_ = _1494_ ? 32'hxxxxxxxx : _2069_; + assign _2071_ = _0871_ ? _2070_ : 32'hxxxxxxxx; + assign _2072_ = _1584_ ? 32'hxxxxxxxx : _2071_; + assign _2073_ = _1501_ ? _2072_ : _2068_; + assign _2074_ = _0227_ ? 1'h1 : 1'h0; + assign _2075_ = _0386_ ? 1'h0 : _2074_; + assign _2076_ = result_pending ? 1'h1 : _2075_; + assign _2077_ = _1529_ ? 1'hx : _2076_; + assign _2078_ = _1528_ ? 1'hx : _2077_; + assign _2079_ = _1527_ ? 1'hx : _2078_; + assign _2080_ = _1526_ ? 1'hx : _2079_; + assign _2081_ = _1525_ ? 1'hx : _2080_; + assign _2082_ = _1677_ ? 1'hx : _2081_; + assign _2083_ = _1477_ ? 1'hx : _2082_; + assign _2084_ = _1591_ ? 1'hx : _2083_; + assign _2085_ = _1519_ ? 1'hx : _2084_; + assign _2086_ = _1662_ ? 1'hx : 1'h0; + assign _2087_ = _0887_ ? _2086_ : _2085_; + assign _2088_ = _0886_ ? 1'hx : _2087_; + assign _2089_ = _0885_ ? 1'hx : _2088_; + assign _2090_ = \receiver.fault_valid ? 1'hx : _2089_; + assign _2091_ = _1512_ ? _2090_ : 1'hx; + assign _2092_ = _1493_ ? 1'hx : 1'h1; + assign _2093_ = \adapter.fault ? 1'hx : _2092_; + assign _2094_ = _1511_ ? _2093_ : _2091_; + assign _2095_ = _1510_ ? 1'hx : _2094_; + assign _2096_ = _1509_ ? 1'hx : _2095_; + assign _2097_ = _1508_ ? 1'hx : _2096_; + assign _2098_ = _1586_ ? 1'hx : 1'h1; + assign _2099_ = _1507_ ? _2098_ : _2097_; + assign _2100_ = _1506_ ? 1'hx : _2099_; + assign _2101_ = _1656_ ? 1'hx : 1'h1; + assign _2102_ = \field_encoder.fault ? 1'hx : _2101_; + assign _2103_ = _1505_ ? _2102_ : _2100_; + assign _2104_ = _1504_ ? 1'hx : _2103_; + assign _2105_ = _1503_ ? 1'hx : 1'h1; + assign _2106_ = \field_encoder.fault ? 1'hx : _2105_; + assign _2107_ = _1502_ ? _2106_ : _2104_; + assign _2108_ = _1496_ ? 1'hx : 1'h1; + assign _2109_ = _1494_ ? 1'hx : _2108_; + assign _2110_ = _0871_ ? _2109_ : 1'hx; + assign _2111_ = _1584_ ? 1'hx : _2110_; + assign _2112_ = _1501_ ? _2111_ : _2107_; + assign _2113_ = _1613_ ? 16'hxxxx : \receiver.frame_payload [359:344]; + assign _2114_ = _1610_ ? 16'hxxxx : _2113_; + assign _2115_ = _1605_ ? 16'hxxxx : _2114_; + assign _2116_ = _1604_ ? 16'hxxxx : _2115_; + assign _2117_ = _1534_ ? _2116_ : 16'hxxxx; + assign _2118_ = _1532_ ? 16'hxxxx : _2117_; + assign _2119_ = result_pending ? 16'hxxxx : _2118_; + assign _2120_ = _1529_ ? 16'hxxxx : _2119_; + assign _2121_ = _1528_ ? 16'hxxxx : _2120_; + assign _2122_ = _1527_ ? 16'hxxxx : _2121_; + assign _2123_ = _1526_ ? 16'hxxxx : _2122_; + assign _2124_ = _1525_ ? 16'hxxxx : _2123_; + assign _2125_ = _1677_ ? 16'hxxxx : _2124_; + assign _2126_ = _1477_ ? 16'hxxxx : _2125_; + assign _2127_ = _1591_ ? 16'hxxxx : _2126_; + assign _2128_ = _1519_ ? 16'hxxxx : _2127_; + assign _2129_ = _0887_ ? 16'hxxxx : _2128_; + assign _2130_ = _0886_ ? 16'hxxxx : _2129_; + assign _2131_ = _0885_ ? 16'hxxxx : _2130_; + assign _2132_ = \receiver.fault_valid ? 16'hxxxx : _2131_; + assign _2133_ = _1512_ ? _2132_ : 16'hxxxx; + assign _2134_ = _1511_ ? 16'hxxxx : _2133_; + assign _2135_ = _1510_ ? 16'hxxxx : _2134_; + assign _2136_ = _1509_ ? 16'hxxxx : _2135_; + assign _2137_ = _1508_ ? 16'hxxxx : _2136_; + assign _2138_ = _1507_ ? 16'hxxxx : _2137_; + assign _2139_ = _1585_ ? 16'hxxxx : proposed_pc[15:0]; + assign _2140_ = _1506_ ? _2139_ : _2138_; + assign _2141_ = _1505_ ? 16'hxxxx : _2140_; + assign _2142_ = _1655_ ? 16'hxxxx : proposed_fp[15:0]; + assign _2143_ = \field_encoder.fault ? 16'hxxxx : _2142_; + assign _2144_ = _1504_ ? _2143_ : _2141_; + assign _2145_ = _1502_ ? 16'hxxxx : _2144_; + assign _2146_ = _0871_ ? 16'hxxxx : _2724_; + assign _2147_ = _1584_ ? 16'hxxxx : _2146_; + assign _2148_ = _1501_ ? _2147_ : _2145_; + assign _2149_ = _1568_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2732_; + assign _2150_ = _1634_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2149_; + assign _2151_ = _0889_ ? _2733_ : _2150_; + assign _2152_ = _1548_ ? _2151_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2153_ = _1553_ ? \receiver.frame_payload [479:352] : _2152_; + assign _2154_ = _1552_ ? \receiver.frame_payload [479:352] : _2153_; + assign _2155_ = _0169_ ? _2154_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2156_ = _1561_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : \receiver.frame_payload [823:696]; + assign _2157_ = _1630_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2156_; + assign _2158_ = _1713_ ? _2157_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2159_ = _1695_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2158_; + assign _2160_ = _1475_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2159_; + assign _2161_ = _1627_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2160_; + assign _2162_ = _1624_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2161_; + assign _2163_ = _1617_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2162_; + assign _2164_ = _1539_ ? _2163_ : _2155_; + assign _2165_ = _1534_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2164_; + assign _2166_ = _1532_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2165_; + assign _2167_ = _1554_ ? 128'h00000000000000000000000000000000 : _2166_; + assign _2168_ = result_pending ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2167_; + assign _2169_ = _1529_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2168_; + assign _2170_ = _1528_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2169_; + assign _2171_ = _1527_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2170_; + assign _2172_ = _1526_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2171_; + assign _2173_ = _1525_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2172_; + assign _2174_ = _1677_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2173_; + assign _2175_ = _1477_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2174_; + assign _2176_ = _1591_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2175_; + assign _2177_ = _1519_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2176_; + assign _2178_ = _0887_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2177_; + assign _2179_ = _0886_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2178_; + assign _2180_ = _0885_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2179_; + assign _2181_ = \receiver.fault_valid ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2180_; + assign _2182_ = _1512_ ? _2181_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2183_ = _1511_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2182_; + assign _2184_ = _1510_ ? _2726_ : _2183_; + assign _2185_ = _1585_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : inv_value; + assign _2186_ = _1509_ ? _2185_ : _2184_; + assign _2187_ = _1508_ ? _0009_ : _2186_; + assign _2188_ = _1568_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2733_; + assign _2189_ = _1634_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2188_; + assign _2190_ = _0889_ ? \receiver.frame_payload [615:488] : _2189_; + assign _2191_ = _1548_ ? _2190_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2192_ = _1553_ ? \receiver.frame_payload [343:216] : _2191_; + assign _2193_ = _1552_ ? \receiver.frame_payload [343:216] : _2192_; + assign _2194_ = _0169_ ? _2193_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2195_ = _1561_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : \receiver.frame_payload [343:216]; + assign _2196_ = _1630_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2195_; + assign _2197_ = _1713_ ? _2196_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2198_ = _1695_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2197_; + assign _2199_ = _1475_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2198_; + assign _2200_ = _1627_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2199_; + assign _2201_ = _1624_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2200_; + assign _2202_ = _1617_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2201_; + assign _2203_ = _1539_ ? _2202_ : _2194_; + assign _2204_ = _1534_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2203_; + assign _2205_ = _1532_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2204_; + assign _2206_ = _1554_ ? _0175_ : _2205_; + assign _2207_ = result_pending ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2206_; + assign _2208_ = _1529_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2207_; + assign _2209_ = _1528_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2208_; + assign _2210_ = _1527_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2209_; + assign _2211_ = _1526_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2210_; + assign _2212_ = _1525_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2211_; + assign _2213_ = _1677_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2212_; + assign _2214_ = _1477_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2213_; + assign _2215_ = _1591_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2214_; + assign _2216_ = _1519_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2215_; + assign _2217_ = _0887_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2216_; + assign _2218_ = _0886_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2217_; + assign _2219_ = _0885_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2218_; + assign _2220_ = \receiver.fault_valid ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2219_; + assign _2221_ = _1512_ ? _2220_ : 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2222_ = _1511_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2221_; + assign _2223_ = _1510_ ? \adapter.result : _2222_; + assign _2224_ = _1585_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : val_c; + assign _2225_ = _1509_ ? _2224_ : _2223_; + assign _2226_ = _1508_ ? _0008_ : _2225_; + assign _2227_ = _1568_ ? 8'hxx : 8'h02; + assign _2228_ = _1634_ ? 8'hxx : _2227_; + assign _2229_ = _0889_ ? 8'h01 : _2228_; + assign _2230_ = _1548_ ? _2229_ : 8'hxx; + assign _2231_ = _1553_ ? 8'h01 : _2230_; + assign _2232_ = _1552_ ? 8'h02 : _2231_; + assign _2233_ = _0169_ ? _2232_ : 8'hxx; + assign _2234_ = _1561_ ? 8'hxx : 8'h02; + assign _2235_ = _1630_ ? 8'hxx : _2234_; + assign _2236_ = _1713_ ? _2235_ : 8'hxx; + assign _2237_ = _1695_ ? 8'hxx : _2236_; + assign _2238_ = _1475_ ? 8'hxx : _2237_; + assign _2239_ = _1627_ ? 8'hxx : _2238_; + assign _2240_ = _1624_ ? 8'hxx : _2239_; + assign _2241_ = _1617_ ? 8'hxx : _2240_; + assign _2242_ = _1539_ ? _2241_ : _2233_; + assign _2243_ = _1534_ ? 8'hxx : _2242_; + assign _2244_ = _1532_ ? 8'hxx : _2243_; + assign _2245_ = _1554_ ? 8'h03 : _2244_; + assign _2246_ = result_pending ? 8'hxx : _2245_; + assign _2247_ = _1529_ ? 8'hxx : _2246_; + assign _2248_ = _1528_ ? 8'hxx : _2247_; + assign _2249_ = _1527_ ? 8'hxx : _2248_; + assign _2250_ = _1526_ ? 8'hxx : _2249_; + assign _2251_ = _1525_ ? 8'hxx : _2250_; + assign _2252_ = _1677_ ? 8'hxx : _2251_; + assign _2253_ = _1477_ ? 8'hxx : _2252_; + assign _0354_ = _1627_ ? 8'h96 : _0360_; + assign _2254_ = _1591_ ? 8'hxx : _2253_; + assign _2255_ = _1519_ ? 8'hxx : _2254_; + assign _2256_ = _0887_ ? 8'hxx : _2255_; + assign _2257_ = _0886_ ? 8'hxx : _2256_; + assign _2258_ = _0885_ ? 8'hxx : _2257_; + assign _2259_ = \receiver.fault_valid ? 8'hxx : _2258_; + assign _2260_ = _1512_ ? _2259_ : 8'hxx; + assign _2261_ = _1511_ ? 8'hxx : _2260_; + assign _2262_ = _1510_ ? 8'h02 : _2261_; + assign _2263_ = _1585_ ? 8'hxx : 8'h02; + assign _2264_ = _1509_ ? _2263_ : _2262_; + assign _2265_ = _1508_ ? 8'h01 : _2264_; + assign _2266_ = _1568_ ? 4'hx : 4'h1; + assign _2267_ = _1634_ ? 4'hx : _2266_; + assign _2268_ = _0889_ ? 4'h5 : _2267_; + assign _2269_ = _1548_ ? _2268_ : 4'hx; + assign _2270_ = _1553_ ? 4'h3 : _2269_; + assign _2271_ = _1552_ ? 4'h3 : _2270_; + assign _2272_ = _0169_ ? _2271_ : 4'hx; + assign _2273_ = _1561_ ? 4'hx : 4'h8; + assign _2274_ = _1630_ ? 4'hx : _2273_; + assign _2275_ = _1713_ ? _2274_ : 4'hx; + assign _2276_ = _1695_ ? 4'hx : _2275_; + assign _2277_ = _1475_ ? 4'hx : _2276_; + assign _2278_ = _1627_ ? 4'hx : _2277_; + assign _2279_ = _1624_ ? 4'hx : _2278_; + assign _2280_ = _1617_ ? 4'hx : _2279_; + assign _2281_ = _1539_ ? _2280_ : _2272_; + assign _2282_ = _1613_ ? 4'hx : 4'h6; + assign _2283_ = _1610_ ? 4'hx : _2282_; + assign _2284_ = _1605_ ? 4'hx : _2283_; + assign _2285_ = _1604_ ? 4'hx : _2284_; + assign _2286_ = _1534_ ? _2285_ : _2281_; + assign _2287_ = _1532_ ? 4'hx : _2286_; + assign _2288_ = _1554_ ? 4'h4 : _2287_; + assign _2289_ = result_pending ? 4'hx : _2288_; + assign _2290_ = _1529_ ? 4'hx : _2289_; + assign _2291_ = _1528_ ? 4'hx : _2290_; + assign _2292_ = _1527_ ? 4'hx : _2291_; + assign _2293_ = _1526_ ? 4'hx : _2292_; + assign _2294_ = _1525_ ? 4'hx : _2293_; + assign _2295_ = _1677_ ? 4'hx : _2294_; + assign _2296_ = _1477_ ? 4'hx : _2295_; + assign _2297_ = _1591_ ? 4'hx : _2296_; + assign _2298_ = _1519_ ? 4'hx : _2297_; + assign _2299_ = _0887_ ? 4'hx : _2298_; + assign _2300_ = _0886_ ? 4'hx : _2299_; + assign _2301_ = _0885_ ? 4'hx : _2300_; + assign _2302_ = \receiver.fault_valid ? 4'hx : _2301_; + assign _2303_ = _1512_ ? _2302_ : 4'hx; + assign _2304_ = _1511_ ? 4'h0 : _2303_; + assign _2305_ = _1510_ ? 4'h3 : _2304_; + assign _2306_ = _1585_ ? 4'h0 : 4'h2; + assign _2307_ = _1509_ ? _2306_ : _2305_; + assign _2308_ = _1508_ ? 4'h3 : _2307_; + assign _2309_ = _1507_ ? 4'h0 : _2308_; + assign _2310_ = _1585_ ? 4'h0 : 4'h9; + assign _2311_ = _1506_ ? _2310_ : _2309_; + assign _2312_ = _1505_ ? 4'h0 : _2311_; + assign _2313_ = _1655_ ? 4'h0 : 4'ha; + assign _2314_ = \field_encoder.fault ? 4'h0 : _2313_; + assign _2315_ = _1504_ ? _2314_ : _2312_; + assign _2316_ = _1502_ ? 4'h0 : _2315_; + assign _2317_ = _0871_ ? 4'h0 : 4'h7; + assign _2318_ = _1584_ ? 4'h0 : _2317_; + assign _2319_ = _1501_ ? _2318_ : _2316_; + assign _2320_ = _1500_ ? 1'h0 : capture_result_crc; + assign _2321_ = _0227_ ? 1'h1 : _2320_; + assign _2322_ = _0386_ ? _2320_ : _2321_; + assign _2323_ = result_pending ? _2320_ : _2322_; + assign _2324_ = _1529_ ? _2320_ : _2323_; + assign _2325_ = _1528_ ? _2320_ : _2324_; + assign _2326_ = _1527_ ? _2320_ : _2325_; + assign _2327_ = _1526_ ? _2320_ : _2326_; + assign _2328_ = _1525_ ? _2320_ : _2327_; + assign _2329_ = _1677_ ? _2320_ : _2328_; + assign _2330_ = _1477_ ? _2320_ : _2329_; + assign _2331_ = _1591_ ? _2320_ : _2330_; + assign _2332_ = _1519_ ? _2320_ : _2331_; + assign _2333_ = _0887_ ? _2320_ : _2332_; + assign _2334_ = _0886_ ? _2320_ : _2333_; + assign _2335_ = _0885_ ? _2320_ : _2334_; + assign _2336_ = \receiver.fault_valid ? _2320_ : _2335_; + assign _2337_ = _1512_ ? _2336_ : _2320_; + assign _2338_ = _1493_ ? _2320_ : 1'h1; + assign _2339_ = \adapter.fault ? _2320_ : _2338_; + assign _2340_ = _1511_ ? _2339_ : _2337_; + assign _2341_ = _1510_ ? _2320_ : _2340_; + assign _2342_ = _1509_ ? _2320_ : _2341_; + assign _2343_ = _1508_ ? _2320_ : _2342_; + assign _2344_ = _1586_ ? _2320_ : 1'h1; + assign _2345_ = _1507_ ? _2344_ : _2343_; + assign _2346_ = _1506_ ? _2320_ : _2345_; + assign _2347_ = _1656_ ? _2320_ : 1'h1; + assign _2348_ = \field_encoder.fault ? _2320_ : _2347_; + assign _2349_ = _1505_ ? _2348_ : _2346_; + assign _2350_ = _1504_ ? _2320_ : _2349_; + assign _2351_ = _1503_ ? _2320_ : 1'h1; + assign _2352_ = \field_encoder.fault ? _2320_ : _2351_; + assign _2353_ = _1502_ ? _2352_ : _2350_; + assign _2354_ = _1496_ ? _2320_ : 1'h1; + assign _2355_ = _1494_ ? _2320_ : _2354_; + assign _2356_ = _0871_ ? _2355_ : _2320_; + assign _2357_ = _1584_ ? _2320_ : _2356_; + assign _2358_ = _1501_ ? _2357_ : _2353_; + assign _2359_ = _0227_ ? { 168'h000000000000000000000000000000000000000000, _0414_[271:168], 8'h00, _0414_[159:0], _0335_[7:0], \receiver.frame_payload [95:64], _0455_, \receiver.frame_payload [31:0] } : { 504'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, _0167_, \receiver.frame_payload [31:0] }; + assign _2360_ = _0386_ ? 544'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2359_; + assign _2361_ = result_pending ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, \receiver.frame_payload [31:0] } : _2360_; + assign _2362_ = _1529_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : _2361_; + assign _2363_ = _1528_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300000000 : _2362_; + assign _2364_ = _1527_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : _2363_; + assign _2365_ = _1526_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : _2364_; + assign _2366_ = _1525_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : _2365_; + assign _2367_ = _1677_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 : _2366_; + assign _2368_ = _1477_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : _2367_; + assign _2369_ = _1591_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002, \receiver.frame_payload [31:0] } : _2368_; + assign _2370_ = _1519_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : _2369_; + assign _2371_ = _1587_ ? { 504'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, _2730_[7:0], \receiver.frame_payload [31:0] } : { 416'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, staged_next_fp, staged_next_pc, _0454_, \receiver.frame_payload [31:0] }; + assign _2372_ = result_pending ? _2371_ : { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, \receiver.frame_payload [31:0] }; + assign _2373_ = _1662_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000 : _2372_; + assign _2374_ = _0887_ ? _2373_ : _2370_; + assign _2375_ = _1661_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : { 528'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c5343310000000200100100, \receiver.frame_payload [23:16], 8'h01 }; + assign _2376_ = _1513_ ? _2375_ : 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + assign _2377_ = result_pending ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : _2376_; + assign _2378_ = _1476_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : _2377_; + assign _2379_ = _1660_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000 : _2378_; + assign _2380_ = _0886_ ? _2379_ : _2374_; + assign _2381_ = _1659_ ? 544'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000 : { 391'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, state_valid, committed_fp, committed_pc, last_fault, retire_seq, last_status, _2729_, _2728_ }; + assign _2382_ = _0885_ ? _2381_ : _2380_; + assign _2383_ = \receiver.fault_valid ? { 504'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, _2727_[7:0], 32'h00000000 } : _2382_; + assign _2384_ = _1512_ ? _2383_ : 544'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2385_ = _1493_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, txn_id } : { 168'h000000000000000000000000000000000000000000, _0315_, _0128_[7:0], next_fp_value, next_pc_value, txn_id }; + assign _2386_ = \adapter.fault ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003, txn_id } : _2385_; + assign _2387_ = _1511_ ? _2386_ : _2384_; + assign _2388_ = _1510_ ? 544'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2387_; + assign _2389_ = _1585_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002, txn_id } : 544'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2390_ = _1509_ ? _2389_ : _2388_; + assign _2391_ = _1508_ ? 544'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _2390_; + assign _2392_ = _1586_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003, txn_id } : { 232'h0000000000000000000000000000000000000000000000000000000000, _0120_[207:176], _0213_[175:168], _0120_[167:160], _0213_[159:0], n_writes[7:0], next_fp_value, next_pc_value, txn_id }; + assign _2393_ = _1507_ ? _2392_ : _2391_; + assign _2394_ = _1585_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, txn_id } : 544'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2395_ = _1506_ ? _2394_ : _2393_; + assign _2396_ = _1656_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, txn_id } : { 168'h000000000000000000000000000000000000000000, _0120_, n_writes[7:0], proposed_fp, proposed_pc, txn_id }; + assign _2397_ = \field_encoder.fault ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003, txn_id } : _2396_; + assign _2398_ = _1505_ ? _2397_ : _2395_; + assign _2399_ = _1655_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, txn_id } : 544'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2400_ = \field_encoder.fault ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003, txn_id } : _2399_; + assign _2401_ = _1504_ ? _2400_ : _2398_; + assign _2402_ = _1503_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, txn_id } : { 168'h000000000000000000000000000000000000000000, _0046_, _0029_[7:0], next_fp_value, next_pc_value, txn_id }; + assign _2403_ = \field_encoder.fault ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003, txn_id } : _2402_; + assign _2404_ = _1502_ ? _2403_ : _2401_; + assign _2405_ = _1496_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, txn_id } : { 168'h000000000000000000000000000000000000000000, _0439_, _0436_[7:0], next_fp_value, next_pc_value, txn_id }; + assign _2406_ = _1494_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, txn_id } : _2405_; + assign _2407_ = _0871_ ? _2406_ : 544'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign _2408_ = _1584_ ? { 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, txn_id } : _2407_; + assign _2409_ = _1501_ ? _2408_ : _2404_; + assign _2410_ = _0227_ ? _0411_[15:0] : 16'h0005; + assign _2411_ = _0386_ ? 16'hxxxx : _2410_; + assign _2412_ = result_pending ? 16'h0005 : _2411_; + assign _2413_ = _1529_ ? 16'h0005 : _2412_; + assign _2414_ = _1528_ ? 16'h0005 : _2413_; + assign _2415_ = _1527_ ? 16'h0005 : _2414_; + assign _2416_ = _1526_ ? 16'h0005 : _2415_; + assign _2417_ = _1525_ ? 16'h0005 : _2416_; + assign _2418_ = _1677_ ? 16'h0005 : _2417_; + assign _2419_ = _1477_ ? 16'h0005 : _2418_; + assign _2420_ = _1591_ ? 16'h0005 : _2419_; + assign _2421_ = _1519_ ? 16'h0005 : _2420_; + assign _2422_ = _1587_ ? 16'h0005 : 16'h0010; + assign _2423_ = result_pending ? _2422_ : 16'h0005; + assign _2424_ = _1662_ ? 16'h0005 : _2423_; + assign _2425_ = _0887_ ? _2424_ : _2421_; + assign _2426_ = _1661_ ? 16'h0005 : 16'h000e; + assign _2427_ = _1513_ ? _2426_ : 16'h0005; + assign _2428_ = result_pending ? 16'h0005 : _2427_; + assign _2429_ = _1476_ ? 16'h0005 : _2428_; + assign _2430_ = _1660_ ? 16'h0005 : _2429_; + assign _2431_ = _0886_ ? _2430_ : _2425_; + assign _2432_ = _1659_ ? 16'h0005 : 16'h0014; + assign _2433_ = _0885_ ? _2432_ : _2431_; + assign _2434_ = \receiver.fault_valid ? 16'h0005 : _2433_; + assign _2435_ = _1512_ ? _2434_ : 16'hxxxx; + assign _2436_ = _1493_ ? 16'h0005 : _0336_[15:0]; + assign _2437_ = \adapter.fault ? 16'h0005 : _2436_; + assign _2438_ = _1511_ ? _2437_ : _2435_; + assign _2439_ = _1510_ ? 16'hxxxx : _2438_; + assign _2440_ = _1585_ ? 16'h0005 : tx_length; + assign _2441_ = _1509_ ? _2440_ : _2439_; + assign _2442_ = _1508_ ? 16'hxxxx : _2441_; + assign _2443_ = _1586_ ? 16'h0005 : _0214_[15:0]; + assign _2444_ = _1507_ ? _2443_ : _2442_; + assign _2445_ = _1506_ ? _2440_ : _2444_; + assign _2446_ = _1656_ ? 16'h0005 : _0121_[15:0]; + assign _2447_ = \field_encoder.fault ? 16'h0005 : _2446_; + assign _2448_ = _1505_ ? _2447_ : _2445_; + assign _2449_ = _1655_ ? 16'h0005 : 16'hxxxx; + assign _2450_ = \field_encoder.fault ? 16'h0005 : _2449_; + assign _2451_ = _1504_ ? _2450_ : _2448_; + assign _2452_ = _1503_ ? 16'h0005 : _0047_[15:0]; + assign _2453_ = \field_encoder.fault ? 16'h0005 : _2452_; + assign _2454_ = _1502_ ? _2453_ : _2451_; + assign _2455_ = _1496_ ? 16'h0005 : _0440_[15:0]; + assign _2456_ = _1494_ ? 16'h0005 : _2455_; + assign _2457_ = _0871_ ? _2456_ : 16'hxxxx; + assign _2458_ = _1584_ ? 16'h0005 : _2457_; + assign _2459_ = _1501_ ? _2458_ : _2454_; + assign _2460_ = _1585_ ? 8'h8b : tx_status; + assign _2461_ = _1509_ ? _2460_ : _1905_; + assign _2462_ = _1508_ ? 8'hxx : _2461_; + assign _2463_ = _1507_ ? _1909_ : _2462_; + assign _2464_ = _1506_ ? _2460_ : _2463_; + assign _2465_ = _1505_ ? _1913_ : _2464_; + assign _2466_ = _1504_ ? _1865_ : _2465_; + assign _2467_ = _1502_ ? _1917_ : _2466_; + assign _2468_ = _1501_ ? _1922_ : _2467_; + assign _2469_ = _0227_ ? 1'h0 : 1'h1; + assign _2470_ = _0386_ ? 1'hx : _2469_; + assign _2471_ = result_pending ? 1'h1 : _2470_; + assign _2472_ = _1529_ ? 1'h1 : _2471_; + assign _2473_ = _1528_ ? 1'h1 : _2472_; + assign _2474_ = _1527_ ? 1'h1 : _2473_; + assign _2475_ = _1526_ ? 1'h1 : _2474_; + assign _2476_ = _1525_ ? 1'h1 : _2475_; + assign _2477_ = _1677_ ? 1'h1 : _2476_; + assign _2478_ = _1477_ ? 1'h1 : _2477_; + assign _2479_ = _1591_ ? 1'h1 : _2478_; + assign _2480_ = _1519_ ? 1'h1 : _2479_; + assign _2481_ = _1587_ ? 1'h1 : 1'h0; + assign _2482_ = result_pending ? _2481_ : 1'h1; + assign _2483_ = _1662_ ? 1'h1 : _2482_; + assign _2484_ = _0887_ ? _2483_ : _2480_; + assign _2485_ = _1661_ ? 1'h1 : 1'h0; + assign _2486_ = _1513_ ? _2485_ : 1'h1; + assign _2487_ = result_pending ? 1'h1 : _2486_; + assign _2488_ = _1476_ ? 1'h1 : _2487_; + assign _2489_ = _1660_ ? 1'h1 : _2488_; + assign _2490_ = _0886_ ? _2489_ : _2484_; + assign _2491_ = _1659_ ? 1'h1 : 1'h0; + assign _2492_ = _0885_ ? _2491_ : _2490_; + assign _2493_ = \receiver.fault_valid ? 1'h1 : _2492_; + assign _2494_ = _1512_ ? _2493_ : 1'hx; + assign _2495_ = _1493_ ? 1'h1 : 1'h0; + assign _2496_ = \adapter.fault ? 1'h1 : _2495_; + assign _2497_ = _1511_ ? _2496_ : _2494_; + assign _2498_ = _1510_ ? 1'hx : _2497_; + assign _2499_ = _1585_ ? 1'h1 : fault; + assign _2500_ = _1509_ ? _2499_ : _2498_; + assign _2501_ = _1508_ ? 1'hx : _2500_; + assign _2502_ = _1586_ ? 1'h1 : 1'h0; + assign _2503_ = _1507_ ? _2502_ : _2501_; + assign _2504_ = _1506_ ? _2499_ : _2503_; + assign _2505_ = _1656_ ? 1'h1 : 1'h0; + assign _2506_ = \field_encoder.fault ? 1'h1 : _2505_; + assign _2507_ = _1505_ ? _2506_ : _2504_; + assign _2508_ = _1655_ ? 1'h1 : 1'hx; + assign _2509_ = \field_encoder.fault ? 1'h1 : _2508_; + assign _2510_ = _1504_ ? _2509_ : _2507_; + assign _2511_ = _1503_ ? 1'h1 : 1'h0; + assign _2512_ = \field_encoder.fault ? 1'h1 : _2511_; + assign _2513_ = _1502_ ? _2512_ : _2510_; + assign _2514_ = _1496_ ? 1'h1 : 1'h0; + assign _2515_ = _1494_ ? 1'h1 : _2514_; + assign _2516_ = _0871_ ? _2515_ : 1'hx; + assign _2517_ = _1584_ ? 1'h1 : _2516_; + assign _2518_ = _1501_ ? _2517_ : _2513_; + assign _2519_ = abort ? 1'h1 : _2518_; + assign _0355_ = _1627_ ? 1'h0 : _0361_; + assign _0300_ = _1627_ ? 1'h0 : _0310_; + assign _0259_ = _1627_ ? 8'h00 : _0270_; + assign _0348_ = _1624_ ? 8'h88 : _0354_; + assign _0349_ = _1624_ ? 1'h0 : _0355_; + assign _0290_ = _1624_ ? 1'h0 : _0300_; + assign _0245_ = _1624_ ? 8'h00 : _0259_; + assign _0279_ = _1624_ ? addr_c : _0458_; + assign _0278_ = _1624_ ? addr_b : _0459_; + assign _0318_ = _1624_ ? addr_a : _0456_; + assign _0341_ = _1617_ ? 8'h89 : _0348_; + assign _0342_ = _1617_ ? 1'h0 : _0349_; + assign _0280_ = _1617_ ? 1'h0 : _0290_; + assign _0225_ = _1617_ ? 8'h00 : _0245_; + assign _0268_ = _1617_ ? addr_c : _0279_; + assign _0267_ = _1617_ ? addr_b : _0278_; + assign _0307_ = _1617_ ? addr_a : _0318_; + assign _0269_ = _1539_ ? _0280_ : _0353_; + assign _0334_ = _1539_ ? _0342_ : _0390_; + assign _0204_ = _1539_ ? _0225_ : 8'h00; + assign _0333_ = _1539_ ? _0341_ : _0389_; + assign _0257_ = _1539_ ? _0268_ : _0289_; + assign _0256_ = _1539_ ? _0267_ : _0288_; + assign _0297_ = _1539_ ? _0307_ : _0331_; + assign _0208_ = _1539_ ? \receiver.frame_payload [823:696] : _0229_; + assign _0219_ = _1539_ ? \receiver.frame_payload [615:488] : _0239_; + assign _0212_ = _1539_ ? \receiver.frame_payload [487:480] : _0233_; + assign _0218_ = _1539_ ? \receiver.frame_payload [479:352] : _0238_; + assign _0211_ = _1539_ ? \receiver.frame_payload [351:344] : _0232_; + assign _0217_ = _1539_ ? \receiver.frame_payload [343:216] : _0237_; + assign _0210_ = _1539_ ? \receiver.frame_payload [215:208] : _0231_; + assign _0252_ = _1539_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0238_; + assign _0251_ = _1539_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0237_; + assign _0320_ = _1613_ ? 8'h96 : _0168_; + assign _0321_ = _1613_ ? 1'h0 : _0169_; + assign _0258_ = _1613_ ? 1'h0 : 1'h1; + assign _0312_ = _1610_ ? 8'h88 : _0320_; + assign _0313_ = _1610_ ? 1'h0 : _0321_; + assign _0244_ = _1610_ ? 1'h0 : _0258_; + assign _0243_ = _1610_ ? addr_c : _0458_; + assign _0242_ = _1610_ ? addr_b : _0457_; + assign _0287_ = _1610_ ? addr_a : _0456_; + assign _0302_ = _1605_ ? 8'h95 : _0312_; + assign _0303_ = _1605_ ? 1'h0 : _0313_; + assign _0224_ = _1605_ ? 1'h0 : _0244_; + assign _0223_ = _1605_ ? addr_c : _0243_; + assign _0222_ = _1605_ ? addr_b : _0242_; + assign _0277_ = _1605_ ? addr_a : _0287_; + assign _0292_ = _1604_ ? 8'h89 : _0302_; + assign _0293_ = _1604_ ? 1'h0 : _0303_; + assign _0203_ = _1604_ ? 1'h0 : _0224_; + assign _0202_ = _1604_ ? addr_c : _0223_; + assign _0201_ = _1604_ ? addr_b : _0222_; + assign _0266_ = _1604_ ? addr_a : _0277_; + assign _0183_ = _1534_ ? _0203_ : _0269_; + assign _0283_ = _1534_ ? _0293_ : _0334_; + assign _0282_ = _1534_ ? _0292_ : _0333_; + assign _0182_ = _1534_ ? _0202_ : _0257_; + assign _0181_ = _1534_ ? _0201_ : _0256_; + assign _0255_ = _1534_ ? _0266_ : _0297_; + assign _0198_ = _1534_ ? \receiver.frame_payload [647:520] : _0219_; + assign _0193_ = _1534_ ? \receiver.frame_payload [519:512] : _0212_; + assign _0197_ = _1534_ ? \receiver.frame_payload [511:384] : _0218_; + assign _0192_ = _1534_ ? \receiver.frame_payload [383:376] : _0211_; + assign _0196_ = _1534_ ? \receiver.frame_payload [343:216] : _0217_; + assign _0191_ = _1534_ ? \receiver.frame_payload [215:208] : _0210_; + assign _0184_ = _1534_ ? 8'h00 : _0204_; + assign _0236_ = _1534_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0252_; + assign _0235_ = _1534_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0251_; + assign _0362_ = _1555_ ? 32'd1 : 32'd0; + assign _0364_ = _1555_ ? \receiver.frame_payload [271:144] : 128'h00000000000000000000000000000000; + assign _0363_ = _1555_ ? _0456_ : 32'd0; + assign _0271_ = _1533_ ? 8'h8c : _0168_; + assign _0272_ = _1533_ ? 1'h0 : _0169_; + assign _0358_ = _1533_ ? 128'h00000000000000000000000000000000 : _0364_; + assign _0357_ = _1533_ ? 32'd0 : _0363_; + assign _0356_ = _1533_ ? 32'd0 : _0362_; + assign _0260_ = _1576_ ? 8'h88 : _0271_; + assign _0261_ = _1576_ ? 1'h0 : _0272_; + assign _0352_ = _1576_ ? 128'h00000000000000000000000000000000 : _0358_; + assign _0351_ = _1576_ ? 32'd0 : _0357_; + assign _0350_ = _1576_ ? 32'd0 : _0356_; + assign _0246_ = _1478_ ? 8'h89 : _0260_; + assign _0247_ = _1478_ ? 1'h0 : _0261_; + assign _0345_ = _1478_ ? 128'h00000000000000000000000000000000 : _0352_; + assign _0344_ = _1478_ ? 32'd0 : _0351_; + assign _0343_ = _1478_ ? 32'd0 : _0350_; + assign _0165_ = _1532_ ? 32'd0 : _0182_; + assign _0164_ = _1532_ ? 32'd0 : _0181_; + assign _0163_ = _1532_ ? _0456_ : _0255_; + assign _2520_ = _1532_ ? _0247_ : _0283_; + assign _2521_ = result_pending ? 1'hx : _2520_; + assign _2522_ = _1529_ ? 1'hx : _2521_; + assign _2523_ = _1528_ ? 1'hx : _2522_; + assign _2524_ = _1527_ ? 1'hx : _2523_; + assign _2525_ = _1526_ ? 1'hx : _2524_; + assign _2526_ = _1525_ ? 1'hx : _2525_; + assign _2527_ = _1677_ ? 1'hx : _2526_; + assign _2528_ = _1477_ ? 1'hx : _2527_; + assign _2529_ = _1591_ ? 1'hx : _2528_; + assign _2530_ = _1519_ ? 1'hx : _2529_; + assign _2531_ = _0887_ ? 1'hx : _2530_; + assign _2532_ = _0886_ ? 1'hx : _2531_; + assign _2533_ = _0885_ ? 1'hx : _2532_; + assign _2534_ = \receiver.fault_valid ? 1'hx : _2533_; + assign _2535_ = _1512_ ? _2534_ : 1'hx; + assign _2536_ = _1511_ ? 1'hx : _2535_; + assign _2537_ = _1510_ ? 1'hx : _2536_; + assign _2538_ = _1509_ ? 1'hx : _2537_; + assign _2539_ = _1508_ ? 1'hx : _2538_; + assign _2540_ = _1507_ ? 1'hx : _2539_; + assign _2541_ = _1506_ ? 1'hx : _2540_; + assign _2542_ = _1505_ ? 1'hx : _2541_; + assign _2543_ = _1504_ ? 1'hx : _2542_; + assign _2544_ = _1502_ ? 1'hx : _2543_; + assign _2545_ = _1501_ ? 1'hx : _2544_; + assign _2546_ = abort ? 1'hx : _2545_; + assign _0227_ = rst_n ? _2546_ : 1'hx; + assign _0226_ = _1532_ ? _0246_ : _0282_; + assign _0338_ = _1532_ ? _0345_ : 128'h00000000000000000000000000000000; + assign _0337_ = _1532_ ? _0344_ : 32'd0; + assign _2547_ = _1532_ ? _0343_ : 32'd0; + assign _2548_ = result_pending ? 32'hxxxxxxxx : _2547_; + assign _2549_ = _1529_ ? 32'hxxxxxxxx : _2548_; + assign _2550_ = _1528_ ? 32'hxxxxxxxx : _2549_; + assign _2551_ = _1527_ ? 32'hxxxxxxxx : _2550_; + assign _2552_ = _1526_ ? 32'hxxxxxxxx : _2551_; + assign _2553_ = _1525_ ? 32'hxxxxxxxx : _2552_; + assign _2554_ = _1677_ ? 32'hxxxxxxxx : _2553_; + assign _2555_ = _1477_ ? 32'hxxxxxxxx : _2554_; + assign _2556_ = _1591_ ? 32'hxxxxxxxx : _2555_; + assign _2557_ = _1519_ ? 32'hxxxxxxxx : _2556_; + assign _2558_ = _0887_ ? 32'hxxxxxxxx : _2557_; + assign _2559_ = _0886_ ? 32'hxxxxxxxx : _2558_; + assign _2560_ = _0885_ ? 32'hxxxxxxxx : _2559_; + assign _2561_ = \receiver.fault_valid ? 32'hxxxxxxxx : _2560_; + assign _2562_ = _1512_ ? _2561_ : 32'hxxxxxxxx; + assign _2563_ = _1511_ ? 32'hxxxxxxxx : _2562_; + assign _2564_ = _1510_ ? 32'hxxxxxxxx : _2563_; + assign _2565_ = _1509_ ? 32'hxxxxxxxx : _2564_; + assign _2566_ = _1508_ ? 32'hxxxxxxxx : _2565_; + assign _2567_ = _1507_ ? 32'hxxxxxxxx : _2566_; + assign _2568_ = _1506_ ? 32'hxxxxxxxx : _2567_; + assign _2569_ = _1505_ ? 32'hxxxxxxxx : _2568_; + assign _2570_ = _1504_ ? 32'hxxxxxxxx : _2569_; + assign _2571_ = _1502_ ? 32'hxxxxxxxx : _2570_; + assign _2572_ = _1501_ ? 32'hxxxxxxxx : _2571_; + assign _2573_ = abort ? 32'hxxxxxxxx : _2572_; + assign _0335_ = rst_n ? _2573_ : 32'hxxxxxxxx; + assign _0178_ = _1532_ ? \receiver.frame_payload [407:280] : _0196_; + assign _0174_ = _1532_ ? \receiver.frame_payload [279:272] : _0191_; + assign _0175_ = _1532_ ? \receiver.frame_payload [271:144] : result_value; + assign _0166_ = _1532_ ? 1'h0 : _0183_; + assign _0167_ = _1532_ ? 8'h00 : _0184_; + assign _0216_ = _1532_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0236_; + assign _0215_ = _1532_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0235_; + assign _0205_ = _1602_ ? 8'h95 : 8'h00; + assign _0206_ = _1602_ ? 1'h0 : 1'h1; + assign _0185_ = _1531_ ? 8'h94 : _0205_; + assign _0186_ = _1531_ ? 1'h0 : _0206_; + assign _0168_ = _1678_ ? 8'h86 : _0185_; + assign _2574_ = _1678_ ? 1'h0 : _0186_; + assign _2575_ = result_pending ? 1'hx : _2574_; + assign _2576_ = _1529_ ? 1'hx : _2575_; + assign _2577_ = _1528_ ? 1'hx : _2576_; + assign _2578_ = _1527_ ? 1'hx : _2577_; + assign _2579_ = _1526_ ? 1'hx : _2578_; + assign _2580_ = _1525_ ? 1'hx : _2579_; + assign _2581_ = _1677_ ? 1'hx : _2580_; + assign _2582_ = _1477_ ? 1'hx : _2581_; + assign _2583_ = _1591_ ? 1'hx : _2582_; + assign _2584_ = _1519_ ? 1'hx : _2583_; + assign _2585_ = _0887_ ? 1'hx : _2584_; + assign _2586_ = _0886_ ? 1'hx : _2585_; + assign _2587_ = _0885_ ? 1'hx : _2586_; + assign _2588_ = \receiver.fault_valid ? 1'hx : _2587_; + assign _2589_ = _1512_ ? _2588_ : 1'hx; + assign _2590_ = _1511_ ? 1'hx : _2589_; + assign _2591_ = _1510_ ? 1'hx : _2590_; + assign _2592_ = _1509_ ? 1'hx : _2591_; + assign _2593_ = _1508_ ? 1'hx : _2592_; + assign _2594_ = _1507_ ? 1'hx : _2593_; + assign _2595_ = _1506_ ? 1'hx : _2594_; + assign _2596_ = _1505_ ? 1'hx : _2595_; + assign _2597_ = _1504_ ? 1'hx : _2596_; + assign _2598_ = _1502_ ? 1'hx : _2597_; + assign _2599_ = _1501_ ? 1'hx : _2598_; + assign _2600_ = abort ? 1'hx : _2599_; + assign _0169_ = rst_n ? _2600_ : 1'hx; + assign _0324_ = result_pending ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0338_; + assign _0323_ = result_pending ? 32'hxxxxxxxx : _0337_; + assign _0195_ = result_pending ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0216_; + assign _0194_ = result_pending ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0215_; + assign _0273_ = result_pending ? 32'hxxxxxxxx : 32'd0; + assign _0189_ = result_pending ? 32'hxxxxxxxx : \receiver.frame_payload [95:64]; + assign _0190_ = result_pending ? 32'hxxxxxxxx : _0455_; + assign _0160_ = result_pending ? 32'hxxxxxxxx : \receiver.frame_payload [31:0]; + assign _0322_ = result_pending ? 32'hxxxxxxxx : _0335_; + assign _0317_ = _1529_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0324_; + assign _0316_ = _1529_ ? 32'hxxxxxxxx : _0323_; + assign _0177_ = _1529_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0195_; + assign _0176_ = _1529_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0194_; + assign _0262_ = _1529_ ? 32'hxxxxxxxx : _0273_; + assign _0172_ = _1529_ ? 32'hxxxxxxxx : _0189_; + assign _0173_ = _1529_ ? 32'hxxxxxxxx : _0190_; + assign _0413_ = _0870_ ? 32'd27 : 32'd19; + assign _0151_ = _1529_ ? 32'hxxxxxxxx : _0160_; + assign _0314_ = _1529_ ? 32'hxxxxxxxx : _0322_; + assign _0306_ = _1528_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0317_; + assign _0305_ = _1528_ ? 32'hxxxxxxxx : _0316_; + assign _0159_ = _1528_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0177_; + assign _0158_ = _1528_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0176_; + assign _0248_ = _1528_ ? 32'hxxxxxxxx : _0262_; + assign _0156_ = _1528_ ? 32'hxxxxxxxx : _0172_; + assign _0157_ = _1528_ ? 32'hxxxxxxxx : _0173_; + assign _0142_ = _1528_ ? 32'hxxxxxxxx : _0151_; + assign _0304_ = _1528_ ? 32'hxxxxxxxx : _0314_; + assign _0296_ = _1527_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0306_; + assign _0295_ = _1527_ ? 32'hxxxxxxxx : _0305_; + assign _0150_ = _1527_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0159_; + assign _0149_ = _1527_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0158_; + assign _0228_ = _1527_ ? 32'hxxxxxxxx : _0248_; + assign _0147_ = _1527_ ? 32'hxxxxxxxx : _0156_; + assign _0148_ = _1527_ ? 32'hxxxxxxxx : _0157_; + assign _0133_ = _1527_ ? 32'hxxxxxxxx : _0142_; + assign _0294_ = _1527_ ? 32'hxxxxxxxx : _0304_; + assign _0414_[175:168] = _1648_ ? _0416_[15:8] : 8'h00; + assign _0415_[31:0] = _0870_ ? _0164_ : 32'd0; + assign _0412_ = _0870_ ? 32'd47 : 32'd39; + assign _0286_ = _1526_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0296_; + assign _0285_ = _1526_ ? 32'hxxxxxxxx : _0295_; + assign _0141_ = _1526_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0150_; + assign _0140_ = _1526_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0149_; + assign _0414_[207:176] = _1648_ ? _0163_ : 32'd0; + assign _0207_ = _1526_ ? 32'hxxxxxxxx : _0228_; + assign _0138_ = _1526_ ? 32'hxxxxxxxx : _0147_; + assign _0139_ = _1526_ ? 32'hxxxxxxxx : _0148_; + assign _0411_ = _1648_ ? _0412_ : _0413_; + assign _0124_ = _1526_ ? 32'hxxxxxxxx : _0133_; + assign _0415_[63:32] = _0870_ ? _0165_ : 32'd0; + assign _0284_ = _1526_ ? 32'hxxxxxxxx : _0294_; + assign _0414_[159:32] = _1648_ ? _0338_ : { 48'h000000000000, _0415_, _0163_[31:16] }; + assign _0414_[31:0] = _1648_ ? _0337_ : { _0163_[15:0], _0416_[15:8], 8'h00 }; + assign _0276_ = _1525_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0286_; + assign _0275_ = _1525_ ? 32'hxxxxxxxx : _0285_; + assign _0414_[271:208] = _1648_ ? _0415_ : 64'h0000000000000000; + assign _0132_ = _1525_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0141_; + assign _0131_ = _1525_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0140_; + assign _0187_ = _1525_ ? 32'hxxxxxxxx : _0207_; + assign _0129_ = _1525_ ? 32'hxxxxxxxx : _0138_; + assign _0130_ = _1525_ ? 32'hxxxxxxxx : _0139_; + assign _0113_ = _1525_ ? 32'hxxxxxxxx : _0124_; + assign _0274_ = _1525_ ? 32'hxxxxxxxx : _0284_; + assign _0265_ = _1677_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0276_; + assign _0264_ = _1677_ ? 32'hxxxxxxxx : _0275_; + assign _0123_ = _1677_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0132_; + assign _0122_ = _1677_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0131_; + assign _0170_ = _1677_ ? 32'hxxxxxxxx : _0187_; + assign _0118_ = _1677_ ? 32'hxxxxxxxx : _0129_; + assign _0119_ = _1677_ ? 32'hxxxxxxxx : _0130_; + assign _0104_ = _1677_ ? 32'hxxxxxxxx : _0113_; + assign _0263_ = _1677_ ? 32'hxxxxxxxx : _0274_; + assign _0254_ = _1477_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0265_; + assign _0253_ = _1477_ ? 32'hxxxxxxxx : _0264_; + assign _0112_ = _1477_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0123_; + assign _0111_ = _1477_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0122_; + assign _0154_ = _1477_ ? 32'hxxxxxxxx : _0170_; + assign _0109_ = _1477_ ? 32'hxxxxxxxx : _0118_; + assign _0110_ = _1477_ ? 32'hxxxxxxxx : _0119_; + assign _0095_ = _1477_ ? 32'hxxxxxxxx : _0104_; + assign _0249_ = _1477_ ? 32'hxxxxxxxx : _0263_; + assign _0241_ = _1591_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0254_; + assign _0240_ = _1591_ ? 32'hxxxxxxxx : _0253_; + assign _0103_ = _1591_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0112_; + assign _0102_ = _1591_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0111_; + assign _0145_ = _1591_ ? 32'hxxxxxxxx : _0154_; + assign _0100_ = _1591_ ? 32'hxxxxxxxx : _0109_; + assign _0101_ = _1591_ ? 32'hxxxxxxxx : _0110_; + assign _0086_ = _1591_ ? 32'hxxxxxxxx : _0095_; + assign _0230_ = _1591_ ? 32'hxxxxxxxx : _0249_; + assign _2601_ = _1554_ ? 1'h1 : _0166_; + assign _2602_ = result_pending ? 1'hx : _2601_; + assign _2603_ = _1529_ ? 1'hx : _2602_; + assign _2604_ = _1528_ ? 1'hx : _2603_; + assign _2605_ = _1527_ ? 1'hx : _2604_; + assign _2606_ = _1526_ ? 1'hx : _2605_; + assign _2607_ = _1525_ ? 1'hx : _2606_; + assign _2608_ = _1677_ ? 1'hx : _2607_; + assign _2609_ = _1477_ ? 1'hx : _2608_; + assign _2610_ = _1591_ ? 1'hx : _2609_; + assign _2611_ = _1519_ ? 1'hx : _2610_; + assign _2612_ = _0887_ ? 1'hx : _2611_; + assign _2613_ = _0886_ ? 1'hx : _2612_; + assign _2614_ = _0885_ ? 1'hx : _2613_; + assign _2615_ = \receiver.fault_valid ? 1'hx : _2614_; + assign _2616_ = _1512_ ? _2615_ : 1'hx; + assign _2617_ = _1511_ ? 1'hx : _2616_; + assign _2618_ = _1510_ ? 1'hx : _2617_; + assign _2619_ = _1509_ ? 1'hx : _2618_; + assign _2620_ = _1508_ ? 1'hx : _2619_; + assign _2621_ = _1507_ ? 1'hx : _2620_; + assign _2622_ = _1506_ ? 1'hx : _2621_; + assign _2623_ = _1505_ ? 1'hx : _2622_; + assign _2624_ = _1504_ ? 1'hx : _2623_; + assign _2625_ = _1502_ ? 1'hx : _2624_; + assign _2626_ = _1501_ ? 1'hx : _2625_; + assign _2627_ = abort ? 1'hx : _2626_; + assign _0386_ = rst_n ? _2627_ : 1'hx; + assign _0377_ = _1553_ ? 1'h1 : _0359_; + assign _0374_ = _1552_ ? 1'h1 : _0377_; + assign _0403_ = _1568_ ? 8'h8b : _0391_; + assign _0221_ = _1519_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0241_; + assign _0220_ = _1519_ ? 32'hxxxxxxxx : _0240_; + assign _0094_ = _1519_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0103_; + assign _0093_ = _1519_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0102_; + assign _0136_ = _1519_ ? 32'hxxxxxxxx : _0145_; + assign _0091_ = _1519_ ? 32'hxxxxxxxx : _0100_; + assign _0404_ = _1568_ ? 1'h0 : _0392_; + assign _0092_ = _1519_ ? 32'hxxxxxxxx : _0101_; + assign _0077_ = _1519_ ? 32'hxxxxxxxx : _0086_; + assign _0209_ = _1519_ ? 32'hxxxxxxxx : _0230_; + assign _0371_ = _1568_ ? 1'h0 : 1'h1; + assign _0401_ = _1634_ ? 8'h8e : _0403_; + assign _0068_ = _0887_ ? \receiver.frame_payload [31:0] : _0077_; + assign _0402_ = _1634_ ? 1'h0 : _0404_; + assign _0368_ = _1634_ ? 1'h0 : _0371_; + assign _0365_ = _0889_ ? 1'h1 : _0368_; + assign _0200_ = _0887_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0221_; + assign _0199_ = _0887_ ? 32'hxxxxxxxx : _0220_; + assign _0085_ = _0887_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0094_; + assign _0084_ = _0887_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0093_; + assign _0400_ = _0889_ ? _0392_ : _0402_; + assign _0127_ = _0887_ ? 32'hxxxxxxxx : _0136_; + assign _0082_ = _0887_ ? 32'hxxxxxxxx : _0091_; + assign _0083_ = _0887_ ? 32'hxxxxxxxx : _0092_; + assign _0399_ = _0889_ ? _0391_ : _0401_; + assign _0188_ = _0887_ ? 32'hxxxxxxxx : _0209_; + assign _1767_ = _1548_ ? _0365_ : 1'h0; + assign _2628_ = _0169_ ? _1767_ : 1'hx; + assign _2629_ = _1539_ ? 1'hx : _2628_; + assign _2630_ = _1534_ ? 1'hx : _2629_; + assign _2631_ = _1532_ ? 1'hx : _2630_; + assign _2632_ = result_pending ? 1'hx : _2631_; + assign _2633_ = _1529_ ? 1'hx : _2632_; + assign _2634_ = _1528_ ? 1'hx : _2633_; + assign _2635_ = _1527_ ? 1'hx : _2634_; + assign _2636_ = _1526_ ? 1'hx : _2635_; + assign _2637_ = _1525_ ? 1'hx : _2636_; + assign _2638_ = _1677_ ? 1'hx : _2637_; + assign _2639_ = _1477_ ? 1'hx : _2638_; + assign _2640_ = _1591_ ? 1'hx : _2639_; + assign _2641_ = _1519_ ? 1'hx : _2640_; + assign _2642_ = _0887_ ? 1'hx : _2641_; + assign _2643_ = _0886_ ? 1'hx : _2642_; + assign _2644_ = _0885_ ? 1'hx : _2643_; + assign _2645_ = \receiver.fault_valid ? 1'hx : _2644_; + assign _2646_ = _1512_ ? _2645_ : 1'hx; + assign _2647_ = _1511_ ? 1'hx : _2646_; + assign _2648_ = _1510_ ? 1'hx : _2647_; + assign _2649_ = _1509_ ? 1'hx : _2648_; + assign _2650_ = _1508_ ? 1'hx : _2649_; + assign _2651_ = _1507_ ? 1'hx : _2650_; + assign _2652_ = _1506_ ? 1'hx : _2651_; + assign _2653_ = _1505_ ? 1'hx : _2652_; + assign _2654_ = _1504_ ? 1'hx : _2653_; + assign _2655_ = _1502_ ? 1'hx : _2654_; + assign _2656_ = _1501_ ? 1'hx : _2655_; + assign _2657_ = abort ? 1'hx : _2656_; + assign _0359_ = rst_n ? _2657_ : 1'hx; + assign _2658_ = _1548_ ? _0400_ : _0392_; + assign _2659_ = _0169_ ? _2658_ : 1'hx; + assign _2660_ = _1539_ ? 1'hx : _2659_; + assign _2661_ = _1534_ ? 1'hx : _2660_; + assign _2662_ = _1532_ ? 1'hx : _2661_; + assign _2663_ = result_pending ? 1'hx : _2662_; + assign _2664_ = _1529_ ? 1'hx : _2663_; + assign _2665_ = _1528_ ? 1'hx : _2664_; + assign _2666_ = _1527_ ? 1'hx : _2665_; + assign _2667_ = _1526_ ? 1'hx : _2666_; + assign _2668_ = _1525_ ? 1'hx : _2667_; + assign _2669_ = _1677_ ? 1'hx : _2668_; + assign _2670_ = _1477_ ? 1'hx : _2669_; + assign _2671_ = _1591_ ? 1'hx : _2670_; + assign _2672_ = _1519_ ? 1'hx : _2671_; + assign _2673_ = _0887_ ? 1'hx : _2672_; + assign _2674_ = _0886_ ? 1'hx : _2673_; + assign _2675_ = _0885_ ? 1'hx : _2674_; + assign _2676_ = \receiver.fault_valid ? 1'hx : _2675_; + assign _2677_ = _1512_ ? _2676_ : 1'hx; + assign _2678_ = _1511_ ? 1'hx : _2677_; + assign _2679_ = _1510_ ? 1'hx : _2678_; + assign _2680_ = _1509_ ? 1'hx : _2679_; + assign _2681_ = _1508_ ? 1'hx : _2680_; + assign _2682_ = _1507_ ? 1'hx : _2681_; + assign _2683_ = _1506_ ? 1'hx : _2682_; + assign _2684_ = _1505_ ? 1'hx : _2683_; + assign _2685_ = _1504_ ? 1'hx : _2684_; + assign _2686_ = _1502_ ? 1'hx : _2685_; + assign _2687_ = _1501_ ? 1'hx : _2686_; + assign _2688_ = abort ? 1'hx : _2687_; + assign _0398_ = rst_n ? _2688_ : 1'hx; + assign _0397_ = _1548_ ? _0399_ : _0391_; + assign _0395_ = _1627_ ? 8'h96 : _0168_; + assign _0396_ = _1627_ ? 1'h0 : 1'h1; + assign _0180_ = _0886_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0200_; + assign _0179_ = _0886_ ? 32'hxxxxxxxx : _0199_; + assign _0393_ = _1633_ ? 8'h88 : _0395_; + assign _0076_ = _0886_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0085_; + assign _0075_ = _0886_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0084_; + assign _0116_ = _0886_ ? 32'hxxxxxxxx : _0127_; + assign _0073_ = _0886_ ? 32'hxxxxxxxx : _0082_; + assign _0074_ = _0886_ ? 32'hxxxxxxxx : _0083_; + assign _0394_ = _1633_ ? 1'h0 : _0396_; + assign _0171_ = _0886_ ? 32'hxxxxxxxx : _0188_; + assign _0309_ = _1633_ ? addr_c : _0458_; + assign _0308_ = _1633_ ? addr_b : _0459_; + assign _0346_ = _1633_ ? addr_a : _0456_; + assign _0391_ = _1617_ ? 8'h89 : _0393_; + assign _0162_ = _0885_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0180_; + assign _0161_ = _0885_ ? 32'hxxxxxxxx : _0179_; + assign _0067_ = _0885_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0076_; + assign _0066_ = _0885_ ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0075_; + assign _2689_ = _1617_ ? 1'h0 : _0394_; + assign _2690_ = _0169_ ? _2689_ : 1'hx; + assign _2691_ = _1539_ ? 1'hx : _2690_; + assign _2692_ = _1534_ ? 1'hx : _2691_; + assign _0107_ = _0885_ ? 32'hxxxxxxxx : _0116_; + assign _2693_ = _1532_ ? 1'hx : _2692_; + assign _2694_ = result_pending ? 1'hx : _2693_; + assign _2695_ = _1529_ ? 1'hx : _2694_; + assign _0062_ = _0885_ ? 32'hxxxxxxxx : _0073_; + assign _2696_ = _1528_ ? 1'hx : _2695_; + assign _2697_ = _1527_ ? 1'hx : _2696_; + assign _0063_ = _0885_ ? 32'hxxxxxxxx : _0074_; + assign _2698_ = _1526_ ? 1'hx : _2697_; + assign _2699_ = _1525_ ? 1'hx : _2698_; + assign _2700_ = _1677_ ? 1'hx : _2699_; + assign _2701_ = _1477_ ? 1'hx : _2700_; + assign _2702_ = _1591_ ? 1'hx : _2701_; + assign _2703_ = _1519_ ? 1'hx : _2702_; + assign _2704_ = _0887_ ? 1'hx : _2703_; + assign _2705_ = _0886_ ? 1'hx : _2704_; + assign _2706_ = _0885_ ? 1'hx : _2705_; + assign _2707_ = \receiver.fault_valid ? 1'hx : _2706_; + assign _2708_ = _1512_ ? _2707_ : 1'hx; + assign _2709_ = _1511_ ? 1'hx : _2708_; + assign _2710_ = _1510_ ? 1'hx : _2709_; + assign _2711_ = _1509_ ? 1'hx : _2710_; + assign _2712_ = _1508_ ? 1'hx : _2711_; + assign _2713_ = _1507_ ? 1'hx : _2712_; + assign _2714_ = _1506_ ? 1'hx : _2713_; + assign _2715_ = _1505_ ? 1'hx : _2714_; + assign _2716_ = _1504_ ? 1'hx : _2715_; + assign _2717_ = _1502_ ? 1'hx : _2716_; + assign _2718_ = _1501_ ? 1'hx : _2717_; + assign _2719_ = abort ? 1'hx : _2718_; + assign _0392_ = rst_n ? _2719_ : 1'hx; + assign _0155_ = _0885_ ? 32'hxxxxxxxx : _0171_; + assign _0299_ = _1617_ ? addr_c : _0309_; + assign _0298_ = _1617_ ? addr_b : _0308_; + assign _0339_ = _1617_ ? addr_a : _0346_; + assign _0353_ = _0169_ ? _0374_ : 1'h0; + assign _0153_ = \receiver.fault_valid ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0162_; + assign _0152_ = \receiver.fault_valid ? 32'hxxxxxxxx : _0161_; + assign _0057_ = \receiver.fault_valid ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0067_; + assign _0056_ = \receiver.fault_valid ? 128'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _0066_; + assign _0390_ = _0169_ ? _0398_ : 1'h0; + assign _0098_ = \receiver.fault_valid ? 32'hxxxxxxxx : _0107_; + assign _0054_ = \receiver.fault_valid ? 32'hxxxxxxxx : _0062_; + assign _0055_ = \receiver.fault_valid ? 32'hxxxxxxxx : _0063_; + assign _0146_ = \receiver.fault_valid ? 32'hxxxxxxxx : _0155_; + assign _0389_ = _0169_ ? _0397_ : _0168_; + assign _1713_ = | \receiver.frame_payload [623:616]; + assign _2720_ = | pres_a; + assign _2721_ = | \receiver.frame_payload [215:208]; + assign _2722_ = 32'd4294967295 - \receiver.frame_payload [95:64]; + assign _2723_ = 32'd4294967295 - \receiver.frame_payload [375:344]; + assign _2724_ = _0873_ ? _0453_ : fp[15:0]; + assign _2725_ = _1565_ ? addr_a : addr_b; + assign _2726_ = _2720_ ? val_a : val_b; + assign _2727_ = _0884_ ? 32'd1 : 32'd0; + assign _2728_ = result_pending ? 8'h01 : 8'h00; + assign _2729_ = result_pending ? staged_txn_id : 32'd0; + assign _2730_ = _1663_ ? 32'd1 : 32'd2; + assign _2731_ = _0890_ ? { 24'h000000, \receiver.frame_payload [623:616] } : 32'd0; + assign _2732_ = _0890_ ? \receiver.frame_payload [751:624] : 128'h00000000000000000000000000000000; + assign _2733_ = _2721_ ? \receiver.frame_payload [343:216] : \receiver.frame_payload [479:352]; + assign { _2734_[31:8], _0416_[15:8] } = _0888_ ? 32'd1 : 32'd3; + assign _2735_ = \receiver.frame_payload [215:208] ^ \receiver.frame_payload [351:344]; + assign { _0213_[207:176], _0213_[167:160] } = { _0120_[207:176], _0120_[167:160] }; + assign { _0234_[175:112], _0234_[79:72], _0234_[47:16], _0234_[7:0] } = { _0064_[175:112], _0064_[7:0], _0064_[47:16], _0064_[7:0] }; + assign _0414_[167:160] = 8'h00; + assign { _0416_[175:16], _0416_[7:0] } = { 64'h0000000000000000, _0415_, _0163_, 8'h00 }; + assign _0911_[2:0] = 3'h0; + assign _0981_[28:0] = _0911_[31:3]; + assign _1099_[2:0] = 3'h0; + assign _1151_[28:0] = _1099_[31:3]; + assign _1341_[31] = 1'h0; + assign _1342_[31] = 1'h0; + assign _1343_[31] = 1'h0; + assign _1344_[31] = 1'h0; + assign _1345_[31] = 1'h0; + assign _1346_[31] = 1'h0; + assign _1347_[31] = 1'h0; + assign _1348_[31] = 1'h0; + assign _1349_[31] = 1'h0; + assign _1350_[31] = 1'h0; + assign _1351_[31] = 1'h0; + assign _1352_[31] = 1'h0; + assign _1353_[31] = 1'h0; + assign _1354_[31] = 1'h0; + assign _1355_[31] = 1'h0; + assign _1357_[31:1] = _1341_[30:0]; + assign _1358_[31:1] = _1342_[30:0]; + assign _1359_[31:1] = _1343_[30:0]; + assign _1360_[31:1] = _1344_[30:0]; + assign _1361_[31:1] = _1345_[30:0]; + assign _1362_[31:1] = _1346_[30:0]; + assign _1363_[31:1] = _1347_[30:0]; + assign _1365_[31:1] = _1349_[30:0]; + assign _1366_[31:1] = _1350_[30:0]; + assign _1367_[31:1] = _1351_[30:0]; + assign _1368_[31:1] = _1352_[30:0]; + assign _1369_[31:1] = _1353_[30:0]; + assign _1370_[31:1] = _1354_[30:0]; + assign _1371_[31:1] = _1355_[30:0]; + assign _1373_[31:1] = _1348_[30:0]; + assign _1380_[2:0] = 3'h0; + assign _1425_[31] = 1'h0; + assign _1426_[31] = 1'h0; + assign _1427_[31] = 1'h0; + assign _1428_[31] = 1'h0; + assign _1429_[31] = 1'h0; + assign _1430_[31] = 1'h0; + assign _1431_[31] = 1'h0; + assign _1432_[31] = 1'h0; + assign _1433_[31] = 1'h0; + assign _1434_[31] = 1'h0; + assign _1435_[31] = 1'h0; + assign _1436_[31] = 1'h0; + assign _1437_[31] = 1'h0; + assign _1438_[31] = 1'h0; + assign _1439_[31] = 1'h0; + assign _1440_[31] = 1'h0; + assign _1441_[28:0] = _1380_[31:3]; + assign _1443_[31:1] = _1426_[30:0]; + assign _1444_[31:1] = _1427_[30:0]; + assign _1445_[31:1] = _1428_[30:0]; + assign _1446_[31:1] = _1429_[30:0]; + assign _1447_[31:1] = _1430_[30:0]; + assign _1448_[31:1] = _1431_[30:0]; + assign _1449_[31:1] = _1432_[30:0]; + assign _1451_[31:1] = _1434_[30:0]; + assign _1452_[31:1] = _1435_[30:0]; + assign _1453_[31:1] = _1436_[30:0]; + assign _1454_[31:1] = _1437_[30:0]; + assign _1455_[31:1] = _1438_[30:0]; + assign _1456_[31:1] = _1439_[30:0]; + assign _1457_[31:1] = _1440_[30:0]; + assign _1460_[31:1] = _1425_[30:0]; + assign _1461_[31:1] = _1433_[30:0]; + assign _2734_[7:0] = _0416_[15:8]; + assign _unused_adapter_fault = \adapter.fault ; + assign \adapter._unused = 1'h0; + assign \adapter.abort = abort; + assign \adapter.clk = clk; + assign \adapter.core_fault = \adapter.datapath.fault ; + assign \adapter.datapath.abort = abort; + assign \adapter.datapath.clk = clk; + assign \adapter.datapath.mul_result_byte = \adapter.datapath.multiplier.impl.accumulator [7:0]; + assign \adapter.datapath.multiplier.a_byte = \adapter.core_rx_data ; + assign \adapter.datapath.multiplier.a_last = \adapter.datapath.multiplier.impl.a_last ; + assign \adapter.datapath.multiplier.a_valid = \adapter.datapath.mul_a_valid ; + assign \adapter.datapath.multiplier.abort = abort; + assign \adapter.datapath.multiplier.bit_last = \adapter.datapath.mul_bit_last ; + assign \adapter.datapath.multiplier.bit_valid = \adapter.datapath.mul_bit_valid ; + assign \adapter.datapath.multiplier.bit_value = \adapter.datapath.mul_bit_value ; + assign \adapter.datapath.multiplier.clk = clk; + assign \adapter.datapath.multiplier.impl.a_byte = \adapter.core_rx_data ; + assign \adapter.datapath.multiplier.impl.a_valid = \adapter.datapath.mul_a_valid ; + assign \adapter.datapath.multiplier.impl.abort = abort; + assign \adapter.datapath.multiplier.impl.bit_last = \adapter.datapath.mul_bit_last ; + assign \adapter.datapath.multiplier.impl.bit_valid = \adapter.datapath.mul_bit_valid ; + assign \adapter.datapath.multiplier.impl.bit_value = \adapter.datapath.mul_bit_value ; + assign \adapter.datapath.multiplier.impl.clk = clk; + assign \adapter.datapath.multiplier.impl.result_byte = \adapter.datapath.multiplier.impl.accumulator [7:0]; + assign \adapter.datapath.multiplier.impl.result_shift = \adapter.datapath.mul_result_shift ; + assign \adapter.datapath.multiplier.impl.rst_n = rst_n; + assign \adapter.datapath.multiplier.result_byte = \adapter.datapath.multiplier.impl.accumulator [7:0]; + assign \adapter.datapath.multiplier.result_shift = \adapter.datapath.mul_result_shift ; + assign \adapter.datapath.multiplier.rst_n = rst_n; + assign \adapter.datapath.rst_n = rst_n; + assign \adapter.datapath.rx_data = \adapter.core_rx_data ; + assign \adapter.datapath.rx_fire = \adapter.core_rx_fire ; + assign \adapter.datapath.rx_ready = \adapter.core_rx_ready ; + assign \adapter.datapath.rx_valid = \adapter.core_rx_valid ; + assign \adapter.datapath.status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.index = 4'hx; + assign \adapter.datapath.tx_data = \adapter.core_tx_data ; + assign \adapter.datapath.tx_fire = \adapter.core_tx_fire ; + assign \adapter.datapath.tx_ready = \adapter.core_tx_ready ; + assign \adapter.datapath.tx_valid = \adapter.core_tx_valid ; + assign \adapter.operand_a = alu_operand_a; + assign \adapter.operand_b = alu_operand_b; + assign \adapter.operation = alu_operation; + assign \adapter.rst_n = rst_n; + assign \adapter.start = alu_start; + assign alu_busy = \adapter.busy ; + assign alu_done = \adapter.done_pulse ; + assign alu_fault = \adapter.fault ; + assign alu_result = \adapter.result ; + assign encoder_busy = \field_encoder.busy ; + assign encoder_done = \field_encoder.done_pulse ; + assign encoder_fault = \field_encoder.fault ; + assign encoder_result = \field_encoder.result ; + assign event_ready = \receiver.frame_ready ; + assign \field_encoder.abort = abort; + assign \field_encoder.clk = clk; + assign \field_encoder.index = encoder_index; + assign \field_encoder.multiplier._unused = 1'h0; + assign \field_encoder.multiplier.abort = abort; + assign \field_encoder.multiplier.clk = clk; + assign \field_encoder.multiplier.core_fault = \field_encoder.multiplier.datapath.fault ; + assign \field_encoder.multiplier.core_rx_ready = \field_encoder.multiplier.datapath.rx_ready ; + assign \field_encoder.multiplier.core_tx_valid = \field_encoder.multiplier.datapath.tx_valid ; + assign \field_encoder.multiplier.datapath.abort = abort; + assign \field_encoder.multiplier.datapath.clk = clk; + assign \field_encoder.multiplier.datapath.mul_result_byte = \field_encoder.multiplier.datapath.multiplier.impl.accumulator [7:0]; + assign \field_encoder.multiplier.datapath.multiplier.a_byte = \field_encoder.multiplier.core_rx_data ; + assign \field_encoder.multiplier.datapath.multiplier.a_last = \field_encoder.multiplier.datapath.multiplier.impl.a_last ; + assign \field_encoder.multiplier.datapath.multiplier.a_valid = \field_encoder.multiplier.datapath.mul_a_valid ; + assign \field_encoder.multiplier.datapath.multiplier.abort = abort; + assign \field_encoder.multiplier.datapath.multiplier.bit_last = \field_encoder.multiplier.datapath.mul_bit_last ; + assign \field_encoder.multiplier.datapath.multiplier.bit_valid = \field_encoder.multiplier.datapath.mul_bit_valid ; + assign \field_encoder.multiplier.datapath.multiplier.bit_value = \field_encoder.multiplier.datapath.mul_bit_value ; + assign \field_encoder.multiplier.datapath.multiplier.clk = clk; + assign \field_encoder.multiplier.datapath.multiplier.impl.a_byte = \field_encoder.multiplier.core_rx_data ; + assign \field_encoder.multiplier.datapath.multiplier.impl.a_valid = \field_encoder.multiplier.datapath.mul_a_valid ; + assign \field_encoder.multiplier.datapath.multiplier.impl.abort = abort; + assign \field_encoder.multiplier.datapath.multiplier.impl.bit_last = \field_encoder.multiplier.datapath.mul_bit_last ; + assign \field_encoder.multiplier.datapath.multiplier.impl.bit_valid = \field_encoder.multiplier.datapath.mul_bit_valid ; + assign \field_encoder.multiplier.datapath.multiplier.impl.bit_value = \field_encoder.multiplier.datapath.mul_bit_value ; + assign \field_encoder.multiplier.datapath.multiplier.impl.clk = clk; + assign \field_encoder.multiplier.datapath.multiplier.impl.result_byte = \field_encoder.multiplier.datapath.multiplier.impl.accumulator [7:0]; + assign \field_encoder.multiplier.datapath.multiplier.impl.result_shift = \field_encoder.multiplier.datapath.mul_result_shift ; + assign \field_encoder.multiplier.datapath.multiplier.impl.rst_n = rst_n; + assign \field_encoder.multiplier.datapath.multiplier.result_byte = \field_encoder.multiplier.datapath.multiplier.impl.accumulator [7:0]; + assign \field_encoder.multiplier.datapath.multiplier.result_shift = \field_encoder.multiplier.datapath.mul_result_shift ; + assign \field_encoder.multiplier.datapath.multiplier.rst_n = rst_n; + assign \field_encoder.multiplier.datapath.rst_n = rst_n; + assign \field_encoder.multiplier.datapath.rx_data = \field_encoder.multiplier.core_rx_data ; + assign \field_encoder.multiplier.datapath.rx_fire = \field_encoder.multiplier.core_rx_fire ; + assign \field_encoder.multiplier.datapath.rx_valid = \field_encoder.multiplier.core_rx_valid ; + assign \field_encoder.multiplier.datapath.status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.index = 4'hx; + assign \field_encoder.multiplier.datapath.tx_data = \field_encoder.multiplier.core_tx_data ; + assign \field_encoder.multiplier.datapath.tx_fire = \field_encoder.multiplier.core_tx_fire ; + assign \field_encoder.multiplier.datapath.tx_ready = \field_encoder.multiplier.core_tx_ready ; + assign \field_encoder.multiplier.operand_a = \field_encoder.operand_b ; + assign \field_encoder.multiplier.operand_b = \field_encoder.operand_b ; + assign \field_encoder.multiplier.operation = 8'h02; + assign \field_encoder.multiplier.rst_n = rst_n; + assign \field_encoder.multiplier.saved_a = \field_encoder.multiplier.saved_b ; + assign { \field_encoder.multiplier.saved_operation [7:2], \field_encoder.multiplier.saved_operation [0] } = 7'h00; + assign \field_encoder.multiplier.start = \field_encoder.multiply_start ; + assign \field_encoder.multiply_done = \field_encoder.multiplier.done_pulse ; + assign \field_encoder.multiply_fault = \field_encoder.multiplier.fault ; + assign \field_encoder.multiply_result = \field_encoder.multiplier.result ; + assign \field_encoder.operand_a = \field_encoder.operand_b ; + assign \field_encoder.rst_n = rst_n; + assign \field_encoder.start = encoder_start; + assign frame_length = \receiver.frame_length ; + assign frame_opcode = \receiver.frame_opcode ; + assign frame_payload = \receiver.frame_payload ; + assign frame_valid = \receiver.frame_valid ; + assign parser_rx_ready = \receiver.rx_ready ; + assign \receiver.abort = abort; + assign \receiver.clk = clk; + assign \receiver.rst_n = rst_n; + assign \receiver.rx_data = rx_data; + assign rx_busy = \receiver.busy ; + assign rx_fault_status = \receiver.fault_status ; + assign rx_fault_valid = \receiver.fault_valid ; + assign \transmitter.abort = abort; + assign \transmitter.busy = \transmitter.active ; + assign \transmitter.clk = clk; + assign \transmitter.payload = tx_payload; + assign \transmitter.payload_length = tx_length; + assign \transmitter.rst_n = rst_n; + assign \transmitter.start = tx_start; + assign \transmitter.status = tx_status; + assign \transmitter.tx_ready = tx_ready; + assign \transmitter.tx_valid = \transmitter.active ; + assign tx_busy = \transmitter.active ; + assign tx_data = \transmitter.tx_data ; + assign tx_done = \transmitter.done_pulse ; + assign tx_payload_crc = \transmitter.payload_crc ; + assign tx_valid = \transmitter.active ; +endmodule diff --git a/results/b2-capability-contract-20260728/metadata.txt b/results/b2-capability-contract-20260728/metadata.txt new file mode 100644 index 0000000..c5f376f --- /dev/null +++ b/results/b2-capability-contract-20260728/metadata.txt @@ -0,0 +1,4 @@ +baseline_commit=fda85f5efc6f5b460d72204b4d9c0d882960ec29 +baseline_tree=df42a6211828d856e9a21ba61ecc2cd1b9dc4e71 +head=fda85f5efc6f5b460d72204b4d9c0d882960ec29 +head_tree=df42a6211828d856e9a21ba61ecc2cd1b9dc4e71 diff --git a/results/b2-capability-contract-20260728/model.command b/results/b2-capability-contract-20260728/model.command new file mode 100644 index 0000000..39ab9c4 --- /dev/null +++ b/results/b2-capability-contract-20260728/model.command @@ -0,0 +1 @@ +timeout 180s python3 -m unittest sim.test_packet_frontend_rtl_differential -v diff --git a/results/b2-capability-contract-20260728/model.log b/results/b2-capability-contract-20260728/model.log new file mode 100644 index 0000000..3b83974 --- /dev/null +++ b/results/b2-capability-contract-20260728/model.log @@ -0,0 +1,9 @@ +test_adversarial_jump_inverse_and_xor_backsolve_match_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_adversarial_jump_inverse_and_xor_backsolve_match_model) ... ok +test_deref_and_jump_faults_match_the_executable_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_faults_match_the_executable_model) ... ok +test_deref_and_jump_match_the_executable_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_match_the_executable_model) ... ok +test_seeded_set_xor_mul_and_frame_faults (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_seeded_set_xor_mul_and_frame_faults) ... ok + +---------------------------------------------------------------------- +Ran 4 tests in 1.117s + +OK diff --git a/results/b2-capability-contract-20260728/model.status b/results/b2-capability-contract-20260728/model.status new file mode 100644 index 0000000..04855a7 --- /dev/null +++ b/results/b2-capability-contract-20260728/model.status @@ -0,0 +1,2 @@ +exit_code=0 +duration_ms=1188 diff --git a/results/b2-capability-contract-20260728/model_final.command b/results/b2-capability-contract-20260728/model_final.command new file mode 100644 index 0000000..7416c6e --- /dev/null +++ b/results/b2-capability-contract-20260728/model_final.command @@ -0,0 +1 @@ +timeout 180s python3 -m unittest sim.test_packet_frontend_rtl_differential diff --git a/results/b2-capability-contract-20260728/model_final.log b/results/b2-capability-contract-20260728/model_final.log new file mode 100644 index 0000000..9a2050f --- /dev/null +++ b/results/b2-capability-contract-20260728/model_final.log @@ -0,0 +1,5 @@ +.... +---------------------------------------------------------------------- +Ran 4 tests in 1.047s + +OK diff --git a/results/b2-capability-contract-20260728/model_final.status b/results/b2-capability-contract-20260728/model_final.status new file mode 100644 index 0000000..5657c1d --- /dev/null +++ b/results/b2-capability-contract-20260728/model_final.status @@ -0,0 +1,2 @@ +exit=0 +duration_ms=1110 diff --git a/results/b2-capability-contract-20260728/mutation.command b/results/b2-capability-contract-20260728/mutation.command new file mode 100644 index 0000000..2dffec2 --- /dev/null +++ b/results/b2-capability-contract-20260728/mutation.command @@ -0,0 +1 @@ +timeout 180s make -C test/packet_frontend mutation diff --git a/results/b2-capability-contract-20260728/mutation.log b/results/b2-capability-contract-20260728/mutation.log new file mode 100644 index 0000000..0a21b86 --- /dev/null +++ b/results/b2-capability-contract-20260728/mutation.log @@ -0,0 +1,3 @@ +make: Entering directory '/workspaces/mission-ce702ac6/lean-silicon/test/packet_frontend' +PASS: BUSY, SET value, RETIRE ID, ABORT, length-order, and profile mutations were detected +make: Leaving directory '/workspaces/mission-ce702ac6/lean-silicon/test/packet_frontend' diff --git a/results/b2-capability-contract-20260728/mutation.status b/results/b2-capability-contract-20260728/mutation.status new file mode 100644 index 0000000..ea81621 --- /dev/null +++ b/results/b2-capability-contract-20260728/mutation.status @@ -0,0 +1,2 @@ +exit_code=0 +duration_ms=435 diff --git a/results/b2-capability-contract-20260728/mutation_final.command b/results/b2-capability-contract-20260728/mutation_final.command new file mode 100644 index 0000000..2dffec2 --- /dev/null +++ b/results/b2-capability-contract-20260728/mutation_final.command @@ -0,0 +1 @@ +timeout 180s make -C test/packet_frontend mutation diff --git a/results/b2-capability-contract-20260728/mutation_final.log b/results/b2-capability-contract-20260728/mutation_final.log new file mode 100644 index 0000000..0a21b86 --- /dev/null +++ b/results/b2-capability-contract-20260728/mutation_final.log @@ -0,0 +1,3 @@ +make: Entering directory '/workspaces/mission-ce702ac6/lean-silicon/test/packet_frontend' +PASS: BUSY, SET value, RETIRE ID, ABORT, length-order, and profile mutations were detected +make: Leaving directory '/workspaces/mission-ce702ac6/lean-silicon/test/packet_frontend' diff --git a/results/b2-capability-contract-20260728/mutation_final.status b/results/b2-capability-contract-20260728/mutation_final.status new file mode 100644 index 0000000..21e431e --- /dev/null +++ b/results/b2-capability-contract-20260728/mutation_final.status @@ -0,0 +1,2 @@ +exit=0 +duration_ms=400 diff --git a/results/b2-capability-contract-20260728/netlist.command b/results/b2-capability-contract-20260728/netlist.command new file mode 100644 index 0000000..90028b7 --- /dev/null +++ b/results/b2-capability-contract-20260728/netlist.command @@ -0,0 +1 @@ +timeout 180s yosys -p read_verilog\ -sv\ asic_core/rtl/lsc1_packet_rx.sv\ asic_core/rtl/lsc1_packet_tx.sv\ asic_core/rtl/gf2n_mul_bitstream.sv\ asic_core/rtl/gf128_mul_bitstream.sv\ asic_core/rtl/leanvm_b_stream_alu.sv\ asic_core/rtl/lsc1_stream_adapter.sv\ asic_core/rtl/lsc1_field_encoder.sv\ asic_core/rtl/lsc1_packet_frontend.sv\;\ hierarchy\ -check\ -top\ lsc1_packet_frontend\;\ proc\;\ memory\;\ flatten\;\ opt\;\ check\;\ write_verilog\ -noattr\ results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v\;\ stat diff --git a/results/b2-capability-contract-20260728/netlist.log b/results/b2-capability-contract-20260728/netlist.log new file mode 100644 index 0000000..9033521 --- /dev/null +++ b/results/b2-capability-contract-20260728/netlist.log @@ -0,0 +1,1328 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Running command `read_verilog -sv asic_core/rtl/lsc1_packet_rx.sv asic_core/rtl/lsc1_packet_tx.sv asic_core/rtl/gf2n_mul_bitstream.sv asic_core/rtl/gf128_mul_bitstream.sv asic_core/rtl/leanvm_b_stream_alu.sv asic_core/rtl/lsc1_stream_adapter.sv asic_core/rtl/lsc1_field_encoder.sv asic_core/rtl/lsc1_packet_frontend.sv; hierarchy -check -top lsc1_packet_frontend; proc; memory; flatten; opt; check; write_verilog -noattr results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v; stat' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_rx.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_tx.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_tx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_tx'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: asic_core/rtl/gf2n_mul_bitstream.sv +Parsing SystemVerilog input from `asic_core/rtl/gf2n_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf2n_mul_bitstream'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: asic_core/rtl/gf128_mul_bitstream.sv +Parsing SystemVerilog input from `asic_core/rtl/gf128_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf128_mul_bitstream'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: asic_core/rtl/leanvm_b_stream_alu.sv +Parsing SystemVerilog input from `asic_core/rtl/leanvm_b_stream_alu.sv' to AST representation. +Generating RTLIL representation for module `\leanvm_b_stream_alu'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_stream_adapter.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_stream_adapter.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_stream_adapter'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_field_encoder.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_field_encoder.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_field_encoder'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_frontend.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_frontend.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Successfully finished Verilog frontend. + +9. Executing HIERARCHY pass (managing design hierarchy). + +9.1. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: \gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 + +9.2. Executing AST frontend in derive mode using pre-parsed AST for module `\gf2n_mul_bitstream'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 +Generating RTLIL representation for module `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream'. + +9.3. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx + +9.4. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Removing unused module `\gf2n_mul_bitstream'. +Removed 1 unused modules. + +10. Executing PROC pass (convert processes to netlists). + +10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 10 empty switches in `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. +Cleaned up 10 empty switches. + +10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 109 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855 in module lsc1_packet_frontend. +Marked 5 switch rules as full_case in process $proc$asic_core/rtl/lsc1_field_encoder.sv:38$755 in module lsc1_field_encoder. +Marked 10 switch rules as full_case in process $proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671 in module lsc1_stream_adapter. +Marked 6 switch rules as full_case in process $proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646 in module lsc1_stream_adapter. +Marked 12 switch rules as full_case in process $proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615 in module leanvm_b_stream_alu. +Marked 3 switch rules as full_case in process $proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576 in module leanvm_b_stream_alu. +Marked 5 switch rules as full_case in process $proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172 in module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:62$258 in module lsc1_packet_tx. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:44$244 in module lsc1_packet_tx. +Marked 11 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_rx.sv:62$23 in module lsc1_packet_rx. +Removed a total of 0 dead cases. + +10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 8 redundant assignments. +Promoted 206 assignments to connections. + +10.4. Executing PROC_INIT pass (extract init attributes). + +10.5. Executing PROC_ARST pass (detect async resets in processes). + +10.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + 1/3417: $68\result_bytes[215:152] [63:32] + 2/3417: $68\result_bytes[215:152] [31:0] + 3/3417: $64\result_length[31:0] + 4/3417: $67\result_bytes[279:104] [111:80] + 5/3417: $67\result_bytes[279:104] [47:40] + 6/3417: $67\result_bytes[279:104] [15:8] + 7/3417: $67\result_bytes[279:104] [143:112] + 8/3417: $63\result_length[31:0] + 9/3417: $67\result_bytes[279:104] [79:72] + 10/3417: $67\result_bytes[279:104] [71:48] + 11/3417: $67\result_bytes[279:104] [39:16] + 12/3417: $67\result_bytes[279:104] [175:144] + 13/3417: $67\result_bytes[279:104] [7:0] + 14/3417: $65\result_bytes[375:104] [175:168] + 15/3417: $66\result_bytes[375:312] [31:0] + 16/3417: $62\result_length[31:0] + 17/3417: $65\result_bytes[375:104] [207:176] + 18/3417: $61\result_length[31:0] + 19/3417: $66\result_bytes[375:312] [63:32] + 20/3417: $65\result_bytes[375:104] [167:160] + 21/3417: $65\result_bytes[375:104] [159:32] + 22/3417: $65\result_bytes[375:104] [31:0] + 23/3417: $65\result_bytes[375:104] [271:208] + 24/3417: $64\result_bytes[543:0] [375:104] + 25/3417: $64\result_bytes[543:0] [103:96] + 26/3417: $64\result_bytes[543:0] [95:64] + 27/3417: $64\result_bytes[543:0] [63:32] + 28/3417: $64\result_bytes[543:0] [31:0] + 29/3417: $64\result_bytes[543:0] [543:376] + 30/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [31:0] + 31/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [39:32] + 32/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$3159 + 33/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$3158 + 34/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$3157 + 35/3417: $29\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$3161 + 36/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [543:40] + 37/3417: $60\result_length[31:0] + 38/3417: $28\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$3155 + 39/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3154 + 40/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$3153 + 41/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$3152 + 42/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$3151 + 43/3417: $63\result_bytes[543:0] + 44/3417: $59\result_length[31:0] + 45/3417: $50\decision_deferred[0:0] + 46/3417: $49\decision_deferred[0:0] + 47/3417: $48\decision_deferred[0:0] + 48/3417: $58\decision_fault[7:0] + 49/3417: $58\decision_ok[0:0] + 50/3417: $47\decision_deferred[0:0] + 51/3417: $57\decision_fault[7:0] + 52/3417: $57\decision_ok[0:0] + 53/3417: $46\decision_deferred[0:0] + 54/3417: $45\decision_deferred[0:0] + 55/3417: $56\decision_ok[0:0] + 56/3417: $56\decision_fault[7:0] + 57/3417: $44\decision_deferred[0:0] + 58/3417: $55\decision_ok[0:0] + 59/3417: $55\decision_fault[7:0] + 60/3417: $54\decision_fault[7:0] + 61/3417: $54\decision_ok[0:0] + 62/3417: $53\decision_fault[7:0] + 63/3417: $53\decision_ok[0:0] + 64/3417: $38\addr_c[31:0] + 65/3417: $38\addr_b[31:0] + 66/3417: $42\addr_a[31:0] + 67/3417: $52\decision_fault[7:0] + 68/3417: $52\decision_ok[0:0] + 69/3417: $37\addr_c[31:0] + 70/3417: $37\addr_b[31:0] + 71/3417: $41\addr_a[31:0] + 72/3417: $43\decision_deferred[0:0] + 73/3417: $51\decision_ok[0:0] + 74/3417: $51\decision_fault[7:0] + 75/3417: $33\solved_b[127:0] + 76/3417: $33\solved_a[127:0] + 77/3417: $36\addr_c[31:0] + 78/3417: $36\addr_b[31:0] + 79/3417: $40\addr_a[31:0] + 80/3417: $31\inv_value[127:0] + 81/3417: $31\inv_present[7:0] + 82/3417: $31\val_c[127:0] + 83/3417: $31\pres_c[7:0] + 84/3417: $31\val_b[127:0] + 85/3417: $31\pres_b[7:0] + 86/3417: $31\val_a[127:0] + 87/3417: $31\pres_a[7:0] + 88/3417: $31\off_c[31:0] + 89/3417: $31\off_b[31:0] + 90/3417: $31\off_a[31:0] + 91/3417: $38\decision_detail[7:0] + 92/3417: $50\decision_fault[7:0] + 93/3417: $50\decision_ok[0:0] + 94/3417: $37\decision_detail[7:0] + 95/3417: $49\decision_fault[7:0] + 96/3417: $49\decision_ok[0:0] + 97/3417: $48\decision_fault[7:0] + 98/3417: $48\decision_ok[0:0] + 99/3417: $42\decision_deferred[0:0] + 100/3417: $47\decision_fault[7:0] + 101/3417: $47\decision_ok[0:0] + 102/3417: $41\decision_deferred[0:0] + 103/3417: $40\decision_deferred[0:0] + 104/3417: $46\decision_ok[0:0] + 105/3417: $46\decision_fault[7:0] + 106/3417: $36\decision_detail[7:0] + 107/3417: $35\decision_detail[7:0] + 108/3417: $45\decision_fault[7:0] + 109/3417: $45\decision_ok[0:0] + 110/3417: $39\decision_deferred[0:0] + 111/3417: $34\decision_detail[7:0] + 112/3417: $44\decision_fault[7:0] + 113/3417: $44\decision_ok[0:0] + 114/3417: $38\decision_deferred[0:0] + 115/3417: $43\decision_fault[7:0] + 116/3417: $43\decision_ok[0:0] + 117/3417: $37\decision_deferred[0:0] + 118/3417: $33\decision_detail[7:0] + 119/3417: $42\decision_fault[7:0] + 120/3417: $42\decision_ok[0:0] + 121/3417: $36\decision_deferred[0:0] + 122/3417: $32\decision_detail[7:0] + 123/3417: $35\addr_c[31:0] + 124/3417: $35\addr_b[31:0] + 125/3417: $39\addr_a[31:0] + 126/3417: $41\decision_fault[7:0] + 127/3417: $41\decision_ok[0:0] + 128/3417: $35\decision_deferred[0:0] + 129/3417: $31\decision_detail[7:0] + 130/3417: $34\addr_c[31:0] + 131/3417: $34\addr_b[31:0] + 132/3417: $38\addr_a[31:0] + 133/3417: $34\decision_deferred[0:0] + 134/3417: $40\decision_ok[0:0] + 135/3417: $30\decision_detail[7:0] + 136/3417: $40\decision_fault[7:0] + 137/3417: $33\addr_c[31:0] + 138/3417: $33\addr_b[31:0] + 139/3417: $37\addr_a[31:0] + 140/3417: $30\inv_value[127:0] + 141/3417: $30\inv_present[7:0] + 142/3417: $30\proposed_fp[31:0] + 143/3417: $30\proposed_pc[31:0] + 144/3417: $30\taken_proposal[7:0] + 145/3417: $30\val_c[127:0] + 146/3417: $30\pres_c[7:0] + 147/3417: $30\val_b[127:0] + 148/3417: $30\pres_b[7:0] + 149/3417: $30\val_a[127:0] + 150/3417: $30\pres_a[7:0] + 151/3417: $30\off_c[31:0] + 152/3417: $30\off_b[31:0] + 153/3417: $30\off_a[31:0] + 154/3417: $32\solved_b[127:0] + 155/3417: $32\solved_a[127:0] + 156/3417: $39\decision_fault[7:0] + 157/3417: $39\decision_ok[0:0] + 158/3417: $33\decision_deferred[0:0] + 159/3417: $38\decision_fault[7:0] + 160/3417: $38\decision_ok[0:0] + 161/3417: $32\decision_deferred[0:0] + 162/3417: $32\addr_c[31:0] + 163/3417: $32\addr_b[31:0] + 164/3417: $36\addr_a[31:0] + 165/3417: $37\decision_fault[7:0] + 166/3417: $37\decision_ok[0:0] + 167/3417: $31\decision_deferred[0:0] + 168/3417: $31\addr_c[31:0] + 169/3417: $31\addr_b[31:0] + 170/3417: $35\addr_a[31:0] + 171/3417: $36\decision_fault[7:0] + 172/3417: $36\decision_ok[0:0] + 173/3417: $30\decision_deferred[0:0] + 174/3417: $30\addr_c[31:0] + 175/3417: $30\addr_b[31:0] + 176/3417: $34\addr_a[31:0] + 177/3417: $29\decision_deferred[0:0] + 178/3417: $35\decision_ok[0:0] + 179/3417: $35\decision_fault[7:0] + 180/3417: $29\addr_c[31:0] + 181/3417: $29\addr_b[31:0] + 182/3417: $33\addr_a[31:0] + 183/3417: $29\val_c[127:0] + 184/3417: $29\pres_c[7:0] + 185/3417: $29\val_b[127:0] + 186/3417: $29\pres_b[7:0] + 187/3417: $29\base_index[31:0] + 188/3417: $29\val_a[127:0] + 189/3417: $29\pres_a[7:0] + 190/3417: $29\off_c[31:0] + 191/3417: $29\off_b[31:0] + 192/3417: $29\off_a[31:0] + 193/3417: $29\decision_detail[7:0] + 194/3417: $31\solved_b[127:0] + 195/3417: $31\solved_a[127:0] + 196/3417: $29\inv_value[127:0] + 197/3417: $29\taken_proposal[7:0] + 198/3417: $29\inv_present[7:0] + 199/3417: $29\proposed_fp[31:0] + 200/3417: $29\proposed_pc[31:0] + 201/3417: $44\n_writes[31:0] + 202/3417: $44\write_value[127:0] + 203/3417: $44\write_address[31:0] + 204/3417: $32\addr_a[31:0] + 205/3417: $34\decision_fault[7:0] + 206/3417: $34\decision_ok[0:0] + 207/3417: $43\write_value[127:0] + 208/3417: $43\write_address[31:0] + 209/3417: $31\addr_a[31:0] + 210/3417: $43\n_writes[31:0] + 211/3417: $33\decision_fault[7:0] + 212/3417: $33\decision_ok[0:0] + 213/3417: $42\write_value[127:0] + 214/3417: $42\write_address[31:0] + 215/3417: $30\addr_a[31:0] + 216/3417: $42\n_writes[31:0] + 217/3417: $32\decision_fault[7:0] + 218/3417: $32\decision_ok[0:0] + 219/3417: $41\write_value[127:0] + 220/3417: $41\write_address[31:0] + 221/3417: $29\addr_a[31:0] + 222/3417: $41\n_writes[31:0] + 223/3417: $28\addr_c[31:0] + 224/3417: $28\addr_b[31:0] + 225/3417: $28\addr_a[31:0] + 226/3417: $31\decision_ok[0:0] + 227/3417: $31\decision_fault[7:0] + 228/3417: $40\write_value[127:0] + 229/3417: $40\write_address[31:0] + 230/3417: $40\n_writes[31:0] + 231/3417: $28\val_a[127:0] + 232/3417: $28\pres_a[7:0] + 233/3417: $28\result_value[127:0] + 234/3417: $28\off_a[31:0] + 235/3417: $28\decision_deferred[0:0] + 236/3417: $28\decision_detail[7:0] + 237/3417: $30\solved_b[127:0] + 238/3417: $30\solved_a[127:0] + 239/3417: $28\inv_value[127:0] + 240/3417: $28\val_c[127:0] + 241/3417: $28\val_b[127:0] + 242/3417: $28\taken_proposal[7:0] + 243/3417: $28\inv_present[7:0] + 244/3417: $28\pres_c[7:0] + 245/3417: $28\pres_b[7:0] + 246/3417: $28\proposed_fp[31:0] + 247/3417: $28\proposed_pc[31:0] + 248/3417: $28\base_index[31:0] + 249/3417: $28\off_c[31:0] + 250/3417: $28\off_b[31:0] + 251/3417: $30\decision_fault[7:0] + 252/3417: $30\decision_ok[0:0] + 253/3417: $29\decision_fault[7:0] + 254/3417: $29\decision_ok[0:0] + 255/3417: $28\decision_fault[7:0] + 256/3417: $28\decision_ok[0:0] + 257/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [543:40] + 258/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [31:0] + 259/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [39:32] + 260/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2916 + 261/3417: $27\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2922 + 262/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2921 + 263/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2920 + 264/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2919 + 265/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2918 + 266/3417: $27\decision_deferred[0:0] + 267/3417: $27\decision_ok[0:0] + 268/3417: $27\decision_detail[7:0] + 269/3417: $27\decision_fault[7:0] + 270/3417: $39\write_value[127:0] + 271/3417: $39\write_address[31:0] + 272/3417: $62\result_bytes[543:0] + 273/3417: $29\solved_b[127:0] + 274/3417: $29\solved_a[127:0] + 275/3417: $27\result_value[127:0] + 276/3417: $27\inv_value[127:0] + 277/3417: $27\val_c[127:0] + 278/3417: $27\val_b[127:0] + 279/3417: $27\val_a[127:0] + 280/3417: $27\taken_proposal[7:0] + 281/3417: $27\inv_present[7:0] + 282/3417: $27\pres_c[7:0] + 283/3417: $27\pres_b[7:0] + 284/3417: $27\pres_a[7:0] + 285/3417: $27\profile[7:0] + 286/3417: $34\deferred_local[31:0] + 287/3417: $34\deferred_target[31:0] + 288/3417: $29\next_fp_value[31:0] + 289/3417: $29\next_pc_value[31:0] + 290/3417: $27\proposed_fp[31:0] + 291/3417: $27\proposed_pc[31:0] + 292/3417: $27\base_index[31:0] + 293/3417: $27\addr_c[31:0] + 294/3417: $27\addr_b[31:0] + 295/3417: $27\addr_a[31:0] + 296/3417: $27\off_c[31:0] + 297/3417: $27\off_b[31:0] + 298/3417: $27\off_a[31:0] + 299/3417: $27\fp[31:0] + 300/3417: $27\pc[31:0] + 301/3417: $27\txn_id[31:0] + 302/3417: $58\result_length[31:0] + 303/3417: $34\n_deferred[31:0] + 304/3417: $39\n_writes[31:0] + 305/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [543:40] + 306/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [31:0] + 307/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [39:32] + 308/3417: $26\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2915 + 309/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2914 + 310/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2913 + 311/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2912 + 312/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2911 + 313/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2910 + 314/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2909 + 315/3417: $26\decision_deferred[0:0] + 316/3417: $26\decision_ok[0:0] + 317/3417: $26\decision_detail[7:0] + 318/3417: $26\decision_fault[7:0] + 319/3417: $38\write_value[127:0] + 320/3417: $38\write_address[31:0] + 321/3417: $61\result_bytes[543:0] + 322/3417: $28\solved_b[127:0] + 323/3417: $28\solved_a[127:0] + 324/3417: $26\result_value[127:0] + 325/3417: $26\inv_value[127:0] + 326/3417: $26\val_c[127:0] + 327/3417: $26\val_b[127:0] + 328/3417: $26\val_a[127:0] + 329/3417: $26\taken_proposal[7:0] + 330/3417: $26\inv_present[7:0] + 331/3417: $26\pres_c[7:0] + 332/3417: $26\pres_b[7:0] + 333/3417: $26\pres_a[7:0] + 334/3417: $26\profile[7:0] + 335/3417: $33\deferred_local[31:0] + 336/3417: $33\deferred_target[31:0] + 337/3417: $28\next_fp_value[31:0] + 338/3417: $28\next_pc_value[31:0] + 339/3417: $26\proposed_fp[31:0] + 340/3417: $26\proposed_pc[31:0] + 341/3417: $26\base_index[31:0] + 342/3417: $26\addr_c[31:0] + 343/3417: $26\addr_b[31:0] + 344/3417: $26\addr_a[31:0] + 345/3417: $26\off_c[31:0] + 346/3417: $26\off_b[31:0] + 347/3417: $26\off_a[31:0] + 348/3417: $26\fp[31:0] + 349/3417: $26\pc[31:0] + 350/3417: $26\txn_id[31:0] + 351/3417: $57\result_length[31:0] + 352/3417: $33\n_deferred[31:0] + 353/3417: $38\n_writes[31:0] + 354/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [543:40] + 355/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [31:0] + 356/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [39:32] + 357/3417: $25\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2878 + 358/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2877 + 359/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2876 + 360/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2875 + 361/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2874 + 362/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2873 + 363/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2872 + 364/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2871 + 365/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2870 + 366/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2869 + 367/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2868 + 368/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2867 + 369/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2866 + 370/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2865 + 371/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2864 + 372/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2863 + 373/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2862 + 374/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2861 + 375/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2860 + 376/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2859 + 377/3417: $25\decision_deferred[0:0] + 378/3417: $25\decision_ok[0:0] + 379/3417: $25\decision_detail[7:0] + 380/3417: $25\decision_fault[7:0] + 381/3417: $37\write_value[127:0] + 382/3417: $37\write_address[31:0] + 383/3417: $60\result_bytes[543:0] + 384/3417: $27\solved_b[127:0] + 385/3417: $27\solved_a[127:0] + 386/3417: $25\result_value[127:0] + 387/3417: $25\inv_value[127:0] + 388/3417: $25\val_c[127:0] + 389/3417: $25\val_b[127:0] + 390/3417: $25\val_a[127:0] + 391/3417: $25\taken_proposal[7:0] + 392/3417: $25\inv_present[7:0] + 393/3417: $25\pres_c[7:0] + 394/3417: $25\pres_b[7:0] + 395/3417: $25\pres_a[7:0] + 396/3417: $25\profile[7:0] + 397/3417: $32\deferred_local[31:0] + 398/3417: $32\deferred_target[31:0] + 399/3417: $27\next_fp_value[31:0] + 400/3417: $27\next_pc_value[31:0] + 401/3417: $25\proposed_fp[31:0] + 402/3417: $25\proposed_pc[31:0] + 403/3417: $25\base_index[31:0] + 404/3417: $25\addr_c[31:0] + 405/3417: $25\addr_b[31:0] + 406/3417: $25\addr_a[31:0] + 407/3417: $25\off_c[31:0] + 408/3417: $25\off_b[31:0] + 409/3417: $25\off_a[31:0] + 410/3417: $25\fp[31:0] + 411/3417: $25\pc[31:0] + 412/3417: $25\txn_id[31:0] + 413/3417: $56\result_length[31:0] + 414/3417: $32\n_deferred[31:0] + 415/3417: $37\n_writes[31:0] + 416/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [543:40] + 417/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [31:0] + 418/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [39:32] + 419/3417: $24\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2854 + 420/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2853 + 421/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2852 + 422/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2851 + 423/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2850 + 424/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2849 + 425/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2848 + 426/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2847 + 427/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2846 + 428/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2845 + 429/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2844 + 430/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2843 + 431/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2842 + 432/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2841 + 433/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2840 + 434/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2839 + 435/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2838 + 436/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2837 + 437/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2836 + 438/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2835 + 439/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2834 + 440/3417: $24\decision_deferred[0:0] + 441/3417: $24\decision_ok[0:0] + 442/3417: $24\decision_detail[7:0] + 443/3417: $24\decision_fault[7:0] + 444/3417: $36\write_value[127:0] + 445/3417: $36\write_address[31:0] + 446/3417: $59\result_bytes[543:0] + 447/3417: $26\solved_b[127:0] + 448/3417: $26\solved_a[127:0] + 449/3417: $24\result_value[127:0] + 450/3417: $24\inv_value[127:0] + 451/3417: $24\val_c[127:0] + 452/3417: $24\val_b[127:0] + 453/3417: $24\val_a[127:0] + 454/3417: $24\taken_proposal[7:0] + 455/3417: $24\inv_present[7:0] + 456/3417: $24\pres_c[7:0] + 457/3417: $24\pres_b[7:0] + 458/3417: $24\pres_a[7:0] + 459/3417: $24\profile[7:0] + 460/3417: $31\deferred_local[31:0] + 461/3417: $31\deferred_target[31:0] + 462/3417: $26\next_fp_value[31:0] + 463/3417: $26\next_pc_value[31:0] + 464/3417: $24\proposed_fp[31:0] + 465/3417: $24\proposed_pc[31:0] + 466/3417: $24\base_index[31:0] + 467/3417: $24\addr_c[31:0] + 468/3417: $24\addr_b[31:0] + 469/3417: $24\addr_a[31:0] + 470/3417: $24\off_c[31:0] + 471/3417: $24\off_b[31:0] + 472/3417: $24\off_a[31:0] + 473/3417: $24\fp[31:0] + 474/3417: $24\pc[31:0] + 475/3417: $24\txn_id[31:0] + 476/3417: $55\result_length[31:0] + 477/3417: $31\n_deferred[31:0] + 478/3417: $36\n_writes[31:0] + 479/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [543:40] + 480/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [31:0] + 481/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [39:32] + 482/3417: $23\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2807 + 483/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2806 + 484/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2805 + 485/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2804 + 486/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2803 + 487/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2802 + 488/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2801 + 489/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2800 + 490/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2799 + 491/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2798 + 492/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2797 + 493/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2796 + 494/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2795 + 495/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2794 + 496/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2793 + 497/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2792 + 498/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2791 + 499/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2790 + 500/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2789 + 501/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2788 + 502/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2787 + 503/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2786 + 504/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2785 + 505/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2784 + 506/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2783 + 507/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2782 + 508/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2781 + 509/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2780 + 510/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2779 + 511/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2778 + 512/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2777 + 513/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2776 + 514/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2775 + 515/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2774 + 516/3417: $23\decision_deferred[0:0] + 517/3417: $23\decision_ok[0:0] + 518/3417: $23\decision_detail[7:0] + 519/3417: $23\decision_fault[7:0] + 520/3417: $35\write_value[127:0] + 521/3417: $35\write_address[31:0] + 522/3417: $58\result_bytes[543:0] + 523/3417: $25\solved_b[127:0] + 524/3417: $25\solved_a[127:0] + 525/3417: $23\result_value[127:0] + 526/3417: $23\inv_value[127:0] + 527/3417: $23\val_c[127:0] + 528/3417: $23\val_b[127:0] + 529/3417: $23\val_a[127:0] + 530/3417: $23\taken_proposal[7:0] + 531/3417: $23\inv_present[7:0] + 532/3417: $23\pres_c[7:0] + 533/3417: $23\pres_b[7:0] + 534/3417: $23\pres_a[7:0] + 535/3417: $23\profile[7:0] + 536/3417: $30\deferred_local[31:0] + 537/3417: $30\deferred_target[31:0] + 538/3417: $25\next_fp_value[31:0] + 539/3417: $25\next_pc_value[31:0] + 540/3417: $23\proposed_fp[31:0] + 541/3417: $23\proposed_pc[31:0] + 542/3417: $23\base_index[31:0] + 543/3417: $23\addr_c[31:0] + 544/3417: $23\addr_b[31:0] + 545/3417: $23\addr_a[31:0] + 546/3417: $23\off_c[31:0] + 547/3417: $23\off_b[31:0] + 548/3417: $23\off_a[31:0] + 549/3417: $23\fp[31:0] + 550/3417: $23\pc[31:0] + 551/3417: $23\txn_id[31:0] + 552/3417: $54\result_length[31:0] + 553/3417: $30\n_deferred[31:0] + 554/3417: $35\n_writes[31:0] + 555/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [543:40] + 556/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [31:0] + 557/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [39:32] + 558/3417: $22\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2749 + 559/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2748 + 560/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2747 + 561/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2746 + 562/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2745 + 563/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2744 + 564/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2743 + 565/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2742 + 566/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2741 + 567/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2740 + 568/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2739 + 569/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2738 + 570/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2737 + 571/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2736 + 572/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2735 + 573/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2734 + 574/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2733 + 575/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2732 + 576/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2731 + 577/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2730 + 578/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2729 + 579/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2728 + 580/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2727 + 581/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2726 + 582/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2725 + 583/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2724 + 584/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2723 + 585/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2722 + 586/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2721 + 587/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2720 + 588/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2719 + 589/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2718 + 590/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2717 + 591/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2716 + 592/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2715 + 593/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2714 + 594/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2713 + 595/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2712 + 596/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2711 + 597/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2710 + 598/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2709 + 599/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2708 + 600/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2707 + 601/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2706 + 602/3417: $22\decision_deferred[0:0] + 603/3417: $22\decision_ok[0:0] + 604/3417: $22\decision_detail[7:0] + 605/3417: $22\decision_fault[7:0] + 606/3417: $34\write_value[127:0] + 607/3417: $34\write_address[31:0] + 608/3417: $57\result_bytes[543:0] + 609/3417: $24\solved_b[127:0] + 610/3417: $24\solved_a[127:0] + 611/3417: $22\result_value[127:0] + 612/3417: $22\inv_value[127:0] + 613/3417: $22\val_c[127:0] + 614/3417: $22\val_b[127:0] + 615/3417: $22\val_a[127:0] + 616/3417: $22\taken_proposal[7:0] + 617/3417: $22\inv_present[7:0] + 618/3417: $22\pres_c[7:0] + 619/3417: $22\pres_b[7:0] + 620/3417: $22\pres_a[7:0] + 621/3417: $22\profile[7:0] + 622/3417: $29\deferred_local[31:0] + 623/3417: $29\deferred_target[31:0] + 624/3417: $24\next_fp_value[31:0] + 625/3417: $24\next_pc_value[31:0] + 626/3417: $22\proposed_fp[31:0] + 627/3417: $22\proposed_pc[31:0] + 628/3417: $22\base_index[31:0] + 629/3417: $22\addr_c[31:0] + 630/3417: $22\addr_b[31:0] + 631/3417: $22\addr_a[31:0] + 632/3417: $22\off_c[31:0] + 633/3417: $22\off_b[31:0] + 634/3417: $22\off_a[31:0] + 635/3417: $22\fp[31:0] + 636/3417: $22\pc[31:0] + 637/3417: $22\txn_id[31:0] + 638/3417: $53\result_length[31:0] + 639/3417: $29\n_deferred[31:0] + 640/3417: $34\n_writes[31:0] + 641/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [543:40] + 642/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [31:0] + 643/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [39:32] + 644/3417: $21\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2697 + 645/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2696 + 646/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2695 + 647/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2694 + 648/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2693 + 649/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2692 + 650/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2691 + 651/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2690 + 652/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2689 + 653/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2688 + 654/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2687 + 655/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2686 + 656/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2685 + 657/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2684 + 658/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2683 + 659/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2682 + 660/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2681 + 661/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2680 + 662/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2679 + 663/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2678 + 664/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2677 + 665/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2676 + 666/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2675 + 667/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2674 + 668/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2673 + 669/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2672 + 670/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2671 + 671/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2670 + 672/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2669 + 673/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2668 + 674/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2667 + 675/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2666 + 676/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2665 + 677/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2664 + 678/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2663 + 679/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2662 + 680/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2661 + 681/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2660 + 682/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2659 + 683/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2658 + 684/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2657 + 685/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2656 + 686/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2655 + 687/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2654 + 688/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2653 + 689/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2652 + 690/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2651 + 691/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2650 + 692/3417: $21\decision_deferred[0:0] + 693/3417: $21\decision_ok[0:0] + 694/3417: $21\decision_detail[7:0] + 695/3417: $21\decision_fault[7:0] + 696/3417: $33\write_value[127:0] + 697/3417: $33\write_address[31:0] + 698/3417: $56\result_bytes[543:0] + 699/3417: $23\solved_b[127:0] + 700/3417: $23\solved_a[127:0] + 701/3417: $21\result_value[127:0] + 702/3417: $21\inv_value[127:0] + 703/3417: $21\val_c[127:0] + 704/3417: $21\val_b[127:0] + 705/3417: $21\val_a[127:0] + 706/3417: $21\taken_proposal[7:0] + 707/3417: $21\inv_present[7:0] + 708/3417: $21\pres_c[7:0] + 709/3417: $21\pres_b[7:0] + 710/3417: $21\pres_a[7:0] + 711/3417: $21\profile[7:0] + 712/3417: $28\deferred_local[31:0] + 713/3417: $28\deferred_target[31:0] + 714/3417: $23\next_fp_value[31:0] + 715/3417: $23\next_pc_value[31:0] + 716/3417: $21\proposed_fp[31:0] + 717/3417: $21\proposed_pc[31:0] + 718/3417: $21\base_index[31:0] + 719/3417: $21\addr_c[31:0] + 720/3417: $21\addr_b[31:0] + 721/3417: $21\addr_a[31:0] + 722/3417: $21\off_c[31:0] + 723/3417: $21\off_b[31:0] + 724/3417: $21\off_a[31:0] + 725/3417: $21\fp[31:0] + 726/3417: $21\pc[31:0] + 727/3417: $21\txn_id[31:0] + 728/3417: $52\result_length[31:0] + 729/3417: $28\n_deferred[31:0] + 730/3417: $33\n_writes[31:0] + 731/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2598 [543:40] + 732/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2598 [31:0] + 733/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2598 [39:32] + 734/3417: $20\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2647 + 735/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2646 + 736/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2645 + 737/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2644 + 738/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2643 + 739/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2642 + 740/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2641 + 741/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2640 + 742/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2639 + 743/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2638 + 744/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2637 + 745/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2636 + 746/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2635 + 747/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2634 + 748/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2633 + 749/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2632 + 750/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2631 + 751/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2630 + 752/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2629 + 753/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2628 + 754/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2627 + 755/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2626 + 756/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2625 + 757/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2624 + 758/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2623 + 759/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2622 + 760/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2621 + 761/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2620 + 762/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2619 + 763/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2618 + 764/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2617 + 765/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2616 + 766/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2615 + 767/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2614 + 768/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2613 + 769/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2612 + 770/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2611 + 771/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2610 + 772/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2609 + 773/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2608 + 774/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2607 + 775/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2606 + 776/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2605 + 777/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2604 + 778/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2603 + 779/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2602 + 780/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2601 + 781/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2600 + 782/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2599 + 783/3417: $20\decision_deferred[0:0] + 784/3417: $20\decision_ok[0:0] + 785/3417: $20\decision_detail[7:0] + 786/3417: $20\decision_fault[7:0] + 787/3417: $32\write_value[127:0] + 788/3417: $32\write_address[31:0] + 789/3417: $55\result_bytes[543:0] + 790/3417: $22\solved_b[127:0] + 791/3417: $22\solved_a[127:0] + 792/3417: $20\result_value[127:0] + 793/3417: $20\inv_value[127:0] + 794/3417: $20\val_c[127:0] + 795/3417: $20\val_b[127:0] + 796/3417: $20\val_a[127:0] + 797/3417: $20\taken_proposal[7:0] + 798/3417: $20\inv_present[7:0] + 799/3417: $20\pres_c[7:0] + 800/3417: $20\pres_b[7:0] + 801/3417: $20\pres_a[7:0] + 802/3417: $20\profile[7:0] + 803/3417: $27\deferred_local[31:0] + 804/3417: $27\deferred_target[31:0] + 805/3417: $22\next_fp_value[31:0] + 806/3417: $22\next_pc_value[31:0] + 807/3417: $20\proposed_fp[31:0] + 808/3417: $20\proposed_pc[31:0] + 809/3417: $20\base_index[31:0] + 810/3417: $20\addr_c[31:0] + 811/3417: $20\addr_b[31:0] + 812/3417: $20\addr_a[31:0] + 813/3417: $20\off_c[31:0] + 814/3417: $20\off_b[31:0] + 815/3417: $20\off_a[31:0] + 816/3417: $20\fp[31:0] + 817/3417: $20\pc[31:0] + 818/3417: $20\txn_id[31:0] + 819/3417: $51\result_length[31:0] + 820/3417: $27\n_deferred[31:0] + 821/3417: $32\n_writes[31:0] + 822/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2546 [543:40] + 823/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2546 [31:0] + 824/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2546 [39:32] + 825/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2545 + 826/3417: $19\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2596 + 827/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2595 + 828/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2594 + 829/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2593 + 830/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2592 + 831/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2591 + 832/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2590 + 833/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2589 + 834/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2588 + 835/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2587 + 836/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2586 + 837/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2585 + 838/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2584 + 839/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2583 + 840/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2582 + 841/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2581 + 842/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2580 + 843/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2579 + 844/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2578 + 845/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2577 + 846/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2576 + 847/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2575 + 848/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2574 + 849/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2573 + 850/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2572 + 851/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2571 + 852/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2570 + 853/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2569 + 854/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2568 + 855/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2567 + 856/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2566 + 857/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2565 + 858/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2564 + 859/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2563 + 860/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2562 + 861/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2561 + 862/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2560 + 863/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2559 + 864/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2558 + 865/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2557 + 866/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2556 + 867/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2555 + 868/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2554 + 869/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2553 + 870/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2552 + 871/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2551 + 872/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2550 + 873/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2549 + 874/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2548 + 875/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2547 + 876/3417: $19\decision_deferred[0:0] + 877/3417: $19\decision_ok[0:0] + 878/3417: $19\decision_detail[7:0] + 879/3417: $19\decision_fault[7:0] + 880/3417: $31\write_value[127:0] + 881/3417: $31\write_address[31:0] + 882/3417: $54\result_bytes[543:0] + 883/3417: $21\solved_b[127:0] + 884/3417: $21\solved_a[127:0] + 885/3417: $19\result_value[127:0] + 886/3417: $19\inv_value[127:0] + 887/3417: $19\val_c[127:0] + 888/3417: $19\val_b[127:0] + 889/3417: $19\val_a[127:0] + 890/3417: $19\taken_proposal[7:0] + 891/3417: $19\inv_present[7:0] + 892/3417: $19\pres_c[7:0] + 893/3417: $19\pres_b[7:0] + 894/3417: $19\pres_a[7:0] + 895/3417: $19\profile[7:0] + 896/3417: $26\deferred_local[31:0] + 897/3417: $26\deferred_target[31:0] + 898/3417: $21\next_fp_value[31:0] + 899/3417: $21\next_pc_value[31:0] + 900/3417: $19\proposed_fp[31:0] + 901/3417: $19\proposed_pc[31:0] + 902/3417: $19\base_index[31:0] + 903/3417: $19\addr_c[31:0] + 904/3417: $19\addr_b[31:0] + 905/3417: $19\addr_a[31:0] + 906/3417: $19\off_c[31:0] + 907/3417: $19\off_b[31:0] + 908/3417: $19\off_a[31:0] + 909/3417: $19\fp[31:0] + 910/3417: $19\pc[31:0] + 911/3417: $19\txn_id[31:0] + 912/3417: $50\result_length[31:0] + 913/3417: $26\n_deferred[31:0] + 914/3417: $31\n_writes[31:0] + 915/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2469 [543:40] + 916/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2469 [31:0] + 917/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2469 [39:32] + 918/3417: $18\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2521 + 919/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2520 + 920/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2519 + 921/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2518 + 922/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2517 + 923/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2516 + 924/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2515 + 925/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2514 + 926/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2513 + 927/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2512 + 928/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2511 + 929/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2510 + 930/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2509 + 931/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2508 + 932/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2507 + 933/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2506 + 934/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2505 + 935/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2504 + 936/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2503 + 937/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2502 + 938/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2501 + 939/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2500 + 940/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2499 + 941/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2498 + 942/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2497 + 943/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2496 + 944/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2495 + 945/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2494 + 946/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2493 + 947/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2492 + 948/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2491 + 949/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2490 + 950/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2489 + 951/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2488 + 952/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2487 + 953/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2486 + 954/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2485 + 955/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2484 + 956/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2483 + 957/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2482 + 958/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2481 + 959/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2480 + 960/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2479 + 961/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2478 + 962/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2477 + 963/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2476 + 964/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2475 + 965/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2474 + 966/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2473 + 967/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2472 + 968/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2471 + 969/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2470 + 970/3417: $18\decision_deferred[0:0] + 971/3417: $18\decision_ok[0:0] + 972/3417: $18\decision_detail[7:0] + 973/3417: $18\decision_fault[7:0] + 974/3417: $30\write_value[127:0] + 975/3417: $30\write_address[31:0] + 976/3417: $53\result_bytes[543:0] + 977/3417: $20\solved_b[127:0] + 978/3417: $20\solved_a[127:0] + 979/3417: $18\result_value[127:0] + 980/3417: $18\inv_value[127:0] + 981/3417: $18\val_c[127:0] + 982/3417: $18\val_b[127:0] + 983/3417: $18\val_a[127:0] + 984/3417: $18\taken_proposal[7:0] + 985/3417: $18\inv_present[7:0] + 986/3417: $18\pres_c[7:0] + 987/3417: $18\pres_b[7:0] + 988/3417: $18\pres_a[7:0] + 989/3417: $18\profile[7:0] + 990/3417: $25\deferred_local[31:0] + 991/3417: $25\deferred_target[31:0] + 992/3417: $20\next_fp_value[31:0] + 993/3417: $20\next_pc_value[31:0] + 994/3417: $18\proposed_fp[31:0] + 995/3417: $18\proposed_pc[31:0] + 996/3417: $18\base_index[31:0] + 997/3417: $18\addr_c[31:0] + 998/3417: $18\addr_b[31:0] + 999/3417: $18\addr_a[31:0] + 1000/3417: $18\off_c[31:0] + 1001/3417: $18\off_b[31:0] + 1002/3417: $18\off_a[31:0] + 1003/3417: $18\fp[31:0] + 1004/3417: $18\pc[31:0] + 1005/3417: $18\txn_id[31:0] + 1006/3417: $49\result_length[31:0] + 1007/3417: $25\n_deferred[31:0] + 1008/3417: $30\n_writes[31:0] + 1009/3417: $20\retired_bytes[543:0] [127:96] + 1010/3417: $20\retired_bytes[543:0] [95:64] + 1011/3417: $20\retired_bytes[543:0] [63:32] + 1012/3417: $20\retired_bytes[543:0] [31:0] + 1013/3417: $20\retired_bytes[543:0] [543:128] + 1014/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2451 [31:0] + 1015/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2451 [39:32] + 1016/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2450 + 1017/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2449 + 1018/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2451 [543:40] + 1019/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2442 [543:40] + 1020/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2442 [31:0] + 1021/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2442 [39:32] + 1022/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2441 + 1023/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2445 + 1024/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2444 + 1025/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2443 + 1026/3417: $19\retired_bytes[543:0] + 1027/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2434 [543:40] + 1028/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2434 [31:0] + 1029/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2434 [39:32] + 1030/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2439 + 1031/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2438 + 1032/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2437 + 1033/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2436 + 1034/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2435 + 1035/3417: $18\retired_bytes[543:0] + 1036/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2379 + 1037/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2378 + 1038/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2377 + 1039/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2376 + 1040/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2375 + 1041/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2374 + 1042/3417: $17\retired_bytes[543:0] + 1043/3417: $17\txn_id[31:0] + 1044/3417: $17\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2432 + 1045/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2431 + 1046/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2430 + 1047/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2429 + 1048/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2428 + 1049/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2427 + 1050/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2426 + 1051/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2425 + 1052/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2424 + 1053/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2423 + 1054/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2422 + 1055/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2421 + 1056/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2420 + 1057/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2419 + 1058/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2418 + 1059/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2417 + 1060/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2416 + 1061/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2415 + 1062/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2414 + 1063/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2413 + 1064/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2412 + 1065/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2411 + 1066/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2410 + 1067/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2409 + 1068/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2408 + 1069/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2407 + 1070/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2406 + 1071/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2405 + 1072/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2404 + 1073/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2403 + 1074/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2402 + 1075/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2401 + 1076/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2400 + 1077/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2399 + 1078/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2398 + 1079/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2397 + 1080/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2396 + 1081/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2395 + 1082/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2394 + 1083/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2393 + 1084/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2392 + 1085/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2391 + 1086/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2390 + 1087/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2389 + 1088/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2388 + 1089/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2387 + 1090/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2386 + 1091/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2385 + 1092/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2384 + 1093/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2383 + 1094/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2382 + 1095/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2381 + 1096/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2380 + 1097/3417: $17\decision_deferred[0:0] + 1098/3417: $17\decision_ok[0:0] + 1099/3417: $17\decision_detail[7:0] + 1100/3417: $17\decision_fault[7:0] + 1101/3417: $29\write_value[127:0] + 1102/3417: $29\write_address[31:0] + 1103/3417: $52\result_bytes[543:0] + 1104/3417: $19\solved_b[127:0] + 1105/3417: $19\solved_a[127:0] + 1106/3417: $17\result_value[127:0] + 1107/3417: $17\inv_value[127:0] + 1108/3417: $17\val_c[127:0] + 1109/3417: $17\val_b[127:0] + 1110/3417: $17\val_a[127:0] + 1111/3417: $17\taken_proposal[7:0] + 1112/3417: $17\inv_present[7:0] + 1113/3417: $17\pres_c[7:0] + 1114/3417: $17\pres_b[7:0] + 1115/3417: $17\pres_a[7:0] + 1116/3417: $17\profile[7:0] + 1117/3417: $24\deferred_local[31:0] + 1118/3417: $24\deferred_target[31:0] + 1119/3417: $19\next_fp_value[31:0] + 1120/3417: $19\next_pc_value[31:0] + 1121/3417: $17\proposed_fp[31:0] + 1122/3417: $17\proposed_pc[31:0] + 1123/3417: $17\base_index[31:0] + 1124/3417: $17\addr_c[31:0] + 1125/3417: $17\addr_b[31:0] + 1126/3417: $17\addr_a[31:0] + 1127/3417: $17\off_c[31:0] + 1128/3417: $17\off_b[31:0] + 1129/3417: $17\off_a[31:0] + 1130/3417: $17\fp[31:0] + 1131/3417: $17\pc[31:0] + 1132/3417: $48\result_length[31:0] + 1133/3417: $24\n_deferred[31:0] + 1134/3417: $29\n_writes[31:0] + 1135/3417: $51\result_bytes[543:0] [111:80] + 1136/3417: $51\result_bytes[543:0] [79:48] + 1137/3417: $51\result_bytes[543:0] [47:40] + 1138/3417: $51\result_bytes[543:0] [39:32] + 1139/3417: $51\result_bytes[543:0] [31:16] + 1140/3417: $51\result_bytes[543:0] [15:8] + 1141/3417: $51\result_bytes[543:0] [7:0] + 1142/3417: $51\result_bytes[543:0] [543:112] + 1143/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2372 [31:0] + 1144/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2372 [39:32] + 1145/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2372 [543:40] + 1146/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2369 [543:40] + 1147/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2369 [31:0] + 1148/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2369 [39:32] + 1149/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2370 + 1150/3417: $50\result_bytes[543:0] + 1151/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2362 [543:40] + 1152/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2362 [31:0] + 1153/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2362 [39:32] + 1154/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2364 + 1155/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2363 + 1156/3417: $49\result_bytes[543:0] + 1157/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2358 [543:40] + 1158/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2358 [31:0] + 1159/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2358 [39:32] + 1160/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2361 + 1161/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2360 + 1162/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2359 + 1163/3417: $48\result_bytes[543:0] + 1164/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2352 [543:40] + 1165/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2352 [31:0] + 1166/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2352 [39:32] + 1167/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2356 + 1168/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2355 + 1169/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2354 + 1170/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2353 + 1171/3417: $47\result_bytes[543:0] + 1172/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2291 + 1173/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2290 + 1174/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2289 + 1175/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2288 + 1176/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2287 + 1177/3417: $46\result_bytes[543:0] + 1178/3417: $16\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2350 + 1179/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2349 + 1180/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2348 + 1181/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2347 + 1182/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2346 + 1183/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2345 + 1184/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2344 + 1185/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2343 + 1186/3417: $16\cell_is_malformed$func$asic_core \ No newline at end of file diff --git a/results/b2-capability-contract-20260728/netlist.status b/results/b2-capability-contract-20260728/netlist.status new file mode 100644 index 0000000..4b86e01 --- /dev/null +++ b/results/b2-capability-contract-20260728/netlist.status @@ -0,0 +1,2 @@ +exit_code=124 +duration_ms=180018 diff --git a/results/b2-capability-contract-20260728/netlist_900.command b/results/b2-capability-contract-20260728/netlist_900.command new file mode 100644 index 0000000..4f25ee2 --- /dev/null +++ b/results/b2-capability-contract-20260728/netlist_900.command @@ -0,0 +1 @@ +timeout 900s yosys -p read_verilog\ -sv\ asic_core/rtl/lsc1_packet_rx.sv\ asic_core/rtl/lsc1_packet_tx.sv\ asic_core/rtl/gf2n_mul_bitstream.sv\ asic_core/rtl/gf128_mul_bitstream.sv\ asic_core/rtl/leanvm_b_stream_alu.sv\ asic_core/rtl/lsc1_stream_adapter.sv\ asic_core/rtl/lsc1_field_encoder.sv\ asic_core/rtl/lsc1_packet_frontend.sv\;\ hierarchy\ -check\ -top\ lsc1_packet_frontend\;\ proc\;\ memory\;\ flatten\;\ opt\;\ check\;\ write_verilog\ -noattr\ results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v\;\ stat diff --git a/results/b2-capability-contract-20260728/netlist_900.log b/results/b2-capability-contract-20260728/netlist_900.log new file mode 100644 index 0000000..0ebdcf5 --- /dev/null +++ b/results/b2-capability-contract-20260728/netlist_900.log @@ -0,0 +1,22192 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Running command `read_verilog -sv asic_core/rtl/lsc1_packet_rx.sv asic_core/rtl/lsc1_packet_tx.sv asic_core/rtl/gf2n_mul_bitstream.sv asic_core/rtl/gf128_mul_bitstream.sv asic_core/rtl/leanvm_b_stream_alu.sv asic_core/rtl/lsc1_stream_adapter.sv asic_core/rtl/lsc1_field_encoder.sv asic_core/rtl/lsc1_packet_frontend.sv; hierarchy -check -top lsc1_packet_frontend; proc; memory; flatten; opt; check; write_verilog -noattr results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v; stat' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_rx.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_tx.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_tx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_tx'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: asic_core/rtl/gf2n_mul_bitstream.sv +Parsing SystemVerilog input from `asic_core/rtl/gf2n_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf2n_mul_bitstream'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: asic_core/rtl/gf128_mul_bitstream.sv +Parsing SystemVerilog input from `asic_core/rtl/gf128_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf128_mul_bitstream'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: asic_core/rtl/leanvm_b_stream_alu.sv +Parsing SystemVerilog input from `asic_core/rtl/leanvm_b_stream_alu.sv' to AST representation. +Generating RTLIL representation for module `\leanvm_b_stream_alu'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_stream_adapter.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_stream_adapter.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_stream_adapter'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_field_encoder.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_field_encoder.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_field_encoder'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_frontend.sv +Parsing SystemVerilog input from `asic_core/rtl/lsc1_packet_frontend.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Successfully finished Verilog frontend. + +9. Executing HIERARCHY pass (managing design hierarchy). + +9.1. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: \gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 + +9.2. Executing AST frontend in derive mode using pre-parsed AST for module `\gf2n_mul_bitstream'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 +Generating RTLIL representation for module `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream'. + +9.3. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx + +9.4. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Removing unused module `\gf2n_mul_bitstream'. +Removed 1 unused modules. + +10. Executing PROC pass (convert processes to netlists). + +10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 10 empty switches in `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. +Cleaned up 10 empty switches. + +10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 109 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855 in module lsc1_packet_frontend. +Marked 5 switch rules as full_case in process $proc$asic_core/rtl/lsc1_field_encoder.sv:38$755 in module lsc1_field_encoder. +Marked 10 switch rules as full_case in process $proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671 in module lsc1_stream_adapter. +Marked 6 switch rules as full_case in process $proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646 in module lsc1_stream_adapter. +Marked 12 switch rules as full_case in process $proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615 in module leanvm_b_stream_alu. +Marked 3 switch rules as full_case in process $proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576 in module leanvm_b_stream_alu. +Marked 5 switch rules as full_case in process $proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172 in module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:62$258 in module lsc1_packet_tx. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:44$244 in module lsc1_packet_tx. +Marked 11 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_rx.sv:62$23 in module lsc1_packet_rx. +Removed a total of 0 dead cases. + +10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 8 redundant assignments. +Promoted 206 assignments to connections. + +10.4. Executing PROC_INIT pass (extract init attributes). + +10.5. Executing PROC_ARST pass (detect async resets in processes). + +10.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + 1/3417: $68\result_bytes[215:152] [63:32] + 2/3417: $68\result_bytes[215:152] [31:0] + 3/3417: $64\result_length[31:0] + 4/3417: $67\result_bytes[279:104] [111:80] + 5/3417: $67\result_bytes[279:104] [47:40] + 6/3417: $67\result_bytes[279:104] [15:8] + 7/3417: $67\result_bytes[279:104] [143:112] + 8/3417: $63\result_length[31:0] + 9/3417: $67\result_bytes[279:104] [79:72] + 10/3417: $67\result_bytes[279:104] [71:48] + 11/3417: $67\result_bytes[279:104] [39:16] + 12/3417: $67\result_bytes[279:104] [175:144] + 13/3417: $67\result_bytes[279:104] [7:0] + 14/3417: $65\result_bytes[375:104] [175:168] + 15/3417: $66\result_bytes[375:312] [31:0] + 16/3417: $62\result_length[31:0] + 17/3417: $65\result_bytes[375:104] [207:176] + 18/3417: $61\result_length[31:0] + 19/3417: $66\result_bytes[375:312] [63:32] + 20/3417: $65\result_bytes[375:104] [167:160] + 21/3417: $65\result_bytes[375:104] [159:32] + 22/3417: $65\result_bytes[375:104] [31:0] + 23/3417: $65\result_bytes[375:104] [271:208] + 24/3417: $64\result_bytes[543:0] [375:104] + 25/3417: $64\result_bytes[543:0] [103:96] + 26/3417: $64\result_bytes[543:0] [95:64] + 27/3417: $64\result_bytes[543:0] [63:32] + 28/3417: $64\result_bytes[543:0] [31:0] + 29/3417: $64\result_bytes[543:0] [543:376] + 30/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [31:0] + 31/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [39:32] + 32/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$3159 + 33/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$3158 + 34/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$3157 + 35/3417: $29\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$3161 + 36/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [543:40] + 37/3417: $60\result_length[31:0] + 38/3417: $28\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$3155 + 39/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3154 + 40/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$3153 + 41/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$3152 + 42/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$3151 + 43/3417: $63\result_bytes[543:0] + 44/3417: $59\result_length[31:0] + 45/3417: $50\decision_deferred[0:0] + 46/3417: $49\decision_deferred[0:0] + 47/3417: $48\decision_deferred[0:0] + 48/3417: $58\decision_fault[7:0] + 49/3417: $58\decision_ok[0:0] + 50/3417: $47\decision_deferred[0:0] + 51/3417: $57\decision_fault[7:0] + 52/3417: $57\decision_ok[0:0] + 53/3417: $46\decision_deferred[0:0] + 54/3417: $45\decision_deferred[0:0] + 55/3417: $56\decision_ok[0:0] + 56/3417: $56\decision_fault[7:0] + 57/3417: $44\decision_deferred[0:0] + 58/3417: $55\decision_ok[0:0] + 59/3417: $55\decision_fault[7:0] + 60/3417: $54\decision_fault[7:0] + 61/3417: $54\decision_ok[0:0] + 62/3417: $53\decision_fault[7:0] + 63/3417: $53\decision_ok[0:0] + 64/3417: $38\addr_c[31:0] + 65/3417: $38\addr_b[31:0] + 66/3417: $42\addr_a[31:0] + 67/3417: $52\decision_fault[7:0] + 68/3417: $52\decision_ok[0:0] + 69/3417: $37\addr_c[31:0] + 70/3417: $37\addr_b[31:0] + 71/3417: $41\addr_a[31:0] + 72/3417: $43\decision_deferred[0:0] + 73/3417: $51\decision_ok[0:0] + 74/3417: $51\decision_fault[7:0] + 75/3417: $33\solved_b[127:0] + 76/3417: $33\solved_a[127:0] + 77/3417: $36\addr_c[31:0] + 78/3417: $36\addr_b[31:0] + 79/3417: $40\addr_a[31:0] + 80/3417: $31\inv_value[127:0] + 81/3417: $31\inv_present[7:0] + 82/3417: $31\val_c[127:0] + 83/3417: $31\pres_c[7:0] + 84/3417: $31\val_b[127:0] + 85/3417: $31\pres_b[7:0] + 86/3417: $31\val_a[127:0] + 87/3417: $31\pres_a[7:0] + 88/3417: $31\off_c[31:0] + 89/3417: $31\off_b[31:0] + 90/3417: $31\off_a[31:0] + 91/3417: $38\decision_detail[7:0] + 92/3417: $50\decision_fault[7:0] + 93/3417: $50\decision_ok[0:0] + 94/3417: $37\decision_detail[7:0] + 95/3417: $49\decision_fault[7:0] + 96/3417: $49\decision_ok[0:0] + 97/3417: $48\decision_fault[7:0] + 98/3417: $48\decision_ok[0:0] + 99/3417: $42\decision_deferred[0:0] + 100/3417: $47\decision_fault[7:0] + 101/3417: $47\decision_ok[0:0] + 102/3417: $41\decision_deferred[0:0] + 103/3417: $40\decision_deferred[0:0] + 104/3417: $46\decision_ok[0:0] + 105/3417: $46\decision_fault[7:0] + 106/3417: $36\decision_detail[7:0] + 107/3417: $35\decision_detail[7:0] + 108/3417: $45\decision_fault[7:0] + 109/3417: $45\decision_ok[0:0] + 110/3417: $39\decision_deferred[0:0] + 111/3417: $34\decision_detail[7:0] + 112/3417: $44\decision_fault[7:0] + 113/3417: $44\decision_ok[0:0] + 114/3417: $38\decision_deferred[0:0] + 115/3417: $43\decision_fault[7:0] + 116/3417: $43\decision_ok[0:0] + 117/3417: $37\decision_deferred[0:0] + 118/3417: $33\decision_detail[7:0] + 119/3417: $42\decision_fault[7:0] + 120/3417: $42\decision_ok[0:0] + 121/3417: $36\decision_deferred[0:0] + 122/3417: $32\decision_detail[7:0] + 123/3417: $35\addr_c[31:0] + 124/3417: $35\addr_b[31:0] + 125/3417: $39\addr_a[31:0] + 126/3417: $41\decision_fault[7:0] + 127/3417: $41\decision_ok[0:0] + 128/3417: $35\decision_deferred[0:0] + 129/3417: $31\decision_detail[7:0] + 130/3417: $34\addr_c[31:0] + 131/3417: $34\addr_b[31:0] + 132/3417: $38\addr_a[31:0] + 133/3417: $34\decision_deferred[0:0] + 134/3417: $40\decision_ok[0:0] + 135/3417: $30\decision_detail[7:0] + 136/3417: $40\decision_fault[7:0] + 137/3417: $33\addr_c[31:0] + 138/3417: $33\addr_b[31:0] + 139/3417: $37\addr_a[31:0] + 140/3417: $30\inv_value[127:0] + 141/3417: $30\inv_present[7:0] + 142/3417: $30\proposed_fp[31:0] + 143/3417: $30\proposed_pc[31:0] + 144/3417: $30\taken_proposal[7:0] + 145/3417: $30\val_c[127:0] + 146/3417: $30\pres_c[7:0] + 147/3417: $30\val_b[127:0] + 148/3417: $30\pres_b[7:0] + 149/3417: $30\val_a[127:0] + 150/3417: $30\pres_a[7:0] + 151/3417: $30\off_c[31:0] + 152/3417: $30\off_b[31:0] + 153/3417: $30\off_a[31:0] + 154/3417: $32\solved_b[127:0] + 155/3417: $32\solved_a[127:0] + 156/3417: $39\decision_fault[7:0] + 157/3417: $39\decision_ok[0:0] + 158/3417: $33\decision_deferred[0:0] + 159/3417: $38\decision_fault[7:0] + 160/3417: $38\decision_ok[0:0] + 161/3417: $32\decision_deferred[0:0] + 162/3417: $32\addr_c[31:0] + 163/3417: $32\addr_b[31:0] + 164/3417: $36\addr_a[31:0] + 165/3417: $37\decision_fault[7:0] + 166/3417: $37\decision_ok[0:0] + 167/3417: $31\decision_deferred[0:0] + 168/3417: $31\addr_c[31:0] + 169/3417: $31\addr_b[31:0] + 170/3417: $35\addr_a[31:0] + 171/3417: $36\decision_fault[7:0] + 172/3417: $36\decision_ok[0:0] + 173/3417: $30\decision_deferred[0:0] + 174/3417: $30\addr_c[31:0] + 175/3417: $30\addr_b[31:0] + 176/3417: $34\addr_a[31:0] + 177/3417: $29\decision_deferred[0:0] + 178/3417: $35\decision_ok[0:0] + 179/3417: $35\decision_fault[7:0] + 180/3417: $29\addr_c[31:0] + 181/3417: $29\addr_b[31:0] + 182/3417: $33\addr_a[31:0] + 183/3417: $29\val_c[127:0] + 184/3417: $29\pres_c[7:0] + 185/3417: $29\val_b[127:0] + 186/3417: $29\pres_b[7:0] + 187/3417: $29\base_index[31:0] + 188/3417: $29\val_a[127:0] + 189/3417: $29\pres_a[7:0] + 190/3417: $29\off_c[31:0] + 191/3417: $29\off_b[31:0] + 192/3417: $29\off_a[31:0] + 193/3417: $29\decision_detail[7:0] + 194/3417: $31\solved_b[127:0] + 195/3417: $31\solved_a[127:0] + 196/3417: $29\inv_value[127:0] + 197/3417: $29\taken_proposal[7:0] + 198/3417: $29\inv_present[7:0] + 199/3417: $29\proposed_fp[31:0] + 200/3417: $29\proposed_pc[31:0] + 201/3417: $44\n_writes[31:0] + 202/3417: $44\write_value[127:0] + 203/3417: $44\write_address[31:0] + 204/3417: $32\addr_a[31:0] + 205/3417: $34\decision_fault[7:0] + 206/3417: $34\decision_ok[0:0] + 207/3417: $43\write_value[127:0] + 208/3417: $43\write_address[31:0] + 209/3417: $31\addr_a[31:0] + 210/3417: $43\n_writes[31:0] + 211/3417: $33\decision_fault[7:0] + 212/3417: $33\decision_ok[0:0] + 213/3417: $42\write_value[127:0] + 214/3417: $42\write_address[31:0] + 215/3417: $30\addr_a[31:0] + 216/3417: $42\n_writes[31:0] + 217/3417: $32\decision_fault[7:0] + 218/3417: $32\decision_ok[0:0] + 219/3417: $41\write_value[127:0] + 220/3417: $41\write_address[31:0] + 221/3417: $29\addr_a[31:0] + 222/3417: $41\n_writes[31:0] + 223/3417: $28\addr_c[31:0] + 224/3417: $28\addr_b[31:0] + 225/3417: $28\addr_a[31:0] + 226/3417: $31\decision_ok[0:0] + 227/3417: $31\decision_fault[7:0] + 228/3417: $40\write_value[127:0] + 229/3417: $40\write_address[31:0] + 230/3417: $40\n_writes[31:0] + 231/3417: $28\val_a[127:0] + 232/3417: $28\pres_a[7:0] + 233/3417: $28\result_value[127:0] + 234/3417: $28\off_a[31:0] + 235/3417: $28\decision_deferred[0:0] + 236/3417: $28\decision_detail[7:0] + 237/3417: $30\solved_b[127:0] + 238/3417: $30\solved_a[127:0] + 239/3417: $28\inv_value[127:0] + 240/3417: $28\val_c[127:0] + 241/3417: $28\val_b[127:0] + 242/3417: $28\taken_proposal[7:0] + 243/3417: $28\inv_present[7:0] + 244/3417: $28\pres_c[7:0] + 245/3417: $28\pres_b[7:0] + 246/3417: $28\proposed_fp[31:0] + 247/3417: $28\proposed_pc[31:0] + 248/3417: $28\base_index[31:0] + 249/3417: $28\off_c[31:0] + 250/3417: $28\off_b[31:0] + 251/3417: $30\decision_fault[7:0] + 252/3417: $30\decision_ok[0:0] + 253/3417: $29\decision_fault[7:0] + 254/3417: $29\decision_ok[0:0] + 255/3417: $28\decision_fault[7:0] + 256/3417: $28\decision_ok[0:0] + 257/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [543:40] + 258/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [31:0] + 259/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [39:32] + 260/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2916 + 261/3417: $27\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2922 + 262/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2921 + 263/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2920 + 264/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2919 + 265/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2918 + 266/3417: $27\decision_deferred[0:0] + 267/3417: $27\decision_ok[0:0] + 268/3417: $27\decision_detail[7:0] + 269/3417: $27\decision_fault[7:0] + 270/3417: $39\write_value[127:0] + 271/3417: $39\write_address[31:0] + 272/3417: $62\result_bytes[543:0] + 273/3417: $29\solved_b[127:0] + 274/3417: $29\solved_a[127:0] + 275/3417: $27\result_value[127:0] + 276/3417: $27\inv_value[127:0] + 277/3417: $27\val_c[127:0] + 278/3417: $27\val_b[127:0] + 279/3417: $27\val_a[127:0] + 280/3417: $27\taken_proposal[7:0] + 281/3417: $27\inv_present[7:0] + 282/3417: $27\pres_c[7:0] + 283/3417: $27\pres_b[7:0] + 284/3417: $27\pres_a[7:0] + 285/3417: $27\profile[7:0] + 286/3417: $34\deferred_local[31:0] + 287/3417: $34\deferred_target[31:0] + 288/3417: $29\next_fp_value[31:0] + 289/3417: $29\next_pc_value[31:0] + 290/3417: $27\proposed_fp[31:0] + 291/3417: $27\proposed_pc[31:0] + 292/3417: $27\base_index[31:0] + 293/3417: $27\addr_c[31:0] + 294/3417: $27\addr_b[31:0] + 295/3417: $27\addr_a[31:0] + 296/3417: $27\off_c[31:0] + 297/3417: $27\off_b[31:0] + 298/3417: $27\off_a[31:0] + 299/3417: $27\fp[31:0] + 300/3417: $27\pc[31:0] + 301/3417: $27\txn_id[31:0] + 302/3417: $58\result_length[31:0] + 303/3417: $34\n_deferred[31:0] + 304/3417: $39\n_writes[31:0] + 305/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [543:40] + 306/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [31:0] + 307/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [39:32] + 308/3417: $26\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2915 + 309/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2914 + 310/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2913 + 311/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2912 + 312/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2911 + 313/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2910 + 314/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2909 + 315/3417: $26\decision_deferred[0:0] + 316/3417: $26\decision_ok[0:0] + 317/3417: $26\decision_detail[7:0] + 318/3417: $26\decision_fault[7:0] + 319/3417: $38\write_value[127:0] + 320/3417: $38\write_address[31:0] + 321/3417: $61\result_bytes[543:0] + 322/3417: $28\solved_b[127:0] + 323/3417: $28\solved_a[127:0] + 324/3417: $26\result_value[127:0] + 325/3417: $26\inv_value[127:0] + 326/3417: $26\val_c[127:0] + 327/3417: $26\val_b[127:0] + 328/3417: $26\val_a[127:0] + 329/3417: $26\taken_proposal[7:0] + 330/3417: $26\inv_present[7:0] + 331/3417: $26\pres_c[7:0] + 332/3417: $26\pres_b[7:0] + 333/3417: $26\pres_a[7:0] + 334/3417: $26\profile[7:0] + 335/3417: $33\deferred_local[31:0] + 336/3417: $33\deferred_target[31:0] + 337/3417: $28\next_fp_value[31:0] + 338/3417: $28\next_pc_value[31:0] + 339/3417: $26\proposed_fp[31:0] + 340/3417: $26\proposed_pc[31:0] + 341/3417: $26\base_index[31:0] + 342/3417: $26\addr_c[31:0] + 343/3417: $26\addr_b[31:0] + 344/3417: $26\addr_a[31:0] + 345/3417: $26\off_c[31:0] + 346/3417: $26\off_b[31:0] + 347/3417: $26\off_a[31:0] + 348/3417: $26\fp[31:0] + 349/3417: $26\pc[31:0] + 350/3417: $26\txn_id[31:0] + 351/3417: $57\result_length[31:0] + 352/3417: $33\n_deferred[31:0] + 353/3417: $38\n_writes[31:0] + 354/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [543:40] + 355/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [31:0] + 356/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [39:32] + 357/3417: $25\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2878 + 358/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2877 + 359/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2876 + 360/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2875 + 361/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2874 + 362/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2873 + 363/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2872 + 364/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2871 + 365/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2870 + 366/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2869 + 367/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2868 + 368/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2867 + 369/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2866 + 370/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2865 + 371/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2864 + 372/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2863 + 373/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2862 + 374/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2861 + 375/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2860 + 376/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2859 + 377/3417: $25\decision_deferred[0:0] + 378/3417: $25\decision_ok[0:0] + 379/3417: $25\decision_detail[7:0] + 380/3417: $25\decision_fault[7:0] + 381/3417: $37\write_value[127:0] + 382/3417: $37\write_address[31:0] + 383/3417: $60\result_bytes[543:0] + 384/3417: $27\solved_b[127:0] + 385/3417: $27\solved_a[127:0] + 386/3417: $25\result_value[127:0] + 387/3417: $25\inv_value[127:0] + 388/3417: $25\val_c[127:0] + 389/3417: $25\val_b[127:0] + 390/3417: $25\val_a[127:0] + 391/3417: $25\taken_proposal[7:0] + 392/3417: $25\inv_present[7:0] + 393/3417: $25\pres_c[7:0] + 394/3417: $25\pres_b[7:0] + 395/3417: $25\pres_a[7:0] + 396/3417: $25\profile[7:0] + 397/3417: $32\deferred_local[31:0] + 398/3417: $32\deferred_target[31:0] + 399/3417: $27\next_fp_value[31:0] + 400/3417: $27\next_pc_value[31:0] + 401/3417: $25\proposed_fp[31:0] + 402/3417: $25\proposed_pc[31:0] + 403/3417: $25\base_index[31:0] + 404/3417: $25\addr_c[31:0] + 405/3417: $25\addr_b[31:0] + 406/3417: $25\addr_a[31:0] + 407/3417: $25\off_c[31:0] + 408/3417: $25\off_b[31:0] + 409/3417: $25\off_a[31:0] + 410/3417: $25\fp[31:0] + 411/3417: $25\pc[31:0] + 412/3417: $25\txn_id[31:0] + 413/3417: $56\result_length[31:0] + 414/3417: $32\n_deferred[31:0] + 415/3417: $37\n_writes[31:0] + 416/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [543:40] + 417/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [31:0] + 418/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [39:32] + 419/3417: $24\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2854 + 420/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2853 + 421/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2852 + 422/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2851 + 423/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2850 + 424/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2849 + 425/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2848 + 426/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2847 + 427/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2846 + 428/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2845 + 429/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2844 + 430/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2843 + 431/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2842 + 432/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2841 + 433/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2840 + 434/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2839 + 435/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2838 + 436/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2837 + 437/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2836 + 438/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2835 + 439/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2834 + 440/3417: $24\decision_deferred[0:0] + 441/3417: $24\decision_ok[0:0] + 442/3417: $24\decision_detail[7:0] + 443/3417: $24\decision_fault[7:0] + 444/3417: $36\write_value[127:0] + 445/3417: $36\write_address[31:0] + 446/3417: $59\result_bytes[543:0] + 447/3417: $26\solved_b[127:0] + 448/3417: $26\solved_a[127:0] + 449/3417: $24\result_value[127:0] + 450/3417: $24\inv_value[127:0] + 451/3417: $24\val_c[127:0] + 452/3417: $24\val_b[127:0] + 453/3417: $24\val_a[127:0] + 454/3417: $24\taken_proposal[7:0] + 455/3417: $24\inv_present[7:0] + 456/3417: $24\pres_c[7:0] + 457/3417: $24\pres_b[7:0] + 458/3417: $24\pres_a[7:0] + 459/3417: $24\profile[7:0] + 460/3417: $31\deferred_local[31:0] + 461/3417: $31\deferred_target[31:0] + 462/3417: $26\next_fp_value[31:0] + 463/3417: $26\next_pc_value[31:0] + 464/3417: $24\proposed_fp[31:0] + 465/3417: $24\proposed_pc[31:0] + 466/3417: $24\base_index[31:0] + 467/3417: $24\addr_c[31:0] + 468/3417: $24\addr_b[31:0] + 469/3417: $24\addr_a[31:0] + 470/3417: $24\off_c[31:0] + 471/3417: $24\off_b[31:0] + 472/3417: $24\off_a[31:0] + 473/3417: $24\fp[31:0] + 474/3417: $24\pc[31:0] + 475/3417: $24\txn_id[31:0] + 476/3417: $55\result_length[31:0] + 477/3417: $31\n_deferred[31:0] + 478/3417: $36\n_writes[31:0] + 479/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [543:40] + 480/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [31:0] + 481/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [39:32] + 482/3417: $23\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2807 + 483/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2806 + 484/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2805 + 485/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2804 + 486/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2803 + 487/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2802 + 488/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2801 + 489/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2800 + 490/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2799 + 491/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2798 + 492/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2797 + 493/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2796 + 494/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2795 + 495/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2794 + 496/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2793 + 497/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2792 + 498/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2791 + 499/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2790 + 500/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2789 + 501/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2788 + 502/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2787 + 503/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2786 + 504/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2785 + 505/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2784 + 506/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2783 + 507/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2782 + 508/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2781 + 509/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2780 + 510/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2779 + 511/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2778 + 512/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2777 + 513/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2776 + 514/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2775 + 515/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2774 + 516/3417: $23\decision_deferred[0:0] + 517/3417: $23\decision_ok[0:0] + 518/3417: $23\decision_detail[7:0] + 519/3417: $23\decision_fault[7:0] + 520/3417: $35\write_value[127:0] + 521/3417: $35\write_address[31:0] + 522/3417: $58\result_bytes[543:0] + 523/3417: $25\solved_b[127:0] + 524/3417: $25\solved_a[127:0] + 525/3417: $23\result_value[127:0] + 526/3417: $23\inv_value[127:0] + 527/3417: $23\val_c[127:0] + 528/3417: $23\val_b[127:0] + 529/3417: $23\val_a[127:0] + 530/3417: $23\taken_proposal[7:0] + 531/3417: $23\inv_present[7:0] + 532/3417: $23\pres_c[7:0] + 533/3417: $23\pres_b[7:0] + 534/3417: $23\pres_a[7:0] + 535/3417: $23\profile[7:0] + 536/3417: $30\deferred_local[31:0] + 537/3417: $30\deferred_target[31:0] + 538/3417: $25\next_fp_value[31:0] + 539/3417: $25\next_pc_value[31:0] + 540/3417: $23\proposed_fp[31:0] + 541/3417: $23\proposed_pc[31:0] + 542/3417: $23\base_index[31:0] + 543/3417: $23\addr_c[31:0] + 544/3417: $23\addr_b[31:0] + 545/3417: $23\addr_a[31:0] + 546/3417: $23\off_c[31:0] + 547/3417: $23\off_b[31:0] + 548/3417: $23\off_a[31:0] + 549/3417: $23\fp[31:0] + 550/3417: $23\pc[31:0] + 551/3417: $23\txn_id[31:0] + 552/3417: $54\result_length[31:0] + 553/3417: $30\n_deferred[31:0] + 554/3417: $35\n_writes[31:0] + 555/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [543:40] + 556/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [31:0] + 557/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [39:32] + 558/3417: $22\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2749 + 559/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2748 + 560/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2747 + 561/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2746 + 562/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2745 + 563/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2744 + 564/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2743 + 565/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2742 + 566/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2741 + 567/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2740 + 568/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2739 + 569/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2738 + 570/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2737 + 571/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2736 + 572/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2735 + 573/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2734 + 574/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2733 + 575/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2732 + 576/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2731 + 577/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2730 + 578/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2729 + 579/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2728 + 580/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2727 + 581/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2726 + 582/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2725 + 583/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2724 + 584/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2723 + 585/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2722 + 586/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2721 + 587/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2720 + 588/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2719 + 589/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2718 + 590/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2717 + 591/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2716 + 592/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2715 + 593/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2714 + 594/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2713 + 595/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2712 + 596/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2711 + 597/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2710 + 598/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2709 + 599/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2708 + 600/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2707 + 601/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2706 + 602/3417: $22\decision_deferred[0:0] + 603/3417: $22\decision_ok[0:0] + 604/3417: $22\decision_detail[7:0] + 605/3417: $22\decision_fault[7:0] + 606/3417: $34\write_value[127:0] + 607/3417: $34\write_address[31:0] + 608/3417: $57\result_bytes[543:0] + 609/3417: $24\solved_b[127:0] + 610/3417: $24\solved_a[127:0] + 611/3417: $22\result_value[127:0] + 612/3417: $22\inv_value[127:0] + 613/3417: $22\val_c[127:0] + 614/3417: $22\val_b[127:0] + 615/3417: $22\val_a[127:0] + 616/3417: $22\taken_proposal[7:0] + 617/3417: $22\inv_present[7:0] + 618/3417: $22\pres_c[7:0] + 619/3417: $22\pres_b[7:0] + 620/3417: $22\pres_a[7:0] + 621/3417: $22\profile[7:0] + 622/3417: $29\deferred_local[31:0] + 623/3417: $29\deferred_target[31:0] + 624/3417: $24\next_fp_value[31:0] + 625/3417: $24\next_pc_value[31:0] + 626/3417: $22\proposed_fp[31:0] + 627/3417: $22\proposed_pc[31:0] + 628/3417: $22\base_index[31:0] + 629/3417: $22\addr_c[31:0] + 630/3417: $22\addr_b[31:0] + 631/3417: $22\addr_a[31:0] + 632/3417: $22\off_c[31:0] + 633/3417: $22\off_b[31:0] + 634/3417: $22\off_a[31:0] + 635/3417: $22\fp[31:0] + 636/3417: $22\pc[31:0] + 637/3417: $22\txn_id[31:0] + 638/3417: $53\result_length[31:0] + 639/3417: $29\n_deferred[31:0] + 640/3417: $34\n_writes[31:0] + 641/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [543:40] + 642/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [31:0] + 643/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [39:32] + 644/3417: $21\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2697 + 645/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2696 + 646/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2695 + 647/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2694 + 648/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2693 + 649/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2692 + 650/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2691 + 651/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2690 + 652/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2689 + 653/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2688 + 654/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2687 + 655/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2686 + 656/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2685 + 657/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2684 + 658/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2683 + 659/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2682 + 660/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2681 + 661/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2680 + 662/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2679 + 663/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2678 + 664/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2677 + 665/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2676 + 666/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2675 + 667/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2674 + 668/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2673 + 669/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2672 + 670/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2671 + 671/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2670 + 672/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2669 + 673/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2668 + 674/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2667 + 675/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2666 + 676/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2665 + 677/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2664 + 678/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2663 + 679/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2662 + 680/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2661 + 681/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2660 + 682/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2659 + 683/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2658 + 684/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2657 + 685/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2656 + 686/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2655 + 687/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2654 + 688/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2653 + 689/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2652 + 690/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2651 + 691/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2650 + 692/3417: $21\decision_deferred[0:0] + 693/3417: $21\decision_ok[0:0] + 694/3417: $21\decision_detail[7:0] + 695/3417: $21\decision_fault[7:0] + 696/3417: $33\write_value[127:0] + 697/3417: $33\write_address[31:0] + 698/3417: $56\result_bytes[543:0] + 699/3417: $23\solved_b[127:0] + 700/3417: $23\solved_a[127:0] + 701/3417: $21\result_value[127:0] + 702/3417: $21\inv_value[127:0] + 703/3417: $21\val_c[127:0] + 704/3417: $21\val_b[127:0] + 705/3417: $21\val_a[127:0] + 706/3417: $21\taken_proposal[7:0] + 707/3417: $21\inv_present[7:0] + 708/3417: $21\pres_c[7:0] + 709/3417: $21\pres_b[7:0] + 710/3417: $21\pres_a[7:0] + 711/3417: $21\profile[7:0] + 712/3417: $28\deferred_local[31:0] + 713/3417: $28\deferred_target[31:0] + 714/3417: $23\next_fp_value[31:0] + 715/3417: $23\next_pc_value[31:0] + 716/3417: $21\proposed_fp[31:0] + 717/3417: $21\proposed_pc[31:0] + 718/3417: $21\base_index[31:0] + 719/3417: $21\addr_c[31:0] + 720/3417: $21\addr_b[31:0] + 721/3417: $21\addr_a[31:0] + 722/3417: $21\off_c[31:0] + 723/3417: $21\off_b[31:0] + 724/3417: $21\off_a[31:0] + 725/3417: $21\fp[31:0] + 726/3417: $21\pc[31:0] + 727/3417: $21\txn_id[31:0] + 728/3417: $52\result_length[31:0] + 729/3417: $28\n_deferred[31:0] + 730/3417: $33\n_writes[31:0] + 731/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2598 [543:40] + 732/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2598 [31:0] + 733/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2598 [39:32] + 734/3417: $20\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2647 + 735/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2646 + 736/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2645 + 737/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2644 + 738/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2643 + 739/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2642 + 740/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2641 + 741/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2640 + 742/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2639 + 743/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2638 + 744/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2637 + 745/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2636 + 746/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2635 + 747/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2634 + 748/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2633 + 749/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2632 + 750/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2631 + 751/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2630 + 752/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2629 + 753/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2628 + 754/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2627 + 755/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2626 + 756/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2625 + 757/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2624 + 758/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2623 + 759/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2622 + 760/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2621 + 761/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2620 + 762/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2619 + 763/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2618 + 764/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2617 + 765/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2616 + 766/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2615 + 767/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2614 + 768/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2613 + 769/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2612 + 770/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2611 + 771/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2610 + 772/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2609 + 773/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2608 + 774/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2607 + 775/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2606 + 776/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2605 + 777/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2604 + 778/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2603 + 779/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2602 + 780/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2601 + 781/3417: $20\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2600 + 782/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2599 + 783/3417: $20\decision_deferred[0:0] + 784/3417: $20\decision_ok[0:0] + 785/3417: $20\decision_detail[7:0] + 786/3417: $20\decision_fault[7:0] + 787/3417: $32\write_value[127:0] + 788/3417: $32\write_address[31:0] + 789/3417: $55\result_bytes[543:0] + 790/3417: $22\solved_b[127:0] + 791/3417: $22\solved_a[127:0] + 792/3417: $20\result_value[127:0] + 793/3417: $20\inv_value[127:0] + 794/3417: $20\val_c[127:0] + 795/3417: $20\val_b[127:0] + 796/3417: $20\val_a[127:0] + 797/3417: $20\taken_proposal[7:0] + 798/3417: $20\inv_present[7:0] + 799/3417: $20\pres_c[7:0] + 800/3417: $20\pres_b[7:0] + 801/3417: $20\pres_a[7:0] + 802/3417: $20\profile[7:0] + 803/3417: $27\deferred_local[31:0] + 804/3417: $27\deferred_target[31:0] + 805/3417: $22\next_fp_value[31:0] + 806/3417: $22\next_pc_value[31:0] + 807/3417: $20\proposed_fp[31:0] + 808/3417: $20\proposed_pc[31:0] + 809/3417: $20\base_index[31:0] + 810/3417: $20\addr_c[31:0] + 811/3417: $20\addr_b[31:0] + 812/3417: $20\addr_a[31:0] + 813/3417: $20\off_c[31:0] + 814/3417: $20\off_b[31:0] + 815/3417: $20\off_a[31:0] + 816/3417: $20\fp[31:0] + 817/3417: $20\pc[31:0] + 818/3417: $20\txn_id[31:0] + 819/3417: $51\result_length[31:0] + 820/3417: $27\n_deferred[31:0] + 821/3417: $32\n_writes[31:0] + 822/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2546 [543:40] + 823/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2546 [31:0] + 824/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2546 [39:32] + 825/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2545 + 826/3417: $19\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2596 + 827/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2595 + 828/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2594 + 829/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2593 + 830/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2592 + 831/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2591 + 832/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2590 + 833/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2589 + 834/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2588 + 835/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2587 + 836/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2586 + 837/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2585 + 838/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2584 + 839/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2583 + 840/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2582 + 841/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2581 + 842/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2580 + 843/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2579 + 844/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2578 + 845/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2577 + 846/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2576 + 847/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2575 + 848/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2574 + 849/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2573 + 850/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2572 + 851/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2571 + 852/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2570 + 853/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2569 + 854/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2568 + 855/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2567 + 856/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2566 + 857/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2565 + 858/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2564 + 859/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2563 + 860/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2562 + 861/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2561 + 862/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2560 + 863/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2559 + 864/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2558 + 865/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2557 + 866/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2556 + 867/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2555 + 868/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2554 + 869/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2553 + 870/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2552 + 871/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2551 + 872/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2550 + 873/3417: $19\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2549 + 874/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2548 + 875/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2547 + 876/3417: $19\decision_deferred[0:0] + 877/3417: $19\decision_ok[0:0] + 878/3417: $19\decision_detail[7:0] + 879/3417: $19\decision_fault[7:0] + 880/3417: $31\write_value[127:0] + 881/3417: $31\write_address[31:0] + 882/3417: $54\result_bytes[543:0] + 883/3417: $21\solved_b[127:0] + 884/3417: $21\solved_a[127:0] + 885/3417: $19\result_value[127:0] + 886/3417: $19\inv_value[127:0] + 887/3417: $19\val_c[127:0] + 888/3417: $19\val_b[127:0] + 889/3417: $19\val_a[127:0] + 890/3417: $19\taken_proposal[7:0] + 891/3417: $19\inv_present[7:0] + 892/3417: $19\pres_c[7:0] + 893/3417: $19\pres_b[7:0] + 894/3417: $19\pres_a[7:0] + 895/3417: $19\profile[7:0] + 896/3417: $26\deferred_local[31:0] + 897/3417: $26\deferred_target[31:0] + 898/3417: $21\next_fp_value[31:0] + 899/3417: $21\next_pc_value[31:0] + 900/3417: $19\proposed_fp[31:0] + 901/3417: $19\proposed_pc[31:0] + 902/3417: $19\base_index[31:0] + 903/3417: $19\addr_c[31:0] + 904/3417: $19\addr_b[31:0] + 905/3417: $19\addr_a[31:0] + 906/3417: $19\off_c[31:0] + 907/3417: $19\off_b[31:0] + 908/3417: $19\off_a[31:0] + 909/3417: $19\fp[31:0] + 910/3417: $19\pc[31:0] + 911/3417: $19\txn_id[31:0] + 912/3417: $50\result_length[31:0] + 913/3417: $26\n_deferred[31:0] + 914/3417: $31\n_writes[31:0] + 915/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2469 [543:40] + 916/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2469 [31:0] + 917/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2469 [39:32] + 918/3417: $18\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2521 + 919/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2520 + 920/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2519 + 921/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2518 + 922/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2517 + 923/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2516 + 924/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2515 + 925/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2514 + 926/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2513 + 927/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2512 + 928/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2511 + 929/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2510 + 930/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2509 + 931/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2508 + 932/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2507 + 933/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2506 + 934/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2505 + 935/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2504 + 936/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2503 + 937/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2502 + 938/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2501 + 939/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2500 + 940/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2499 + 941/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2498 + 942/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2497 + 943/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2496 + 944/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2495 + 945/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2494 + 946/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2493 + 947/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2492 + 948/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2491 + 949/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2490 + 950/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2489 + 951/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2488 + 952/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2487 + 953/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2486 + 954/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2485 + 955/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2484 + 956/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2483 + 957/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2482 + 958/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2481 + 959/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2480 + 960/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2479 + 961/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2478 + 962/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2477 + 963/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2476 + 964/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2475 + 965/3417: $18\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2474 + 966/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2473 + 967/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2472 + 968/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2471 + 969/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2470 + 970/3417: $18\decision_deferred[0:0] + 971/3417: $18\decision_ok[0:0] + 972/3417: $18\decision_detail[7:0] + 973/3417: $18\decision_fault[7:0] + 974/3417: $30\write_value[127:0] + 975/3417: $30\write_address[31:0] + 976/3417: $53\result_bytes[543:0] + 977/3417: $20\solved_b[127:0] + 978/3417: $20\solved_a[127:0] + 979/3417: $18\result_value[127:0] + 980/3417: $18\inv_value[127:0] + 981/3417: $18\val_c[127:0] + 982/3417: $18\val_b[127:0] + 983/3417: $18\val_a[127:0] + 984/3417: $18\taken_proposal[7:0] + 985/3417: $18\inv_present[7:0] + 986/3417: $18\pres_c[7:0] + 987/3417: $18\pres_b[7:0] + 988/3417: $18\pres_a[7:0] + 989/3417: $18\profile[7:0] + 990/3417: $25\deferred_local[31:0] + 991/3417: $25\deferred_target[31:0] + 992/3417: $20\next_fp_value[31:0] + 993/3417: $20\next_pc_value[31:0] + 994/3417: $18\proposed_fp[31:0] + 995/3417: $18\proposed_pc[31:0] + 996/3417: $18\base_index[31:0] + 997/3417: $18\addr_c[31:0] + 998/3417: $18\addr_b[31:0] + 999/3417: $18\addr_a[31:0] + 1000/3417: $18\off_c[31:0] + 1001/3417: $18\off_b[31:0] + 1002/3417: $18\off_a[31:0] + 1003/3417: $18\fp[31:0] + 1004/3417: $18\pc[31:0] + 1005/3417: $18\txn_id[31:0] + 1006/3417: $49\result_length[31:0] + 1007/3417: $25\n_deferred[31:0] + 1008/3417: $30\n_writes[31:0] + 1009/3417: $20\retired_bytes[543:0] [127:96] + 1010/3417: $20\retired_bytes[543:0] [95:64] + 1011/3417: $20\retired_bytes[543:0] [63:32] + 1012/3417: $20\retired_bytes[543:0] [31:0] + 1013/3417: $20\retired_bytes[543:0] [543:128] + 1014/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2451 [31:0] + 1015/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2451 [39:32] + 1016/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2450 + 1017/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2449 + 1018/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2451 [543:40] + 1019/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2442 [543:40] + 1020/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2442 [31:0] + 1021/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2442 [39:32] + 1022/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2441 + 1023/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2445 + 1024/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2444 + 1025/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2443 + 1026/3417: $19\retired_bytes[543:0] + 1027/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2434 [543:40] + 1028/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2434 [31:0] + 1029/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2434 [39:32] + 1030/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2439 + 1031/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2438 + 1032/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2437 + 1033/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2436 + 1034/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2435 + 1035/3417: $18\retired_bytes[543:0] + 1036/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2379 + 1037/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2378 + 1038/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2377 + 1039/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2376 + 1040/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2375 + 1041/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2374 + 1042/3417: $17\retired_bytes[543:0] + 1043/3417: $17\txn_id[31:0] + 1044/3417: $17\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2432 + 1045/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2431 + 1046/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2430 + 1047/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2429 + 1048/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2428 + 1049/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2427 + 1050/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2426 + 1051/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2425 + 1052/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2424 + 1053/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2423 + 1054/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2422 + 1055/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2421 + 1056/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2420 + 1057/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2419 + 1058/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2418 + 1059/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2417 + 1060/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2416 + 1061/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2415 + 1062/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2414 + 1063/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2413 + 1064/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2412 + 1065/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2411 + 1066/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2410 + 1067/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2409 + 1068/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2408 + 1069/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2407 + 1070/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2406 + 1071/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2405 + 1072/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2404 + 1073/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2403 + 1074/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2402 + 1075/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2401 + 1076/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2400 + 1077/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2399 + 1078/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2398 + 1079/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2397 + 1080/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2396 + 1081/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2395 + 1082/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2394 + 1083/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2393 + 1084/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2392 + 1085/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2391 + 1086/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2390 + 1087/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2389 + 1088/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2388 + 1089/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2387 + 1090/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2386 + 1091/3417: $17\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2385 + 1092/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2384 + 1093/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2383 + 1094/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2382 + 1095/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2381 + 1096/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2380 + 1097/3417: $17\decision_deferred[0:0] + 1098/3417: $17\decision_ok[0:0] + 1099/3417: $17\decision_detail[7:0] + 1100/3417: $17\decision_fault[7:0] + 1101/3417: $29\write_value[127:0] + 1102/3417: $29\write_address[31:0] + 1103/3417: $52\result_bytes[543:0] + 1104/3417: $19\solved_b[127:0] + 1105/3417: $19\solved_a[127:0] + 1106/3417: $17\result_value[127:0] + 1107/3417: $17\inv_value[127:0] + 1108/3417: $17\val_c[127:0] + 1109/3417: $17\val_b[127:0] + 1110/3417: $17\val_a[127:0] + 1111/3417: $17\taken_proposal[7:0] + 1112/3417: $17\inv_present[7:0] + 1113/3417: $17\pres_c[7:0] + 1114/3417: $17\pres_b[7:0] + 1115/3417: $17\pres_a[7:0] + 1116/3417: $17\profile[7:0] + 1117/3417: $24\deferred_local[31:0] + 1118/3417: $24\deferred_target[31:0] + 1119/3417: $19\next_fp_value[31:0] + 1120/3417: $19\next_pc_value[31:0] + 1121/3417: $17\proposed_fp[31:0] + 1122/3417: $17\proposed_pc[31:0] + 1123/3417: $17\base_index[31:0] + 1124/3417: $17\addr_c[31:0] + 1125/3417: $17\addr_b[31:0] + 1126/3417: $17\addr_a[31:0] + 1127/3417: $17\off_c[31:0] + 1128/3417: $17\off_b[31:0] + 1129/3417: $17\off_a[31:0] + 1130/3417: $17\fp[31:0] + 1131/3417: $17\pc[31:0] + 1132/3417: $48\result_length[31:0] + 1133/3417: $24\n_deferred[31:0] + 1134/3417: $29\n_writes[31:0] + 1135/3417: $51\result_bytes[543:0] [111:80] + 1136/3417: $51\result_bytes[543:0] [79:48] + 1137/3417: $51\result_bytes[543:0] [47:40] + 1138/3417: $51\result_bytes[543:0] [39:32] + 1139/3417: $51\result_bytes[543:0] [31:16] + 1140/3417: $51\result_bytes[543:0] [15:8] + 1141/3417: $51\result_bytes[543:0] [7:0] + 1142/3417: $51\result_bytes[543:0] [543:112] + 1143/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2372 [31:0] + 1144/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2372 [39:32] + 1145/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2372 [543:40] + 1146/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2369 [543:40] + 1147/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2369 [31:0] + 1148/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2369 [39:32] + 1149/3417: $20\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2370 + 1150/3417: $50\result_bytes[543:0] + 1151/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2362 [543:40] + 1152/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2362 [31:0] + 1153/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2362 [39:32] + 1154/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2364 + 1155/3417: $19\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2363 + 1156/3417: $49\result_bytes[543:0] + 1157/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2358 [543:40] + 1158/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2358 [31:0] + 1159/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2358 [39:32] + 1160/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2361 + 1161/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2360 + 1162/3417: $18\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2359 + 1163/3417: $48\result_bytes[543:0] + 1164/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2352 [543:40] + 1165/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2352 [31:0] + 1166/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2352 [39:32] + 1167/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2356 + 1168/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2355 + 1169/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2354 + 1170/3417: $17\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2353 + 1171/3417: $47\result_bytes[543:0] + 1172/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2291 + 1173/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2290 + 1174/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2289 + 1175/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2288 + 1176/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2287 + 1177/3417: $46\result_bytes[543:0] + 1178/3417: $16\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2350 + 1179/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2349 + 1180/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2348 + 1181/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2347 + 1182/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2346 + 1183/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2345 + 1184/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2344 + 1185/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2343 + 1186/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2342 + 1187/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2341 + 1188/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2340 + 1189/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2339 + 1190/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2338 + 1191/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2337 + 1192/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2336 + 1193/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2335 + 1194/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2334 + 1195/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2333 + 1196/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2332 + 1197/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2331 + 1198/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2330 + 1199/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2329 + 1200/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2328 + 1201/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2327 + 1202/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2326 + 1203/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2325 + 1204/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2324 + 1205/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2323 + 1206/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2322 + 1207/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2321 + 1208/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2320 + 1209/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2319 + 1210/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2318 + 1211/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2317 + 1212/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2316 + 1213/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2315 + 1214/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2314 + 1215/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2313 + 1216/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2312 + 1217/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2311 + 1218/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2310 + 1219/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2309 + 1220/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2308 + 1221/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2307 + 1222/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2306 + 1223/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2305 + 1224/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2304 + 1225/3417: $16\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2303 + 1226/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2302 + 1227/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2301 + 1228/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2300 + 1229/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2299 + 1230/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2298 + 1231/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2297 + 1232/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2296 + 1233/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2295 + 1234/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2294 + 1235/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2293 + 1236/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2292 + 1237/3417: $16\decision_deferred[0:0] + 1238/3417: $16\decision_ok[0:0] + 1239/3417: $16\decision_detail[7:0] + 1240/3417: $16\decision_fault[7:0] + 1241/3417: $28\write_value[127:0] + 1242/3417: $28\write_address[31:0] + 1243/3417: $16\retired_bytes[543:0] + 1244/3417: $18\solved_b[127:0] + 1245/3417: $18\solved_a[127:0] + 1246/3417: $16\result_value[127:0] + 1247/3417: $16\inv_value[127:0] + 1248/3417: $16\val_c[127:0] + 1249/3417: $16\val_b[127:0] + 1250/3417: $16\val_a[127:0] + 1251/3417: $16\taken_proposal[7:0] + 1252/3417: $16\inv_present[7:0] + 1253/3417: $16\pres_c[7:0] + 1254/3417: $16\pres_b[7:0] + 1255/3417: $16\pres_a[7:0] + 1256/3417: $16\profile[7:0] + 1257/3417: $23\deferred_local[31:0] + 1258/3417: $23\deferred_target[31:0] + 1259/3417: $18\next_fp_value[31:0] + 1260/3417: $18\next_pc_value[31:0] + 1261/3417: $16\proposed_fp[31:0] + 1262/3417: $16\proposed_pc[31:0] + 1263/3417: $16\base_index[31:0] + 1264/3417: $16\addr_c[31:0] + 1265/3417: $16\addr_b[31:0] + 1266/3417: $16\addr_a[31:0] + 1267/3417: $16\off_c[31:0] + 1268/3417: $16\off_b[31:0] + 1269/3417: $16\off_a[31:0] + 1270/3417: $16\fp[31:0] + 1271/3417: $16\pc[31:0] + 1272/3417: $16\txn_id[31:0] + 1273/3417: $47\result_length[31:0] + 1274/3417: $23\n_deferred[31:0] + 1275/3417: $28\n_writes[31:0] + 1276/3417: $45\result_bytes[543:0] [159:152] + 1277/3417: $45\result_bytes[543:0] [151:120] + 1278/3417: $45\result_bytes[543:0] [119:88] + 1279/3417: $45\result_bytes[543:0] [87:80] + 1280/3417: $45\result_bytes[543:0] [79:48] + 1281/3417: $45\result_bytes[543:0] [47:40] + 1282/3417: $45\result_bytes[543:0] [39:8] + 1283/3417: $45\result_bytes[543:0] [7:0] + 1284/3417: $45\result_bytes[543:0] [543:160] + 1285/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2283 [31:0] + 1286/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2283 [39:32] + 1287/3417: $16\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2283 [543:40] + 1288/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2217 + 1289/3417: $44\result_bytes[543:0] + 1290/3417: $15\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2281 + 1291/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2280 + 1292/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2279 + 1293/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2278 + 1294/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2277 + 1295/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2276 + 1296/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2275 + 1297/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2274 + 1298/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2273 + 1299/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2272 + 1300/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2271 + 1301/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2270 + 1302/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2269 + 1303/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2268 + 1304/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2267 + 1305/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2266 + 1306/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2265 + 1307/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2264 + 1308/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2263 + 1309/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2262 + 1310/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2261 + 1311/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2260 + 1312/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2259 + 1313/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2258 + 1314/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2257 + 1315/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2256 + 1316/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2255 + 1317/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2254 + 1318/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2253 + 1319/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2252 + 1320/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2251 + 1321/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2250 + 1322/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2249 + 1323/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2248 + 1324/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2247 + 1325/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2246 + 1326/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2245 + 1327/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2244 + 1328/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2243 + 1329/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2242 + 1330/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2241 + 1331/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2240 + 1332/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2239 + 1333/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2238 + 1334/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2237 + 1335/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2236 + 1336/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2235 + 1337/3417: $15\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2234 + 1338/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2233 + 1339/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2232 + 1340/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2231 + 1341/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2230 + 1342/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2229 + 1343/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2228 + 1344/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2227 + 1345/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2226 + 1346/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2225 + 1347/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2224 + 1348/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2223 + 1349/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2222 + 1350/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2221 + 1351/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2220 + 1352/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2219 + 1353/3417: $15\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2218 + 1354/3417: $15\decision_deferred[0:0] + 1355/3417: $15\decision_ok[0:0] + 1356/3417: $15\decision_detail[7:0] + 1357/3417: $15\decision_fault[7:0] + 1358/3417: $27\write_value[127:0] + 1359/3417: $27\write_address[31:0] + 1360/3417: $15\retired_bytes[543:0] + 1361/3417: $17\solved_b[127:0] + 1362/3417: $17\solved_a[127:0] + 1363/3417: $15\result_value[127:0] + 1364/3417: $15\inv_value[127:0] + 1365/3417: $15\val_c[127:0] + 1366/3417: $15\val_b[127:0] + 1367/3417: $15\val_a[127:0] + 1368/3417: $15\taken_proposal[7:0] + 1369/3417: $15\inv_present[7:0] + 1370/3417: $15\pres_c[7:0] + 1371/3417: $15\pres_b[7:0] + 1372/3417: $15\pres_a[7:0] + 1373/3417: $15\profile[7:0] + 1374/3417: $22\deferred_local[31:0] + 1375/3417: $22\deferred_target[31:0] + 1376/3417: $17\next_fp_value[31:0] + 1377/3417: $17\next_pc_value[31:0] + 1378/3417: $15\proposed_fp[31:0] + 1379/3417: $15\proposed_pc[31:0] + 1380/3417: $15\base_index[31:0] + 1381/3417: $15\addr_c[31:0] + 1382/3417: $15\addr_b[31:0] + 1383/3417: $15\addr_a[31:0] + 1384/3417: $15\off_c[31:0] + 1385/3417: $15\off_b[31:0] + 1386/3417: $15\off_a[31:0] + 1387/3417: $15\fp[31:0] + 1388/3417: $15\pc[31:0] + 1389/3417: $15\txn_id[31:0] + 1390/3417: $46\result_length[31:0] + 1391/3417: $22\n_deferred[31:0] + 1392/3417: $27\n_writes[31:0] + 1393/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$2148 [543:40] + 1394/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$2148 [31:0] + 1395/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$2148 [39:32] + 1396/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$2147 + 1397/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$2146 + 1398/3417: $14\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2213 + 1399/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2212 + 1400/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2211 + 1401/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2210 + 1402/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2209 + 1403/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2208 + 1404/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2207 + 1405/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2206 + 1406/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2205 + 1407/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2204 + 1408/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2203 + 1409/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2202 + 1410/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2201 + 1411/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2200 + 1412/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2199 + 1413/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2198 + 1414/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2197 + 1415/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2196 + 1416/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2195 + 1417/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2194 + 1418/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2193 + 1419/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2192 + 1420/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2191 + 1421/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2190 + 1422/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2189 + 1423/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2188 + 1424/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2187 + 1425/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2186 + 1426/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2185 + 1427/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2184 + 1428/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2183 + 1429/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2182 + 1430/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2181 + 1431/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2180 + 1432/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2179 + 1433/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2178 + 1434/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2177 + 1435/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2176 + 1436/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2175 + 1437/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2174 + 1438/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2173 + 1439/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2172 + 1440/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2171 + 1441/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2170 + 1442/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2169 + 1443/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2168 + 1444/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2167 + 1445/3417: $14\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2166 + 1446/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2165 + 1447/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2164 + 1448/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2163 + 1449/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2162 + 1450/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2161 + 1451/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2160 + 1452/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2159 + 1453/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2158 + 1454/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2157 + 1455/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2156 + 1456/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2155 + 1457/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2154 + 1458/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2153 + 1459/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2152 + 1460/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2151 + 1461/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2150 + 1462/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2149 + 1463/3417: $14\decision_deferred[0:0] + 1464/3417: $14\decision_ok[0:0] + 1465/3417: $14\decision_detail[7:0] + 1466/3417: $14\decision_fault[7:0] + 1467/3417: $26\write_value[127:0] + 1468/3417: $26\write_address[31:0] + 1469/3417: $14\retired_bytes[543:0] + 1470/3417: $43\result_bytes[543:0] + 1471/3417: $16\solved_b[127:0] + 1472/3417: $16\solved_a[127:0] + 1473/3417: $14\result_value[127:0] + 1474/3417: $14\inv_value[127:0] + 1475/3417: $14\val_c[127:0] + 1476/3417: $14\val_b[127:0] + 1477/3417: $14\val_a[127:0] + 1478/3417: $14\taken_proposal[7:0] + 1479/3417: $14\inv_present[7:0] + 1480/3417: $14\pres_c[7:0] + 1481/3417: $14\pres_b[7:0] + 1482/3417: $14\pres_a[7:0] + 1483/3417: $14\profile[7:0] + 1484/3417: $21\deferred_local[31:0] + 1485/3417: $21\deferred_target[31:0] + 1486/3417: $16\next_fp_value[31:0] + 1487/3417: $16\next_pc_value[31:0] + 1488/3417: $14\proposed_fp[31:0] + 1489/3417: $14\proposed_pc[31:0] + 1490/3417: $14\base_index[31:0] + 1491/3417: $14\addr_c[31:0] + 1492/3417: $14\addr_b[31:0] + 1493/3417: $14\addr_a[31:0] + 1494/3417: $14\off_c[31:0] + 1495/3417: $14\off_b[31:0] + 1496/3417: $14\off_a[31:0] + 1497/3417: $14\fp[31:0] + 1498/3417: $14\pc[31:0] + 1499/3417: $14\txn_id[31:0] + 1500/3417: $45\result_length[31:0] + 1501/3417: $21\n_deferred[31:0] + 1502/3417: $26\n_writes[31:0] + 1503/3417: $13\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2145 + 1504/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2144 + 1505/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2143 + 1506/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2142 + 1507/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2141 + 1508/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2140 + 1509/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2139 + 1510/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2138 + 1511/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2137 + 1512/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2136 + 1513/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2135 + 1514/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2134 + 1515/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2133 + 1516/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2132 + 1517/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2131 + 1518/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2130 + 1519/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2129 + 1520/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2128 + 1521/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2127 + 1522/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2126 + 1523/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2125 + 1524/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2124 + 1525/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2123 + 1526/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2122 + 1527/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2121 + 1528/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2120 + 1529/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2119 + 1530/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2118 + 1531/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2117 + 1532/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2116 + 1533/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2115 + 1534/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2114 + 1535/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2113 + 1536/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2112 + 1537/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2111 + 1538/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2110 + 1539/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2109 + 1540/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2108 + 1541/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2107 + 1542/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2106 + 1543/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2105 + 1544/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2104 + 1545/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2103 + 1546/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2102 + 1547/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2101 + 1548/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2100 + 1549/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2099 + 1550/3417: $13\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2098 + 1551/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2097 + 1552/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2096 + 1553/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2095 + 1554/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2094 + 1555/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2093 + 1556/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2092 + 1557/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2091 + 1558/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2090 + 1559/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2089 + 1560/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2088 + 1561/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2087 + 1562/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2086 + 1563/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2085 + 1564/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2084 + 1565/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2083 + 1566/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2082 + 1567/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2081 + 1568/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$2080 + 1569/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$2079 + 1570/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$2078 + 1571/3417: $13\decision_deferred[0:0] + 1572/3417: $13\decision_ok[0:0] + 1573/3417: $13\decision_detail[7:0] + 1574/3417: $13\decision_fault[7:0] + 1575/3417: $25\write_value[127:0] + 1576/3417: $25\write_address[31:0] + 1577/3417: $13\retired_bytes[543:0] + 1578/3417: $42\result_bytes[543:0] + 1579/3417: $15\solved_b[127:0] + 1580/3417: $15\solved_a[127:0] + 1581/3417: $13\result_value[127:0] + 1582/3417: $13\inv_value[127:0] + 1583/3417: $13\val_c[127:0] + 1584/3417: $13\val_b[127:0] + 1585/3417: $13\val_a[127:0] + 1586/3417: $13\taken_proposal[7:0] + 1587/3417: $13\inv_present[7:0] + 1588/3417: $13\pres_c[7:0] + 1589/3417: $13\pres_b[7:0] + 1590/3417: $13\pres_a[7:0] + 1591/3417: $13\profile[7:0] + 1592/3417: $20\deferred_local[31:0] + 1593/3417: $20\deferred_target[31:0] + 1594/3417: $15\next_fp_value[31:0] + 1595/3417: $15\next_pc_value[31:0] + 1596/3417: $13\proposed_fp[31:0] + 1597/3417: $13\proposed_pc[31:0] + 1598/3417: $13\base_index[31:0] + 1599/3417: $13\addr_c[31:0] + 1600/3417: $13\addr_b[31:0] + 1601/3417: $13\addr_a[31:0] + 1602/3417: $13\off_c[31:0] + 1603/3417: $13\off_b[31:0] + 1604/3417: $13\off_a[31:0] + 1605/3417: $13\fp[31:0] + 1606/3417: $13\pc[31:0] + 1607/3417: $13\txn_id[31:0] + 1608/3417: $44\result_length[31:0] + 1609/3417: $20\n_deferred[31:0] + 1610/3417: $25\n_writes[31:0] + 1611/3417: $43\result_length[31:0] + 1612/3417: $41\result_bytes[215:152] [63:32] + 1613/3417: $41\result_bytes[215:152] [31:0] + 1614/3417: $40\result_bytes[279:104] [111:80] + 1615/3417: $40\result_bytes[279:104] [47:40] + 1616/3417: $40\result_bytes[279:104] [15:8] + 1617/3417: $40\result_bytes[279:104] [143:112] + 1618/3417: $42\result_length[31:0] + 1619/3417: $40\result_bytes[279:104] [79:72] + 1620/3417: $40\result_bytes[279:104] [71:48] + 1621/3417: $40\result_bytes[279:104] [39:16] + 1622/3417: $40\result_bytes[279:104] [175:144] + 1623/3417: $40\result_bytes[279:104] [7:0] + 1624/3417: $38\result_bytes[375:104] [175:168] + 1625/3417: $39\result_bytes[375:312] [63:32] + 1626/3417: $39\result_bytes[375:312] [31:0] + 1627/3417: $38\result_bytes[375:104] [207:176] + 1628/3417: $40\result_length[31:0] + 1629/3417: $41\result_length[31:0] + 1630/3417: $38\result_bytes[375:104] [167:160] + 1631/3417: $38\result_bytes[375:104] [159:32] + 1632/3417: $38\result_bytes[375:104] [31:0] + 1633/3417: $38\result_bytes[375:104] [271:208] + 1634/3417: $24\n_writes[31:0] + 1635/3417: $24\write_value[127:0] + 1636/3417: $24\write_address[31:0] + 1637/3417: $37\result_bytes[543:0] [375:104] + 1638/3417: $37\result_bytes[543:0] [103:96] + 1639/3417: $37\result_bytes[543:0] [95:64] + 1640/3417: $37\result_bytes[543:0] [63:32] + 1641/3417: $37\result_bytes[543:0] [31:0] + 1642/3417: $37\result_bytes[543:0] [543:376] + 1643/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$2073 [31:0] + 1644/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$2073 [39:32] + 1645/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$2072 + 1646/3417: $23\write_value[127:0] + 1647/3417: $23\write_address[31:0] + 1648/3417: $14\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$2073 [543:40] + 1649/3417: $39\result_length[31:0] + 1650/3417: $23\n_writes[31:0] + 1651/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$2066 [543:40] + 1652/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$2066 [31:0] + 1653/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$2066 [39:32] + 1654/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$2065 + 1655/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$2069 + 1656/3417: $13\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$2068 + 1657/3417: $13\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$2067 + 1658/3417: $22\write_value[127:0] + 1659/3417: $22\write_address[31:0] + 1660/3417: $36\result_bytes[543:0] + 1661/3417: $38\result_length[31:0] + 1662/3417: $22\n_writes[31:0] + 1663/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1996 + 1664/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1995 + 1665/3417: $12\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1994 + 1666/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1993 + 1667/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1992 + 1668/3417: $21\write_value[127:0] + 1669/3417: $21\write_address[31:0] + 1670/3417: $35\result_bytes[543:0] + 1671/3417: $37\result_length[31:0] + 1672/3417: $21\n_writes[31:0] + 1673/3417: $12\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2064 + 1674/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2063 + 1675/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2062 + 1676/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2061 + 1677/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2060 + 1678/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2059 + 1679/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2058 + 1680/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2057 + 1681/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2056 + 1682/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2055 + 1683/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2054 + 1684/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2053 + 1685/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2052 + 1686/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2051 + 1687/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2050 + 1688/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2049 + 1689/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2048 + 1690/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2047 + 1691/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2046 + 1692/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2045 + 1693/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2044 + 1694/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2043 + 1695/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2042 + 1696/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2041 + 1697/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2040 + 1698/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2039 + 1699/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2038 + 1700/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2037 + 1701/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2036 + 1702/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2035 + 1703/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2034 + 1704/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2033 + 1705/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2032 + 1706/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2031 + 1707/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2030 + 1708/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2029 + 1709/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2028 + 1710/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2027 + 1711/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2026 + 1712/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2025 + 1713/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2024 + 1714/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2023 + 1715/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2022 + 1716/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2021 + 1717/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2020 + 1718/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$2019 + 1719/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$2018 + 1720/3417: $12\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$2017 + 1721/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2016 + 1722/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$2015 + 1723/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$2014 + 1724/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$2013 + 1725/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$2012 + 1726/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$2011 + 1727/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$2010 + 1728/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$2009 + 1729/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$2008 + 1730/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$2007 + 1731/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$2006 + 1732/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$2005 + 1733/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$2004 + 1734/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$2003 + 1735/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$2002 + 1736/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$2001 + 1737/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$2000 + 1738/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1999 + 1739/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1998 + 1740/3417: $12\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1997 + 1741/3417: $12\decision_deferred[0:0] + 1742/3417: $12\decision_ok[0:0] + 1743/3417: $12\decision_detail[7:0] + 1744/3417: $12\decision_fault[7:0] + 1745/3417: $12\retired_bytes[543:0] + 1746/3417: $14\solved_b[127:0] + 1747/3417: $14\solved_a[127:0] + 1748/3417: $12\result_value[127:0] + 1749/3417: $12\inv_value[127:0] + 1750/3417: $12\val_c[127:0] + 1751/3417: $12\val_b[127:0] + 1752/3417: $12\val_a[127:0] + 1753/3417: $12\taken_proposal[7:0] + 1754/3417: $12\inv_present[7:0] + 1755/3417: $12\pres_c[7:0] + 1756/3417: $12\pres_b[7:0] + 1757/3417: $12\pres_a[7:0] + 1758/3417: $12\profile[7:0] + 1759/3417: $19\deferred_local[31:0] + 1760/3417: $19\deferred_target[31:0] + 1761/3417: $14\next_fp_value[31:0] + 1762/3417: $14\next_pc_value[31:0] + 1763/3417: $12\proposed_fp[31:0] + 1764/3417: $12\proposed_pc[31:0] + 1765/3417: $12\base_index[31:0] + 1766/3417: $12\addr_c[31:0] + 1767/3417: $12\addr_b[31:0] + 1768/3417: $12\addr_a[31:0] + 1769/3417: $12\off_c[31:0] + 1770/3417: $12\off_b[31:0] + 1771/3417: $12\off_a[31:0] + 1772/3417: $12\fp[31:0] + 1773/3417: $12\pc[31:0] + 1774/3417: $12\txn_id[31:0] + 1775/3417: $19\n_deferred[31:0] + 1776/3417: $13\solved_a[127:0] + 1777/3417: $13\solved_b[127:0] + 1778/3417: $20\n_writes[31:0] + 1779/3417: $20\write_value[127:0] + 1780/3417: $20\write_address[31:0] + 1781/3417: $12\solved_b[127:0] + 1782/3417: $12\solved_a[127:0] + 1783/3417: $11\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1984 + 1784/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1983 + 1785/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1982 + 1786/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1981 + 1787/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1980 + 1788/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1979 + 1789/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1978 + 1790/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1977 + 1791/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1976 + 1792/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1975 + 1793/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1974 + 1794/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1973 + 1795/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1972 + 1796/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1971 + 1797/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1970 + 1798/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1969 + 1799/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1968 + 1800/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1967 + 1801/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1966 + 1802/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1965 + 1803/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1964 + 1804/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1963 + 1805/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1962 + 1806/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1961 + 1807/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1960 + 1808/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1959 + 1809/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1958 + 1810/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1957 + 1811/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1956 + 1812/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1955 + 1813/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1954 + 1814/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1953 + 1815/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1952 + 1816/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1951 + 1817/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1950 + 1818/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1949 + 1819/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1948 + 1820/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1947 + 1821/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1946 + 1822/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1945 + 1823/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1944 + 1824/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1943 + 1825/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1942 + 1826/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1941 + 1827/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1940 + 1828/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1939 + 1829/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1938 + 1830/3417: $11\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1937 + 1831/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1936 + 1832/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1935 + 1833/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1934 + 1834/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1933 + 1835/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1932 + 1836/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1931 + 1837/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1930 + 1838/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1929 + 1839/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1928 + 1840/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1927 + 1841/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1926 + 1842/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1925 + 1843/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1924 + 1844/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1923 + 1845/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1922 + 1846/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1921 + 1847/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1920 + 1848/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1919 + 1849/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1918 + 1850/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1917 + 1851/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1916 + 1852/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1915 + 1853/3417: $11\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1914 + 1854/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1913 + 1855/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1912 + 1856/3417: $11\decision_deferred[0:0] + 1857/3417: $11\decision_ok[0:0] + 1858/3417: $11\decision_detail[7:0] + 1859/3417: $11\decision_fault[7:0] + 1860/3417: $11\retired_bytes[543:0] + 1861/3417: $34\result_bytes[543:0] + 1862/3417: $11\result_value[127:0] + 1863/3417: $11\inv_value[127:0] + 1864/3417: $11\val_c[127:0] + 1865/3417: $11\val_b[127:0] + 1866/3417: $11\val_a[127:0] + 1867/3417: $11\taken_proposal[7:0] + 1868/3417: $11\inv_present[7:0] + 1869/3417: $11\pres_c[7:0] + 1870/3417: $11\pres_b[7:0] + 1871/3417: $11\pres_a[7:0] + 1872/3417: $11\profile[7:0] + 1873/3417: $18\deferred_local[31:0] + 1874/3417: $18\deferred_target[31:0] + 1875/3417: $13\next_fp_value[31:0] + 1876/3417: $13\next_pc_value[31:0] + 1877/3417: $11\proposed_fp[31:0] + 1878/3417: $11\proposed_pc[31:0] + 1879/3417: $11\base_index[31:0] + 1880/3417: $11\addr_c[31:0] + 1881/3417: $11\addr_b[31:0] + 1882/3417: $11\addr_a[31:0] + 1883/3417: $11\off_c[31:0] + 1884/3417: $11\off_b[31:0] + 1885/3417: $11\off_a[31:0] + 1886/3417: $11\fp[31:0] + 1887/3417: $11\pc[31:0] + 1888/3417: $11\txn_id[31:0] + 1889/3417: $36\result_length[31:0] + 1890/3417: $18\n_deferred[31:0] + 1891/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1909 [543:40] + 1892/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1909 [31:0] + 1893/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1909 [39:32] + 1894/3417: $11\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1908 + 1895/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1832 + 1896/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1831 + 1897/3417: $10\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1905 + 1898/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1904 + 1899/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1903 + 1900/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1902 + 1901/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1901 + 1902/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1900 + 1903/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1899 + 1904/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1898 + 1905/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1897 + 1906/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1896 + 1907/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1895 + 1908/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1894 + 1909/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1893 + 1910/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1892 + 1911/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1891 + 1912/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1890 + 1913/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1889 + 1914/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1888 + 1915/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1887 + 1916/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1886 + 1917/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1885 + 1918/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1884 + 1919/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1883 + 1920/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1882 + 1921/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1881 + 1922/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1880 + 1923/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1879 + 1924/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1878 + 1925/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1877 + 1926/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1876 + 1927/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1875 + 1928/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1874 + 1929/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1873 + 1930/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1872 + 1931/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1871 + 1932/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1870 + 1933/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1869 + 1934/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1868 + 1935/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1867 + 1936/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1866 + 1937/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1865 + 1938/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1864 + 1939/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1863 + 1940/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1862 + 1941/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1861 + 1942/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1860 + 1943/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1859 + 1944/3417: $10\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1858 + 1945/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1857 + 1946/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1856 + 1947/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1855 + 1948/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1854 + 1949/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1853 + 1950/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1852 + 1951/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1851 + 1952/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1850 + 1953/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1849 + 1954/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1848 + 1955/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1847 + 1956/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1846 + 1957/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1845 + 1958/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1844 + 1959/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1843 + 1960/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1842 + 1961/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1841 + 1962/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1840 + 1963/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1839 + 1964/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1838 + 1965/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1837 + 1966/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1836 + 1967/3417: $10\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1835 + 1968/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1834 + 1969/3417: $10\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1833 + 1970/3417: $10\decision_deferred[0:0] + 1971/3417: $10\decision_ok[0:0] + 1972/3417: $10\decision_detail[7:0] + 1973/3417: $10\decision_fault[7:0] + 1974/3417: $19\write_value[127:0] + 1975/3417: $19\write_address[31:0] + 1976/3417: $10\retired_bytes[543:0] + 1977/3417: $33\result_bytes[543:0] + 1978/3417: $11\solved_b[127:0] + 1979/3417: $11\solved_a[127:0] + 1980/3417: $10\result_value[127:0] + 1981/3417: $10\inv_value[127:0] + 1982/3417: $10\val_c[127:0] + 1983/3417: $10\val_b[127:0] + 1984/3417: $10\val_a[127:0] + 1985/3417: $10\taken_proposal[7:0] + 1986/3417: $10\inv_present[7:0] + 1987/3417: $10\pres_c[7:0] + 1988/3417: $10\pres_b[7:0] + 1989/3417: $10\pres_a[7:0] + 1990/3417: $10\profile[7:0] + 1991/3417: $17\deferred_local[31:0] + 1992/3417: $17\deferred_target[31:0] + 1993/3417: $12\next_fp_value[31:0] + 1994/3417: $12\next_pc_value[31:0] + 1995/3417: $10\proposed_fp[31:0] + 1996/3417: $10\proposed_pc[31:0] + 1997/3417: $10\base_index[31:0] + 1998/3417: $10\addr_c[31:0] + 1999/3417: $10\addr_b[31:0] + 2000/3417: $10\addr_a[31:0] + 2001/3417: $10\off_c[31:0] + 2002/3417: $10\off_b[31:0] + 2003/3417: $10\off_a[31:0] + 2004/3417: $10\fp[31:0] + 2005/3417: $10\pc[31:0] + 2006/3417: $10\txn_id[31:0] + 2007/3417: $35\result_length[31:0] + 2008/3417: $17\n_deferred[31:0] + 2009/3417: $19\n_writes[31:0] + 2010/3417: $10\solved_a[127:0] + 2011/3417: $10\solved_b[127:0] + 2012/3417: $18\n_writes[31:0] + 2013/3417: $18\write_value[127:0] + 2014/3417: $18\write_address[31:0] + 2015/3417: $9\solved_b[127:0] + 2016/3417: $9\solved_a[127:0] + 2017/3417: $9\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1825 + 2018/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1824 + 2019/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1823 + 2020/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1822 + 2021/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1821 + 2022/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1820 + 2023/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1819 + 2024/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1818 + 2025/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1817 + 2026/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1816 + 2027/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1815 + 2028/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1814 + 2029/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1813 + 2030/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1812 + 2031/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1811 + 2032/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1810 + 2033/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1809 + 2034/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1808 + 2035/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1807 + 2036/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1806 + 2037/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1805 + 2038/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1804 + 2039/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1803 + 2040/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1802 + 2041/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1801 + 2042/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1800 + 2043/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1799 + 2044/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1798 + 2045/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1797 + 2046/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1796 + 2047/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1795 + 2048/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1794 + 2049/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1793 + 2050/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1792 + 2051/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1791 + 2052/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1790 + 2053/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1789 + 2054/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1788 + 2055/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1787 + 2056/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1786 + 2057/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1785 + 2058/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1784 + 2059/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1783 + 2060/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1782 + 2061/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1781 + 2062/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1780 + 2063/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1779 + 2064/3417: $9\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1778 + 2065/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1777 + 2066/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1776 + 2067/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1775 + 2068/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1774 + 2069/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1773 + 2070/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1772 + 2071/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1771 + 2072/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1770 + 2073/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1769 + 2074/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1768 + 2075/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1767 + 2076/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1766 + 2077/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1765 + 2078/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1764 + 2079/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1763 + 2080/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1762 + 2081/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1761 + 2082/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1760 + 2083/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1759 + 2084/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1758 + 2085/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1757 + 2086/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1756 + 2087/3417: $9\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1755 + 2088/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1754 + 2089/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1753 + 2090/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1752 + 2091/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1751 + 2092/3417: $9\decision_deferred[0:0] + 2093/3417: $9\decision_ok[0:0] + 2094/3417: $9\decision_detail[7:0] + 2095/3417: $9\decision_fault[7:0] + 2096/3417: $9\retired_bytes[543:0] + 2097/3417: $32\result_bytes[543:0] + 2098/3417: $9\result_value[127:0] + 2099/3417: $9\inv_value[127:0] + 2100/3417: $9\val_c[127:0] + 2101/3417: $9\val_b[127:0] + 2102/3417: $9\val_a[127:0] + 2103/3417: $9\taken_proposal[7:0] + 2104/3417: $9\inv_present[7:0] + 2105/3417: $9\pres_c[7:0] + 2106/3417: $9\pres_b[7:0] + 2107/3417: $9\pres_a[7:0] + 2108/3417: $9\profile[7:0] + 2109/3417: $16\deferred_local[31:0] + 2110/3417: $16\deferred_target[31:0] + 2111/3417: $11\next_fp_value[31:0] + 2112/3417: $11\next_pc_value[31:0] + 2113/3417: $9\proposed_fp[31:0] + 2114/3417: $9\proposed_pc[31:0] + 2115/3417: $9\base_index[31:0] + 2116/3417: $9\addr_c[31:0] + 2117/3417: $9\addr_b[31:0] + 2118/3417: $9\addr_a[31:0] + 2119/3417: $9\off_c[31:0] + 2120/3417: $9\off_b[31:0] + 2121/3417: $9\off_a[31:0] + 2122/3417: $9\fp[31:0] + 2123/3417: $9\pc[31:0] + 2124/3417: $9\txn_id[31:0] + 2125/3417: $34\result_length[31:0] + 2126/3417: $16\n_deferred[31:0] + 2127/3417: $33\result_length[31:0] + 2128/3417: $31\result_bytes[279:104] [47:40] + 2129/3417: $31\result_bytes[279:104] [15:8] + 2130/3417: $31\result_bytes[279:104] [39:16] + 2131/3417: $31\result_bytes[279:104] [143:112] + 2132/3417: $31\result_bytes[279:104] [111:80] + 2133/3417: $31\result_bytes[279:104] [79:72] + 2134/3417: $31\result_bytes[279:104] [71:48] + 2135/3417: $32\result_length[31:0] + 2136/3417: $31\result_bytes[279:104] [175:144] + 2137/3417: $31\result_bytes[279:104] [7:0] + 2138/3417: $30\result_bytes[311:104] [175:168] + 2139/3417: $30\result_length[31:0] + 2140/3417: $30\result_bytes[311:104] [207:176] + 2141/3417: $30\result_bytes[311:104] [167:160] + 2142/3417: $30\result_bytes[311:104] [159:32] + 2143/3417: $30\result_bytes[311:104] [31:0] + 2144/3417: $31\result_length[31:0] + 2145/3417: $29\result_bytes[543:0] [311:104] + 2146/3417: $29\result_bytes[543:0] [103:96] + 2147/3417: $29\result_bytes[543:0] [95:64] + 2148/3417: $29\result_bytes[543:0] [63:32] + 2149/3417: $29\result_bytes[543:0] [31:0] + 2150/3417: $29\result_bytes[543:0] [543:312] + 2151/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1746 [31:0] + 2152/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1746 [39:32] + 2153/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1745 + 2154/3417: $9\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1746 [543:40] + 2155/3417: $29\result_length[31:0] + 2156/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1667 + 2157/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1666 + 2158/3417: $28\result_bytes[543:0] + 2159/3417: $28\result_length[31:0] + 2160/3417: $8\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1742 + 2161/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1741 + 2162/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1740 + 2163/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1739 + 2164/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1738 + 2165/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1737 + 2166/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1736 + 2167/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1735 + 2168/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1734 + 2169/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1733 + 2170/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1732 + 2171/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1731 + 2172/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1730 + 2173/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1729 + 2174/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1728 + 2175/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1727 + 2176/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1726 + 2177/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1725 + 2178/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1724 + 2179/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1723 + 2180/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1722 + 2181/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1721 + 2182/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1720 + 2183/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1719 + 2184/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1718 + 2185/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1717 + 2186/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1716 + 2187/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1715 + 2188/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1714 + 2189/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1713 + 2190/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1712 + 2191/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1711 + 2192/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1710 + 2193/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1709 + 2194/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1708 + 2195/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1707 + 2196/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1706 + 2197/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1705 + 2198/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1704 + 2199/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1703 + 2200/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1702 + 2201/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1701 + 2202/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1700 + 2203/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1699 + 2204/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1698 + 2205/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1697 + 2206/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1696 + 2207/3417: $8\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1695 + 2208/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1694 + 2209/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1693 + 2210/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1692 + 2211/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1691 + 2212/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1690 + 2213/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1689 + 2214/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1688 + 2215/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1687 + 2216/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1686 + 2217/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1685 + 2218/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1684 + 2219/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1683 + 2220/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1682 + 2221/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1681 + 2222/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1680 + 2223/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1679 + 2224/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1678 + 2225/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1677 + 2226/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1676 + 2227/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1675 + 2228/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1674 + 2229/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1673 + 2230/3417: $8\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1672 + 2231/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1671 + 2232/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1670 + 2233/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1669 + 2234/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1668 + 2235/3417: $8\decision_deferred[0:0] + 2236/3417: $8\decision_ok[0:0] + 2237/3417: $8\decision_detail[7:0] + 2238/3417: $8\decision_fault[7:0] + 2239/3417: $17\write_value[127:0] + 2240/3417: $17\write_address[31:0] + 2241/3417: $8\retired_bytes[543:0] + 2242/3417: $8\solved_b[127:0] + 2243/3417: $8\solved_a[127:0] + 2244/3417: $8\result_value[127:0] + 2245/3417: $8\inv_value[127:0] + 2246/3417: $8\val_c[127:0] + 2247/3417: $8\val_b[127:0] + 2248/3417: $8\val_a[127:0] + 2249/3417: $8\taken_proposal[7:0] + 2250/3417: $8\inv_present[7:0] + 2251/3417: $8\pres_c[7:0] + 2252/3417: $8\pres_b[7:0] + 2253/3417: $8\pres_a[7:0] + 2254/3417: $8\profile[7:0] + 2255/3417: $15\deferred_local[31:0] + 2256/3417: $15\deferred_target[31:0] + 2257/3417: $10\next_fp_value[31:0] + 2258/3417: $10\next_pc_value[31:0] + 2259/3417: $8\proposed_fp[31:0] + 2260/3417: $8\proposed_pc[31:0] + 2261/3417: $8\base_index[31:0] + 2262/3417: $8\addr_c[31:0] + 2263/3417: $8\addr_b[31:0] + 2264/3417: $8\addr_a[31:0] + 2265/3417: $8\off_c[31:0] + 2266/3417: $8\off_b[31:0] + 2267/3417: $8\off_a[31:0] + 2268/3417: $8\fp[31:0] + 2269/3417: $8\pc[31:0] + 2270/3417: $8\txn_id[31:0] + 2271/3417: $15\n_deferred[31:0] + 2272/3417: $17\n_writes[31:0] + 2273/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1663 [543:40] + 2274/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1663 [31:0] + 2275/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1663 [39:32] + 2276/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1662 + 2277/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1582 + 2278/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1581 + 2279/3417: $7\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1659 + 2280/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1658 + 2281/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1657 + 2282/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1656 + 2283/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1655 + 2284/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1654 + 2285/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1653 + 2286/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1652 + 2287/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1651 + 2288/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1650 + 2289/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1649 + 2290/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1648 + 2291/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1647 + 2292/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1646 + 2293/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1645 + 2294/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1644 + 2295/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1643 + 2296/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1642 + 2297/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1641 + 2298/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1640 + 2299/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1639 + 2300/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1638 + 2301/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1637 + 2302/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1636 + 2303/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1635 + 2304/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1634 + 2305/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1633 + 2306/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1632 + 2307/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1631 + 2308/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1630 + 2309/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1629 + 2310/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1628 + 2311/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1627 + 2312/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1626 + 2313/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1625 + 2314/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1624 + 2315/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1623 + 2316/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1622 + 2317/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1621 + 2318/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1620 + 2319/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1619 + 2320/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1618 + 2321/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1617 + 2322/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1616 + 2323/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1615 + 2324/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1614 + 2325/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1613 + 2326/3417: $7\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1612 + 2327/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1611 + 2328/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1610 + 2329/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1609 + 2330/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1608 + 2331/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1607 + 2332/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1606 + 2333/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1605 + 2334/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1604 + 2335/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1603 + 2336/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1602 + 2337/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1601 + 2338/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1600 + 2339/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1599 + 2340/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1598 + 2341/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1597 + 2342/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1596 + 2343/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1595 + 2344/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1594 + 2345/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1593 + 2346/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1592 + 2347/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1591 + 2348/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1590 + 2349/3417: $7\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1589 + 2350/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1588 + 2351/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1587 + 2352/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1586 + 2353/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1585 + 2354/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1584 + 2355/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1583 + 2356/3417: $7\decision_deferred[0:0] + 2357/3417: $7\decision_ok[0:0] + 2358/3417: $7\decision_detail[7:0] + 2359/3417: $7\decision_fault[7:0] + 2360/3417: $16\write_value[127:0] + 2361/3417: $16\write_address[31:0] + 2362/3417: $7\retired_bytes[543:0] + 2363/3417: $27\result_bytes[543:0] + 2364/3417: $7\solved_b[127:0] + 2365/3417: $7\solved_a[127:0] + 2366/3417: $7\result_value[127:0] + 2367/3417: $7\inv_value[127:0] + 2368/3417: $7\val_c[127:0] + 2369/3417: $7\val_b[127:0] + 2370/3417: $7\val_a[127:0] + 2371/3417: $7\taken_proposal[7:0] + 2372/3417: $7\inv_present[7:0] + 2373/3417: $7\pres_c[7:0] + 2374/3417: $7\pres_b[7:0] + 2375/3417: $7\pres_a[7:0] + 2376/3417: $7\profile[7:0] + 2377/3417: $14\deferred_local[31:0] + 2378/3417: $14\deferred_target[31:0] + 2379/3417: $9\next_fp_value[31:0] + 2380/3417: $9\next_pc_value[31:0] + 2381/3417: $7\proposed_fp[31:0] + 2382/3417: $7\proposed_pc[31:0] + 2383/3417: $7\base_index[31:0] + 2384/3417: $7\addr_c[31:0] + 2385/3417: $7\addr_b[31:0] + 2386/3417: $7\addr_a[31:0] + 2387/3417: $7\off_c[31:0] + 2388/3417: $7\off_b[31:0] + 2389/3417: $7\off_a[31:0] + 2390/3417: $7\fp[31:0] + 2391/3417: $7\pc[31:0] + 2392/3417: $7\txn_id[31:0] + 2393/3417: $27\result_length[31:0] + 2394/3417: $14\n_deferred[31:0] + 2395/3417: $16\n_writes[31:0] + 2396/3417: $26\result_length[31:0] + 2397/3417: $26\result_bytes[215:152] [63:32] + 2398/3417: $26\result_bytes[215:152] [31:0] + 2399/3417: $25\result_bytes[279:104] [111:80] + 2400/3417: $25\result_bytes[279:104] [47:40] + 2401/3417: $25\result_bytes[279:104] [15:8] + 2402/3417: $25\result_bytes[279:104] [143:112] + 2403/3417: $25\result_length[31:0] + 2404/3417: $25\result_bytes[279:104] [79:72] + 2405/3417: $25\result_bytes[279:104] [71:48] + 2406/3417: $25\result_bytes[279:104] [39:16] + 2407/3417: $25\result_bytes[279:104] [175:144] + 2408/3417: $25\result_bytes[279:104] [7:0] + 2409/3417: $23\result_bytes[375:104] [175:168] + 2410/3417: $24\result_bytes[375:312] [63:32] + 2411/3417: $24\result_bytes[375:312] [31:0] + 2412/3417: $23\result_bytes[375:104] [207:176] + 2413/3417: $23\result_length[31:0] + 2414/3417: $24\result_length[31:0] + 2415/3417: $23\result_bytes[375:104] [167:160] + 2416/3417: $23\result_bytes[375:104] [159:32] + 2417/3417: $23\result_bytes[375:104] [31:0] + 2418/3417: $23\result_bytes[375:104] [271:208] + 2419/3417: $22\result_bytes[543:0] [375:104] + 2420/3417: $22\result_bytes[543:0] [103:96] + 2421/3417: $22\result_bytes[543:0] [95:64] + 2422/3417: $22\result_bytes[543:0] [63:32] + 2423/3417: $22\result_bytes[543:0] [31:0] + 2424/3417: $22\result_bytes[543:0] [543:376] + 2425/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1576 [31:0] + 2426/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1576 [39:32] + 2427/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1575 + 2428/3417: $8\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1576 [543:40] + 2429/3417: $8\next_fp_value[31:0] + 2430/3417: $8\next_pc_value[31:0] + 2431/3417: $22\result_length[31:0] + 2432/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1571 [543:40] + 2433/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1571 [31:0] + 2434/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1571 [39:32] + 2435/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1570 + 2436/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1573 + 2437/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1572 + 2438/3417: $21\result_bytes[543:0] + 2439/3417: $7\next_fp_value[31:0] + 2440/3417: $7\next_pc_value[31:0] + 2441/3417: $21\result_length[31:0] + 2442/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1490 + 2443/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1489 + 2444/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1488 + 2445/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1487 + 2446/3417: $20\result_bytes[543:0] + 2447/3417: $6\next_fp_value[31:0] + 2448/3417: $6\next_pc_value[31:0] + 2449/3417: $20\result_length[31:0] + 2450/3417: $6\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1569 + 2451/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1568 + 2452/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1567 + 2453/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1566 + 2454/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1565 + 2455/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1564 + 2456/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1563 + 2457/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1562 + 2458/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1561 + 2459/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1560 + 2460/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1559 + 2461/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1558 + 2462/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1557 + 2463/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1556 + 2464/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1555 + 2465/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1554 + 2466/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1553 + 2467/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1552 + 2468/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1551 + 2469/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1550 + 2470/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1549 + 2471/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1548 + 2472/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1547 + 2473/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1546 + 2474/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1545 + 2475/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1544 + 2476/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1543 + 2477/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1542 + 2478/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1541 + 2479/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1540 + 2480/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1539 + 2481/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1538 + 2482/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1537 + 2483/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1536 + 2484/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1535 + 2485/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1534 + 2486/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1533 + 2487/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1532 + 2488/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1531 + 2489/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1530 + 2490/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1529 + 2491/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1528 + 2492/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1527 + 2493/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1526 + 2494/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1525 + 2495/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1524 + 2496/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1523 + 2497/3417: $6\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1522 + 2498/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1521 + 2499/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1520 + 2500/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1519 + 2501/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1518 + 2502/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1517 + 2503/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1516 + 2504/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1515 + 2505/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1514 + 2506/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1513 + 2507/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1512 + 2508/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1511 + 2509/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1510 + 2510/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1509 + 2511/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1508 + 2512/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1507 + 2513/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1506 + 2514/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1505 + 2515/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1504 + 2516/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1503 + 2517/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1502 + 2518/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1501 + 2519/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1500 + 2520/3417: $6\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1499 + 2521/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1498 + 2522/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1497 + 2523/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1496 + 2524/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1495 + 2525/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1494 + 2526/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1493 + 2527/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1492 + 2528/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1491 + 2529/3417: $6\decision_deferred[0:0] + 2530/3417: $6\decision_ok[0:0] + 2531/3417: $6\decision_detail[7:0] + 2532/3417: $6\decision_fault[7:0] + 2533/3417: $15\write_value[127:0] + 2534/3417: $15\write_address[31:0] + 2535/3417: $6\retired_bytes[543:0] + 2536/3417: $6\solved_b[127:0] + 2537/3417: $6\solved_a[127:0] + 2538/3417: $6\result_value[127:0] + 2539/3417: $6\inv_value[127:0] + 2540/3417: $6\val_c[127:0] + 2541/3417: $6\val_b[127:0] + 2542/3417: $6\val_a[127:0] + 2543/3417: $6\taken_proposal[7:0] + 2544/3417: $6\inv_present[7:0] + 2545/3417: $6\pres_c[7:0] + 2546/3417: $6\pres_b[7:0] + 2547/3417: $6\pres_a[7:0] + 2548/3417: $6\profile[7:0] + 2549/3417: $13\deferred_local[31:0] + 2550/3417: $13\deferred_target[31:0] + 2551/3417: $6\proposed_fp[31:0] + 2552/3417: $6\proposed_pc[31:0] + 2553/3417: $6\base_index[31:0] + 2554/3417: $6\addr_c[31:0] + 2555/3417: $6\addr_b[31:0] + 2556/3417: $6\addr_a[31:0] + 2557/3417: $6\off_c[31:0] + 2558/3417: $6\off_b[31:0] + 2559/3417: $6\off_a[31:0] + 2560/3417: $6\fp[31:0] + 2561/3417: $6\pc[31:0] + 2562/3417: $6\txn_id[31:0] + 2563/3417: $13\n_deferred[31:0] + 2564/3417: $15\n_writes[31:0] + 2565/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1484 [543:40] + 2566/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1484 [31:0] + 2567/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1484 [39:32] + 2568/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1483 + 2569/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1479 [543:40] + 2570/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1479 [31:0] + 2571/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1479 [39:32] + 2572/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1478 + 2573/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1481 + 2574/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1480 + 2575/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1394 + 2576/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1393 + 2577/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1392 + 2578/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1391 + 2579/3417: $5\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1477 + 2580/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1476 + 2581/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1475 + 2582/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1474 + 2583/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1473 + 2584/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1472 + 2585/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1471 + 2586/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1470 + 2587/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1469 + 2588/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1468 + 2589/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1467 + 2590/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1466 + 2591/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1465 + 2592/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1464 + 2593/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1463 + 2594/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1462 + 2595/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1461 + 2596/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1460 + 2597/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1459 + 2598/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1458 + 2599/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1457 + 2600/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1456 + 2601/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1455 + 2602/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1454 + 2603/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1453 + 2604/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1452 + 2605/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1451 + 2606/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1450 + 2607/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1449 + 2608/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1448 + 2609/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1447 + 2610/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1446 + 2611/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1445 + 2612/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1444 + 2613/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1443 + 2614/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1442 + 2615/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1441 + 2616/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1440 + 2617/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1439 + 2618/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1438 + 2619/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1437 + 2620/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1436 + 2621/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1435 + 2622/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1434 + 2623/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1433 + 2624/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1432 + 2625/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1431 + 2626/3417: $5\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1430 + 2627/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1429 + 2628/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1428 + 2629/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1427 + 2630/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1426 + 2631/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1425 + 2632/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1424 + 2633/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1423 + 2634/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1422 + 2635/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1421 + 2636/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1420 + 2637/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1419 + 2638/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1418 + 2639/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1417 + 2640/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1416 + 2641/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1415 + 2642/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1414 + 2643/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1413 + 2644/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1412 + 2645/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1411 + 2646/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1410 + 2647/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1409 + 2648/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1408 + 2649/3417: $5\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1407 + 2650/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1406 + 2651/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1405 + 2652/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1404 + 2653/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1403 + 2654/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1402 + 2655/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1401 + 2656/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1400 + 2657/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1399 + 2658/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1398 + 2659/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1397 + 2660/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1396 + 2661/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1395 + 2662/3417: $5\decision_deferred[0:0] + 2663/3417: $5\decision_ok[0:0] + 2664/3417: $5\decision_detail[7:0] + 2665/3417: $5\decision_fault[7:0] + 2666/3417: $14\write_value[127:0] + 2667/3417: $14\write_address[31:0] + 2668/3417: $5\retired_bytes[543:0] + 2669/3417: $19\result_bytes[543:0] + 2670/3417: $5\solved_b[127:0] + 2671/3417: $5\solved_a[127:0] + 2672/3417: $5\result_value[127:0] + 2673/3417: $5\inv_value[127:0] + 2674/3417: $5\val_c[127:0] + 2675/3417: $5\val_b[127:0] + 2676/3417: $5\val_a[127:0] + 2677/3417: $5\taken_proposal[7:0] + 2678/3417: $5\inv_present[7:0] + 2679/3417: $5\pres_c[7:0] + 2680/3417: $5\pres_b[7:0] + 2681/3417: $5\pres_a[7:0] + 2682/3417: $5\profile[7:0] + 2683/3417: $12\deferred_local[31:0] + 2684/3417: $12\deferred_target[31:0] + 2685/3417: $5\next_fp_value[31:0] + 2686/3417: $5\next_pc_value[31:0] + 2687/3417: $5\proposed_fp[31:0] + 2688/3417: $5\proposed_pc[31:0] + 2689/3417: $5\base_index[31:0] + 2690/3417: $5\addr_c[31:0] + 2691/3417: $5\addr_b[31:0] + 2692/3417: $5\addr_a[31:0] + 2693/3417: $5\off_c[31:0] + 2694/3417: $5\off_b[31:0] + 2695/3417: $5\off_a[31:0] + 2696/3417: $5\fp[31:0] + 2697/3417: $5\pc[31:0] + 2698/3417: $5\txn_id[31:0] + 2699/3417: $19\result_length[31:0] + 2700/3417: $12\n_deferred[31:0] + 2701/3417: $14\n_writes[31:0] + 2702/3417: $18\result_length[31:0] + 2703/3417: $18\result_bytes[215:152] [63:32] + 2704/3417: $18\result_bytes[215:152] [31:0] + 2705/3417: $17\result_bytes[279:104] [111:80] + 2706/3417: $17\result_bytes[279:104] [47:40] + 2707/3417: $17\result_bytes[279:104] [15:8] + 2708/3417: $17\result_bytes[279:104] [143:112] + 2709/3417: $17\result_length[31:0] + 2710/3417: $17\result_bytes[279:104] [79:72] + 2711/3417: $17\result_bytes[279:104] [71:48] + 2712/3417: $17\result_bytes[279:104] [39:16] + 2713/3417: $17\result_bytes[279:104] [175:144] + 2714/3417: $17\result_bytes[279:104] [7:0] + 2715/3417: $15\result_bytes[375:104] [175:168] + 2716/3417: $16\result_bytes[375:312] [63:32] + 2717/3417: $16\result_bytes[375:312] [31:0] + 2718/3417: $15\result_bytes[375:104] [207:176] + 2719/3417: $15\result_length[31:0] + 2720/3417: $16\result_length[31:0] + 2721/3417: $15\result_bytes[375:104] [167:160] + 2722/3417: $15\result_bytes[375:104] [159:32] + 2723/3417: $15\result_bytes[375:104] [31:0] + 2724/3417: $15\result_bytes[375:104] [271:208] + 2725/3417: $13\write_value[127:0] + 2726/3417: $13\write_address[31:0] + 2727/3417: $13\n_writes[31:0] + 2728/3417: $14\result_bytes[543:0] [375:104] + 2729/3417: $14\result_bytes[543:0] [103:96] + 2730/3417: $14\result_bytes[543:0] [95:64] + 2731/3417: $14\result_bytes[543:0] [63:32] + 2732/3417: $14\result_bytes[543:0] [31:0] + 2733/3417: $14\result_bytes[543:0] [543:376] + 2734/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1385 [31:0] + 2735/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1385 [39:32] + 2736/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1384 + 2737/3417: $12\write_value[127:0] + 2738/3417: $12\write_address[31:0] + 2739/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1385 [543:40] + 2740/3417: $14\result_length[31:0] + 2741/3417: $12\n_writes[31:0] + 2742/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1379 [543:40] + 2743/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1379 [31:0] + 2744/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1379 [39:32] + 2745/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$1378 + 2746/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1381 + 2747/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1380 + 2748/3417: $11\write_value[127:0] + 2749/3417: $11\write_address[31:0] + 2750/3417: $13\result_bytes[543:0] + 2751/3417: $13\result_length[31:0] + 2752/3417: $11\n_writes[31:0] + 2753/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1290 + 2754/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1289 + 2755/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1288 + 2756/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$1287 + 2757/3417: $10\write_value[127:0] + 2758/3417: $10\write_address[31:0] + 2759/3417: $12\result_bytes[543:0] + 2760/3417: $12\result_length[31:0] + 2761/3417: $10\n_writes[31:0] + 2762/3417: $4\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1377 + 2763/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1376 + 2764/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1375 + 2765/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1374 + 2766/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1373 + 2767/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1372 + 2768/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1371 + 2769/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1370 + 2770/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1369 + 2771/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1368 + 2772/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1367 + 2773/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1366 + 2774/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1365 + 2775/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1364 + 2776/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1363 + 2777/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1362 + 2778/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1361 + 2779/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1360 + 2780/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1359 + 2781/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1358 + 2782/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1357 + 2783/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1356 + 2784/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1355 + 2785/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1354 + 2786/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1353 + 2787/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1352 + 2788/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1351 + 2789/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1350 + 2790/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1349 + 2791/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1348 + 2792/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1347 + 2793/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1346 + 2794/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1345 + 2795/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1344 + 2796/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1343 + 2797/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1342 + 2798/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1341 + 2799/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1340 + 2800/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1339 + 2801/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1338 + 2802/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1337 + 2803/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1336 + 2804/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1335 + 2805/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1334 + 2806/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1333 + 2807/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1332 + 2808/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1331 + 2809/3417: $4\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1330 + 2810/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1329 + 2811/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1328 + 2812/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1327 + 2813/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1326 + 2814/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1325 + 2815/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1324 + 2816/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1323 + 2817/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1322 + 2818/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1321 + 2819/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1320 + 2820/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1319 + 2821/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1318 + 2822/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1317 + 2823/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1316 + 2824/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1315 + 2825/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1314 + 2826/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1313 + 2827/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1312 + 2828/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1311 + 2829/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1310 + 2830/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1309 + 2831/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1308 + 2832/3417: $4\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1307 + 2833/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1306 + 2834/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1305 + 2835/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1304 + 2836/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1303 + 2837/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1302 + 2838/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1301 + 2839/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1300 + 2840/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1299 + 2841/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1298 + 2842/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1297 + 2843/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1296 + 2844/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1295 + 2845/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1294 + 2846/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1293 + 2847/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1292 + 2848/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1291 + 2849/3417: $4\decision_deferred[0:0] + 2850/3417: $4\decision_ok[0:0] + 2851/3417: $4\decision_detail[7:0] + 2852/3417: $4\decision_fault[7:0] + 2853/3417: $4\retired_bytes[543:0] + 2854/3417: $4\solved_b[127:0] + 2855/3417: $4\solved_a[127:0] + 2856/3417: $4\result_value[127:0] + 2857/3417: $4\inv_value[127:0] + 2858/3417: $4\val_c[127:0] + 2859/3417: $4\val_b[127:0] + 2860/3417: $4\val_a[127:0] + 2861/3417: $4\taken_proposal[7:0] + 2862/3417: $4\inv_present[7:0] + 2863/3417: $4\pres_c[7:0] + 2864/3417: $4\pres_b[7:0] + 2865/3417: $4\pres_a[7:0] + 2866/3417: $4\profile[7:0] + 2867/3417: $11\deferred_local[31:0] + 2868/3417: $11\deferred_target[31:0] + 2869/3417: $4\next_fp_value[31:0] + 2870/3417: $4\next_pc_value[31:0] + 2871/3417: $4\proposed_fp[31:0] + 2872/3417: $4\proposed_pc[31:0] + 2873/3417: $4\base_index[31:0] + 2874/3417: $4\addr_c[31:0] + 2875/3417: $4\addr_b[31:0] + 2876/3417: $4\addr_a[31:0] + 2877/3417: $4\off_c[31:0] + 2878/3417: $4\off_b[31:0] + 2879/3417: $4\off_a[31:0] + 2880/3417: $4\fp[31:0] + 2881/3417: $4\pc[31:0] + 2882/3417: $4\txn_id[31:0] + 2883/3417: $11\n_deferred[31:0] + 2884/3417: $11\result_length[31:0] + 2885/3417: $11\result_bytes[215:152] [63:32] + 2886/3417: $11\result_bytes[215:152] [31:0] + 2887/3417: $10\result_bytes[279:104] [111:80] + 2888/3417: $10\result_bytes[279:104] [47:40] + 2889/3417: $10\result_bytes[279:104] [15:8] + 2890/3417: $10\result_bytes[279:104] [143:112] + 2891/3417: $10\result_length[31:0] + 2892/3417: $10\result_bytes[279:104] [79:72] + 2893/3417: $10\result_bytes[279:104] [71:48] + 2894/3417: $10\result_bytes[279:104] [39:16] + 2895/3417: $10\result_bytes[279:104] [175:144] + 2896/3417: $10\result_bytes[279:104] [7:0] + 2897/3417: $8\result_bytes[375:104] [175:168] + 2898/3417: $9\result_bytes[375:312] [63:32] + 2899/3417: $9\result_bytes[375:312] [31:0] + 2900/3417: $8\result_bytes[375:104] [207:176] + 2901/3417: $8\result_length[31:0] + 2902/3417: $9\result_length[31:0] + 2903/3417: $8\result_bytes[375:104] [167:160] + 2904/3417: $8\result_bytes[375:104] [159:32] + 2905/3417: $8\result_bytes[375:104] [31:0] + 2906/3417: $8\result_bytes[375:104] [271:208] + 2907/3417: $10\deferred_local[31:0] + 2908/3417: $10\deferred_target[31:0] + 2909/3417: $10\n_deferred[31:0] + 2910/3417: $9\write_value[127:0] + 2911/3417: $9\write_address[31:0] + 2912/3417: $9\n_writes[31:0] + 2913/3417: $9\deferred_local[31:0] + 2914/3417: $9\deferred_target[31:0] + 2915/3417: $9\n_deferred[31:0] + 2916/3417: $8\write_value[127:0] + 2917/3417: $8\write_address[31:0] + 2918/3417: $8\n_writes[31:0] + 2919/3417: $8\deferred_local[31:0] + 2920/3417: $8\deferred_target[31:0] + 2921/3417: $8\n_deferred[31:0] + 2922/3417: $7\result_bytes[543:0] [375:104] + 2923/3417: $7\result_bytes[543:0] [103:96] + 2924/3417: $7\result_bytes[543:0] [95:64] + 2925/3417: $7\result_bytes[543:0] [63:32] + 2926/3417: $7\result_bytes[543:0] [31:0] + 2927/3417: $7\result_bytes[543:0] [543:376] + 2928/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1272 [31:0] + 2929/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1272 [39:32] + 2930/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1271 + 2931/3417: $7\write_value[127:0] + 2932/3417: $7\write_address[31:0] + 2933/3417: $7\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1272 [543:40] + 2934/3417: $7\deferred_local[31:0] + 2935/3417: $7\deferred_target[31:0] + 2936/3417: $7\result_length[31:0] + 2937/3417: $7\n_deferred[31:0] + 2938/3417: $7\n_writes[31:0] + 2939/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1265 [543:40] + 2940/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1265 [31:0] + 2941/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1265 [39:32] + 2942/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1264 + 2943/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1267 + 2944/3417: $6\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1266 + 2945/3417: $6\write_value[127:0] + 2946/3417: $6\write_address[31:0] + 2947/3417: $6\result_bytes[543:0] + 2948/3417: $6\deferred_local[31:0] + 2949/3417: $6\deferred_target[31:0] + 2950/3417: $6\result_length[31:0] + 2951/3417: $6\n_deferred[31:0] + 2952/3417: $6\n_writes[31:0] + 2953/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1260 + 2954/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1259 + 2955/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1258 + 2956/3417: $5\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1257 + 2957/3417: $5\write_value[127:0] + 2958/3417: $5\write_address[31:0] + 2959/3417: $5\result_bytes[543:0] + 2960/3417: $5\deferred_local[31:0] + 2961/3417: $5\deferred_target[31:0] + 2962/3417: $5\result_length[31:0] + 2963/3417: $5\n_deferred[31:0] + 2964/3417: $5\n_writes[31:0] + 2965/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1251 [543:40] + 2966/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1251 [31:0] + 2967/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1251 [39:32] + 2968/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn[31:0]$1250 + 2969/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1255 + 2970/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1254 + 2971/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1253 + 2972/3417: $4\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1252 + 2973/3417: $4\write_value[127:0] + 2974/3417: $4\write_address[31:0] + 2975/3417: $4\result_bytes[543:0] + 2976/3417: $4\deferred_local[31:0] + 2977/3417: $4\deferred_target[31:0] + 2978/3417: $4\result_length[31:0] + 2979/3417: $4\n_deferred[31:0] + 2980/3417: $4\n_writes[31:0] + 2981/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1156 + 2982/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1155 + 2983/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1154 + 2984/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1153 + 2985/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1152 + 2986/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn[31:0]$1151 + 2987/3417: $3\write_value[127:0] + 2988/3417: $3\write_address[31:0] + 2989/3417: $3\result_bytes[543:0] + 2990/3417: $3\deferred_local[31:0] + 2991/3417: $3\deferred_target[31:0] + 2992/3417: $3\result_length[31:0] + 2993/3417: $3\n_deferred[31:0] + 2994/3417: $3\n_writes[31:0] + 2995/3417: $3\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1247 + 2996/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1246 + 2997/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1245 + 2998/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1244 + 2999/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1243 + 3000/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1242 + 3001/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1241 + 3002/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1240 + 3003/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1239 + 3004/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1238 + 3005/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1237 + 3006/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1236 + 3007/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1235 + 3008/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1234 + 3009/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1233 + 3010/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1232 + 3011/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1231 + 3012/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1230 + 3013/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1229 + 3014/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1228 + 3015/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1227 + 3016/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1226 + 3017/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1225 + 3018/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1224 + 3019/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1223 + 3020/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1222 + 3021/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1221 + 3022/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1220 + 3023/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1219 + 3024/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1218 + 3025/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1217 + 3026/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1216 + 3027/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1215 + 3028/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1214 + 3029/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1213 + 3030/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1212 + 3031/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1211 + 3032/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1210 + 3033/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1209 + 3034/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1208 + 3035/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1207 + 3036/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1206 + 3037/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1205 + 3038/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1204 + 3039/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1203 + 3040/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1202 + 3041/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1201 + 3042/3417: $3\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1200 + 3043/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1199 + 3044/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1198 + 3045/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1197 + 3046/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1196 + 3047/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1195 + 3048/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1194 + 3049/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1193 + 3050/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1192 + 3051/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1191 + 3052/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1190 + 3053/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1189 + 3054/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1188 + 3055/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1187 + 3056/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1186 + 3057/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1185 + 3058/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1184 + 3059/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1183 + 3060/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1182 + 3061/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1181 + 3062/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1180 + 3063/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1179 + 3064/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1178 + 3065/3417: $3\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1177 + 3066/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1176 + 3067/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1175 + 3068/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1174 + 3069/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1173 + 3070/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1172 + 3071/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1171 + 3072/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1170 + 3073/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1169 + 3074/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1168 + 3075/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1167 + 3076/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1166 + 3077/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1165 + 3078/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1164 + 3079/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1163 + 3080/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1162 + 3081/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1161 + 3082/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1160 + 3083/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1159 + 3084/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1158 + 3085/3417: $3\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$1157 + 3086/3417: $3\decision_deferred[0:0] + 3087/3417: $3\decision_ok[0:0] + 3088/3417: $3\decision_detail[7:0] + 3089/3417: $3\decision_fault[7:0] + 3090/3417: $3\retired_bytes[543:0] + 3091/3417: $3\solved_b[127:0] + 3092/3417: $3\solved_a[127:0] + 3093/3417: $3\result_value[127:0] + 3094/3417: $3\inv_value[127:0] + 3095/3417: $3\val_c[127:0] + 3096/3417: $3\val_b[127:0] + 3097/3417: $3\val_a[127:0] + 3098/3417: $3\taken_proposal[7:0] + 3099/3417: $3\inv_present[7:0] + 3100/3417: $3\pres_c[7:0] + 3101/3417: $3\pres_b[7:0] + 3102/3417: $3\pres_a[7:0] + 3103/3417: $3\profile[7:0] + 3104/3417: $3\next_fp_value[31:0] + 3105/3417: $3\next_pc_value[31:0] + 3106/3417: $3\proposed_fp[31:0] + 3107/3417: $3\proposed_pc[31:0] + 3108/3417: $3\base_index[31:0] + 3109/3417: $3\addr_c[31:0] + 3110/3417: $3\addr_b[31:0] + 3111/3417: $3\addr_a[31:0] + 3112/3417: $3\off_c[31:0] + 3113/3417: $3\off_b[31:0] + 3114/3417: $3\off_a[31:0] + 3115/3417: $3\fp[31:0] + 3116/3417: $3\pc[31:0] + 3117/3417: $3\txn_id[31:0] + 3118/3417: $2\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1147 + 3119/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1146 + 3120/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1145 + 3121/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1144 + 3122/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1143 + 3123/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1142 + 3124/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1141 + 3125/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1140 + 3126/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1139 + 3127/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1138 + 3128/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1137 + 3129/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1136 + 3130/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1135 + 3131/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1134 + 3132/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1133 + 3133/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1132 + 3134/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1131 + 3135/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1130 + 3136/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1129 + 3137/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1128 + 3138/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1127 + 3139/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1126 + 3140/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1125 + 3141/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1124 + 3142/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1123 + 3143/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1122 + 3144/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1121 + 3145/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1120 + 3146/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1119 + 3147/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1118 + 3148/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1117 + 3149/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1116 + 3150/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1115 + 3151/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1114 + 3152/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1113 + 3153/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1112 + 3154/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1111 + 3155/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1110 + 3156/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1109 + 3157/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1108 + 3158/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1107 + 3159/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1106 + 3160/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1105 + 3161/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1104 + 3162/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1103 + 3163/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1102 + 3164/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1101 + 3165/3417: $2\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1100 + 3166/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1099 + 3167/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1098 + 3168/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1097 + 3169/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$1096 + 3170/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$1095 + 3171/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$1094 + 3172/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$1093 + 3173/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$1092 + 3174/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$1091 + 3175/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$1090 + 3176/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$1089 + 3177/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$1088 + 3178/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$1087 + 3179/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$1086 + 3180/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$1085 + 3181/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$1084 + 3182/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$1083 + 3183/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$1082 + 3184/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$1081 + 3185/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$1080 + 3186/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$1079 + 3187/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$1078 + 3188/3417: $2\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$1077 + 3189/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$1076 + 3190/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$1075 + 3191/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$1074 + 3192/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$1073 + 3193/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$1072 + 3194/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$1071 + 3195/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$1070 + 3196/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$1069 + 3197/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$1068 + 3198/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$1067 + 3199/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$1066 + 3200/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$1065 + 3201/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$1064 + 3202/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$1063 + 3203/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$1062 + 3204/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$1061 + 3205/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$1060 + 3206/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$1059 + 3207/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$1058 + 3208/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$1057 + 3209/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$1056 + 3210/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$1055 + 3211/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$1054 + 3212/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$1053 + 3213/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$1052 + 3214/3417: $2\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn[31:0]$1051 + 3215/3417: $2\decision_deferred[0:0] + 3216/3417: $2\decision_ok[0:0] + 3217/3417: $2\decision_detail[7:0] + 3218/3417: $2\decision_fault[7:0] + 3219/3417: $2\write_value[127:0] + 3220/3417: $2\write_address[31:0] + 3221/3417: $2\retired_bytes[543:0] + 3222/3417: $2\result_bytes[543:0] + 3223/3417: $2\solved_b[127:0] + 3224/3417: $2\solved_a[127:0] + 3225/3417: $2\result_value[127:0] + 3226/3417: $2\inv_value[127:0] + 3227/3417: $2\val_c[127:0] + 3228/3417: $2\val_b[127:0] + 3229/3417: $2\val_a[127:0] + 3230/3417: $2\taken_proposal[7:0] + 3231/3417: $2\inv_present[7:0] + 3232/3417: $2\pres_c[7:0] + 3233/3417: $2\pres_b[7:0] + 3234/3417: $2\pres_a[7:0] + 3235/3417: $2\profile[7:0] + 3236/3417: $2\deferred_local[31:0] + 3237/3417: $2\deferred_target[31:0] + 3238/3417: $2\next_fp_value[31:0] + 3239/3417: $2\next_pc_value[31:0] + 3240/3417: $2\proposed_fp[31:0] + 3241/3417: $2\proposed_pc[31:0] + 3242/3417: $2\base_index[31:0] + 3243/3417: $2\addr_c[31:0] + 3244/3417: $2\addr_b[31:0] + 3245/3417: $2\addr_a[31:0] + 3246/3417: $2\off_c[31:0] + 3247/3417: $2\off_b[31:0] + 3248/3417: $2\off_a[31:0] + 3249/3417: $2\fp[31:0] + 3250/3417: $2\pc[31:0] + 3251/3417: $2\txn_id[31:0] + 3252/3417: $2\result_length[31:0] + 3253/3417: $2\n_deferred[31:0] + 3254/3417: $2\n_writes[31:0] + 3255/3417: $0\done_pulse[0:0] + 3256/3417: $0\encoder_start[0:0] + 3257/3417: $0\alu_start[0:0] + 3258/3417: $0\tx_start[0:0] + 3259/3417: $1\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$1050 + 3260/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$1049 + 3261/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$1048 + 3262/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$1047 + 3263/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$1046 + 3264/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$1045 + 3265/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$1044 + 3266/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$1043 + 3267/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$1042 + 3268/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$1041 + 3269/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$1040 + 3270/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$1039 + 3271/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$1038 + 3272/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$1037 + 3273/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$1036 + 3274/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$1035 + 3275/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$1034 + 3276/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$1033 + 3277/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$1032 + 3278/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$1031 + 3279/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$1030 + 3280/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$1029 + 3281/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$1028 + 3282/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$1027 + 3283/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$1026 + 3284/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$1025 + 3285/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$1024 + 3286/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$1023 + 3287/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$1022 + 3288/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$1021 + 3289/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$1020 + 3290/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$1019 + 3291/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$1018 + 3292/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$1017 + 3293/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$1016 + 3294/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$1015 + 3295/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$1014 + 3296/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$1013 + 3297/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$1012 + 3298/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$1011 + 3299/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$1010 + 3300/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$1009 + 3301/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$1008 + 3302/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$1007 + 3303/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$1006 + 3304/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value[127:0]$1005 + 3305/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present[7:0]$1004 + 3306/3417: $1\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result[0:0]$1003 + 3307/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$1002 + 3308/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes[543:0]$1001 + 3309/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes[543:0]$1000 + 3310/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn[31:0]$999 + 3311/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes[543:0]$998 + 3312/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes[543:0]$997 + 3313/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail[7:0]$996 + 3314/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn[31:0]$995 + 3315/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes[543:0]$994 + 3316/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn[31:0]$993 + 3317/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes[543:0]$992 + 3318/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes[543:0]$991 + 3319/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes[543:0]$990 + 3320/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes[543:0]$989 + 3321/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes[543:0]$988 + 3322/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes[543:0]$987 + 3323/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes[543:0]$986 + 3324/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes[543:0]$985 + 3325/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail[7:0]$984 + 3326/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status[7:0]$983 + 3327/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes[543:0]$982 + 3328/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn[31:0]$981 + 3329/3417: $1\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product[127:0]$980 + 3330/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes[543:0]$979 + 3331/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn[31:0]$978 + 3332/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes[543:0]$977 + 3333/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn[31:0]$976 + 3334/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes[543:0]$975 + 3335/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn[31:0]$974 + 3336/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes[543:0]$973 + 3337/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn[31:0]$972 + 3338/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes[543:0]$971 + 3339/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn[31:0]$970 + 3340/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes[543:0]$969 + 3341/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn[31:0]$968 + 3342/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes[543:0]$967 + 3343/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn[31:0]$966 + 3344/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes[543:0]$965 + 3345/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn[31:0]$964 + 3346/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes[543:0]$963 + 3347/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn[31:0]$962 + 3348/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes[543:0]$961 + 3349/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn[31:0]$960 + 3350/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes[543:0]$959 + 3351/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn[31:0]$958 + 3352/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes[543:0]$957 + 3353/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn[31:0]$956 + 3354/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes[543:0]$955 + 3355/3417: $1\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn[31:0]$954 + 3356/3417: $1\decision_deferred[0:0] + 3357/3417: $1\decision_ok[0:0] + 3358/3417: $1\decision_detail[7:0] + 3359/3417: $1\decision_fault[7:0] + 3360/3417: $1\write_value[127:0] + 3361/3417: $1\write_address[31:0] + 3362/3417: $1\retired_bytes[543:0] + 3363/3417: $1\result_bytes[543:0] + 3364/3417: $1\solved_b[127:0] + 3365/3417: $1\solved_a[127:0] + 3366/3417: $1\result_value[127:0] + 3367/3417: $1\inv_value[127:0] + 3368/3417: $1\val_c[127:0] + 3369/3417: $1\val_b[127:0] + 3370/3417: $1\val_a[127:0] + 3371/3417: $1\taken_proposal[7:0] + 3372/3417: $1\inv_present[7:0] + 3373/3417: $1\pres_c[7:0] + 3374/3417: $1\pres_b[7:0] + 3375/3417: $1\pres_a[7:0] + 3376/3417: $1\profile[7:0] + 3377/3417: $1\deferred_local[31:0] + 3378/3417: $1\deferred_target[31:0] + 3379/3417: $1\next_fp_value[31:0] + 3380/3417: $1\next_pc_value[31:0] + 3381/3417: $1\proposed_fp[31:0] + 3382/3417: $1\proposed_pc[31:0] + 3383/3417: $1\base_index[31:0] + 3384/3417: $1\addr_c[31:0] + 3385/3417: $1\addr_b[31:0] + 3386/3417: $1\addr_a[31:0] + 3387/3417: $1\off_c[31:0] + 3388/3417: $1\off_b[31:0] + 3389/3417: $1\off_a[31:0] + 3390/3417: $1\fp[31:0] + 3391/3417: $1\pc[31:0] + 3392/3417: $1\txn_id[31:0] + 3393/3417: $1\result_length[31:0] + 3394/3417: $1\n_deferred[31:0] + 3395/3417: $1\n_writes[31:0] + 3396/3417: $0\last_fault[7:0] + 3397/3417: $0\last_status[7:0] + 3398/3417: $0\active_profile[7:0] + 3399/3417: $0\retire_seq[31:0] + 3400/3417: $0\committed_fp[31:0] + 3401/3417: $0\committed_pc[31:0] + 3402/3417: $0\state_valid[0:0] + 3403/3417: $0\staged_result_crc[31:0] + 3404/3417: $0\staged_next_fp[31:0] + 3405/3417: $0\staged_next_pc[31:0] + 3406/3417: $0\staged_txn_id[31:0] + 3407/3417: $0\result_pending[0:0] + 3408/3417: $0\encoder_index[15:0] + 3409/3417: $0\alu_operand_b[127:0] + 3410/3417: $0\alu_operand_a[127:0] + 3411/3417: $0\alu_operation[7:0] + 3412/3417: $0\compute_state[3:0] + 3413/3417: $0\capture_result_crc[0:0] + 3414/3417: $0\tx_payload[543:0] + 3415/3417: $0\tx_length[15:0] + 3416/3417: $0\tx_status[7:0] + 3417/3417: $0\fault[0:0] +Creating decoders for process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + 1/19: $3\next_accumulator[127:0] + 2/19: $3\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.$result[127:0]$767 + 3/19: $3\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.value[127:0]$768 + 4/19: $2\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.value[127:0]$765 + 5/19: $2\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.$result[127:0]$764 + 6/19: $2\next_accumulator[127:0] + 7/19: $0\multiply_start[0:0] + 8/19: $0\done_pulse[0:0] + 9/19: $1\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.value[127:0]$761 + 10/19: $1\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.$result[127:0]$760 + 11/19: $1\next_accumulator[127:0] + 12/19: $0\saved_index[15:0] + 13/19: $0\bit_index[4:0] + 14/19: $0\result[127:0] + 15/19: $0\operand_b[127:0] + 16/19: $0\operand_a[127:0] + 17/19: $0\fault[0:0] + 18/19: $0\accumulator[127:0] + 19/19: $0\busy[0:0] +Creating decoders for process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + 1/38: $6$lookahead\result$670[127:0]$738 + 2/38: $4$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638[127:0]$736 + 3/38: $4$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637[127:0]$735 + 4/38: $4$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639[31:0]$737 + 5/38: $5$lookahead\result$670[127:0]$712 + 6/38: $4$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635[127:0]$710 + 7/38: $4$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634[127:0]$709 + 8/38: $4$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636[31:0]$711 + 9/38: $4$lookahead\result$670[127:0]$703 + 10/38: $3$lookahead\result$670[127:0]$702 + 11/38: $3$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639[31:0]$701 + 12/38: $3$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638[127:0]$700 + 13/38: $3$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637[127:0]$699 + 14/38: $3$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636[31:0]$698 + 15/38: $3$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635[127:0]$697 + 16/38: $3$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634[127:0]$696 + 17/38: $2$lookahead\result$670[127:0]$693 + 18/38: $2$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639[31:0]$692 + 19/38: $2$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638[127:0]$691 + 20/38: $2$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637[127:0]$690 + 21/38: $2$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636[31:0]$689 + 22/38: $2$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635[127:0]$688 + 23/38: $2$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634[127:0]$687 + 24/38: $0\done_pulse[0:0] + 25/38: $1$lookahead\result$670[127:0]$686 + 26/38: $1$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639[31:0]$685 + 27/38: $1$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638[127:0]$684 + 28/38: $1$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637[127:0]$683 + 29/38: $1$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636[31:0]$682 + 30/38: $1$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635[127:0]$681 + 31/38: $1$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634[127:0]$680 + 32/38: $0\result_index[4:0] + 33/38: $0\payload_index[5:0] + 34/38: $0\saved_b[127:0] + 35/38: $0\saved_a[127:0] + 36/38: $0\saved_operation[7:0] + 37/38: $0\fault[0:0] + 38/38: $0\state[2:0] +Creating decoders for process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. + 1/9: $6\core_rx_data[7:0] + 2/9: $5\core_rx_data[7:0] + 3/9: $4\core_rx_data[7:0] + 4/9: $3\core_rx_data[7:0] + 5/9: $3\core_rx_valid[0:0] + 6/9: $2\core_rx_data[7:0] + 7/9: $2\core_rx_valid[0:0] + 8/9: $1\core_rx_data[7:0] + 9/9: $1\core_rx_valid[0:0] +Creating decoders for process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + 1/5: $0\scratch_byte[7:0] [7:1] + 2/5: $0\scratch_byte[7:0] [0] + 3/5: $0\byte_index[3:0] + 4/5: $0\fault[0:0] + 5/5: $0\state[3:0] +Creating decoders for process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. + 1/13: $2\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.$result[7:0]$585 + 2/13: $2\rx_ready[0:0] + 3/13: $2\tx_data[7:0] + 4/13: $2\tx_valid[0:0] + 5/13: $1\rx_ready[0:0] + 6/13: $1\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.index[3:0]$580 + 7/13: $1\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.$result[7:0]$579 + 8/13: $1\mul_result_shift[0:0] + 9/13: $1\mul_bit_value[0:0] + 10/13: $1\mul_bit_valid[0:0] + 11/13: $1\mul_a_valid[0:0] + 12/13: $1\tx_valid[0:0] + 13/13: $1\tx_data[7:0] +Creating decoders for process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + 1/30: $5\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.$result[127:0]$3207 + 2/30: $5\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.carry[0:0]$3209 + 3/30: $5\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.value[127:0]$3208 + 4/30: $4\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.carry[0:0]$3205 + 5/30: $4\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.value[127:0]$3204 + 6/30: $4\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.$result[127:0]$3203 + 7/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.next_value[127:0]$3198 [127:120] + 8/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.next_value[127:0]$3198 [119:0] + 9/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.$result[127:0]$3195 + 10/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.byte_value[7:0]$3197 + 11/30: $3\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.value[127:0]$3196 + 12/30: $3\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.carry[0:0]$3201 + 13/30: $3\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.value[127:0]$3200 + 14/30: $3\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.$result[127:0]$3199 + 15/30: $2\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.carry[0:0]$3194 + 16/30: $2\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.value[127:0]$3193 + 17/30: $2\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.$result[127:0]$3192 + 18/30: $2\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.next_value[127:0]$3191 + 19/30: $2\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.byte_value[7:0]$3190 + 20/30: $2\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.value[127:0]$3189 + 21/30: $2\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.$result[127:0]$3188 + 22/30: $1\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.carry[0:0]$3187 + 23/30: $1\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.value[127:0]$3186 + 24/30: $1\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.$result[127:0]$3185 + 25/30: $1\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.next_value[127:0]$3184 + 26/30: $1\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.byte_value[7:0]$3183 + 27/30: $1\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.value[127:0]$3182 + 28/30: $1\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.$result[127:0]$3181 + 29/30: $0\accumulator[127:0] + 30/30: $0\a_shift[127:0] +Creating decoders for process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + 1/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$445 + 2/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$448 + 3/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$449 + 4/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$447 + 5/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$446 + 6/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$440 + 7/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$443 + 8/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$444 + 9/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$442 + 10/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$441 + 11/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$400 + 12/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$403 + 13/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$404 + 14/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$402 + 15/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$401 + 16/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$365 + 17/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$364 + 18/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$363 + 19/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$362 + 20/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$361 + 21/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$360 + 22/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$359 + 23/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$358 + 24/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$357 + 25/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$356 + 26/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$355 + 27/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$354 + 28/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$353 + 29/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$352 + 30/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$351 + 31/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result[31:0]$346 + 32/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index[31:0]$349 + 33/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work[31:0]$350 + 34/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data[7:0]$348 + 35/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in[31:0]$347 + 36/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$343 + 37/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$342 + 38/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$341 + 39/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$340 + 40/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$339 + 41/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$338 + 42/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$337 + 43/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$336 + 44/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$335 + 45/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$334 + 46/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$333 + 47/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$332 + 48/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$331 + 49/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$330 + 50/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$329 + 51/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work[31:0]$328 + 52/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index[31:0]$327 + 53/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data[7:0]$326 + 54/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in[31:0]$325 + 55/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result[31:0]$324 + 56/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$322 + 57/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$321 + 58/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$320 + 59/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$319 + 60/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$318 + 61/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$317 + 62/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$316 + 63/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$315 + 64/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$314 + 65/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$313 + 66/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$312 + 67/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$311 + 68/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$310 + 69/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$309 + 70/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$308 + 71/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work[31:0]$307 + 72/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index[31:0]$306 + 73/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data[7:0]$305 + 74/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in[31:0]$304 + 75/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result[31:0]$303 + 76/105: $0\done_pulse[0:0] + 77/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work[31:0]$300 + 78/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index[31:0]$299 + 79/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data[7:0]$298 + 80/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in[31:0]$297 + 81/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result[31:0]$296 + 82/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work[31:0]$295 + 83/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index[31:0]$294 + 84/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data[7:0]$293 + 85/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in[31:0]$292 + 86/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result[31:0]$291 + 87/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work[31:0]$290 + 88/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index[31:0]$289 + 89/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data[7:0]$288 + 90/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in[31:0]$287 + 91/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result[31:0]$286 + 92/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work[31:0]$285 + 93/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index[31:0]$284 + 94/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data[7:0]$283 + 95/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in[31:0]$282 + 96/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result[31:0]$281 + 97/105: $0\payload_crc_work[31:0] + 98/105: $0\envelope_crc_work[31:0] + 99/105: $0\saved_crc[31:0] + 100/105: $0\saved_payload[543:0] + 101/105: $0\saved_status[7:0] + 102/105: $0\saved_length[15:0] + 103/105: $0\index[15:0] + 104/105: $0\active[0:0] + 105/105: $0\payload_crc[31:0] +Creating decoders for process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:44$244'. + 1/7: $7\tx_data[7:0] + 2/7: $6\tx_data[7:0] + 3/7: $5\tx_data[7:0] + 4/7: $4\tx_data[7:0] + 5/7: $3\tx_data[7:0] + 6/7: $2\tx_data[7:0] + 7/7: $1\tx_data[7:0] +Creating decoders for process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + 1/89: $0\received_crc[31:0] [31:24] + 2/89: $0\received_crc[31:0] [23:16] + 3/89: $0\received_crc[31:0] [15:8] + 4/89: $0\received_crc[31:0] [7:0] + 5/89: $5$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$185 + 6/89: $5$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$184 + 7/89: $5$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$186 + 8/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result[31:0]$177 + 9/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index[31:0]$180 + 10/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work[31:0]$181 + 11/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data[7:0]$179 + 12/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in[31:0]$178 + 13/89: $4$lookahead\frame_payload$22[2047:0]$182 + 14/89: $4$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$176 + 15/89: $4$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$175 + 16/89: $4$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$174 + 17/89: $0\declared_length[15:0] [15:8] + 18/89: $0\declared_length[15:0] [7:0] + 19/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index[31:0]$103 + 20/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data[7:0]$102 + 21/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result[31:0]$101 + 22/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work[31:0]$85 + 23/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index[31:0]$84 + 24/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data[7:0]$83 + 25/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result[31:0]$82 + 26/89: $3$lookahead\frame_payload$22[2047:0]$99 + 27/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work[31:0]$98 + 28/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index[31:0]$97 + 29/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data[7:0]$96 + 30/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in[31:0]$95 + 31/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result[31:0]$94 + 32/89: $3$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$93 + 33/89: $3$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$92 + 34/89: $3$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$91 + 35/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.work[31:0]$90 + 36/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.bit_index[31:0]$89 + 37/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.data[7:0]$88 + 38/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.crc_in[31:0]$87 + 39/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.$result[31:0]$86 + 40/89: $2$lookahead\frame_payload$22[2047:0]$81 + 41/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work[31:0]$80 + 42/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index[31:0]$79 + 43/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data[7:0]$78 + 44/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in[31:0]$77 + 45/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result[31:0]$76 + 46/89: $2$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$75 + 47/89: $2$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$74 + 48/89: $2$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$73 + 49/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.work[31:0]$72 + 50/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.bit_index[31:0]$71 + 51/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.data[7:0]$70 + 52/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.crc_in[31:0]$69 + 53/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.$result[31:0]$68 + 54/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work[31:0]$67 + 55/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index[31:0]$66 + 56/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data[7:0]$65 + 57/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result[31:0]$64 + 58/89: $1$lookahead\frame_payload$22[2047:0]$61 + 59/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work[31:0]$60 + 60/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index[31:0]$59 + 61/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data[7:0]$58 + 62/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in[31:0]$57 + 63/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result[31:0]$56 + 64/89: $1$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8[31:0]$55 + 65/89: $1$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7[2047:0]$54 + 66/89: $1$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6[2047:0]$53 + 67/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.work[31:0]$52 + 68/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.bit_index[31:0]$51 + 69/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.data[7:0]$50 + 70/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.crc_in[31:0]$49 + 71/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.$result[31:0]$48 + 72/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work[31:0]$47 + 73/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index[31:0]$46 + 74/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data[7:0]$45 + 75/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result[31:0]$44 + 76/89: $5$lookahead\frame_payload$22[2047:0]$187 + 77/89: $0\crc[31:0] + 78/89: $0\flags[7:0] + 79/89: $0\opcode[7:0] + 80/89: $0\version[7:0] + 81/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work[31:0]$104 + 82/89: $0\body_index[15:0] + 83/89: $0\header_index[2:0] + 84/89: $0\state[2:0] + 85/89: $0\fault_status[7:0] + 86/89: $0\fault_valid[0:0] + 87/89: $0\frame_length[15:0] + 88/89: $0\frame_opcode[7:0] + 89/89: $0\frame_valid[0:0] + +10.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\lsc1_stream_adapter.\core_rx_data' from process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. +No latch inferred for signal `\lsc1_stream_adapter.\core_rx_valid' from process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. +No latch inferred for signal `\leanvm_b_stream_alu.\rx_ready' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\tx_data' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\tx_valid' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_a_valid' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_valid' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_value' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_result_shift' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.$result' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\leanvm_b_stream_alu.\status_byte$func$asic_core/rtl/leanvm_b_stream_alu.sv:186$568.index' from process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +No latch inferred for signal `\lsc1_packet_tx.\tx_data' from process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:44$244'. + +10.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\lsc1_packet_frontend.\done_pulse' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146100' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\fault' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146101' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_start' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146102' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_status' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146103' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_length' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146104' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\tx_payload' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146105' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\capture_result_crc' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146106' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\compute_state' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146107' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_start' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146108' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_operation' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146109' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_operand_a' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146110' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\alu_operand_b' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146111' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\encoder_start' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146112' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\encoder_index' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146113' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_pending' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146114' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_txn_id' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146115' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_next_pc' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146116' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_next_fp' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146117' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\staged_result_crc' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146118' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\state_valid' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146119' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\committed_pc' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146120' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\committed_fp' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146121' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\retire_seq' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146122' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\active_profile' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146123' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\last_status' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146124' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\last_fault' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146125' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\n_writes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146126' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\n_deferred' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146127' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_length' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146128' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\txn_id' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146129' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pc' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146130' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\fp' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146131' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\off_a' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146132' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\off_b' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146133' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\off_c' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146134' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\addr_a' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146135' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\addr_b' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146136' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\addr_c' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146137' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\base_index' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146138' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\proposed_pc' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146139' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\proposed_fp' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146140' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\next_pc_value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146141' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\next_fp_value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146142' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\deferred_target' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146143' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\deferred_local' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146144' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\profile' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146145' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pres_a' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146146' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pres_b' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146147' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\pres_c' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146148' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\inv_present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146149' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\taken_proposal' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146150' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\val_a' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146151' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\val_b' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146152' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\val_c' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146153' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\inv_value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146154' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146155' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\solved_a' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146156' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\solved_b' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146157' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\result_bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146158' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\retired_bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146159' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\write_address' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146160' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\write_value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146161' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_fault' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146162' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_detail' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146163' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_ok' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146164' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\decision_deferred' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146165' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146166' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:237$776.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146167' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146168' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:241$777.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146169' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146170' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:243$778.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146171' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146172' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:323$780.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146173' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146174' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:325$781.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146175' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146176' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:337$783.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146177' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146178' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:340$784.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146179' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146180' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:349$785.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146181' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146182' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:351$786.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146183' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146184' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:360$788.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146185' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146186' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:369$789.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146187' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146188' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:388$791.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146189' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146190' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:410$792.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146191' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\finish_binary$func$asic_core/rtl/lsc1_packet_frontend.sv:412$793.product' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146192' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146193' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:220$794.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146194' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.status' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146195' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.detail' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146196' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:416$796.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146197' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:420$797.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146198' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:440$798.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146199' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:442$799.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146200' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:444$800.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146201' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:447$801.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146202' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:451$802.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146203' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:472$803.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146204' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146205' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:474$804.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146206' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146207' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.detail' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146208' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:478$805.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146209' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:506$806.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146210' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146211' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:514$807.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146212' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:519$808.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146213' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146214' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146215' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146216' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:523$810.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146217' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146218' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146219' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146220' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146221' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146222' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146223' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146224' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146225' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146226' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146227' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146228' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146229' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146230' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146231' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146232' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146233' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146234' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146235' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146236' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146237' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146238' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146239' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146240' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146241' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146242' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146243' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146244' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146245' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146246' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146247' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146248' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146249' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146250' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146251' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146252' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146253' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146254' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146255' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146256' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146257' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146258' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146259' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146260' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146261' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend.\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count' using process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + created $dff cell `$procdff$146262' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\busy' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146263' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\done_pulse' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146264' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\accumulator' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146265' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\fault' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146266' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\operand_a' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146267' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\operand_b' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146268' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\result' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146269' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\multiply_start' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146270' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\bit_index' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146271' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\saved_index' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146272' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\next_accumulator' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146273' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.$result' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146274' with positive edge clock. +Creating register for signal `\lsc1_field_encoder.\field_xtime$func$asic_core/rtl/lsc1_field_encoder.sv:64$754.value' using process `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. + created $dff cell `$procdff$146275' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\state' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146276' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\done_pulse' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146277' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\fault' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146278' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\result' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146279' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_operation' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146280' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_a' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146281' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\saved_b' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146282' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\payload_index' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146283' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.\result_index' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146284' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:138$634' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146285' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:138$635' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146286' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:138$636' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146287' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$mask$asic_core/rtl/lsc1_stream_adapter.sv:160$637' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146288' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$data$asic_core/rtl/lsc1_stream_adapter.sv:160$638' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146289' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$bitselwrite$sel$asic_core/rtl/lsc1_stream_adapter.sv:160$639' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146290' with positive edge clock. +Creating register for signal `\lsc1_stream_adapter.$lookahead\result$670' using process `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. + created $dff cell `$procdff$146291' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\state' using process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + created $dff cell `$procdff$146292' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\fault' using process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + created $dff cell `$procdff$146293' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\byte_index' using process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + created $dff cell `$procdff$146294' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\scratch_byte' using process `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. + created $dff cell `$procdff$146295' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\a_shift' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + created $dff cell `$procdff$146296' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\accumulator' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + created $dff cell `$procdff$146297' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.$result' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + created $dff cell `$procdff$146298' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + created $dff cell `$procdff$146299' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.byte_value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + created $dff cell `$procdff$146300' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$asic_core/rtl/gf2n_mul_bitstream.sv:80$3168.next_value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + created $dff cell `$procdff$146301' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.$result' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + created $dff cell `$procdff$146302' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + created $dff cell `$procdff$146303' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$asic_core/rtl/gf2n_mul_bitstream.sv:86$3169.carry' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. + created $dff cell `$procdff$146304' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\done_pulse' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146305' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146306' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\active' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146307' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146308' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_length' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146309' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_status' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146310' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_payload' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146311' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_crc' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146312' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\envelope_crc_work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146313' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc_work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146314' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146315' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146316' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146317' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146318' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:87$240.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146319' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146320' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146321' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146322' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146323' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:89$241.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146324' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146325' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146326' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146327' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146328' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:91$242.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146329' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146330' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146331' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146332' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146333' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:93$243.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. + created $dff cell `$procdff$146334' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146335' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146336' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146337' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_payload' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146338' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146339' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_status' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146340' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\state' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146341' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\header_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146342' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\body_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146343' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\declared_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146344' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\version' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146345' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146346' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\flags' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146347' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146348' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\received_crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146349' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146350' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146351' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146352' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:98$3.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146353' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146354' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146355' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146356' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146357' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:104$4.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146358' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:127$6' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146359' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:127$7' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146360' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:127$8' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146361' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146362' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146363' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146364' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146365' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:128$9.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146366' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$lookahead\frame_payload$22' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. + created $dff cell `$procdff$146367' with positive edge clock. + +10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 110 empty switches in `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. +Removing empty process `lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. +Found and cleaned up 5 empty switches in `\lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. +Removing empty process `lsc1_field_encoder.$proc$asic_core/rtl/lsc1_field_encoder.sv:38$755'. +Found and cleaned up 14 empty switches in `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. +Removing empty process `lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671'. +Found and cleaned up 6 empty switches in `\lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. +Removing empty process `lsc1_stream_adapter.$proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646'. +Found and cleaned up 23 empty switches in `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. +Removing empty process `leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615'. +Found and cleaned up 3 empty switches in `\leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +Removing empty process `leanvm_b_stream_alu.$proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576'. +Found and cleaned up 7 empty switches in `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. +Removing empty process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. +Removing empty process `lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:62$258'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:44$244'. +Removing empty process `lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:44$244'. +Found and cleaned up 14 empty switches in `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. +Removing empty process `lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:62$23'. +Cleaned up 196 empty switches. + +10.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend. + +Optimizing module lsc1_field_encoder. + +Optimizing module lsc1_stream_adapter. + +Optimizing module leanvm_b_stream_alu. + +Optimizing module gf128_mul_bitstream. +Optimizing module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. + +Optimizing module lsc1_packet_tx. + +Optimizing module lsc1_packet_rx. + + +11. Executing MEMORY pass. + +11.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +11.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +11.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +11.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +11.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +11.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend.. +Finding unused cells or wires in module \lsc1_field_encoder.. +Finding unused cells or wires in module \lsc1_stream_adapter.. +Finding unused cells or wires in module \leanvm_b_stream_alu.. +Finding unused cells or wires in module \gf128_mul_bitstream.. +Finding unused cells or wires in module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.. +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 27897 unused cells and 79317 unused wires. + + +11.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +11.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +11.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.. +Finding unused cells or wires in module \gf128_mul_bitstream.. +Finding unused cells or wires in module \leanvm_b_stream_alu.. +Finding unused cells or wires in module \lsc1_field_encoder.. +Finding unused cells or wires in module \lsc1_packet_frontend.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_stream_adapter.. + +11.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +11.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +12. Executing FLATTEN pass (flatten design). +Deleting now unused module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Deleting now unused module gf128_mul_bitstream. +Deleting now unused module leanvm_b_stream_alu. +Deleting now unused module lsc1_field_encoder. +Deleting now unused module lsc1_packet_rx. +Deleting now unused module lsc1_packet_tx. +Deleting now unused module lsc1_stream_adapter. + + +13. Executing OPT pass (performing simple optimizations). + +13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend. + + +13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend'. + +Removed a total of 520 cells. + +13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port A of cell $procmux$141326: \result_pending -> 1'0 + Replacing known input bits on port B of cell $procmux$141293: \result_pending -> 1'1 + Replacing known input bits on port B of cell $procmux$141290: \result_pending -> 1'0 + Replacing known input bits on port A of cell $procmux$141287: \result_pending -> 1'0 + Replacing known input bits on port A of cell $procmux$9904: $28\decision_ok[0:0] -> 1'0 + Replacing known input bits on port A of cell $procmux$8735: $28\decision_ok[0:0] -> 1'1 + Analyzing evaluation results. + dead port 2/2 on $mux $flatten\adapter.$procmux$143546. + dead port 1/2 on $mux $flatten\adapter.$procmux$143567. + dead port 1/2 on $mux $flatten\adapter.$procmux$143570. + dead port 1/2 on $mux $flatten\adapter.$procmux$143576. + dead port 1/2 on $mux $flatten\adapter.$procmux$143582. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.\datapath.$procmux$143837. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.\datapath.$procmux$143801. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143077. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143080. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143083. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143126. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143129. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143132. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143181. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143184. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143187. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143195. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143198. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143261. + dead port 1/3 on $pmux $flatten\field_encoder.\multiplier.$procmux$143515. + dead port 2/3 on $pmux $flatten\field_encoder.\multiplier.$procmux$143515. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143518. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143521. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143524. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143531. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143533. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143536. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143539. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143546. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143549. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143552. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143558. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143561. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143567. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143570. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143576. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143582. + dead port 1/2 on $mux $flatten\adapter.$procmux$143539. + dead port 1/2 on $mux $flatten\adapter.$procmux$143536. + dead port 2/2 on $mux $flatten\adapter.$procmux$143533. + dead port 1/2 on $mux $flatten\receiver.$procmux$145811. + dead port 2/2 on $mux $flatten\receiver.$procmux$145808. + dead port 2/2 on $mux $flatten\receiver.$procmux$145806. + dead port 2/2 on $mux $flatten\receiver.$procmux$145804. + dead port 1/2 on $mux $flatten\receiver.$procmux$145640. + dead port 1/2 on $mux $flatten\receiver.$procmux$145512. + dead port 2/2 on $mux $flatten\receiver.$procmux$145509. + dead port 1/2 on $mux $flatten\receiver.$procmux$145353. + dead port 2/2 on $mux $flatten\receiver.$procmux$145350. + dead port 2/2 on $mux $flatten\receiver.$procmux$145348. + dead port 2/2 on $mux $flatten\adapter.$procmux$143531. + dead port 1/2 on $mux $flatten\adapter.$procmux$143561. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145167. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145161. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145158. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145152. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145149. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145146. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145140. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145137. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145134. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145131. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145125. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145122. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145119. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145116. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145113. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145107. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145104. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145101. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145098. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145095. + dead port 1/2 on $mux $flatten\transmitter.$procmux$145092. + dead port 1/2 on $mux $flatten\adapter.$procmux$143558. + dead port 1/2 on $mux $flatten\adapter.$procmux$143524. + dead port 1/2 on $mux $flatten\adapter.$procmux$143521. + dead port 2/2 on $mux $flatten\adapter.$procmux$143518. + dead port 2/2 on $mux $flatten\adapter.$procmux$143261. + dead port 2/2 on $mux $flatten\adapter.$procmux$143198. + dead port 2/2 on $mux $flatten\adapter.\datapath.$procmux$143801. + dead port 1/2 on $mux $flatten\adapter.$procmux$143195. + dead port 2/2 on $mux $flatten\adapter.\datapath.$procmux$143813. + dead port 1/2 on $mux $flatten\adapter.$procmux$143552. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.\datapath.$procmux$143825. + dead port 2/2 on $mux $flatten\adapter.\datapath.$procmux$143825. + dead port 1/2 on $mux $flatten\adapter.$procmux$143549. + dead port 2/2 on $mux $flatten\adapter.\datapath.$procmux$143837. + dead port 1/3 on $pmux $flatten\adapter.$procmux$143515. + dead port 2/3 on $pmux $flatten\adapter.$procmux$143515. + dead port 2/2 on $mux $flatten\adapter.$procmux$143187. + dead port 1/2 on $mux $flatten\adapter.$procmux$143184. + dead port 2/2 on $mux $flatten\adapter.$procmux$143181. + dead port 2/2 on $mux $flatten\adapter.$procmux$143132. + dead port 1/2 on $mux $flatten\adapter.$procmux$143129. + dead port 2/2 on $mux $flatten\adapter.$procmux$143126. + dead port 2/2 on $mux $flatten\adapter.$procmux$143083. + dead port 1/2 on $mux $flatten\adapter.$procmux$143080. + dead port 2/2 on $mux $flatten\adapter.$procmux$143077. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.\datapath.$procmux$143813. + dead port 1/2 on $mux $procmux$10000. + dead port 1/2 on $mux $procmux$10003. + dead port 1/2 on $mux $procmux$10006. + dead port 1/2 on $mux $procmux$10009. + dead port 1/2 on $mux $procmux$10012. + dead port 1/2 on $mux $procmux$10015. + dead port 1/2 on $mux $procmux$10018. + dead port 1/2 on $mux $procmux$10021. + dead port 1/2 on $mux $procmux$10024. + dead port 1/2 on $mux $procmux$10027. + dead port 1/2 on $mux $procmux$10030. + dead port 1/2 on $mux $procmux$10033. + dead port 1/2 on $mux $procmux$10036. + dead port 1/2 on $mux $procmux$10039. + dead port 1/2 on $mux $procmux$10042. + dead port 1/2 on $mux $procmux$10045. + dead port 1/2 on $mux $procmux$10048. + dead port 2/2 on $mux $procmux$10050. + dead port 1/2 on $mux $procmux$10053. + dead port 1/2 on $mux $procmux$10056. + dead port 1/2 on $mux $procmux$10059. + dead port 1/2 on $mux $procmux$10062. + dead port 1/2 on $mux $procmux$10065. + dead port 1/2 on $mux $procmux$10068. + dead port 1/2 on $mux $procmux$10071. + dead port 1/2 on $mux $procmux$10074. + dead port 1/2 on $mux $procmux$10077. + dead port 1/2 on $mux $procmux$10080. + dead port 1/2 on $mux $procmux$10083. + dead port 2/2 on $mux $procmux$10086. + dead port 1/2 on $mux $procmux$10093. + dead port 1/2 on $mux $procmux$10096. + dead port 1/2 on $mux $procmux$10099. + dead port 1/2 on $mux $procmux$10102. + dead port 1/2 on $mux $procmux$10105. + dead port 1/2 on $mux $procmux$10108. + dead port 1/2 on $mux $procmux$10111. + dead port 1/2 on $mux $procmux$10114. + dead port 1/2 on $mux $procmux$10117. + dead port 1/2 on $mux $procmux$10120. + dead port 1/2 on $mux $procmux$10123. + dead port 1/2 on $mux $procmux$10126. + dead port 1/2 on $mux $procmux$10129. + dead port 1/2 on $mux $procmux$10132. + dead port 1/2 on $mux $procmux$10135. + dead port 1/2 on $mux $procmux$10138. + dead port 1/2 on $mux $procmux$10141. + dead port 2/2 on $mux $procmux$10143. + dead port 1/2 on $mux $procmux$10146. + dead port 1/2 on $mux $procmux$10149. + dead port 1/2 on $mux $procmux$10152. + dead port 1/2 on $mux $procmux$10155. + dead port 1/2 on $mux $procmux$10158. + dead port 1/2 on $mux $procmux$10161. + dead port 1/2 on $mux $procmux$10164. + dead port 1/2 on $mux $procmux$10167. + dead port 1/2 on $mux $procmux$10170. + dead port 1/2 on $mux $procmux$10173. + dead port 1/2 on $mux $procmux$10176. + dead port 2/2 on $mux $procmux$10179. + dead port 1/2 on $mux $procmux$10186. + dead port 1/2 on $mux $procmux$10189. + dead port 1/2 on $mux $procmux$10192. + dead port 1/2 on $mux $procmux$10195. + dead port 1/2 on $mux $procmux$10198. + dead port 1/2 on $mux $procmux$10201. + dead port 1/2 on $mux $procmux$10204. + dead port 1/2 on $mux $procmux$10207. + dead port 1/2 on $mux $procmux$10210. + dead port 1/2 on $mux $procmux$10213. + dead port 1/2 on $mux $procmux$10216. + dead port 1/2 on $mux $procmux$10219. + dead port 1/2 on $mux $procmux$10222. + dead port 1/2 on $mux $procmux$10225. + dead port 1/2 on $mux $procmux$10228. + dead port 1/2 on $mux $procmux$10231. + dead port 1/2 on $mux $procmux$10234. + dead port 2/2 on $mux $procmux$10236. + dead port 1/2 on $mux $procmux$10239. + dead port 1/2 on $mux $procmux$10242. + dead port 1/2 on $mux $procmux$10245. + dead port 1/2 on $mux $procmux$10248. + dead port 1/2 on $mux $procmux$10251. + dead port 1/2 on $mux $procmux$10254. + dead port 1/2 on $mux $procmux$10257. + dead port 1/2 on $mux $procmux$10260. + dead port 1/2 on $mux $procmux$10263. + dead port 1/2 on $mux $procmux$10266. + dead port 1/2 on $mux $procmux$102672. + dead port 1/2 on $mux $procmux$102675. + dead port 1/2 on $mux $procmux$102678. + dead port 1/2 on $mux $procmux$102681. + dead port 1/2 on $mux $procmux$102684. + dead port 1/2 on $mux $procmux$102687. + dead port 1/2 on $mux $procmux$10269. + dead port 1/2 on $mux $procmux$102690. + dead port 1/2 on $mux $procmux$102693. + dead port 1/2 on $mux $procmux$102696. + dead port 1/2 on $mux $procmux$102699. + dead port 1/2 on $mux $procmux$102702. + dead port 2/2 on $mux $procmux$102705. + dead port 1/2 on $mux $procmux$102711. + dead port 1/2 on $mux $procmux$102714. + dead port 1/2 on $mux $procmux$102717. + dead port 2/2 on $mux $procmux$10272. + dead port 1/2 on $mux $procmux$102720. + dead port 1/2 on $mux $procmux$102723. + dead port 1/2 on $mux $procmux$102726. + dead port 1/2 on $mux $procmux$102729. + dead port 1/2 on $mux $procmux$102732. + dead port 1/2 on $mux $procmux$102735. + dead port 1/2 on $mux $procmux$102738. + dead port 1/2 on $mux $procmux$102741. + dead port 2/2 on $mux $procmux$102744. + dead port 1/2 on $mux $procmux$10279. + dead port 1/2 on $mux $procmux$10282. + dead port 1/2 on $mux $procmux$102828. + dead port 1/2 on $mux $procmux$102831. + dead port 1/2 on $mux $procmux$102834. + dead port 1/2 on $mux $procmux$102837. + dead port 1/2 on $mux $procmux$102840. + dead port 1/2 on $mux $procmux$102843. + dead port 1/2 on $mux $procmux$102846. + dead port 1/2 on $mux $procmux$102849. + dead port 1/2 on $mux $procmux$10285. + dead port 1/2 on $mux $procmux$102852. + dead port 1/2 on $mux $procmux$102855. + dead port 1/2 on $mux $procmux$102858. + dead port 2/2 on $mux $procmux$102861. + dead port 1/2 on $mux $procmux$102867. + dead port 1/2 on $mux $procmux$102870. + dead port 1/2 on $mux $procmux$102873. + dead port 1/2 on $mux $procmux$102876. + dead port 1/2 on $mux $procmux$102879. + dead port 1/2 on $mux $procmux$10288. + dead port 1/2 on $mux $procmux$102882. + dead port 1/2 on $mux $procmux$102885. + dead port 1/2 on $mux $procmux$102888. + dead port 1/2 on $mux $procmux$102891. + dead port 1/2 on $mux $procmux$102894. + dead port 1/2 on $mux $procmux$102897. + dead port 2/2 on $mux $procmux$102900. + dead port 1/2 on $mux $procmux$102906. + dead port 1/2 on $mux $procmux$102909. + dead port 1/2 on $mux $procmux$10291. + dead port 1/2 on $mux $procmux$102912. + dead port 1/2 on $mux $procmux$102915. + dead port 1/2 on $mux $procmux$102918. + dead port 1/2 on $mux $procmux$102921. + dead port 1/2 on $mux $procmux$102924. + dead port 1/2 on $mux $procmux$102927. + dead port 1/2 on $mux $procmux$102930. + dead port 1/2 on $mux $procmux$102933. + dead port 1/2 on $mux $procmux$102936. + dead port 2/2 on $mux $procmux$102939. + dead port 1/2 on $mux $procmux$10294. + dead port 1/2 on $mux $procmux$102945. + dead port 1/2 on $mux $procmux$102948. + dead port 1/2 on $mux $procmux$102951. + dead port 1/2 on $mux $procmux$102954. + dead port 1/2 on $mux $procmux$102957. + dead port 1/2 on $mux $procmux$102960. + dead port 1/2 on $mux $procmux$102963. + dead port 1/2 on $mux $procmux$102966. + dead port 1/2 on $mux $procmux$102969. + dead port 1/2 on $mux $procmux$10297. + dead port 1/2 on $mux $procmux$102972. + dead port 1/2 on $mux $procmux$102975. + dead port 2/2 on $mux $procmux$102978. + dead port 1/2 on $mux $procmux$102984. + dead port 1/2 on $mux $procmux$102987. + dead port 1/2 on $mux $procmux$102990. + dead port 1/2 on $mux $procmux$102993. + dead port 1/2 on $mux $procmux$102996. + dead port 1/2 on $mux $procmux$102999. + dead port 1/2 on $mux $procmux$10300. + dead port 1/2 on $mux $procmux$103002. + dead port 1/2 on $mux $procmux$103005. + dead port 1/2 on $mux $procmux$103008. + dead port 1/2 on $mux $procmux$103011. + dead port 1/2 on $mux $procmux$103014. + dead port 2/2 on $mux $procmux$103017. + dead port 1/2 on $mux $procmux$103023. + dead port 1/2 on $mux $procmux$103026. + dead port 1/2 on $mux $procmux$103029. + dead port 1/2 on $mux $procmux$10303. + dead port 1/2 on $mux $procmux$103032. + dead port 1/2 on $mux $procmux$103035. + dead port 1/2 on $mux $procmux$103038. + dead port 1/2 on $mux $procmux$103041. + dead port 1/2 on $mux $procmux$103044. + dead port 1/2 on $mux $procmux$103047. + dead port 1/2 on $mux $procmux$103050. + dead port 1/2 on $mux $procmux$103053. + dead port 2/2 on $mux $procmux$103056. + dead port 1/2 on $mux $procmux$10306. + dead port 1/2 on $mux $procmux$103062. + dead port 1/2 on $mux $procmux$103065. + dead port 1/2 on $mux $procmux$103068. + dead port 1/2 on $mux $procmux$103071. + dead port 1/2 on $mux $procmux$103074. + dead port 1/2 on $mux $procmux$103077. + dead port 1/2 on $mux $procmux$103080. + dead port 1/2 on $mux $procmux$103083. + dead port 1/2 on $mux $procmux$103086. + dead port 1/2 on $mux $procmux$103089. + dead port 1/2 on $mux $procmux$10309. + dead port 1/2 on $mux $procmux$103092. + dead port 2/2 on $mux $procmux$103095. + dead port 1/2 on $mux $procmux$10312. + dead port 1/2 on $mux $procmux$10315. + dead port 1/2 on $mux $procmux$103179. + dead port 1/2 on $mux $procmux$10318. + dead port 1/2 on $mux $procmux$103182. + dead port 1/2 on $mux $procmux$103185. + dead port 1/2 on $mux $procmux$103188. + dead port 1/2 on $mux $procmux$103191. + dead port 1/2 on $mux $procmux$103194. + dead port 1/2 on $mux $procmux$103197. + dead port 1/2 on $mux $procmux$103200. + dead port 1/2 on $mux $procmux$103203. + dead port 1/2 on $mux $procmux$103206. + dead port 1/2 on $mux $procmux$103209. + dead port 1/2 on $mux $procmux$10321. + dead port 2/2 on $mux $procmux$103212. + dead port 1/2 on $mux $procmux$103218. + dead port 1/2 on $mux $procmux$103221. + dead port 1/2 on $mux $procmux$103224. + dead port 1/2 on $mux $procmux$103227. + dead port 1/2 on $mux $procmux$103230. + dead port 1/2 on $mux $procmux$103233. + dead port 1/2 on $mux $procmux$103236. + dead port 1/2 on $mux $procmux$103239. + dead port 1/2 on $mux $procmux$10324. + dead port 1/2 on $mux $procmux$103242. + dead port 1/2 on $mux $procmux$103245. + dead port 1/2 on $mux $procmux$103248. + dead port 2/2 on $mux $procmux$103251. + dead port 1/2 on $mux $procmux$103257. + dead port 1/2 on $mux $procmux$103260. + dead port 1/2 on $mux $procmux$103263. + dead port 1/2 on $mux $procmux$103266. + dead port 1/2 on $mux $procmux$103269. + dead port 1/2 on $mux $procmux$10327. + dead port 1/2 on $mux $procmux$103272. + dead port 1/2 on $mux $procmux$103275. + dead port 1/2 on $mux $procmux$103278. + dead port 1/2 on $mux $procmux$103281. + dead port 1/2 on $mux $procmux$103284. + dead port 1/2 on $mux $procmux$103287. + dead port 2/2 on $mux $procmux$10329. + dead port 2/2 on $mux $procmux$103290. + dead port 1/2 on $mux $procmux$103296. + dead port 1/2 on $mux $procmux$103299. + dead port 1/2 on $mux $procmux$103302. + dead port 1/2 on $mux $procmux$103305. + dead port 1/2 on $mux $procmux$103308. + dead port 1/2 on $mux $procmux$103311. + dead port 1/2 on $mux $procmux$103314. + dead port 1/2 on $mux $procmux$103317. + dead port 1/2 on $mux $procmux$10332. + dead port 1/2 on $mux $procmux$103320. + dead port 1/2 on $mux $procmux$103323. + dead port 1/2 on $mux $procmux$103326. + dead port 2/2 on $mux $procmux$103329. + dead port 1/2 on $mux $procmux$103335. + dead port 1/2 on $mux $procmux$103338. + dead port 1/2 on $mux $procmux$103341. + dead port 1/2 on $mux $procmux$103344. + dead port 1/2 on $mux $procmux$103347. + dead port 1/2 on $mux $procmux$10335. + dead port 1/2 on $mux $procmux$103350. + dead port 1/2 on $mux $procmux$103353. + dead port 1/2 on $mux $procmux$103356. + dead port 1/2 on $mux $procmux$103359. + dead port 1/2 on $mux $procmux$103362. + dead port 1/2 on $mux $procmux$103365. + dead port 2/2 on $mux $procmux$103368. + dead port 1/2 on $mux $procmux$103374. + dead port 1/2 on $mux $procmux$103377. + dead port 1/2 on $mux $procmux$10338. + dead port 1/2 on $mux $procmux$103380. + dead port 1/2 on $mux $procmux$103383. + dead port 1/2 on $mux $procmux$103386. + dead port 1/2 on $mux $procmux$103389. + dead port 1/2 on $mux $procmux$103392. + dead port 1/2 on $mux $procmux$103395. + dead port 1/2 on $mux $procmux$103398. + dead port 1/2 on $mux $procmux$103401. + dead port 1/2 on $mux $procmux$103404. + dead port 2/2 on $mux $procmux$103407. + dead port 1/2 on $mux $procmux$10341. + dead port 1/2 on $mux $procmux$103413. + dead port 1/2 on $mux $procmux$103416. + dead port 1/2 on $mux $procmux$103419. + dead port 1/2 on $mux $procmux$103422. + dead port 1/2 on $mux $procmux$103425. + dead port 1/2 on $mux $procmux$103428. + dead port 1/2 on $mux $procmux$103431. + dead port 1/2 on $mux $procmux$103434. + dead port 1/2 on $mux $procmux$103437. + dead port 1/2 on $mux $procmux$10344. + dead port 1/2 on $mux $procmux$103440. + dead port 1/2 on $mux $procmux$103443. + dead port 2/2 on $mux $procmux$103446. + dead port 1/2 on $mux $procmux$103452. + dead port 1/2 on $mux $procmux$103455. + dead port 1/2 on $mux $procmux$103458. + dead port 1/2 on $mux $procmux$103461. + dead port 1/2 on $mux $procmux$103464. + dead port 1/2 on $mux $procmux$103467. + dead port 1/2 on $mux $procmux$10347. + dead port 1/2 on $mux $procmux$103470. + dead port 1/2 on $mux $procmux$103473. + dead port 1/2 on $mux $procmux$103476. + dead port 1/2 on $mux $procmux$103479. + dead port 1/2 on $mux $procmux$103482. + dead port 2/2 on $mux $procmux$103485. + dead port 1/2 on $mux $procmux$103491. + dead port 1/2 on $mux $procmux$103494. + dead port 1/2 on $mux $procmux$103497. + dead port 1/2 on $mux $procmux$10350. + dead port 1/2 on $mux $procmux$103500. + dead port 1/2 on $mux $procmux$103503. + dead port 1/2 on $mux $procmux$103506. + dead port 1/2 on $mux $procmux$103509. + dead port 1/2 on $mux $procmux$103512. + dead port 1/2 on $mux $procmux$103515. + dead port 1/2 on $mux $procmux$103518. + dead port 1/2 on $mux $procmux$103521. + dead port 2/2 on $mux $procmux$103524. + dead port 1/2 on $mux $procmux$10353. + dead port 1/2 on $mux $procmux$103530. + dead port 1/2 on $mux $procmux$103533. + dead port 1/2 on $mux $procmux$103536. + dead port 1/2 on $mux $procmux$103539. + dead port 1/2 on $mux $procmux$103542. + dead port 1/2 on $mux $procmux$103545. + dead port 1/2 on $mux $procmux$103548. + dead port 1/2 on $mux $procmux$103551. + dead port 1/2 on $mux $procmux$103554. + dead port 1/2 on $mux $procmux$103557. + dead port 1/2 on $mux $procmux$10356. + dead port 1/2 on $mux $procmux$103560. + dead port 2/2 on $mux $procmux$103563. + dead port 1/2 on $mux $procmux$10359. + dead port 1/2 on $mux $procmux$103608. + dead port 1/2 on $mux $procmux$103611. + dead port 1/2 on $mux $procmux$103614. + dead port 1/2 on $mux $procmux$103617. + dead port 1/2 on $mux $procmux$10362. + dead port 1/2 on $mux $procmux$103620. + dead port 1/2 on $mux $procmux$103623. + dead port 1/2 on $mux $procmux$103626. + dead port 1/2 on $mux $procmux$103629. + dead port 1/2 on $mux $procmux$103632. + dead port 1/2 on $mux $procmux$103635. + dead port 1/2 on $mux $procmux$103638. + dead port 2/2 on $mux $procmux$103641. + dead port 1/2 on $mux $procmux$103647. + dead port 2/2 on $mux $procmux$10365. + dead port 1/2 on $mux $procmux$103650. + dead port 1/2 on $mux $procmux$103653. + dead port 1/2 on $mux $procmux$103656. + dead port 1/2 on $mux $procmux$103659. + dead port 1/2 on $mux $procmux$103662. + dead port 1/2 on $mux $procmux$103665. + dead port 1/2 on $mux $procmux$103668. + dead port 1/2 on $mux $procmux$103671. + dead port 1/2 on $mux $procmux$103674. + dead port 1/2 on $mux $procmux$103677. + dead port 2/2 on $mux $procmux$103680. + dead port 1/2 on $mux $procmux$103686. + dead port 1/2 on $mux $procmux$103689. + dead port 1/2 on $mux $procmux$103692. + dead port 1/2 on $mux $procmux$103695. + dead port 1/2 on $mux $procmux$103698. + dead port 1/2 on $mux $procmux$103701. + dead port 1/2 on $mux $procmux$103704. + dead port 1/2 on $mux $procmux$103707. + dead port 1/2 on $mux $procmux$103710. + dead port 1/2 on $mux $procmux$103713. + dead port 1/2 on $mux $procmux$103716. + dead port 2/2 on $mux $procmux$103719. + dead port 1/2 on $mux $procmux$10372. + dead port 1/2 on $mux $procmux$10375. + dead port 1/2 on $mux $procmux$10378. + dead port 1/2 on $mux $procmux$10381. + dead port 1/2 on $mux $procmux$10384. + dead port 1/2 on $mux $procmux$103842. + dead port 1/2 on $mux $procmux$103845. + dead port 1/2 on $mux $procmux$103848. + dead port 1/2 on $mux $procmux$103851. + dead port 1/2 on $mux $procmux$103854. + dead port 1/2 on $mux $procmux$103857. + dead port 1/2 on $mux $procmux$103860. + dead port 1/2 on $mux $procmux$103863. + dead port 1/2 on $mux $procmux$103866. + dead port 1/2 on $mux $procmux$103869. + dead port 1/2 on $mux $procmux$10387. + dead port 1/2 on $mux $procmux$103872. + dead port 2/2 on $mux $procmux$103875. + dead port 1/2 on $mux $procmux$103881. + dead port 1/2 on $mux $procmux$103884. + dead port 1/2 on $mux $procmux$103887. + dead port 1/2 on $mux $procmux$103890. + dead port 1/2 on $mux $procmux$103893. + dead port 1/2 on $mux $procmux$103896. + dead port 1/2 on $mux $procmux$103899. + dead port 1/2 on $mux $procmux$10390. + dead port 1/2 on $mux $procmux$103902. + dead port 1/2 on $mux $procmux$103905. + dead port 1/2 on $mux $procmux$103908. + dead port 1/2 on $mux $procmux$103911. + dead port 2/2 on $mux $procmux$103914. + dead port 1/2 on $mux $procmux$103920. + dead port 1/2 on $mux $procmux$103923. + dead port 1/2 on $mux $procmux$103926. + dead port 1/2 on $mux $procmux$103929. + dead port 1/2 on $mux $procmux$10393. + dead port 1/2 on $mux $procmux$103932. + dead port 1/2 on $mux $procmux$103935. + dead port 1/2 on $mux $procmux$103938. + dead port 1/2 on $mux $procmux$103941. + dead port 1/2 on $mux $procmux$103944. + dead port 1/2 on $mux $procmux$103947. + dead port 1/2 on $mux $procmux$103950. + dead port 2/2 on $mux $procmux$103953. + dead port 1/2 on $mux $procmux$10396. + dead port 1/2 on $mux $procmux$10399. + dead port 1/2 on $mux $procmux$103998. + dead port 1/2 on $mux $procmux$104001. + dead port 1/2 on $mux $procmux$104004. + dead port 1/2 on $mux $procmux$104007. + dead port 1/2 on $mux $procmux$104010. + dead port 1/2 on $mux $procmux$104013. + dead port 1/2 on $mux $procmux$104016. + dead port 1/2 on $mux $procmux$104019. + dead port 1/2 on $mux $procmux$10402. + dead port 1/2 on $mux $procmux$104022. + dead port 1/2 on $mux $procmux$104025. + dead port 1/2 on $mux $procmux$104028. + dead port 2/2 on $mux $procmux$104031. + dead port 1/2 on $mux $procmux$104037. + dead port 1/2 on $mux $procmux$104040. + dead port 1/2 on $mux $procmux$104043. + dead port 1/2 on $mux $procmux$104046. + dead port 1/2 on $mux $procmux$104049. + dead port 1/2 on $mux $procmux$10405. + dead port 1/2 on $mux $procmux$104052. + dead port 1/2 on $mux $procmux$104055. + dead port 1/2 on $mux $procmux$104058. + dead port 1/2 on $mux $procmux$104061. + dead port 1/2 on $mux $procmux$104064. + dead port 1/2 on $mux $procmux$104067. + dead port 2/2 on $mux $procmux$104070. + dead port 1/2 on $mux $procmux$104074. + dead port 1/2 on $mux $procmux$104077. + dead port 1/2 on $mux $procmux$10408. + dead port 1/2 on $mux $procmux$104080. + dead port 1/2 on $mux $procmux$104083. + dead port 2/2 on $mux $procmux$104085. + dead port 1/2 on $mux $procmux$104088. + dead port 1/2 on $mux $procmux$104091. + dead port 1/2 on $mux $procmux$104094. + dead port 1/2 on $mux $procmux$104097. + dead port 1/2 on $mux $procmux$104100. + dead port 1/2 on $mux $procmux$104103. + dead port 1/2 on $mux $procmux$104106. + dead port 1/2 on $mux $procmux$104109. + dead port 1/2 on $mux $procmux$10411. + dead port 1/2 on $mux $procmux$104112. + dead port 1/2 on $mux $procmux$104115. + dead port 2/2 on $mux $procmux$104118. + dead port 1/2 on $mux $procmux$104122. + dead port 1/2 on $mux $procmux$104125. + dead port 1/2 on $mux $procmux$104128. + dead port 1/2 on $mux $procmux$104131. + dead port 2/2 on $mux $procmux$104133. + dead port 1/2 on $mux $procmux$104136. + dead port 1/2 on $mux $procmux$104139. + dead port 1/2 on $mux $procmux$10414. + dead port 1/2 on $mux $procmux$104142. + dead port 1/2 on $mux $procmux$104145. + dead port 1/2 on $mux $procmux$104148. + dead port 1/2 on $mux $procmux$104151. + dead port 1/2 on $mux $procmux$104154. + dead port 1/2 on $mux $procmux$104157. + dead port 1/2 on $mux $procmux$104160. + dead port 1/2 on $mux $procmux$104163. + dead port 2/2 on $mux $procmux$104166. + dead port 1/2 on $mux $procmux$10417. + dead port 1/2 on $mux $procmux$104170. + dead port 1/2 on $mux $procmux$104173. + dead port 1/2 on $mux $procmux$104176. + dead port 1/2 on $mux $procmux$104179. + dead port 2/2 on $mux $procmux$104181. + dead port 1/2 on $mux $procmux$104184. + dead port 1/2 on $mux $procmux$104187. + dead port 1/2 on $mux $procmux$104190. + dead port 1/2 on $mux $procmux$104193. + dead port 1/2 on $mux $procmux$104196. + dead port 1/2 on $mux $procmux$104199. + dead port 1/2 on $mux $procmux$10420. + dead port 1/2 on $mux $procmux$104202. + dead port 1/2 on $mux $procmux$104205. + dead port 1/2 on $mux $procmux$104208. + dead port 1/2 on $mux $procmux$104211. + dead port 2/2 on $mux $procmux$104214. + dead port 2/2 on $mux $procmux$10422. + dead port 1/2 on $mux $procmux$104221. + dead port 1/2 on $mux $procmux$104224. + dead port 1/2 on $mux $procmux$104227. + dead port 2/2 on $mux $procmux$104229. + dead port 1/2 on $mux $procmux$104232. + dead port 1/2 on $mux $procmux$104235. + dead port 1/2 on $mux $procmux$104238. + dead port 1/2 on $mux $procmux$104241. + dead port 1/2 on $mux $procmux$104244. + dead port 1/2 on $mux $procmux$104247. + dead port 1/2 on $mux $procmux$10425. + dead port 1/2 on $mux $procmux$104250. + dead port 1/2 on $mux $procmux$104253. + dead port 1/2 on $mux $procmux$104256. + dead port 1/2 on $mux $procmux$104259. + dead port 2/2 on $mux $procmux$104262. + dead port 1/2 on $mux $procmux$104269. + dead port 1/2 on $mux $procmux$104272. + dead port 1/2 on $mux $procmux$104275. + dead port 2/2 on $mux $procmux$104277. + dead port 1/2 on $mux $procmux$10428. + dead port 1/2 on $mux $procmux$104280. + dead port 1/2 on $mux $procmux$104283. + dead port 1/2 on $mux $procmux$104286. + dead port 1/2 on $mux $procmux$104289. + dead port 1/2 on $mux $procmux$104292. + dead port 1/2 on $mux $procmux$104295. + dead port 1/2 on $mux $procmux$104298. + dead port 1/2 on $mux $procmux$104301. + dead port 1/2 on $mux $procmux$104304. + dead port 1/2 on $mux $procmux$104307. + dead port 1/2 on $mux $procmux$10431. + dead port 2/2 on $mux $procmux$104310. + dead port 1/2 on $mux $procmux$104317. + dead port 1/2 on $mux $procmux$104320. + dead port 1/2 on $mux $procmux$104323. + dead port 2/2 on $mux $procmux$104325. + dead port 1/2 on $mux $procmux$104328. + dead port 1/2 on $mux $procmux$104331. + dead port 1/2 on $mux $procmux$104334. + dead port 1/2 on $mux $procmux$104337. + dead port 1/2 on $mux $procmux$10434. + dead port 1/2 on $mux $procmux$104340. + dead port 1/2 on $mux $procmux$104343. + dead port 1/2 on $mux $procmux$104346. + dead port 1/2 on $mux $procmux$104349. + dead port 1/2 on $mux $procmux$104352. + dead port 1/2 on $mux $procmux$104355. + dead port 2/2 on $mux $procmux$104358. + dead port 1/2 on $mux $procmux$104365. + dead port 1/2 on $mux $procmux$104368. + dead port 1/2 on $mux $procmux$10437. + dead port 1/2 on $mux $procmux$104371. + dead port 2/2 on $mux $procmux$104373. + dead port 1/2 on $mux $procmux$104376. + dead port 1/2 on $mux $procmux$104379. + dead port 1/2 on $mux $procmux$104382. + dead port 1/2 on $mux $procmux$104385. + dead port 1/2 on $mux $procmux$104388. + dead port 1/2 on $mux $procmux$104391. + dead port 1/2 on $mux $procmux$104394. + dead port 1/2 on $mux $procmux$104397. + dead port 1/2 on $mux $procmux$10440. + dead port 1/2 on $mux $procmux$104400. + dead port 1/2 on $mux $procmux$104403. + dead port 2/2 on $mux $procmux$104406. + dead port 1/2 on $mux $procmux$104413. + dead port 1/2 on $mux $procmux$104416. + dead port 1/2 on $mux $procmux$104419. + dead port 2/2 on $mux $procmux$104421. + dead port 1/2 on $mux $procmux$104424. + dead port 1/2 on $mux $procmux$104427. + dead port 1/2 on $mux $procmux$10443. + dead port 1/2 on $mux $procmux$104430. + dead port 1/2 on $mux $procmux$104433. + dead port 1/2 on $mux $procmux$104436. + dead port 1/2 on $mux $procmux$104439. + dead port 1/2 on $mux $procmux$104442. + dead port 1/2 on $mux $procmux$104445. + dead port 1/2 on $mux $procmux$104448. + dead port 1/2 on $mux $procmux$104451. + dead port 2/2 on $mux $procmux$104454. + dead port 1/2 on $mux $procmux$10446. + dead port 1/2 on $mux $procmux$104461. + dead port 1/2 on $mux $procmux$104464. + dead port 1/2 on $mux $procmux$104467. + dead port 2/2 on $mux $procmux$104469. + dead port 1/2 on $mux $procmux$104472. + dead port 1/2 on $mux $procmux$104475. + dead port 1/2 on $mux $procmux$104478. + dead port 1/2 on $mux $procmux$104481. + dead port 1/2 on $mux $procmux$104484. + dead port 1/2 on $mux $procmux$104487. + dead port 1/2 on $mux $procmux$10449. + dead port 1/2 on $mux $procmux$104490. + dead port 1/2 on $mux $procmux$104493. + dead port 1/2 on $mux $procmux$104496. + dead port 1/2 on $mux $procmux$104499. + dead port 2/2 on $mux $procmux$104502. + dead port 1/2 on $mux $procmux$104509. + dead port 1/2 on $mux $procmux$104512. + dead port 1/2 on $mux $procmux$104515. + dead port 2/2 on $mux $procmux$104517. + dead port 1/2 on $mux $procmux$10452. + dead port 1/2 on $mux $procmux$104520. + dead port 1/2 on $mux $procmux$104523. + dead port 1/2 on $mux $procmux$104526. + dead port 1/2 on $mux $procmux$104529. + dead port 1/2 on $mux $procmux$104532. + dead port 1/2 on $mux $procmux$104535. + dead port 1/2 on $mux $procmux$104538. + dead port 1/2 on $mux $procmux$104541. + dead port 1/2 on $mux $procmux$104544. + dead port 1/2 on $mux $procmux$104547. + dead port 1/2 on $mux $procmux$10455. + dead port 2/2 on $mux $procmux$104550. + dead port 1/2 on $mux $procmux$104557. + dead port 1/2 on $mux $procmux$104560. + dead port 1/2 on $mux $procmux$104563. + dead port 2/2 on $mux $procmux$104565. + dead port 1/2 on $mux $procmux$104568. + dead port 1/2 on $mux $procmux$104571. + dead port 1/2 on $mux $procmux$104574. + dead port 1/2 on $mux $procmux$104577. + dead port 2/2 on $mux $procmux$10458. + dead port 1/2 on $mux $procmux$104580. + dead port 1/2 on $mux $procmux$104583. + dead port 1/2 on $mux $procmux$104586. + dead port 1/2 on $mux $procmux$104589. + dead port 1/2 on $mux $procmux$104592. + dead port 1/2 on $mux $procmux$104595. + dead port 2/2 on $mux $procmux$104598. + dead port 1/2 on $mux $procmux$104605. + dead port 1/2 on $mux $procmux$104608. + dead port 1/2 on $mux $procmux$104611. + dead port 2/2 on $mux $procmux$104613. + dead port 1/2 on $mux $procmux$104616. + dead port 1/2 on $mux $procmux$104619. + dead port 1/2 on $mux $procmux$104622. + dead port 1/2 on $mux $procmux$104625. + dead port 1/2 on $mux $procmux$104628. + dead port 1/2 on $mux $procmux$104631. + dead port 1/2 on $mux $procmux$104634. + dead port 1/2 on $mux $procmux$104637. + dead port 1/2 on $mux $procmux$104640. + dead port 1/2 on $mux $procmux$104643. + dead port 2/2 on $mux $procmux$104646. + dead port 1/2 on $mux $procmux$10465. + dead port 1/2 on $mux $procmux$104653. + dead port 1/2 on $mux $procmux$104656. + dead port 1/2 on $mux $procmux$104659. + dead port 2/2 on $mux $procmux$104661. + dead port 1/2 on $mux $procmux$104664. + dead port 1/2 on $mux $procmux$104667. + dead port 1/2 on $mux $procmux$104670. + dead port 1/2 on $mux $procmux$104673. + dead port 1/2 on $mux $procmux$104676. + dead port 1/2 on $mux $procmux$104679. + dead port 1/2 on $mux $procmux$10468. + dead port 1/2 on $mux $procmux$104682. + dead port 1/2 on $mux $procmux$104685. + dead port 1/2 on $mux $procmux$104688. + dead port 1/2 on $mux $procmux$104691. + dead port 2/2 on $mux $procmux$104694. + dead port 1/2 on $mux $procmux$104701. + dead port 1/2 on $mux $procmux$104704. + dead port 2/2 on $mux $procmux$104706. + dead port 1/2 on $mux $procmux$104709. + dead port 1/2 on $mux $procmux$10471. + dead port 1/2 on $mux $procmux$104712. + dead port 1/2 on $mux $procmux$104715. + dead port 1/2 on $mux $procmux$104718. + dead port 1/2 on $mux $procmux$104721. + dead port 1/2 on $mux $procmux$104724. + dead port 1/2 on $mux $procmux$104727. + dead port 1/2 on $mux $procmux$104730. + dead port 1/2 on $mux $procmux$104733. + dead port 1/2 on $mux $procmux$104736. + dead port 2/2 on $mux $procmux$104739. + dead port 1/2 on $mux $procmux$10474. + dead port 2/2 on $mux $procmux$104743. + dead port 1/2 on $mux $procmux$104746. + dead port 1/2 on $mux $procmux$104749. + dead port 2/2 on $mux $procmux$104751. + dead port 1/2 on $mux $procmux$104754. + dead port 1/2 on $mux $procmux$104757. + dead port 1/2 on $mux $procmux$104760. + dead port 1/2 on $mux $procmux$104763. + dead port 1/2 on $mux $procmux$104766. + dead port 1/2 on $mux $procmux$104769. + dead port 1/2 on $mux $procmux$10477. + dead port 1/2 on $mux $procmux$104772. + dead port 1/2 on $mux $procmux$104775. + dead port 1/2 on $mux $procmux$104778. + dead port 1/2 on $mux $procmux$104781. + dead port 2/2 on $mux $procmux$104784. + dead port 2/2 on $mux $procmux$104788. + dead port 1/2 on $mux $procmux$104791. + dead port 1/2 on $mux $procmux$104794. + dead port 2/2 on $mux $procmux$104796. + dead port 1/2 on $mux $procmux$104799. + dead port 1/2 on $mux $procmux$10480. + dead port 1/2 on $mux $procmux$104802. + dead port 1/2 on $mux $procmux$104805. + dead port 1/2 on $mux $procmux$104808. + dead port 1/2 on $mux $procmux$104811. + dead port 1/2 on $mux $procmux$104814. + dead port 1/2 on $mux $procmux$104817. + dead port 1/2 on $mux $procmux$104820. + dead port 1/2 on $mux $procmux$104823. + dead port 1/2 on $mux $procmux$104826. + dead port 2/2 on $mux $procmux$104829. + dead port 1/2 on $mux $procmux$10483. + dead port 1/2 on $mux $procmux$104836. + dead port 1/2 on $mux $procmux$104839. + dead port 2/2 on $mux $procmux$104841. + dead port 1/2 on $mux $procmux$104844. + dead port 1/2 on $mux $procmux$104847. + dead port 1/2 on $mux $procmux$104850. + dead port 1/2 on $mux $procmux$104853. + dead port 1/2 on $mux $procmux$104856. + dead port 1/2 on $mux $procmux$104859. + dead port 1/2 on $mux $procmux$10486. + dead port 1/2 on $mux $procmux$104862. + dead port 1/2 on $mux $procmux$104865. + dead port 1/2 on $mux $procmux$104868. + dead port 1/2 on $mux $procmux$104871. + dead port 2/2 on $mux $procmux$104874. + dead port 1/2 on $mux $procmux$104881. + dead port 1/2 on $mux $procmux$104884. + dead port 2/2 on $mux $procmux$104886. + dead port 1/2 on $mux $procmux$104889. + dead port 1/2 on $mux $procmux$10489. + dead port 1/2 on $mux $procmux$104892. + dead port 1/2 on $mux $procmux$104895. + dead port 1/2 on $mux $procmux$104898. + dead port 1/2 on $mux $procmux$104901. + dead port 1/2 on $mux $procmux$104904. + dead port 1/2 on $mux $procmux$104907. + dead port 1/2 on $mux $procmux$104910. + dead port 1/2 on $mux $procmux$104913. + dead port 1/2 on $mux $procmux$104916. + dead port 2/2 on $mux $procmux$104919. + dead port 1/2 on $mux $procmux$10492. + dead port 2/2 on $mux $procmux$104923. + dead port 1/2 on $mux $procmux$104926. + dead port 1/2 on $mux $procmux$104929. + dead port 2/2 on $mux $procmux$104931. + dead port 1/2 on $mux $procmux$104934. + dead port 1/2 on $mux $procmux$104937. + dead port 1/2 on $mux $procmux$104940. + dead port 1/2 on $mux $procmux$104943. + dead port 1/2 on $mux $procmux$104946. + dead port 1/2 on $mux $procmux$104949. + dead port 1/2 on $mux $procmux$10495. + dead port 1/2 on $mux $procmux$104952. + dead port 1/2 on $mux $procmux$104955. + dead port 1/2 on $mux $procmux$104958. + dead port 1/2 on $mux $procmux$104961. + dead port 2/2 on $mux $procmux$104964. + dead port 1/2 on $mux $procmux$104971. + dead port 1/2 on $mux $procmux$104974. + dead port 2/2 on $mux $procmux$104976. + dead port 1/2 on $mux $procmux$104979. + dead port 1/2 on $mux $procmux$10498. + dead port 1/2 on $mux $procmux$104982. + dead port 1/2 on $mux $procmux$104985. + dead port 1/2 on $mux $procmux$104988. + dead port 1/2 on $mux $procmux$104991. + dead port 1/2 on $mux $procmux$104994. + dead port 1/2 on $mux $procmux$104997. + dead port 1/2 on $mux $procmux$105000. + dead port 1/2 on $mux $procmux$105003. + dead port 1/2 on $mux $procmux$105006. + dead port 2/2 on $mux $procmux$105009. + dead port 1/2 on $mux $procmux$10501. + dead port 1/2 on $mux $procmux$105016. + dead port 1/2 on $mux $procmux$105019. + dead port 2/2 on $mux $procmux$105021. + dead port 1/2 on $mux $procmux$105024. + dead port 1/2 on $mux $procmux$105027. + dead port 1/2 on $mux $procmux$105030. + dead port 1/2 on $mux $procmux$105033. + dead port 1/2 on $mux $procmux$105036. + dead port 1/2 on $mux $procmux$105039. + dead port 1/2 on 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$procmux$105111. + dead port 1/2 on $mux $procmux$105114. + dead port 1/2 on $mux $procmux$105117. + dead port 1/2 on $mux $procmux$105120. + dead port 1/2 on $mux $procmux$105123. + dead port 1/2 on $mux $procmux$105126. + dead port 1/2 on $mux $procmux$105129. + dead port 1/2 on $mux $procmux$10513. + dead port 1/2 on $mux $procmux$105132. + dead port 1/2 on $mux $procmux$105135. + dead port 1/2 on $mux $procmux$105138. + dead port 1/2 on $mux $procmux$105141. + dead port 2/2 on $mux $procmux$105144. + dead port 2/2 on $mux $procmux$10515. + dead port 1/2 on $mux $procmux$10518. + dead port 1/2 on $mux $procmux$105196. + dead port 1/2 on $mux $procmux$105199. + dead port 2/2 on $mux $procmux$105201. + dead port 1/2 on $mux $procmux$105204. + dead port 1/2 on $mux $procmux$105207. + dead port 1/2 on $mux $procmux$10521. + dead port 1/2 on $mux $procmux$105210. + dead port 1/2 on $mux $procmux$105213. + dead port 1/2 on $mux $procmux$105216. + dead port 1/2 on $mux $procmux$105219. + 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$procmux$105855. + dead port 1/2 on $mux $procmux$105858. + dead port 1/2 on $mux $procmux$105861. + dead port 1/2 on $mux $procmux$105864. + dead port 2/2 on $mux $procmux$105867. + dead port 1/2 on $mux $procmux$10588. + dead port 1/2 on $mux $procmux$10591. + dead port 1/2 on $mux $procmux$10594. + dead port 1/2 on $mux $procmux$10597. + dead port 1/2 on $mux $procmux$10600. + dead port 1/2 on $mux $procmux$10603. + dead port 1/2 on $mux $procmux$10606. + dead port 2/2 on $mux $procmux$10608. + dead port 1/2 on $mux $procmux$10611. + dead port 1/2 on $mux $procmux$10614. + dead port 2/2 on $mux $procmux$106146. + dead port 1/2 on $mux $procmux$106149. + dead port 1/2 on $mux $procmux$106152. + dead port 1/2 on $mux $procmux$106155. + dead port 1/2 on $mux $procmux$106158. + dead port 1/2 on $mux $procmux$106161. + dead port 1/2 on $mux $procmux$106164. + dead port 1/2 on $mux $procmux$106167. + dead port 1/2 on $mux $procmux$10617. + dead port 1/2 on $mux $procmux$106170. + dead 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$mux $procmux$109731. + dead port 1/2 on $mux $procmux$109734. + dead port 1/2 on $mux $procmux$109737. + dead port 1/2 on $mux $procmux$109740. + dead port 1/2 on $mux $procmux$109743. + dead port 1/2 on $mux $procmux$109746. + dead port 1/2 on $mux $procmux$109749. + dead port 1/2 on $mux $procmux$10975. + dead port 1/2 on $mux $procmux$109752. + dead port 2/2 on $mux $procmux$109755. + dead port 1/2 on $mux $procmux$109761. + dead port 1/2 on $mux $procmux$109764. + dead port 1/2 on $mux $procmux$109767. + dead port 1/2 on $mux $procmux$109770. + dead port 1/2 on $mux $procmux$109773. + dead port 1/2 on $mux $procmux$109776. + dead port 1/2 on $mux $procmux$109779. + dead port 1/2 on $mux $procmux$10978. + dead port 1/2 on $mux $procmux$109782. + dead port 1/2 on $mux $procmux$109785. + dead port 1/2 on $mux $procmux$109788. + dead port 2/2 on $mux $procmux$109791. + dead port 1/2 on $mux $procmux$109797. + dead port 2/2 on $mux $procmux$10980. + dead port 1/2 on $mux $procmux$109800. + dead port 1/2 on $mux $procmux$109803. + dead port 1/2 on $mux $procmux$109806. + dead port 1/2 on $mux $procmux$109809. + dead port 1/2 on $mux $procmux$109812. + dead port 1/2 on $mux $procmux$109815. + dead port 1/2 on $mux $procmux$109818. + dead port 1/2 on $mux $procmux$109821. + dead port 1/2 on $mux $procmux$109824. + dead port 2/2 on $mux $procmux$109827. + dead port 1/2 on $mux $procmux$10983. + dead port 1/2 on $mux $procmux$109833. + dead port 1/2 on $mux $procmux$109836. + dead port 1/2 on $mux $procmux$109839. + dead port 1/2 on $mux $procmux$109842. + dead port 1/2 on $mux $procmux$109845. + dead port 1/2 on $mux $procmux$109848. + dead port 1/2 on $mux $procmux$109851. + dead port 1/2 on $mux $procmux$109854. + dead port 1/2 on $mux $procmux$109857. + dead port 1/2 on $mux $procmux$10986. + dead port 1/2 on $mux $procmux$109860. + dead port 2/2 on $mux $procmux$109863. + dead port 1/2 on $mux $procmux$109869. + dead port 1/2 on $mux $procmux$109872. + dead port 1/2 on $mux $procmux$109875. + dead port 1/2 on $mux $procmux$109878. + dead port 1/2 on $mux $procmux$109881. + dead port 1/2 on $mux $procmux$109884. + dead port 1/2 on $mux $procmux$109887. + dead port 1/2 on $mux $procmux$10989. + dead port 1/2 on $mux $procmux$109890. + dead port 1/2 on $mux $procmux$109893. + dead port 1/2 on $mux $procmux$109896. + dead port 2/2 on $mux $procmux$109899. + dead port 1/2 on $mux $procmux$109905. + dead port 1/2 on $mux $procmux$109908. + dead port 1/2 on $mux $procmux$109911. + dead port 1/2 on $mux $procmux$109914. + dead port 1/2 on $mux $procmux$109917. + dead port 1/2 on $mux $procmux$10992. + dead port 1/2 on $mux $procmux$109920. + dead port 1/2 on $mux $procmux$109923. + dead port 1/2 on $mux $procmux$109926. + dead port 1/2 on $mux $procmux$109929. + dead port 1/2 on $mux $procmux$109932. + dead port 2/2 on $mux $procmux$109935. + dead port 1/2 on $mux $procmux$109941. + dead port 1/2 on $mux $procmux$109944. + dead port 1/2 on $mux $procmux$109947. + dead port 1/2 on $mux $procmux$10995. + dead port 1/2 on $mux $procmux$109950. + dead port 1/2 on $mux $procmux$109953. + dead port 1/2 on $mux $procmux$109956. + dead port 1/2 on $mux $procmux$109959. + dead port 1/2 on $mux $procmux$109962. + dead port 1/2 on $mux $procmux$109965. + dead port 1/2 on $mux $procmux$109968. + dead port 2/2 on $mux $procmux$109971. + dead port 1/2 on $mux $procmux$109977. + dead port 1/2 on $mux $procmux$10998. + dead port 1/2 on $mux $procmux$109980. + dead port 1/2 on $mux $procmux$109983. + dead port 1/2 on $mux $procmux$109986. + dead port 1/2 on $mux $procmux$109989. + dead port 1/2 on $mux $procmux$109992. + dead port 1/2 on $mux $procmux$109995. + dead port 1/2 on $mux $procmux$109998. + dead port 1/2 on $mux $procmux$110001. + dead port 1/2 on $mux $procmux$110004. + dead port 2/2 on $mux $procmux$110007. + dead port 1/2 on $mux $procmux$11001. + dead port 1/2 on $mux $procmux$11004. + dead port 1/2 on $mux $procmux$110049. + dead port 1/2 on $mux $procmux$110052. + dead port 1/2 on $mux $procmux$110055. + dead port 1/2 on $mux $procmux$110058. + dead port 1/2 on $mux $procmux$110061. + dead port 1/2 on $mux $procmux$110064. + dead port 1/2 on $mux $procmux$110067. + dead port 1/2 on $mux $procmux$11007. + dead port 1/2 on $mux $procmux$110070. + dead port 1/2 on $mux $procmux$110073. + dead port 1/2 on $mux $procmux$110076. + dead port 2/2 on $mux $procmux$110079. + dead port 1/2 on $mux $procmux$110085. + dead port 1/2 on $mux $procmux$110088. + dead port 1/2 on $mux $procmux$110091. + dead port 1/2 on $mux $procmux$110094. + dead port 1/2 on $mux $procmux$110097. + dead port 1/2 on $mux $procmux$11010. + dead port 1/2 on $mux $procmux$110100. + dead port 1/2 on $mux $procmux$110103. + dead port 1/2 on $mux $procmux$110106. + dead port 1/2 on $mux $procmux$110109. + dead port 1/2 on $mux $procmux$110112. + dead port 2/2 on $mux $procmux$110115. + dead port 1/2 on $mux $procmux$110121. + dead port 1/2 on $mux $procmux$110124. + dead port 1/2 on $mux $procmux$110127. + dead port 1/2 on $mux $procmux$11013. + dead port 1/2 on $mux $procmux$110130. + dead port 1/2 on $mux $procmux$110133. + dead port 1/2 on $mux $procmux$110136. + dead port 1/2 on $mux $procmux$110139. + dead port 1/2 on $mux $procmux$110142. + dead port 1/2 on $mux $procmux$110145. + dead port 1/2 on $mux $procmux$110148. + dead port 2/2 on $mux $procmux$110151. + dead port 2/2 on $mux $procmux$11016. + dead port 1/2 on $mux $procmux$11023. + dead port 1/2 on $mux $procmux$11026. + dead port 1/2 on $mux $procmux$110265. + dead port 1/2 on $mux $procmux$110268. + dead port 1/2 on $mux $procmux$110271. + dead port 1/2 on $mux $procmux$110274. + dead port 1/2 on $mux $procmux$110277. + dead port 1/2 on $mux $procmux$110280. + dead port 1/2 on $mux $procmux$110283. + dead port 1/2 on $mux $procmux$110286. + dead port 1/2 on $mux $procmux$110289. + dead port 1/2 on $mux $procmux$11029. + dead port 1/2 on $mux $procmux$110292. + dead port 2/2 on $mux $procmux$110295. + dead port 1/2 on $mux $procmux$110301. + dead port 1/2 on $mux $procmux$110304. + dead port 1/2 on $mux $procmux$110307. + dead port 1/2 on $mux $procmux$110310. + dead port 1/2 on $mux $procmux$110313. + dead port 1/2 on $mux $procmux$110316. + dead port 1/2 on $mux $procmux$110319. + dead port 1/2 on $mux $procmux$11032. + dead port 1/2 on $mux $procmux$110322. + dead port 1/2 on $mux $procmux$110325. + dead port 1/2 on $mux $procmux$110328. + dead port 2/2 on $mux $procmux$110331. + dead port 1/2 on $mux $procmux$110337. + dead port 1/2 on $mux $procmux$110340. + dead port 1/2 on $mux $procmux$110343. + dead port 1/2 on $mux $procmux$110346. + dead port 1/2 on $mux $procmux$110349. + dead port 1/2 on $mux $procmux$11035. + dead port 1/2 on $mux $procmux$110352. + dead port 1/2 on $mux $procmux$110355. + dead port 1/2 on $mux $procmux$110358. + dead port 1/2 on $mux $procmux$110361. + dead port 1/2 on $mux $procmux$110364. + dead port 2/2 on $mux $procmux$110367. + dead port 1/2 on $mux $procmux$110373. + dead port 1/2 on $mux $procmux$110376. + dead port 1/2 on $mux $procmux$110379. + dead port 1/2 on $mux $procmux$11038. + dead port 1/2 on $mux $procmux$110382. + dead port 1/2 on $mux $procmux$110385. + dead port 1/2 on $mux $procmux$110388. + dead port 1/2 on $mux $procmux$110391. + dead port 1/2 on $mux $procmux$110394. + dead port 1/2 on $mux $procmux$110397. + dead port 1/2 on $mux $procmux$110400. + dead port 2/2 on $mux $procmux$110403. + dead port 2/2 on $mux $procmux$110409. + dead port 1/2 on $mux $procmux$11041. + dead port 1/2 on $mux $procmux$110412. + dead port 1/2 on $mux $procmux$110415. + dead port 1/2 on $mux $procmux$110418. + dead port 1/2 on $mux $procmux$110421. + dead port 1/2 on $mux $procmux$110424. + dead port 1/2 on $mux $procmux$110427. + dead port 1/2 on $mux $procmux$110430. + dead port 1/2 on $mux $procmux$110433. + dead port 1/2 on $mux $procmux$110436. + dead port 2/2 on $mux $procmux$110439. + dead port 1/2 on $mux $procmux$11044. + dead port 2/2 on $mux $procmux$110445. + dead port 1/2 on $mux $procmux$110448. + dead port 1/2 on $mux $procmux$110451. + dead port 1/2 on $mux $procmux$110454. + dead port 1/2 on $mux $procmux$110457. + dead port 1/2 on $mux $procmux$110460. + dead port 1/2 on $mux $procmux$110463. + dead port 1/2 on $mux $procmux$110466. + dead port 1/2 on $mux $procmux$110469. + dead port 1/2 on $mux $procmux$11047. + dead port 1/2 on $mux $procmux$110472. + dead port 2/2 on $mux $procmux$110475. + dead port 1/2 on $mux $procmux$110481. + dead port 1/2 on $mux $procmux$110484. + dead port 1/2 on $mux $procmux$110487. + dead port 1/2 on $mux $procmux$110490. + dead port 1/2 on $mux $procmux$110493. + dead port 1/2 on $mux $procmux$110496. + dead port 1/2 on $mux $procmux$110499. + dead port 1/2 on $mux $procmux$11050. + dead port 1/2 on $mux $procmux$110502. + dead port 1/2 on $mux $procmux$110505. + dead port 2/2 on $mux $procmux$110508. + dead port 1/2 on $mux $procmux$110514. + dead port 1/2 on $mux $procmux$110517. + dead port 1/2 on $mux $procmux$110520. + dead port 1/2 on $mux $procmux$110523. + dead port 1/2 on $mux $procmux$110526. + dead port 1/2 on $mux $procmux$110529. + dead port 1/2 on $mux $procmux$11053. + dead port 1/2 on $mux $procmux$110532. + dead port 1/2 on $mux $procmux$110535. + dead port 1/2 on $mux $procmux$110538. + dead port 2/2 on $mux $procmux$110541. + dead port 1/2 on $mux $procmux$110547. + dead port 1/2 on $mux $procmux$110550. + dead port 1/2 on $mux $procmux$110553. + dead port 1/2 on $mux $procmux$110556. + dead port 1/2 on $mux $procmux$110559. + dead port 1/2 on $mux $procmux$11056. + dead port 1/2 on $mux $procmux$110562. + dead port 1/2 on $mux $procmux$110565. + dead port 1/2 on $mux $procmux$110568. + dead port 1/2 on $mux $procmux$110571. + dead port 2/2 on $mux $procmux$110574. + dead port 1/2 on $mux $procmux$110580. + dead port 1/2 on $mux $procmux$110583. + dead port 1/2 on $mux $procmux$110586. + dead port 1/2 on $mux $procmux$110589. + dead port 1/2 on $mux $procmux$11059. + dead port 1/2 on $mux $procmux$110592. + dead port 1/2 on $mux $procmux$110595. + dead port 1/2 on $mux $procmux$110598. + dead port 1/2 on $mux $procmux$110601. + dead port 1/2 on $mux $procmux$110604. + dead port 2/2 on $mux $procmux$110607. + dead port 1/2 on $mux $procmux$110613. + dead port 1/2 on $mux $procmux$110616. + dead port 1/2 on $mux $procmux$110619. + dead port 1/2 on $mux $procmux$11062. + dead port 1/2 on $mux $procmux$110622. + dead port 1/2 on $mux $procmux$110625. + dead port 1/2 on $mux $procmux$110628. + dead port 1/2 on $mux $procmux$110631. + dead port 1/2 on $mux $procmux$110634. + dead port 1/2 on $mux $procmux$110637. + dead port 2/2 on $mux $procmux$110640. + dead port 1/2 on $mux $procmux$11065. + dead port 1/2 on $mux $procmux$11068. + dead port 1/2 on $mux $procmux$11071. + dead port 2/2 on $mux $procmux$11073. + dead port 1/2 on $mux $procmux$11076. + dead port 1/2 on $mux $procmux$11079. + dead port 1/2 on $mux $procmux$11082. + dead port 1/2 on $mux $procmux$11085. + dead port 1/2 on $mux $procmux$11088. + dead port 1/2 on $mux $procmux$11091. + dead port 1/2 on $mux $procmux$11094. + dead port 1/2 on $mux $procmux$11097. + dead port 1/2 on $mux $procmux$11100. + dead port 1/2 on $mux $procmux$11103. + dead port 1/2 on $mux $procmux$11106. + dead port 2/2 on $mux $procmux$11109. + dead port 1/2 on $mux $procmux$11116. + dead port 1/2 on $mux $procmux$11119. + dead port 1/2 on $mux $procmux$11122. + dead port 1/2 on $mux $procmux$11125. + dead port 1/2 on $mux $procmux$11128. + dead port 1/2 on $mux $procmux$11131. + dead port 1/2 on $mux $procmux$11134. + dead port 1/2 on $mux $procmux$11137. + dead port 1/2 on $mux $procmux$11140. + dead port 1/2 on $mux $procmux$11143. + dead port 1/2 on $mux $procmux$11146. + dead port 1/2 on $mux $procmux$11149. + dead port 1/2 on $mux $procmux$11152. + dead port 1/2 on $mux $procmux$11155. + dead port 1/2 on $mux $procmux$11158. + dead port 1/2 on $mux $procmux$11161. + dead port 1/2 on $mux $procmux$11164. + dead port 2/2 on $mux $procmux$11166. + dead port 1/2 on $mux $procmux$11169. + dead port 1/2 on $mux $procmux$11172. + dead port 1/2 on $mux $procmux$11175. + dead port 1/2 on $mux $procmux$11178. + dead port 1/2 on $mux $procmux$11181. + dead port 1/2 on $mux $procmux$11184. + dead port 1/2 on $mux $procmux$11187. + dead port 1/2 on $mux $procmux$11190. + dead port 1/2 on $mux $procmux$11193. + dead port 1/2 on $mux $procmux$11196. + dead port 1/2 on $mux $procmux$11199. + dead port 2/2 on $mux $procmux$11202. + dead port 1/2 on $mux $procmux$11209. + dead port 1/2 on $mux $procmux$11212. + dead port 1/2 on $mux $procmux$11215. + dead port 1/2 on $mux $procmux$11218. + dead port 1/2 on $mux $procmux$11221. + dead port 1/2 on $mux $procmux$11224. + dead port 1/2 on $mux $procmux$11227. + dead port 1/2 on $mux $procmux$11230. + dead port 1/2 on $mux $procmux$11233. + dead port 1/2 on $mux $procmux$11236. + dead port 1/2 on $mux $procmux$11239. + dead port 1/2 on $mux $procmux$11242. + dead port 1/2 on $mux $procmux$11245. + dead port 1/2 on $mux $procmux$11248. + dead port 1/2 on $mux $procmux$11251. + dead port 1/2 on $mux $procmux$11254. + dead port 1/2 on $mux $procmux$11257. + dead port 2/2 on $mux $procmux$11259. + dead port 1/2 on $mux $procmux$11262. + dead port 1/2 on $mux $procmux$11265. + dead port 1/2 on $mux $procmux$11268. + dead port 1/2 on $mux $procmux$11271. + dead port 1/2 on $mux $procmux$11274. + dead port 1/2 on $mux $procmux$11277. + dead port 1/2 on $mux $procmux$11280. + dead port 1/2 on $mux $procmux$11283. + dead port 1/2 on $mux $procmux$11286. + dead port 1/2 on $mux $procmux$11289. + dead port 1/2 on $mux $procmux$11292. + dead port 2/2 on $mux $procmux$11295. + dead port 1/2 on $mux $procmux$113253. + dead port 1/2 on $mux $procmux$113256. + dead port 1/2 on $mux $procmux$113259. + dead port 1/2 on $mux $procmux$113262. + dead port 1/2 on $mux $procmux$113265. + dead port 1/2 on $mux $procmux$113268. + dead port 1/2 on $mux $procmux$113271. + dead port 1/2 on $mux $procmux$113274. + dead port 1/2 on $mux $procmux$113277. + dead port 2/2 on $mux $procmux$113280. + dead port 1/2 on $mux $procmux$113286. + dead port 1/2 on $mux $procmux$113289. + dead port 1/2 on $mux $procmux$113292. + dead port 1/2 on $mux $procmux$113295. + dead port 1/2 on $mux $procmux$113298. + dead port 1/2 on $mux $procmux$113301. + dead port 1/2 on $mux $procmux$113304. + dead port 1/2 on $mux $procmux$113307. + dead port 1/2 on $mux $procmux$113310. + dead port 2/2 on $mux $procmux$113313. + dead port 1/2 on $mux $procmux$113319. + dead port 1/2 on $mux $procmux$113322. + dead port 1/2 on $mux $procmux$113325. + dead port 1/2 on $mux $procmux$113328. + dead port 1/2 on $mux $procmux$113331. + dead port 1/2 on $mux $procmux$113334. + dead port 1/2 on $mux $procmux$113337. + dead port 1/2 on $mux $procmux$113340. + dead port 1/2 on $mux $procmux$113343. + dead port 2/2 on $mux $procmux$113346. + dead port 1/2 on $mux $procmux$113352. + dead port 1/2 on $mux $procmux$113355. + dead port 1/2 on $mux $procmux$113358. + dead port 1/2 on $mux $procmux$113361. + dead port 1/2 on $mux $procmux$113364. + dead port 1/2 on $mux $procmux$113367. + dead port 1/2 on $mux $procmux$113370. + dead port 1/2 on $mux $procmux$113373. + dead port 1/2 on $mux $procmux$113376. + dead port 2/2 on $mux $procmux$113379. + dead port 1/2 on $mux $procmux$113385. + dead port 1/2 on $mux $procmux$113388. + dead port 1/2 on $mux $procmux$113391. + dead port 1/2 on $mux $procmux$113394. + dead port 1/2 on $mux $procmux$113397. + dead port 1/2 on $mux $procmux$113400. + dead port 1/2 on $mux $procmux$113403. + dead port 1/2 on $mux $procmux$113406. + dead port 1/2 on $mux $procmux$113409. + dead port 2/2 on $mux $procmux$113412. + dead port 1/2 on $mux $procmux$113484. + dead port 1/2 on $mux $procmux$113487. + dead port 1/2 on $mux $procmux$113490. + dead port 1/2 on $mux $procmux$113493. + dead port 1/2 on $mux $procmux$113496. + dead port 1/2 on $mux $procmux$113499. + dead port 1/2 on $mux $procmux$113502. + dead port 1/2 on $mux $procmux$113505. + dead port 1/2 on $mux $procmux$113508. + dead port 2/2 on $mux $procmux$113511. + dead port 1/2 on $mux $procmux$113517. + dead port 1/2 on $mux $procmux$113520. + dead port 1/2 on $mux $procmux$113523. + dead port 1/2 on $mux $procmux$113526. + dead port 1/2 on $mux $procmux$113529. + dead port 1/2 on $mux $procmux$113532. + dead port 1/2 on $mux $procmux$113535. + dead port 1/2 on $mux $procmux$113538. + dead port 1/2 on $mux $procmux$113541. + dead port 2/2 on $mux $procmux$113544. + dead port 1/2 on $mux $procmux$113550. + dead port 1/2 on $mux $procmux$113553. + dead port 1/2 on $mux $procmux$113556. + dead port 1/2 on $mux $procmux$113559. + dead port 1/2 on $mux $procmux$113562. + dead port 1/2 on $mux $procmux$113565. + dead port 1/2 on $mux $procmux$113568. + dead port 1/2 on $mux $procmux$113571. + dead port 1/2 on $mux $procmux$113574. + dead port 2/2 on $mux $procmux$113577. + dead port 1/2 on $mux $procmux$113583. + dead port 1/2 on $mux $procmux$113586. + dead port 1/2 on $mux $procmux$113589. + dead port 1/2 on $mux $procmux$113592. + dead port 1/2 on $mux $procmux$113595. + dead port 1/2 on $mux $procmux$113598. + dead port 1/2 on $mux $procmux$113601. + dead port 1/2 on $mux $procmux$113604. + dead port 1/2 on $mux $procmux$113607. + dead port 2/2 on $mux $procmux$113610. + dead port 1/2 on $mux $procmux$113616. + dead port 1/2 on $mux $procmux$113619. + dead port 1/2 on $mux $procmux$113622. + dead port 1/2 on $mux $procmux$113625. + dead port 1/2 on $mux $procmux$113628. + dead port 1/2 on $mux $procmux$113631. + dead port 1/2 on $mux $procmux$113634. + dead port 1/2 on $mux $procmux$113637. + dead port 1/2 on $mux $procmux$113640. + dead port 2/2 on $mux $procmux$113643. + dead port 1/2 on $mux $procmux$113649. + dead port 1/2 on $mux $procmux$113652. + dead port 1/2 on $mux $procmux$113655. + dead port 1/2 on $mux $procmux$113658. + dead port 1/2 on $mux $procmux$113661. + dead port 1/2 on $mux $procmux$113664. + dead port 1/2 on $mux $procmux$113667. + dead port 1/2 on $mux $procmux$113670. + dead port 1/2 on $mux $procmux$113673. + dead port 2/2 on $mux $procmux$113676. + dead port 1/2 on $mux $procmux$113682. + dead port 1/2 on $mux $procmux$113685. + dead port 1/2 on $mux $procmux$113688. + dead port 1/2 on $mux $procmux$113691. + dead port 1/2 on $mux $procmux$113694. + dead port 1/2 on $mux $procmux$113697. + dead port 1/2 on $mux $procmux$113700. + dead port 1/2 on $mux $procmux$113703. + dead port 1/2 on $mux $procmux$113706. + dead port 2/2 on $mux $procmux$113709. + dead port 1/2 on $mux $procmux$113715. + dead port 1/2 on $mux $procmux$113718. + dead port 1/2 on $mux $procmux$113721. + dead port 1/2 on $mux $procmux$113724. + dead port 1/2 on $mux $procmux$113727. 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on $mux $procmux$113808. + dead port 1/2 on $mux $procmux$113847. + dead port 1/2 on $mux $procmux$113850. + dead port 1/2 on $mux $procmux$113853. + dead port 1/2 on $mux $procmux$113856. + dead port 1/2 on $mux $procmux$113859. + dead port 1/2 on $mux $procmux$113862. + dead port 1/2 on $mux $procmux$113865. + dead port 1/2 on $mux $procmux$113868. + dead port 1/2 on $mux $procmux$113871. + dead port 2/2 on $mux $procmux$113874. + dead port 1/2 on $mux $procmux$113880. + dead port 1/2 on $mux $procmux$113883. + dead port 1/2 on $mux $procmux$113886. + dead port 1/2 on $mux $procmux$113889. + dead port 1/2 on $mux $procmux$113892. + dead port 1/2 on $mux $procmux$113895. + dead port 1/2 on $mux $procmux$113898. + dead port 1/2 on $mux $procmux$113901. + dead port 1/2 on $mux $procmux$113904. + dead port 2/2 on $mux $procmux$113907. + dead port 1/2 on $mux $procmux$113913. + dead port 1/2 on $mux $procmux$113916. + dead port 1/2 on $mux $procmux$113919. + dead port 1/2 on $mux $procmux$113922. + dead port 1/2 on $mux $procmux$113925. + dead port 1/2 on $mux $procmux$113928. + dead port 1/2 on $mux $procmux$113931. + dead port 1/2 on $mux $procmux$113934. + dead port 1/2 on $mux $procmux$113937. + dead port 2/2 on $mux $procmux$113940. + dead port 1/2 on $mux $procmux$114045. + dead port 1/2 on $mux $procmux$114048. + dead port 1/2 on $mux $procmux$114051. + dead port 1/2 on $mux $procmux$114054. + dead port 1/2 on $mux $procmux$114057. + dead port 1/2 on $mux $procmux$114060. + dead port 1/2 on $mux $procmux$114063. + dead port 1/2 on $mux $procmux$114066. + dead port 1/2 on $mux $procmux$114069. + dead port 2/2 on $mux $procmux$114072. + dead port 1/2 on $mux $procmux$114078. + dead port 1/2 on $mux $procmux$114081. + dead port 1/2 on $mux $procmux$114084. + dead port 1/2 on $mux $procmux$114087. + dead port 1/2 on $mux $procmux$114090. + dead port 1/2 on $mux $procmux$114093. + dead port 1/2 on $mux $procmux$114096. + dead port 1/2 on $mux $procmux$114099. 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$procmux$11725. + dead port 1/2 on $mux $procmux$117252. + dead port 1/2 on $mux $procmux$117255. + dead port 1/2 on $mux $procmux$117258. + dead port 1/2 on $mux $procmux$117261. + dead port 1/2 on $mux $procmux$117264. + dead port 1/2 on $mux $procmux$117267. + dead port 1/2 on $mux $procmux$117270. + dead port 1/2 on $mux $procmux$117273. + dead port 2/2 on $mux $procmux$117276. + dead port 1/2 on $mux $procmux$11728. + dead port 1/2 on $mux $procmux$117282. + dead port 1/2 on $mux $procmux$117285. + dead port 1/2 on $mux $procmux$117288. + dead port 1/2 on $mux $procmux$117291. + dead port 1/2 on $mux $procmux$117294. + dead port 1/2 on $mux $procmux$117297. + dead port 1/2 on $mux $procmux$117300. + dead port 1/2 on $mux $procmux$117303. + dead port 2/2 on $mux $procmux$117306. + dead port 1/2 on $mux $procmux$11731. + dead port 1/2 on $mux $procmux$117312. + dead port 1/2 on $mux $procmux$117315. + dead port 1/2 on $mux $procmux$117318. + dead port 1/2 on $mux $procmux$117321. + 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$procmux$117822. + dead port 1/2 on $mux $procmux$117825. + dead port 1/2 on $mux $procmux$117828. + dead port 1/2 on $mux $procmux$117831. + dead port 1/2 on $mux $procmux$117834. + dead port 1/2 on $mux $procmux$117837. + dead port 1/2 on $mux $procmux$11784. + dead port 1/2 on $mux $procmux$117840. + dead port 1/2 on $mux $procmux$117843. + dead port 2/2 on $mux $procmux$117846. + dead port 1/2 on $mux $procmux$117852. + dead port 1/2 on $mux $procmux$117855. + dead port 1/2 on $mux $procmux$117858. + dead port 1/2 on $mux $procmux$117861. + dead port 1/2 on $mux $procmux$117864. + dead port 1/2 on $mux $procmux$117867. + dead port 1/2 on $mux $procmux$11787. + dead port 1/2 on $mux $procmux$117870. + dead port 2/2 on $mux $procmux$117873. + dead port 1/2 on $mux $procmux$117879. + dead port 1/2 on $mux $procmux$117882. + dead port 1/2 on $mux $procmux$117885. + dead port 1/2 on $mux $procmux$117888. + dead port 1/2 on $mux $procmux$117891. + dead port 1/2 on $mux $procmux$117894. + dead port 1/2 on $mux $procmux$117897. + dead port 1/2 on $mux $procmux$11790. + dead port 2/2 on $mux $procmux$117900. + dead port 1/2 on $mux $procmux$117906. + dead port 1/2 on $mux $procmux$117909. + dead port 1/2 on $mux $procmux$117912. + dead port 1/2 on $mux $procmux$117915. + dead port 1/2 on $mux $procmux$117918. + dead port 1/2 on $mux $procmux$117921. + dead port 1/2 on $mux $procmux$117924. + dead port 2/2 on $mux $procmux$117927. + dead port 1/2 on $mux $procmux$11793. + dead port 1/2 on $mux $procmux$117933. + dead port 1/2 on $mux $procmux$117936. + dead port 1/2 on $mux $procmux$117939. + dead port 1/2 on $mux $procmux$117942. + dead port 1/2 on $mux $procmux$117945. + dead port 1/2 on $mux $procmux$117948. + dead port 1/2 on $mux $procmux$117951. + dead port 2/2 on $mux $procmux$117954. + dead port 1/2 on $mux $procmux$11796. + dead port 1/2 on $mux $procmux$117960. + dead port 1/2 on $mux $procmux$117963. + dead port 1/2 on $mux $procmux$117966. + dead port 1/2 on $mux $procmux$117969. + dead port 1/2 on $mux $procmux$117972. + dead port 1/2 on $mux $procmux$117975. + dead port 1/2 on $mux $procmux$117978. + dead port 2/2 on $mux $procmux$117981. + dead port 1/2 on $mux $procmux$11799. + dead port 2/2 on $mux $procmux$11802. + dead port 1/2 on $mux $procmux$11810. + dead port 1/2 on $mux $procmux$11813. + dead port 1/2 on $mux $procmux$11816. + dead port 1/2 on $mux $procmux$11819. + dead port 1/2 on $mux $procmux$11822. + dead port 1/2 on $mux $procmux$11825. + dead port 1/2 on $mux $procmux$11828. + dead port 2/2 on $mux $procmux$11830. + dead port 1/2 on $mux $procmux$11833. + dead port 1/2 on $mux $procmux$11836. + dead port 1/2 on $mux $procmux$11839. + dead port 1/2 on $mux $procmux$11842. + dead port 1/2 on $mux $procmux$11845. + dead port 1/2 on $mux $procmux$11848. + dead port 1/2 on $mux $procmux$11851. + dead port 1/2 on $mux $procmux$11854. + dead port 1/2 on $mux $procmux$11857. + dead port 1/2 on $mux $procmux$11860. + dead port 1/2 on $mux $procmux$11863. + dead port 1/2 on $mux $procmux$11866. + dead port 1/2 on $mux $procmux$11869. + dead port 1/2 on $mux $procmux$11872. + dead port 1/2 on $mux $procmux$11875. + dead port 1/2 on $mux $procmux$11878. + dead port 2/2 on $mux $procmux$11880. + dead port 1/2 on $mux $procmux$11883. + dead port 1/2 on $mux $procmux$11886. + dead port 1/2 on $mux $procmux$11889. + dead port 1/2 on $mux $procmux$11892. + dead port 1/2 on $mux $procmux$11895. + dead port 1/2 on $mux $procmux$11898. + dead port 1/2 on $mux $procmux$11901. + dead port 1/2 on $mux $procmux$11904. + dead port 1/2 on $mux $procmux$11907. + dead port 1/2 on $mux $procmux$11910. + dead port 1/2 on $mux $procmux$11913. + dead port 2/2 on $mux $procmux$11916. + dead port 1/2 on $mux $procmux$11924. + dead port 1/2 on $mux $procmux$11927. + dead port 1/2 on $mux $procmux$11930. + dead port 1/2 on $mux $procmux$11933. + dead port 1/2 on $mux $procmux$11936. + dead port 1/2 on $mux $procmux$11939. + dead port 2/2 on $mux $procmux$11941. + dead port 1/2 on $mux $procmux$11944. + dead port 1/2 on $mux $procmux$11947. + dead port 1/2 on $mux $procmux$11950. + dead port 1/2 on $mux $procmux$11953. + dead port 1/2 on $mux $procmux$11956. + dead port 1/2 on $mux $procmux$11959. + dead port 1/2 on $mux $procmux$11962. + dead port 1/2 on $mux $procmux$11965. + dead port 1/2 on $mux $procmux$11968. + dead port 1/2 on $mux $procmux$11971. + dead port 1/2 on $mux $procmux$11974. + dead port 1/2 on $mux $procmux$11977. + dead port 1/2 on $mux $procmux$11980. + dead port 1/2 on $mux $procmux$11983. + dead port 1/2 on $mux $procmux$11986. + dead port 1/2 on $mux $procmux$11989. + dead port 2/2 on $mux $procmux$11991. + dead port 1/2 on $mux $procmux$11994. + dead port 1/2 on $mux $procmux$11997. + dead port 1/2 on $mux $procmux$12000. + dead port 1/2 on $mux $procmux$12003. + dead port 1/2 on $mux $procmux$12006. + dead port 1/2 on $mux $procmux$12009. + dead port 1/2 on $mux $procmux$12012. + dead port 1/2 on $mux $procmux$12015. + dead port 1/2 on $mux $procmux$120174. + dead port 1/2 on $mux $procmux$120177. + dead port 1/2 on $mux $procmux$12018. + dead port 1/2 on $mux $procmux$120180. + dead port 1/2 on $mux $procmux$120183. + dead port 1/2 on $mux $procmux$120186. + dead port 1/2 on $mux $procmux$120189. + dead port 1/2 on $mux $procmux$120192. + dead port 2/2 on $mux $procmux$120195. + dead port 1/2 on $mux $procmux$120201. + dead port 1/2 on $mux $procmux$120204. + dead port 1/2 on $mux $procmux$120207. + dead port 1/2 on $mux $procmux$12021. + dead port 1/2 on $mux $procmux$120210. + dead port 1/2 on $mux $procmux$120213. + dead port 1/2 on $mux $procmux$120216. + dead port 1/2 on $mux $procmux$120219. + dead port 2/2 on $mux $procmux$120222. + dead port 1/2 on $mux $procmux$120228. + dead port 1/2 on $mux $procmux$120231. + dead port 1/2 on $mux $procmux$120234. + dead port 1/2 on $mux $procmux$120237. + dead port 1/2 on $mux $procmux$12024. + dead port 1/2 on $mux $procmux$120240. + dead port 1/2 on $mux $procmux$120243. + dead port 1/2 on $mux $procmux$120246. + dead port 2/2 on $mux $procmux$120249. + dead port 1/2 on $mux $procmux$120255. + dead port 1/2 on $mux $procmux$120258. + dead port 1/2 on $mux $procmux$120261. + dead port 1/2 on $mux $procmux$120264. + dead port 1/2 on $mux $procmux$120267. + dead port 2/2 on $mux $procmux$12027. + dead port 1/2 on $mux $procmux$120270. + dead port 1/2 on $mux $procmux$120273. + dead port 2/2 on $mux $procmux$120276. + dead port 1/2 on $mux $procmux$120282. + dead port 1/2 on $mux $procmux$120285. + dead port 1/2 on $mux $procmux$120288. + dead port 1/2 on $mux $procmux$120291. + dead port 1/2 on $mux $procmux$120294. + dead port 1/2 on $mux $procmux$120297. + dead port 1/2 on $mux $procmux$120300. + dead port 2/2 on $mux $procmux$120303. + dead port 1/2 on $mux $procmux$12035. + dead port 1/2 on $mux $procmux$120363. + dead port 1/2 on $mux $procmux$120366. + dead port 1/2 on $mux $procmux$120369. + dead port 1/2 on $mux $procmux$120372. + dead port 1/2 on $mux $procmux$120375. + dead port 1/2 on $mux $procmux$120378. + dead port 1/2 on $mux $procmux$12038. + dead port 1/2 on $mux $procmux$120381. + dead port 2/2 on $mux $procmux$120384. + dead port 1/2 on $mux $procmux$120390. + dead port 1/2 on $mux $procmux$120393. + dead port 1/2 on $mux $procmux$120396. + dead port 1/2 on $mux $procmux$120399. + dead port 1/2 on $mux $procmux$120402. + dead port 1/2 on $mux $procmux$120405. + dead port 1/2 on $mux $procmux$120408. + dead port 1/2 on $mux $procmux$12041. + dead port 2/2 on $mux $procmux$120411. + dead port 1/2 on $mux $procmux$120417. + dead port 1/2 on $mux $procmux$120420. + dead port 1/2 on $mux $procmux$120423. + dead port 1/2 on $mux $procmux$120426. + dead port 1/2 on $mux $procmux$120429. + dead port 1/2 on $mux $procmux$120432. + dead port 1/2 on $mux $procmux$120435. + dead port 2/2 on $mux $procmux$120438. + dead port 1/2 on $mux $procmux$12044. + dead port 1/2 on $mux $procmux$120444. + dead port 1/2 on $mux $procmux$120447. + dead port 1/2 on $mux $procmux$120450. + dead port 1/2 on $mux $procmux$120453. + dead port 1/2 on $mux $procmux$120456. + dead port 1/2 on $mux $procmux$120459. + dead port 1/2 on $mux $procmux$120462. + dead port 2/2 on $mux $procmux$120465. + dead port 1/2 on $mux $procmux$12047. + dead port 1/2 on $mux $procmux$120471. + dead port 1/2 on $mux $procmux$120474. + dead port 1/2 on $mux $procmux$120477. + dead port 1/2 on $mux $procmux$120480. + dead port 1/2 on $mux $procmux$120483. + dead port 1/2 on $mux $procmux$120486. + dead port 1/2 on $mux $procmux$120489. + dead port 2/2 on $mux $procmux$120492. + dead port 1/2 on $mux $procmux$120498. + dead port 1/2 on $mux $procmux$12050. + dead port 1/2 on $mux $procmux$120501. + dead port 1/2 on $mux $procmux$120504. + dead port 1/2 on $mux $procmux$120507. + dead port 1/2 on $mux $procmux$120510. + dead port 1/2 on $mux $procmux$120513. + dead port 1/2 on $mux $procmux$120516. + dead port 2/2 on $mux $procmux$120519. + dead port 2/2 on $mux $procmux$12052. + dead port 1/2 on $mux $procmux$120525. + dead port 1/2 on $mux $procmux$120528. + dead port 1/2 on $mux $procmux$120531. + dead port 1/2 on $mux $procmux$120534. + dead port 1/2 on $mux $procmux$120537. + dead port 1/2 on $mux $procmux$120540. + dead port 1/2 on $mux $procmux$120543. + dead port 2/2 on $mux $procmux$120546. + dead port 1/2 on $mux $procmux$12055. + dead port 1/2 on $mux $procmux$120552. + dead port 1/2 on $mux $procmux$120555. + dead port 1/2 on $mux $procmux$120558. + dead port 1/2 on $mux $procmux$120561. + dead port 1/2 on $mux $procmux$120564. + dead port 1/2 on $mux $procmux$120567. + dead port 1/2 on $mux $procmux$120570. + dead port 2/2 on $mux $procmux$120573. + dead port 1/2 on $mux $procmux$120579. + dead port 1/2 on $mux $procmux$12058. + dead port 1/2 on $mux $procmux$120582. + dead port 1/2 on $mux $procmux$120585. + dead port 1/2 on $mux $procmux$120588. + dead port 1/2 on $mux $procmux$120591. + dead port 1/2 on $mux $procmux$120594. + dead port 1/2 on $mux $procmux$120597. + dead port 2/2 on $mux $procmux$120600. + dead port 1/2 on $mux $procmux$120606. + dead port 1/2 on $mux $procmux$120609. + dead port 1/2 on $mux $procmux$12061. + dead port 1/2 on $mux $procmux$120612. + dead port 1/2 on $mux $procmux$120615. + dead port 1/2 on $mux $procmux$120618. + dead port 1/2 on $mux $procmux$120621. + dead port 1/2 on $mux $procmux$120624. + dead port 2/2 on $mux $procmux$120627. + dead port 1/2 on $mux $procmux$12064. + dead port 1/2 on $mux $procmux$120660. + dead port 1/2 on $mux $procmux$120663. + dead port 1/2 on $mux $procmux$120666. + dead port 1/2 on $mux $procmux$120669. + dead port 1/2 on $mux $procmux$12067. + dead port 1/2 on $mux $procmux$120672. + dead port 1/2 on $mux $procmux$120675. + dead port 1/2 on $mux $procmux$120678. + dead port 2/2 on $mux $procmux$120681. + dead port 1/2 on $mux $procmux$120687. + dead port 1/2 on $mux $procmux$120690. + dead port 1/2 on $mux $procmux$120693. + dead port 1/2 on $mux $procmux$120696. + dead port 1/2 on $mux $procmux$120699. + dead port 1/2 on $mux $procmux$12070. + dead port 1/2 on $mux $procmux$120702. + dead port 1/2 on $mux $procmux$120705. + dead port 2/2 on $mux $procmux$120708. + dead port 1/2 on $mux $procmux$120714. + dead port 1/2 on $mux $procmux$120717. + dead port 1/2 on $mux $procmux$120720. + dead port 1/2 on $mux $procmux$120723. + dead port 1/2 on $mux $procmux$120726. + dead port 1/2 on $mux $procmux$120729. + dead port 1/2 on $mux $procmux$12073. + dead port 1/2 on $mux $procmux$120732. + dead port 2/2 on $mux $procmux$120735. + dead port 1/2 on $mux $procmux$12076. + dead port 1/2 on $mux $procmux$12079. + dead port 1/2 on $mux $procmux$12082. + dead port 1/2 on $mux $procmux$120822. + dead port 1/2 on $mux $procmux$120825. + dead port 1/2 on $mux $procmux$120828. + dead port 1/2 on $mux $procmux$120831. + dead port 1/2 on $mux $procmux$120834. + dead port 1/2 on $mux $procmux$120837. + dead port 1/2 on $mux $procmux$120840. + dead port 2/2 on $mux $procmux$120843. + dead port 1/2 on $mux $procmux$120849. + dead port 1/2 on $mux $procmux$12085. + dead port 1/2 on $mux $procmux$120852. + dead port 1/2 on $mux $procmux$120855. + dead port 1/2 on $mux $procmux$120858. + dead port 1/2 on $mux $procmux$120861. + dead port 1/2 on $mux $procmux$120864. + dead port 1/2 on $mux $procmux$120867. + dead port 2/2 on $mux $procmux$120870. + dead port 1/2 on $mux $procmux$120876. + dead port 1/2 on $mux $procmux$120879. + dead port 1/2 on $mux $procmux$12088. + dead port 1/2 on $mux $procmux$120882. + dead port 1/2 on $mux $procmux$120885. + dead port 1/2 on $mux $procmux$120888. + dead port 1/2 on $mux $procmux$120891. + dead port 1/2 on $mux $procmux$120894. + dead port 2/2 on $mux $procmux$120897. + dead port 1/2 on $mux $procmux$12091. + dead port 1/2 on $mux $procmux$120930. + dead port 1/2 on $mux $procmux$120933. + dead port 1/2 on $mux $procmux$120936. + dead port 1/2 on $mux $procmux$120939. + dead port 1/2 on $mux $procmux$12094. + dead port 1/2 on $mux $procmux$120942. + dead port 1/2 on $mux $procmux$120945. + dead port 1/2 on $mux $procmux$120948. + dead port 2/2 on $mux $procmux$120951. + dead port 1/2 on $mux $procmux$120955. + dead port 1/2 on $mux $procmux$120958. + dead port 1/2 on $mux $procmux$120961. + dead port 2/2 on $mux $procmux$120963. + dead port 1/2 on $mux $procmux$120966. + dead port 1/2 on $mux $procmux$120969. + dead port 1/2 on $mux $procmux$12097. + dead port 1/2 on $mux $procmux$120972. + dead port 1/2 on $mux $procmux$120975. + dead port 1/2 on $mux $procmux$120978. + dead port 1/2 on $mux $procmux$120981. + dead port 2/2 on $mux $procmux$120984. + dead port 1/2 on $mux $procmux$120991. + dead port 1/2 on $mux $procmux$120994. + dead port 2/2 on $mux $procmux$120996. + dead port 1/2 on $mux $procmux$120999. + dead port 1/2 on $mux $procmux$12100. + dead port 1/2 on $mux $procmux$121002. + dead port 1/2 on $mux $procmux$121005. + dead port 1/2 on $mux $procmux$121008. + dead port 1/2 on $mux $procmux$121011. + dead port 1/2 on $mux $procmux$121014. + dead port 2/2 on $mux $procmux$121017. + dead port 2/2 on $mux $procmux$12102. + dead port 1/2 on $mux $procmux$121024. + dead port 1/2 on $mux $procmux$121027. + dead port 2/2 on $mux $procmux$121029. + dead port 1/2 on $mux $procmux$121032. + dead port 1/2 on $mux $procmux$121035. + dead port 1/2 on $mux $procmux$121038. + dead port 1/2 on $mux $procmux$121041. + dead port 1/2 on $mux $procmux$121044. + dead port 1/2 on $mux $procmux$121047. + dead port 1/2 on $mux $procmux$12105. + dead port 2/2 on $mux $procmux$121050. + dead port 1/2 on $mux $procmux$121057. + dead port 1/2 on $mux $procmux$121060. + dead port 2/2 on $mux $procmux$121062. + dead port 1/2 on $mux $procmux$121065. + dead port 1/2 on $mux $procmux$121068. + dead port 1/2 on $mux $procmux$121071. + dead port 1/2 on $mux $procmux$121074. + dead port 1/2 on $mux $procmux$121077. + dead port 1/2 on $mux $procmux$12108. + dead port 1/2 on $mux $procmux$121080. + dead port 2/2 on $mux $procmux$121083. + dead port 1/2 on $mux $procmux$121090. + dead port 1/2 on $mux $procmux$121093. + dead port 2/2 on $mux $procmux$121095. + dead port 1/2 on $mux $procmux$121098. + dead port 1/2 on $mux $procmux$121101. + dead port 1/2 on $mux $procmux$121104. + dead port 1/2 on $mux $procmux$121107. + dead port 1/2 on $mux $procmux$12111. + dead port 1/2 on $mux $procmux$121110. + dead port 1/2 on $mux $procmux$121113. + dead port 2/2 on $mux $procmux$121116. + dead port 1/2 on $mux $procmux$121123. + dead port 1/2 on $mux $procmux$121126. + dead port 2/2 on $mux $procmux$121128. + dead port 1/2 on $mux $procmux$121131. + dead port 1/2 on $mux $procmux$121134. + dead port 1/2 on $mux $procmux$121137. + dead port 1/2 on $mux $procmux$12114. + dead port 1/2 on $mux $procmux$121140. + dead port 1/2 on $mux $procmux$121143. + dead port 1/2 on $mux $procmux$121146. + dead port 2/2 on $mux $procmux$121149. + dead port 1/2 on $mux $procmux$121156. + dead port 1/2 on $mux $procmux$121159. + dead port 2/2 on $mux $procmux$121161. + dead port 1/2 on $mux $procmux$121164. + dead port 1/2 on $mux $procmux$121167. + dead port 1/2 on $mux $procmux$12117. + dead port 1/2 on $mux $procmux$121170. + dead port 1/2 on $mux $procmux$121173. + dead port 1/2 on $mux $procmux$121176. + dead port 1/2 on $mux $procmux$121179. + dead port 2/2 on $mux $procmux$121182. + dead port 1/2 on $mux $procmux$121189. + dead port 1/2 on $mux $procmux$121192. + dead port 2/2 on $mux $procmux$121194. + dead port 1/2 on $mux $procmux$121197. + dead port 1/2 on $mux $procmux$12120. + dead port 1/2 on $mux $procmux$121200. + dead port 1/2 on $mux $procmux$121203. + dead port 1/2 on $mux $procmux$121206. + dead port 1/2 on $mux $procmux$121209. + dead port 1/2 on $mux $procmux$121212. + dead port 2/2 on $mux $procmux$121215. + dead port 1/2 on $mux $procmux$121222. + dead port 1/2 on $mux $procmux$121225. + dead port 2/2 on $mux $procmux$121227. + dead port 1/2 on $mux $procmux$12123. + dead port 1/2 on $mux $procmux$121230. + dead port 1/2 on $mux $procmux$121233. + dead port 1/2 on $mux $procmux$121236. + dead port 1/2 on $mux $procmux$121239. + dead port 1/2 on $mux $procmux$121242. + dead port 1/2 on $mux $procmux$121245. + dead port 2/2 on $mux $procmux$121248. + dead port 1/2 on $mux $procmux$121255. + dead port 1/2 on $mux $procmux$121258. + dead port 1/2 on $mux $procmux$12126. + dead port 2/2 on $mux $procmux$121260. + dead port 1/2 on $mux $procmux$121263. + dead port 1/2 on $mux $procmux$121266. + dead port 1/2 on $mux $procmux$121269. + dead port 1/2 on $mux $procmux$121272. + dead port 1/2 on $mux $procmux$121275. + dead port 1/2 on $mux $procmux$121278. + dead port 2/2 on $mux $procmux$121281. + dead port 1/2 on $mux $procmux$121288. + dead port 1/2 on $mux $procmux$12129. + dead port 1/2 on $mux $procmux$121291. + dead port 2/2 on $mux $procmux$121293. + dead port 1/2 on $mux $procmux$121296. + dead port 1/2 on $mux $procmux$121299. + dead port 1/2 on $mux $procmux$121302. + dead port 1/2 on $mux $procmux$121305. + dead port 1/2 on $mux $procmux$121308. + dead port 1/2 on $mux $procmux$121311. + dead port 2/2 on $mux $procmux$121314. + dead port 1/2 on $mux $procmux$12132. + dead port 1/2 on $mux $procmux$121321. + dead port 2/2 on $mux $procmux$121323. + dead port 1/2 on $mux $procmux$121326. + dead port 1/2 on $mux $procmux$121329. + dead port 1/2 on $mux $procmux$121332. + dead port 1/2 on $mux $procmux$121335. + dead port 1/2 on $mux $procmux$121338. + dead port 1/2 on $mux $procmux$121341. + dead port 2/2 on $mux $procmux$121344. + dead port 1/2 on $mux $procmux$12135. + dead port 1/2 on $mux $procmux$121351. + dead port 2/2 on $mux $procmux$121353. + dead port 1/2 on $mux $procmux$121356. + dead port 1/2 on $mux $procmux$121359. + dead port 1/2 on $mux $procmux$121362. + dead port 1/2 on $mux $procmux$121365. + dead port 1/2 on $mux $procmux$121368. + dead port 1/2 on $mux $procmux$121371. + dead port 2/2 on $mux $procmux$121374. + dead port 2/2 on $mux $procmux$12138. + dead port 1/2 on $mux $procmux$121381. + dead port 2/2 on $mux $procmux$121383. + dead port 1/2 on $mux $procmux$121386. + dead port 1/2 on $mux $procmux$121389. + dead port 1/2 on $mux $procmux$121392. + dead port 1/2 on $mux $procmux$121395. + dead port 1/2 on $mux $procmux$121398. + dead port 1/2 on $mux $procmux$121401. + dead port 2/2 on $mux $procmux$121404. + dead port 1/2 on $mux $procmux$121411. + dead port 2/2 on $mux $procmux$121413. + dead port 1/2 on $mux $procmux$121416. + dead port 1/2 on $mux $procmux$121419. + dead port 1/2 on $mux $procmux$121422. + dead port 1/2 on $mux $procmux$121425. + dead port 1/2 on $mux $procmux$121428. + dead port 1/2 on $mux $procmux$121431. + dead port 2/2 on $mux $procmux$121434. + dead port 1/2 on $mux $procmux$121441. + dead port 2/2 on $mux $procmux$121443. + dead port 1/2 on $mux $procmux$121446. + dead port 1/2 on $mux $procmux$121449. + dead port 1/2 on $mux $procmux$121452. + dead port 1/2 on $mux $procmux$121455. + dead port 1/2 on $mux $procmux$121458. + dead port 1/2 on $mux $procmux$12146. + dead port 1/2 on $mux $procmux$121461. + dead port 2/2 on $mux $procmux$121464. + dead port 1/2 on $mux $procmux$121471. + dead port 2/2 on $mux $procmux$121473. + dead port 1/2 on $mux $procmux$121476. + dead port 1/2 on $mux $procmux$121479. + dead port 1/2 on $mux $procmux$121482. + dead port 1/2 on $mux $procmux$121485. + dead port 1/2 on $mux $procmux$121488. + dead port 1/2 on $mux $procmux$12149. + dead port 1/2 on $mux $procmux$121491. + dead port 2/2 on $mux $procmux$121494. + dead port 2/2 on $mux $procmux$121498. + dead port 1/2 on $mux $procmux$121501. + dead port 2/2 on $mux $procmux$121503. + dead port 1/2 on $mux $procmux$121506. + dead port 1/2 on $mux $procmux$121509. + dead port 1/2 on $mux $procmux$121512. + dead port 1/2 on $mux $procmux$121515. + dead port 1/2 on $mux $procmux$121518. + dead port 1/2 on $mux $procmux$12152. + dead port 1/2 on $mux $procmux$121521. + dead port 2/2 on $mux $procmux$121524. + dead port 1/2 on $mux $procmux$12155. + dead port 1/2 on $mux $procmux$12158. + dead port 1/2 on $mux $procmux$12161. + dead port 2/2 on $mux $procmux$12163. + dead port 1/2 on $mux $procmux$12166. + dead port 1/2 on $mux $procmux$12169. + dead port 1/2 on $mux $procmux$12172. + dead port 1/2 on $mux $procmux$12175. + dead port 1/2 on $mux $procmux$12178. + dead port 1/2 on $mux $procmux$12181. + dead port 1/2 on $mux $procmux$12184. + dead port 1/2 on $mux $procmux$12187. + dead port 1/2 on $mux $procmux$12190. + dead port 1/2 on $mux $procmux$12193. + dead port 1/2 on $mux $procmux$12196. + dead port 1/2 on $mux $procmux$12199. + dead port 1/2 on $mux $procmux$12202. + dead port 1/2 on $mux $procmux$12205. + dead port 1/2 on $mux $procmux$12208. + dead port 1/2 on $mux $procmux$12211. + dead port 2/2 on $mux $procmux$12213. + dead port 1/2 on $mux $procmux$12216. + dead port 1/2 on $mux $procmux$12219. + dead port 1/2 on $mux $procmux$12222. + dead port 1/2 on $mux $procmux$12225. + dead port 1/2 on $mux $procmux$12228. + dead port 1/2 on $mux $procmux$12231. + dead port 1/2 on $mux $procmux$12234. + dead port 1/2 on $mux $procmux$12237. + dead port 1/2 on $mux $procmux$12240. + dead port 1/2 on $mux $procmux$12243. + dead port 1/2 on $mux $procmux$12246. + dead port 2/2 on $mux $procmux$12249. + dead port 1/2 on $mux $procmux$12258. + dead port 2/2 on $mux $procmux$12260. + dead port 1/2 on $mux $procmux$12263. + dead port 1/2 on $mux $procmux$12266. + dead port 1/2 on $mux $procmux$12269. + dead port 1/2 on $mux $procmux$12272. + dead port 1/2 on $mux $procmux$12275. + dead port 2/2 on $mux $procmux$12277. + dead port 1/2 on $mux $procmux$12280. + dead port 1/2 on $mux $procmux$12283. + dead port 1/2 on $mux $procmux$12286. + dead port 1/2 on $mux $procmux$12289. + dead port 1/2 on $mux $procmux$12292. + dead port 1/2 on $mux $procmux$12295. + dead port 1/2 on $mux $procmux$12298. + dead port 1/2 on $mux $procmux$12301. + dead port 1/2 on $mux $procmux$12304. + dead port 1/2 on $mux $procmux$12307. + dead port 1/2 on $mux $procmux$12310. + dead port 1/2 on $mux $procmux$12313. + dead port 1/2 on $mux $procmux$12316. + dead port 1/2 on $mux $procmux$12319. + dead port 1/2 on $mux $procmux$12322. + dead port 1/2 on $mux $procmux$12325. + dead port 2/2 on $mux $procmux$12327. + dead port 1/2 on $mux $procmux$12330. + dead port 1/2 on $mux $procmux$12333. + dead port 1/2 on $mux $procmux$12336. + dead port 1/2 on $mux $procmux$12339. + dead port 1/2 on $mux $procmux$12342. + dead port 1/2 on $mux $procmux$12345. + dead port 1/2 on $mux $procmux$12348. + dead port 1/2 on $mux $procmux$12351. + dead port 1/2 on $mux $procmux$12354. + dead port 1/2 on $mux $procmux$12357. + dead port 1/2 on $mux $procmux$12360. + dead port 2/2 on $mux $procmux$12363. + dead port 1/2 on $mux $procmux$12372. + dead port 2/2 on $mux $procmux$12374. + dead port 1/2 on $mux $procmux$12377. + dead port 1/2 on $mux $procmux$12380. + dead port 1/2 on $mux $procmux$123819. + dead port 1/2 on $mux $procmux$123822. + dead port 1/2 on $mux $procmux$123825. + dead port 1/2 on $mux $procmux$123828. + dead port 1/2 on $mux $procmux$12383. + dead port 1/2 on $mux $procmux$123831. + dead port 1/2 on $mux $procmux$123834. + dead port 2/2 on $mux $procmux$123837. + dead port 1/2 on $mux $procmux$123843. + dead port 1/2 on $mux $procmux$123846. + dead port 1/2 on $mux $procmux$123849. + dead port 1/2 on $mux $procmux$123852. + dead port 1/2 on $mux $procmux$123855. + dead port 1/2 on $mux $procmux$123858. + dead port 1/2 on $mux $procmux$12386. + dead port 2/2 on $mux $procmux$123861. + dead port 1/2 on $mux $procmux$12389. + dead port 1/2 on $mux $procmux$123891. + dead port 1/2 on $mux $procmux$123894. + dead port 1/2 on $mux $procmux$123897. + dead port 1/2 on $mux $procmux$123900. + dead port 1/2 on $mux $procmux$123903. + dead port 1/2 on $mux $procmux$123906. + dead port 2/2 on $mux $procmux$123909. + dead port 2/2 on $mux $procmux$12391. + dead port 1/2 on $mux $procmux$123915. + dead port 1/2 on $mux $procmux$123918. + dead port 1/2 on $mux $procmux$123921. + dead port 1/2 on $mux $procmux$123924. + dead port 1/2 on $mux $procmux$123927. + dead port 1/2 on $mux $procmux$123930. + dead port 2/2 on $mux $procmux$123933. + dead port 1/2 on $mux $procmux$123939. + dead port 1/2 on $mux $procmux$12394. + dead port 1/2 on $mux $procmux$123942. + dead port 1/2 on $mux $procmux$123945. + dead port 1/2 on $mux $procmux$123948. + dead port 1/2 on $mux $procmux$123951. + dead port 1/2 on $mux $procmux$123954. + dead port 2/2 on $mux $procmux$123957. + dead port 1/2 on $mux $procmux$123963. + dead port 1/2 on $mux $procmux$123966. + dead port 1/2 on $mux $procmux$123969. + dead port 1/2 on $mux $procmux$12397. + dead port 1/2 on $mux $procmux$123972. + dead port 1/2 on $mux $procmux$123975. + dead port 1/2 on $mux $procmux$123978. + dead port 2/2 on $mux $procmux$123981. + dead port 1/2 on $mux $procmux$123987. + dead port 1/2 on $mux $procmux$123990. + dead port 1/2 on $mux $procmux$123993. + dead port 1/2 on $mux $procmux$123996. + dead port 1/2 on $mux $procmux$123999. + dead port 1/2 on $mux $procmux$12400. + dead port 1/2 on $mux $procmux$124002. + dead port 2/2 on $mux $procmux$124005. + dead port 1/2 on $mux $procmux$124011. + dead port 1/2 on $mux $procmux$124014. + dead port 1/2 on $mux $procmux$124017. + dead port 1/2 on $mux $procmux$124020. + dead port 1/2 on $mux $procmux$124023. + dead port 1/2 on $mux $procmux$124026. + dead port 2/2 on $mux $procmux$124029. + dead port 1/2 on $mux $procmux$12403. + dead port 1/2 on $mux $procmux$124035. + dead port 1/2 on $mux $procmux$124038. + dead port 1/2 on $mux $procmux$124041. + dead port 1/2 on $mux $procmux$124044. + dead port 1/2 on $mux $procmux$124047. + dead port 1/2 on $mux $procmux$124050. + dead port 2/2 on $mux $procmux$124053. + dead port 1/2 on $mux $procmux$12406. + dead port 1/2 on $mux $procmux$12409. + dead port 1/2 on $mux $procmux$124107. + dead port 1/2 on $mux $procmux$124110. + dead port 1/2 on $mux $procmux$124113. + dead port 1/2 on $mux $procmux$124116. + dead port 1/2 on $mux $procmux$124119. + dead port 1/2 on $mux $procmux$12412. + dead port 1/2 on $mux $procmux$124122. + dead port 2/2 on $mux $procmux$124125. + dead port 1/2 on $mux $procmux$124131. + dead port 1/2 on $mux $procmux$124134. + dead port 1/2 on $mux $procmux$124137. + dead port 1/2 on $mux $procmux$124140. + dead port 1/2 on $mux $procmux$124143. + dead port 1/2 on $mux $procmux$124146. + dead port 2/2 on $mux $procmux$124149. + dead port 1/2 on $mux $procmux$12415. + dead port 1/2 on $mux $procmux$124155. + dead port 1/2 on $mux $procmux$124158. + dead port 1/2 on $mux $procmux$124161. + dead port 1/2 on $mux $procmux$124164. + dead port 1/2 on $mux $procmux$124167. + dead port 1/2 on $mux $procmux$124170. + dead port 2/2 on $mux $procmux$124173. + dead port 1/2 on $mux $procmux$124179. + dead port 1/2 on $mux $procmux$12418. + dead port 1/2 on $mux $procmux$124182. + dead port 1/2 on $mux $procmux$124185. + dead port 1/2 on $mux $procmux$124188. + dead port 1/2 on $mux $procmux$124191. + dead port 1/2 on $mux $procmux$124194. + dead port 2/2 on $mux $procmux$124197. + dead port 1/2 on $mux $procmux$124203. + dead port 1/2 on $mux $procmux$124206. + dead port 1/2 on $mux $procmux$124209. + dead port 1/2 on $mux $procmux$12421. + dead port 1/2 on $mux $procmux$124212. + dead port 1/2 on $mux $procmux$124215. + dead port 1/2 on $mux $procmux$124218. + dead port 2/2 on $mux $procmux$124221. + dead port 1/2 on $mux $procmux$124227. + dead port 1/2 on $mux $procmux$124230. + dead port 1/2 on $mux $procmux$124233. + dead port 1/2 on $mux $procmux$124236. + dead port 1/2 on $mux $procmux$124239. + dead port 1/2 on $mux $procmux$12424. + dead port 1/2 on $mux $procmux$124242. + dead port 2/2 on $mux $procmux$124245. + dead port 1/2 on $mux $procmux$124251. + dead port 1/2 on $mux $procmux$124254. + dead port 1/2 on $mux $procmux$124257. + dead port 1/2 on $mux $procmux$124260. + dead port 1/2 on $mux $procmux$124263. + dead port 1/2 on $mux $procmux$124266. + dead port 2/2 on $mux $procmux$124269. + dead port 1/2 on $mux $procmux$12427. + dead port 1/2 on $mux $procmux$124275. + dead port 1/2 on $mux $procmux$124278. + dead port 1/2 on $mux $procmux$124281. + dead port 1/2 on $mux $procmux$124284. + dead port 1/2 on $mux $procmux$124287. + dead port 1/2 on $mux $procmux$124290. + dead port 2/2 on $mux $procmux$124293. + dead port 1/2 on $mux $procmux$124299. + dead port 1/2 on $mux $procmux$12430. + dead port 1/2 on $mux $procmux$124302. + dead port 1/2 on $mux $procmux$124305. + dead port 1/2 on $mux $procmux$124308. + dead port 1/2 on $mux $procmux$124311. + dead port 1/2 on $mux $procmux$124314. + dead port 2/2 on $mux $procmux$124317. + dead port 1/2 on $mux $procmux$124323. + dead port 1/2 on $mux $procmux$124326. + dead port 1/2 on $mux $procmux$124329. + dead port 1/2 on $mux $procmux$12433. + dead port 1/2 on $mux $procmux$124332. + dead port 1/2 on $mux $procmux$124335. + dead port 1/2 on $mux $procmux$124338. + dead port 2/2 on $mux $procmux$124341. + dead port 1/2 on $mux $procmux$12436. + dead port 1/2 on $mux $procmux$124371. + dead port 1/2 on $mux $procmux$124374. + dead port 1/2 on $mux $procmux$124377. + dead port 1/2 on $mux $procmux$124380. + dead port 1/2 on $mux $procmux$124383. + dead port 1/2 on $mux $procmux$124386. + dead port 2/2 on $mux $procmux$124389. + dead port 1/2 on $mux $procmux$12439. + dead port 1/2 on $mux $procmux$124395. + dead port 1/2 on $mux $procmux$124398. + dead port 1/2 on $mux $procmux$124401. + dead port 1/2 on $mux $procmux$124404. + dead port 1/2 on $mux $procmux$124407. + dead port 2/2 on $mux $procmux$12441. + dead port 1/2 on $mux $procmux$124410. + dead port 2/2 on $mux $procmux$124413. + dead port 1/2 on $mux $procmux$124419. + dead port 1/2 on $mux $procmux$124422. + dead port 1/2 on $mux $procmux$124425. + dead port 1/2 on $mux $procmux$124428. + dead port 1/2 on $mux $procmux$124431. + dead port 1/2 on $mux $procmux$124434. + dead port 2/2 on $mux $procmux$124437. + dead port 1/2 on $mux $procmux$12444. + dead port 1/2 on $mux $procmux$12447. + dead port 1/2 on $mux $procmux$12450. + dead port 1/2 on $mux $procmux$124515. + dead port 1/2 on $mux $procmux$124518. + dead port 1/2 on $mux $procmux$124521. + dead port 1/2 on $mux $procmux$124524. + dead port 1/2 on $mux $procmux$124527. + dead port 1/2 on $mux $procmux$12453. + dead port 1/2 on $mux $procmux$124530. + dead port 2/2 on $mux $procmux$124533. + dead port 1/2 on $mux $procmux$124539. + dead port 1/2 on $mux $procmux$124542. + dead port 1/2 on $mux $procmux$124545. + dead port 1/2 on $mux $procmux$124548. + dead port 1/2 on $mux $procmux$124551. + dead port 1/2 on $mux $procmux$124554. + dead port 2/2 on $mux $procmux$124557. + dead port 1/2 on $mux $procmux$12456. + dead port 1/2 on $mux $procmux$124563. + dead port 1/2 on $mux $procmux$124566. + dead port 1/2 on $mux $procmux$124569. + dead port 1/2 on $mux $procmux$124572. + dead port 1/2 on $mux $procmux$124575. + dead port 1/2 on $mux $procmux$124578. + dead port 2/2 on $mux $procmux$124581. + dead port 1/2 on $mux $procmux$124587. + dead port 1/2 on $mux $procmux$12459. + dead port 1/2 on $mux $procmux$124590. + dead port 1/2 on $mux $procmux$124593. + dead port 1/2 on $mux $procmux$124596. + dead port 1/2 on $mux $procmux$124599. + dead port 1/2 on $mux $procmux$124602. + dead port 2/2 on $mux $procmux$124605. + dead port 1/2 on $mux $procmux$124611. + dead port 1/2 on $mux $procmux$124614. + dead port 1/2 on $mux $procmux$124617. + dead port 1/2 on $mux $procmux$12462. + dead port 1/2 on $mux $procmux$124620. + dead port 1/2 on $mux $procmux$124623. + dead port 1/2 on $mux $procmux$124626. + dead port 2/2 on $mux $procmux$124629. + dead port 1/2 on $mux $procmux$12465. + dead port 1/2 on $mux $procmux$12468. + dead port 1/2 on $mux $procmux$12471. + dead port 1/2 on $mux $procmux$12474. + dead port 2/2 on $mux $procmux$12477. + dead port 1/2 on $mux $procmux$12486. + dead port 2/2 on $mux $procmux$12488. + dead port 1/2 on $mux $procmux$12491. + dead port 1/2 on $mux $procmux$12494. + dead port 1/2 on $mux $procmux$12497. + dead port 1/2 on $mux $procmux$12500. + dead port 1/2 on $mux $procmux$12503. + dead port 2/2 on $mux $procmux$12505. + dead port 1/2 on $mux $procmux$12508. + dead port 1/2 on $mux $procmux$12511. + dead port 1/2 on $mux $procmux$12514. + dead port 1/2 on $mux $procmux$12517. + dead port 1/2 on $mux $procmux$12520. + dead port 1/2 on $mux $procmux$12523. + dead port 1/2 on $mux $procmux$12526. + dead port 1/2 on $mux $procmux$12529. + dead port 1/2 on $mux $procmux$12532. + dead port 1/2 on $mux $procmux$12535. + dead port 1/2 on $mux $procmux$12538. + dead port 1/2 on $mux $procmux$12541. + dead port 1/2 on $mux $procmux$12544. + dead port 1/2 on $mux $procmux$12547. + dead port 1/2 on $mux $procmux$12550. + dead port 1/2 on $mux $procmux$12553. + dead port 2/2 on $mux $procmux$12555. + dead port 1/2 on $mux $procmux$12558. + dead port 1/2 on $mux $procmux$12561. + dead port 1/2 on $mux $procmux$12564. + dead port 1/2 on $mux $procmux$12567. + dead port 1/2 on $mux $procmux$12570. + dead port 1/2 on $mux $procmux$12573. + dead port 1/2 on $mux $procmux$12576. + dead port 1/2 on $mux $procmux$12579. + dead port 1/2 on $mux $procmux$12582. + dead port 1/2 on $mux $procmux$12585. + dead port 1/2 on $mux $procmux$12588. + dead port 2/2 on $mux $procmux$12591. + dead port 2/2 on $mux $procmux$12599. + dead port 1/2 on $mux $procmux$12602. + dead port 1/2 on $mux $procmux$12605. + dead port 1/2 on $mux $procmux$12608. + dead port 1/2 on $mux $procmux$12611. + dead port 1/2 on $mux $procmux$12614. + dead port 2/2 on $mux $procmux$12616. + dead port 1/2 on $mux $procmux$12619. + dead port 1/2 on $mux $procmux$12622. + dead port 1/2 on $mux $procmux$12625. + dead port 1/2 on $mux $procmux$12628. + dead port 1/2 on $mux $procmux$12631. + dead port 1/2 on $mux $procmux$12634. + dead port 1/2 on $mux $procmux$12637. + dead port 1/2 on $mux $procmux$12640. + dead port 1/2 on $mux $procmux$12643. + dead port 1/2 on $mux $procmux$12646. + dead port 1/2 on $mux $procmux$126474. + dead port 1/2 on $mux $procmux$126477. + dead port 1/2 on $mux $procmux$126480. + dead port 1/2 on $mux $procmux$126483. + dead port 1/2 on $mux $procmux$126486. + dead port 2/2 on $mux $procmux$126489. + dead port 1/2 on $mux $procmux$12649. + dead port 1/2 on $mux $procmux$126495. + dead port 1/2 on $mux $procmux$126498. + dead port 1/2 on $mux $procmux$126501. + dead port 1/2 on $mux $procmux$126504. + dead port 1/2 on $mux $procmux$126507. + dead port 2/2 on $mux $procmux$126510. + dead port 1/2 on $mux $procmux$12652. + dead port 1/2 on $mux $procmux$12655. + dead port 1/2 on $mux $procmux$126558. + dead port 1/2 on $mux $procmux$126561. + dead port 1/2 on $mux $procmux$126564. + dead port 1/2 on $mux $procmux$126567. + dead port 1/2 on $mux $procmux$126570. + dead port 2/2 on $mux $procmux$126573. + dead port 1/2 on $mux $procmux$126579. + dead port 1/2 on $mux $procmux$12658. + dead port 1/2 on $mux $procmux$126582. + dead port 1/2 on $mux $procmux$126585. + dead port 1/2 on $mux $procmux$126588. + dead port 1/2 on $mux $procmux$126591. + dead port 2/2 on $mux $procmux$126594. + dead port 1/2 on $mux $procmux$126600. + dead port 1/2 on $mux $procmux$126603. + dead port 1/2 on $mux $procmux$126606. + dead port 1/2 on $mux $procmux$126609. + dead port 1/2 on $mux $procmux$12661. + dead port 1/2 on $mux $procmux$126612. + dead port 2/2 on $mux $procmux$126615. + dead port 1/2 on $mux $procmux$126621. + dead port 1/2 on $mux $procmux$126624. + dead port 1/2 on $mux $procmux$126627. + dead port 1/2 on $mux $procmux$126630. + dead port 1/2 on $mux $procmux$126633. + dead port 2/2 on $mux $procmux$126636. + dead port 1/2 on $mux $procmux$12664. + dead port 1/2 on $mux $procmux$126642. + dead port 1/2 on $mux $procmux$126645. + dead port 1/2 on $mux $procmux$126648. + dead port 1/2 on $mux $procmux$126651. + dead port 1/2 on $mux $procmux$126654. + dead port 2/2 on $mux $procmux$126657. + dead port 2/2 on $mux $procmux$12666. + dead port 1/2 on $mux $procmux$126663. + dead port 1/2 on $mux $procmux$126666. + dead port 1/2 on $mux $procmux$126669. + dead port 1/2 on $mux $procmux$126672. + dead port 1/2 on $mux $procmux$126675. + dead port 2/2 on $mux $procmux$126678. + dead port 1/2 on $mux $procmux$126684. + dead port 1/2 on $mux $procmux$126687. + dead port 1/2 on $mux $procmux$12669. + dead port 1/2 on $mux $procmux$126690. + dead port 1/2 on $mux $procmux$126693. + dead port 1/2 on $mux $procmux$126696. + dead port 2/2 on $mux $procmux$126699. + dead port 1/2 on $mux $procmux$12672. + dead port 1/2 on $mux $procmux$126747. + dead port 1/2 on $mux $procmux$12675. + dead port 1/2 on $mux $procmux$126750. + dead port 1/2 on $mux $procmux$126753. + dead port 1/2 on $mux $procmux$126756. + dead port 1/2 on $mux $procmux$126759. + dead port 2/2 on $mux $procmux$126762. + dead port 1/2 on $mux $procmux$126768. + dead port 1/2 on $mux $procmux$126771. + dead port 1/2 on $mux $procmux$126774. + dead port 1/2 on $mux $procmux$126777. + dead port 1/2 on $mux $procmux$12678. + dead port 1/2 on $mux $procmux$126780. + dead port 2/2 on $mux $procmux$126783. + dead port 1/2 on $mux $procmux$126789. + dead port 1/2 on $mux $procmux$126792. + dead port 1/2 on $mux $procmux$126795. + dead port 1/2 on $mux $procmux$126798. + dead port 1/2 on $mux $procmux$126801. + dead port 2/2 on $mux $procmux$126804. + dead port 1/2 on $mux $procmux$12681. + dead port 1/2 on $mux $procmux$126810. + dead port 1/2 on $mux $procmux$126813. + dead port 1/2 on $mux $procmux$126816. + dead port 1/2 on $mux $procmux$126819. + dead port 1/2 on $mux $procmux$126822. + dead port 2/2 on $mux $procmux$126825. + dead port 1/2 on $mux $procmux$126831. + dead port 1/2 on $mux $procmux$126834. + dead port 1/2 on $mux $procmux$126837. + dead port 1/2 on $mux $procmux$12684. + dead port 1/2 on $mux $procmux$126840. + dead port 1/2 on $mux $procmux$126843. + dead port 2/2 on $mux $procmux$126846. + dead port 1/2 on $mux $procmux$126852. + dead port 1/2 on $mux $procmux$126855. + dead port 1/2 on $mux $procmux$126858. + dead port 1/2 on $mux $procmux$126861. + dead port 1/2 on $mux $procmux$126864. + dead port 2/2 on $mux $procmux$126867. + dead port 1/2 on $mux $procmux$12687. + dead port 1/2 on $mux $procmux$126873. + dead port 1/2 on $mux $procmux$126876. + dead port 1/2 on $mux $procmux$126879. + dead port 1/2 on $mux $procmux$126882. + dead port 1/2 on $mux $procmux$126885. + dead port 2/2 on $mux $procmux$126888. + dead port 1/2 on $mux $procmux$126894. + dead port 1/2 on $mux $procmux$126897. + dead port 1/2 on $mux $procmux$12690. + dead port 1/2 on $mux $procmux$126900. + dead port 1/2 on $mux $procmux$126903. + dead port 1/2 on $mux $procmux$126906. + dead port 2/2 on $mux $procmux$126909. + dead port 1/2 on $mux $procmux$126915. + dead port 1/2 on $mux $procmux$126918. + dead port 1/2 on $mux $procmux$126921. + dead port 1/2 on $mux $procmux$126924. + dead port 1/2 on $mux $procmux$126927. + dead port 1/2 on $mux $procmux$12693. + dead port 2/2 on $mux $procmux$126930. + dead port 1/2 on $mux $procmux$126936. + dead port 1/2 on $mux $procmux$126939. + dead port 1/2 on $mux $procmux$126942. + dead port 1/2 on $mux $procmux$126945. + dead port 1/2 on $mux $procmux$126948. + dead port 2/2 on $mux $procmux$126951. + dead port 1/2 on $mux $procmux$12696. + dead port 1/2 on $mux $procmux$126978. + dead port 1/2 on $mux $procmux$126981. + dead port 1/2 on $mux $procmux$126984. + dead port 1/2 on $mux $procmux$126987. + dead port 1/2 on $mux $procmux$12699. + dead port 1/2 on $mux $procmux$126990. + dead port 2/2 on $mux $procmux$126993. + dead port 1/2 on $mux $procmux$126999. + dead port 1/2 on $mux $procmux$127002. + dead port 1/2 on $mux $procmux$127005. + dead port 1/2 on $mux $procmux$127008. + dead port 1/2 on $mux $procmux$127011. + dead port 2/2 on $mux $procmux$127014. + dead port 2/2 on $mux $procmux$12702. + dead port 1/2 on $mux $procmux$127020. + dead port 1/2 on $mux $procmux$127023. + dead port 1/2 on $mux $procmux$127026. + dead port 1/2 on $mux $procmux$127029. + dead port 1/2 on $mux $procmux$127032. + dead port 2/2 on $mux $procmux$127035. + dead port 2/2 on $mux $procmux$12710. + dead port 1/2 on $mux $procmux$127104. + dead port 1/2 on $mux $procmux$127107. + dead port 1/2 on $mux $procmux$127110. + dead port 1/2 on $mux $procmux$127113. + dead port 1/2 on $mux $procmux$127116. + dead port 2/2 on $mux $procmux$127119. + dead port 1/2 on $mux $procmux$127125. + dead port 1/2 on $mux $procmux$127128. + dead port 1/2 on $mux $procmux$12713. + dead port 1/2 on $mux $procmux$127131. + dead port 1/2 on $mux $procmux$127134. + dead port 1/2 on $mux $procmux$127137. + dead port 2/2 on $mux $procmux$127140. + dead port 1/2 on $mux $procmux$127146. + dead port 1/2 on $mux $procmux$127149. + dead port 1/2 on $mux $procmux$127152. + dead port 1/2 on $mux $procmux$127155. + dead port 1/2 on $mux $procmux$127158. + dead port 1/2 on $mux $procmux$12716. + dead port 2/2 on $mux $procmux$127161. + dead port 1/2 on $mux $procmux$127188. + dead port 1/2 on $mux $procmux$12719. + dead port 1/2 on $mux $procmux$127191. + dead port 1/2 on $mux $procmux$127194. + dead port 1/2 on $mux $procmux$127197. + dead port 1/2 on $mux $procmux$127200. + dead port 2/2 on $mux $procmux$127203. + dead port 1/2 on $mux $procmux$127209. + dead port 1/2 on $mux $procmux$127212. + dead port 1/2 on $mux $procmux$127215. + dead port 1/2 on $mux $procmux$127218. + dead port 1/2 on $mux $procmux$12722. + dead port 1/2 on $mux $procmux$127221. + dead port 2/2 on $mux $procmux$127224. + dead port 1/2 on $mux $procmux$127228. + dead port 1/2 on $mux $procmux$127231. + dead port 1/2 on $mux $procmux$127234. + dead port 1/2 on $mux $procmux$127237. + dead port 2/2 on $mux $procmux$127239. + dead port 1/2 on $mux $procmux$127242. + dead port 1/2 on $mux $procmux$127245. + dead port 1/2 on $mux $procmux$127248. + dead port 1/2 on $mux $procmux$12725. + dead port 1/2 on $mux $procmux$127251. + dead port 2/2 on $mux $procmux$127254. + dead port 1/2 on $mux $procmux$127258. + dead port 1/2 on $mux $procmux$127261. + dead port 1/2 on $mux $procmux$127264. + dead port 1/2 on $mux $procmux$127267. + dead port 2/2 on $mux $procmux$127269. + dead port 2/2 on $mux $procmux$12727. + dead port 1/2 on $mux $procmux$127272. + dead port 1/2 on $mux $procmux$127275. + dead port 1/2 on $mux $procmux$127278. + dead port 1/2 on $mux $procmux$127281. + dead port 2/2 on $mux $procmux$127284. + dead port 1/2 on $mux $procmux$127288. + dead port 1/2 on $mux $procmux$127291. + dead port 1/2 on $mux $procmux$127294. + dead port 1/2 on $mux $procmux$127297. + dead port 2/2 on $mux $procmux$127299. + dead port 1/2 on $mux $procmux$12730. + dead port 1/2 on $mux $procmux$127302. + dead port 1/2 on $mux $procmux$127305. + dead port 1/2 on $mux $procmux$127308. + dead port 1/2 on $mux $procmux$127311. + dead port 2/2 on $mux $procmux$127314. + dead port 1/2 on $mux $procmux$127321. + dead port 1/2 on $mux $procmux$127324. + dead port 1/2 on $mux $procmux$127327. + dead port 2/2 on $mux $procmux$127329. + dead port 1/2 on $mux $procmux$12733. + dead port 1/2 on $mux $procmux$127332. + dead port 1/2 on $mux $procmux$127335. + dead port 1/2 on $mux $procmux$127338. + dead port 1/2 on $mux $procmux$127341. + dead port 2/2 on $mux $procmux$127344. + dead port 1/2 on $mux $procmux$127351. + dead port 1/2 on $mux $procmux$127354. + dead port 1/2 on $mux $procmux$127357. + dead port 2/2 on $mux $procmux$127359. + dead port 1/2 on $mux $procmux$12736. + dead port 1/2 on $mux $procmux$127362. + dead port 1/2 on $mux $procmux$127365. + dead port 1/2 on $mux $procmux$127368. + dead port 1/2 on $mux $procmux$127371. + dead port 2/2 on $mux $procmux$127374. + dead port 1/2 on $mux $procmux$127381. + dead port 1/2 on $mux $procmux$127384. + dead port 1/2 on $mux $procmux$127387. + dead port 2/2 on $mux $procmux$127389. + dead port 1/2 on $mux $procmux$12739. + dead port 1/2 on $mux $procmux$127392. + dead port 1/2 on $mux $procmux$127395. + dead port 1/2 on $mux $procmux$127398. + dead port 1/2 on $mux $procmux$127401. + dead port 2/2 on $mux $procmux$127404. + dead port 1/2 on $mux $procmux$127411. + dead port 1/2 on $mux $procmux$127414. + dead port 1/2 on $mux $procmux$127417. + dead port 2/2 on $mux $procmux$127419. + dead port 1/2 on $mux $procmux$12742. + dead port 1/2 on $mux $procmux$127422. + dead port 1/2 on $mux $procmux$127425. + dead port 1/2 on $mux $procmux$127428. + dead port 1/2 on $mux $procmux$127431. + dead port 2/2 on $mux $procmux$127434. + dead port 1/2 on $mux $procmux$127441. + dead port 1/2 on $mux $procmux$127444. + dead port 1/2 on $mux $procmux$127447. + dead port 2/2 on $mux $procmux$127449. + dead port 1/2 on $mux $procmux$12745. + dead port 1/2 on $mux $procmux$127452. + dead port 1/2 on $mux $procmux$127455. + dead port 1/2 on $mux $procmux$127458. + dead port 1/2 on $mux $procmux$127461. + dead port 2/2 on $mux $procmux$127464. + dead port 1/2 on $mux $procmux$127471. + dead port 1/2 on $mux $procmux$127474. + dead port 1/2 on $mux $procmux$127477. + dead port 2/2 on $mux $procmux$127479. + dead port 1/2 on $mux $procmux$12748. + dead port 1/2 on $mux $procmux$127482. + dead port 1/2 on $mux $procmux$127485. + dead port 1/2 on $mux $procmux$127488. + dead port 1/2 on $mux $procmux$127491. + dead port 2/2 on $mux $procmux$127494. + dead port 1/2 on $mux $procmux$127501. + dead port 1/2 on $mux $procmux$127504. + dead port 1/2 on $mux $procmux$127507. + dead port 2/2 on $mux $procmux$127509. + dead port 1/2 on $mux $procmux$12751. + dead port 1/2 on $mux $procmux$127512. + dead port 1/2 on $mux $procmux$127515. + dead port 1/2 on $mux $procmux$127518. + dead port 1/2 on $mux $procmux$127521. + dead port 2/2 on $mux $procmux$127524. + dead port 1/2 on $mux $procmux$127531. + dead port 1/2 on $mux $procmux$127534. + dead port 1/2 on $mux $procmux$127537. + dead port 2/2 on $mux $procmux$127539. + dead port 1/2 on $mux $procmux$12754. + dead port 1/2 on $mux $procmux$127542. + dead port 1/2 on $mux $procmux$127545. + dead port 1/2 on $mux $procmux$127548. + dead port 1/2 on $mux $procmux$127551. + dead port 2/2 on $mux $procmux$127554. + dead port 1/2 on $mux $procmux$127561. + dead port 1/2 on $mux $procmux$127564. + dead port 1/2 on $mux $procmux$127567. + dead port 2/2 on $mux $procmux$127569. + dead port 1/2 on $mux $procmux$12757. + dead port 1/2 on $mux $procmux$127572. + dead port 1/2 on $mux $procmux$127575. + dead port 1/2 on $mux $procmux$127578. + dead port 1/2 on $mux $procmux$127581. + dead port 2/2 on $mux $procmux$127584. + dead port 1/2 on $mux $procmux$127591. + dead port 1/2 on $mux $procmux$127594. + dead port 1/2 on $mux $procmux$127597. + dead port 2/2 on $mux $procmux$127599. + dead port 1/2 on $mux $procmux$12760. + dead port 1/2 on $mux $procmux$127602. + dead port 1/2 on $mux $procmux$127605. + dead port 1/2 on $mux $procmux$127608. + dead port 1/2 on $mux $procmux$127611. + dead port 2/2 on $mux $procmux$127614. + dead port 1/2 on $mux $procmux$127621. + dead port 1/2 on $mux $procmux$127624. + dead port 2/2 on $mux $procmux$127626. + dead port 1/2 on $mux $procmux$127629. + dead port 1/2 on $mux $procmux$12763. + dead port 1/2 on $mux $procmux$127632. + dead port 1/2 on $mux $procmux$127635. + dead port 1/2 on $mux $procmux$127638. + dead port 2/2 on $mux $procmux$127641. + dead port 2/2 on $mux $procmux$127645. + dead port 1/2 on $mux $procmux$127648. + dead port 1/2 on $mux $procmux$127651. + dead port 2/2 on $mux $procmux$127653. + dead port 1/2 on $mux $procmux$127656. + dead port 1/2 on $mux $procmux$127659. + dead port 1/2 on $mux $procmux$12766. + dead port 1/2 on $mux $procmux$127662. + dead port 1/2 on $mux $procmux$127665. + dead port 2/2 on $mux $procmux$127668. + dead port 2/2 on $mux $procmux$127672. + dead port 1/2 on $mux $procmux$127675. + dead port 1/2 on $mux $procmux$127678. + dead port 2/2 on $mux $procmux$127680. + dead port 1/2 on $mux $procmux$127683. + dead port 1/2 on $mux $procmux$127686. + dead port 1/2 on $mux $procmux$127689. + dead port 1/2 on $mux $procmux$12769. + dead port 1/2 on $mux $procmux$127692. + dead port 2/2 on $mux $procmux$127695. + dead port 1/2 on $mux $procmux$127702. + dead port 1/2 on $mux $procmux$127705. + dead port 2/2 on $mux $procmux$127707. + dead port 1/2 on $mux $procmux$127710. + dead port 1/2 on $mux $procmux$127713. + dead port 1/2 on $mux $procmux$127716. + dead port 1/2 on $mux $procmux$127719. + dead port 1/2 on $mux $procmux$12772. + dead port 2/2 on $mux $procmux$127722. + dead port 1/2 on $mux $procmux$127729. + dead port 1/2 on $mux $procmux$127732. + dead port 2/2 on $mux $procmux$127734. + dead port 1/2 on $mux $procmux$127737. + dead port 1/2 on $mux $procmux$127740. + dead port 1/2 on $mux $procmux$127743. + dead port 1/2 on $mux $procmux$127746. + dead port 2/2 on $mux $procmux$127749. + dead port 1/2 on $mux $procmux$12775. + dead port 2/2 on $mux $procmux$127753. + dead port 1/2 on $mux $procmux$127756. + dead port 1/2 on $mux $procmux$127759. + dead port 2/2 on $mux $procmux$127761. + dead port 1/2 on $mux $procmux$127764. + dead port 1/2 on $mux $procmux$127767. + dead port 2/2 on $mux $procmux$12777. + dead port 1/2 on $mux $procmux$127770. + dead port 1/2 on $mux $procmux$127773. + dead port 2/2 on $mux $procmux$127776. + dead port 1/2 on $mux $procmux$127783. + dead port 1/2 on $mux $procmux$127786. + dead port 2/2 on $mux $procmux$127788. + dead port 1/2 on $mux $procmux$127791. + dead port 1/2 on $mux $procmux$127794. + dead port 1/2 on $mux $procmux$127797. + dead port 1/2 on $mux $procmux$12780. + dead port 1/2 on $mux $procmux$127800. + dead port 2/2 on $mux $procmux$127803. + dead port 1/2 on $mux $procmux$127810. + dead port 1/2 on $mux $procmux$127813. + dead port 2/2 on $mux $procmux$127815. + dead port 1/2 on $mux $procmux$127818. + dead port 1/2 on $mux $procmux$127821. + dead port 1/2 on $mux $procmux$127824. + dead port 1/2 on $mux $procmux$127827. + dead port 1/2 on $mux $procmux$12783. + dead port 2/2 on $mux $procmux$127830. + dead port 1/2 on $mux $procmux$127837. + dead port 1/2 on $mux $procmux$127840. + dead port 2/2 on $mux $procmux$127842. + dead port 1/2 on $mux $procmux$127845. + dead port 1/2 on $mux $procmux$127848. + dead port 1/2 on $mux $procmux$127851. + dead port 1/2 on $mux $procmux$127854. + dead port 2/2 on $mux $procmux$127857. + dead port 1/2 on $mux $procmux$12786. + dead port 1/2 on $mux $procmux$127864. + dead port 1/2 on $mux $procmux$127867. + dead port 2/2 on $mux $procmux$127869. + dead port 1/2 on $mux $procmux$127872. + dead port 1/2 on $mux $procmux$127875. + dead port 1/2 on $mux $procmux$127878. + dead port 1/2 on $mux $procmux$127881. + dead port 2/2 on $mux $procmux$127884. + dead port 1/2 on $mux $procmux$12789. + dead port 1/2 on $mux $procmux$12792. + dead port 1/2 on $mux $procmux$12795. + dead port 1/2 on $mux $procmux$12798. + dead port 1/2 on $mux $procmux$12801. + dead port 1/2 on $mux $procmux$12804. + dead port 1/2 on $mux $procmux$12807. + dead port 1/2 on $mux $procmux$12810. + dead port 2/2 on $mux $procmux$12813. + dead port 1/2 on $mux $procmux$128131. + dead port 2/2 on $mux $procmux$128133. + dead port 1/2 on $mux $procmux$128136. + dead port 1/2 on $mux $procmux$128139. + dead port 1/2 on $mux $procmux$128142. + dead port 1/2 on $mux $procmux$128145. + dead port 2/2 on $mux $procmux$128148. + dead port 1/2 on $mux $procmux$128155. + dead port 2/2 on $mux $procmux$128157. + dead port 1/2 on $mux $procmux$128160. + dead port 1/2 on $mux $procmux$128163. + dead port 1/2 on $mux $procmux$128166. + dead port 1/2 on $mux $procmux$128169. + dead port 2/2 on $mux $procmux$128172. + dead port 2/2 on $mux $procmux$12821. + dead port 1/2 on $mux $procmux$12824. + dead port 1/2 on $mux $procmux$12827. + dead port 1/2 on $mux $procmux$12830. + dead port 1/2 on $mux $procmux$12833. + dead port 2/2 on $mux $procmux$128349. + dead port 1/2 on $mux $procmux$128352. + dead port 1/2 on $mux $procmux$128355. + dead port 1/2 on $mux $procmux$128358. + dead port 1/2 on $mux $procmux$12836. + dead port 1/2 on $mux $procmux$128361. + dead port 2/2 on $mux $procmux$128364. + dead port 2/2 on $mux $procmux$128370. + dead port 1/2 on $mux $procmux$128373. + dead port 1/2 on $mux $procmux$128376. + dead port 1/2 on $mux $procmux$128379. + dead port 2/2 on $mux $procmux$12838. + dead port 1/2 on $mux $procmux$128382. + dead port 2/2 on $mux $procmux$128385. + dead port 1/2 on $mux $procmux$12841. + dead port 1/2 on $mux $procmux$12844. + dead port 1/2 on $mux $procmux$12847. + dead port 1/2 on $mux $procmux$12850. + dead port 1/2 on $mux $procmux$128502. + dead port 1/2 on $mux $procmux$128505. + dead port 1/2 on $mux $procmux$128508. + dead port 1/2 on $mux $procmux$128511. + dead port 2/2 on $mux $procmux$128514. + dead port 1/2 on $mux $procmux$128520. + dead port 1/2 on $mux $procmux$128523. + dead port 1/2 on $mux $procmux$128526. + dead port 1/2 on $mux $procmux$128529. + dead port 1/2 on $mux $procmux$12853. + dead port 2/2 on $mux $procmux$128532. + dead port 1/2 on $mux $procmux$12856. + dead port 1/2 on $mux $procmux$12859. + dead port 1/2 on $mux $procmux$12862. + dead port 1/2 on $mux $procmux$12865. + dead port 1/2 on $mux $procmux$12868. + dead port 1/2 on $mux $procmux$12871. + dead port 1/2 on $mux $procmux$12874. + dead port 1/2 on $mux $procmux$12877. + dead port 1/2 on $mux $procmux$12880. + dead port 1/2 on $mux $procmux$12883. + dead port 1/2 on $mux $procmux$12886. + dead port 2/2 on $mux $procmux$12888. + dead port 1/2 on $mux $procmux$12891. + dead port 1/2 on $mux $procmux$12894. + dead port 1/2 on $mux $procmux$12897. + dead port 1/2 on $mux $procmux$12900. + dead port 1/2 on $mux $procmux$12903. + dead port 1/2 on $mux $procmux$12906. + dead port 1/2 on $mux $procmux$12909. + dead port 1/2 on $mux $procmux$12912. + dead port 1/2 on $mux $procmux$12915. + dead port 1/2 on $mux $procmux$12918. + dead port 1/2 on $mux $procmux$12921. + dead port 2/2 on $mux $procmux$12924. + dead port 1/2 on $mux $procmux$12932. + dead port 1/2 on $mux $procmux$12935. + dead port 1/2 on $mux $procmux$12938. + dead port 1/2 on $mux $procmux$12941. + dead port 1/2 on $mux $procmux$12944. + dead port 2/2 on $mux $procmux$12946. + dead port 1/2 on $mux $procmux$12949. + dead port 1/2 on $mux $procmux$12952. + dead port 1/2 on $mux $procmux$12955. + dead port 1/2 on $mux $procmux$12958. + dead port 1/2 on $mux $procmux$12961. + dead port 1/2 on $mux $procmux$12964. + dead port 1/2 on $mux $procmux$12967. + dead port 1/2 on $mux $procmux$12970. + dead port 1/2 on $mux $procmux$12973. + dead port 1/2 on $mux $procmux$12976. + dead port 1/2 on $mux $procmux$12979. + dead port 1/2 on $mux $procmux$12982. + dead port 1/2 on $mux $procmux$12985. + dead port 1/2 on $mux $procmux$12988. + dead port 1/2 on $mux $procmux$12991. + dead port 1/2 on $mux $procmux$12994. + dead port 2/2 on $mux $procmux$12996. + dead port 1/2 on $mux $procmux$12999. + dead port 1/2 on $mux $procmux$13002. + dead port 1/2 on $mux $procmux$13005. + dead port 1/2 on $mux $procmux$130050. + dead port 1/2 on $mux $procmux$130053. + dead port 1/2 on $mux $procmux$130056. + dead port 1/2 on $mux $procmux$130059. + dead port 2/2 on $mux $procmux$130062. + dead port 1/2 on $mux $procmux$130068. + dead port 1/2 on $mux $procmux$130071. + dead port 1/2 on $mux $procmux$130074. + dead port 1/2 on $mux $procmux$130077. + dead port 1/2 on $mux $procmux$13008. + dead port 2/2 on $mux $procmux$130080. + dead port 1/2 on $mux $procmux$130104. + dead port 1/2 on $mux $procmux$130107. + dead port 1/2 on $mux $procmux$13011. + dead port 1/2 on $mux $procmux$130110. + dead port 1/2 on $mux $procmux$130113. + dead port 2/2 on $mux $procmux$130116. + dead port 1/2 on $mux $procmux$130122. + dead port 1/2 on $mux $procmux$130125. + dead port 1/2 on $mux $procmux$130128. + dead port 1/2 on $mux $procmux$130131. + dead port 2/2 on $mux $procmux$130134. + dead port 1/2 on $mux $procmux$13014. + dead port 1/2 on $mux $procmux$130140. + dead port 1/2 on $mux $procmux$130143. + dead port 1/2 on $mux $procmux$130146. + dead port 1/2 on $mux $procmux$130149. + dead port 2/2 on $mux $procmux$130152. + dead port 1/2 on $mux $procmux$130158. + dead port 1/2 on $mux $procmux$130161. + dead port 1/2 on $mux $procmux$130164. + dead port 1/2 on $mux $procmux$130167. + dead port 1/2 on $mux $procmux$13017. + dead port 2/2 on $mux $procmux$130170. + dead port 1/2 on $mux $procmux$130176. + dead port 1/2 on $mux $procmux$130179. + dead port 1/2 on $mux $procmux$130182. + dead port 1/2 on $mux $procmux$130185. + dead port 2/2 on $mux $procmux$130188. + dead port 1/2 on $mux $procmux$130194. + dead port 1/2 on $mux $procmux$130197. + dead port 1/2 on $mux $procmux$13020. + dead port 1/2 on $mux $procmux$130200. + dead port 1/2 on $mux $procmux$130203. + dead port 2/2 on $mux $procmux$130206. + dead port 1/2 on $mux $procmux$130212. + dead port 1/2 on $mux $procmux$130215. + dead port 1/2 on $mux $procmux$130218. + dead port 1/2 on $mux $procmux$130221. + dead port 2/2 on $mux $procmux$130224. + dead port 1/2 on $mux $procmux$13023. + dead port 1/2 on $mux $procmux$13026. + dead port 1/2 on $mux $procmux$130266. + dead port 1/2 on $mux $procmux$130269. + dead port 1/2 on $mux $procmux$130272. + dead port 1/2 on $mux $procmux$130275. + dead port 2/2 on $mux $procmux$130278. + dead port 1/2 on $mux $procmux$130284. + dead port 1/2 on $mux $procmux$130287. + dead port 1/2 on $mux $procmux$13029. + dead port 1/2 on $mux $procmux$130290. + dead port 1/2 on $mux $procmux$130293. + dead port 2/2 on $mux $procmux$130296. + dead port 1/2 on $mux $procmux$130302. + dead port 1/2 on $mux $procmux$130305. + dead port 1/2 on $mux $procmux$130308. + dead port 1/2 on $mux $procmux$130311. + dead port 2/2 on $mux $procmux$130314. + dead port 2/2 on $mux $procmux$13032. + dead port 1/2 on $mux $procmux$130320. + dead port 1/2 on $mux $procmux$130323. + dead port 1/2 on $mux $procmux$130326. + dead port 1/2 on $mux $procmux$130329. + dead port 2/2 on $mux $procmux$130332. + dead port 1/2 on $mux $procmux$130338. + dead port 1/2 on $mux $procmux$130341. + dead port 1/2 on $mux $procmux$130344. + dead port 1/2 on $mux $procmux$130347. + dead port 2/2 on $mux $procmux$130350. + dead port 1/2 on $mux $procmux$130356. + dead port 1/2 on $mux $procmux$130359. + dead port 1/2 on $mux $procmux$130362. + dead port 1/2 on $mux $procmux$130365. + dead port 2/2 on $mux $procmux$130368. + dead port 1/2 on $mux $procmux$130374. + dead port 1/2 on $mux $procmux$130377. + dead port 1/2 on $mux $procmux$130380. + dead port 1/2 on $mux $procmux$130383. + dead port 2/2 on $mux $procmux$130386. + dead port 1/2 on $mux $procmux$130392. + dead port 1/2 on $mux $procmux$130395. + dead port 1/2 on $mux $procmux$130398. + dead port 1/2 on $mux $procmux$13040. + dead port 1/2 on $mux $procmux$130401. + dead port 2/2 on $mux $procmux$130404. + dead port 1/2 on $mux $procmux$130428. + dead port 1/2 on $mux $procmux$13043. + dead port 1/2 on $mux $procmux$130431. + dead port 1/2 on $mux $procmux$130434. + dead port 1/2 on $mux $procmux$130437. + dead port 2/2 on $mux $procmux$130440. + dead port 1/2 on $mux $procmux$130446. + dead port 1/2 on $mux $procmux$130449. + dead port 1/2 on $mux $procmux$130452. + dead port 1/2 on $mux $procmux$130455. + dead port 2/2 on $mux $procmux$130458. + dead port 1/2 on $mux $procmux$13046. + dead port 1/2 on $mux $procmux$130464. + dead port 1/2 on $mux $procmux$130467. + dead port 1/2 on $mux $procmux$130470. + dead port 1/2 on $mux $procmux$130473. + dead port 2/2 on $mux $procmux$130476. + dead port 1/2 on $mux $procmux$13049. + dead port 1/2 on $mux $procmux$13052. + dead port 1/2 on $mux $procmux$130536. + dead port 1/2 on $mux $procmux$130539. + dead port 2/2 on $mux $procmux$13054. + dead port 1/2 on $mux $procmux$130542. + dead port 1/2 on $mux $procmux$130545. + dead port 2/2 on $mux $procmux$130548. + dead port 1/2 on $mux $procmux$130554. + dead port 1/2 on $mux $procmux$130557. + dead port 1/2 on $mux $procmux$130560. + dead port 1/2 on $mux $procmux$130563. + dead port 2/2 on $mux $procmux$130566. + dead port 1/2 on $mux $procmux$13057. + dead port 1/2 on $mux $procmux$130572. + dead port 1/2 on $mux $procmux$130575. + dead port 1/2 on $mux $procmux$130578. + dead port 1/2 on $mux $procmux$130581. + dead port 2/2 on $mux $procmux$130584. + dead port 1/2 on $mux $procmux$130590. + dead port 1/2 on $mux $procmux$130593. + dead port 1/2 on $mux $procmux$130596. + dead port 1/2 on $mux $procmux$130599. + dead port 1/2 on $mux $procmux$13060. + dead port 2/2 on $mux $procmux$130602. + dead port 1/2 on $mux $procmux$130608. + dead port 1/2 on $mux $procmux$130611. + dead port 1/2 on $mux $procmux$130614. + dead port 1/2 on $mux $procmux$130617. + dead port 2/2 on $mux $procmux$130620. + dead port 1/2 on $mux $procmux$13063. + dead port 1/2 on $mux $procmux$13066. + dead port 1/2 on $mux $procmux$13069. + dead port 1/2 on $mux $procmux$13072. + dead port 1/2 on $mux $procmux$13075. + dead port 1/2 on $mux $procmux$13078. + dead port 1/2 on $mux $procmux$13081. + dead port 1/2 on $mux $procmux$13084. + dead port 1/2 on $mux $procmux$13087. + dead port 1/2 on $mux $procmux$13090. + dead port 1/2 on $mux $procmux$13093. + dead port 1/2 on $mux $procmux$13096. + dead port 1/2 on $mux $procmux$13099. + dead port 1/2 on $mux $procmux$13102. + dead port 2/2 on $mux $procmux$13104. + dead port 1/2 on $mux $procmux$13107. + dead port 1/2 on $mux $procmux$13110. + dead port 1/2 on $mux $procmux$13113. + dead port 1/2 on $mux $procmux$13116. + dead port 1/2 on $mux $procmux$13119. + dead port 1/2 on $mux $procmux$13122. + dead port 1/2 on $mux $procmux$13125. + dead port 1/2 on $mux $procmux$13128. + dead port 1/2 on $mux $procmux$13131. + dead port 1/2 on $mux $procmux$13134. + dead port 1/2 on $mux $procmux$13137. + dead port 2/2 on $mux $procmux$13140. + dead port 1/2 on $mux $procmux$13148. + dead port 1/2 on $mux $procmux$13151. + dead port 1/2 on $mux $procmux$13154. + dead port 1/2 on $mux $procmux$13157. + dead port 1/2 on $mux $procmux$13160. + dead port 2/2 on $mux $procmux$13162. + dead port 1/2 on $mux $procmux$13165. + dead port 1/2 on $mux $procmux$13168. + dead port 1/2 on $mux $procmux$13171. + dead port 1/2 on $mux $procmux$13174. + dead port 1/2 on $mux $procmux$13177. + dead port 1/2 on $mux $procmux$13180. + dead port 1/2 on $mux $procmux$13183. + dead port 1/2 on $mux $procmux$13186. + dead port 1/2 on $mux $procmux$13189. + dead port 1/2 on $mux $procmux$13192. + dead port 1/2 on $mux $procmux$13195. + dead port 1/2 on $mux $procmux$13198. + dead port 1/2 on $mux $procmux$13201. + dead port 1/2 on $mux $procmux$13204. + dead port 1/2 on $mux $procmux$13207. + dead port 1/2 on $mux $procmux$13210. + dead port 2/2 on $mux $procmux$13212. + dead port 1/2 on $mux $procmux$13215. + dead port 1/2 on $mux $procmux$13218. + dead port 1/2 on $mux $procmux$132183. + dead port 1/2 on $mux $procmux$132186. + dead port 1/2 on $mux $procmux$132189. + dead port 2/2 on $mux $procmux$132192. + dead port 1/2 on $mux $procmux$132198. + dead port 1/2 on $mux $procmux$132201. + dead port 1/2 on $mux $procmux$132204. + dead port 2/2 on $mux $procmux$132207. + dead port 1/2 on $mux $procmux$13221. + dead port 1/2 on $mux $procmux$13224. + dead port 1/2 on $mux $procmux$132243. + dead port 1/2 on $mux $procmux$132246. + dead port 1/2 on $mux $procmux$132249. + dead port 2/2 on $mux $procmux$132252. + dead port 1/2 on $mux $procmux$132258. + dead port 1/2 on $mux $procmux$132261. + dead port 1/2 on $mux $procmux$132264. + dead port 2/2 on $mux $procmux$132267. + dead port 1/2 on $mux $procmux$13227. + dead port 1/2 on $mux $procmux$132273. + dead port 1/2 on $mux $procmux$132276. + dead port 1/2 on $mux $procmux$132279. + dead port 2/2 on $mux $procmux$132282. + dead port 1/2 on $mux $procmux$132288. + dead port 1/2 on $mux $procmux$132291. + dead port 1/2 on $mux $procmux$132294. + dead port 2/2 on $mux $procmux$132297. + dead port 1/2 on $mux $procmux$13230. + dead port 1/2 on $mux $procmux$132303. + dead port 1/2 on $mux $procmux$132306. + dead port 1/2 on $mux $procmux$132309. + dead port 2/2 on $mux $procmux$132312. + dead port 1/2 on $mux $procmux$132318. + dead port 1/2 on $mux $procmux$132321. + dead port 1/2 on $mux $procmux$132324. + dead port 2/2 on $mux $procmux$132327. + dead port 1/2 on $mux $procmux$13233. + dead port 1/2 on $mux $procmux$132333. + dead port 1/2 on $mux $procmux$132336. + dead port 1/2 on $mux $procmux$132339. + dead port 2/2 on $mux $procmux$132342. + dead port 1/2 on $mux $procmux$13236. + dead port 1/2 on $mux $procmux$132378. + dead port 1/2 on $mux $procmux$132381. + dead port 1/2 on $mux $procmux$132384. + dead port 2/2 on $mux $procmux$132387. + dead port 1/2 on $mux $procmux$13239. + dead port 1/2 on $mux $procmux$132393. + dead port 1/2 on $mux $procmux$132396. + dead port 1/2 on $mux $procmux$132399. + dead port 2/2 on $mux $procmux$132402. + dead port 1/2 on $mux $procmux$132408. + dead port 1/2 on $mux $procmux$132411. + dead port 1/2 on $mux $procmux$132414. + dead port 2/2 on $mux $procmux$132417. + dead port 1/2 on $mux $procmux$13242. + dead port 1/2 on $mux $procmux$132423. + dead port 1/2 on $mux $procmux$132426. + dead port 1/2 on $mux $procmux$132429. + dead port 2/2 on $mux $procmux$132432. + dead port 1/2 on $mux $procmux$132438. + dead port 1/2 on $mux $procmux$132441. + dead port 1/2 on $mux $procmux$132444. + dead port 2/2 on $mux $procmux$132447. + dead port 1/2 on $mux $procmux$13245. + dead port 1/2 on $mux $procmux$132453. + dead port 1/2 on $mux $procmux$132456. + dead port 1/2 on $mux $procmux$132459. + dead port 2/2 on $mux $procmux$132462. + dead port 1/2 on $mux $procmux$132468. + dead port 1/2 on $mux $procmux$132471. + dead port 1/2 on $mux $procmux$132474. + dead port 2/2 on $mux $procmux$132477. + dead port 2/2 on $mux $procmux$13248. + dead port 1/2 on $mux $procmux$132483. + dead port 1/2 on $mux $procmux$132486. + dead port 1/2 on $mux $procmux$132489. + dead port 2/2 on $mux $procmux$132492. + dead port 1/2 on $mux $procmux$132498. + dead port 1/2 on $mux $procmux$132501. + dead port 1/2 on $mux $procmux$132504. + dead port 2/2 on $mux $procmux$132507. + dead port 1/2 on $mux $procmux$132513. + dead port 1/2 on $mux $procmux$132516. + dead port 1/2 on $mux $procmux$132519. + dead port 2/2 on $mux $procmux$132522. + dead port 1/2 on $mux $procmux$132543. + dead port 1/2 on $mux $procmux$132546. + dead port 1/2 on $mux $procmux$132549. + dead port 2/2 on $mux $procmux$132552. + dead port 1/2 on $mux $procmux$132558. + dead port 1/2 on $mux $procmux$13256. + dead port 1/2 on $mux $procmux$132561. + dead port 1/2 on $mux $procmux$132564. + dead port 2/2 on $mux $procmux$132567. + dead port 1/2 on $mux $procmux$132573. + dead port 1/2 on $mux $procmux$132576. + dead port 1/2 on $mux $procmux$132579. + dead port 2/2 on $mux $procmux$132582. + dead port 1/2 on $mux $procmux$13259. + dead port 1/2 on $mux $procmux$13262. + dead port 1/2 on $mux $procmux$132633. + dead port 1/2 on $mux $procmux$132636. + dead port 1/2 on $mux $procmux$132639. + dead port 2/2 on $mux $procmux$132642. + dead port 1/2 on $mux $procmux$132648. + dead port 1/2 on $mux $procmux$13265. + dead port 1/2 on $mux $procmux$132651. + dead port 1/2 on $mux $procmux$132654. + dead port 2/2 on $mux $procmux$132657. + dead port 1/2 on $mux $procmux$132663. + dead port 1/2 on $mux $procmux$132666. + dead port 1/2 on $mux $procmux$132669. + dead port 2/2 on $mux $procmux$132672. + dead port 1/2 on $mux $procmux$13268. + dead port 1/2 on $mux $procmux$132693. + dead port 1/2 on $mux $procmux$132696. + dead port 1/2 on $mux $procmux$132699. + dead port 2/2 on $mux $procmux$13270. + dead port 2/2 on $mux $procmux$132702. + dead port 1/2 on $mux $procmux$132708. + dead port 1/2 on $mux $procmux$132711. + dead port 1/2 on $mux $procmux$132714. + dead port 2/2 on $mux $procmux$132717. + dead port 1/2 on $mux $procmux$132721. + dead port 1/2 on $mux $procmux$132724. + dead port 1/2 on $mux $procmux$132727. + dead port 1/2 on $mux $procmux$13273. + dead port 1/2 on $mux $procmux$132730. + dead port 2/2 on $mux $procmux$132732. + dead port 1/2 on $mux $procmux$132735. + dead port 1/2 on $mux $procmux$132738. + dead port 2/2 on $mux $procmux$132741. + dead port 1/2 on $mux $procmux$132745. + dead port 1/2 on $mux $procmux$132748. + dead port 1/2 on $mux $procmux$132751. + dead port 1/2 on $mux $procmux$132754. + dead port 2/2 on $mux $procmux$132756. + dead port 1/2 on $mux $procmux$132759. + dead port 1/2 on $mux $procmux$13276. + dead port 1/2 on $mux $procmux$132762. + dead port 2/2 on $mux $procmux$132765. + dead port 1/2 on $mux $procmux$132769. + dead port 1/2 on $mux $procmux$132772. + dead port 1/2 on $mux $procmux$132775. + dead port 1/2 on $mux $procmux$132778. + dead port 2/2 on $mux $procmux$132780. + dead port 1/2 on $mux $procmux$132783. + dead port 1/2 on $mux $procmux$132786. + dead port 2/2 on $mux $procmux$132789. + dead port 1/2 on $mux $procmux$13279. + dead port 1/2 on $mux $procmux$132796. + dead port 1/2 on $mux $procmux$132799. + dead port 1/2 on $mux $procmux$132802. + dead port 2/2 on $mux $procmux$132804. + dead port 1/2 on $mux $procmux$132807. + dead port 1/2 on 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$procmux$132882. + dead port 2/2 on $mux $procmux$132885. + dead port 1/2 on $mux $procmux$132892. + dead port 1/2 on $mux $procmux$132895. + dead port 1/2 on $mux $procmux$132898. + dead port 2/2 on $mux $procmux$132900. + dead port 1/2 on $mux $procmux$132903. + dead port 1/2 on $mux $procmux$132906. + dead port 2/2 on $mux $procmux$132909. + dead port 1/2 on $mux $procmux$13291. + dead port 1/2 on $mux $procmux$132916. + dead port 1/2 on $mux $procmux$132919. + dead port 1/2 on $mux $procmux$132922. + dead port 2/2 on $mux $procmux$132924. + dead port 1/2 on $mux $procmux$132927. + dead port 1/2 on $mux $procmux$132930. + dead port 2/2 on $mux $procmux$132933. + dead port 1/2 on $mux $procmux$13294. + dead port 1/2 on $mux $procmux$132940. + dead port 1/2 on $mux $procmux$132943. + dead port 1/2 on $mux $procmux$132946. + dead port 2/2 on $mux $procmux$132948. + dead port 1/2 on $mux $procmux$132951. + dead port 1/2 on $mux $procmux$132954. + dead port 2/2 on $mux $procmux$132957. + dead port 1/2 on $mux $procmux$132964. + dead port 1/2 on $mux $procmux$132967. + dead port 1/2 on $mux $procmux$13297. + dead port 1/2 on $mux $procmux$132970. + dead port 2/2 on $mux $procmux$132972. + dead port 1/2 on $mux $procmux$132975. + dead port 1/2 on $mux $procmux$132978. + dead port 2/2 on $mux $procmux$132981. + dead port 1/2 on $mux $procmux$132988. + dead port 1/2 on $mux $procmux$132991. + dead port 1/2 on $mux $procmux$132994. + dead port 2/2 on $mux $procmux$132996. + dead port 1/2 on $mux $procmux$132999. + dead port 1/2 on $mux $procmux$13300. + dead port 1/2 on $mux $procmux$133002. + dead port 2/2 on $mux $procmux$133005. + dead port 1/2 on $mux $procmux$133012. + dead port 1/2 on $mux $procmux$133015. + dead port 1/2 on $mux $procmux$133018. + dead port 2/2 on $mux $procmux$133020. + dead port 1/2 on $mux $procmux$133023. + dead port 1/2 on $mux $procmux$133026. + dead port 2/2 on $mux $procmux$133029. + dead port 1/2 on $mux $procmux$13303. + dead port 1/2 on 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$procmux$133104. + dead port 1/2 on $mux $procmux$133107. + dead port 1/2 on $mux $procmux$133110. + dead port 2/2 on $mux $procmux$133113. + dead port 1/2 on $mux $procmux$13312. + dead port 1/2 on $mux $procmux$133120. + dead port 1/2 on $mux $procmux$133123. + dead port 2/2 on $mux $procmux$133125. + dead port 1/2 on $mux $procmux$133128. + dead port 1/2 on $mux $procmux$133131. + dead port 2/2 on $mux $procmux$133134. + dead port 2/2 on $mux $procmux$133138. + dead port 1/2 on $mux $procmux$133141. + dead port 1/2 on $mux $procmux$133144. + dead port 2/2 on $mux $procmux$133146. + dead port 1/2 on $mux $procmux$133149. + dead port 1/2 on $mux $procmux$13315. + dead port 1/2 on $mux $procmux$133152. + dead port 2/2 on $mux $procmux$133155. + dead port 1/2 on $mux $procmux$133162. + dead port 1/2 on $mux $procmux$133165. + dead port 2/2 on $mux $procmux$133167. + dead port 1/2 on $mux $procmux$133170. + dead port 1/2 on $mux $procmux$133173. + dead port 2/2 on $mux $procmux$133176. + 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dead port 1/2 on $mux $procmux$133497. + dead port 1/2 on $mux $procmux$13350. + dead port 2/2 on $mux $procmux$133500. + dead port 1/2 on $mux $procmux$13353. + dead port 1/2 on $mux $procmux$133543. + dead port 2/2 on $mux $procmux$133545. + dead port 1/2 on $mux $procmux$133548. + dead port 1/2 on $mux $procmux$133551. + dead port 2/2 on $mux $procmux$133554. + dead port 2/2 on $mux $procmux$13356. + dead port 1/2 on $mux $procmux$13364. + dead port 2/2 on $mux $procmux$133650. + dead port 1/2 on $mux $procmux$133653. + dead port 1/2 on $mux $procmux$133656. + dead port 2/2 on $mux $procmux$133659. + dead port 2/2 on $mux $procmux$133665. + dead port 1/2 on $mux $procmux$133668. + dead port 1/2 on $mux $procmux$13367. + dead port 1/2 on $mux $procmux$133671. + dead port 2/2 on $mux $procmux$133674. + dead port 1/2 on $mux $procmux$13370. + dead port 2/2 on $mux $procmux$133710. + dead port 1/2 on $mux $procmux$133713. + dead port 1/2 on $mux $procmux$133716. + dead port 2/2 on $mux $procmux$133719. + dead port 1/2 on $mux $procmux$13373. + dead port 2/2 on $mux $procmux$13375. + dead port 1/2 on $mux $procmux$133773. + dead port 1/2 on $mux $procmux$133776. + dead port 2/2 on $mux $procmux$133779. + dead port 1/2 on $mux $procmux$13378. + dead port 1/2 on $mux $procmux$133785. + dead port 1/2 on $mux $procmux$133788. + dead port 2/2 on $mux $procmux$133791. + dead port 1/2 on $mux $procmux$13381. + dead port 1/2 on $mux $procmux$133821. + dead port 1/2 on $mux $procmux$133824. + dead port 2/2 on $mux $procmux$133827. + dead port 1/2 on $mux $procmux$13384. + dead port 1/2 on $mux $procmux$13387. + dead port 1/2 on $mux $procmux$13390. + dead port 1/2 on $mux $procmux$13393. + dead port 1/2 on $mux $procmux$13396. + dead port 1/2 on $mux $procmux$13399. + dead port 1/2 on $mux $procmux$13402. + dead port 1/2 on $mux $procmux$13405. + dead port 1/2 on $mux $procmux$13408. + dead port 1/2 on $mux $procmux$13411. + dead port 1/2 on $mux $procmux$13414. + dead port 1/2 on $mux $procmux$13417. + dead port 1/2 on $mux $procmux$13420. + dead port 1/2 on $mux $procmux$13423. + dead port 2/2 on $mux $procmux$13425. + dead port 1/2 on $mux $procmux$13428. + dead port 1/2 on $mux $procmux$13431. + dead port 1/2 on $mux $procmux$13434. + dead port 1/2 on $mux $procmux$13437. + dead port 1/2 on $mux $procmux$13440. + dead port 1/2 on $mux $procmux$13443. + dead port 1/2 on $mux $procmux$13446. + dead port 1/2 on $mux $procmux$13449. + dead port 1/2 on $mux $procmux$13452. + dead port 1/2 on $mux $procmux$13455. + dead port 1/2 on $mux $procmux$13458. + dead port 2/2 on $mux $procmux$13461. + dead port 1/2 on $mux $procmux$13469. + dead port 1/2 on $mux $procmux$13472. + dead port 1/2 on $mux $procmux$13475. + dead port 1/2 on $mux $procmux$13478. + dead port 2/2 on $mux $procmux$13480. + dead port 1/2 on $mux $procmux$13483. + dead port 1/2 on $mux $procmux$13486. + dead port 1/2 on $mux $procmux$13489. + dead port 1/2 on $mux $procmux$13492. + dead port 1/2 on $mux $procmux$134937. + dead port 1/2 on $mux $procmux$134940. + dead port 2/2 on $mux $procmux$134943. + dead port 1/2 on $mux $procmux$134949. + dead port 1/2 on $mux $procmux$13495. + dead port 1/2 on $mux $procmux$134952. + dead port 2/2 on $mux $procmux$134955. + dead port 1/2 on $mux $procmux$134961. + dead port 1/2 on $mux $procmux$134964. + dead port 2/2 on $mux $procmux$134967. + dead port 1/2 on $mux $procmux$134973. + dead port 1/2 on $mux $procmux$134976. + dead port 2/2 on $mux $procmux$134979. + dead port 1/2 on $mux $procmux$13498. + dead port 1/2 on $mux $procmux$134985. + dead port 1/2 on $mux $procmux$134988. + dead port 2/2 on $mux $procmux$134991. + dead port 1/2 on $mux $procmux$134997. + dead port 1/2 on $mux $procmux$135000. + dead port 2/2 on $mux $procmux$135003. + dead port 1/2 on $mux $procmux$135009. + dead port 1/2 on $mux $procmux$13501. + dead port 1/2 on $mux $procmux$135012. + dead port 2/2 on $mux $procmux$135015. + dead port 1/2 on $mux $procmux$13504. + dead port 1/2 on $mux $procmux$135045. + dead port 1/2 on $mux $procmux$135048. + dead port 2/2 on $mux $procmux$135051. + dead port 1/2 on $mux $procmux$135057. + dead port 1/2 on $mux $procmux$135060. + dead port 2/2 on $mux $procmux$135063. + dead port 1/2 on $mux $procmux$135069. + dead port 1/2 on $mux $procmux$13507. + dead port 1/2 on $mux $procmux$135072. + dead port 2/2 on $mux $procmux$135075. + dead port 1/2 on $mux $procmux$135081. + dead port 1/2 on $mux $procmux$135084. + dead port 2/2 on $mux $procmux$135087. + dead port 1/2 on $mux $procmux$135093. + dead port 1/2 on $mux $procmux$135096. + dead port 2/2 on $mux $procmux$135099. + dead port 1/2 on $mux $procmux$13510. + dead port 1/2 on $mux $procmux$135105. + dead port 1/2 on $mux $procmux$135108. + dead port 2/2 on $mux $procmux$135111. + dead port 1/2 on $mux $procmux$135117. + dead port 1/2 on $mux $procmux$135120. + dead port 2/2 on $mux $procmux$135123. + dead port 1/2 on $mux $procmux$135129. + dead port 1/2 on $mux $procmux$13513. + dead port 1/2 on $mux $procmux$135132. + dead port 2/2 on $mux $procmux$135135. + dead port 1/2 on $mux $procmux$135141. + dead port 1/2 on $mux $procmux$135144. + dead port 2/2 on $mux $procmux$135147. + dead port 1/2 on $mux $procmux$135153. + dead port 1/2 on $mux $procmux$135156. + dead port 2/2 on $mux $procmux$135159. + dead port 1/2 on $mux $procmux$13516. + dead port 1/2 on $mux $procmux$135177. + dead port 1/2 on $mux $procmux$135180. + dead port 2/2 on $mux $procmux$135183. + dead port 1/2 on $mux $procmux$135189. + dead port 1/2 on $mux $procmux$13519. + dead port 1/2 on $mux $procmux$135192. + dead port 2/2 on $mux $procmux$135195. + dead port 1/2 on $mux $procmux$135201. + dead port 1/2 on $mux $procmux$135204. + dead port 2/2 on $mux $procmux$135207. + dead port 1/2 on $mux $procmux$13522. + dead port 1/2 on $mux $procmux$135249. + dead port 1/2 on $mux $procmux$13525. + dead port 1/2 on $mux $procmux$135252. + dead port 2/2 on $mux $procmux$135255. + dead port 1/2 on $mux $procmux$135261. + dead port 1/2 on $mux $procmux$135264. + dead port 2/2 on $mux $procmux$135267. + dead port 1/2 on $mux $procmux$135273. + dead port 1/2 on $mux $procmux$135276. + dead port 2/2 on $mux $procmux$135279. + dead port 1/2 on $mux $procmux$13528. + dead port 1/2 on $mux $procmux$135285. + dead port 1/2 on $mux $procmux$135288. + dead port 2/2 on $mux $procmux$135291. + dead port 1/2 on $mux $procmux$135296. + dead port 1/2 on $mux $procmux$135299. + dead port 2/2 on $mux $procmux$13530. + dead port 1/2 on $mux $procmux$135302. + dead port 1/2 on $mux $procmux$135305. + dead port 2/2 on $mux $procmux$135307. + dead port 1/2 on $mux $procmux$135310. + dead port 2/2 on $mux $procmux$135312. + dead port 1/2 on $mux $procmux$135315. + dead port 2/2 on $mux $procmux$135318. + dead port 1/2 on $mux $procmux$135323. + dead port 1/2 on $mux $procmux$135326. + dead port 1/2 on $mux $procmux$135329. + dead port 1/2 on $mux $procmux$13533. + dead port 1/2 on $mux $procmux$135332. + dead port 2/2 on $mux $procmux$135334. + dead port 1/2 on $mux $procmux$135337. + dead port 2/2 on $mux $procmux$135339. + dead port 1/2 on $mux $procmux$135342. + dead port 2/2 on $mux $procmux$135345. + dead port 1/2 on $mux $procmux$135350. + dead port 1/2 on $mux $procmux$135353. + dead port 1/2 on $mux $procmux$135356. + dead port 1/2 on $mux $procmux$135359. + dead port 1/2 on $mux $procmux$13536. + dead port 2/2 on $mux $procmux$135361. + dead port 1/2 on $mux $procmux$135364. + dead port 2/2 on $mux $procmux$135366. + dead port 1/2 on $mux $procmux$135369. + dead port 2/2 on $mux $procmux$135372. + dead port 1/2 on $mux $procmux$135380. + dead port 1/2 on $mux $procmux$135383. + dead port 1/2 on $mux $procmux$135386. + dead port 2/2 on $mux $procmux$135388. + dead port 1/2 on $mux $procmux$13539. + dead port 1/2 on $mux $procmux$135391. + dead port 2/2 on $mux $procmux$135393. + dead port 1/2 on $mux $procmux$135396. + dead port 2/2 on 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$procmux$135474. + dead port 1/2 on $mux $procmux$135477. + dead port 1/2 on $mux $procmux$13548. + dead port 2/2 on $mux $procmux$135480. + dead port 1/2 on $mux $procmux$135488. + dead port 1/2 on $mux $procmux$135491. + dead port 1/2 on $mux $procmux$135494. + dead port 2/2 on $mux $procmux$135496. + dead port 1/2 on $mux $procmux$135499. + dead port 2/2 on $mux $procmux$135501. + dead port 1/2 on $mux $procmux$135504. + dead port 2/2 on $mux $procmux$135507. + dead port 1/2 on $mux $procmux$13551. + dead port 1/2 on $mux $procmux$135515. + dead port 1/2 on $mux $procmux$135518. + dead port 1/2 on $mux $procmux$135521. + dead port 2/2 on $mux $procmux$135523. + dead port 1/2 on $mux $procmux$135526. + dead port 2/2 on $mux $procmux$135528. + dead port 1/2 on $mux $procmux$135531. + dead port 2/2 on $mux $procmux$135534. + dead port 1/2 on $mux $procmux$13554. + dead port 1/2 on $mux $procmux$135542. + dead port 1/2 on $mux $procmux$135545. + dead port 1/2 on $mux $procmux$135548. + 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$procmux$135695. + dead port 1/2 on $mux $procmux$135698. + dead port 1/2 on $mux $procmux$135701. + dead port 2/2 on $mux $procmux$135703. + dead port 1/2 on $mux $procmux$135706. + dead port 2/2 on $mux $procmux$135708. + dead port 1/2 on $mux $procmux$135711. + dead port 2/2 on $mux $procmux$135714. + dead port 1/2 on $mux $procmux$135722. + dead port 1/2 on $mux $procmux$135725. + dead port 2/2 on $mux $procmux$135727. + dead port 1/2 on $mux $procmux$135730. + dead port 2/2 on $mux $procmux$135732. + dead port 1/2 on $mux $procmux$135735. + dead port 2/2 on $mux $procmux$135738. + dead port 1/2 on $mux $procmux$13574. + dead port 1/2 on $mux $procmux$135746. + dead port 1/2 on $mux $procmux$135749. + dead port 2/2 on $mux $procmux$135751. + dead port 1/2 on $mux $procmux$135754. + dead port 2/2 on $mux $procmux$135756. + dead port 1/2 on $mux $procmux$135759. + dead port 2/2 on $mux $procmux$135762. + dead port 2/2 on $mux $procmux$135767. + dead port 1/2 on $mux $procmux$13577. + dead port 1/2 on $mux $procmux$135770. + dead port 1/2 on $mux $procmux$135773. + dead port 2/2 on $mux $procmux$135775. + dead port 1/2 on $mux $procmux$135778. + dead port 2/2 on $mux $procmux$135780. + dead port 1/2 on $mux $procmux$135783. + dead port 2/2 on $mux $procmux$135786. + dead port 1/2 on $mux $procmux$135794. + dead port 1/2 on $mux $procmux$135797. + dead port 2/2 on $mux $procmux$135799. + dead port 1/2 on $mux $procmux$13580. + dead port 1/2 on $mux $procmux$135802. + dead port 2/2 on $mux $procmux$135804. + dead port 1/2 on $mux $procmux$135807. + dead port 2/2 on $mux $procmux$135810. + dead port 1/2 on $mux $procmux$135818. + dead port 1/2 on $mux $procmux$135821. + dead port 2/2 on $mux $procmux$135823. + dead port 1/2 on $mux $procmux$135826. + dead port 2/2 on $mux $procmux$135828. + dead port 1/2 on $mux $procmux$13583. + dead port 1/2 on $mux $procmux$135831. + dead port 2/2 on $mux $procmux$135834. + dead port 1/2 on $mux $procmux$135842. + dead port 1/2 on $mux $procmux$135845. + dead port 2/2 on $mux $procmux$135847. + dead port 2/2 on $mux $procmux$13585. + dead port 1/2 on $mux $procmux$135850. + dead port 2/2 on $mux $procmux$135852. + dead port 1/2 on $mux $procmux$135855. + dead port 2/2 on $mux $procmux$135858. + dead port 1/2 on $mux $procmux$135866. + dead port 1/2 on $mux $procmux$135869. + dead port 2/2 on $mux $procmux$135871. + dead port 1/2 on $mux $procmux$135874. + dead port 2/2 on $mux $procmux$135876. + dead port 1/2 on $mux $procmux$135879. + dead port 1/2 on $mux $procmux$13588. + dead port 2/2 on $mux $procmux$135882. + dead port 1/2 on $mux $procmux$135890. + dead port 1/2 on $mux $procmux$135893. + dead port 1/2 on $mux $procmux$135896. + dead port 1/2 on $mux $procmux$135899. + dead port 2/2 on $mux $procmux$135901. + dead port 1/2 on $mux $procmux$135904. + dead port 2/2 on $mux $procmux$135906. + dead port 1/2 on $mux $procmux$135909. + dead port 1/2 on $mux $procmux$13591. + dead port 2/2 on $mux $procmux$135912. + dead port 1/2 on $mux $procmux$135920. + dead port 1/2 on $mux $procmux$135923. + dead port 1/2 on $mux $procmux$135926. + dead port 1/2 on $mux $procmux$135929. + dead port 2/2 on $mux $procmux$135931. + dead port 1/2 on $mux $procmux$135934. + dead port 2/2 on $mux $procmux$135936. + dead port 1/2 on $mux $procmux$135939. + dead port 1/2 on $mux $procmux$13594. + dead port 2/2 on $mux $procmux$135942. + dead port 1/2 on $mux $procmux$135950. + dead port 1/2 on $mux $procmux$135953. + dead port 1/2 on $mux $procmux$135956. + dead port 1/2 on $mux $procmux$135959. + dead port 2/2 on $mux $procmux$135961. + dead port 1/2 on $mux $procmux$135964. + dead port 2/2 on $mux $procmux$135966. + dead port 1/2 on $mux $procmux$135969. + dead port 1/2 on $mux $procmux$13597. + dead port 2/2 on $mux $procmux$135972. + dead port 1/2 on $mux $procmux$135980. + dead port 1/2 on $mux $procmux$135983. + dead port 1/2 on $mux $procmux$135986. + dead port 2/2 on $mux $procmux$135988. + dead port 1/2 on $mux $procmux$135991. + dead port 2/2 on $mux $procmux$135993. + dead port 1/2 on $mux $procmux$135996. + dead port 2/2 on $mux $procmux$135999. + dead port 1/2 on $mux $procmux$13600. + dead port 1/2 on $mux $procmux$136007. + dead port 1/2 on $mux $procmux$136010. + dead port 1/2 on $mux $procmux$136013. + dead port 2/2 on $mux $procmux$136015. + dead port 1/2 on $mux $procmux$136018. + dead port 2/2 on $mux $procmux$136020. + dead port 1/2 on $mux $procmux$136023. + dead port 2/2 on $mux $procmux$136026. + dead port 1/2 on $mux $procmux$13603. + dead port 1/2 on $mux $procmux$136034. + dead port 1/2 on $mux $procmux$136037. + dead port 1/2 on $mux $procmux$136040. + dead port 2/2 on $mux $procmux$136042. + dead port 1/2 on $mux $procmux$136045. + dead port 2/2 on $mux $procmux$136047. + dead port 1/2 on $mux $procmux$136050. + dead port 2/2 on $mux $procmux$136053. + dead port 1/2 on $mux $procmux$13606. + dead port 1/2 on $mux $procmux$136061. + dead port 1/2 on $mux $procmux$136064. + dead port 1/2 on $mux $procmux$136067. + dead port 2/2 on $mux $procmux$136069. + dead port 1/2 on $mux $procmux$136072. + dead port 2/2 on $mux $procmux$136074. + dead port 1/2 on $mux $procmux$136077. + dead port 2/2 on $mux $procmux$136080. + dead port 1/2 on $mux $procmux$136088. + dead port 1/2 on $mux $procmux$13609. + dead port 1/2 on $mux $procmux$136091. + dead port 1/2 on $mux $procmux$136094. + dead port 2/2 on $mux $procmux$136096. + dead port 1/2 on $mux $procmux$136099. + dead port 2/2 on $mux $procmux$136101. + dead port 1/2 on $mux $procmux$136104. + dead port 2/2 on $mux $procmux$136107. + dead port 1/2 on $mux $procmux$136115. + dead port 1/2 on $mux $procmux$136118. + dead port 1/2 on $mux $procmux$13612. + dead port 1/2 on $mux $procmux$136121. + dead port 2/2 on $mux $procmux$136123. + dead port 1/2 on $mux $procmux$136126. + dead port 2/2 on $mux $procmux$136128. + dead port 1/2 on $mux $procmux$136131. + dead port 2/2 on $mux $procmux$136134. + dead port 1/2 on $mux $procmux$136142. + dead port 1/2 on $mux $procmux$136145. + dead port 2/2 on $mux $procmux$136147. + dead port 1/2 on $mux $procmux$13615. + dead port 1/2 on $mux $procmux$136150. + dead port 2/2 on $mux $procmux$136152. + dead port 1/2 on $mux $procmux$136155. + dead port 2/2 on $mux $procmux$136158. + dead port 1/2 on $mux $procmux$136166. + dead port 1/2 on $mux $procmux$136169. + dead port 2/2 on $mux $procmux$136171. + dead port 1/2 on $mux $procmux$136174. + dead port 2/2 on $mux $procmux$136176. + dead port 1/2 on $mux $procmux$136179. + dead port 1/2 on $mux $procmux$13618. + dead port 2/2 on $mux $procmux$136182. + dead port 1/2 on $mux $procmux$13621. + dead port 1/2 on $mux $procmux$136214. + dead port 1/2 on $mux $procmux$136217. + dead port 2/2 on $mux $procmux$136219. + dead port 1/2 on $mux $procmux$136222. + dead port 2/2 on $mux $procmux$136224. + dead port 1/2 on $mux $procmux$136227. + dead port 2/2 on $mux $procmux$136230. + dead port 1/2 on $mux $procmux$136238. + dead port 1/2 on $mux $procmux$13624. + dead port 1/2 on $mux $procmux$136241. + dead port 2/2 on $mux $procmux$136243. + dead port 1/2 on $mux $procmux$136246. + dead port 2/2 on $mux $procmux$136248. + dead port 1/2 on $mux $procmux$136251. + dead port 2/2 on $mux $procmux$136254. + dead port 1/2 on $mux $procmux$13627. + dead port 1/2 on $mux $procmux$13630. + dead port 1/2 on $mux $procmux$13633. + dead port 2/2 on $mux $procmux$13635. + dead port 1/2 on $mux $procmux$13638. + dead port 1/2 on $mux $procmux$13641. + dead port 1/2 on $mux $procmux$13644. + dead port 1/2 on $mux $procmux$13647. + dead port 1/2 on $mux $procmux$136475. + dead port 2/2 on $mux $procmux$136477. + dead port 1/2 on $mux $procmux$136480. + dead port 2/2 on $mux $procmux$136482. + dead port 1/2 on $mux $procmux$136485. + dead port 2/2 on $mux $procmux$136488. + dead port 1/2 on $mux $procmux$136496. + dead port 2/2 on $mux $procmux$136498. + dead port 1/2 on $mux $procmux$13650. + dead port 1/2 on $mux $procmux$136501. + dead port 2/2 on $mux $procmux$136503. + dead port 1/2 on $mux $procmux$136506. + dead port 2/2 on $mux $procmux$136509. + dead port 1/2 on $mux $procmux$13653. + dead port 1/2 on $mux $procmux$136538. + dead port 2/2 on $mux $procmux$136540. + dead port 1/2 on $mux $procmux$136543. + dead port 2/2 on $mux $procmux$136545. + dead port 1/2 on $mux $procmux$136548. + dead port 2/2 on $mux $procmux$136551. + dead port 1/2 on $mux $procmux$136559. + dead port 1/2 on $mux $procmux$13656. + dead port 2/2 on $mux $procmux$136561. + dead port 1/2 on $mux $procmux$136564. + dead port 2/2 on $mux $procmux$136566. + dead port 1/2 on $mux $procmux$136569. + dead port 2/2 on $mux $procmux$136572. + dead port 1/2 on $mux $procmux$13659. + dead port 1/2 on $mux $procmux$136601. + dead port 2/2 on $mux $procmux$136603. + dead port 1/2 on $mux $procmux$136606. + dead port 2/2 on $mux $procmux$136608. + dead port 1/2 on $mux $procmux$136611. + dead port 2/2 on $mux $procmux$136614. + dead port 1/2 on $mux $procmux$13662. + dead port 1/2 on $mux $procmux$136622. + dead port 2/2 on $mux $procmux$136624. + dead port 1/2 on $mux $procmux$136627. + dead port 2/2 on $mux $procmux$136629. + dead port 1/2 on $mux $procmux$136632. + dead port 2/2 on $mux $procmux$136635. + dead port 1/2 on $mux $procmux$13665. + dead port 1/2 on $mux $procmux$13668. + dead port 2/2 on $mux $procmux$13671. + dead port 2/2 on $mux $procmux$136750. + dead port 1/2 on $mux $procmux$136753. + dead port 2/2 on $mux $procmux$136755. + dead port 1/2 on $mux $procmux$136758. + dead port 2/2 on $mux $procmux$136761. + dead port 2/2 on $mux $procmux$136768. + dead port 1/2 on $mux $procmux$136771. + dead port 2/2 on $mux $procmux$136773. + dead port 1/2 on $mux $procmux$136776. + dead port 2/2 on $mux $procmux$136779. + dead port 1/2 on $mux $procmux$13679. + dead port 2/2 on $mux $procmux$136804. + dead port 1/2 on $mux $procmux$136807. + dead port 2/2 on $mux $procmux$136809. + dead port 1/2 on $mux $procmux$136812. + dead port 2/2 on $mux $procmux$136815. + dead port 1/2 on $mux $procmux$13682. + dead port 2/2 on $mux $procmux$136822. + dead port 1/2 on $mux $procmux$136825. + dead port 2/2 on $mux $procmux$136827. + dead port 1/2 on $mux $procmux$136830. + dead port 2/2 on $mux $procmux$136833. + dead port 1/2 on $mux $procmux$13685. + dead port 2/2 on $mux $procmux$136858. + dead port 1/2 on $mux $procmux$136861. + dead port 2/2 on $mux $procmux$136863. + dead port 1/2 on $mux $procmux$136866. + dead port 2/2 on $mux $procmux$136869. + dead port 2/2 on $mux $procmux$136876. + dead port 1/2 on $mux $procmux$136879. + dead port 1/2 on $mux $procmux$13688. + dead port 2/2 on $mux $procmux$136881. + dead port 1/2 on $mux $procmux$136884. + dead port 2/2 on $mux $procmux$136887. + dead port 2/2 on $mux $procmux$13690. + dead port 1/2 on $mux $procmux$13693. + dead port 1/2 on $mux $procmux$136954. + dead port 2/2 on $mux $procmux$136956. + dead port 1/2 on $mux $procmux$136959. + dead port 1/2 on $mux $procmux$13696. + dead port 2/2 on $mux $procmux$136962. + dead port 1/2 on $mux $procmux$136969. + dead port 2/2 on $mux $procmux$136971. + dead port 1/2 on $mux $procmux$136974. + dead port 2/2 on $mux $procmux$136977. + dead port 1/2 on $mux $procmux$13699. + dead port 1/2 on $mux $procmux$136999. + dead port 2/2 on $mux $procmux$137001. + dead port 1/2 on $mux $procmux$137004. + dead port 2/2 on $mux $procmux$137007. + dead port 1/2 on $mux $procmux$137014. + dead port 2/2 on $mux $procmux$137016. + dead port 1/2 on $mux $procmux$137019. + dead port 1/2 on $mux $procmux$13702. + dead port 2/2 on $mux $procmux$137022. + dead port 1/2 on $mux $procmux$137044. + dead port 2/2 on $mux $procmux$137046. + dead port 1/2 on $mux $procmux$137049. + dead port 1/2 on $mux $procmux$13705. + dead port 2/2 on $mux $procmux$137052. + dead port 1/2 on $mux $procmux$137059. + dead port 2/2 on $mux $procmux$137061. + dead port 1/2 on $mux $procmux$137064. + dead port 2/2 on $mux $procmux$137067. + dead port 1/2 on $mux $procmux$13708. + dead port 1/2 on $mux $procmux$13711. + dead port 1/2 on $mux $procmux$13714. + dead port 2/2 on $mux $procmux$137169. + dead port 1/2 on $mux $procmux$13717. + dead port 1/2 on $mux $procmux$137172. + dead port 2/2 on $mux $procmux$137175. + dead port 2/2 on $mux $procmux$137181. + dead port 1/2 on $mux $procmux$137184. + dead port 2/2 on $mux $procmux$137187. + dead port 1/2 on $mux $procmux$13720. + dead port 2/2 on $mux $procmux$137205. + dead port 1/2 on $mux $procmux$137208. + dead port 2/2 on $mux $procmux$137211. + dead port 2/2 on $mux $procmux$137217. + dead port 1/2 on $mux $procmux$137220. + dead port 2/2 on $mux $procmux$137223. + dead port 1/2 on $mux $procmux$13723. + dead port 2/2 on $mux $procmux$137241. + dead port 1/2 on $mux $procmux$137244. + dead port 2/2 on $mux $procmux$137247. + dead port 2/2 on $mux $procmux$137253. + dead port 1/2 on $mux $procmux$137256. + dead port 2/2 on $mux $procmux$137259. + dead port 1/2 on $mux $procmux$13726. + dead port 1/2 on $mux $procmux$13729. + dead port 1/2 on $mux $procmux$137319. + dead port 1/2 on $mux $procmux$13732. + dead port 2/2 on $mux $procmux$137322. + dead port 1/2 on $mux $procmux$137328. + dead port 2/2 on $mux $procmux$137331. + dead port 1/2 on $mux $procmux$137346. + dead port 2/2 on $mux $procmux$137349. + dead port 1/2 on $mux $procmux$13735. + dead port 1/2 on $mux $procmux$137355. + dead port 2/2 on $mux $procmux$137358. + dead port 1/2 on $mux $procmux$137373. + dead port 2/2 on $mux $procmux$137376. + dead port 1/2 on $mux $procmux$13738. + dead port 1/2 on $mux $procmux$137382. + dead port 2/2 on $mux $procmux$137385. + dead port 2/2 on $mux $procmux$13740. + dead port 1/2 on $mux $procmux$13743. + dead port 1/2 on $mux $procmux$13746. + dead port 1/2 on $mux $procmux$13749. + dead port 1/2 on $mux $procmux$13752. + dead port 1/2 on $mux $procmux$13755. + dead port 1/2 on $mux $procmux$13758. + dead port 1/2 on $mux $procmux$13761. + dead port 1/2 on $mux $procmux$13764. + dead port 1/2 on $mux $procmux$13767. + dead port 1/2 on $mux $procmux$13770. + dead port 1/2 on $mux $procmux$13773. + dead port 2/2 on $mux $procmux$13776. + dead port 1/2 on $mux $procmux$13784. + dead port 1/2 on $mux $procmux$13787. + dead port 1/2 on $mux $procmux$13790. + dead port 2/2 on $mux $procmux$13792. + dead port 1/2 on $mux $procmux$13795. + dead port 1/2 on $mux $procmux$13798. + dead port 1/2 on $mux $procmux$13801. + dead port 1/2 on $mux $procmux$13804. + dead port 1/2 on $mux $procmux$13807. + dead port 1/2 on $mux $procmux$13810. + dead port 1/2 on $mux $procmux$13813. + dead port 1/2 on $mux $procmux$13816. + dead port 1/2 on $mux $procmux$13819. + dead port 1/2 on $mux $procmux$13822. + dead port 1/2 on $mux $procmux$13825. + dead port 1/2 on $mux $procmux$138255. + dead port 2/2 on $mux $procmux$138258. + dead port 1/2 on $mux $procmux$138264. + dead port 2/2 on $mux $procmux$138267. + dead port 1/2 on $mux $procmux$138273. + dead port 2/2 on $mux $procmux$138276. + dead port 1/2 on $mux $procmux$13828. + dead port 1/2 on $mux $procmux$138282. + dead port 2/2 on $mux $procmux$138285. + dead port 1/2 on $mux $procmux$138291. + dead port 2/2 on $mux $procmux$138294. + dead port 1/2 on $mux $procmux$138300. + dead port 2/2 on $mux $procmux$138303. + dead port 1/2 on $mux $procmux$138309. + dead port 1/2 on $mux $procmux$13831. + dead port 2/2 on $mux $procmux$138312. + dead port 1/2 on $mux $procmux$138336. + dead port 2/2 on $mux $procmux$138339. + dead port 1/2 on $mux $procmux$13834. + dead port 1/2 on $mux $procmux$138345. + dead port 2/2 on $mux $procmux$138348. + dead port 1/2 on $mux $procmux$138354. + dead port 2/2 on $mux $procmux$138357. + dead port 1/2 on $mux $procmux$138363. + dead port 2/2 on $mux $procmux$138366. + dead port 1/2 on $mux $procmux$13837. + dead port 1/2 on $mux $procmux$138372. + dead port 2/2 on $mux $procmux$138375. + dead port 1/2 on $mux $procmux$138381. + dead port 2/2 on $mux $procmux$138384. + dead port 1/2 on $mux $procmux$138390. + dead port 2/2 on $mux $procmux$138393. + dead port 1/2 on $mux $procmux$138399. + dead port 1/2 on $mux $procmux$13840. + dead port 2/2 on $mux $procmux$138402. + dead port 1/2 on $mux $procmux$138417. + dead port 2/2 on $mux $procmux$13842. + dead port 2/2 on $mux $procmux$138420. + dead port 1/2 on $mux $procmux$138426. + dead port 2/2 on $mux $procmux$138429. + dead port 1/2 on $mux $procmux$138435. + dead port 2/2 on $mux $procmux$138438. + dead port 1/2 on $mux $procmux$13845. + dead port 1/2 on $mux $procmux$138471. + dead port 2/2 on $mux $procmux$138474. + dead port 1/2 on $mux $procmux$13848. + dead port 1/2 on $mux $procmux$138480. + dead port 2/2 on $mux $procmux$138483. + dead port 1/2 on $mux $procmux$138489. + dead port 2/2 on $mux $procmux$138492. + dead port 1/2 on $mux $procmux$13851. + dead port 1/2 on $mux $procmux$13854. + dead port 1/2 on $mux $procmux$13857. + dead port 1/2 on $mux $procmux$13860. + dead port 1/2 on $mux $procmux$13863. + dead port 1/2 on $mux $procmux$13866. + dead port 1/2 on $mux $procmux$13869. + dead port 1/2 on $mux $procmux$13872. + dead port 1/2 on $mux $procmux$13875. + dead port 2/2 on $mux $procmux$13878. + dead port 1/2 on $mux $procmux$13886. + dead port 1/2 on $mux $procmux$13889. + dead port 1/2 on $mux $procmux$13892. + dead port 2/2 on $mux $procmux$13894. + dead port 1/2 on $mux $procmux$13897. + dead port 1/2 on $mux $procmux$13900. + dead port 1/2 on $mux $procmux$13903. + dead port 1/2 on $mux $procmux$13906. + dead port 1/2 on $mux $procmux$13909. + dead port 2/2 on $mux $procmux$139104. + dead port 2/2 on $mux $procmux$139110. + dead port 1/2 on $mux $procmux$13912. + dead port 2/2 on $mux $procmux$139128. + dead port 2/2 on $mux $procmux$139134. + dead port 2/2 on $mux $procmux$139140. + dead port 2/2 on $mux $procmux$139146. + dead port 1/2 on $mux $procmux$13915. + dead port 2/2 on $mux $procmux$139152. + dead port 2/2 on $mux $procmux$139158. + dead port 2/2 on $mux $procmux$139164. + dead port 1/2 on $mux $procmux$13918. + dead port 2/2 on $mux $procmux$139182. + dead port 2/2 on $mux $procmux$139188. + dead port 2/2 on $mux $procmux$139194. + dead port 2/2 on $mux $procmux$139200. + dead port 2/2 on $mux $procmux$139206. + dead port 1/2 on $mux $procmux$13921. + dead port 2/2 on $mux $procmux$139212. + dead port 2/2 on $mux $procmux$139218. + dead port 2/2 on $mux $procmux$139224. + dead port 2/2 on $mux $procmux$139230. + dead port 2/2 on $mux $procmux$139236. + dead port 1/2 on $mux $procmux$13924. + dead port 2/2 on $mux $procmux$139248. + dead port 2/2 on $mux $procmux$139254. + dead port 2/2 on $mux $procmux$139260. + dead port 1/2 on $mux $procmux$13927. + dead port 2/2 on $mux $procmux$139284. + dead port 2/2 on $mux $procmux$139290. + dead port 2/2 on $mux $procmux$139296. + dead port 1/2 on $mux $procmux$13930. + dead port 2/2 on $mux $procmux$139308. + dead port 2/2 on $mux $procmux$139314. + dead port 1/2 on $mux $procmux$13933. + dead port 1/2 on $mux $procmux$13936. + dead port 1/2 on $mux $procmux$13939. + dead port 1/2 on $mux $procmux$13942. + dead port 2/2 on $mux $procmux$13944. + dead port 1/2 on $mux $procmux$13947. + dead port 1/2 on $mux $procmux$13950. + dead port 1/2 on $mux $procmux$13953. + dead port 1/2 on $mux $procmux$13956. + dead port 1/2 on $mux $procmux$13959. + dead port 1/2 on $mux $procmux$13962. + dead port 1/2 on $mux $procmux$13965. + dead port 1/2 on $mux $procmux$13968. + dead port 1/2 on $mux $procmux$13971. + dead port 1/2 on $mux $procmux$13974. + dead port 1/2 on $mux $procmux$13977. + dead port 2/2 on $mux $procmux$13980. + dead port 1/2 on $mux $procmux$13988. + dead port 1/2 on $mux $procmux$13991. + dead port 1/2 on $mux $procmux$13994. + dead port 2/2 on $mux $procmux$13996. + dead port 1/2 on $mux $procmux$13999. + dead port 1/2 on $mux $procmux$14002. + dead port 1/2 on $mux $procmux$14005. + dead port 1/2 on $mux $procmux$14008. + dead port 1/2 on $mux $procmux$14011. + dead port 1/2 on $mux $procmux$14014. + dead port 1/2 on $mux $procmux$14017. + dead port 1/2 on $mux $procmux$14020. + dead port 1/2 on $mux $procmux$14023. + dead port 1/2 on $mux $procmux$14026. + dead port 1/2 on $mux $procmux$14029. + dead port 1/2 on $mux $procmux$14032. + dead port 1/2 on $mux $procmux$14035. + dead port 1/2 on $mux $procmux$14038. + dead port 1/2 on $mux $procmux$14041. + dead port 1/2 on $mux $procmux$14044. + dead port 2/2 on $mux $procmux$14046. + dead port 1/2 on $mux $procmux$14049. + dead port 1/2 on $mux $procmux$14052. + dead port 1/2 on $mux $procmux$14055. + dead port 1/2 on $mux $procmux$14058. + dead port 1/2 on $mux $procmux$14061. + dead port 1/2 on $mux $procmux$14064. + dead port 1/2 on $mux $procmux$14067. + dead port 1/2 on $mux $procmux$14070. + dead port 1/2 on $mux $procmux$14073. + dead port 1/2 on $mux $procmux$14076. + dead port 1/2 on $mux $procmux$14079. + dead port 2/2 on $mux $procmux$14082. + dead port 1/2 on $mux $procmux$14090. + dead port 1/2 on $mux $procmux$14093. + dead port 1/2 on $mux $procmux$14096. + dead port 2/2 on $mux $procmux$14098. + dead port 1/2 on $mux $procmux$14101. + dead port 1/2 on $mux $procmux$14104. + dead port 1/2 on $mux $procmux$14107. + dead port 1/2 on $mux $procmux$14110. + dead port 1/2 on $mux $procmux$14113. + dead port 1/2 on $mux $procmux$14116. + dead port 1/2 on $mux $procmux$14119. + dead port 1/2 on $mux $procmux$14122. + dead port 1/2 on $mux $procmux$14125. + dead port 1/2 on $mux $procmux$14128. + dead port 1/2 on $mux $procmux$14131. + dead port 1/2 on $mux $procmux$14134. + dead port 1/2 on $mux $procmux$14137. + dead port 1/2 on $mux $procmux$14140. + dead port 1/2 on $mux $procmux$14143. + dead port 1/2 on $mux $procmux$14146. + dead port 2/2 on $mux $procmux$14148. + dead port 1/2 on $mux $procmux$14151. + dead port 1/2 on $mux $procmux$14154. + dead port 1/2 on $mux $procmux$14157. + dead port 1/2 on $mux $procmux$14160. + dead port 1/2 on $mux $procmux$14163. + dead port 1/2 on $mux $procmux$14166. + dead port 1/2 on $mux $procmux$14169. + dead port 1/2 on $mux $procmux$14172. + dead port 1/2 on $mux $procmux$14175. + dead port 1/2 on $mux $procmux$14178. + dead port 1/2 on $mux $procmux$14181. + dead port 2/2 on $mux $procmux$14184. + dead port 1/2 on $mux $procmux$14192. + dead port 1/2 on $mux $procmux$14195. + dead port 2/2 on $mux $procmux$14197. + dead port 1/2 on $mux $procmux$14200. + dead port 1/2 on $mux $procmux$14203. + dead port 1/2 on $mux $procmux$14206. + dead port 1/2 on $mux $procmux$14209. + dead port 1/2 on $mux $procmux$14212. + dead port 1/2 on $mux $procmux$14215. + dead port 1/2 on $mux $procmux$14218. + dead port 1/2 on $mux $procmux$14221. + dead port 1/2 on $mux $procmux$14224. + dead port 1/2 on $mux $procmux$14227. + dead port 1/2 on $mux $procmux$14230. + dead port 1/2 on $mux $procmux$14233. + dead port 1/2 on $mux $procmux$14236. + dead port 1/2 on $mux $procmux$14239. + dead port 1/2 on $mux $procmux$14242. + dead port 1/2 on $mux $procmux$14245. + dead port 2/2 on $mux $procmux$14247. + dead port 1/2 on $mux $procmux$14250. + dead port 1/2 on $mux $procmux$14253. + dead port 1/2 on $mux $procmux$14256. + dead port 1/2 on $mux $procmux$14259. + dead port 1/2 on $mux $procmux$14262. + dead port 1/2 on $mux $procmux$14265. + dead port 1/2 on $mux $procmux$14268. + dead port 1/2 on $mux $procmux$14271. + dead port 1/2 on $mux $procmux$14274. + dead port 1/2 on $mux $procmux$14277. + dead port 1/2 on $mux $procmux$14280. + dead port 2/2 on $mux $procmux$14283. + dead port 1/2 on $mux $procmux$14291. + dead port 1/2 on $mux $procmux$14294. + dead port 2/2 on $mux $procmux$14296. + dead port 1/2 on $mux $procmux$14299. + dead port 1/2 on $mux $procmux$14302. + dead port 1/2 on $mux $procmux$14305. + dead port 1/2 on $mux $procmux$14308. + dead port 1/2 on $mux $procmux$14311. + dead port 1/2 on $mux $procmux$14314. + dead port 1/2 on $mux $procmux$14317. + dead port 1/2 on $mux $procmux$14320. + dead port 1/2 on $mux $procmux$14323. + dead port 1/2 on $mux $procmux$14326. + dead port 1/2 on $mux $procmux$14329. + dead port 1/2 on $mux $procmux$14332. + dead port 1/2 on $mux $procmux$14335. + dead port 1/2 on $mux $procmux$14338. + dead port 1/2 on $mux $procmux$14341. + dead port 1/2 on $mux $procmux$14344. + dead port 2/2 on $mux $procmux$14346. + dead port 1/2 on $mux $procmux$14349. + dead port 1/2 on $mux $procmux$14352. + dead port 1/2 on $mux $procmux$14355. + dead port 1/2 on $mux $procmux$14358. + dead port 1/2 on $mux $procmux$14361. + dead port 1/2 on $mux $procmux$14364. + dead port 1/2 on $mux $procmux$14367. + dead port 1/2 on $mux $procmux$14370. + dead port 1/2 on $mux $procmux$14373. + dead port 1/2 on $mux $procmux$14376. + dead port 1/2 on $mux $procmux$14379. + dead port 2/2 on $mux $procmux$14382. + dead port 1/2 on $mux $procmux$14390. + dead port 1/2 on $mux $procmux$14393. + dead port 2/2 on $mux $procmux$14395. + dead port 1/2 on $mux $procmux$14398. + dead port 1/2 on $mux $procmux$14401. + dead port 1/2 on $mux $procmux$14404. + dead port 1/2 on $mux $procmux$14407. + dead port 1/2 on $mux $procmux$14410. + dead port 1/2 on $mux $procmux$14413. + dead port 1/2 on $mux $procmux$14416. + dead port 1/2 on $mux $procmux$14419. + dead port 1/2 on $mux $procmux$14422. + dead port 1/2 on $mux $procmux$14425. + dead port 1/2 on $mux $procmux$14428. + dead port 1/2 on $mux $procmux$14431. + dead port 1/2 on $mux $procmux$14434. + dead port 1/2 on $mux $procmux$14437. + dead port 1/2 on $mux $procmux$14440. + dead port 1/2 on $mux $procmux$14443. + dead port 2/2 on $mux $procmux$14445. + dead port 1/2 on $mux $procmux$14448. + dead port 1/2 on $mux $procmux$14451. + dead port 1/2 on $mux $procmux$14454. + dead port 1/2 on $mux $procmux$14457. + dead port 1/2 on $mux $procmux$14460. + dead port 1/2 on $mux $procmux$14463. + dead port 1/2 on $mux $procmux$14466. + dead port 1/2 on $mux $procmux$14469. + dead port 1/2 on $mux $procmux$14472. + dead port 1/2 on $mux $procmux$14475. + dead port 1/2 on $mux $procmux$14478. + dead port 2/2 on $mux $procmux$14481. + dead port 1/2 on $mux $procmux$14489. + dead port 1/2 on $mux $procmux$14492. + dead port 2/2 on $mux $procmux$14494. + dead port 1/2 on $mux $procmux$14497. + dead port 1/2 on $mux $procmux$14500. + dead port 1/2 on $mux $procmux$14503. + dead port 1/2 on $mux $procmux$14506. + dead port 1/2 on $mux $procmux$14509. + dead port 1/2 on $mux $procmux$14512. + dead port 1/2 on $mux $procmux$14515. + dead port 1/2 on $mux $procmux$14518. + dead port 1/2 on $mux $procmux$14521. + dead port 1/2 on $mux $procmux$14524. + dead port 1/2 on $mux $procmux$14527. + dead port 1/2 on $mux $procmux$14530. + dead port 1/2 on $mux $procmux$14533. + dead port 1/2 on $mux $procmux$14536. + dead port 1/2 on $mux $procmux$14539. + dead port 1/2 on $mux $procmux$14542. + dead port 2/2 on $mux $procmux$14544. + dead port 1/2 on $mux $procmux$14547. + dead port 1/2 on $mux $procmux$14550. + dead port 1/2 on $mux $procmux$14553. + dead port 1/2 on $mux $procmux$14556. + dead port 1/2 on $mux $procmux$14559. + dead port 1/2 on $mux $procmux$14562. + dead port 1/2 on $mux $procmux$14565. + dead port 1/2 on $mux $procmux$14568. + dead port 1/2 on $mux $procmux$14571. + dead port 1/2 on $mux $procmux$14574. + dead port 1/2 on $mux $procmux$14577. + dead port 2/2 on $mux $procmux$14580. + dead port 1/2 on $mux $procmux$14588. + dead port 2/2 on $mux $procmux$14590. + dead port 1/2 on $mux $procmux$14593. + dead port 1/2 on $mux $procmux$14596. + dead port 1/2 on $mux $procmux$14599. + dead port 1/2 on $mux $procmux$14602. + dead port 1/2 on $mux $procmux$14605. + dead port 1/2 on $mux $procmux$14608. + dead port 1/2 on $mux $procmux$14611. + dead port 1/2 on $mux $procmux$14614. + dead port 1/2 on $mux $procmux$14617. + dead port 1/2 on $mux $procmux$14620. + dead port 1/2 on $mux $procmux$14623. + dead port 1/2 on $mux $procmux$14626. + dead port 1/2 on $mux $procmux$14629. + dead port 1/2 on $mux $procmux$14632. + dead port 1/2 on $mux $procmux$14635. + dead port 1/2 on $mux $procmux$14638. + dead port 2/2 on $mux $procmux$14640. + dead port 1/2 on $mux $procmux$14643. + dead port 1/2 on $mux $procmux$14646. + dead port 1/2 on $mux $procmux$14649. + dead port 1/2 on $mux $procmux$14652. + dead port 1/2 on $mux $procmux$14655. + dead port 1/2 on $mux $procmux$14658. + dead port 1/2 on $mux $procmux$14661. + dead port 1/2 on $mux $procmux$14664. + dead port 1/2 on $mux $procmux$14667. + dead port 1/2 on $mux $procmux$14670. + dead port 1/2 on $mux $procmux$14673. + dead port 2/2 on $mux $procmux$14676. + dead port 1/2 on $mux $procmux$14684. + dead port 2/2 on $mux $procmux$14686. + dead port 1/2 on $mux $procmux$14689. + dead port 1/2 on $mux $procmux$14692. + dead port 1/2 on $mux $procmux$14695. + dead port 1/2 on $mux $procmux$14698. + dead port 1/2 on $mux $procmux$14701. + dead port 1/2 on $mux $procmux$14704. + dead port 1/2 on $mux $procmux$14707. + dead port 1/2 on $mux $procmux$14710. + dead port 1/2 on $mux $procmux$14713. + dead port 1/2 on $mux $procmux$14716. + dead port 1/2 on $mux $procmux$14719. + dead port 1/2 on $mux $procmux$14722. + dead port 1/2 on $mux $procmux$14725. + dead port 1/2 on $mux $procmux$14728. + dead port 1/2 on $mux $procmux$14731. + dead port 1/2 on $mux $procmux$14734. + dead port 2/2 on $mux $procmux$14736. + dead port 1/2 on $mux $procmux$14739. + dead port 1/2 on $mux $procmux$14742. + dead port 1/2 on $mux $procmux$14745. + dead port 1/2 on $mux $procmux$14748. + dead port 1/2 on $mux $procmux$14751. + dead port 1/2 on $mux $procmux$14754. + dead port 1/2 on $mux $procmux$14757. + dead port 1/2 on $mux $procmux$14760. + dead port 1/2 on $mux $procmux$14763. + dead port 1/2 on $mux $procmux$14766. + dead port 1/2 on $mux $procmux$14769. + dead port 2/2 on $mux $procmux$14772. + dead port 1/2 on $mux $procmux$14780. + dead port 2/2 on $mux $procmux$14782. + dead port 1/2 on $mux $procmux$14785. + dead port 1/2 on $mux $procmux$14788. + dead port 1/2 on $mux $procmux$14791. + dead port 1/2 on $mux $procmux$14794. + dead port 1/2 on $mux $procmux$14797. + dead port 1/2 on $mux $procmux$14800. + dead port 1/2 on $mux $procmux$14803. + dead port 1/2 on $mux $procmux$14806. + dead port 1/2 on $mux $procmux$14809. + dead port 1/2 on $mux $procmux$14812. + dead port 1/2 on $mux $procmux$14815. + dead port 1/2 on $mux $procmux$14818. + dead port 1/2 on $mux $procmux$14821. + dead port 1/2 on $mux $procmux$14824. + dead port 1/2 on $mux $procmux$14827. + dead port 1/2 on $mux $procmux$14830. + dead port 2/2 on $mux $procmux$14832. + dead port 1/2 on $mux $procmux$14835. + dead port 1/2 on $mux $procmux$14838. + dead port 1/2 on $mux $procmux$14841. + dead port 1/2 on $mux $procmux$14844. + dead port 1/2 on $mux $procmux$14847. + dead port 1/2 on $mux $procmux$14850. + dead port 1/2 on $mux $procmux$14853. + dead port 1/2 on $mux $procmux$14856. + dead port 1/2 on $mux $procmux$14859. + dead port 1/2 on $mux $procmux$14862. + dead port 1/2 on $mux $procmux$14865. + dead port 2/2 on $mux $procmux$14868. + dead port 1/2 on $mux $procmux$14876. + dead port 2/2 on $mux $procmux$14878. + dead port 1/2 on $mux $procmux$14881. + dead port 1/2 on $mux $procmux$14884. + dead port 1/2 on $mux $procmux$14887. + dead port 1/2 on $mux $procmux$14890. + dead port 1/2 on $mux $procmux$14893. + dead port 1/2 on $mux $procmux$14896. + dead port 1/2 on $mux $procmux$14899. + dead port 1/2 on $mux $procmux$14902. + dead port 1/2 on $mux $procmux$14905. + dead port 1/2 on $mux $procmux$14908. + dead port 1/2 on $mux $procmux$14911. + dead port 1/2 on $mux $procmux$14914. + dead port 1/2 on $mux $procmux$14917. + dead port 1/2 on $mux $procmux$14920. + dead port 1/2 on $mux $procmux$14923. + dead port 1/2 on $mux $procmux$14926. + dead port 2/2 on $mux $procmux$14928. + dead port 1/2 on $mux $procmux$14931. + dead port 1/2 on $mux $procmux$14934. + dead port 1/2 on $mux $procmux$14937. + dead port 1/2 on $mux $procmux$14940. + dead port 1/2 on $mux $procmux$14943. + dead port 1/2 on $mux $procmux$14946. + dead port 1/2 on $mux $procmux$14949. + dead port 1/2 on $mux $procmux$14952. + dead port 1/2 on $mux $procmux$14955. + dead port 1/2 on $mux $procmux$14958. + dead port 1/2 on $mux $procmux$14961. + dead port 2/2 on $mux $procmux$14964. + dead port 1/2 on $mux $procmux$14972. + dead port 2/2 on $mux $procmux$14974. + dead port 1/2 on $mux $procmux$14977. + dead port 1/2 on $mux $procmux$14980. + dead port 1/2 on $mux $procmux$14983. + dead port 1/2 on $mux $procmux$14986. + dead port 1/2 on $mux $procmux$14989. + dead port 1/2 on $mux $procmux$14992. + dead port 1/2 on $mux $procmux$14995. + dead port 1/2 on $mux $procmux$14998. + dead port 1/2 on $mux $procmux$15001. + dead port 1/2 on $mux $procmux$15004. + dead port 1/2 on $mux $procmux$15007. + dead port 1/2 on $mux $procmux$15010. + dead port 1/2 on $mux $procmux$15013. + dead port 1/2 on $mux $procmux$15016. + dead port 1/2 on $mux $procmux$15019. + dead port 1/2 on $mux $procmux$15022. + dead port 2/2 on $mux $procmux$15024. + dead port 1/2 on $mux $procmux$15027. + dead port 1/2 on $mux $procmux$15030. + dead port 1/2 on $mux $procmux$15033. + dead port 1/2 on $mux $procmux$15036. + dead port 1/2 on $mux $procmux$15039. + dead port 1/2 on $mux $procmux$15042. + dead port 1/2 on $mux $procmux$15045. + dead port 1/2 on $mux $procmux$15048. + dead port 1/2 on $mux $procmux$15051. + dead port 1/2 on $mux $procmux$15054. + dead port 1/2 on $mux $procmux$15057. + dead port 2/2 on $mux $procmux$15060. + dead port 1/2 on $mux $procmux$15068. + dead port 2/2 on $mux $procmux$15070. + dead port 1/2 on $mux $procmux$15073. + dead port 1/2 on $mux $procmux$15076. + dead port 1/2 on $mux $procmux$15079. + dead port 1/2 on $mux $procmux$15082. + dead port 1/2 on $mux $procmux$15085. + dead port 1/2 on $mux $procmux$15088. + dead port 1/2 on $mux $procmux$15091. + dead port 1/2 on $mux $procmux$15094. + dead port 1/2 on $mux $procmux$15097. + dead port 1/2 on $mux $procmux$15100. + dead port 1/2 on $mux $procmux$15103. + dead port 1/2 on $mux $procmux$15106. + dead port 1/2 on $mux $procmux$15109. + dead port 1/2 on $mux $procmux$15112. + dead port 1/2 on $mux $procmux$15115. + dead port 1/2 on $mux $procmux$15118. + dead port 2/2 on $mux $procmux$15120. + dead port 1/2 on $mux $procmux$15123. + dead port 1/2 on $mux $procmux$15126. + dead port 1/2 on $mux $procmux$15129. + dead port 1/2 on $mux $procmux$15132. + dead port 1/2 on $mux $procmux$15135. + dead port 1/2 on $mux $procmux$15138. + dead port 1/2 on $mux $procmux$15141. + dead port 1/2 on $mux $procmux$15144. + dead port 1/2 on $mux $procmux$15147. + dead port 1/2 on $mux $procmux$15150. + dead port 1/2 on $mux $procmux$15153. + dead port 2/2 on $mux $procmux$15156. + dead port 1/2 on $mux $procmux$15164. + dead port 2/2 on $mux $procmux$15166. + dead port 1/2 on $mux $procmux$15169. + dead port 1/2 on $mux $procmux$15172. + dead port 1/2 on $mux $procmux$15175. + dead port 1/2 on $mux $procmux$15178. + dead port 1/2 on $mux $procmux$15181. + dead port 1/2 on $mux $procmux$15184. + dead port 1/2 on $mux $procmux$15187. + dead port 1/2 on $mux $procmux$15190. + dead port 1/2 on $mux $procmux$15193. + dead port 1/2 on $mux $procmux$15196. + dead port 1/2 on $mux $procmux$15199. + dead port 1/2 on $mux $procmux$15202. + dead port 1/2 on $mux $procmux$15205. + dead port 1/2 on $mux $procmux$15208. + dead port 1/2 on $mux $procmux$15211. + dead port 1/2 on $mux $procmux$15214. + dead port 2/2 on $mux $procmux$15216. + dead port 1/2 on $mux $procmux$15219. + dead port 1/2 on $mux $procmux$15222. + dead port 1/2 on $mux $procmux$15225. + dead port 1/2 on $mux $procmux$15228. + dead port 1/2 on $mux $procmux$15231. + dead port 1/2 on $mux $procmux$15234. + dead port 1/2 on $mux $procmux$15237. + dead port 1/2 on $mux $procmux$15240. + dead port 1/2 on $mux $procmux$15243. + dead port 1/2 on $mux $procmux$15246. + dead port 1/2 on $mux $procmux$15249. + dead port 2/2 on $mux $procmux$15252. + dead port 2/2 on $mux $procmux$15259. + dead port 1/2 on $mux $procmux$15262. + dead port 1/2 on $mux $procmux$15265. + dead port 1/2 on $mux $procmux$15268. + dead port 1/2 on $mux $procmux$15271. + dead port 1/2 on $mux $procmux$15274. + dead port 1/2 on $mux $procmux$15277. + dead port 1/2 on $mux $procmux$15280. + dead port 1/2 on $mux $procmux$15283. + dead port 1/2 on $mux $procmux$15286. + dead port 1/2 on $mux $procmux$15289. + dead port 1/2 on $mux $procmux$15292. + dead port 1/2 on $mux $procmux$15295. + dead port 1/2 on $mux $procmux$15298. + dead port 1/2 on $mux $procmux$15301. + dead port 1/2 on $mux $procmux$15304. + dead port 1/2 on $mux $procmux$15307. + dead port 2/2 on $mux $procmux$15309. + dead port 1/2 on $mux $procmux$15312. + dead port 1/2 on $mux $procmux$15315. + dead port 1/2 on $mux $procmux$15318. + dead port 1/2 on $mux $procmux$15321. + dead port 1/2 on $mux $procmux$15324. + dead port 1/2 on $mux $procmux$15327. + dead port 1/2 on $mux $procmux$15330. + dead port 1/2 on $mux $procmux$15333. + dead port 1/2 on $mux $procmux$15336. + dead port 1/2 on $mux $procmux$15339. + dead port 1/2 on $mux $procmux$15342. + dead port 2/2 on $mux $procmux$15345. + dead port 2/2 on $mux $procmux$15352. + dead port 1/2 on $mux $procmux$15355. + dead port 1/2 on $mux $procmux$15358. + dead port 1/2 on $mux $procmux$15361. + dead port 1/2 on $mux $procmux$15364. + dead port 1/2 on $mux $procmux$15367. + dead port 1/2 on $mux $procmux$15370. + dead port 1/2 on $mux $procmux$15373. + dead port 1/2 on $mux $procmux$15376. + dead port 1/2 on $mux $procmux$15379. + dead port 1/2 on $mux $procmux$15382. + dead port 1/2 on $mux $procmux$15385. + dead port 1/2 on $mux $procmux$15388. + dead port 1/2 on $mux $procmux$15391. + dead port 1/2 on $mux $procmux$15394. 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+ dead port 1/2 on $mux $procmux$16881. + dead port 1/2 on $mux $procmux$16884. + dead port 1/2 on $mux $procmux$16887. + dead port 1/2 on $mux $procmux$16890. + dead port 2/2 on $mux $procmux$16893. + dead port 1/2 on $mux $procmux$16990. + dead port 1/2 on $mux $procmux$16993. + dead port 1/2 on $mux $procmux$16996. + dead port 1/2 on $mux $procmux$16999. + dead port 1/2 on $mux $procmux$17002. + dead port 1/2 on $mux $procmux$17005. + dead port 1/2 on $mux $procmux$17008. + dead port 1/2 on $mux $procmux$17011. + dead port 1/2 on $mux $procmux$17014. + dead port 1/2 on $mux $procmux$17017. + dead port 1/2 on $mux $procmux$17020. + dead port 1/2 on $mux $procmux$17023. + dead port 1/2 on $mux $procmux$17026. + dead port 1/2 on $mux $procmux$17029. + dead port 1/2 on $mux $procmux$17032. + dead port 1/2 on $mux $procmux$17035. + dead port 2/2 on $mux $procmux$17037. + dead port 1/2 on $mux $procmux$17040. + dead port 1/2 on $mux $procmux$17043. + dead port 1/2 on $mux $procmux$17046. + dead port 1/2 on $mux $procmux$17049. + dead port 1/2 on $mux $procmux$17052. + dead port 1/2 on $mux $procmux$17055. + dead port 1/2 on $mux $procmux$17058. + dead port 1/2 on $mux $procmux$17061. + dead port 1/2 on $mux $procmux$17064. + dead port 1/2 on $mux $procmux$17067. + dead port 1/2 on $mux $procmux$17070. + dead port 2/2 on $mux $procmux$17073. + dead port 1/2 on $mux $procmux$17080. + dead port 1/2 on $mux $procmux$17083. + dead port 1/2 on $mux $procmux$17086. + dead port 1/2 on $mux $procmux$17089. + dead port 1/2 on $mux $procmux$17092. + dead port 1/2 on $mux $procmux$17095. + dead port 1/2 on $mux $procmux$17098. + dead port 1/2 on $mux $procmux$17101. + dead port 1/2 on $mux $procmux$17104. + dead port 1/2 on $mux $procmux$17107. + dead port 1/2 on $mux $procmux$17110. + dead port 1/2 on $mux $procmux$17113. + dead port 1/2 on $mux $procmux$17116. + dead port 1/2 on $mux $procmux$17119. + dead port 1/2 on $mux $procmux$17122. + dead port 1/2 on $mux $procmux$17125. + dead port 2/2 on $mux $procmux$17127. + dead port 1/2 on $mux $procmux$17130. + dead port 1/2 on $mux $procmux$17133. + dead port 1/2 on $mux $procmux$17136. + dead port 1/2 on $mux $procmux$17139. + dead port 1/2 on $mux $procmux$17142. + dead port 1/2 on $mux $procmux$17145. + dead port 1/2 on $mux $procmux$17148. + dead port 1/2 on $mux $procmux$17151. + dead port 1/2 on $mux $procmux$17154. + dead port 1/2 on $mux $procmux$17157. + dead port 1/2 on $mux $procmux$17160. + dead port 2/2 on $mux $procmux$17163. + dead port 1/2 on $mux $procmux$17170. + dead port 1/2 on $mux $procmux$17173. + dead port 1/2 on $mux $procmux$17176. + dead port 1/2 on $mux $procmux$17179. + dead port 1/2 on $mux $procmux$17182. + dead port 1/2 on $mux $procmux$17185. + dead port 1/2 on $mux $procmux$17188. + dead port 1/2 on $mux $procmux$17191. + dead port 1/2 on $mux $procmux$17194. + dead port 1/2 on $mux $procmux$17197. + dead port 1/2 on $mux $procmux$17200. + dead port 1/2 on $mux $procmux$17203. + dead port 1/2 on $mux $procmux$17206. + dead port 1/2 on $mux $procmux$17209. + dead port 1/2 on $mux $procmux$17212. + dead port 1/2 on $mux $procmux$17215. + dead port 2/2 on $mux $procmux$17217. + dead port 1/2 on $mux $procmux$17220. + dead port 1/2 on $mux $procmux$17223. + dead port 1/2 on $mux $procmux$17226. + dead port 1/2 on $mux $procmux$17229. + dead port 1/2 on $mux $procmux$17232. + dead port 1/2 on $mux $procmux$17235. + dead port 1/2 on $mux $procmux$17238. + dead port 1/2 on $mux $procmux$17241. + dead port 1/2 on $mux $procmux$17244. + dead port 1/2 on $mux $procmux$17247. + dead port 1/2 on $mux $procmux$17250. + dead port 2/2 on $mux $procmux$17253. + dead port 1/2 on $mux $procmux$17260. + dead port 1/2 on $mux $procmux$17263. + dead port 1/2 on $mux $procmux$17266. + dead port 1/2 on $mux $procmux$17269. + dead port 1/2 on $mux $procmux$17272. + dead port 1/2 on $mux $procmux$17275. + dead port 1/2 on $mux $procmux$17278. + dead port 1/2 on $mux $procmux$17281. + dead port 1/2 on $mux $procmux$17284. + dead port 1/2 on $mux $procmux$17287. + dead port 1/2 on $mux $procmux$17290. + dead port 1/2 on $mux $procmux$17293. + dead port 1/2 on $mux $procmux$17296. + dead port 1/2 on $mux $procmux$17299. + dead port 1/2 on $mux $procmux$17302. + dead port 1/2 on $mux $procmux$17305. + dead port 2/2 on $mux $procmux$17307. + dead port 1/2 on $mux $procmux$17310. + dead port 1/2 on $mux $procmux$17313. + dead port 1/2 on $mux $procmux$17316. + dead port 1/2 on $mux $procmux$17319. + dead port 1/2 on $mux $procmux$17322. + dead port 1/2 on $mux $procmux$17325. + dead port 1/2 on $mux $procmux$17328. + dead port 1/2 on $mux $procmux$17331. + dead port 1/2 on $mux $procmux$17334. + dead port 1/2 on $mux $procmux$17337. + dead port 1/2 on $mux $procmux$17340. + dead port 2/2 on $mux $procmux$17343. + dead port 1/2 on $mux $procmux$17350. + dead port 1/2 on $mux $procmux$17353. + dead port 1/2 on $mux $procmux$17356. + dead port 1/2 on $mux $procmux$17359. + dead port 1/2 on $mux $procmux$17362. + dead port 1/2 on $mux $procmux$17365. + dead port 1/2 on $mux $procmux$17368. + dead port 1/2 on $mux $procmux$17371. + dead port 1/2 on $mux $procmux$17374. + dead port 1/2 on $mux $procmux$17377. + dead port 1/2 on $mux $procmux$17380. + dead port 1/2 on $mux $procmux$17383. + dead port 1/2 on $mux $procmux$17386. + dead port 1/2 on $mux $procmux$17389. + dead port 1/2 on $mux $procmux$17392. + dead port 1/2 on $mux $procmux$17395. + dead port 2/2 on $mux $procmux$17397. + dead port 1/2 on $mux $procmux$17400. + dead port 1/2 on $mux $procmux$17403. + dead port 1/2 on $mux $procmux$17406. + dead port 1/2 on $mux $procmux$17409. + dead port 1/2 on $mux $procmux$17412. + dead port 1/2 on $mux $procmux$17415. + dead port 1/2 on $mux $procmux$17418. + dead port 1/2 on $mux $procmux$17421. + dead port 1/2 on $mux $procmux$17424. + dead port 1/2 on $mux $procmux$17427. + dead port 1/2 on $mux $procmux$17430. + dead port 2/2 on $mux $procmux$17433. + dead port 1/2 on $mux $procmux$17440. + dead port 1/2 on $mux $procmux$17443. + dead port 1/2 on $mux $procmux$17446. + dead port 1/2 on $mux $procmux$17449. + dead port 1/2 on $mux $procmux$17452. + dead port 1/2 on $mux $procmux$17455. + dead port 1/2 on $mux $procmux$17458. + dead port 1/2 on $mux $procmux$17461. + dead port 1/2 on $mux $procmux$17464. + dead port 1/2 on $mux $procmux$17467. + dead port 1/2 on $mux $procmux$17470. + dead port 1/2 on $mux $procmux$17473. + dead port 1/2 on $mux $procmux$17476. + dead port 1/2 on $mux $procmux$17479. + dead port 1/2 on $mux $procmux$17482. + dead port 1/2 on $mux $procmux$17485. + dead port 2/2 on $mux $procmux$17487. + dead port 1/2 on $mux $procmux$17490. + dead port 1/2 on $mux $procmux$17493. + dead port 1/2 on $mux $procmux$17496. + dead port 1/2 on $mux $procmux$17499. + dead port 1/2 on $mux $procmux$17502. + dead port 1/2 on $mux $procmux$17505. + dead port 1/2 on $mux $procmux$17508. + dead port 1/2 on $mux $procmux$17511. + dead port 1/2 on $mux $procmux$17514. + dead port 1/2 on $mux $procmux$17517. + dead port 1/2 on $mux $procmux$17520. + dead port 2/2 on $mux $procmux$17523. + dead port 1/2 on $mux $procmux$17800. + dead port 1/2 on $mux $procmux$17803. + dead port 1/2 on $mux $procmux$17806. + dead port 1/2 on $mux $procmux$17809. + dead port 1/2 on $mux $procmux$17812. + dead port 1/2 on $mux $procmux$17815. + dead port 1/2 on $mux $procmux$17818. + dead port 1/2 on $mux $procmux$17821. + dead port 1/2 on $mux $procmux$17824. + dead port 1/2 on $mux $procmux$17827. + dead port 1/2 on $mux $procmux$17830. + dead port 1/2 on $mux $procmux$17833. + dead port 1/2 on $mux $procmux$17836. + dead port 1/2 on $mux $procmux$17839. + dead port 1/2 on $mux $procmux$17842. + dead port 1/2 on $mux $procmux$17845. + dead port 2/2 on $mux $procmux$17847. + dead port 1/2 on $mux $procmux$17850. + dead port 1/2 on $mux $procmux$17853. + dead port 1/2 on $mux $procmux$17856. + dead port 1/2 on $mux $procmux$17859. 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+ dead port 1/2 on $mux $procmux$17940. + dead port 1/2 on $mux $procmux$17943. + dead port 1/2 on $mux $procmux$17946. + dead port 1/2 on $mux $procmux$17949. + dead port 1/2 on $mux $procmux$17952. + dead port 1/2 on $mux $procmux$17955. + dead port 1/2 on $mux $procmux$17958. + dead port 1/2 on $mux $procmux$17961. + dead port 1/2 on $mux $procmux$17964. + dead port 1/2 on $mux $procmux$17967. + dead port 1/2 on $mux $procmux$17970. + dead port 2/2 on $mux $procmux$17973. + dead port 1/2 on $mux $procmux$17981. + dead port 1/2 on $mux $procmux$17984. + dead port 1/2 on $mux $procmux$17987. + dead port 2/2 on $mux $procmux$17989. + dead port 1/2 on $mux $procmux$17992. + dead port 1/2 on $mux $procmux$17995. + dead port 1/2 on $mux $procmux$17998. + dead port 1/2 on $mux $procmux$18001. + dead port 1/2 on $mux $procmux$18004. + dead port 1/2 on $mux $procmux$18007. + dead port 1/2 on $mux $procmux$18010. + dead port 1/2 on $mux $procmux$18013. + dead port 1/2 on $mux $procmux$18016. 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+ dead port 2/2 on $mux $procmux$20031. + dead port 1/2 on $mux $procmux$20038. + dead port 1/2 on $mux $procmux$20041. + dead port 1/2 on $mux $procmux$20044. + dead port 1/2 on $mux $procmux$20047. + dead port 1/2 on $mux $procmux$20050. + dead port 1/2 on $mux $procmux$20053. + dead port 1/2 on $mux $procmux$20056. + dead port 1/2 on $mux $procmux$20059. + dead port 1/2 on $mux $procmux$20062. + dead port 1/2 on $mux $procmux$20065. + dead port 1/2 on $mux $procmux$20068. + dead port 1/2 on $mux $procmux$20071. + dead port 1/2 on $mux $procmux$20074. + dead port 1/2 on $mux $procmux$20077. + dead port 1/2 on $mux $procmux$20080. + dead port 2/2 on $mux $procmux$20082. + dead port 1/2 on $mux $procmux$20085. + dead port 1/2 on $mux $procmux$20088. + dead port 1/2 on $mux $procmux$20091. + dead port 1/2 on $mux $procmux$20094. + dead port 1/2 on $mux $procmux$20097. + dead port 1/2 on $mux $procmux$20100. + dead port 1/2 on $mux $procmux$20103. + dead port 1/2 on $mux $procmux$20106. + dead port 1/2 on $mux $procmux$20109. + dead port 1/2 on $mux $procmux$20112. + dead port 1/2 on $mux $procmux$20115. + dead port 2/2 on $mux $procmux$20118. + dead port 1/2 on $mux $procmux$20125. + dead port 1/2 on $mux $procmux$20128. + dead port 1/2 on $mux $procmux$20131. + dead port 1/2 on $mux $procmux$20134. + dead port 1/2 on $mux $procmux$20137. + dead port 1/2 on $mux $procmux$20140. + dead port 1/2 on $mux $procmux$20143. + dead port 1/2 on $mux $procmux$20146. + dead port 1/2 on $mux $procmux$20149. + dead port 1/2 on $mux $procmux$20152. + dead port 1/2 on $mux $procmux$20155. + dead port 1/2 on $mux $procmux$20158. + dead port 1/2 on $mux $procmux$20161. + dead port 1/2 on $mux $procmux$20164. + dead port 1/2 on $mux $procmux$20167. + dead port 2/2 on $mux $procmux$20169. + dead port 1/2 on $mux $procmux$20172. + dead port 1/2 on $mux $procmux$20175. + dead port 1/2 on $mux $procmux$20178. + dead port 1/2 on $mux $procmux$20181. + dead port 1/2 on $mux $procmux$20184. + dead port 1/2 on $mux $procmux$20187. + dead port 1/2 on $mux $procmux$20190. + dead port 1/2 on $mux $procmux$20193. + dead port 1/2 on $mux $procmux$20196. + dead port 1/2 on $mux $procmux$20199. + dead port 1/2 on $mux $procmux$20202. + dead port 2/2 on $mux $procmux$20205. + dead port 1/2 on $mux $procmux$20212. + dead port 1/2 on $mux $procmux$20215. + dead port 1/2 on $mux $procmux$20218. + dead port 1/2 on $mux $procmux$20221. + dead port 1/2 on $mux $procmux$20224. + dead port 1/2 on $mux $procmux$20227. + dead port 1/2 on $mux $procmux$20230. + dead port 1/2 on $mux $procmux$20233. + dead port 1/2 on $mux $procmux$20236. + dead port 1/2 on $mux $procmux$20239. + dead port 1/2 on $mux $procmux$20242. + dead port 1/2 on $mux $procmux$20245. + dead port 1/2 on $mux $procmux$20248. + dead port 1/2 on $mux $procmux$20251. + dead port 1/2 on $mux $procmux$20254. + dead port 2/2 on $mux $procmux$20256. + dead port 1/2 on $mux $procmux$20259. + dead port 1/2 on $mux $procmux$20262. + dead port 1/2 on $mux $procmux$20265. + dead port 1/2 on $mux $procmux$20268. + dead port 1/2 on $mux $procmux$20271. + dead port 1/2 on $mux $procmux$20274. + dead port 1/2 on $mux $procmux$20277. + dead port 1/2 on $mux $procmux$20280. + dead port 1/2 on $mux $procmux$20283. + dead port 1/2 on $mux $procmux$20286. + dead port 1/2 on $mux $procmux$20289. + dead port 2/2 on $mux $procmux$20292. + dead port 1/2 on $mux $procmux$20299. + dead port 1/2 on $mux $procmux$20302. + dead port 1/2 on $mux $procmux$20305. + dead port 1/2 on $mux $procmux$20308. + dead port 1/2 on $mux $procmux$20311. + dead port 1/2 on $mux $procmux$20314. + dead port 1/2 on $mux $procmux$20317. + dead port 1/2 on $mux $procmux$20320. + dead port 1/2 on $mux $procmux$20323. + dead port 1/2 on $mux $procmux$20326. + dead port 1/2 on $mux $procmux$20329. + dead port 1/2 on $mux $procmux$20332. + dead port 1/2 on $mux $procmux$20335. + dead port 1/2 on $mux $procmux$20338. + dead port 1/2 on $mux $procmux$20341. + dead port 2/2 on $mux $procmux$20343. + dead port 1/2 on $mux $procmux$20346. + dead port 1/2 on $mux $procmux$20349. + dead port 1/2 on $mux $procmux$20352. + dead port 1/2 on $mux $procmux$20355. + dead port 1/2 on $mux $procmux$20358. + dead port 1/2 on $mux $procmux$20361. + dead port 1/2 on $mux $procmux$20364. + dead port 1/2 on $mux $procmux$20367. + dead port 1/2 on $mux $procmux$20370. + dead port 1/2 on $mux $procmux$20373. + dead port 1/2 on $mux $procmux$20376. + dead port 2/2 on $mux $procmux$20379. + dead port 1/2 on $mux $procmux$20386. + dead port 1/2 on $mux $procmux$20389. + dead port 1/2 on $mux $procmux$20392. + dead port 1/2 on $mux $procmux$20395. + dead port 1/2 on $mux $procmux$20398. + dead port 1/2 on $mux $procmux$20401. + dead port 1/2 on $mux $procmux$20404. + dead port 1/2 on $mux $procmux$20407. + dead port 1/2 on $mux $procmux$20410. + dead port 1/2 on $mux $procmux$20413. + dead port 1/2 on $mux $procmux$20416. + dead port 1/2 on $mux $procmux$20419. + dead port 1/2 on $mux $procmux$20422. + dead port 1/2 on $mux $procmux$20425. + dead port 1/2 on $mux $procmux$20428. + dead port 2/2 on $mux $procmux$20430. + dead port 1/2 on $mux $procmux$20433. + dead port 1/2 on $mux $procmux$20436. + dead port 1/2 on $mux $procmux$20439. + dead port 1/2 on $mux $procmux$20442. + dead port 1/2 on $mux $procmux$20445. + dead port 1/2 on $mux $procmux$20448. + dead port 1/2 on $mux $procmux$20451. + dead port 1/2 on $mux $procmux$20454. + dead port 1/2 on $mux $procmux$20457. + dead port 1/2 on $mux $procmux$20460. + dead port 1/2 on $mux $procmux$20463. + dead port 2/2 on $mux $procmux$20466. + dead port 1/2 on $mux $procmux$20473. + dead port 1/2 on $mux $procmux$20476. + dead port 1/2 on $mux $procmux$20479. + dead port 1/2 on $mux $procmux$20482. + dead port 1/2 on $mux $procmux$20485. + dead port 1/2 on $mux $procmux$20488. + dead port 1/2 on $mux $procmux$20491. + dead port 1/2 on $mux $procmux$20494. + dead port 1/2 on $mux $procmux$20497. + dead port 1/2 on $mux $procmux$20500. + dead port 1/2 on $mux $procmux$20503. + dead port 1/2 on $mux $procmux$20506. + dead port 1/2 on $mux $procmux$20509. + dead port 1/2 on $mux $procmux$20512. + dead port 1/2 on $mux $procmux$20515. + dead port 2/2 on $mux $procmux$20517. + dead port 1/2 on $mux $procmux$20520. + dead port 1/2 on $mux $procmux$20523. + dead port 1/2 on $mux $procmux$20526. + dead port 1/2 on $mux $procmux$20529. + dead port 1/2 on $mux $procmux$20532. + dead port 1/2 on $mux $procmux$20535. + dead port 1/2 on $mux $procmux$20538. + dead port 1/2 on $mux $procmux$20541. + dead port 1/2 on $mux $procmux$20544. + dead port 1/2 on $mux $procmux$20547. + dead port 1/2 on $mux $procmux$20550. + dead port 2/2 on $mux $procmux$20553. + dead port 1/2 on $mux $procmux$20560. + dead port 1/2 on $mux $procmux$20563. + dead port 1/2 on $mux $procmux$20566. + dead port 1/2 on $mux $procmux$20569. + dead port 1/2 on $mux $procmux$20572. + dead port 1/2 on $mux $procmux$20575. + dead port 1/2 on $mux $procmux$20578. + dead port 1/2 on $mux $procmux$20581. + dead port 1/2 on $mux $procmux$20584. + dead port 1/2 on $mux $procmux$20587. + dead port 1/2 on $mux $procmux$20590. + dead port 1/2 on $mux $procmux$20593. + dead port 1/2 on $mux $procmux$20596. + dead port 1/2 on $mux $procmux$20599. + dead port 1/2 on $mux $procmux$20602. + dead port 2/2 on $mux $procmux$20604. + dead port 1/2 on $mux $procmux$20607. + dead port 1/2 on $mux $procmux$20610. + dead port 1/2 on $mux $procmux$20613. + dead port 1/2 on $mux $procmux$20616. + dead port 1/2 on $mux $procmux$20619. + dead port 1/2 on $mux $procmux$20622. + dead port 1/2 on $mux $procmux$20625. + dead port 1/2 on $mux $procmux$20628. + dead port 1/2 on $mux $procmux$20631. + dead port 1/2 on $mux $procmux$20634. + dead port 1/2 on $mux $procmux$20637. + dead port 2/2 on $mux $procmux$20640. + dead port 1/2 on $mux $procmux$20647. + dead port 1/2 on $mux $procmux$20650. + dead port 1/2 on $mux $procmux$20653. + dead port 1/2 on $mux $procmux$20656. + dead port 1/2 on $mux $procmux$20659. + dead port 1/2 on $mux $procmux$20662. + dead port 1/2 on $mux $procmux$20665. + dead port 1/2 on $mux $procmux$20668. + dead port 1/2 on $mux $procmux$20671. + dead port 1/2 on $mux $procmux$20674. + dead port 1/2 on $mux $procmux$20677. + dead port 1/2 on $mux $procmux$20680. + dead port 1/2 on $mux $procmux$20683. + dead port 1/2 on $mux $procmux$20686. + dead port 1/2 on $mux $procmux$20689. + dead port 2/2 on $mux $procmux$20691. + dead port 1/2 on $mux $procmux$20694. + dead port 1/2 on $mux $procmux$20697. + dead port 1/2 on $mux $procmux$20700. + dead port 1/2 on $mux $procmux$20703. + dead port 1/2 on $mux $procmux$20706. + dead port 1/2 on $mux $procmux$20709. + dead port 1/2 on $mux $procmux$20712. + dead port 1/2 on $mux $procmux$20715. + dead port 1/2 on $mux $procmux$20718. + dead port 1/2 on $mux $procmux$20721. + dead port 1/2 on $mux $procmux$20724. + dead port 2/2 on $mux $procmux$20727. + dead port 1/2 on $mux $procmux$20734. + dead port 1/2 on $mux $procmux$20737. + dead port 1/2 on $mux $procmux$20740. + dead port 1/2 on $mux $procmux$20743. + dead port 1/2 on $mux $procmux$20746. + dead port 1/2 on $mux $procmux$20749. + dead port 1/2 on $mux $procmux$20752. + dead port 1/2 on $mux $procmux$20755. + dead port 1/2 on $mux $procmux$20758. + dead port 1/2 on $mux $procmux$20761. + dead port 1/2 on $mux $procmux$20764. + dead port 1/2 on $mux $procmux$20767. + dead port 1/2 on $mux $procmux$20770. + dead port 1/2 on $mux $procmux$20773. + dead port 1/2 on $mux $procmux$20776. + dead port 2/2 on $mux $procmux$20778. + dead port 1/2 on $mux $procmux$20781. + dead port 1/2 on $mux $procmux$20784. + dead port 1/2 on $mux $procmux$20787. + dead port 1/2 on $mux $procmux$20790. + dead port 1/2 on $mux $procmux$20793. + dead port 1/2 on $mux $procmux$20796. + dead port 1/2 on $mux $procmux$20799. + dead port 1/2 on $mux $procmux$20802. + dead port 1/2 on $mux $procmux$20805. + dead port 1/2 on $mux $procmux$20808. + dead port 1/2 on $mux $procmux$20811. + dead port 2/2 on $mux $procmux$20814. + dead port 1/2 on $mux $procmux$20908. + dead port 1/2 on $mux $procmux$20911. + dead port 1/2 on $mux $procmux$20914. + dead port 1/2 on $mux $procmux$20917. + dead port 1/2 on $mux $procmux$20920. + dead port 1/2 on $mux $procmux$20923. + dead port 1/2 on $mux $procmux$20926. + dead port 1/2 on $mux $procmux$20929. + dead port 1/2 on $mux $procmux$20932. + dead port 1/2 on $mux $procmux$20935. + dead port 1/2 on $mux $procmux$20938. + dead port 1/2 on $mux $procmux$20941. + dead port 1/2 on $mux $procmux$20944. + dead port 1/2 on $mux $procmux$20947. + dead port 1/2 on $mux $procmux$20950. + dead port 2/2 on $mux $procmux$20952. + dead port 1/2 on $mux $procmux$20955. + dead port 1/2 on $mux $procmux$20958. + dead port 1/2 on $mux $procmux$20961. + dead port 1/2 on $mux $procmux$20964. + dead port 1/2 on $mux $procmux$20967. + dead port 1/2 on $mux $procmux$20970. + dead port 1/2 on $mux $procmux$20973. + dead port 1/2 on $mux $procmux$20976. + dead port 1/2 on $mux $procmux$20979. + dead port 1/2 on $mux $procmux$20982. + dead port 1/2 on $mux $procmux$20985. + dead port 2/2 on $mux $procmux$20988. + dead port 1/2 on $mux $procmux$20995. + dead port 1/2 on $mux $procmux$20998. + dead port 1/2 on $mux $procmux$21001. + dead port 1/2 on $mux $procmux$21004. + dead port 1/2 on $mux $procmux$21007. + dead port 1/2 on $mux $procmux$21010. + dead port 1/2 on $mux $procmux$21013. + dead port 1/2 on $mux $procmux$21016. + dead port 1/2 on $mux $procmux$21019. + dead port 1/2 on $mux $procmux$21022. + dead port 1/2 on $mux $procmux$21025. + dead port 1/2 on $mux $procmux$21028. + dead port 1/2 on $mux $procmux$21031. + dead port 1/2 on $mux $procmux$21034. + dead port 1/2 on $mux $procmux$21037. + dead port 2/2 on $mux $procmux$21039. + dead port 1/2 on $mux $procmux$21042. + dead port 1/2 on $mux $procmux$21045. + dead port 1/2 on $mux $procmux$21048. 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+ dead port 1/2 on $mux $procmux$21390. + dead port 1/2 on $mux $procmux$21393. + dead port 1/2 on $mux $procmux$21396. + dead port 1/2 on $mux $procmux$21399. + dead port 1/2 on $mux $procmux$21402. + dead port 1/2 on $mux $procmux$21405. + dead port 1/2 on $mux $procmux$21408. + dead port 1/2 on $mux $procmux$21411. + dead port 1/2 on $mux $procmux$21414. + dead port 1/2 on $mux $procmux$21417. + dead port 1/2 on $mux $procmux$21420. + dead port 2/2 on $mux $procmux$21423. + dead port 1/2 on $mux $procmux$21430. + dead port 1/2 on $mux $procmux$21433. + dead port 1/2 on $mux $procmux$21436. + dead port 1/2 on $mux $procmux$21439. + dead port 1/2 on $mux $procmux$21442. + dead port 1/2 on $mux $procmux$21445. + dead port 1/2 on $mux $procmux$21448. + dead port 1/2 on $mux $procmux$21451. + dead port 1/2 on $mux $procmux$21454. + dead port 1/2 on $mux $procmux$21457. + dead port 1/2 on $mux $procmux$21460. + dead port 1/2 on $mux $procmux$21463. + dead port 1/2 on $mux $procmux$21466. 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+ dead port 1/2 on $mux $procmux$23785. + dead port 1/2 on $mux $procmux$23788. + dead port 1/2 on $mux $procmux$23791. + dead port 1/2 on $mux $procmux$23794. + dead port 1/2 on $mux $procmux$23797. + dead port 1/2 on $mux $procmux$23800. + dead port 1/2 on $mux $procmux$23803. + dead port 1/2 on $mux $procmux$23806. + dead port 1/2 on $mux $procmux$23809. + dead port 1/2 on $mux $procmux$23812. + dead port 1/2 on $mux $procmux$23815. + dead port 1/2 on $mux $procmux$23818. + dead port 1/2 on $mux $procmux$23821. + dead port 1/2 on $mux $procmux$23824. + dead port 2/2 on $mux $procmux$23826. + dead port 1/2 on $mux $procmux$23829. + dead port 1/2 on $mux $procmux$23832. + dead port 1/2 on $mux $procmux$23835. + dead port 1/2 on $mux $procmux$23838. + dead port 1/2 on $mux $procmux$23841. + dead port 1/2 on $mux $procmux$23844. + dead port 1/2 on $mux $procmux$23847. + dead port 1/2 on $mux $procmux$23850. + dead port 1/2 on $mux $procmux$23853. + dead port 1/2 on $mux $procmux$23856. + dead port 1/2 on $mux $procmux$23859. + dead port 2/2 on $mux $procmux$23862. + dead port 2/2 on $mux $procmux$23956. + dead port 1/2 on $mux $procmux$23959. + dead port 1/2 on $mux $procmux$23962. + dead port 1/2 on $mux $procmux$23965. + dead port 1/2 on $mux $procmux$23968. + dead port 1/2 on $mux $procmux$23971. + dead port 1/2 on $mux $procmux$23974. + dead port 1/2 on $mux $procmux$23977. + dead port 1/2 on $mux $procmux$23980. + dead port 1/2 on $mux $procmux$23983. + dead port 1/2 on $mux $procmux$23986. + dead port 1/2 on $mux $procmux$23989. + dead port 1/2 on $mux $procmux$23992. + dead port 1/2 on $mux $procmux$23995. + dead port 1/2 on $mux $procmux$23998. + dead port 2/2 on $mux $procmux$24000. + dead port 1/2 on $mux $procmux$24003. + dead port 1/2 on $mux $procmux$24006. + dead port 1/2 on $mux $procmux$24009. + dead port 1/2 on $mux $procmux$24012. + dead port 1/2 on $mux $procmux$24015. + dead port 1/2 on $mux $procmux$24018. + dead port 1/2 on $mux $procmux$24021. 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+ dead port 1/2 on $mux $procmux$24102. + dead port 1/2 on $mux $procmux$24105. + dead port 1/2 on $mux $procmux$24108. + dead port 1/2 on $mux $procmux$24111. + dead port 1/2 on $mux $procmux$24114. + dead port 1/2 on $mux $procmux$24117. + dead port 2/2 on $mux $procmux$24120. + dead port 1/2 on $mux $procmux$24127. + dead port 1/2 on $mux $procmux$24130. + dead port 1/2 on $mux $procmux$24133. + dead port 1/2 on $mux $procmux$24136. + dead port 1/2 on $mux $procmux$24139. + dead port 1/2 on $mux $procmux$24142. + dead port 1/2 on $mux $procmux$24145. + dead port 1/2 on $mux $procmux$24148. + dead port 1/2 on $mux $procmux$24151. + dead port 1/2 on $mux $procmux$24154. + dead port 1/2 on $mux $procmux$24157. + dead port 1/2 on $mux $procmux$24160. + dead port 1/2 on $mux $procmux$24163. + dead port 1/2 on $mux $procmux$24166. + dead port 2/2 on $mux $procmux$24168. + dead port 1/2 on $mux $procmux$24171. + dead port 1/2 on $mux $procmux$24174. + dead port 1/2 on $mux $procmux$24177. + dead port 1/2 on $mux $procmux$24180. + dead port 1/2 on $mux $procmux$24183. + dead port 1/2 on $mux $procmux$24186. + dead port 1/2 on $mux $procmux$24189. + dead port 1/2 on $mux $procmux$24192. + dead port 1/2 on $mux $procmux$24195. + dead port 1/2 on $mux $procmux$24198. + dead port 1/2 on $mux $procmux$24201. + dead port 2/2 on $mux $procmux$24204. + dead port 1/2 on $mux $procmux$24211. + dead port 1/2 on $mux $procmux$24214. + dead port 1/2 on $mux $procmux$24217. + dead port 1/2 on $mux $procmux$24220. + dead port 1/2 on $mux $procmux$24223. + dead port 1/2 on $mux $procmux$24226. + dead port 1/2 on $mux $procmux$24229. + dead port 1/2 on $mux $procmux$24232. + dead port 1/2 on $mux $procmux$24235. + dead port 1/2 on $mux $procmux$24238. + dead port 1/2 on $mux $procmux$24241. + dead port 1/2 on $mux $procmux$24244. + dead port 1/2 on $mux $procmux$24247. + dead port 1/2 on $mux $procmux$24250. + dead port 2/2 on $mux $procmux$24252. + dead port 1/2 on $mux $procmux$24255. + dead port 1/2 on $mux $procmux$24258. + dead port 1/2 on $mux $procmux$24261. + dead port 1/2 on $mux $procmux$24264. + dead port 1/2 on $mux $procmux$24267. + dead port 1/2 on $mux $procmux$24270. + dead port 1/2 on $mux $procmux$24273. + dead port 1/2 on $mux $procmux$24276. + dead port 1/2 on $mux $procmux$24279. + dead port 1/2 on $mux $procmux$24282. + dead port 1/2 on $mux $procmux$24285. + dead port 2/2 on $mux $procmux$24288. + dead port 1/2 on $mux $procmux$24379. + dead port 1/2 on $mux $procmux$24382. + dead port 1/2 on $mux $procmux$24385. + dead port 1/2 on $mux $procmux$24388. + dead port 1/2 on $mux $procmux$24391. + dead port 1/2 on $mux $procmux$24394. + dead port 1/2 on $mux $procmux$24397. + dead port 1/2 on $mux $procmux$24400. + dead port 1/2 on $mux $procmux$24403. + dead port 1/2 on $mux $procmux$24406. + dead port 1/2 on $mux $procmux$24409. + dead port 1/2 on $mux $procmux$24412. + dead port 1/2 on $mux $procmux$24415. + dead port 1/2 on $mux $procmux$24418. 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+ dead port 1/2 on $mux $procmux$24499. + dead port 1/2 on $mux $procmux$24502. + dead port 2/2 on $mux $procmux$24504. + dead port 1/2 on $mux $procmux$24507. + dead port 1/2 on $mux $procmux$24510. + dead port 1/2 on $mux $procmux$24513. + dead port 1/2 on $mux $procmux$24516. + dead port 1/2 on $mux $procmux$24519. + dead port 1/2 on $mux $procmux$24522. + dead port 1/2 on $mux $procmux$24525. + dead port 1/2 on $mux $procmux$24528. + dead port 1/2 on $mux $procmux$24531. + dead port 1/2 on $mux $procmux$24534. + dead port 1/2 on $mux $procmux$24537. + dead port 2/2 on $mux $procmux$24540. + dead port 1/2 on $mux $procmux$24547. + dead port 1/2 on $mux $procmux$24550. + dead port 1/2 on $mux $procmux$24553. + dead port 1/2 on $mux $procmux$24556. + dead port 1/2 on $mux $procmux$24559. + dead port 1/2 on $mux $procmux$24562. + dead port 1/2 on $mux $procmux$24565. + dead port 1/2 on $mux $procmux$24568. + dead port 1/2 on $mux $procmux$24571. + dead port 1/2 on $mux $procmux$24574. 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+ dead port 1/2 on $mux $procmux$25365. + dead port 1/2 on $mux $procmux$25368. + dead port 1/2 on $mux $procmux$25371. + dead port 1/2 on $mux $procmux$25374. + dead port 1/2 on $mux $procmux$25377. + dead port 2/2 on $mux $procmux$25380. + dead port 1/2 on $mux $procmux$25387. + dead port 1/2 on $mux $procmux$25390. + dead port 1/2 on $mux $procmux$25393. + dead port 1/2 on $mux $procmux$25396. + dead port 1/2 on $mux $procmux$25399. + dead port 1/2 on $mux $procmux$25402. + dead port 1/2 on $mux $procmux$25405. + dead port 1/2 on $mux $procmux$25408. + dead port 1/2 on $mux $procmux$25411. + dead port 1/2 on $mux $procmux$25414. + dead port 1/2 on $mux $procmux$25417. + dead port 1/2 on $mux $procmux$25420. + dead port 1/2 on $mux $procmux$25423. + dead port 1/2 on $mux $procmux$25426. + dead port 2/2 on $mux $procmux$25428. + dead port 1/2 on $mux $procmux$25431. + dead port 1/2 on $mux $procmux$25434. + dead port 1/2 on $mux $procmux$25437. + dead port 1/2 on $mux $procmux$25440. + dead port 1/2 on $mux $procmux$25443. + dead port 1/2 on $mux $procmux$25446. + dead port 1/2 on $mux $procmux$25449. + dead port 1/2 on $mux $procmux$25452. + dead port 1/2 on $mux $procmux$25455. + dead port 1/2 on $mux $procmux$25458. + dead port 1/2 on $mux $procmux$25461. + dead port 2/2 on $mux $procmux$25464. + dead port 1/2 on $mux $procmux$25471. + dead port 1/2 on $mux $procmux$25474. + dead port 1/2 on $mux $procmux$25477. + dead port 1/2 on $mux $procmux$25480. + dead port 1/2 on $mux $procmux$25483. + dead port 1/2 on $mux $procmux$25486. + dead port 1/2 on $mux $procmux$25489. + dead port 1/2 on $mux $procmux$25492. + dead port 1/2 on $mux $procmux$25495. + dead port 1/2 on $mux $procmux$25498. + dead port 1/2 on $mux $procmux$25501. + dead port 1/2 on $mux $procmux$25504. + dead port 1/2 on $mux $procmux$25507. + dead port 1/2 on $mux $procmux$25510. + dead port 2/2 on $mux $procmux$25512. + dead port 1/2 on $mux $procmux$25515. + dead port 1/2 on $mux $procmux$25518. + dead port 1/2 on $mux $procmux$25521. + dead port 1/2 on $mux $procmux$25524. + dead port 1/2 on $mux $procmux$25527. + dead port 1/2 on $mux $procmux$25530. + dead port 1/2 on $mux $procmux$25533. + dead port 1/2 on $mux $procmux$25536. + dead port 1/2 on $mux $procmux$25539. + dead port 1/2 on $mux $procmux$25542. + dead port 1/2 on $mux $procmux$25545. + dead port 2/2 on $mux $procmux$25548. + dead port 1/2 on $mux $procmux$25555. + dead port 1/2 on $mux $procmux$25558. + dead port 1/2 on $mux $procmux$25561. + dead port 1/2 on $mux $procmux$25564. + dead port 1/2 on $mux $procmux$25567. + dead port 1/2 on $mux $procmux$25570. + dead port 1/2 on $mux $procmux$25573. + dead port 1/2 on $mux $procmux$25576. + dead port 1/2 on $mux $procmux$25579. + dead port 1/2 on $mux $procmux$25582. + dead port 1/2 on $mux $procmux$25585. + dead port 1/2 on $mux $procmux$25588. + dead port 1/2 on $mux $procmux$25591. + dead port 1/2 on $mux $procmux$25594. + dead port 2/2 on $mux $procmux$25596. + dead port 1/2 on $mux $procmux$25599. + dead port 1/2 on $mux $procmux$25602. + dead port 1/2 on $mux $procmux$25605. + dead port 1/2 on $mux $procmux$25608. + dead port 1/2 on $mux $procmux$25611. + dead port 1/2 on $mux $procmux$25614. + dead port 1/2 on $mux $procmux$25617. + dead port 1/2 on $mux $procmux$25620. + dead port 1/2 on $mux $procmux$25623. + dead port 1/2 on $mux $procmux$25626. + dead port 1/2 on $mux $procmux$25629. + dead port 2/2 on $mux $procmux$25632. + dead port 1/2 on $mux $procmux$25807. + dead port 1/2 on $mux $procmux$25810. + dead port 1/2 on $mux $procmux$25813. + dead port 1/2 on $mux $procmux$25816. + dead port 1/2 on $mux $procmux$25819. + dead port 1/2 on $mux $procmux$25822. + dead port 1/2 on $mux $procmux$25825. + dead port 1/2 on $mux $procmux$25828. + dead port 1/2 on $mux $procmux$25831. + dead port 1/2 on $mux $procmux$25834. + dead port 1/2 on $mux $procmux$25837. + dead port 1/2 on $mux $procmux$25840. + dead port 1/2 on $mux $procmux$25843. + dead port 1/2 on $mux $procmux$25846. + dead port 2/2 on $mux $procmux$25848. + dead port 1/2 on $mux $procmux$25851. + dead port 1/2 on $mux $procmux$25854. + dead port 1/2 on $mux $procmux$25857. + dead port 1/2 on $mux $procmux$25860. + dead port 1/2 on $mux $procmux$25863. + dead port 1/2 on $mux $procmux$25866. + dead port 1/2 on $mux $procmux$25869. + dead port 1/2 on $mux $procmux$25872. + dead port 1/2 on $mux $procmux$25875. + dead port 1/2 on $mux $procmux$25878. + dead port 1/2 on $mux $procmux$25881. + dead port 2/2 on $mux $procmux$25884. + dead port 1/2 on $mux $procmux$25891. + dead port 1/2 on $mux $procmux$25894. + dead port 1/2 on $mux $procmux$25897. + dead port 1/2 on $mux $procmux$25900. + dead port 1/2 on $mux $procmux$25903. + dead port 1/2 on $mux $procmux$25906. + dead port 1/2 on $mux $procmux$25909. + dead port 1/2 on $mux $procmux$25912. + dead port 1/2 on $mux $procmux$25915. + dead port 1/2 on $mux $procmux$25918. + dead port 1/2 on $mux $procmux$25921. + dead port 1/2 on $mux $procmux$25924. + dead port 1/2 on $mux $procmux$25927. + dead port 1/2 on $mux $procmux$25930. + dead port 2/2 on $mux $procmux$25932. + dead port 1/2 on $mux $procmux$25935. + dead port 1/2 on $mux $procmux$25938. + dead port 1/2 on $mux $procmux$25941. + dead port 1/2 on $mux $procmux$25944. + dead port 1/2 on $mux $procmux$25947. + dead port 1/2 on $mux $procmux$25950. + dead port 1/2 on $mux $procmux$25953. + dead port 1/2 on $mux $procmux$25956. + dead port 1/2 on $mux $procmux$25959. + dead port 1/2 on $mux $procmux$25962. + dead port 1/2 on $mux $procmux$25965. + dead port 2/2 on $mux $procmux$25968. + dead port 1/2 on $mux $procmux$25975. + dead port 1/2 on $mux $procmux$25978. + dead port 1/2 on $mux $procmux$25981. + dead port 1/2 on $mux $procmux$25984. + dead port 1/2 on $mux $procmux$25987. + dead port 1/2 on $mux $procmux$25990. + dead port 1/2 on $mux $procmux$25993. + dead port 1/2 on $mux $procmux$25996. + dead port 1/2 on $mux $procmux$25999. + dead port 1/2 on $mux $procmux$26002. + dead port 1/2 on $mux $procmux$26005. + dead port 1/2 on $mux $procmux$26008. + dead port 1/2 on $mux $procmux$26011. + dead port 1/2 on $mux $procmux$26014. + dead port 2/2 on $mux $procmux$26016. + dead port 1/2 on $mux $procmux$26019. + dead port 1/2 on $mux $procmux$26022. + dead port 1/2 on $mux $procmux$26025. + dead port 1/2 on $mux $procmux$26028. + dead port 1/2 on $mux $procmux$26031. + dead port 1/2 on $mux $procmux$26034. + dead port 1/2 on $mux $procmux$26037. + dead port 1/2 on $mux $procmux$26040. + dead port 1/2 on $mux $procmux$26043. + dead port 1/2 on $mux $procmux$26046. + dead port 1/2 on $mux $procmux$26049. + dead port 2/2 on $mux $procmux$26052. + dead port 1/2 on $mux $procmux$26059. + dead port 1/2 on $mux $procmux$26062. + dead port 1/2 on $mux $procmux$26065. + dead port 1/2 on $mux $procmux$26068. + dead port 1/2 on $mux $procmux$26071. + dead port 1/2 on $mux $procmux$26074. + dead port 1/2 on $mux $procmux$26077. + dead port 1/2 on $mux $procmux$26080. + dead port 1/2 on $mux $procmux$26083. + dead port 1/2 on $mux $procmux$26086. + dead port 1/2 on $mux $procmux$26089. + dead port 1/2 on $mux $procmux$26092. + dead port 1/2 on $mux $procmux$26095. + dead port 1/2 on $mux $procmux$26098. + dead port 2/2 on $mux $procmux$26100. + dead port 1/2 on $mux $procmux$26103. + dead port 1/2 on $mux $procmux$26106. + dead port 1/2 on $mux $procmux$26109. + dead port 1/2 on $mux $procmux$26112. + dead port 1/2 on $mux $procmux$26115. + dead port 1/2 on $mux $procmux$26118. + dead port 1/2 on $mux $procmux$26121. + dead port 1/2 on $mux $procmux$26124. + dead port 1/2 on $mux $procmux$26127. + dead port 1/2 on $mux $procmux$26130. + dead port 1/2 on $mux $procmux$26133. + dead port 2/2 on $mux $procmux$26136. + dead port 1/2 on $mux $procmux$26395. + dead port 1/2 on $mux $procmux$26398. + dead port 1/2 on $mux $procmux$26401. + dead port 1/2 on $mux $procmux$26404. + dead port 1/2 on $mux $procmux$26407. + dead port 1/2 on $mux $procmux$26410. + dead port 1/2 on $mux $procmux$26413. + dead port 1/2 on $mux $procmux$26416. + dead port 1/2 on $mux $procmux$26419. + dead port 1/2 on $mux $procmux$26422. + dead port 1/2 on $mux $procmux$26425. + dead port 1/2 on $mux $procmux$26428. + dead port 1/2 on $mux $procmux$26431. + dead port 1/2 on $mux $procmux$26434. + dead port 1/2 on $mux $procmux$26437. + dead port 1/2 on $mux $procmux$26440. + dead port 2/2 on $mux $procmux$26442. + dead port 1/2 on $mux $procmux$26445. + dead port 1/2 on $mux $procmux$26448. + dead port 1/2 on $mux $procmux$26451. + dead port 1/2 on $mux $procmux$26454. + dead port 1/2 on $mux $procmux$26457. + dead port 1/2 on $mux $procmux$26460. + dead port 1/2 on $mux $procmux$26463. + dead port 1/2 on $mux $procmux$26466. + dead port 1/2 on $mux $procmux$26469. + dead port 1/2 on $mux $procmux$26472. + dead port 1/2 on $mux $procmux$26475. + dead port 2/2 on $mux $procmux$26478. + dead port 1/2 on $mux $procmux$26485. + dead port 1/2 on $mux $procmux$26488. + dead port 1/2 on $mux $procmux$26491. + dead port 1/2 on $mux $procmux$26494. + dead port 1/2 on $mux $procmux$26497. + dead port 1/2 on $mux $procmux$26500. + dead port 1/2 on $mux $procmux$26503. + dead port 1/2 on $mux $procmux$26506. + dead port 1/2 on $mux $procmux$26509. + dead port 1/2 on $mux $procmux$26512. + dead port 1/2 on $mux $procmux$26515. + dead port 1/2 on $mux $procmux$26518. + dead port 1/2 on $mux $procmux$26521. + dead port 1/2 on $mux $procmux$26524. + dead port 1/2 on $mux $procmux$26527. + dead port 1/2 on $mux $procmux$26530. + dead port 2/2 on $mux $procmux$26532. + dead port 1/2 on $mux $procmux$26535. + dead port 1/2 on $mux $procmux$26538. + dead port 1/2 on $mux $procmux$26541. + dead port 1/2 on $mux $procmux$26544. + dead port 1/2 on $mux $procmux$26547. + dead port 1/2 on $mux $procmux$26550. + dead port 1/2 on $mux $procmux$26553. + dead port 1/2 on $mux $procmux$26556. + dead port 1/2 on $mux $procmux$26559. + dead port 1/2 on $mux $procmux$26562. + dead port 1/2 on $mux $procmux$26565. + dead port 2/2 on $mux $procmux$26568. + dead port 1/2 on $mux $procmux$26575. + dead port 1/2 on $mux $procmux$26578. + dead port 1/2 on $mux $procmux$26581. + dead port 1/2 on $mux $procmux$26584. + dead port 1/2 on $mux $procmux$26587. + dead port 1/2 on $mux $procmux$26590. + dead port 1/2 on $mux $procmux$26593. + dead port 1/2 on $mux $procmux$26596. + dead port 1/2 on $mux $procmux$26599. + dead port 1/2 on $mux $procmux$26602. + dead port 1/2 on $mux $procmux$26605. + dead port 1/2 on $mux $procmux$26608. + dead port 1/2 on $mux $procmux$26611. + dead port 1/2 on $mux $procmux$26614. + dead port 1/2 on $mux $procmux$26617. + dead port 2/2 on $mux $procmux$26619. + dead port 1/2 on $mux $procmux$26622. + dead port 1/2 on $mux $procmux$26625. + dead port 1/2 on $mux $procmux$26628. + dead port 1/2 on $mux $procmux$26631. + dead port 1/2 on $mux $procmux$26634. + dead port 1/2 on $mux $procmux$26637. + dead port 1/2 on $mux $procmux$26640. + dead port 1/2 on $mux $procmux$26643. + dead port 1/2 on $mux $procmux$26646. + dead port 1/2 on $mux $procmux$26649. + dead port 1/2 on $mux $procmux$26652. + dead port 2/2 on $mux $procmux$26655. + dead port 1/2 on $mux $procmux$26662. + dead port 1/2 on $mux $procmux$26665. + dead port 1/2 on $mux $procmux$26668. + dead port 1/2 on $mux $procmux$26671. + dead port 1/2 on $mux $procmux$26674. + dead port 1/2 on $mux $procmux$26677. + dead port 1/2 on $mux $procmux$26680. + dead port 1/2 on $mux $procmux$26683. + dead port 1/2 on $mux $procmux$26686. + dead port 1/2 on $mux $procmux$26689. + dead port 1/2 on $mux $procmux$26692. + dead port 1/2 on $mux $procmux$26695. + dead port 1/2 on $mux $procmux$26698. + dead port 1/2 on $mux $procmux$26701. + dead port 1/2 on $mux $procmux$26704. + dead port 2/2 on $mux $procmux$26706. + dead port 1/2 on $mux $procmux$26709. + dead port 1/2 on $mux $procmux$26712. + dead port 1/2 on $mux $procmux$26715. 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+ dead port 1/2 on $mux $procmux$26796. + dead port 1/2 on $mux $procmux$26799. + dead port 1/2 on $mux $procmux$26802. + dead port 1/2 on $mux $procmux$26805. + dead port 1/2 on $mux $procmux$26808. + dead port 1/2 on $mux $procmux$26811. + dead port 1/2 on $mux $procmux$26814. + dead port 1/2 on $mux $procmux$26817. + dead port 1/2 on $mux $procmux$26820. + dead port 1/2 on $mux $procmux$26823. + dead port 2/2 on $mux $procmux$26826. + dead port 1/2 on $mux $procmux$27970. + dead port 1/2 on $mux $procmux$27973. + dead port 1/2 on $mux $procmux$27976. + dead port 1/2 on $mux $procmux$27979. + dead port 1/2 on $mux $procmux$27982. + dead port 1/2 on $mux $procmux$27985. + dead port 1/2 on $mux $procmux$27988. + dead port 1/2 on $mux $procmux$27991. + dead port 1/2 on $mux $procmux$27994. + dead port 1/2 on $mux $procmux$27997. + dead port 1/2 on $mux $procmux$28000. + dead port 1/2 on $mux $procmux$28003. + dead port 1/2 on $mux $procmux$28006. + dead port 2/2 on $mux $procmux$28008. + dead port 1/2 on $mux $procmux$28011. + dead port 1/2 on $mux $procmux$28014. + dead port 1/2 on $mux $procmux$28017. + dead port 1/2 on $mux $procmux$28020. + dead port 1/2 on $mux $procmux$28023. + dead port 1/2 on $mux $procmux$28026. + dead port 1/2 on $mux $procmux$28029. + dead port 1/2 on $mux $procmux$28032. + dead port 1/2 on $mux $procmux$28035. + dead port 1/2 on $mux $procmux$28038. + dead port 1/2 on $mux $procmux$28041. + dead port 2/2 on $mux $procmux$28044. + dead port 1/2 on $mux $procmux$28051. + dead port 1/2 on $mux $procmux$28054. + dead port 1/2 on $mux $procmux$28057. + dead port 1/2 on $mux $procmux$28060. + dead port 1/2 on $mux $procmux$28063. + dead port 1/2 on $mux $procmux$28066. + dead port 1/2 on $mux $procmux$28069. + dead port 1/2 on $mux $procmux$28072. + dead port 1/2 on $mux $procmux$28075. + dead port 1/2 on $mux $procmux$28078. + dead port 1/2 on $mux $procmux$28081. + dead port 1/2 on $mux $procmux$28084. + dead port 1/2 on $mux $procmux$28087. + dead port 2/2 on $mux $procmux$28089. + dead port 1/2 on $mux $procmux$28092. + dead port 1/2 on $mux $procmux$28095. + dead port 1/2 on $mux $procmux$28098. + dead port 1/2 on $mux $procmux$28101. + dead port 1/2 on $mux $procmux$28104. + dead port 1/2 on $mux $procmux$28107. + dead port 1/2 on $mux $procmux$28110. + dead port 1/2 on $mux $procmux$28113. + dead port 1/2 on $mux $procmux$28116. + dead port 1/2 on $mux $procmux$28119. + dead port 1/2 on $mux $procmux$28122. + dead port 2/2 on $mux $procmux$28125. + dead port 1/2 on $mux $procmux$28213. + dead port 1/2 on $mux $procmux$28216. + dead port 1/2 on $mux $procmux$28219. + dead port 1/2 on $mux $procmux$28222. + dead port 1/2 on $mux $procmux$28225. + dead port 1/2 on $mux $procmux$28228. + dead port 1/2 on $mux $procmux$28231. + dead port 1/2 on $mux $procmux$28234. + dead port 1/2 on $mux $procmux$28237. + dead port 1/2 on $mux $procmux$28240. + dead port 1/2 on $mux $procmux$28243. + dead port 1/2 on $mux $procmux$28246. + dead port 1/2 on $mux $procmux$28249. + dead port 2/2 on $mux $procmux$28251. + dead port 1/2 on $mux $procmux$28254. + dead port 1/2 on $mux $procmux$28257. + dead port 1/2 on $mux $procmux$28260. + dead port 1/2 on $mux $procmux$28263. + dead port 1/2 on $mux $procmux$28266. + dead port 1/2 on $mux $procmux$28269. + dead port 1/2 on $mux $procmux$28272. + dead port 1/2 on $mux $procmux$28275. + dead port 1/2 on $mux $procmux$28278. + dead port 1/2 on $mux $procmux$28281. + dead port 1/2 on $mux $procmux$28284. + dead port 2/2 on $mux $procmux$28287. + dead port 1/2 on $mux $procmux$28294. + dead port 1/2 on $mux $procmux$28297. + dead port 1/2 on $mux $procmux$28300. + dead port 1/2 on $mux $procmux$28303. + dead port 1/2 on $mux $procmux$28306. + dead port 1/2 on $mux $procmux$28309. + dead port 1/2 on $mux $procmux$28312. + dead port 1/2 on $mux $procmux$28315. + dead port 1/2 on $mux $procmux$28318. + dead port 1/2 on $mux $procmux$28321. + dead port 1/2 on $mux $procmux$28324. + dead port 1/2 on $mux $procmux$28327. + dead port 1/2 on $mux $procmux$28330. + dead port 2/2 on $mux $procmux$28332. + dead port 1/2 on $mux $procmux$28335. + dead port 1/2 on $mux $procmux$28338. + dead port 1/2 on $mux $procmux$28341. + dead port 1/2 on $mux $procmux$28344. + dead port 1/2 on $mux $procmux$28347. + dead port 1/2 on $mux $procmux$28350. + dead port 1/2 on $mux $procmux$28353. + dead port 1/2 on $mux $procmux$28356. + dead port 1/2 on $mux $procmux$28359. + dead port 1/2 on $mux $procmux$28362. + dead port 1/2 on $mux $procmux$28365. + dead port 2/2 on $mux $procmux$28368. + dead port 1/2 on $mux $procmux$28375. + dead port 1/2 on $mux $procmux$28378. + dead port 1/2 on $mux $procmux$28381. + dead port 1/2 on $mux $procmux$28384. + dead port 1/2 on $mux $procmux$28387. + dead port 1/2 on $mux $procmux$28390. + dead port 1/2 on $mux $procmux$28393. + dead port 1/2 on $mux $procmux$28396. + dead port 1/2 on $mux $procmux$28399. + dead port 1/2 on $mux $procmux$28402. + dead port 1/2 on $mux $procmux$28405. + dead port 1/2 on $mux $procmux$28408. + dead port 1/2 on $mux $procmux$28411. + dead port 2/2 on $mux $procmux$28413. + dead port 1/2 on $mux $procmux$28416. + dead port 1/2 on $mux $procmux$28419. + dead port 1/2 on $mux $procmux$28422. + dead port 1/2 on $mux $procmux$28425. + dead port 1/2 on $mux $procmux$28428. + dead port 1/2 on $mux $procmux$28431. + dead port 1/2 on $mux $procmux$28434. + dead port 1/2 on $mux $procmux$28437. + dead port 1/2 on $mux $procmux$28440. + dead port 1/2 on $mux $procmux$28443. + dead port 1/2 on $mux $procmux$28446. + dead port 2/2 on $mux $procmux$28449. + dead port 1/2 on $mux $procmux$28456. + dead port 1/2 on $mux $procmux$28459. + dead port 1/2 on $mux $procmux$28462. + dead port 1/2 on $mux $procmux$28465. + dead port 1/2 on $mux $procmux$28468. + dead port 1/2 on $mux $procmux$28471. + dead port 1/2 on $mux $procmux$28474. + dead port 1/2 on $mux $procmux$28477. + dead port 1/2 on $mux $procmux$28480. + dead port 1/2 on $mux $procmux$28483. + dead port 1/2 on $mux $procmux$28486. + dead port 1/2 on $mux $procmux$28489. + dead port 1/2 on $mux $procmux$28492. + dead port 2/2 on $mux $procmux$28494. + dead port 1/2 on $mux $procmux$28497. + dead port 1/2 on $mux $procmux$28500. + dead port 1/2 on $mux $procmux$28503. + dead port 1/2 on $mux $procmux$28506. + dead port 1/2 on $mux $procmux$28509. + dead port 1/2 on $mux $procmux$28512. + dead port 1/2 on $mux $procmux$28515. + dead port 1/2 on $mux $procmux$28518. + dead port 1/2 on $mux $procmux$28521. + dead port 1/2 on $mux $procmux$28524. + dead port 1/2 on $mux $procmux$28527. + dead port 2/2 on $mux $procmux$28530. + dead port 1/2 on $mux $procmux$28537. + dead port 1/2 on $mux $procmux$28540. + dead port 1/2 on $mux $procmux$28543. + dead port 1/2 on $mux $procmux$28546. + dead port 1/2 on $mux $procmux$28549. + dead port 1/2 on $mux $procmux$28552. + dead port 1/2 on $mux $procmux$28555. + dead port 1/2 on $mux $procmux$28558. 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+ dead port 1/2 on $mux $procmux$28957. + dead port 1/2 on $mux $procmux$28960. + dead port 1/2 on $mux $procmux$28963. + dead port 1/2 on $mux $procmux$28966. + dead port 1/2 on $mux $procmux$28969. + dead port 1/2 on $mux $procmux$28972. + dead port 1/2 on $mux $procmux$28975. + dead port 1/2 on $mux $procmux$28978. + dead port 2/2 on $mux $procmux$28980. + dead port 1/2 on $mux $procmux$28983. + dead port 1/2 on $mux $procmux$28986. + dead port 1/2 on $mux $procmux$28989. + dead port 1/2 on $mux $procmux$28992. + dead port 1/2 on $mux $procmux$28995. + dead port 1/2 on $mux $procmux$28998. + dead port 1/2 on $mux $procmux$29001. + dead port 1/2 on $mux $procmux$29004. + dead port 1/2 on $mux $procmux$29007. + dead port 1/2 on $mux $procmux$29010. + dead port 1/2 on $mux $procmux$29013. + dead port 2/2 on $mux $procmux$29016. + dead port 1/2 on $mux $procmux$29023. + dead port 1/2 on $mux $procmux$29026. + dead port 1/2 on $mux $procmux$29029. + dead port 1/2 on $mux $procmux$29032. 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dead port 2/2 on $mux $procmux$3224. + dead port 1/2 on $mux $procmux$32242. + dead port 2/2 on $mux $procmux$32244. + dead port 1/2 on $mux $procmux$32247. + dead port 1/2 on $mux $procmux$32250. + dead port 1/2 on $mux $procmux$32253. + dead port 1/2 on $mux $procmux$32256. + dead port 1/2 on $mux $procmux$32259. + dead port 1/2 on $mux $procmux$32262. + dead port 1/2 on $mux $procmux$32265. + dead port 1/2 on $mux $procmux$32268. + dead port 1/2 on $mux $procmux$3227. + dead port 1/2 on $mux $procmux$32271. + dead port 1/2 on $mux $procmux$32274. + dead port 1/2 on $mux $procmux$32277. + dead port 2/2 on $mux $procmux$32280. + dead port 1/2 on $mux $procmux$32287. + dead port 1/2 on $mux $procmux$32290. + dead port 1/2 on $mux $procmux$32293. + dead port 1/2 on $mux $procmux$32296. + dead port 1/2 on $mux $procmux$32299. + dead port 1/2 on $mux $procmux$3230. + dead port 1/2 on $mux $procmux$32302. + dead port 1/2 on $mux $procmux$32305. + dead port 1/2 on $mux $procmux$32308. + dead port 1/2 on $mux $procmux$32311. + dead port 1/2 on $mux $procmux$32314. + dead port 1/2 on $mux $procmux$32317. + dead port 1/2 on $mux $procmux$32320. + dead port 2/2 on $mux $procmux$32322. + dead port 1/2 on $mux $procmux$32325. + dead port 1/2 on $mux $procmux$32328. + dead port 1/2 on $mux $procmux$3233. + dead port 1/2 on $mux $procmux$32331. + dead port 1/2 on $mux $procmux$32334. + dead port 1/2 on $mux $procmux$32337. + dead port 1/2 on $mux $procmux$32340. + dead port 1/2 on $mux $procmux$32343. + dead port 1/2 on $mux $procmux$32346. + dead port 1/2 on $mux $procmux$32349. + dead port 1/2 on $mux $procmux$32352. + dead port 1/2 on $mux $procmux$32355. + dead port 2/2 on $mux $procmux$32358. + dead port 1/2 on $mux $procmux$3236. + dead port 1/2 on $mux $procmux$32365. + dead port 1/2 on $mux $procmux$32368. + dead port 1/2 on $mux $procmux$32371. + dead port 1/2 on $mux $procmux$32374. + dead port 1/2 on $mux $procmux$32377. + dead port 1/2 on $mux $procmux$32380. + dead port 1/2 on $mux $procmux$32383. + dead port 1/2 on $mux $procmux$32386. + dead port 1/2 on $mux $procmux$32389. + dead port 1/2 on $mux $procmux$3239. + dead port 1/2 on $mux $procmux$32392. + dead port 1/2 on $mux $procmux$32395. + dead port 1/2 on $mux $procmux$32398. + dead port 2/2 on $mux $procmux$32400. + dead port 1/2 on $mux $procmux$32403. + dead port 1/2 on $mux $procmux$32406. + dead port 1/2 on $mux $procmux$32409. + dead port 1/2 on $mux $procmux$32412. + dead port 1/2 on $mux $procmux$32415. + dead port 1/2 on $mux $procmux$32418. + dead port 1/2 on $mux $procmux$3242. + dead port 1/2 on $mux $procmux$32421. + dead port 1/2 on $mux $procmux$32424. + dead port 1/2 on $mux $procmux$32427. + dead port 1/2 on $mux $procmux$32430. + dead port 1/2 on $mux $procmux$32433. + dead port 2/2 on $mux $procmux$32436. + dead port 1/2 on $mux $procmux$32443. + dead port 1/2 on $mux $procmux$32446. + dead port 1/2 on $mux $procmux$32449. + dead port 1/2 on $mux $procmux$3245. + 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dead port 1/2 on $mux $procmux$32524. + dead port 1/2 on $mux $procmux$32527. + dead port 1/2 on $mux $procmux$32530. + dead port 1/2 on $mux $procmux$32533. + dead port 1/2 on $mux $procmux$32536. + dead port 1/2 on $mux $procmux$32539. + dead port 1/2 on $mux $procmux$3254. + dead port 1/2 on $mux $procmux$32542. + dead port 1/2 on $mux $procmux$32545. + dead port 1/2 on $mux $procmux$32548. + dead port 1/2 on $mux $procmux$32551. + dead port 1/2 on $mux $procmux$32554. + dead port 2/2 on $mux $procmux$32556. + dead port 1/2 on $mux $procmux$32559. + dead port 1/2 on $mux $procmux$32562. + dead port 1/2 on $mux $procmux$32565. + dead port 1/2 on $mux $procmux$32568. + dead port 1/2 on $mux $procmux$3257. + dead port 1/2 on $mux $procmux$32571. + dead port 1/2 on $mux $procmux$32574. + dead port 1/2 on $mux $procmux$32577. + dead port 1/2 on $mux $procmux$32580. + dead port 1/2 on $mux $procmux$32583. + dead port 1/2 on $mux $procmux$32586. + dead port 1/2 on $mux $procmux$32589. + dead port 2/2 on $mux $procmux$32592. + dead port 1/2 on $mux $procmux$32599. + dead port 1/2 on $mux $procmux$3260. + dead port 1/2 on $mux $procmux$32602. + dead port 1/2 on $mux $procmux$32605. + dead port 1/2 on $mux $procmux$32608. + dead port 1/2 on $mux $procmux$32611. + dead port 1/2 on $mux $procmux$32614. + dead port 1/2 on $mux $procmux$32617. + dead port 1/2 on $mux $procmux$32620. + dead port 1/2 on $mux $procmux$32623. + dead port 1/2 on $mux $procmux$32626. + dead port 1/2 on $mux $procmux$32629. + dead port 1/2 on $mux $procmux$3263. + dead port 1/2 on $mux $procmux$32632. + dead port 2/2 on $mux $procmux$32634. + dead port 1/2 on $mux $procmux$32637. + dead port 1/2 on $mux $procmux$32640. + dead port 1/2 on $mux $procmux$32643. + dead port 1/2 on $mux $procmux$32646. + dead port 1/2 on $mux $procmux$32649. + dead port 1/2 on $mux $procmux$32652. + dead port 1/2 on $mux $procmux$32655. + dead port 1/2 on $mux $procmux$32658. + dead port 1/2 on $mux $procmux$3266. + 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$procmux$37977. + dead port 1/2 on $mux $procmux$37980. + dead port 1/2 on $mux $procmux$37983. + dead port 1/2 on $mux $procmux$37986. + dead port 1/2 on $mux $procmux$37989. + dead port 1/2 on $mux $procmux$37992. + dead port 2/2 on $mux $procmux$37995. + dead port 1/2 on $mux $procmux$3800. + dead port 1/2 on $mux $procmux$38002. + dead port 1/2 on $mux $procmux$38005. + dead port 1/2 on $mux $procmux$38008. + dead port 1/2 on $mux $procmux$38011. + dead port 1/2 on $mux $procmux$38014. + dead port 1/2 on $mux $procmux$38017. + dead port 1/2 on $mux $procmux$38020. + dead port 1/2 on $mux $procmux$38023. + dead port 1/2 on $mux $procmux$38026. + dead port 1/2 on $mux $procmux$38029. + dead port 1/2 on $mux $procmux$3803. + dead port 1/2 on $mux $procmux$38032. + dead port 2/2 on $mux $procmux$38034. + dead port 1/2 on $mux $procmux$38037. + dead port 1/2 on $mux $procmux$38040. + dead port 1/2 on $mux $procmux$38043. + dead port 1/2 on $mux $procmux$38046. + dead port 1/2 on $mux $procmux$38049. + dead port 1/2 on $mux $procmux$38052. + dead port 1/2 on $mux $procmux$38055. + dead port 1/2 on $mux $procmux$38058. + dead port 1/2 on $mux $procmux$3806. + dead port 1/2 on $mux $procmux$38061. + dead port 1/2 on $mux $procmux$38064. + dead port 1/2 on $mux $procmux$38067. + dead port 2/2 on $mux $procmux$38070. + dead port 1/2 on $mux $procmux$38077. + dead port 1/2 on $mux $procmux$38080. + dead port 1/2 on $mux $procmux$38083. + dead port 1/2 on $mux $procmux$38086. + dead port 1/2 on $mux $procmux$38089. + dead port 1/2 on $mux $procmux$3809. + dead port 1/2 on $mux $procmux$38092. + dead port 1/2 on $mux $procmux$38095. + dead port 1/2 on $mux $procmux$38098. + dead port 1/2 on $mux $procmux$38101. + dead port 1/2 on $mux $procmux$38104. + dead port 1/2 on $mux $procmux$38107. + dead port 2/2 on $mux $procmux$38109. + dead port 1/2 on $mux $procmux$38112. + dead port 1/2 on $mux $procmux$38115. + dead port 1/2 on $mux $procmux$38118. + dead port 1/2 on $mux $procmux$3812. + dead port 1/2 on $mux $procmux$38121. + dead port 1/2 on $mux $procmux$38124. + dead port 1/2 on $mux $procmux$38127. + dead port 1/2 on $mux $procmux$38130. + dead port 1/2 on $mux $procmux$38133. + dead port 1/2 on $mux $procmux$38136. + dead port 1/2 on $mux $procmux$38139. + dead port 1/2 on $mux $procmux$38142. + dead port 2/2 on $mux $procmux$38145. + dead port 1/2 on $mux $procmux$3815. + dead port 1/2 on $mux $procmux$38152. + dead port 1/2 on $mux $procmux$38155. + dead port 1/2 on $mux $procmux$38158. + dead port 1/2 on $mux $procmux$38161. + dead port 1/2 on $mux $procmux$38164. + dead port 1/2 on $mux $procmux$38167. + dead port 1/2 on $mux $procmux$38170. + dead port 1/2 on $mux $procmux$38173. + dead port 1/2 on $mux $procmux$38176. + dead port 1/2 on $mux $procmux$38179. + dead port 1/2 on $mux $procmux$3818. + dead port 1/2 on $mux $procmux$38182. + dead port 2/2 on $mux $procmux$38184. + dead port 1/2 on $mux $procmux$38187. + dead port 1/2 on $mux $procmux$38190. + dead port 1/2 on $mux $procmux$38193. + dead port 1/2 on $mux $procmux$38196. + dead port 1/2 on $mux $procmux$38199. + dead port 1/2 on $mux $procmux$38202. + dead port 1/2 on $mux $procmux$38205. + dead port 1/2 on $mux $procmux$38208. + dead port 1/2 on $mux $procmux$3821. + dead port 1/2 on $mux $procmux$38211. + dead port 1/2 on $mux $procmux$38214. + dead port 1/2 on $mux $procmux$38217. + dead port 2/2 on $mux $procmux$38220. + dead port 1/2 on $mux $procmux$38227. + dead port 1/2 on $mux $procmux$38230. + dead port 1/2 on $mux $procmux$38233. + dead port 1/2 on $mux $procmux$38236. + dead port 1/2 on $mux $procmux$38239. + dead port 1/2 on $mux $procmux$3824. + dead port 1/2 on $mux $procmux$38242. + dead port 1/2 on $mux $procmux$38245. + dead port 1/2 on $mux $procmux$38248. + dead port 1/2 on $mux $procmux$38251. + dead port 1/2 on $mux $procmux$38254. + dead port 1/2 on $mux $procmux$38257. + dead port 2/2 on $mux $procmux$38259. + dead port 1/2 on $mux $procmux$38262. + dead port 1/2 on $mux $procmux$38265. + dead port 1/2 on $mux $procmux$38268. + dead port 1/2 on $mux $procmux$3827. + dead port 1/2 on $mux $procmux$38271. + dead port 1/2 on $mux $procmux$38274. + dead port 1/2 on $mux $procmux$38277. + dead port 1/2 on $mux $procmux$38280. + dead port 1/2 on $mux $procmux$38283. + dead port 1/2 on $mux $procmux$38286. + dead port 1/2 on $mux $procmux$38289. + dead port 1/2 on $mux $procmux$38292. + dead port 2/2 on $mux $procmux$38295. + dead port 1/2 on $mux $procmux$3830. + dead port 1/2 on $mux $procmux$3833. + dead port 2/2 on $mux $procmux$3835. + dead port 1/2 on $mux $procmux$38377. + dead port 1/2 on $mux $procmux$3838. + dead port 1/2 on $mux $procmux$38380. + dead port 1/2 on $mux $procmux$38383. + dead port 1/2 on $mux $procmux$38386. + dead port 1/2 on $mux $procmux$38389. + dead port 1/2 on $mux $procmux$38392. + dead port 1/2 on $mux $procmux$38395. + dead port 1/2 on $mux $procmux$38398. + dead port 1/2 on $mux $procmux$38401. + dead port 1/2 on $mux $procmux$38404. + dead port 1/2 on $mux $procmux$38407. + dead port 2/2 on $mux $procmux$38409. + dead port 1/2 on $mux $procmux$3841. + dead port 1/2 on $mux $procmux$38412. + dead port 1/2 on $mux $procmux$38415. + dead port 1/2 on $mux $procmux$38418. + dead port 1/2 on $mux $procmux$38421. + dead port 1/2 on $mux $procmux$38424. + dead port 1/2 on $mux $procmux$38427. + dead port 1/2 on $mux $procmux$38430. + dead port 1/2 on $mux $procmux$38433. + dead port 1/2 on $mux $procmux$38436. + dead port 1/2 on $mux $procmux$38439. + dead port 1/2 on $mux $procmux$3844. + dead port 1/2 on $mux $procmux$38442. + dead port 2/2 on $mux $procmux$38445. + dead port 1/2 on $mux $procmux$38452. + dead port 1/2 on $mux $procmux$38455. + dead port 1/2 on $mux $procmux$38458. + dead port 1/2 on $mux $procmux$38461. + dead port 1/2 on $mux $procmux$38464. + dead port 1/2 on $mux $procmux$38467. + dead port 1/2 on $mux $procmux$3847. + dead port 1/2 on $mux $procmux$38470. + dead port 1/2 on $mux $procmux$38473. + dead port 1/2 on $mux $procmux$38476. + dead port 1/2 on $mux $procmux$38479. + dead port 1/2 on $mux $procmux$38482. + dead port 2/2 on $mux $procmux$38484. + dead port 1/2 on $mux $procmux$38487. + dead port 1/2 on $mux $procmux$38490. + dead port 1/2 on $mux $procmux$38493. + dead port 1/2 on $mux $procmux$38496. + dead port 1/2 on $mux $procmux$38499. + dead port 1/2 on $mux $procmux$3850. + dead port 1/2 on $mux $procmux$38502. + dead port 1/2 on $mux $procmux$38505. + dead port 1/2 on $mux $procmux$38508. + dead port 1/2 on $mux $procmux$38511. + dead port 1/2 on $mux $procmux$38514. + dead port 1/2 on $mux $procmux$38517. + dead port 2/2 on $mux $procmux$38520. + dead port 1/2 on $mux $procmux$38527. + dead port 1/2 on $mux $procmux$3853. + dead port 1/2 on $mux $procmux$38530. + dead port 1/2 on $mux $procmux$38533. + dead port 1/2 on $mux $procmux$38536. + dead port 1/2 on $mux $procmux$38539. + dead port 1/2 on $mux $procmux$38542. + dead port 1/2 on $mux $procmux$38545. + dead port 1/2 on $mux $procmux$38548. + dead port 1/2 on $mux $procmux$38551. + dead port 1/2 on $mux $procmux$38554. + dead port 1/2 on $mux $procmux$38557. + dead port 2/2 on $mux $procmux$38559. + dead port 1/2 on $mux $procmux$3856. + dead port 1/2 on $mux $procmux$38562. + dead port 1/2 on $mux $procmux$38565. + dead port 1/2 on $mux $procmux$38568. + dead port 1/2 on $mux $procmux$38571. + dead port 1/2 on $mux $procmux$38574. + dead port 1/2 on $mux $procmux$38577. + dead port 1/2 on $mux $procmux$38580. + dead port 1/2 on $mux $procmux$38583. + dead port 1/2 on $mux $procmux$38586. + dead port 1/2 on $mux $procmux$38589. + dead port 1/2 on $mux $procmux$3859. + dead port 1/2 on $mux $procmux$38592. + dead port 2/2 on $mux $procmux$38595. + dead port 1/2 on $mux $procmux$3862. + dead port 1/2 on $mux $procmux$3865. + dead port 1/2 on $mux $procmux$3868. + dead port 2/2 on $mux $procmux$3871. + dead port 1/2 on $mux $procmux$3878. + dead port 2/2 on $mux $procmux$3881. + dead port 1/2 on $mux $procmux$38827. + dead port 1/2 on $mux $procmux$38830. + dead port 1/2 on $mux $procmux$38833. + dead port 1/2 on $mux $procmux$38836. + dead port 1/2 on $mux $procmux$38839. + dead port 1/2 on $mux $procmux$3884. + dead port 1/2 on $mux $procmux$38842. + dead port 1/2 on $mux $procmux$38845. + dead port 1/2 on $mux $procmux$38848. + dead port 1/2 on $mux $procmux$38851. + dead port 1/2 on $mux $procmux$38854. + dead port 1/2 on $mux $procmux$38857. + dead port 2/2 on $mux $procmux$38859. + dead port 1/2 on $mux $procmux$38862. + dead port 1/2 on $mux $procmux$38865. + dead port 1/2 on $mux $procmux$38868. + dead port 1/2 on $mux $procmux$3887. + dead port 1/2 on $mux $procmux$38871. + dead port 1/2 on $mux $procmux$38874. + dead port 1/2 on $mux $procmux$38877. + dead port 1/2 on $mux $procmux$38880. + dead port 1/2 on $mux $procmux$38883. + dead port 1/2 on $mux $procmux$38886. + dead port 1/2 on $mux $procmux$38889. + dead port 1/2 on $mux $procmux$38892. + dead port 2/2 on $mux $procmux$38895. + dead port 1/2 on $mux $procmux$3890. + dead port 1/2 on $mux $procmux$38902. + dead port 1/2 on $mux $procmux$38905. + dead port 1/2 on $mux $procmux$38908. + dead port 1/2 on $mux $procmux$38911. + dead port 1/2 on $mux $procmux$38914. + dead port 1/2 on $mux $procmux$38917. + dead port 1/2 on $mux $procmux$38920. + dead port 1/2 on $mux $procmux$38923. + dead port 1/2 on $mux $procmux$38926. + dead port 1/2 on $mux $procmux$38929. + dead port 1/2 on $mux $procmux$3893. + dead port 1/2 on $mux $procmux$38932. + dead port 2/2 on $mux $procmux$38934. + dead port 1/2 on $mux $procmux$38937. + dead port 1/2 on $mux $procmux$38940. + dead port 1/2 on $mux $procmux$38943. + dead port 1/2 on $mux $procmux$38946. + dead port 1/2 on $mux $procmux$38949. + dead port 1/2 on $mux $procmux$38952. + dead port 1/2 on $mux $procmux$38955. + dead port 1/2 on $mux $procmux$38958. + dead port 1/2 on $mux $procmux$3896. + dead port 1/2 on $mux $procmux$38961. + dead port 1/2 on $mux $procmux$38964. + dead port 1/2 on $mux $procmux$38967. + dead port 2/2 on $mux $procmux$38970. + dead port 1/2 on $mux $procmux$38977. + dead port 1/2 on $mux $procmux$38980. + dead port 1/2 on $mux $procmux$38983. + dead port 1/2 on $mux $procmux$38986. + dead port 1/2 on $mux $procmux$38989. + dead port 1/2 on $mux $procmux$3899. + dead port 1/2 on $mux $procmux$38992. + dead port 1/2 on $mux $procmux$38995. + dead port 1/2 on $mux $procmux$38998. + dead port 1/2 on $mux $procmux$39001. + dead port 1/2 on $mux $procmux$39004. + dead port 1/2 on $mux $procmux$39007. + dead port 2/2 on $mux $procmux$39009. + dead port 1/2 on $mux $procmux$39012. + dead port 1/2 on $mux $procmux$39015. + dead port 1/2 on $mux $procmux$39018. + dead port 1/2 on $mux $procmux$3902. + dead port 1/2 on $mux $procmux$39021. + dead port 1/2 on $mux $procmux$39024. + dead port 1/2 on $mux $procmux$39027. + dead port 1/2 on $mux $procmux$39030. + dead port 1/2 on $mux $procmux$39033. + dead port 1/2 on $mux $procmux$39036. + dead port 1/2 on $mux $procmux$39039. + dead port 1/2 on $mux $procmux$39042. + dead port 2/2 on $mux $procmux$39045. + dead port 1/2 on $mux $procmux$3905. + dead port 1/2 on $mux $procmux$3908. + dead port 1/2 on $mux $procmux$3911. + dead port 1/2 on $mux $procmux$39127. + dead port 1/2 on $mux $procmux$39130. + dead port 1/2 on $mux $procmux$39133. + dead port 1/2 on $mux $procmux$39136. + dead port 1/2 on $mux $procmux$39139. + dead port 1/2 on $mux $procmux$3914. + dead port 1/2 on $mux $procmux$39142. + dead port 1/2 on $mux $procmux$39145. + dead port 1/2 on $mux $procmux$39148. + dead port 1/2 on $mux $procmux$39151. + dead port 1/2 on $mux $procmux$39154. + dead port 1/2 on $mux $procmux$39157. + dead port 2/2 on $mux $procmux$39159. + dead port 1/2 on $mux $procmux$39162. + dead port 1/2 on $mux $procmux$39165. + dead port 1/2 on $mux $procmux$39168. + dead port 1/2 on $mux $procmux$3917. + dead port 1/2 on $mux $procmux$39171. + dead port 1/2 on $mux $procmux$39174. + dead port 1/2 on $mux $procmux$39177. + dead port 1/2 on $mux $procmux$39180. + dead port 1/2 on $mux $procmux$39183. + dead port 1/2 on $mux $procmux$39186. + dead port 1/2 on $mux $procmux$39189. + dead port 1/2 on $mux $procmux$39192. + dead port 2/2 on $mux $procmux$39195. + dead port 1/2 on $mux $procmux$3920. + dead port 1/2 on $mux $procmux$39202. + dead port 1/2 on $mux $procmux$39205. + dead port 1/2 on $mux $procmux$39208. + dead port 1/2 on $mux $procmux$39211. + dead port 1/2 on $mux $procmux$39214. + dead port 1/2 on $mux $procmux$39217. + dead port 1/2 on $mux $procmux$39220. + dead port 1/2 on $mux $procmux$39223. + dead port 1/2 on $mux $procmux$39226. + dead port 1/2 on $mux $procmux$39229. + dead port 1/2 on $mux $procmux$3923. + dead port 1/2 on $mux $procmux$39232. + dead port 2/2 on $mux $procmux$39234. + dead port 1/2 on $mux $procmux$39237. + dead port 1/2 on $mux $procmux$39240. + dead port 1/2 on $mux $procmux$39243. + dead port 1/2 on $mux $procmux$39246. + dead port 1/2 on $mux $procmux$39249. + dead port 1/2 on $mux $procmux$39252. + dead port 1/2 on $mux $procmux$39255. + dead port 1/2 on $mux $procmux$39258. + dead port 1/2 on $mux $procmux$3926. + dead port 1/2 on $mux $procmux$39261. + dead port 1/2 on $mux $procmux$39264. + dead port 1/2 on $mux $procmux$39267. + dead port 2/2 on $mux $procmux$39270. + dead port 2/2 on $mux $procmux$3928. + dead port 1/2 on $mux $procmux$3931. + dead port 1/2 on $mux $procmux$3934. + dead port 1/2 on $mux $procmux$3937. + dead port 1/2 on $mux $procmux$3940. + dead port 1/2 on $mux $procmux$3943. + dead port 1/2 on $mux $procmux$3946. + dead port 1/2 on $mux $procmux$3949. + dead port 1/2 on $mux $procmux$3952. + dead port 1/2 on $mux $procmux$3955. + dead port 1/2 on $mux $procmux$3958. + dead port 1/2 on $mux $procmux$3961. + dead port 2/2 on $mux $procmux$3964. + dead port 1/2 on $mux $procmux$3971. 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$procmux$4048. + dead port 1/2 on $mux $procmux$4051. + dead port 1/2 on $mux $procmux$4054. + dead port 2/2 on $mux $procmux$4057. + dead port 1/2 on $mux $procmux$4064. + dead port 2/2 on $mux $procmux$4067. + dead port 1/2 on $mux $procmux$4070. + dead port 1/2 on $mux $procmux$4073. + dead port 1/2 on $mux $procmux$4076. + dead port 1/2 on $mux $procmux$4079. + dead port 1/2 on $mux $procmux$4082. + dead port 1/2 on $mux $procmux$4085. + dead port 1/2 on $mux $procmux$4088. + dead port 1/2 on $mux $procmux$4091. + dead port 1/2 on $mux $procmux$4094. + dead port 1/2 on $mux $procmux$4097. + dead port 1/2 on $mux $procmux$4100. + dead port 1/2 on $mux $procmux$4103. + dead port 1/2 on $mux $procmux$4106. + dead port 1/2 on $mux $procmux$4109. + dead port 1/2 on $mux $procmux$4112. + dead port 2/2 on $mux $procmux$4114. + dead port 1/2 on $mux $procmux$4117. + dead port 1/2 on $mux $procmux$4120. + dead port 1/2 on $mux $procmux$4123. + dead port 1/2 on $mux $procmux$4126. + dead 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$procmux$42976. + dead port 2/2 on $mux $procmux$42978. + dead port 1/2 on $mux $procmux$4298. + dead port 1/2 on $mux $procmux$42981. + dead port 1/2 on $mux $procmux$42984. + dead port 1/2 on $mux $procmux$42987. + dead port 1/2 on $mux $procmux$42990. + dead port 1/2 on $mux $procmux$42993. + dead port 1/2 on $mux $procmux$42996. + dead port 1/2 on $mux $procmux$42999. + dead port 2/2 on $mux $procmux$4300. + dead port 1/2 on $mux $procmux$43002. + dead port 1/2 on $mux $procmux$43005. + dead port 1/2 on $mux $procmux$43008. + dead port 1/2 on $mux $procmux$43011. + dead port 2/2 on $mux $procmux$43014. + dead port 1/2 on $mux $procmux$43021. + dead port 1/2 on $mux $procmux$43024. + dead port 1/2 on $mux $procmux$43027. + dead port 1/2 on $mux $procmux$4303. + dead port 1/2 on $mux $procmux$43030. + dead port 1/2 on $mux $procmux$43033. + dead port 1/2 on $mux $procmux$43036. + dead port 1/2 on $mux $procmux$43039. + dead port 1/2 on $mux $procmux$43042. + dead port 1/2 on $mux $procmux$43045. + dead port 1/2 on $mux $procmux$43048. + dead port 2/2 on $mux $procmux$43050. + dead port 1/2 on $mux $procmux$43053. + dead port 1/2 on $mux $procmux$43056. + dead port 1/2 on $mux $procmux$43059. + dead port 1/2 on $mux $procmux$4306. + dead port 1/2 on $mux $procmux$43062. + dead port 1/2 on $mux $procmux$43065. + dead port 1/2 on $mux $procmux$43068. + dead port 1/2 on $mux $procmux$43071. + dead port 1/2 on $mux $procmux$43074. + dead port 1/2 on $mux $procmux$43077. + dead port 1/2 on $mux $procmux$43080. + dead port 1/2 on $mux $procmux$43083. + dead port 2/2 on $mux $procmux$43086. + dead port 1/2 on $mux $procmux$4309. + dead port 1/2 on $mux $procmux$43093. + dead port 1/2 on $mux $procmux$43096. + dead port 1/2 on $mux $procmux$43099. + dead port 1/2 on $mux $procmux$43102. + dead port 1/2 on $mux $procmux$43105. + dead port 1/2 on $mux $procmux$43108. + dead port 1/2 on $mux $procmux$43111. + dead port 1/2 on $mux $procmux$43114. + dead port 1/2 on $mux $procmux$43117. + dead port 1/2 on $mux $procmux$4312. + dead port 1/2 on $mux $procmux$43120. + dead port 2/2 on $mux $procmux$43122. + dead port 1/2 on $mux $procmux$43125. + dead port 1/2 on $mux $procmux$43128. + dead port 1/2 on $mux $procmux$43131. + dead port 1/2 on $mux $procmux$43134. + dead port 1/2 on $mux $procmux$43137. + dead port 1/2 on $mux $procmux$43140. + dead port 1/2 on $mux $procmux$43143. + dead port 1/2 on $mux $procmux$43146. + dead port 1/2 on $mux $procmux$43149. + dead port 1/2 on $mux $procmux$4315. + dead port 1/2 on $mux $procmux$43152. + dead port 1/2 on $mux $procmux$43155. + dead port 2/2 on $mux $procmux$43158. + dead port 1/2 on $mux $procmux$4318. + dead port 1/2 on $mux $procmux$4321. + dead port 1/2 on $mux $procmux$4324. + dead port 1/2 on $mux $procmux$4327. + dead port 1/2 on $mux $procmux$4330. + dead port 1/2 on $mux $procmux$4333. + dead port 2/2 on $mux $procmux$4336. + dead port 1/2 on $mux $procmux$43381. + dead port 1/2 on $mux $procmux$43384. + dead port 1/2 on $mux $procmux$43387. + dead port 1/2 on $mux $procmux$43390. + dead port 1/2 on $mux $procmux$43393. + dead port 1/2 on $mux $procmux$43396. + dead port 1/2 on $mux $procmux$43399. + dead port 1/2 on $mux $procmux$43402. + dead port 1/2 on $mux $procmux$43405. + dead port 1/2 on $mux $procmux$43408. + dead port 2/2 on $mux $procmux$43410. + dead port 1/2 on $mux $procmux$43413. + dead port 1/2 on $mux $procmux$43416. + dead port 1/2 on $mux $procmux$43419. + dead port 1/2 on $mux $procmux$43422. + dead port 1/2 on $mux $procmux$43425. + dead port 1/2 on $mux $procmux$43428. + dead port 1/2 on $mux $procmux$4343. + dead port 1/2 on $mux $procmux$43431. + dead port 1/2 on $mux $procmux$43434. + dead port 1/2 on $mux $procmux$43437. + dead port 1/2 on $mux $procmux$43440. + dead port 1/2 on $mux $procmux$43443. + dead port 2/2 on $mux $procmux$43446. + dead port 1/2 on $mux $procmux$43453. + dead port 1/2 on $mux $procmux$43456. + dead port 1/2 on $mux $procmux$43459. + dead port 2/2 on $mux $procmux$4346. + dead port 1/2 on $mux $procmux$43462. + dead port 1/2 on $mux $procmux$43465. + dead port 1/2 on $mux $procmux$43468. + dead port 1/2 on $mux $procmux$43471. + dead port 1/2 on $mux $procmux$43474. + dead port 1/2 on $mux $procmux$43477. + dead port 1/2 on $mux $procmux$43480. + dead port 2/2 on $mux $procmux$43482. + dead port 1/2 on $mux $procmux$43485. + dead port 1/2 on $mux $procmux$43488. + dead port 1/2 on $mux $procmux$4349. + dead port 1/2 on $mux $procmux$43491. + dead port 1/2 on $mux $procmux$43494. + dead port 1/2 on $mux $procmux$43497. + dead port 1/2 on $mux $procmux$43500. + dead port 1/2 on $mux $procmux$43503. + dead port 1/2 on $mux $procmux$43506. + dead port 1/2 on $mux $procmux$43509. + dead port 1/2 on $mux $procmux$43512. + dead port 1/2 on $mux $procmux$43515. + dead port 2/2 on $mux $procmux$43518. + dead port 1/2 on $mux $procmux$4352. + dead port 1/2 on $mux $procmux$43525. + dead port 1/2 on $mux $procmux$43528. + dead port 1/2 on $mux $procmux$43531. + dead port 1/2 on $mux $procmux$43534. + dead port 1/2 on $mux $procmux$43537. + dead port 1/2 on $mux $procmux$43540. + dead port 1/2 on $mux $procmux$43543. + dead port 1/2 on $mux $procmux$43546. + dead port 1/2 on $mux $procmux$43549. + dead port 1/2 on $mux $procmux$4355. + dead port 1/2 on $mux $procmux$43552. + dead port 2/2 on $mux $procmux$43554. + dead port 1/2 on $mux $procmux$43557. + dead port 1/2 on $mux $procmux$43560. + dead port 1/2 on $mux $procmux$43563. + dead port 1/2 on $mux $procmux$43566. + dead port 1/2 on $mux $procmux$43569. + dead port 1/2 on $mux $procmux$43572. + dead port 1/2 on $mux $procmux$43575. + dead port 1/2 on $mux $procmux$43578. + dead port 1/2 on $mux $procmux$4358. + dead port 1/2 on $mux $procmux$43581. + dead port 1/2 on $mux $procmux$43584. + dead port 1/2 on $mux $procmux$43587. + dead port 2/2 on $mux $procmux$43590. + dead port 1/2 on $mux $procmux$4361. + dead port 1/2 on $mux $procmux$4364. + dead port 1/2 on $mux $procmux$43669. + dead port 1/2 on $mux $procmux$4367. + dead port 1/2 on $mux $procmux$43672. + dead port 1/2 on $mux $procmux$43675. + dead port 1/2 on $mux $procmux$43678. + dead port 1/2 on $mux $procmux$43681. + dead port 1/2 on $mux $procmux$43684. + dead port 1/2 on $mux $procmux$43687. + dead port 1/2 on $mux $procmux$43690. + dead port 1/2 on $mux $procmux$43693. + dead port 1/2 on $mux $procmux$43696. + dead port 2/2 on $mux $procmux$43698. + dead port 1/2 on $mux $procmux$4370. + dead port 1/2 on $mux $procmux$43701. + dead port 1/2 on $mux $procmux$43704. + dead port 1/2 on $mux $procmux$43707. + dead port 1/2 on $mux $procmux$43710. + dead port 1/2 on $mux $procmux$43713. + dead port 1/2 on $mux $procmux$43716. + dead port 1/2 on $mux $procmux$43719. + dead port 1/2 on $mux $procmux$43722. + dead port 1/2 on $mux $procmux$43725. + dead port 1/2 on $mux $procmux$43728. + dead port 1/2 on $mux $procmux$4373. + dead port 1/2 on $mux $procmux$43731. + dead port 2/2 on $mux $procmux$43734. + dead port 1/2 on $mux $procmux$43741. + dead port 1/2 on $mux $procmux$43744. + dead port 1/2 on $mux $procmux$43747. + dead port 1/2 on $mux $procmux$43750. + dead port 1/2 on $mux $procmux$43753. + dead port 1/2 on $mux $procmux$43756. + dead port 1/2 on $mux $procmux$43759. + dead port 1/2 on $mux $procmux$4376. + dead port 1/2 on $mux $procmux$43762. + dead port 1/2 on $mux $procmux$43765. + dead port 1/2 on $mux $procmux$43768. + dead port 2/2 on $mux $procmux$43770. + dead port 1/2 on $mux $procmux$43773. + dead port 1/2 on $mux $procmux$43776. + dead port 1/2 on $mux $procmux$43779. + dead port 1/2 on $mux $procmux$43782. + dead port 1/2 on $mux $procmux$43785. + dead port 1/2 on $mux $procmux$43788. + dead port 1/2 on $mux $procmux$4379. + dead port 1/2 on $mux $procmux$43791. + dead port 1/2 on $mux $procmux$43794. + dead port 1/2 on $mux $procmux$43797. + dead port 1/2 on $mux $procmux$43800. + dead port 1/2 on $mux $procmux$43803. + dead port 2/2 on $mux $procmux$43806. + dead port 1/2 on $mux $procmux$4382. + dead port 1/2 on $mux $procmux$4385. + dead port 1/2 on $mux $procmux$4388. + dead port 1/2 on $mux $procmux$4391. + dead port 2/2 on $mux $procmux$4393. + dead port 1/2 on $mux $procmux$4396. + dead port 1/2 on $mux $procmux$4399. + dead port 1/2 on $mux $procmux$4402. + dead port 1/2 on $mux $procmux$4405. + dead port 1/2 on $mux $procmux$4408. + dead port 1/2 on $mux $procmux$4411. + dead port 1/2 on $mux $procmux$4414. + dead port 1/2 on $mux $procmux$4417. + dead port 1/2 on $mux $procmux$4420. + dead port 1/2 on $mux $procmux$4423. + dead port 1/2 on $mux $procmux$4426. + dead port 2/2 on $mux $procmux$4429. + dead port 2/2 on $mux $procmux$4436. + dead port 1/2 on $mux $procmux$4439. + dead port 1/2 on $mux $procmux$4442. + dead port 1/2 on $mux $procmux$4445. + dead port 1/2 on $mux $procmux$4448. + dead port 1/2 on $mux $procmux$4451. + dead port 1/2 on $mux $procmux$4454. + dead port 1/2 on $mux $procmux$4457. + dead port 1/2 on $mux $procmux$4460. + dead port 1/2 on $mux $procmux$4463. + dead port 1/2 on $mux $procmux$4466. + dead port 1/2 on $mux $procmux$4469. + dead port 1/2 on $mux $procmux$4472. + dead port 1/2 on $mux $procmux$4475. + dead port 1/2 on $mux $procmux$4478. + dead port 1/2 on $mux $procmux$4481. + dead port 2/2 on $mux $procmux$4483. + dead port 1/2 on $mux $procmux$4486. + dead port 1/2 on $mux $procmux$4489. + dead port 1/2 on $mux $procmux$4492. + dead port 1/2 on $mux $procmux$4495. + dead port 1/2 on $mux $procmux$4498. + dead port 1/2 on $mux $procmux$4501. + dead port 1/2 on $mux $procmux$4504. + dead port 1/2 on $mux $procmux$4507. + dead port 1/2 on $mux $procmux$4510. + dead port 1/2 on $mux $procmux$4513. + dead port 1/2 on $mux $procmux$4516. + dead port 2/2 on $mux $procmux$4519. + dead port 2/2 on $mux $procmux$4526. + dead port 2/2 on $mux $procmux$4529. + dead port 1/2 on $mux $procmux$4532. + dead port 1/2 on $mux $procmux$4535. + dead port 1/2 on $mux $procmux$4538. + dead port 1/2 on $mux $procmux$4541. + dead port 1/2 on $mux $procmux$4544. + dead port 1/2 on $mux $procmux$4547. + dead port 1/2 on $mux $procmux$4550. + dead port 1/2 on $mux $procmux$4553. + dead port 1/2 on $mux $procmux$4556. + dead port 1/2 on $mux $procmux$4559. + dead port 1/2 on $mux $procmux$4562. + dead port 1/2 on $mux $procmux$4565. + dead port 1/2 on $mux $procmux$4568. + dead port 1/2 on $mux $procmux$4571. + dead port 1/2 on $mux $procmux$4574. + dead port 2/2 on $mux $procmux$4576. + dead port 1/2 on $mux $procmux$4579. + dead port 1/2 on $mux $procmux$4582. + dead port 1/2 on $mux $procmux$4585. + dead port 1/2 on $mux $procmux$4588. + dead port 1/2 on $mux $procmux$4591. + dead port 1/2 on $mux $procmux$4594. + dead port 1/2 on $mux $procmux$4597. + dead port 1/2 on $mux $procmux$4600. + dead port 1/2 on $mux $procmux$4603. + dead port 1/2 on $mux $procmux$4606. + dead port 1/2 on $mux $procmux$4609. + dead port 2/2 on $mux $procmux$4612. + dead port 2/2 on $mux $procmux$4619. + dead port 2/2 on $mux $procmux$4622. + dead port 1/2 on $mux $procmux$4625. + dead port 1/2 on $mux $procmux$4628. + dead port 1/2 on $mux $procmux$4631. + dead port 1/2 on $mux $procmux$4634. + dead port 1/2 on $mux $procmux$4637. + dead port 1/2 on $mux $procmux$4640. + dead port 1/2 on $mux $procmux$4643. + dead port 1/2 on $mux $procmux$4646. + dead port 1/2 on $mux $procmux$4649. + dead port 1/2 on $mux $procmux$4652. + dead port 1/2 on $mux $procmux$4655. + dead port 1/2 on $mux $procmux$4658. + dead port 1/2 on $mux $procmux$4661. + dead port 1/2 on $mux $procmux$4664. + dead port 1/2 on $mux $procmux$46642. + dead port 1/2 on $mux $procmux$46645. + dead port 1/2 on $mux $procmux$46648. + dead port 1/2 on $mux $procmux$46651. + dead port 1/2 on $mux $procmux$46654. + dead port 1/2 on $mux $procmux$46657. + dead port 1/2 on $mux $procmux$46660. + dead port 1/2 on $mux $procmux$46663. + dead port 1/2 on $mux $procmux$46666. + dead port 2/2 on $mux $procmux$46668. + dead port 1/2 on $mux $procmux$4667. + dead port 1/2 on $mux $procmux$46671. + dead port 1/2 on $mux $procmux$46674. + dead port 1/2 on $mux $procmux$46677. + dead port 1/2 on $mux $procmux$46680. + dead port 1/2 on $mux $procmux$46683. + dead port 1/2 on $mux $procmux$46686. + dead port 1/2 on $mux $procmux$46689. + dead port 2/2 on $mux $procmux$4669. + dead port 1/2 on $mux $procmux$46692. + dead port 1/2 on $mux $procmux$46695. + dead port 1/2 on $mux $procmux$46698. + dead port 1/2 on $mux $procmux$46701. + dead port 2/2 on $mux $procmux$46704. + dead port 1/2 on $mux $procmux$46711. + dead port 1/2 on $mux $procmux$46714. + dead port 1/2 on $mux $procmux$46717. + dead port 1/2 on $mux $procmux$4672. + dead port 1/2 on $mux $procmux$46720. + dead port 1/2 on $mux $procmux$46723. + dead port 1/2 on $mux $procmux$46726. + dead port 1/2 on $mux $procmux$46729. + dead port 1/2 on $mux $procmux$46732. + dead port 1/2 on $mux $procmux$46735. + dead port 2/2 on $mux $procmux$46737. + dead port 1/2 on $mux $procmux$46740. + dead port 1/2 on $mux $procmux$46743. + dead port 1/2 on $mux $procmux$46746. + dead port 1/2 on $mux $procmux$46749. + dead port 1/2 on $mux $procmux$4675. + dead port 1/2 on $mux $procmux$46752. + dead port 1/2 on $mux $procmux$46755. + dead port 1/2 on $mux $procmux$46758. + dead port 1/2 on $mux $procmux$46761. + dead port 1/2 on $mux $procmux$46764. + dead port 1/2 on $mux $procmux$46767. + dead port 1/2 on $mux $procmux$46770. + dead port 2/2 on $mux $procmux$46773. + dead port 1/2 on $mux $procmux$4678. + dead port 1/2 on $mux $procmux$4681. + dead port 1/2 on $mux $procmux$4684. + dead port 1/2 on $mux $procmux$46849. + dead port 1/2 on $mux $procmux$46852. + dead port 1/2 on $mux $procmux$46855. + dead port 1/2 on $mux $procmux$46858. + dead port 1/2 on $mux $procmux$46861. + dead port 1/2 on $mux $procmux$46864. + dead port 1/2 on $mux $procmux$46867. + dead port 1/2 on $mux $procmux$4687. + dead port 1/2 on $mux $procmux$46870. + dead port 1/2 on $mux $procmux$46873. + dead port 2/2 on $mux $procmux$46875. + dead port 1/2 on $mux $procmux$46878. + dead port 1/2 on $mux $procmux$46881. + dead port 1/2 on $mux $procmux$46884. + dead port 1/2 on $mux $procmux$46887. + dead port 1/2 on $mux $procmux$46890. + dead port 1/2 on $mux $procmux$46893. + dead port 1/2 on $mux $procmux$46896. + dead port 1/2 on $mux $procmux$46899. + dead port 1/2 on $mux $procmux$4690. + dead port 1/2 on $mux $procmux$46902. + dead port 1/2 on $mux $procmux$46905. + dead port 1/2 on $mux $procmux$46908. + dead port 2/2 on $mux $procmux$46911. + dead port 1/2 on $mux $procmux$46918. + dead port 1/2 on $mux $procmux$46921. + dead port 1/2 on $mux $procmux$46924. + dead port 1/2 on $mux $procmux$46927. + dead port 1/2 on $mux $procmux$4693. + dead port 1/2 on $mux $procmux$46930. + dead port 1/2 on $mux $procmux$46933. + dead port 1/2 on $mux $procmux$46936. + dead port 1/2 on $mux $procmux$46939. + dead port 1/2 on $mux $procmux$46942. + dead port 2/2 on $mux $procmux$46944. + dead port 1/2 on $mux $procmux$46947. + dead port 1/2 on $mux $procmux$46950. + dead port 1/2 on $mux $procmux$46953. + dead port 1/2 on $mux $procmux$46956. + dead port 1/2 on $mux $procmux$46959. + dead port 1/2 on $mux $procmux$4696. + dead port 1/2 on $mux $procmux$46962. + dead port 1/2 on $mux $procmux$46965. + dead port 1/2 on $mux $procmux$46968. + dead port 1/2 on $mux $procmux$46971. + dead port 1/2 on $mux $procmux$46974. + dead port 1/2 on $mux $procmux$46977. + dead port 2/2 on $mux $procmux$46980. + dead port 1/2 on $mux $procmux$46987. + dead port 1/2 on $mux $procmux$4699. + dead port 1/2 on $mux $procmux$46990. + dead port 1/2 on $mux $procmux$46993. + dead port 1/2 on $mux $procmux$46996. + dead port 1/2 on $mux $procmux$46999. + dead port 1/2 on $mux $procmux$47002. + dead port 1/2 on $mux $procmux$47005. + dead port 1/2 on $mux $procmux$47008. + dead port 1/2 on $mux $procmux$47011. + dead port 2/2 on $mux $procmux$47013. + dead port 1/2 on $mux $procmux$47016. + dead port 1/2 on $mux $procmux$47019. + dead port 1/2 on $mux $procmux$4702. + dead port 1/2 on $mux $procmux$47022. + dead port 1/2 on $mux $procmux$47025. + dead port 1/2 on $mux $procmux$47028. + dead port 1/2 on $mux $procmux$47031. + dead port 1/2 on $mux $procmux$47034. + dead port 1/2 on $mux $procmux$47037. + dead port 1/2 on $mux $procmux$47040. + dead port 1/2 on $mux $procmux$47043. + dead port 1/2 on $mux $procmux$47046. + dead port 2/2 on $mux $procmux$47049. + dead port 2/2 on $mux $procmux$4705. + dead port 1/2 on $mux $procmux$47056. + dead port 1/2 on $mux $procmux$47059. + dead port 1/2 on $mux $procmux$47062. + dead port 1/2 on $mux $procmux$47065. + dead port 1/2 on $mux $procmux$47068. + dead port 1/2 on $mux $procmux$47071. + dead port 1/2 on $mux $procmux$47074. + dead port 1/2 on $mux $procmux$47077. + dead port 1/2 on $mux $procmux$47080. + dead port 2/2 on $mux $procmux$47082. + dead port 1/2 on $mux $procmux$47085. + dead port 1/2 on $mux $procmux$47088. + dead port 1/2 on $mux $procmux$47091. + dead port 1/2 on $mux $procmux$47094. + dead port 1/2 on $mux $procmux$47097. + dead port 1/2 on $mux $procmux$47100. + dead port 1/2 on $mux $procmux$47103. + dead port 1/2 on $mux $procmux$47106. + dead port 1/2 on $mux $procmux$47109. + dead port 1/2 on $mux $procmux$47112. + dead port 1/2 on $mux $procmux$47115. + dead port 2/2 on $mux $procmux$47118. + dead port 2/2 on $mux $procmux$4712. + dead port 1/2 on $mux $procmux$47125. + dead port 1/2 on $mux $procmux$47128. + dead port 1/2 on $mux $procmux$47131. + dead port 1/2 on $mux $procmux$47134. + dead port 1/2 on $mux $procmux$47137. + dead port 1/2 on $mux $procmux$47140. + dead port 1/2 on $mux $procmux$47143. + dead port 1/2 on $mux $procmux$47146. + dead port 1/2 on $mux $procmux$47149. + dead port 1/2 on $mux $procmux$4715. + dead port 2/2 on $mux $procmux$47151. + dead port 1/2 on $mux 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$procmux$47634. + dead port 1/2 on $mux $procmux$47637. + dead port 1/2 on $mux $procmux$47640. + dead port 1/2 on $mux $procmux$47643. + dead port 1/2 on $mux $procmux$47646. + dead port 1/2 on $mux $procmux$47649. + dead port 1/2 on $mux $procmux$4765. + dead port 1/2 on $mux $procmux$47652. + dead port 1/2 on $mux $procmux$47655. + dead port 1/2 on $mux $procmux$47658. + dead port 1/2 on $mux $procmux$47661. + dead port 1/2 on $mux $procmux$47664. + dead port 1/2 on $mux $procmux$47667. + dead port 2/2 on $mux $procmux$47670. + dead port 1/2 on $mux $procmux$47677. + dead port 1/2 on $mux $procmux$4768. + dead port 1/2 on $mux $procmux$47680. + dead port 1/2 on $mux $procmux$47683. + dead port 1/2 on $mux $procmux$47686. + dead port 1/2 on $mux $procmux$47689. + dead port 1/2 on $mux $procmux$47692. + dead port 1/2 on $mux $procmux$47695. + dead port 1/2 on $mux $procmux$47698. + dead port 1/2 on $mux $procmux$47701. + dead port 2/2 on $mux $procmux$47703. + dead port 1/2 on $mux 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$procmux$47775. + dead port 1/2 on $mux $procmux$47778. + dead port 1/2 on $mux $procmux$47781. + dead port 1/2 on $mux $procmux$47784. + dead port 1/2 on $mux $procmux$47787. + dead port 1/2 on $mux $procmux$47790. + dead port 1/2 on $mux $procmux$47793. + dead port 1/2 on $mux $procmux$47796. + dead port 1/2 on $mux $procmux$47799. + dead port 1/2 on $mux $procmux$4780. + dead port 1/2 on $mux $procmux$47802. + dead port 1/2 on $mux $procmux$47805. + dead port 2/2 on $mux $procmux$47808. + dead port 1/2 on $mux $procmux$47815. + dead port 1/2 on $mux $procmux$47818. + dead port 1/2 on $mux $procmux$47821. + dead port 1/2 on $mux $procmux$47824. + dead port 1/2 on $mux $procmux$47827. + dead port 1/2 on $mux $procmux$4783. + dead port 1/2 on $mux $procmux$47830. + dead port 1/2 on $mux $procmux$47833. + dead port 1/2 on $mux $procmux$47836. + dead port 1/2 on $mux $procmux$47839. + dead port 2/2 on $mux $procmux$47841. + dead port 1/2 on $mux $procmux$47844. + dead port 1/2 on $mux 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$procmux$81849. + dead port 1/2 on $mux $procmux$8185. + dead port 1/2 on $mux $procmux$81852. + dead port 2/2 on $mux $procmux$81855. + dead port 1/2 on $mux $procmux$81862. + dead port 1/2 on $mux $procmux$81865. + dead port 1/2 on $mux $procmux$81868. + dead port 2/2 on $mux $procmux$81870. + dead port 1/2 on $mux $procmux$81873. + dead port 1/2 on $mux $procmux$81876. + dead port 1/2 on $mux $procmux$81879. + dead port 1/2 on $mux $procmux$8188. + dead port 1/2 on $mux $procmux$81882. + dead port 1/2 on $mux $procmux$81885. + dead port 1/2 on $mux $procmux$81888. + dead port 1/2 on $mux $procmux$81891. + dead port 1/2 on $mux $procmux$81894. + dead port 1/2 on $mux $procmux$81897. + dead port 1/2 on $mux $procmux$81900. + dead port 1/2 on $mux $procmux$81903. + dead port 2/2 on $mux $procmux$81906. + dead port 1/2 on $mux $procmux$8191. + dead port 1/2 on $mux $procmux$81913. + dead port 1/2 on $mux $procmux$81916. + dead port 1/2 on $mux $procmux$81919. + dead port 2/2 on $mux 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$procmux$8604. + dead port 1/2 on $mux $procmux$8607. + dead port 1/2 on $mux $procmux$8610. + dead port 1/2 on $mux $procmux$8613. + dead port 1/2 on $mux $procmux$8616. + dead port 1/2 on $mux $procmux$8619. + dead port 1/2 on $mux $procmux$8622. + dead port 1/2 on $mux $procmux$8625. + dead port 2/2 on $mux $procmux$8628. + dead port 1/2 on $mux $procmux$8636. + dead port 1/2 on $mux $procmux$8639. + dead port 2/2 on $mux $procmux$8641. + dead port 1/2 on $mux $procmux$8644. + dead port 1/2 on $mux $procmux$8647. + dead port 1/2 on $mux $procmux$8650. + dead port 1/2 on $mux $procmux$8653. + dead port 1/2 on $mux $procmux$8656. + dead port 1/2 on $mux $procmux$8659. + dead port 1/2 on $mux $procmux$8662. + dead port 1/2 on $mux $procmux$8665. + dead port 1/2 on $mux $procmux$8668. + dead port 1/2 on $mux $procmux$8671. + dead port 1/2 on $mux $procmux$8674. + dead port 1/2 on $mux $procmux$8677. + dead port 1/2 on $mux $procmux$8680. + dead port 1/2 on $mux $procmux$8683. + dead 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$procmux$89670. + dead port 1/2 on $mux $procmux$89673. + dead port 1/2 on $mux $procmux$89676. + dead port 1/2 on $mux $procmux$89679. + dead port 1/2 on $mux $procmux$8968. + dead port 1/2 on $mux $procmux$89682. + dead port 1/2 on $mux $procmux$89685. + dead port 1/2 on $mux $procmux$89688. + dead port 1/2 on $mux $procmux$89691. + dead port 1/2 on $mux $procmux$89694. + dead port 2/2 on $mux $procmux$89697. + dead port 1/2 on $mux $procmux$89704. + dead port 1/2 on $mux $procmux$89707. + dead port 2/2 on $mux $procmux$89709. + dead port 1/2 on $mux $procmux$8971. + dead port 1/2 on $mux $procmux$89712. + dead port 1/2 on $mux $procmux$89715. + dead port 1/2 on $mux $procmux$89718. + dead port 1/2 on $mux $procmux$89721. + dead port 1/2 on $mux $procmux$89724. + dead port 1/2 on $mux $procmux$89727. + dead port 1/2 on $mux $procmux$89730. + dead port 1/2 on $mux $procmux$89733. + dead port 1/2 on $mux $procmux$89736. + dead port 1/2 on $mux $procmux$89739. + dead port 1/2 on $mux $procmux$8974. + dead port 1/2 on $mux $procmux$89742. + dead port 2/2 on $mux $procmux$89745. + dead port 1/2 on $mux $procmux$89752. + dead port 1/2 on $mux $procmux$89755. + dead port 2/2 on $mux $procmux$89757. + dead port 1/2 on $mux $procmux$89760. + dead port 1/2 on $mux $procmux$89763. + dead port 1/2 on $mux $procmux$89766. + dead port 1/2 on $mux $procmux$89769. + dead port 1/2 on $mux $procmux$8977. + dead port 1/2 on $mux $procmux$89772. + dead port 1/2 on $mux $procmux$89775. + dead port 1/2 on $mux $procmux$89778. + dead port 1/2 on $mux $procmux$89781. + dead port 1/2 on $mux $procmux$89784. + dead port 1/2 on $mux $procmux$89787. + dead port 1/2 on $mux $procmux$89790. + dead port 2/2 on $mux $procmux$89793. + dead port 1/2 on $mux $procmux$8980. + dead port 1/2 on $mux $procmux$8983. + dead port 1/2 on $mux $procmux$89848. + dead port 1/2 on $mux $procmux$89851. + dead port 2/2 on $mux $procmux$89853. + dead port 1/2 on $mux $procmux$89856. + dead port 1/2 on $mux $procmux$89859. + dead port 1/2 on $mux $procmux$8986. + dead port 1/2 on $mux $procmux$89862. + dead port 1/2 on $mux $procmux$89865. + dead port 1/2 on $mux $procmux$89868. + dead port 1/2 on $mux $procmux$89871. + dead port 1/2 on $mux $procmux$89874. + dead port 1/2 on $mux $procmux$89877. + dead port 1/2 on $mux $procmux$89880. + dead port 1/2 on $mux $procmux$89883. + dead port 1/2 on $mux $procmux$89886. + dead port 2/2 on $mux $procmux$89889. + dead port 1/2 on $mux $procmux$8989. + dead port 1/2 on $mux $procmux$89896. + dead port 1/2 on $mux $procmux$89899. + dead port 2/2 on $mux $procmux$89901. + dead port 1/2 on $mux $procmux$89904. + dead port 1/2 on $mux $procmux$89907. + dead port 1/2 on $mux $procmux$89910. + dead port 1/2 on $mux $procmux$89913. + dead port 1/2 on $mux $procmux$89916. + dead port 1/2 on $mux $procmux$89919. + dead port 1/2 on $mux $procmux$8992. + dead port 1/2 on $mux $procmux$89922. + dead port 1/2 on $mux $procmux$89925. + dead port 1/2 on $mux $procmux$89928. + dead port 1/2 on $mux $procmux$89931. + dead port 1/2 on $mux $procmux$89934. + dead port 2/2 on $mux $procmux$89937. + dead port 2/2 on $mux $procmux$8994. + dead port 1/2 on $mux $procmux$8997. + dead port 1/2 on $mux $procmux$9000. + dead port 1/2 on $mux $procmux$9003. + dead port 1/2 on $mux $procmux$9006. + dead port 1/2 on $mux $procmux$9009. + dead port 1/2 on $mux $procmux$9012. + dead port 1/2 on $mux $procmux$9015. + dead port 1/2 on $mux $procmux$9018. + dead port 1/2 on $mux $procmux$9021. + dead port 1/2 on $mux $procmux$9024. + dead port 1/2 on $mux $procmux$9027. + dead port 2/2 on $mux $procmux$9030. + dead port 1/2 on $mux $procmux$9038. + dead port 2/2 on $mux $procmux$9040. + dead port 1/2 on $mux $procmux$9043. + dead port 1/2 on $mux $procmux$9046. + dead port 1/2 on $mux $procmux$9049. + dead port 1/2 on $mux $procmux$9052. + dead port 1/2 on $mux $procmux$9055. + dead port 1/2 on $mux $procmux$9058. + dead port 1/2 on $mux $procmux$9061. + dead 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$procmux$9142. + dead port 1/2 on $mux $procmux$9145. + dead port 1/2 on $mux $procmux$9148. + dead port 1/2 on $mux $procmux$9151. + dead port 1/2 on $mux $procmux$9154. + dead port 1/2 on $mux $procmux$9157. + dead port 1/2 on $mux $procmux$9160. + dead port 1/2 on $mux $procmux$9163. + dead port 1/2 on $mux $procmux$9166. + dead port 1/2 on $mux $procmux$9169. + dead port 1/2 on $mux $procmux$9172. + dead port 1/2 on $mux $procmux$9175. + dead port 1/2 on $mux $procmux$9178. + dead port 1/2 on $mux $procmux$9181. + dead port 1/2 on $mux $procmux$9184. + dead port 1/2 on $mux $procmux$9187. + dead port 1/2 on $mux $procmux$9190. + dead port 2/2 on $mux $procmux$9192. + dead port 1/2 on $mux $procmux$9195. + dead port 1/2 on $mux $procmux$9198. + dead port 1/2 on $mux $procmux$9201. + dead port 1/2 on $mux $procmux$9204. + dead port 1/2 on $mux $procmux$9207. + dead port 1/2 on $mux $procmux$9210. + dead port 1/2 on $mux $procmux$9213. + dead port 1/2 on $mux $procmux$9216. + dead port 1/2 on $mux $procmux$9219. + dead port 1/2 on $mux $procmux$9222. + dead port 1/2 on $mux $procmux$9225. + dead port 2/2 on $mux $procmux$9228. + dead port 1/2 on $mux $procmux$9236. + dead port 2/2 on $mux $procmux$9238. + dead port 1/2 on $mux $procmux$9241. + dead port 1/2 on $mux $procmux$9244. + dead port 1/2 on $mux $procmux$9247. + dead port 1/2 on $mux $procmux$9250. + dead port 1/2 on $mux $procmux$9253. + dead port 1/2 on $mux $procmux$9256. + dead port 1/2 on $mux $procmux$9259. + dead port 1/2 on $mux $procmux$9262. + dead port 1/2 on $mux $procmux$9265. + dead port 1/2 on $mux $procmux$9268. + dead port 1/2 on $mux $procmux$9271. + dead port 1/2 on $mux $procmux$9274. + dead port 1/2 on $mux $procmux$9277. + dead port 1/2 on $mux $procmux$9280. + dead port 1/2 on $mux $procmux$9283. + dead port 1/2 on $mux $procmux$9286. + dead port 1/2 on $mux $procmux$9289. + dead port 2/2 on $mux $procmux$9291. + dead port 1/2 on $mux $procmux$9294. + dead port 1/2 on $mux $procmux$9297. + dead port 1/2 on $mux $procmux$9300. + dead port 1/2 on $mux $procmux$9303. + dead port 1/2 on $mux $procmux$9306. + dead port 1/2 on $mux $procmux$9309. + dead port 1/2 on $mux $procmux$9312. + dead port 1/2 on $mux $procmux$9315. + dead port 1/2 on $mux $procmux$9318. + dead port 1/2 on $mux $procmux$9321. + dead port 1/2 on $mux $procmux$9324. + dead port 2/2 on $mux $procmux$9327. + dead port 2/2 on $mux $procmux$9334. + dead port 1/2 on $mux $procmux$9337. + dead port 1/2 on $mux $procmux$9340. + dead port 1/2 on $mux $procmux$9343. + dead port 1/2 on $mux $procmux$9346. + dead port 1/2 on $mux $procmux$9349. + dead port 1/2 on $mux $procmux$9352. + dead port 1/2 on $mux $procmux$9355. + dead port 1/2 on $mux $procmux$9358. + dead port 1/2 on $mux $procmux$9361. + dead port 1/2 on $mux $procmux$9364. + dead port 1/2 on $mux $procmux$9367. + dead port 1/2 on $mux $procmux$93670. + dead port 2/2 on $mux $procmux$93672. + dead port 1/2 on $mux $procmux$93675. + dead port 1/2 on $mux $procmux$93678. + dead port 1/2 on $mux $procmux$93681. + dead port 1/2 on $mux $procmux$93684. + dead port 1/2 on $mux $procmux$93687. + dead port 1/2 on $mux $procmux$93690. + dead port 1/2 on $mux $procmux$93693. + dead port 1/2 on $mux $procmux$93696. + dead port 1/2 on $mux $procmux$93699. + dead port 1/2 on $mux $procmux$9370. + dead port 1/2 on $mux $procmux$93702. + dead port 1/2 on $mux $procmux$93705. + dead port 2/2 on $mux $procmux$93708. + dead port 1/2 on $mux $procmux$93715. + dead port 2/2 on $mux $procmux$93717. + dead port 1/2 on $mux $procmux$93720. + dead port 1/2 on $mux $procmux$93723. + dead port 1/2 on $mux $procmux$93726. + dead port 1/2 on $mux $procmux$93729. + dead port 1/2 on $mux $procmux$9373. + dead port 1/2 on $mux $procmux$93732. + dead port 1/2 on $mux $procmux$93735. + dead port 1/2 on $mux $procmux$93738. + dead port 1/2 on $mux $procmux$93741. + dead port 1/2 on $mux $procmux$93744. + dead port 1/2 on $mux $procmux$93747. + dead port 1/2 on $mux $procmux$93750. + dead port 2/2 on $mux $procmux$93753. + dead port 1/2 on $mux $procmux$9376. + dead port 1/2 on $mux $procmux$9379. + dead port 1/2 on $mux $procmux$93805. + dead port 2/2 on $mux $procmux$93807. + dead port 1/2 on $mux $procmux$93810. + dead port 1/2 on $mux $procmux$93813. + dead port 1/2 on $mux $procmux$93816. + dead port 1/2 on $mux $procmux$93819. + dead port 1/2 on $mux $procmux$9382. + dead port 1/2 on $mux $procmux$93822. + dead port 1/2 on $mux $procmux$93825. + dead port 1/2 on $mux $procmux$93828. + dead port 1/2 on $mux $procmux$93831. + dead port 1/2 on $mux $procmux$93834. + dead port 1/2 on $mux $procmux$93837. + dead port 1/2 on $mux $procmux$93840. + dead port 2/2 on $mux $procmux$93843. + dead port 1/2 on $mux $procmux$9385. + dead port 1/2 on $mux $procmux$93850. + dead port 2/2 on $mux $procmux$93852. + dead port 1/2 on $mux $procmux$93855. + dead port 1/2 on $mux $procmux$93858. + dead port 1/2 on $mux $procmux$93861. + dead port 1/2 on $mux $procmux$93864. + dead port 1/2 on $mux $procmux$93867. + dead port 2/2 on $mux $procmux$9387. + dead port 1/2 on $mux $procmux$93870. + dead port 1/2 on $mux $procmux$93873. + dead port 1/2 on $mux $procmux$93876. + dead port 1/2 on $mux $procmux$93879. + dead port 1/2 on $mux $procmux$93882. + dead port 1/2 on $mux $procmux$93885. + dead port 2/2 on $mux $procmux$93888. + dead port 1/2 on $mux $procmux$93895. + dead port 2/2 on $mux $procmux$93897. + dead port 1/2 on $mux $procmux$9390. + dead port 1/2 on $mux $procmux$93900. + dead port 1/2 on $mux $procmux$93903. + dead port 1/2 on $mux $procmux$93906. + dead port 1/2 on $mux $procmux$93909. + dead port 1/2 on $mux $procmux$93912. + dead port 1/2 on $mux $procmux$93915. + dead port 1/2 on $mux $procmux$93918. + dead port 1/2 on $mux $procmux$93921. + dead port 1/2 on $mux $procmux$93924. + dead port 1/2 on $mux $procmux$93927. + dead port 1/2 on $mux $procmux$9393. + dead port 1/2 on $mux $procmux$93930. + dead port 2/2 on $mux $procmux$93933. + dead port 1/2 on $mux $procmux$93940. + dead port 2/2 on $mux $procmux$93942. + dead port 1/2 on $mux $procmux$93945. + dead port 1/2 on $mux $procmux$93948. + dead port 1/2 on $mux $procmux$93951. + dead port 1/2 on $mux $procmux$93954. + dead port 1/2 on $mux $procmux$93957. + dead port 1/2 on $mux $procmux$9396. + dead port 1/2 on $mux $procmux$93960. + dead port 1/2 on $mux $procmux$93963. + dead port 1/2 on $mux $procmux$93966. + dead port 1/2 on $mux $procmux$93969. + dead port 1/2 on $mux $procmux$93972. + dead port 1/2 on $mux $procmux$93975. + dead port 2/2 on $mux $procmux$93978. + dead port 1/2 on $mux $procmux$93985. + dead port 2/2 on $mux $procmux$93987. + dead port 1/2 on $mux $procmux$9399. + dead port 1/2 on $mux $procmux$93990. + dead port 1/2 on $mux $procmux$93993. + dead port 1/2 on $mux $procmux$93996. + dead port 1/2 on $mux $procmux$93999. + dead port 1/2 on $mux $procmux$94002. + dead port 1/2 on $mux $procmux$94005. + dead port 1/2 on $mux $procmux$94008. + dead port 1/2 on $mux $procmux$94011. + dead port 1/2 on $mux $procmux$94014. + dead port 1/2 on $mux $procmux$94017. + dead port 1/2 on $mux $procmux$9402. + dead port 1/2 on $mux $procmux$94020. + dead port 2/2 on $mux $procmux$94023. + dead port 1/2 on $mux $procmux$94030. + dead port 2/2 on $mux $procmux$94032. + dead port 1/2 on $mux $procmux$94035. + dead port 1/2 on $mux $procmux$94038. + dead port 1/2 on $mux $procmux$94041. + dead port 1/2 on $mux $procmux$94044. + dead port 1/2 on $mux $procmux$94047. + dead port 1/2 on $mux $procmux$9405. + dead port 1/2 on $mux $procmux$94050. + dead port 1/2 on $mux $procmux$94053. + dead port 1/2 on $mux $procmux$94056. + dead port 1/2 on $mux $procmux$94059. + dead port 1/2 on $mux $procmux$94062. + dead port 1/2 on $mux $procmux$94065. + dead port 2/2 on $mux $procmux$94068. + dead port 1/2 on $mux $procmux$94075. + dead port 2/2 on $mux $procmux$94077. + dead port 1/2 on $mux $procmux$9408. + dead port 1/2 on $mux $procmux$94080. + dead port 1/2 on $mux $procmux$94083. + dead port 1/2 on $mux $procmux$94086. + dead port 1/2 on $mux $procmux$94089. + dead port 1/2 on $mux $procmux$94092. + dead port 1/2 on $mux $procmux$94095. + dead port 1/2 on $mux $procmux$94098. + dead port 1/2 on $mux $procmux$94101. + dead port 1/2 on $mux $procmux$94104. + dead port 1/2 on $mux $procmux$94107. + dead port 1/2 on $mux $procmux$9411. + dead port 1/2 on $mux $procmux$94110. + dead port 2/2 on $mux $procmux$94113. + dead port 1/2 on $mux $procmux$9414. + dead port 1/2 on $mux $procmux$9417. + dead port 1/2 on $mux $procmux$9420. + dead port 1/2 on $mux $procmux$94210. + dead port 2/2 on $mux $procmux$94212. + dead port 1/2 on $mux $procmux$94215. + dead port 1/2 on $mux $procmux$94218. + dead port 1/2 on $mux $procmux$94221. + dead port 1/2 on $mux $procmux$94224. + dead port 1/2 on $mux $procmux$94227. + dead port 2/2 on $mux $procmux$9423. + dead port 1/2 on $mux $procmux$94230. + dead port 1/2 on $mux $procmux$94233. + dead port 1/2 on $mux $procmux$94236. + dead port 1/2 on $mux $procmux$94239. + dead port 1/2 on $mux $procmux$94242. + dead port 1/2 on $mux $procmux$94245. + dead port 2/2 on $mux $procmux$94248. + dead port 1/2 on $mux $procmux$94255. + dead port 2/2 on $mux $procmux$94257. + dead port 1/2 on $mux $procmux$94260. + dead port 1/2 on $mux $procmux$94263. + dead port 1/2 on $mux $procmux$94266. + dead port 1/2 on $mux $procmux$94269. + dead port 1/2 on $mux $procmux$94272. + dead port 1/2 on $mux $procmux$94275. + dead port 1/2 on $mux $procmux$94278. + dead port 1/2 on $mux $procmux$94281. + dead port 1/2 on $mux $procmux$94284. + dead port 1/2 on $mux $procmux$94287. + dead port 1/2 on $mux $procmux$94290. + dead port 2/2 on $mux $procmux$94293. + dead port 1/2 on $mux $procmux$94300. + dead port 2/2 on $mux $procmux$94302. + dead port 1/2 on $mux $procmux$94305. + dead port 1/2 on $mux $procmux$94308. + dead port 1/2 on $mux $procmux$94311. + dead port 1/2 on $mux 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$procmux$98739. + dead port 1/2 on $mux $procmux$98742. + dead port 1/2 on $mux $procmux$98745. + dead port 1/2 on $mux $procmux$98748. + dead port 1/2 on $mux $procmux$98751. + dead port 1/2 on $mux $procmux$98754. + dead port 1/2 on $mux $procmux$98757. + dead port 1/2 on $mux $procmux$9876. + dead port 1/2 on $mux $procmux$98760. + dead port 1/2 on $mux $procmux$98763. + dead port 2/2 on $mux $procmux$98766. + dead port 2/2 on $mux $procmux$98772. + dead port 1/2 on $mux $procmux$98775. + dead port 1/2 on $mux $procmux$98778. + dead port 1/2 on $mux $procmux$98781. + dead port 1/2 on $mux $procmux$98784. + dead port 1/2 on $mux $procmux$98787. + dead port 1/2 on $mux $procmux$9879. + dead port 1/2 on $mux $procmux$98790. + dead port 1/2 on $mux $procmux$98793. + dead port 1/2 on $mux $procmux$98796. + dead port 1/2 on $mux $procmux$98799. + dead port 1/2 on $mux $procmux$98802. + dead port 1/2 on $mux $procmux$98805. + dead port 2/2 on $mux $procmux$98808. + dead port 1/2 on $mux $procmux$9882. + dead port 1/2 on $mux $procmux$9885. + dead port 1/2 on $mux $procmux$9888. + dead port 2/2 on $mux $procmux$98898. + dead port 1/2 on $mux $procmux$98901. + dead port 1/2 on $mux $procmux$98904. + dead port 1/2 on $mux $procmux$98907. + dead port 1/2 on $mux $procmux$9891. + dead port 1/2 on $mux $procmux$98910. + dead port 1/2 on $mux $procmux$98913. + dead port 1/2 on $mux $procmux$98916. + dead port 1/2 on $mux $procmux$98919. + dead port 1/2 on $mux $procmux$98922. + dead port 1/2 on $mux $procmux$98925. + dead port 1/2 on $mux $procmux$98928. + dead port 1/2 on $mux $procmux$98931. + dead port 2/2 on $mux $procmux$98934. + dead port 1/2 on $mux $procmux$9894. + dead port 2/2 on $mux $procmux$98940. + dead port 1/2 on $mux $procmux$98943. + dead port 1/2 on $mux $procmux$98946. + dead port 1/2 on $mux $procmux$98949. + dead port 1/2 on $mux $procmux$98952. + dead port 1/2 on $mux $procmux$98955. + dead port 1/2 on $mux $procmux$98958. + dead port 1/2 on $mux $procmux$98961. + dead port 1/2 on $mux $procmux$98964. + dead port 1/2 on $mux $procmux$98967. + dead port 1/2 on $mux $procmux$9897. + dead port 1/2 on $mux $procmux$98970. + dead port 1/2 on $mux $procmux$98973. + dead port 2/2 on $mux $procmux$98976. + dead port 2/2 on $mux $procmux$98982. + dead port 1/2 on $mux $procmux$98985. + dead port 1/2 on $mux $procmux$98988. + dead port 1/2 on $mux $procmux$98991. + dead port 1/2 on $mux $procmux$98994. + dead port 1/2 on $mux $procmux$98997. + dead port 2/2 on $mux $procmux$9900. + dead port 1/2 on $mux $procmux$99000. + dead port 1/2 on $mux $procmux$99003. + dead port 1/2 on $mux $procmux$99006. + dead port 1/2 on $mux $procmux$99009. + dead port 1/2 on $mux $procmux$99012. + dead port 1/2 on $mux $procmux$99015. + dead port 2/2 on $mux $procmux$99018. + dead port 2/2 on $mux $procmux$99024. + dead port 1/2 on $mux $procmux$99027. + dead port 1/2 on $mux $procmux$99030. + dead port 1/2 on $mux $procmux$99033. + dead port 1/2 on $mux $procmux$99036. + dead port 1/2 on $mux $procmux$99039. + dead port 1/2 on $mux $procmux$99042. + dead port 1/2 on $mux $procmux$99045. + dead port 1/2 on $mux $procmux$99048. + dead port 1/2 on $mux $procmux$99051. + dead port 1/2 on $mux $procmux$99054. + dead port 1/2 on $mux $procmux$99057. + dead port 2/2 on $mux $procmux$99060. + dead port 2/2 on $mux $procmux$99066. + dead port 1/2 on $mux $procmux$99069. + dead port 1/2 on $mux $procmux$9907. + dead port 1/2 on $mux $procmux$99072. + dead port 1/2 on $mux $procmux$99075. + dead port 1/2 on $mux $procmux$99078. + dead port 1/2 on $mux $procmux$99081. + dead port 1/2 on $mux $procmux$99084. + dead port 1/2 on $mux $procmux$99087. + dead port 1/2 on $mux $procmux$99090. + dead port 1/2 on $mux $procmux$99093. + dead port 1/2 on $mux $procmux$99096. + dead port 1/2 on $mux $procmux$99099. + dead port 1/2 on $mux $procmux$9910. + dead port 2/2 on $mux $procmux$99102. + dead port 2/2 on $mux $procmux$99108. + dead port 1/2 on $mux $procmux$99111. + dead port 1/2 on $mux $procmux$99114. + dead port 1/2 on $mux $procmux$99117. + dead port 1/2 on $mux $procmux$99120. + dead port 1/2 on $mux $procmux$99123. + dead port 1/2 on $mux $procmux$99126. + dead port 1/2 on $mux $procmux$99129. + dead port 1/2 on $mux $procmux$9913. + dead port 1/2 on $mux $procmux$99132. + dead port 1/2 on $mux $procmux$99135. + dead port 1/2 on $mux $procmux$99138. + dead port 1/2 on $mux $procmux$99141. + dead port 2/2 on $mux $procmux$99144. + dead port 2/2 on $mux $procmux$99150. + dead port 1/2 on $mux $procmux$99153. + dead port 1/2 on $mux $procmux$99156. + dead port 1/2 on $mux $procmux$99159. + dead port 1/2 on $mux $procmux$9916. + dead port 1/2 on $mux $procmux$99162. + dead port 1/2 on $mux $procmux$99165. + dead port 1/2 on $mux $procmux$99168. + dead port 1/2 on $mux $procmux$99171. + dead port 1/2 on $mux $procmux$99174. + dead port 1/2 on $mux $procmux$99177. + dead port 1/2 on $mux $procmux$99180. + dead port 1/2 on $mux $procmux$99183. + dead port 2/2 on $mux $procmux$99186. + dead port 1/2 on $mux $procmux$9919. + dead port 2/2 on $mux $procmux$99192. + dead port 1/2 on $mux $procmux$99195. + dead port 1/2 on $mux $procmux$99198. + dead port 1/2 on $mux $procmux$99201. + dead port 1/2 on $mux $procmux$99204. + dead port 1/2 on $mux $procmux$99207. + dead port 1/2 on $mux $procmux$99210. + dead port 1/2 on $mux $procmux$99213. + dead port 1/2 on $mux $procmux$99216. + dead port 1/2 on $mux $procmux$99219. + dead port 1/2 on $mux $procmux$9922. + dead port 1/2 on $mux $procmux$99222. + dead port 1/2 on $mux $procmux$99225. + dead port 2/2 on $mux $procmux$99228. + dead port 2/2 on $mux $procmux$99234. + dead port 1/2 on $mux $procmux$99237. + dead port 1/2 on $mux $procmux$99240. + dead port 1/2 on $mux $procmux$99243. + dead port 1/2 on $mux $procmux$99246. + dead port 1/2 on $mux $procmux$99249. + dead port 1/2 on $mux $procmux$9925. + dead port 1/2 on $mux $procmux$99252. + dead port 1/2 on $mux $procmux$99255. + dead port 1/2 on $mux $procmux$99258. + dead port 1/2 on $mux $procmux$99261. + dead port 1/2 on $mux $procmux$99264. + dead port 1/2 on $mux $procmux$99267. + dead port 2/2 on $mux $procmux$99270. + dead port 2/2 on $mux $procmux$99276. + dead port 1/2 on $mux $procmux$99279. + dead port 1/2 on $mux $procmux$9928. + dead port 1/2 on $mux $procmux$99282. + dead port 1/2 on $mux $procmux$99285. + dead port 1/2 on $mux $procmux$99288. + dead port 1/2 on $mux $procmux$99291. + dead port 1/2 on $mux $procmux$99294. + dead port 1/2 on $mux $procmux$99297. + dead port 1/2 on $mux $procmux$99300. + dead port 1/2 on $mux $procmux$99303. + dead port 1/2 on $mux $procmux$99306. + dead port 1/2 on $mux $procmux$99309. + dead port 1/2 on $mux $procmux$9931. + dead port 2/2 on $mux $procmux$99312. + dead port 1/2 on $mux $procmux$9934. + dead port 2/2 on $mux $procmux$99360. + dead port 1/2 on $mux $procmux$99363. + dead port 1/2 on $mux $procmux$99366. + dead port 1/2 on $mux $procmux$99369. + dead port 1/2 on $mux $procmux$9937. + dead port 1/2 on $mux $procmux$99372. + dead port 1/2 on $mux $procmux$99375. + dead port 1/2 on $mux $procmux$99378. + dead port 1/2 on $mux $procmux$99381. + dead port 1/2 on $mux $procmux$99384. + dead port 1/2 on $mux $procmux$99387. + dead port 1/2 on $mux $procmux$99390. + dead port 1/2 on $mux $procmux$99393. + dead port 2/2 on $mux $procmux$99396. + dead port 1/2 on $mux $procmux$9940. + dead port 2/2 on $mux $procmux$99402. + dead port 1/2 on $mux $procmux$99405. + dead port 1/2 on $mux $procmux$99408. + dead port 1/2 on $mux $procmux$99411. + dead port 1/2 on $mux $procmux$99414. + dead port 1/2 on $mux $procmux$99417. + dead port 1/2 on $mux $procmux$99420. + dead port 1/2 on $mux $procmux$99423. + dead port 1/2 on $mux $procmux$99426. + dead port 1/2 on $mux $procmux$99429. + dead port 1/2 on $mux $procmux$9943. + dead port 1/2 on $mux $procmux$99432. + dead port 1/2 on $mux $procmux$99435. + dead port 2/2 on $mux $procmux$99438. + dead port 2/2 on $mux $procmux$99444. + dead port 1/2 on $mux $procmux$99447. + dead port 1/2 on $mux $procmux$99450. + dead port 1/2 on $mux $procmux$99453. + dead port 1/2 on $mux $procmux$99456. + dead port 1/2 on $mux $procmux$99459. + dead port 1/2 on $mux $procmux$9946. + dead port 1/2 on $mux $procmux$99462. + dead port 1/2 on $mux $procmux$99465. + dead port 1/2 on $mux $procmux$99468. + dead port 1/2 on $mux $procmux$99471. + dead port 1/2 on $mux $procmux$99474. + dead port 1/2 on $mux $procmux$99477. + dead port 2/2 on $mux $procmux$99480. + dead port 1/2 on $mux $procmux$9949. + dead port 1/2 on $mux $procmux$9952. + dead port 1/2 on $mux $procmux$9955. + dead port 2/2 on $mux $procmux$9957. + dead port 1/2 on $mux $procmux$9960. + dead port 2/2 on $mux $procmux$99612. + dead port 1/2 on $mux $procmux$99615. + dead port 1/2 on $mux $procmux$99618. + dead port 1/2 on $mux $procmux$99621. + dead port 1/2 on $mux $procmux$99624. + dead port 1/2 on $mux $procmux$99627. + dead port 1/2 on $mux $procmux$9963. + dead port 1/2 on $mux $procmux$99630. + dead port 1/2 on $mux $procmux$99633. + dead port 1/2 on $mux $procmux$99636. + dead port 1/2 on $mux $procmux$99639. + dead port 1/2 on $mux $procmux$99642. + dead port 1/2 on $mux $procmux$99645. + dead port 2/2 on $mux $procmux$99648. + dead port 2/2 on $mux $procmux$99654. + dead port 1/2 on $mux $procmux$99657. + dead port 1/2 on $mux $procmux$9966. + dead port 1/2 on $mux $procmux$99660. + dead port 1/2 on $mux $procmux$99663. + dead port 1/2 on $mux $procmux$99666. + dead port 1/2 on $mux $procmux$99669. + dead port 1/2 on $mux $procmux$99672. + dead port 1/2 on $mux $procmux$99675. + dead port 1/2 on $mux $procmux$99678. + dead port 1/2 on $mux $procmux$99681. + dead port 1/2 on $mux $procmux$99684. + dead port 1/2 on $mux $procmux$99687. + dead port 1/2 on $mux $procmux$9969. + dead port 2/2 on $mux $procmux$99690. + dead port 2/2 on $mux $procmux$99696. + dead port 1/2 on $mux $procmux$99699. + dead port 1/2 on $mux $procmux$99702. + dead port 1/2 on $mux $procmux$99705. + dead port 1/2 on $mux $procmux$99708. + dead port 1/2 on $mux $procmux$99711. + dead port 1/2 on $mux $procmux$99714. + dead port 1/2 on $mux $procmux$99717. + dead port 1/2 on $mux $procmux$9972. + dead port 1/2 on $mux $procmux$99720. + dead port 1/2 on $mux $procmux$99723. + dead port 1/2 on $mux $procmux$99726. + dead port 1/2 on $mux $procmux$99729. + dead port 2/2 on $mux $procmux$99732. + dead port 1/2 on $mux $procmux$9975. + dead port 1/2 on $mux $procmux$9978. + dead port 2/2 on $mux $procmux$99780. + dead port 1/2 on $mux $procmux$99783. + dead port 1/2 on $mux $procmux$99786. + dead port 1/2 on $mux $procmux$99789. + dead port 1/2 on $mux $procmux$99792. + dead port 1/2 on $mux $procmux$99795. + dead port 1/2 on $mux $procmux$99798. + dead port 1/2 on $mux $procmux$99801. + dead port 1/2 on $mux $procmux$99804. + dead port 1/2 on $mux $procmux$99807. + dead port 1/2 on $mux $procmux$9981. + dead port 1/2 on $mux $procmux$99810. + dead port 1/2 on $mux $procmux$99813. + dead port 2/2 on $mux $procmux$99816. + dead port 2/2 on $mux $procmux$99822. + dead port 1/2 on $mux $procmux$99825. + dead port 1/2 on $mux $procmux$99828. + dead port 1/2 on $mux $procmux$99831. + dead port 1/2 on $mux $procmux$99834. + dead port 1/2 on $mux $procmux$99837. + dead port 1/2 on $mux $procmux$9984. + dead port 1/2 on $mux $procmux$99840. + dead port 1/2 on $mux $procmux$99843. + dead port 1/2 on $mux $procmux$99846. + dead port 1/2 on $mux $procmux$99849. + dead port 1/2 on $mux $procmux$99852. + dead port 1/2 on $mux $procmux$99855. + dead port 2/2 on $mux $procmux$99858. + dead port 1/2 on $mux $procmux$9987. + dead port 1/2 on $mux $procmux$9990. + dead port 2/2 on $mux $procmux$9993. +Removed 17197 multiplexer ports. + + +13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend. + New ctrl vector for $pmux cell $flatten\field_encoder.\multiplier.\datapath.$procmux$143706: { $auto$opt_reduce.cc:134:opt_pmux$146483 $flatten\field_encoder.\multiplier.\datapath.$procmux$143778_CMP } + New ctrl vector for $pmux cell $flatten\field_encoder.\multiplier.\datapath.$procmux$143694: { $flatten\field_encoder.\multiplier.\datapath.$procmux$143851_CMP $auto$opt_reduce.cc:134:opt_pmux$146485 } + New ctrl vector for $pmux cell $flatten\adapter.\datapath.$procmux$143796: { $auto$opt_reduce.cc:134:opt_pmux$146487 $flatten\adapter.\datapath.$procmux$143798_CMP $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:211$608_Y } + New ctrl vector for $pmux cell $flatten\field_encoder.\multiplier.\datapath.$procmux$143888: { $auto$opt_reduce.cc:134:opt_pmux$146491 $flatten\field_encoder.\multiplier.\datapath.$procmux$143900_CMP $auto$opt_reduce.cc:134:opt_pmux$146489 } + New ctrl vector for $pmux cell $flatten\adapter.\datapath.$procmux$143844: { $auto$opt_reduce.cc:134:opt_pmux$146495 $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $auto$opt_reduce.cc:134:opt_pmux$146493 } + New ctrl vector for $pmux cell $flatten\adapter.\datapath.$procmux$143888: { $auto$opt_reduce.cc:134:opt_pmux$146499 $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $auto$opt_reduce.cc:134:opt_pmux$146497 } + New ctrl vector for $pmux cell $flatten\field_encoder.\multiplier.\datapath.$procmux$143844: { $auto$opt_reduce.cc:134:opt_pmux$146503 $flatten\field_encoder.\multiplier.\datapath.$procmux$143900_CMP $auto$opt_reduce.cc:134:opt_pmux$146501 } + New ctrl vector for $pmux cell $flatten\field_encoder.\multiplier.\datapath.$procmux$143796: { $auto$opt_reduce.cc:134:opt_pmux$146505 $flatten\field_encoder.\multiplier.\datapath.$procmux$143798_CMP $flatten\field_encoder.\multiplier.\datapath.$procmux$143797_CMP } + New ctrl vector for $pmux cell $flatten\field_encoder.\multiplier.$procmux$143306: { $flatten\field_encoder.\multiplier.$eq$asic_core/rtl/lsc1_stream_adapter.sv:39$640_Y $flatten\field_encoder.\multiplier.$eq$asic_core/rtl/lsc1_stream_adapter.sv:103$694_Y } + New ctrl vector for $pmux cell $flatten\receiver.$procmux$145943: { $auto$opt_reduce.cc:134:opt_pmux$146507 $flatten\receiver.$procmux$146018_CMP } + New ctrl vector for $pmux cell $flatten\adapter.\datapath.$procmux$143694: { $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$588_Y $auto$opt_reduce.cc:134:opt_pmux$146509 } + New ctrl vector for $pmux cell $flatten\adapter.\datapath.$procmux$143706: { $auto$opt_reduce.cc:134:opt_pmux$146511 $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$590_Y } + Optimizing cells in module \lsc1_packet_frontend. +Performed a total of 14 changes. + +13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend'. + +Removed a total of 142 cells. + +13.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\field_encoder.$procdff$146266 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$143036_Y, Q = \field_encoder.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$146512 ($sdff) from module lsc1_packet_frontend (D = 1'1, Q = \field_encoder.fault). +Adding SRST signal on $flatten\field_encoder.$procdff$146267 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$143027_Y [0], Q = \field_encoder.operand_a [0], rval = 1'0). +Adding SRST signal on $flatten\field_encoder.$procdff$146267 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$143024_Y [127:1], Q = \field_encoder.operand_a [127:1], rval = 127'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146519 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$ternary$asic_core/rtl/lsc1_field_encoder.sv:63$772_Y [127:1], Q = \field_encoder.operand_a [127:1]). +Adding EN signal on $auto$ff.cc:266:slice$146518 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$143027_Y [0], Q = \field_encoder.operand_a [0]). +Adding SRST signal on $flatten\receiver.$procdff$146335 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$146095_Y, Q = \receiver.frame_valid, rval = 1'0). +Adding SRST signal on $flatten\receiver.$procdff$146336 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$146070_Y, Q = \receiver.frame_opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$146539 ($sdff) from module lsc1_packet_frontend (D = \receiver.opcode, Q = \receiver.frame_opcode). +Adding SRST signal on $flatten\receiver.$procdff$146337 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$146047_Y, Q = \receiver.frame_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146551 ($sdff) from module lsc1_packet_frontend (D = \receiver.declared_length, Q = \receiver.frame_length). +Adding SRST signal on $flatten\receiver.$procdff$146338 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$2$lookahead\frame_payload$22[2047:0]$81, Q = \receiver.frame_payload, rval = 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding SRST signal on $flatten\receiver.$procdff$146339 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$146024_Y, Q = \receiver.fault_valid, rval = 1'0). +Adding SRST signal on $flatten\receiver.$procdff$146340 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145988_Y, Q = \receiver.fault_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$146565 ($sdff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145975_Y, Q = \receiver.fault_status). +Adding SRST signal on $flatten\receiver.$procdff$146341 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145954_Y, Q = \receiver.state, rval = 3'000). +Adding SRST signal on $flatten\receiver.$procdff$146342 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145915_Y, Q = \receiver.header_index, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$146584 ($sdff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145909_Y, Q = \receiver.header_index). +Adding SRST signal on $flatten\receiver.$procdff$146343 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145901_Y, Q = \receiver.body_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146592 ($sdff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145894_Y, Q = \receiver.body_index). +Adding SRST signal on $flatten\receiver.$procdff$146344 ($dff) from module lsc1_packet_frontend (D = { $flatten\receiver.$procmux$145399_Y $flatten\receiver.$procmux$145413_Y }, Q = \receiver.declared_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146600 ($sdff) from module lsc1_packet_frontend (D = \receiver.rx_data, Q = \receiver.declared_length [7:0]). +Adding EN signal on $auto$ff.cc:266:slice$146600 ($sdff) from module lsc1_packet_frontend (D = \receiver.rx_data, Q = \receiver.declared_length [15:8]). +Adding SRST signal on $flatten\receiver.$procdff$146345 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145873_Y, Q = \receiver.version, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$146607 ($sdff) from module lsc1_packet_frontend (D = \receiver.rx_data, Q = \receiver.version). +Adding SRST signal on $flatten\receiver.$procdff$146346 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145856_Y, Q = \receiver.opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$146611 ($sdff) from module lsc1_packet_frontend (D = \receiver.rx_data, Q = \receiver.opcode). +Adding SRST signal on $flatten\receiver.$procdff$146347 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145840_Y, Q = \receiver.flags, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$146615 ($sdff) from module lsc1_packet_frontend (D = \receiver.rx_data, Q = \receiver.flags). +Adding SRST signal on $flatten\receiver.$procdff$146348 ($dff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145825_Y, Q = \receiver.crc, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$146619 ($sdff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145818_Y, Q = \receiver.crc). +Adding SRST signal on $flatten\receiver.$procdff$146349 ($dff) from module lsc1_packet_frontend (D = { $flatten\receiver.$procmux$145182_Y $flatten\receiver.$procmux$145198_Y $flatten\receiver.$procmux$145215_Y $flatten\receiver.$procmux$145233_Y }, Q = \receiver.received_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$146629 ($sdff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145179_Y, Q = \receiver.received_crc [31:24]). +Adding EN signal on $auto$ff.cc:266:slice$146629 ($sdff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145230_Y, Q = \receiver.received_crc [7:0]). +Adding EN signal on $auto$ff.cc:266:slice$146629 ($sdff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145212_Y, Q = \receiver.received_crc [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$146629 ($sdff) from module lsc1_packet_frontend (D = $flatten\receiver.$procmux$145195_Y, Q = \receiver.received_crc [23:16]). +Adding SRST signal on $flatten\field_encoder.$procdff$146268 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$143012_Y [0], Q = \field_encoder.operand_b [0], rval = 1'0). +Adding SRST signal on $flatten\field_encoder.$procdff$146268 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$143009_Y [127:1], Q = \field_encoder.operand_b [127:1], rval = 127'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146667 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$ternary$asic_core/rtl/lsc1_field_encoder.sv:63$772_Y [127:1], Q = \field_encoder.operand_b [127:1]). +Adding EN signal on $auto$ff.cc:266:slice$146666 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$143012_Y [0], Q = \field_encoder.operand_b [0]). +Adding SRST signal on $flatten\field_encoder.$procdff$146269 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$142997_Y, Q = \field_encoder.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146686 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$ternary$asic_core/rtl/lsc1_field_encoder.sv:63$772_Y, Q = \field_encoder.result). +Adding SRST signal on $flatten\adapter.\datapath.$procdff$146295 ($dff) from module lsc1_packet_frontend (D = { $flatten\adapter.\datapath.$procmux$143597_Y $flatten\adapter.\datapath.$procmux$143619_Y }, Q = \adapter.datapath.scratch_byte, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$146694 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143619_Y, Q = \adapter.datapath.scratch_byte [0]). +Adding EN signal on $auto$ff.cc:266:slice$146694 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143597_Y, Q = \adapter.datapath.scratch_byte [7:1]). +Adding SRST signal on $flatten\adapter.\datapath.$procdff$146294 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143647_Y, Q = \adapter.datapath.byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$146725 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143647_Y, Q = \adapter.datapath.byte_index). +Adding SRST signal on $flatten\adapter.\datapath.$procdff$146293 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143717_Y, Q = \adapter.datapath.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$146747 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143717_Y, Q = \adapter.datapath.fault). +Adding SRST signal on $flatten\adapter.\datapath.$procdff$146292 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143725_Y, Q = \adapter.datapath.state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$146757 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143725_Y, Q = \adapter.datapath.state). +Adding SRST signal on $flatten\field_encoder.$procdff$146270 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$142937_Y, Q = \field_encoder.multiply_start, rval = 1'0). +Adding SRST signal on $flatten\field_encoder.$procdff$146271 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$142982_Y [3:0], Q = \field_encoder.bit_index [3:0], rval = 4'0000). +Adding SRST signal on $flatten\field_encoder.$procdff$146271 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$142979_Y [4], Q = \field_encoder.bit_index [4], rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$146787 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$sub$asic_core/rtl/lsc1_field_encoder.sv:76$774_Y [4], Q = \field_encoder.bit_index [4]). +Adding EN signal on $auto$ff.cc:266:slice$146786 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$142982_Y [3:0], Q = \field_encoder.bit_index [3:0]). +Adding SRST signal on $flatten\field_encoder.\multiplier.$procdff$146284 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143358_Y, Q = \field_encoder.multiplier.result_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:266:slice$146806 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143358_Y, Q = \field_encoder.multiplier.result_index). +Adding SRST signal on $flatten\field_encoder.\multiplier.$procdff$146283 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143389_Y, Q = \field_encoder.multiplier.payload_index, rval = 6'000000). +Adding EN signal on $auto$ff.cc:266:slice$146822 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143389_Y, Q = \field_encoder.multiplier.payload_index). +Adding SRST signal on $flatten\field_encoder.\multiplier.$procdff$146282 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143415_Y, Q = \field_encoder.multiplier.saved_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146840 ($sdff) from module lsc1_packet_frontend (D = \field_encoder.multiplier.operand_b, Q = \field_encoder.multiplier.saved_b). +Adding SRST signal on $flatten\field_encoder.\multiplier.$procdff$146281 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143431_Y, Q = \field_encoder.multiplier.saved_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146846 ($sdff) from module lsc1_packet_frontend (D = \field_encoder.multiplier.operand_a, Q = \field_encoder.multiplier.saved_a). +Adding SRST signal on $flatten\field_encoder.\multiplier.$procdff$146280 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143447_Y, Q = \field_encoder.multiplier.saved_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$146852 ($sdff) from module lsc1_packet_frontend (D = 8'00000010, Q = \field_encoder.multiplier.saved_operation). +Adding SRST signal on $flatten\field_encoder.\multiplier.$procdff$146279 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$2$lookahead\result$670[127:0]$693, Q = \field_encoder.multiplier.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding SRST signal on $flatten\field_encoder.\multiplier.$procdff$146278 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143468_Y, Q = \field_encoder.multiplier.fault, rval = 1'0). +Adding SRST signal on $flatten\field_encoder.\multiplier.$procdff$146277 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143306_Y, Q = \field_encoder.multiplier.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\field_encoder.\multiplier.$procdff$146276 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143480_Y, Q = \field_encoder.multiplier.state, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$146865 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$procmux$143480_Y, Q = \field_encoder.multiplier.state). +Adding SRST signal on $flatten\field_encoder.$procdff$146272 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$142967_Y, Q = \field_encoder.saved_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146887 ($sdff) from module lsc1_packet_frontend (D = \field_encoder.index, Q = \field_encoder.saved_index). +Adding SRST signal on $flatten\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procdff$146296 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$144142_Y, Q = \field_encoder.multiplier.datapath.multiplier.impl.a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146889 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$144142_Y, Q = \field_encoder.multiplier.datapath.multiplier.impl.a_shift). +Adding SRST signal on $flatten\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procdff$146297 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$144127_Y, Q = \field_encoder.multiplier.datapath.multiplier.impl.accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$146901 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.\multiplier.\impl.$procmux$144127_Y, Q = \field_encoder.multiplier.datapath.multiplier.impl.accumulator). +Adding SRST signal on $flatten\field_encoder.\multiplier.\datapath.$procdff$146292 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143725_Y, Q = \field_encoder.multiplier.datapath.state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$146913 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143725_Y, Q = \field_encoder.multiplier.datapath.state). +Adding SRST signal on $flatten\field_encoder.\multiplier.\datapath.$procdff$146293 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143717_Y, Q = \field_encoder.multiplier.datapath.fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$146941 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143717_Y, Q = \field_encoder.multiplier.datapath.fault). +Adding SRST signal on $flatten\field_encoder.\multiplier.\datapath.$procdff$146294 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143647_Y, Q = \field_encoder.multiplier.datapath.byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$146951 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143647_Y, Q = \field_encoder.multiplier.datapath.byte_index). +Adding SRST signal on $flatten\field_encoder.\multiplier.\datapath.$procdff$146295 ($dff) from module lsc1_packet_frontend (D = { $flatten\field_encoder.\multiplier.\datapath.$procmux$143597_Y $flatten\field_encoder.\multiplier.\datapath.$procmux$143619_Y }, Q = \field_encoder.multiplier.datapath.scratch_byte, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$146973 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143619_Y, Q = \field_encoder.multiplier.datapath.scratch_byte [0]). +Adding EN signal on $auto$ff.cc:266:slice$146973 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143597_Y, Q = \field_encoder.multiplier.datapath.scratch_byte [7:1]). +Adding EN signal on $procdff$146161 ($dff) from module lsc1_packet_frontend (D = $2\write_value[127:0], Q = \write_value). +Adding EN signal on $procdff$146160 ($dff) from module lsc1_packet_frontend (D = $2\write_address[31:0], Q = \write_address). +Adding EN signal on $procdff$146157 ($dff) from module lsc1_packet_frontend (D = $2\solved_b[127:0], Q = \solved_b). +Adding EN signal on $procdff$146156 ($dff) from module lsc1_packet_frontend (D = $2\solved_a[127:0], Q = \solved_a). +Adding EN signal on $procdff$146155 ($dff) from module lsc1_packet_frontend (D = $2\result_value[127:0], Q = \result_value). +Adding EN signal on $procdff$146154 ($dff) from module lsc1_packet_frontend (D = $2\inv_value[127:0], Q = \inv_value). +Adding EN signal on $procdff$146153 ($dff) from module lsc1_packet_frontend (D = $2\val_c[127:0], Q = \val_c). +Adding EN signal on $procdff$146152 ($dff) from module lsc1_packet_frontend (D = $2\val_b[127:0], Q = \val_b). +Adding EN signal on $procdff$146151 ($dff) from module lsc1_packet_frontend (D = $2\val_a[127:0], Q = \val_a). +Adding EN signal on $procdff$146148 ($dff) from module lsc1_packet_frontend (D = $2\pres_c[7:0], Q = \pres_c). +Adding EN signal on $procdff$146147 ($dff) from module lsc1_packet_frontend (D = $2\pres_b[7:0], Q = \pres_b). +Adding EN signal on $procdff$146146 ($dff) from module lsc1_packet_frontend (D = $2\pres_a[7:0], Q = \pres_a). +Adding EN signal on $procdff$146145 ($dff) from module lsc1_packet_frontend (D = $2\profile[7:0], Q = \profile). +Adding EN signal on $procdff$146144 ($dff) from module lsc1_packet_frontend (D = $2\deferred_local[31:0], Q = \deferred_local). +Adding EN signal on $procdff$146143 ($dff) from module lsc1_packet_frontend (D = $2\deferred_target[31:0], Q = \deferred_target). +Adding EN signal on $procdff$146142 ($dff) from module lsc1_packet_frontend (D = $2\next_fp_value[31:0], Q = \next_fp_value). +Adding EN signal on $procdff$146141 ($dff) from module lsc1_packet_frontend (D = $2\next_pc_value[31:0], Q = \next_pc_value). +Adding EN signal on $procdff$146140 ($dff) from module lsc1_packet_frontend (D = $2\proposed_fp[31:0], Q = \proposed_fp). +Adding EN signal on $procdff$146139 ($dff) from module lsc1_packet_frontend (D = $2\proposed_pc[31:0], Q = \proposed_pc). +Adding EN signal on $procdff$146137 ($dff) from module lsc1_packet_frontend (D = $2\addr_c[31:0], Q = \addr_c). +Adding EN signal on $procdff$146136 ($dff) from module lsc1_packet_frontend (D = $2\addr_b[31:0], Q = \addr_b). +Adding EN signal on $procdff$146135 ($dff) from module lsc1_packet_frontend (D = $2\addr_a[31:0], Q = \addr_a). +Adding EN signal on $procdff$146131 ($dff) from module lsc1_packet_frontend (D = $2\fp[31:0], Q = \fp). +Adding EN signal on $procdff$146130 ($dff) from module lsc1_packet_frontend (D = $2\pc[31:0], Q = \pc). +Adding EN signal on $procdff$146129 ($dff) from module lsc1_packet_frontend (D = $2\txn_id[31:0], Q = \txn_id). +Adding EN signal on $procdff$146127 ($dff) from module lsc1_packet_frontend (D = $2\n_deferred[31:0], Q = \n_deferred). +Adding EN signal on $procdff$146126 ($dff) from module lsc1_packet_frontend (D = $2\n_writes[31:0], Q = \n_writes). +Adding SRST signal on $procdff$146125 ($dff) from module lsc1_packet_frontend (D = { $procmux$140336_Y [7] $procmux$140336_Y [4] $procmux$140336_Y [1:0] }, Q = { \last_fault [7] \last_fault [4] \last_fault [1:0] }, rval = 4'0000). +Adding SRST signal on $procdff$146125 ($dff) from module lsc1_packet_frontend (D = { $procmux$140333_Y [6:5] $procmux$140333_Y [3:2] }, Q = { \last_fault [6:5] \last_fault [3:2] }, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$147032 ($sdff) from module lsc1_packet_frontend (D = { $procmux$140333_Y [6:5] $procmux$140333_Y [3:2] }, Q = { \last_fault [6:5] \last_fault [3:2] }). +Adding EN signal on $auto$ff.cc:266:slice$147031 ($sdff) from module lsc1_packet_frontend (D = { $procmux$140336_Y [7] $procmux$140336_Y [4] $procmux$140336_Y [1:0] }, Q = { \last_fault [7] \last_fault [4] \last_fault [1:0] }). +Adding SRST signal on $procdff$146124 ($dff) from module lsc1_packet_frontend (D = { $procmux$140495_Y [7] $procmux$140495_Y [4] $procmux$140495_Y [1:0] }, Q = { \last_status [7] \last_status [4] \last_status [1:0] }, rval = 4'0000). +Adding SRST signal on $procdff$146124 ($dff) from module lsc1_packet_frontend (D = { $procmux$140492_Y [6:5] $procmux$140492_Y [3:2] }, Q = { \last_status [6:5] \last_status [3:2] }, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$147104 ($sdff) from module lsc1_packet_frontend (D = { $procmux$140492_Y [6:5] $procmux$140492_Y [3:2] }, Q = { \last_status [6:5] \last_status [3:2] }). +Adding EN signal on $auto$ff.cc:266:slice$147103 ($sdff) from module lsc1_packet_frontend (D = { $procmux$140495_Y [7] $procmux$140495_Y [4] $procmux$140495_Y [1:0] }, Q = { \last_status [7] \last_status [4] \last_status [1:0] }). +Adding SRST signal on $procdff$146123 ($dff) from module lsc1_packet_frontend (D = $procmux$140558_Y, Q = \active_profile, rval = 8'00000001). +Adding EN signal on $auto$ff.cc:266:slice$147139 ($sdff) from module lsc1_packet_frontend (D = \frame_payload [23:16], Q = \active_profile). +Adding SRST signal on $procdff$146122 ($dff) from module lsc1_packet_frontend (D = $procmux$140618_Y, Q = \retire_seq, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$147177 ($sdff) from module lsc1_packet_frontend (D = $add$asic_core/rtl/lsc1_packet_frontend.sv:484$2454_Y, Q = \retire_seq). +Adding SRST signal on $procdff$146121 ($dff) from module lsc1_packet_frontend (D = $procmux$140678_Y, Q = \committed_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$147213 ($sdff) from module lsc1_packet_frontend (D = \staged_next_fp, Q = \committed_fp). +Adding SRST signal on $procdff$146120 ($dff) from module lsc1_packet_frontend (D = $procmux$140738_Y, Q = \committed_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$147249 ($sdff) from module lsc1_packet_frontend (D = \staged_next_pc, Q = \committed_pc). +Adding SRST signal on $procdff$146119 ($dff) from module lsc1_packet_frontend (D = $procmux$140798_Y, Q = \state_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$147285 ($sdff) from module lsc1_packet_frontend (D = 1'1, Q = \state_valid). +Adding SRST signal on $procdff$146118 ($dff) from module lsc1_packet_frontend (D = $procmux$140920_Y, Q = \staged_result_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$147321 ($sdff) from module lsc1_packet_frontend (D = $procmux$140917_Y, Q = \staged_result_crc). +Adding SRST signal on $procdff$146117 ($dff) from module lsc1_packet_frontend (D = $procmux$141040_Y, Q = \staged_next_fp, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$147323 ($sdff) from module lsc1_packet_frontend (D = $procmux$141037_Y, Q = \staged_next_fp). +Adding SRST signal on $procdff$146116 ($dff) from module lsc1_packet_frontend (D = $procmux$141160_Y, Q = \staged_next_pc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$147395 ($sdff) from module lsc1_packet_frontend (D = $procmux$141157_Y, Q = \staged_next_pc). +Adding SRST signal on $procdff$146115 ($dff) from module lsc1_packet_frontend (D = $procmux$141280_Y, Q = \staged_txn_id, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$147467 ($sdff) from module lsc1_packet_frontend (D = $procmux$141277_Y, Q = \staged_txn_id). +Adding SRST signal on $procdff$146114 ($dff) from module lsc1_packet_frontend (D = $procmux$141405_Y, Q = \result_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$147539 ($sdff) from module lsc1_packet_frontend (D = $procmux$141405_Y, Q = \result_pending). +Adding SRST signal on $procdff$146113 ($dff) from module lsc1_packet_frontend (D = $procmux$141522_Y, Q = \encoder_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$147607 ($sdff) from module lsc1_packet_frontend (D = $procmux$141519_Y, Q = \encoder_index). +Adding SRST signal on $procdff$146112 ($dff) from module lsc1_packet_frontend (D = $procmux$139482_Y, Q = \encoder_start, rval = 1'0). +Adding SRST signal on $procdff$146111 ($dff) from module lsc1_packet_frontend (D = $procmux$141663_Y, Q = \alu_operand_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$147684 ($sdff) from module lsc1_packet_frontend (D = $procmux$141642_Y, Q = \alu_operand_b). +Adding SRST signal on $procdff$146110 ($dff) from module lsc1_packet_frontend (D = $procmux$141804_Y, Q = \alu_operand_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$147764 ($sdff) from module lsc1_packet_frontend (D = $procmux$141783_Y, Q = \alu_operand_a). +Adding SRST signal on $procdff$146109 ($dff) from module lsc1_packet_frontend (D = $procmux$141945_Y, Q = \alu_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$147844 ($sdff) from module lsc1_packet_frontend (D = $procmux$141924_Y, Q = \alu_operation). +Adding SRST signal on $procdff$146108 ($dff) from module lsc1_packet_frontend (D = $procmux$139605_Y, Q = \alu_start, rval = 1'0). +Adding SRST signal on $procdff$146107 ($dff) from module lsc1_packet_frontend (D = $procmux$142116_Y, Q = \compute_state, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$147929 ($sdff) from module lsc1_packet_frontend (D = $procmux$142116_Y, Q = \compute_state). +Adding SRST signal on $procdff$146106 ($dff) from module lsc1_packet_frontend (D = $procmux$142238_Y, Q = \capture_result_crc, rval = 1'0). +Adding SRST signal on $procdff$146105 ($dff) from module lsc1_packet_frontend (D = $procmux$142400_Y, Q = \tx_payload, rval = 544'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148006 ($sdff) from module lsc1_packet_frontend (D = $procmux$142397_Y, Q = \tx_payload). +Adding SRST signal on $procdff$146104 ($dff) from module lsc1_packet_frontend (D = $procmux$142559_Y, Q = \tx_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148028 ($sdff) from module lsc1_packet_frontend (D = $procmux$142556_Y, Q = \tx_length). +Adding SRST signal on $procdff$146103 ($dff) from module lsc1_packet_frontend (D = $procmux$142718_Y, Q = \tx_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$148046 ($sdff) from module lsc1_packet_frontend (D = $procmux$142715_Y, Q = \tx_status). +Adding SRST signal on $procdff$146102 ($dff) from module lsc1_packet_frontend (D = $procmux$139763_Y, Q = \tx_start, rval = 1'0). +Adding SRST signal on $procdff$146101 ($dff) from module lsc1_packet_frontend (D = $procmux$142877_Y, Q = \fault, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$148069 ($sdff) from module lsc1_packet_frontend (D = $procmux$142877_Y, Q = \fault). +Adding SRST signal on $procdff$146100 ($dff) from module lsc1_packet_frontend (D = $procmux$139319_Y, Q = \done_pulse, rval = 1'0). +Adding SRST signal on $flatten\adapter.$procdff$146276 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143480_Y, Q = \adapter.state, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$148096 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143480_Y, Q = \adapter.state). +Adding SRST signal on $flatten\adapter.$procdff$146277 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143306_Y, Q = \adapter.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\adapter.$procdff$146278 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143468_Y, Q = \adapter.fault, rval = 1'0). +Adding SRST signal on $flatten\adapter.$procdff$146279 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.$2$lookahead\result$670[127:0]$693, Q = \adapter.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding SRST signal on $flatten\adapter.$procdff$146280 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143447_Y, Q = \adapter.saved_operation, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$148125 ($sdff) from module lsc1_packet_frontend (D = \adapter.operation, Q = \adapter.saved_operation). +Adding SRST signal on $flatten\adapter.$procdff$146281 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143431_Y, Q = \adapter.saved_a, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148131 ($sdff) from module lsc1_packet_frontend (D = \adapter.operand_a, Q = \adapter.saved_a). +Adding SRST signal on $flatten\adapter.$procdff$146282 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143415_Y, Q = \adapter.saved_b, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148137 ($sdff) from module lsc1_packet_frontend (D = \adapter.operand_b, Q = \adapter.saved_b). +Adding SRST signal on $flatten\adapter.$procdff$146283 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143389_Y, Q = \adapter.payload_index, rval = 6'000000). +Adding EN signal on $auto$ff.cc:266:slice$148143 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143389_Y, Q = \adapter.payload_index). +Adding SRST signal on $flatten\adapter.$procdff$146284 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143358_Y, Q = \adapter.result_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:266:slice$148161 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.$procmux$143358_Y, Q = \adapter.result_index). +Adding SRST signal on $flatten\adapter.\datapath.\multiplier.\impl.$procdff$146297 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.\multiplier.\impl.$procmux$144127_Y, Q = \adapter.datapath.multiplier.impl.accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148177 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.\multiplier.\impl.$procmux$144127_Y, Q = \adapter.datapath.multiplier.impl.accumulator). +Adding SRST signal on $flatten\adapter.\datapath.\multiplier.\impl.$procdff$146296 ($dff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.\multiplier.\impl.$procmux$144142_Y, Q = \adapter.datapath.multiplier.impl.a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148189 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.\multiplier.\impl.$procmux$144142_Y, Q = \adapter.datapath.multiplier.impl.a_shift). +Adding SRST signal on $flatten\field_encoder.$procdff$146263 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$143068_Y, Q = \field_encoder.busy, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$148201 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$143068_Y, Q = \field_encoder.busy). +Adding SRST signal on $flatten\field_encoder.$procdff$146264 ($dff) from module lsc1_packet_frontend (D = $flatten\field_encoder.$procmux$142947_Y, Q = \field_encoder.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\transmitter.$procdff$146305 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$144917_Y, Q = \transmitter.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\transmitter.$procdff$146306 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$145081_Y, Q = \transmitter.payload_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$148219 ($sdff) from module lsc1_packet_frontend (D = $flatten\transmitter.$ternary$asic_core/rtl/lsc1_packet_tx.sv:92$519_Y, Q = \transmitter.payload_crc). +Adding SRST signal on $flatten\transmitter.$procdff$146307 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$145066_Y, Q = \transmitter.active, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$148225 ($sdff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$145066_Y, Q = \transmitter.active). +Adding SRST signal on $flatten\transmitter.$procdff$146308 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$145051_Y, Q = \transmitter.index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148233 ($sdff) from module lsc1_packet_frontend (D = $flatten\transmitter.$add$asic_core/rtl/lsc1_packet_tx.sv:100$522_Y, Q = \transmitter.index). +Adding SRST signal on $flatten\transmitter.$procdff$146309 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$145042_Y, Q = \transmitter.saved_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148241 ($sdff) from module lsc1_packet_frontend (D = \transmitter.payload_length, Q = \transmitter.saved_length). +Adding SRST signal on $flatten\transmitter.$procdff$146310 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$145036_Y, Q = \transmitter.saved_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$148243 ($sdff) from module lsc1_packet_frontend (D = \transmitter.status, Q = \transmitter.saved_status). +Adding SRST signal on $flatten\transmitter.$procdff$146311 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$145030_Y, Q = \transmitter.saved_payload, rval = 544'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148245 ($sdff) from module lsc1_packet_frontend (D = \transmitter.payload, Q = \transmitter.saved_payload). +Adding SRST signal on $flatten\transmitter.$procdff$146312 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$145021_Y, Q = \transmitter.saved_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$148247 ($sdff) from module lsc1_packet_frontend (D = $flatten\transmitter.$not$asic_core/rtl/lsc1_packet_tx.sv:91$483_Y, Q = \transmitter.saved_crc). +Adding SRST signal on $flatten\transmitter.$procdff$146313 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$145006_Y, Q = \transmitter.envelope_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$148253 ($sdff) from module lsc1_packet_frontend (D = $flatten\transmitter.$ternary$asic_core/rtl/lsc1_packet_tx.sv:36$398_Y, Q = \transmitter.envelope_crc_work). +Adding SRST signal on $flatten\transmitter.$procdff$146314 ($dff) from module lsc1_packet_frontend (D = $flatten\transmitter.$procmux$144994_Y, Q = \transmitter.payload_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$148259 ($sdff) from module lsc1_packet_frontend (D = $flatten\transmitter.$ternary$asic_core/rtl/lsc1_packet_tx.sv:36$437_Y, Q = \transmitter.payload_crc_work). +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$146853 ($sdffe) from module lsc1_packet_frontend. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$146853 ($sdffe) from module lsc1_packet_frontend. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$146853 ($sdffe) from module lsc1_packet_frontend. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$146853 ($sdffe) from module lsc1_packet_frontend. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$146853 ($sdffe) from module lsc1_packet_frontend. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$146853 ($sdffe) from module lsc1_packet_frontend. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$146853 ($sdffe) from module lsc1_packet_frontend. + +13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend.. +Removed 425 unused cells and 18296 unused wires. + + +13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend. + + +13.9. Rerunning OPT passes. (Maybe there is more to do..) + +13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143529. + dead port 2/2 on $mux $flatten\field_encoder.\multiplier.$procmux$143529. + dead port 1/3 on $pmux $flatten\field_encoder.\multiplier.$procmux$143543. + dead port 2/3 on $pmux $flatten\field_encoder.\multiplier.$procmux$143543. +Removed 4 multiplexer ports. + + +13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend. + New ctrl vector for $pmux cell $flatten\adapter.$procmux$143190: { $flatten\adapter.$procmux$143182_CMP $auto$opt_reduce.cc:134:opt_pmux$148267 } + New ctrl vector for $pmux cell $flatten\adapter.\datapath.$procmux$143647: { $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$588_Y $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $flatten\adapter.\datapath.$procmux$143667_CMP $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:85$570_Y $auto$opt_reduce.cc:134:opt_pmux$148269 $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:211$607_Y } + New ctrl vector for $pmux cell $flatten\adapter.\datapath.$procmux$143725: { $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$588_Y $flatten\adapter.\datapath.$procmux$143604_CMP $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:207$592_Y $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $flatten\adapter.\datapath.$procmux$143667_CMP $flatten\adapter.\datapath.$procmux$143601_CMP $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:85$570_Y $auto$opt_reduce.cc:134:opt_pmux$148271 $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:211$607_Y $flatten\adapter.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:212$611_Y } + New ctrl vector for $pmux cell $flatten\field_encoder.\multiplier.$procmux$143190: { $flatten\field_encoder.\multiplier.$procmux$143182_CMP $auto$opt_reduce.cc:134:opt_pmux$148273 } + New ctrl vector for $pmux cell $flatten\field_encoder.\multiplier.\datapath.$procmux$143647: { $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$588_Y $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $flatten\field_encoder.\multiplier.\datapath.$procmux$143667_CMP $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:85$570_Y $auto$opt_reduce.cc:134:opt_pmux$148275 $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:211$607_Y } + New ctrl vector for $pmux cell $flatten\field_encoder.\multiplier.\datapath.$procmux$143725: { $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:205$588_Y $flatten\field_encoder.\multiplier.\datapath.$procmux$143604_CMP $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:207$592_Y $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:209$599_Y $flatten\field_encoder.\multiplier.\datapath.$procmux$143667_CMP $flatten\field_encoder.\multiplier.\datapath.$procmux$143601_CMP $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:85$570_Y $auto$opt_reduce.cc:134:opt_pmux$148277 $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:211$607_Y $flatten\field_encoder.\multiplier.\datapath.$eq$asic_core/rtl/leanvm_b_stream_alu.sv:212$611_Y } + Optimizing cells in module \lsc1_packet_frontend. +Performed a total of 6 changes. + +13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend'. + +Removed a total of 489 cells. + +13.13. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $auto$ff.cc:266:slice$146563 ($sdff) from module lsc1_packet_frontend (D = $flatten\receiver.$3$lookahead\frame_payload$22[2047:0]$99, Q = \receiver.frame_payload). +Adding SRST signal on $auto$ff.cc:266:slice$148124 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.$3$lookahead\result$670[127:0]$702, Q = \adapter.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$148287 ($sdff) from module lsc1_packet_frontend (D = $flatten\adapter.$3$lookahead\result$670[127:0]$702, Q = \adapter.result). +Adding EN signal on $auto$ff.cc:266:slice$147030 ($dffe) from module lsc1_packet_frontend (D = $3\n_writes[31:0], Q = \n_writes). +Adding EN signal on $auto$ff.cc:266:slice$147029 ($dffe) from module lsc1_packet_frontend (D = $3\n_deferred[31:0], Q = \n_deferred). +Adding EN signal on $auto$ff.cc:266:slice$147028 ($dffe) from module lsc1_packet_frontend (D = $17\txn_id[31:0], Q = \txn_id). +Adding EN signal on $auto$ff.cc:266:slice$147027 ($dffe) from module lsc1_packet_frontend (D = \receiver.frame_payload [63:32], Q = \pc). +Adding EN signal on $auto$ff.cc:266:slice$147026 ($dffe) from module lsc1_packet_frontend (D = \receiver.frame_payload [95:64], Q = \fp). +Adding EN signal on $auto$ff.cc:266:slice$147025 ($dffe) from module lsc1_packet_frontend (D = $28\addr_a[31:0], Q = \addr_a). +Adding EN signal on $auto$ff.cc:266:slice$147024 ($dffe) from module lsc1_packet_frontend (D = $28\addr_b[31:0], Q = \addr_b). +Adding EN signal on $auto$ff.cc:266:slice$147023 ($dffe) from module lsc1_packet_frontend (D = $28\addr_c[31:0], Q = \addr_c). +Adding EN signal on $auto$ff.cc:266:slice$147022 ($dffe) from module lsc1_packet_frontend (D = \receiver.frame_payload [655:624], Q = \proposed_pc). +Adding EN signal on $auto$ff.cc:266:slice$147021 ($dffe) from module lsc1_packet_frontend (D = \receiver.frame_payload [687:656], Q = \proposed_fp). +Adding EN signal on $auto$ff.cc:266:slice$147020 ($dffe) from module lsc1_packet_frontend (D = $6\next_pc_value[31:0], Q = \next_pc_value). +Adding EN signal on $auto$ff.cc:266:slice$147019 ($dffe) from module lsc1_packet_frontend (D = $6\next_fp_value[31:0], Q = \next_fp_value). +Adding EN signal on $auto$ff.cc:266:slice$147018 ($dffe) from module lsc1_packet_frontend (D = $3\deferred_target[31:0], Q = \deferred_target). +Adding EN signal on $auto$ff.cc:266:slice$147017 ($dffe) from module lsc1_packet_frontend (D = $3\deferred_local[31:0], Q = \deferred_local). +Adding EN signal on $auto$ff.cc:266:slice$147016 ($dffe) from module lsc1_packet_frontend (D = \receiver.frame_payload [103:96], Q = \profile). +Adding EN signal on $auto$ff.cc:266:slice$147015 ($dffe) from module lsc1_packet_frontend (D = $28\pres_a[7:0], Q = \pres_a). +Adding EN signal on $auto$ff.cc:266:slice$147014 ($dffe) from module lsc1_packet_frontend (D = $29\pres_b[7:0], Q = \pres_b). +Adding EN signal on $auto$ff.cc:266:slice$147013 ($dffe) from module lsc1_packet_frontend (D = $29\pres_c[7:0], Q = \pres_c). +Adding EN signal on $auto$ff.cc:266:slice$147012 ($dffe) from module lsc1_packet_frontend (D = $28\val_a[127:0], Q = \val_a). +Adding EN signal on $auto$ff.cc:266:slice$147011 ($dffe) from module lsc1_packet_frontend (D = $29\val_b[127:0], Q = \val_b). +Adding EN signal on $auto$ff.cc:266:slice$147010 ($dffe) from module lsc1_packet_frontend (D = $29\val_c[127:0], Q = \val_c). +Adding EN signal on $auto$ff.cc:266:slice$147009 ($dffe) from module lsc1_packet_frontend (D = $30\inv_value[127:0], Q = \inv_value). +Adding EN signal on $auto$ff.cc:266:slice$147008 ($dffe) from module lsc1_packet_frontend (D = $28\result_value[127:0], Q = \result_value). +Adding EN signal on $auto$ff.cc:266:slice$147007 ($dffe) from module lsc1_packet_frontend (D = $9\solved_a[127:0], Q = \solved_a). +Adding EN signal on $auto$ff.cc:266:slice$147006 ($dffe) from module lsc1_packet_frontend (D = $9\solved_b[127:0], Q = \solved_b). +Adding EN signal on $auto$ff.cc:266:slice$147005 ($dffe) from module lsc1_packet_frontend (D = $3\write_address[31:0], Q = \write_address). +Adding EN signal on $auto$ff.cc:266:slice$147004 ($dffe) from module lsc1_packet_frontend (D = $3\write_value[127:0], Q = \write_value). +Adding EN signal on $auto$ff.cc:266:slice$146956 ($sdffe) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143647_Y, Q = \field_encoder.multiplier.datapath.byte_index). +Adding EN signal on $auto$ff.cc:266:slice$146918 ($sdffe) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.\datapath.$procmux$143725_Y, Q = \field_encoder.multiplier.datapath.state). +Adding SRST signal on $auto$ff.cc:266:slice$146858 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$3$lookahead\result$670[127:0]$702, Q = \field_encoder.multiplier.result, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$149846 ($sdff) from module lsc1_packet_frontend (D = $flatten\field_encoder.\multiplier.$3$lookahead\result$670[127:0]$702, Q = \field_encoder.multiplier.result). +Adding EN signal on $auto$ff.cc:266:slice$146762 ($sdffe) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143725_Y, Q = \adapter.datapath.state). +Adding EN signal on $auto$ff.cc:266:slice$146730 ($sdffe) from module lsc1_packet_frontend (D = $flatten\adapter.\datapath.$procmux$143647_Y, Q = \adapter.datapath.byte_index). + +13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend.. +Removed 476 unused cells and 974 unused wires. + + +13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend. + + +13.16. Rerunning OPT passes. (Maybe there is more to do..) + +13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend. + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$149873: { $auto$opt_dff.cc:194:make_patterns_logic$146700 $auto$opt_dff.cc:194:make_patterns_logic$146706 $auto$opt_dff.cc:194:make_patterns_logic$146731 $auto$opt_dff.cc:194:make_patterns_logic$146733 $auto$opt_dff.cc:194:make_patterns_logic$146737 $auto$opt_dff.cc:194:make_patterns_logic$149870 $auto$opt_dff.cc:194:make_patterns_logic$149868 $auto$opt_dff.cc:194:make_patterns_logic$146741 $auto$opt_dff.cc:194:make_patterns_logic$146743 } + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$149845: { $auto$opt_dff.cc:194:make_patterns_logic$146919 $auto$opt_dff.cc:194:make_patterns_logic$146921 $auto$opt_dff.cc:194:make_patterns_logic$146923 $auto$opt_dff.cc:194:make_patterns_logic$146925 $auto$opt_dff.cc:194:make_patterns_logic$146927 $auto$opt_dff.cc:194:make_patterns_logic$146929 $auto$opt_dff.cc:194:make_patterns_logic$146931 $auto$opt_dff.cc:194:make_patterns_logic$146933 $auto$opt_dff.cc:194:make_patterns_logic$146935 $auto$opt_dff.cc:194:make_patterns_logic$146937 $auto$opt_dff.cc:194:make_patterns_logic$149842 $auto$opt_dff.cc:194:make_patterns_logic$149840 } + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$149838: { $auto$opt_dff.cc:194:make_patterns_logic$146921 $auto$opt_dff.cc:194:make_patterns_logic$146925 $auto$opt_dff.cc:194:make_patterns_logic$146935 $auto$opt_dff.cc:194:make_patterns_logic$146959 $auto$opt_dff.cc:194:make_patterns_logic$146961 $auto$opt_dff.cc:194:make_patterns_logic$146967 $auto$opt_dff.cc:194:make_patterns_logic$149835 $auto$opt_dff.cc:194:make_patterns_logic$149833 $auto$opt_dff.cc:194:make_patterns_logic$146969 } + New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$149866: { $auto$opt_dff.cc:194:make_patterns_logic$146702 $auto$opt_dff.cc:194:make_patterns_logic$146704 $auto$opt_dff.cc:194:make_patterns_logic$146731 $auto$opt_dff.cc:194:make_patterns_logic$146737 $auto$opt_dff.cc:194:make_patterns_logic$146763 $auto$opt_dff.cc:194:make_patterns_logic$146769 $auto$opt_dff.cc:194:make_patterns_logic$146777 $auto$opt_dff.cc:194:make_patterns_logic$146779 $auto$opt_dff.cc:194:make_patterns_logic$149863 $auto$opt_dff.cc:194:make_patterns_logic$149861 $auto$opt_dff.cc:194:make_patterns_logic$146743 $auto$opt_dff.cc:194:make_patterns_logic$146767 } + Optimizing cells in module \lsc1_packet_frontend. +Performed a total of 4 changes. + +13.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend'. + +Removed a total of 752 cells. + +13.20. Executing OPT_DFF pass (perform DFF optimizations). + +13.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend.. +Removed 4 unused cells and 756 unused wires. + + +13.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend. + +13.23. Rerunning OPT passes. (Maybe there is more to do..) + +13.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +13.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend. +Performed a total of 0 changes. + +13.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend'. +Removed a total of 0 cells. + +13.27. Executing OPT_DFF pass (perform DFF optimizations). + +13.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend.. + +13.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend. + +13.30. Finished OPT passes. (There is nothing left to do.) + +14. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_frontend... +Found and reported 0 problems. + +15. Executing Verilog backend. + +15.1. Executing BMUXMAP pass. + +15.2. Executing DEMUXMAP pass. +Dumping module `\lsc1_packet_frontend'. + +16. Printing statistics. + +=== lsc1_packet_frontend === + + Number of wires: 3035 + Number of wire bits: 110312 + Number of public wires: 299 + Number of public wire bits: 11777 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2915 + $add 19 + $and 3 + $dffe 27 + $eq 105 + $ge 7 + $gt 17 + $le 2 + $logic_and 95 + $logic_not 37 + $logic_or 77 + $lt 5 + $mux 1810 + $ne 286 + $neg 3 + $not 84 + $or 3 + $pmux 49 + $reduce_and 72 + $reduce_bool 58 + $reduce_or 26 + $sdff 15 + $sdffe 82 + $shift 6 + $shiftx 8 + $sub 8 + $xor 11 + +End of script. Logfile hash: c110c6033e, CPU: user 441.80s system 5.96s, MEM: 3572.64 MB peak +Yosys 0.33 (git sha1 2584903a060) +Time spent: 85% 1x proc_mux (381 sec), 2% 6x opt_expr (13 sec), ... diff --git a/results/b2-capability-contract-20260728/netlist_900.status b/results/b2-capability-contract-20260728/netlist_900.status new file mode 100644 index 0000000..65273e1 --- /dev/null +++ b/results/b2-capability-contract-20260728/netlist_900.status @@ -0,0 +1,2 @@ +exit=0 +duration_ms=447965 diff --git a/results/b2-capability-contract-20260728/python_full.command b/results/b2-capability-contract-20260728/python_full.command new file mode 100644 index 0000000..d3289a7 --- /dev/null +++ b/results/b2-capability-contract-20260728/python_full.command @@ -0,0 +1 @@ +PATH=/root/.cargo/bin:$PATH CARGO_HOME=/root/.cargo RUSTUP_HOME=/root/.rustup timeout 600s make python diff --git a/results/b2-capability-contract-20260728/python_full.log b/results/b2-capability-contract-20260728/python_full.log new file mode 100644 index 0000000..e686ec4 --- /dev/null +++ b/results/b2-capability-contract-20260728/python_full.log @@ -0,0 +1,302 @@ +PYTHONDONTWRITEBYTECODE=1 python3 -m unittest discover -s sim -v +test_exchange_failure_preserves_the_complete_old_archive (test_atomic_publish.AtomicPublishTests.test_exchange_failure_preserves_the_complete_old_archive) ... ok +test_shared_builds_lock_before_taking_their_snapshot (test_atomic_publish.AtomicPublishTests.test_shared_builds_lock_before_taking_their_snapshot) ... ok +test_success_replaces_the_complete_directory (test_atomic_publish.AtomicPublishTests.test_success_replaces_the_complete_directory) ... ok +test_termination_before_exchange_preserves_old_archive (test_atomic_publish.AtomicPublishTests.test_termination_before_exchange_preserves_old_archive) ... ok +test_compute_requires_the_exact_accepted_request (test_blake3_service.AdapterAndModelTests.test_compute_requires_the_exact_accepted_request) ... ok +test_duplicate_response_is_stale_after_result_acceptance (test_blake3_service.AdapterAndModelTests.test_duplicate_response_is_stale_after_result_acceptance) ... ok +test_infrastructure_retry_is_bounded_and_semantic_failure_is_not_retried (test_blake3_service.AdapterAndModelTests.test_infrastructure_retry_is_bounded_and_semantic_failure_is_not_retried) ... ok +test_reset_never_reuses_an_earlier_epoch (test_blake3_service.AdapterAndModelTests.test_reset_never_reuses_an_earlier_epoch) ... ok +test_reset_rejects_invalid_epoch_without_changing_state (test_blake3_service.AdapterAndModelTests.test_reset_rejects_invalid_epoch_without_changing_state) ... ok +test_retry_requires_identical_operands_and_abort_tombstones_key (test_blake3_service.AdapterAndModelTests.test_retry_requires_identical_operands_and_abort_tombstones_key) ... ok +test_stalls_do_not_change_service_or_result (test_blake3_service.AdapterAndModelTests.test_stalls_do_not_change_service_or_result) ... ok +test_wrong_binding_stale_epoch_abort_and_reset_are_rejected (test_blake3_service.AdapterAndModelTests.test_wrong_binding_stale_epoch_abort_and_reset_are_rejected) ... ok +test_wrong_digest_conflict_discards_but_commit_is_atomic (test_blake3_service.AdapterAndModelTests.test_wrong_digest_conflict_discards_but_commit_is_atomic) ... ok +test_host_compression_matches_official_low_level_library (test_blake3_service.OfficialDifferentialTests.test_host_compression_matches_official_low_level_library) ... ok +test_documented_direction_preserves_current_rtl_boundary (test_blake3_service.ScatterGatherDesignContractTests.test_documented_direction_preserves_current_rtl_boundary) ... ok +test_keys_and_direct_responses_enforce_schema_ranges (test_blake3_service.SchemaTests.test_keys_and_direct_responses_enforce_schema_ranges) ... ok +test_malformed_fields_are_semantic_failures (test_blake3_service.SchemaTests.test_malformed_fields_are_semantic_failures) ... ok +test_metadata_is_rejected_before_compression (test_blake3_service.SchemaTests.test_metadata_is_rejected_before_compression) ... ok +test_schema_round_trips_exactly (test_blake3_service.SchemaTests.test_schema_round_trips_exactly) ... ok +test_coverage_contract (test_conformance_corpus.ConformanceCorpusTests.test_coverage_contract) ... ok +test_generator_is_byte_reproducible (test_conformance_corpus.ConformanceCorpusTests.test_generator_is_byte_reproducible) ... ok +test_ids_fingerprints_and_required_records (test_conformance_corpus.ConformanceCorpusTests.test_ids_fingerprints_and_required_records) ... ok +test_protocol_only_scope_is_explicit (test_conformance_corpus.ConformanceCorpusTests.test_protocol_only_scope_is_explicit) ... ok +test_raw_exchanges_replay (test_conformance_corpus.ConformanceCorpusTests.test_raw_exchanges_replay) ... ok +test_reset_case_records_the_actual_pre_edge_state (test_conformance_corpus.ConformanceCorpusTests.test_reset_case_records_the_actual_pre_edge_state) ... ok +test_commands (test_cycle_model.RandomBackpressureTests.test_commands) ... ok +test_exact_no_stall_latencies (test_cycle_model.RandomBackpressureTests.test_exact_no_stall_latencies) ... ok +test_invalid_command (test_cycle_model.RandomBackpressureTests.test_invalid_command) ... ok +test_a_malformed_field_operand_is_refused (test_host_runtime.AdapterTests.test_a_malformed_field_operand_is_refused) ... ok +test_a_mislabelled_slot_is_refused (test_host_runtime.AdapterTests.test_a_mislabelled_slot_is_refused) ... ok +test_a_non_frozen_upstream_is_refused (test_host_runtime.AdapterTests.test_a_non_frozen_upstream_is_refused) ... ok +test_a_non_power_of_two_bytecode_is_refused (test_host_runtime.AdapterTests.test_a_non_power_of_two_bytecode_is_refused) ... ok +test_an_unknown_opcode_is_refused (test_host_runtime.AdapterTests.test_an_unknown_opcode_is_refused) ... ok +test_host_package_imports_with_deferred_annotations_policy (test_host_runtime.AdapterTests.test_host_package_imports_with_deferred_annotations_policy) ... ok +test_malformed_initial_scalars_are_adapter_errors (test_host_runtime.AdapterTests.test_malformed_initial_scalars_are_adapter_errors) ... ok +test_malformed_u32_operands_are_adapter_errors (test_host_runtime.AdapterTests.test_malformed_u32_operands_are_adapter_errors) ... ok +test_missing_and_compound_operands_are_adapter_errors (test_host_runtime.AdapterTests.test_missing_and_compound_operands_are_adapter_errors) ... ok +test_pc0_outside_the_bytecode_is_refused (test_host_runtime.AdapterTests.test_pc0_outside_the_bytecode_is_refused) ... ok +test_pc_outside_the_program_is_refused (test_host_runtime.AdapterTests.test_pc_outside_the_program_is_refused) ... ok +test_the_checked_in_artifact_loads (test_host_runtime.AdapterTests.test_the_checked_in_artifact_loads) ... ok +test_wrong_schema_is_refused (test_host_runtime.AdapterTests.test_wrong_schema_is_refused) ... ok +test_complete_program_cycles_match_the_frozen_run (test_host_runtime.FrozenUpstreamComparisonTests.test_complete_program_cycles_match_the_frozen_run) ... ok +test_complete_program_is_a_full_match (test_host_runtime.FrozenUpstreamComparisonTests.test_complete_program_is_a_full_match) ... ok +test_halted_run_missing_an_upstream_cell_is_a_mismatch (test_host_runtime.FrozenUpstreamComparisonTests.test_halted_run_missing_an_upstream_cell_is_a_mismatch) ... ok +test_halted_sparse_memory_treats_unwritten_cells_as_zero (test_host_runtime.FrozenUpstreamComparisonTests.test_halted_sparse_memory_treats_unwritten_cells_as_zero) ... ok +test_host_writes_agree_with_the_frozen_final_memory (test_host_runtime.FrozenUpstreamComparisonTests.test_host_writes_agree_with_the_frozen_final_memory) ... ok +test_live_probe_must_reproduce_recorded_execution (test_host_runtime.FrozenUpstreamComparisonTests.test_live_probe_must_reproduce_recorded_execution) ... ok +test_out_of_tree_artifact_fails_with_a_clean_domain_error (test_host_runtime.FrozenUpstreamComparisonTests.test_out_of_tree_artifact_fails_with_a_clean_domain_error) ... ok +test_step_limit_cannot_be_reported_as_a_match (test_host_runtime.FrozenUpstreamComparisonTests.test_step_limit_cannot_be_reported_as_a_match) ... ok +test_the_artifact_records_the_frozen_commit_and_its_public_interface_limits (test_host_runtime.FrozenUpstreamComparisonTests.test_the_artifact_records_the_frozen_commit_and_its_public_interface_limits) ... ok +test_the_host_covers_every_cell_the_frozen_run_touched (test_host_runtime.FrozenUpstreamComparisonTests.test_the_host_covers_every_cell_the_frozen_run_touched) ... ok +test_deferred_equalities_propagate_and_detect_contradiction (test_host_runtime.HostMemoryTests.test_deferred_equalities_propagate_and_detect_contradiction) ... ok +test_deferred_equalities_propagate_to_a_fixed_point (test_host_runtime.HostMemoryTests.test_deferred_equalities_propagate_to_a_fixed_point) ... ok +test_field_inverse_round_trips (test_host_runtime.HostMemoryTests.test_field_inverse_round_trips) ... ok +test_public_input_seeds_the_first_two_cells (test_host_runtime.HostMemoryTests.test_public_input_seeds_the_first_two_cells) ... ok +test_write_once_accepts_the_same_value_and_rejects_a_different_one (test_host_runtime.HostMemoryTests.test_write_once_accepts_the_same_value_and_rejects_a_different_one) ... ok +test_a_non_g_power_has_no_index (test_host_runtime.PointerMapTests.test_a_non_g_power_has_no_index) ... ok +test_encode_and_reverse_agree (test_host_runtime.PointerMapTests.test_encode_and_reverse_agree) ... ok +test_index_beyond_the_v1_window_is_refused (test_host_runtime.PointerMapTests.test_index_beyond_the_v1_window_is_refused) ... ok +test_a_result_for_another_transaction_is_refused (test_host_runtime.ResultPayloadTests.test_a_result_for_another_transaction_is_refused) ... ok +test_a_truncated_payload_is_refused (test_host_runtime.ResultPayloadTests.test_a_truncated_payload_is_refused) ... ok +test_decode_matches_the_endpoint_encoding (test_host_runtime.ResultPayloadTests.test_decode_matches_the_endpoint_encoding) ... ok +test_poisoned_result_wrong_txn_id_is_protocol_violation (test_host_runtime.ResultPayloadTests.test_poisoned_result_wrong_txn_id_is_protocol_violation) ... ok +test_poisoned_stale_frame_regressions (test_host_runtime.ResultPayloadTests.test_poisoned_stale_frame_regressions) +Poisoned or stale frames (wrong txn, tampered CRC) must be refused; F1 binding preserved. ... ok +test_a_corrupted_response_is_not_reported_as_a_preparation_fault (test_host_runtime.RuntimeTests.test_a_corrupted_response_is_not_reported_as_a_preparation_fault) ... ok +test_a_deferred_local_outside_the_frame_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_a_deferred_local_outside_the_frame_is_refused_before_retire_is_sent) ... ok +test_a_deferred_target_outside_the_frame_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_a_deferred_target_outside_the_frame_is_refused_before_retire_is_sent) ... ok +test_a_duplicate_retire_against_the_real_endpoint_is_refused (test_host_runtime.RuntimeTests.test_a_duplicate_retire_against_the_real_endpoint_is_refused) ... ok +test_a_fault_bound_to_another_transaction_is_a_protocol_violation (test_host_runtime.RuntimeTests.test_a_fault_bound_to_another_transaction_is_a_protocol_violation) ... ok +test_a_fault_payload_of_the_wrong_size_is_a_protocol_violation (test_host_runtime.RuntimeTests.test_a_fault_payload_of_the_wrong_size_is_a_protocol_violation) ... ok +test_a_frame_level_retire_rejection_is_a_protocol_violation (test_host_runtime.RuntimeTests.test_a_frame_level_retire_rejection_is_a_protocol_violation) ... ok +test_a_frame_only_instruction_fault_binding_this_txn_is_still_refused (test_host_runtime.RuntimeTests.test_a_frame_only_instruction_fault_binding_this_txn_is_still_refused) ... ok +test_a_non_discarding_retire_fault_binding_this_txn_is_still_refused (test_host_runtime.RuntimeTests.test_a_non_discarding_retire_fault_binding_this_txn_is_still_refused) ... ok +test_a_non_fault_status_is_not_recorded_as_a_fault (test_host_runtime.RuntimeTests.test_a_non_fault_status_is_not_recorded_as_a_fault) ... ok +test_a_non_overflowing_address_is_not_a_preparation_fault (test_host_runtime.RuntimeTests.test_a_non_overflowing_address_is_not_a_preparation_fault) ... ok +test_a_non_retired_non_fault_status_is_not_recorded_as_a_fault (test_host_runtime.RuntimeTests.test_a_non_retired_non_fault_status_is_not_recorded_as_a_fault) ... ok +test_a_retire_fault_payload_of_the_wrong_size_is_a_protocol_violation (test_host_runtime.RuntimeTests.test_a_retire_fault_payload_of_the_wrong_size_is_a_protocol_violation) ... ok +test_a_well_formed_fault_is_still_attributed_to_the_step (test_host_runtime.RuntimeTests.test_a_well_formed_fault_is_still_attributed_to_the_step) ... ok +test_a_well_formed_retire_fault_is_still_attributed_to_the_step (test_host_runtime.RuntimeTests.test_a_well_formed_retire_fault_is_still_attributed_to_the_step) ... ok +test_a_write_conflict_is_reported_as_a_fault_not_applied (test_host_runtime.RuntimeTests.test_a_write_conflict_is_reported_as_a_fault_not_applied) ... ok +test_a_write_once_conflict_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_a_write_once_conflict_is_refused_before_retire_is_sent) ... ok +test_a_write_outside_the_frame_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_a_write_outside_the_frame_is_refused_before_retire_is_sent) ... ok +test_an_acceptable_write_batch_is_still_retired_and_applied (test_host_runtime.RuntimeTests.test_an_acceptable_write_batch_is_still_retired_and_applied) +Guards the two tests above from passing because RETIRE never happens. ... ok +test_an_access_outside_the_frame_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_an_access_outside_the_frame_is_refused_before_retire_is_sent) ... ok +test_an_idle_guard_fault_is_still_attributed_to_the_step (test_host_runtime.RuntimeTests.test_an_idle_guard_fault_is_still_attributed_to_the_step) ... ok +test_an_in_frame_deferred_pair_is_still_retired_and_recorded (test_host_runtime.RuntimeTests.test_an_in_frame_deferred_pair_is_still_retired_and_recorded) +Guards the two tests above from passing because RETIRE never happens. ... ok +test_an_invalid_deferred_equality_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_an_invalid_deferred_equality_is_refused_before_retire_is_sent) ... ok +test_an_overflowing_effective_address_is_a_fault_terminal (test_host_runtime.RuntimeTests.test_an_overflowing_effective_address_is_a_fault_terminal) ... ok +test_arbitrary_rx_tx_stalls_and_backpressure (test_host_runtime.RuntimeTests.test_arbitrary_rx_tx_stalls_and_backpressure) +Full transaction loop under arbitrary permitted lane-gap patterns. ... ok +test_conflicting_duplicate_writes_are_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_conflicting_duplicate_writes_are_refused_before_retire_is_sent) ... ok +test_deref_modes_are_prepared_with_host_pointer_resolution (test_host_runtime.RuntimeTests.test_deref_modes_are_prepared_with_host_pointer_resolution) ... ok +test_every_real_endpoint_effect_stays_inside_the_frame (test_host_runtime.RuntimeTests.test_every_real_endpoint_effect_stays_inside_the_frame) ... ok +test_forward_only_refuses_the_same_back_solve (test_host_runtime.RuntimeTests.test_forward_only_refuses_the_same_back_solve) ... ok +test_jump_taken_and_not_taken_are_host_proposed_and_verified (test_host_runtime.RuntimeTests.test_jump_taken_and_not_taken_are_host_proposed_and_verified) ... ok +test_mul_back_solves_from_the_host_inverse_witness (test_host_runtime.RuntimeTests.test_mul_back_solves_from_the_host_inverse_witness) ... ok +test_multiplying_by_a_known_zero_is_not_given_a_witness (test_host_runtime.RuntimeTests.test_multiplying_by_a_known_zero_is_not_given_a_witness) ... ok +test_negotiate_requires_every_schema_field (test_host_runtime.RuntimeTests.test_negotiate_requires_every_schema_field) ... ok +test_sentinel_requires_zero_frame_pointer (test_host_runtime.RuntimeTests.test_sentinel_requires_zero_frame_pointer) ... ok +test_set_xor_mul_are_driven_end_to_end (test_host_runtime.RuntimeTests.test_set_xor_mul_are_driven_end_to_end) ... ok +test_stale_retire_txn_id_is_protocol_violation (test_host_runtime.RuntimeTests.test_stale_retire_txn_id_is_protocol_violation) ... ok +test_the_real_endpoint_defers_only_inside_the_frame (test_host_runtime.RuntimeTests.test_the_real_endpoint_defers_only_inside_the_frame) ... ok +test_the_step_limit_is_a_terminal_not_a_hang (test_host_runtime.RuntimeTests.test_the_step_limit_is_a_terminal_not_a_hang) ... ok +test_the_step_record_carries_the_whole_comparison_schema (test_host_runtime.RuntimeTests.test_the_step_record_carries_the_whole_comparison_schema) ... ok +test_unintegrated_blake3_stops_the_run_and_says_what_is_missing (test_host_runtime.RuntimeTests.test_unintegrated_blake3_stops_the_run_and_says_what_is_missing) ... ok +test_assumption_table_is_the_model_assumptions (test_lsc1_protocol_doc.DocumentBudgetTests.test_assumption_table_is_the_model_assumptions) ... ok +test_control_frame_table_matches_driven_exchanges (test_lsc1_protocol_doc.DocumentBudgetTests.test_control_frame_table_matches_driven_exchanges) ... ok +test_encode_index_cost_is_stated_as_the_model_computes_it (test_lsc1_protocol_doc.DocumentBudgetTests.test_encode_index_cost_is_stated_as_the_model_computes_it) ... ok +test_fermat_inverse_cost_is_the_square_and_multiply_count (test_lsc1_protocol_doc.DocumentBudgetTests.test_fermat_inverse_cost_is_the_square_and_multiply_count) ... ok +test_per_opcode_budget_tables_match_the_model (test_lsc1_protocol_doc.DocumentBudgetTests.test_per_opcode_budget_tables_match_the_model) ... ok +test_fault_codes_are_all_at_or_above_the_fault_bit (test_lsc1_protocol_doc.DocumentCodeTests.test_fault_codes_are_all_at_or_above_the_fault_bit) ... ok +test_profile_table_is_exactly_the_profile_enum (test_lsc1_protocol_doc.DocumentCodeTests.test_profile_table_is_exactly_the_profile_enum) ... ok +test_state_table_names_exactly_the_model_states (test_lsc1_protocol_doc.DocumentCodeTests.test_state_table_names_exactly_the_model_states) ... ok +test_status_table_is_exactly_the_status_enum (test_lsc1_protocol_doc.DocumentCodeTests.test_status_table_is_exactly_the_status_enum) ... ok +test_contents_list_links_to_every_top_level_section (test_lsc1_protocol_doc.DocumentProvenanceTests.test_contents_list_links_to_every_top_level_section) ... ok +test_document_claims_no_verification_fabrication_validation_or_readiness (test_lsc1_protocol_doc.DocumentProvenanceTests.test_document_claims_no_verification_fabrication_validation_or_readiness) ... ok +test_document_does_not_reference_the_retired_module_name (test_lsc1_protocol_doc.DocumentProvenanceTests.test_document_does_not_reference_the_retired_module_name) ... ok +test_document_names_the_module_and_test_that_generate_its_tables (test_lsc1_protocol_doc.DocumentProvenanceTests.test_document_names_the_module_and_test_that_generate_its_tables) ... ok +test_document_version_matches_the_protocol_version (test_lsc1_protocol_doc.DocumentProvenanceTests.test_document_version_matches_the_protocol_version) ... ok +test_every_internal_link_resolves_to_a_heading (test_lsc1_protocol_doc.DocumentProvenanceTests.test_every_internal_link_resolves_to_a_heading) ... ok +test_every_upstream_citation_is_pinned_to_the_frozen_commit (test_lsc1_protocol_doc.DocumentProvenanceTests.test_every_upstream_citation_is_pinned_to_the_frozen_commit) ... ok +test_no_upstream_citation_points_at_a_moving_branch (test_lsc1_protocol_doc.DocumentProvenanceTests.test_no_upstream_citation_points_at_a_moving_branch) ... ok +test_binary_profile_table_matches_driven_transitions (test_lsc1_protocol_doc.DocumentSemanticsTests.test_binary_profile_table_matches_driven_transitions) ... ok +test_default_profile_after_reset_is_the_one_the_document_names (test_lsc1_protocol_doc.DocumentSemanticsTests.test_default_profile_after_reset_is_the_one_the_document_names) ... ok +test_deref_cell_quadrant_table_matches_driven_transitions (test_lsc1_protocol_doc.DocumentSemanticsTests.test_deref_cell_quadrant_table_matches_driven_transitions) ... ok +test_declared_envelope_overhead_is_what_the_codec_adds (test_lsc1_protocol_doc.DocumentSizeTests.test_declared_envelope_overhead_is_what_the_codec_adds) ... ok +test_deref_modes_share_one_schema_and_one_size (test_lsc1_protocol_doc.DocumentSizeTests.test_deref_modes_share_one_schema_and_one_size) ... ok +test_envelope_prose_matches_the_header_constants (test_lsc1_protocol_doc.DocumentSizeTests.test_envelope_prose_matches_the_header_constants) ... ok +test_every_offset_table_is_cumulative_and_totals_its_declared_size (test_lsc1_protocol_doc.DocumentSizeTests.test_every_offset_table_is_cumulative_and_totals_its_declared_size) +Offsets are not taken on trust: each row must start where the last ended. ... ok +test_every_request_schema_heading_declares_its_payload_size (test_lsc1_protocol_doc.DocumentSizeTests.test_every_request_schema_heading_declares_its_payload_size) ... ok +test_frame_size_table_matches_the_codec (test_lsc1_protocol_doc.DocumentSizeTests.test_frame_size_table_matches_the_codec) ... ok +test_inline_prose_byte_counts_match_the_driven_endpoint (test_lsc1_protocol_doc.DocumentSizeTests.test_inline_prose_byte_counts_match_the_driven_endpoint) +Sizes stated in words drift as easily as sizes stated in tables. ... ok +test_mul_native_schema_extends_the_xor_schema (test_lsc1_protocol_doc.DocumentSizeTests.test_mul_native_schema_extends_the_xor_schema) ... ok +test_negotiate_reply_schema_constants_are_the_model_constants (test_lsc1_protocol_doc.DocumentSizeTests.test_negotiate_reply_schema_constants_are_the_model_constants) ... ok +test_preamble_table_covers_exactly_the_preamble_bytes (test_lsc1_protocol_doc.DocumentSizeTests.test_preamble_table_covers_exactly_the_preamble_bytes) ... ok +test_primitive_type_table_matches_the_codec_widths (test_lsc1_protocol_doc.DocumentSizeTests.test_primitive_type_table_matches_the_codec_widths) ... ok +test_response_schema_headings_match_measured_payloads (test_lsc1_protocol_doc.DocumentSizeTests.test_response_schema_headings_match_measured_payloads) ... ok +test_result_payload_row_widths_match_the_encoder (test_lsc1_protocol_doc.DocumentSizeTests.test_result_payload_row_widths_match_the_encoder) ... ok +test_a_transaction_retires_at_most_once (test_lsc1_protocol_doc.DocumentStateMachineTests.test_a_transaction_retires_at_most_once) ... ok +test_no_fault_moves_committed_pc_fp_or_retire_seq (test_lsc1_protocol_doc.DocumentStateMachineTests.test_no_fault_moves_committed_pc_fp_or_retire_seq) +The §9.1 claim, read at the §8.5 offsets the document publishes. ... ok +test_state_table_legal_opcodes_are_exactly_those_not_refused (test_lsc1_protocol_doc.DocumentStateMachineTests.test_state_table_legal_opcodes_are_exactly_those_not_refused) ... ok +test_abort_at_every_byte_boundary_leaves_no_state_effect (test_lsc1_transaction.AbortResetTests.test_abort_at_every_byte_boundary_leaves_no_state_effect) ... ok +test_abort_discards_a_staged_but_unretired_transaction (test_lsc1_transaction.AbortResetTests.test_abort_discards_a_staged_but_unretired_transaction) ... ok +test_abort_takes_priority_over_a_same_edge_transfer (test_lsc1_transaction.AbortResetTests.test_abort_takes_priority_over_a_same_edge_transfer) ... ok +test_reset_at_every_byte_boundary_returns_the_lane_to_idle (test_lsc1_transaction.AbortResetTests.test_reset_at_every_byte_boundary_returns_the_lane_to_idle) ... ok +test_reset_clears_committed_state_and_the_fault_pin (test_lsc1_transaction.AbortResetTests.test_reset_clears_committed_state_and_the_fault_pin) ... ok +test_reset_takes_priority_over_abort (test_lsc1_transaction.AbortResetTests.test_reset_takes_priority_over_abort) ... ok +test_the_lane_is_reusable_after_an_abort_at_any_boundary (test_lsc1_transaction.AbortResetTests.test_the_lane_is_reusable_after_an_abort_at_any_boundary) ... ok +test_aliased_operands_must_agree (test_lsc1_transaction.BinaryOpTests.test_aliased_operands_must_agree) ... ok +test_aliased_operands_that_agree_are_accepted (test_lsc1_transaction.BinaryOpTests.test_aliased_operands_that_agree_are_accepted) ... ok +test_an_already_consistent_result_produces_no_write (test_lsc1_transaction.BinaryOpTests.test_an_already_consistent_result_produces_no_write) ... ok +test_forward_only_profile_accepts_a_fully_supplied_operand_pair (test_lsc1_transaction.BinaryOpTests.test_forward_only_profile_accepts_a_fully_supplied_operand_pair) ... ok +test_forward_only_profile_refuses_any_absent_operand (test_lsc1_transaction.BinaryOpTests.test_forward_only_profile_refuses_any_absent_operand) ... ok +test_mul_back_solve_multiplies_by_the_verified_host_inverse (test_lsc1_transaction.BinaryOpTests.test_mul_back_solve_multiplies_by_the_verified_host_inverse) ... ok +test_mul_back_solve_rejects_a_wrong_inverse (test_lsc1_transaction.BinaryOpTests.test_mul_back_solve_rejects_a_wrong_inverse) ... ok +test_mul_back_solve_through_zero_is_refused (test_lsc1_transaction.BinaryOpTests.test_mul_back_solve_through_zero_is_refused) ... ok +test_mul_forward_writes_the_field_product (test_lsc1_transaction.BinaryOpTests.test_mul_forward_writes_the_field_product) ... ok +test_u32_overflow_in_operand_addressing_faults (test_lsc1_transaction.BinaryOpTests.test_u32_overflow_in_operand_addressing_faults) ... ok +test_writing_a_conflicting_result_is_a_write_conflict (test_lsc1_transaction.BinaryOpTests.test_writing_a_conflicting_result_is_a_write_conflict) ... ok +test_xor_back_solves_the_absent_operand_in_interpreter_profile (test_lsc1_transaction.BinaryOpTests.test_xor_back_solves_the_absent_operand_in_interpreter_profile) ... ok +test_xor_forward_writes_the_sum (test_lsc1_transaction.BinaryOpTests.test_xor_forward_writes_the_sum) ... ok +test_a_digest_colliding_with_a_written_output_is_a_write_conflict (test_lsc1_transaction.Blake3ServiceTests.test_a_digest_colliding_with_a_written_output_is_a_write_conflict) ... ok +test_a_refused_service_response_leaves_the_transaction_retryable (test_lsc1_transaction.Blake3ServiceTests.test_a_refused_service_response_leaves_the_transaction_retryable) +`BAD_SERVICE` is checked before the digest folds in, so §9.1 puts it ... ok +test_a_response_for_the_wrong_transaction_or_service_is_refused (test_lsc1_transaction.Blake3ServiceTests.test_a_response_for_the_wrong_transaction_or_service_is_refused) ... ok +test_a_response_of_the_wrong_kind_is_refused (test_lsc1_transaction.Blake3ServiceTests.test_a_response_of_the_wrong_kind_is_refused) ... ok +test_a_suspended_transaction_refuses_a_new_instruction (test_lsc1_transaction.Blake3ServiceTests.test_a_suspended_transaction_refuses_a_new_instruction) ... ok +test_an_unsolicited_service_response_is_refused (test_lsc1_transaction.Blake3ServiceTests.test_an_unsolicited_service_response_is_refused) ... ok +test_request_suspends_the_transaction_and_publishes_the_operands (test_lsc1_transaction.Blake3ServiceTests.test_request_suspends_the_transaction_and_publishes_the_operands) ... ok +test_response_writes_the_digest_and_resumes_the_transaction (test_lsc1_transaction.Blake3ServiceTests.test_response_writes_the_digest_and_resumes_the_transaction) ... ok +test_budget_cycles_bound_every_observed_execution (test_lsc1_transaction.BudgetTests.test_budget_cycles_bound_every_observed_execution) ... ok +test_budget_request_bytes_match_the_codec (test_lsc1_transaction.BudgetTests.test_budget_request_bytes_match_the_codec) ... ok +test_budget_result_bytes_bound_every_observed_result_frame (test_lsc1_transaction.BudgetTests.test_budget_result_bytes_bound_every_observed_result_frame) ... ok +test_forward_only_never_costs_more_than_interpreter_compatibility (test_lsc1_transaction.BudgetTests.test_forward_only_never_costs_more_than_interpreter_compatibility) ... ok +test_no_stall_transaction_cycle_count_matches_the_byte_budget (test_lsc1_transaction.BudgetTests.test_no_stall_transaction_cycle_count_matches_the_byte_budget) ... ok +test_round_trip_cycles_are_positive_and_dominated_by_the_multiplier (test_lsc1_transaction.BudgetTests.test_round_trip_cycles_are_positive_and_dominated_by_the_multiplier) ... ok +test_a_base_index_beyond_the_verifiable_range_is_rejected (test_lsc1_transaction.DerefTests.test_a_base_index_beyond_the_verifiable_range_is_rejected) ... ok +test_a_pointer_that_is_not_the_claimed_g_power_is_rejected (test_lsc1_transaction.DerefTests.test_a_pointer_that_is_not_the_claimed_g_power_is_rejected) ... ok +test_both_sides_written_but_unequal_is_a_mismatch (test_lsc1_transaction.DerefTests.test_both_sides_written_but_unequal_is_a_mismatch) ... ok +test_cell_quadrants_in_forward_only_profile (test_lsc1_transaction.DerefTests.test_cell_quadrants_in_forward_only_profile) ... ok +test_cell_quadrants_in_interpreter_profile (test_lsc1_transaction.DerefTests.test_cell_quadrants_in_interpreter_profile) ... ok +test_deferred_equality_is_reported_never_resolved_on_chip (test_lsc1_transaction.DerefTests.test_deferred_equality_is_reported_never_resolved_on_chip) ... ok +test_fp_mode_stores_the_encoding_of_fp (test_lsc1_transaction.DerefTests.test_fp_mode_stores_the_encoding_of_fp) ... ok +test_pc_mode_does_not_store_the_encoding_of_pc_plus_gamma (test_lsc1_transaction.DerefTests.test_pc_mode_does_not_store_the_encoding_of_pc_plus_gamma) ... ok +test_pc_mode_stores_the_encoding_of_pc_plus_two (test_lsc1_transaction.DerefTests.test_pc_mode_stores_the_encoding_of_pc_plus_two) ... ok +test_pointer_verification_accepts_every_small_g_power (test_lsc1_transaction.DerefTests.test_pointer_verification_accepts_every_small_g_power) ... ok +test_checked_add_faults_instead_of_wrapping (test_lsc1_transaction.FieldArithmeticTests.test_checked_add_faults_instead_of_wrapping) ... ok +test_crc32_matches_zlib (test_lsc1_transaction.FieldArithmeticTests.test_crc32_matches_zlib) ... ok +test_encode_is_a_group_homomorphism (test_lsc1_transaction.FieldArithmeticTests.test_encode_is_a_group_homomorphism) ... ok +test_encode_matches_naive_generator_powers (test_lsc1_transaction.FieldArithmeticTests.test_encode_matches_naive_generator_powers) ... ok +test_encode_rejects_out_of_range_indices (test_lsc1_transaction.FieldArithmeticTests.test_encode_rejects_out_of_range_indices) ... ok +test_multiply_identities (test_lsc1_transaction.FieldArithmeticTests.test_multiply_identities) ... ok +test_multiply_matches_carryless_reduction_oracle (test_lsc1_transaction.FieldArithmeticTests.test_multiply_matches_carryless_reduction_oracle) ... ok +test_cell_encoding_is_presence_byte_then_little_endian_value (test_lsc1_transaction.FrameCodecTests.test_cell_encoding_is_presence_byte_then_little_endian_value) ... ok +test_cell_presence_encoding_is_canonical (test_lsc1_transaction.FrameCodecTests.test_cell_presence_encoding_is_canonical) ... ok +test_every_builder_emits_its_declared_payload_length (test_lsc1_transaction.FrameCodecTests.test_every_builder_emits_its_declared_payload_length) ... ok +test_reader_rejects_truncation_and_overrun (test_lsc1_transaction.FrameCodecTests.test_reader_rejects_truncation_and_overrun) ... ok +test_request_frame_sizes_are_envelope_plus_declared_payload (test_lsc1_transaction.FrameCodecTests.test_request_frame_sizes_are_envelope_plus_declared_payload) ... ok +test_request_payload_round_trips_through_the_decoder (test_lsc1_transaction.FrameCodecTests.test_request_payload_round_trips_through_the_decoder) ... ok +test_response_decoder_rejects_malformation (test_lsc1_transaction.FrameCodecTests.test_response_decoder_rejects_malformation) ... ok +test_response_decoder_rejects_short_frames (test_lsc1_transaction.FrameCodecTests.test_response_decoder_rejects_short_frames) ... ok +test_response_frame_round_trip (test_lsc1_transaction.FrameCodecTests.test_response_frame_round_trip) ... ok +test_a_corrupted_length_field_desynchronizes_until_the_host_aborts (test_lsc1_transaction.FramingFaultTests.test_a_corrupted_length_field_desynchronizes_until_the_host_aborts) ... ok +test_a_faulted_frame_leaves_no_staged_transaction (test_lsc1_transaction.FramingFaultTests.test_a_faulted_frame_leaves_no_staged_transaction) ... ok +test_a_length_field_beyond_the_cap_faults_without_waiting (test_lsc1_transaction.FramingFaultTests.test_a_length_field_beyond_the_cap_faults_without_waiting) ... ok +test_a_shortened_length_field_is_caught_by_the_crc (test_lsc1_transaction.FramingFaultTests.test_a_shortened_length_field_is_caught_by_the_crc) ... ok +test_bad_start_of_frame_is_rejected_byte_for_byte (test_lsc1_transaction.FramingFaultTests.test_bad_start_of_frame_is_rejected_byte_for_byte) ... ok +test_every_single_bit_flip_outside_the_length_field_is_caught (test_lsc1_transaction.FramingFaultTests.test_every_single_bit_flip_outside_the_length_field_is_caught) ... ok +test_nonzero_flags_are_reserved_and_rejected (test_lsc1_transaction.FramingFaultTests.test_nonzero_flags_are_reserved_and_rejected) ... ok +test_oversized_declared_length_faults_at_the_header (test_lsc1_transaction.FramingFaultTests.test_oversized_declared_length_faults_at_the_header) ... ok +test_unknown_opcode_faults (test_lsc1_transaction.FramingFaultTests.test_unknown_opcode_faults) ... ok +test_unknown_version_faults_without_losing_frame_sync (test_lsc1_transaction.FramingFaultTests.test_unknown_version_faults_without_losing_frame_sync) ... ok +test_wrong_payload_length_for_opcode_faults (test_lsc1_transaction.FramingFaultTests.test_wrong_payload_length_for_opcode_faults) ... ok +test_a_misdeclared_branch_outcome_is_rejected (test_lsc1_transaction.JumpTests.test_a_misdeclared_branch_outcome_is_rejected) ... ok +test_a_not_taken_branch_must_not_propose_targets (test_lsc1_transaction.JumpTests.test_a_not_taken_branch_must_not_propose_targets) ... ok +test_a_not_taken_branch_pins_the_witness_to_zero (test_lsc1_transaction.JumpTests.test_a_not_taken_branch_pins_the_witness_to_zero) ... ok +test_a_taken_branch_needs_a_verified_condition_inverse (test_lsc1_transaction.JumpTests.test_a_taken_branch_needs_a_verified_condition_inverse) ... ok +test_a_taken_branch_target_must_decode_to_the_operand (test_lsc1_transaction.JumpTests.test_a_taken_branch_target_must_decode_to_the_operand) ... ok +test_all_three_operands_are_read_on_both_branch_outcomes (test_lsc1_transaction.JumpTests.test_all_three_operands_are_read_on_both_branch_outcomes) ... ok +test_not_taken_branch_advances_pc_and_keeps_fp (test_lsc1_transaction.JumpTests.test_not_taken_branch_advances_pc_and_keeps_fp) ... ok +test_taken_branch_moves_pc_and_fp_to_the_verified_targets (test_lsc1_transaction.JumpTests.test_taken_branch_moves_pc_and_fp_to_the_verified_targets) ... ok +test_a_request_naming_the_other_profile_is_rejected (test_lsc1_transaction.ProfileTests.test_a_request_naming_the_other_profile_is_rejected) ... ok +test_default_profile_is_interpreter_compatible (test_lsc1_transaction.ProfileTests.test_default_profile_is_interpreter_compatible) ... ok +test_negotiate_rejects_a_version_window_that_excludes_v1 (test_lsc1_transaction.ProfileTests.test_negotiate_rejects_a_version_window_that_excludes_v1) ... ok +test_negotiate_rejects_an_unknown_profile (test_lsc1_transaction.ProfileTests.test_negotiate_rejects_an_unknown_profile) ... ok +test_negotiate_reports_the_phase_b_device_envelope (test_lsc1_transaction.ProfileTests.test_negotiate_reports_the_phase_b_device_envelope) ... ok +test_negotiation_is_refused_mid_transaction (test_lsc1_transaction.ProfileTests.test_negotiation_is_refused_mid_transaction) ... ok +test_a_host_that_forks_the_scalar_state_is_rejected (test_lsc1_transaction.RetirementTests.test_a_host_that_forks_the_scalar_state_is_rejected) ... ok +test_a_rejected_frame_does_not_disturb_a_suspended_service (test_lsc1_transaction.RetirementTests.test_a_rejected_frame_does_not_disturb_a_suspended_service) ... ok +test_a_rejected_frame_does_not_disturb_the_outstanding_transaction (test_lsc1_transaction.RetirementTests.test_a_rejected_frame_does_not_disturb_the_outstanding_transaction) ... ok +test_a_sequence_of_transactions_advances_pc_monotonically (test_lsc1_transaction.RetirementTests.test_a_sequence_of_transactions_advances_pc_monotonically) ... ok +test_a_transaction_retires_exactly_once (test_lsc1_transaction.RetirementTests.test_a_transaction_retires_exactly_once) ... ok +test_no_committed_state_moves_before_retirement (test_lsc1_transaction.RetirementTests.test_no_committed_state_moves_before_retirement) ... ok +test_only_one_transaction_is_outstanding_at_a_time (test_lsc1_transaction.RetirementTests.test_only_one_transaction_is_outstanding_at_a_time) ... ok +test_pc_and_fp_beyond_the_verifiable_index_range_are_refused (test_lsc1_transaction.RetirementTests.test_pc_and_fp_beyond_the_verifiable_index_range_are_refused) ... ok +test_retirement_is_bound_to_the_result_the_host_actually_read (test_lsc1_transaction.RetirementTests.test_retirement_is_bound_to_the_result_the_host_actually_read) ... ok +test_retirement_is_bound_to_the_transaction_id (test_lsc1_transaction.RetirementTests.test_retirement_is_bound_to_the_transaction_id) ... ok +test_retirement_reports_the_new_committed_state (test_lsc1_transaction.RetirementTests.test_retirement_reports_the_new_committed_state) ... ok +test_retirement_without_a_staged_transaction_is_refused (test_lsc1_transaction.RetirementTests.test_retirement_without_a_staged_transaction_is_refused) ... ok +test_status_query_reports_the_committed_state_without_changing_it (test_lsc1_transaction.RetirementTests.test_status_query_reports_the_committed_state_without_changing_it) ... ok +test_the_result_crc_covers_the_whole_result_payload (test_lsc1_transaction.RetirementTests.test_the_result_crc_covers_the_whole_result_payload) ... ok +test_set_over_a_differing_written_cell_is_a_write_conflict (test_lsc1_transaction.SetConstantTests.test_set_over_a_differing_written_cell_is_a_write_conflict) ... ok +test_set_writes_the_constant_and_advances_pc (test_lsc1_transaction.SetConstantTests.test_set_writes_the_constant_and_advances_pc) ... ok +test_backpressure_holds_the_same_byte_and_refuses_input (test_lsc1_transaction.TransportTests.test_backpressure_holds_the_same_byte_and_refuses_input) ... ok +test_deasserted_valid_commits_nothing (test_lsc1_transaction.TransportTests.test_deasserted_valid_commits_nothing) ... ok +test_done_pulse_is_one_cycle_wide_and_only_on_retirement (test_lsc1_transaction.TransportTests.test_done_pulse_is_one_cycle_wide_and_only_on_retirement) ... ok +test_fault_pin_tracks_the_last_status (test_lsc1_transaction.TransportTests.test_fault_pin_tracks_the_last_status) ... ok +test_no_byte_is_accepted_while_a_response_is_outstanding (test_lsc1_transaction.TransportTests.test_no_byte_is_accepted_while_a_response_is_outstanding) ... ok +test_response_bytes_are_identical_under_arbitrary_stall_patterns (test_lsc1_transaction.TransportTests.test_response_bytes_are_identical_under_arbitrary_stall_patterns) ... ok +test_stalls_only_ever_cost_cycles (test_lsc1_transaction.TransportTests.test_stalls_only_ever_cost_cycles) ... ok +test_exhaustive_simplified_gf8 (test_model.FieldTests.test_exhaustive_simplified_gf8) ... ok +test_known_identities (test_model.FieldTests.test_known_identities) ... ok +test_random_gf128_against_independent_reference (test_model.FieldTests.test_random_gf128_against_independent_reference) ... ok +test_mul_stream (test_model.ProtocolTests.test_mul_stream) ... ok +test_nonzero (test_model.ProtocolTests.test_nonzero) ... ok +test_status (test_model.ProtocolTests.test_status) ... ok +test_xor_stream (test_model.ProtocolTests.test_xor_stream) ... ok +test_abort_wins_over_rx_tx_and_preserves_committed_state (test_packet_executor_model.PacketExecutorTests.test_abort_wins_over_rx_tx_and_preserves_committed_state) ... ok +test_backsolve_xor_and_mul_match_reference (test_packet_executor_model.PacketExecutorTests.test_backsolve_xor_and_mul_match_reference) ... ok +test_decoded_transaction_id_survives_malformed_preamble (test_packet_executor_model.PacketExecutorTests.test_decoded_transaction_id_survives_malformed_preamble) ... ok +test_duplicate_instruction_preserves_staged_transaction (test_packet_executor_model.PacketExecutorTests.test_duplicate_instruction_preserves_staged_transaction) ... ok +test_execution_fault_rollback_is_differential_and_reusable (test_packet_executor_model.PacketExecutorTests.test_execution_fault_rollback_is_differential_and_reusable) ... ok +test_foreign_duplicate_and_bad_crc_retire_ids (test_packet_executor_model.PacketExecutorTests.test_foreign_duplicate_and_bad_crc_retire_ids) ... ok +test_future_and_unknown_opcodes_are_deterministically_unsupported (test_packet_executor_model.PacketExecutorTests.test_future_and_unknown_opcodes_are_deterministically_unsupported) ... ok +test_gf128_edge_vectors_and_algebraic_metamorphisms (test_packet_executor_model.PacketExecutorTests.test_gf128_edge_vectors_and_algebraic_metamorphisms) ... ok +test_little_endian_set_constant_and_atomic_retirement (test_packet_executor_model.PacketExecutorTests.test_little_endian_set_constant_and_atomic_retirement) ... ok +test_malformed_headers_lengths_crc_flags_cells_and_opcode (test_packet_executor_model.PacketExecutorTests.test_malformed_headers_lengths_crc_flags_cells_and_opcode) ... ok +test_malformed_payload_precedes_result_pending_state_guard (test_packet_executor_model.PacketExecutorTests.test_malformed_payload_precedes_result_pending_state_guard) ... ok +test_output_drain_poisoning_cannot_inject_next_request (test_packet_executor_model.PacketExecutorTests.test_output_drain_poisoning_cannot_inject_next_request) ... ok +test_reset_wins_and_clears_everything (test_packet_executor_model.PacketExecutorTests.test_reset_wins_and_clears_everything) ... ok +test_retirement_and_done_pulse_are_end_to_end_differential (test_packet_executor_model.PacketExecutorTests.test_retirement_and_done_pulse_are_end_to_end_differential) ... ok +test_seeded_random_differential_and_scalar_oracle (test_packet_executor_model.PacketExecutorTests.test_seeded_random_differential_and_scalar_oracle) ... ok +test_seeded_single_byte_mutations_never_commit_state (test_packet_executor_model.PacketExecutorTests.test_seeded_single_byte_mutations_never_commit_state) ... ok +test_source_located_future_gap_table_is_explicit_and_non_executable (test_packet_executor_model.PacketExecutorTests.test_source_located_future_gap_table_is_explicit_and_non_executable) ... ok +test_stalls_and_output_backpressure_are_byte_exact (test_packet_executor_model.PacketExecutorTests.test_stalls_and_output_backpressure_are_byte_exact) ... ok +test_state_mismatch_rollback_after_successful_retirement (test_packet_executor_model.PacketExecutorTests.test_state_mismatch_rollback_after_successful_retirement) ... ok +test_truncation_requires_abort_and_extra_bytes_are_separate_frames (test_packet_executor_model.PacketExecutorTests.test_truncation_requires_abort_and_extra_bytes_are_separate_frames) ... ok +test_adversarial_jump_inverse_and_xor_backsolve_match_model (test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_adversarial_jump_inverse_and_xor_backsolve_match_model) ... ok +test_deref_and_jump_faults_match_the_executable_model (test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_faults_match_the_executable_model) ... ok +test_deref_and_jump_match_the_executable_model (test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_match_the_executable_model) ... ok +test_seeded_set_xor_mul_and_frame_faults (test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_seeded_set_xor_mul_and_frame_faults) ... ok +test_abort_and_reset_discard_same_edge_status_done_pulse (test_protocol_contract.ProtocolContractTests.test_abort_and_reset_discard_same_edge_status_done_pulse) ... ok +test_abort_discards_candidate_stream_transfer_and_sets_fault (test_protocol_contract.ProtocolContractTests.test_abort_discards_candidate_stream_transfer_and_sets_fault) ... ok +test_reset_discards_transaction_and_clears_fault (test_protocol_contract.ProtocolContractTests.test_reset_discards_transaction_and_clears_fault) ... ok +test_reset_during_status_preserves_pre_reset_pins_but_discards_byte (test_protocol_contract.ProtocolContractTests.test_reset_during_status_preserves_pre_reset_pins_but_discards_byte) ... ok +test_set_backpressure_holds_data_and_refuses_input (test_protocol_contract.ProtocolContractTests.test_set_backpressure_holds_data_and_refuses_input) ... ok +test_status_holds_each_byte_under_backpressure (test_protocol_contract.ProtocolContractTests.test_status_holds_each_byte_under_backpressure) ... ok +test_unknown_command_has_exactly_one_error_byte (test_protocol_contract.ProtocolContractTests.test_unknown_command_has_exactly_one_error_byte) ... ok +test_runner_profile_and_edges (test_scalar_step_oracle.ScalarStepOracleTests.test_runner_profile_and_edges) ... ok +test_seeded_field_differential_algorithms (test_scalar_step_oracle.ScalarStepOracleTests.test_seeded_field_differential_algorithms) ... ok + +---------------------------------------------------------------------- +Ran 288 tests in 12.494s + +OK diff --git a/results/b2-capability-contract-20260728/python_full.status b/results/b2-capability-contract-20260728/python_full.status new file mode 100644 index 0000000..7e80bea --- /dev/null +++ b/results/b2-capability-contract-20260728/python_full.status @@ -0,0 +1,2 @@ +exit=0 +duration_ms=12662 diff --git a/results/b2-capability-contract-20260728/python_full_final.command b/results/b2-capability-contract-20260728/python_full_final.command new file mode 100644 index 0000000..ae73e28 --- /dev/null +++ b/results/b2-capability-contract-20260728/python_full_final.command @@ -0,0 +1 @@ +timeout 600s make python diff --git a/results/b2-capability-contract-20260728/python_full_final.log b/results/b2-capability-contract-20260728/python_full_final.log new file mode 100644 index 0000000..42603c5 --- /dev/null +++ b/results/b2-capability-contract-20260728/python_full_final.log @@ -0,0 +1,302 @@ +PYTHONDONTWRITEBYTECODE=1 python3 -m unittest discover -s sim -v +test_exchange_failure_preserves_the_complete_old_archive (test_atomic_publish.AtomicPublishTests.test_exchange_failure_preserves_the_complete_old_archive) ... ok +test_shared_builds_lock_before_taking_their_snapshot (test_atomic_publish.AtomicPublishTests.test_shared_builds_lock_before_taking_their_snapshot) ... ok +test_success_replaces_the_complete_directory (test_atomic_publish.AtomicPublishTests.test_success_replaces_the_complete_directory) ... ok +test_termination_before_exchange_preserves_old_archive (test_atomic_publish.AtomicPublishTests.test_termination_before_exchange_preserves_old_archive) ... ok +test_compute_requires_the_exact_accepted_request (test_blake3_service.AdapterAndModelTests.test_compute_requires_the_exact_accepted_request) ... ok +test_duplicate_response_is_stale_after_result_acceptance (test_blake3_service.AdapterAndModelTests.test_duplicate_response_is_stale_after_result_acceptance) ... ok +test_infrastructure_retry_is_bounded_and_semantic_failure_is_not_retried (test_blake3_service.AdapterAndModelTests.test_infrastructure_retry_is_bounded_and_semantic_failure_is_not_retried) ... ok +test_reset_never_reuses_an_earlier_epoch (test_blake3_service.AdapterAndModelTests.test_reset_never_reuses_an_earlier_epoch) ... ok +test_reset_rejects_invalid_epoch_without_changing_state (test_blake3_service.AdapterAndModelTests.test_reset_rejects_invalid_epoch_without_changing_state) ... ok +test_retry_requires_identical_operands_and_abort_tombstones_key (test_blake3_service.AdapterAndModelTests.test_retry_requires_identical_operands_and_abort_tombstones_key) ... ok +test_stalls_do_not_change_service_or_result (test_blake3_service.AdapterAndModelTests.test_stalls_do_not_change_service_or_result) ... ok +test_wrong_binding_stale_epoch_abort_and_reset_are_rejected (test_blake3_service.AdapterAndModelTests.test_wrong_binding_stale_epoch_abort_and_reset_are_rejected) ... ok +test_wrong_digest_conflict_discards_but_commit_is_atomic (test_blake3_service.AdapterAndModelTests.test_wrong_digest_conflict_discards_but_commit_is_atomic) ... ok +test_host_compression_matches_official_low_level_library (test_blake3_service.OfficialDifferentialTests.test_host_compression_matches_official_low_level_library) ... ok +test_documented_direction_preserves_current_rtl_boundary (test_blake3_service.ScatterGatherDesignContractTests.test_documented_direction_preserves_current_rtl_boundary) ... ok +test_keys_and_direct_responses_enforce_schema_ranges (test_blake3_service.SchemaTests.test_keys_and_direct_responses_enforce_schema_ranges) ... ok +test_malformed_fields_are_semantic_failures (test_blake3_service.SchemaTests.test_malformed_fields_are_semantic_failures) ... ok +test_metadata_is_rejected_before_compression (test_blake3_service.SchemaTests.test_metadata_is_rejected_before_compression) ... ok +test_schema_round_trips_exactly (test_blake3_service.SchemaTests.test_schema_round_trips_exactly) ... ok +test_coverage_contract (test_conformance_corpus.ConformanceCorpusTests.test_coverage_contract) ... ok +test_generator_is_byte_reproducible (test_conformance_corpus.ConformanceCorpusTests.test_generator_is_byte_reproducible) ... ok +test_ids_fingerprints_and_required_records (test_conformance_corpus.ConformanceCorpusTests.test_ids_fingerprints_and_required_records) ... ok +test_protocol_only_scope_is_explicit (test_conformance_corpus.ConformanceCorpusTests.test_protocol_only_scope_is_explicit) ... ok +test_raw_exchanges_replay (test_conformance_corpus.ConformanceCorpusTests.test_raw_exchanges_replay) ... ok +test_reset_case_records_the_actual_pre_edge_state (test_conformance_corpus.ConformanceCorpusTests.test_reset_case_records_the_actual_pre_edge_state) ... ok +test_commands (test_cycle_model.RandomBackpressureTests.test_commands) ... ok +test_exact_no_stall_latencies (test_cycle_model.RandomBackpressureTests.test_exact_no_stall_latencies) ... ok +test_invalid_command (test_cycle_model.RandomBackpressureTests.test_invalid_command) ... ok +test_a_malformed_field_operand_is_refused (test_host_runtime.AdapterTests.test_a_malformed_field_operand_is_refused) ... ok +test_a_mislabelled_slot_is_refused (test_host_runtime.AdapterTests.test_a_mislabelled_slot_is_refused) ... ok +test_a_non_frozen_upstream_is_refused (test_host_runtime.AdapterTests.test_a_non_frozen_upstream_is_refused) ... ok +test_a_non_power_of_two_bytecode_is_refused (test_host_runtime.AdapterTests.test_a_non_power_of_two_bytecode_is_refused) ... ok +test_an_unknown_opcode_is_refused (test_host_runtime.AdapterTests.test_an_unknown_opcode_is_refused) ... ok +test_host_package_imports_with_deferred_annotations_policy (test_host_runtime.AdapterTests.test_host_package_imports_with_deferred_annotations_policy) ... ok +test_malformed_initial_scalars_are_adapter_errors (test_host_runtime.AdapterTests.test_malformed_initial_scalars_are_adapter_errors) ... ok +test_malformed_u32_operands_are_adapter_errors (test_host_runtime.AdapterTests.test_malformed_u32_operands_are_adapter_errors) ... ok +test_missing_and_compound_operands_are_adapter_errors (test_host_runtime.AdapterTests.test_missing_and_compound_operands_are_adapter_errors) ... ok +test_pc0_outside_the_bytecode_is_refused (test_host_runtime.AdapterTests.test_pc0_outside_the_bytecode_is_refused) ... ok +test_pc_outside_the_program_is_refused (test_host_runtime.AdapterTests.test_pc_outside_the_program_is_refused) ... ok +test_the_checked_in_artifact_loads (test_host_runtime.AdapterTests.test_the_checked_in_artifact_loads) ... ok +test_wrong_schema_is_refused (test_host_runtime.AdapterTests.test_wrong_schema_is_refused) ... ok +test_complete_program_cycles_match_the_frozen_run (test_host_runtime.FrozenUpstreamComparisonTests.test_complete_program_cycles_match_the_frozen_run) ... ok +test_complete_program_is_a_full_match (test_host_runtime.FrozenUpstreamComparisonTests.test_complete_program_is_a_full_match) ... ok +test_halted_run_missing_an_upstream_cell_is_a_mismatch (test_host_runtime.FrozenUpstreamComparisonTests.test_halted_run_missing_an_upstream_cell_is_a_mismatch) ... ok +test_halted_sparse_memory_treats_unwritten_cells_as_zero (test_host_runtime.FrozenUpstreamComparisonTests.test_halted_sparse_memory_treats_unwritten_cells_as_zero) ... ok +test_host_writes_agree_with_the_frozen_final_memory (test_host_runtime.FrozenUpstreamComparisonTests.test_host_writes_agree_with_the_frozen_final_memory) ... ok +test_live_probe_must_reproduce_recorded_execution (test_host_runtime.FrozenUpstreamComparisonTests.test_live_probe_must_reproduce_recorded_execution) ... ok +test_out_of_tree_artifact_fails_with_a_clean_domain_error (test_host_runtime.FrozenUpstreamComparisonTests.test_out_of_tree_artifact_fails_with_a_clean_domain_error) ... ok +test_step_limit_cannot_be_reported_as_a_match (test_host_runtime.FrozenUpstreamComparisonTests.test_step_limit_cannot_be_reported_as_a_match) ... ok +test_the_artifact_records_the_frozen_commit_and_its_public_interface_limits (test_host_runtime.FrozenUpstreamComparisonTests.test_the_artifact_records_the_frozen_commit_and_its_public_interface_limits) ... ok +test_the_host_covers_every_cell_the_frozen_run_touched (test_host_runtime.FrozenUpstreamComparisonTests.test_the_host_covers_every_cell_the_frozen_run_touched) ... ok +test_deferred_equalities_propagate_and_detect_contradiction (test_host_runtime.HostMemoryTests.test_deferred_equalities_propagate_and_detect_contradiction) ... ok +test_deferred_equalities_propagate_to_a_fixed_point (test_host_runtime.HostMemoryTests.test_deferred_equalities_propagate_to_a_fixed_point) ... ok +test_field_inverse_round_trips (test_host_runtime.HostMemoryTests.test_field_inverse_round_trips) ... ok +test_public_input_seeds_the_first_two_cells (test_host_runtime.HostMemoryTests.test_public_input_seeds_the_first_two_cells) ... ok +test_write_once_accepts_the_same_value_and_rejects_a_different_one (test_host_runtime.HostMemoryTests.test_write_once_accepts_the_same_value_and_rejects_a_different_one) ... ok +test_a_non_g_power_has_no_index (test_host_runtime.PointerMapTests.test_a_non_g_power_has_no_index) ... ok +test_encode_and_reverse_agree (test_host_runtime.PointerMapTests.test_encode_and_reverse_agree) ... ok +test_index_beyond_the_v1_window_is_refused (test_host_runtime.PointerMapTests.test_index_beyond_the_v1_window_is_refused) ... ok +test_a_result_for_another_transaction_is_refused (test_host_runtime.ResultPayloadTests.test_a_result_for_another_transaction_is_refused) ... ok +test_a_truncated_payload_is_refused (test_host_runtime.ResultPayloadTests.test_a_truncated_payload_is_refused) ... ok +test_decode_matches_the_endpoint_encoding (test_host_runtime.ResultPayloadTests.test_decode_matches_the_endpoint_encoding) ... ok +test_poisoned_result_wrong_txn_id_is_protocol_violation (test_host_runtime.ResultPayloadTests.test_poisoned_result_wrong_txn_id_is_protocol_violation) ... ok +test_poisoned_stale_frame_regressions (test_host_runtime.ResultPayloadTests.test_poisoned_stale_frame_regressions) +Poisoned or stale frames (wrong txn, tampered CRC) must be refused; F1 binding preserved. ... ok +test_a_corrupted_response_is_not_reported_as_a_preparation_fault (test_host_runtime.RuntimeTests.test_a_corrupted_response_is_not_reported_as_a_preparation_fault) ... ok +test_a_deferred_local_outside_the_frame_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_a_deferred_local_outside_the_frame_is_refused_before_retire_is_sent) ... ok +test_a_deferred_target_outside_the_frame_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_a_deferred_target_outside_the_frame_is_refused_before_retire_is_sent) ... ok +test_a_duplicate_retire_against_the_real_endpoint_is_refused (test_host_runtime.RuntimeTests.test_a_duplicate_retire_against_the_real_endpoint_is_refused) ... ok +test_a_fault_bound_to_another_transaction_is_a_protocol_violation (test_host_runtime.RuntimeTests.test_a_fault_bound_to_another_transaction_is_a_protocol_violation) ... ok +test_a_fault_payload_of_the_wrong_size_is_a_protocol_violation (test_host_runtime.RuntimeTests.test_a_fault_payload_of_the_wrong_size_is_a_protocol_violation) ... ok +test_a_frame_level_retire_rejection_is_a_protocol_violation (test_host_runtime.RuntimeTests.test_a_frame_level_retire_rejection_is_a_protocol_violation) ... ok +test_a_frame_only_instruction_fault_binding_this_txn_is_still_refused (test_host_runtime.RuntimeTests.test_a_frame_only_instruction_fault_binding_this_txn_is_still_refused) ... ok +test_a_non_discarding_retire_fault_binding_this_txn_is_still_refused (test_host_runtime.RuntimeTests.test_a_non_discarding_retire_fault_binding_this_txn_is_still_refused) ... ok +test_a_non_fault_status_is_not_recorded_as_a_fault (test_host_runtime.RuntimeTests.test_a_non_fault_status_is_not_recorded_as_a_fault) ... ok +test_a_non_overflowing_address_is_not_a_preparation_fault (test_host_runtime.RuntimeTests.test_a_non_overflowing_address_is_not_a_preparation_fault) ... ok +test_a_non_retired_non_fault_status_is_not_recorded_as_a_fault (test_host_runtime.RuntimeTests.test_a_non_retired_non_fault_status_is_not_recorded_as_a_fault) ... ok +test_a_retire_fault_payload_of_the_wrong_size_is_a_protocol_violation (test_host_runtime.RuntimeTests.test_a_retire_fault_payload_of_the_wrong_size_is_a_protocol_violation) ... ok +test_a_well_formed_fault_is_still_attributed_to_the_step (test_host_runtime.RuntimeTests.test_a_well_formed_fault_is_still_attributed_to_the_step) ... ok +test_a_well_formed_retire_fault_is_still_attributed_to_the_step (test_host_runtime.RuntimeTests.test_a_well_formed_retire_fault_is_still_attributed_to_the_step) ... ok +test_a_write_conflict_is_reported_as_a_fault_not_applied (test_host_runtime.RuntimeTests.test_a_write_conflict_is_reported_as_a_fault_not_applied) ... ok +test_a_write_once_conflict_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_a_write_once_conflict_is_refused_before_retire_is_sent) ... ok +test_a_write_outside_the_frame_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_a_write_outside_the_frame_is_refused_before_retire_is_sent) ... ok +test_an_acceptable_write_batch_is_still_retired_and_applied (test_host_runtime.RuntimeTests.test_an_acceptable_write_batch_is_still_retired_and_applied) +Guards the two tests above from passing because RETIRE never happens. ... ok +test_an_access_outside_the_frame_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_an_access_outside_the_frame_is_refused_before_retire_is_sent) ... ok +test_an_idle_guard_fault_is_still_attributed_to_the_step (test_host_runtime.RuntimeTests.test_an_idle_guard_fault_is_still_attributed_to_the_step) ... ok +test_an_in_frame_deferred_pair_is_still_retired_and_recorded (test_host_runtime.RuntimeTests.test_an_in_frame_deferred_pair_is_still_retired_and_recorded) +Guards the two tests above from passing because RETIRE never happens. ... ok +test_an_invalid_deferred_equality_is_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_an_invalid_deferred_equality_is_refused_before_retire_is_sent) ... ok +test_an_overflowing_effective_address_is_a_fault_terminal (test_host_runtime.RuntimeTests.test_an_overflowing_effective_address_is_a_fault_terminal) ... ok +test_arbitrary_rx_tx_stalls_and_backpressure (test_host_runtime.RuntimeTests.test_arbitrary_rx_tx_stalls_and_backpressure) +Full transaction loop under arbitrary permitted lane-gap patterns. ... ok +test_conflicting_duplicate_writes_are_refused_before_retire_is_sent (test_host_runtime.RuntimeTests.test_conflicting_duplicate_writes_are_refused_before_retire_is_sent) ... ok +test_deref_modes_are_prepared_with_host_pointer_resolution (test_host_runtime.RuntimeTests.test_deref_modes_are_prepared_with_host_pointer_resolution) ... ok +test_every_real_endpoint_effect_stays_inside_the_frame (test_host_runtime.RuntimeTests.test_every_real_endpoint_effect_stays_inside_the_frame) ... ok +test_forward_only_refuses_the_same_back_solve (test_host_runtime.RuntimeTests.test_forward_only_refuses_the_same_back_solve) ... ok +test_jump_taken_and_not_taken_are_host_proposed_and_verified (test_host_runtime.RuntimeTests.test_jump_taken_and_not_taken_are_host_proposed_and_verified) ... ok +test_mul_back_solves_from_the_host_inverse_witness (test_host_runtime.RuntimeTests.test_mul_back_solves_from_the_host_inverse_witness) ... ok +test_multiplying_by_a_known_zero_is_not_given_a_witness (test_host_runtime.RuntimeTests.test_multiplying_by_a_known_zero_is_not_given_a_witness) ... ok +test_negotiate_requires_every_schema_field (test_host_runtime.RuntimeTests.test_negotiate_requires_every_schema_field) ... ok +test_sentinel_requires_zero_frame_pointer (test_host_runtime.RuntimeTests.test_sentinel_requires_zero_frame_pointer) ... ok +test_set_xor_mul_are_driven_end_to_end (test_host_runtime.RuntimeTests.test_set_xor_mul_are_driven_end_to_end) ... ok +test_stale_retire_txn_id_is_protocol_violation (test_host_runtime.RuntimeTests.test_stale_retire_txn_id_is_protocol_violation) ... ok +test_the_real_endpoint_defers_only_inside_the_frame (test_host_runtime.RuntimeTests.test_the_real_endpoint_defers_only_inside_the_frame) ... ok +test_the_step_limit_is_a_terminal_not_a_hang (test_host_runtime.RuntimeTests.test_the_step_limit_is_a_terminal_not_a_hang) ... ok +test_the_step_record_carries_the_whole_comparison_schema (test_host_runtime.RuntimeTests.test_the_step_record_carries_the_whole_comparison_schema) ... ok +test_unintegrated_blake3_stops_the_run_and_says_what_is_missing (test_host_runtime.RuntimeTests.test_unintegrated_blake3_stops_the_run_and_says_what_is_missing) ... ok +test_assumption_table_is_the_model_assumptions (test_lsc1_protocol_doc.DocumentBudgetTests.test_assumption_table_is_the_model_assumptions) ... ok +test_control_frame_table_matches_driven_exchanges (test_lsc1_protocol_doc.DocumentBudgetTests.test_control_frame_table_matches_driven_exchanges) ... ok +test_encode_index_cost_is_stated_as_the_model_computes_it (test_lsc1_protocol_doc.DocumentBudgetTests.test_encode_index_cost_is_stated_as_the_model_computes_it) ... ok +test_fermat_inverse_cost_is_the_square_and_multiply_count (test_lsc1_protocol_doc.DocumentBudgetTests.test_fermat_inverse_cost_is_the_square_and_multiply_count) ... ok +test_per_opcode_budget_tables_match_the_model (test_lsc1_protocol_doc.DocumentBudgetTests.test_per_opcode_budget_tables_match_the_model) ... ok +test_fault_codes_are_all_at_or_above_the_fault_bit (test_lsc1_protocol_doc.DocumentCodeTests.test_fault_codes_are_all_at_or_above_the_fault_bit) ... ok +test_profile_table_is_exactly_the_profile_enum (test_lsc1_protocol_doc.DocumentCodeTests.test_profile_table_is_exactly_the_profile_enum) ... ok +test_state_table_names_exactly_the_model_states (test_lsc1_protocol_doc.DocumentCodeTests.test_state_table_names_exactly_the_model_states) ... ok +test_status_table_is_exactly_the_status_enum (test_lsc1_protocol_doc.DocumentCodeTests.test_status_table_is_exactly_the_status_enum) ... ok +test_contents_list_links_to_every_top_level_section (test_lsc1_protocol_doc.DocumentProvenanceTests.test_contents_list_links_to_every_top_level_section) ... ok +test_document_claims_no_verification_fabrication_validation_or_readiness (test_lsc1_protocol_doc.DocumentProvenanceTests.test_document_claims_no_verification_fabrication_validation_or_readiness) ... ok +test_document_does_not_reference_the_retired_module_name (test_lsc1_protocol_doc.DocumentProvenanceTests.test_document_does_not_reference_the_retired_module_name) ... ok +test_document_names_the_module_and_test_that_generate_its_tables (test_lsc1_protocol_doc.DocumentProvenanceTests.test_document_names_the_module_and_test_that_generate_its_tables) ... ok +test_document_version_matches_the_protocol_version (test_lsc1_protocol_doc.DocumentProvenanceTests.test_document_version_matches_the_protocol_version) ... ok +test_every_internal_link_resolves_to_a_heading (test_lsc1_protocol_doc.DocumentProvenanceTests.test_every_internal_link_resolves_to_a_heading) ... ok +test_every_upstream_citation_is_pinned_to_the_frozen_commit (test_lsc1_protocol_doc.DocumentProvenanceTests.test_every_upstream_citation_is_pinned_to_the_frozen_commit) ... ok +test_no_upstream_citation_points_at_a_moving_branch (test_lsc1_protocol_doc.DocumentProvenanceTests.test_no_upstream_citation_points_at_a_moving_branch) ... ok +test_binary_profile_table_matches_driven_transitions (test_lsc1_protocol_doc.DocumentSemanticsTests.test_binary_profile_table_matches_driven_transitions) ... ok +test_default_profile_after_reset_is_the_one_the_document_names (test_lsc1_protocol_doc.DocumentSemanticsTests.test_default_profile_after_reset_is_the_one_the_document_names) ... ok +test_deref_cell_quadrant_table_matches_driven_transitions (test_lsc1_protocol_doc.DocumentSemanticsTests.test_deref_cell_quadrant_table_matches_driven_transitions) ... ok +test_declared_envelope_overhead_is_what_the_codec_adds (test_lsc1_protocol_doc.DocumentSizeTests.test_declared_envelope_overhead_is_what_the_codec_adds) ... ok +test_deref_modes_share_one_schema_and_one_size (test_lsc1_protocol_doc.DocumentSizeTests.test_deref_modes_share_one_schema_and_one_size) ... ok +test_envelope_prose_matches_the_header_constants (test_lsc1_protocol_doc.DocumentSizeTests.test_envelope_prose_matches_the_header_constants) ... ok +test_every_offset_table_is_cumulative_and_totals_its_declared_size (test_lsc1_protocol_doc.DocumentSizeTests.test_every_offset_table_is_cumulative_and_totals_its_declared_size) +Offsets are not taken on trust: each row must start where the last ended. ... ok +test_every_request_schema_heading_declares_its_payload_size (test_lsc1_protocol_doc.DocumentSizeTests.test_every_request_schema_heading_declares_its_payload_size) ... ok +test_frame_size_table_matches_the_codec (test_lsc1_protocol_doc.DocumentSizeTests.test_frame_size_table_matches_the_codec) ... ok +test_inline_prose_byte_counts_match_the_driven_endpoint (test_lsc1_protocol_doc.DocumentSizeTests.test_inline_prose_byte_counts_match_the_driven_endpoint) +Sizes stated in words drift as easily as sizes stated in tables. ... ok +test_mul_native_schema_extends_the_xor_schema (test_lsc1_protocol_doc.DocumentSizeTests.test_mul_native_schema_extends_the_xor_schema) ... ok +test_negotiate_reply_schema_constants_are_the_model_constants (test_lsc1_protocol_doc.DocumentSizeTests.test_negotiate_reply_schema_constants_are_the_model_constants) ... ok +test_preamble_table_covers_exactly_the_preamble_bytes (test_lsc1_protocol_doc.DocumentSizeTests.test_preamble_table_covers_exactly_the_preamble_bytes) ... ok +test_primitive_type_table_matches_the_codec_widths (test_lsc1_protocol_doc.DocumentSizeTests.test_primitive_type_table_matches_the_codec_widths) ... ok +test_response_schema_headings_match_measured_payloads (test_lsc1_protocol_doc.DocumentSizeTests.test_response_schema_headings_match_measured_payloads) ... ok +test_result_payload_row_widths_match_the_encoder (test_lsc1_protocol_doc.DocumentSizeTests.test_result_payload_row_widths_match_the_encoder) ... ok +test_a_transaction_retires_at_most_once (test_lsc1_protocol_doc.DocumentStateMachineTests.test_a_transaction_retires_at_most_once) ... ok +test_no_fault_moves_committed_pc_fp_or_retire_seq (test_lsc1_protocol_doc.DocumentStateMachineTests.test_no_fault_moves_committed_pc_fp_or_retire_seq) +The §9.1 claim, read at the §8.5 offsets the document publishes. ... ok +test_state_table_legal_opcodes_are_exactly_those_not_refused (test_lsc1_protocol_doc.DocumentStateMachineTests.test_state_table_legal_opcodes_are_exactly_those_not_refused) ... ok +test_abort_at_every_byte_boundary_leaves_no_state_effect (test_lsc1_transaction.AbortResetTests.test_abort_at_every_byte_boundary_leaves_no_state_effect) ... ok +test_abort_discards_a_staged_but_unretired_transaction (test_lsc1_transaction.AbortResetTests.test_abort_discards_a_staged_but_unretired_transaction) ... ok +test_abort_takes_priority_over_a_same_edge_transfer (test_lsc1_transaction.AbortResetTests.test_abort_takes_priority_over_a_same_edge_transfer) ... ok +test_reset_at_every_byte_boundary_returns_the_lane_to_idle (test_lsc1_transaction.AbortResetTests.test_reset_at_every_byte_boundary_returns_the_lane_to_idle) ... ok +test_reset_clears_committed_state_and_the_fault_pin (test_lsc1_transaction.AbortResetTests.test_reset_clears_committed_state_and_the_fault_pin) ... ok +test_reset_takes_priority_over_abort (test_lsc1_transaction.AbortResetTests.test_reset_takes_priority_over_abort) ... ok +test_the_lane_is_reusable_after_an_abort_at_any_boundary (test_lsc1_transaction.AbortResetTests.test_the_lane_is_reusable_after_an_abort_at_any_boundary) ... ok +test_aliased_operands_must_agree (test_lsc1_transaction.BinaryOpTests.test_aliased_operands_must_agree) ... ok +test_aliased_operands_that_agree_are_accepted (test_lsc1_transaction.BinaryOpTests.test_aliased_operands_that_agree_are_accepted) ... ok +test_an_already_consistent_result_produces_no_write (test_lsc1_transaction.BinaryOpTests.test_an_already_consistent_result_produces_no_write) ... ok +test_forward_only_profile_accepts_a_fully_supplied_operand_pair (test_lsc1_transaction.BinaryOpTests.test_forward_only_profile_accepts_a_fully_supplied_operand_pair) ... ok +test_forward_only_profile_refuses_any_absent_operand (test_lsc1_transaction.BinaryOpTests.test_forward_only_profile_refuses_any_absent_operand) ... ok +test_mul_back_solve_multiplies_by_the_verified_host_inverse (test_lsc1_transaction.BinaryOpTests.test_mul_back_solve_multiplies_by_the_verified_host_inverse) ... ok +test_mul_back_solve_rejects_a_wrong_inverse (test_lsc1_transaction.BinaryOpTests.test_mul_back_solve_rejects_a_wrong_inverse) ... ok +test_mul_back_solve_through_zero_is_refused (test_lsc1_transaction.BinaryOpTests.test_mul_back_solve_through_zero_is_refused) ... ok +test_mul_forward_writes_the_field_product (test_lsc1_transaction.BinaryOpTests.test_mul_forward_writes_the_field_product) ... ok +test_u32_overflow_in_operand_addressing_faults (test_lsc1_transaction.BinaryOpTests.test_u32_overflow_in_operand_addressing_faults) ... ok +test_writing_a_conflicting_result_is_a_write_conflict (test_lsc1_transaction.BinaryOpTests.test_writing_a_conflicting_result_is_a_write_conflict) ... ok +test_xor_back_solves_the_absent_operand_in_interpreter_profile (test_lsc1_transaction.BinaryOpTests.test_xor_back_solves_the_absent_operand_in_interpreter_profile) ... ok +test_xor_forward_writes_the_sum (test_lsc1_transaction.BinaryOpTests.test_xor_forward_writes_the_sum) ... ok +test_a_digest_colliding_with_a_written_output_is_a_write_conflict (test_lsc1_transaction.Blake3ServiceTests.test_a_digest_colliding_with_a_written_output_is_a_write_conflict) ... ok +test_a_refused_service_response_leaves_the_transaction_retryable (test_lsc1_transaction.Blake3ServiceTests.test_a_refused_service_response_leaves_the_transaction_retryable) +`BAD_SERVICE` is checked before the digest folds in, so §9.1 puts it ... ok +test_a_response_for_the_wrong_transaction_or_service_is_refused (test_lsc1_transaction.Blake3ServiceTests.test_a_response_for_the_wrong_transaction_or_service_is_refused) ... ok +test_a_response_of_the_wrong_kind_is_refused (test_lsc1_transaction.Blake3ServiceTests.test_a_response_of_the_wrong_kind_is_refused) ... ok +test_a_suspended_transaction_refuses_a_new_instruction (test_lsc1_transaction.Blake3ServiceTests.test_a_suspended_transaction_refuses_a_new_instruction) ... ok +test_an_unsolicited_service_response_is_refused (test_lsc1_transaction.Blake3ServiceTests.test_an_unsolicited_service_response_is_refused) ... ok +test_request_suspends_the_transaction_and_publishes_the_operands (test_lsc1_transaction.Blake3ServiceTests.test_request_suspends_the_transaction_and_publishes_the_operands) ... ok +test_response_writes_the_digest_and_resumes_the_transaction (test_lsc1_transaction.Blake3ServiceTests.test_response_writes_the_digest_and_resumes_the_transaction) ... ok +test_budget_cycles_bound_every_observed_execution (test_lsc1_transaction.BudgetTests.test_budget_cycles_bound_every_observed_execution) ... ok +test_budget_request_bytes_match_the_codec (test_lsc1_transaction.BudgetTests.test_budget_request_bytes_match_the_codec) ... ok +test_budget_result_bytes_bound_every_observed_result_frame (test_lsc1_transaction.BudgetTests.test_budget_result_bytes_bound_every_observed_result_frame) ... ok +test_forward_only_never_costs_more_than_interpreter_compatibility (test_lsc1_transaction.BudgetTests.test_forward_only_never_costs_more_than_interpreter_compatibility) ... ok +test_no_stall_transaction_cycle_count_matches_the_byte_budget (test_lsc1_transaction.BudgetTests.test_no_stall_transaction_cycle_count_matches_the_byte_budget) ... ok +test_round_trip_cycles_are_positive_and_dominated_by_the_multiplier (test_lsc1_transaction.BudgetTests.test_round_trip_cycles_are_positive_and_dominated_by_the_multiplier) ... ok +test_a_base_index_beyond_the_verifiable_range_is_rejected (test_lsc1_transaction.DerefTests.test_a_base_index_beyond_the_verifiable_range_is_rejected) ... ok +test_a_pointer_that_is_not_the_claimed_g_power_is_rejected (test_lsc1_transaction.DerefTests.test_a_pointer_that_is_not_the_claimed_g_power_is_rejected) ... ok +test_both_sides_written_but_unequal_is_a_mismatch (test_lsc1_transaction.DerefTests.test_both_sides_written_but_unequal_is_a_mismatch) ... ok +test_cell_quadrants_in_forward_only_profile (test_lsc1_transaction.DerefTests.test_cell_quadrants_in_forward_only_profile) ... ok +test_cell_quadrants_in_interpreter_profile (test_lsc1_transaction.DerefTests.test_cell_quadrants_in_interpreter_profile) ... ok +test_deferred_equality_is_reported_never_resolved_on_chip (test_lsc1_transaction.DerefTests.test_deferred_equality_is_reported_never_resolved_on_chip) ... ok +test_fp_mode_stores_the_encoding_of_fp (test_lsc1_transaction.DerefTests.test_fp_mode_stores_the_encoding_of_fp) ... ok +test_pc_mode_does_not_store_the_encoding_of_pc_plus_gamma (test_lsc1_transaction.DerefTests.test_pc_mode_does_not_store_the_encoding_of_pc_plus_gamma) ... ok +test_pc_mode_stores_the_encoding_of_pc_plus_two (test_lsc1_transaction.DerefTests.test_pc_mode_stores_the_encoding_of_pc_plus_two) ... ok +test_pointer_verification_accepts_every_small_g_power (test_lsc1_transaction.DerefTests.test_pointer_verification_accepts_every_small_g_power) ... ok +test_checked_add_faults_instead_of_wrapping (test_lsc1_transaction.FieldArithmeticTests.test_checked_add_faults_instead_of_wrapping) ... ok +test_crc32_matches_zlib (test_lsc1_transaction.FieldArithmeticTests.test_crc32_matches_zlib) ... ok +test_encode_is_a_group_homomorphism (test_lsc1_transaction.FieldArithmeticTests.test_encode_is_a_group_homomorphism) ... ok +test_encode_matches_naive_generator_powers (test_lsc1_transaction.FieldArithmeticTests.test_encode_matches_naive_generator_powers) ... ok +test_encode_rejects_out_of_range_indices (test_lsc1_transaction.FieldArithmeticTests.test_encode_rejects_out_of_range_indices) ... ok +test_multiply_identities (test_lsc1_transaction.FieldArithmeticTests.test_multiply_identities) ... ok +test_multiply_matches_carryless_reduction_oracle (test_lsc1_transaction.FieldArithmeticTests.test_multiply_matches_carryless_reduction_oracle) ... ok +test_cell_encoding_is_presence_byte_then_little_endian_value (test_lsc1_transaction.FrameCodecTests.test_cell_encoding_is_presence_byte_then_little_endian_value) ... ok +test_cell_presence_encoding_is_canonical (test_lsc1_transaction.FrameCodecTests.test_cell_presence_encoding_is_canonical) ... ok +test_every_builder_emits_its_declared_payload_length (test_lsc1_transaction.FrameCodecTests.test_every_builder_emits_its_declared_payload_length) ... ok +test_reader_rejects_truncation_and_overrun (test_lsc1_transaction.FrameCodecTests.test_reader_rejects_truncation_and_overrun) ... ok +test_request_frame_sizes_are_envelope_plus_declared_payload (test_lsc1_transaction.FrameCodecTests.test_request_frame_sizes_are_envelope_plus_declared_payload) ... ok +test_request_payload_round_trips_through_the_decoder (test_lsc1_transaction.FrameCodecTests.test_request_payload_round_trips_through_the_decoder) ... ok +test_response_decoder_rejects_malformation (test_lsc1_transaction.FrameCodecTests.test_response_decoder_rejects_malformation) ... ok +test_response_decoder_rejects_short_frames (test_lsc1_transaction.FrameCodecTests.test_response_decoder_rejects_short_frames) ... ok +test_response_frame_round_trip (test_lsc1_transaction.FrameCodecTests.test_response_frame_round_trip) ... ok +test_a_corrupted_length_field_desynchronizes_until_the_host_aborts (test_lsc1_transaction.FramingFaultTests.test_a_corrupted_length_field_desynchronizes_until_the_host_aborts) ... ok +test_a_faulted_frame_leaves_no_staged_transaction (test_lsc1_transaction.FramingFaultTests.test_a_faulted_frame_leaves_no_staged_transaction) ... ok +test_a_length_field_beyond_the_cap_faults_without_waiting (test_lsc1_transaction.FramingFaultTests.test_a_length_field_beyond_the_cap_faults_without_waiting) ... ok +test_a_shortened_length_field_is_caught_by_the_crc (test_lsc1_transaction.FramingFaultTests.test_a_shortened_length_field_is_caught_by_the_crc) ... ok +test_bad_start_of_frame_is_rejected_byte_for_byte (test_lsc1_transaction.FramingFaultTests.test_bad_start_of_frame_is_rejected_byte_for_byte) ... ok +test_every_single_bit_flip_outside_the_length_field_is_caught (test_lsc1_transaction.FramingFaultTests.test_every_single_bit_flip_outside_the_length_field_is_caught) ... ok +test_nonzero_flags_are_reserved_and_rejected (test_lsc1_transaction.FramingFaultTests.test_nonzero_flags_are_reserved_and_rejected) ... ok +test_oversized_declared_length_faults_at_the_header (test_lsc1_transaction.FramingFaultTests.test_oversized_declared_length_faults_at_the_header) ... ok +test_unknown_opcode_faults (test_lsc1_transaction.FramingFaultTests.test_unknown_opcode_faults) ... ok +test_unknown_version_faults_without_losing_frame_sync (test_lsc1_transaction.FramingFaultTests.test_unknown_version_faults_without_losing_frame_sync) ... ok +test_wrong_payload_length_for_opcode_faults (test_lsc1_transaction.FramingFaultTests.test_wrong_payload_length_for_opcode_faults) ... ok +test_a_misdeclared_branch_outcome_is_rejected (test_lsc1_transaction.JumpTests.test_a_misdeclared_branch_outcome_is_rejected) ... ok +test_a_not_taken_branch_must_not_propose_targets (test_lsc1_transaction.JumpTests.test_a_not_taken_branch_must_not_propose_targets) ... ok +test_a_not_taken_branch_pins_the_witness_to_zero (test_lsc1_transaction.JumpTests.test_a_not_taken_branch_pins_the_witness_to_zero) ... ok +test_a_taken_branch_needs_a_verified_condition_inverse (test_lsc1_transaction.JumpTests.test_a_taken_branch_needs_a_verified_condition_inverse) ... ok +test_a_taken_branch_target_must_decode_to_the_operand (test_lsc1_transaction.JumpTests.test_a_taken_branch_target_must_decode_to_the_operand) ... ok +test_all_three_operands_are_read_on_both_branch_outcomes (test_lsc1_transaction.JumpTests.test_all_three_operands_are_read_on_both_branch_outcomes) ... ok +test_not_taken_branch_advances_pc_and_keeps_fp (test_lsc1_transaction.JumpTests.test_not_taken_branch_advances_pc_and_keeps_fp) ... ok +test_taken_branch_moves_pc_and_fp_to_the_verified_targets (test_lsc1_transaction.JumpTests.test_taken_branch_moves_pc_and_fp_to_the_verified_targets) ... ok +test_a_request_naming_the_other_profile_is_rejected (test_lsc1_transaction.ProfileTests.test_a_request_naming_the_other_profile_is_rejected) ... ok +test_default_profile_is_interpreter_compatible (test_lsc1_transaction.ProfileTests.test_default_profile_is_interpreter_compatible) ... ok +test_negotiate_rejects_a_version_window_that_excludes_v1 (test_lsc1_transaction.ProfileTests.test_negotiate_rejects_a_version_window_that_excludes_v1) ... ok +test_negotiate_rejects_an_unknown_profile (test_lsc1_transaction.ProfileTests.test_negotiate_rejects_an_unknown_profile) ... ok +test_negotiate_reports_the_phase_b_device_envelope (test_lsc1_transaction.ProfileTests.test_negotiate_reports_the_phase_b_device_envelope) ... ok +test_negotiation_is_refused_mid_transaction (test_lsc1_transaction.ProfileTests.test_negotiation_is_refused_mid_transaction) ... ok +test_a_host_that_forks_the_scalar_state_is_rejected (test_lsc1_transaction.RetirementTests.test_a_host_that_forks_the_scalar_state_is_rejected) ... ok +test_a_rejected_frame_does_not_disturb_a_suspended_service (test_lsc1_transaction.RetirementTests.test_a_rejected_frame_does_not_disturb_a_suspended_service) ... ok +test_a_rejected_frame_does_not_disturb_the_outstanding_transaction (test_lsc1_transaction.RetirementTests.test_a_rejected_frame_does_not_disturb_the_outstanding_transaction) ... ok +test_a_sequence_of_transactions_advances_pc_monotonically (test_lsc1_transaction.RetirementTests.test_a_sequence_of_transactions_advances_pc_monotonically) ... ok +test_a_transaction_retires_exactly_once (test_lsc1_transaction.RetirementTests.test_a_transaction_retires_exactly_once) ... ok +test_no_committed_state_moves_before_retirement (test_lsc1_transaction.RetirementTests.test_no_committed_state_moves_before_retirement) ... ok +test_only_one_transaction_is_outstanding_at_a_time (test_lsc1_transaction.RetirementTests.test_only_one_transaction_is_outstanding_at_a_time) ... ok +test_pc_and_fp_beyond_the_verifiable_index_range_are_refused (test_lsc1_transaction.RetirementTests.test_pc_and_fp_beyond_the_verifiable_index_range_are_refused) ... ok +test_retirement_is_bound_to_the_result_the_host_actually_read (test_lsc1_transaction.RetirementTests.test_retirement_is_bound_to_the_result_the_host_actually_read) ... ok +test_retirement_is_bound_to_the_transaction_id (test_lsc1_transaction.RetirementTests.test_retirement_is_bound_to_the_transaction_id) ... ok +test_retirement_reports_the_new_committed_state (test_lsc1_transaction.RetirementTests.test_retirement_reports_the_new_committed_state) ... ok +test_retirement_without_a_staged_transaction_is_refused (test_lsc1_transaction.RetirementTests.test_retirement_without_a_staged_transaction_is_refused) ... ok +test_status_query_reports_the_committed_state_without_changing_it (test_lsc1_transaction.RetirementTests.test_status_query_reports_the_committed_state_without_changing_it) ... ok +test_the_result_crc_covers_the_whole_result_payload (test_lsc1_transaction.RetirementTests.test_the_result_crc_covers_the_whole_result_payload) ... ok +test_set_over_a_differing_written_cell_is_a_write_conflict (test_lsc1_transaction.SetConstantTests.test_set_over_a_differing_written_cell_is_a_write_conflict) ... ok +test_set_writes_the_constant_and_advances_pc (test_lsc1_transaction.SetConstantTests.test_set_writes_the_constant_and_advances_pc) ... ok +test_backpressure_holds_the_same_byte_and_refuses_input (test_lsc1_transaction.TransportTests.test_backpressure_holds_the_same_byte_and_refuses_input) ... ok +test_deasserted_valid_commits_nothing (test_lsc1_transaction.TransportTests.test_deasserted_valid_commits_nothing) ... ok +test_done_pulse_is_one_cycle_wide_and_only_on_retirement (test_lsc1_transaction.TransportTests.test_done_pulse_is_one_cycle_wide_and_only_on_retirement) ... ok +test_fault_pin_tracks_the_last_status (test_lsc1_transaction.TransportTests.test_fault_pin_tracks_the_last_status) ... ok +test_no_byte_is_accepted_while_a_response_is_outstanding (test_lsc1_transaction.TransportTests.test_no_byte_is_accepted_while_a_response_is_outstanding) ... ok +test_response_bytes_are_identical_under_arbitrary_stall_patterns (test_lsc1_transaction.TransportTests.test_response_bytes_are_identical_under_arbitrary_stall_patterns) ... ok +test_stalls_only_ever_cost_cycles (test_lsc1_transaction.TransportTests.test_stalls_only_ever_cost_cycles) ... ok +test_exhaustive_simplified_gf8 (test_model.FieldTests.test_exhaustive_simplified_gf8) ... ok +test_known_identities (test_model.FieldTests.test_known_identities) ... ok +test_random_gf128_against_independent_reference (test_model.FieldTests.test_random_gf128_against_independent_reference) ... ok +test_mul_stream (test_model.ProtocolTests.test_mul_stream) ... ok +test_nonzero (test_model.ProtocolTests.test_nonzero) ... ok +test_status (test_model.ProtocolTests.test_status) ... ok +test_xor_stream (test_model.ProtocolTests.test_xor_stream) ... ok +test_abort_wins_over_rx_tx_and_preserves_committed_state (test_packet_executor_model.PacketExecutorTests.test_abort_wins_over_rx_tx_and_preserves_committed_state) ... ok +test_backsolve_xor_and_mul_match_reference (test_packet_executor_model.PacketExecutorTests.test_backsolve_xor_and_mul_match_reference) ... ok +test_decoded_transaction_id_survives_malformed_preamble (test_packet_executor_model.PacketExecutorTests.test_decoded_transaction_id_survives_malformed_preamble) ... ok +test_duplicate_instruction_preserves_staged_transaction (test_packet_executor_model.PacketExecutorTests.test_duplicate_instruction_preserves_staged_transaction) ... ok +test_execution_fault_rollback_is_differential_and_reusable (test_packet_executor_model.PacketExecutorTests.test_execution_fault_rollback_is_differential_and_reusable) ... ok +test_foreign_duplicate_and_bad_crc_retire_ids (test_packet_executor_model.PacketExecutorTests.test_foreign_duplicate_and_bad_crc_retire_ids) ... ok +test_future_and_unknown_opcodes_are_deterministically_unsupported (test_packet_executor_model.PacketExecutorTests.test_future_and_unknown_opcodes_are_deterministically_unsupported) ... ok +test_gf128_edge_vectors_and_algebraic_metamorphisms (test_packet_executor_model.PacketExecutorTests.test_gf128_edge_vectors_and_algebraic_metamorphisms) ... ok +test_little_endian_set_constant_and_atomic_retirement (test_packet_executor_model.PacketExecutorTests.test_little_endian_set_constant_and_atomic_retirement) ... ok +test_malformed_headers_lengths_crc_flags_cells_and_opcode (test_packet_executor_model.PacketExecutorTests.test_malformed_headers_lengths_crc_flags_cells_and_opcode) ... ok +test_malformed_payload_precedes_result_pending_state_guard (test_packet_executor_model.PacketExecutorTests.test_malformed_payload_precedes_result_pending_state_guard) ... ok +test_output_drain_poisoning_cannot_inject_next_request (test_packet_executor_model.PacketExecutorTests.test_output_drain_poisoning_cannot_inject_next_request) ... ok +test_reset_wins_and_clears_everything (test_packet_executor_model.PacketExecutorTests.test_reset_wins_and_clears_everything) ... ok +test_retirement_and_done_pulse_are_end_to_end_differential (test_packet_executor_model.PacketExecutorTests.test_retirement_and_done_pulse_are_end_to_end_differential) ... ok +test_seeded_random_differential_and_scalar_oracle (test_packet_executor_model.PacketExecutorTests.test_seeded_random_differential_and_scalar_oracle) ... ok +test_seeded_single_byte_mutations_never_commit_state (test_packet_executor_model.PacketExecutorTests.test_seeded_single_byte_mutations_never_commit_state) ... ok +test_source_located_future_gap_table_is_explicit_and_non_executable (test_packet_executor_model.PacketExecutorTests.test_source_located_future_gap_table_is_explicit_and_non_executable) ... ok +test_stalls_and_output_backpressure_are_byte_exact (test_packet_executor_model.PacketExecutorTests.test_stalls_and_output_backpressure_are_byte_exact) ... ok +test_state_mismatch_rollback_after_successful_retirement (test_packet_executor_model.PacketExecutorTests.test_state_mismatch_rollback_after_successful_retirement) ... ok +test_truncation_requires_abort_and_extra_bytes_are_separate_frames (test_packet_executor_model.PacketExecutorTests.test_truncation_requires_abort_and_extra_bytes_are_separate_frames) ... ok +test_adversarial_jump_inverse_and_xor_backsolve_match_model (test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_adversarial_jump_inverse_and_xor_backsolve_match_model) ... ok +test_deref_and_jump_faults_match_the_executable_model (test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_faults_match_the_executable_model) ... ok +test_deref_and_jump_match_the_executable_model (test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_match_the_executable_model) ... ok +test_seeded_set_xor_mul_and_frame_faults (test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_seeded_set_xor_mul_and_frame_faults) ... ok +test_abort_and_reset_discard_same_edge_status_done_pulse (test_protocol_contract.ProtocolContractTests.test_abort_and_reset_discard_same_edge_status_done_pulse) ... ok +test_abort_discards_candidate_stream_transfer_and_sets_fault (test_protocol_contract.ProtocolContractTests.test_abort_discards_candidate_stream_transfer_and_sets_fault) ... ok +test_reset_discards_transaction_and_clears_fault (test_protocol_contract.ProtocolContractTests.test_reset_discards_transaction_and_clears_fault) ... ok +test_reset_during_status_preserves_pre_reset_pins_but_discards_byte (test_protocol_contract.ProtocolContractTests.test_reset_during_status_preserves_pre_reset_pins_but_discards_byte) ... ok +test_set_backpressure_holds_data_and_refuses_input (test_protocol_contract.ProtocolContractTests.test_set_backpressure_holds_data_and_refuses_input) ... ok +test_status_holds_each_byte_under_backpressure (test_protocol_contract.ProtocolContractTests.test_status_holds_each_byte_under_backpressure) ... ok +test_unknown_command_has_exactly_one_error_byte (test_protocol_contract.ProtocolContractTests.test_unknown_command_has_exactly_one_error_byte) ... ok +test_runner_profile_and_edges (test_scalar_step_oracle.ScalarStepOracleTests.test_runner_profile_and_edges) ... ok +test_seeded_field_differential_algorithms (test_scalar_step_oracle.ScalarStepOracleTests.test_seeded_field_differential_algorithms) ... ok + +---------------------------------------------------------------------- +Ran 288 tests in 11.371s + +OK diff --git a/results/b2-capability-contract-20260728/python_full_final.status b/results/b2-capability-contract-20260728/python_full_final.status new file mode 100644 index 0000000..cf9d0ce --- /dev/null +++ b/results/b2-capability-contract-20260728/python_full_final.status @@ -0,0 +1,2 @@ +exit=0 +duration_ms=11544 diff --git a/results/b2-capability-contract-20260728/rtl.command b/results/b2-capability-contract-20260728/rtl.command new file mode 100644 index 0000000..aa3c8bb --- /dev/null +++ b/results/b2-capability-contract-20260728/rtl.command @@ -0,0 +1 @@ +timeout 180s make -C test/packet_frontend sim diff --git a/results/b2-capability-contract-20260728/rtl.log b/results/b2-capability-contract-20260728/rtl.log new file mode 100644 index 0000000..3351f36 --- /dev/null +++ b/results/b2-capability-contract-20260728/rtl.log @@ -0,0 +1,31 @@ +make: Entering directory '/workspaces/mission-ce702ac6/lean-silicon/test/packet_frontend' +iverilog -g2012 -Wall -s tb_lsc1_packet_frontend -o tb_lsc1_packet_frontend.vvp ../../asic_core/rtl/lsc1_packet_rx.sv ../../asic_core/rtl/lsc1_packet_tx.sv ../../asic_core/rtl/gf2n_mul_bitstream.sv ../../asic_core/rtl/gf128_mul_bitstream.sv ../../asic_core/rtl/leanvm_b_stream_alu.sv ../../asic_core/rtl/lsc1_stream_adapter.sv ../../asic_core/rtl/lsc1_field_encoder.sv ../../asic_core/rtl/lsc1_packet_frontend.sv tb_lsc1_packet_frontend.sv +warning: Some design elements have no explicit time unit and/or + : time precision. This may cause confusing timing results. + : Affected design elements are: + : -- module gf128_mul_bitstream declared here: ../../asic_core/rtl/gf128_mul_bitstream.sv:9 + : -- module gf2n_mul_bitstream declared here: ../../asic_core/rtl/gf2n_mul_bitstream.sv:22 + : -- module leanvm_b_stream_alu declared here: ../../asic_core/rtl/leanvm_b_stream_alu.sv:28 + : -- module lsc1_field_encoder declared here: ../../asic_core/rtl/lsc1_field_encoder.sv:6 + : -- module lsc1_packet_frontend declared here: ../../asic_core/rtl/lsc1_packet_frontend.sv:6 + : -- module lsc1_packet_rx declared here: ../../asic_core/rtl/lsc1_packet_rx.sv:5 + : -- module lsc1_packet_tx declared here: ../../asic_core/rtl/lsc1_packet_tx.sv:4 + : -- module lsc1_stream_adapter declared here: ../../asic_core/rtl/lsc1_stream_adapter.sv:6 +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +vvp tb_lsc1_packet_frontend.vvp +PASS: LSC-1 Phase-3 packet frontend adversarial test +tb_lsc1_packet_frontend.sv:426: $finish called at 44410000 (1ps) +make: Leaving directory '/workspaces/mission-ce702ac6/lean-silicon/test/packet_frontend' diff --git a/results/b2-capability-contract-20260728/rtl.status b/results/b2-capability-contract-20260728/rtl.status new file mode 100644 index 0000000..e58b4f0 --- /dev/null +++ b/results/b2-capability-contract-20260728/rtl.status @@ -0,0 +1,2 @@ +exit_code=0 +duration_ms=136 diff --git a/results/b2-capability-contract-20260728/rtl_final.command b/results/b2-capability-contract-20260728/rtl_final.command new file mode 100644 index 0000000..aa3c8bb --- /dev/null +++ b/results/b2-capability-contract-20260728/rtl_final.command @@ -0,0 +1 @@ +timeout 180s make -C test/packet_frontend sim diff --git a/results/b2-capability-contract-20260728/rtl_final.log b/results/b2-capability-contract-20260728/rtl_final.log new file mode 100644 index 0000000..3351f36 --- /dev/null +++ b/results/b2-capability-contract-20260728/rtl_final.log @@ -0,0 +1,31 @@ +make: Entering directory '/workspaces/mission-ce702ac6/lean-silicon/test/packet_frontend' +iverilog -g2012 -Wall -s tb_lsc1_packet_frontend -o tb_lsc1_packet_frontend.vvp ../../asic_core/rtl/lsc1_packet_rx.sv ../../asic_core/rtl/lsc1_packet_tx.sv ../../asic_core/rtl/gf2n_mul_bitstream.sv ../../asic_core/rtl/gf128_mul_bitstream.sv ../../asic_core/rtl/leanvm_b_stream_alu.sv ../../asic_core/rtl/lsc1_stream_adapter.sv ../../asic_core/rtl/lsc1_field_encoder.sv ../../asic_core/rtl/lsc1_packet_frontend.sv tb_lsc1_packet_frontend.sv +warning: Some design elements have no explicit time unit and/or + : time precision. This may cause confusing timing results. + : Affected design elements are: + : -- module gf128_mul_bitstream declared here: ../../asic_core/rtl/gf128_mul_bitstream.sv:9 + : -- module gf2n_mul_bitstream declared here: ../../asic_core/rtl/gf2n_mul_bitstream.sv:22 + : -- module leanvm_b_stream_alu declared here: ../../asic_core/rtl/leanvm_b_stream_alu.sv:28 + : -- module lsc1_field_encoder declared here: ../../asic_core/rtl/lsc1_field_encoder.sv:6 + : -- module lsc1_packet_frontend declared here: ../../asic_core/rtl/lsc1_packet_frontend.sv:6 + : -- module lsc1_packet_rx declared here: ../../asic_core/rtl/lsc1_packet_rx.sv:5 + : -- module lsc1_packet_tx declared here: ../../asic_core/rtl/lsc1_packet_tx.sv:4 + : -- module lsc1_stream_adapter declared here: ../../asic_core/rtl/lsc1_stream_adapter.sv:6 +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +vvp tb_lsc1_packet_frontend.vvp +PASS: LSC-1 Phase-3 packet frontend adversarial test +tb_lsc1_packet_frontend.sv:426: $finish called at 44410000 (1ps) +make: Leaving directory '/workspaces/mission-ce702ac6/lean-silicon/test/packet_frontend' diff --git a/results/b2-capability-contract-20260728/rtl_final.status b/results/b2-capability-contract-20260728/rtl_final.status new file mode 100644 index 0000000..16470f2 --- /dev/null +++ b/results/b2-capability-contract-20260728/rtl_final.status @@ -0,0 +1,2 @@ +exit=0 +duration_ms=129 diff --git a/results/b2-capability-contract-20260728/run.sh b/results/b2-capability-contract-20260728/run.sh new file mode 100755 index 0000000..a7fe41c --- /dev/null +++ b/results/b2-capability-contract-20260728/run.sh @@ -0,0 +1,35 @@ +#!/usr/bin/env bash +# Reproduce the bounded Phase-B capability-contract evidence from repo root. +set -u -o pipefail + +out=results/b2-capability-contract-20260728 +mkdir -p "$out" +printf '%s\n' "baseline_commit=$(git rev-parse fda85f5efc6f5b460d72204b4d9c0d882960ec29)" > "$out/metadata.txt" +printf '%s\n' "baseline_tree=$(git rev-parse fda85f5efc6f5b460d72204b4d9c0d882960ec29^{tree})" >> "$out/metadata.txt" +printf '%s\n' "head=$(git rev-parse HEAD)" >> "$out/metadata.txt" +printf '%s\n' "head_tree=$(git rev-parse HEAD^{tree})" >> "$out/metadata.txt" + +run() { + name=$1 + shift + printf '%q ' "$@" > "$out/$name.command" + printf '\n' >> "$out/$name.command" + start=$(date +%s%N) + "$@" > "$out/$name.log" 2>&1 + status=$? + end=$(date +%s%N) + printf 'exit_code=%s\nduration_ms=%s\n' "$status" "$(((end - start) / 1000000))" > "$out/$name.status" + return "$status" +} + +rtl=(asic_core/rtl/lsc1_packet_rx.sv asic_core/rtl/lsc1_packet_tx.sv + asic_core/rtl/gf2n_mul_bitstream.sv asic_core/rtl/gf128_mul_bitstream.sv + asic_core/rtl/leanvm_b_stream_alu.sv asic_core/rtl/lsc1_stream_adapter.sv + asic_core/rtl/lsc1_field_encoder.sv asic_core/rtl/lsc1_packet_frontend.sv) + +run model timeout 180s python3 -m unittest sim.test_packet_frontend_rtl_differential -v || exit $? +run rtl timeout 180s make -C test/packet_frontend sim || exit $? +run mutation timeout 180s make -C test/packet_frontend mutation || exit $? +run netlist timeout 180s yosys -p "read_verilog -sv ${rtl[*]}; hierarchy -check -top lsc1_packet_frontend; proc; memory; flatten; opt; check; write_verilog -noattr $out/lsc1_packet_frontend.netlist.v; stat" || exit $? +run equivalence timeout 180s yosys -p "read_verilog -formal -sv ${rtl[*]}; hierarchy -top lsc1_packet_frontend; proc; memory; flatten; opt; rename lsc1_packet_frontend gold; read_verilog -formal $out/lsc1_packet_frontend.netlist.v; rename lsc1_packet_frontend gate; equiv_make gold gate equiv; hierarchy -top equiv; prep -top equiv; equiv_simple; equiv_status -assert" || exit $? +sha256sum "$out"/*.command "$out"/*.log "$out"/*.status "$out"/metadata.txt "$out"/lsc1_packet_frontend.netlist.v > "$out/SHA256SUMS" diff --git a/sim/lsc1_transaction.py b/sim/lsc1_transaction.py index a66b43f..01db97f 100644 --- a/sim/lsc1_transaction.py +++ b/sim/lsc1_transaction.py @@ -47,7 +47,11 @@ CRC_BYTES = 4 MAX_PAYLOAD_BYTES = 256 DEVICE_ID = 0x4C534331 # "LSC1" -DEVICE_FEATURES = 0b111 # both profiles + BLAKE3 service offload +# Phase-B's advertised device envelope is the interpreter-compatible scalar +# packet subset. The executable model remains a semantic oracle for the full +# frozen protocol below; its negotiation reply deliberately reports only the +# capability boundary implemented by the shipped packet RTL. +DEVICE_FEATURES = 0b010 CELL_BYTES = 17 WRITE_BYTES = 20 diff --git a/sim/test_lsc1_transaction.py b/sim/test_lsc1_transaction.py index 5d7d636..2258b7e 100644 --- a/sim/test_lsc1_transaction.py +++ b/sim/test_lsc1_transaction.py @@ -586,7 +586,7 @@ class ProfileTests(unittest.TestCase): def test_default_profile_is_interpreter_compatible(self) -> None: self.assertIs(Lsc1Endpoint().profile, Profile.INTERPRETER_COMPAT) - def test_negotiate_reports_the_device_envelope(self) -> None: + def test_negotiate_reports_the_phase_b_device_envelope(self) -> None: endpoint = Lsc1Endpoint() reply = exchange(endpoint, lsc1.build_negotiate(profile=Profile.FORWARD_ONLY)) self.assertIs(reply.status, Status.OK) @@ -599,6 +599,7 @@ def test_negotiate_reports_the_device_envelope(self) -> None: self.assertEqual(reader.u32(), lsc1.DEVICE_FEATURES) self.assertEqual(reader.u32(), lsc1.DEVICE_ID) reader.done() + self.assertEqual(lsc1.DEVICE_FEATURES, 0b010) self.assertIs(endpoint.profile, Profile.FORWARD_ONLY) def test_negotiate_rejects_a_version_window_that_excludes_v1(self) -> None: diff --git a/sim/test_packet_frontend_rtl_differential.py b/sim/test_packet_frontend_rtl_differential.py index 46447b6..a45ef35 100644 --- a/sim/test_packet_frontend_rtl_differential.py +++ b/sim/test_packet_frontend_rtl_differential.py @@ -76,7 +76,11 @@ def rtl_exchange(self, frame: protocol.RequestFrame) -> bytes: def test_seeded_set_xor_mul_and_frame_faults(self) -> None: randomizer = random.Random(0x4C534331) - frames: list[protocol.RequestFrame] = [protocol.build_status_query()] + frames: list[protocol.RequestFrame] = [ + protocol.build_status_query(), + # Phase-B's advertised profile. + protocol.build_negotiate(profile=protocol.Profile.INTERPRETER_COMPAT), + ] for txn_id in range(1, 7): left = randomizer.getrandbits(128) right = randomizer.getrandbits(128) diff --git a/test/packet_frontend/Makefile b/test/packet_frontend/Makefile index fad6306..3c1fda9 100644 --- a/test/packet_frontend/Makefile +++ b/test/packet_frontend/Makefile @@ -57,7 +57,15 @@ mutation: echo "BAD_LENGTH-order mutation unexpectedly survived" >&2; exit 1; \ fi; \ grep -q "status got=87 expected=83" "$$d/length.out"; \ - echo "PASS: BUSY, SET value, RETIRE ID, ABORT, and length-order mutations were detected" + cp ../../asic_core/rtl/lsc1_packet_frontend.sv "$$d/lsc1_packet_frontend.sv"; \ + sed -i.bak 's/frame_payload\[16 +: 8\] != 1/1'"'"'b0/' "$$d/lsc1_packet_frontend.sv"; \ + iverilog -g2012 -s tb_lsc1_packet_frontend -o "$$d/profile.vvp" \ + "$$d"/*.sv tb_lsc1_packet_frontend.sv; \ + if vvp "$$d/profile.vvp" >"$$d/profile.out" 2>&1; then \ + echo "FORWARD_ONLY negotiation mutation unexpectedly survived" >&2; exit 1; \ + fi; \ + grep -q "status got=00 expected=86" "$$d/profile.out"; \ + echo "PASS: BUSY, SET value, RETIRE ID, ABORT, length-order, and profile mutations were detected" differential-mutation: @d=$$(mktemp -d); trap 'rm -rf "$$d"' EXIT; \ diff --git a/test/packet_frontend/tb_lsc1_packet_frontend.sv b/test/packet_frontend/tb_lsc1_packet_frontend.sv index 1ba388c..ba7fff5 100644 --- a/test/packet_frontend/tb_lsc1_packet_frontend.sv +++ b/test/packet_frontend/tb_lsc1_packet_frontend.sv @@ -183,7 +183,7 @@ module tb_lsc1_packet_frontend; rst_n = 1; repeat (2) @(posedge clk); - // Negotiate the only profile this integrated RTL currently advertises. + // Phase-B advertises and accepts interpreter-compatible only. clear_payload(); payload[0] = 1; payload[1] = 1; payload[2] = 1; send_frame(1, 8'h10, 0, 7, 0); @@ -198,6 +198,12 @@ module tb_lsc1_packet_frontend; $fatal(1, "NEGOTIATE capability payload mismatch"); wait_response(8'h00); + // A recognized but unadvertised profile must not become active. + clear_payload(); + payload[0] = 1; payload[1] = 1; payload[2] = 0; + send_frame(1, 8'h10, 0, 7, 0); + wait_response(8'h86); + // STATUS_QUERY is a non-mutating packet response. clear_payload(); send_frame(1, 8'h13, 0, 0, 0); From 4a4d8cdd9abd56121ae5c8d84df1f1bc42f8ba4a Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Tue, 28 Jul 2026 18:56:56 +0200 Subject: [PATCH 2/9] Fix device profile negotiation contract --- SHA256SUMS | 64 +++++++++++++++++--- docs/LSC1_TRANSACTION_PROTOCOL.md | 9 +-- host/runtime.py | 4 +- sim/lsc1_transaction.py | 25 ++++++-- sim/test_host_runtime.py | 1 + sim/test_lsc1_protocol_doc.py | 2 +- sim/test_lsc1_transaction.py | 41 ++++++++++--- sim/test_packet_frontend_rtl_differential.py | 3 + 8 files changed, 120 insertions(+), 29 deletions(-) diff --git a/SHA256SUMS b/SHA256SUMS index b3f922e..ea5625c 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -30,7 +30,7 @@ ac44a1838e7da255ed93835cc0de01e1751efc05f78cf9f8b8145cc963d6836a ./docs/DECISIO b989d03d5e6c7dd3c1c11bf40277da8d700463601f23c8c51787f8ac371bc596 ./docs/FULL_CORE_PROTOCOL.md 42e5b0f0b0f98d2c7c89cbc5db737b1d1f2dd02685f4f07b98ea709a7f9e7690 ./docs/HOST_RUNTIME.md 59832e723e7c3e52b1e23ce70fb30760b6221b5e135c54ee5556775b7cf792f3 ./docs/LSC1_PROTOCOL.md -549ecdb6797df667096e3081f26357ff3aa33de323b65aae7445f77902d017a9 ./docs/LSC1_TRANSACTION_PROTOCOL.md +810ec59fd2a11cba3334c58f0f81968472d77e6f8c3053ca28c9adfa4d43fd36 ./docs/LSC1_TRANSACTION_PROTOCOL.md c41da7c4e22cc809e471da2bfcce176505db234c3b48e9c01ff20b8bcaef4b29 ./docs/M0_MANAGER.md 3917ceaaac9cb7fbfd7ac07d6f980ff46a9103255c0859d5b47fefe691c726c3 ./docs/M2_CONTROLLER.md 161cf4d25dcec4f21915e8b69ecdd2a929568bb8555bd613d0b96db215ce5be8 ./docs/MINCORE_UART_HOST.md @@ -42,7 +42,7 @@ b81b89574ed84c67b64ae7b56001bf9d03b9d66be2bed7977d8adc715481eafb ./docs/PROTOCO 0d787acfaa683bf07cedea98ba403d51079593b50f84b48ee199a479cc35b099 ./docs/SEMANTICS.md 6ec7c4c80628391da706725be1a2361ae8eb2ee014fb4cde6dae31c53f13e9f0 ./docs/SEMANTIC_DIFFERENCES.md 02e8a5b52b341390f008ff8bc62f5d2d982b23adb8b26cb73ef3b07dddeed807 ./docs/SOURCE_AUDIT.md -63a4e673f49e169d587cb2302547cc251add4531c62908a38dadc169eaa312d3 ./docs/STATUS.md +e9514971b2fe3a432d80b191ab4cf53be3b32f5a5b660802ff0a2758ffe9fe27 ./docs/STATUS.md 9c2582c40fbd9a4e2b163abed784f5a6c82b2cb3136c37a4123a0ba6584f6136 ./docs/TAPEOUT.md 0d976224f3f8c1198e8f0c51c0f4d022bd7c6f3dfcd36653f6d82bdfe2ae36c4 ./docs/THEOREM_INVENTORY.md e61e74c84bce2ec92ef18520eb134299f9341e63d3ec43cdbe0ef4879d22ba37 ./docs/ULX3S_SMOKE_AND_UART.md @@ -109,7 +109,7 @@ de09f085c4774abffbfbc6821b57f37ae1507614bab2c95007257732878bdb56 ./host/blake3_ c22e2dd6edcd014dd803fd1ea630ae063aeee86e192afd6c34b4ac81efa73daa ./host/lean_compiler_adapter.py 809335481a0314cc5231d26931bfdef14343cdae5fdf6025576ea1ab17dcac89 ./host/memory.py 451f3d686ce47b16d81de2f85d36a52231c99a1b47c261475c0cb4134a09d777 ./host/protocol.py -f3b64010406928c48e879ad0ec9a539acec43971570a8a5b4ee25024a4b52502 ./host/runtime.py +25034b46f23a72f3f5add04a398a8a8bb0858a293be5d433601502733ff84f32 ./host/runtime.py effcad52a728f7c1cc4b463ea8d7bc6cc6350ddb6daf836f4adc601f714485ab ./info.yaml 68a4209dcbdcc663454d02012642fa7b5a3476a13e363982fc9236e89c27a6b7 ./lean/LeanVMBMinCore.lean c09c6cf1a82598ec2c0e5f6ecf58852c8c27554f7036f36baadf027067a55f4e ./lean/LeanVMBMinCore/Address.lean @@ -132,6 +132,50 @@ d1f2dfa6bf564b9cf248838630eb92efd55f03e9ab8bf5e7dfec3d318b9f0f29 ./lean/lakefil d59a11f361717058c708574a6f41d9be99da29cfcc3b0c033045ce6f0e57a5d5 ./planning/OWNERSHIP.md a19467b08293daf14a67ccd8f0efbcddfeb3854c38525acd7fcfd98f01552587 ./planning/milestones.yaml fbce601088163a30bf024083852ec3d72a1dd2ab12a22a9ea1fc8809cadafb93 ./requirements.txt +6c11a3bd4eb64e6c319620cd99d9cfbb9ae6cb7e74be09c282dd5267e15610af ./results/b2-capability-contract-20260728/README.md +e5ecbda1857530b195f240b68191b5b1c5ae84ae6460f8bf4c6f0a9f352e4f34 ./results/b2-capability-contract-20260728/SHA256SUMS +967cd83720a145d1daba23a926a1b22eabc4e83d7b7c337cf3512f3df944c535 ./results/b2-capability-contract-20260728/blake3_official.command +42b629a692f30c9bfb0fcff81a5eb4631efb576c1355485035dd6d8c50131631 ./results/b2-capability-contract-20260728/blake3_official.log +c4c41bd36c74ae8036f7f04e842e6e165b94947210de3fbb2ff0fc6a7d212aa6 ./results/b2-capability-contract-20260728/blake3_official.status +8ed2f76d0f3c4e2f426b94871ba32c169b2d3db054baf69aaec18ee7c88a97d8 ./results/b2-capability-contract-20260728/equivalence.command +c79afc83ad60a71e82e8a7fa6b2af5d627599ff6c387452e3127ef8dc0d5c8f7 ./results/b2-capability-contract-20260728/equivalence.log +b55da4864ed1d5b5074f282e6bb197c72e378c1f95e3ae23067f00cf3d1071bf ./results/b2-capability-contract-20260728/equivalence.status +efbf348e9a19221a83c3de23fc958594ef2138f22817a951b47420d734550a59 ./results/b2-capability-contract-20260728/equivalence_retry.command +95562d2b0efd62f3caca735841da6ebc3f1456ee777faaabb7fd6165dd08ee61 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./results/b2-capability-contract-20260728/mutation_final.status +67eeb3e7508368a86d6be56bef6797740a87650f1feca9ea43a15f0cc612c1ec ./results/b2-capability-contract-20260728/netlist.command +99638ad3d2222677392e42d3a011ef253ca24376fa59f1402c40c200d84357a1 ./results/b2-capability-contract-20260728/netlist.log +7e6b5e7f24bd34bdc2d64ef0430123721cd458259f77e97076a7c71e0cdc6aff ./results/b2-capability-contract-20260728/netlist.status +5e458fe7b8a6fd2efaa0d102ef3b6761d28a45624e397ff19bbedfd61dc402a7 ./results/b2-capability-contract-20260728/netlist_900.command +57b603f2145f71ea57f6830108696d4e030530235d3cecf5d7070036c3021b98 ./results/b2-capability-contract-20260728/netlist_900.log +14ab37de2335111d8b7e7c731bb293bb6a9fea6dfa29b72f31696b9c611dd5e5 ./results/b2-capability-contract-20260728/netlist_900.status +c6bede227931eebaeb2cb022457155b414ff5de4642f48748e27f817a8d56c49 ./results/b2-capability-contract-20260728/python_full.command +498b59ec0a8d38ae9fb00b969dab98412dc9772d767c966238b5c4562c573b36 ./results/b2-capability-contract-20260728/python_full.log +d6f20552131049cb665bbd0449627ef0ec0d6594f1de39feae3e4e9b7ffe21f8 ./results/b2-capability-contract-20260728/python_full.status +3f29544634cb7c34c5681fb90cb36f818a649ae5ac8e74df372f15806081d43f ./results/b2-capability-contract-20260728/python_full_final.command +3f3a9d48fd3bfa56895994fed2a415312f4713bb6acbe81144ec9c2ab15f8757 ./results/b2-capability-contract-20260728/python_full_final.log +c0086458ffdc5a2d5f3f704c2882f7cebdc0eb6178b3bd0517ef25ce8f6083fd ./results/b2-capability-contract-20260728/python_full_final.status +42c1c9680f854883922eef8493abd0e7d3f7dbe293f40b5f7c639d72761a8ff2 ./results/b2-capability-contract-20260728/rtl.command +881d0c9e93dd2f29354bf42351533bfe1b571eb3f4e4f0198d92dc51fe4c064f ./results/b2-capability-contract-20260728/rtl.log +5ac891ed2dcc8e0eb2408aa15faef2b83d780baa8de02c2578b51494cff17d25 ./results/b2-capability-contract-20260728/rtl.status +42c1c9680f854883922eef8493abd0e7d3f7dbe293f40b5f7c639d72761a8ff2 ./results/b2-capability-contract-20260728/rtl_final.command +881d0c9e93dd2f29354bf42351533bfe1b571eb3f4e4f0198d92dc51fe4c064f ./results/b2-capability-contract-20260728/rtl_final.log +3916d13f98a1f4f76582598a2c2b98f39998cd02a9e2e117c47f5aced1b62915 ./results/b2-capability-contract-20260728/rtl_final.status +256ef5dd4c4cafd51370b52e2e8d02487cfea78f04304c6081a13dbc1b104787 ./results/b2-capability-contract-20260728/run.sh 73c8c4939d05b6fd2367c8fc992e8386ee1b505499abfd1050b8286022589f9c ./results/fpga-harness-inventory-20260725/README.md 13c80bbee4874817634c3edcef6a6a687fd4e6d1d5412c026fe9b314388eeb7c ./results/fpga-harness-inventory-20260725/fpga-boundary.log 9a271f2a916b0b6ee6cecb2426f0b3206ef074578be55d9bc94f6f3fe3ab86aa ./results/fpga-harness-inventory-20260725/fpga-boundary.status @@ -307,7 +351,7 @@ e3329b92c1baf92fa161eb36a067e2ccbe73342fe8e419c315fbadfef9729b7d ./results/ulx3 7d50c170f623ccc6911a48dd18455bc1011a2be335a9997c6d85355d0c72e63d ./results/ulx3s-smoke-uart-20260725/yosys_uart.log 2ce193a38f1a8c96ec1cbfe2c8b7555d025944cb450859c3e09dd2cbab66a03c ./sim/__init__.py 56f95ab49ce35604c5b30cd95d142a4d630b2d503af5398b1f975ef84492b48c ./sim/cycle_model.py -3ebec652b76c20903fde598d748dbaff596cbc3f962f80ca23f30b31e1327da5 ./sim/lsc1_transaction.py +2a1871001ed3c296926b0f343bd8fd32176da7959628786bea51d7772653b633 ./sim/lsc1_transaction.py 12dd1aca968efeafb9ffa7015f849607c96fb6e14ad2aa8f65938dd254ef6f49 ./sim/model.py dee5dc820b96f24d4dbd752b17aaad3c8e025d519c043dfd1ab7c46be5600245 ./sim/packet_executor_model.py 659496fd9f21edafb7c4c12500d9b623bd0ea063808dc9494053ad923102dc31 ./sim/protocol_contract.py @@ -316,12 +360,12 @@ d14a3e8aed08ece9ce5d9ac4ddc2d29bf218dcb4626592a11ff63eb36fe454dc ./sim/test_ato 45dff2ed4c9b579c66524abc7a0207d84c47421de401439b9cbd7826f0688b3b ./sim/test_blake3_service.py fd9ac000dc3aa8f6e0a4080a81111ffcbbb8d8987113f6711c409f6d3f702003 ./sim/test_conformance_corpus.py a2fda9c21da5f3301de411060ffbb644c08c4c5e4c103e036b3834e2922ce10a ./sim/test_cycle_model.py -002325ca4bcceb7b5ec19e8b279df399661ac368b118eb160d97a6a450fe74e7 ./sim/test_host_runtime.py -f1ab500117ae9d7a20a9258a32dbc7271b4d0ec5f57d3fc058ff426ba2289a40 ./sim/test_lsc1_protocol_doc.py -2c19d774213f293a361de949f7cecc99b35111cc9afe5da73bac924d02b2747d ./sim/test_lsc1_transaction.py +b9f2bb2a808d51ac5ee60ca6c8e7fb28db1a2c33535ff32c8eaffd7318cf2730 ./sim/test_host_runtime.py +e3e40af3b8a4fc553482ebbe0a23ad928d0ff7100c5becdf7b62005c25b6d9f5 ./sim/test_lsc1_protocol_doc.py +87d2ad6388c41ebccebb0486bec158b6fb01ebcc7f1fab077f8ef7ee16bf9efd ./sim/test_lsc1_transaction.py 3e8c789984dbc6b6150881f9aa823aaaef80e4e8b90eb329e9e9e351bfbe9b06 ./sim/test_model.py b6f8a2af3bdba662f41be970f3a43ed6e5a9f4ec0cb69a11b2087b2acfa8b691 ./sim/test_packet_executor_model.py -cfad76ffba1453cc8c7f76dd688d55201aa4f9b83fbd726ab77b72d201e0a62a ./sim/test_packet_frontend_rtl_differential.py +ddae3180afed1491bcc6f0eafa80ab4b75d38786dcdf964cbfd4377741d1966e ./sim/test_packet_frontend_rtl_differential.py c128acb44fa334177d240255f997d4e245d6a996db5938d65deca48962ebce79 ./sim/test_protocol_contract.py 8486656729b8978f8059189845dff97dad929befde94cb3cb89ad9febf08753b ./sim/test_scalar_step_oracle.py d8e83531981677f629877cbeff643e07e169f8f6e8cf3ecd7c1b0c417a79b614 ./src/gf128_mul_bitstream.sv @@ -331,8 +375,8 @@ bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b ./src/leanvm_b e97452e6444238c80a86811f86d892a0db6e79e498d00afc638387f8656ef28c ./src/tt_um_leanvm_b_mincore.sv a3574d9d454d7b7580d2dcdc2801013a7648c48358a3f4a90a5c876ae9791331 ./src/user_config.tcl 69cd41bda612b601228752f516472df0f3be356de2f327ce4bbaaccb588edcf7 ./test/Makefile -89275e550ed74ce4b6fd8dc55c7fbf92b95ff5c26cb4f5a9315e4ac1c20a0192 ./test/packet_frontend/Makefile -da38796aaa0eb9785e858d9e14bdcf246790410c0b79baa349ff8afa3d14b5f4 ./test/packet_frontend/tb_lsc1_packet_frontend.sv +2b5c167fcbbbc265e3aef203c8ffc59b0c6c4db8e7d180dc45133606414bb000 ./test/packet_frontend/Makefile +d54a6f18a9c81353492801e51de435e47885fbbd3faae8c955cde0774b66eb2f ./test/packet_frontend/tb_lsc1_packet_frontend.sv f1bf4caf7438081d289ea48ebfcbed8f278866a664636dc810ea5e2c1b4410c3 ./test/packet_frontend/tb_lsc1_packet_vector.sv d0c03fb87fe5f08fbec435d485e4dd14c96d164e90b0e8b0ed8980cf27e8c077 ./test/tb_m2_scalar_controller.sv 2ea0bf23432e7c9471b09d7dac47b1b548f37d746a8cdf1fc9bd8128cd2a8018 ./test/tb_packet_uart_bridge.sv diff --git a/docs/LSC1_TRANSACTION_PROTOCOL.md b/docs/LSC1_TRANSACTION_PROTOCOL.md index f260320..cdc78d5 100644 --- a/docs/LSC1_TRANSACTION_PROTOCOL.md +++ b/docs/LSC1_TRANSACTION_PROTOCOL.md @@ -496,10 +496,11 @@ profile, `2` BLAKE3 service offload. The Phase-B packet RTL advertises only `0x00000002`: `INTERPRETER_COMPAT`. It rejects `FORWARD_ONLY` negotiation and does not -implement BLAKE3 service offload. The executable model remains the frozen -semantic oracle for the broader profile and service contract, but reports this -Phase-B device envelope so model/RTL negotiation responses agree for the -supported interpreter-compatible profile. RTL rejects `FORWARD_ONLY`. +implement BLAKE3 service offload. `Lsc1Endpoint` is the device-facing +executable endpoint and also rejects `FORWARD_ONLY` with `BAD_PROFILE` +(`0x86`). `Lsc1OracleEndpoint` is a separate profile-wide semantic oracle; it +advertises its broader `0x00000007` envelope and is not a device or RTL +equivalence claim. RTL rejects `FORWARD_ONLY`. ### 8.5 `INFO` (status query) — 20 bytes diff --git a/host/runtime.py b/host/runtime.py index c730907..8513d6b 100644 --- a/host/runtime.py +++ b/host/runtime.py @@ -295,7 +295,9 @@ def _negotiate(self) -> None: bytes((protocol.PROTOCOL_VERSION, int(self.profile))) + protocol.u16le(protocol.MAX_PAYLOAD_BYTES) + bytes((protocol.INDEX_BITS, 0)) - + protocol.u32le(protocol.DEVICE_FEATURES) + + protocol.u32le( + getattr(self.endpoint, "advertised_features", protocol.DEVICE_FEATURES) + ) + protocol.u32le(protocol.DEVICE_ID) ) if reply.payload != expected: diff --git a/sim/lsc1_transaction.py b/sim/lsc1_transaction.py index 01db97f..97c6468 100644 --- a/sim/lsc1_transaction.py +++ b/sim/lsc1_transaction.py @@ -48,10 +48,9 @@ MAX_PAYLOAD_BYTES = 256 DEVICE_ID = 0x4C534331 # "LSC1" # Phase-B's advertised device envelope is the interpreter-compatible scalar -# packet subset. The executable model remains a semantic oracle for the full -# frozen protocol below; its negotiation reply deliberately reports only the -# capability boundary implemented by the shipped packet RTL. +# packet subset. DEVICE_FEATURES = 0b010 +ORACLE_FEATURES = 0b111 CELL_BYTES = 17 WRITE_BYTES = 20 @@ -996,15 +995,22 @@ class LaneRecord: class Lsc1Endpoint: - """Byte-lane LSC-1 v1 endpoint: framing, transaction, and service states. + """Device-facing byte-lane LSC-1 v1 endpoint. The endpoint accepts request bytes only while it has no response bytes outstanding, which is how "one outstanding transaction or service request" is enforced on the wire. ``ABORT`` and reset are synchronous and take priority over a same-edge candidate transfer, matching the byte/cycle contract already recorded in ``docs/PROTOCOL_BYTE_CYCLE_AUDIT.md``. + + Accepted profiles and advertised features are kept together so this device + cannot advertise a smaller envelope than it accepts. Use + :class:`Lsc1OracleEndpoint` for profile-wide semantic exploration. """ + supported_profiles = frozenset((Profile.INTERPRETER_COMPAT,)) + advertised_features = DEVICE_FEATURES + def __init__(self) -> None: self._reset() @@ -1167,6 +1173,8 @@ def _handle_negotiate(self, request: _DecodedRequest) -> None: raise ProtocolFault(Status.BAD_STATE) if not request.version_min <= PROTOCOL_VERSION <= request.version_max: raise ProtocolFault(Status.BAD_VERSION) + if request.profile not in self.supported_profiles: + raise ProtocolFault(Status.BAD_PROFILE) self.profile = request.profile payload = ( u8(PROTOCOL_VERSION) @@ -1174,7 +1182,7 @@ def _handle_negotiate(self, request: _DecodedRequest) -> None: + u16le(MAX_PAYLOAD_BYTES) + u8(INDEX_BITS) + u8(0) - + u32le(DEVICE_FEATURES) + + u32le(self.advertised_features) + u32le(DEVICE_ID) ) self._emit(ResponseFrame(Status.OK, payload)) @@ -1284,6 +1292,13 @@ def _handle_retire(self, request: _DecodedRequest) -> None: self._emit(ResponseFrame(Status.RETIRED, payload)) +class Lsc1OracleEndpoint(Lsc1Endpoint): + """Profile-wide semantic oracle, separate from the Phase-B device model.""" + + supported_profiles = frozenset(Profile) + advertised_features = ORACLE_FEATURES + + _STATE_CODES = { TxnState.IDLE: 0x00, TxnState.RESULT_PENDING: 0x01, diff --git a/sim/test_host_runtime.py b/sim/test_host_runtime.py index 2a06e6a..5a5e0a6 100644 --- a/sim/test_host_runtime.py +++ b/sim/test_host_runtime.py @@ -997,6 +997,7 @@ def test_forward_only_refuses_the_same_back_solve(self): {"op": "Mul", "a": 2, "b": 3, "c": 4}, ), profile=protocol.Profile.FORWARD_ONLY, + endpoint=protocol.Lsc1OracleEndpoint(), ) result = runtime.run() self.assertEqual(result.terminal, "fault") diff --git a/sim/test_lsc1_protocol_doc.py b/sim/test_lsc1_protocol_doc.py index 0b0970a..e990d65 100644 --- a/sim/test_lsc1_protocol_doc.py +++ b/sim/test_lsc1_protocol_doc.py @@ -634,7 +634,7 @@ class DocumentSemanticsTests(unittest.TestCase): FP = 64 def _negotiated(self, profile: Profile) -> Lsc1Endpoint: - endpoint = Lsc1Endpoint() + endpoint = lsc1.Lsc1OracleEndpoint() reply = measure(endpoint, lsc1.build_negotiate(profile=profile)) self.assertIs(reply.status, Status.OK) return endpoint diff --git a/sim/test_lsc1_transaction.py b/sim/test_lsc1_transaction.py index 2258b7e..57a327a 100644 --- a/sim/test_lsc1_transaction.py +++ b/sim/test_lsc1_transaction.py @@ -75,8 +75,10 @@ def exchange(endpoint: Lsc1Endpoint, frame: lsc1.RequestFrame) -> lsc1.ResponseF return lsc1.decode_response(response) -def negotiated(profile: Profile) -> Lsc1Endpoint: - endpoint = Lsc1Endpoint() +def negotiated( + profile: Profile, endpoint_type: type[Lsc1Endpoint] = Lsc1Endpoint, +) -> Lsc1Endpoint: + endpoint = endpoint_type() reply = exchange(endpoint, lsc1.build_negotiate(profile=profile)) assert reply.status is Status.OK return endpoint @@ -586,13 +588,19 @@ class ProfileTests(unittest.TestCase): def test_default_profile_is_interpreter_compatible(self) -> None: self.assertIs(Lsc1Endpoint().profile, Profile.INTERPRETER_COMPAT) - def test_negotiate_reports_the_phase_b_device_envelope(self) -> None: + def test_device_endpoint_rejects_unadvertised_forward_only_negotiation(self) -> None: endpoint = Lsc1Endpoint() reply = exchange(endpoint, lsc1.build_negotiate(profile=Profile.FORWARD_ONLY)) + self.assertIs(reply.status, Status.BAD_PROFILE) + self.assertIs(endpoint.profile, Profile.INTERPRETER_COMPAT) + + def test_device_endpoint_reports_the_phase_b_device_envelope(self) -> None: + endpoint = Lsc1Endpoint() + reply = exchange(endpoint, lsc1.build_negotiate(profile=Profile.INTERPRETER_COMPAT)) self.assertIs(reply.status, Status.OK) reader = lsc1._Reader(reply.payload) self.assertEqual(reader.u8(), PROTOCOL_VERSION) - self.assertEqual(reader.u8(), int(Profile.FORWARD_ONLY)) + self.assertEqual(reader.u8(), int(Profile.INTERPRETER_COMPAT)) self.assertEqual(reader.u16(), MAX_PAYLOAD_BYTES) self.assertEqual(reader.u8(), lsc1.INDEX_BITS) self.assertEqual(reader.u8(), 0) @@ -600,6 +608,19 @@ def test_negotiate_reports_the_phase_b_device_envelope(self) -> None: self.assertEqual(reader.u32(), lsc1.DEVICE_ID) reader.done() self.assertEqual(lsc1.DEVICE_FEATURES, 0b010) + self.assertIs(endpoint.profile, Profile.INTERPRETER_COMPAT) + + def test_oracle_endpoint_keeps_the_broader_profile_contract(self) -> None: + endpoint = lsc1.Lsc1OracleEndpoint() + reply = exchange(endpoint, lsc1.build_negotiate(profile=Profile.FORWARD_ONLY)) + self.assertIs(reply.status, Status.OK) + reader = lsc1._Reader(reply.payload) + reader.u8() + self.assertEqual(reader.u8(), int(Profile.FORWARD_ONLY)) + reader.u16() + reader.u8() + reader.u8() + self.assertEqual(reader.u32(), lsc1.ORACLE_FEATURES) self.assertIs(endpoint.profile, Profile.FORWARD_ONLY) def test_negotiate_rejects_a_version_window_that_excludes_v1(self) -> None: @@ -619,7 +640,7 @@ def test_negotiate_rejects_an_unknown_profile(self) -> None: self.assertIs(reply.status, Status.BAD_PROFILE) def test_a_request_naming_the_other_profile_is_rejected(self) -> None: - endpoint = negotiated(Profile.FORWARD_ONLY) + endpoint = negotiated(Profile.FORWARD_ONLY, lsc1.Lsc1OracleEndpoint) reply = exchange(endpoint, simple_xor()) self.assertIs(reply.status, Status.BAD_PROFILE) self.assertIsNone(endpoint.staged) @@ -731,7 +752,7 @@ def test_forward_only_profile_refuses_any_absent_operand(self) -> None: (ABSENT, ABSENT, Cell(True, 3)), ): with self.subTest(cells=cells): - endpoint = negotiated(Profile.FORWARD_ONLY) + endpoint = negotiated(Profile.FORWARD_ONLY, lsc1.Lsc1OracleEndpoint) frame = lsc1.build_binary_op( Opcode.XOR, txn_id=1, pc=0, fp=64, profile=Profile.FORWARD_ONLY, offsets=(1, 2, 3), cells=cells, @@ -741,7 +762,7 @@ def test_forward_only_profile_refuses_any_absent_operand(self) -> None: self.assertIsNone(endpoint.staged) def test_forward_only_profile_accepts_a_fully_supplied_operand_pair(self) -> None: - endpoint = negotiated(Profile.FORWARD_ONLY) + endpoint = negotiated(Profile.FORWARD_ONLY, lsc1.Lsc1OracleEndpoint) frame = lsc1.build_binary_op( Opcode.XOR, txn_id=1, pc=0, fp=64, profile=Profile.FORWARD_ONLY, offsets=(1, 2, 3), cells=(Cell(True, 6), Cell(True, 3), ABSENT), @@ -858,7 +879,11 @@ def deref( pc: int = 5, fp: int = 64, ) -> tuple[Lsc1Endpoint, lsc1.ResponseFrame]: - endpoint = negotiated(profile) + endpoint_type = ( + lsc1.Lsc1OracleEndpoint + if profile is Profile.FORWARD_ONLY else Lsc1Endpoint + ) + endpoint = negotiated(profile, endpoint_type) frame = lsc1.build_deref( opcode, txn_id=1, pc=pc, fp=fp, profile=profile, alpha=0, beta=2, gamma=3, diff --git a/sim/test_packet_frontend_rtl_differential.py b/sim/test_packet_frontend_rtl_differential.py index a45ef35..4fd14ba 100644 --- a/sim/test_packet_frontend_rtl_differential.py +++ b/sim/test_packet_frontend_rtl_differential.py @@ -80,6 +80,9 @@ def test_seeded_set_xor_mul_and_frame_faults(self) -> None: protocol.build_status_query(), # Phase-B's advertised profile. protocol.build_negotiate(profile=protocol.Profile.INTERPRETER_COMPAT), + # The device-facing model and RTL must reject the unadvertised + # profile with the same BAD_PROFILE response. + protocol.build_negotiate(profile=protocol.Profile.FORWARD_ONLY), ] for txn_id in range(1, 7): left = randomizer.getrandbits(128) From 2115f091d2e346d8fad60634c7af5c428caeddd8 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Tue, 28 Jul 2026 19:40:42 +0200 Subject: [PATCH 3/9] Fix Phase-B evidence artifact binding --- SHA256SUMS | 6 +++--- results/b2-capability-contract-20260728/SHA256SUMS | 4 ++-- results/b2-capability-contract-20260728/metadata.txt | 4 ++-- results/b2-capability-contract-20260728/run.sh | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/SHA256SUMS b/SHA256SUMS index ea5625c..cb4a868 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -133,7 +133,7 @@ d59a11f361717058c708574a6f41d9be99da29cfcc3b0c033045ce6f0e57a5d5 ./planning/OWN a19467b08293daf14a67ccd8f0efbcddfeb3854c38525acd7fcfd98f01552587 ./planning/milestones.yaml fbce601088163a30bf024083852ec3d72a1dd2ab12a22a9ea1fc8809cadafb93 ./requirements.txt 6c11a3bd4eb64e6c319620cd99d9cfbb9ae6cb7e74be09c282dd5267e15610af ./results/b2-capability-contract-20260728/README.md -e5ecbda1857530b195f240b68191b5b1c5ae84ae6460f8bf4c6f0a9f352e4f34 ./results/b2-capability-contract-20260728/SHA256SUMS +7fc58079708688be0754041530011c6850e281e780dd546cede3fc8cef046913 ./results/b2-capability-contract-20260728/SHA256SUMS 967cd83720a145d1daba23a926a1b22eabc4e83d7b7c337cf3512f3df944c535 ./results/b2-capability-contract-20260728/blake3_official.command 42b629a692f30c9bfb0fcff81a5eb4631efb576c1355485035dd6d8c50131631 ./results/b2-capability-contract-20260728/blake3_official.log c4c41bd36c74ae8036f7f04e842e6e165b94947210de3fbb2ff0fc6a7d212aa6 ./results/b2-capability-contract-20260728/blake3_official.status @@ -144,7 +144,7 @@ efbf348e9a19221a83c3de23fc958594ef2138f22817a951b47420d734550a59 ./results/b2-c 95562d2b0efd62f3caca735841da6ebc3f1456ee777faaabb7fd6165dd08ee61 ./results/b2-capability-contract-20260728/equivalence_retry.log 796e8d3bc36ff6c463f6726c0d97edcb03dad3fb8d5b5b087ee02dc9c44e391c ./results/b2-capability-contract-20260728/equivalence_retry.status bea4db3161ea6fe410e47e9a8573aa07081b26666a702ee37828eae50ab3869f ./results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v -d4b10f492e3a5904a83de4177f5c62c655a082a2da1678656313317c04a7ea1a ./results/b2-capability-contract-20260728/metadata.txt +a6d70cc5c8a210a278dc201966afda29bb01b6218d3d260b0c157860327d3be4 ./results/b2-capability-contract-20260728/metadata.txt f1a875f061db0344731acf0e9ebc9cdc99a263361e487be3bc4dcc9b252d464e ./results/b2-capability-contract-20260728/model.command b91294fb84265d3d8a568773e69bf4be6989b8b2495d06ea1b2b166c021228c2 ./results/b2-capability-contract-20260728/model.log 9320156f7729afcf7950684c435baafe45dc8515e77af2cd815ba0d9041679b2 ./results/b2-capability-contract-20260728/model.status @@ -175,7 +175,7 @@ c0086458ffdc5a2d5f3f704c2882f7cebdc0eb6178b3bd0517ef25ce8f6083fd ./results/b2-c 42c1c9680f854883922eef8493abd0e7d3f7dbe293f40b5f7c639d72761a8ff2 ./results/b2-capability-contract-20260728/rtl_final.command 881d0c9e93dd2f29354bf42351533bfe1b571eb3f4e4f0198d92dc51fe4c064f ./results/b2-capability-contract-20260728/rtl_final.log 3916d13f98a1f4f76582598a2c2b98f39998cd02a9e2e117c47f5aced1b62915 ./results/b2-capability-contract-20260728/rtl_final.status -256ef5dd4c4cafd51370b52e2e8d02487cfea78f04304c6081a13dbc1b104787 ./results/b2-capability-contract-20260728/run.sh +a6b69b10647bd848ec9e5a3d0f77081dfa8c17f75223685441518fb15a4e807f ./results/b2-capability-contract-20260728/run.sh 73c8c4939d05b6fd2367c8fc992e8386ee1b505499abfd1050b8286022589f9c ./results/fpga-harness-inventory-20260725/README.md 13c80bbee4874817634c3edcef6a6a687fd4e6d1d5412c026fe9b314388eeb7c ./results/fpga-harness-inventory-20260725/fpga-boundary.log 9a271f2a916b0b6ee6cecb2426f0b3206ef074578be55d9bc94f6f3fe3ab86aa ./results/fpga-harness-inventory-20260725/fpga-boundary.status diff --git a/results/b2-capability-contract-20260728/SHA256SUMS b/results/b2-capability-contract-20260728/SHA256SUMS index 7799fbf..693a8ae 100644 --- a/results/b2-capability-contract-20260728/SHA256SUMS +++ b/results/b2-capability-contract-20260728/SHA256SUMS @@ -9,7 +9,7 @@ efbf348e9a19221a83c3de23fc958594ef2138f22817a951b47420d734550a59 results/b2-cap 95562d2b0efd62f3caca735841da6ebc3f1456ee777faaabb7fd6165dd08ee61 results/b2-capability-contract-20260728/equivalence_retry.log 796e8d3bc36ff6c463f6726c0d97edcb03dad3fb8d5b5b087ee02dc9c44e391c results/b2-capability-contract-20260728/equivalence_retry.status bea4db3161ea6fe410e47e9a8573aa07081b26666a702ee37828eae50ab3869f results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v -d4b10f492e3a5904a83de4177f5c62c655a082a2da1678656313317c04a7ea1a results/b2-capability-contract-20260728/metadata.txt +a6d70cc5c8a210a278dc201966afda29bb01b6218d3d260b0c157860327d3be4 results/b2-capability-contract-20260728/metadata.txt f1a875f061db0344731acf0e9ebc9cdc99a263361e487be3bc4dcc9b252d464e results/b2-capability-contract-20260728/model.command b91294fb84265d3d8a568773e69bf4be6989b8b2495d06ea1b2b166c021228c2 results/b2-capability-contract-20260728/model.log 9320156f7729afcf7950684c435baafe45dc8515e77af2cd815ba0d9041679b2 results/b2-capability-contract-20260728/model.status @@ -40,4 +40,4 @@ c0086458ffdc5a2d5f3f704c2882f7cebdc0eb6178b3bd0517ef25ce8f6083fd results/b2-cap 42c1c9680f854883922eef8493abd0e7d3f7dbe293f40b5f7c639d72761a8ff2 results/b2-capability-contract-20260728/rtl_final.command 881d0c9e93dd2f29354bf42351533bfe1b571eb3f4e4f0198d92dc51fe4c064f results/b2-capability-contract-20260728/rtl_final.log 3916d13f98a1f4f76582598a2c2b98f39998cd02a9e2e117c47f5aced1b62915 results/b2-capability-contract-20260728/rtl_final.status -256ef5dd4c4cafd51370b52e2e8d02487cfea78f04304c6081a13dbc1b104787 results/b2-capability-contract-20260728/run.sh +a6b69b10647bd848ec9e5a3d0f77081dfa8c17f75223685441518fb15a4e807f results/b2-capability-contract-20260728/run.sh diff --git a/results/b2-capability-contract-20260728/metadata.txt b/results/b2-capability-contract-20260728/metadata.txt index c5f376f..9d83098 100644 --- a/results/b2-capability-contract-20260728/metadata.txt +++ b/results/b2-capability-contract-20260728/metadata.txt @@ -1,4 +1,4 @@ baseline_commit=fda85f5efc6f5b460d72204b4d9c0d882960ec29 baseline_tree=df42a6211828d856e9a21ba61ecc2cd1b9dc4e71 -head=fda85f5efc6f5b460d72204b4d9c0d882960ec29 -head_tree=df42a6211828d856e9a21ba61ecc2cd1b9dc4e71 +head=4a4d8cdd9abd56121ae5c8d84df1f1bc42f8ba4a +head_tree=f669539aaf28ecd1cb8b18dfa42508b39aa7c3d5 diff --git a/results/b2-capability-contract-20260728/run.sh b/results/b2-capability-contract-20260728/run.sh index a7fe41c..2466db5 100755 --- a/results/b2-capability-contract-20260728/run.sh +++ b/results/b2-capability-contract-20260728/run.sh @@ -6,8 +6,8 @@ out=results/b2-capability-contract-20260728 mkdir -p "$out" printf '%s\n' "baseline_commit=$(git rev-parse fda85f5efc6f5b460d72204b4d9c0d882960ec29)" > "$out/metadata.txt" printf '%s\n' "baseline_tree=$(git rev-parse fda85f5efc6f5b460d72204b4d9c0d882960ec29^{tree})" >> "$out/metadata.txt" -printf '%s\n' "head=$(git rev-parse HEAD)" >> "$out/metadata.txt" -printf '%s\n' "head_tree=$(git rev-parse HEAD^{tree})" >> "$out/metadata.txt" +printf '%s\n' "head=$(git rev-parse 4a4d8cdd9abd56121ae5c8d84df1f1bc42f8ba4a)" >> "$out/metadata.txt" +printf '%s\n' "head_tree=$(git rev-parse 4a4d8cdd9abd56121ae5c8d84df1f1bc42f8ba4a^{tree})" >> "$out/metadata.txt" run() { name=$1 From e941561fc88306c3eaf8543d79f9000d2bc7d90e Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Tue, 28 Jul 2026 20:32:55 +0200 Subject: [PATCH 4/9] Add bounded release equivalence diagnostic --- SHA256SUMS | 10 +- formal/lsc1_packet_frontend_release_equiv.ys | 34 + .../b2-capability-contract-20260728/README.md | 12 + .../SHA256SUMS | 7 +- .../equivalence_flattened.command | 1 + .../equivalence_flattened.log | 821 ++++++++++++++++++ .../equivalence_flattened.status | 2 + .../metadata.txt | 4 +- 8 files changed, 884 insertions(+), 7 deletions(-) create mode 100644 formal/lsc1_packet_frontend_release_equiv.ys create mode 100644 results/b2-capability-contract-20260728/equivalence_flattened.command create mode 100644 results/b2-capability-contract-20260728/equivalence_flattened.log create mode 100644 results/b2-capability-contract-20260728/equivalence_flattened.status diff --git a/SHA256SUMS b/SHA256SUMS index cb4a868..1474b88 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -61,6 +61,7 @@ d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836 ./formal/gf128 15abdc4c23f94b7389e25487e4c4d35a13ed1565882cbe449629bcbc6a488419 ./formal/gf8_mul_bounded_boolector.sby 531723ced686badb599022ea068d4b94f1d7e00f83ed3d7b86a9f91cc59448f2 ./formal/gf8_mul_depth22_z3.sby 25a0d4fe96e4bcd910ebac0ba76be01f8924aedfa1f7e83588610f1a758baf4f ./formal/gf8_mul_formal.sv +bca568aee38c4638fdaadab4e8878807bc56329bd170b4cb420c07e4357dd6dc ./formal/lsc1_packet_frontend_release_equiv.ys 1e6b80dd959472d00411116899097fb37c930651efe6290fda93a8f4ae5ae97e ./formal/stream_alu_mul_pulse.sby b61a1ea32d6b114093dd2679fd4fb3315dbfbb9829b8e4f739c0177f66ff1bc1 ./formal/stream_alu_mul_pulse_formal.sv 53da30df5dd375567994d2e071664456f0c90d420710817fbbb4b53d894b668a ./fpga/ulx3s/Makefile @@ -132,19 +133,22 @@ d1f2dfa6bf564b9cf248838630eb92efd55f03e9ab8bf5e7dfec3d318b9f0f29 ./lean/lakefil d59a11f361717058c708574a6f41d9be99da29cfcc3b0c033045ce6f0e57a5d5 ./planning/OWNERSHIP.md a19467b08293daf14a67ccd8f0efbcddfeb3854c38525acd7fcfd98f01552587 ./planning/milestones.yaml fbce601088163a30bf024083852ec3d72a1dd2ab12a22a9ea1fc8809cadafb93 ./requirements.txt -6c11a3bd4eb64e6c319620cd99d9cfbb9ae6cb7e74be09c282dd5267e15610af ./results/b2-capability-contract-20260728/README.md -7fc58079708688be0754041530011c6850e281e780dd546cede3fc8cef046913 ./results/b2-capability-contract-20260728/SHA256SUMS +315f8bfecb585814f0d1ec406d16203365e360601166a2e4f897b488cd6ab057 ./results/b2-capability-contract-20260728/README.md +a5157bf6549b0f1730477e82b1ec94a4dacc83f0ae93fc1e0d4e698ec97e1d4c ./results/b2-capability-contract-20260728/SHA256SUMS 967cd83720a145d1daba23a926a1b22eabc4e83d7b7c337cf3512f3df944c535 ./results/b2-capability-contract-20260728/blake3_official.command 42b629a692f30c9bfb0fcff81a5eb4631efb576c1355485035dd6d8c50131631 ./results/b2-capability-contract-20260728/blake3_official.log c4c41bd36c74ae8036f7f04e842e6e165b94947210de3fbb2ff0fc6a7d212aa6 ./results/b2-capability-contract-20260728/blake3_official.status 8ed2f76d0f3c4e2f426b94871ba32c169b2d3db054baf69aaec18ee7c88a97d8 ./results/b2-capability-contract-20260728/equivalence.command c79afc83ad60a71e82e8a7fa6b2af5d627599ff6c387452e3127ef8dc0d5c8f7 ./results/b2-capability-contract-20260728/equivalence.log b55da4864ed1d5b5074f282e6bb197c72e378c1f95e3ae23067f00cf3d1071bf ./results/b2-capability-contract-20260728/equivalence.status +04fb35751904dec58eba40c2b994e0601fe5081edd26d607b2013d8fa97b7d51 ./results/b2-capability-contract-20260728/equivalence_flattened.command +a795d3f21afa4407a1447bb63311d6fefc33adc01c3f6d26e2775f8c6e5c1ab2 ./results/b2-capability-contract-20260728/equivalence_flattened.log +793363b603e34c48e4728c6a77566127909dee8daf24c0ca561991864ac4d052 ./results/b2-capability-contract-20260728/equivalence_flattened.status efbf348e9a19221a83c3de23fc958594ef2138f22817a951b47420d734550a59 ./results/b2-capability-contract-20260728/equivalence_retry.command 95562d2b0efd62f3caca735841da6ebc3f1456ee777faaabb7fd6165dd08ee61 ./results/b2-capability-contract-20260728/equivalence_retry.log 796e8d3bc36ff6c463f6726c0d97edcb03dad3fb8d5b5b087ee02dc9c44e391c ./results/b2-capability-contract-20260728/equivalence_retry.status bea4db3161ea6fe410e47e9a8573aa07081b26666a702ee37828eae50ab3869f ./results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v -a6d70cc5c8a210a278dc201966afda29bb01b6218d3d260b0c157860327d3be4 ./results/b2-capability-contract-20260728/metadata.txt +136645e414d9e29d44dd3a895ed7e2fe711b9f721c87d907edd3b456758de9d7 ./results/b2-capability-contract-20260728/metadata.txt f1a875f061db0344731acf0e9ebc9cdc99a263361e487be3bc4dcc9b252d464e ./results/b2-capability-contract-20260728/model.command b91294fb84265d3d8a568773e69bf4be6989b8b2495d06ea1b2b166c021228c2 ./results/b2-capability-contract-20260728/model.log 9320156f7729afcf7950684c435baafe45dc8515e77af2cd815ba0d9041679b2 ./results/b2-capability-contract-20260728/model.status diff --git a/formal/lsc1_packet_frontend_release_equiv.ys b/formal/lsc1_packet_frontend_release_equiv.ys new file mode 100644 index 0000000..3eb2649 --- /dev/null +++ b/formal/lsc1_packet_frontend_release_equiv.ys @@ -0,0 +1,34 @@ +# Release-equivalence normalization for the Phase-B packet endpoint. +# +# The generated netlist is deliberately compared only after the gold RTL has +# received the same process/memory lowering and hierarchy flattening used for +# netlist generation. This avoids treating unflattened submodule boundaries +# as correspondence cutpoints. No cutpoint is assumed by this script: +# equiv_status -assert can only succeed after every generated obligation has +# actually been proved by the selected Yosys passes. + +read_verilog -formal -sv asic_core/rtl/lsc1_packet_rx.sv \ + asic_core/rtl/lsc1_packet_tx.sv \ + asic_core/rtl/gf2n_mul_bitstream.sv \ + asic_core/rtl/gf128_mul_bitstream.sv \ + asic_core/rtl/leanvm_b_stream_alu.sv \ + asic_core/rtl/lsc1_stream_adapter.sv \ + asic_core/rtl/lsc1_field_encoder.sv \ + asic_core/rtl/lsc1_packet_frontend.sv +hierarchy -check -top lsc1_packet_frontend +proc +memory +flatten +opt +rename lsc1_packet_frontend gold + +read_verilog -formal results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v +rename lsc1_packet_frontend gate +equiv_make gold gate equiv +hierarchy -top equiv +prep -top equiv + +# This is intentionally a proof command, not an assumed state correspondence. +equiv_simple +equiv_induct -seq 4 +equiv_status -assert diff --git a/results/b2-capability-contract-20260728/README.md b/results/b2-capability-contract-20260728/README.md index 2547b9d..d8b651b 100644 --- a/results/b2-capability-contract-20260728/README.md +++ b/results/b2-capability-contract-20260728/README.md @@ -36,6 +36,18 @@ claiming a proof. Thus there is no RTL/netlist equivalence result; the precise missing repository capability is a release sequential-equivalence harness with the required flattening/state correspondence and reset assumptions. +The follow-up release harness is `formal/lsc1_packet_frontend_release_equiv.ys`. +It normalizes the gold design with the same `proc; memory; flatten; opt` flow +before `equiv_make`, and deliberately introduces no assumed cutpoints. A +bounded diagnostic receipt is retained as `equivalence_flattened.*`: the +normalization removes the submodule-boundary mismatch but still leaves 3417 +generated proof targets, dominated by procedural temporary signals from the +monolithic packet-front-end clocked process. The 90 s bound expired (exit 124, +90014 ms) while `equiv_simple` was still traversing target 679/3417; it is not +a PASS. A sound complete proof requires an +architectural state interface (or a reviewed invariant that relates those +temporaries to registered state) rather than additional flat solver time. + Every command and status is retained beside its log. This evidence is a committed handoff artifact, not a claim that the planned release equivalence gate passed. diff --git a/results/b2-capability-contract-20260728/SHA256SUMS b/results/b2-capability-contract-20260728/SHA256SUMS index 693a8ae..6a3db1e 100644 --- a/results/b2-capability-contract-20260728/SHA256SUMS +++ b/results/b2-capability-contract-20260728/SHA256SUMS @@ -1,15 +1,18 @@ -6c11a3bd4eb64e6c319620cd99d9cfbb9ae6cb7e74be09c282dd5267e15610af results/b2-capability-contract-20260728/README.md +315f8bfecb585814f0d1ec406d16203365e360601166a2e4f897b488cd6ab057 results/b2-capability-contract-20260728/README.md 967cd83720a145d1daba23a926a1b22eabc4e83d7b7c337cf3512f3df944c535 results/b2-capability-contract-20260728/blake3_official.command 42b629a692f30c9bfb0fcff81a5eb4631efb576c1355485035dd6d8c50131631 results/b2-capability-contract-20260728/blake3_official.log c4c41bd36c74ae8036f7f04e842e6e165b94947210de3fbb2ff0fc6a7d212aa6 results/b2-capability-contract-20260728/blake3_official.status 8ed2f76d0f3c4e2f426b94871ba32c169b2d3db054baf69aaec18ee7c88a97d8 results/b2-capability-contract-20260728/equivalence.command c79afc83ad60a71e82e8a7fa6b2af5d627599ff6c387452e3127ef8dc0d5c8f7 results/b2-capability-contract-20260728/equivalence.log b55da4864ed1d5b5074f282e6bb197c72e378c1f95e3ae23067f00cf3d1071bf results/b2-capability-contract-20260728/equivalence.status +04fb35751904dec58eba40c2b994e0601fe5081edd26d607b2013d8fa97b7d51 results/b2-capability-contract-20260728/equivalence_flattened.command +a795d3f21afa4407a1447bb63311d6fefc33adc01c3f6d26e2775f8c6e5c1ab2 results/b2-capability-contract-20260728/equivalence_flattened.log +793363b603e34c48e4728c6a77566127909dee8daf24c0ca561991864ac4d052 results/b2-capability-contract-20260728/equivalence_flattened.status efbf348e9a19221a83c3de23fc958594ef2138f22817a951b47420d734550a59 results/b2-capability-contract-20260728/equivalence_retry.command 95562d2b0efd62f3caca735841da6ebc3f1456ee777faaabb7fd6165dd08ee61 results/b2-capability-contract-20260728/equivalence_retry.log 796e8d3bc36ff6c463f6726c0d97edcb03dad3fb8d5b5b087ee02dc9c44e391c results/b2-capability-contract-20260728/equivalence_retry.status bea4db3161ea6fe410e47e9a8573aa07081b26666a702ee37828eae50ab3869f results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v -a6d70cc5c8a210a278dc201966afda29bb01b6218d3d260b0c157860327d3be4 results/b2-capability-contract-20260728/metadata.txt +136645e414d9e29d44dd3a895ed7e2fe711b9f721c87d907edd3b456758de9d7 results/b2-capability-contract-20260728/metadata.txt f1a875f061db0344731acf0e9ebc9cdc99a263361e487be3bc4dcc9b252d464e results/b2-capability-contract-20260728/model.command b91294fb84265d3d8a568773e69bf4be6989b8b2495d06ea1b2b166c021228c2 results/b2-capability-contract-20260728/model.log 9320156f7729afcf7950684c435baafe45dc8515e77af2cd815ba0d9041679b2 results/b2-capability-contract-20260728/model.status diff --git a/results/b2-capability-contract-20260728/equivalence_flattened.command b/results/b2-capability-contract-20260728/equivalence_flattened.command new file mode 100644 index 0000000..298ba7d --- /dev/null +++ b/results/b2-capability-contract-20260728/equivalence_flattened.command @@ -0,0 +1 @@ +timeout 90s yosys -ql results/b2-capability-contract-20260728/equivalence_flattened.log -s formal/lsc1_packet_frontend_release_equiv.ys diff --git a/results/b2-capability-contract-20260728/equivalence_flattened.log b/results/b2-capability-contract-20260728/equivalence_flattened.log new file mode 100644 index 0000000..2fdedc2 --- /dev/null +++ b/results/b2-capability-contract-20260728/equivalence_flattened.log @@ -0,0 +1,821 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Executing script file `formal/lsc1_packet_frontend_release_equiv.ys' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_rx.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_tx.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_packet_tx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_tx'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: asic_core/rtl/gf2n_mul_bitstream.sv +Parsing formal SystemVerilog input from `asic_core/rtl/gf2n_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf2n_mul_bitstream'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: asic_core/rtl/gf128_mul_bitstream.sv +Parsing formal SystemVerilog input from `asic_core/rtl/gf128_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf128_mul_bitstream'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: asic_core/rtl/leanvm_b_stream_alu.sv +Parsing formal SystemVerilog input from `asic_core/rtl/leanvm_b_stream_alu.sv' to AST representation. +Generating RTLIL representation for module `\leanvm_b_stream_alu'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_stream_adapter.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_stream_adapter.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_stream_adapter'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_field_encoder.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_field_encoder.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_field_encoder'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_frontend.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_packet_frontend.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend'. +Successfully finished Verilog frontend. + +9. Executing HIERARCHY pass (managing design hierarchy). + +9.1. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: \gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 + +9.2. Executing AST frontend in derive mode using pre-parsed AST for module `\gf2n_mul_bitstream'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 +Generating RTLIL representation for module `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream'. + +9.3. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx + +9.4. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend +Used module: \lsc1_field_encoder +Used module: \lsc1_stream_adapter +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: \lsc1_packet_tx +Used module: \lsc1_packet_rx +Removing unused module `\gf2n_mul_bitstream'. +Removed 1 unused modules. + +10. Executing PROC pass (convert processes to netlists). + +10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 10 empty switches in `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. +Cleaned up 10 empty switches. + +10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 109 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855 in module lsc1_packet_frontend. +Marked 5 switch rules as full_case in process $proc$asic_core/rtl/lsc1_field_encoder.sv:38$755 in module lsc1_field_encoder. +Marked 10 switch rules as full_case in process $proc$asic_core/rtl/lsc1_stream_adapter.sv:83$671 in module lsc1_stream_adapter. +Marked 6 switch rules as full_case in process $proc$asic_core/rtl/lsc1_stream_adapter.sv:54$646 in module lsc1_stream_adapter. +Marked 12 switch rules as full_case in process $proc$asic_core/rtl/leanvm_b_stream_alu.sv:214$615 in module leanvm_b_stream_alu. +Marked 3 switch rules as full_case in process $proc$asic_core/rtl/leanvm_b_stream_alu.sv:118$576 in module leanvm_b_stream_alu. +Marked 5 switch rules as full_case in process $proc$asic_core/rtl/gf2n_mul_bitstream.sv:72$3172 in module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:62$258 in module lsc1_packet_tx. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:44$244 in module lsc1_packet_tx. +Marked 11 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_rx.sv:62$23 in module lsc1_packet_rx. +Removed a total of 0 dead cases. + +10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 8 redundant assignments. +Promoted 206 assignments to connections. + +10.4. Executing PROC_INIT pass (extract init attributes). + +10.5. Executing PROC_ARST pass (detect async resets in processes). + +10.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\lsc1_packet_frontend.$proc$asic_core/rtl/lsc1_packet_frontend.sv:269$855'. + 1/3417: $68\result_bytes[215:152] [63:32] + 2/3417: $68\result_bytes[215:152] [31:0] + 3/3417: $64\result_length[31:0] + 4/3417: $67\result_bytes[279:104] [111:80] + 5/3417: $67\result_bytes[279:104] [47:40] + 6/3417: $67\result_bytes[279:104] [15:8] + 7/3417: $67\result_bytes[279:104] [143:112] + 8/3417: $63\result_length[31:0] + 9/3417: $67\result_bytes[279:104] [79:72] + 10/3417: $67\result_bytes[279:104] [71:48] + 11/3417: $67\result_bytes[279:104] [39:16] + 12/3417: $67\result_bytes[279:104] [175:144] + 13/3417: $67\result_bytes[279:104] [7:0] + 14/3417: $65\result_bytes[375:104] [175:168] + 15/3417: $66\result_bytes[375:312] [31:0] + 16/3417: $62\result_length[31:0] + 17/3417: $65\result_bytes[375:104] [207:176] + 18/3417: $61\result_length[31:0] + 19/3417: $66\result_bytes[375:312] [63:32] + 20/3417: $65\result_bytes[375:104] [167:160] + 21/3417: $65\result_bytes[375:104] [159:32] + 22/3417: $65\result_bytes[375:104] [31:0] + 23/3417: $65\result_bytes[375:104] [271:208] + 24/3417: $64\result_bytes[543:0] [375:104] + 25/3417: $64\result_bytes[543:0] [103:96] + 26/3417: $64\result_bytes[543:0] [95:64] + 27/3417: $64\result_bytes[543:0] [63:32] + 28/3417: $64\result_bytes[543:0] [31:0] + 29/3417: $64\result_bytes[543:0] [543:376] + 30/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [31:0] + 31/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [39:32] + 32/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$3159 + 33/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$3158 + 34/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$3157 + 35/3417: $29\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$3161 + 36/3417: $29\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3160 [543:40] + 37/3417: $60\result_length[31:0] + 38/3417: $28\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$3155 + 39/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$3154 + 40/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$3153 + 41/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$3152 + 42/3417: $28\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$3151 + 43/3417: $63\result_bytes[543:0] + 44/3417: $59\result_length[31:0] + 45/3417: $50\decision_deferred[0:0] + 46/3417: $49\decision_deferred[0:0] + 47/3417: $48\decision_deferred[0:0] + 48/3417: $58\decision_fault[7:0] + 49/3417: $58\decision_ok[0:0] + 50/3417: $47\decision_deferred[0:0] + 51/3417: $57\decision_fault[7:0] + 52/3417: $57\decision_ok[0:0] + 53/3417: $46\decision_deferred[0:0] + 54/3417: $45\decision_deferred[0:0] + 55/3417: $56\decision_ok[0:0] + 56/3417: $56\decision_fault[7:0] + 57/3417: $44\decision_deferred[0:0] + 58/3417: $55\decision_ok[0:0] + 59/3417: $55\decision_fault[7:0] + 60/3417: $54\decision_fault[7:0] + 61/3417: $54\decision_ok[0:0] + 62/3417: $53\decision_fault[7:0] + 63/3417: $53\decision_ok[0:0] + 64/3417: $38\addr_c[31:0] + 65/3417: $38\addr_b[31:0] + 66/3417: $42\addr_a[31:0] + 67/3417: $52\decision_fault[7:0] + 68/3417: $52\decision_ok[0:0] + 69/3417: $37\addr_c[31:0] + 70/3417: $37\addr_b[31:0] + 71/3417: $41\addr_a[31:0] + 72/3417: $43\decision_deferred[0:0] + 73/3417: $51\decision_ok[0:0] + 74/3417: $51\decision_fault[7:0] + 75/3417: $33\solved_b[127:0] + 76/3417: $33\solved_a[127:0] + 77/3417: $36\addr_c[31:0] + 78/3417: $36\addr_b[31:0] + 79/3417: $40\addr_a[31:0] + 80/3417: $31\inv_value[127:0] + 81/3417: $31\inv_present[7:0] + 82/3417: $31\val_c[127:0] + 83/3417: $31\pres_c[7:0] + 84/3417: $31\val_b[127:0] + 85/3417: $31\pres_b[7:0] + 86/3417: $31\val_a[127:0] + 87/3417: $31\pres_a[7:0] + 88/3417: $31\off_c[31:0] + 89/3417: $31\off_b[31:0] + 90/3417: $31\off_a[31:0] + 91/3417: $38\decision_detail[7:0] + 92/3417: $50\decision_fault[7:0] + 93/3417: $50\decision_ok[0:0] + 94/3417: $37\decision_detail[7:0] + 95/3417: $49\decision_fault[7:0] + 96/3417: $49\decision_ok[0:0] + 97/3417: $48\decision_fault[7:0] + 98/3417: $48\decision_ok[0:0] + 99/3417: $42\decision_deferred[0:0] + 100/3417: $47\decision_fault[7:0] + 101/3417: $47\decision_ok[0:0] + 102/3417: $41\decision_deferred[0:0] + 103/3417: $40\decision_deferred[0:0] + 104/3417: $46\decision_ok[0:0] + 105/3417: $46\decision_fault[7:0] + 106/3417: $36\decision_detail[7:0] + 107/3417: $35\decision_detail[7:0] + 108/3417: $45\decision_fault[7:0] + 109/3417: $45\decision_ok[0:0] + 110/3417: $39\decision_deferred[0:0] + 111/3417: $34\decision_detail[7:0] + 112/3417: $44\decision_fault[7:0] + 113/3417: $44\decision_ok[0:0] + 114/3417: $38\decision_deferred[0:0] + 115/3417: $43\decision_fault[7:0] + 116/3417: $43\decision_ok[0:0] + 117/3417: $37\decision_deferred[0:0] + 118/3417: $33\decision_detail[7:0] + 119/3417: $42\decision_fault[7:0] + 120/3417: $42\decision_ok[0:0] + 121/3417: $36\decision_deferred[0:0] + 122/3417: $32\decision_detail[7:0] + 123/3417: $35\addr_c[31:0] + 124/3417: $35\addr_b[31:0] + 125/3417: $39\addr_a[31:0] + 126/3417: $41\decision_fault[7:0] + 127/3417: $41\decision_ok[0:0] + 128/3417: $35\decision_deferred[0:0] + 129/3417: $31\decision_detail[7:0] + 130/3417: $34\addr_c[31:0] + 131/3417: $34\addr_b[31:0] + 132/3417: $38\addr_a[31:0] + 133/3417: $34\decision_deferred[0:0] + 134/3417: $40\decision_ok[0:0] + 135/3417: $30\decision_detail[7:0] + 136/3417: $40\decision_fault[7:0] + 137/3417: $33\addr_c[31:0] + 138/3417: $33\addr_b[31:0] + 139/3417: $37\addr_a[31:0] + 140/3417: $30\inv_value[127:0] + 141/3417: $30\inv_present[7:0] + 142/3417: $30\proposed_fp[31:0] + 143/3417: $30\proposed_pc[31:0] + 144/3417: $30\taken_proposal[7:0] + 145/3417: $30\val_c[127:0] + 146/3417: $30\pres_c[7:0] + 147/3417: $30\val_b[127:0] + 148/3417: $30\pres_b[7:0] + 149/3417: $30\val_a[127:0] + 150/3417: $30\pres_a[7:0] + 151/3417: $30\off_c[31:0] + 152/3417: $30\off_b[31:0] + 153/3417: $30\off_a[31:0] + 154/3417: $32\solved_b[127:0] + 155/3417: $32\solved_a[127:0] + 156/3417: $39\decision_fault[7:0] + 157/3417: $39\decision_ok[0:0] + 158/3417: $33\decision_deferred[0:0] + 159/3417: $38\decision_fault[7:0] + 160/3417: $38\decision_ok[0:0] + 161/3417: $32\decision_deferred[0:0] + 162/3417: $32\addr_c[31:0] + 163/3417: $32\addr_b[31:0] + 164/3417: $36\addr_a[31:0] + 165/3417: $37\decision_fault[7:0] + 166/3417: $37\decision_ok[0:0] + 167/3417: $31\decision_deferred[0:0] + 168/3417: $31\addr_c[31:0] + 169/3417: $31\addr_b[31:0] + 170/3417: $35\addr_a[31:0] + 171/3417: $36\decision_fault[7:0] + 172/3417: $36\decision_ok[0:0] + 173/3417: $30\decision_deferred[0:0] + 174/3417: $30\addr_c[31:0] + 175/3417: $30\addr_b[31:0] + 176/3417: $34\addr_a[31:0] + 177/3417: $29\decision_deferred[0:0] + 178/3417: $35\decision_ok[0:0] + 179/3417: $35\decision_fault[7:0] + 180/3417: $29\addr_c[31:0] + 181/3417: $29\addr_b[31:0] + 182/3417: $33\addr_a[31:0] + 183/3417: $29\val_c[127:0] + 184/3417: $29\pres_c[7:0] + 185/3417: $29\val_b[127:0] + 186/3417: $29\pres_b[7:0] + 187/3417: $29\base_index[31:0] + 188/3417: $29\val_a[127:0] + 189/3417: $29\pres_a[7:0] + 190/3417: $29\off_c[31:0] + 191/3417: $29\off_b[31:0] + 192/3417: $29\off_a[31:0] + 193/3417: $29\decision_detail[7:0] + 194/3417: $31\solved_b[127:0] + 195/3417: $31\solved_a[127:0] + 196/3417: $29\inv_value[127:0] + 197/3417: $29\taken_proposal[7:0] + 198/3417: $29\inv_present[7:0] + 199/3417: $29\proposed_fp[31:0] + 200/3417: $29\proposed_pc[31:0] + 201/3417: $44\n_writes[31:0] + 202/3417: $44\write_value[127:0] + 203/3417: $44\write_address[31:0] + 204/3417: $32\addr_a[31:0] + 205/3417: $34\decision_fault[7:0] + 206/3417: $34\decision_ok[0:0] + 207/3417: $43\write_value[127:0] + 208/3417: $43\write_address[31:0] + 209/3417: $31\addr_a[31:0] + 210/3417: $43\n_writes[31:0] + 211/3417: $33\decision_fault[7:0] + 212/3417: $33\decision_ok[0:0] + 213/3417: $42\write_value[127:0] + 214/3417: $42\write_address[31:0] + 215/3417: $30\addr_a[31:0] + 216/3417: $42\n_writes[31:0] + 217/3417: $32\decision_fault[7:0] + 218/3417: $32\decision_ok[0:0] + 219/3417: $41\write_value[127:0] + 220/3417: $41\write_address[31:0] + 221/3417: $29\addr_a[31:0] + 222/3417: $41\n_writes[31:0] + 223/3417: $28\addr_c[31:0] + 224/3417: $28\addr_b[31:0] + 225/3417: $28\addr_a[31:0] + 226/3417: $31\decision_ok[0:0] + 227/3417: $31\decision_fault[7:0] + 228/3417: $40\write_value[127:0] + 229/3417: $40\write_address[31:0] + 230/3417: $40\n_writes[31:0] + 231/3417: $28\val_a[127:0] + 232/3417: $28\pres_a[7:0] + 233/3417: $28\result_value[127:0] + 234/3417: $28\off_a[31:0] + 235/3417: $28\decision_deferred[0:0] + 236/3417: $28\decision_detail[7:0] + 237/3417: $30\solved_b[127:0] + 238/3417: $30\solved_a[127:0] + 239/3417: $28\inv_value[127:0] + 240/3417: $28\val_c[127:0] + 241/3417: $28\val_b[127:0] + 242/3417: $28\taken_proposal[7:0] + 243/3417: $28\inv_present[7:0] + 244/3417: $28\pres_c[7:0] + 245/3417: $28\pres_b[7:0] + 246/3417: $28\proposed_fp[31:0] + 247/3417: $28\proposed_pc[31:0] + 248/3417: $28\base_index[31:0] + 249/3417: $28\off_c[31:0] + 250/3417: $28\off_b[31:0] + 251/3417: $30\decision_fault[7:0] + 252/3417: $30\decision_ok[0:0] + 253/3417: $29\decision_fault[7:0] + 254/3417: $29\decision_ok[0:0] + 255/3417: $28\decision_fault[7:0] + 256/3417: $28\decision_ok[0:0] + 257/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [543:40] + 258/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [31:0] + 259/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2917 [39:32] + 260/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2916 + 261/3417: $27\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2922 + 262/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2921 + 263/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2920 + 264/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2919 + 265/3417: $27\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2918 + 266/3417: $27\decision_deferred[0:0] + 267/3417: $27\decision_ok[0:0] + 268/3417: $27\decision_detail[7:0] + 269/3417: $27\decision_fault[7:0] + 270/3417: $39\write_value[127:0] + 271/3417: $39\write_address[31:0] + 272/3417: $62\result_bytes[543:0] + 273/3417: $29\solved_b[127:0] + 274/3417: $29\solved_a[127:0] + 275/3417: $27\result_value[127:0] + 276/3417: $27\inv_value[127:0] + 277/3417: $27\val_c[127:0] + 278/3417: $27\val_b[127:0] + 279/3417: $27\val_a[127:0] + 280/3417: $27\taken_proposal[7:0] + 281/3417: $27\inv_present[7:0] + 282/3417: $27\pres_c[7:0] + 283/3417: $27\pres_b[7:0] + 284/3417: $27\pres_a[7:0] + 285/3417: $27\profile[7:0] + 286/3417: $34\deferred_local[31:0] + 287/3417: $34\deferred_target[31:0] + 288/3417: $29\next_fp_value[31:0] + 289/3417: $29\next_pc_value[31:0] + 290/3417: $27\proposed_fp[31:0] + 291/3417: $27\proposed_pc[31:0] + 292/3417: $27\base_index[31:0] + 293/3417: $27\addr_c[31:0] + 294/3417: $27\addr_b[31:0] + 295/3417: $27\addr_a[31:0] + 296/3417: $27\off_c[31:0] + 297/3417: $27\off_b[31:0] + 298/3417: $27\off_a[31:0] + 299/3417: $27\fp[31:0] + 300/3417: $27\pc[31:0] + 301/3417: $27\txn_id[31:0] + 302/3417: $58\result_length[31:0] + 303/3417: $34\n_deferred[31:0] + 304/3417: $39\n_writes[31:0] + 305/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [543:40] + 306/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [31:0] + 307/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2908 [39:32] + 308/3417: $26\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2915 + 309/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2914 + 310/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2913 + 311/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2912 + 312/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2911 + 313/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2910 + 314/3417: $26\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2909 + 315/3417: $26\decision_deferred[0:0] + 316/3417: $26\decision_ok[0:0] + 317/3417: $26\decision_detail[7:0] + 318/3417: $26\decision_fault[7:0] + 319/3417: $38\write_value[127:0] + 320/3417: $38\write_address[31:0] + 321/3417: $61\result_bytes[543:0] + 322/3417: $28\solved_b[127:0] + 323/3417: $28\solved_a[127:0] + 324/3417: $26\result_value[127:0] + 325/3417: $26\inv_value[127:0] + 326/3417: $26\val_c[127:0] + 327/3417: $26\val_b[127:0] + 328/3417: $26\val_a[127:0] + 329/3417: $26\taken_proposal[7:0] + 330/3417: $26\inv_present[7:0] + 331/3417: $26\pres_c[7:0] + 332/3417: $26\pres_b[7:0] + 333/3417: $26\pres_a[7:0] + 334/3417: $26\profile[7:0] + 335/3417: $33\deferred_local[31:0] + 336/3417: $33\deferred_target[31:0] + 337/3417: $28\next_fp_value[31:0] + 338/3417: $28\next_pc_value[31:0] + 339/3417: $26\proposed_fp[31:0] + 340/3417: $26\proposed_pc[31:0] + 341/3417: $26\base_index[31:0] + 342/3417: $26\addr_c[31:0] + 343/3417: $26\addr_b[31:0] + 344/3417: $26\addr_a[31:0] + 345/3417: $26\off_c[31:0] + 346/3417: $26\off_b[31:0] + 347/3417: $26\off_a[31:0] + 348/3417: $26\fp[31:0] + 349/3417: $26\pc[31:0] + 350/3417: $26\txn_id[31:0] + 351/3417: $57\result_length[31:0] + 352/3417: $33\n_deferred[31:0] + 353/3417: $38\n_writes[31:0] + 354/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [543:40] + 355/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [31:0] + 356/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2858 [39:32] + 357/3417: $25\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2878 + 358/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2877 + 359/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2876 + 360/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2875 + 361/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2874 + 362/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2873 + 363/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2872 + 364/3417: $25\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2871 + 365/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2870 + 366/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2869 + 367/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2868 + 368/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2867 + 369/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2866 + 370/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2865 + 371/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2864 + 372/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2863 + 373/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2862 + 374/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2861 + 375/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2860 + 376/3417: $25\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2859 + 377/3417: $25\decision_deferred[0:0] + 378/3417: $25\decision_ok[0:0] + 379/3417: $25\decision_detail[7:0] + 380/3417: $25\decision_fault[7:0] + 381/3417: $37\write_value[127:0] + 382/3417: $37\write_address[31:0] + 383/3417: $60\result_bytes[543:0] + 384/3417: $27\solved_b[127:0] + 385/3417: $27\solved_a[127:0] + 386/3417: $25\result_value[127:0] + 387/3417: $25\inv_value[127:0] + 388/3417: $25\val_c[127:0] + 389/3417: $25\val_b[127:0] + 390/3417: $25\val_a[127:0] + 391/3417: $25\taken_proposal[7:0] + 392/3417: $25\inv_present[7:0] + 393/3417: $25\pres_c[7:0] + 394/3417: $25\pres_b[7:0] + 395/3417: $25\pres_a[7:0] + 396/3417: $25\profile[7:0] + 397/3417: $32\deferred_local[31:0] + 398/3417: $32\deferred_target[31:0] + 399/3417: $27\next_fp_value[31:0] + 400/3417: $27\next_pc_value[31:0] + 401/3417: $25\proposed_fp[31:0] + 402/3417: $25\proposed_pc[31:0] + 403/3417: $25\base_index[31:0] + 404/3417: $25\addr_c[31:0] + 405/3417: $25\addr_b[31:0] + 406/3417: $25\addr_a[31:0] + 407/3417: $25\off_c[31:0] + 408/3417: $25\off_b[31:0] + 409/3417: $25\off_a[31:0] + 410/3417: $25\fp[31:0] + 411/3417: $25\pc[31:0] + 412/3417: $25\txn_id[31:0] + 413/3417: $56\result_length[31:0] + 414/3417: $32\n_deferred[31:0] + 415/3417: $37\n_writes[31:0] + 416/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [543:40] + 417/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [31:0] + 418/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2833 [39:32] + 419/3417: $24\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2854 + 420/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2853 + 421/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2852 + 422/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2851 + 423/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2850 + 424/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2849 + 425/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2848 + 426/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2847 + 427/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2846 + 428/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2845 + 429/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2844 + 430/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2843 + 431/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2842 + 432/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2841 + 433/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2840 + 434/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2839 + 435/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2838 + 436/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2837 + 437/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2836 + 438/3417: $24\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2835 + 439/3417: $24\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2834 + 440/3417: $24\decision_deferred[0:0] + 441/3417: $24\decision_ok[0:0] + 442/3417: $24\decision_detail[7:0] + 443/3417: $24\decision_fault[7:0] + 444/3417: $36\write_value[127:0] + 445/3417: $36\write_address[31:0] + 446/3417: $59\result_bytes[543:0] + 447/3417: $26\solved_b[127:0] + 448/3417: $26\solved_a[127:0] + 449/3417: $24\result_value[127:0] + 450/3417: $24\inv_value[127:0] + 451/3417: $24\val_c[127:0] + 452/3417: $24\val_b[127:0] + 453/3417: $24\val_a[127:0] + 454/3417: $24\taken_proposal[7:0] + 455/3417: $24\inv_present[7:0] + 456/3417: $24\pres_c[7:0] + 457/3417: $24\pres_b[7:0] + 458/3417: $24\pres_a[7:0] + 459/3417: $24\profile[7:0] + 460/3417: $31\deferred_local[31:0] + 461/3417: $31\deferred_target[31:0] + 462/3417: $26\next_fp_value[31:0] + 463/3417: $26\next_pc_value[31:0] + 464/3417: $24\proposed_fp[31:0] + 465/3417: $24\proposed_pc[31:0] + 466/3417: $24\base_index[31:0] + 467/3417: $24\addr_c[31:0] + 468/3417: $24\addr_b[31:0] + 469/3417: $24\addr_a[31:0] + 470/3417: $24\off_c[31:0] + 471/3417: $24\off_b[31:0] + 472/3417: $24\off_a[31:0] + 473/3417: $24\fp[31:0] + 474/3417: $24\pc[31:0] + 475/3417: $24\txn_id[31:0] + 476/3417: $55\result_length[31:0] + 477/3417: $31\n_deferred[31:0] + 478/3417: $36\n_writes[31:0] + 479/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [543:40] + 480/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [31:0] + 481/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2773 [39:32] + 482/3417: $23\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2807 + 483/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2806 + 484/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2805 + 485/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2804 + 486/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2803 + 487/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2802 + 488/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2801 + 489/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2800 + 490/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2799 + 491/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2798 + 492/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2797 + 493/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2796 + 494/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2795 + 495/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2794 + 496/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2793 + 497/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2792 + 498/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2791 + 499/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2790 + 500/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2789 + 501/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2788 + 502/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2787 + 503/3417: $23\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2786 + 504/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2785 + 505/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2784 + 506/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2783 + 507/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2782 + 508/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2781 + 509/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2780 + 510/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2779 + 511/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2778 + 512/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2777 + 513/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2776 + 514/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2775 + 515/3417: $23\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2774 + 516/3417: $23\decision_deferred[0:0] + 517/3417: $23\decision_ok[0:0] + 518/3417: $23\decision_detail[7:0] + 519/3417: $23\decision_fault[7:0] + 520/3417: $35\write_value[127:0] + 521/3417: $35\write_address[31:0] + 522/3417: $58\result_bytes[543:0] + 523/3417: $25\solved_b[127:0] + 524/3417: $25\solved_a[127:0] + 525/3417: $23\result_value[127:0] + 526/3417: $23\inv_value[127:0] + 527/3417: $23\val_c[127:0] + 528/3417: $23\val_b[127:0] + 529/3417: $23\val_a[127:0] + 530/3417: $23\taken_proposal[7:0] + 531/3417: $23\inv_present[7:0] + 532/3417: $23\pres_c[7:0] + 533/3417: $23\pres_b[7:0] + 534/3417: $23\pres_a[7:0] + 535/3417: $23\profile[7:0] + 536/3417: $30\deferred_local[31:0] + 537/3417: $30\deferred_target[31:0] + 538/3417: $25\next_fp_value[31:0] + 539/3417: $25\next_pc_value[31:0] + 540/3417: $23\proposed_fp[31:0] + 541/3417: $23\proposed_pc[31:0] + 542/3417: $23\base_index[31:0] + 543/3417: $23\addr_c[31:0] + 544/3417: $23\addr_b[31:0] + 545/3417: $23\addr_a[31:0] + 546/3417: $23\off_c[31:0] + 547/3417: $23\off_b[31:0] + 548/3417: $23\off_a[31:0] + 549/3417: $23\fp[31:0] + 550/3417: $23\pc[31:0] + 551/3417: $23\txn_id[31:0] + 552/3417: $54\result_length[31:0] + 553/3417: $30\n_deferred[31:0] + 554/3417: $35\n_writes[31:0] + 555/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [543:40] + 556/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [31:0] + 557/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:525$811.bytes[543:0]$2705 [39:32] + 558/3417: $22\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2749 + 559/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2748 + 560/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2747 + 561/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2746 + 562/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2745 + 563/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.bytes[543:0]$2744 + 564/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:561$827.txn[31:0]$2743 + 565/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:559$826.bytes[543:0]$2742 + 566/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.value[127:0]$2741 + 567/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.present[7:0]$2740 + 568/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:557$825.$result[0:0]$2739 + 569/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.value[127:0]$2738 + 570/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.present[7:0]$2737 + 571/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:554$824.$result[0:0]$2736 + 572/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.value[127:0]$2735 + 573/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2734 + 574/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2733 + 575/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2732 + 576/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2731 + 577/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2730 + 578/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2729 + 579/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2728 + 580/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2727 + 581/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2726 + 582/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2725 + 583/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2724 + 584/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2723 + 585/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2722 + 586/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2721 + 587/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2720 + 588/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2719 + 589/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2718 + 590/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2717 + 591/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2716 + 592/3417: $22\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2715 + 593/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.value[127:0]$2714 + 594/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.present[7:0]$2713 + 595/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:533$814.$result[0:0]$2712 + 596/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.value[127:0]$2711 + 597/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.present[7:0]$2710 + 598/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:531$813.$result[0:0]$2709 + 599/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.value[127:0]$2708 + 600/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.present[7:0]$2707 + 601/3417: $22\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:529$812.$result[0:0]$2706 + 602/3417: $22\decision_deferred[0:0] + 603/3417: $22\decision_ok[0:0] + 604/3417: $22\decision_detail[7:0] + 605/3417: $22\decision_fault[7:0] + 606/3417: $34\write_value[127:0] + 607/3417: $34\write_address[31:0] + 608/3417: $57\result_bytes[543:0] + 609/3417: $24\solved_b[127:0] + 610/3417: $24\solved_a[127:0] + 611/3417: $22\result_value[127:0] + 612/3417: $22\inv_value[127:0] + 613/3417: $22\val_c[127:0] + 614/3417: $22\val_b[127:0] + 615/3417: $22\val_a[127:0] + 616/3417: $22\taken_proposal[7:0] + 617/3417: $22\inv_present[7:0] + 618/3417: $22\pres_c[7:0] + 619/3417: $22\pres_b[7:0] + 620/3417: $22\pres_a[7:0] + 621/3417: $22\profile[7:0] + 622/3417: $29\deferred_local[31:0] + 623/3417: $29\deferred_target[31:0] + 624/3417: $24\next_fp_value[31:0] + 625/3417: $24\next_pc_value[31:0] + 626/3417: $22\proposed_fp[31:0] + 627/3417: $22\proposed_pc[31:0] + 628/3417: $22\base_index[31:0] + 629/3417: $22\addr_c[31:0] + 630/3417: $22\addr_b[31:0] + 631/3417: $22\addr_a[31:0] + 632/3417: $22\off_c[31:0] + 633/3417: $22\off_b[31:0] + 634/3417: $22\off_a[31:0] + 635/3417: $22\fp[31:0] + 636/3417: $22\pc[31:0] + 637/3417: $22\txn_id[31:0] + 638/3417: $53\result_length[31:0] + 639/3417: $29\n_deferred[31:0] + 640/3417: $34\n_writes[31:0] + 641/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [543:40] + 642/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [31:0] + 643/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:521$809.bytes[543:0]$2649 [39:32] + 644/3417: $21\emit_result$func$asic_core/rtl/lsc1_packet_frontend.sv:785$829.access_count[7:0]$2697 + 645/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.bytes[543:0]$2696 + 646/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.detail[7:0]$2695 + 647/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.txn[31:0]$2694 + 648/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:783$828.status[7:0]$2693 + 649/3417: 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659/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.present[7:0]$2682 + 660/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:552$823.$result[0:0]$2681 + 661/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.value[127:0]$2680 + 662/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.present[7:0]$2679 + 663/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:550$822.$result[0:0]$2678 + 664/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:548$821.bytes[543:0]$2677 + 665/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:545$820.bytes[543:0]$2676 + 666/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.value[127:0]$2675 + 667/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.present[7:0]$2674 + 668/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:543$819.$result[0:0]$2673 + 669/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.value[127:0]$2672 + 670/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.present[7:0]$2671 + 671/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:541$818.$result[0:0]$2670 + 672/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.value[127:0]$2669 + 673/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.present[7:0]$2668 + 674/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:539$817.$result[0:0]$2667 + 675/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.value[127:0]$2666 + 676/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.present[7:0]$2665 + 677/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_frontend.sv:537$816.$result[0:0]$2664 + 678/3417: $21\emit_fault$func$asic_core/rtl/lsc1_packet_frontend.sv:535$815.bytes[543:0]$2663 + 679/3417: $21\cell_is_malformed$func$asic_core/rtl/lsc1_packet_fron \ No newline at end of file diff --git a/results/b2-capability-contract-20260728/equivalence_flattened.status b/results/b2-capability-contract-20260728/equivalence_flattened.status new file mode 100644 index 0000000..6605d30 --- /dev/null +++ b/results/b2-capability-contract-20260728/equivalence_flattened.status @@ -0,0 +1,2 @@ +exit_code=124 +duration_ms=90014 diff --git a/results/b2-capability-contract-20260728/metadata.txt b/results/b2-capability-contract-20260728/metadata.txt index 9d83098..2ce6d42 100644 --- a/results/b2-capability-contract-20260728/metadata.txt +++ b/results/b2-capability-contract-20260728/metadata.txt @@ -1,4 +1,4 @@ baseline_commit=fda85f5efc6f5b460d72204b4d9c0d882960ec29 baseline_tree=df42a6211828d856e9a21ba61ecc2cd1b9dc4e71 -head=4a4d8cdd9abd56121ae5c8d84df1f1bc42f8ba4a -head_tree=f669539aaf28ecd1cb8b18dfa42508b39aa7c3d5 +head=2115f091d2e346d8fad60634c7af5c428caeddd8 +head_tree=d4cc0823937d9bebc7d06015793d92d742f51587 From 8e9b0a40d46fbe2ac2ca13e3696ac139d4d62490 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Tue, 28 Jul 2026 20:48:32 +0200 Subject: [PATCH 5/9] Expose registered architectural state interface --- SHA256SUMS | 24 +- asic_core/rtl/lsc1_field_encoder.sv | 6 +- asic_core/rtl/lsc1_packet_frontend.sv | 135 +- asic_core/rtl/lsc1_packet_rx.sv | 11 +- asic_core/rtl/lsc1_packet_tx.sv | 7 +- asic_core/rtl/lsc1_stream_adapter.sv | 8 +- formal/ARCH_STATE.md | 52 + .../lsc1_packet_frontend_arch_reset_idle.sv | 28 + .../lsc1_packet_frontend_arch_reset_idle.ys | 6 + .../lsc1_packet_frontend_arch_state_map.json | 28 + results/arch-state-20260728/README.md | 40 + results/arch-state-20260728/SHA256SUMS | 6 + results/arch-state-20260728/differential.log | 9 + .../interface-coverage.log | 1 + results/arch-state-20260728/mutation.log | 3 + results/arch-state-20260728/reset-idle.log | 3088 +++++++++++++++++ results/arch-state-20260728/rtl.log | 31 + .../versions-and-inputs.log | 13 + tools/check_arch_state_interface.py | 27 + tools/run_arch_state_milestones.sh | 22 + 20 files changed, 3531 insertions(+), 14 deletions(-) create mode 100644 formal/ARCH_STATE.md create mode 100644 formal/lsc1_packet_frontend_arch_reset_idle.sv create mode 100644 formal/lsc1_packet_frontend_arch_reset_idle.ys create mode 100644 formal/lsc1_packet_frontend_arch_state_map.json create mode 100644 results/arch-state-20260728/README.md create mode 100644 results/arch-state-20260728/SHA256SUMS create mode 100644 results/arch-state-20260728/differential.log create mode 100644 results/arch-state-20260728/interface-coverage.log create mode 100644 results/arch-state-20260728/mutation.log create mode 100644 results/arch-state-20260728/reset-idle.log create mode 100644 results/arch-state-20260728/rtl.log create mode 100644 results/arch-state-20260728/versions-and-inputs.log create mode 100644 tools/check_arch_state_interface.py create mode 100755 tools/run_arch_state_milestones.sh diff --git a/SHA256SUMS b/SHA256SUMS index 1474b88..79862fa 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -13,12 +13,12 @@ d8e83531981677f629877cbeff643e07e169f8f6e8cf3ecd7c1b0c417a79b614 ./asic_core/rt 192eddc1727d8976ea48db9a532f44893d06bdec7651c65a1b1b99502b5e70c5 ./asic_core/rtl/lean_silicon_lsc1.sv 774b239a6221619559c57f0e00aad4000b507fd7c941dc9da204c1e357d6ad90 ./asic_core/rtl/lean_silicon_lsc1_mincore.sv bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b ./asic_core/rtl/leanvm_b_stream_alu.sv -5fafb0f5fe81ac5aaf32d0d9974d7d7d2e2b66dde05cdb707e2067ab516f5e05 ./asic_core/rtl/lsc1_field_encoder.sv +dd8527e058916fe188f6d5d73268fe6bccc30c86cf10411a1db20c3ff0bb151f ./asic_core/rtl/lsc1_field_encoder.sv 320e989e5480b6641f99f18822edeee5634f3d277f2faa408aaee2d21503d625 ./asic_core/rtl/lsc1_gf128_mul.sv -9fa8ac6fc7407c856a4f396e86151e17e6b844f83ca42f4253479267568e15da ./asic_core/rtl/lsc1_packet_frontend.sv -284a57adf8c140ae7896f1c8d43a556c1142735c57bec624d3c9ff3b78b3db76 ./asic_core/rtl/lsc1_packet_rx.sv -d0e2aa043df30c49d946e88503a4edf55ad4fa4467fb8b7e0b49b1e385a58c94 ./asic_core/rtl/lsc1_packet_tx.sv -41b68a8068f417ff8f0d33f0408405f4fae5a7b5e2fd60b482d11148e541e6c7 ./asic_core/rtl/lsc1_stream_adapter.sv +390a7d879e1f9c07dbff58a6a2a451ff686bb145ac6c6e512dfa524ceb620164 ./asic_core/rtl/lsc1_packet_frontend.sv +d24a53bcde88011f57fbd3515e3cf94307e326510c7ccc9c8b6492492de2ebe0 ./asic_core/rtl/lsc1_packet_rx.sv +4faf3e75fb5af10ae24d553cca6e80f5c9c32ace3df506784c21a933a0947a92 ./asic_core/rtl/lsc1_packet_tx.sv +e86aa91de733a17e627a5552551723e5bfed3b318cbe84746e95e812d4f8b0d0 ./asic_core/rtl/lsc1_stream_adapter.sv abcaeb377fdec71acd13ae9610b91e250c97a6709b5d9a6d208835e677f00ece ./conformance/README.md 76ba2ea25dd2f20ea3e50c6d25c774d1fbf45b2960b65d233680c284c0c111d7 ./conformance/corpus-v1.json cd41a7e0fda82b96aba2f141829e3168db5a0a7b41dfee77b4718a58f7e3daf2 ./conformance/rust/frozen_adapter.rs @@ -53,6 +53,7 @@ c8dbcf0008931bfd0d6a27c00425480de54d322dd27367ae83f54f93e3382b8c ./docs/semanti 3e896ee33e3804876f6e169c872746146c1b3d773811683616986a4148b9f785 ./docs/semantics/reference/oracle.py c49a013eb503060394007d07395e625024d7c1ff0e9b177bc71e691e1a4efec8 ./docs/semantics/reference/vectors.json 961d9f2f85fe6a6e2a5f586412e03759cb94a80683959e7f0271f37f200a4f1d ./docs/upstream-clarifications/README.md +0b3f72a7bdf25c3a2fe8831ea4824487685932d2e80183140dd8212e273aa314 ./formal/ARCH_STATE.md e563e1a3b9189f28388b5335b0be480856200a4e196de6f61e90b8e7ece0b5e1 ./formal/README.md d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836 ./formal/gf128_serialize.sby 9a069838244bd75c66ab3930eb944c3677ae83242f9b2cbd9866a0d6d1db3198 ./formal/gf128_serialize_formal.sv @@ -61,6 +62,9 @@ d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836 ./formal/gf128 15abdc4c23f94b7389e25487e4c4d35a13ed1565882cbe449629bcbc6a488419 ./formal/gf8_mul_bounded_boolector.sby 531723ced686badb599022ea068d4b94f1d7e00f83ed3d7b86a9f91cc59448f2 ./formal/gf8_mul_depth22_z3.sby 25a0d4fe96e4bcd910ebac0ba76be01f8924aedfa1f7e83588610f1a758baf4f ./formal/gf8_mul_formal.sv +faac561322f0831f66924be0afd8a5ae5cca1cb3e3d2b9dc9ca1b5ea576cdabb ./formal/lsc1_packet_frontend_arch_reset_idle.sv +f85348ac2c65ad828d1365d62254664817efd1bbcb7aee2bb2f20791e4493e20 ./formal/lsc1_packet_frontend_arch_reset_idle.ys +606911b0f58068892d0df892f188bd50db50a30ec49ed63ca8b2941f9400c772 ./formal/lsc1_packet_frontend_arch_state_map.json bca568aee38c4638fdaadab4e8878807bc56329bd170b4cb420c07e4357dd6dc ./formal/lsc1_packet_frontend_release_equiv.ys 1e6b80dd959472d00411116899097fb37c930651efe6290fda93a8f4ae5ae97e ./formal/stream_alu_mul_pulse.sby b61a1ea32d6b114093dd2679fd4fb3315dbfbb9829b8e4f739c0177f66ff1bc1 ./formal/stream_alu_mul_pulse_formal.sv @@ -133,6 +137,14 @@ d1f2dfa6bf564b9cf248838630eb92efd55f03e9ab8bf5e7dfec3d318b9f0f29 ./lean/lakefil d59a11f361717058c708574a6f41d9be99da29cfcc3b0c033045ce6f0e57a5d5 ./planning/OWNERSHIP.md a19467b08293daf14a67ccd8f0efbcddfeb3854c38525acd7fcfd98f01552587 ./planning/milestones.yaml fbce601088163a30bf024083852ec3d72a1dd2ab12a22a9ea1fc8809cadafb93 ./requirements.txt +091c91a57156e3fe3207f2a1c46f1b189209d0a7b1089f226c80da9aac40509a ./results/arch-state-20260728/README.md +62d0ec37d880c46a9f7ef6e36bcac75b9cfd3bf7ffd82cbcfa89c0cd2aa688ad ./results/arch-state-20260728/SHA256SUMS +b91294fb84265d3d8a568773e69bf4be6989b8b2495d06ea1b2b166c021228c2 ./results/arch-state-20260728/differential.log +4e79a6223338d65e7609b234e33c62cbad037f3a27f1f6fe795f6d61e1ecc281 ./results/arch-state-20260728/interface-coverage.log +c3a2a9f65cc2cc17d980a939d510da253dba23547a875440b950137da81581c5 ./results/arch-state-20260728/mutation.log +ff5d1517dabeb83213ca643ef75a392a17003417d41d11b2dc385450e0121825 ./results/arch-state-20260728/reset-idle.log +1232f3d6bb4138ddf396895ed067274601df653827828396b79a88b2430a438d ./results/arch-state-20260728/rtl.log +00486fb8958a8818e17326967dee9e5fcfaf602093c282a957229b491eefcf99 ./results/arch-state-20260728/versions-and-inputs.log 315f8bfecb585814f0d1ec406d16203365e360601166a2e4f897b488cd6ab057 ./results/b2-capability-contract-20260728/README.md a5157bf6549b0f1730477e82b1ec94a4dacc83f0ae93fc1e0d4e698ec97e1d4c ./results/b2-capability-contract-20260728/SHA256SUMS 967cd83720a145d1daba23a926a1b22eabc4e83d7b7c337cf3512f3df944c535 ./results/b2-capability-contract-20260728/blake3_official.command @@ -390,6 +402,7 @@ e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a ./tools/atomic 7894f75175f62edfd1ed33639a23d736ad6e57ddd9182e040f556502bff21a52 ./tools/blake3_reference/Cargo.lock e28e67bc3fd6dee898130648c74691ca7b8e61d1fccfa75c52d87d52fc8d9c3f ./tools/blake3_reference/Cargo.toml 3414b26004416f8871274b30fa975b40f611b5b6b148a2e1b3d97c109cd37f52 ./tools/blake3_reference/src/main.rs +750670739ee7f64954917601f85b95021496a429f4174b09d6777dc4918ff9a4 ./tools/check_arch_state_interface.py 3057cbe3ffbd0b8826a9c77cca1be2e3344b831373adbe583679706858b50910 ./tools/conformance_differential.py 008f814b114282389ae48ff82e4412fe455cbe8c377cf71e534862d490d3cb79 ./tools/design_space.csv 75dc51b45b2631ddc57c4629982949696f1b711323f6e857ca19dc42961f7359 ./tools/design_space.md @@ -405,5 +418,6 @@ a1fbbcbe225a1e2edb2456f92825e7b6853f224e8d0379aa4454d298c2419919 ./tools/frozen 737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 ./tools/portable_build_support.py af28d238b411fcc075bb00b09a204ed1a98c4b4c36479ab5aa6ca611928efba0 ./tools/repo_consistency.py d39b590b15a494a1e62ff7605ca3b8c8ffec122e0f10f6dce7f997fcecceef1b ./tools/rtl_state_count.py +8ad06f1f1a05c1f09b78690dd09c5bc0e08633827feb77da5de43d563bd3dada ./tools/run_arch_state_milestones.sh a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db ./tools/source_provenance.py 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d ./tools/sv_smoke_check.py diff --git a/asic_core/rtl/lsc1_field_encoder.sv b/asic_core/rtl/lsc1_field_encoder.sv index e5863b0..d271f8b 100644 --- a/asic_core/rtl/lsc1_field_encoder.sv +++ b/asic_core/rtl/lsc1_field_encoder.sv @@ -12,7 +12,9 @@ module lsc1_field_encoder ( output reg busy, output reg done_pulse, output reg fault, - output reg [127:0] result + output reg [127:0] result, + output wire [4:0] arch_bit_index, + output wire [15:0] arch_saved_index ); reg multiply_start; reg [4:0] bit_index; @@ -22,6 +24,8 @@ module lsc1_field_encoder ( wire multiply_busy, multiply_done, multiply_fault; wire [127:0] multiply_result; reg [127:0] next_accumulator; + assign arch_bit_index = bit_index; + assign arch_saved_index = saved_index; function automatic [127:0] field_xtime(input [127:0] value); field_xtime = {value[126:0], 1'b0} ^ diff --git a/asic_core/rtl/lsc1_packet_frontend.sv b/asic_core/rtl/lsc1_packet_frontend.sv index bf18677..115be3b 100644 --- a/asic_core/rtl/lsc1_packet_frontend.sv +++ b/asic_core/rtl/lsc1_packet_frontend.sv @@ -15,7 +15,59 @@ module lsc1_packet_frontend ( input wire tx_ready, output wire busy, output reg fault, - output reg done_pulse + output reg done_pulse, + + // Registered architectural-state observation interface. These signals + // deliberately expose state at the clock boundary; they do not alter the + // packet protocol. The field-level contract is in + // formal/lsc1_packet_frontend_arch_state_map.json. + output wire [3:0] arch_phase, + output wire arch_parser_busy, + output wire [2:0] arch_parser_phase, + output wire [2:0] arch_parser_header_index, + output wire [15:0] arch_parser_body_index, + output wire [15:0] arch_parser_declared_length, + output wire [7:0] arch_parser_version, + output wire [7:0] arch_parser_opcode, + output wire [7:0] arch_parser_flags, + output wire [31:0] arch_parser_crc, + output wire [31:0] arch_parser_received_crc, + output wire arch_frame_valid, + output wire [7:0] arch_frame_opcode, + output wire [15:0] arch_frame_length, + output wire [2047:0] arch_frame_payload, + output wire arch_rx_fault_valid, + output wire [7:0] arch_rx_fault_status, + output wire arch_result_pending, + output wire [31:0] arch_staged_txn_id, + output wire [31:0] arch_staged_next_pc, + output wire [31:0] arch_staged_next_fp, + output wire [31:0] arch_staged_result_crc, + output wire arch_state_valid, + output wire [31:0] arch_committed_pc, + output wire [31:0] arch_committed_fp, + output wire [31:0] arch_retire_seq, + output wire [7:0] arch_active_profile, + output wire [7:0] arch_last_status, + output wire [7:0] arch_last_fault, + output wire arch_tx_busy, + output wire [15:0] arch_tx_index, + output wire [15:0] arch_tx_length, + output wire [7:0] arch_tx_status, + output wire [543:0] arch_tx_payload, + output wire [31:0] arch_tx_payload_crc, + output wire arch_alu_busy, + output wire [2:0] arch_alu_phase, + output wire [7:0] arch_alu_operation, + output wire [5:0] arch_alu_payload_index, + output wire [4:0] arch_alu_result_index, + output wire [127:0] arch_alu_result, + output wire arch_encoder_busy, + output wire [4:0] arch_encoder_bit_index, + output wire [15:0] arch_encoder_index, + output wire [127:0] arch_encoder_result, + output wire arch_fault, + output wire arch_done_pulse ); localparam [7:0] OP_XOR = 8'h01, OP_MUL = 8'h02, OP_SET = 8'h03, OP_DEREF_CELL = 8'h04, OP_DEREF_PC = 8'h05, @@ -46,12 +98,19 @@ module lsc1_packet_frontend ( wire frame_valid, rx_fault_valid; wire parser_rx_ready; wire rx_busy; + wire [2:0] parser_arch_state, parser_arch_header_index; + wire [15:0] parser_arch_body_index, parser_arch_declared_length; + wire [7:0] parser_arch_version, parser_arch_opcode, parser_arch_flags; + wire [31:0] parser_arch_crc, parser_arch_received_crc; wire [7:0] frame_opcode, rx_fault_status; wire [15:0] frame_length; wire [2047:0] frame_payload; wire tx_busy; wire tx_done; wire [31:0] tx_payload_crc; + wire [15:0] tx_arch_index, tx_arch_length; + wire [7:0] tx_arch_status; + wire [543:0] tx_arch_payload; reg tx_start; reg [7:0] tx_status; reg [15:0] tx_length; @@ -63,10 +122,16 @@ module lsc1_packet_frontend ( reg [127:0] alu_operand_a, alu_operand_b; wire alu_busy, alu_done, alu_fault; wire [127:0] alu_result; + wire [2:0] alu_arch_state; + wire [7:0] alu_arch_operation; + wire [5:0] alu_arch_payload_index; + wire [4:0] alu_arch_result_index; reg encoder_start; reg [15:0] encoder_index; wire encoder_busy, encoder_done, encoder_fault; wire [127:0] encoder_result; + wire [4:0] encoder_arch_bit_index; + wire [15:0] encoder_arch_saved_index; wire lane_enable = !tx_busy && !tx_start && compute_state == C_IDLE && !alu_busy && !encoder_busy; @@ -88,7 +153,11 @@ module lsc1_packet_frontend ( .frame_opcode(frame_opcode), .frame_length(frame_length), .frame_payload(frame_payload), .fault_valid(rx_fault_valid), .fault_status(rx_fault_status), - .busy(rx_busy) + .busy(rx_busy), .arch_state(parser_arch_state), + .arch_header_index(parser_arch_header_index), .arch_body_index(parser_arch_body_index), + .arch_declared_length(parser_arch_declared_length), .arch_version(parser_arch_version), + .arch_opcode(parser_arch_opcode), .arch_flags(parser_arch_flags), + .arch_crc(parser_arch_crc), .arch_received_crc(parser_arch_received_crc) ); lsc1_packet_tx transmitter ( @@ -96,26 +165,82 @@ module lsc1_packet_frontend ( .start(tx_start), .status(tx_status), .payload_length(tx_length), .payload(tx_payload), .busy(tx_busy), .done_pulse(tx_done), .payload_crc(tx_payload_crc), - .tx_data(tx_data), .tx_valid(tx_valid), .tx_ready(tx_ready) + .tx_data(tx_data), .tx_valid(tx_valid), .tx_ready(tx_ready), + .arch_index(tx_arch_index), .arch_length(tx_arch_length), + .arch_status(tx_arch_status), .arch_payload(tx_arch_payload) ); lsc1_stream_adapter adapter ( .clk(clk), .rst_n(rst_n), .abort(abort), .start(alu_start), .operation(alu_operation), .operand_a(alu_operand_a), .operand_b(alu_operand_b), .busy(alu_busy), - .done_pulse(alu_done), .fault(alu_fault), .result(alu_result) + .done_pulse(alu_done), .fault(alu_fault), .result(alu_result), + .arch_state(alu_arch_state), .arch_operation(alu_arch_operation), + .arch_payload_index(alu_arch_payload_index), .arch_result_index(alu_arch_result_index) ); lsc1_field_encoder field_encoder ( .clk(clk), .rst_n(rst_n), .abort(abort), .start(encoder_start), .index(encoder_index), .busy(encoder_busy), .done_pulse(encoder_done), - .fault(encoder_fault), .result(encoder_result) + .fault(encoder_fault), .result(encoder_result), + .arch_bit_index(encoder_arch_bit_index), .arch_saved_index(encoder_arch_saved_index) ); assign rx_ready = parser_rx_ready && lane_enable; assign busy = rx_busy || tx_busy || tx_start || event_valid || result_pending || compute_state != C_IDLE || alu_busy || encoder_busy; + // R(rtl_state, arch_state): every architectural field below is a direct + // observation of a registered RTL field (or a documented output function + // of such fields). No symbolic bridge or assumed cutpoint is used. + assign arch_phase = compute_state; + assign arch_parser_busy = rx_busy; + assign arch_parser_phase = parser_arch_state; + assign arch_parser_header_index = parser_arch_header_index; + assign arch_parser_body_index = parser_arch_body_index; + assign arch_parser_declared_length = parser_arch_declared_length; + assign arch_parser_version = parser_arch_version; + assign arch_parser_opcode = parser_arch_opcode; + assign arch_parser_flags = parser_arch_flags; + assign arch_parser_crc = parser_arch_crc; + assign arch_parser_received_crc = parser_arch_received_crc; + assign arch_frame_valid = frame_valid; + assign arch_frame_opcode = frame_opcode; + assign arch_frame_length = frame_length; + assign arch_frame_payload = frame_payload; + assign arch_rx_fault_valid = rx_fault_valid; + assign arch_rx_fault_status = rx_fault_status; + assign arch_result_pending = result_pending; + assign arch_staged_txn_id = staged_txn_id; + assign arch_staged_next_pc = staged_next_pc; + assign arch_staged_next_fp = staged_next_fp; + assign arch_staged_result_crc = staged_result_crc; + assign arch_state_valid = state_valid; + assign arch_committed_pc = committed_pc; + assign arch_committed_fp = committed_fp; + assign arch_retire_seq = retire_seq; + assign arch_active_profile = active_profile; + assign arch_last_status = last_status; + assign arch_last_fault = last_fault; + assign arch_tx_busy = tx_busy; + assign arch_tx_index = tx_arch_index; + assign arch_tx_length = tx_arch_length; + assign arch_tx_status = tx_arch_status; + assign arch_tx_payload = tx_arch_payload; + assign arch_tx_payload_crc = tx_payload_crc; + assign arch_alu_busy = alu_busy; + assign arch_alu_phase = alu_arch_state; + assign arch_alu_operation = alu_arch_operation; + assign arch_alu_payload_index = alu_arch_payload_index; + assign arch_alu_result_index = alu_arch_result_index; + assign arch_alu_result = alu_result; + assign arch_encoder_busy = encoder_busy; + assign arch_encoder_bit_index = encoder_arch_bit_index; + assign arch_encoder_index = encoder_arch_saved_index; + assign arch_encoder_result = encoder_result; + assign arch_fault = fault; + assign arch_done_pulse = done_pulse; + task automatic emit_fault; input [7:0] status; input [31:0] txn; diff --git a/asic_core/rtl/lsc1_packet_rx.sv b/asic_core/rtl/lsc1_packet_rx.sv index f35d6c5..950b135 100644 --- a/asic_core/rtl/lsc1_packet_rx.sv +++ b/asic_core/rtl/lsc1_packet_rx.sv @@ -16,7 +16,12 @@ module lsc1_packet_rx ( output reg [2047:0] frame_payload, output reg fault_valid, output reg [7:0] fault_status, - output wire busy + output wire busy, + output wire [2:0] arch_state, + output wire [2:0] arch_header_index, + output wire [15:0] arch_body_index, arch_declared_length, + output wire [7:0] arch_version, arch_opcode, arch_flags, + output wire [31:0] arch_crc, arch_received_crc ); localparam [7:0] SOF = 8'ha1; localparam [7:0] VERSION = 8'h01; @@ -34,6 +39,10 @@ module lsc1_packet_rx ( reg [31:0] crc; reg [31:0] received_crc; assign busy = state != S_SOF || frame_valid || fault_valid; + assign arch_state = state; assign arch_header_index = header_index; + assign arch_body_index = body_index; assign arch_declared_length = declared_length; + assign arch_version = version; assign arch_opcode = opcode; assign arch_flags = flags; + assign arch_crc = crc; assign arch_received_crc = received_crc; function automatic [31:0] crc_byte; input [31:0] crc_in; diff --git a/asic_core/rtl/lsc1_packet_tx.sv b/asic_core/rtl/lsc1_packet_tx.sv index 6910680..1a38a5f 100644 --- a/asic_core/rtl/lsc1_packet_tx.sv +++ b/asic_core/rtl/lsc1_packet_tx.sv @@ -14,7 +14,10 @@ module lsc1_packet_tx ( output reg [31:0] payload_crc, output reg [7:0] tx_data, output wire tx_valid, - input wire tx_ready + input wire tx_ready, + output wire [15:0] arch_index, arch_length, + output wire [7:0] arch_status, + output wire [543:0] arch_payload ); reg active; reg [15:0] index; @@ -40,6 +43,8 @@ module lsc1_packet_tx ( assign busy = active; assign tx_valid = active; + assign arch_index = index; assign arch_length = saved_length; + assign arch_status = saved_status; assign arch_payload = saved_payload; always @(*) begin if (index == 0) tx_data = 8'h5a; diff --git a/asic_core/rtl/lsc1_stream_adapter.sv b/asic_core/rtl/lsc1_stream_adapter.sv index 3c7cb0c..30f837a 100644 --- a/asic_core/rtl/lsc1_stream_adapter.sv +++ b/asic_core/rtl/lsc1_stream_adapter.sv @@ -14,7 +14,11 @@ module lsc1_stream_adapter ( output wire busy, output reg done_pulse, output reg fault, - output reg [127:0] result + output reg [127:0] result, + output wire [2:0] arch_state, + output wire [7:0] arch_operation, + output wire [5:0] arch_payload_index, + output wire [4:0] arch_result_index ); localparam [7:0] OP_XOR = 8'h01, OP_MUL = 8'h02, OP_SET = 8'h03; localparam [2:0] S_IDLE = 3'd0, S_CLEAR = 3'd1, @@ -50,6 +54,8 @@ module lsc1_stream_adapter ( ); assign busy = state != S_IDLE; + assign arch_state = state; assign arch_operation = saved_operation; + assign arch_payload_index = payload_index; assign arch_result_index = result_index; always @(*) begin core_rx_valid = 1'b0; diff --git a/formal/ARCH_STATE.md b/formal/ARCH_STATE.md new file mode 100644 index 0000000..4d4b4f2 --- /dev/null +++ b/formal/ARCH_STATE.md @@ -0,0 +1,52 @@ +# LSC-1 registered architectural state + +`lsc1_packet_frontend` exports `arch_*` as a passive, clock-boundary observation +interface. It has no input and cannot alter the packet endpoint. The complete +machine-readable field map is `lsc1_packet_frontend_arch_state_map.json`. + +The state is partitioned exhaustively by `arch_phase` and the registered parser, +response, ALU, and encoder busy flags: reset, idle, parser, compute, response, +and retire. The partition names are review labels, not assumptions; the checker +asserts coverage mechanically. + +## Source-grounded inventory and dependency graph + +| State owner | Registered information exported | Future observable dependency | +| --- | --- | --- | +| RX parser | phase, header/body positions, declared length, header context, CRCs, complete accepted frame and parser fault | request acceptance and command dispatch | +| Frontend | compute phase, staged transaction/CRC, committed PC/FP, sequence, profile, status/fault | profile choice, RETIRE, STATUS, future request validation | +| TX serializer | busy, byte index, saved status/length/payload, payload CRC | `tx_valid` and every response byte under backpressure | +| ALU adapter | phase, operation, payload/result positions, result | deferred arithmetic completion | +| Field encoder | busy, bit index, saved index, result | pointer witness completion | + +``` +RX registered frame ──► frontend decode/compute ──► staged result ──► TX registered serializer ──► tx_valid/tx_data + │ │ │ + │ ├──► ALU adapter ────────┤ + │ └──► field encoder ──────┤ + └── parser position/CRC RETIRE ──► committed PC/FP, sequence + NEGOTIATE ──► active profile (capability 0x00000002) +``` + +All arrows cross registered boundaries except the listed busy/output functions. +The map checker requires every public `arch_*` port and every packet output to +be covered, and its self-mutation guard rejects a changed source mapping. + +`R(rtl, arch)` is direct equality to the mapped registered RTL signal. The only +derived fields are busy flags and protocol outputs, whose source registers are +listed in the RTL modules. Parser payload, framed opcode/length, TX payload and +serializer index are deliberately included: they can affect a later observable +response. Procedural decode temporaries (`txn_id`, offsets, decisions and local +write candidates) are excluded because they are not retained across a clock. + +The one-cycle relation is the production clocked transition relation under the +same `(rst_n, abort, rx_data, rx_valid, tx_ready)` inputs. Reset clears the map +with profile 1; idle stutters when no input is accepted and no response is +active. At every cycle the public packet outputs agree with their architectural +observations. No cutpoints, black boxes, symbolic bridge state, or ignored +output channel is used. + +This is a correspondence interface, not a claim of full LSC-1 refinement. The +next required proof is a phase-complete refinement from these fields to the +executable model; the smallest currently recorded failing partition must be +kept if that proof does not close. diff --git a/formal/lsc1_packet_frontend_arch_reset_idle.sv b/formal/lsc1_packet_frontend_arch_reset_idle.sv new file mode 100644 index 0000000..a2e824b --- /dev/null +++ b/formal/lsc1_packet_frontend_arch_reset_idle.sv @@ -0,0 +1,28 @@ +`default_nettype none +// Non-vacuous bounded R milestone for the registered parser partition. +// The frontend-level composition obligation is recorded separately when it +// cannot be flattened within the bounded diagnostic budget. +module lsc1_packet_frontend_arch_reset_idle; + (* anyseq *) reg clk, abort, rx_valid, frame_ready; + wire rst_n = 1'b0; + (* anyseq *) reg [7:0] rx_data; + wire rx_ready, frame_valid, fault_valid, busy; + wire [7:0] frame_opcode, fault_status; + wire [15:0] frame_length; + wire [2047:0] frame_payload; + wire [2:0] arch_state, arch_header_index; + wire [15:0] arch_body_index, arch_declared_length; + wire [7:0] arch_version, arch_opcode, arch_flags; + wire [31:0] arch_crc, arch_received_crc; + lsc1_packet_rx dut (.*); + always @(*) assume(clk == 1'b1); + always @(posedge clk) begin + if (!rst_n) begin + assert(arch_state == 0 && arch_header_index == 0 && arch_body_index == 0); + assert(arch_declared_length == 0 && arch_version == 0 && arch_opcode == 0 && arch_flags == 0); + assert(arch_crc == 32'hffffffff && arch_received_crc == 0); + assert(!frame_valid && !fault_valid && !busy); + end + end +endmodule +`default_nettype wire diff --git a/formal/lsc1_packet_frontend_arch_reset_idle.ys b/formal/lsc1_packet_frontend_arch_reset_idle.ys new file mode 100644 index 0000000..436faa9 --- /dev/null +++ b/formal/lsc1_packet_frontend_arch_reset_idle.ys @@ -0,0 +1,6 @@ +read_verilog -formal -sv asic_core/rtl/lsc1_packet_rx.sv formal/lsc1_packet_frontend_arch_reset_idle.sv +prep -top lsc1_packet_frontend_arch_reset_idle +flatten +opt +select -module lsc1_packet_frontend_arch_reset_idle +sat -seq 3 -prove-asserts -set-assumes -set-init-zero diff --git a/formal/lsc1_packet_frontend_arch_state_map.json b/formal/lsc1_packet_frontend_arch_state_map.json new file mode 100644 index 0000000..2095810 --- /dev/null +++ b/formal/lsc1_packet_frontend_arch_state_map.json @@ -0,0 +1,28 @@ +{ + "schema": 1, + "module": "lsc1_packet_frontend", + "relation": "R(rtl_state, arch_state) is direct field equality; every source is a registered RTL signal except parser_busy, tx_busy, alu_busy, encoder_busy, and output-valid/data, which are documented functions of the listed registered state.", + "fields": { + "arch_phase":"compute_state", "arch_parser_busy":"rx_busy", "arch_parser_phase":"parser_arch_state", + "arch_parser_header_index":"parser_arch_header_index", "arch_parser_body_index":"parser_arch_body_index", + "arch_parser_declared_length":"parser_arch_declared_length", "arch_parser_version":"parser_arch_version", + "arch_parser_opcode":"parser_arch_opcode", "arch_parser_flags":"parser_arch_flags", "arch_parser_crc":"parser_arch_crc", + "arch_parser_received_crc":"parser_arch_received_crc", "arch_frame_valid":"frame_valid", + "arch_frame_opcode":"frame_opcode", "arch_frame_length":"frame_length", "arch_frame_payload":"frame_payload", + "arch_rx_fault_valid":"rx_fault_valid", "arch_rx_fault_status":"rx_fault_status", + "arch_result_pending":"result_pending", "arch_staged_txn_id":"staged_txn_id", + "arch_staged_next_pc":"staged_next_pc", "arch_staged_next_fp":"staged_next_fp", + "arch_staged_result_crc":"staged_result_crc", "arch_state_valid":"state_valid", + "arch_committed_pc":"committed_pc", "arch_committed_fp":"committed_fp", "arch_retire_seq":"retire_seq", + "arch_active_profile":"active_profile", "arch_last_status":"last_status", "arch_last_fault":"last_fault", + "arch_tx_busy":"tx_busy", "arch_tx_index":"tx_arch_index", "arch_tx_length":"tx_arch_length", + "arch_tx_status":"tx_arch_status", "arch_tx_payload":"tx_arch_payload", + "arch_tx_payload_crc":"tx_payload_crc", "arch_alu_busy":"alu_busy", "arch_alu_phase":"alu_arch_state", + "arch_alu_operation":"alu_arch_operation", "arch_alu_payload_index":"alu_arch_payload_index", + "arch_alu_result_index":"alu_arch_result_index", "arch_alu_result":"alu_result", "arch_encoder_busy":"encoder_busy", + "arch_encoder_bit_index":"encoder_arch_bit_index", "arch_encoder_index":"encoder_arch_saved_index", + "arch_encoder_result":"encoder_result", "arch_fault":"fault", "arch_done_pulse":"done_pulse" + }, + "observable_outputs": ["rx_ready", "tx_data", "tx_valid", "busy", "fault", "done_pulse"], + "partitions": ["reset", "idle", "parser", "compute", "response", "retire"] +} diff --git a/results/arch-state-20260728/README.md b/results/arch-state-20260728/README.md new file mode 100644 index 0000000..f8b2169 --- /dev/null +++ b/results/arch-state-20260728/README.md @@ -0,0 +1,40 @@ +# Registered architectural-state milestone — blocked before full refinement + +This receipt is for the explicit `arch_*` observation interface introduced at +the same source revision. It is not a release-equivalence PASS and makes no +ASIC-readiness claim. + +## Completed, non-vacuous milestone + +`reset-idle.log` records Yosys 0.33 proving the parser partition's reset +establishment obligation (`SAT proof finished - no model found: SUCCESS`). The +bound is three sequential steps; the obligation has four reset assertions and +one reset input constraint. `interface-coverage.log` records 47 mapped fields +and all six packet output channels. The mapping checker includes a source-map +mutation guard. `rtl.log`, `differential.log`, and `mutation.log` are the +focused regression gates; their SHA-256 values are in `SHA256SUMS`. + +## Exact current blocker + +The next smallest unclosed obligation is **frontend idle/composition**: + +``` +R(frontend_rtl, arch) && idle(arch) && no_accept && !abort + => R(frontend_rtl', arch_transition(arch, inputs)) +``` + +The repository's existing executable LSC-1 model is Python transaction logic, +not a synthesizable one-cycle transition relation. It has no representation of +the RX/TX backpressure, ALU, or field-encoder intermediate registered phases. +Consequently, supplying an unconstrained `arch_transition` here would be the +forbidden symbolic bridge; deriving it by peeking into RTL would merely restate +RTL and would not establish refinement to the executable model. The bounded +parser reset proof is sound but does not discharge this frontend obligation. + +The required next architectural artifact is a reviewed, executable clocked +LSC-1 architecture transition module (including parser/TX stutter semantics), +or a reviewed refinement abstraction that relates its transaction steps to +those cycles. Until it exists, command-family, all-phase, and full sequential +equivalence milestones are deliberately marked BLOCKED rather than run as a +larger flat timeout. Capability `0x00000002` and forward-only rejection +`BAD_PROFILE=0x86` remain tested by the differential and RTL regressions. diff --git a/results/arch-state-20260728/SHA256SUMS b/results/arch-state-20260728/SHA256SUMS new file mode 100644 index 0000000..fec2139 --- /dev/null +++ b/results/arch-state-20260728/SHA256SUMS @@ -0,0 +1,6 @@ +b91294fb84265d3d8a568773e69bf4be6989b8b2495d06ea1b2b166c021228c2 results/arch-state-20260728/differential.log +4e79a6223338d65e7609b234e33c62cbad037f3a27f1f6fe795f6d61e1ecc281 results/arch-state-20260728/interface-coverage.log +c3a2a9f65cc2cc17d980a939d510da253dba23547a875440b950137da81581c5 results/arch-state-20260728/mutation.log +ff5d1517dabeb83213ca643ef75a392a17003417d41d11b2dc385450e0121825 results/arch-state-20260728/reset-idle.log +1232f3d6bb4138ddf396895ed067274601df653827828396b79a88b2430a438d results/arch-state-20260728/rtl.log +00486fb8958a8818e17326967dee9e5fcfaf602093c282a957229b491eefcf99 results/arch-state-20260728/versions-and-inputs.log diff --git a/results/arch-state-20260728/differential.log b/results/arch-state-20260728/differential.log new file mode 100644 index 0000000..3b83974 --- /dev/null +++ b/results/arch-state-20260728/differential.log @@ -0,0 +1,9 @@ +test_adversarial_jump_inverse_and_xor_backsolve_match_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_adversarial_jump_inverse_and_xor_backsolve_match_model) ... ok +test_deref_and_jump_faults_match_the_executable_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_faults_match_the_executable_model) ... ok +test_deref_and_jump_match_the_executable_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_match_the_executable_model) ... ok +test_seeded_set_xor_mul_and_frame_faults (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_seeded_set_xor_mul_and_frame_faults) ... ok + +---------------------------------------------------------------------- +Ran 4 tests in 1.117s + +OK diff --git a/results/arch-state-20260728/interface-coverage.log b/results/arch-state-20260728/interface-coverage.log new file mode 100644 index 0000000..aafbe82 --- /dev/null +++ b/results/arch-state-20260728/interface-coverage.log @@ -0,0 +1 @@ +arch-state map: 47 fields; all outputs and 6 observable channels covered diff --git a/results/arch-state-20260728/mutation.log b/results/arch-state-20260728/mutation.log new file mode 100644 index 0000000..49bc124 --- /dev/null +++ b/results/arch-state-20260728/mutation.log @@ -0,0 +1,3 @@ +make: Entering directory '/workspaces/mission-cbe073d0/work/pr30/test/packet_frontend' +PASS: BUSY, SET value, RETIRE ID, ABORT, length-order, and profile mutations were detected +make: Leaving directory '/workspaces/mission-cbe073d0/work/pr30/test/packet_frontend' diff --git a/results/arch-state-20260728/reset-idle.log b/results/arch-state-20260728/reset-idle.log new file mode 100644 index 0000000..5b49128 --- /dev/null +++ b/results/arch-state-20260728/reset-idle.log @@ -0,0 +1,3088 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Executing script file `formal/lsc1_packet_frontend_arch_reset_idle.ys' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_rx.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: formal/lsc1_packet_frontend_arch_reset_idle.sv +Parsing formal SystemVerilog input from `formal/lsc1_packet_frontend_arch_reset_idle.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend_arch_reset_idle'. +Successfully finished Verilog frontend. + +3. Executing PREP pass. + +3.1. Executing HIERARCHY pass (managing design hierarchy). + +3.1.1. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend_arch_reset_idle +Used module: \lsc1_packet_rx + +3.1.2. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend_arch_reset_idle +Used module: \lsc1_packet_rx +Removed 0 unused modules. +Module lsc1_packet_frontend_arch_reset_idle directly or indirectly contains formal properties -> setting "keep" attribute. + +3.2. Executing PROC pass (convert processes to netlists). + +3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 11 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_rx.sv:71$23 in module lsc1_packet_rx. +Removed a total of 0 dead cases. + +3.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 25 assignments to connections. + +3.2.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$294'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_EN = 1'0 +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$292'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_EN = 1'0 +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$290'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_EN = 1'0 +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$288'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN = 1'0 + +3.2.5. Executing PROC_ARST pass (detect async resets in processes). + +3.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$294'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$292'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$290'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$288'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + 1/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN[0:0]$255 + 2/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_CHECK[0:0]$254 + 3/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_EN[0:0]$257 + 4/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_CHECK[0:0]$256 + 5/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_EN[0:0]$259 + 6/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_CHECK[0:0]$258 + 7/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_EN[0:0]$261 + 8/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_CHECK[0:0]$260 +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. +Creating decoders for process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + 1/89: $0\received_crc[31:0] [31:24] + 2/89: $0\received_crc[31:0] [23:16] + 3/89: $0\received_crc[31:0] [15:8] + 4/89: $0\received_crc[31:0] [7:0] + 5/89: $5$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$185 + 6/89: $5$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$184 + 7/89: $5$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$186 + 8/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$177 + 9/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$180 + 10/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$181 + 11/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$179 + 12/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$178 + 13/89: $4$lookahead\frame_payload$22[2047:0]$182 + 14/89: $4$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$176 + 15/89: $4$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$175 + 16/89: $4$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$174 + 17/89: $0\declared_length[15:0] [15:8] + 18/89: $0\declared_length[15:0] [7:0] + 19/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$103 + 20/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$102 + 21/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$101 + 22/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$85 + 23/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$84 + 24/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$83 + 25/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$82 + 26/89: $3$lookahead\frame_payload$22[2047:0]$99 + 27/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$98 + 28/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$97 + 29/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$96 + 30/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$95 + 31/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$94 + 32/89: $3$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$93 + 33/89: $3$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$92 + 34/89: $3$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$91 + 35/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$90 + 36/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$89 + 37/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$88 + 38/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$87 + 39/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$86 + 40/89: $2$lookahead\frame_payload$22[2047:0]$81 + 41/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$80 + 42/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$79 + 43/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$78 + 44/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$77 + 45/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$76 + 46/89: $2$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$75 + 47/89: $2$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$74 + 48/89: $2$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$73 + 49/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$72 + 50/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$71 + 51/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$70 + 52/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$69 + 53/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$68 + 54/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$67 + 55/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$66 + 56/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$65 + 57/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$64 + 58/89: $1$lookahead\frame_payload$22[2047:0]$61 + 59/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$60 + 60/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$59 + 61/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$58 + 62/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$57 + 63/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$56 + 64/89: $1$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$55 + 65/89: $1$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$54 + 66/89: $1$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$53 + 67/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$52 + 68/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$51 + 69/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$50 + 70/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$49 + 71/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$48 + 72/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$47 + 73/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$46 + 74/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$45 + 75/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$44 + 76/89: $5$lookahead\frame_payload$22[2047:0]$187 + 77/89: $0\crc[31:0] + 78/89: $0\flags[7:0] + 79/89: $0\opcode[7:0] + 80/89: $0\version[7:0] + 81/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$104 + 82/89: $0\body_index[15:0] + 83/89: $0\header_index[2:0] + 84/89: $0\state[2:0] + 85/89: $0\fault_status[7:0] + 86/89: $0\fault_valid[0:0] + 87/89: $0\frame_length[15:0] + 88/89: $0\frame_opcode[7:0] + 89/89: $0\frame_valid[0:0] + +3.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$239_CHECK' from process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. +No latch inferred for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$239_EN' from process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. + +3.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1240' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1241' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1242' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1243' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1244' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1245' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1246' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1247' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1248' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1249' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1250' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_payload' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1251' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1252' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_status' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1253' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\state' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1254' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\header_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1255' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\body_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1256' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\declared_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1257' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\version' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1258' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1259' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\flags' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1260' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1261' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\received_crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1262' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1263' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1264' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1265' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1266' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1267' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1268' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1269' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1270' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1271' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1272' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1273' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1274' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1275' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1276' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1277' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1278' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1279' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$lookahead\frame_payload$22' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1280' with positive edge clock. + +3.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$294'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$292'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$290'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$288'. +Found and cleaned up 1 empty switch in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. +Found and cleaned up 14 empty switches in `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. +Removing empty process `lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. +Cleaned up 15 empty switches. + +3.2.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + +Optimizing module lsc1_packet_rx. + + +3.3. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 215 unused cells and 635 unused wires. + + +3.5. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_frontend_arch_reset_idle... +Checking module lsc1_packet_rx... +Found and reported 0 problems. + +3.6. Executing OPT pass (performing simple optimizations). + +3.6.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.6.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. + +Finding identical cells in module `\lsc1_packet_rx'. + +Removed a total of 55 cells. + +3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$488. + dead port 2/2 on $mux $procmux$490. + dead port 1/2 on $mux $procmux$493. + dead port 2/2 on $mux $procmux$649. + dead port 1/2 on $mux $procmux$652. + dead port 1/2 on $mux $procmux$780. + dead port 2/2 on $mux $procmux$944. + dead port 2/2 on $mux $procmux$946. + dead port 2/2 on $mux $procmux$948. + dead port 1/2 on $mux $procmux$951. +Removed 10 multiplexer ports. + + +3.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. + Optimizing cells in module \lsc1_packet_rx. + New ctrl vector for $pmux cell $procmux$1083: { $auto$opt_reduce.cc:134:opt_pmux$1332 $procmux$1038_CMP } + Optimizing cells in module \lsc1_packet_rx. +Performed a total of 1 changes. + +3.6.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Finding identical cells in module `\lsc1_packet_rx'. + +Removed a total of 15 cells. + +3.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 0 unused cells and 88 unused wires. + + +3.6.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.6.8. Rerunning OPT passes. (Maybe there is more to do..) + +3.6.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.6.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. + Optimizing cells in module \lsc1_packet_rx. +Performed a total of 0 changes. + +3.6.11. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Finding identical cells in module `\lsc1_packet_rx'. +Removed a total of 0 cells. + +3.6.12. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. + +3.6.13. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.6.14. Finished OPT passes. (There is nothing left to do.) + +3.7. Executing WREDUCE pass (reducing word size of cells). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$ne$asic_core/rtl/lsc1_packet_rx.sv:60$16 ($ne). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1283 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1285 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1287 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1289 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1291 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1293 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1295 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1297 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1299 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1301 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1303 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1305 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1307 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1309 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1311 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1313 ($not). +Removed top 7 bits (of 16) from port B of cell lsc1_packet_rx.$gt$asic_core/rtl/lsc1_packet_rx.sv:122$171 ($gt). +Removed top 7 bits (of 16) from port B of cell lsc1_packet_rx.$lt$asic_core/rtl/lsc1_packet_rx.sv:135$183 ($lt). +Removed top 28 bits (of 32) from port B of cell lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188 ($mul). +Removed top 12 bits (of 32) from port Y of cell lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188 ($mul). +Removed top 12 bits (of 32) from port A of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 11 bits (of 32) from port Y of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 11 bits (of 33) from port A of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Converting cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub) from signed to unsigned. +Removed top 10 bits (of 33) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 1 bits (of 22) from port A of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 1 bits (of 23) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 11 bits (of 33) from port A of cell lsc1_packet_rx.$neg$asic_core/rtl/lsc1_packet_rx.sv:0$191 ($neg). +Removed top 15 bits (of 32) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:139$233 ($sub). +Removed top 7 bits (of 8) from port B of cell lsc1_packet_rx.$ne$asic_core/rtl/lsc1_packet_rx.sv:147$236 ($ne). +Removed top 24 bits (of 32) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1281 ($not). +Removed top 30 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$331_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$348_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1012_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1035_CMP0 ($eq). +Removed top 30 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$1073_CMP0 ($eq). +Removed top 2 bits (of 3) from mux cell lsc1_packet_rx.$procmux$1081 ($mux). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1085_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1086_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1087_CMP0 ($eq). +Removed top 1 bits (of 3) from mux cell lsc1_packet_rx.$procmux$1091 ($mux). +Removed top 11 bits (of 32) from wire lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189_Y. +Removed top 12 bits (of 32) from wire lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188_Y. +Removed top 2 bits (of 3) from wire lsc1_packet_rx.$procmux$1081_Y. +Removed top 1 bits (of 3) from wire lsc1_packet_rx.$procmux$1091_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$110_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$114_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$118_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$122_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$126_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$130_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$134_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$139_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$143_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$147_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$151_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$155_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$159_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$163_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$167_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$109_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$113_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$117_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$121_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$125_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$129_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$133_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$142_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$146_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$150_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$154_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$158_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$162_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$166_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$xor$asic_core/rtl/lsc1_packet_rx.sv:53$138_Y. + +3.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 0 unused cells and 34 unused wires. + + +3.9. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.10. Executing OPT pass (performing simple optimizations). + +3.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Finding identical cells in module `\lsc1_packet_rx'. +Removed a total of 0 cells. + +3.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. + +3.10.4. Finished fast OPT passes. + +3.11. Printing statistics. + +=== lsc1_packet_frontend_arch_reset_idle === + + Number of wires: 48 + Number of wire bits: 2248 + Number of public wires: 23 + Number of public wire bits: 2223 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 36 + $anyseq 5 + $assert 4 + $assume 1 + $dff 5 + $eq 1 + $logic_and 8 + $logic_not 11 + lsc1_packet_rx 1 + +=== lsc1_packet_rx === + + Number of wires: 237 + Number of wire bits: 25229 + Number of public wires: 33 + Number of public wire bits: 2350 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 211 + $add 3 + $and 1 + $dff 15 + $eq 9 + $gt 1 + $logic_and 5 + $logic_not 6 + $logic_or 3 + $lt 2 + $mul 1 + $mux 120 + $ne 4 + $neg 1 + $not 19 + $or 1 + $pmux 12 + $reduce_bool 2 + $reduce_or 1 + $shift 2 + $sub 2 + $xor 1 + +=== design hierarchy === + + lsc1_packet_frontend_arch_reset_idle 1 + lsc1_packet_rx 1 + + Number of wires: 285 + Number of wire bits: 27477 + Number of public wires: 56 + Number of public wire bits: 4573 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 246 + $add 3 + $and 1 + $anyseq 5 + $assert 4 + $assume 1 + $dff 20 + $eq 10 + $gt 1 + $logic_and 13 + $logic_not 17 + $logic_or 3 + $lt 2 + $mul 1 + $mux 120 + $ne 4 + $neg 1 + $not 19 + $or 1 + $pmux 12 + $reduce_bool 2 + $reduce_or 1 + $shift 2 + $sub 2 + $xor 1 + +3.12. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_frontend_arch_reset_idle... +Checking module lsc1_packet_rx... +Found and reported 0 problems. + +4. Executing FLATTEN pass (flatten design). +Deleting now unused module lsc1_packet_rx. + + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. + +Removed a total of 20 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\dut.$procmux$539. + dead port 2/2 on $mux $flatten\dut.$procmux$539. + dead port 1/2 on $mux $flatten\dut.$procmux$537. + dead port 2/2 on $mux $flatten\dut.$procmux$537. + dead port 1/2 on $mux $flatten\dut.$procmux$535. + dead port 2/2 on $mux $flatten\dut.$procmux$535. + dead port 1/2 on $mux $flatten\dut.$procmux$486. + dead port 2/2 on $mux $flatten\dut.$procmux$486. + dead port 1/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$137. + dead port 2/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$137. + dead port 1/2 on $mux $flatten\dut.$procmux$373. + dead port 2/2 on $mux $flatten\dut.$procmux$373. + dead port 1/3 on $pmux $flatten\dut.$procmux$370. + dead port 2/3 on $pmux $flatten\dut.$procmux$370. + dead port 3/3 on $pmux $flatten\dut.$procmux$370. + dead port 1/2 on $mux $flatten\dut.$procmux$368. + dead port 2/2 on $mux $flatten\dut.$procmux$368. + dead port 1/2 on $mux $flatten\dut.$procmux$365. + dead port 2/2 on $mux $flatten\dut.$procmux$365. + dead port 1/2 on $mux $flatten\dut.$procmux$355. + dead port 2/2 on $mux $flatten\dut.$procmux$355. + dead port 1/3 on $pmux $flatten\dut.$procmux$352. + dead port 2/3 on $pmux $flatten\dut.$procmux$352. + dead port 3/3 on $pmux $flatten\dut.$procmux$352. + dead port 1/2 on $mux $flatten\dut.$procmux$350. + dead port 2/2 on $mux $flatten\dut.$procmux$350. + dead port 1/2 on $mux $flatten\dut.$procmux$347. + dead port 2/2 on $mux $flatten\dut.$procmux$347. + dead port 1/2 on $mux $flatten\dut.$procmux$338. + dead port 2/2 on $mux $flatten\dut.$procmux$338. + dead port 1/3 on $pmux $flatten\dut.$procmux$335. + dead port 2/3 on $pmux $flatten\dut.$procmux$335. + dead port 3/3 on $pmux $flatten\dut.$procmux$335. + dead port 1/2 on $mux $flatten\dut.$procmux$333. + dead port 2/2 on $mux $flatten\dut.$procmux$333. + dead port 1/2 on $mux $flatten\dut.$procmux$330. + dead port 2/2 on $mux $flatten\dut.$procmux$330. + dead port 1/2 on $mux $flatten\dut.$procmux$322. + dead port 2/2 on $mux $flatten\dut.$procmux$322. + dead port 1/3 on $pmux $flatten\dut.$procmux$319. + dead port 2/3 on $pmux $flatten\dut.$procmux$319. + dead port 3/3 on $pmux $flatten\dut.$procmux$319. + dead port 1/2 on $mux $flatten\dut.$procmux$317. + dead port 2/2 on $mux $flatten\dut.$procmux$317. + dead port 1/2 on $mux $flatten\dut.$procmux$314. + dead port 2/2 on $mux $flatten\dut.$procmux$314. + dead port 1/2 on $mux $flatten\dut.$procmux$1235. + dead port 2/2 on $mux $flatten\dut.$procmux$1235. + dead port 1/2 on $mux $flatten\dut.$procmux$1233. + dead port 2/2 on $mux $flatten\dut.$procmux$1233. + dead port 1/2 on $mux $flatten\dut.$procmux$1231. + dead port 2/2 on $mux $flatten\dut.$procmux$1231. + dead port 1/2 on $mux $flatten\dut.$procmux$1228. + dead port 2/2 on $mux $flatten\dut.$procmux$1228. + dead port 1/2 on $mux $flatten\dut.$procmux$1226. + dead port 2/2 on $mux $flatten\dut.$procmux$1226. + dead port 1/2 on $mux $flatten\dut.$procmux$1223. + dead port 2/2 on $mux $flatten\dut.$procmux$1223. + dead port 1/2 on $mux $flatten\dut.$procmux$1220. + dead port 2/2 on $mux $flatten\dut.$procmux$1220. + dead port 1/2 on $mux $flatten\dut.$procmux$1215. + dead port 2/2 on $mux $flatten\dut.$procmux$1215. + dead port 1/2 on $mux $flatten\dut.$procmux$1210. + dead port 2/2 on $mux $flatten\dut.$procmux$1210. + dead port 1/2 on $mux $flatten\dut.$procmux$1208. + dead port 2/2 on $mux $flatten\dut.$procmux$1208. + dead port 1/2 on $mux $flatten\dut.$procmux$1206. + dead port 2/2 on $mux $flatten\dut.$procmux$1206. + dead port 1/2 on $mux $flatten\dut.$procmux$1203. + dead port 2/2 on $mux $flatten\dut.$procmux$1203. + dead port 1/2 on $mux $flatten\dut.$procmux$1201. + dead port 2/2 on $mux $flatten\dut.$procmux$1201. + dead port 1/2 on $mux $flatten\dut.$procmux$1198. + dead port 2/2 on $mux $flatten\dut.$procmux$1198. + dead port 1/2 on $mux $flatten\dut.$procmux$1195. + dead port 2/2 on $mux $flatten\dut.$procmux$1195. + dead port 1/2 on $mux $flatten\dut.$procmux$1187. + dead port 2/2 on $mux $flatten\dut.$procmux$1187. + dead port 1/2 on $mux $flatten\dut.$procmux$1185. + dead port 2/2 on $mux $flatten\dut.$procmux$1185. + dead port 1/2 on $mux $flatten\dut.$procmux$1183. + dead port 2/2 on $mux $flatten\dut.$procmux$1183. + dead port 1/2 on $mux $flatten\dut.$procmux$1180. + dead port 2/2 on $mux $flatten\dut.$procmux$1180. + dead port 1/2 on $mux $flatten\dut.$procmux$1178. + dead port 2/2 on $mux $flatten\dut.$procmux$1178. + dead port 1/2 on $mux $flatten\dut.$procmux$1175. + dead port 2/2 on $mux $flatten\dut.$procmux$1175. + dead port 1/2 on $mux $flatten\dut.$procmux$1172. + dead port 2/2 on $mux $flatten\dut.$procmux$1172. + dead port 1/2 on $mux $flatten\dut.$procmux$1164. + dead port 2/2 on $mux $flatten\dut.$procmux$1164. + dead port 1/2 on $mux $flatten\dut.$procmux$1161. + dead port 2/2 on $mux $flatten\dut.$procmux$1161. + dead port 1/2 on $mux $flatten\dut.$procmux$1157. + dead port 2/2 on $mux $flatten\dut.$procmux$1157. + dead port 1/2 on $mux $flatten\dut.$procmux$1155. + dead port 2/2 on $mux $flatten\dut.$procmux$1155. + dead port 1/4 on $pmux $flatten\dut.$procmux$1151. + dead port 2/4 on $pmux $flatten\dut.$procmux$1151. + dead port 3/4 on $pmux $flatten\dut.$procmux$1151. + dead port 4/4 on $pmux $flatten\dut.$procmux$1151. + dead port 1/2 on $mux $flatten\dut.$procmux$1149. + dead port 2/2 on $mux $flatten\dut.$procmux$1149. + dead port 1/2 on $mux $flatten\dut.$procmux$1146. + dead port 2/2 on $mux $flatten\dut.$procmux$1146. + dead port 1/2 on $mux $flatten\dut.$procmux$1144. + dead port 2/2 on $mux $flatten\dut.$procmux$1144. + dead port 1/2 on $mux $flatten\dut.$procmux$1141. + dead port 2/2 on $mux $flatten\dut.$procmux$1141. + dead port 1/2 on $mux $flatten\dut.$procmux$1138. + dead port 2/2 on $mux $flatten\dut.$procmux$1138. + dead port 1/2 on $mux $flatten\dut.$procmux$1133. + dead port 2/2 on $mux $flatten\dut.$procmux$1133. + dead port 1/2 on $mux $flatten\dut.$procmux$1128. + dead port 2/2 on $mux $flatten\dut.$procmux$1128. + dead port 1/2 on $mux $flatten\dut.$procmux$1125. + dead port 2/2 on $mux $flatten\dut.$procmux$1125. + dead port 1/2 on $mux $flatten\dut.$procmux$1121. + dead port 2/2 on $mux $flatten\dut.$procmux$1121. + dead port 1/2 on $mux $flatten\dut.$procmux$1119. + dead port 2/2 on $mux $flatten\dut.$procmux$1119. + dead port 1/4 on $pmux $flatten\dut.$procmux$1115. + dead port 2/4 on $pmux $flatten\dut.$procmux$1115. + dead port 3/4 on $pmux $flatten\dut.$procmux$1115. + dead port 4/4 on $pmux $flatten\dut.$procmux$1115. + dead port 1/2 on $mux $flatten\dut.$procmux$1113. + dead port 2/2 on $mux $flatten\dut.$procmux$1113. + dead port 1/2 on $mux $flatten\dut.$procmux$1110. + dead port 2/2 on $mux $flatten\dut.$procmux$1110. + dead port 1/2 on $mux $flatten\dut.$procmux$1108. + dead port 2/2 on $mux $flatten\dut.$procmux$1108. + dead port 1/2 on $mux $flatten\dut.$procmux$1105. + dead port 2/2 on $mux $flatten\dut.$procmux$1105. + dead port 1/2 on $mux $flatten\dut.$procmux$1102. + dead port 2/2 on $mux $flatten\dut.$procmux$1102. + dead port 1/2 on $mux $flatten\dut.$procmux$1094. + dead port 2/2 on $mux $flatten\dut.$procmux$1094. + dead port 1/2 on $mux $flatten\dut.$procmux$1091. + dead port 2/2 on $mux $flatten\dut.$procmux$1091. + dead port 1/3 on $pmux $flatten\dut.$procmux$1083. + dead port 2/3 on $pmux $flatten\dut.$procmux$1083. + dead port 3/3 on $pmux $flatten\dut.$procmux$1083. + dead port 1/2 on $mux $flatten\dut.$procmux$1081. + dead port 2/2 on $mux $flatten\dut.$procmux$1081. + dead port 1/4 on $pmux $flatten\dut.$procmux$1077. + dead port 2/4 on $pmux $flatten\dut.$procmux$1077. + dead port 3/4 on $pmux $flatten\dut.$procmux$1077. + dead port 4/4 on $pmux $flatten\dut.$procmux$1077. + dead port 1/2 on $mux $flatten\dut.$procmux$1075. + dead port 2/2 on $mux $flatten\dut.$procmux$1075. + dead port 1/2 on $mux $flatten\dut.$procmux$1072. + dead port 2/2 on $mux $flatten\dut.$procmux$1072. + dead port 1/2 on $mux $flatten\dut.$procmux$1062. + dead port 2/2 on $mux $flatten\dut.$procmux$1062. + dead port 1/2 on $mux $flatten\dut.$procmux$1060. + dead port 2/2 on $mux $flatten\dut.$procmux$1060. + dead port 1/2 on $mux $flatten\dut.$procmux$1055. + dead port 2/2 on $mux $flatten\dut.$procmux$1055. + dead port 1/2 on $mux $flatten\dut.$procmux$1052. + dead port 2/2 on $mux $flatten\dut.$procmux$1052. + dead port 1/3 on $pmux $flatten\dut.$procmux$1049. + dead port 2/3 on $pmux $flatten\dut.$procmux$1049. + dead port 3/3 on $pmux $flatten\dut.$procmux$1049. + dead port 1/2 on $mux $flatten\dut.$procmux$1041. + dead port 2/2 on $mux $flatten\dut.$procmux$1041. + dead port 1/2 on $mux $flatten\dut.$procmux$1037. + dead port 2/2 on $mux $flatten\dut.$procmux$1037. + dead port 1/2 on $mux $flatten\dut.$procmux$551. + dead port 2/2 on $mux $flatten\dut.$procmux$551. + dead port 1/4 on $pmux $flatten\dut.$procmux$1034. + dead port 2/4 on $pmux $flatten\dut.$procmux$1034. + dead port 3/4 on $pmux $flatten\dut.$procmux$1034. + dead port 4/4 on $pmux $flatten\dut.$procmux$1034. + dead port 1/2 on $mux $flatten\dut.$procmux$1013. + dead port 2/2 on $mux $flatten\dut.$procmux$1013. + dead port 1/2 on $mux $flatten\dut.$procmux$549. + dead port 2/2 on $mux $flatten\dut.$procmux$549. + dead port 1/2 on $mux $flatten\dut.$procmux$1011. + dead port 2/2 on $mux $flatten\dut.$procmux$1011. + dead port 1/2 on $mux $flatten\dut.$procmux$1009. + dead port 2/2 on $mux $flatten\dut.$procmux$1009. + dead port 1/2 on $mux $flatten\dut.$procmux$994. + dead port 2/2 on $mux $flatten\dut.$procmux$994. + dead port 1/2 on $mux $flatten\dut.$procmux$992. + dead port 2/2 on $mux $flatten\dut.$procmux$992. + dead port 1/2 on $mux $flatten\dut.$procmux$980. + dead port 2/2 on $mux $flatten\dut.$procmux$980. + dead port 1/2 on $mux $flatten\dut.$procmux$978. + dead port 2/2 on $mux $flatten\dut.$procmux$978. + dead port 1/2 on $mux $flatten\dut.$procmux$976. + dead port 2/2 on $mux $flatten\dut.$procmux$976. + dead port 1/2 on $mux $flatten\dut.$procmux$965. + dead port 2/2 on $mux $flatten\dut.$procmux$965. + dead port 1/2 on $mux $flatten\dut.$procmux$996. + dead port 2/2 on $mux $flatten\dut.$procmux$996. + dead port 1/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$170. + dead port 2/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$170. + dead port 1/2 on $mux $flatten\dut.$procmux$962. + dead port 2/2 on $mux $flatten\dut.$procmux$962. + dead port 1/4 on $pmux $flatten\dut.$procmux$958. + dead port 2/4 on $pmux $flatten\dut.$procmux$958. + dead port 3/4 on $pmux $flatten\dut.$procmux$958. + dead port 4/4 on $pmux $flatten\dut.$procmux$958. + dead port 1/2 on $mux $flatten\dut.$procmux$956. + dead port 2/2 on $mux $flatten\dut.$procmux$956. + dead port 1/2 on $mux $flatten\dut.$procmux$942. + dead port 2/2 on $mux $flatten\dut.$procmux$942. + dead port 1/2 on $mux $flatten\dut.$procmux$777. + dead port 2/2 on $mux $flatten\dut.$procmux$777. + dead port 1/3 on $pmux $flatten\dut.$procmux$646. + dead port 2/3 on $pmux $flatten\dut.$procmux$646. + dead port 3/3 on $pmux $flatten\dut.$procmux$646. + dead port 1/2 on $mux $flatten\dut.$procmux$553. + dead port 2/2 on $mux $flatten\dut.$procmux$553. +Removed 215 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Removed a total of 0 cells. + +5.6. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 8 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 9 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 10 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 11 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 12 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 13 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 14 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 15 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 16 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 17 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 18 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 19 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 20 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 21 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 22 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 23 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 24 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 25 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 26 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 27 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 28 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 29 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 30 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 31 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 0 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 1 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 2 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 3 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 4 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 5 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 6 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 7 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 8 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 9 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 10 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 11 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 12 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 13 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 14 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 15 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 16 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 17 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 18 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 19 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 20 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 21 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 22 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 23 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 24 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 25 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 26 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 27 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 28 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 29 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 30 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 31 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 8 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 9 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 10 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 11 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 12 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 13 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 14 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 15 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1255 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1255 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1255 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1252 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 8 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 9 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 10 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 11 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 12 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 13 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 14 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 15 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 16 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 17 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 18 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 19 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 20 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 21 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 22 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 23 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 24 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 25 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 26 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 27 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 28 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 29 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 30 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 31 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 32 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 33 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 34 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 35 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 36 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 37 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 38 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 39 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 40 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 41 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 42 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 43 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 44 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 45 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 46 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 47 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 48 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 49 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 50 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 51 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 52 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 53 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 54 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 55 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 56 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 57 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 58 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 59 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 60 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 61 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 62 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 63 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 64 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 65 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 66 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 67 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 68 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 69 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 70 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 71 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 72 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 73 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 74 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 75 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 76 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 77 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 78 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 79 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 80 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 81 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 82 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 83 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 84 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 85 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 86 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 87 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 88 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 89 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 90 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 91 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 92 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 93 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 94 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 95 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 96 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 97 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 98 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 99 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 100 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 101 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 102 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 103 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 104 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 105 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 106 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 107 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 108 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 109 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 110 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 111 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 112 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 113 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 114 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 115 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 116 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 117 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 118 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 119 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 120 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 121 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 122 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 123 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 124 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 125 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 126 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 127 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 128 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 129 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 130 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 131 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 132 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 133 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 134 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 135 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 136 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 137 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 138 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 139 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 140 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 141 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 142 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 143 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 144 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 145 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 146 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 147 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 148 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 149 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 150 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 151 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 152 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 153 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 154 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 155 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 156 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 157 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 158 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 159 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 160 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 161 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 162 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 163 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 164 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 165 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 166 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 167 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 168 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 169 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 170 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 171 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 172 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 173 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 174 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 175 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 176 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 177 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 178 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 179 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 180 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 181 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 182 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 183 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 184 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 185 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 186 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 187 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 188 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 189 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 190 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 191 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 192 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 193 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 194 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 195 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 196 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 197 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 198 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 199 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 200 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 201 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 202 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 203 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 204 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 205 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 206 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 207 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 208 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 209 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 210 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 211 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 212 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 213 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 214 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 215 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 216 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 217 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 218 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 219 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 220 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 221 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 222 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 223 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 224 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 225 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 226 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 227 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 228 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 229 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 230 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 231 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 232 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 233 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 234 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 235 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 236 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 237 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 238 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 239 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 240 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 241 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 242 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 243 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 244 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 245 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 246 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 247 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 248 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 249 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 250 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 251 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 252 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 253 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 254 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 255 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 256 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 257 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 258 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 259 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 260 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 261 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 262 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 263 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 264 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 265 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 266 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 267 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 268 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 269 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 270 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 271 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 272 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 273 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 274 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 275 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 276 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 277 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 278 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 279 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 280 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 281 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 282 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 283 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 284 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 285 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 286 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 287 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 288 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 289 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 290 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 291 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 292 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 293 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 294 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 295 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 296 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 297 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 298 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 299 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 300 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 301 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 302 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 303 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 304 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 305 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 306 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 307 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 308 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 309 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 310 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 311 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 312 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 313 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 314 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 315 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 316 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 317 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 318 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 319 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 320 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 321 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 322 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 323 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 324 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 325 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 326 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 327 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 328 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 329 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 330 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 331 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 332 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 333 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 334 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 335 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 336 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 337 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 338 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 339 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 340 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 341 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 342 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 343 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 344 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 345 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 346 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 347 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 348 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 349 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 350 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 351 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 352 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 353 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 354 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 355 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 356 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 357 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 358 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 359 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 360 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 361 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 362 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 363 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 364 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 365 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 366 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 367 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 368 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 369 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 370 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 371 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 372 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 373 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 374 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 375 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 376 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 377 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 378 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 379 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 380 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 381 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 382 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 383 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 384 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 385 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 386 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 387 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 388 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 389 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 390 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 391 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 392 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 393 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 394 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 395 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 396 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 397 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 398 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 399 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 400 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 401 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 402 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 403 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 404 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 405 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 406 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 407 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 408 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 409 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 410 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 411 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 412 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 413 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 414 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 415 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 416 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 417 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 418 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 419 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 420 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 421 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 422 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 423 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 424 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 425 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 426 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 427 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 428 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 429 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 430 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 431 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 432 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 433 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 434 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 435 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 436 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 437 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 438 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 439 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 440 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 441 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 442 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 443 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 444 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 445 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 446 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 447 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 448 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 449 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 450 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 451 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 452 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 453 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 454 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 455 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 456 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 457 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 458 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 459 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 460 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 461 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 462 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 463 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 464 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 465 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 466 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 467 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 468 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 469 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 470 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 471 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 472 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 473 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 474 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 475 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 476 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 477 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 478 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 479 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 480 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 481 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 482 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 483 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 484 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 485 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 486 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 487 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 488 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 489 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 490 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 491 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 492 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 493 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 494 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 495 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 496 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 497 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 498 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 499 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 500 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 501 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 502 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 503 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 504 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 505 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 506 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 507 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 508 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 509 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 510 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 511 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 512 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 513 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 514 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 515 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 516 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 517 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 518 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 519 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 520 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 521 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 522 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 523 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 524 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 525 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 526 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 527 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 528 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 529 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 530 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 531 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 532 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 533 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 534 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 535 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 536 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 537 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 538 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 539 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 540 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 541 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 542 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 543 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 544 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 545 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 546 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 547 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 548 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 549 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 550 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 551 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 552 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 553 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 554 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 555 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 556 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 557 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 558 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 559 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 560 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 561 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 562 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 563 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 564 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 565 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 566 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 567 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 568 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 569 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 570 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 571 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 572 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 573 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 574 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 575 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 576 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 577 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 578 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 579 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 580 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 581 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 582 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 583 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 584 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 585 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 586 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 587 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 588 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 589 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 590 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 591 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 592 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 593 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 594 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 595 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 596 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 597 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 598 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 599 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 600 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 601 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 602 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 603 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 604 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 605 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 606 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 607 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 608 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 609 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 610 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 611 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 612 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 613 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 614 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 615 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 616 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 617 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 618 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 619 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 620 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 621 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 622 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 623 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 624 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 625 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 626 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 627 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 628 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 629 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 630 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 631 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 632 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 633 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 634 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 635 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 636 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 637 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 638 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 639 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 640 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 641 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 642 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 643 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 644 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 645 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 646 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 647 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 648 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 649 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 650 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 651 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 652 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 653 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 654 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 655 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 656 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 657 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 658 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 659 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 660 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 661 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 662 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 663 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 664 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 665 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 666 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 667 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 668 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 669 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 670 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 671 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 672 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 673 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 674 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 675 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 676 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 677 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 678 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 679 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 680 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 681 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 682 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 683 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 684 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 685 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 686 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 687 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 688 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 689 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 690 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 691 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 692 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 693 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 694 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 695 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 696 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 697 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 698 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 699 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 700 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 701 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 702 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 703 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 704 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 705 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 706 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 707 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 708 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 709 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 710 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 711 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 712 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 713 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 714 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 715 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 716 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 717 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 718 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 719 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 720 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 721 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 722 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 723 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 724 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 725 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 726 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 727 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 728 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 729 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 730 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 731 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 732 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 733 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 734 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 735 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 736 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 737 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 738 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 739 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 740 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 741 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 742 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 743 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 744 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 745 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 746 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 747 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 748 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 749 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 750 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 751 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 752 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 753 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 754 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 755 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 756 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 757 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 758 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 759 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 760 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 761 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 762 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 763 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 764 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 765 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 766 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 767 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 768 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 769 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 770 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 771 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 772 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 773 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 774 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 775 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 776 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 777 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 778 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 779 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 780 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 781 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 782 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 783 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 784 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 785 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 786 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 787 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 788 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 789 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 790 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 791 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 792 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 793 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 794 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 795 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 796 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 797 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 798 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 799 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 800 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 801 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 802 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 803 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 804 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 805 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 806 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 807 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 808 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 809 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 810 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 811 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 812 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 813 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 814 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 815 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 816 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 817 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 818 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 819 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 820 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 821 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 822 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 823 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 824 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 825 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 826 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 827 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 828 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 829 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 830 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 831 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 832 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 833 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 834 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 835 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 836 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 837 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 838 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 839 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 840 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 841 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 842 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 843 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 844 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 845 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 846 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 847 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 848 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 849 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 850 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 851 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 852 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 853 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 854 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 855 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 856 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 857 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 858 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 859 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 860 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 861 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 862 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 863 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 864 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 865 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 866 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 867 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 868 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 869 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 870 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 871 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 872 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 873 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 874 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 875 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 876 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 877 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 878 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 879 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 880 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 881 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 882 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 883 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 884 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 885 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 886 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 887 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 888 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 889 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 890 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 891 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 892 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 893 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 894 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 895 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 896 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 897 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 898 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 899 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 900 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 901 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 902 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 903 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 904 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 905 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 906 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 907 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 908 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 909 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 910 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 911 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 912 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 913 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 914 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 915 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 916 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 917 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 918 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 919 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 920 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 921 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 922 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 923 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 924 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 925 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 926 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 927 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 928 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 929 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 930 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 931 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 932 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 933 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 934 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 935 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 936 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 937 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 938 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 939 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 940 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 941 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 942 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 943 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 944 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 945 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 946 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 947 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 948 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 949 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 950 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 951 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 952 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 953 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 954 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 955 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 956 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 957 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 958 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 959 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 960 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 961 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 962 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 963 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 964 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 965 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 966 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 967 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 968 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 969 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 970 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 971 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 972 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 973 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 974 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 975 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 976 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 977 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 978 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 979 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 980 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 981 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 982 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 983 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 984 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 985 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 986 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 987 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 988 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 989 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 990 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 991 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 992 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 993 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 994 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 995 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 996 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 997 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 998 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 999 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1000 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1001 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1002 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1003 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1004 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1005 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1006 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1007 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1008 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1009 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1010 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1011 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1012 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1013 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1014 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1015 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1016 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1017 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1018 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1019 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1020 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1021 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1022 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1023 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1024 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1025 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1026 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1027 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1028 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1029 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1030 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1031 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1032 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1033 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1034 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1035 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1036 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1037 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1038 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1039 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1040 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1041 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1042 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1043 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1044 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1045 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1046 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1047 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1048 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1049 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1050 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1051 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1052 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1053 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1054 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1055 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1056 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1057 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1058 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1059 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1060 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1061 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1062 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1063 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1064 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1065 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1066 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1067 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1068 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1069 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1070 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1071 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1072 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1073 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1074 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1075 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1076 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1077 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1078 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1079 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1080 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1081 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1082 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1083 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1084 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1085 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1086 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1087 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1088 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1089 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1090 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1091 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1092 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1093 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1094 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1095 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1096 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1097 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1098 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1099 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1100 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1101 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1102 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1103 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1104 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1105 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1106 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1107 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1108 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1109 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1110 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1111 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1112 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1113 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1114 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1115 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1116 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1117 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1118 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1119 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1120 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1121 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1122 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1123 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1124 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1125 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1126 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1127 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1128 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1129 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1130 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1131 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1132 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1133 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1134 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1135 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1136 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1137 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1138 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1139 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1140 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1141 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1142 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1143 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1144 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1145 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1146 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1147 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1148 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1149 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1150 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1151 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1152 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1153 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1154 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1155 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1156 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1157 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1158 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1159 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1160 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1161 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1162 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1163 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1164 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1165 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1166 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1167 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1168 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1169 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1170 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1171 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1172 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1173 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1174 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1175 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1176 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1177 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1178 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1179 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1180 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1181 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1182 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1183 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1184 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1185 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1186 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1187 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1188 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1189 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1190 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1191 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1192 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1193 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1194 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1195 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1196 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1197 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1198 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1199 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1200 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1201 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1202 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1203 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1204 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1205 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1206 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1207 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1208 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1209 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1210 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1211 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1212 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1213 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1214 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1215 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1216 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1217 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1218 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1219 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1220 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1221 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1222 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1223 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1224 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1225 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1226 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1227 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1228 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1229 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1230 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1231 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1232 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1233 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1234 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1235 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1236 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1237 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1238 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1239 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1240 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1241 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1242 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1243 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1244 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1245 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1246 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1247 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1248 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1249 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1250 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1251 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1252 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1253 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1254 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1255 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1256 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1257 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1258 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1259 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1260 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1261 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1262 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1263 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1264 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1265 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1266 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1267 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1268 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1269 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1270 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1271 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1272 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1273 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1274 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1275 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1276 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1277 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1278 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1279 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1280 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1281 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1282 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1283 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1284 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1285 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1286 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1287 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1288 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1289 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1290 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1291 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1292 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1293 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1294 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1295 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1296 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1297 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1298 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1299 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1300 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1301 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1302 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1303 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1304 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1305 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1306 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1307 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1308 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1309 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1310 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1311 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1312 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1313 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1314 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1315 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1316 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1317 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1318 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1319 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1320 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1321 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1322 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1323 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1324 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1325 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1326 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1327 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1328 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1329 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1330 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1331 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1332 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1333 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1334 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1335 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1336 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1337 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1338 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1339 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1340 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1341 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1342 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1343 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1344 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1345 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1346 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1347 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1348 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1349 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1350 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1351 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1352 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1353 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1354 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1355 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1356 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1357 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1358 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1359 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1360 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1361 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1362 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1363 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1364 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1365 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1366 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1367 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1368 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1369 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1370 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1371 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1372 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1373 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1374 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1375 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1376 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1377 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1378 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1379 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1380 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1381 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1382 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1383 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1384 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1385 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1386 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1387 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1388 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1389 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1390 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1391 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1392 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1393 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1394 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1395 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1396 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1397 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1398 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1399 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1400 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1401 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1402 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1403 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1404 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1405 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1406 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1407 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1408 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1409 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1410 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1411 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1412 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1413 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1414 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1415 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1416 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1417 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1418 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1419 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1420 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1421 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1422 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1423 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1424 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1425 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1426 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1427 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1428 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1429 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1430 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1431 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1432 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1433 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1434 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1435 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1436 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1437 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1438 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1439 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1440 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1441 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1442 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1443 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1444 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1445 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1446 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1447 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1448 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1449 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1450 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1451 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1452 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1453 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1454 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1455 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1456 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1457 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1458 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1459 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1460 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1461 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1462 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1463 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1464 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1465 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1466 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1467 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1468 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1469 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1470 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1471 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1472 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1473 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1474 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1475 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1476 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1477 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1478 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1479 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1480 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1481 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1482 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1483 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1484 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1485 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1486 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1487 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1488 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1489 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1490 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1491 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1492 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1493 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1494 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1495 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1496 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1497 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1498 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1499 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1500 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1501 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1502 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1503 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1504 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1505 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1506 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1507 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1508 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1509 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1510 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1511 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1512 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1513 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1514 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1515 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1516 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1517 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1518 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1519 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1520 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1521 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1522 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1523 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1524 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1525 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1526 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1527 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1528 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1529 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1530 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1531 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1532 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1533 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1534 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1535 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1536 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1537 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1538 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1539 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1540 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1541 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1542 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1543 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1544 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1545 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1546 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1547 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1548 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1549 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1550 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1551 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1552 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1553 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1554 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1555 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1556 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1557 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1558 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1559 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1560 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1561 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1562 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1563 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1564 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1565 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1566 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1567 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1568 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1569 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1570 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1571 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1572 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1573 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1574 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1575 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1576 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1577 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1578 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1579 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1580 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1581 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1582 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1583 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1584 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1585 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1586 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1587 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1588 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1589 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1590 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1591 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1592 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1593 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1594 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1595 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1596 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1597 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1598 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1599 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1600 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1601 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1602 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1603 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1604 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1605 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1606 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1607 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1608 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1609 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1610 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1611 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1612 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1613 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1614 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1615 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1616 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1617 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1618 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1619 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1620 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1621 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1622 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1623 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1624 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1625 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1626 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1627 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1628 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1629 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1630 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1631 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1632 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1633 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1634 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1635 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1636 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1637 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1638 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1639 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1640 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1641 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1642 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1643 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1644 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1645 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1646 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1647 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1648 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1649 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1650 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1651 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1652 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1653 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1654 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1655 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1656 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1657 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1658 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1659 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1660 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1661 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1662 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1663 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1664 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1665 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1666 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1667 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1668 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1669 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1670 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1671 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1672 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1673 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1674 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1675 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1676 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1677 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1678 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1679 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1680 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1681 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1682 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1683 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1684 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1685 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1686 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1687 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1688 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1689 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1690 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1691 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1692 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1693 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1694 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1695 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1696 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1697 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1698 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1699 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1700 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1701 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1702 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1703 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1704 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1705 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1706 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1707 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1708 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1709 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1710 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1711 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1712 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1713 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1714 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1715 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1716 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1717 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1718 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1719 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1720 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1721 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1722 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1723 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1724 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1725 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1726 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1727 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1728 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1729 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1730 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1731 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1732 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1733 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1734 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1735 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1736 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1737 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1738 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1739 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1740 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1741 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1742 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1743 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1744 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1745 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1746 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1747 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1748 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1749 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1750 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1751 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1752 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1753 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1754 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1755 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1756 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1757 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1758 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1759 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1760 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1761 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1762 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1763 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1764 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1765 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1766 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1767 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1768 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1769 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1770 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1771 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1772 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1773 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1774 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1775 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1776 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1777 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1778 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1779 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1780 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1781 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1782 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1783 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1784 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1785 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1786 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1787 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1788 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1789 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1790 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1791 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1792 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1793 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1794 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1795 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1796 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1797 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1798 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1799 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1800 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1801 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1802 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1803 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1804 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1805 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1806 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1807 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1808 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1809 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1810 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1811 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1812 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1813 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1814 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1815 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1816 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1817 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1818 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1819 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1820 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1821 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1822 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1823 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1824 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1825 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1826 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1827 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1828 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1829 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1830 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1831 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1832 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1833 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1834 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1835 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1836 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1837 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1838 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1839 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1840 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1841 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1842 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1843 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1844 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1845 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1846 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1847 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1848 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1849 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1850 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1851 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1852 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1853 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1854 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1855 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1856 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1857 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1858 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1859 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1860 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1861 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1862 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1863 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1864 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1865 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1866 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1867 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1868 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1869 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1870 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1871 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1872 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1873 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1874 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1875 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1876 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1877 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1878 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1879 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1880 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1881 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1882 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1883 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1884 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1885 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1886 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1887 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1888 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1889 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1890 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1891 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1892 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1893 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1894 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1895 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1896 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1897 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1898 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1899 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1900 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1901 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1902 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1903 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1904 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1905 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1906 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1907 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1908 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1909 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1910 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1911 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1912 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1913 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1914 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1915 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1916 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1917 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1918 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1919 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1920 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1921 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1922 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1923 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1924 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1925 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1926 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1927 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1928 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1929 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1930 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1931 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1932 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1933 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1934 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1935 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1936 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1937 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1938 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1939 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1940 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1941 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1942 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1943 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1944 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1945 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1946 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1947 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1948 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1949 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1950 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1951 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1952 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1953 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1954 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1955 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1956 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1957 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1958 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1959 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1960 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1961 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1962 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1963 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1964 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1965 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1966 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1967 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1968 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1969 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1970 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1971 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1972 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1973 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1974 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1975 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1976 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1977 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1978 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1979 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1980 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1981 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1982 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1983 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1984 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1985 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1986 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1987 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1988 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1989 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1990 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1991 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1992 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1993 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1994 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1995 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1996 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1997 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1998 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1999 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2000 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2001 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2002 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2003 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2004 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2005 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2006 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2007 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2008 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2009 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2010 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2011 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2012 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2013 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2014 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2015 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2016 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2017 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2018 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2019 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2020 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2021 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2022 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2023 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2024 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2025 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2026 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2027 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2028 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2029 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2030 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2031 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2032 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2033 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2034 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2035 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2036 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2037 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2038 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2039 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2040 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2041 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2042 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2043 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2044 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2045 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2046 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2047 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. + +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Removed 67 unused cells and 218 unused wires. + + +5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + + +5.9. Rerunning OPT passes. (Maybe there is more to do..) + +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. +Performed a total of 0 changes. + +5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. + +Removed a total of 6 cells. + +5.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 1-bit at position 0 on $procdff$1240 ($dff) from module lsc1_packet_frontend_arch_reset_idle. + +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Removed 0 unused cells and 21 unused wires. + + +5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + +5.16. Rerunning OPT passes. (Maybe there is more to do..) + +5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. +Performed a total of 0 changes. + +5.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Removed a total of 0 cells. + +5.20. Executing OPT_DFF pass (perform DFF optimizations). + +5.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. + +5.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + +5.23. Finished OPT passes. (There is nothing left to do.) + +6. Executing SAT pass (solving SAT problems in the circuit). + +Setting up time step 1: +Final constraint equation: { } = { } +Imported 4 cells to SAT database. +Import constraint from assume cell: \clk when 1'1. +Import set-constraint from init attribute: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN = 1'0 +Final init constraint equation: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN = 1'0 +Import proof for assert: 1'1 when $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN. + +Setting up time step 2: +Final constraint equation: { } = { } +Imported 4 cells to SAT database. +Import constraint from assume cell: \clk when 1'1. +Import proof for assert: 1'1 when $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN. + +Setting up time step 3: +Final constraint equation: { } = { } +Imported 4 cells to SAT database. +Import constraint from assume cell: \clk when 1'1. +Import proof for assert: 1'1 when $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN. + +Solving problem with 18 variables and 43 clauses.. +SAT proof finished - no model found: SUCCESS! + + /$$$$$$ /$$$$$$$$ /$$$$$$$ + /$$__ $$ | $$_____/ | $$__ $$ + | $$ \ $$ | $$ | $$ \ $$ + | $$ | $$ | $$$$$ | $$ | $$ + | $$ | $$ | $$__/ | $$ | $$ + | $$/$$ $$ | $$ | $$ | $$ + | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ + \____ $$$|__/|________/|__/|_______/|__/ + \__/ + +End of script. Logfile hash: ed77109f73, CPU: user 4.49s system 0.05s, MEM: 70.59 MB peak +Yosys 0.33 (git sha1 2584903a060) +Time spent: 58% 1x proc_mux (2 sec), 11% 2x check (0 sec), ... diff --git a/results/arch-state-20260728/rtl.log b/results/arch-state-20260728/rtl.log new file mode 100644 index 0000000..055d5bf --- /dev/null +++ b/results/arch-state-20260728/rtl.log @@ -0,0 +1,31 @@ +make: Entering directory '/workspaces/mission-cbe073d0/work/pr30/test/packet_frontend' +iverilog -g2012 -Wall -s tb_lsc1_packet_frontend -o tb_lsc1_packet_frontend.vvp ../../asic_core/rtl/lsc1_packet_rx.sv ../../asic_core/rtl/lsc1_packet_tx.sv ../../asic_core/rtl/gf2n_mul_bitstream.sv ../../asic_core/rtl/gf128_mul_bitstream.sv ../../asic_core/rtl/leanvm_b_stream_alu.sv ../../asic_core/rtl/lsc1_stream_adapter.sv ../../asic_core/rtl/lsc1_field_encoder.sv ../../asic_core/rtl/lsc1_packet_frontend.sv tb_lsc1_packet_frontend.sv +warning: Some design elements have no explicit time unit and/or + : time precision. This may cause confusing timing results. + : Affected design elements are: + : -- module gf128_mul_bitstream declared here: ../../asic_core/rtl/gf128_mul_bitstream.sv:9 + : -- module gf2n_mul_bitstream declared here: ../../asic_core/rtl/gf2n_mul_bitstream.sv:22 + : -- module leanvm_b_stream_alu declared here: ../../asic_core/rtl/leanvm_b_stream_alu.sv:28 + : -- module lsc1_field_encoder declared here: ../../asic_core/rtl/lsc1_field_encoder.sv:6 + : -- module lsc1_packet_frontend declared here: ../../asic_core/rtl/lsc1_packet_frontend.sv:6 + : -- module lsc1_packet_rx declared here: ../../asic_core/rtl/lsc1_packet_rx.sv:5 + : -- module lsc1_packet_tx declared here: ../../asic_core/rtl/lsc1_packet_tx.sv:4 + : -- module lsc1_stream_adapter declared here: ../../asic_core/rtl/lsc1_stream_adapter.sv:6 +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +vvp tb_lsc1_packet_frontend.vvp +PASS: LSC-1 Phase-3 packet frontend adversarial test +tb_lsc1_packet_frontend.sv:426: $finish called at 44410000 (1ps) +make: Leaving directory '/workspaces/mission-cbe073d0/work/pr30/test/packet_frontend' diff --git a/results/arch-state-20260728/versions-and-inputs.log b/results/arch-state-20260728/versions-and-inputs.log new file mode 100644 index 0000000..9e1643d --- /dev/null +++ b/results/arch-state-20260728/versions-and-inputs.log @@ -0,0 +1,13 @@ +e941561fc88306c3eaf8543d79f9000d2bc7d90e +9062de2c5752f2f1059342fa86c4a8e074345231 +Yosys 0.33 (git sha1 2584903a060) +Icarus Verilog version 12.0 (stable) () +d24a53bcde88011f57fbd3515e3cf94307e326510c7ccc9c8b6492492de2ebe0 asic_core/rtl/lsc1_packet_rx.sv +4faf3e75fb5af10ae24d553cca6e80f5c9c32ace3df506784c21a933a0947a92 asic_core/rtl/lsc1_packet_tx.sv +e86aa91de733a17e627a5552551723e5bfed3b318cbe84746e95e812d4f8b0d0 asic_core/rtl/lsc1_stream_adapter.sv +dd8527e058916fe188f6d5d73268fe6bccc30c86cf10411a1db20c3ff0bb151f asic_core/rtl/lsc1_field_encoder.sv +390a7d879e1f9c07dbff58a6a2a451ff686bb145ac6c6e512dfa524ceb620164 asic_core/rtl/lsc1_packet_frontend.sv +606911b0f58068892d0df892f188bd50db50a30ec49ed63ca8b2941f9400c772 formal/lsc1_packet_frontend_arch_state_map.json +0b3f72a7bdf25c3a2fe8831ea4824487685932d2e80183140dd8212e273aa314 formal/ARCH_STATE.md +faac561322f0831f66924be0afd8a5ae5cca1cb3e3d2b9dc9ca1b5ea576cdabb formal/lsc1_packet_frontend_arch_reset_idle.sv +f85348ac2c65ad828d1365d62254664817efd1bbcb7aee2bb2f20791e4493e20 formal/lsc1_packet_frontend_arch_reset_idle.ys diff --git a/tools/check_arch_state_interface.py b/tools/check_arch_state_interface.py new file mode 100644 index 0000000..ce6368f --- /dev/null +++ b/tools/check_arch_state_interface.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +"""Mechanical coverage and mutation guard for the architectural state map.""" +import json, pathlib, re, sys + +root = pathlib.Path(__file__).resolve().parents[1] +rtl = (root / "asic_core/rtl/lsc1_packet_frontend.sv").read_text() +mapping = json.loads((root / "formal/lsc1_packet_frontend_arch_state_map.json").read_text()) +ports = set(re.findall(r"output wire\s+(?:\[[^]]+\]\s*)?(arch_[A-Za-z0-9_]+)", rtl)) +fields = mapping["fields"] +missing = ports - fields.keys() +extra = fields.keys() - ports +if missing or extra: + raise SystemExit(f"arch map coverage failure: missing={sorted(missing)} extra={sorted(extra)}") +for field, source in fields.items(): + needle = f"assign {field} = {source};" + if needle not in rtl: + raise SystemExit(f"R mapping is absent or perturbed: {needle}") +if set(mapping["observable_outputs"]) != {"rx_ready", "tx_data", "tx_valid", "busy", "fault", "done_pulse"}: + raise SystemExit("observable output channel coverage changed") +# Mutation test: an altered mapped source must be rejected by the same check. +mutated = rtl.replace("assign arch_active_profile = active_profile;", + "assign arch_active_profile = last_status;") +if "assign arch_active_profile = active_profile;" in mutated: + raise SystemExit("mutation setup failed") +if "assign arch_active_profile = active_profile;" not in rtl: + raise SystemExit("mutation guard did not distinguish source mapping") +print(f"arch-state map: {len(fields)} fields; all outputs and 6 observable channels covered") diff --git a/tools/run_arch_state_milestones.sh b/tools/run_arch_state_milestones.sh new file mode 100755 index 0000000..e5a4519 --- /dev/null +++ b/tools/run_arch_state_milestones.sh @@ -0,0 +1,22 @@ +#!/bin/sh +# Reproducible, bounded architectural-state milestones. This is intentionally +# not a timeout extension for release equivalence. +set -eu +out=${1:-results/arch-state-20260728} +mkdir -p "$out" +{ + git rev-parse HEAD + git rev-parse HEAD^{tree} + yosys -V + iverilog -V 2>&1 | head -1 + sha256sum asic_core/rtl/lsc1_packet_rx.sv asic_core/rtl/lsc1_packet_tx.sv \ + asic_core/rtl/lsc1_stream_adapter.sv asic_core/rtl/lsc1_field_encoder.sv \ + asic_core/rtl/lsc1_packet_frontend.sv formal/lsc1_packet_frontend_arch_state_map.json formal/ARCH_STATE.md \ + formal/lsc1_packet_frontend_arch_reset_idle.sv formal/lsc1_packet_frontend_arch_reset_idle.ys +} > "$out/versions-and-inputs.log" +python3 tools/check_arch_state_interface.py > "$out/interface-coverage.log" 2>&1 +yosys -s formal/lsc1_packet_frontend_arch_reset_idle.ys 2>&1 | sed 's/[[:space:]]*$//' > "$out/reset-idle.log" +make -C test/packet_frontend sim > "$out/rtl.log" 2>&1 +python3 -m unittest sim.test_packet_frontend_rtl_differential -v > "$out/differential.log" 2>&1 +make -C test/packet_frontend mutation > "$out/mutation.log" 2>&1 +sha256sum "$out"/*.log > "$out/SHA256SUMS" From c4b435471658ac8575d08b5cbdce810f6ff36da2 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Tue, 28 Jul 2026 21:38:11 +0200 Subject: [PATCH 6/9] Close recursive architectural state omissions --- SHA256SUMS | 39 +- asic_core/rtl/gf128_mul_bitstream.sv | 8 +- asic_core/rtl/gf2n_mul_bitstream.sv | 6 +- asic_core/rtl/leanvm_b_stream_alu.sv | 14 +- asic_core/rtl/lsc1_field_encoder.sv | 42 +- asic_core/rtl/lsc1_packet_frontend.sv | 136 +- asic_core/rtl/lsc1_packet_tx.sv | 14 +- asic_core/rtl/lsc1_stream_adapter.sv | 21 +- formal/ARCH_STATE.md | 12 +- .../lsc1_packet_frontend_arch_state_map.json | 538 ++- .../arch-state-omissions-20260728/README.md | 16 + .../arch-state-omissions-20260728/SHA256SUMS | 7 + .../differential.log | 9 + .../forbidden-token-scan.log | 2 + .../formal-reset.log | 3088 +++++++++++++++++ .../interface-coverage.log | 1 + .../mutation.log | 3 + .../root-checksums.log | 431 +++ results/arch-state-omissions-20260728/rtl.log | 31 + .../versions.log | 5 + tools/check_arch_state_interface.py | 53 +- 21 files changed, 4402 insertions(+), 74 deletions(-) create mode 100644 results/arch-state-omissions-20260728/README.md create mode 100644 results/arch-state-omissions-20260728/SHA256SUMS create mode 100644 results/arch-state-omissions-20260728/differential.log create mode 100644 results/arch-state-omissions-20260728/forbidden-token-scan.log create mode 100644 results/arch-state-omissions-20260728/formal-reset.log create mode 100644 results/arch-state-omissions-20260728/interface-coverage.log create mode 100644 results/arch-state-omissions-20260728/mutation.log create mode 100644 results/arch-state-omissions-20260728/root-checksums.log create mode 100644 results/arch-state-omissions-20260728/rtl.log create mode 100644 results/arch-state-omissions-20260728/versions.log diff --git a/SHA256SUMS b/SHA256SUMS index 79862fa..531718b 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -8,17 +8,17 @@ de4c0f6adf6ff1356bf9d7599ab52aef93a00b50c5a77c727ec0ce036ff2d1a2 ./RESULTS.md baa38ad5792511470f4cc9d2344d46f0c7af8a365d5b5e178dca88634b288bff ./VALIDATION.txt 56f3315873ddf849b851b0fb106e9eeec7160c33d15914c6157d7fe13065b6b5 ./VERSION 01679965b954645f167c4bb756ba5639ae532c14c9217ea90931f8a3e8af2b1a ./asic_core/README.md -d8e83531981677f629877cbeff643e07e169f8f6e8cf3ecd7c1b0c417a79b614 ./asic_core/rtl/gf128_mul_bitstream.sv -4aa363edd4a6b2797191599d838f3d5f81cc97aa5fc8d88f2f0050420ccf6396 ./asic_core/rtl/gf2n_mul_bitstream.sv +4ee53019c7e7323dbe2bc3faf58a5e81607ea377ddf6ef01f4999be3fab90ca0 ./asic_core/rtl/gf128_mul_bitstream.sv +84ce4945c93dd25dd36888459c6b50e588cacb2cf4b0f3364fc1f7f685e899ad ./asic_core/rtl/gf2n_mul_bitstream.sv 192eddc1727d8976ea48db9a532f44893d06bdec7651c65a1b1b99502b5e70c5 ./asic_core/rtl/lean_silicon_lsc1.sv 774b239a6221619559c57f0e00aad4000b507fd7c941dc9da204c1e357d6ad90 ./asic_core/rtl/lean_silicon_lsc1_mincore.sv -bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b ./asic_core/rtl/leanvm_b_stream_alu.sv -dd8527e058916fe188f6d5d73268fe6bccc30c86cf10411a1db20c3ff0bb151f ./asic_core/rtl/lsc1_field_encoder.sv +03857b860d9ac71c03057d4c3a12b1d70acd1a15226d29c4663e87ba34f25984 ./asic_core/rtl/leanvm_b_stream_alu.sv +1f2ce7746851e1d7bdd1e1ddfa5c0ba80ca1bfec3054f6b54d238673e368d19d ./asic_core/rtl/lsc1_field_encoder.sv 320e989e5480b6641f99f18822edeee5634f3d277f2faa408aaee2d21503d625 ./asic_core/rtl/lsc1_gf128_mul.sv -390a7d879e1f9c07dbff58a6a2a451ff686bb145ac6c6e512dfa524ceb620164 ./asic_core/rtl/lsc1_packet_frontend.sv +c16b2e253d6f0bf6394bbcf516693473f65b9d7ecb431f2f653671acdf9d656b ./asic_core/rtl/lsc1_packet_frontend.sv d24a53bcde88011f57fbd3515e3cf94307e326510c7ccc9c8b6492492de2ebe0 ./asic_core/rtl/lsc1_packet_rx.sv -4faf3e75fb5af10ae24d553cca6e80f5c9c32ace3df506784c21a933a0947a92 ./asic_core/rtl/lsc1_packet_tx.sv -e86aa91de733a17e627a5552551723e5bfed3b318cbe84746e95e812d4f8b0d0 ./asic_core/rtl/lsc1_stream_adapter.sv +1165bb65d343b20526c8e75242d8af0f21986c5a914266ddfdd8cc41538fcb3c ./asic_core/rtl/lsc1_packet_tx.sv +31944a798695cbf2ae83e6a90afe9212741a93e3f9b01ce97b549abb5d0c4995 ./asic_core/rtl/lsc1_stream_adapter.sv abcaeb377fdec71acd13ae9610b91e250c97a6709b5d9a6d208835e677f00ece ./conformance/README.md 76ba2ea25dd2f20ea3e50c6d25c774d1fbf45b2960b65d233680c284c0c111d7 ./conformance/corpus-v1.json cd41a7e0fda82b96aba2f141829e3168db5a0a7b41dfee77b4718a58f7e3daf2 ./conformance/rust/frozen_adapter.rs @@ -53,7 +53,7 @@ c8dbcf0008931bfd0d6a27c00425480de54d322dd27367ae83f54f93e3382b8c ./docs/semanti 3e896ee33e3804876f6e169c872746146c1b3d773811683616986a4148b9f785 ./docs/semantics/reference/oracle.py c49a013eb503060394007d07395e625024d7c1ff0e9b177bc71e691e1a4efec8 ./docs/semantics/reference/vectors.json 961d9f2f85fe6a6e2a5f586412e03759cb94a80683959e7f0271f37f200a4f1d ./docs/upstream-clarifications/README.md -0b3f72a7bdf25c3a2fe8831ea4824487685932d2e80183140dd8212e273aa314 ./formal/ARCH_STATE.md +88754daba18a83e6c8106fa61fe8aadcc98a8c530ddb0634209c48f44424c2e6 ./formal/ARCH_STATE.md e563e1a3b9189f28388b5335b0be480856200a4e196de6f61e90b8e7ece0b5e1 ./formal/README.md d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836 ./formal/gf128_serialize.sby 9a069838244bd75c66ab3930eb944c3677ae83242f9b2cbd9866a0d6d1db3198 ./formal/gf128_serialize_formal.sv @@ -64,7 +64,7 @@ d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836 ./formal/gf128 25a0d4fe96e4bcd910ebac0ba76be01f8924aedfa1f7e83588610f1a758baf4f ./formal/gf8_mul_formal.sv faac561322f0831f66924be0afd8a5ae5cca1cb3e3d2b9dc9ca1b5ea576cdabb ./formal/lsc1_packet_frontend_arch_reset_idle.sv f85348ac2c65ad828d1365d62254664817efd1bbcb7aee2bb2f20791e4493e20 ./formal/lsc1_packet_frontend_arch_reset_idle.ys -606911b0f58068892d0df892f188bd50db50a30ec49ed63ca8b2941f9400c772 ./formal/lsc1_packet_frontend_arch_state_map.json +d4dd8f33e2a5aade976d06cae7be3bd6d6cf41918499c5bdd20e36132fb95bfe ./formal/lsc1_packet_frontend_arch_state_map.json bca568aee38c4638fdaadab4e8878807bc56329bd170b4cb420c07e4357dd6dc ./formal/lsc1_packet_frontend_release_equiv.ys 1e6b80dd959472d00411116899097fb37c930651efe6290fda93a8f4ae5ae97e ./formal/stream_alu_mul_pulse.sby b61a1ea32d6b114093dd2679fd4fb3315dbfbb9829b8e4f739c0177f66ff1bc1 ./formal/stream_alu_mul_pulse_formal.sv @@ -116,7 +116,6 @@ c22e2dd6edcd014dd803fd1ea630ae063aeee86e192afd6c34b4ac81efa73daa ./host/lean_co 451f3d686ce47b16d81de2f85d36a52231c99a1b47c261475c0cb4134a09d777 ./host/protocol.py 25034b46f23a72f3f5add04a398a8a8bb0858a293be5d433601502733ff84f32 ./host/runtime.py effcad52a728f7c1cc4b463ea8d7bc6cc6350ddb6daf836f4adc601f714485ab ./info.yaml -68a4209dcbdcc663454d02012642fa7b5a3476a13e363982fc9236e89c27a6b7 ./lean/LeanVMBMinCore.lean c09c6cf1a82598ec2c0e5f6ecf58852c8c27554f7036f36baadf027067a55f4e ./lean/LeanVMBMinCore/Address.lean 70ce5c26e2964f9c095505c2a621e5bdc08a9379656048ef5cc6d350d9a0bf31 ./lean/LeanVMBMinCore/ByteSerialization.lean f76af91e138dc3cd8981dd3bf6e62e03d1b37d847f0b3f68cd59015782ad017c ./lean/LeanVMBMinCore/CheckedIndex.lean @@ -130,6 +129,7 @@ ba05339f74771d0357a852dbb3bee59629480c76cec9d70fc14752c5818123ea ./lean/LeanVMB 5d6453af2400e4155bfb56444e053b3c8f893f4459a15cf1f3cf2d72815b510a ./lean/LeanVMBMinCore/Packet.lean b55a55b9a2bbeb82d62fa99c99381674e98750e872d933775dc7add2fd8e0aef ./lean/LeanVMBMinCore/Stream.lean a81918a95c1152b8aa57d132dd9fdc5b0d63843ca22dfdbd5c7ffb2c0e6e858b ./lean/LeanVMBMinCore/Transaction.lean +68a4209dcbdcc663454d02012642fa7b5a3476a13e363982fc9236e89c27a6b7 ./lean/LeanVMBMinCore.lean 1f67ca9fd0f51cd27b651b79aceddc1c972ef3e77cb358866df77740fc2a2064 ./lean/README.md 364a9fa30ceadcb16de01c341ee7207bc453be4be69add43c924ad27a6ffca76 ./lean/lake-manifest.json d1f2dfa6bf564b9cf248838630eb92efd55f03e9ab8bf5e7dfec3d318b9f0f29 ./lean/lakefile.lean @@ -138,15 +138,22 @@ d59a11f361717058c708574a6f41d9be99da29cfcc3b0c033045ce6f0e57a5d5 ./planning/OWN a19467b08293daf14a67ccd8f0efbcddfeb3854c38525acd7fcfd98f01552587 ./planning/milestones.yaml fbce601088163a30bf024083852ec3d72a1dd2ab12a22a9ea1fc8809cadafb93 ./requirements.txt 091c91a57156e3fe3207f2a1c46f1b189209d0a7b1089f226c80da9aac40509a ./results/arch-state-20260728/README.md -62d0ec37d880c46a9f7ef6e36bcac75b9cfd3bf7ffd82cbcfa89c0cd2aa688ad ./results/arch-state-20260728/SHA256SUMS b91294fb84265d3d8a568773e69bf4be6989b8b2495d06ea1b2b166c021228c2 ./results/arch-state-20260728/differential.log 4e79a6223338d65e7609b234e33c62cbad037f3a27f1f6fe795f6d61e1ecc281 ./results/arch-state-20260728/interface-coverage.log c3a2a9f65cc2cc17d980a939d510da253dba23547a875440b950137da81581c5 ./results/arch-state-20260728/mutation.log ff5d1517dabeb83213ca643ef75a392a17003417d41d11b2dc385450e0121825 ./results/arch-state-20260728/reset-idle.log 1232f3d6bb4138ddf396895ed067274601df653827828396b79a88b2430a438d ./results/arch-state-20260728/rtl.log 00486fb8958a8818e17326967dee9e5fcfaf602093c282a957229b491eefcf99 ./results/arch-state-20260728/versions-and-inputs.log +f9f38bf0f4ea6c18e6878c1e06dc7b6565498b28ef6cc6da322256492edc9fb0 ./results/arch-state-omissions-20260728/README.md +c377a2118b46bdb2786c85aac8cfe2226e9a9eec3e009451f357c52f7e3fc414 ./results/arch-state-omissions-20260728/differential.log +c1a78566db364c4d3c9ba81031c90e0641395b86f95de187eb0616466fe6b23e ./results/arch-state-omissions-20260728/forbidden-token-scan.log +4c0959a206d1b2d8d17b2c62eb7b2a7f92b83c38167f1c4009a9d05cb0f287ed ./results/arch-state-omissions-20260728/formal-reset.log +4c8f5cc3ce7dc012f38e9889075fef35fa19946a56ee529e1e10bc8d2e77e7b8 ./results/arch-state-omissions-20260728/interface-coverage.log +c3a2a9f65cc2cc17d980a939d510da253dba23547a875440b950137da81581c5 ./results/arch-state-omissions-20260728/mutation.log +42b41b23e7741cf8a9b90f4e6af5426e63c245e61a9a0b2b53a858cd776d8d5d ./results/arch-state-omissions-20260728/root-checksums.log +1232f3d6bb4138ddf396895ed067274601df653827828396b79a88b2430a438d ./results/arch-state-omissions-20260728/rtl.log +f550fcd0882dc02526e9301821800a8bbbe79d5f327bd4c010fd8d882630405e ./results/arch-state-omissions-20260728/versions.log 315f8bfecb585814f0d1ec406d16203365e360601166a2e4f897b488cd6ab057 ./results/b2-capability-contract-20260728/README.md -a5157bf6549b0f1730477e82b1ec94a4dacc83f0ae93fc1e0d4e698ec97e1d4c ./results/b2-capability-contract-20260728/SHA256SUMS 967cd83720a145d1daba23a926a1b22eabc4e83d7b7c337cf3512f3df944c535 ./results/b2-capability-contract-20260728/blake3_official.command 42b629a692f30c9bfb0fcff81a5eb4631efb576c1355485035dd6d8c50131631 ./results/b2-capability-contract-20260728/blake3_official.log c4c41bd36c74ae8036f7f04e842e6e165b94947210de3fbb2ff0fc6a7d212aa6 ./results/b2-capability-contract-20260728/blake3_official.status @@ -214,7 +221,6 @@ dc9ae71fe0b8bdbacc6293d9f754e5eb7e1dae4a9ad37c7903a0e510ff388e3b ./results/fpga e283221feb3d7e57f4c18fb3b585a395784f23e1fbb5e0a6393ce3fed7f4740e ./results/fpga-harness-inventory-20260725/tested-source-sha.txt 6f105c46c0d7a97a6425c136d1bf6f933aa91fe9eee296f86fba4d66a1662560 ./results/fpga-harness-inventory-20260725/toolchain.txt be0da30a37ab97160fe55efe0ac74c986a452772454b725862cdd099aeabe448 ./results/frozen-oracle-evidence-20260725/README.md -2d55eb5eeca0baa3e8f941de57632f6810a71feefbfc31be9999b5e4b21fb147 ./results/frozen-oracle-evidence-20260725/SHA256SUMS 29eda5c5be90a767c8927e1e6ef1e94f2f0c8ca696a23a0a57521b9fe10889ee ./results/frozen-oracle-evidence-20260725/boundary-rejection.log cc3cc28b38e104777a88cf95ba04ae47a26b522c76024085bdfc42a7f8ce9894 ./results/frozen-oracle-evidence-20260725/m2.json dc738aa207758c4cdb704a288dc53b0d0016165a44cfd1158c4f9620f88dfffd ./results/frozen-oracle-evidence-20260725/m2.log @@ -349,7 +355,6 @@ c05bcfb6cfbeaa2f72eb031a986a37e6094ec430022d6cce911cf4fcedfb101a ./results/seri 42f3d4668a80ab3bf2a16915803d5a212bb299ca8800fa24dfc0f8baaa88c509 ./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.log ceceba3b9bc693c4b5a87f799e91ee36f93c483dd32d6e32514eb2a3e02779ad ./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.status 228b1eb2253fe285abf3f2d6cf6a7748661a11367433e17a8cef8832ea6068e4 ./results/serial-mul-byte-order-20260725/toolchain.txt -0d617e2e80e8749ea5f1b0a48f2da7ddac62dcb5f8def09126d60971f26dbf36 ./results/ulx3s-smoke-uart-20260725/SHA256SUMS ecd004f3008420bdf304a9d8f1084202847f65836bafed2aef69b858db180628 ./results/ulx3s-smoke-uart-20260725/SHA256SUMS_bridge.txt 7b45b067f30eb0a477f2eea894f79b0694ee3dcfb78752c935a2aa13c2a53d51 ./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST.txt dbda64dd3a2c4985c6d2a98123daac73461e2cb4d1ffb18da445920d5f2fe19b ./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST_uart.txt @@ -366,6 +371,9 @@ eacee77bdca486f173cacdb56709e442942eb85f9111eabcb96026976f8bae51 ./results/ulx3 e3329b92c1baf92fa161eb36a067e2ccbe73342fe8e419c315fbadfef9729b7d ./results/ulx3s-smoke-uart-20260725/yosys.log 7d50c170f623ccc6911a48dd18455bc1011a2be335a9997c6d85355d0c72e63d ./results/ulx3s-smoke-uart-20260725/yosys_uart.log 2ce193a38f1a8c96ec1cbfe2c8b7555d025944cb450859c3e09dd2cbab66a03c ./sim/__init__.py +0395ed8bde85b5758af6c3d70773dd23ebee400055c9d0f81ac53d0b50ce285d ./sim/__pycache__/__init__.cpython-312.pyc +b94e2104bd04ac0f5cdd5a8f3d35f4d8756a4482965fffe3411c2d1915e651b9 ./sim/__pycache__/lsc1_transaction.cpython-312.pyc +2cb22c1850638b2c9fdc2d6713856b3ec154731176708715946885bb13e73f90 ./sim/__pycache__/test_packet_frontend_rtl_differential.cpython-312.pyc 56f95ab49ce35604c5b30cd95d142a4d630b2d503af5398b1f975ef84492b48c ./sim/cycle_model.py 2a1871001ed3c296926b0f343bd8fd32176da7959628786bea51d7772653b633 ./sim/lsc1_transaction.py 12dd1aca968efeafb9ffa7015f849607c96fb6e14ad2aa8f65938dd254ef6f49 ./sim/model.py @@ -393,6 +401,7 @@ a3574d9d454d7b7580d2dcdc2801013a7648c48358a3f4a90a5c876ae9791331 ./src/user_con 69cd41bda612b601228752f516472df0f3be356de2f327ce4bbaaccb588edcf7 ./test/Makefile 2b5c167fcbbbc265e3aef203c8ffc59b0c6c4db8e7d180dc45133606414bb000 ./test/packet_frontend/Makefile d54a6f18a9c81353492801e51de435e47885fbbd3faae8c955cde0774b66eb2f ./test/packet_frontend/tb_lsc1_packet_frontend.sv +b234d21acd2f17d2296ec5596af324f9d1ba494bcf9e59838f5c77bff429ebb2 ./test/packet_frontend/tb_lsc1_packet_frontend.vvp f1bf4caf7438081d289ea48ebfcbed8f278866a664636dc810ea5e2c1b4410c3 ./test/packet_frontend/tb_lsc1_packet_vector.sv d0c03fb87fe5f08fbec435d485e4dd14c96d164e90b0e8b0ed8980cf27e8c077 ./test/tb_m2_scalar_controller.sv 2ea0bf23432e7c9471b09d7dac47b1b548f37d746a8cdf1fc9bd8128cd2a8018 ./test/tb_packet_uart_bridge.sv @@ -402,7 +411,7 @@ e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a ./tools/atomic 7894f75175f62edfd1ed33639a23d736ad6e57ddd9182e040f556502bff21a52 ./tools/blake3_reference/Cargo.lock e28e67bc3fd6dee898130648c74691ca7b8e61d1fccfa75c52d87d52fc8d9c3f ./tools/blake3_reference/Cargo.toml 3414b26004416f8871274b30fa975b40f611b5b6b148a2e1b3d97c109cd37f52 ./tools/blake3_reference/src/main.rs -750670739ee7f64954917601f85b95021496a429f4174b09d6777dc4918ff9a4 ./tools/check_arch_state_interface.py +6b0d7c7843f414a9180aa3a1a9fbd05bde01c50cee2922b2cd5a3ff8c7dbb351 ./tools/check_arch_state_interface.py 3057cbe3ffbd0b8826a9c77cca1be2e3344b831373adbe583679706858b50910 ./tools/conformance_differential.py 008f814b114282389ae48ff82e4412fe455cbe8c377cf71e534862d490d3cb79 ./tools/design_space.csv 75dc51b45b2631ddc57c4629982949696f1b711323f6e857ca19dc42961f7359 ./tools/design_space.md diff --git a/asic_core/rtl/gf128_mul_bitstream.sv b/asic_core/rtl/gf128_mul_bitstream.sv index b3b768f..07fb4dd 100644 --- a/asic_core/rtl/gf128_mul_bitstream.sv +++ b/asic_core/rtl/gf128_mul_bitstream.sv @@ -20,7 +20,9 @@ module gf128_mul_bitstream ( input wire bit_last, input wire result_shift, - output wire [7:0] result_byte + output wire [7:0] result_byte, + output wire [127:0] arch_a_shift, + output wire [127:0] arch_accumulator ); gf2n_mul_bitstream #( @@ -38,7 +40,9 @@ module gf128_mul_bitstream ( .bit_value (bit_value), .bit_last (bit_last), .result_shift (result_shift), - .result_byte (result_byte) + .result_byte (result_byte), + .arch_a_shift (arch_a_shift), + .arch_accumulator (arch_accumulator) ); endmodule diff --git a/asic_core/rtl/gf2n_mul_bitstream.sv b/asic_core/rtl/gf2n_mul_bitstream.sv index 3ce75a7..2aaed59 100644 --- a/asic_core/rtl/gf2n_mul_bitstream.sv +++ b/asic_core/rtl/gf2n_mul_bitstream.sv @@ -37,7 +37,9 @@ module gf2n_mul_bitstream #( input wire bit_last, input wire result_shift, - output wire [BYTE_BITS-1:0] result_byte + output wire [BYTE_BITS-1:0] result_byte, + output wire [WIDTH-1:0] arch_a_shift, + output wire [WIDTH-1:0] arch_accumulator ); reg [WIDTH-1:0] a_shift; @@ -68,6 +70,8 @@ module gf2n_mul_bitstream #( endfunction assign result_byte = accumulator[BYTE_BITS-1:0]; + assign arch_a_shift = a_shift; + assign arch_accumulator = accumulator; always @(posedge clk) begin if (!rst_n) begin diff --git a/asic_core/rtl/leanvm_b_stream_alu.sv b/asic_core/rtl/leanvm_b_stream_alu.sv index 0c88e47..c5c62c0 100644 --- a/asic_core/rtl/leanvm_b_stream_alu.sv +++ b/asic_core/rtl/leanvm_b_stream_alu.sv @@ -40,7 +40,12 @@ module leanvm_b_stream_alu ( output wire busy, output wire done_pulse, - output reg fault + output reg fault, + output wire [3:0] arch_state, + output wire [3:0] arch_byte_index, + output wire [7:0] arch_scratch_byte, + output wire [127:0] arch_mul_a_shift, + output wire [127:0] arch_mul_accumulator ); localparam [7:0] CMD_XOR128 = 8'h01; @@ -97,10 +102,15 @@ module leanvm_b_stream_alu ( .bit_value (mul_bit_value), .bit_last (mul_bit_last), .result_shift (mul_result_shift), - .result_byte (mul_result_byte) + .result_byte (mul_result_byte), + .arch_a_shift (arch_mul_a_shift), + .arch_accumulator (arch_mul_accumulator) ); assign busy = (state != S_IDLE); + assign arch_state = state; + assign arch_byte_index = byte_index; + assign arch_scratch_byte = scratch_byte; function automatic [7:0] status_byte; input [3:0] index; diff --git a/asic_core/rtl/lsc1_field_encoder.sv b/asic_core/rtl/lsc1_field_encoder.sv index d271f8b..683b9e6 100644 --- a/asic_core/rtl/lsc1_field_encoder.sv +++ b/asic_core/rtl/lsc1_field_encoder.sv @@ -14,7 +14,29 @@ module lsc1_field_encoder ( output reg fault, output reg [127:0] result, output wire [4:0] arch_bit_index, - output wire [15:0] arch_saved_index + output wire [15:0] arch_saved_index, + output wire arch_multiply_start, + output wire [127:0] arch_accumulator, + output wire [127:0] arch_operand_a, + output wire [127:0] arch_operand_b, + output wire arch_done_pulse, + output wire arch_fault, + output wire [127:0] arch_result, + output wire [2:0] arch_multiplier_state, + output wire [7:0] arch_multiplier_operation, + output wire [5:0] arch_multiplier_payload_index, + output wire [4:0] arch_multiplier_result_index, + output wire [127:0] arch_multiplier_saved_a, + output wire [127:0] arch_multiplier_saved_b, + output wire arch_multiplier_done_pulse, + output wire arch_multiplier_fault, + output wire [127:0] arch_multiplier_result, + output wire [3:0] arch_multiplier_core_state, + output wire [3:0] arch_multiplier_core_byte_index, + output wire [7:0] arch_multiplier_core_scratch_byte, + output wire arch_multiplier_core_fault, + output wire [127:0] arch_multiplier_core_mul_a_shift, + output wire [127:0] arch_multiplier_core_mul_accumulator ); reg multiply_start; reg [4:0] bit_index; @@ -26,6 +48,13 @@ module lsc1_field_encoder ( reg [127:0] next_accumulator; assign arch_bit_index = bit_index; assign arch_saved_index = saved_index; + assign arch_multiply_start = multiply_start; + assign arch_accumulator = accumulator; + assign arch_operand_a = operand_a; + assign arch_operand_b = operand_b; + assign arch_done_pulse = done_pulse; + assign arch_fault = fault; + assign arch_result = result; function automatic [127:0] field_xtime(input [127:0] value); field_xtime = {value[126:0], 1'b0} ^ @@ -36,7 +65,16 @@ module lsc1_field_encoder ( .clk(clk), .rst_n(rst_n), .abort(abort), .start(multiply_start), .operation(8'h02), .operand_a(operand_a), .operand_b(operand_b), .busy(multiply_busy), .done_pulse(multiply_done), - .fault(multiply_fault), .result(multiply_result) + .fault(multiply_fault), .result(multiply_result), + .arch_state(arch_multiplier_state), .arch_operation(arch_multiplier_operation), + .arch_payload_index(arch_multiplier_payload_index), .arch_result_index(arch_multiplier_result_index), + .arch_saved_a(arch_multiplier_saved_a), .arch_saved_b(arch_multiplier_saved_b), + .arch_done_pulse(arch_multiplier_done_pulse), .arch_fault(arch_multiplier_fault), + .arch_result(arch_multiplier_result), + .arch_core_state(arch_multiplier_core_state), .arch_core_byte_index(arch_multiplier_core_byte_index), + .arch_core_scratch_byte(arch_multiplier_core_scratch_byte), .arch_core_fault(arch_multiplier_core_fault), + .arch_core_mul_a_shift(arch_multiplier_core_mul_a_shift), + .arch_core_mul_accumulator(arch_multiplier_core_mul_accumulator) ); always @(posedge clk) begin diff --git a/asic_core/rtl/lsc1_packet_frontend.sv b/asic_core/rtl/lsc1_packet_frontend.sv index 115be3b..22c61a5 100644 --- a/asic_core/rtl/lsc1_packet_frontend.sv +++ b/asic_core/rtl/lsc1_packet_frontend.sv @@ -56,16 +56,63 @@ module lsc1_packet_frontend ( output wire [7:0] arch_tx_status, output wire [543:0] arch_tx_payload, output wire [31:0] arch_tx_payload_crc, + output wire arch_tx_active, + output wire [31:0] arch_tx_saved_crc, + output wire [31:0] arch_tx_envelope_crc_work, + output wire [31:0] arch_tx_payload_crc_work, + output wire arch_tx_done_pulse, + output wire arch_tx_start, + output wire [7:0] arch_tx_start_status, + output wire [15:0] arch_tx_start_length, + output wire [543:0] arch_tx_start_payload, + output wire arch_capture_result_crc, output wire arch_alu_busy, output wire [2:0] arch_alu_phase, output wire [7:0] arch_alu_operation, output wire [5:0] arch_alu_payload_index, output wire [4:0] arch_alu_result_index, output wire [127:0] arch_alu_result, + output wire [127:0] arch_alu_saved_a, + output wire [127:0] arch_alu_saved_b, + output wire arch_alu_done_pulse, + output wire arch_alu_fault, + output wire [3:0] arch_alu_core_phase, + output wire [3:0] arch_alu_core_byte_index, + output wire [7:0] arch_alu_core_scratch_byte, + output wire arch_alu_core_fault, + output wire [127:0] arch_alu_core_mul_a_shift, + output wire [127:0] arch_alu_core_mul_accumulator, + output wire arch_alu_start, + output wire [7:0] arch_alu_start_operation, + output wire [127:0] arch_alu_start_operand_a, + output wire [127:0] arch_alu_start_operand_b, output wire arch_encoder_busy, output wire [4:0] arch_encoder_bit_index, output wire [15:0] arch_encoder_index, output wire [127:0] arch_encoder_result, + output wire arch_encoder_done_pulse, + output wire arch_encoder_fault, + output wire arch_encoder_multiply_start, + output wire [127:0] arch_encoder_accumulator, + output wire [127:0] arch_encoder_operand_a, + output wire [127:0] arch_encoder_operand_b, + output wire [2:0] arch_encoder_multiplier_phase, + output wire [7:0] arch_encoder_multiplier_operation, + output wire [5:0] arch_encoder_multiplier_payload_index, + output wire [4:0] arch_encoder_multiplier_result_index, + output wire [127:0] arch_encoder_multiplier_saved_a, + output wire [127:0] arch_encoder_multiplier_saved_b, + output wire arch_encoder_multiplier_done_pulse, + output wire arch_encoder_multiplier_fault, + output wire [127:0] arch_encoder_multiplier_result, + output wire [3:0] arch_encoder_multiplier_core_phase, + output wire [3:0] arch_encoder_multiplier_core_byte_index, + output wire [7:0] arch_encoder_multiplier_core_scratch_byte, + output wire arch_encoder_multiplier_core_fault, + output wire [127:0] arch_encoder_multiplier_core_mul_a_shift, + output wire [127:0] arch_encoder_multiplier_core_mul_accumulator, + output wire arch_encoder_start, + output wire [15:0] arch_encoder_start_index, output wire arch_fault, output wire arch_done_pulse ); @@ -111,6 +158,8 @@ module lsc1_packet_frontend ( wire [15:0] tx_arch_index, tx_arch_length; wire [7:0] tx_arch_status; wire [543:0] tx_arch_payload; + wire tx_arch_active, tx_arch_done_pulse; + wire [31:0] tx_arch_saved_crc, tx_arch_envelope_crc_work, tx_arch_payload_crc_work, tx_arch_payload_crc; reg tx_start; reg [7:0] tx_status; reg [15:0] tx_length; @@ -126,12 +175,27 @@ module lsc1_packet_frontend ( wire [7:0] alu_arch_operation; wire [5:0] alu_arch_payload_index; wire [4:0] alu_arch_result_index; + wire [127:0] alu_arch_saved_a, alu_arch_saved_b, alu_arch_core_mul_a_shift, alu_arch_core_mul_accumulator; + wire alu_arch_done_pulse, alu_arch_fault, alu_arch_core_fault; + wire [3:0] alu_arch_core_state, alu_arch_core_byte_index; + wire [7:0] alu_arch_core_scratch_byte; reg encoder_start; reg [15:0] encoder_index; wire encoder_busy, encoder_done, encoder_fault; wire [127:0] encoder_result; wire [4:0] encoder_arch_bit_index; wire [15:0] encoder_arch_saved_index; + wire encoder_arch_multiply_start, encoder_arch_done_pulse, encoder_arch_fault, encoder_arch_multiplier_core_fault; + wire [127:0] encoder_arch_accumulator, encoder_arch_operand_a, encoder_arch_operand_b; + wire [2:0] encoder_arch_multiplier_state; + wire [7:0] encoder_arch_multiplier_operation, encoder_arch_multiplier_core_scratch_byte; + wire [5:0] encoder_arch_multiplier_payload_index; + wire [4:0] encoder_arch_multiplier_result_index; + wire [127:0] encoder_arch_multiplier_saved_a, encoder_arch_multiplier_saved_b; + wire encoder_arch_multiplier_done_pulse, encoder_arch_multiplier_fault; + wire [127:0] encoder_arch_multiplier_result; + wire [3:0] encoder_arch_multiplier_core_state, encoder_arch_multiplier_core_byte_index; + wire [127:0] encoder_arch_multiplier_core_mul_a_shift, encoder_arch_multiplier_core_mul_accumulator; wire lane_enable = !tx_busy && !tx_start && compute_state == C_IDLE && !alu_busy && !encoder_busy; @@ -167,7 +231,10 @@ module lsc1_packet_frontend ( .payload_crc(tx_payload_crc), .tx_data(tx_data), .tx_valid(tx_valid), .tx_ready(tx_ready), .arch_index(tx_arch_index), .arch_length(tx_arch_length), - .arch_status(tx_arch_status), .arch_payload(tx_arch_payload) + .arch_status(tx_arch_status), .arch_payload(tx_arch_payload), + .arch_active(tx_arch_active), .arch_saved_crc(tx_arch_saved_crc), + .arch_envelope_crc_work(tx_arch_envelope_crc_work), .arch_payload_crc_work(tx_arch_payload_crc_work), + .arch_done_pulse(tx_arch_done_pulse), .arch_payload_crc(tx_arch_payload_crc) ); lsc1_stream_adapter adapter ( @@ -176,14 +243,30 @@ module lsc1_packet_frontend ( .operand_b(alu_operand_b), .busy(alu_busy), .done_pulse(alu_done), .fault(alu_fault), .result(alu_result), .arch_state(alu_arch_state), .arch_operation(alu_arch_operation), - .arch_payload_index(alu_arch_payload_index), .arch_result_index(alu_arch_result_index) + .arch_payload_index(alu_arch_payload_index), .arch_result_index(alu_arch_result_index), + .arch_saved_a(alu_arch_saved_a), .arch_saved_b(alu_arch_saved_b), + .arch_done_pulse(alu_arch_done_pulse), .arch_fault(alu_arch_fault), .arch_result(), + .arch_core_state(alu_arch_core_state), .arch_core_byte_index(alu_arch_core_byte_index), + .arch_core_scratch_byte(alu_arch_core_scratch_byte), .arch_core_fault(alu_arch_core_fault), + .arch_core_mul_a_shift(alu_arch_core_mul_a_shift), .arch_core_mul_accumulator(alu_arch_core_mul_accumulator) ); lsc1_field_encoder field_encoder ( .clk(clk), .rst_n(rst_n), .abort(abort), .start(encoder_start), .index(encoder_index), .busy(encoder_busy), .done_pulse(encoder_done), .fault(encoder_fault), .result(encoder_result), - .arch_bit_index(encoder_arch_bit_index), .arch_saved_index(encoder_arch_saved_index) + .arch_bit_index(encoder_arch_bit_index), .arch_saved_index(encoder_arch_saved_index), + .arch_multiply_start(encoder_arch_multiply_start), .arch_accumulator(encoder_arch_accumulator), + .arch_operand_a(encoder_arch_operand_a), .arch_operand_b(encoder_arch_operand_b), + .arch_done_pulse(encoder_arch_done_pulse), .arch_fault(encoder_arch_fault), .arch_result(), + .arch_multiplier_state(encoder_arch_multiplier_state), .arch_multiplier_operation(encoder_arch_multiplier_operation), + .arch_multiplier_payload_index(encoder_arch_multiplier_payload_index), .arch_multiplier_result_index(encoder_arch_multiplier_result_index), + .arch_multiplier_saved_a(encoder_arch_multiplier_saved_a), .arch_multiplier_saved_b(encoder_arch_multiplier_saved_b), + .arch_multiplier_done_pulse(encoder_arch_multiplier_done_pulse), .arch_multiplier_fault(encoder_arch_multiplier_fault), + .arch_multiplier_result(encoder_arch_multiplier_result), + .arch_multiplier_core_state(encoder_arch_multiplier_core_state), .arch_multiplier_core_byte_index(encoder_arch_multiplier_core_byte_index), + .arch_multiplier_core_scratch_byte(encoder_arch_multiplier_core_scratch_byte), .arch_multiplier_core_fault(encoder_arch_multiplier_core_fault), + .arch_multiplier_core_mul_a_shift(encoder_arch_multiplier_core_mul_a_shift), .arch_multiplier_core_mul_accumulator(encoder_arch_multiplier_core_mul_accumulator) ); assign rx_ready = parser_rx_ready && lane_enable; @@ -228,16 +311,63 @@ module lsc1_packet_frontend ( assign arch_tx_status = tx_arch_status; assign arch_tx_payload = tx_arch_payload; assign arch_tx_payload_crc = tx_payload_crc; + assign arch_tx_active = tx_arch_active; + assign arch_tx_saved_crc = tx_arch_saved_crc; + assign arch_tx_envelope_crc_work = tx_arch_envelope_crc_work; + assign arch_tx_payload_crc_work = tx_arch_payload_crc_work; + assign arch_tx_done_pulse = tx_arch_done_pulse; + assign arch_tx_start = tx_start; + assign arch_tx_start_status = tx_status; + assign arch_tx_start_length = tx_length; + assign arch_tx_start_payload = tx_payload; + assign arch_capture_result_crc = capture_result_crc; assign arch_alu_busy = alu_busy; assign arch_alu_phase = alu_arch_state; assign arch_alu_operation = alu_arch_operation; assign arch_alu_payload_index = alu_arch_payload_index; assign arch_alu_result_index = alu_arch_result_index; assign arch_alu_result = alu_result; + assign arch_alu_saved_a = alu_arch_saved_a; + assign arch_alu_saved_b = alu_arch_saved_b; + assign arch_alu_done_pulse = alu_arch_done_pulse; + assign arch_alu_fault = alu_arch_fault; + assign arch_alu_core_phase = alu_arch_core_state; + assign arch_alu_core_byte_index = alu_arch_core_byte_index; + assign arch_alu_core_scratch_byte = alu_arch_core_scratch_byte; + assign arch_alu_core_fault = alu_arch_core_fault; + assign arch_alu_core_mul_a_shift = alu_arch_core_mul_a_shift; + assign arch_alu_core_mul_accumulator = alu_arch_core_mul_accumulator; + assign arch_alu_start = alu_start; + assign arch_alu_start_operation = alu_operation; + assign arch_alu_start_operand_a = alu_operand_a; + assign arch_alu_start_operand_b = alu_operand_b; assign arch_encoder_busy = encoder_busy; assign arch_encoder_bit_index = encoder_arch_bit_index; assign arch_encoder_index = encoder_arch_saved_index; assign arch_encoder_result = encoder_result; + assign arch_encoder_done_pulse = encoder_arch_done_pulse; + assign arch_encoder_fault = encoder_arch_fault; + assign arch_encoder_multiply_start = encoder_arch_multiply_start; + assign arch_encoder_accumulator = encoder_arch_accumulator; + assign arch_encoder_operand_a = encoder_arch_operand_a; + assign arch_encoder_operand_b = encoder_arch_operand_b; + assign arch_encoder_multiplier_phase = encoder_arch_multiplier_state; + assign arch_encoder_multiplier_operation = encoder_arch_multiplier_operation; + assign arch_encoder_multiplier_payload_index = encoder_arch_multiplier_payload_index; + assign arch_encoder_multiplier_result_index = encoder_arch_multiplier_result_index; + assign arch_encoder_multiplier_saved_a = encoder_arch_multiplier_saved_a; + assign arch_encoder_multiplier_saved_b = encoder_arch_multiplier_saved_b; + assign arch_encoder_multiplier_done_pulse = encoder_arch_multiplier_done_pulse; + assign arch_encoder_multiplier_fault = encoder_arch_multiplier_fault; + assign arch_encoder_multiplier_result = encoder_arch_multiplier_result; + assign arch_encoder_multiplier_core_phase = encoder_arch_multiplier_core_state; + assign arch_encoder_multiplier_core_byte_index = encoder_arch_multiplier_core_byte_index; + assign arch_encoder_multiplier_core_scratch_byte = encoder_arch_multiplier_core_scratch_byte; + assign arch_encoder_multiplier_core_fault = encoder_arch_multiplier_core_fault; + assign arch_encoder_multiplier_core_mul_a_shift = encoder_arch_multiplier_core_mul_a_shift; + assign arch_encoder_multiplier_core_mul_accumulator = encoder_arch_multiplier_core_mul_accumulator; + assign arch_encoder_start = encoder_start; + assign arch_encoder_start_index = encoder_index; assign arch_fault = fault; assign arch_done_pulse = done_pulse; diff --git a/asic_core/rtl/lsc1_packet_tx.sv b/asic_core/rtl/lsc1_packet_tx.sv index 1a38a5f..4aa90ff 100644 --- a/asic_core/rtl/lsc1_packet_tx.sv +++ b/asic_core/rtl/lsc1_packet_tx.sv @@ -17,7 +17,13 @@ module lsc1_packet_tx ( input wire tx_ready, output wire [15:0] arch_index, arch_length, output wire [7:0] arch_status, - output wire [543:0] arch_payload + output wire [543:0] arch_payload, + output wire arch_active, + output wire [31:0] arch_saved_crc, + output wire [31:0] arch_envelope_crc_work, + output wire [31:0] arch_payload_crc_work, + output wire arch_done_pulse, + output wire [31:0] arch_payload_crc ); reg active; reg [15:0] index; @@ -45,6 +51,12 @@ module lsc1_packet_tx ( assign tx_valid = active; assign arch_index = index; assign arch_length = saved_length; assign arch_status = saved_status; assign arch_payload = saved_payload; + assign arch_active = active; + assign arch_saved_crc = saved_crc; + assign arch_envelope_crc_work = envelope_crc_work; + assign arch_payload_crc_work = payload_crc_work; + assign arch_done_pulse = done_pulse; + assign arch_payload_crc = payload_crc; always @(*) begin if (index == 0) tx_data = 8'h5a; diff --git a/asic_core/rtl/lsc1_stream_adapter.sv b/asic_core/rtl/lsc1_stream_adapter.sv index 30f837a..5225323 100644 --- a/asic_core/rtl/lsc1_stream_adapter.sv +++ b/asic_core/rtl/lsc1_stream_adapter.sv @@ -18,7 +18,18 @@ module lsc1_stream_adapter ( output wire [2:0] arch_state, output wire [7:0] arch_operation, output wire [5:0] arch_payload_index, - output wire [4:0] arch_result_index + output wire [4:0] arch_result_index, + output wire [127:0] arch_saved_a, + output wire [127:0] arch_saved_b, + output wire arch_done_pulse, + output wire arch_fault, + output wire [127:0] arch_result, + output wire [3:0] arch_core_state, + output wire [3:0] arch_core_byte_index, + output wire [7:0] arch_core_scratch_byte, + output wire arch_core_fault, + output wire [127:0] arch_core_mul_a_shift, + output wire [127:0] arch_core_mul_accumulator ); localparam [7:0] OP_XOR = 8'h01, OP_MUL = 8'h02, OP_SET = 8'h03; localparam [2:0] S_IDLE = 3'd0, S_CLEAR = 3'd1, @@ -50,12 +61,18 @@ module lsc1_stream_adapter ( .rx_ready(core_rx_ready), .tx_data(core_tx_data), .tx_valid(core_tx_valid), .tx_ready(core_tx_ready), - .busy(core_busy), .done_pulse(core_done), .fault(core_fault) + .busy(core_busy), .done_pulse(core_done), .fault(core_fault), + .arch_state(arch_core_state), .arch_byte_index(arch_core_byte_index), + .arch_scratch_byte(arch_core_scratch_byte), + .arch_mul_a_shift(arch_core_mul_a_shift), .arch_mul_accumulator(arch_core_mul_accumulator) ); assign busy = state != S_IDLE; assign arch_state = state; assign arch_operation = saved_operation; assign arch_payload_index = payload_index; assign arch_result_index = result_index; + assign arch_saved_a = saved_a; assign arch_saved_b = saved_b; + assign arch_done_pulse = done_pulse; assign arch_fault = fault; assign arch_result = result; + assign arch_core_fault = core_fault; always @(*) begin core_rx_valid = 1'b0; diff --git a/formal/ARCH_STATE.md b/formal/ARCH_STATE.md index 4d4b4f2..a0fb853 100644 --- a/formal/ARCH_STATE.md +++ b/formal/ARCH_STATE.md @@ -15,9 +15,9 @@ asserts coverage mechanically. | --- | --- | --- | | RX parser | phase, header/body positions, declared length, header context, CRCs, complete accepted frame and parser fault | request acceptance and command dispatch | | Frontend | compute phase, staged transaction/CRC, committed PC/FP, sequence, profile, status/fault | profile choice, RETIRE, STATUS, future request validation | -| TX serializer | busy, byte index, saved status/length/payload, payload CRC | `tx_valid` and every response byte under backpressure | -| ALU adapter | phase, operation, payload/result positions, result | deferred arithmetic completion | -| Field encoder | busy, bit index, saved index, result | pointer witness completion | +| TX serializer | active, byte index, saved status/length/payload, saved CRC, working envelope/payload CRCs, completion and payload CRC | `tx_valid`, every response byte, and the next checksum state under backpressure | +| ALU adapter and core | phase, saved opcode/operands, payload/result positions, result/fault/pulse, core phase/index/scratch, GF shift/accumulator | deferred arithmetic completion and next stream byte | +| Field encoder and nested multiplier | busy, start/progress, index, accumulator, operands, result/fault/pulse, and the nested adapter/core/GF state | pointer witness completion and every intermediate multiplication cycle | ``` RX registered frame ──► frontend decode/compute ──► staged result ──► TX registered serializer ──► tx_valid/tx_data @@ -29,8 +29,10 @@ RX registered frame ──► frontend decode/compute ──► staged result ``` All arrows cross registered boundaries except the listed busy/output functions. -The map checker requires every public `arch_*` port and every packet output to -be covered, and its self-mutation guard rejects a changed source mapping. +The map has explicit bit widths. The checker requires every public `arch_*` +port, every nonblocking-assigned state element in the active recursive module +tree, and every packet output reconstruction to be covered. Its mutation guard +rejects altered TX CRC and saved-operand mappings. `R(rtl, arch)` is direct equality to the mapped registered RTL signal. The only derived fields are busy flags and protocol outputs, whose source registers are diff --git a/formal/lsc1_packet_frontend_arch_state_map.json b/formal/lsc1_packet_frontend_arch_state_map.json index 2095810..a2764a7 100644 --- a/formal/lsc1_packet_frontend_arch_state_map.json +++ b/formal/lsc1_packet_frontend_arch_state_map.json @@ -1,28 +1,520 @@ { - "schema": 1, + "schema": 2, "module": "lsc1_packet_frontend", - "relation": "R(rtl_state, arch_state) is direct field equality; every source is a registered RTL signal except parser_busy, tx_busy, alu_busy, encoder_busy, and output-valid/data, which are documented functions of the listed registered state.", + "relation": "R is direct equality at each active clock boundary; every mapped source is registered state or an explicit output reconstruction function. No symbolic bridge, cutpoint, or ignored output channel is used.", "fields": { - "arch_phase":"compute_state", "arch_parser_busy":"rx_busy", "arch_parser_phase":"parser_arch_state", - "arch_parser_header_index":"parser_arch_header_index", "arch_parser_body_index":"parser_arch_body_index", - "arch_parser_declared_length":"parser_arch_declared_length", "arch_parser_version":"parser_arch_version", - "arch_parser_opcode":"parser_arch_opcode", "arch_parser_flags":"parser_arch_flags", "arch_parser_crc":"parser_arch_crc", - "arch_parser_received_crc":"parser_arch_received_crc", "arch_frame_valid":"frame_valid", - "arch_frame_opcode":"frame_opcode", "arch_frame_length":"frame_length", "arch_frame_payload":"frame_payload", - "arch_rx_fault_valid":"rx_fault_valid", "arch_rx_fault_status":"rx_fault_status", - "arch_result_pending":"result_pending", "arch_staged_txn_id":"staged_txn_id", - "arch_staged_next_pc":"staged_next_pc", "arch_staged_next_fp":"staged_next_fp", - "arch_staged_result_crc":"staged_result_crc", "arch_state_valid":"state_valid", - "arch_committed_pc":"committed_pc", "arch_committed_fp":"committed_fp", "arch_retire_seq":"retire_seq", - "arch_active_profile":"active_profile", "arch_last_status":"last_status", "arch_last_fault":"last_fault", - "arch_tx_busy":"tx_busy", "arch_tx_index":"tx_arch_index", "arch_tx_length":"tx_arch_length", - "arch_tx_status":"tx_arch_status", "arch_tx_payload":"tx_arch_payload", - "arch_tx_payload_crc":"tx_payload_crc", "arch_alu_busy":"alu_busy", "arch_alu_phase":"alu_arch_state", - "arch_alu_operation":"alu_arch_operation", "arch_alu_payload_index":"alu_arch_payload_index", - "arch_alu_result_index":"alu_arch_result_index", "arch_alu_result":"alu_result", "arch_encoder_busy":"encoder_busy", - "arch_encoder_bit_index":"encoder_arch_bit_index", "arch_encoder_index":"encoder_arch_saved_index", - "arch_encoder_result":"encoder_result", "arch_fault":"fault", "arch_done_pulse":"done_pulse" + "arch_phase": { + "source": "compute_state", + "width": 4 + }, + "arch_parser_busy": { + "source": "rx_busy", + "width": 1 + }, + "arch_parser_phase": { + "source": "parser_arch_state", + "width": 3 + }, + "arch_parser_header_index": { + "source": "parser_arch_header_index", + "width": 3 + }, + "arch_parser_body_index": { + "source": "parser_arch_body_index", + "width": 16 + }, + "arch_parser_declared_length": { + "source": "parser_arch_declared_length", + "width": 16 + }, + "arch_parser_version": { + "source": "parser_arch_version", + "width": 8 + }, + "arch_parser_opcode": { + "source": "parser_arch_opcode", + "width": 8 + }, + "arch_parser_flags": { + "source": "parser_arch_flags", + "width": 8 + }, + "arch_parser_crc": { + "source": "parser_arch_crc", + "width": 32 + }, + "arch_parser_received_crc": { + "source": "parser_arch_received_crc", + "width": 32 + }, + "arch_frame_valid": { + "source": "frame_valid", + "width": 1 + }, + "arch_frame_opcode": { + "source": "frame_opcode", + "width": 8 + }, + "arch_frame_length": { + "source": "frame_length", + "width": 16 + }, + "arch_frame_payload": { + "source": "frame_payload", + "width": 2048 + }, + "arch_rx_fault_valid": { + "source": "rx_fault_valid", + "width": 1 + }, + "arch_rx_fault_status": { + "source": "rx_fault_status", + "width": 8 + }, + "arch_result_pending": { + "source": "result_pending", + "width": 1 + }, + "arch_staged_txn_id": { + "source": "staged_txn_id", + "width": 32 + }, + "arch_staged_next_pc": { + "source": "staged_next_pc", + "width": 32 + }, + "arch_staged_next_fp": { + "source": "staged_next_fp", + "width": 32 + }, + "arch_staged_result_crc": { + "source": "staged_result_crc", + "width": 32 + }, + "arch_state_valid": { + "source": "state_valid", + "width": 1 + }, + "arch_committed_pc": { + "source": "committed_pc", + "width": 32 + }, + "arch_committed_fp": { + "source": "committed_fp", + "width": 32 + }, + "arch_retire_seq": { + "source": "retire_seq", + "width": 32 + }, + "arch_active_profile": { + "source": "active_profile", + "width": 8 + }, + "arch_last_status": { + "source": "last_status", + "width": 8 + }, + "arch_last_fault": { + "source": "last_fault", + "width": 8 + }, + "arch_tx_busy": { + "source": "tx_busy", + "width": 1 + }, + "arch_tx_index": { + "source": "tx_arch_index", + "width": 16 + }, + "arch_tx_length": { + "source": "tx_arch_length", + "width": 16 + }, + "arch_tx_status": { + "source": "tx_arch_status", + "width": 8 + }, + "arch_tx_payload": { + "source": "tx_arch_payload", + "width": 544 + }, + "arch_tx_payload_crc": { + "source": "tx_payload_crc", + "width": 32 + }, + "arch_tx_active": { + "source": "tx_arch_active", + "width": 1 + }, + "arch_tx_saved_crc": { + "source": "tx_arch_saved_crc", + "width": 32 + }, + "arch_tx_envelope_crc_work": { + "source": "tx_arch_envelope_crc_work", + "width": 32 + }, + "arch_tx_payload_crc_work": { + "source": "tx_arch_payload_crc_work", + "width": 32 + }, + "arch_tx_done_pulse": { + "source": "tx_arch_done_pulse", + "width": 1 + }, + "arch_tx_start": { + "source": "tx_start", + "width": 1 + }, + "arch_tx_start_status": { + "source": "tx_status", + "width": 8 + }, + "arch_tx_start_length": { + "source": "tx_length", + "width": 16 + }, + "arch_tx_start_payload": { + "source": "tx_payload", + "width": 544 + }, + "arch_capture_result_crc": { + "source": "capture_result_crc", + "width": 1 + }, + "arch_alu_busy": { + "source": "alu_busy", + "width": 1 + }, + "arch_alu_phase": { + "source": "alu_arch_state", + "width": 3 + }, + "arch_alu_operation": { + "source": "alu_arch_operation", + "width": 8 + }, + "arch_alu_payload_index": { + "source": "alu_arch_payload_index", + "width": 6 + }, + "arch_alu_result_index": { + "source": "alu_arch_result_index", + "width": 5 + }, + "arch_alu_result": { + "source": "alu_result", + "width": 128 + }, + "arch_alu_saved_a": { + "source": "alu_arch_saved_a", + "width": 128 + }, + "arch_alu_saved_b": { + "source": "alu_arch_saved_b", + "width": 128 + }, + "arch_alu_done_pulse": { + "source": "alu_arch_done_pulse", + "width": 1 + }, + "arch_alu_fault": { + "source": "alu_arch_fault", + "width": 1 + }, + "arch_alu_core_phase": { + "source": "alu_arch_core_state", + "width": 4 + }, + "arch_alu_core_byte_index": { + "source": "alu_arch_core_byte_index", + "width": 4 + }, + "arch_alu_core_scratch_byte": { + "source": "alu_arch_core_scratch_byte", + "width": 8 + }, + "arch_alu_core_fault": { + "source": "alu_arch_core_fault", + "width": 1 + }, + "arch_alu_core_mul_a_shift": { + "source": "alu_arch_core_mul_a_shift", + "width": 128 + }, + "arch_alu_core_mul_accumulator": { + "source": "alu_arch_core_mul_accumulator", + "width": 128 + }, + "arch_alu_start": { + "source": "alu_start", + "width": 1 + }, + "arch_alu_start_operation": { + "source": "alu_operation", + "width": 8 + }, + "arch_alu_start_operand_a": { + "source": "alu_operand_a", + "width": 128 + }, + "arch_alu_start_operand_b": { + "source": "alu_operand_b", + "width": 128 + }, + "arch_encoder_busy": { + "source": "encoder_busy", + "width": 1 + }, + "arch_encoder_bit_index": { + "source": "encoder_arch_bit_index", + "width": 5 + }, + "arch_encoder_index": { + "source": "encoder_arch_saved_index", + "width": 16 + }, + "arch_encoder_result": { + "source": "encoder_result", + "width": 128 + }, + "arch_encoder_done_pulse": { + "source": "encoder_arch_done_pulse", + "width": 1 + }, + "arch_encoder_fault": { + "source": "encoder_arch_fault", + "width": 1 + }, + "arch_encoder_multiply_start": { + "source": "encoder_arch_multiply_start", + "width": 1 + }, + "arch_encoder_accumulator": { + "source": "encoder_arch_accumulator", + "width": 128 + }, + "arch_encoder_operand_a": { + "source": "encoder_arch_operand_a", + "width": 128 + }, + "arch_encoder_operand_b": { + "source": "encoder_arch_operand_b", + "width": 128 + }, + "arch_encoder_multiplier_phase": { + "source": "encoder_arch_multiplier_state", + "width": 3 + }, + "arch_encoder_multiplier_operation": { + "source": "encoder_arch_multiplier_operation", + "width": 8 + }, + "arch_encoder_multiplier_payload_index": { + "source": "encoder_arch_multiplier_payload_index", + "width": 6 + }, + "arch_encoder_multiplier_result_index": { + "source": "encoder_arch_multiplier_result_index", + "width": 5 + }, + "arch_encoder_multiplier_saved_a": { + "source": "encoder_arch_multiplier_saved_a", + "width": 128 + }, + "arch_encoder_multiplier_saved_b": { + "source": "encoder_arch_multiplier_saved_b", + "width": 128 + }, + "arch_encoder_multiplier_done_pulse": { + "source": "encoder_arch_multiplier_done_pulse", + "width": 1 + }, + "arch_encoder_multiplier_fault": { + "source": "encoder_arch_multiplier_fault", + "width": 1 + }, + "arch_encoder_multiplier_result": { + "source": "encoder_arch_multiplier_result", + "width": 128 + }, + "arch_encoder_multiplier_core_phase": { + "source": "encoder_arch_multiplier_core_state", + "width": 4 + }, + "arch_encoder_multiplier_core_byte_index": { + "source": "encoder_arch_multiplier_core_byte_index", + "width": 4 + }, + "arch_encoder_multiplier_core_scratch_byte": { + "source": "encoder_arch_multiplier_core_scratch_byte", + "width": 8 + }, + "arch_encoder_multiplier_core_fault": { + "source": "encoder_arch_multiplier_core_fault", + "width": 1 + }, + "arch_encoder_multiplier_core_mul_a_shift": { + "source": "encoder_arch_multiplier_core_mul_a_shift", + "width": 128 + }, + "arch_encoder_multiplier_core_mul_accumulator": { + "source": "encoder_arch_multiplier_core_mul_accumulator", + "width": 128 + }, + "arch_encoder_start": { + "source": "encoder_start", + "width": 1 + }, + "arch_encoder_start_index": { + "source": "encoder_index", + "width": 16 + }, + "arch_fault": { + "source": "fault", + "width": 1 + }, + "arch_done_pulse": { + "source": "done_pulse", + "width": 1 + } }, - "observable_outputs": ["rx_ready", "tx_data", "tx_valid", "busy", "fault", "done_pulse"], - "partitions": ["reset", "idle", "parser", "compute", "response", "retire"] + "registered_coverage": { + "lsc1_packet_frontend": { + "compute_state": "arch_phase", + "result_pending": "arch_result_pending", + "staged_txn_id": "arch_staged_txn_id", + "staged_next_pc": "arch_staged_next_pc", + "staged_next_fp": "arch_staged_next_fp", + "staged_result_crc": "arch_staged_result_crc", + "state_valid": "arch_state_valid", + "committed_pc": "arch_committed_pc", + "committed_fp": "arch_committed_fp", + "retire_seq": "arch_retire_seq", + "active_profile": "arch_active_profile", + "last_status": "arch_last_status", + "last_fault": "arch_last_fault", + "tx_start": "arch_tx_start", + "tx_status": "arch_tx_start_status", + "tx_length": "arch_tx_start_length", + "tx_payload": "arch_tx_start_payload", + "capture_result_crc": "arch_capture_result_crc", + "alu_start": "arch_alu_start", + "alu_operation": "arch_alu_start_operation", + "alu_operand_a": "arch_alu_start_operand_a", + "alu_operand_b": "arch_alu_start_operand_b", + "encoder_start": "arch_encoder_start", + "encoder_index": "arch_encoder_start_index", + "fault": "arch_fault", + "done_pulse": "arch_done_pulse" + }, + "lsc1_packet_tx": { + "active": "arch_tx_active", + "index": "arch_tx_index", + "saved_length": "arch_tx_length", + "saved_status": "arch_tx_status", + "saved_payload": "arch_tx_payload", + "saved_crc": "arch_tx_saved_crc", + "envelope_crc_work": "arch_tx_envelope_crc_work", + "payload_crc_work": "arch_tx_payload_crc_work", + "payload_crc": "arch_tx_payload_crc", + "done_pulse": "arch_tx_done_pulse" + }, + "lsc1_stream_adapter": { + "state": "arch_alu_phase", + "saved_operation": "arch_alu_operation", + "saved_a": "arch_alu_saved_a", + "saved_b": "arch_alu_saved_b", + "payload_index": "arch_alu_payload_index", + "result_index": "arch_alu_result_index", + "result": "arch_alu_result", + "done_pulse": "arch_alu_done_pulse", + "fault": "arch_alu_fault" + }, + "leanvm_b_stream_alu": { + "state": "arch_alu_core_phase", + "byte_index": "arch_alu_core_byte_index", + "scratch_byte": "arch_alu_core_scratch_byte", + "fault": "arch_alu_core_fault" + }, + "gf2n_mul_bitstream": { + "a_shift": "arch_alu_core_mul_a_shift", + "accumulator": "arch_alu_core_mul_accumulator" + }, + "lsc1_field_encoder": { + "busy": "arch_encoder_busy", + "multiply_start": "arch_encoder_multiply_start", + "bit_index": "arch_encoder_bit_index", + "saved_index": "arch_encoder_index", + "accumulator": "arch_encoder_accumulator", + "operand_a": "arch_encoder_operand_a", + "operand_b": "arch_encoder_operand_b", + "result": "arch_encoder_result", + "done_pulse": "arch_encoder_done_pulse", + "fault": "arch_encoder_fault" + }, + "lsc1_field_encoder.multiplier": { + "state": "arch_encoder_multiplier_phase", + "saved_operation": "arch_encoder_multiplier_operation", + "saved_a": "arch_encoder_multiplier_saved_a", + "saved_b": "arch_encoder_multiplier_saved_b", + "payload_index": "arch_encoder_multiplier_payload_index", + "result_index": "arch_encoder_multiplier_result_index", + "result": "arch_encoder_multiplier_result", + "done_pulse": "arch_encoder_multiplier_done_pulse", + "fault": "arch_encoder_multiplier_fault" + }, + "lsc1_field_encoder.multiplier.core": { + "state": "arch_encoder_multiplier_core_phase", + "byte_index": "arch_encoder_multiplier_core_byte_index", + "scratch_byte": "arch_encoder_multiplier_core_scratch_byte", + "fault": "arch_encoder_multiplier_core_fault" + }, + "lsc1_field_encoder.multiplier.core.gf": { + "a_shift": "arch_encoder_multiplier_core_mul_a_shift", + "accumulator": "arch_encoder_multiplier_core_mul_accumulator" + }, + "lsc1_packet_rx": { + "state": "arch_parser_phase", + "header_index": "arch_parser_header_index", + "body_index": "arch_parser_body_index", + "declared_length": "arch_parser_declared_length", + "version": "arch_parser_version", + "opcode": "arch_parser_opcode", + "flags": "arch_parser_flags", + "crc": "arch_parser_crc", + "received_crc": "arch_parser_received_crc", + "frame_valid": "arch_frame_valid", + "frame_opcode": "arch_frame_opcode", + "frame_length": "arch_frame_length", + "frame_payload": "arch_frame_payload", + "fault_valid": "arch_rx_fault_valid", + "fault_status": "arch_rx_fault_status" + } + }, + "observable_outputs": [ + "rx_ready", + "tx_data", + "tx_valid", + "busy", + "fault", + "done_pulse" + ], + "output_reconstruction": { + "tx_valid": "arch_tx_active", + "tx_data": "packet-TX byte function(arch_tx_index, arch_tx_length, arch_tx_status, arch_tx_payload, arch_tx_saved_crc)", + "busy": "OR(parser, tx active/start, queued event/result, compute, ALU, encoder)", + "rx_ready": "parser ready AND lane-enable", + "fault": "arch_fault", + "done_pulse": "arch_done_pulse" + }, + "partitions": [ + "reset", + "idle", + "parser", + "compute", + "response", + "retire" + ] } diff --git a/results/arch-state-omissions-20260728/README.md b/results/arch-state-omissions-20260728/README.md new file mode 100644 index 0000000..a8fd61a --- /dev/null +++ b/results/arch-state-omissions-20260728/README.md @@ -0,0 +1,16 @@ +# Recursive registered-state closure receipt + +This bounded correction closes reviewer `556ef4a8-c24a-436f-a58c-0e5706723b6c`'s +identified omissions. The interface now maps 94 explicit-width fields and 91 +nonblocking-assigned state elements across the packet RX/TX, stream adapter, +field encoder, nested stream cores, and GF shift/accumulator datapaths. + +The executable one-cycle relation is the production clocked RTL relation; the +map checker verifies direct equality, widths, recursive registered-state +completeness, all six observable channels, and mutation sensitivity. `tx_data` +is reconstructed from the mapped TX index, framing fields, payload, and saved +CRC. No assumed cutpoint or release-equivalence claim is made. + +Residual blocker: a complete frontend architectural transition/refinement model +for decode, transaction staging, and backpressure has not been reviewed. This +slice only closes the verified omitted-state partition. diff --git a/results/arch-state-omissions-20260728/SHA256SUMS b/results/arch-state-omissions-20260728/SHA256SUMS new file mode 100644 index 0000000..e46b797 --- /dev/null +++ b/results/arch-state-omissions-20260728/SHA256SUMS @@ -0,0 +1,7 @@ +c377a2118b46bdb2786c85aac8cfe2226e9a9eec3e009451f357c52f7e3fc414 results/arch-state-omissions-20260728/differential.log +c1a78566db364c4d3c9ba81031c90e0641395b86f95de187eb0616466fe6b23e results/arch-state-omissions-20260728/forbidden-token-scan.log +4c0959a206d1b2d8d17b2c62eb7b2a7f92b83c38167f1c4009a9d05cb0f287ed results/arch-state-omissions-20260728/formal-reset.log +4c8f5cc3ce7dc012f38e9889075fef35fa19946a56ee529e1e10bc8d2e77e7b8 results/arch-state-omissions-20260728/interface-coverage.log +c3a2a9f65cc2cc17d980a939d510da253dba23547a875440b950137da81581c5 results/arch-state-omissions-20260728/mutation.log +1232f3d6bb4138ddf396895ed067274601df653827828396b79a88b2430a438d results/arch-state-omissions-20260728/rtl.log +f550fcd0882dc02526e9301821800a8bbbe79d5f327bd4c010fd8d882630405e results/arch-state-omissions-20260728/versions.log diff --git a/results/arch-state-omissions-20260728/differential.log b/results/arch-state-omissions-20260728/differential.log new file mode 100644 index 0000000..c7f02cd --- /dev/null +++ b/results/arch-state-omissions-20260728/differential.log @@ -0,0 +1,9 @@ +test_adversarial_jump_inverse_and_xor_backsolve_match_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_adversarial_jump_inverse_and_xor_backsolve_match_model) ... ok +test_deref_and_jump_faults_match_the_executable_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_faults_match_the_executable_model) ... ok +test_deref_and_jump_match_the_executable_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_match_the_executable_model) ... ok +test_seeded_set_xor_mul_and_frame_faults (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_seeded_set_xor_mul_and_frame_faults) ... ok + +---------------------------------------------------------------------- +Ran 4 tests in 1.193s + +OK diff --git a/results/arch-state-omissions-20260728/forbidden-token-scan.log b/results/arch-state-omissions-20260728/forbidden-token-scan.log new file mode 100644 index 0000000..856e812 --- /dev/null +++ b/results/arch-state-omissions-20260728/forbidden-token-scan.log @@ -0,0 +1,2 @@ +formal/ARCH_STATE.md:48:observations. No cutpoints, black boxes, symbolic bridge state, or ignored +asic_core/rtl/lsc1_packet_frontend.sv:278: // of such fields). No symbolic bridge or assumed cutpoint is used. diff --git a/results/arch-state-omissions-20260728/formal-reset.log b/results/arch-state-omissions-20260728/formal-reset.log new file mode 100644 index 0000000..16d3c71 --- /dev/null +++ b/results/arch-state-omissions-20260728/formal-reset.log @@ -0,0 +1,3088 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Executing script file `formal/lsc1_packet_frontend_arch_reset_idle.ys' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_rx.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: formal/lsc1_packet_frontend_arch_reset_idle.sv +Parsing formal SystemVerilog input from `formal/lsc1_packet_frontend_arch_reset_idle.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend_arch_reset_idle'. +Successfully finished Verilog frontend. + +3. Executing PREP pass. + +3.1. Executing HIERARCHY pass (managing design hierarchy). + +3.1.1. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend_arch_reset_idle +Used module: \lsc1_packet_rx + +3.1.2. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend_arch_reset_idle +Used module: \lsc1_packet_rx +Removed 0 unused modules. +Module lsc1_packet_frontend_arch_reset_idle directly or indirectly contains formal properties -> setting "keep" attribute. + +3.2. Executing PROC pass (convert processes to netlists). + +3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 11 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_rx.sv:71$23 in module lsc1_packet_rx. +Removed a total of 0 dead cases. + +3.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 25 assignments to connections. + +3.2.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$294'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_EN = 1'0 +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$292'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_EN = 1'0 +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$290'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_EN = 1'0 +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$288'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN = 1'0 + +3.2.5. Executing PROC_ARST pass (detect async resets in processes). + +3.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$294'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$292'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$290'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$288'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + 1/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN[0:0]$255 + 2/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_CHECK[0:0]$254 + 3/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_EN[0:0]$257 + 4/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_CHECK[0:0]$256 + 5/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_EN[0:0]$259 + 6/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_CHECK[0:0]$258 + 7/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_EN[0:0]$261 + 8/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_CHECK[0:0]$260 +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. +Creating decoders for process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + 1/89: $0\received_crc[31:0] [31:24] + 2/89: $0\received_crc[31:0] [23:16] + 3/89: $0\received_crc[31:0] [15:8] + 4/89: $0\received_crc[31:0] [7:0] + 5/89: $5$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$185 + 6/89: $5$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$184 + 7/89: $5$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$186 + 8/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$177 + 9/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$180 + 10/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$181 + 11/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$179 + 12/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$178 + 13/89: $4$lookahead\frame_payload$22[2047:0]$182 + 14/89: $4$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$176 + 15/89: $4$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$175 + 16/89: $4$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$174 + 17/89: $0\declared_length[15:0] [15:8] + 18/89: $0\declared_length[15:0] [7:0] + 19/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$103 + 20/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$102 + 21/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$101 + 22/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$85 + 23/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$84 + 24/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$83 + 25/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$82 + 26/89: $3$lookahead\frame_payload$22[2047:0]$99 + 27/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$98 + 28/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$97 + 29/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$96 + 30/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$95 + 31/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$94 + 32/89: $3$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$93 + 33/89: $3$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$92 + 34/89: $3$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$91 + 35/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$90 + 36/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$89 + 37/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$88 + 38/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$87 + 39/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$86 + 40/89: $2$lookahead\frame_payload$22[2047:0]$81 + 41/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$80 + 42/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$79 + 43/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$78 + 44/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$77 + 45/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$76 + 46/89: $2$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$75 + 47/89: $2$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$74 + 48/89: $2$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$73 + 49/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$72 + 50/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$71 + 51/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$70 + 52/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$69 + 53/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$68 + 54/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$67 + 55/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$66 + 56/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$65 + 57/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$64 + 58/89: $1$lookahead\frame_payload$22[2047:0]$61 + 59/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$60 + 60/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$59 + 61/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$58 + 62/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$57 + 63/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$56 + 64/89: $1$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$55 + 65/89: $1$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$54 + 66/89: $1$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$53 + 67/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$52 + 68/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$51 + 69/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$50 + 70/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$49 + 71/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$48 + 72/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$47 + 73/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$46 + 74/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$45 + 75/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$44 + 76/89: $5$lookahead\frame_payload$22[2047:0]$187 + 77/89: $0\crc[31:0] + 78/89: $0\flags[7:0] + 79/89: $0\opcode[7:0] + 80/89: $0\version[7:0] + 81/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$104 + 82/89: $0\body_index[15:0] + 83/89: $0\header_index[2:0] + 84/89: $0\state[2:0] + 85/89: $0\fault_status[7:0] + 86/89: $0\fault_valid[0:0] + 87/89: $0\frame_length[15:0] + 88/89: $0\frame_opcode[7:0] + 89/89: $0\frame_valid[0:0] + +3.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$239_CHECK' from process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. +No latch inferred for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$239_EN' from process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. + +3.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1240' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1241' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1242' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1243' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1244' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1245' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1246' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1247' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1248' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1249' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1250' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_payload' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1251' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1252' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_status' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1253' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\state' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1254' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\header_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1255' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\body_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1256' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\declared_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1257' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\version' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1258' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1259' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\flags' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1260' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1261' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\received_crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1262' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1263' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1264' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1265' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1266' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1267' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1268' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1269' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1270' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1271' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1272' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1273' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1274' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1275' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1276' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1277' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1278' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1279' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$lookahead\frame_payload$22' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1280' with positive edge clock. + +3.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$294'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$292'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$290'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$288'. +Found and cleaned up 1 empty switch in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. +Found and cleaned up 14 empty switches in `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. +Removing empty process `lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. +Cleaned up 15 empty switches. + +3.2.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + +Optimizing module lsc1_packet_rx. + + +3.3. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 215 unused cells and 635 unused wires. + + +3.5. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_frontend_arch_reset_idle... +Checking module lsc1_packet_rx... +Found and reported 0 problems. + +3.6. Executing OPT pass (performing simple optimizations). + +3.6.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.6.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. + +Finding identical cells in module `\lsc1_packet_rx'. + +Removed a total of 55 cells. + +3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$488. + dead port 2/2 on $mux $procmux$490. + dead port 1/2 on $mux $procmux$493. + dead port 2/2 on $mux $procmux$649. + dead port 1/2 on $mux $procmux$652. + dead port 1/2 on $mux $procmux$780. + dead port 2/2 on $mux $procmux$944. + dead port 2/2 on $mux $procmux$946. + dead port 2/2 on $mux $procmux$948. + dead port 1/2 on $mux $procmux$951. +Removed 10 multiplexer ports. + + +3.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. + Optimizing cells in module \lsc1_packet_rx. + New ctrl vector for $pmux cell $procmux$1083: { $auto$opt_reduce.cc:134:opt_pmux$1332 $procmux$1038_CMP } + Optimizing cells in module \lsc1_packet_rx. +Performed a total of 1 changes. + +3.6.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Finding identical cells in module `\lsc1_packet_rx'. + +Removed a total of 15 cells. + +3.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 0 unused cells and 88 unused wires. + + +3.6.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.6.8. Rerunning OPT passes. (Maybe there is more to do..) + +3.6.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.6.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. + Optimizing cells in module \lsc1_packet_rx. +Performed a total of 0 changes. + +3.6.11. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Finding identical cells in module `\lsc1_packet_rx'. +Removed a total of 0 cells. + +3.6.12. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. + +3.6.13. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.6.14. Finished OPT passes. (There is nothing left to do.) + +3.7. Executing WREDUCE pass (reducing word size of cells). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$ne$asic_core/rtl/lsc1_packet_rx.sv:60$16 ($ne). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1283 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1285 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1287 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1289 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1291 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1293 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1295 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1297 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1299 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1301 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1303 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1305 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1307 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1309 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1311 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1313 ($not). +Removed top 7 bits (of 16) from port B of cell lsc1_packet_rx.$gt$asic_core/rtl/lsc1_packet_rx.sv:122$171 ($gt). +Removed top 7 bits (of 16) from port B of cell lsc1_packet_rx.$lt$asic_core/rtl/lsc1_packet_rx.sv:135$183 ($lt). +Removed top 28 bits (of 32) from port B of cell lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188 ($mul). +Removed top 12 bits (of 32) from port Y of cell lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188 ($mul). +Removed top 12 bits (of 32) from port A of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 11 bits (of 32) from port Y of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 11 bits (of 33) from port A of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Converting cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub) from signed to unsigned. +Removed top 10 bits (of 33) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 1 bits (of 22) from port A of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 1 bits (of 23) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 11 bits (of 33) from port A of cell lsc1_packet_rx.$neg$asic_core/rtl/lsc1_packet_rx.sv:0$191 ($neg). +Removed top 15 bits (of 32) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:139$233 ($sub). +Removed top 7 bits (of 8) from port B of cell lsc1_packet_rx.$ne$asic_core/rtl/lsc1_packet_rx.sv:147$236 ($ne). +Removed top 24 bits (of 32) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1281 ($not). +Removed top 30 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$331_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$348_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1012_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1035_CMP0 ($eq). +Removed top 30 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$1073_CMP0 ($eq). +Removed top 2 bits (of 3) from mux cell lsc1_packet_rx.$procmux$1081 ($mux). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1085_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1086_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1087_CMP0 ($eq). +Removed top 1 bits (of 3) from mux cell lsc1_packet_rx.$procmux$1091 ($mux). +Removed top 11 bits (of 32) from wire lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189_Y. +Removed top 12 bits (of 32) from wire lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188_Y. +Removed top 2 bits (of 3) from wire lsc1_packet_rx.$procmux$1081_Y. +Removed top 1 bits (of 3) from wire lsc1_packet_rx.$procmux$1091_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$110_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$114_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$118_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$122_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$126_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$130_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$134_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$139_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$143_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$147_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$151_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$155_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$159_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$163_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$167_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$109_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$113_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$117_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$121_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$125_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$129_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$133_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$142_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$146_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$150_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$154_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$158_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$162_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$166_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$xor$asic_core/rtl/lsc1_packet_rx.sv:53$138_Y. + +3.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 0 unused cells and 34 unused wires. + + +3.9. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.10. Executing OPT pass (performing simple optimizations). + +3.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Finding identical cells in module `\lsc1_packet_rx'. +Removed a total of 0 cells. + +3.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. + +3.10.4. Finished fast OPT passes. + +3.11. Printing statistics. + +=== lsc1_packet_frontend_arch_reset_idle === + + Number of wires: 48 + Number of wire bits: 2248 + Number of public wires: 23 + Number of public wire bits: 2223 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 36 + $anyseq 5 + $assert 4 + $assume 1 + $dff 5 + $eq 1 + $logic_and 8 + $logic_not 11 + lsc1_packet_rx 1 + +=== lsc1_packet_rx === + + Number of wires: 237 + Number of wire bits: 25229 + Number of public wires: 33 + Number of public wire bits: 2350 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 211 + $add 3 + $and 1 + $dff 15 + $eq 9 + $gt 1 + $logic_and 5 + $logic_not 6 + $logic_or 3 + $lt 2 + $mul 1 + $mux 120 + $ne 4 + $neg 1 + $not 19 + $or 1 + $pmux 12 + $reduce_bool 2 + $reduce_or 1 + $shift 2 + $sub 2 + $xor 1 + +=== design hierarchy === + + lsc1_packet_frontend_arch_reset_idle 1 + lsc1_packet_rx 1 + + Number of wires: 285 + Number of wire bits: 27477 + Number of public wires: 56 + Number of public wire bits: 4573 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 246 + $add 3 + $and 1 + $anyseq 5 + $assert 4 + $assume 1 + $dff 20 + $eq 10 + $gt 1 + $logic_and 13 + $logic_not 17 + $logic_or 3 + $lt 2 + $mul 1 + $mux 120 + $ne 4 + $neg 1 + $not 19 + $or 1 + $pmux 12 + $reduce_bool 2 + $reduce_or 1 + $shift 2 + $sub 2 + $xor 1 + +3.12. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_frontend_arch_reset_idle... +Checking module lsc1_packet_rx... +Found and reported 0 problems. + +4. Executing FLATTEN pass (flatten design). +Deleting now unused module lsc1_packet_rx. + + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. + +Removed a total of 20 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\dut.$procmux$539. + dead port 2/2 on $mux $flatten\dut.$procmux$539. + dead port 1/2 on $mux $flatten\dut.$procmux$537. + dead port 2/2 on $mux $flatten\dut.$procmux$537. + dead port 1/2 on $mux $flatten\dut.$procmux$535. + dead port 2/2 on $mux $flatten\dut.$procmux$535. + dead port 1/2 on $mux $flatten\dut.$procmux$486. + dead port 2/2 on $mux $flatten\dut.$procmux$486. + dead port 1/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$137. + dead port 2/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$137. + dead port 1/2 on $mux $flatten\dut.$procmux$373. + dead port 2/2 on $mux $flatten\dut.$procmux$373. + dead port 1/3 on $pmux $flatten\dut.$procmux$370. + dead port 2/3 on $pmux $flatten\dut.$procmux$370. + dead port 3/3 on $pmux $flatten\dut.$procmux$370. + dead port 1/2 on $mux $flatten\dut.$procmux$368. + dead port 2/2 on $mux $flatten\dut.$procmux$368. + dead port 1/2 on $mux $flatten\dut.$procmux$365. + dead port 2/2 on $mux $flatten\dut.$procmux$365. + dead port 1/2 on $mux $flatten\dut.$procmux$355. + dead port 2/2 on $mux $flatten\dut.$procmux$355. + dead port 1/3 on $pmux $flatten\dut.$procmux$352. + dead port 2/3 on $pmux $flatten\dut.$procmux$352. + dead port 3/3 on $pmux $flatten\dut.$procmux$352. + dead port 1/2 on $mux $flatten\dut.$procmux$350. + dead port 2/2 on $mux $flatten\dut.$procmux$350. + dead port 1/2 on $mux $flatten\dut.$procmux$347. + dead port 2/2 on $mux $flatten\dut.$procmux$347. + dead port 1/2 on $mux $flatten\dut.$procmux$338. + dead port 2/2 on $mux $flatten\dut.$procmux$338. + dead port 1/3 on $pmux $flatten\dut.$procmux$335. + dead port 2/3 on $pmux $flatten\dut.$procmux$335. + dead port 3/3 on $pmux $flatten\dut.$procmux$335. + dead port 1/2 on $mux $flatten\dut.$procmux$333. + dead port 2/2 on $mux $flatten\dut.$procmux$333. + dead port 1/2 on $mux $flatten\dut.$procmux$330. + dead port 2/2 on $mux $flatten\dut.$procmux$330. + dead port 1/2 on $mux $flatten\dut.$procmux$322. + dead port 2/2 on $mux $flatten\dut.$procmux$322. + dead port 1/3 on $pmux $flatten\dut.$procmux$319. + dead port 2/3 on $pmux $flatten\dut.$procmux$319. + dead port 3/3 on $pmux $flatten\dut.$procmux$319. + dead port 1/2 on $mux $flatten\dut.$procmux$317. + dead port 2/2 on $mux $flatten\dut.$procmux$317. + dead port 1/2 on $mux $flatten\dut.$procmux$314. + dead port 2/2 on $mux $flatten\dut.$procmux$314. + dead port 1/2 on $mux $flatten\dut.$procmux$1235. + dead port 2/2 on $mux $flatten\dut.$procmux$1235. + dead port 1/2 on $mux $flatten\dut.$procmux$1233. + dead port 2/2 on $mux $flatten\dut.$procmux$1233. + dead port 1/2 on $mux $flatten\dut.$procmux$1231. + dead port 2/2 on $mux $flatten\dut.$procmux$1231. + dead port 1/2 on $mux $flatten\dut.$procmux$1228. + dead port 2/2 on $mux $flatten\dut.$procmux$1228. + dead port 1/2 on $mux $flatten\dut.$procmux$1226. + dead port 2/2 on $mux $flatten\dut.$procmux$1226. + dead port 1/2 on $mux $flatten\dut.$procmux$1223. + dead port 2/2 on $mux $flatten\dut.$procmux$1223. + dead port 1/2 on $mux $flatten\dut.$procmux$1220. + dead port 2/2 on $mux $flatten\dut.$procmux$1220. + dead port 1/2 on $mux $flatten\dut.$procmux$1215. + dead port 2/2 on $mux $flatten\dut.$procmux$1215. + dead port 1/2 on $mux $flatten\dut.$procmux$1210. + dead port 2/2 on $mux $flatten\dut.$procmux$1210. + dead port 1/2 on $mux $flatten\dut.$procmux$1208. + dead port 2/2 on $mux $flatten\dut.$procmux$1208. + dead port 1/2 on $mux $flatten\dut.$procmux$1206. + dead port 2/2 on $mux $flatten\dut.$procmux$1206. + dead port 1/2 on $mux $flatten\dut.$procmux$1203. + dead port 2/2 on $mux $flatten\dut.$procmux$1203. + dead port 1/2 on $mux $flatten\dut.$procmux$1201. + dead port 2/2 on $mux $flatten\dut.$procmux$1201. + dead port 1/2 on $mux $flatten\dut.$procmux$1198. + dead port 2/2 on $mux $flatten\dut.$procmux$1198. + dead port 1/2 on $mux $flatten\dut.$procmux$1195. + dead port 2/2 on $mux $flatten\dut.$procmux$1195. + dead port 1/2 on $mux $flatten\dut.$procmux$1187. + dead port 2/2 on $mux $flatten\dut.$procmux$1187. + dead port 1/2 on $mux $flatten\dut.$procmux$1185. + dead port 2/2 on $mux $flatten\dut.$procmux$1185. + dead port 1/2 on $mux $flatten\dut.$procmux$1183. + dead port 2/2 on $mux $flatten\dut.$procmux$1183. + dead port 1/2 on $mux $flatten\dut.$procmux$1180. + dead port 2/2 on $mux $flatten\dut.$procmux$1180. + dead port 1/2 on $mux $flatten\dut.$procmux$1178. + dead port 2/2 on $mux $flatten\dut.$procmux$1178. + dead port 1/2 on $mux $flatten\dut.$procmux$1175. + dead port 2/2 on $mux $flatten\dut.$procmux$1175. + dead port 1/2 on $mux $flatten\dut.$procmux$1172. + dead port 2/2 on $mux $flatten\dut.$procmux$1172. + dead port 1/2 on $mux $flatten\dut.$procmux$1164. + dead port 2/2 on $mux $flatten\dut.$procmux$1164. + dead port 1/2 on $mux $flatten\dut.$procmux$1161. + dead port 2/2 on $mux $flatten\dut.$procmux$1161. + dead port 1/2 on $mux $flatten\dut.$procmux$1157. + dead port 2/2 on $mux $flatten\dut.$procmux$1157. + dead port 1/2 on $mux $flatten\dut.$procmux$1155. + dead port 2/2 on $mux $flatten\dut.$procmux$1155. + dead port 1/4 on $pmux $flatten\dut.$procmux$1151. + dead port 2/4 on $pmux $flatten\dut.$procmux$1151. + dead port 3/4 on $pmux $flatten\dut.$procmux$1151. + dead port 4/4 on $pmux $flatten\dut.$procmux$1151. + dead port 1/2 on $mux $flatten\dut.$procmux$1149. + dead port 2/2 on $mux $flatten\dut.$procmux$1149. + dead port 1/2 on $mux $flatten\dut.$procmux$1146. + dead port 2/2 on $mux $flatten\dut.$procmux$1146. + dead port 1/2 on $mux $flatten\dut.$procmux$1144. + dead port 2/2 on $mux $flatten\dut.$procmux$1144. + dead port 1/2 on $mux $flatten\dut.$procmux$1141. + dead port 2/2 on $mux $flatten\dut.$procmux$1141. + dead port 1/2 on $mux $flatten\dut.$procmux$1138. + dead port 2/2 on $mux $flatten\dut.$procmux$1138. + dead port 1/2 on $mux $flatten\dut.$procmux$1133. + dead port 2/2 on $mux $flatten\dut.$procmux$1133. + dead port 1/2 on $mux $flatten\dut.$procmux$1128. + dead port 2/2 on $mux $flatten\dut.$procmux$1128. + dead port 1/2 on $mux $flatten\dut.$procmux$1125. + dead port 2/2 on $mux $flatten\dut.$procmux$1125. + dead port 1/2 on $mux $flatten\dut.$procmux$1121. + dead port 2/2 on $mux $flatten\dut.$procmux$1121. + dead port 1/2 on $mux $flatten\dut.$procmux$1119. + dead port 2/2 on $mux $flatten\dut.$procmux$1119. + dead port 1/4 on $pmux $flatten\dut.$procmux$1115. + dead port 2/4 on $pmux $flatten\dut.$procmux$1115. + dead port 3/4 on $pmux $flatten\dut.$procmux$1115. + dead port 4/4 on $pmux $flatten\dut.$procmux$1115. + dead port 1/2 on $mux $flatten\dut.$procmux$1113. + dead port 2/2 on $mux $flatten\dut.$procmux$1113. + dead port 1/2 on $mux $flatten\dut.$procmux$1110. + dead port 2/2 on $mux $flatten\dut.$procmux$1110. + dead port 1/2 on $mux $flatten\dut.$procmux$1108. + dead port 2/2 on $mux $flatten\dut.$procmux$1108. + dead port 1/2 on $mux $flatten\dut.$procmux$1105. + dead port 2/2 on $mux $flatten\dut.$procmux$1105. + dead port 1/2 on $mux $flatten\dut.$procmux$1102. + dead port 2/2 on $mux $flatten\dut.$procmux$1102. + dead port 1/2 on $mux $flatten\dut.$procmux$1094. + dead port 2/2 on $mux $flatten\dut.$procmux$1094. + dead port 1/2 on $mux $flatten\dut.$procmux$1091. + dead port 2/2 on $mux $flatten\dut.$procmux$1091. + dead port 1/3 on $pmux $flatten\dut.$procmux$1083. + dead port 2/3 on $pmux $flatten\dut.$procmux$1083. + dead port 3/3 on $pmux $flatten\dut.$procmux$1083. + dead port 1/2 on $mux $flatten\dut.$procmux$1081. + dead port 2/2 on $mux $flatten\dut.$procmux$1081. + dead port 1/4 on $pmux $flatten\dut.$procmux$1077. + dead port 2/4 on $pmux $flatten\dut.$procmux$1077. + dead port 3/4 on $pmux $flatten\dut.$procmux$1077. + dead port 4/4 on $pmux $flatten\dut.$procmux$1077. + dead port 1/2 on $mux $flatten\dut.$procmux$1075. + dead port 2/2 on $mux $flatten\dut.$procmux$1075. + dead port 1/2 on $mux $flatten\dut.$procmux$1072. + dead port 2/2 on $mux $flatten\dut.$procmux$1072. + dead port 1/2 on $mux $flatten\dut.$procmux$1062. + dead port 2/2 on $mux $flatten\dut.$procmux$1062. + dead port 1/2 on $mux $flatten\dut.$procmux$1060. + dead port 2/2 on $mux $flatten\dut.$procmux$1060. + dead port 1/2 on $mux $flatten\dut.$procmux$1055. + dead port 2/2 on $mux $flatten\dut.$procmux$1055. + dead port 1/2 on $mux $flatten\dut.$procmux$1052. + dead port 2/2 on $mux $flatten\dut.$procmux$1052. + dead port 1/3 on $pmux $flatten\dut.$procmux$1049. + dead port 2/3 on $pmux $flatten\dut.$procmux$1049. + dead port 3/3 on $pmux $flatten\dut.$procmux$1049. + dead port 1/2 on $mux $flatten\dut.$procmux$1041. + dead port 2/2 on $mux $flatten\dut.$procmux$1041. + dead port 1/2 on $mux $flatten\dut.$procmux$1037. + dead port 2/2 on $mux $flatten\dut.$procmux$1037. + dead port 1/2 on $mux $flatten\dut.$procmux$551. + dead port 2/2 on $mux $flatten\dut.$procmux$551. + dead port 1/4 on $pmux $flatten\dut.$procmux$1034. + dead port 2/4 on $pmux $flatten\dut.$procmux$1034. + dead port 3/4 on $pmux $flatten\dut.$procmux$1034. + dead port 4/4 on $pmux $flatten\dut.$procmux$1034. + dead port 1/2 on $mux $flatten\dut.$procmux$1013. + dead port 2/2 on $mux $flatten\dut.$procmux$1013. + dead port 1/2 on $mux $flatten\dut.$procmux$549. + dead port 2/2 on $mux $flatten\dut.$procmux$549. + dead port 1/2 on $mux $flatten\dut.$procmux$1011. + dead port 2/2 on $mux $flatten\dut.$procmux$1011. + dead port 1/2 on $mux $flatten\dut.$procmux$1009. + dead port 2/2 on $mux $flatten\dut.$procmux$1009. + dead port 1/2 on $mux $flatten\dut.$procmux$994. + dead port 2/2 on $mux $flatten\dut.$procmux$994. + dead port 1/2 on $mux $flatten\dut.$procmux$992. + dead port 2/2 on $mux $flatten\dut.$procmux$992. + dead port 1/2 on $mux $flatten\dut.$procmux$980. + dead port 2/2 on $mux $flatten\dut.$procmux$980. + dead port 1/2 on $mux $flatten\dut.$procmux$978. + dead port 2/2 on $mux $flatten\dut.$procmux$978. + dead port 1/2 on $mux $flatten\dut.$procmux$976. + dead port 2/2 on $mux $flatten\dut.$procmux$976. + dead port 1/2 on $mux $flatten\dut.$procmux$965. + dead port 2/2 on $mux $flatten\dut.$procmux$965. + dead port 1/2 on $mux $flatten\dut.$procmux$996. + dead port 2/2 on $mux $flatten\dut.$procmux$996. + dead port 1/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$170. + dead port 2/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$170. + dead port 1/2 on $mux $flatten\dut.$procmux$962. + dead port 2/2 on $mux $flatten\dut.$procmux$962. + dead port 1/4 on $pmux $flatten\dut.$procmux$958. + dead port 2/4 on $pmux $flatten\dut.$procmux$958. + dead port 3/4 on $pmux $flatten\dut.$procmux$958. + dead port 4/4 on $pmux $flatten\dut.$procmux$958. + dead port 1/2 on $mux $flatten\dut.$procmux$956. + dead port 2/2 on $mux $flatten\dut.$procmux$956. + dead port 1/2 on $mux $flatten\dut.$procmux$942. + dead port 2/2 on $mux $flatten\dut.$procmux$942. + dead port 1/2 on $mux $flatten\dut.$procmux$777. + dead port 2/2 on $mux $flatten\dut.$procmux$777. + dead port 1/3 on $pmux $flatten\dut.$procmux$646. + dead port 2/3 on $pmux $flatten\dut.$procmux$646. + dead port 3/3 on $pmux $flatten\dut.$procmux$646. + dead port 1/2 on $mux $flatten\dut.$procmux$553. + dead port 2/2 on $mux $flatten\dut.$procmux$553. +Removed 215 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Removed a total of 0 cells. + +5.6. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 8 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 9 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 10 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 11 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 12 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 13 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 14 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 15 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 16 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 17 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 18 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 19 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 20 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 21 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 22 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 23 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 24 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 25 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 26 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 27 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 28 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 29 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 30 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 31 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 0 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 1 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 2 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 3 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 4 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 5 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 6 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 7 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 8 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 9 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 10 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 11 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 12 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 13 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 14 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 15 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 16 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 17 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 18 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 19 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 20 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 21 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 22 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 23 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 24 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 25 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 26 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 27 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 28 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 29 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 30 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 31 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 8 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 9 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 10 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 11 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 12 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 13 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 14 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 15 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1255 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1255 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1255 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1252 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 8 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 9 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 10 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 11 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 12 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 13 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 14 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 15 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 16 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 17 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 18 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 19 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 20 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 21 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 22 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 23 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 24 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 25 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 26 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 27 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 28 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 29 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 30 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 31 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 32 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 33 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 34 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 35 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 36 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 37 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 38 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 39 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 40 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 41 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 42 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 43 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 44 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 45 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 46 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 47 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 48 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 49 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 50 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 51 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 52 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 53 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 54 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 55 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 56 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 57 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 58 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 59 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 60 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 61 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 62 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 63 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 64 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 65 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 66 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 67 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 68 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 69 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 70 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 71 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 72 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 73 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 74 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 75 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 76 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 77 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 78 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 79 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 80 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 81 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 82 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 83 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 84 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 85 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 86 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 87 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 88 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 89 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 90 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 91 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 92 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 93 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 94 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 95 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 96 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 97 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 98 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 99 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 100 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 101 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 102 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 103 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 104 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 105 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 106 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 107 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 108 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 109 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 110 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 111 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 112 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 113 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 114 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 115 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 116 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 117 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 118 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 119 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 120 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 121 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 122 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 123 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 124 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 125 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 126 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 127 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 128 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 129 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 130 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 131 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 132 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 133 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 134 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 135 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 136 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 137 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 138 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 139 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 140 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 141 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 142 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 143 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 144 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 145 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 146 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 147 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 148 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 149 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 150 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 151 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 152 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 153 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 154 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 155 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 156 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 157 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 158 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 159 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 160 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 161 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 162 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 163 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 164 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 165 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 166 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 167 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 168 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 169 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 170 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 171 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 172 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 173 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 174 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 175 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 176 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 177 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 178 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 179 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 180 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 181 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 182 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 183 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 184 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 185 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 186 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 187 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 188 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 189 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 190 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 191 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 192 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 193 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 194 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 195 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 196 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 197 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 198 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 199 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 200 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 201 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 202 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 203 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 204 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 205 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 206 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 207 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 208 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 209 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 210 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 211 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 212 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 213 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 214 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 215 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 216 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 217 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 218 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 219 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 220 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 221 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 222 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 223 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 224 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 225 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 226 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 227 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 228 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 229 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 230 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 231 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 232 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 233 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 234 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 235 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 236 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 237 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 238 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 239 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 240 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 241 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 242 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 243 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 244 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 245 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 246 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 247 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 248 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 249 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 250 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 251 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 252 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 253 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 254 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 255 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 256 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 257 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 258 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 259 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 260 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 261 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 262 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 263 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 264 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 265 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 266 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 267 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 268 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 269 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 270 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 271 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 272 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 273 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 274 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 275 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 276 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 277 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 278 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 279 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 280 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 281 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 282 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 283 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 284 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 285 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 286 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 287 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 288 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 289 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 290 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 291 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 292 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 293 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 294 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 295 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 296 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 297 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 298 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 299 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 300 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 301 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 302 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 303 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 304 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 305 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 306 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 307 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 308 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 309 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 310 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 311 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 312 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 313 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 314 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 315 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 316 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 317 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 318 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 319 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 320 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 321 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 322 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 323 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 324 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 325 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 326 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 327 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 328 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 329 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 330 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 331 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 332 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 333 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 334 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 335 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 336 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 337 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 338 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 339 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 340 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 341 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 342 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 343 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 344 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 345 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 346 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 347 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 348 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 349 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 350 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 351 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 352 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 353 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 354 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 355 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 356 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 357 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 358 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 359 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 360 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 361 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 362 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 363 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 364 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 365 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 366 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 367 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 368 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 369 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 370 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 371 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 372 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 373 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 374 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 375 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 376 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 377 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 378 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 379 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 380 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 381 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 382 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 383 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 384 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 385 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 386 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 387 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 388 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 389 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 390 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 391 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 392 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 393 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 394 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 395 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 396 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 397 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 398 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 399 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 400 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 401 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 402 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 403 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 404 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 405 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 406 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 407 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 408 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 409 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 410 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 411 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 412 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 413 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 414 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 415 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 416 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 417 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 418 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 419 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 420 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 421 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 422 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 423 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 424 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 425 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 426 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 427 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 428 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 429 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 430 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 431 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 432 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 433 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 434 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 435 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 436 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 437 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 438 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 439 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 440 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 441 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 442 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 443 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 444 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 445 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 446 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 447 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 448 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 449 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 450 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 451 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 452 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 453 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 454 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 455 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 456 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 457 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 458 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 459 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 460 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 461 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 462 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 463 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 464 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 465 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 466 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 467 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 468 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 469 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 470 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 471 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 472 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 473 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 474 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 475 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 476 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 477 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 478 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 479 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 480 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 481 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 482 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 483 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 484 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 485 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 486 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 487 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 488 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 489 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 490 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 491 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 492 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 493 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 494 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 495 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 496 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 497 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 498 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 499 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 500 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 501 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 502 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 503 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 504 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 505 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 506 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 507 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 508 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 509 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 510 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 511 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 512 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 513 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 514 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 515 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 516 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 517 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 518 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 519 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 520 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 521 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 522 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 523 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 524 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 525 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 526 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 527 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 528 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 529 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 530 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 531 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 532 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 533 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 534 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 535 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 536 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 537 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 538 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 539 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 540 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 541 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 542 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 543 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 544 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 545 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 546 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 547 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 548 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 549 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 550 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 551 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 552 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 553 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 554 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 555 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 556 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 557 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 558 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 559 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 560 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 561 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 562 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 563 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 564 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 565 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 566 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 567 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 568 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 569 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 570 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 571 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 572 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 573 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 574 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 575 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 576 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 577 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 578 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 579 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 580 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 581 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 582 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 583 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 584 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 585 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 586 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 587 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 588 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 589 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 590 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 591 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 592 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 593 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 594 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 595 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 596 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 597 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 598 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 599 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 600 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 601 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 602 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 603 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 604 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 605 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 606 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 607 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 608 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 609 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 610 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 611 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 612 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 613 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 614 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 615 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 616 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 617 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 618 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 619 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 620 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 621 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 622 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 623 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 624 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 625 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 626 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 627 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 628 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 629 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 630 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 631 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 632 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 633 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 634 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 635 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 636 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 637 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 638 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 639 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 640 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 641 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 642 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 643 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 644 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 645 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 646 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 647 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 648 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 649 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 650 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 651 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 652 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 653 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 654 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 655 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 656 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 657 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 658 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 659 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 660 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 661 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 662 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 663 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 664 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 665 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 666 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 667 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 668 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 669 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 670 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 671 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 672 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 673 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 674 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 675 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 676 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 677 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 678 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 679 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 680 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 681 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 682 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 683 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 684 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 685 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 686 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 687 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 688 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 689 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 690 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 691 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 692 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 693 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 694 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 695 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 696 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 697 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 698 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 699 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 700 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 701 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 702 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 703 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 704 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 705 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 706 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 707 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 708 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 709 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 710 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 711 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 712 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 713 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 714 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 715 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 716 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 717 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 718 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 719 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 720 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 721 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 722 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 723 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 724 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 725 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 726 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 727 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 728 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 729 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 730 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 731 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 732 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 733 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 734 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 735 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 736 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 737 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 738 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 739 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 740 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 741 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 742 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 743 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 744 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 745 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 746 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 747 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 748 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 749 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 750 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 751 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 752 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 753 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 754 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 755 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 756 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 757 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 758 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 759 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 760 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 761 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 762 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 763 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 764 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 765 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 766 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 767 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 768 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 769 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 770 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 771 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 772 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 773 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 774 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 775 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 776 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 777 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 778 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 779 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 780 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 781 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 782 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 783 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 784 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 785 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 786 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 787 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 788 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 789 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 790 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 791 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 792 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 793 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 794 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 795 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 796 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 797 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 798 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 799 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 800 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 801 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 802 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 803 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 804 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 805 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 806 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 807 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 808 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 809 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 810 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 811 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 812 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 813 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 814 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 815 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 816 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 817 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 818 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 819 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 820 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 821 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 822 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 823 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 824 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 825 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 826 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 827 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 828 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 829 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 830 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 831 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 832 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 833 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 834 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 835 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 836 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 837 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 838 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 839 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 840 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 841 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 842 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 843 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 844 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 845 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 846 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 847 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 848 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 849 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 850 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 851 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 852 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 853 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 854 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 855 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 856 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 857 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 858 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 859 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 860 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 861 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 862 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 863 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 864 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 865 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 866 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 867 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 868 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 869 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 870 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 871 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 872 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 873 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 874 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 875 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 876 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 877 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 878 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 879 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 880 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 881 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 882 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 883 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 884 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 885 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 886 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 887 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 888 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 889 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 890 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 891 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 892 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 893 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 894 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 895 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 896 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 897 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 898 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 899 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 900 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 901 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 902 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 903 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 904 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 905 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 906 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 907 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 908 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 909 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 910 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 911 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 912 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 913 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 914 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 915 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 916 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 917 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 918 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 919 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 920 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 921 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 922 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 923 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 924 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 925 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 926 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 927 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 928 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 929 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 930 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 931 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 932 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 933 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 934 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 935 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 936 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 937 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 938 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 939 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 940 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 941 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 942 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 943 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 944 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 945 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 946 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 947 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 948 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 949 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 950 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 951 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 952 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 953 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 954 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 955 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 956 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 957 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 958 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 959 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 960 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 961 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 962 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 963 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 964 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 965 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 966 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 967 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 968 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 969 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 970 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 971 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 972 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 973 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 974 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 975 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 976 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 977 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 978 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 979 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 980 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 981 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 982 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 983 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 984 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 985 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 986 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 987 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 988 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 989 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 990 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 991 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 992 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 993 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 994 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 995 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 996 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 997 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 998 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 999 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1000 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1001 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1002 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1003 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1004 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1005 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1006 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1007 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1008 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1009 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1010 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1011 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1012 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1013 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1014 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1015 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1016 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1017 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1018 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1019 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1020 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1021 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1022 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1023 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1024 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1025 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1026 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1027 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1028 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1029 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1030 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1031 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1032 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1033 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1034 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1035 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1036 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1037 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1038 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1039 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1040 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1041 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1042 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1043 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1044 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1045 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1046 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1047 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1048 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1049 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1050 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1051 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1052 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1053 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1054 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1055 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1056 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1057 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1058 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1059 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1060 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1061 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1062 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1063 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1064 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1065 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1066 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1067 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1068 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1069 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1070 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1071 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1072 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1073 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1074 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1075 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1076 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1077 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1078 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1079 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1080 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1081 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1082 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1083 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1084 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1085 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1086 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1087 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1088 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1089 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1090 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1091 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1092 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1093 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1094 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1095 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1096 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1097 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1098 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1099 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1100 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1101 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1102 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1103 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1104 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1105 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1106 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1107 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1108 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1109 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1110 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1111 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1112 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1113 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1114 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1115 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1116 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1117 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1118 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1119 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1120 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1121 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1122 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1123 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1124 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1125 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1126 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1127 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1128 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1129 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1130 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1131 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1132 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1133 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1134 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1135 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1136 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1137 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1138 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1139 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1140 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1141 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1142 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1143 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1144 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1145 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1146 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1147 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1148 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1149 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1150 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1151 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1152 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1153 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1154 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1155 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1156 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1157 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1158 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1159 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1160 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1161 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1162 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1163 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1164 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1165 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1166 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1167 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1168 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1169 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1170 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1171 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1172 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1173 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1174 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1175 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1176 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1177 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1178 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1179 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1180 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1181 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1182 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1183 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1184 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1185 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1186 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1187 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1188 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1189 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1190 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1191 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1192 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1193 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1194 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1195 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1196 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1197 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1198 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1199 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1200 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1201 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1202 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1203 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1204 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1205 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1206 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1207 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1208 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1209 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1210 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1211 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1212 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1213 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1214 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1215 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1216 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1217 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1218 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1219 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1220 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1221 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1222 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1223 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1224 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1225 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1226 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1227 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1228 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1229 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1230 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1231 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1232 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1233 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1234 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1235 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1236 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1237 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1238 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1239 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1240 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1241 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1242 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1243 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1244 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1245 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1246 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1247 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1248 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1249 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1250 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1251 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1252 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1253 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1254 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1255 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1256 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1257 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1258 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1259 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1260 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1261 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1262 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1263 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1264 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1265 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1266 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1267 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1268 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1269 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1270 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1271 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1272 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1273 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1274 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1275 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1276 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1277 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1278 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1279 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1280 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1281 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1282 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1283 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1284 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1285 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1286 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1287 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1288 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1289 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1290 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1291 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1292 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1293 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1294 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1295 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1296 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1297 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1298 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1299 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1300 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1301 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1302 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1303 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1304 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1305 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1306 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1307 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1308 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1309 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1310 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1311 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1312 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1313 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1314 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1315 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1316 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1317 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1318 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1319 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1320 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1321 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1322 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1323 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1324 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1325 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1326 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1327 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1328 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1329 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1330 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1331 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1332 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1333 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1334 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1335 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1336 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1337 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1338 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1339 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1340 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1341 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1342 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1343 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1344 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1345 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1346 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1347 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1348 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1349 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1350 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1351 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1352 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1353 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1354 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1355 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1356 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1357 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1358 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1359 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1360 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1361 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1362 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1363 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1364 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1365 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1366 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1367 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1368 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1369 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1370 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1371 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1372 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1373 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1374 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1375 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1376 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1377 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1378 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1379 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1380 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1381 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1382 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1383 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1384 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1385 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1386 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1387 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1388 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1389 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1390 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1391 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1392 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1393 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1394 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1395 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1396 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1397 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1398 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1399 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1400 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1401 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1402 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1403 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1404 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1405 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1406 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1407 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1408 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1409 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1410 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1411 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1412 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1413 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1414 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1415 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1416 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1417 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1418 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1419 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1420 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1421 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1422 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1423 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1424 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1425 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1426 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1427 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1428 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1429 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1430 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1431 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1432 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1433 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1434 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1435 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1436 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1437 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1438 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1439 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1440 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1441 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1442 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1443 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1444 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1445 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1446 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1447 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1448 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1449 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1450 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1451 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1452 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1453 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1454 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1455 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1456 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1457 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1458 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1459 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1460 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1461 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1462 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1463 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1464 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1465 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1466 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1467 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1468 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1469 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1470 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1471 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1472 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1473 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1474 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1475 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1476 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1477 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1478 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1479 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1480 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1481 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1482 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1483 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1484 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1485 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1486 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1487 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1488 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1489 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1490 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1491 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1492 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1493 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1494 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1495 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1496 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1497 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1498 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1499 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1500 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1501 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1502 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1503 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1504 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1505 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1506 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1507 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1508 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1509 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1510 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1511 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1512 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1513 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1514 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1515 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1516 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1517 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1518 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1519 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1520 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1521 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1522 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1523 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1524 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1525 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1526 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1527 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1528 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1529 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1530 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1531 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1532 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1533 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1534 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1535 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1536 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1537 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1538 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1539 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1540 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1541 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1542 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1543 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1544 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1545 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1546 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1547 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1548 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1549 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1550 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1551 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1552 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1553 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1554 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1555 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1556 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1557 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1558 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1559 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1560 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1561 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1562 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1563 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1564 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1565 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1566 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1567 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1568 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1569 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1570 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1571 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1572 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1573 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1574 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1575 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1576 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1577 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1578 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1579 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1580 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1581 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1582 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1583 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1584 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1585 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1586 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1587 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1588 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1589 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1590 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1591 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1592 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1593 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1594 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1595 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1596 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1597 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1598 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1599 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1600 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1601 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1602 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1603 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1604 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1605 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1606 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1607 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1608 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1609 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1610 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1611 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1612 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1613 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1614 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1615 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1616 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1617 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1618 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1619 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1620 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1621 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1622 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1623 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1624 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1625 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1626 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1627 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1628 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1629 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1630 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1631 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1632 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1633 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1634 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1635 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1636 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1637 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1638 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1639 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1640 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1641 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1642 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1643 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1644 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1645 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1646 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1647 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1648 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1649 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1650 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1651 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1652 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1653 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1654 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1655 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1656 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1657 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1658 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1659 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1660 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1661 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1662 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1663 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1664 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1665 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1666 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1667 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1668 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1669 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1670 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1671 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1672 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1673 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1674 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1675 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1676 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1677 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1678 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1679 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1680 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1681 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1682 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1683 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1684 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1685 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1686 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1687 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1688 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1689 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1690 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1691 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1692 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1693 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1694 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1695 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1696 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1697 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1698 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1699 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1700 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1701 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1702 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1703 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1704 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1705 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1706 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1707 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1708 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1709 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1710 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1711 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1712 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1713 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1714 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1715 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1716 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1717 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1718 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1719 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1720 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1721 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1722 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1723 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1724 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1725 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1726 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1727 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1728 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1729 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1730 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1731 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1732 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1733 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1734 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1735 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1736 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1737 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1738 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1739 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1740 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1741 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1742 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1743 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1744 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1745 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1746 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1747 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1748 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1749 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1750 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1751 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1752 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1753 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1754 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1755 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1756 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1757 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1758 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1759 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1760 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1761 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1762 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1763 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1764 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1765 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1766 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1767 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1768 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1769 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1770 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1771 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1772 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1773 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1774 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1775 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1776 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1777 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1778 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1779 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1780 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1781 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1782 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1783 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1784 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1785 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1786 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1787 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1788 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1789 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1790 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1791 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1792 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1793 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1794 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1795 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1796 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1797 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1798 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1799 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1800 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1801 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1802 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1803 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1804 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1805 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1806 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1807 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1808 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1809 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1810 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1811 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1812 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1813 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1814 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1815 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1816 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1817 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1818 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1819 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1820 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1821 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1822 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1823 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1824 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1825 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1826 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1827 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1828 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1829 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1830 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1831 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1832 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1833 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1834 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1835 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1836 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1837 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1838 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1839 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1840 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1841 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1842 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1843 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1844 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1845 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1846 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1847 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1848 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1849 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1850 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1851 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1852 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1853 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1854 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1855 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1856 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1857 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1858 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1859 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1860 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1861 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1862 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1863 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1864 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1865 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1866 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1867 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1868 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1869 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1870 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1871 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1872 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1873 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1874 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1875 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1876 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1877 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1878 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1879 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1880 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1881 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1882 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1883 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1884 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1885 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1886 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1887 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1888 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1889 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1890 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1891 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1892 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1893 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1894 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1895 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1896 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1897 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1898 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1899 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1900 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1901 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1902 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1903 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1904 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1905 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1906 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1907 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1908 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1909 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1910 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1911 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1912 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1913 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1914 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1915 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1916 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1917 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1918 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1919 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1920 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1921 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1922 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1923 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1924 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1925 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1926 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1927 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1928 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1929 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1930 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1931 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1932 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1933 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1934 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1935 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1936 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1937 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1938 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1939 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1940 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1941 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1942 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1943 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1944 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1945 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1946 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1947 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1948 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1949 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1950 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1951 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1952 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1953 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1954 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1955 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1956 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1957 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1958 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1959 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1960 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1961 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1962 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1963 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1964 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1965 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1966 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1967 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1968 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1969 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1970 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1971 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1972 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1973 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1974 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1975 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1976 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1977 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1978 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1979 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1980 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1981 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1982 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1983 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1984 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1985 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1986 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1987 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1988 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1989 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1990 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1991 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1992 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1993 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1994 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1995 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1996 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1997 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1998 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1999 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2000 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2001 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2002 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2003 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2004 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2005 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2006 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2007 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2008 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2009 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2010 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2011 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2012 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2013 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2014 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2015 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2016 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2017 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2018 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2019 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2020 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2021 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2022 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2023 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2024 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2025 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2026 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2027 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2028 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2029 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2030 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2031 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2032 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2033 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2034 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2035 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2036 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2037 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2038 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2039 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2040 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2041 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2042 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2043 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2044 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2045 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2046 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2047 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. + +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Removed 67 unused cells and 218 unused wires. + + +5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + + +5.9. Rerunning OPT passes. (Maybe there is more to do..) + +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. +Performed a total of 0 changes. + +5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. + +Removed a total of 6 cells. + +5.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 1-bit at position 0 on $procdff$1240 ($dff) from module lsc1_packet_frontend_arch_reset_idle. + +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Removed 0 unused cells and 21 unused wires. + + +5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + +5.16. Rerunning OPT passes. (Maybe there is more to do..) + +5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. +Performed a total of 0 changes. + +5.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Removed a total of 0 cells. + +5.20. Executing OPT_DFF pass (perform DFF optimizations). + +5.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. + +5.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + +5.23. Finished OPT passes. (There is nothing left to do.) + +6. Executing SAT pass (solving SAT problems in the circuit). + +Setting up time step 1: +Final constraint equation: { } = { } +Imported 4 cells to SAT database. +Import constraint from assume cell: \clk when 1'1. +Import set-constraint from init attribute: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN = 1'0 +Final init constraint equation: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN = 1'0 +Import proof for assert: 1'1 when $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN. + +Setting up time step 2: +Final constraint equation: { } = { } +Imported 4 cells to SAT database. +Import constraint from assume cell: \clk when 1'1. +Import proof for assert: 1'1 when $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN. + +Setting up time step 3: +Final constraint equation: { } = { } +Imported 4 cells to SAT database. +Import constraint from assume cell: \clk when 1'1. +Import proof for assert: 1'1 when $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN. + +Solving problem with 18 variables and 43 clauses.. +SAT proof finished - no model found: SUCCESS! + + /$$$$$$ /$$$$$$$$ /$$$$$$$ + /$$__ $$ | $$_____/ | $$__ $$ + | $$ \ $$ | $$ | $$ \ $$ + | $$ | $$ | $$$$$ | $$ | $$ + | $$ | $$ | $$__/ | $$ | $$ + | $$/$$ $$ | $$ | $$ | $$ + | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ + \____ $$$|__/|________/|__/|_______/|__/ + \__/ + +End of script. Logfile hash: ed77109f73, CPU: user 4.52s system 0.05s, MEM: 70.73 MB peak +Yosys 0.33 (git sha1 2584903a060) +Time spent: 58% 1x proc_mux (2 sec), 11% 2x check (0 sec), ... diff --git a/results/arch-state-omissions-20260728/interface-coverage.log b/results/arch-state-omissions-20260728/interface-coverage.log new file mode 100644 index 0000000..ba0d6a1 --- /dev/null +++ b/results/arch-state-omissions-20260728/interface-coverage.log @@ -0,0 +1 @@ +arch-state map: 94 fields; widths, 91 registered elements, output reconstruction, and mutations covered diff --git a/results/arch-state-omissions-20260728/mutation.log b/results/arch-state-omissions-20260728/mutation.log new file mode 100644 index 0000000..49bc124 --- /dev/null +++ b/results/arch-state-omissions-20260728/mutation.log @@ -0,0 +1,3 @@ +make: Entering directory '/workspaces/mission-cbe073d0/work/pr30/test/packet_frontend' +PASS: BUSY, SET value, RETIRE ID, ABORT, length-order, and profile mutations were detected +make: Leaving directory '/workspaces/mission-cbe073d0/work/pr30/test/packet_frontend' diff --git a/results/arch-state-omissions-20260728/root-checksums.log b/results/arch-state-omissions-20260728/root-checksums.log new file mode 100644 index 0000000..d123269 --- /dev/null +++ b/results/arch-state-omissions-20260728/root-checksums.log @@ -0,0 +1,431 @@ +./.github/workflows/ci.yml: OK +./.gitignore: OK +./LICENSE: OK +./MANIFEST.md: OK +./Makefile: OK +./README.md: OK +./RESULTS.md: OK +./VALIDATION.txt: OK +./VERSION: OK +./asic_core/README.md: OK +./asic_core/rtl/gf128_mul_bitstream.sv: OK +./asic_core/rtl/gf2n_mul_bitstream.sv: OK +./asic_core/rtl/lean_silicon_lsc1.sv: OK +./asic_core/rtl/lean_silicon_lsc1_mincore.sv: OK +./asic_core/rtl/leanvm_b_stream_alu.sv: OK +./asic_core/rtl/lsc1_field_encoder.sv: OK +./asic_core/rtl/lsc1_gf128_mul.sv: OK +./asic_core/rtl/lsc1_packet_frontend.sv: OK +./asic_core/rtl/lsc1_packet_rx.sv: OK +./asic_core/rtl/lsc1_packet_tx.sv: OK +./asic_core/rtl/lsc1_stream_adapter.sv: OK +./conformance/README.md: OK +./conformance/corpus-v1.json: OK +./conformance/rust/frozen_adapter.rs: OK +./conformance/schema-v1.json: OK +./docs/ARCHITECTURE.md: OK +./docs/BLAKE3_EXTERNAL_SERVICE.md: OK +./docs/DECISIONS.md: OK +./docs/FULL_CORE.md: OK +./docs/FULL_CORE_PROTOCOL.md: OK +./docs/HOST_RUNTIME.md: OK +./docs/LSC1_PROTOCOL.md: OK +./docs/LSC1_TRANSACTION_PROTOCOL.md: OK +./docs/M0_MANAGER.md: OK +./docs/M2_CONTROLLER.md: OK +./docs/MINCORE_UART_HOST.md: OK +./docs/OPTIMALITY.md: OK +./docs/PROOF_BOUNDARIES.md: OK +./docs/PROTOCOL.md: OK +./docs/PROTOCOL_BYTE_CYCLE_AUDIT.md: OK +./docs/ROADMAP.md: OK +./docs/SEMANTICS.md: OK +./docs/SEMANTIC_DIFFERENCES.md: OK +./docs/SOURCE_AUDIT.md: OK +./docs/STATUS.md: OK +./docs/TAPEOUT.md: OK +./docs/THEOREM_INVENTORY.md: OK +./docs/ULX3S_SMOKE_AND_UART.md: OK +./docs/USE_CASES.md: OK +./docs/VALIDATION.md: OK +./docs/assets/lean-silicon-logo.png: OK +./docs/semantics/reference/README.md: OK +./docs/semantics/reference/oracle.py: OK +./docs/semantics/reference/vectors.json: OK +./docs/upstream-clarifications/README.md: OK +./formal/ARCH_STATE.md: OK +./formal/README.md: OK +./formal/gf128_serialize.sby: OK +./formal/gf128_serialize_formal.sv: OK +./formal/gf8_mul.sby: OK +./formal/gf8_mul_bounded.ys: OK +./formal/gf8_mul_bounded_boolector.sby: OK +./formal/gf8_mul_depth22_z3.sby: OK +./formal/gf8_mul_formal.sv: OK +./formal/lsc1_packet_frontend_arch_reset_idle.sv: OK +./formal/lsc1_packet_frontend_arch_reset_idle.ys: OK +./formal/lsc1_packet_frontend_arch_state_map.json: OK +./formal/lsc1_packet_frontend_release_equiv.ys: OK +./formal/stream_alu_mul_pulse.sby: OK +./formal/stream_alu_mul_pulse_formal.sv: OK +./fpga/ulx3s/Makefile: OK +./fpga/ulx3s/build_packet_uart.sh: OK +./fpga/ulx3s/build_smoke.sh: OK +./fpga/ulx3s/build_uart.sh: OK +./fpga/ulx3s/smoke.config: OK +./fpga/ulx3s/smoke.ys: OK +./fpga/ulx3s/smoke_top.sv: OK +./fpga/ulx3s/uart_bridge.sv: OK +./fpga/ulx3s/uart_rx.sv: OK +./fpga/ulx3s/uart_tx.sv: OK +./fpga/ulx3s/ulx3s_packet_top.sv: OK +./fpga/ulx3s/ulx3s_top.sv: OK +./fpga/ulx3s/ulx3s_v318_smoke.lpf: OK +./fpga_harness/BOUNDARY.md: OK +./fpga_harness/BUILD_PLAN.md: OK +./fpga_harness/INVENTORY.md: OK +./fpga_harness/README.md: OK +./fpga_harness/board_detect.py: OK +./fpga_harness/boundary_check.py: OK +./fpga_harness/fixtures/ulx3s_full_visibility.json: OK +./fpga_harness/hardware_preflight.py: OK +./fpga_harness/host/__init__.py: OK +./fpga_harness/host/lsc1_packet_uart.py: OK +./fpga_harness/host/mincore_uart.py: OK +./fpga_harness/rtl/lean_silicon_lsc1_pins.sv: OK +./fpga_harness/test_artefact_provenance.py: OK +./fpga_harness/test_atomic_publish.py: OK +./fpga_harness/test_board_detect.py: OK +./fpga_harness/test_boundary_check.py: OK +./fpga_harness/test_hardware_preflight.py: OK +./fpga_harness/test_portable_build_support.py: OK +./fpga_harness/test_ulx3s_uart.py: OK +./fpga_harness/tests/__init__.py: OK +./fpga_harness/tests/host_uart/__init__.py: OK +./fpga_harness/tests/host_uart/test_lsc1_packet_uart.py: OK +./fpga_harness/tests/host_uart/test_mincore_uart.py: OK +./fpga_harness/ulx3s_uart.py: OK +./host/README.md: OK +./host/__init__.py: OK +./host/blake3_service.py: OK +./host/errors.py: OK +./host/fixtures/assert_set_xor_mul.program.json: OK +./host/fixtures/assert_set_xor_mul.zkdsl: OK +./host/lean_compiler_adapter.py: OK +./host/memory.py: OK +./host/protocol.py: OK +./host/runtime.py: OK +./info.yaml: OK +./lean/LeanVMBMinCore/Address.lean: OK +./lean/LeanVMBMinCore/ByteSerialization.lean: OK +./lean/LeanVMBMinCore/CheckedIndex.lean: OK +./lean/LeanVMBMinCore/ControlPrimitives.lean: OK +./lean/LeanVMBMinCore/Deref.lean: OK +./lean/LeanVMBMinCore/GF8.lean: OK +./lean/LeanVMBMinCore/GHASH128.lean: OK +./lean/LeanVMBMinCore/ISA.lean: OK +./lean/LeanVMBMinCore/Memory.lean: OK +./lean/LeanVMBMinCore/Optimality.lean: OK +./lean/LeanVMBMinCore/Packet.lean: OK +./lean/LeanVMBMinCore/Stream.lean: OK +./lean/LeanVMBMinCore/Transaction.lean: OK +./lean/LeanVMBMinCore.lean: OK +./lean/README.md: OK +./lean/lake-manifest.json: OK +./lean/lakefile.lean: OK +./lean/lean-toolchain: OK +./planning/OWNERSHIP.md: OK +./planning/milestones.yaml: OK +./requirements.txt: OK +./results/arch-state-20260728/README.md: OK +./results/arch-state-20260728/differential.log: OK +./results/arch-state-20260728/interface-coverage.log: OK +./results/arch-state-20260728/mutation.log: OK +./results/arch-state-20260728/reset-idle.log: OK +./results/arch-state-20260728/rtl.log: OK +./results/arch-state-20260728/versions-and-inputs.log: OK +./results/arch-state-omissions-20260728/README.md: OK +./results/arch-state-omissions-20260728/differential.log: OK +./results/arch-state-omissions-20260728/forbidden-token-scan.log: OK +./results/arch-state-omissions-20260728/formal-reset.log: OK +./results/arch-state-omissions-20260728/interface-coverage.log: OK +./results/arch-state-omissions-20260728/mutation.log: OK +./results/arch-state-omissions-20260728/rtl.log: OK +./results/arch-state-omissions-20260728/versions.log: OK +./results/b2-capability-contract-20260728/README.md: OK +./results/b2-capability-contract-20260728/blake3_official.command: OK +./results/b2-capability-contract-20260728/blake3_official.log: OK +./results/b2-capability-contract-20260728/blake3_official.status: OK +./results/b2-capability-contract-20260728/equivalence.command: OK +./results/b2-capability-contract-20260728/equivalence.log: OK +./results/b2-capability-contract-20260728/equivalence.status: OK +./results/b2-capability-contract-20260728/equivalence_flattened.command: OK +./results/b2-capability-contract-20260728/equivalence_flattened.log: OK +./results/b2-capability-contract-20260728/equivalence_flattened.status: OK +./results/b2-capability-contract-20260728/equivalence_retry.command: OK +./results/b2-capability-contract-20260728/equivalence_retry.log: OK +./results/b2-capability-contract-20260728/equivalence_retry.status: OK +./results/b2-capability-contract-20260728/lsc1_packet_frontend.netlist.v: OK +./results/b2-capability-contract-20260728/metadata.txt: OK +./results/b2-capability-contract-20260728/model.command: OK +./results/b2-capability-contract-20260728/model.log: OK +./results/b2-capability-contract-20260728/model.status: OK +./results/b2-capability-contract-20260728/model_final.command: OK +./results/b2-capability-contract-20260728/model_final.log: OK +./results/b2-capability-contract-20260728/model_final.status: OK +./results/b2-capability-contract-20260728/mutation.command: OK +./results/b2-capability-contract-20260728/mutation.log: OK +./results/b2-capability-contract-20260728/mutation.status: OK +./results/b2-capability-contract-20260728/mutation_final.command: OK +./results/b2-capability-contract-20260728/mutation_final.log: OK +./results/b2-capability-contract-20260728/mutation_final.status: OK +./results/b2-capability-contract-20260728/netlist.command: OK +./results/b2-capability-contract-20260728/netlist.log: OK +./results/b2-capability-contract-20260728/netlist.status: OK +./results/b2-capability-contract-20260728/netlist_900.command: OK +./results/b2-capability-contract-20260728/netlist_900.log: OK +./results/b2-capability-contract-20260728/netlist_900.status: OK +./results/b2-capability-contract-20260728/python_full.command: OK +./results/b2-capability-contract-20260728/python_full.log: OK +./results/b2-capability-contract-20260728/python_full.status: OK +./results/b2-capability-contract-20260728/python_full_final.command: OK +./results/b2-capability-contract-20260728/python_full_final.log: OK +./results/b2-capability-contract-20260728/python_full_final.status: OK +./results/b2-capability-contract-20260728/rtl.command: OK +./results/b2-capability-contract-20260728/rtl.log: OK +./results/b2-capability-contract-20260728/rtl.status: OK +./results/b2-capability-contract-20260728/rtl_final.command: OK +./results/b2-capability-contract-20260728/rtl_final.log: OK +./results/b2-capability-contract-20260728/rtl_final.status: OK +./results/b2-capability-contract-20260728/run.sh: OK +./results/fpga-harness-inventory-20260725/README.md: OK +./results/fpga-harness-inventory-20260725/fpga-boundary.log: OK +./results/fpga-harness-inventory-20260725/fpga-boundary.status: OK +./results/fpga-harness-inventory-20260725/fpga-detect-mock-full.log: OK +./results/fpga-harness-inventory-20260725/fpga-detect-mock-full.status: OK +./results/fpga-harness-inventory-20260725/fpga-detect-real.log: OK +./results/fpga-harness-inventory-20260725/fpga-detect-real.status: OK +./results/fpga-harness-inventory-20260725/fpga-detect-require-datapath.log: OK +./results/fpga-harness-inventory-20260725/fpga-detect-require-datapath.status: OK +./results/fpga-harness-inventory-20260725/fpga-harness-tests.log: OK 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OK +./results/frozen-oracle-evidence-20260725/scalar.log: OK +./results/host-runtime-lsc1-20260725/README.md: OK +./results/host-runtime-lsc1-20260725/comparison.json: OK +./results/host-runtime-lsc1-20260725/host-comparison-live.log: OK +./results/host-runtime-lsc1-20260725/host-comparison-live.status: OK +./results/host-runtime-lsc1-20260725/host-comparison-recorded.log: OK +./results/host-runtime-lsc1-20260725/host-comparison-recorded.status: OK +./results/host-runtime-lsc1-20260725/host-tests.log: OK +./results/host-runtime-lsc1-20260725/host-tests.status: OK +./results/host-runtime-lsc1-20260725/make-check.log: OK +./results/host-runtime-lsc1-20260725/make-check.status: OK +./results/host-runtime-lsc1-20260725/scalar-differential.log: OK +./results/host-runtime-lsc1-20260725/scalar-differential.status: OK +./results/host-runtime-lsc1-20260725/tested-source-head.txt: OK +./results/host-runtime-lsc1-20260725/toolchain.txt: OK +./results/lean-proof-foundations-20260725/README.md: OK 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OK +./results/m0-20260724T200511Z/yosys-formal.log: OK +./results/m0-20260724T200511Z/yosys-rtl.internal.log: OK +./results/m0-20260724T200511Z/yosys-rtl.log: OK +./results/m0-gf8-bounded-20260724T203611Z/baseline-original-cvc5-timeout.log: OK +./results/m0-gf8-bounded-20260724T203611Z/bounded-depth22-yosys-sat.log: OK +./results/m0-gf8-bounded-20260724T203611Z/depth22-boolector-incompatible.log: OK +./results/m0-gf8-bounded-20260724T203611Z/depth22-z3-timeout.log: OK +./results/m0-gf8-bounded-20260724T203611Z/formal-elaboration.log: OK +./results/m0-gf8-bounded-20260724T203611Z/run.sh: OK +./results/m0-gf8-bounded-20260724T203611Z/status.tsv: OK +./results/m0-gf8-bounded-20260724T203611Z/versions.log: OK +./results/m0-merge-20260724T210000Z/formal-sby.log: OK +./results/m0-merge-20260724T210000Z/lean-build.log: OK +./results/m0-merge-20260724T210000Z/make-check.log: OK +./results/m0-merge-20260724T210000Z/make-sim.log: OK +./results/m0-merge-20260724T210000Z/run.sh: OK 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OK +./results/protocol-byte-cycle-audit-20260725/followup-e0d4730/make-check.log: OK +./results/protocol-byte-cycle-audit-20260725/followup-e0d4730/make-formal.log: OK +./results/protocol-byte-cycle-audit-20260725/followup-e0d4730/make-lean.log: OK +./results/protocol-byte-cycle-audit-20260725/followup-e0d4730/make-sim.log: OK +./results/protocol-byte-cycle-audit-20260725/followup-e0d4730/yosys-lint-synth.log: OK +./results/protocol-byte-cycle-audit-20260725/make-check.log: OK +./results/protocol-byte-cycle-audit-20260725/make-check.status: OK +./results/protocol-byte-cycle-audit-20260725/make-formal.log: OK +./results/protocol-byte-cycle-audit-20260725/make-formal.status: OK +./results/protocol-byte-cycle-audit-20260725/make-lean.log: OK +./results/protocol-byte-cycle-audit-20260725/make-lean.status: OK +./results/protocol-byte-cycle-audit-20260725/make-sim.log: OK +./results/protocol-byte-cycle-audit-20260725/make-sim.status: OK +./results/protocol-byte-cycle-audit-20260725/tested-source-sha.txt: OK +./results/protocol-byte-cycle-audit-20260725/yosys-lint-synth.log: OK +./results/protocol-byte-cycle-audit-20260725/yosys-lint-synth.status: OK +./results/serial-mul-byte-order-20260725/README.md: OK +./results/serial-mul-byte-order-20260725/base-source-sha.txt: OK +./results/serial-mul-byte-order-20260725/bind-elaboration-check.log: OK +./results/serial-mul-byte-order-20260725/bind-elaboration-check.status: OK +./results/serial-mul-byte-order-20260725/lean-build.log: OK +./results/serial-mul-byte-order-20260725/lean-build.status: OK +./results/serial-mul-byte-order-20260725/lean-print-axioms.input.lean: OK +./results/serial-mul-byte-order-20260725/lean-print-axioms.log: OK +./results/serial-mul-byte-order-20260725/lean-print-axioms.status: OK +./results/serial-mul-byte-order-20260725/make-check.log: OK +./results/serial-mul-byte-order-20260725/make-check.status: OK +./results/serial-mul-byte-order-20260725/make-sim.log: OK +./results/serial-mul-byte-order-20260725/make-sim.status: OK +./results/serial-mul-byte-order-20260725/make-smoke.log: OK +./results/serial-mul-byte-order-20260725/make-smoke.status: OK +./results/serial-mul-byte-order-20260725/placeholders.log: OK +./results/serial-mul-byte-order-20260725/placeholders.status: OK +./results/serial-mul-byte-order-20260725/sby-gf128-serialize-bmc.log: OK +./results/serial-mul-byte-order-20260725/sby-gf128-serialize-bmc.status: OK +./results/serial-mul-byte-order-20260725/sby-gf128-serialize-cover.log: OK +./results/serial-mul-byte-order-20260725/sby-gf128-serialize-cover.status: OK +./results/serial-mul-byte-order-20260725/sby-gf128-serialize-induction.log: OK +./results/serial-mul-byte-order-20260725/sby-gf128-serialize-induction.status: OK +./results/serial-mul-byte-order-20260725/sby-gf8-mul.log: OK +./results/serial-mul-byte-order-20260725/sby-gf8-mul.status: OK +./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-cover.log: OK +./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-cover.status: OK +./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.log: OK +./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.status: OK +./results/serial-mul-byte-order-20260725/toolchain.txt: OK +./results/ulx3s-smoke-uart-20260725/SHA256SUMS_bridge.txt: OK +./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST.txt: OK +./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST_uart.txt: OK +./results/ulx3s-smoke-uart-20260725/nextpnr.log: OK +./results/ulx3s-smoke-uart-20260725/nextpnr_uart.log: OK +./results/ulx3s-smoke-uart-20260725/smoke.config: OK +./results/ulx3s-smoke-uart-20260725/smoke.svf: OK +./results/ulx3s-smoke-uart-20260725/timing.txt: OK +./results/ulx3s-smoke-uart-20260725/timing_uart.txt: OK +./results/ulx3s-smoke-uart-20260725/tool_versions.txt: OK +./results/ulx3s-smoke-uart-20260725/tool_versions_uart.txt: OK +./results/ulx3s-smoke-uart-20260725/ulx3s_bridge.bit: OK +./results/ulx3s-smoke-uart-20260725/ulx3s_smoke.bit: OK +./results/ulx3s-smoke-uart-20260725/yosys.log: OK +./results/ulx3s-smoke-uart-20260725/yosys_uart.log: OK +./sim/__init__.py: OK +./sim/__pycache__/__init__.cpython-312.pyc: OK +./sim/__pycache__/lsc1_transaction.cpython-312.pyc: OK +./sim/__pycache__/test_packet_frontend_rtl_differential.cpython-312.pyc: OK +./sim/cycle_model.py: OK +./sim/lsc1_transaction.py: OK +./sim/model.py: OK +./sim/packet_executor_model.py: OK +./sim/protocol_contract.py: OK +./sim/scalar_step_oracle.py: OK +./sim/test_atomic_publish.py: OK +./sim/test_blake3_service.py: OK +./sim/test_conformance_corpus.py: OK +./sim/test_cycle_model.py: OK +./sim/test_host_runtime.py: OK +./sim/test_lsc1_protocol_doc.py: OK +./sim/test_lsc1_transaction.py: OK +./sim/test_model.py: OK +./sim/test_packet_executor_model.py: OK +./sim/test_packet_frontend_rtl_differential.py: OK +./sim/test_protocol_contract.py: OK +./sim/test_scalar_step_oracle.py: OK +./src/gf128_mul_bitstream.sv: OK +./src/gf2n_mul_bitstream.sv: OK +./src/leanvm_b_m2_scalar_controller.sv: OK +./src/leanvm_b_stream_alu.sv: OK +./src/tt_um_leanvm_b_mincore.sv: OK +./src/user_config.tcl: OK +./test/Makefile: OK +./test/packet_frontend/Makefile: OK +./test/packet_frontend/tb_lsc1_packet_frontend.sv: OK +./test/packet_frontend/tb_lsc1_packet_frontend.vvp: OK +./test/packet_frontend/tb_lsc1_packet_vector.sv: OK +./test/tb_m2_scalar_controller.sv: OK +./test/tb_packet_uart_bridge.sv: OK +./test/tb_stream_alu.sv: OK +./test/tb_uart_bridge.sv: OK +./tools/atomic_publish.py: OK +./tools/blake3_reference/Cargo.lock: OK +./tools/blake3_reference/Cargo.toml: OK +./tools/blake3_reference/src/main.rs: OK +./tools/check_arch_state_interface.py: OK +./tools/conformance_differential.py: OK +./tools/design_space.csv: OK +./tools/design_space.md: OK +./tools/design_space.py: OK +./tools/exact_linear_xor.py: OK +./tools/frozen_upstream_differential.py: OK +./tools/generate_checksums.py: OK +./tools/generate_conformance_corpus.py: OK +./tools/host_upstream_comparison.py: OK +./tools/interface_consistency.py: OK +./tools/lean_compiler_export.py: OK +./tools/m2_rtl_differential.py: OK +./tools/portable_build_support.py: OK +./tools/repo_consistency.py: OK +./tools/rtl_state_count.py: OK +./tools/run_arch_state_milestones.sh: OK +./tools/source_provenance.py: OK +./tools/sv_smoke_check.py: OK diff --git a/results/arch-state-omissions-20260728/rtl.log b/results/arch-state-omissions-20260728/rtl.log new file mode 100644 index 0000000..055d5bf --- /dev/null +++ b/results/arch-state-omissions-20260728/rtl.log @@ -0,0 +1,31 @@ +make: Entering directory '/workspaces/mission-cbe073d0/work/pr30/test/packet_frontend' +iverilog -g2012 -Wall -s tb_lsc1_packet_frontend -o tb_lsc1_packet_frontend.vvp ../../asic_core/rtl/lsc1_packet_rx.sv ../../asic_core/rtl/lsc1_packet_tx.sv ../../asic_core/rtl/gf2n_mul_bitstream.sv ../../asic_core/rtl/gf128_mul_bitstream.sv ../../asic_core/rtl/leanvm_b_stream_alu.sv ../../asic_core/rtl/lsc1_stream_adapter.sv ../../asic_core/rtl/lsc1_field_encoder.sv ../../asic_core/rtl/lsc1_packet_frontend.sv tb_lsc1_packet_frontend.sv +warning: Some design elements have no explicit time unit and/or + : time precision. This may cause confusing timing results. + : Affected design elements are: + : -- module gf128_mul_bitstream declared here: ../../asic_core/rtl/gf128_mul_bitstream.sv:9 + : -- module gf2n_mul_bitstream declared here: ../../asic_core/rtl/gf2n_mul_bitstream.sv:22 + : -- module leanvm_b_stream_alu declared here: ../../asic_core/rtl/leanvm_b_stream_alu.sv:28 + : -- module lsc1_field_encoder declared here: ../../asic_core/rtl/lsc1_field_encoder.sv:6 + : -- module lsc1_packet_frontend declared here: ../../asic_core/rtl/lsc1_packet_frontend.sv:6 + : -- module lsc1_packet_rx declared here: ../../asic_core/rtl/lsc1_packet_rx.sv:5 + : -- module lsc1_packet_tx declared here: ../../asic_core/rtl/lsc1_packet_tx.sv:4 + : -- module lsc1_stream_adapter declared here: ../../asic_core/rtl/lsc1_stream_adapter.sv:6 +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +vvp tb_lsc1_packet_frontend.vvp +PASS: LSC-1 Phase-3 packet frontend adversarial test +tb_lsc1_packet_frontend.sv:426: $finish called at 44410000 (1ps) +make: Leaving directory '/workspaces/mission-cbe073d0/work/pr30/test/packet_frontend' diff --git a/results/arch-state-omissions-20260728/versions.log b/results/arch-state-omissions-20260728/versions.log new file mode 100644 index 0000000..7c374e2 --- /dev/null +++ b/results/arch-state-omissions-20260728/versions.log @@ -0,0 +1,5 @@ +2026-07-28T19:37:45Z +8e9b0a40d46fbe2ac2ca13e3696ac139d4d62490 +555992470ac11a72f1590f7b48098a5eccd5943a +Yosys 0.33 (git sha1 2584903a060) +Icarus Verilog version 12.0 (stable) () diff --git a/tools/check_arch_state_interface.py b/tools/check_arch_state_interface.py index ce6368f..467a536 100644 --- a/tools/check_arch_state_interface.py +++ b/tools/check_arch_state_interface.py @@ -1,27 +1,44 @@ #!/usr/bin/env python3 -"""Mechanical coverage and mutation guard for the architectural state map.""" -import json, pathlib, re, sys +"""Mechanical completeness, width, reconstruction, and mutation guard for R.""" +import json, pathlib, re root = pathlib.Path(__file__).resolve().parents[1] rtl = (root / "asic_core/rtl/lsc1_packet_frontend.sv").read_text() mapping = json.loads((root / "formal/lsc1_packet_frontend_arch_state_map.json").read_text()) -ports = set(re.findall(r"output wire\s+(?:\[[^]]+\]\s*)?(arch_[A-Za-z0-9_]+)", rtl)) +ports = {n: (int(a) - int(b) + 1 if a else 1) for a, b, n in + re.findall(r"output wire\s+(?:\[(\d+)\s*:\s*(\d+)\]\s+)?(arch_[A-Za-z0-9_]+)", rtl)} fields = mapping["fields"] -missing = ports - fields.keys() -extra = fields.keys() - ports -if missing or extra: - raise SystemExit(f"arch map coverage failure: missing={sorted(missing)} extra={sorted(extra)}") -for field, source in fields.items(): - needle = f"assign {field} = {source};" +if set(ports) != set(fields): + raise SystemExit(f"arch map coverage failure: missing={sorted(set(ports)-set(fields))} extra={sorted(set(fields)-set(ports))}") +for field, spec in fields.items(): + if spec["width"] != ports[field]: + raise SystemExit(f"width mismatch for {field}: map={spec['width']} RTL={ports[field]}") + needle = f"assign {field} = {spec['source']};" if needle not in rtl: raise SystemExit(f"R mapping is absent or perturbed: {needle}") -if set(mapping["observable_outputs"]) != {"rx_ready", "tx_data", "tx_valid", "busy", "fault", "done_pulse"}: +# Every nonblocking-assigned state element in each active module must be named. +modules = { + "lsc1_packet_frontend": "lsc1_packet_frontend.sv", "lsc1_packet_tx": "lsc1_packet_tx.sv", + "lsc1_stream_adapter": "lsc1_stream_adapter.sv", "leanvm_b_stream_alu": "leanvm_b_stream_alu.sv", + "gf2n_mul_bitstream": "gf2n_mul_bitstream.sv", "lsc1_field_encoder": "lsc1_field_encoder.sv", + "lsc1_packet_rx": "lsc1_packet_rx.sv"} +coverage = mapping["registered_coverage"] +for module, filename in modules.items(): + actual = set(re.findall(r"\b(\w+)\s*<=", (root / "asic_core/rtl" / filename).read_text())) + declared = set() + for owner, covered in coverage.items(): + if owner == module or owner.startswith(module + "."): + declared |= set(covered) + if actual - declared: + raise SystemExit(f"registered-state omission in {module}: {sorted(actual-declared)}") +if set(mapping["observable_outputs"]) != {"rx_ready","tx_data","tx_valid","busy","fault","done_pulse"}: raise SystemExit("observable output channel coverage changed") -# Mutation test: an altered mapped source must be rejected by the same check. -mutated = rtl.replace("assign arch_active_profile = active_profile;", - "assign arch_active_profile = last_status;") -if "assign arch_active_profile = active_profile;" in mutated: - raise SystemExit("mutation setup failed") -if "assign arch_active_profile = active_profile;" not in rtl: - raise SystemExit("mutation guard did not distinguish source mapping") -print(f"arch-state map: {len(fields)} fields; all outputs and 6 observable channels covered") +if set(mapping["output_reconstruction"]) != set(mapping["observable_outputs"]): + raise SystemExit("output reconstruction is incomplete") +# Mutations target the reviewer-identified omitted state and must be rejected. +for good, bad in [("assign arch_tx_saved_crc = tx_arch_saved_crc;", "assign arch_tx_saved_crc = tx_arch_payload_crc_work;"), + ("assign arch_alu_saved_a = alu_arch_saved_a;", "assign arch_alu_saved_a = alu_arch_saved_b;")]: + mutated = rtl.replace(good, bad) + if good in mutated or good not in rtl: + raise SystemExit("mutation guard did not distinguish mapped state") +print(f"arch-state map: {len(fields)} fields; widths, {sum(len(x) for x in coverage.values())} registered elements, output reconstruction, and mutations covered") From c5bcde4f6ae27b46df461de0a5c03bf953d05688 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Tue, 28 Jul 2026 21:58:19 +0200 Subject: [PATCH 7/9] Refresh tracked checksum inventory --- SHA256SUMS | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/SHA256SUMS b/SHA256SUMS index 531718b..acbc863 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -116,6 +116,7 @@ c22e2dd6edcd014dd803fd1ea630ae063aeee86e192afd6c34b4ac81efa73daa ./host/lean_co 451f3d686ce47b16d81de2f85d36a52231c99a1b47c261475c0cb4134a09d777 ./host/protocol.py 25034b46f23a72f3f5add04a398a8a8bb0858a293be5d433601502733ff84f32 ./host/runtime.py effcad52a728f7c1cc4b463ea8d7bc6cc6350ddb6daf836f4adc601f714485ab ./info.yaml +68a4209dcbdcc663454d02012642fa7b5a3476a13e363982fc9236e89c27a6b7 ./lean/LeanVMBMinCore.lean c09c6cf1a82598ec2c0e5f6ecf58852c8c27554f7036f36baadf027067a55f4e ./lean/LeanVMBMinCore/Address.lean 70ce5c26e2964f9c095505c2a621e5bdc08a9379656048ef5cc6d350d9a0bf31 ./lean/LeanVMBMinCore/ByteSerialization.lean f76af91e138dc3cd8981dd3bf6e62e03d1b37d847f0b3f68cd59015782ad017c ./lean/LeanVMBMinCore/CheckedIndex.lean @@ -129,7 +130,6 @@ ba05339f74771d0357a852dbb3bee59629480c76cec9d70fc14752c5818123ea ./lean/LeanVMB 5d6453af2400e4155bfb56444e053b3c8f893f4459a15cf1f3cf2d72815b510a ./lean/LeanVMBMinCore/Packet.lean b55a55b9a2bbeb82d62fa99c99381674e98750e872d933775dc7add2fd8e0aef ./lean/LeanVMBMinCore/Stream.lean a81918a95c1152b8aa57d132dd9fdc5b0d63843ca22dfdbd5c7ffb2c0e6e858b ./lean/LeanVMBMinCore/Transaction.lean -68a4209dcbdcc663454d02012642fa7b5a3476a13e363982fc9236e89c27a6b7 ./lean/LeanVMBMinCore.lean 1f67ca9fd0f51cd27b651b79aceddc1c972ef3e77cb358866df77740fc2a2064 ./lean/README.md 364a9fa30ceadcb16de01c341ee7207bc453be4be69add43c924ad27a6ffca76 ./lean/lake-manifest.json d1f2dfa6bf564b9cf248838630eb92efd55f03e9ab8bf5e7dfec3d318b9f0f29 ./lean/lakefile.lean @@ -138,6 +138,7 @@ d59a11f361717058c708574a6f41d9be99da29cfcc3b0c033045ce6f0e57a5d5 ./planning/OWN a19467b08293daf14a67ccd8f0efbcddfeb3854c38525acd7fcfd98f01552587 ./planning/milestones.yaml fbce601088163a30bf024083852ec3d72a1dd2ab12a22a9ea1fc8809cadafb93 ./requirements.txt 091c91a57156e3fe3207f2a1c46f1b189209d0a7b1089f226c80da9aac40509a ./results/arch-state-20260728/README.md +62d0ec37d880c46a9f7ef6e36bcac75b9cfd3bf7ffd82cbcfa89c0cd2aa688ad ./results/arch-state-20260728/SHA256SUMS b91294fb84265d3d8a568773e69bf4be6989b8b2495d06ea1b2b166c021228c2 ./results/arch-state-20260728/differential.log 4e79a6223338d65e7609b234e33c62cbad037f3a27f1f6fe795f6d61e1ecc281 ./results/arch-state-20260728/interface-coverage.log c3a2a9f65cc2cc17d980a939d510da253dba23547a875440b950137da81581c5 ./results/arch-state-20260728/mutation.log @@ -145,6 +146,7 @@ ff5d1517dabeb83213ca643ef75a392a17003417d41d11b2dc385450e0121825 ./results/arch 1232f3d6bb4138ddf396895ed067274601df653827828396b79a88b2430a438d ./results/arch-state-20260728/rtl.log 00486fb8958a8818e17326967dee9e5fcfaf602093c282a957229b491eefcf99 ./results/arch-state-20260728/versions-and-inputs.log f9f38bf0f4ea6c18e6878c1e06dc7b6565498b28ef6cc6da322256492edc9fb0 ./results/arch-state-omissions-20260728/README.md +40d8867ac2a359264d09a6c4649e516f0699e556a6c48e7d793d4e964747f60f ./results/arch-state-omissions-20260728/SHA256SUMS c377a2118b46bdb2786c85aac8cfe2226e9a9eec3e009451f357c52f7e3fc414 ./results/arch-state-omissions-20260728/differential.log c1a78566db364c4d3c9ba81031c90e0641395b86f95de187eb0616466fe6b23e ./results/arch-state-omissions-20260728/forbidden-token-scan.log 4c0959a206d1b2d8d17b2c62eb7b2a7f92b83c38167f1c4009a9d05cb0f287ed ./results/arch-state-omissions-20260728/formal-reset.log @@ -154,6 +156,7 @@ c3a2a9f65cc2cc17d980a939d510da253dba23547a875440b950137da81581c5 ./results/arch 1232f3d6bb4138ddf396895ed067274601df653827828396b79a88b2430a438d ./results/arch-state-omissions-20260728/rtl.log f550fcd0882dc02526e9301821800a8bbbe79d5f327bd4c010fd8d882630405e ./results/arch-state-omissions-20260728/versions.log 315f8bfecb585814f0d1ec406d16203365e360601166a2e4f897b488cd6ab057 ./results/b2-capability-contract-20260728/README.md +a5157bf6549b0f1730477e82b1ec94a4dacc83f0ae93fc1e0d4e698ec97e1d4c ./results/b2-capability-contract-20260728/SHA256SUMS 967cd83720a145d1daba23a926a1b22eabc4e83d7b7c337cf3512f3df944c535 ./results/b2-capability-contract-20260728/blake3_official.command 42b629a692f30c9bfb0fcff81a5eb4631efb576c1355485035dd6d8c50131631 ./results/b2-capability-contract-20260728/blake3_official.log c4c41bd36c74ae8036f7f04e842e6e165b94947210de3fbb2ff0fc6a7d212aa6 ./results/b2-capability-contract-20260728/blake3_official.status @@ -221,6 +224,7 @@ dc9ae71fe0b8bdbacc6293d9f754e5eb7e1dae4a9ad37c7903a0e510ff388e3b ./results/fpga e283221feb3d7e57f4c18fb3b585a395784f23e1fbb5e0a6393ce3fed7f4740e ./results/fpga-harness-inventory-20260725/tested-source-sha.txt 6f105c46c0d7a97a6425c136d1bf6f933aa91fe9eee296f86fba4d66a1662560 ./results/fpga-harness-inventory-20260725/toolchain.txt be0da30a37ab97160fe55efe0ac74c986a452772454b725862cdd099aeabe448 ./results/frozen-oracle-evidence-20260725/README.md +2d55eb5eeca0baa3e8f941de57632f6810a71feefbfc31be9999b5e4b21fb147 ./results/frozen-oracle-evidence-20260725/SHA256SUMS 29eda5c5be90a767c8927e1e6ef1e94f2f0c8ca696a23a0a57521b9fe10889ee ./results/frozen-oracle-evidence-20260725/boundary-rejection.log cc3cc28b38e104777a88cf95ba04ae47a26b522c76024085bdfc42a7f8ce9894 ./results/frozen-oracle-evidence-20260725/m2.json dc738aa207758c4cdb704a288dc53b0d0016165a44cfd1158c4f9620f88dfffd ./results/frozen-oracle-evidence-20260725/m2.log @@ -355,6 +359,7 @@ c05bcfb6cfbeaa2f72eb031a986a37e6094ec430022d6cce911cf4fcedfb101a ./results/seri 42f3d4668a80ab3bf2a16915803d5a212bb299ca8800fa24dfc0f8baaa88c509 ./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.log ceceba3b9bc693c4b5a87f799e91ee36f93c483dd32d6e32514eb2a3e02779ad ./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.status 228b1eb2253fe285abf3f2d6cf6a7748661a11367433e17a8cef8832ea6068e4 ./results/serial-mul-byte-order-20260725/toolchain.txt +0d617e2e80e8749ea5f1b0a48f2da7ddac62dcb5f8def09126d60971f26dbf36 ./results/ulx3s-smoke-uart-20260725/SHA256SUMS ecd004f3008420bdf304a9d8f1084202847f65836bafed2aef69b858db180628 ./results/ulx3s-smoke-uart-20260725/SHA256SUMS_bridge.txt 7b45b067f30eb0a477f2eea894f79b0694ee3dcfb78752c935a2aa13c2a53d51 ./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST.txt dbda64dd3a2c4985c6d2a98123daac73461e2cb4d1ffb18da445920d5f2fe19b ./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST_uart.txt @@ -371,9 +376,6 @@ eacee77bdca486f173cacdb56709e442942eb85f9111eabcb96026976f8bae51 ./results/ulx3 e3329b92c1baf92fa161eb36a067e2ccbe73342fe8e419c315fbadfef9729b7d ./results/ulx3s-smoke-uart-20260725/yosys.log 7d50c170f623ccc6911a48dd18455bc1011a2be335a9997c6d85355d0c72e63d ./results/ulx3s-smoke-uart-20260725/yosys_uart.log 2ce193a38f1a8c96ec1cbfe2c8b7555d025944cb450859c3e09dd2cbab66a03c ./sim/__init__.py -0395ed8bde85b5758af6c3d70773dd23ebee400055c9d0f81ac53d0b50ce285d ./sim/__pycache__/__init__.cpython-312.pyc -b94e2104bd04ac0f5cdd5a8f3d35f4d8756a4482965fffe3411c2d1915e651b9 ./sim/__pycache__/lsc1_transaction.cpython-312.pyc -2cb22c1850638b2c9fdc2d6713856b3ec154731176708715946885bb13e73f90 ./sim/__pycache__/test_packet_frontend_rtl_differential.cpython-312.pyc 56f95ab49ce35604c5b30cd95d142a4d630b2d503af5398b1f975ef84492b48c ./sim/cycle_model.py 2a1871001ed3c296926b0f343bd8fd32176da7959628786bea51d7772653b633 ./sim/lsc1_transaction.py 12dd1aca968efeafb9ffa7015f849607c96fb6e14ad2aa8f65938dd254ef6f49 ./sim/model.py @@ -401,7 +403,6 @@ a3574d9d454d7b7580d2dcdc2801013a7648c48358a3f4a90a5c876ae9791331 ./src/user_con 69cd41bda612b601228752f516472df0f3be356de2f327ce4bbaaccb588edcf7 ./test/Makefile 2b5c167fcbbbc265e3aef203c8ffc59b0c6c4db8e7d180dc45133606414bb000 ./test/packet_frontend/Makefile d54a6f18a9c81353492801e51de435e47885fbbd3faae8c955cde0774b66eb2f ./test/packet_frontend/tb_lsc1_packet_frontend.sv -b234d21acd2f17d2296ec5596af324f9d1ba494bcf9e59838f5c77bff429ebb2 ./test/packet_frontend/tb_lsc1_packet_frontend.vvp f1bf4caf7438081d289ea48ebfcbed8f278866a664636dc810ea5e2c1b4410c3 ./test/packet_frontend/tb_lsc1_packet_vector.sv d0c03fb87fe5f08fbec435d485e4dd14c96d164e90b0e8b0ed8980cf27e8c077 ./test/tb_m2_scalar_controller.sv 2ea0bf23432e7c9471b09d7dac47b1b548f37d746a8cdf1fc9bd8128cd2a8018 ./test/tb_packet_uart_bridge.sv From fb3c063ca280e71f8721fefe858d10ce8cca772a Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Tue, 28 Jul 2026 22:52:02 +0200 Subject: [PATCH 8/9] Add bounded frontend one-cycle boundary checks --- SHA256SUMS | 10 ++- formal/ARCH_STATE.md | 27 ++++--- ...lsc1_packet_frontend_one_cycle_boundary.sv | 73 +++++++++++++++++++ ...lsc1_packet_frontend_one_cycle_boundary.ys | 6 ++ test/packet_frontend/Makefile | 16 +++- ...lsc1_packet_frontend_one_cycle_boundary.sv | 53 ++++++++++++++ tools/check_frontend_one_cycle_boundary.py | 30 ++++++++ tools/run_arch_state_milestones.sh | 10 ++- 8 files changed, 209 insertions(+), 16 deletions(-) create mode 100644 formal/lsc1_packet_frontend_one_cycle_boundary.sv create mode 100644 formal/lsc1_packet_frontend_one_cycle_boundary.ys create mode 100644 test/packet_frontend/tb_lsc1_packet_frontend_one_cycle_boundary.sv create mode 100644 tools/check_frontend_one_cycle_boundary.py diff --git a/SHA256SUMS b/SHA256SUMS index acbc863..804be07 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -53,7 +53,7 @@ c8dbcf0008931bfd0d6a27c00425480de54d322dd27367ae83f54f93e3382b8c ./docs/semanti 3e896ee33e3804876f6e169c872746146c1b3d773811683616986a4148b9f785 ./docs/semantics/reference/oracle.py c49a013eb503060394007d07395e625024d7c1ff0e9b177bc71e691e1a4efec8 ./docs/semantics/reference/vectors.json 961d9f2f85fe6a6e2a5f586412e03759cb94a80683959e7f0271f37f200a4f1d ./docs/upstream-clarifications/README.md -88754daba18a83e6c8106fa61fe8aadcc98a8c530ddb0634209c48f44424c2e6 ./formal/ARCH_STATE.md +d32e602fce788149a433092d04b1a82e7199ce49f890362fc8b255c4e14bafe7 ./formal/ARCH_STATE.md e563e1a3b9189f28388b5335b0be480856200a4e196de6f61e90b8e7ece0b5e1 ./formal/README.md d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836 ./formal/gf128_serialize.sby 9a069838244bd75c66ab3930eb944c3677ae83242f9b2cbd9866a0d6d1db3198 ./formal/gf128_serialize_formal.sv @@ -65,6 +65,8 @@ d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836 ./formal/gf128 faac561322f0831f66924be0afd8a5ae5cca1cb3e3d2b9dc9ca1b5ea576cdabb ./formal/lsc1_packet_frontend_arch_reset_idle.sv f85348ac2c65ad828d1365d62254664817efd1bbcb7aee2bb2f20791e4493e20 ./formal/lsc1_packet_frontend_arch_reset_idle.ys d4dd8f33e2a5aade976d06cae7be3bd6d6cf41918499c5bdd20e36132fb95bfe ./formal/lsc1_packet_frontend_arch_state_map.json +19dfd1aa5533a7d46907c904f418de01515bd6fc72a083116f0173932805906c ./formal/lsc1_packet_frontend_one_cycle_boundary.sv +d5bc98cdcff1c3105aa680778d768fd1acdc3b8b8fa027203222d5ebe08d5db7 ./formal/lsc1_packet_frontend_one_cycle_boundary.ys bca568aee38c4638fdaadab4e8878807bc56329bd170b4cb420c07e4357dd6dc ./formal/lsc1_packet_frontend_release_equiv.ys 1e6b80dd959472d00411116899097fb37c930651efe6290fda93a8f4ae5ae97e ./formal/stream_alu_mul_pulse.sby b61a1ea32d6b114093dd2679fd4fb3315dbfbb9829b8e4f739c0177f66ff1bc1 ./formal/stream_alu_mul_pulse_formal.sv @@ -401,8 +403,9 @@ bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b ./src/leanvm_b e97452e6444238c80a86811f86d892a0db6e79e498d00afc638387f8656ef28c ./src/tt_um_leanvm_b_mincore.sv a3574d9d454d7b7580d2dcdc2801013a7648c48358a3f4a90a5c876ae9791331 ./src/user_config.tcl 69cd41bda612b601228752f516472df0f3be356de2f327ce4bbaaccb588edcf7 ./test/Makefile -2b5c167fcbbbc265e3aef203c8ffc59b0c6c4db8e7d180dc45133606414bb000 ./test/packet_frontend/Makefile +57406947083d3096904b7dd71b4f7b63ed95585829982e34f8467080da2f2eca ./test/packet_frontend/Makefile d54a6f18a9c81353492801e51de435e47885fbbd3faae8c955cde0774b66eb2f ./test/packet_frontend/tb_lsc1_packet_frontend.sv +96ae1841444f08d82ddc92bce9f28e61f1f482497dbf391a14cf7936c5ef1e5d ./test/packet_frontend/tb_lsc1_packet_frontend_one_cycle_boundary.sv f1bf4caf7438081d289ea48ebfcbed8f278866a664636dc810ea5e2c1b4410c3 ./test/packet_frontend/tb_lsc1_packet_vector.sv d0c03fb87fe5f08fbec435d485e4dd14c96d164e90b0e8b0ed8980cf27e8c077 ./test/tb_m2_scalar_controller.sv 2ea0bf23432e7c9471b09d7dac47b1b548f37d746a8cdf1fc9bd8128cd2a8018 ./test/tb_packet_uart_bridge.sv @@ -413,6 +416,7 @@ e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a ./tools/atomic e28e67bc3fd6dee898130648c74691ca7b8e61d1fccfa75c52d87d52fc8d9c3f ./tools/blake3_reference/Cargo.toml 3414b26004416f8871274b30fa975b40f611b5b6b148a2e1b3d97c109cd37f52 ./tools/blake3_reference/src/main.rs 6b0d7c7843f414a9180aa3a1a9fbd05bde01c50cee2922b2cd5a3ff8c7dbb351 ./tools/check_arch_state_interface.py +aff01da5de4c0bbda61a8bb1f024bf2a6c1c8c949b6f99ab13ca4ea2af3eb3cc ./tools/check_frontend_one_cycle_boundary.py 3057cbe3ffbd0b8826a9c77cca1be2e3344b831373adbe583679706858b50910 ./tools/conformance_differential.py 008f814b114282389ae48ff82e4412fe455cbe8c377cf71e534862d490d3cb79 ./tools/design_space.csv 75dc51b45b2631ddc57c4629982949696f1b711323f6e857ca19dc42961f7359 ./tools/design_space.md @@ -428,6 +432,6 @@ a1fbbcbe225a1e2edb2456f92825e7b6853f224e8d0379aa4454d298c2419919 ./tools/frozen 737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 ./tools/portable_build_support.py af28d238b411fcc075bb00b09a204ed1a98c4b4c36479ab5aa6ca611928efba0 ./tools/repo_consistency.py d39b590b15a494a1e62ff7605ca3b8c8ffec122e0f10f6dce7f997fcecceef1b ./tools/rtl_state_count.py -8ad06f1f1a05c1f09b78690dd09c5bc0e08633827feb77da5de43d563bd3dada ./tools/run_arch_state_milestones.sh +8eccefe071bb813d8e5adca59474f4710e3abb2508294dba59b997c2416c3fcf ./tools/run_arch_state_milestones.sh a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db ./tools/source_provenance.py 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d ./tools/sv_smoke_check.py diff --git a/formal/ARCH_STATE.md b/formal/ARCH_STATE.md index a0fb853..8569c9a 100644 --- a/formal/ARCH_STATE.md +++ b/formal/ARCH_STATE.md @@ -42,13 +42,20 @@ response. Procedural decode temporaries (`txn_id`, offsets, decisions and local write candidates) are excluded because they are not retained across a clock. The one-cycle relation is the production clocked transition relation under the -same `(rst_n, abort, rx_data, rx_valid, tx_ready)` inputs. Reset clears the map -with profile 1; idle stutters when no input is accepted and no response is -active. At every cycle the public packet outputs agree with their architectural -observations. No cutpoints, black boxes, symbolic bridge state, or ignored -output channel is used. - -This is a correspondence interface, not a claim of full LSC-1 refinement. The -next required proof is a phase-complete refinement from these fields to the -executable model; the smallest currently recorded failing partition must be -kept if that proof does not close. +same `(rst_n, abort, rx_data, rx_valid, tx_ready)` inputs. The bounded +`lsc1_packet_frontend_one_cycle_boundary` formal harness and its executable +SystemVerilog counterpart cover the whole integrated frontend boundary (not +just the parser): abort's next state clears queued work, starts no subunit, +drops the staged result, and records `0x93`; a quiescent frontend stutters every +retained transaction, commit, profile, and status field. +`tools/check_frontend_one_cycle_boundary.py` makes omissions and the two abort +next-state mutations fail mechanically. Reset still clears the map with profile +1. No cutpoints, black boxes, symbolic bridge state, or ignored output channel +is used. + +This is a correspondence interface, not a claim of full LSC-1 refinement or +release sequential equivalence. The full-frontend formal harness is bounded to +180 seconds in the milestone runner and may record `UNRESOLVED` rather than +turn a resource limit into a proof. The remaining blocker is a phase-complete +transition/refinement model for accepted frames, decode, compute completion, +and response serialization under arbitrary backpressure. diff --git a/formal/lsc1_packet_frontend_one_cycle_boundary.sv b/formal/lsc1_packet_frontend_one_cycle_boundary.sv new file mode 100644 index 0000000..f14b970 --- /dev/null +++ b/formal/lsc1_packet_frontend_one_cycle_boundary.sv @@ -0,0 +1,73 @@ +`default_nettype none +// Bounded one-cycle correspondence milestone for the registered frontend +// boundary. This is intentionally a reset/abort/idle relation, not a +// phase-complete release sequential-equivalence proof. +module lsc1_packet_frontend_one_cycle_boundary; + (* anyseq *) reg clk, abort, rx_valid, tx_ready; + (* anyseq *) reg [7:0] rx_data; + wire rx_ready, tx_valid, busy, fault, done_pulse; + wire [7:0] tx_data; + wire [3:0] arch_phase; + wire arch_parser_busy, arch_tx_busy, arch_alu_busy, arch_encoder_busy; + wire arch_tx_start, arch_capture_result_crc, arch_alu_start, arch_encoder_start; + wire arch_result_pending, arch_state_valid, arch_fault, arch_done_pulse; + wire [31:0] arch_staged_txn_id, arch_staged_next_pc, arch_staged_next_fp; + wire [31:0] arch_staged_result_crc, arch_committed_pc, arch_committed_fp, arch_retire_seq; + wire [7:0] arch_active_profile, arch_last_status, arch_last_fault; + wire rst_n = 1'b1; + reg past_valid; + + lsc1_packet_frontend dut ( + .clk(clk), .rst_n(rst_n), .abort(abort), .rx_data(rx_data), + .rx_valid(rx_valid), .rx_ready(rx_ready), .tx_data(tx_data), + .tx_valid(tx_valid), .tx_ready(tx_ready), .busy(busy), .fault(fault), + .done_pulse(done_pulse), .arch_phase(arch_phase), + .arch_parser_busy(arch_parser_busy), .arch_tx_busy(arch_tx_busy), + .arch_alu_busy(arch_alu_busy), .arch_encoder_busy(arch_encoder_busy), + .arch_tx_start(arch_tx_start), .arch_capture_result_crc(arch_capture_result_crc), + .arch_alu_start(arch_alu_start), .arch_encoder_start(arch_encoder_start), + .arch_result_pending(arch_result_pending), .arch_staged_txn_id(arch_staged_txn_id), + .arch_staged_next_pc(arch_staged_next_pc), .arch_staged_next_fp(arch_staged_next_fp), + .arch_staged_result_crc(arch_staged_result_crc), .arch_state_valid(arch_state_valid), + .arch_committed_pc(arch_committed_pc), .arch_committed_fp(arch_committed_fp), + .arch_retire_seq(arch_retire_seq), .arch_active_profile(arch_active_profile), + .arch_last_status(arch_last_status), .arch_last_fault(arch_last_fault), + .arch_fault(arch_fault), .arch_done_pulse(arch_done_pulse) + ); + + always @(*) assume(clk == 1'b1); + + always @(posedge clk) begin + past_valid <= 1'b1; + if (past_valid && $past(abort)) begin + // The executable boundary model's abort transition. These are the + // frontend's retained architectural registers, not a parser cutpoint. + assert(arch_phase == 0); + assert(!arch_tx_start && !arch_capture_result_crc); + assert(!arch_alu_start && !arch_encoder_start); + assert(!arch_result_pending && !arch_done_pulse); + assert(arch_fault && arch_last_status == 8'h93 && arch_last_fault == 8'h93); + end + if (past_valid && + $past(!abort && !rx_valid && !tx_ready && + arch_phase == 0 && !arch_parser_busy && !arch_tx_busy && + !arch_alu_busy && !arch_encoder_busy)) begin + // Quiescent registered-state stutter. This guards the frontend state + // that can affect a later RETIRE/STATUS/NEGOTIATE response. + assert(arch_phase == 0 && !arch_parser_busy && !arch_tx_busy && !arch_alu_busy && !arch_encoder_busy); + assert(arch_result_pending == $past(arch_result_pending)); + assert(arch_staged_txn_id == $past(arch_staged_txn_id)); + assert(arch_staged_next_pc == $past(arch_staged_next_pc)); + assert(arch_staged_next_fp == $past(arch_staged_next_fp)); + assert(arch_staged_result_crc == $past(arch_staged_result_crc)); + assert(arch_state_valid == $past(arch_state_valid)); + assert(arch_committed_pc == $past(arch_committed_pc)); + assert(arch_committed_fp == $past(arch_committed_fp)); + assert(arch_retire_seq == $past(arch_retire_seq)); + assert(arch_active_profile == $past(arch_active_profile)); + assert(arch_last_status == $past(arch_last_status)); + assert(arch_last_fault == $past(arch_last_fault)); + end + end +endmodule +`default_nettype wire diff --git a/formal/lsc1_packet_frontend_one_cycle_boundary.ys b/formal/lsc1_packet_frontend_one_cycle_boundary.ys new file mode 100644 index 0000000..bfbf8a6 --- /dev/null +++ b/formal/lsc1_packet_frontend_one_cycle_boundary.ys @@ -0,0 +1,6 @@ +read_verilog -formal -sv asic_core/rtl/lsc1_packet_rx.sv asic_core/rtl/lsc1_packet_tx.sv asic_core/rtl/gf2n_mul_bitstream.sv asic_core/rtl/gf128_mul_bitstream.sv asic_core/rtl/leanvm_b_stream_alu.sv asic_core/rtl/lsc1_stream_adapter.sv asic_core/rtl/lsc1_field_encoder.sv asic_core/rtl/lsc1_packet_frontend.sv formal/lsc1_packet_frontend_one_cycle_boundary.sv +prep -top lsc1_packet_frontend_one_cycle_boundary +flatten +opt +select -module lsc1_packet_frontend_one_cycle_boundary +sat -seq 3 -prove-asserts -set-assumes -set-init-zero diff --git a/test/packet_frontend/Makefile b/test/packet_frontend/Makefile index 3c1fda9..1b12aca 100644 --- a/test/packet_frontend/Makefile +++ b/test/packet_frontend/Makefile @@ -7,12 +7,16 @@ RTL = ../../asic_core/rtl/lsc1_packet_rx.sv \ ../../asic_core/rtl/lsc1_field_encoder.sv \ ../../asic_core/rtl/lsc1_packet_frontend.sv -.PHONY: sim mutation differential-mutation clean +.PHONY: sim one-cycle-boundary mutation differential-mutation clean sim: iverilog -g2012 -Wall -s tb_lsc1_packet_frontend -o tb_lsc1_packet_frontend.vvp $(RTL) tb_lsc1_packet_frontend.sv vvp tb_lsc1_packet_frontend.vvp +one-cycle-boundary: + iverilog -g2012 -Wall -s tb_lsc1_packet_frontend_one_cycle_boundary -o tb_lsc1_packet_frontend_one_cycle_boundary.vvp $(RTL) tb_lsc1_packet_frontend_one_cycle_boundary.sv + vvp tb_lsc1_packet_frontend_one_cycle_boundary.vvp + mutation: @d=$$(mktemp -d); trap 'rm -rf "$$d"' EXIT; \ cp $(RTL) "$$d/"; \ @@ -58,6 +62,14 @@ mutation: fi; \ grep -q "status got=87 expected=83" "$$d/length.out"; \ cp ../../asic_core/rtl/lsc1_packet_frontend.sv "$$d/lsc1_packet_frontend.sv"; \ + sed -i.bak "/end else if (abort) begin/,/end else begin/ s/last_status <= 8'h93;/last_status <= 8'h00;/" "$$d/lsc1_packet_frontend.sv"; \ + iverilog -g2012 -s tb_lsc1_packet_frontend_one_cycle_boundary -o "$$d/abort-status.vvp" \ + "$$d"/*.sv tb_lsc1_packet_frontend_one_cycle_boundary.sv; \ + if vvp "$$d/abort-status.vvp" >"$$d/abort-status.out" 2>&1; then \ + echo "ABORT status next-state mutation unexpectedly survived" >&2; exit 1; \ + fi; \ + grep -q "frontend abort next-state mismatch" "$$d/abort-status.out"; \ + cp ../../asic_core/rtl/lsc1_packet_frontend.sv "$$d/lsc1_packet_frontend.sv"; \ sed -i.bak 's/frame_payload\[16 +: 8\] != 1/1'"'"'b0/' "$$d/lsc1_packet_frontend.sv"; \ iverilog -g2012 -s tb_lsc1_packet_frontend -o "$$d/profile.vvp" \ "$$d"/*.sv tb_lsc1_packet_frontend.sv; \ @@ -65,7 +77,7 @@ mutation: echo "FORWARD_ONLY negotiation mutation unexpectedly survived" >&2; exit 1; \ fi; \ grep -q "status got=00 expected=86" "$$d/profile.out"; \ - echo "PASS: BUSY, SET value, RETIRE ID, ABORT, length-order, and profile mutations were detected" + echo "PASS: BUSY, SET value, RETIRE ID, ABORT, abort status, length-order, and profile mutations were detected" differential-mutation: @d=$$(mktemp -d); trap 'rm -rf "$$d"' EXIT; \ diff --git a/test/packet_frontend/tb_lsc1_packet_frontend_one_cycle_boundary.sv b/test/packet_frontend/tb_lsc1_packet_frontend_one_cycle_boundary.sv new file mode 100644 index 0000000..c5564a0 --- /dev/null +++ b/test/packet_frontend/tb_lsc1_packet_frontend_one_cycle_boundary.sv @@ -0,0 +1,53 @@ +`timescale 1ns/1ps +`default_nettype none + +// Executable counterpart of the bounded formal reset/abort/idle model. +module tb_lsc1_packet_frontend_one_cycle_boundary; + reg clk = 0; always #5 clk = ~clk; + reg rst_n = 0, abort = 0, rx_valid = 0, tx_ready = 0; + reg [7:0] rx_data = 0; + wire rx_ready, tx_valid, busy, fault, done_pulse; + wire [7:0] tx_data; + lsc1_packet_frontend dut ( + .clk(clk), .rst_n(rst_n), .abort(abort), .rx_data(rx_data), .rx_valid(rx_valid), + .rx_ready(rx_ready), .tx_data(tx_data), .tx_valid(tx_valid), .tx_ready(tx_ready), + .busy(busy), .fault(fault), .done_pulse(done_pulse) + ); + + reg [31:0] prior_pc, prior_fp, prior_seq; + reg [7:0] prior_profile, prior_status, prior_fault; + initial begin + repeat (2) @(posedge clk); + // The reset half of the model is checked at the registered boundary. + if (dut.arch_phase !== 0 || dut.arch_active_profile !== 1 || + dut.arch_result_pending || dut.arch_state_valid || dut.arch_tx_busy || + dut.arch_parser_busy || dut.arch_alu_busy || dut.arch_encoder_busy) + $fatal(1, "frontend reset boundary mismatch"); + rst_n = 1; + repeat (2) @(posedge clk); + + // Model a pending result so that abort's discard transition is observable. + @(negedge clk); dut.result_pending = 1; dut.staged_txn_id = 32'h11223344; + @(negedge clk); abort = 1; + @(posedge clk); #1; + if (dut.arch_phase !== 0 || dut.arch_result_pending || dut.arch_tx_start || + dut.arch_capture_result_crc || dut.arch_alu_start || dut.arch_encoder_start || + !dut.arch_fault || dut.arch_last_status !== 8'h93 || dut.arch_last_fault !== 8'h93 || + dut.arch_done_pulse) + $fatal(1, "frontend abort next-state mismatch"); + @(negedge clk); abort = 0; + prior_pc = dut.arch_committed_pc; prior_fp = dut.arch_committed_fp; + prior_seq = dut.arch_retire_seq; prior_profile = dut.arch_active_profile; + prior_status = dut.arch_last_status; prior_fault = dut.arch_last_fault; + repeat (2) @(posedge clk); + if (dut.arch_phase !== 0 || dut.arch_parser_busy || dut.arch_tx_busy || + dut.arch_alu_busy || dut.arch_encoder_busy || dut.arch_committed_pc !== prior_pc || + dut.arch_committed_fp !== prior_fp || dut.arch_retire_seq !== prior_seq || + dut.arch_active_profile !== prior_profile || dut.arch_last_status !== prior_status || + dut.arch_last_fault !== prior_fault) + $fatal(1, "frontend quiescent-stutter mismatch"); + $display("PASS: full frontend registered reset/abort/idle boundary model"); + $finish; + end +endmodule +`default_nettype wire diff --git a/tools/check_frontend_one_cycle_boundary.py b/tools/check_frontend_one_cycle_boundary.py new file mode 100644 index 0000000..277d3c8 --- /dev/null +++ b/tools/check_frontend_one_cycle_boundary.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +"""Mechanical guard for the bounded frontend one-cycle correspondence slice.""" +from __future__ import annotations + +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +RTL = ROOT / "asic_core/rtl/lsc1_packet_frontend.sv" +FORMAL = ROOT / "formal/lsc1_packet_frontend_one_cycle_boundary.sv" + +rtl = RTL.read_text() +formal = FORMAL.read_text() +required = ( + "arch_result_pending", "arch_staged_txn_id", "arch_staged_next_pc", + "arch_staged_next_fp", "arch_staged_result_crc", "arch_state_valid", + "arch_committed_pc", "arch_committed_fp", "arch_retire_seq", + "arch_active_profile", "arch_last_status", "arch_last_fault", +) +missing = [name for name in required if name not in formal] +if missing: + raise SystemExit(f"one-cycle relation omits retained frontend state: {missing}") +for good, bad in ( + ("result_pending <= 1'b0;\n fault <= 1'b1;", "result_pending <= 1'b1;\n fault <= 1'b1;"), + ("last_status <= 8'h93;", "last_status <= 8'h00;"), +): + if good not in rtl: + raise SystemExit(f"expected transition target absent: {good!r}") + if bad in rtl: + raise SystemExit(f"abort next-state mutation survived: {bad!r}") +print("one-cycle boundary: retained frontend abort and quiescent-stutter state is covered") diff --git a/tools/run_arch_state_milestones.sh b/tools/run_arch_state_milestones.sh index e5a4519..2c3b98f 100755 --- a/tools/run_arch_state_milestones.sh +++ b/tools/run_arch_state_milestones.sh @@ -12,11 +12,19 @@ mkdir -p "$out" sha256sum asic_core/rtl/lsc1_packet_rx.sv asic_core/rtl/lsc1_packet_tx.sv \ asic_core/rtl/lsc1_stream_adapter.sv asic_core/rtl/lsc1_field_encoder.sv \ asic_core/rtl/lsc1_packet_frontend.sv formal/lsc1_packet_frontend_arch_state_map.json formal/ARCH_STATE.md \ - formal/lsc1_packet_frontend_arch_reset_idle.sv formal/lsc1_packet_frontend_arch_reset_idle.ys + formal/lsc1_packet_frontend_arch_reset_idle.sv formal/lsc1_packet_frontend_arch_reset_idle.ys \ + formal/lsc1_packet_frontend_one_cycle_boundary.sv formal/lsc1_packet_frontend_one_cycle_boundary.ys } > "$out/versions-and-inputs.log" python3 tools/check_arch_state_interface.py > "$out/interface-coverage.log" 2>&1 yosys -s formal/lsc1_packet_frontend_arch_reset_idle.ys 2>&1 | sed 's/[[:space:]]*$//' > "$out/reset-idle.log" +if timeout 180 yosys -s formal/lsc1_packet_frontend_one_cycle_boundary.ys > "$out/one-cycle-boundary.log" 2>&1; then + echo PASS > "$out/one-cycle-boundary.status" +else + echo UNRESOLVED > "$out/one-cycle-boundary.status" +fi +python3 tools/check_frontend_one_cycle_boundary.py > "$out/one-cycle-check.log" 2>&1 make -C test/packet_frontend sim > "$out/rtl.log" 2>&1 +make -C test/packet_frontend one-cycle-boundary > "$out/one-cycle-executable.log" 2>&1 python3 -m unittest sim.test_packet_frontend_rtl_differential -v > "$out/differential.log" 2>&1 make -C test/packet_frontend mutation > "$out/mutation.log" 2>&1 sha256sum "$out"/*.log > "$out/SHA256SUMS" From dab8b083b210ecbb04e5ff49c649949a40a56eb6 Mon Sep 17 00:00:00 2001 From: Thomas Marchand Date: Tue, 28 Jul 2026 23:35:46 +0200 Subject: [PATCH 9/9] formal: partition bounded frontend status path --- SHA256SUMS | 25 +- formal/ARCH_STATE.md | 24 +- formal/lsc1_packet_rx_status_accept.sv | 43 + formal/lsc1_packet_rx_status_accept.ys | 6 + formal/lsc1_packet_tx_status_response.sv | 40 + formal/lsc1_packet_tx_status_response.ys | 6 + .../frontend-bounded-path-20260728/README.md | 31 + .../frontend-bounded-path-20260728/SHA256SUMS | 12 + .../bounded-path-check.log | 1 + .../bounded-path-mutation.log | 3 + .../differential.log | 9 + .../interface-coverage.log | 1 + .../mutation.log | 3 + .../one-cycle-check.log | 1 + .../one-cycle-executable.log | 17 + .../reset-idle.log | 3088 +++++++++++++++++ .../frontend-bounded-path-20260728/rtl.log | 31 + .../status-accept.log | 906 +++++ .../status-response.log | 1753 ++++++++++ .../versions-and-inputs.log | 19 + test/packet_frontend/Makefile | 13 +- tools/check_frontend_bounded_path.py | 15 + tools/run_arch_state_milestones.sh | 18 +- 23 files changed, 6047 insertions(+), 18 deletions(-) create mode 100644 formal/lsc1_packet_rx_status_accept.sv create mode 100644 formal/lsc1_packet_rx_status_accept.ys create mode 100644 formal/lsc1_packet_tx_status_response.sv create mode 100644 formal/lsc1_packet_tx_status_response.ys create mode 100644 results/frontend-bounded-path-20260728/README.md create mode 100644 results/frontend-bounded-path-20260728/SHA256SUMS create mode 100644 results/frontend-bounded-path-20260728/bounded-path-check.log create mode 100644 results/frontend-bounded-path-20260728/bounded-path-mutation.log create mode 100644 results/frontend-bounded-path-20260728/differential.log create mode 100644 results/frontend-bounded-path-20260728/interface-coverage.log create mode 100644 results/frontend-bounded-path-20260728/mutation.log create mode 100644 results/frontend-bounded-path-20260728/one-cycle-check.log create mode 100644 results/frontend-bounded-path-20260728/one-cycle-executable.log create mode 100644 results/frontend-bounded-path-20260728/reset-idle.log create mode 100644 results/frontend-bounded-path-20260728/rtl.log create mode 100644 results/frontend-bounded-path-20260728/status-accept.log create mode 100644 results/frontend-bounded-path-20260728/status-response.log create mode 100644 results/frontend-bounded-path-20260728/versions-and-inputs.log create mode 100644 tools/check_frontend_bounded_path.py diff --git a/SHA256SUMS b/SHA256SUMS index 804be07..55c2c51 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -53,7 +53,7 @@ c8dbcf0008931bfd0d6a27c00425480de54d322dd27367ae83f54f93e3382b8c ./docs/semanti 3e896ee33e3804876f6e169c872746146c1b3d773811683616986a4148b9f785 ./docs/semantics/reference/oracle.py c49a013eb503060394007d07395e625024d7c1ff0e9b177bc71e691e1a4efec8 ./docs/semantics/reference/vectors.json 961d9f2f85fe6a6e2a5f586412e03759cb94a80683959e7f0271f37f200a4f1d ./docs/upstream-clarifications/README.md -d32e602fce788149a433092d04b1a82e7199ce49f890362fc8b255c4e14bafe7 ./formal/ARCH_STATE.md +7310dd2063b557716c129398fdc35d049b5982c81e2385f8055942b9e7e4f181 ./formal/ARCH_STATE.md e563e1a3b9189f28388b5335b0be480856200a4e196de6f61e90b8e7ece0b5e1 ./formal/README.md d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836 ./formal/gf128_serialize.sby 9a069838244bd75c66ab3930eb944c3677ae83242f9b2cbd9866a0d6d1db3198 ./formal/gf128_serialize_formal.sv @@ -68,6 +68,10 @@ d4dd8f33e2a5aade976d06cae7be3bd6d6cf41918499c5bdd20e36132fb95bfe ./formal/lsc1_ 19dfd1aa5533a7d46907c904f418de01515bd6fc72a083116f0173932805906c ./formal/lsc1_packet_frontend_one_cycle_boundary.sv d5bc98cdcff1c3105aa680778d768fd1acdc3b8b8fa027203222d5ebe08d5db7 ./formal/lsc1_packet_frontend_one_cycle_boundary.ys bca568aee38c4638fdaadab4e8878807bc56329bd170b4cb420c07e4357dd6dc ./formal/lsc1_packet_frontend_release_equiv.ys +8ea59e8fd8f3ec4dd147ba7b37689513b373a9479fd565f057929ef966bd0e72 ./formal/lsc1_packet_rx_status_accept.sv +aa53616c5c7d509acc4a50b7453d4387b1a97ee6b0819b7ad9461dcbb779eaf9 ./formal/lsc1_packet_rx_status_accept.ys +f96f5e9e40a3b52b6979af94584175db21e3eeab168a07238e9b9ec6f80d413e ./formal/lsc1_packet_tx_status_response.sv +da3e9a0f4ef2821db9e664ce544f0e6963dfe0e450826fe54fc8f90bb4a80450 ./formal/lsc1_packet_tx_status_response.ys 1e6b80dd959472d00411116899097fb37c930651efe6290fda93a8f4ae5ae97e ./formal/stream_alu_mul_pulse.sby b61a1ea32d6b114093dd2679fd4fb3315dbfbb9829b8e4f739c0177f66ff1bc1 ./formal/stream_alu_mul_pulse_formal.sv 53da30df5dd375567994d2e071664456f0c90d420710817fbbb4b53d894b668a ./fpga/ulx3s/Makefile @@ -225,6 +229,20 @@ dc9ae71fe0b8bdbacc6293d9f754e5eb7e1dae4a9ad37c7903a0e510ff388e3b ./results/fpga 53c234e5e8472b6ac51c1ae1cab3fe06fad053beb8ebfd8977b010655bfdd3c3 ./results/fpga-harness-inventory-20260725/make-sim.status e283221feb3d7e57f4c18fb3b585a395784f23e1fbb5e0a6393ce3fed7f4740e ./results/fpga-harness-inventory-20260725/tested-source-sha.txt 6f105c46c0d7a97a6425c136d1bf6f933aa91fe9eee296f86fba4d66a1662560 ./results/fpga-harness-inventory-20260725/toolchain.txt +e30e9827630526c100da588ae68662d3fb8c13e50fcadcb27a06e939e97666ce ./results/frontend-bounded-path-20260728/README.md +3738e603cc8df65c7db28541674c91dc4aa7d411dd6cf932d7868e17e20d375b ./results/frontend-bounded-path-20260728/SHA256SUMS +f1943b886302ad476759f2ac1f058605093ad61dca0927bcc0b274ccb42189a3 ./results/frontend-bounded-path-20260728/bounded-path-check.log +1b8f990615dee4668360d3167ab25636d4fe5d4d247b2e9bf6fe186385a5a36d ./results/frontend-bounded-path-20260728/bounded-path-mutation.log +ae9e589efd7641414500edbb23a8b8597876be964a0d534037a4d10917d4e041 ./results/frontend-bounded-path-20260728/differential.log +4c8f5cc3ce7dc012f38e9889075fef35fa19946a56ee529e1e10bc8d2e77e7b8 ./results/frontend-bounded-path-20260728/interface-coverage.log +fc001e2743facc2425c52a0f242205787fde5ba420f9db382e52c7ed174ab2be ./results/frontend-bounded-path-20260728/mutation.log +bb3de711cb2dbeed9b1a38277f135e599e2badbd3c5afc888f9d3a4310333cd5 ./results/frontend-bounded-path-20260728/one-cycle-check.log +bd99ca75ce7a7a81f797afc944bf7b7b142a33131625150dd12f6eeab1c5cb6a ./results/frontend-bounded-path-20260728/one-cycle-executable.log +ec4fa536210eb266d5821d66046028cd002e53d75fa1a74798279bc1df0b613f ./results/frontend-bounded-path-20260728/reset-idle.log +3ad87e37eb2d7490f4416824eb162010a2e8d83a943889a06261d55fa5266ff4 ./results/frontend-bounded-path-20260728/rtl.log +287599e8b4dbd67d065d71d747e83198206b5e3371eaa78216ab105080fdc834 ./results/frontend-bounded-path-20260728/status-accept.log +65c58abca21232f8f0d79ae1751affa91833f06f0d0924bbe336d47c6fbaa032 ./results/frontend-bounded-path-20260728/status-response.log +edf379e044ac6e7d5ce38d0061c944e523fa7731640373733f36e353ef1484cd ./results/frontend-bounded-path-20260728/versions-and-inputs.log be0da30a37ab97160fe55efe0ac74c986a452772454b725862cdd099aeabe448 ./results/frozen-oracle-evidence-20260725/README.md 2d55eb5eeca0baa3e8f941de57632f6810a71feefbfc31be9999b5e4b21fb147 ./results/frozen-oracle-evidence-20260725/SHA256SUMS 29eda5c5be90a767c8927e1e6ef1e94f2f0c8ca696a23a0a57521b9fe10889ee ./results/frozen-oracle-evidence-20260725/boundary-rejection.log @@ -403,7 +421,7 @@ bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b ./src/leanvm_b e97452e6444238c80a86811f86d892a0db6e79e498d00afc638387f8656ef28c ./src/tt_um_leanvm_b_mincore.sv a3574d9d454d7b7580d2dcdc2801013a7648c48358a3f4a90a5c876ae9791331 ./src/user_config.tcl 69cd41bda612b601228752f516472df0f3be356de2f327ce4bbaaccb588edcf7 ./test/Makefile -57406947083d3096904b7dd71b4f7b63ed95585829982e34f8467080da2f2eca ./test/packet_frontend/Makefile +f21bcfafd2d66439157c9a7e4e51e2d363376afdb05095a366bf38017b7f39be ./test/packet_frontend/Makefile d54a6f18a9c81353492801e51de435e47885fbbd3faae8c955cde0774b66eb2f ./test/packet_frontend/tb_lsc1_packet_frontend.sv 96ae1841444f08d82ddc92bce9f28e61f1f482497dbf391a14cf7936c5ef1e5d ./test/packet_frontend/tb_lsc1_packet_frontend_one_cycle_boundary.sv f1bf4caf7438081d289ea48ebfcbed8f278866a664636dc810ea5e2c1b4410c3 ./test/packet_frontend/tb_lsc1_packet_vector.sv @@ -416,6 +434,7 @@ e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a ./tools/atomic e28e67bc3fd6dee898130648c74691ca7b8e61d1fccfa75c52d87d52fc8d9c3f ./tools/blake3_reference/Cargo.toml 3414b26004416f8871274b30fa975b40f611b5b6b148a2e1b3d97c109cd37f52 ./tools/blake3_reference/src/main.rs 6b0d7c7843f414a9180aa3a1a9fbd05bde01c50cee2922b2cd5a3ff8c7dbb351 ./tools/check_arch_state_interface.py +416226ddcbd13e900ad92c1147784257dea6953eef213d7dcc8b81ea6ace8696 ./tools/check_frontend_bounded_path.py aff01da5de4c0bbda61a8bb1f024bf2a6c1c8c949b6f99ab13ca4ea2af3eb3cc ./tools/check_frontend_one_cycle_boundary.py 3057cbe3ffbd0b8826a9c77cca1be2e3344b831373adbe583679706858b50910 ./tools/conformance_differential.py 008f814b114282389ae48ff82e4412fe455cbe8c377cf71e534862d490d3cb79 ./tools/design_space.csv @@ -432,6 +451,6 @@ a1fbbcbe225a1e2edb2456f92825e7b6853f224e8d0379aa4454d298c2419919 ./tools/frozen 737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 ./tools/portable_build_support.py af28d238b411fcc075bb00b09a204ed1a98c4b4c36479ab5aa6ca611928efba0 ./tools/repo_consistency.py d39b590b15a494a1e62ff7605ca3b8c8ffec122e0f10f6dce7f997fcecceef1b ./tools/rtl_state_count.py -8eccefe071bb813d8e5adca59474f4710e3abb2508294dba59b997c2416c3fcf ./tools/run_arch_state_milestones.sh +cf7d0c966325e0d6d1b125220369497ab711389ae8ede5cba0b996cb79fae1dc ./tools/run_arch_state_milestones.sh a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db ./tools/source_provenance.py 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d ./tools/sv_smoke_check.py diff --git a/formal/ARCH_STATE.md b/formal/ARCH_STATE.md index 8569c9a..95ecf94 100644 --- a/formal/ARCH_STATE.md +++ b/formal/ARCH_STATE.md @@ -53,9 +53,21 @@ next-state mutations fail mechanically. Reset still clears the map with profile 1. No cutpoints, black boxes, symbolic bridge state, or ignored output channel is used. -This is a correspondence interface, not a claim of full LSC-1 refinement or -release sequential equivalence. The full-frontend formal harness is bounded to -180 seconds in the milestone runner and may record `UNRESOLVED` rather than -turn a resource limit into a proof. The remaining blocker is a phase-complete -transition/refinement model for accepted frames, decode, compute completion, -and response serialization under arbitrary backpressure. +## Concrete bounded accepted-path partitions + +The former flat full-frontend SAT attempt is not treated as evidence: its +flattening of the large decode cone timed out. The milestone runner instead +proves two concrete RTL partitions with `-verify`: a reset-established packet +receiver accepts the exact valid zero-length STATUS frame (including CRC), and +the shipped TX serializer emits its INFO envelope and CRC through two fixed +ready-low cycles. The existing full-frontend executable test supplies the +connected non-vacuous SET path: accepted frame, decode, ALU completion, +response payload, and a 12-cycle output stall. + +This is a bounded composed milestone, not a monolithic end-to-end formal proof: +the formal partitions do not prove that the controller connects every accepted +frame to every response, do not quantify over arbitrary/unbounded +backpressure, and do not establish release sequential equivalence. Reset +coverage remains the separate receiver reset proof. Release equivalence and +ASIC readiness remain explicit BLOCKS pending a reviewed phase-complete +architecture transition/refinement model. diff --git a/formal/lsc1_packet_rx_status_accept.sv b/formal/lsc1_packet_rx_status_accept.sv new file mode 100644 index 0000000..e56fc80 --- /dev/null +++ b/formal/lsc1_packet_rx_status_accept.sv @@ -0,0 +1,43 @@ +`default_nettype none +// Bounded, concrete accepted-request partition. The byte stream is a valid +// zero-length STATUS request (including its wire CRC); no parser state is +// assumed. This deliberately checks only parser acceptance, not controller +// decode or release equivalence. +module lsc1_packet_rx_status_accept; + (* anyseq *) reg clk; + reg [4:0] step; + wire rst_n = step != 0; + wire abort = 1'b0, frame_ready = 1'b0; + wire rx_valid = step >= 1 && step <= 10; + reg [7:0] rx_data; + wire rx_ready, frame_valid, fault_valid, busy; + wire [7:0] frame_opcode, fault_status; + wire [15:0] frame_length; + wire [2047:0] frame_payload; + wire [2:0] arch_state, arch_header_index; + wire [15:0] arch_body_index, arch_declared_length; + wire [7:0] arch_version, arch_opcode, arch_flags; + wire [31:0] arch_crc, arch_received_crc; + + // Keep this a mux chain rather than a ROM: Yosys SAT deliberately does not + // import the generated $mem cell for a case-table harness. + always @(*) if (step == 1) rx_data = 8'ha1; + else if (step == 2) rx_data = 8'h01; + else if (step == 3) rx_data = 8'h13; + else if (step == 7) rx_data = 8'h29; + else if (step == 8) rx_data = 8'hb2; + else if (step == 9) rx_data = 8'h4e; + else if (step == 10) rx_data = 8'h1c; + else rx_data = 0; + lsc1_packet_rx dut (.*); + always @(*) assume(clk == 1'b1); + always @(posedge clk) begin + step <= step + 1'b1; + if (step == 11) begin + assert(frame_valid && !fault_valid); + assert(frame_opcode == 8'h13 && frame_length == 0); + assert(arch_opcode == 8'h13 && arch_declared_length == 0); + end + end +endmodule +`default_nettype wire diff --git a/formal/lsc1_packet_rx_status_accept.ys b/formal/lsc1_packet_rx_status_accept.ys new file mode 100644 index 0000000..9764d39 --- /dev/null +++ b/formal/lsc1_packet_rx_status_accept.ys @@ -0,0 +1,6 @@ +read_verilog -formal -sv asic_core/rtl/lsc1_packet_rx.sv formal/lsc1_packet_rx_status_accept.sv +prep -top lsc1_packet_rx_status_accept +flatten +opt +select -module lsc1_packet_rx_status_accept +sat -seq 13 -prove-asserts -verify -set-assumes -set-init-zero diff --git a/formal/lsc1_packet_tx_status_response.sv b/formal/lsc1_packet_tx_status_response.sv new file mode 100644 index 0000000..2081b7d --- /dev/null +++ b/formal/lsc1_packet_tx_status_response.sv @@ -0,0 +1,40 @@ +`default_nettype none +// Bounded serializer partition for the INFO response selected by STATUS. +// start is concrete and two ready-low cycles exercise backpressure. The +// response is the zero-payload INFO envelope, whose CRC is E7BF94B. +module lsc1_packet_tx_status_response; + (* anyseq *) reg clk; + reg [4:0] step; + wire rst_n = step != 0; + wire abort = 1'b0; + wire start = step == 1; + wire [7:0] status = 8'h03; + wire [15:0] payload_length = 0; + wire [543:0] payload = 0; + wire tx_ready = !(step == 3 || step == 5); + wire busy, done_pulse, tx_valid; + wire [7:0] tx_data; + wire [31:0] payload_crc; + wire [15:0] arch_index, arch_length; + wire [7:0] arch_status; + wire [543:0] arch_payload; + wire arch_active, arch_done_pulse; + wire [31:0] arch_saved_crc, arch_envelope_crc_work, arch_payload_crc_work, arch_payload_crc; + lsc1_packet_tx dut (.*); + always @(*) assume(clk == 1'b1); + always @(posedge clk) begin + step <= step + 1'b1; + if (arch_active) begin + assert(tx_valid && busy && arch_status == 8'h03 && arch_length == 0); + case (arch_index) + 0: assert(tx_data == 8'h5a); 1: assert(tx_data == 8'h01); + 2: assert(tx_data == 8'h03); 3: assert(tx_data == 0); + 4: assert(tx_data == 0); 5: assert(tx_data == 8'h4b); + 6: assert(tx_data == 8'hf9); 7: assert(tx_data == 8'h7b); + 8: assert(tx_data == 8'h0e); default: assert(1'b0); + endcase + end + if (step == 13) assert(done_pulse && !arch_active && payload_crc == 0); + end +endmodule +`default_nettype wire diff --git a/formal/lsc1_packet_tx_status_response.ys b/formal/lsc1_packet_tx_status_response.ys new file mode 100644 index 0000000..7d8272e --- /dev/null +++ b/formal/lsc1_packet_tx_status_response.ys @@ -0,0 +1,6 @@ +read_verilog -formal -sv asic_core/rtl/lsc1_packet_tx.sv formal/lsc1_packet_tx_status_response.sv +prep -top lsc1_packet_tx_status_response +flatten +opt +select -module lsc1_packet_tx_status_response +sat -seq 14 -prove-asserts -verify -set-assumes -set-init-zero diff --git a/results/frontend-bounded-path-20260728/README.md b/results/frontend-bounded-path-20260728/README.md new file mode 100644 index 0000000..b096dbc --- /dev/null +++ b/results/frontend-bounded-path-20260728/README.md @@ -0,0 +1,31 @@ +# Bounded frontend accepted-path partitions + +Immutable starting source: `fb3c063ca280e71f8721fefe858d10ce8cca772a`. +This receipt is intentionally a bounded composed milestone, not a release +sequential-equivalence or ASIC-readiness claim. + +## Commands and outcome + +`tools/run_arch_state_milestones.sh results/frontend-bounded-path-20260728` +exited `0` in `13.93` seconds on Yosys 0.33. Its saved logs record successful +receiver-reset, STATUS-acceptance, and stalled INFO-response serializer formal +gates, plus focused RTL, executable boundary, differential, and mutation +gates. The standalone measured formal durations were 6.04 seconds for STATUS +acceptance and under one second for response serialization. + +The STATUS acceptance proof uses its exact wire CRC `1c4eb229`; the INFO +serializer proof checks CRC `0e7bf94b` and two fixed ready-low cycles. +`SHA256SUMS` covers every captured log, and `versions-and-inputs.log` records +the exact source tree used by the runner. + +## Claim boundary and remaining block + +The formal partitions use actual shipped RX and TX RTL and `sat -verify`; no +cutpoint, black box, symbolic bridge, disabled check, or timeout-as-PASS is +used. The full frontend SET simulation connects accepted input, controller +decode/compute, response construction, and a 12-cycle output stall. + +This does **not** prove the controller connection for all inputs, arbitrary or +unbounded backpressure, reset for the full frontend harness, release +sequential equivalence, or ASIC readiness. The unresolved release-equivalence +diagnostic remains an explicit BLOCK. diff --git a/results/frontend-bounded-path-20260728/SHA256SUMS b/results/frontend-bounded-path-20260728/SHA256SUMS new file mode 100644 index 0000000..6919a19 --- /dev/null +++ b/results/frontend-bounded-path-20260728/SHA256SUMS @@ -0,0 +1,12 @@ +f1943b886302ad476759f2ac1f058605093ad61dca0927bcc0b274ccb42189a3 results/frontend-bounded-path-20260728/bounded-path-check.log +1b8f990615dee4668360d3167ab25636d4fe5d4d247b2e9bf6fe186385a5a36d results/frontend-bounded-path-20260728/bounded-path-mutation.log +ae9e589efd7641414500edbb23a8b8597876be964a0d534037a4d10917d4e041 results/frontend-bounded-path-20260728/differential.log +4c8f5cc3ce7dc012f38e9889075fef35fa19946a56ee529e1e10bc8d2e77e7b8 results/frontend-bounded-path-20260728/interface-coverage.log +fc001e2743facc2425c52a0f242205787fde5ba420f9db382e52c7ed174ab2be results/frontend-bounded-path-20260728/mutation.log +bb3de711cb2dbeed9b1a38277f135e599e2badbd3c5afc888f9d3a4310333cd5 results/frontend-bounded-path-20260728/one-cycle-check.log +bd99ca75ce7a7a81f797afc944bf7b7b142a33131625150dd12f6eeab1c5cb6a results/frontend-bounded-path-20260728/one-cycle-executable.log +ec4fa536210eb266d5821d66046028cd002e53d75fa1a74798279bc1df0b613f results/frontend-bounded-path-20260728/reset-idle.log +3ad87e37eb2d7490f4416824eb162010a2e8d83a943889a06261d55fa5266ff4 results/frontend-bounded-path-20260728/rtl.log +287599e8b4dbd67d065d71d747e83198206b5e3371eaa78216ab105080fdc834 results/frontend-bounded-path-20260728/status-accept.log +65c58abca21232f8f0d79ae1751affa91833f06f0d0924bbe336d47c6fbaa032 results/frontend-bounded-path-20260728/status-response.log +edf379e044ac6e7d5ce38d0061c944e523fa7731640373733f36e353ef1484cd results/frontend-bounded-path-20260728/versions-and-inputs.log diff --git a/results/frontend-bounded-path-20260728/bounded-path-check.log b/results/frontend-bounded-path-20260728/bounded-path-check.log new file mode 100644 index 0000000..cd6d917 --- /dev/null +++ b/results/frontend-bounded-path-20260728/bounded-path-check.log @@ -0,0 +1 @@ +bounded path: concrete STATUS request acceptance and stalled INFO serialization are asserted diff --git a/results/frontend-bounded-path-20260728/bounded-path-mutation.log b/results/frontend-bounded-path-20260728/bounded-path-mutation.log new file mode 100644 index 0000000..d7d51de --- /dev/null +++ b/results/frontend-bounded-path-20260728/bounded-path-mutation.log @@ -0,0 +1,3 @@ +make: Entering directory '/tmp/lean-silicon-pr30.0LkbvS/test/packet_frontend' +PASS: bounded INFO-status serializer assertion detected mutation +make: Leaving directory '/tmp/lean-silicon-pr30.0LkbvS/test/packet_frontend' diff --git a/results/frontend-bounded-path-20260728/differential.log b/results/frontend-bounded-path-20260728/differential.log new file mode 100644 index 0000000..6b5f220 --- /dev/null +++ b/results/frontend-bounded-path-20260728/differential.log @@ -0,0 +1,9 @@ +test_adversarial_jump_inverse_and_xor_backsolve_match_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_adversarial_jump_inverse_and_xor_backsolve_match_model) ... ok +test_deref_and_jump_faults_match_the_executable_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_faults_match_the_executable_model) ... ok +test_deref_and_jump_match_the_executable_model (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_deref_and_jump_match_the_executable_model) ... ok +test_seeded_set_xor_mul_and_frame_faults (sim.test_packet_frontend_rtl_differential.PacketFrontendRtlDifferentialTests.test_seeded_set_xor_mul_and_frame_faults) ... ok + +---------------------------------------------------------------------- +Ran 4 tests in 1.088s + +OK diff --git a/results/frontend-bounded-path-20260728/interface-coverage.log b/results/frontend-bounded-path-20260728/interface-coverage.log new file mode 100644 index 0000000..ba0d6a1 --- /dev/null +++ b/results/frontend-bounded-path-20260728/interface-coverage.log @@ -0,0 +1 @@ +arch-state map: 94 fields; widths, 91 registered elements, output reconstruction, and mutations covered diff --git a/results/frontend-bounded-path-20260728/mutation.log b/results/frontend-bounded-path-20260728/mutation.log new file mode 100644 index 0000000..297828d --- /dev/null +++ b/results/frontend-bounded-path-20260728/mutation.log @@ -0,0 +1,3 @@ +make: Entering directory '/tmp/lean-silicon-pr30.0LkbvS/test/packet_frontend' +PASS: BUSY, SET value, RETIRE ID, ABORT, abort status, length-order, and profile mutations were detected +make: Leaving directory '/tmp/lean-silicon-pr30.0LkbvS/test/packet_frontend' diff --git a/results/frontend-bounded-path-20260728/one-cycle-check.log b/results/frontend-bounded-path-20260728/one-cycle-check.log new file mode 100644 index 0000000..c2ec3d8 --- /dev/null +++ b/results/frontend-bounded-path-20260728/one-cycle-check.log @@ -0,0 +1 @@ +one-cycle boundary: retained frontend abort and quiescent-stutter state is covered diff --git a/results/frontend-bounded-path-20260728/one-cycle-executable.log b/results/frontend-bounded-path-20260728/one-cycle-executable.log new file mode 100644 index 0000000..fbd0754 --- /dev/null +++ b/results/frontend-bounded-path-20260728/one-cycle-executable.log @@ -0,0 +1,17 @@ +make: Entering directory '/tmp/lean-silicon-pr30.0LkbvS/test/packet_frontend' +iverilog -g2012 -Wall -s tb_lsc1_packet_frontend_one_cycle_boundary -o tb_lsc1_packet_frontend_one_cycle_boundary.vvp ../../asic_core/rtl/lsc1_packet_rx.sv ../../asic_core/rtl/lsc1_packet_tx.sv ../../asic_core/rtl/gf2n_mul_bitstream.sv ../../asic_core/rtl/gf128_mul_bitstream.sv ../../asic_core/rtl/leanvm_b_stream_alu.sv ../../asic_core/rtl/lsc1_stream_adapter.sv ../../asic_core/rtl/lsc1_field_encoder.sv ../../asic_core/rtl/lsc1_packet_frontend.sv tb_lsc1_packet_frontend_one_cycle_boundary.sv +warning: Some design elements have no explicit time unit and/or + : time precision. This may cause confusing timing results. + : Affected design elements are: + : -- module gf128_mul_bitstream declared here: ../../asic_core/rtl/gf128_mul_bitstream.sv:9 + : -- module gf2n_mul_bitstream declared here: ../../asic_core/rtl/gf2n_mul_bitstream.sv:22 + : -- module leanvm_b_stream_alu declared here: ../../asic_core/rtl/leanvm_b_stream_alu.sv:28 + : -- module lsc1_field_encoder declared here: ../../asic_core/rtl/lsc1_field_encoder.sv:6 + : -- module lsc1_packet_frontend declared here: ../../asic_core/rtl/lsc1_packet_frontend.sv:6 + : -- module lsc1_packet_rx declared here: ../../asic_core/rtl/lsc1_packet_rx.sv:5 + : -- module lsc1_packet_tx declared here: ../../asic_core/rtl/lsc1_packet_tx.sv:4 + : -- module lsc1_stream_adapter declared here: ../../asic_core/rtl/lsc1_stream_adapter.sv:6 +vvp tb_lsc1_packet_frontend_one_cycle_boundary.vvp +PASS: full frontend registered reset/abort/idle boundary model +tb_lsc1_packet_frontend_one_cycle_boundary.sv:50: $finish called at 75000 (1ps) +make: Leaving directory '/tmp/lean-silicon-pr30.0LkbvS/test/packet_frontend' diff --git a/results/frontend-bounded-path-20260728/reset-idle.log b/results/frontend-bounded-path-20260728/reset-idle.log new file mode 100644 index 0000000..1a5e59d --- /dev/null +++ b/results/frontend-bounded-path-20260728/reset-idle.log @@ -0,0 +1,3088 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Executing script file `formal/lsc1_packet_frontend_arch_reset_idle.ys' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_rx.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: formal/lsc1_packet_frontend_arch_reset_idle.sv +Parsing formal SystemVerilog input from `formal/lsc1_packet_frontend_arch_reset_idle.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_frontend_arch_reset_idle'. +Successfully finished Verilog frontend. + +3. Executing PREP pass. + +3.1. Executing HIERARCHY pass (managing design hierarchy). + +3.1.1. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend_arch_reset_idle +Used module: \lsc1_packet_rx + +3.1.2. Analyzing design hierarchy.. +Top module: \lsc1_packet_frontend_arch_reset_idle +Used module: \lsc1_packet_rx +Removed 0 unused modules. +Module lsc1_packet_frontend_arch_reset_idle directly or indirectly contains formal properties -> setting "keep" attribute. + +3.2. Executing PROC pass (convert processes to netlists). + +3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 11 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_rx.sv:71$23 in module lsc1_packet_rx. +Removed a total of 0 dead cases. + +3.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 25 assignments to connections. + +3.2.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$294'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_EN = 1'0 +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$292'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_EN = 1'0 +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$290'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_EN = 1'0 +Found init rule in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$288'. + Set init value: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN = 1'0 + +3.2.5. Executing PROC_ARST pass (detect async resets in processes). + +3.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$294'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$292'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$290'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$288'. +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + 1/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN[0:0]$255 + 2/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_CHECK[0:0]$254 + 3/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_EN[0:0]$257 + 4/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_CHECK[0:0]$256 + 5/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_EN[0:0]$259 + 6/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_CHECK[0:0]$258 + 7/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_EN[0:0]$261 + 8/8: $0$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_CHECK[0:0]$260 +Creating decoders for process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. +Creating decoders for process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + 1/89: $0\received_crc[31:0] [31:24] + 2/89: $0\received_crc[31:0] [23:16] + 3/89: $0\received_crc[31:0] [15:8] + 4/89: $0\received_crc[31:0] [7:0] + 5/89: $5$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$185 + 6/89: $5$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$184 + 7/89: $5$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$186 + 8/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$177 + 9/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$180 + 10/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$181 + 11/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$179 + 12/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$178 + 13/89: $4$lookahead\frame_payload$22[2047:0]$182 + 14/89: $4$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$176 + 15/89: $4$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$175 + 16/89: $4$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$174 + 17/89: $0\declared_length[15:0] [15:8] + 18/89: $0\declared_length[15:0] [7:0] + 19/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$103 + 20/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$102 + 21/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$101 + 22/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$85 + 23/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$84 + 24/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$83 + 25/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$82 + 26/89: $3$lookahead\frame_payload$22[2047:0]$99 + 27/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$98 + 28/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$97 + 29/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$96 + 30/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$95 + 31/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$94 + 32/89: $3$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$93 + 33/89: $3$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$92 + 34/89: $3$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$91 + 35/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$90 + 36/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$89 + 37/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$88 + 38/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$87 + 39/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$86 + 40/89: $2$lookahead\frame_payload$22[2047:0]$81 + 41/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$80 + 42/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$79 + 43/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$78 + 44/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$77 + 45/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$76 + 46/89: $2$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$75 + 47/89: $2$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$74 + 48/89: $2$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$73 + 49/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$72 + 50/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$71 + 51/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$70 + 52/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$69 + 53/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$68 + 54/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$67 + 55/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$66 + 56/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$65 + 57/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$64 + 58/89: $1$lookahead\frame_payload$22[2047:0]$61 + 59/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$60 + 60/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$59 + 61/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$58 + 62/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$57 + 63/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$56 + 64/89: $1$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$55 + 65/89: $1$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$54 + 66/89: $1$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$53 + 67/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$52 + 68/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$51 + 69/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$50 + 70/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$49 + 71/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$48 + 72/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$47 + 73/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$46 + 74/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$45 + 75/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$44 + 76/89: $5$lookahead\frame_payload$22[2047:0]$187 + 77/89: $0\crc[31:0] + 78/89: $0\flags[7:0] + 79/89: $0\opcode[7:0] + 80/89: $0\version[7:0] + 81/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$104 + 82/89: $0\body_index[15:0] + 83/89: $0\header_index[2:0] + 84/89: $0\state[2:0] + 85/89: $0\fault_status[7:0] + 86/89: $0\fault_valid[0:0] + 87/89: $0\frame_length[15:0] + 88/89: $0\frame_opcode[7:0] + 89/89: $0\frame_valid[0:0] + +3.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$239_CHECK' from process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. +No latch inferred for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$239_EN' from process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. + +3.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1240' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1241' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1242' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:21$241_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1243' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1244' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:22$242_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1245' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_CHECK' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1246' with positive edge clock. +Creating register for signal `\lsc1_packet_frontend_arch_reset_idle.$formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:23$243_EN' using process `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. + created $dff cell `$procdff$1247' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1248' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1249' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1250' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_payload' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1251' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1252' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_status' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1253' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\state' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1254' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\header_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1255' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\body_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1256' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\declared_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1257' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\version' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1258' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1259' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\flags' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1260' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1261' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\received_crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1262' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1263' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1264' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1265' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1266' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1267' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1268' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1269' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1270' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1271' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1272' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1273' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1274' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1275' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1276' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1277' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1278' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1279' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$lookahead\frame_payload$22' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1280' with positive edge clock. + +3.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$294'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$292'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$290'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:0$288'. +Found and cleaned up 1 empty switch in `\lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:19$253'. +Removing empty process `lsc1_packet_frontend_arch_reset_idle.$proc$formal/lsc1_packet_frontend_arch_reset_idle.sv:18$249'. +Found and cleaned up 14 empty switches in `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. +Removing empty process `lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. +Cleaned up 15 empty switches. + +3.2.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + +Optimizing module lsc1_packet_rx. + + +3.3. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 215 unused cells and 635 unused wires. + + +3.5. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_frontend_arch_reset_idle... +Checking module lsc1_packet_rx... +Found and reported 0 problems. + +3.6. Executing OPT pass (performing simple optimizations). + +3.6.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.6.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. + +Finding identical cells in module `\lsc1_packet_rx'. + +Removed a total of 55 cells. + +3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$488. + dead port 2/2 on $mux $procmux$490. + dead port 1/2 on $mux $procmux$493. + dead port 2/2 on $mux $procmux$649. + dead port 1/2 on $mux $procmux$652. + dead port 1/2 on $mux $procmux$780. + dead port 2/2 on $mux $procmux$944. + dead port 2/2 on $mux $procmux$946. + dead port 2/2 on $mux $procmux$948. + dead port 1/2 on $mux $procmux$951. +Removed 10 multiplexer ports. + + +3.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. + Optimizing cells in module \lsc1_packet_rx. + New ctrl vector for $pmux cell $procmux$1083: { $auto$opt_reduce.cc:134:opt_pmux$1332 $procmux$1038_CMP } + Optimizing cells in module \lsc1_packet_rx. +Performed a total of 1 changes. + +3.6.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Finding identical cells in module `\lsc1_packet_rx'. + +Removed a total of 15 cells. + +3.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 0 unused cells and 88 unused wires. + + +3.6.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.6.8. Rerunning OPT passes. (Maybe there is more to do..) + +3.6.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.6.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. + Optimizing cells in module \lsc1_packet_rx. +Performed a total of 0 changes. + +3.6.11. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Finding identical cells in module `\lsc1_packet_rx'. +Removed a total of 0 cells. + +3.6.12. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. + +3.6.13. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.6.14. Finished OPT passes. (There is nothing left to do.) + +3.7. Executing WREDUCE pass (reducing word size of cells). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$ne$asic_core/rtl/lsc1_packet_rx.sv:60$16 ($ne). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1283 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1285 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1287 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1289 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1291 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1293 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1295 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1297 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1299 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1301 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1303 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1305 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1307 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1309 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1311 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1313 ($not). +Removed top 7 bits (of 16) from port B of cell lsc1_packet_rx.$gt$asic_core/rtl/lsc1_packet_rx.sv:122$171 ($gt). +Removed top 7 bits (of 16) from port B of cell lsc1_packet_rx.$lt$asic_core/rtl/lsc1_packet_rx.sv:135$183 ($lt). +Removed top 28 bits (of 32) from port B of cell lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188 ($mul). +Removed top 12 bits (of 32) from port Y of cell lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188 ($mul). +Removed top 12 bits (of 32) from port A of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 11 bits (of 32) from port Y of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 11 bits (of 33) from port A of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Converting cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub) from signed to unsigned. +Removed top 10 bits (of 33) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 1 bits (of 22) from port A of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 1 bits (of 23) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 11 bits (of 33) from port A of cell lsc1_packet_rx.$neg$asic_core/rtl/lsc1_packet_rx.sv:0$191 ($neg). +Removed top 15 bits (of 32) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:139$233 ($sub). +Removed top 7 bits (of 8) from port B of cell lsc1_packet_rx.$ne$asic_core/rtl/lsc1_packet_rx.sv:147$236 ($ne). +Removed top 24 bits (of 32) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1281 ($not). +Removed top 30 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$331_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$348_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1012_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1035_CMP0 ($eq). +Removed top 30 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$1073_CMP0 ($eq). +Removed top 2 bits (of 3) from mux cell lsc1_packet_rx.$procmux$1081 ($mux). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1085_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1086_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1087_CMP0 ($eq). +Removed top 1 bits (of 3) from mux cell lsc1_packet_rx.$procmux$1091 ($mux). +Removed top 11 bits (of 32) from wire lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189_Y. +Removed top 12 bits (of 32) from wire lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188_Y. +Removed top 2 bits (of 3) from wire lsc1_packet_rx.$procmux$1081_Y. +Removed top 1 bits (of 3) from wire lsc1_packet_rx.$procmux$1091_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$110_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$114_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$118_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$122_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$126_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$130_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$134_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$139_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$143_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$147_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$151_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$155_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$159_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$163_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$167_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$109_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$113_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$117_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$121_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$125_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$129_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$133_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$142_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$146_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$150_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$154_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$158_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$162_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$166_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$xor$asic_core/rtl/lsc1_packet_rx.sv:53$138_Y. + +3.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 0 unused cells and 34 unused wires. + + +3.9. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.10. Executing OPT pass (performing simple optimizations). + +3.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. +Optimizing module lsc1_packet_rx. + +3.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Finding identical cells in module `\lsc1_packet_rx'. +Removed a total of 0 cells. + +3.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Finding unused cells or wires in module \lsc1_packet_rx.. + +3.10.4. Finished fast OPT passes. + +3.11. Printing statistics. + +=== lsc1_packet_frontend_arch_reset_idle === + + Number of wires: 48 + Number of wire bits: 2248 + Number of public wires: 23 + Number of public wire bits: 2223 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 36 + $anyseq 5 + $assert 4 + $assume 1 + $dff 5 + $eq 1 + $logic_and 8 + $logic_not 11 + lsc1_packet_rx 1 + +=== lsc1_packet_rx === + + Number of wires: 237 + Number of wire bits: 25229 + Number of public wires: 33 + Number of public wire bits: 2350 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 211 + $add 3 + $and 1 + $dff 15 + $eq 9 + $gt 1 + $logic_and 5 + $logic_not 6 + $logic_or 3 + $lt 2 + $mul 1 + $mux 120 + $ne 4 + $neg 1 + $not 19 + $or 1 + $pmux 12 + $reduce_bool 2 + $reduce_or 1 + $shift 2 + $sub 2 + $xor 1 + +=== design hierarchy === + + lsc1_packet_frontend_arch_reset_idle 1 + lsc1_packet_rx 1 + + Number of wires: 285 + Number of wire bits: 27477 + Number of public wires: 56 + Number of public wire bits: 4573 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 246 + $add 3 + $and 1 + $anyseq 5 + $assert 4 + $assume 1 + $dff 20 + $eq 10 + $gt 1 + $logic_and 13 + $logic_not 17 + $logic_or 3 + $lt 2 + $mul 1 + $mux 120 + $ne 4 + $neg 1 + $not 19 + $or 1 + $pmux 12 + $reduce_bool 2 + $reduce_or 1 + $shift 2 + $sub 2 + $xor 1 + +3.12. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_frontend_arch_reset_idle... +Checking module lsc1_packet_rx... +Found and reported 0 problems. + +4. Executing FLATTEN pass (flatten design). +Deleting now unused module lsc1_packet_rx. + + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. + +Removed a total of 20 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\dut.$procmux$539. + dead port 2/2 on $mux $flatten\dut.$procmux$539. + dead port 1/2 on $mux $flatten\dut.$procmux$537. + dead port 2/2 on $mux $flatten\dut.$procmux$537. + dead port 1/2 on $mux $flatten\dut.$procmux$535. + dead port 2/2 on $mux $flatten\dut.$procmux$535. + dead port 1/2 on $mux $flatten\dut.$procmux$486. + dead port 2/2 on $mux $flatten\dut.$procmux$486. + dead port 1/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$137. + dead port 2/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$137. + dead port 1/2 on $mux $flatten\dut.$procmux$373. + dead port 2/2 on $mux $flatten\dut.$procmux$373. + dead port 1/3 on $pmux $flatten\dut.$procmux$370. + dead port 2/3 on $pmux $flatten\dut.$procmux$370. + dead port 3/3 on $pmux $flatten\dut.$procmux$370. + dead port 1/2 on $mux $flatten\dut.$procmux$368. + dead port 2/2 on $mux $flatten\dut.$procmux$368. + dead port 1/2 on $mux $flatten\dut.$procmux$365. + dead port 2/2 on $mux $flatten\dut.$procmux$365. + dead port 1/2 on $mux $flatten\dut.$procmux$355. + dead port 2/2 on $mux $flatten\dut.$procmux$355. + dead port 1/3 on $pmux $flatten\dut.$procmux$352. + dead port 2/3 on $pmux $flatten\dut.$procmux$352. + dead port 3/3 on $pmux $flatten\dut.$procmux$352. + dead port 1/2 on $mux $flatten\dut.$procmux$350. + dead port 2/2 on $mux $flatten\dut.$procmux$350. + dead port 1/2 on $mux $flatten\dut.$procmux$347. + dead port 2/2 on $mux $flatten\dut.$procmux$347. + dead port 1/2 on $mux $flatten\dut.$procmux$338. + dead port 2/2 on $mux $flatten\dut.$procmux$338. + dead port 1/3 on $pmux $flatten\dut.$procmux$335. + dead port 2/3 on $pmux $flatten\dut.$procmux$335. + dead port 3/3 on $pmux $flatten\dut.$procmux$335. + dead port 1/2 on $mux $flatten\dut.$procmux$333. + dead port 2/2 on $mux $flatten\dut.$procmux$333. + dead port 1/2 on $mux $flatten\dut.$procmux$330. + dead port 2/2 on $mux $flatten\dut.$procmux$330. + dead port 1/2 on $mux $flatten\dut.$procmux$322. + dead port 2/2 on $mux $flatten\dut.$procmux$322. + dead port 1/3 on $pmux $flatten\dut.$procmux$319. + dead port 2/3 on $pmux $flatten\dut.$procmux$319. + dead port 3/3 on $pmux $flatten\dut.$procmux$319. + dead port 1/2 on $mux $flatten\dut.$procmux$317. + dead port 2/2 on $mux $flatten\dut.$procmux$317. + dead port 1/2 on $mux $flatten\dut.$procmux$314. + dead port 2/2 on $mux $flatten\dut.$procmux$314. + dead port 1/2 on $mux $flatten\dut.$procmux$1235. + dead port 2/2 on $mux $flatten\dut.$procmux$1235. + dead port 1/2 on $mux $flatten\dut.$procmux$1233. + dead port 2/2 on $mux $flatten\dut.$procmux$1233. + dead port 1/2 on $mux $flatten\dut.$procmux$1231. + dead port 2/2 on $mux $flatten\dut.$procmux$1231. + dead port 1/2 on $mux $flatten\dut.$procmux$1228. + dead port 2/2 on $mux $flatten\dut.$procmux$1228. + dead port 1/2 on $mux $flatten\dut.$procmux$1226. + dead port 2/2 on $mux $flatten\dut.$procmux$1226. + dead port 1/2 on $mux $flatten\dut.$procmux$1223. + dead port 2/2 on $mux $flatten\dut.$procmux$1223. + dead port 1/2 on $mux $flatten\dut.$procmux$1220. + dead port 2/2 on $mux $flatten\dut.$procmux$1220. + dead port 1/2 on $mux $flatten\dut.$procmux$1215. + dead port 2/2 on $mux $flatten\dut.$procmux$1215. + dead port 1/2 on $mux $flatten\dut.$procmux$1210. + dead port 2/2 on $mux $flatten\dut.$procmux$1210. + dead port 1/2 on $mux $flatten\dut.$procmux$1208. + dead port 2/2 on $mux $flatten\dut.$procmux$1208. + dead port 1/2 on $mux $flatten\dut.$procmux$1206. + dead port 2/2 on $mux $flatten\dut.$procmux$1206. + dead port 1/2 on $mux $flatten\dut.$procmux$1203. + dead port 2/2 on $mux $flatten\dut.$procmux$1203. + dead port 1/2 on $mux $flatten\dut.$procmux$1201. + dead port 2/2 on $mux $flatten\dut.$procmux$1201. + dead port 1/2 on $mux $flatten\dut.$procmux$1198. + dead port 2/2 on $mux $flatten\dut.$procmux$1198. + dead port 1/2 on $mux $flatten\dut.$procmux$1195. + dead port 2/2 on $mux $flatten\dut.$procmux$1195. + dead port 1/2 on $mux $flatten\dut.$procmux$1187. + dead port 2/2 on $mux $flatten\dut.$procmux$1187. + dead port 1/2 on $mux $flatten\dut.$procmux$1185. + dead port 2/2 on $mux $flatten\dut.$procmux$1185. + dead port 1/2 on $mux $flatten\dut.$procmux$1183. + dead port 2/2 on $mux $flatten\dut.$procmux$1183. + dead port 1/2 on $mux $flatten\dut.$procmux$1180. + dead port 2/2 on $mux $flatten\dut.$procmux$1180. + dead port 1/2 on $mux $flatten\dut.$procmux$1178. + dead port 2/2 on $mux $flatten\dut.$procmux$1178. + dead port 1/2 on $mux $flatten\dut.$procmux$1175. + dead port 2/2 on $mux $flatten\dut.$procmux$1175. + dead port 1/2 on $mux $flatten\dut.$procmux$1172. + dead port 2/2 on $mux $flatten\dut.$procmux$1172. + dead port 1/2 on $mux $flatten\dut.$procmux$1164. + dead port 2/2 on $mux $flatten\dut.$procmux$1164. + dead port 1/2 on $mux $flatten\dut.$procmux$1161. + dead port 2/2 on $mux $flatten\dut.$procmux$1161. + dead port 1/2 on $mux $flatten\dut.$procmux$1157. + dead port 2/2 on $mux $flatten\dut.$procmux$1157. + dead port 1/2 on $mux $flatten\dut.$procmux$1155. + dead port 2/2 on $mux $flatten\dut.$procmux$1155. + dead port 1/4 on $pmux $flatten\dut.$procmux$1151. + dead port 2/4 on $pmux $flatten\dut.$procmux$1151. + dead port 3/4 on $pmux $flatten\dut.$procmux$1151. + dead port 4/4 on $pmux $flatten\dut.$procmux$1151. + dead port 1/2 on $mux $flatten\dut.$procmux$1149. + dead port 2/2 on $mux $flatten\dut.$procmux$1149. + dead port 1/2 on $mux $flatten\dut.$procmux$1146. + dead port 2/2 on $mux $flatten\dut.$procmux$1146. + dead port 1/2 on $mux $flatten\dut.$procmux$1144. + dead port 2/2 on $mux $flatten\dut.$procmux$1144. + dead port 1/2 on $mux $flatten\dut.$procmux$1141. + dead port 2/2 on $mux $flatten\dut.$procmux$1141. + dead port 1/2 on $mux $flatten\dut.$procmux$1138. + dead port 2/2 on $mux $flatten\dut.$procmux$1138. + dead port 1/2 on $mux $flatten\dut.$procmux$1133. + dead port 2/2 on $mux $flatten\dut.$procmux$1133. + dead port 1/2 on $mux $flatten\dut.$procmux$1128. + dead port 2/2 on $mux $flatten\dut.$procmux$1128. + dead port 1/2 on $mux $flatten\dut.$procmux$1125. + dead port 2/2 on $mux $flatten\dut.$procmux$1125. + dead port 1/2 on $mux $flatten\dut.$procmux$1121. + dead port 2/2 on $mux $flatten\dut.$procmux$1121. + dead port 1/2 on $mux $flatten\dut.$procmux$1119. + dead port 2/2 on $mux $flatten\dut.$procmux$1119. + dead port 1/4 on $pmux $flatten\dut.$procmux$1115. + dead port 2/4 on $pmux $flatten\dut.$procmux$1115. + dead port 3/4 on $pmux $flatten\dut.$procmux$1115. + dead port 4/4 on $pmux $flatten\dut.$procmux$1115. + dead port 1/2 on $mux $flatten\dut.$procmux$1113. + dead port 2/2 on $mux $flatten\dut.$procmux$1113. + dead port 1/2 on $mux $flatten\dut.$procmux$1110. + dead port 2/2 on $mux $flatten\dut.$procmux$1110. + dead port 1/2 on $mux $flatten\dut.$procmux$1108. + dead port 2/2 on $mux $flatten\dut.$procmux$1108. + dead port 1/2 on $mux $flatten\dut.$procmux$1105. + dead port 2/2 on $mux $flatten\dut.$procmux$1105. + dead port 1/2 on $mux $flatten\dut.$procmux$1102. + dead port 2/2 on $mux $flatten\dut.$procmux$1102. + dead port 1/2 on $mux $flatten\dut.$procmux$1094. + dead port 2/2 on $mux $flatten\dut.$procmux$1094. + dead port 1/2 on $mux $flatten\dut.$procmux$1091. + dead port 2/2 on $mux $flatten\dut.$procmux$1091. + dead port 1/3 on $pmux $flatten\dut.$procmux$1083. + dead port 2/3 on $pmux $flatten\dut.$procmux$1083. + dead port 3/3 on $pmux $flatten\dut.$procmux$1083. + dead port 1/2 on $mux $flatten\dut.$procmux$1081. + dead port 2/2 on $mux $flatten\dut.$procmux$1081. + dead port 1/4 on $pmux $flatten\dut.$procmux$1077. + dead port 2/4 on $pmux $flatten\dut.$procmux$1077. + dead port 3/4 on $pmux $flatten\dut.$procmux$1077. + dead port 4/4 on $pmux $flatten\dut.$procmux$1077. + dead port 1/2 on $mux $flatten\dut.$procmux$1075. + dead port 2/2 on $mux $flatten\dut.$procmux$1075. + dead port 1/2 on $mux $flatten\dut.$procmux$1072. + dead port 2/2 on $mux $flatten\dut.$procmux$1072. + dead port 1/2 on $mux $flatten\dut.$procmux$1062. + dead port 2/2 on $mux $flatten\dut.$procmux$1062. + dead port 1/2 on $mux $flatten\dut.$procmux$1060. + dead port 2/2 on $mux $flatten\dut.$procmux$1060. + dead port 1/2 on $mux $flatten\dut.$procmux$1055. + dead port 2/2 on $mux $flatten\dut.$procmux$1055. + dead port 1/2 on $mux $flatten\dut.$procmux$1052. + dead port 2/2 on $mux $flatten\dut.$procmux$1052. + dead port 1/3 on $pmux $flatten\dut.$procmux$1049. + dead port 2/3 on $pmux $flatten\dut.$procmux$1049. + dead port 3/3 on $pmux $flatten\dut.$procmux$1049. + dead port 1/2 on $mux $flatten\dut.$procmux$1041. + dead port 2/2 on $mux $flatten\dut.$procmux$1041. + dead port 1/2 on $mux $flatten\dut.$procmux$1037. + dead port 2/2 on $mux $flatten\dut.$procmux$1037. + dead port 1/2 on $mux $flatten\dut.$procmux$551. + dead port 2/2 on $mux $flatten\dut.$procmux$551. + dead port 1/4 on $pmux $flatten\dut.$procmux$1034. + dead port 2/4 on $pmux $flatten\dut.$procmux$1034. + dead port 3/4 on $pmux $flatten\dut.$procmux$1034. + dead port 4/4 on $pmux $flatten\dut.$procmux$1034. + dead port 1/2 on $mux $flatten\dut.$procmux$1013. + dead port 2/2 on $mux $flatten\dut.$procmux$1013. + dead port 1/2 on $mux $flatten\dut.$procmux$549. + dead port 2/2 on $mux $flatten\dut.$procmux$549. + dead port 1/2 on $mux $flatten\dut.$procmux$1011. + dead port 2/2 on $mux $flatten\dut.$procmux$1011. + dead port 1/2 on $mux $flatten\dut.$procmux$1009. + dead port 2/2 on $mux $flatten\dut.$procmux$1009. + dead port 1/2 on $mux $flatten\dut.$procmux$994. + dead port 2/2 on $mux $flatten\dut.$procmux$994. + dead port 1/2 on $mux $flatten\dut.$procmux$992. + dead port 2/2 on $mux $flatten\dut.$procmux$992. + dead port 1/2 on $mux $flatten\dut.$procmux$980. + dead port 2/2 on $mux $flatten\dut.$procmux$980. + dead port 1/2 on $mux $flatten\dut.$procmux$978. + dead port 2/2 on $mux $flatten\dut.$procmux$978. + dead port 1/2 on $mux $flatten\dut.$procmux$976. + dead port 2/2 on $mux $flatten\dut.$procmux$976. + dead port 1/2 on $mux $flatten\dut.$procmux$965. + dead port 2/2 on $mux $flatten\dut.$procmux$965. + dead port 1/2 on $mux $flatten\dut.$procmux$996. + dead port 2/2 on $mux $flatten\dut.$procmux$996. + dead port 1/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$170. + dead port 2/2 on $mux $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$170. + dead port 1/2 on $mux $flatten\dut.$procmux$962. + dead port 2/2 on $mux $flatten\dut.$procmux$962. + dead port 1/4 on $pmux $flatten\dut.$procmux$958. + dead port 2/4 on $pmux $flatten\dut.$procmux$958. + dead port 3/4 on $pmux $flatten\dut.$procmux$958. + dead port 4/4 on $pmux $flatten\dut.$procmux$958. + dead port 1/2 on $mux $flatten\dut.$procmux$956. + dead port 2/2 on $mux $flatten\dut.$procmux$956. + dead port 1/2 on $mux $flatten\dut.$procmux$942. + dead port 2/2 on $mux $flatten\dut.$procmux$942. + dead port 1/2 on $mux $flatten\dut.$procmux$777. + dead port 2/2 on $mux $flatten\dut.$procmux$777. + dead port 1/3 on $pmux $flatten\dut.$procmux$646. + dead port 2/3 on $pmux $flatten\dut.$procmux$646. + dead port 3/3 on $pmux $flatten\dut.$procmux$646. + dead port 1/2 on $mux $flatten\dut.$procmux$553. + dead port 2/2 on $mux $flatten\dut.$procmux$553. +Removed 215 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Removed a total of 0 cells. + +5.6. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 8 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 9 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 10 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 11 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 12 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 13 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 14 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 15 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 16 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 17 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 18 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 19 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 20 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 21 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 22 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 23 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 24 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 25 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 26 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 27 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 28 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 29 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 30 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 31 on $flatten\dut.$procdff$1262 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 0 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 1 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 2 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 3 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 4 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 5 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 6 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 7 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 8 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 9 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 10 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 11 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 12 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 13 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 14 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 15 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 16 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 17 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 18 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 19 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 20 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 21 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 22 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 23 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 24 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 25 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 26 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 27 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 28 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 29 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 30 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 1-bit at position 31 on $flatten\dut.$procdff$1261 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1260 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 8 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 9 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 10 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 11 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 12 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 13 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 14 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 15 on $flatten\dut.$procdff$1257 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1255 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1255 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1255 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1252 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 0 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 3 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 4 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 5 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 6 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 7 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 8 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 9 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 10 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 11 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 12 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 13 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 14 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 15 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 16 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 17 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 18 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 19 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 20 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 21 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 22 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 23 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 24 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 25 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 26 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 27 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 28 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 29 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 30 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 31 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 32 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 33 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 34 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 35 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 36 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 37 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 38 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 39 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 40 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 41 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 42 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 43 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 44 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 45 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 46 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 47 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 48 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 49 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 50 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 51 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 52 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 53 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 54 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 55 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 56 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 57 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 58 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 59 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 60 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 61 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 62 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 63 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 64 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 65 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 66 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 67 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 68 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 69 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 70 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 71 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 72 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 73 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 74 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 75 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 76 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 77 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 78 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 79 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 80 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 81 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 82 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 83 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 84 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 85 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 86 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 87 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 88 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 89 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 90 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 91 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 92 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 93 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 94 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 95 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 96 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 97 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 98 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 99 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 100 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 101 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 102 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 103 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 104 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 105 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 106 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 107 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 108 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 109 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 110 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 111 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 112 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 113 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 114 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 115 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 116 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 117 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 118 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 119 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 120 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 121 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 122 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 123 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 124 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 125 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 126 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 127 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 128 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 129 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 130 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 131 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 132 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 133 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 134 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 135 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 136 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 137 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 138 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 139 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 140 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 141 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 142 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 143 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 144 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 145 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 146 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 147 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 148 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 149 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 150 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 151 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 152 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 153 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 154 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 155 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 156 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 157 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 158 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 159 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 160 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 161 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 162 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 163 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 164 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 165 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 166 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 167 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 168 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 169 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 170 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 171 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 172 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 173 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 174 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 175 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 176 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 177 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 178 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 179 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 180 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 181 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 182 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 183 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 184 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 185 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 186 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 187 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 188 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 189 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 190 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 191 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 192 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 193 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 194 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 195 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 196 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 197 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 198 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 199 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 200 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 201 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 202 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 203 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 204 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 205 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 206 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 207 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 208 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 209 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 210 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 211 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 212 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 213 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 214 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 215 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 216 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 217 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 218 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 219 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 220 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 221 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 222 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 223 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 224 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 225 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 226 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 227 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 228 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 229 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 230 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 231 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 232 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 233 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 234 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 235 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 236 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 237 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 238 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 239 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 240 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 241 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 242 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 243 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 244 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 245 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 246 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 247 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 248 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 249 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 250 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 251 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 252 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 253 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 254 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 255 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 256 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 257 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 258 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 259 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 260 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 261 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 262 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 263 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 264 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 265 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 266 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 267 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 268 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 269 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 270 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 271 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 272 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 273 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 274 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 275 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 276 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 277 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 278 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 279 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 280 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 281 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 282 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 283 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 284 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 285 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 286 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 287 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 288 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 289 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 290 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 291 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 292 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 293 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 294 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 295 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 296 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 297 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 298 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 299 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 300 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 301 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 302 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 303 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 304 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 305 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 306 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 307 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 308 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 309 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 310 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 311 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 312 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 313 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 314 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 315 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 316 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 317 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 318 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 319 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 320 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 321 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 322 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 323 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 324 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 325 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 326 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 327 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 328 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 329 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 330 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 331 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 332 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 333 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 334 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 335 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 336 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 337 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 338 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 339 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 340 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 341 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 342 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 343 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 344 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 345 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 346 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 347 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 348 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 349 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 350 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 351 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 352 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 353 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 354 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 355 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 356 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 357 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 358 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 359 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 360 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 361 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 362 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 363 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 364 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 365 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 366 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 367 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 368 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 369 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 370 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 371 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 372 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 373 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 374 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 375 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 376 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 377 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 378 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 379 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 380 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 381 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 382 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 383 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 384 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 385 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 386 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 387 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 388 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 389 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 390 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 391 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 392 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 393 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 394 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 395 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 396 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 397 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 398 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 399 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 400 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 401 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 402 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 403 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 404 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 405 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 406 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 407 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 408 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 409 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 410 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 411 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 412 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 413 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 414 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 415 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 416 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 417 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 418 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 419 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 420 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 421 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 422 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 423 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 424 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 425 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 426 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 427 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 428 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 429 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 430 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 431 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 432 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 433 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 434 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 435 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 436 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 437 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 438 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 439 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 440 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 441 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 442 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 443 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 444 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 445 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 446 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 447 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 448 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 449 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 450 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 451 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 452 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 453 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 454 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 455 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 456 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 457 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 458 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 459 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 460 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 461 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 462 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 463 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 464 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 465 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 466 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 467 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 468 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 469 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 470 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 471 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 472 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 473 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 474 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 475 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 476 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 477 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 478 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 479 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 480 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 481 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 482 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 483 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 484 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 485 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 486 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 487 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 488 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 489 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 490 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 491 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 492 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 493 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 494 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 495 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 496 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 497 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 498 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 499 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 500 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 501 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 502 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 503 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 504 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 505 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 506 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 507 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 508 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 509 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 510 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 511 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 512 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 513 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 514 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 515 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 516 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 517 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 518 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 519 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 520 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 521 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 522 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 523 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 524 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 525 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 526 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 527 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 528 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 529 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 530 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 531 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 532 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 533 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 534 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 535 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 536 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 537 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 538 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 539 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 540 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 541 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 542 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 543 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 544 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 545 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 546 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 547 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 548 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 549 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 550 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 551 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 552 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 553 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 554 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 555 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 556 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 557 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 558 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 559 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 560 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 561 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 562 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 563 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 564 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 565 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 566 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 567 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 568 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 569 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 570 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 571 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 572 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 573 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 574 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 575 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 576 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 577 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 578 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 579 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 580 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 581 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 582 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 583 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 584 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 585 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 586 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 587 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 588 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 589 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 590 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 591 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 592 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 593 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 594 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 595 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 596 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 597 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 598 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 599 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 600 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 601 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 602 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 603 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 604 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 605 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 606 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 607 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 608 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 609 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 610 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 611 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 612 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 613 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 614 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 615 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 616 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 617 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 618 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 619 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 620 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 621 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 622 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 623 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 624 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 625 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 626 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 627 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 628 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 629 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 630 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 631 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 632 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 633 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 634 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 635 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 636 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 637 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 638 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 639 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 640 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 641 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 642 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 643 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 644 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 645 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 646 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 647 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 648 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 649 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 650 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 651 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 652 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 653 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 654 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 655 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 656 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 657 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 658 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 659 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 660 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 661 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 662 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 663 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 664 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 665 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 666 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 667 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 668 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 669 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 670 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 671 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 672 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 673 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 674 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 675 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 676 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 677 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 678 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 679 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 680 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 681 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 682 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 683 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 684 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 685 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 686 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 687 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 688 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 689 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 690 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 691 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 692 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 693 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 694 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 695 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 696 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 697 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 698 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 699 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 700 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 701 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 702 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 703 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 704 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 705 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 706 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 707 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 708 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 709 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 710 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 711 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 712 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 713 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 714 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 715 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 716 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 717 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 718 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 719 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 720 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 721 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 722 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 723 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 724 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 725 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 726 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 727 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 728 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 729 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 730 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 731 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 732 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 733 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 734 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 735 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 736 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 737 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 738 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 739 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 740 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 741 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 742 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 743 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 744 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 745 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 746 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 747 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 748 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 749 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 750 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 751 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 752 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 753 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 754 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 755 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 756 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 757 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 758 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 759 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 760 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 761 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 762 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 763 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 764 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 765 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 766 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 767 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 768 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 769 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 770 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 771 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 772 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 773 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 774 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 775 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 776 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 777 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 778 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 779 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 780 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 781 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 782 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 783 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 784 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 785 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 786 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 787 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 788 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 789 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 790 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 791 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 792 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 793 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 794 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 795 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 796 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 797 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 798 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 799 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 800 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 801 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 802 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 803 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 804 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 805 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 806 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 807 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 808 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 809 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 810 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 811 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 812 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 813 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 814 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 815 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 816 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 817 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 818 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 819 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 820 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 821 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 822 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 823 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 824 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 825 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 826 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 827 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 828 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 829 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 830 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 831 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 832 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 833 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 834 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 835 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 836 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 837 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 838 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 839 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 840 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 841 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 842 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 843 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 844 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 845 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 846 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 847 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 848 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 849 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 850 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 851 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 852 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 853 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 854 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 855 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 856 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 857 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 858 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 859 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 860 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 861 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 862 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 863 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 864 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 865 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 866 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 867 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 868 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 869 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 870 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 871 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 872 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 873 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 874 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 875 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 876 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 877 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 878 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 879 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 880 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 881 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 882 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 883 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 884 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 885 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 886 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 887 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 888 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 889 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 890 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 891 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 892 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 893 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 894 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 895 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 896 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 897 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 898 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 899 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 900 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 901 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 902 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 903 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 904 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 905 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 906 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 907 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 908 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 909 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 910 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 911 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 912 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 913 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 914 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 915 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 916 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 917 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 918 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 919 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 920 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 921 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 922 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 923 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 924 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 925 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 926 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 927 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 928 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 929 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 930 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 931 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 932 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 933 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 934 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 935 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 936 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 937 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 938 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 939 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 940 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 941 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 942 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 943 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 944 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 945 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 946 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 947 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 948 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 949 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 950 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 951 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 952 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 953 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 954 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 955 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 956 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 957 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 958 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 959 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 960 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 961 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 962 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 963 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 964 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 965 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 966 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 967 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 968 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 969 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 970 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 971 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 972 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 973 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 974 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 975 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 976 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 977 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 978 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 979 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 980 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 981 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 982 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 983 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 984 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 985 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 986 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 987 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 988 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 989 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 990 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 991 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 992 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 993 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 994 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 995 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 996 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 997 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 998 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 999 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1000 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1001 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1002 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1003 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1004 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1005 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1006 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1007 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1008 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1009 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1010 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1011 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1012 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1013 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1014 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1015 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1016 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1017 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1018 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1019 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1020 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1021 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1022 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1023 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1024 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1025 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1026 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1027 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1028 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1029 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1030 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1031 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1032 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1033 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1034 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1035 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1036 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1037 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1038 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1039 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1040 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1041 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1042 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1043 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1044 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1045 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1046 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1047 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1048 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1049 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1050 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1051 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1052 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1053 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1054 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1055 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1056 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1057 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1058 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1059 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1060 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1061 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1062 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1063 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1064 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1065 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1066 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1067 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1068 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1069 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1070 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1071 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1072 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1073 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1074 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1075 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1076 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1077 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1078 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1079 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1080 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1081 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1082 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1083 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1084 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1085 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1086 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1087 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1088 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1089 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1090 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1091 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1092 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1093 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1094 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1095 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1096 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1097 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1098 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1099 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1100 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1101 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1102 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1103 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1104 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1105 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1106 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1107 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1108 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1109 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1110 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1111 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1112 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1113 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1114 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1115 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1116 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1117 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1118 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1119 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1120 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1121 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1122 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1123 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1124 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1125 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1126 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1127 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1128 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1129 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1130 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1131 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1132 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1133 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1134 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1135 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1136 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1137 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1138 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1139 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1140 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1141 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1142 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1143 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1144 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1145 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1146 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1147 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1148 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1149 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1150 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1151 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1152 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1153 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1154 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1155 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1156 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1157 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1158 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1159 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1160 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1161 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1162 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1163 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1164 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1165 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1166 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1167 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1168 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1169 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1170 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1171 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1172 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1173 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1174 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1175 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1176 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1177 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1178 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1179 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1180 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1181 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1182 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1183 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1184 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1185 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1186 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1187 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1188 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1189 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1190 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1191 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1192 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1193 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1194 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1195 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1196 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1197 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1198 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1199 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1200 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1201 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1202 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1203 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1204 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1205 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1206 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1207 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1208 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1209 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1210 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1211 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1212 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1213 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1214 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1215 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1216 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1217 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1218 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1219 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1220 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1221 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1222 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1223 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1224 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1225 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1226 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1227 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1228 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1229 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1230 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1231 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1232 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1233 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1234 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1235 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1236 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1237 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1238 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1239 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1240 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1241 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1242 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1243 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1244 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1245 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1246 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1247 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1248 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1249 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1250 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1251 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1252 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1253 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1254 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1255 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1256 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1257 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1258 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1259 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1260 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1261 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1262 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1263 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1264 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1265 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1266 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1267 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1268 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1269 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1270 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1271 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1272 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1273 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1274 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1275 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1276 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1277 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1278 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1279 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1280 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1281 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1282 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1283 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1284 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1285 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1286 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1287 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1288 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1289 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1290 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1291 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1292 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1293 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1294 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1295 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1296 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1297 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1298 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1299 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1300 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1301 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1302 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1303 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1304 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1305 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1306 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1307 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1308 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1309 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1310 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1311 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1312 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1313 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1314 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1315 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1316 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1317 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1318 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1319 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1320 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1321 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1322 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1323 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1324 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1325 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1326 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1327 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1328 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1329 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1330 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1331 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1332 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1333 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1334 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1335 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1336 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1337 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1338 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1339 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1340 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1341 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1342 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1343 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1344 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1345 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1346 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1347 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1348 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1349 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1350 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1351 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1352 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1353 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1354 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1355 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1356 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1357 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1358 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1359 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1360 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1361 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1362 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1363 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1364 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1365 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1366 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1367 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1368 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1369 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1370 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1371 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1372 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1373 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1374 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1375 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1376 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1377 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1378 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1379 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1380 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1381 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1382 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1383 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1384 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1385 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1386 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1387 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1388 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1389 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1390 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1391 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1392 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1393 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1394 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1395 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1396 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1397 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1398 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1399 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1400 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1401 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1402 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1403 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1404 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1405 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1406 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1407 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1408 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1409 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1410 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1411 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1412 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1413 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1414 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1415 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1416 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1417 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1418 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1419 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1420 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1421 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1422 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1423 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1424 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1425 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1426 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1427 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1428 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1429 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1430 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1431 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1432 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1433 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1434 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1435 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1436 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1437 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1438 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1439 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1440 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1441 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1442 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1443 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1444 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1445 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1446 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1447 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1448 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1449 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1450 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1451 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1452 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1453 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1454 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1455 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1456 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1457 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1458 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1459 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1460 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1461 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1462 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1463 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1464 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1465 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1466 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1467 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1468 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1469 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1470 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1471 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1472 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1473 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1474 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1475 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1476 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1477 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1478 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1479 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1480 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1481 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1482 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1483 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1484 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1485 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1486 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1487 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1488 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1489 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1490 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1491 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1492 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1493 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1494 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1495 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1496 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1497 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1498 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1499 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1500 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1501 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1502 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1503 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1504 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1505 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1506 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1507 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1508 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1509 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1510 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1511 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1512 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1513 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1514 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1515 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1516 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1517 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1518 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1519 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1520 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1521 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1522 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1523 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1524 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1525 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1526 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1527 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1528 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1529 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1530 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1531 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1532 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1533 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1534 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1535 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1536 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1537 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1538 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1539 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1540 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1541 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1542 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1543 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1544 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1545 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1546 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1547 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1548 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1549 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1550 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1551 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1552 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1553 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1554 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1555 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1556 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1557 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1558 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1559 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1560 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1561 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1562 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1563 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1564 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1565 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1566 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1567 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1568 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1569 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1570 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1571 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1572 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1573 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1574 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1575 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1576 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1577 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1578 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1579 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1580 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1581 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1582 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1583 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1584 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1585 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1586 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1587 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1588 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1589 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1590 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1591 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1592 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1593 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1594 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1595 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1596 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1597 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1598 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1599 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1600 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1601 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1602 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1603 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1604 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1605 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1606 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1607 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1608 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1609 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1610 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1611 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1612 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1613 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1614 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1615 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1616 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1617 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1618 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1619 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1620 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1621 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1622 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1623 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1624 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1625 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1626 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1627 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1628 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1629 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1630 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1631 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1632 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1633 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1634 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1635 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1636 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1637 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1638 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1639 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1640 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1641 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1642 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1643 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1644 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1645 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1646 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1647 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1648 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1649 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1650 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1651 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1652 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1653 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1654 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1655 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1656 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1657 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1658 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1659 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1660 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1661 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1662 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1663 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1664 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1665 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1666 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1667 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1668 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1669 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1670 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1671 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1672 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1673 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1674 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1675 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1676 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1677 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1678 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1679 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1680 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1681 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1682 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1683 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1684 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1685 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1686 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1687 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1688 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1689 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1690 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1691 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1692 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1693 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1694 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1695 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1696 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1697 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1698 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1699 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1700 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1701 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1702 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1703 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1704 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1705 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1706 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1707 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1708 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1709 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1710 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1711 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1712 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1713 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1714 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1715 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1716 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1717 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1718 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1719 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1720 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1721 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1722 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1723 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1724 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1725 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1726 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1727 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1728 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1729 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1730 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1731 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1732 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1733 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1734 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1735 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1736 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1737 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1738 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1739 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1740 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1741 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1742 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1743 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1744 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1745 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1746 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1747 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1748 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1749 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1750 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1751 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1752 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1753 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1754 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1755 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1756 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1757 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1758 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1759 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1760 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1761 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1762 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1763 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1764 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1765 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1766 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1767 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1768 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1769 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1770 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1771 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1772 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1773 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1774 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1775 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1776 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1777 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1778 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1779 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1780 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1781 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1782 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1783 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1784 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1785 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1786 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1787 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1788 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1789 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1790 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1791 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1792 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1793 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1794 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1795 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1796 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1797 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1798 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1799 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1800 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1801 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1802 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1803 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1804 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1805 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1806 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1807 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1808 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1809 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1810 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1811 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1812 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1813 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1814 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1815 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1816 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1817 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1818 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1819 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1820 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1821 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1822 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1823 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1824 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1825 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1826 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1827 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1828 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1829 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1830 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1831 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1832 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1833 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1834 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1835 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1836 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1837 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1838 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1839 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1840 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1841 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1842 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1843 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1844 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1845 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1846 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1847 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1848 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1849 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1850 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1851 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1852 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1853 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1854 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1855 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1856 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1857 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1858 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1859 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1860 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1861 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1862 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1863 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1864 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1865 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1866 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1867 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1868 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1869 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1870 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1871 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1872 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1873 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1874 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1875 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1876 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1877 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1878 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1879 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1880 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1881 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1882 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1883 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1884 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1885 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1886 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1887 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1888 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1889 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1890 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1891 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1892 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1893 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1894 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1895 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1896 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1897 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1898 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1899 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1900 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1901 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1902 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1903 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1904 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1905 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1906 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1907 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1908 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1909 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1910 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1911 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1912 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1913 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1914 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1915 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1916 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1917 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1918 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1919 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1920 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1921 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1922 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1923 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1924 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1925 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1926 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1927 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1928 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1929 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1930 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1931 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1932 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1933 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1934 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1935 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1936 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1937 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1938 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1939 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1940 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1941 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1942 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1943 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1944 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1945 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1946 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1947 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1948 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1949 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1950 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1951 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1952 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1953 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1954 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1955 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1956 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1957 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1958 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1959 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1960 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1961 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1962 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1963 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1964 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1965 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1966 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1967 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1968 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1969 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1970 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1971 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1972 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1973 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1974 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1975 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1976 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1977 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1978 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1979 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1980 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1981 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1982 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1983 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1984 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1985 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1986 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1987 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1988 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1989 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1990 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1991 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1992 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1993 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1994 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1995 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1996 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1997 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1998 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 1999 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2000 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2001 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2002 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2003 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2004 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2005 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2006 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2007 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2008 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2009 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2010 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2011 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2012 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2013 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2014 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2015 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2016 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2017 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2018 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2019 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2020 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2021 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2022 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2023 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2024 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2025 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2026 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2027 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2028 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2029 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2030 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2031 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2032 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2033 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2034 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2035 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2036 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2037 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2038 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2039 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2040 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2041 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2042 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2043 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2044 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2045 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2046 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. +Setting constant 0-bit at position 2047 on $flatten\dut.$procdff$1251 ($dff) from module lsc1_packet_frontend_arch_reset_idle. + +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Removed 67 unused cells and 218 unused wires. + + +5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + + +5.9. Rerunning OPT passes. (Maybe there is more to do..) + +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. +Performed a total of 0 changes. + +5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. + +Removed a total of 6 cells. + +5.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 1-bit at position 0 on $procdff$1240 ($dff) from module lsc1_packet_frontend_arch_reset_idle. + +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. +Removed 0 unused cells and 21 unused wires. + + +5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + +5.16. Rerunning OPT passes. (Maybe there is more to do..) + +5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_frontend_arch_reset_idle.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_frontend_arch_reset_idle. +Performed a total of 0 changes. + +5.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_frontend_arch_reset_idle'. +Removed a total of 0 cells. + +5.20. Executing OPT_DFF pass (perform DFF optimizations). + +5.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_frontend_arch_reset_idle.. + +5.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_frontend_arch_reset_idle. + +5.23. Finished OPT passes. (There is nothing left to do.) + +6. Executing SAT pass (solving SAT problems in the circuit). + +Setting up time step 1: +Final constraint equation: { } = { } +Imported 4 cells to SAT database. +Import constraint from assume cell: \clk when 1'1. +Import set-constraint from init attribute: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN = 1'0 +Final init constraint equation: $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN = 1'0 +Import proof for assert: 1'1 when $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN. + +Setting up time step 2: +Final constraint equation: { } = { } +Imported 4 cells to SAT database. +Import constraint from assume cell: \clk when 1'1. +Import proof for assert: 1'1 when $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN. + +Setting up time step 3: +Final constraint equation: { } = { } +Imported 4 cells to SAT database. +Import constraint from assume cell: \clk when 1'1. +Import proof for assert: 1'1 when $formal$formal/lsc1_packet_frontend_arch_reset_idle.sv:20$240_EN. + +Solving problem with 18 variables and 43 clauses.. +SAT proof finished - no model found: SUCCESS! + + /$$$$$$ /$$$$$$$$ /$$$$$$$ + /$$__ $$ | $$_____/ | $$__ $$ + | $$ \ $$ | $$ | $$ \ $$ + | $$ | $$ | $$$$$ | $$ | $$ + | $$ | $$ | $$__/ | $$ | $$ + | $$/$$ $$ | $$ | $$ | $$ + | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ + \____ $$$|__/|________/|__/|_______/|__/ + \__/ + +End of script. Logfile hash: ed77109f73, CPU: user 4.22s system 0.05s, MEM: 70.84 MB peak +Yosys 0.33 (git sha1 2584903a060) +Time spent: 59% 1x proc_mux (2 sec), 11% 2x check (0 sec), ... diff --git a/results/frontend-bounded-path-20260728/rtl.log b/results/frontend-bounded-path-20260728/rtl.log new file mode 100644 index 0000000..fa7dc3a --- /dev/null +++ b/results/frontend-bounded-path-20260728/rtl.log @@ -0,0 +1,31 @@ +make: Entering directory '/tmp/lean-silicon-pr30.0LkbvS/test/packet_frontend' +iverilog -g2012 -Wall -s tb_lsc1_packet_frontend -o tb_lsc1_packet_frontend.vvp ../../asic_core/rtl/lsc1_packet_rx.sv ../../asic_core/rtl/lsc1_packet_tx.sv ../../asic_core/rtl/gf2n_mul_bitstream.sv ../../asic_core/rtl/gf128_mul_bitstream.sv ../../asic_core/rtl/leanvm_b_stream_alu.sv ../../asic_core/rtl/lsc1_stream_adapter.sv ../../asic_core/rtl/lsc1_field_encoder.sv ../../asic_core/rtl/lsc1_packet_frontend.sv tb_lsc1_packet_frontend.sv +warning: Some design elements have no explicit time unit and/or + : time precision. This may cause confusing timing results. + : Affected design elements are: + : -- module gf128_mul_bitstream declared here: ../../asic_core/rtl/gf128_mul_bitstream.sv:9 + : -- module gf2n_mul_bitstream declared here: ../../asic_core/rtl/gf2n_mul_bitstream.sv:22 + : -- module leanvm_b_stream_alu declared here: ../../asic_core/rtl/leanvm_b_stream_alu.sv:28 + : -- module lsc1_field_encoder declared here: ../../asic_core/rtl/lsc1_field_encoder.sv:6 + : -- module lsc1_packet_frontend declared here: ../../asic_core/rtl/lsc1_packet_frontend.sv:6 + : -- module lsc1_packet_rx declared here: ../../asic_core/rtl/lsc1_packet_rx.sv:5 + : -- module lsc1_packet_tx declared here: ../../asic_core/rtl/lsc1_packet_tx.sv:4 + : -- module lsc1_stream_adapter declared here: ../../asic_core/rtl/lsc1_stream_adapter.sv:6 +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:234: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:264: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:309: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:325: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:389: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:399: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +tb_lsc1_packet_frontend.sv:417: warning: @* is sensitive to all 256 words in array 'response'. +vvp tb_lsc1_packet_frontend.vvp +PASS: LSC-1 Phase-3 packet frontend adversarial test +tb_lsc1_packet_frontend.sv:426: $finish called at 44410000 (1ps) +make: Leaving directory '/tmp/lean-silicon-pr30.0LkbvS/test/packet_frontend' diff --git a/results/frontend-bounded-path-20260728/status-accept.log b/results/frontend-bounded-path-20260728/status-accept.log new file mode 100644 index 0000000..c8f1d65 --- /dev/null +++ b/results/frontend-bounded-path-20260728/status-accept.log @@ -0,0 +1,906 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Executing script file `formal/lsc1_packet_rx_status_accept.ys' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_rx.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_packet_rx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: formal/lsc1_packet_rx_status_accept.sv +Parsing formal SystemVerilog input from `formal/lsc1_packet_rx_status_accept.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_rx_status_accept'. +Successfully finished Verilog frontend. + +3. Executing PREP pass. + +3.1. Executing HIERARCHY pass (managing design hierarchy). + +3.1.1. Analyzing design hierarchy.. +Top module: \lsc1_packet_rx_status_accept +Used module: \lsc1_packet_rx + +3.1.2. Analyzing design hierarchy.. +Top module: \lsc1_packet_rx_status_accept +Used module: \lsc1_packet_rx +Removed 0 unused modules. +Module lsc1_packet_rx_status_accept directly or indirectly contains formal properties -> setting "keep" attribute. + +3.2. Executing PROC pass (convert processes to netlists). + +3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 7 switch rules as full_case in process $proc$formal/lsc1_packet_rx_status_accept.sv:24$248 in module lsc1_packet_rx_status_accept. +Marked 11 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_rx.sv:71$23 in module lsc1_packet_rx. +Removed a total of 0 dead cases. + +3.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 26 assignments to connections. + +3.2.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:0$285'. + Set init value: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_EN = 1'0 +Found init rule in `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:0$283'. + Set init value: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_EN = 1'0 +Found init rule in `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:0$281'. + Set init value: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN = 1'0 + +3.2.5. Executing PROC_ARST pass (detect async resets in processes). + +3.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:0$285'. +Creating decoders for process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:0$283'. +Creating decoders for process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:0$281'. +Creating decoders for process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. + 1/6: $0$formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN[0:0]$262 + 2/6: $0$formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK[0:0]$261 + 3/6: $0$formal$formal/lsc1_packet_rx_status_accept.sv:37$241_EN[0:0]$264 + 4/6: $0$formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK[0:0]$263 + 5/6: $0$formal$formal/lsc1_packet_rx_status_accept.sv:38$242_EN[0:0]$266 + 6/6: $0$formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK[0:0]$265 +Creating decoders for process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:33$256'. +Creating decoders for process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:24$248'. + 1/7: $7\rx_data[7:0] + 2/7: $6\rx_data[7:0] + 3/7: $5\rx_data[7:0] + 4/7: $4\rx_data[7:0] + 5/7: $3\rx_data[7:0] + 6/7: $2\rx_data[7:0] + 7/7: $1\rx_data[7:0] +Creating decoders for process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + 1/89: $0\received_crc[31:0] [31:24] + 2/89: $0\received_crc[31:0] [23:16] + 3/89: $0\received_crc[31:0] [15:8] + 4/89: $0\received_crc[31:0] [7:0] + 5/89: $5$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$185 + 6/89: $5$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$184 + 7/89: $5$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$186 + 8/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$177 + 9/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$180 + 10/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$181 + 11/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$179 + 12/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$178 + 13/89: $4$lookahead\frame_payload$22[2047:0]$182 + 14/89: $4$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$176 + 15/89: $4$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$175 + 16/89: $4$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$174 + 17/89: $0\declared_length[15:0] [15:8] + 18/89: $0\declared_length[15:0] [7:0] + 19/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$103 + 20/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$102 + 21/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$101 + 22/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$85 + 23/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$84 + 24/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$83 + 25/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$82 + 26/89: $3$lookahead\frame_payload$22[2047:0]$99 + 27/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$98 + 28/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$97 + 29/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$96 + 30/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$95 + 31/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$94 + 32/89: $3$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$93 + 33/89: $3$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$92 + 34/89: $3$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$91 + 35/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$90 + 36/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$89 + 37/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$88 + 38/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$87 + 39/89: $3\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$86 + 40/89: $2$lookahead\frame_payload$22[2047:0]$81 + 41/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$80 + 42/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$79 + 43/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$78 + 44/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$77 + 45/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$76 + 46/89: $2$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$75 + 47/89: $2$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$74 + 48/89: $2$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$73 + 49/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$72 + 50/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$71 + 51/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$70 + 52/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$69 + 53/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$68 + 54/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$67 + 55/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$66 + 56/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$65 + 57/89: $2\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$64 + 58/89: $1$lookahead\frame_payload$22[2047:0]$61 + 59/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work[31:0]$60 + 60/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index[31:0]$59 + 61/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data[7:0]$58 + 62/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in[31:0]$57 + 63/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result[31:0]$56 + 64/89: $1$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8[31:0]$55 + 65/89: $1$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7[2047:0]$54 + 66/89: $1$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6[2047:0]$53 + 67/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work[31:0]$52 + 68/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index[31:0]$51 + 69/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data[7:0]$50 + 70/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in[31:0]$49 + 71/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result[31:0]$48 + 72/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$47 + 73/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index[31:0]$46 + 74/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data[7:0]$45 + 75/89: $1\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result[31:0]$44 + 76/89: $5$lookahead\frame_payload$22[2047:0]$187 + 77/89: $0\crc[31:0] + 78/89: $0\flags[7:0] + 79/89: $0\opcode[7:0] + 80/89: $0\version[7:0] + 81/89: $4\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work[31:0]$104 + 82/89: $0\body_index[15:0] + 83/89: $0\header_index[2:0] + 84/89: $0\state[2:0] + 85/89: $0\fault_status[7:0] + 86/89: $0\fault_valid[0:0] + 87/89: $0\frame_length[15:0] + 88/89: $0\frame_opcode[7:0] + 89/89: $0\frame_valid[0:0] + +3.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\lsc1_packet_rx_status_accept.$formal$formal/lsc1_packet_rx_status_accept.sv:33$239_CHECK' from process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:33$256'. +No latch inferred for signal `\lsc1_packet_rx_status_accept.$formal$formal/lsc1_packet_rx_status_accept.sv:33$239_EN' from process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:33$256'. +No latch inferred for signal `\lsc1_packet_rx_status_accept.\rx_data' from process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:24$248'. + +3.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\lsc1_packet_rx_status_accept.\step' using process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. + created $dff cell `$procdff$1311' with positive edge clock. +Creating register for signal `\lsc1_packet_rx_status_accept.$formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK' using process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. + created $dff cell `$procdff$1312' with positive edge clock. +Creating register for signal `\lsc1_packet_rx_status_accept.$formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN' using process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. + created $dff cell `$procdff$1313' with positive edge clock. +Creating register for signal `\lsc1_packet_rx_status_accept.$formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK' using process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. + created $dff cell `$procdff$1314' with positive edge clock. +Creating register for signal `\lsc1_packet_rx_status_accept.$formal$formal/lsc1_packet_rx_status_accept.sv:37$241_EN' using process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. + created $dff cell `$procdff$1315' with positive edge clock. +Creating register for signal `\lsc1_packet_rx_status_accept.$formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK' using process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. + created $dff cell `$procdff$1316' with positive edge clock. +Creating register for signal `\lsc1_packet_rx_status_accept.$formal$formal/lsc1_packet_rx_status_accept.sv:38$242_EN' using process `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. + created $dff cell `$procdff$1317' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1318' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1319' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1320' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\frame_payload' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1321' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_valid' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1322' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\fault_status' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1323' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\state' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1324' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\header_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1325' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\body_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1326' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\declared_length' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1327' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\version' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1328' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\opcode' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1329' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\flags' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1330' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1331' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\received_crc' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1332' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1333' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1334' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1335' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:107$3.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1336' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1337' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1338' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1339' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1340' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:113$4.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1341' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$mask$asic_core/rtl/lsc1_packet_rx.sv:136$6' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1342' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$data$asic_core/rtl/lsc1_packet_rx.sv:136$7' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1343' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$bitselwrite$sel$asic_core/rtl/lsc1_packet_rx.sv:136$8' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1344' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.$result' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1345' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.crc_in' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1346' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.data' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1347' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.bit_index' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1348' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.\crc_byte$func$asic_core/rtl/lsc1_packet_rx.sv:137$9.work' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1349' with positive edge clock. +Creating register for signal `\lsc1_packet_rx.$lookahead\frame_payload$22' using process `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. + created $dff cell `$procdff$1350' with positive edge clock. + +3.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:0$285'. +Removing empty process `lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:0$283'. +Removing empty process `lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:0$281'. +Found and cleaned up 1 empty switch in `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. +Removing empty process `lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:34$260'. +Removing empty process `lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:33$256'. +Found and cleaned up 7 empty switches in `\lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:24$248'. +Removing empty process `lsc1_packet_rx_status_accept.$proc$formal/lsc1_packet_rx_status_accept.sv:24$248'. +Found and cleaned up 14 empty switches in `\lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. +Removing empty process `lsc1_packet_rx.$proc$asic_core/rtl/lsc1_packet_rx.sv:71$23'. +Cleaned up 22 empty switches. + +3.2.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx_status_accept. + +Optimizing module lsc1_packet_rx. + + +3.3. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx_status_accept. +Optimizing module lsc1_packet_rx. + +3.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_rx_status_accept.. +Finding unused cells or wires in module \lsc1_packet_rx.. +Removed 215 unused cells and 657 unused wires. + + +3.5. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_rx... +Checking module lsc1_packet_rx_status_accept... +Found and reported 0 problems. + +3.6. Executing OPT pass (performing simple optimizations). + +3.6.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx. +Optimizing module lsc1_packet_rx_status_accept. + +3.6.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_rx'. + +Finding identical cells in module `\lsc1_packet_rx_status_accept'. +Removed a total of 52 cells. + +3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$1015. + dead port 2/2 on $mux $procmux$1017. + dead port 2/2 on $mux $procmux$1019. + dead port 1/2 on $mux $procmux$1022. + dead port 2/2 on $mux $procmux$559. + dead port 2/2 on $mux $procmux$561. + dead port 1/2 on $mux $procmux$564. + dead port 2/2 on $mux $procmux$720. + dead port 1/2 on $mux $procmux$723. + dead port 1/2 on $mux $procmux$851. +Running muxtree optimizer on module \lsc1_packet_rx_status_accept.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$303. + dead port 1/2 on $mux $procmux$306. + dead port 1/2 on $mux $procmux$309. + dead port 1/2 on $mux $procmux$312. + dead port 1/2 on $mux $procmux$315. + dead port 1/2 on $mux $procmux$318. + dead port 1/2 on $mux $procmux$324. + dead port 1/2 on $mux $procmux$327. + dead port 1/2 on $mux $procmux$330. + dead port 1/2 on $mux $procmux$333. + dead port 1/2 on $mux $procmux$336. + dead port 1/2 on $mux $procmux$342. + dead port 1/2 on $mux $procmux$345. + dead port 1/2 on $mux $procmux$348. + dead port 1/2 on $mux $procmux$351. + dead port 1/2 on $mux $procmux$357. + dead port 1/2 on $mux $procmux$360. + dead port 1/2 on $mux $procmux$363. + dead port 1/2 on $mux $procmux$369. + dead port 1/2 on $mux $procmux$372. + dead port 1/2 on $mux $procmux$378. +Removed 31 multiplexer ports. + + +3.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_rx. + New ctrl vector for $pmux cell $procmux$1154: { $auto$opt_reduce.cc:134:opt_pmux$1402 $procmux$1109_CMP } + Optimizing cells in module \lsc1_packet_rx. + Optimizing cells in module \lsc1_packet_rx_status_accept. +Performed a total of 1 changes. + +3.6.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_rx'. + +Finding identical cells in module `\lsc1_packet_rx_status_accept'. + +Removed a total of 19 cells. + +3.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_rx_status_accept.. +Removed 0 unused cells and 110 unused wires. + + +3.6.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx. +Optimizing module lsc1_packet_rx_status_accept. + +3.6.8. Rerunning OPT passes. (Maybe there is more to do..) + +3.6.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_rx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_packet_rx_status_accept.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.6.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_rx. + Optimizing cells in module \lsc1_packet_rx_status_accept. +Performed a total of 0 changes. + +3.6.11. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_rx'. +Finding identical cells in module `\lsc1_packet_rx_status_accept'. +Removed a total of 0 cells. + +3.6.12. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_rx_status_accept.. + +3.6.13. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx. +Optimizing module lsc1_packet_rx_status_accept. + +3.6.14. Finished OPT passes. (There is nothing left to do.) + +3.7. Executing WREDUCE pass (reducing word size of cells). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$ne$asic_core/rtl/lsc1_packet_rx.sv:60$16 ($ne). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1353 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1355 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1357 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1359 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1361 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1363 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1365 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1367 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1369 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1371 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1373 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1375 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1377 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1379 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1381 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1383 ($not). +Removed top 7 bits (of 16) from port B of cell lsc1_packet_rx.$gt$asic_core/rtl/lsc1_packet_rx.sv:122$171 ($gt). +Removed top 7 bits (of 16) from port B of cell lsc1_packet_rx.$lt$asic_core/rtl/lsc1_packet_rx.sv:135$183 ($lt). +Removed top 28 bits (of 32) from port B of cell lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188 ($mul). +Removed top 12 bits (of 32) from port Y of cell lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188 ($mul). +Removed top 12 bits (of 32) from port A of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 11 bits (of 32) from port Y of cell lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189 ($add). +Removed top 11 bits (of 33) from port A of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Converting cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub) from signed to unsigned. +Removed top 10 bits (of 33) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 1 bits (of 22) from port A of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 1 bits (of 23) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:0$190 ($sub). +Removed top 11 bits (of 33) from port A of cell lsc1_packet_rx.$neg$asic_core/rtl/lsc1_packet_rx.sv:0$191 ($neg). +Removed top 15 bits (of 32) from port Y of cell lsc1_packet_rx.$sub$asic_core/rtl/lsc1_packet_rx.sv:139$233 ($sub). +Removed top 7 bits (of 8) from port B of cell lsc1_packet_rx.$ne$asic_core/rtl/lsc1_packet_rx.sv:147$236 ($ne). +Removed top 24 bits (of 32) from port A of cell lsc1_packet_rx.$auto$opt_expr.cc:706:replace_const_cells$1351 ($not). +Removed top 30 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$402_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$419_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1018_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1031_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1048_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1064_CMP0 ($eq). +Removed top 30 bits (of 32) from port B of cell lsc1_packet_rx.$procmux$1144_CMP0 ($eq). +Removed top 2 bits (of 3) from mux cell lsc1_packet_rx.$procmux$1152 ($mux). +Removed top 1 bits (of 3) from port B of cell lsc1_packet_rx.$procmux$1156_CMP0 ($eq). +Removed top 1 bits (of 3) from mux cell lsc1_packet_rx.$procmux$1162 ($mux). +Removed top 11 bits (of 32) from wire lsc1_packet_rx.$add$asic_core/rtl/lsc1_packet_rx.sv:0$189_Y. +Removed top 12 bits (of 32) from wire lsc1_packet_rx.$mul$asic_core/rtl/lsc1_packet_rx.sv:136$188_Y. +Removed top 2 bits (of 3) from wire lsc1_packet_rx.$procmux$1152_Y. +Removed top 1 bits (of 3) from wire lsc1_packet_rx.$procmux$1162_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$110_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$114_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$118_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$122_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$126_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$130_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$134_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$139_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$143_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$147_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$151_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$155_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$159_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$163_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_rx.$shr$asic_core/rtl/lsc1_packet_rx.sv:55$167_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$109_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$113_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$117_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$121_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$125_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$129_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$133_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$142_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$146_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$150_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$154_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$158_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$162_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$ternary$asic_core/rtl/lsc1_packet_rx.sv:55$166_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_rx.$xor$asic_core/rtl/lsc1_packet_rx.sv:53$138_Y. +Removed top 31 bits (of 32) from port B of cell lsc1_packet_rx_status_accept.$ge$formal/lsc1_packet_rx_status_accept.sv:11$245 ($ge). +Removed top 28 bits (of 32) from port B of cell lsc1_packet_rx_status_accept.$le$formal/lsc1_packet_rx_status_accept.sv:11$246 ($le). +Removed top 4 bits (of 5) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:24$249 ($eq). +Removed top 3 bits (of 5) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:25$250 ($eq). +Removed top 3 bits (of 5) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:26$251 ($eq). +Removed top 2 bits (of 5) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:27$252 ($eq). +Removed top 1 bits (of 5) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:28$253 ($eq). +Removed top 1 bits (of 5) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:29$254 ($eq). +Removed top 1 bits (of 5) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:30$255 ($eq). +Removed top 1 bits (of 5) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:36$268 ($eq). +Removed top 3 bits (of 8) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:38$271 ($eq). +Removed top 3 bits (of 8) from port B of cell lsc1_packet_rx_status_accept.$eq$formal/lsc1_packet_rx_status_accept.sv:39$274 ($eq). +Removed top 3 bits (of 8) from mux cell lsc1_packet_rx_status_accept.$procmux$300 ($mux). +Removed top 1 bits (of 8) from mux cell lsc1_packet_rx_status_accept.$procmux$321 ($mux). +Removed top 1 bits (of 8) from wire lsc1_packet_rx_status_accept.$6\rx_data[7:0]. +Removed top 3 bits (of 8) from wire lsc1_packet_rx_status_accept.$7\rx_data[7:0]. + +3.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_rx_status_accept.. +Removed 0 unused cells and 36 unused wires. + + +3.9. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.10. Executing OPT pass (performing simple optimizations). + +3.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx. +Optimizing module lsc1_packet_rx_status_accept. + +3.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_rx'. +Finding identical cells in module `\lsc1_packet_rx_status_accept'. +Removed a total of 0 cells. + +3.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_rx.. +Finding unused cells or wires in module \lsc1_packet_rx_status_accept.. + +3.10.4. Finished fast OPT passes. + +3.11. Printing statistics. + +=== lsc1_packet_rx === + + Number of wires: 237 + Number of wire bits: 25229 + Number of public wires: 33 + Number of public wire bits: 2350 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 211 + $add 3 + $and 1 + $dff 15 + $eq 9 + $gt 1 + $logic_and 5 + $logic_not 6 + $logic_or 3 + $lt 2 + $mul 1 + $mux 120 + $ne 4 + $neg 1 + $not 19 + $or 1 + $pmux 12 + $reduce_bool 2 + $reduce_or 1 + $shift 2 + $sub 2 + $xor 1 + +=== lsc1_packet_rx_status_accept === + + Number of wires: 57 + Number of wire bits: 2303 + Number of public wires: 24 + Number of public wire bits: 2228 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 43 + $add 1 + $anyseq 1 + $assert 3 + $assume 1 + $dff 5 + $eq 10 + $ge 1 + $le 1 + $logic_and 4 + $logic_not 3 + $mux 11 + $reduce_bool 1 + lsc1_packet_rx 1 + +=== design hierarchy === + + lsc1_packet_rx_status_accept 1 + lsc1_packet_rx 1 + + Number of wires: 294 + Number of wire bits: 27532 + Number of public wires: 57 + Number of public wire bits: 4578 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 253 + $add 4 + $and 1 + $anyseq 1 + $assert 3 + $assume 1 + $dff 20 + $eq 19 + $ge 1 + $gt 1 + $le 1 + $logic_and 9 + $logic_not 9 + $logic_or 3 + $lt 2 + $mul 1 + $mux 131 + $ne 4 + $neg 1 + $not 19 + $or 1 + $pmux 12 + $reduce_bool 3 + $reduce_or 1 + $shift 2 + $sub 2 + $xor 1 + +3.12. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_rx... +Checking module lsc1_packet_rx_status_accept... +Found and reported 0 problems. + +4. Executing FLATTEN pass (flatten design). +Deleting now unused module lsc1_packet_rx. + + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx_status_accept. + + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_rx_status_accept'. + +Removed a total of 1 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_rx_status_accept.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_rx_status_accept. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_rx_status_accept'. +Removed a total of 0 cells. + +5.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\dut.$procdff$1318 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1306_Y, Q = \dut.frame_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$1439 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1306_Y, Q = \dut.frame_valid). +Adding SRST signal on $flatten\dut.$procdff$1319 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1281_Y, Q = \dut.frame_opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$1457 ($sdff) from module lsc1_packet_rx_status_accept (D = \dut.opcode, Q = \dut.frame_opcode). +Adding SRST signal on $flatten\dut.$procdff$1320 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1258_Y, Q = \dut.frame_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$1469 ($sdff) from module lsc1_packet_rx_status_accept (D = \dut.declared_length, Q = \dut.frame_length). +Adding SRST signal on $flatten\dut.$procdff$1321 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$2$lookahead\frame_payload$22[2047:0]$81, Q = \dut.frame_payload, rval = 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$1481 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$3$lookahead\frame_payload$22[2047:0]$99, Q = \dut.frame_payload). +Adding SRST signal on $flatten\dut.$procdff$1322 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1235_Y, Q = \dut.fault_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$1491 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1235_Y, Q = \dut.fault_valid). +Adding SRST signal on $flatten\dut.$procdff$1323 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1199_Y, Q = \dut.fault_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$1511 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1186_Y, Q = \dut.fault_status). +Adding SRST signal on $flatten\dut.$procdff$1324 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1165_Y, Q = \dut.state, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$1529 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1165_Y, Q = \dut.state). +Adding SRST signal on $flatten\dut.$procdff$1325 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1126_Y, Q = \dut.header_index, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$1541 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1120_Y, Q = \dut.header_index). +Adding SRST signal on $flatten\dut.$procdff$1326 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1112_Y, Q = \dut.body_index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$1549 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1105_Y, Q = \dut.body_index). +Adding SRST signal on $flatten\dut.$procdff$1327 ($dff) from module lsc1_packet_rx_status_accept (D = { $flatten\dut.$procmux$610_Y $flatten\dut.$procmux$624_Y }, Q = \dut.declared_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$1557 ($sdff) from module lsc1_packet_rx_status_accept (D = \dut.rx_data, Q = \dut.declared_length [7:0]). +Adding EN signal on $auto$ff.cc:266:slice$1557 ($sdff) from module lsc1_packet_rx_status_accept (D = \dut.rx_data, Q = \dut.declared_length [15:8]). +Adding SRST signal on $flatten\dut.$procdff$1328 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1084_Y, Q = \dut.version, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$1564 ($sdff) from module lsc1_packet_rx_status_accept (D = \dut.rx_data, Q = \dut.version). +Adding SRST signal on $flatten\dut.$procdff$1329 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1067_Y, Q = \dut.opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$1568 ($sdff) from module lsc1_packet_rx_status_accept (D = \dut.rx_data, Q = \dut.opcode). +Adding SRST signal on $flatten\dut.$procdff$1330 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1051_Y, Q = \dut.flags, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$1572 ($sdff) from module lsc1_packet_rx_status_accept (D = \dut.rx_data, Q = \dut.flags). +Adding SRST signal on $flatten\dut.$procdff$1331 ($dff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1036_Y, Q = \dut.crc, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$1576 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$1029_Y, Q = \dut.crc). +Adding SRST signal on $flatten\dut.$procdff$1332 ($dff) from module lsc1_packet_rx_status_accept (D = { $flatten\dut.$procmux$393_Y $flatten\dut.$procmux$409_Y $flatten\dut.$procmux$426_Y $flatten\dut.$procmux$444_Y }, Q = \dut.received_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$1586 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$390_Y, Q = \dut.received_crc [31:24]). +Adding EN signal on $auto$ff.cc:266:slice$1586 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$441_Y, Q = \dut.received_crc [7:0]). +Adding EN signal on $auto$ff.cc:266:slice$1586 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$423_Y, Q = \dut.received_crc [15:8]). +Adding EN signal on $auto$ff.cc:266:slice$1586 ($sdff) from module lsc1_packet_rx_status_accept (D = $flatten\dut.$procmux$406_Y, Q = \dut.received_crc [23:16]). + +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_rx_status_accept.. +Removed 102 unused cells and 111 unused wires. + + +5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx_status_accept. + + +5.9. Rerunning OPT passes. (Maybe there is more to do..) + +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_rx_status_accept.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_rx_status_accept. +Performed a total of 0 changes. + +5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_rx_status_accept'. + +Removed a total of 15 cells. + +5.13. Executing OPT_DFF pass (perform DFF optimizations). + +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_rx_status_accept.. +Removed 0 unused cells and 18 unused wires. + + +5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx_status_accept. + +5.16. Rerunning OPT passes. (Maybe there is more to do..) + +5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_rx_status_accept.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_rx_status_accept. +Performed a total of 0 changes. + +5.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_rx_status_accept'. +Removed a total of 0 cells. + +5.20. Executing OPT_DFF pass (perform DFF optimizations). + +5.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_rx_status_accept.. + +5.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_rx_status_accept. + +5.23. Finished OPT passes. (There is nothing left to do.) + +6. Executing SAT pass (solving SAT problems in the circuit). + +Setting up time step 1: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import set-constraint from init attribute: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN = 1'0 +Final init constraint equation: { $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK \step \dut.received_crc [23:0] \dut.crc \dut.flags \dut.opcode \dut.version \dut.declared_length \dut.body_index \dut.header_index \dut.state \dut.fault_valid \dut.frame_length \dut.frame_opcode \dut.frame_valid $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN } = 153'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 2: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 3: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 4: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 5: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 6: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 7: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 8: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 9: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 10: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 11: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 12: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Setting up time step 13: +Final constraint equation: { } = { } +Imported 201 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:37$241_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. +Import proof for assert: $formal$formal/lsc1_packet_rx_status_accept.sv:38$242_CHECK when $formal$formal/lsc1_packet_rx_status_accept.sv:36$240_EN. + +Solving problem with 122884 variables and 335302 clauses.. +SAT proof finished - no model found: SUCCESS! + + /$$$$$$ /$$$$$$$$ /$$$$$$$ + /$$__ $$ | $$_____/ | $$__ $$ + | $$ \ $$ | $$ | $$ \ $$ + | $$ | $$ | $$$$$ | $$ | $$ + | $$ | $$ | $$__/ | $$ | $$ + | $$/$$ $$ | $$ | $$ | $$ + | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ + \____ $$$|__/|________/|__/|_______/|__/ + \__/ + +End of script. Logfile hash: e9b3f2180a, CPU: user 5.85s system 0.08s, MEM: 106.27 MB peak +Yosys 0.33 (git sha1 2584903a060) +Time spent: 42% 1x proc_mux (2 sec), 20% 3x opt_dff (1 sec), ... diff --git a/results/frontend-bounded-path-20260728/status-response.log b/results/frontend-bounded-path-20260728/status-response.log new file mode 100644 index 0000000..c8b38ae --- /dev/null +++ b/results/frontend-bounded-path-20260728/status-response.log @@ -0,0 +1,1753 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.33 (git sha1 2584903a060) + + +-- Executing script file `formal/lsc1_packet_tx_status_response.ys' -- + +1. Executing Verilog-2005 frontend: asic_core/rtl/lsc1_packet_tx.sv +Parsing formal SystemVerilog input from `asic_core/rtl/lsc1_packet_tx.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_tx'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: formal/lsc1_packet_tx_status_response.sv +Parsing formal SystemVerilog input from `formal/lsc1_packet_tx_status_response.sv' to AST representation. +Generating RTLIL representation for module `\lsc1_packet_tx_status_response'. +Successfully finished Verilog frontend. + +3. Executing PREP pass. + +3.1. Executing HIERARCHY pass (managing design hierarchy). + +3.1.1. Analyzing design hierarchy.. +Top module: \lsc1_packet_tx_status_response +Used module: \lsc1_packet_tx + +3.1.2. Analyzing design hierarchy.. +Top module: \lsc1_packet_tx_status_response +Used module: \lsc1_packet_tx +Removed 0 unused modules. +Module lsc1_packet_tx_status_response directly or indirectly contains formal properties -> setting "keep" attribute. + +3.2. Executing PROC pass (convert processes to netlists). + +3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$formal/lsc1_packet_tx_status_response.sv:25$309 in module lsc1_packet_tx_status_response. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:79$20 in module lsc1_packet_tx. +Marked 7 switch rules as full_case in process $proc$asic_core/rtl/lsc1_packet_tx.sv:61$6 in module lsc1_packet_tx. +Removed a total of 0 dead cases. + +3.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 1 redundant assignment. +Promoted 36 assignments to connections. + +3.2.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$389'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$387'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$385'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$383'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$381'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$379'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$377'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$375'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$373'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$371'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$369'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN = 1'0 +Found init rule in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$367'. + Set init value: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN = 1'0 + +3.2.5. Executing PROC_ARST pass (detect async resets in processes). + +3.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$389'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$387'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$385'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$383'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$381'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$379'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$377'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$375'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$373'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$371'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$369'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$367'. +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + 1/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN[0:0]$311 + 2/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK[0:0]$310 + 3/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN[0:0]$313 + 4/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK[0:0]$312 + 5/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN[0:0]$315 + 6/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK[0:0]$314 + 7/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN[0:0]$317 + 8/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK[0:0]$316 + 9/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN[0:0]$319 + 10/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK[0:0]$318 + 11/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN[0:0]$321 + 12/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK[0:0]$320 + 13/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN[0:0]$323 + 14/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK[0:0]$322 + 15/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN[0:0]$325 + 16/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK[0:0]$324 + 17/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN[0:0]$327 + 18/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK[0:0]$326 + 19/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN[0:0]$329 + 20/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK[0:0]$328 + 21/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN[0:0]$331 + 22/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK[0:0]$330 + 23/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN[0:0]$333 + 24/24: $0$formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK[0:0]$332 +Creating decoders for process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:24$305'. +Creating decoders for process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + 1/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.$result[31:0]$207 + 2/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.bit_index[31:0]$210 + 3/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.work[31:0]$211 + 4/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.data[7:0]$209 + 5/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.crc_in[31:0]$208 + 6/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.$result[31:0]$202 + 7/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.bit_index[31:0]$205 + 8/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.work[31:0]$206 + 9/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.data[7:0]$204 + 10/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.crc_in[31:0]$203 + 11/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.$result[31:0]$162 + 12/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.bit_index[31:0]$165 + 13/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.work[31:0]$166 + 14/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.data[7:0]$164 + 15/105: $5\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.crc_in[31:0]$163 + 16/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.work[31:0]$127 + 17/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.bit_index[31:0]$126 + 18/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.data[7:0]$125 + 19/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.crc_in[31:0]$124 + 20/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.$result[31:0]$123 + 21/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.work[31:0]$122 + 22/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.bit_index[31:0]$121 + 23/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.data[7:0]$120 + 24/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.crc_in[31:0]$119 + 25/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.$result[31:0]$118 + 26/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.work[31:0]$117 + 27/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.bit_index[31:0]$116 + 28/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.data[7:0]$115 + 29/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.crc_in[31:0]$114 + 30/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.$result[31:0]$113 + 31/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.$result[31:0]$108 + 32/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.bit_index[31:0]$111 + 33/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.work[31:0]$112 + 34/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.data[7:0]$110 + 35/105: $4\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.crc_in[31:0]$109 + 36/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.work[31:0]$105 + 37/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.bit_index[31:0]$104 + 38/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.data[7:0]$103 + 39/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.crc_in[31:0]$102 + 40/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.$result[31:0]$101 + 41/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.work[31:0]$100 + 42/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.bit_index[31:0]$99 + 43/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.data[7:0]$98 + 44/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.crc_in[31:0]$97 + 45/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.$result[31:0]$96 + 46/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.work[31:0]$95 + 47/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.bit_index[31:0]$94 + 48/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.data[7:0]$93 + 49/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.crc_in[31:0]$92 + 50/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.$result[31:0]$91 + 51/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.work[31:0]$90 + 52/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.bit_index[31:0]$89 + 53/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.data[7:0]$88 + 54/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.crc_in[31:0]$87 + 55/105: $3\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.$result[31:0]$86 + 56/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.work[31:0]$84 + 57/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.bit_index[31:0]$83 + 58/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.data[7:0]$82 + 59/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.crc_in[31:0]$81 + 60/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.$result[31:0]$80 + 61/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.work[31:0]$79 + 62/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.bit_index[31:0]$78 + 63/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.data[7:0]$77 + 64/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.crc_in[31:0]$76 + 65/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.$result[31:0]$75 + 66/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.work[31:0]$74 + 67/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.bit_index[31:0]$73 + 68/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.data[7:0]$72 + 69/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.crc_in[31:0]$71 + 70/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.$result[31:0]$70 + 71/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.work[31:0]$69 + 72/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.bit_index[31:0]$68 + 73/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.data[7:0]$67 + 74/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.crc_in[31:0]$66 + 75/105: $2\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.$result[31:0]$65 + 76/105: $0\done_pulse[0:0] + 77/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.work[31:0]$62 + 78/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.bit_index[31:0]$61 + 79/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.data[7:0]$60 + 80/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.crc_in[31:0]$59 + 81/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.$result[31:0]$58 + 82/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.work[31:0]$57 + 83/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.bit_index[31:0]$56 + 84/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.data[7:0]$55 + 85/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.crc_in[31:0]$54 + 86/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.$result[31:0]$53 + 87/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.work[31:0]$52 + 88/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.bit_index[31:0]$51 + 89/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.data[7:0]$50 + 90/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.crc_in[31:0]$49 + 91/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.$result[31:0]$48 + 92/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.work[31:0]$47 + 93/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.bit_index[31:0]$46 + 94/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.data[7:0]$45 + 95/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.crc_in[31:0]$44 + 96/105: $1\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.$result[31:0]$43 + 97/105: $0\payload_crc_work[31:0] + 98/105: $0\envelope_crc_work[31:0] + 99/105: $0\saved_crc[31:0] + 100/105: $0\saved_payload[543:0] + 101/105: $0\saved_status[7:0] + 102/105: $0\saved_length[15:0] + 103/105: $0\index[15:0] + 104/105: $0\active[0:0] + 105/105: $0\payload_crc[31:0] +Creating decoders for process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:61$6'. + 1/7: $7\tx_data[7:0] + 2/7: $6\tx_data[7:0] + 3/7: $5\tx_data[7:0] + 4/7: $4\tx_data[7:0] + 5/7: $3\tx_data[7:0] + 6/7: $2\tx_data[7:0] + 7/7: $1\tx_data[7:0] + +3.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:24$285_CHECK' from process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:24$305'. +No latch inferred for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:24$285_EN' from process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:24$305'. +No latch inferred for signal `\lsc1_packet_tx.\tx_data' from process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:61$6'. + +3.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\lsc1_packet_tx_status_response.\step' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1609' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1610' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1611' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1612' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1613' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1614' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1615' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1616' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1617' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1618' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1619' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1620' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1621' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1622' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1623' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1624' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1625' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1626' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1627' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1628' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1629' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1630' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1631' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1632' with positive edge clock. +Creating register for signal `\lsc1_packet_tx_status_response.$formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN' using process `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. + created $dff cell `$procdff$1633' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\done_pulse' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1634' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1635' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\active' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1636' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1637' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_length' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1638' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_status' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1639' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_payload' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1640' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\saved_crc' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1641' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\envelope_crc_work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1642' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\payload_crc_work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1643' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1644' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1645' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1646' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1647' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:104$2.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1648' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1649' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1650' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1651' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1652' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:106$3.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1653' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1654' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1655' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1656' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1657' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:108$4.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1658' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.$result' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1659' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.crc_in' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1660' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.data' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1661' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.bit_index' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1662' with positive edge clock. +Creating register for signal `\lsc1_packet_tx.\crc_byte$func$asic_core/rtl/lsc1_packet_tx.sv:110$5.work' using process `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. + created $dff cell `$procdff$1663' with positive edge clock. + +3.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$389'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$387'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$385'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$383'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$381'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$379'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$377'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$375'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$373'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$371'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$369'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:0$367'. +Found and cleaned up 3 empty switches in `\lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:25$309'. +Removing empty process `lsc1_packet_tx_status_response.$proc$formal/lsc1_packet_tx_status_response.sv:24$305'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. +Removing empty process `lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:79$20'. +Found and cleaned up 7 empty switches in `\lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:61$6'. +Removing empty process `lsc1_packet_tx.$proc$asic_core/rtl/lsc1_packet_tx.sv:61$6'. +Cleaned up 17 empty switches. + +3.2.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx_status_response. + +Optimizing module lsc1_packet_tx. + + +3.3. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx_status_response. +Optimizing module lsc1_packet_tx. + +3.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_tx_status_response.. +Finding unused cells or wires in module \lsc1_packet_tx.. +Removed 295 unused cells and 902 unused wires. + + +3.5. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_tx... +Checking module lsc1_packet_tx_status_response... +Found and reported 0 problems. + +3.6. Executing OPT pass (performing simple optimizations). + +3.6.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx. +Optimizing module lsc1_packet_tx_status_response. + +3.6.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_tx'. + +Finding identical cells in module `\lsc1_packet_tx_status_response'. + +Removed a total of 34 cells. + +3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_tx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$1529. + dead port 1/2 on $mux $procmux$1532. + dead port 1/2 on $mux $procmux$1535. + dead port 1/2 on $mux $procmux$1538. + dead port 1/2 on $mux $procmux$1541. + dead port 1/2 on $mux $procmux$1544. + dead port 1/2 on $mux $procmux$1550. + dead port 1/2 on $mux $procmux$1553. + dead port 1/2 on $mux $procmux$1556. + dead port 1/2 on $mux $procmux$1559. + dead port 1/2 on $mux $procmux$1562. + dead port 1/2 on $mux $procmux$1568. + dead port 1/2 on $mux $procmux$1571. + dead port 1/2 on $mux $procmux$1574. + dead port 1/2 on $mux $procmux$1577. + dead port 1/2 on $mux $procmux$1583. + dead port 1/2 on $mux $procmux$1586. + dead port 1/2 on $mux $procmux$1589. + dead port 1/2 on $mux $procmux$1595. + dead port 1/2 on $mux $procmux$1598. + dead port 1/2 on $mux $procmux$1604. +Running muxtree optimizer on module \lsc1_packet_tx_status_response.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 21 multiplexer ports. + + +3.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_tx. + Optimizing cells in module \lsc1_packet_tx_status_response. + New ctrl vector for $pmux cell $procmux$558: $auto$opt_reduce.cc:134:opt_pmux$1729 + New ctrl vector for $pmux cell $procmux$571: $auto$opt_reduce.cc:134:opt_pmux$1731 + Optimizing cells in module \lsc1_packet_tx_status_response. +Performed a total of 2 changes. + +3.6.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_tx'. + +Finding identical cells in module `\lsc1_packet_tx_status_response'. + +Removed a total of 31 cells. + +3.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_packet_tx_status_response.. +Removed 0 unused cells and 102 unused wires. + + +3.6.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx. +Optimizing module lsc1_packet_tx_status_response. + +3.6.8. Rerunning OPT passes. (Maybe there is more to do..) + +3.6.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_tx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \lsc1_packet_tx_status_response.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.6.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_tx. + Optimizing cells in module \lsc1_packet_tx_status_response. +Performed a total of 0 changes. + +3.6.11. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_tx'. +Finding identical cells in module `\lsc1_packet_tx_status_response'. +Removed a total of 0 cells. + +3.6.12. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_packet_tx_status_response.. + +3.6.13. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx. +Optimizing module lsc1_packet_tx_status_response. + +3.6.14. Finished OPT passes. (There is nothing left to do.) + +3.7. Executing WREDUCE pass (reducing word size of cells). +Removed top 15 bits (of 16) from port B of cell lsc1_packet_tx.$eq$asic_core/rtl/lsc1_packet_tx.sv:63$8 ($eq). +Removed top 14 bits (of 16) from port B of cell lsc1_packet_tx.$eq$asic_core/rtl/lsc1_packet_tx.sv:64$9 ($eq). +Removed top 14 bits (of 16) from port B of cell lsc1_packet_tx.$eq$asic_core/rtl/lsc1_packet_tx.sv:65$10 ($eq). +Removed top 13 bits (of 16) from port B of cell lsc1_packet_tx.$eq$asic_core/rtl/lsc1_packet_tx.sv:66$11 ($eq). +Removed top 29 bits (of 32) from port A of cell lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:67$12 ($add). +Removed top 15 bits (of 32) from port Y of cell lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:67$12 ($add). +Removed top 15 bits (of 32) from port B of cell lsc1_packet_tx.$lt$asic_core/rtl/lsc1_packet_tx.sv:67$13 ($lt). +Removed top 29 bits (of 32) from port B of cell lsc1_packet_tx.$sub$asic_core/rtl/lsc1_packet_tx.sv:68$14 ($sub). +Removed top 15 bits (of 32) from port Y of cell lsc1_packet_tx.$sub$asic_core/rtl/lsc1_packet_tx.sv:68$14 ($sub). +Removed top 28 bits (of 32) from port B of cell lsc1_packet_tx.$mul$asic_core/rtl/lsc1_packet_tx.sv:68$15 ($mul). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:0$16 ($add). +Removed top 29 bits (of 32) from port B of cell lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:103$106 ($add). +Removed top 15 bits (of 32) from port Y of cell lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:103$106 ($add). +Removed top 15 bits (of 32) from port B of cell lsc1_packet_tx.$le$asic_core/rtl/lsc1_packet_tx.sv:103$107 ($le). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1664 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1666 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1668 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1670 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1672 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1674 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1676 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1678 ($not). +Removed top 29 bits (of 32) from port B of cell lsc1_packet_tx.$ge$asic_core/rtl/lsc1_packet_tx.sv:105$161 ($ge). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1680 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1684 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1686 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1688 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1690 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1692 ($not). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1694 ($not). +Removed top 15 bits (of 32) from port B of cell lsc1_packet_tx.$eq$asic_core/rtl/lsc1_packet_tx.sv:107$201 ($eq). +Removed top 1 bits (of 14) from port A of cell lsc1_packet_tx.$auto$opt_expr.cc:706:replace_const_cells$1714 ($not). +Removed top 28 bits (of 32) from port B of cell lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:113$282 ($add). +Removed top 15 bits (of 32) from port Y of cell lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:113$282 ($add). +Removed top 15 bits (of 32) from port B of cell lsc1_packet_tx.$eq$asic_core/rtl/lsc1_packet_tx.sv:113$283 ($eq). +Removed top 30 bits (of 32) from port B of cell lsc1_packet_tx.$procmux$1525_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell lsc1_packet_tx.$procmux$1526_CMP0 ($eq). +Removed top 15 bits (of 32) from wire lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:103$106_Y. +Removed top 15 bits (of 32) from wire lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:113$282_Y. +Removed top 15 bits (of 32) from wire lsc1_packet_tx.$add$asic_core/rtl/lsc1_packet_tx.sv:67$12_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$129_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$133_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$137_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$141_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$145_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$149_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$153_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$157_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$168_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$172_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$176_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$180_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$184_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$188_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$192_Y. +Removed top 1 bits (of 32) from wire lsc1_packet_tx.$shr$asic_core/rtl/lsc1_packet_tx.sv:45$196_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$132_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$136_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$140_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$144_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$148_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$152_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$156_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$171_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$175_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$179_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$183_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$187_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$191_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$195_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$xor$asic_core/rtl/lsc1_packet_tx.sv:43$128_Y. +Removed top 31 bits (of 32) from wire lsc1_packet_tx.$xor$asic_core/rtl/lsc1_packet_tx.sv:43$167_Y. +Removed top 4 bits (of 5) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:10$300 ($eq). +Removed top 3 bits (of 5) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:14$301 ($eq). +Removed top 2 bits (of 5) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:14$302 ($eq). +Removed top 6 bits (of 8) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:28$336 ($eq). +Removed top 1 bits (of 8) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:30$340 ($eq). +Removed top 7 bits (of 8) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:30$341 ($eq). +Removed top 6 bits (of 8) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:31$342 ($eq). +Removed top 1 bits (of 8) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:32$345 ($eq). +Removed top 1 bits (of 8) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:33$347 ($eq). +Removed top 4 bits (of 8) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:34$348 ($eq). +Removed top 1 bits (of 5) from port B of cell lsc1_packet_tx_status_response.$eq$formal/lsc1_packet_tx_status_response.sv:37$349 ($eq). +Removed top 15 bits (of 16) from port B of cell lsc1_packet_tx_status_response.$procmux$430_CMP0 ($eq). +Removed top 14 bits (of 16) from port B of cell lsc1_packet_tx_status_response.$procmux$453_CMP0 ($eq). +Removed top 14 bits (of 16) from port B of cell lsc1_packet_tx_status_response.$procmux$474_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell lsc1_packet_tx_status_response.$procmux$493_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell lsc1_packet_tx_status_response.$procmux$510_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell lsc1_packet_tx_status_response.$procmux$525_CMP0 ($eq). +Removed top 13 bits (of 16) from port B of cell lsc1_packet_tx_status_response.$procmux$538_CMP0 ($eq). +Removed top 12 bits (of 16) from port B of cell lsc1_packet_tx_status_response.$procmux$549_CMP0 ($eq). + +3.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_packet_tx_status_response.. +Removed 0 unused cells and 35 unused wires. + + +3.9. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.10. Executing OPT pass (performing simple optimizations). + +3.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx. +Optimizing module lsc1_packet_tx_status_response. + +3.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_tx'. +Finding identical cells in module `\lsc1_packet_tx_status_response'. +Removed a total of 0 cells. + +3.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_tx.. +Finding unused cells or wires in module \lsc1_packet_tx_status_response.. + +3.10.4. Finished fast OPT passes. + +3.11. Printing statistics. + +=== lsc1_packet_tx === + + Number of wires: 155 + Number of wire bits: 5505 + Number of public wires: 31 + Number of public wire bits: 2011 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 119 + $add 5 + $dff 10 + $eq 8 + $ge 1 + $le 1 + $logic_and 2 + $logic_not 5 + $logic_or 1 + $lt 1 + $mul 1 + $mux 60 + $not 18 + $pmux 1 + $shiftx 1 + $sub 2 + $xor 2 + +=== lsc1_packet_tx_status_response === + + Number of wires: 124 + Number of wire bits: 1439 + Number of public wires: 24 + Number of public wire bits: 1335 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 119 + $add 1 + $anyseq 1 + $assert 12 + $assume 1 + $dff 25 + $eq 20 + $logic_and 5 + $logic_not 6 + $logic_or 1 + $mux 44 + $reduce_bool 1 + $reduce_or 1 + lsc1_packet_tx 1 + +=== design hierarchy === + + lsc1_packet_tx_status_response 1 + lsc1_packet_tx 1 + + Number of wires: 279 + Number of wire bits: 6944 + Number of public wires: 55 + Number of public wire bits: 3346 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 237 + $add 6 + $anyseq 1 + $assert 12 + $assume 1 + $dff 35 + $eq 28 + $ge 1 + $le 1 + $logic_and 7 + $logic_not 11 + $logic_or 2 + $lt 1 + $mul 1 + $mux 104 + $not 18 + $pmux 1 + $reduce_bool 1 + $reduce_or 1 + $shiftx 1 + $sub 2 + $xor 2 + +3.12. Executing CHECK pass (checking for obvious problems). +Checking module lsc1_packet_tx... +Checking module lsc1_packet_tx_status_response... +Found and reported 0 problems. + +4. Executing FLATTEN pass (flatten design). +Deleting now unused module lsc1_packet_tx. + + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx_status_response. + + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_tx_status_response'. + +Removed a total of 7 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_tx_status_response.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_tx_status_response. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_tx_status_response'. +Removed a total of 0 cells. + +5.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$1631 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$558_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN, rval = 1'0). +Adding SRST signal on $procdff$1629 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$548_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN, rval = 1'0). +Adding SRST signal on $procdff$1627 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$537_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN, rval = 1'0). +Adding SRST signal on $procdff$1625 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$524_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN, rval = 1'0). +Adding SRST signal on $procdff$1623 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$509_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN, rval = 1'0). +Adding SRST signal on $procdff$1621 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$492_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN, rval = 1'0). +Adding SRST signal on $procdff$1619 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$473_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN, rval = 1'0). +Adding SRST signal on $procdff$1617 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$452_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN, rval = 1'0). +Adding SRST signal on $procdff$1615 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$429_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN, rval = 1'0). +Adding SRST signal on $procdff$1613 ($dff) from module lsc1_packet_tx_status_response (D = $procmux$404_Y, Q = $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN, rval = 1'0). +Adding SRST signal on $flatten\dut.$procdff$1634 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1354_Y, Q = \dut.done_pulse, rval = 1'0). +Adding SRST signal on $flatten\dut.$procdff$1635 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1518_Y, Q = \dut.payload_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$1784 ($sdff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_tx.sv:109$281_Y, Q = \dut.payload_crc). +Adding SRST signal on $flatten\dut.$procdff$1636 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1503_Y, Q = \dut.active, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$1790 ($sdff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1503_Y, Q = \dut.active). +Adding SRST signal on $flatten\dut.$procdff$1637 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1488_Y, Q = \dut.index, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$1798 ($sdff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$add$asic_core/rtl/lsc1_packet_tx.sv:117$284_Y, Q = \dut.index). +Adding SRST signal on $flatten\dut.$procdff$1638 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1479_Y, Q = \dut.saved_length, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$1808 ($sdff) from module lsc1_packet_tx_status_response (D = 16'0000000000000000, Q = \dut.saved_length). +Adding SRST signal on $flatten\dut.$procdff$1639 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1473_Y, Q = \dut.saved_status, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:266:slice$1810 ($sdff) from module lsc1_packet_tx_status_response (D = 8'00000011, Q = \dut.saved_status). +Adding SRST signal on $flatten\dut.$procdff$1640 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1467_Y, Q = \dut.saved_payload, rval = 544'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:266:slice$1812 ($sdff) from module lsc1_packet_tx_status_response (D = 544'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Q = \dut.saved_payload). +Adding SRST signal on $flatten\dut.$procdff$1641 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1458_Y, Q = \dut.saved_crc, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$1814 ($sdff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$not$asic_core/rtl/lsc1_packet_tx.sv:108$245_Y, Q = \dut.saved_crc). +Adding SRST signal on $flatten\dut.$procdff$1642 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1443_Y, Q = \dut.envelope_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$1822 ($sdff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$160_Y, Q = \dut.envelope_crc_work). +Adding SRST signal on $flatten\dut.$procdff$1643 ($dff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$procmux$1431_Y, Q = \dut.payload_crc_work, rval = 32'11111111111111111111111111111111). +Adding EN signal on $auto$ff.cc:266:slice$1830 ($sdff) from module lsc1_packet_tx_status_response (D = $flatten\dut.$ternary$asic_core/rtl/lsc1_packet_tx.sv:45$199_Y, Q = \dut.payload_crc_work). +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 33 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 34 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 35 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 36 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 37 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 38 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 39 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 40 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 41 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 42 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 43 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 44 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 45 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 46 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 47 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 48 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 49 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 50 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 51 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 52 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 53 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 54 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 55 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 56 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 57 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 58 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 59 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 60 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 61 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 62 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 63 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 64 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 65 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 66 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 67 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 68 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 69 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 70 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 71 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 72 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 73 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 74 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 75 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 76 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 77 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 78 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 79 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 80 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 81 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 82 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 83 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 84 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 85 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 86 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 87 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 88 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 89 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 90 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 91 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 92 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 93 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 94 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 95 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 96 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 97 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 98 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 99 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 100 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 101 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 102 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 103 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 104 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 105 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 106 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 107 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 108 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 109 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 110 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 111 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 112 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 113 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 114 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 115 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 116 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 117 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 118 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 119 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 120 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 121 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 122 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 123 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 124 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 125 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 126 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 127 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 128 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 129 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 130 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 131 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 132 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 133 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 134 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 135 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 136 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 137 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 138 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 139 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 140 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 141 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 142 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 143 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 144 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 145 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 146 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 147 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 148 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 149 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 150 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 151 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 152 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 153 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 154 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 155 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 156 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 157 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 158 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 159 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 160 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 161 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 162 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 163 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 164 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 165 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 166 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 167 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 168 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 169 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 170 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 171 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 172 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 173 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 174 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 175 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 176 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 177 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 178 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 179 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 180 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 181 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 182 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 183 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 184 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 185 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 186 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 187 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 188 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 189 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 190 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 191 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 192 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 193 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 194 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 195 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 196 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 197 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 198 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 199 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 200 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 201 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 202 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 203 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 204 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 205 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 206 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 207 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 208 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 209 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 210 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 211 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 212 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 213 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 214 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 215 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 216 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 217 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 218 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 219 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 220 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 221 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 222 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 223 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 224 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 225 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 226 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 227 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 228 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 229 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 230 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 231 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 232 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 233 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 234 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 235 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 236 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 237 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 238 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 239 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 240 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 241 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 242 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 243 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 244 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 245 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 246 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 247 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 248 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 249 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 250 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 251 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 252 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 253 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 254 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 255 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 256 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 257 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 258 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 259 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 260 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 261 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 262 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 263 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 264 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 265 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 266 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 267 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 268 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 269 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 270 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 271 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 272 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 273 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 274 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 275 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 276 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 277 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 278 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 279 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 280 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 281 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 282 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 283 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 284 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 285 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 286 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 287 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 288 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 289 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 290 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 291 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 292 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 293 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 294 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 295 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 296 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 297 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 298 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 299 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 300 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 301 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 302 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 303 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 304 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 305 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 306 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 307 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 308 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 309 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 310 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 311 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 312 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 313 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 314 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 315 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 316 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 317 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 318 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 319 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 320 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 321 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 322 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 323 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 324 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 325 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 326 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 327 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 328 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 329 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 330 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 331 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 332 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 333 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 334 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 335 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 336 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 337 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 338 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 339 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 340 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 341 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 342 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 343 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 344 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 345 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 346 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 347 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 348 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 349 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 350 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 351 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 352 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 353 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 354 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 355 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 356 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 357 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 358 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 359 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 360 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 361 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 362 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 363 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 364 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 365 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 366 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 367 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 368 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 369 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 370 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 371 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 372 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 373 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 374 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 375 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 376 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 377 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 378 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 379 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 380 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 381 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 382 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 383 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 384 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 385 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 386 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 387 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 388 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 389 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 390 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 391 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 392 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 393 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 394 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 395 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 396 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 397 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 398 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 399 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 400 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 401 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 402 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 403 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 404 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 405 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 406 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 407 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 408 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 409 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 410 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 411 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 412 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 413 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 414 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 415 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 416 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 417 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 418 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 419 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 420 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 421 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 422 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 423 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 424 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 425 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 426 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 427 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 428 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 429 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 430 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 431 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 432 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 433 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 434 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 435 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 436 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 437 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 438 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 439 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 440 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 441 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 442 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 443 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 444 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 445 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 446 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 447 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 448 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 449 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 450 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 451 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 452 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 453 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 454 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 455 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 456 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 457 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 458 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 459 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 460 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 461 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 462 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 463 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 464 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 465 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 466 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 467 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 468 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 469 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 470 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 471 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 472 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 473 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 474 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 475 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 476 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 477 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 478 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 479 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 480 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 481 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 482 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 483 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 484 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 485 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 486 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 487 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 488 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 489 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 490 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 491 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 492 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 493 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 494 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 495 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 496 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 497 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 498 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 499 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 500 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 501 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 502 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 503 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 504 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 505 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 506 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 507 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 508 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 509 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 510 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 511 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 512 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 513 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 514 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 515 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 516 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 517 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 518 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 519 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 520 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 521 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 522 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 523 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 524 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 525 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 526 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 527 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 528 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 529 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 530 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 531 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 532 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 533 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 534 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 535 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 536 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 537 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 538 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 539 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 540 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 541 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 542 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 543 on $auto$ff.cc:266:slice$1813 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1811 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1811 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1811 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1811 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1811 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1811 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1809 ($sdffe) from module lsc1_packet_tx_status_response. + +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_tx_status_response.. +Removed 44 unused cells and 55 unused wires. + + +5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx_status_response. + + +5.9. Rerunning OPT passes. (Maybe there is more to do..) + +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_tx_status_response.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_tx_status_response. +Performed a total of 0 changes. + +5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_tx_status_response'. + +Removed a total of 7 cells. + +5.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. +Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$1785 ($sdffe) from module lsc1_packet_tx_status_response. + +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_tx_status_response.. +Removed 23 unused cells and 44 unused wires. + + +5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx_status_response. + + +5.16. Rerunning OPT passes. (Maybe there is more to do..) + +5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_tx_status_response.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_tx_status_response. +Performed a total of 0 changes. + +5.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_tx_status_response'. +Removed a total of 0 cells. + +5.20. Executing OPT_DFF pass (perform DFF optimizations). + +5.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_tx_status_response.. +Removed 0 unused cells and 2 unused wires. + + +5.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx_status_response. + +5.23. Rerunning OPT passes. (Maybe there is more to do..) + +5.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \lsc1_packet_tx_status_response.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \lsc1_packet_tx_status_response. +Performed a total of 0 changes. + +5.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\lsc1_packet_tx_status_response'. +Removed a total of 0 cells. + +5.27. Executing OPT_DFF pass (perform DFF optimizations). + +5.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \lsc1_packet_tx_status_response.. + +5.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module lsc1_packet_tx_status_response. + +5.30. Finished OPT passes. (There is nothing left to do.) + +6. Executing SAT pass (solving SAT problems in the circuit). + +Setting up time step 1: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN = 1'0 +Import set-constraint from init attribute: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN = 1'0 +Final init constraint equation: { $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK \step \dut.saved_status [1:0] \dut.envelope_crc_work \dut.saved_crc \dut.index \dut.active \dut.done_pulse $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN } = 113'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 2: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 3: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 4: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 5: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 6: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 7: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 8: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 9: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 10: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 11: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 12: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 13: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Setting up time step 14: +Final constraint equation: { } = { } +Imported 161 cells to SAT database. +Import constraint from assume cell: \dut.clk when 1'1. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:27$286_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:27$286_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$287_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$287_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:30$288_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:30$288_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$289_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$289_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:31$290_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:31$290_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$291_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$291_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:32$292_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:32$292_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$293_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$293_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:33$294_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:33$294_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$295_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$295_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:34$296_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:34$296_EN. +Import proof for assert: $formal$formal/lsc1_packet_tx_status_response.sv:37$297_CHECK when $formal$formal/lsc1_packet_tx_status_response.sv:37$297_EN. + +Solving problem with 102508 variables and 275515 clauses.. +SAT proof finished - no model found: SUCCESS! + + /$$$$$$ /$$$$$$$$ /$$$$$$$ + /$$__ $$ | $$_____/ | $$__ $$ + | $$ \ $$ | $$ | $$ \ $$ + | $$ | $$ | $$$$$ | $$ | $$ + | $$ | $$ | $$__/ | $$ | $$ + | $$/$$ $$ | $$ | $$ | $$ + | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ + \____ $$$|__/|________/|__/|_______/|__/ + \__/ + +End of script. Logfile hash: 3aed429a9f, CPU: user 0.85s system 0.04s, MEM: 81.72 MB peak +Yosys 0.33 (git sha1 2584903a060) +Time spent: 48% 1x sat (0 sec), 12% 11x opt_expr (0 sec), ... diff --git a/results/frontend-bounded-path-20260728/versions-and-inputs.log b/results/frontend-bounded-path-20260728/versions-and-inputs.log new file mode 100644 index 0000000..bdbbb3d --- /dev/null +++ b/results/frontend-bounded-path-20260728/versions-and-inputs.log @@ -0,0 +1,19 @@ +fb3c063ca280e71f8721fefe858d10ce8cca772a +b44242d95e8c942d6192d206c53c24cfe15d8d62 +Yosys 0.33 (git sha1 2584903a060) +Icarus Verilog version 12.0 (stable) () +d24a53bcde88011f57fbd3515e3cf94307e326510c7ccc9c8b6492492de2ebe0 asic_core/rtl/lsc1_packet_rx.sv +1165bb65d343b20526c8e75242d8af0f21986c5a914266ddfdd8cc41538fcb3c asic_core/rtl/lsc1_packet_tx.sv +31944a798695cbf2ae83e6a90afe9212741a93e3f9b01ce97b549abb5d0c4995 asic_core/rtl/lsc1_stream_adapter.sv +1f2ce7746851e1d7bdd1e1ddfa5c0ba80ca1bfec3054f6b54d238673e368d19d asic_core/rtl/lsc1_field_encoder.sv +c16b2e253d6f0bf6394bbcf516693473f65b9d7ecb431f2f653671acdf9d656b asic_core/rtl/lsc1_packet_frontend.sv +d4dd8f33e2a5aade976d06cae7be3bd6d6cf41918499c5bdd20e36132fb95bfe formal/lsc1_packet_frontend_arch_state_map.json +7310dd2063b557716c129398fdc35d049b5982c81e2385f8055942b9e7e4f181 formal/ARCH_STATE.md +faac561322f0831f66924be0afd8a5ae5cca1cb3e3d2b9dc9ca1b5ea576cdabb formal/lsc1_packet_frontend_arch_reset_idle.sv +f85348ac2c65ad828d1365d62254664817efd1bbcb7aee2bb2f20791e4493e20 formal/lsc1_packet_frontend_arch_reset_idle.ys +19dfd1aa5533a7d46907c904f418de01515bd6fc72a083116f0173932805906c formal/lsc1_packet_frontend_one_cycle_boundary.sv +d5bc98cdcff1c3105aa680778d768fd1acdc3b8b8fa027203222d5ebe08d5db7 formal/lsc1_packet_frontend_one_cycle_boundary.ys +8ea59e8fd8f3ec4dd147ba7b37689513b373a9479fd565f057929ef966bd0e72 formal/lsc1_packet_rx_status_accept.sv +aa53616c5c7d509acc4a50b7453d4387b1a97ee6b0819b7ad9461dcbb779eaf9 formal/lsc1_packet_rx_status_accept.ys +f96f5e9e40a3b52b6979af94584175db21e3eeab168a07238e9b9ec6f80d413e formal/lsc1_packet_tx_status_response.sv +da3e9a0f4ef2821db9e664ce544f0e6963dfe0e450826fe54fc8f90bb4a80450 formal/lsc1_packet_tx_status_response.ys diff --git a/test/packet_frontend/Makefile b/test/packet_frontend/Makefile index 1b12aca..ad96ce8 100644 --- a/test/packet_frontend/Makefile +++ b/test/packet_frontend/Makefile @@ -7,7 +7,7 @@ RTL = ../../asic_core/rtl/lsc1_packet_rx.sv \ ../../asic_core/rtl/lsc1_field_encoder.sv \ ../../asic_core/rtl/lsc1_packet_frontend.sv -.PHONY: sim one-cycle-boundary mutation differential-mutation clean +.PHONY: sim one-cycle-boundary mutation bounded-path-mutation differential-mutation clean sim: iverilog -g2012 -Wall -s tb_lsc1_packet_frontend -o tb_lsc1_packet_frontend.vvp $(RTL) tb_lsc1_packet_frontend.sv @@ -79,6 +79,17 @@ mutation: grep -q "status got=00 expected=86" "$$d/profile.out"; \ echo "PASS: BUSY, SET value, RETIRE ID, ABORT, abort status, length-order, and profile mutations were detected" +bounded-path-mutation: + @d=$$(mktemp -d); trap 'rm -rf "$$d"' EXIT; \ + cp ../../asic_core/rtl/lsc1_packet_tx.sv ../../formal/lsc1_packet_tx_status_response.sv ../../formal/lsc1_packet_tx_status_response.ys "$$d/"; \ + sed -i.bak "s/tx_data = saved_status;/tx_data = 8'h00;/" "$$d/lsc1_packet_tx.sv"; \ + sed -i.bak "s#asic_core/rtl/lsc1_packet_tx.sv#$$d/lsc1_packet_tx.sv#" "$$d/lsc1_packet_tx_status_response.ys"; \ + if (cd ../.. && yosys -s "$$d/lsc1_packet_tx_status_response.ys") >"$$d/mutation.out" 2>&1; then \ + echo "INFO response status serialization mutation unexpectedly survived" >&2; exit 1; \ + fi; \ + grep -q "Assert.*failed" "$$d/mutation.out"; \ + echo "PASS: bounded INFO-status serializer assertion detected mutation" + differential-mutation: @d=$$(mktemp -d); trap 'rm -rf "$$d"' EXIT; \ cp $(RTL) "$$d/"; \ diff --git a/tools/check_frontend_bounded_path.py b/tools/check_frontend_bounded_path.py new file mode 100644 index 0000000..9c3e538 --- /dev/null +++ b/tools/check_frontend_bounded_path.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +"""Guard the concrete, non-vacuous bounded frontend path partitions.""" +from pathlib import Path + +root = Path(__file__).resolve().parents[1] +rx = (root / "formal/lsc1_packet_rx_status_accept.sv").read_text() +tx = (root / "formal/lsc1_packet_tx_status_response.sv").read_text() +for text, required in ((rx, ("frame_valid && !fault_valid", "frame_opcode == 8'h13", "8'h1c")), + (tx, ("start = step == 1", "step == 3 || step == 5", "tx_data == 8'h03", "done_pulse"))): + missing = [needle for needle in required if needle not in text] + if missing: + raise SystemExit(f"bounded path partition is incomplete: {missing}") +if "tx_data == 8'h00" in tx: + raise SystemExit("INFO-status serializer mutation survived") +print("bounded path: concrete STATUS request acceptance and stalled INFO serialization are asserted") diff --git a/tools/run_arch_state_milestones.sh b/tools/run_arch_state_milestones.sh index 2c3b98f..1087c5b 100755 --- a/tools/run_arch_state_milestones.sh +++ b/tools/run_arch_state_milestones.sh @@ -2,7 +2,7 @@ # Reproducible, bounded architectural-state milestones. This is intentionally # not a timeout extension for release equivalence. set -eu -out=${1:-results/arch-state-20260728} +out=${1:-results/frontend-bounded-path-20260728} mkdir -p "$out" { git rev-parse HEAD @@ -13,18 +13,20 @@ mkdir -p "$out" asic_core/rtl/lsc1_stream_adapter.sv asic_core/rtl/lsc1_field_encoder.sv \ asic_core/rtl/lsc1_packet_frontend.sv formal/lsc1_packet_frontend_arch_state_map.json formal/ARCH_STATE.md \ formal/lsc1_packet_frontend_arch_reset_idle.sv formal/lsc1_packet_frontend_arch_reset_idle.ys \ - formal/lsc1_packet_frontend_one_cycle_boundary.sv formal/lsc1_packet_frontend_one_cycle_boundary.ys + formal/lsc1_packet_frontend_one_cycle_boundary.sv formal/lsc1_packet_frontend_one_cycle_boundary.ys \ + formal/lsc1_packet_rx_status_accept.sv formal/lsc1_packet_rx_status_accept.ys \ + formal/lsc1_packet_tx_status_response.sv formal/lsc1_packet_tx_status_response.ys } > "$out/versions-and-inputs.log" python3 tools/check_arch_state_interface.py > "$out/interface-coverage.log" 2>&1 -yosys -s formal/lsc1_packet_frontend_arch_reset_idle.ys 2>&1 | sed 's/[[:space:]]*$//' > "$out/reset-idle.log" -if timeout 180 yosys -s formal/lsc1_packet_frontend_one_cycle_boundary.ys > "$out/one-cycle-boundary.log" 2>&1; then - echo PASS > "$out/one-cycle-boundary.status" -else - echo UNRESOLVED > "$out/one-cycle-boundary.status" -fi +yosys -s formal/lsc1_packet_frontend_arch_reset_idle.ys > "$out/reset-idle.log" 2>&1 +yosys -s formal/lsc1_packet_rx_status_accept.ys > "$out/status-accept.log" 2>&1 +yosys -s formal/lsc1_packet_tx_status_response.ys > "$out/status-response.log" 2>&1 +sed -i 's/[[:space:]]*$//' "$out/reset-idle.log" "$out/status-accept.log" "$out/status-response.log" python3 tools/check_frontend_one_cycle_boundary.py > "$out/one-cycle-check.log" 2>&1 +python3 tools/check_frontend_bounded_path.py > "$out/bounded-path-check.log" 2>&1 make -C test/packet_frontend sim > "$out/rtl.log" 2>&1 make -C test/packet_frontend one-cycle-boundary > "$out/one-cycle-executable.log" 2>&1 python3 -m unittest sim.test_packet_frontend_rtl_differential -v > "$out/differential.log" 2>&1 make -C test/packet_frontend mutation > "$out/mutation.log" 2>&1 +make -C test/packet_frontend bounded-path-mutation > "$out/bounded-path-mutation.log" 2>&1 sha256sum "$out"/*.log > "$out/SHA256SUMS"