From b3c6fe6f13fb7f0a8ac8e78d9cd4d73c8ef63642 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:42 +0000 Subject: [PATCH 1/4] riscv: dts: spacemit: k3: add clock tree Add clock support to SpacemiT K3 SoC, the clock tree consist of several blocks which are APBC, APMU, DCIU, MPUM. Signed-off-by: Yixun Lan Signed-off-by: Linux RISC-V bot --- arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index b69cf81b5d553c..e3d7f3102fd575 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2026 Guodong Xu */ +#include #include /dts-v1/; @@ -398,6 +399,36 @@ }; }; + clocks { + vctcxo_1m: clock-1m { + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "vctcxo_1m"; + #clock-cells = <0>; + }; + + vctcxo_24m: clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "vctcxo_24m"; + #clock-cells = <0>; + }; + + vctcxo_3m: clock-3m { + compatible = "fixed-clock"; + clock-frequency = <3000000>; + clock-output-names = "vctcxo_3m"; + #clock-cells = <0>; + }; + + osc_32k: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&saplic>; @@ -406,6 +437,15 @@ dma-noncoherent; ranges; + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart0: serial@d4017000 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017000 0x0 0x100>; @@ -506,6 +546,41 @@ status = "disabled"; }; + syscon_mpmu: system-controller@d4050000 { + compatible = "spacemit,k3-syscon-mpmu"; + reg = <0x0 0xd4050000 0x0 0x10000>; + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + + pll: clock-controller@d4090000 { + compatible = "spacemit,k3-pll"; + reg = <0x0 0xd4090000 0x0 0x10000>; + clocks = <&vctcxo_24m>; + spacemit,mpmu = <&syscon_mpmu>; + #clock-cells = <1>; + }; + + syscon_apmu: system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x0 0xd4282800 0x0 0x400>; + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + + syscon_dciu: system-controller@d8440000 { + compatible = "spacemit,k3-syscon-dciu"; + reg = <0x0 0xd8440000 0x0 0xc000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + simsic: interrupt-controller@e0400000 { compatible = "spacemit,k3-imsics", "riscv,imsics"; reg = <0x0 0xe0400000 0x0 0x200000>; From e94bd0a1bddd128ec809898ae1973ac01adff7ca Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:43 +0000 Subject: [PATCH 2/4] riscv: dts: spacemit: k3: add pinctrl support Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices can request pinctrl resource properly. Signed-off-by: Yixun Lan Signed-off-by: Linux RISC-V bot --- arch/riscv/boot/dts/spacemit/k3.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index e3d7f3102fd575..6449ab0562938b 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -536,6 +536,14 @@ status = "disabled"; }; + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; + clocks = <&syscon_apbc CLK_APBC_AIB>, + <&syscon_apbc CLK_APBC_AIB_BUS>; + clock-names = "func", "bus"; + }; + uart10: serial@d401f000 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd401f000 0x0 0x100>; From 5b510b6d2c3415aea3dd2e14c892281b4da0e5cb Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:44 +0000 Subject: [PATCH 3/4] riscv: dts: spacemit: k3: add GPIO support Add GPIO node in the Device Tree, so devices are able to request GPIO resource properly. Signed-off-by: Yixun Lan Signed-off-by: Linux RISC-V bot --- arch/riscv/boot/dts/spacemit/k3.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 6449ab0562938b..3683a1a6536286 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -536,6 +536,24 @@ status = "disabled"; }; + gpio: gpio@d4019000 { + compatible = "spacemit,k3-gpio"; + reg = <0x0 0xd4019000 0x0 0x100>; + clocks = <&syscon_apbc CLK_APBC_GPIO>, + <&syscon_apbc CLK_APBC_GPIO_BUS>; + clock-names = "core", "bus"; + gpio-controller; + #gpio-cells = <3>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-ranges = <&pinctrl 0 0 0 32>, + <&pinctrl 1 0 32 32>, + <&pinctrl 2 0 64 32>, + <&pinctrl 3 0 96 32>; + }; + pinctrl: pinctrl@d401e000 { compatible = "spacemit,k3-pinctrl"; reg = <0x0 0xd401e000 0x0 0x1000>; From 0120a72fd3902f266f72d029d7d48bda490ef152 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:45 +0000 Subject: [PATCH 4/4] riscv: dts: spacemit: k3: add full resource to UART Previously the UART rely on external bootloader to initialize clock, pinctrl and reset, to solve this, explicitly adding those resource in Device Tree, so UART driver will handle them properly. Signed-off-by: Yixun Lan Signed-off-by: Linux RISC-V bot --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 24 +++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 51 ++++++++++++++++---- 3 files changed, 68 insertions(+), 10 deletions(-) create mode 100644 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index b691304d4b7460..b098dbd0e7a15f 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -5,6 +5,7 @@ */ #include "k3.dtsi" +#include "k3-pinctrl.dtsi" / { model = "SpacemiT K3 Pico-ITX"; @@ -25,5 +26,7 @@ }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; status = "okay"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi new file mode 100644 index 00000000000000..efb0f157218870 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026 Yixun Lan + */ + +#include + +#define K3_PADCONF(pin, func) (((pin) << 16) | (func)) + +/* Map GPIO pin to each bank's */ +#define K3_GPIO(x) (x / 32) (x % 32) + +&pinctrl { + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { + pinmux = , /* uart0 tx */ + ; /* uart0 rx */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 3683a1a6536286..a3a8ceddabec49 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include /dts-v1/; @@ -451,7 +452,10 @@ reg = <0x0 0xd4017000 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART0>, + <&syscon_apbc CLK_APBC_UART0_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART0>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -461,7 +465,10 @@ reg = <0x0 0xd4017100 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART2>, + <&syscon_apbc CLK_APBC_UART2_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART2>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -471,7 +478,10 @@ reg = <0x0 0xd4017200 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART3>, + <&syscon_apbc CLK_APBC_UART3_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART3>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -481,7 +491,10 @@ reg = <0x0 0xd4017300 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART4>, + <&syscon_apbc CLK_APBC_UART4_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART4>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -491,7 +504,10 @@ reg = <0x0 0xd4017400 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART5>, + <&syscon_apbc CLK_APBC_UART5_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART5>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -501,7 +517,10 @@ reg = <0x0 0xd4017500 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART6>, + <&syscon_apbc CLK_APBC_UART6_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART6>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -511,7 +530,10 @@ reg = <0x0 0xd4017600 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART7>, + <&syscon_apbc CLK_APBC_UART7_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART7>; interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -521,7 +543,10 @@ reg = <0x0 0xd4017700 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART8>, + <&syscon_apbc CLK_APBC_UART8_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART8>; interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -531,7 +556,10 @@ reg = <0x0 0xd4017800 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART9>, + <&syscon_apbc CLK_APBC_UART9_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART9>; interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -567,7 +595,10 @@ reg = <0x0 0xd401f000 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART10>, + <&syscon_apbc CLK_APBC_UART10_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART10>; interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; };