diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index e7ea7eb532a8f3..dc98cc5093c24d 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -133,8 +133,8 @@ secondary_start_sbi:
 	csrw CSR_IP, zero
 
 #ifndef CONFIG_RISCV_M_MODE
-	/* Enable time CSR */
-	li t0, 0x2
+	/* Enable CY, TM, and IR counters in U mode */
+	li t0, 0x7
 	csrw CSR_SCOUNTEREN, t0
 #endif
 
@@ -247,8 +247,8 @@ SYM_CODE_START(_start_kernel)
 	 */
 	csrr a0, CSR_MHARTID
 #else
-	/* Enable time CSR */
-	li t0, 0x2
+	/* Enable CY, TM, and IR counters in U mode */
+	li t0, 0x7
 	csrw CSR_SCOUNTEREN, t0
 #endif /* CONFIG_RISCV_M_MODE */