From 96d4c4256e1f4697bda9d1adab249aad2567422d Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 9 Apr 2026 00:45:11 +0000 Subject: [PATCH 1/2] dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K3 PWM support The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 generation, while the difference is that one additional bus clock is added. Signed-off-by: Yixun Lan Signed-off-by: Linux RISC-V bot --- .../bindings/pwm/marvell,pxa-pwm.yaml | 53 +++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml index 8df327e5281075..3427c8ef39455f 100644 --- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: contains: - const: spacemit,k1-pwm + enum: + - spacemit,k1-pwm + - spacemit,k3-pwm then: properties: "#pwm-cells": @@ -26,6 +28,38 @@ allOf: const: 1 description: | Used for specifying the period length in nanoseconds. + - if: + properties: + compatible: + contains: + enum: + - spacemit,k3-pwm + then: + properties: + clock-names: + items: + - const: func + - const: bus + - if: + properties: + compatible: + contains: + enum: + - spacemit,k3-pwm + then: + required: + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 properties: compatible: @@ -36,7 +70,9 @@ properties: - marvell,pxa168-pwm - marvell,pxa910-pwm - items: - - const: spacemit,k1-pwm + - enum: + - spacemit,k1-pwm + - spacemit,k3-pwm - const: marvell,pxa910-pwm reg: @@ -47,7 +83,18 @@ properties: description: Number of cells in a pwm specifier. clocks: - maxItems: 1 + minItems: 1 + items: + - description: The function clock + - description: An optional bus clock + + clock-names: + minItems: 1 + maxItems: 2 + oneOf: + - items: + - const: func + - const: bus resets: maxItems: 1 From 49fa7bac63b0de768f919d2b4158150443384d9d Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 9 Apr 2026 00:45:12 +0000 Subject: [PATCH 2/2] pwm: pxa: Add optional bus clock Add one secondary optional bus clock for the PWM PXA driver, also keep it compatible with old single clock. The SpacemiT K3 SoC require one bus clock for PWM controller, acquire and enable it during probe phase. Signed-off-by: Yixun Lan Signed-off-by: Linux RISC-V bot --- drivers/pwm/pwm-pxa.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c index 0f5bdb0e395ea0..2ace31405c2dde 100644 --- a/drivers/pwm/pwm-pxa.c +++ b/drivers/pwm/pwm-pxa.c @@ -53,6 +53,7 @@ struct pxa_pwm_chip { struct device *dev; struct clk *clk; + struct clk *bus_clk; void __iomem *mmio_base; }; @@ -177,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev) return PTR_ERR(chip); pc = to_pxa_pwm_chip(chip); - pc->clk = devm_clk_get(dev, NULL); + pc->bus_clk = devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(pc->bus_clk)) + return dev_err_probe(dev, PTR_ERR(pc->bus_clk), "Failed to get bus clock\n"); + + /* Get named func clk if bus clock is valid */ + pc->clk = devm_clk_get(dev, pc->bus_clk ? "func" : NULL); if (IS_ERR(pc->clk)) return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n");