From c172b4f48f35232b23a4b37d7174f536f4e155e8 Mon Sep 17 00:00:00 2001 From: Chen Pei Date: Mon, 13 Apr 2026 21:20:09 +0800 Subject: [PATCH] riscv: smp: Align secondary_start_sbi to 4 bytes During SMP boot, the secondary_start_sbi address is passed to the slave core via sbi_hsm_hart_start. In OpenSBI, this address is written to STVEC in sbi_hart_switch_mode. According to the privileged specification, the BASE field of STVEC must always be aligned on a 4-byte boundary. However, System.map reveals that secondary_start_sbi is not a 4-byte aligned address. For example, the address of secondary_start_sbi is 0xffffffff80001066, and the disassembly is as follows: Dump of assembler code from 0xffffffff80001052 to 0xffffffff8000107a: 0xffffffff80001052 <_start+4178>: c.nop -11 0xffffffff80001054 <_start+4180>: auipc gp,0x1a1f 0xffffffff80001058 <_start+4184>: addi gp,gp,84 0xffffffff8000105c <_start+4188>: csrw satp,a2 0xffffffff80001060 <_start+4192>: sfence.vma 0xffffffff80001064 <_start+4196>: ret 0xffffffff80001066 <_start+4198>: csrw sie,zero 0xffffffff8000106a <_start+4202>: csrw sip,zero 0xffffffff8000106e <_start+4206>: li t0,2 0xffffffff80001070 <_start+4208>: csrw scounteren,t0 0xffffffff80001074 <_start+4212>: auipc gp,0x1a1f 0xffffffff80001078 <_start+4216>: addi gp,gp,52 When writing to STVEC at address 0xffffffff80001066, the actual write address is 0xffffffff80001064, corresponding to the address of the previous ret instruction. This is unexpected, and if an interrupt occurs at this point, it will cause unpredictable results. However, secondary_start_sbi immediately masks all interrupts and updates STVEC, so no problems occurred. In summary, it is more reasonable to make secondary_start_sbi satisfy 4-byte alignment. Changes in v2: - Place `.align 2` inside `#ifdef CONFIG_SMP`, above the tag. - Add two Reviewed-by tags. - Based on Linux 7.0. Reviewed-by: Andrew Jones Reviewed-by: Guo Ren (Alibaba DAMO Academy) Signed-off-by: Chen Pei Signed-off-by: Linux RISC-V bot --- arch/riscv/kernel/head.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 9c99c5ad6fe8a3..9f33be6260e1d4 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -127,6 +127,7 @@ relocate_enable_mmu: #endif /* CONFIG_MMU */ #ifdef CONFIG_SMP .global secondary_start_sbi + .align 2 secondary_start_sbi: /* Mask all interrupts */ csrw CSR_IE, zero