From 6eccbe14e53c33a8296532f48b8eca215cdb457f Mon Sep 17 00:00:00 2001 From: Zhengyu He Date: Tue, 19 May 2026 14:15:55 +0800 Subject: [PATCH 1/3] spi: dt-bindings: fsl-qspi: support SpacemiT K3 Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. K3 has its own SoC integration, so board DTs should describe it with a K3-specific compatible instead of reusing the K1 string. Signed-off-by: Zhengyu He Signed-off-by: Cody Kang Signed-off-by: Linux RISC-V bot --- Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml index 1d10cfbad86c74..025f10ed242c0a 100644 --- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml @@ -20,6 +20,7 @@ properties: - fsl,ls1021a-qspi - fsl,ls2080a-qspi - spacemit,k1-qspi + - spacemit,k3-qspi - items: - enum: - fsl,ls1043a-qspi @@ -72,7 +73,9 @@ allOf: compatible: not: contains: - const: spacemit,k1-qspi + enum: + - spacemit,k1-qspi + - spacemit,k3-qspi then: properties: resets: false From 37a3d5af25ccdb5d46f93b27c8918cfc21ed9787 Mon Sep 17 00:00:00 2001 From: Zhengyu He Date: Tue, 19 May 2026 14:15:56 +0800 Subject: [PATCH 2/3] spi: fsl-qspi: add SpacemiT K3 support K3 uses the FSL QSPI controller with the same programming model as the existing SpacemiT integration, but has its own compatible string. Add the match entry so DTs using the K3 compatible bind to the driver. Signed-off-by: Zhengyu He Signed-off-by: Cody Kang Signed-off-by: Linux RISC-V bot --- drivers/spi/spi-fsl-qspi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index 57358851029ba5..bb94fae326096a 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -1015,6 +1015,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = { { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, }, { .compatible = "spacemit,k1-qspi", .data = &spacemit_k1_data, }, + { .compatible = "spacemit,k3-qspi", .data = &spacemit_k1_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids); From a1468a1b26f95b8d25c459113a1e64e05c430dc5 Mon Sep 17 00:00:00 2001 From: Zhengyu He Date: Tue, 19 May 2026 14:15:57 +0800 Subject: [PATCH 3/3] riscv: dts: spacemit: add QSPI support for K3 Pico-ITX Describe the K3 QSPI controller and the pin configuration needed by boards. Enable the bus on Pico-ITX because the board wires QSPI to NOR flash powered from the board 1.8 V QSPI rail. Signed-off-by: Zhengyu He Signed-off-by: Cody Kang Signed-off-by: Linux RISC-V bot --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 58 ++++++++++++++++++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 21 +++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++ 3 files changed, 95 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 4486dc1fe114da..61cbf924830b07 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -192,6 +192,64 @@ }; }; +&pinctrl { + qspi-cfg { + qspi-pins { + power-source = <1800>; + }; + + qspi-cs0-pins { + power-source = <1800>; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */ + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x0 0x20000>; + }; + + fsbl@20000 { + reg = <0x20000 0x80000>; + }; + + env@a0000 { + reg = <0xa0000 0x10000>; + }; + + esos@b0000 { + reg = <0xb0000 0x100000>; + }; + + opensbi@1b0000 { + reg = <0x1b0000 0x60000>; + }; + + uboot@210000 { + reg = <0x210000 0x5f0000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_0_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 23899d3f308a02..5d976379118076 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -56,6 +56,27 @@ }; }; + /omit-if-no-ref/ + qspi_cfg: qspi-cfg { + qspi-pins { + pinmux = , /* qspi dat0 */ + , /* qspi dat1 */ + , /* qspi dat2 */ + , /* qspi dat3 */ + ; /* qspi clk */ + + bias-disable; + drive-strength = <25>; + }; + + qspi-cs0-pins { + pinmux = ; /* qspi cs0 */ + + bias-disable; + drive-strength = <25>; + }; + }; + /omit-if-no-ref/ uart0_0_cfg: uart0-0-cfg { uart0-0-pins { diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 815debd16409be..800efc2929a409 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -836,6 +836,22 @@ #clock-cells = <1>; }; + qspi: spi@d420c000 { + compatible = "spacemit,k3-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xd420c000 0x0 0x1000>, + <0x0 0xb8000000 0x0 0xc00000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, + <&syscon_apmu CLK_APMU_QSPI>; + clock-names = "qspi_en", "qspi"; + resets = <&syscon_apmu RESET_APMU_QSPI>, + <&syscon_apmu RESET_APMU_QSPI_BUS>; + interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + syscon_apmu: system-controller@d4282800 { compatible = "spacemit,k3-syscon-apmu"; reg = <0x0 0xd4282800 0x0 0x400>;