From d21a05b8505ca693d5e8aa96010f62003b2c7a11 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Fri, 18 Apr 2025 21:19:50 +0800 Subject: [PATCH 1/4] dt-bindings: phy: spacemit: add K1 USB2 PHY Add support for USB2 PHY found on SpacemiT K1 SoC. Reviewed-by: Rob Herring (Arm) Signed-off-by: Ze Huang Signed-off-by: Linux RISC-V bot --- .../bindings/phy/spacemit,usb2-phy.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml new file mode 100644 index 00000000000000..ea999cff9c250b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC USB 2.0 PHY + +maintainers: + - Ze Huang + +properties: + compatible: + const: spacemit,k1-usb2-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - "#phy-cells" + +additionalProperties: false + +examples: + - | + usb-phy@c09c0000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0xc09c0000 0x200>; + clocks = <&syscon_apmu 15>; + #phy-cells = <0>; + }; From cb9649d2c8ab7df048140e386fca9dc17099064f Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Fri, 18 Apr 2025 21:19:51 +0800 Subject: [PATCH 2/4] dt-bindings: phy: spacemit: add K1 PCIe/USB3 combo PHY Introduce support for SpacemiT K1 PCIe/USB3 combo PHY controller. PCIe portA and USB3 controller share this phy, only one of them can work at any given application scenario. Co-developed-by: Junzhong Pan Signed-off-by: Ze Huang Signed-off-by: Linux RISC-V bot --- .../bindings/phy/spacemit,k1-combphy.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml new file mode 100644 index 00000000000000..3c2e7dfb34a27b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/spacemit,k1-combphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PCIe/USB3 Combo PHY + +maintainers: + - Ze Huang + +description: + Combo PHY on SpacemiT K1 SoC. PCIe port A and USB3 controller share this + phy, only one of PCIe port A and USB3 port can work at any given application + scenario. + +properties: + compatible: + const: spacemit,k1-combphy + + reg: + items: + - description: PHY control registers + - description: PCIe/USB3 mode selection register + + reg-names: + items: + - const: ctrl + - const: sel + + resets: + maxItems: 1 + + "#phy-cells": + const: 1 + description: + Indicates the PHY mode to select. The value determines whether the PHY + operates in PCIe or USB3 mode. + + spacemit,lfps-threshold: + description: + Controls the LFPS signal detection threshold, affects polling.LFPS + handshake. Lower the threshold when core voltage rises. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xff + + spacemit,rx-always-on: + description: + Affects RX.detect, enhance compatibility of some DFPs in device mode but + increase power consumption. + type: boolean + +required: + - compatible + - reg + - reg-names + - resets + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@c0b10000 { + compatible = "spacemit,k1-combphy"; + reg = <0xc0b10000 0x800>, + <0xd4282910 0x400>; + reg-names = "ctrl", "sel"; + resets = <&syscon_apmu 19>; + #phy-cells = <1>; + }; From cb320d5f042cd262b94cb4b5076d5f86376d5493 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Fri, 18 Apr 2025 21:19:52 +0800 Subject: [PATCH 3/4] phy: spacemit: support K1 USB2.0 PHY controller Add support for SpacemiT K1 USB2.0 PHY. Signed-off-by: Ze Huang Signed-off-by: Linux RISC-V bot --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/spacemit/Kconfig | 13 +++ drivers/phy/spacemit/Makefile | 2 + drivers/phy/spacemit/phy-k1-usb2.c | 131 +++++++++++++++++++++++++++++ 5 files changed, 148 insertions(+) create mode 100644 drivers/phy/spacemit/Kconfig create mode 100644 drivers/phy/spacemit/Makefile create mode 100644 drivers/phy/spacemit/phy-k1-usb2.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 8d58efe998ec5f..fca589aa7926eb 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -114,6 +114,7 @@ source "drivers/phy/renesas/Kconfig" source "drivers/phy/rockchip/Kconfig" source "drivers/phy/samsung/Kconfig" source "drivers/phy/socionext/Kconfig" +source "drivers/phy/spacemit/Kconfig" source "drivers/phy/st/Kconfig" source "drivers/phy/starfive/Kconfig" source "drivers/phy/sunplus/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index e281442acc7528..05993ff8a15daf 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -34,6 +34,7 @@ obj-y += allwinner/ \ rockchip/ \ samsung/ \ socionext/ \ + spacemit/ \ st/ \ starfive/ \ sunplus/ \ diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig new file mode 100644 index 00000000000000..0136aee2e8a2f5 --- /dev/null +++ b/drivers/phy/spacemit/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for SpacemiT platforms +# +config PHY_SPACEMIT_K1_USB2 + tristate "SpacemiT K1 USB 2.0 PHY support" + depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF + depends on COMMON_CLK + depends on USB_COMMON + select GENERIC_PHY + help + Enable this to support K1 USB 2.0 PHY driver. This driver takes care of + enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile new file mode 100644 index 00000000000000..fec0b425a94854 --- /dev/null +++ b/drivers/phy/spacemit/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c new file mode 100644 index 00000000000000..4a5684f3185f61 --- /dev/null +++ b/drivers/phy/spacemit/phy-k1-usb2.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SpacemiT K1 USB 2.0 PHY driver + * + * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (C) 2025 Ze Huang + */ + +#include +#include +#include +#include + +#define USB2_PHY_REG01 0x04 +#define USB2_PHY_REG01_VAL 0x60ef +#define USB2_PHY_REG01_PLL_IS_READY BIT(0) +#define USB2_PHY_REG04 0x10 +#define USB2_PHY_REG04_AUTO_CLEAR_DIS BIT(2) +#define USB2_PHY_REG0D 0x34 +#define USB2_PHY_REG0D_VAL 0x1c +#define USB2_PHY_REG26 0x98 +#define USB2_PHY_REG26_VAL 0xbec4 + +#define USB2D_CTRL_RESET_TIME_MS 50 + +struct spacemit_usb2phy { + struct phy *phy; + struct clk *clk; + void __iomem *base; +}; + +static int spacemit_usb2phy_init(struct phy *phy) +{ + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); + void __iomem *base = sphy->base; + u32 val; + int ret; + + ret = clk_prepare_enable(sphy->clk); + if (ret) { + dev_err(&phy->dev, "failed to enable clock\n"); + return ret; + } + + /* + * make sure the usb controller is not under reset process before + * any configuration + */ + usleep_range(150, 200); + writel(USB2_PHY_REG26_VAL, base + USB2_PHY_REG26); /* 24M ref clk */ + + ret = read_poll_timeout(readl, val, (val & USB2_PHY_REG01_PLL_IS_READY), + 500, USB2D_CTRL_RESET_TIME_MS * 1000, true, + base + USB2_PHY_REG01); + if (ret) { + dev_err(&phy->dev, "wait PHY_REG01[PLLREADY] timeout\n"); + return ret; + } + + /* release usb2 phy internal reset and enable clock gating */ + writel(USB2_PHY_REG01_VAL, base + USB2_PHY_REG01); + writel(USB2_PHY_REG0D_VAL, base + USB2_PHY_REG0D); + + /* auto clear host disc */ + val = readl(base + USB2_PHY_REG04); + val |= USB2_PHY_REG04_AUTO_CLEAR_DIS; + writel(val, base + USB2_PHY_REG04); + + return 0; +} + +static int spacemit_usb2phy_exit(struct phy *phy) +{ + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); + + clk_disable_unprepare(sphy->clk); + + return 0; +} + +static const struct phy_ops spacemit_usb2phy_ops = { + .init = spacemit_usb2phy_init, + .exit = spacemit_usb2phy_exit, + .owner = THIS_MODULE, +}; + +static int spacemit_usb2phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct spacemit_usb2phy *sphy; + + sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); + if (!sphy) + return -ENOMEM; + + sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); + if (IS_ERR(sphy->clk)) + return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); + + sphy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sphy->base)) + return PTR_ERR(sphy->base); + + sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); + if (IS_ERR(sphy->phy)) + return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); + + phy_set_drvdata(sphy->phy, sphy); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id spacemit_usb2phy_dt_match[] = { + { .compatible = "spacemit,k1-usb2-phy", }, + { /* sentinal */ } +}; +MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); + +static struct platform_driver spacemit_usb2_phy_driver = { + .probe = spacemit_usb2phy_probe, + .driver = { + .name = "spacemit-usb2-phy", + .of_match_table = spacemit_usb2phy_dt_match, + }, +}; +module_platform_driver(spacemit_usb2_phy_driver); + +MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver"); +MODULE_LICENSE("GPL"); From 288966d8ead388c6f87a6fc2944d4ccfac68cc50 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Fri, 18 Apr 2025 21:19:53 +0800 Subject: [PATCH 4/4] phy: spacemit: add USB3 support for K1 PCIe/USB3 combo PHY Add support for USB 3.0 mode on the K1 PCIe/USB3 combo PHY. Currently, only USB mode is supported; PCIe support is not included in this change. Signed-off-by: Ze Huang Signed-off-by: Linux RISC-V bot --- drivers/phy/spacemit/Kconfig | 8 + drivers/phy/spacemit/Makefile | 1 + drivers/phy/spacemit/phy-k1-combphy.c | 251 ++++++++++++++++++++++++++ 3 files changed, 260 insertions(+) create mode 100644 drivers/phy/spacemit/phy-k1-combphy.c diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig index 0136aee2e8a2f5..ccc6bf9ea49f49 100644 --- a/drivers/phy/spacemit/Kconfig +++ b/drivers/phy/spacemit/Kconfig @@ -11,3 +11,11 @@ config PHY_SPACEMIT_K1_USB2 help Enable this to support K1 USB 2.0 PHY driver. This driver takes care of enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. + +config PHY_SPACEMIT_K1_COMBPHY + tristate "SpacemiT K1 PCIe/USB3 combo PHY support" + depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF + depends on COMMON_CLK + select GENERIC_PHY + help + USB3/PCIe Combo PHY Support for SpacemiT K1 SoC diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile index fec0b425a94854..1fd0c65f2c5cd1 100644 --- a/drivers/phy/spacemit/Makefile +++ b/drivers/phy/spacemit/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_SPACEMIT_K1_COMBPHY) += phy-k1-combphy.o obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o diff --git a/drivers/phy/spacemit/phy-k1-combphy.c b/drivers/phy/spacemit/phy-k1-combphy.c new file mode 100644 index 00000000000000..a291b7a78fae2f --- /dev/null +++ b/drivers/phy/spacemit/phy-k1-combphy.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SpacemiT K1 PCIE/USB3 PHY driver + * + * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (C) 2025 Ze Huang + */ + +#include +#include +#include +#include +#include +#include +#include + +#define COMBPHY_USB_REG1 0x68 +#define COMBPHY_USB_REG1_VAL 0x00 +#define COMBPHY_USB_REG2 0x48 +#define COMBPHY_USB_REG2_VAL 0x603a2276 +#define COMBPHY_USB_REG3 0x08 +#define COMBPHY_USB_REG3_VAL 0x97c +#define COMBPHY_USB_REG4 0x18 +#define COMBPHY_USB_REG4_VAL 0x00 +#define COMBPHY_USB_TERM_SHORT_MASK 0x3000 +#define COMBPHY_USB_TERM_SHORT_VAL 0x3000 +#define COMBPHY_USB_PLL_REG 0x08 +#define COMBPHY_USB_PLL_MASK 0x01 +#define COMBPHY_USB_PLL_VAL 0x01 +#define COMBPHY_USB_LFPS_REG 0x58 +#define COMBPHY_USB_LFPS_MASK 0x700 +#define COMBPHY_USB_LFPS_THRES_DEFAULT 0x03 + +#define COMBPHY_MODE_SEL BIT(3) +#define COMBPHY_WAIT_TIMEOUT 1000 + +struct spacemit_combphy_priv { + struct device *dev; + struct phy *phy; + struct reset_control *phy_rst; + void __iomem *phy_ctrl; + void __iomem *phy_sel; + bool rx_always_on; + u8 lfps_threshold; + u8 type; +}; + +static void spacemit_reg_update(void __iomem *reg, u32 offset, u32 mask, u32 val) +{ + u32 tmp; + + tmp = readl(reg + offset); + tmp = (tmp & ~(mask)) | val; + writel(tmp, reg + offset); +} + +static int spacemit_combphy_wait_ready(struct spacemit_combphy_priv *priv, + u32 offset, u32 mask, u32 val) +{ + u32 reg_val; + int ret = 0; + + ret = read_poll_timeout(readl, reg_val, (reg_val & mask) == val, + 1000, COMBPHY_WAIT_TIMEOUT * 1000, false, + priv->phy_ctrl + offset); + + return ret; +} + +static int spacemit_combphy_set_mode(struct spacemit_combphy_priv *priv) +{ + int ret = 0; + + switch (priv->type) { + case PHY_TYPE_USB3: + spacemit_reg_update(priv->phy_sel, 0, 0, COMBPHY_MODE_SEL); + break; + default: + dev_err(priv->dev, "PHY type %x not supported\n", priv->type); + ret = -EINVAL; + break; + } + + return ret; +} + +static int spacemit_combphy_init_usb(struct spacemit_combphy_priv *priv) +{ + void __iomem *base = priv->phy_ctrl; + int ret; + + writel(COMBPHY_USB_REG1_VAL, base + COMBPHY_USB_REG1); + writel(COMBPHY_USB_REG2_VAL, base + COMBPHY_USB_REG2); + writel(COMBPHY_USB_REG3_VAL, base + COMBPHY_USB_REG3); + writel(COMBPHY_USB_REG4_VAL, base + COMBPHY_USB_REG4); + + ret = spacemit_combphy_wait_ready(priv, COMBPHY_USB_PLL_REG, + COMBPHY_USB_PLL_MASK, + COMBPHY_USB_PLL_VAL); + + dev_dbg(priv->dev, "USB3 PHY init lfps threshold %d\n", priv->lfps_threshold); + spacemit_reg_update(base, COMBPHY_USB_LFPS_REG, + COMBPHY_USB_LFPS_MASK, + (priv->lfps_threshold << 8)); + + if (priv->rx_always_on) + spacemit_reg_update(base, COMBPHY_USB_REG4, + COMBPHY_USB_TERM_SHORT_MASK, + COMBPHY_USB_TERM_SHORT_VAL); + + if (ret) + dev_err(priv->dev, "USB3 PHY init timeout!\n"); + + return ret; +} + +static int spacemit_combphy_init(struct phy *phy) +{ + struct spacemit_combphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = spacemit_combphy_set_mode(priv); + if (ret) { + dev_err(priv->dev, "failed to set mode for PHY type %x\n", + priv->type); + goto out; + } + + ret = reset_control_deassert(priv->phy_rst); + if (ret) { + dev_err(priv->dev, "failed to deassert rst\n"); + goto err_rst; + } + + switch (priv->type) { + case PHY_TYPE_USB3: + ret = spacemit_combphy_init_usb(priv); + break; + default: + dev_err(priv->dev, "PHY type %x not supported\n", priv->type); + ret = -EINVAL; + break; + } + + if (ret) + goto err_rst; + + return 0; + +err_rst: + reset_control_assert(priv->phy_rst); +out: + return ret; +} + +static int spacemit_combphy_exit(struct phy *phy) +{ + struct spacemit_combphy_priv *priv = phy_get_drvdata(phy); + + reset_control_assert(priv->phy_rst); + + return 0; +} + +static struct phy *spacemit_combphy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct spacemit_combphy_priv *priv = dev_get_drvdata(dev); + + if (args->args_count != 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (priv->type != PHY_NONE && priv->type != args->args[0]) + dev_warn(dev, "PHY type %d is selected to override %d\n", + args->args[0], priv->type); + + priv->type = args->args[0]; + + if (args->args_count > 1) + dev_dbg(dev, "combo phy idx: %d selected", args->args[1]); + + return priv->phy; +} + +static const struct phy_ops spacemit_combphy_ops = { + .init = spacemit_combphy_init, + .exit = spacemit_combphy_exit, + .owner = THIS_MODULE, +}; + +static int spacemit_combphy_probe(struct platform_device *pdev) +{ + struct spacemit_combphy_priv *priv; + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->phy_ctrl = devm_platform_ioremap_resource_byname(pdev, "ctrl"); + if (IS_ERR(priv->phy_ctrl)) + return PTR_ERR(priv->phy_ctrl); + + priv->phy_sel = devm_platform_ioremap_resource_byname(pdev, "sel"); + if (IS_ERR(priv->phy_sel)) + return PTR_ERR(priv->phy_sel); + + priv->lfps_threshold = COMBPHY_USB_LFPS_THRES_DEFAULT; + device_property_read_u8(&pdev->dev, "spacemit,lfps-threshold", &priv->lfps_threshold); + + priv->rx_always_on = device_property_read_bool(&pdev->dev, "spacemit,rx-always-on"); + priv->type = PHY_NONE; + priv->dev = dev; + + priv->phy_rst = devm_reset_control_get(dev, NULL); + if (IS_ERR(priv->phy_rst)) + return dev_err_probe(dev, PTR_ERR(priv->phy_rst), + "failed to get phy reset\n"); + + priv->phy = devm_phy_create(dev, NULL, &spacemit_combphy_ops); + if (IS_ERR(priv->phy)) + return dev_err_probe(dev, PTR_ERR(priv->phy), + "failed to create combphy\n"); + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + phy_provider = devm_of_phy_provider_register(dev, spacemit_combphy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id spacemit_combphy_of_match[] = { + { .compatible = "spacemit,k1-combphy", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, spacemit_combphy_of_match); + +static struct platform_driver spacemit_combphy_driver = { + .probe = spacemit_combphy_probe, + .driver = { + .name = "spacemit-k1-combphy", + .of_match_table = spacemit_combphy_of_match, + }, +}; +module_platform_driver(spacemit_combphy_driver); + +MODULE_DESCRIPTION("Spacemit PCIE/USB3.0 COMBO PHY driver"); +MODULE_LICENSE("GPL");