diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index b136b6c4128c05..8dd1a3c60bc436 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -256,11 +256,13 @@ cpu0: cpu@0 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -281,11 +283,13 @@ cpu1: cpu@1 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -306,11 +310,13 @@ cpu2: cpu@2 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -331,11 +337,13 @@ cpu3: cpu@3 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -356,11 +364,13 @@ cpu4: cpu@4 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <4>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -381,11 +391,13 @@ cpu5: cpu@5 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <5>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -406,11 +418,13 @@ cpu6: cpu@6 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <6>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -431,11 +445,13 @@ cpu7: cpu@7 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <7>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -456,11 +472,13 @@ cpu8: cpu@8 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <8>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -481,11 +499,13 @@ cpu9: cpu@9 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <9>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -506,11 +526,13 @@ cpu10: cpu@10 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <10>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -531,11 +553,13 @@ cpu11: cpu@11 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <11>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -556,11 +580,13 @@ cpu12: cpu@12 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <12>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -581,11 +607,13 @@ cpu13: cpu@13 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <13>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -606,11 +634,13 @@ cpu14: cpu@14 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <14>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -631,11 +661,13 @@ cpu15: cpu@15 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <15>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -656,11 +688,13 @@ cpu16: cpu@16 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <16>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -681,11 +715,13 @@ cpu17: cpu@17 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <17>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -706,11 +742,13 @@ cpu18: cpu@18 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <18>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -731,11 +769,13 @@ cpu19: cpu@19 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <19>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -756,11 +796,13 @@ cpu20: cpu@20 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <20>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -781,11 +823,13 @@ cpu21: cpu@21 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <21>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -806,11 +850,13 @@ cpu22: cpu@22 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <22>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -831,11 +877,13 @@ cpu23: cpu@23 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <23>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -856,11 +904,13 @@ cpu24: cpu@24 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <24>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -881,11 +931,13 @@ cpu25: cpu@25 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <25>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -906,11 +958,13 @@ cpu26: cpu@26 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <26>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -931,11 +985,13 @@ cpu27: cpu@27 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <27>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -956,11 +1012,13 @@ cpu28: cpu@28 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <28>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -981,11 +1039,13 @@ cpu29: cpu@29 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <29>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1006,11 +1066,13 @@ cpu30: cpu@30 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <30>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1031,11 +1093,13 @@ cpu31: cpu@31 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <31>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1056,11 +1120,13 @@ cpu32: cpu@32 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <32>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1081,11 +1147,13 @@ cpu33: cpu@33 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <33>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1106,11 +1174,13 @@ cpu34: cpu@34 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <34>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1131,11 +1201,13 @@ cpu35: cpu@35 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <35>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1156,11 +1228,13 @@ cpu36: cpu@36 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <36>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1181,11 +1255,13 @@ cpu37: cpu@37 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <37>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1206,11 +1282,13 @@ cpu38: cpu@38 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <38>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1231,11 +1309,13 @@ cpu39: cpu@39 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <39>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1256,11 +1336,13 @@ cpu40: cpu@40 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <40>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1281,11 +1363,13 @@ cpu41: cpu@41 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <41>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1306,11 +1390,13 @@ cpu42: cpu@42 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <42>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1331,11 +1417,13 @@ cpu43: cpu@43 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <43>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1356,11 +1444,13 @@ cpu44: cpu@44 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <44>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1381,11 +1471,13 @@ cpu45: cpu@45 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <45>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1406,11 +1498,13 @@ cpu46: cpu@46 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <46>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1431,11 +1525,13 @@ cpu47: cpu@47 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <47>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1456,11 +1552,13 @@ cpu48: cpu@48 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <48>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1481,11 +1579,13 @@ cpu49: cpu@49 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <49>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1506,11 +1606,13 @@ cpu50: cpu@50 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <50>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1531,11 +1633,13 @@ cpu51: cpu@51 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <51>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1556,11 +1660,13 @@ cpu52: cpu@52 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <52>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1581,11 +1687,13 @@ cpu53: cpu@53 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <53>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1606,11 +1714,13 @@ cpu54: cpu@54 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <54>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1631,11 +1741,13 @@ cpu55: cpu@55 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <55>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1656,11 +1768,13 @@ cpu56: cpu@56 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <56>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1681,11 +1795,13 @@ cpu57: cpu@57 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <57>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1706,11 +1822,13 @@ cpu58: cpu@58 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <58>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1731,11 +1849,13 @@ cpu59: cpu@59 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <59>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1756,11 +1876,13 @@ cpu60: cpu@60 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <60>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1781,11 +1903,13 @@ cpu61: cpu@61 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <61>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1806,11 +1930,13 @@ cpu62: cpu@62 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <62>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1831,11 +1957,13 @@ cpu63: cpu@63 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <63>; i-cache-block-size = <64>; i-cache-size = <65536>;