From b1b36635dd1c59746036c798754f04ca267c897a Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:02:59 +0800 Subject: [PATCH 01/12] dt-bindings: riscv: Add xsfvqmaccdod and xsfvqmaccqoq ISA extension description Add "xsfvqmaccdod" and "xsfvqmaccqoq" ISA extensions which are provided by SiFive for int8 matrix multiplication instructions support. Signed-off-by: Cyan Yang Acked-by: Conor Dooley Signed-off-by: Linux RISC-V bot --- .../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index bcab59e0cc2e1d..d36e7c68d69a18 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -662,6 +662,19 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + # SiFive + - const: xsfvqmaccdod + description: + SiFive Int8 Matrix Multiplication Extensions Specification. + See more details in + https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification + + - const: xsfvqmaccqoq + description: + SiFive Int8 Matrix Multiplication Extensions Specification. + See more details in + https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification + # T-HEAD - const: xtheadvector description: From c1bee3215db3e8b62fd4262af3741f47ea8513e4 Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:00 +0800 Subject: [PATCH 02/12] riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions Add SiFive vendor extension support to the kernel with the target of "xsfvqmaccdod" and "xsfvqmaccqoq". Signed-off-by: Cyan Yang Signed-off-by: Linux RISC-V bot --- arch/riscv/Kconfig.vendor | 13 +++++++++++++ .../include/asm/vendor_extensions/sifive.h | 14 ++++++++++++++ arch/riscv/kernel/vendor_extensions.c | 10 ++++++++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + arch/riscv/kernel/vendor_extensions/sifive.c | 19 +++++++++++++++++++ 5 files changed, 57 insertions(+) create mode 100644 arch/riscv/include/asm/vendor_extensions/sifive.h create mode 100644 arch/riscv/kernel/vendor_extensions/sifive.c diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index b096548fe0ffdd..e14f26368963c1 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES If you don't know what to do here, say Y. endmenu +menu "SiFive" +config RISCV_ISA_VENDOR_EXT_SIFIVE + bool "SiFive vendor extension support" + select RISCV_ISA_VENDOR_EXT + default y + help + Say N here if you want to disable all SiFive vendor extension + support. This will cause any SiFive vendor extensions that are + requested by hardware probing to be ignored. + + If you don't know what to do here, say Y. +endmenu + menu "T-Head" config RISCV_ISA_VENDOR_EXT_THEAD bool "T-Head vendor extension support" diff --git a/arch/riscv/include/asm/vendor_extensions/sifive.h b/arch/riscv/include/asm/vendor_extensions/sifive.h new file mode 100644 index 00000000000000..608004250e2ef3 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/sifive.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H + +#include + +#include + +#define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD 0 +#define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ 1 + +extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive; + +#endif diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c index 9feb7f67a0a390..92d8ff81f42c9c 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -15,6 +16,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = { #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES &riscv_isa_vendor_ext_list_andes, #endif +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE + &riscv_isa_vendor_ext_list_sifive, +#endif #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD &riscv_isa_vendor_ext_list_thead, #endif @@ -45,6 +49,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap; break; #endif + #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE + case SIFIVE_VENDOR_ID: + bmap = &riscv_isa_vendor_ext_list_sifive.all_harts_isa_bitmap; + cpu_bmap = riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap; + break; + #endif #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD case THEAD_VENDOR_ID: bmap = &riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap; diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile index 866414c81a9f5e..d5fdde0e863b17 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o diff --git a/arch/riscv/kernel/vendor_extensions/sifive.c b/arch/riscv/kernel/vendor_extensions/sifive.c new file mode 100644 index 00000000000000..6042cc3021de77 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/sifive.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +/* All SiFive vendor extensions supported in Linux */ +static const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = { + __RISCV_ISA_EXT_DATA(xsfvqmaccdod, RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD), + __RISCV_ISA_EXT_DATA(xsfvqmaccqoq, RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ), +}; + +struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive = { + .ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_sifive), + .ext_data = riscv_isa_vendor_ext_sifive, +}; From 744f9e8ec9faf18af2c8d60e29943cede0115643 Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:01 +0800 Subject: [PATCH 03/12] riscv: hwprobe: Document SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions Document the support for sifive vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 and two vendor extensions for SiFive Int8 Matrix Multiplication Instructions using RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD and RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ. Signed-off-by: Cyan Yang Signed-off-by: Linux RISC-V bot --- Documentation/arch/riscv/hwprobe.rst | 14 ++++++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 1 + 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index f60bf599175597..df13822977d9b0 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -335,3 +335,17 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which represents the size of the Zicbom block in bytes. + +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`: A bitmask containing the + sifive vendor extensions that are compatible with the + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * SIFIVE + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor + extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication + Extensions Specification. + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor + extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication + Instruction Extensions Specification. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 1f690fea0e03de..1c69773057765b 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,7 +8,7 @@ #include -#define RISCV_HWPROBE_MAX_KEY 12 +#define RISCV_HWPROBE_MAX_KEY 13 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 3c2fce939673b9..9c70101f021b3c 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -104,6 +104,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED 4 #define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 11 #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12 +#define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ /* Flags */ From 14d65c1581795d43e3daa761458f6fde0e26646d Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:02 +0800 Subject: [PATCH 04/12] riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0" which allows userspace to probe for the new vendor extensions from SiFive. Also, add new hwprobe for SiFive "xsfvqmaccdod" and "xsfvqmaccqoq" vendor extensions. Signed-off-by: Cyan Yang Signed-off-by: Linux RISC-V bot --- arch/riscv/include/asm/hwprobe.h | 1 + .../asm/vendor_extensions/sifive_hwprobe.h | 19 ++++++++++++++++++ arch/riscv/include/uapi/asm/vendor/sifive.h | 4 ++++ arch/riscv/kernel/sys_hwprobe.c | 5 +++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + .../kernel/vendor_extensions/sifive_hwprobe.c | 20 +++++++++++++++++++ 6 files changed, 50 insertions(+) create mode 100644 arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h create mode 100644 arch/riscv/include/uapi/asm/vendor/sifive.h create mode 100644 arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 1c69773057765b..7fe0a379474ae2 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -22,6 +22,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) case RISCV_HWPROBE_KEY_IMA_EXT_0: case RISCV_HWPROBE_KEY_CPUPERF_0: case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: + case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0: return true; } diff --git a/arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h new file mode 100644 index 00000000000000..90a61abd033ce7 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_HWPROBE_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_HWPROBE_H + +#include + +#include + +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE +void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cpumask *cpus); +#else +static inline void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + pair->value = 0; +} +#endif + +#endif diff --git a/arch/riscv/include/uapi/asm/vendor/sifive.h b/arch/riscv/include/uapi/asm/vendor/sifive.h new file mode 100644 index 00000000000000..f25d8cf110d1e8 --- /dev/null +++ b/arch/riscv/include/uapi/asm/vendor/sifive.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD (1 << 0) +#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ (1 << 1) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 249aec8594a92a..138e74f05de78e 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -300,6 +301,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, pair->value = riscv_timebase; break; + case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0: + hwprobe_isa_vendor_ext_sifive_0(pair, cpus); + break; + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: hwprobe_isa_vendor_ext_thead_0(pair, cpus); break; diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile index d5fdde0e863b17..a4eca96d1c8a2f 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive_hwprobe.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o diff --git a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c new file mode 100644 index 00000000000000..461ce0f305ce03 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +#include +#include + +void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cpumask *cpus) +{ + VENDOR_EXTENSION_SUPPORTED(pair, cpus, + riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap, { + VENDOR_EXT_KEY(XSFVQMACCDOD); + VENDOR_EXT_KEY(XSFVQMACCQOQ); + }); +} From 1bb2dad73d2da3f335e99f96af07ed19b284bc4f Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:03 +0800 Subject: [PATCH 05/12] dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description Add "xsfvfnrclipxfqf" ISA extension which is provided by SiFive for FP32-to-int8 ranged clip instructions support. Signed-off-by: Cyan Yang Acked-by: Conor Dooley Signed-off-by: Linux RISC-V bot --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index d36e7c68d69a18..be203df29eb838 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -675,6 +675,12 @@ properties: See more details in https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification + - const: xsfvfnrclipxfqf + description: + SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. + See more details in + https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions + # T-HEAD - const: xtheadvector description: From f8e2bec201a4d9861692b843b8b3cde3d16b01f3 Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:04 +0800 Subject: [PATCH 06/12] riscv: Add SiFive xsfvfnrclipxfqf vendor extension Add SiFive vendor extension "xsfvfnrclipxfqf" support to the kernel. Signed-off-by: Cyan Yang Signed-off-by: Linux RISC-V bot --- arch/riscv/include/asm/vendor_extensions/sifive.h | 1 + arch/riscv/kernel/vendor_extensions/sifive.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/vendor_extensions/sifive.h b/arch/riscv/include/asm/vendor_extensions/sifive.h index 608004250e2ef3..2d05e3e731704c 100644 --- a/arch/riscv/include/asm/vendor_extensions/sifive.h +++ b/arch/riscv/include/asm/vendor_extensions/sifive.h @@ -8,6 +8,7 @@ #define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD 0 #define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ 1 +#define RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF 2 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive; diff --git a/arch/riscv/kernel/vendor_extensions/sifive.c b/arch/riscv/kernel/vendor_extensions/sifive.c index 6042cc3021de77..9376e1ce133aaa 100644 --- a/arch/riscv/kernel/vendor_extensions/sifive.c +++ b/arch/riscv/kernel/vendor_extensions/sifive.c @@ -9,6 +9,7 @@ /* All SiFive vendor extensions supported in Linux */ static const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = { + __RISCV_ISA_EXT_DATA(xsfvfnrclipxfqf, RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF), __RISCV_ISA_EXT_DATA(xsfvqmaccdod, RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD), __RISCV_ISA_EXT_DATA(xsfvqmaccqoq, RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ), }; From 2d3a563d5de6bfc71cb879c063f44034221bea7a Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:05 +0800 Subject: [PATCH 07/12] riscv: hwprobe: Document SiFive xsfvfnrclipxfqf vendor extension Document the support for SiFive vendor extensions for FP32-to-int8 Ranged Clip Instructions using RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF. Signed-off-by: Cyan Yang Signed-off-by: Linux RISC-V bot --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index df13822977d9b0..e59eec6506555b 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -349,3 +349,7 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Instruction Extensions Specification. + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf + vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged + Clip Instructions Extensions Specification. From 418f392b5486151cc12e29f6ad8e3dcb7372f8d3 Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:06 +0800 Subject: [PATCH 08/12] riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extension Add hwprobe for SiFive "xsfvfnrclipxfqf" vendor extension. Signed-off-by: Cyan Yang Signed-off-by: Linux RISC-V bot --- arch/riscv/include/uapi/asm/vendor/sifive.h | 1 + arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/uapi/asm/vendor/sifive.h b/arch/riscv/include/uapi/asm/vendor/sifive.h index f25d8cf110d1e8..b772d463128401 100644 --- a/arch/riscv/include/uapi/asm/vendor/sifive.h +++ b/arch/riscv/include/uapi/asm/vendor/sifive.h @@ -2,3 +2,4 @@ #define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD (1 << 0) #define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ (1 << 1) +#define RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF (1 << 2) diff --git a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c index 461ce0f305ce03..2b9505079a9f1d 100644 --- a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c +++ b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c @@ -16,5 +16,6 @@ void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cp riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap, { VENDOR_EXT_KEY(XSFVQMACCDOD); VENDOR_EXT_KEY(XSFVQMACCQOQ); + VENDOR_EXT_KEY(XSFVFNRCLIPXFQF); }); } From ed5169dcdd0f25c881987591f0747061e356b0b7 Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:07 +0800 Subject: [PATCH 09/12] dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description Add "xsfvfwmaccqqq" ISA extension which is provided by SiFive for matrix multiply accumulate instructions support. Signed-off-by: Cyan Yang Acked-by: Conor Dooley Signed-off-by: Linux RISC-V bot --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index be203df29eb838..ede6a58ccf5347 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -681,6 +681,12 @@ properties: See more details in https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions + - const: xsfvfwmaccqqq + description: + SiFive Matrix Multiply Accumulate Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction + # T-HEAD - const: xtheadvector description: From 1adb4e005f106eb35adaf6ef5ac1dc848022c831 Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:08 +0800 Subject: [PATCH 10/12] riscv: Add SiFive xsfvfwmaccqqq vendor extension Add SiFive vendor extension "xsfvfwmaccqqq" support to the kernel. Signed-off-by: Cyan Yang Signed-off-by: Linux RISC-V bot --- arch/riscv/include/asm/vendor_extensions/sifive.h | 1 + arch/riscv/kernel/vendor_extensions/sifive.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/vendor_extensions/sifive.h b/arch/riscv/include/asm/vendor_extensions/sifive.h index 2d05e3e731704c..ac00e500361c24 100644 --- a/arch/riscv/include/asm/vendor_extensions/sifive.h +++ b/arch/riscv/include/asm/vendor_extensions/sifive.h @@ -9,6 +9,7 @@ #define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD 0 #define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ 1 #define RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF 2 +#define RISCV_ISA_VENDOR_EXT_XSFVFWMACCQQQ 3 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive; diff --git a/arch/riscv/kernel/vendor_extensions/sifive.c b/arch/riscv/kernel/vendor_extensions/sifive.c index 9376e1ce133aaa..8fcf67e8c07fac 100644 --- a/arch/riscv/kernel/vendor_extensions/sifive.c +++ b/arch/riscv/kernel/vendor_extensions/sifive.c @@ -10,6 +10,7 @@ /* All SiFive vendor extensions supported in Linux */ static const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = { __RISCV_ISA_EXT_DATA(xsfvfnrclipxfqf, RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF), + __RISCV_ISA_EXT_DATA(xsfvfwmaccqqq, RISCV_ISA_VENDOR_EXT_XSFVFWMACCQQQ), __RISCV_ISA_EXT_DATA(xsfvqmaccdod, RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD), __RISCV_ISA_EXT_DATA(xsfvqmaccqoq, RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ), }; From fefbad5ba504d4f4e9503634f2a2605eaab899d2 Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:09 +0800 Subject: [PATCH 11/12] riscv: hwprobe: Document SiFive xsfvfwmaccqqq vendor extension Document the support for matrix multiply accumulate instruction from SiFive using RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ. Signed-off-by: Cyan Yang Signed-off-by: Linux RISC-V bot --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index e59eec6506555b..e3ad9e4af6d564 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -353,3 +353,7 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq + vendor extension is supported in version 1.0 of Matrix Multiply Accumulate + Instruction Extensions Specification. \ No newline at end of file From 3b2a9bde2c063d433ae8d792b1dc296db826cc12 Mon Sep 17 00:00:00 2001 From: Cyan Yang Date: Fri, 16 May 2025 11:03:10 +0800 Subject: [PATCH 12/12] riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension Add hwprobe for SiFive "xsfvfwmaccqqq" vendor extension. Signed-off-by: Cyan Yang Signed-off-by: Linux RISC-V bot --- arch/riscv/include/uapi/asm/vendor/sifive.h | 1 + arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/uapi/asm/vendor/sifive.h b/arch/riscv/include/uapi/asm/vendor/sifive.h index b772d463128401..9f3278a4b298a7 100644 --- a/arch/riscv/include/uapi/asm/vendor/sifive.h +++ b/arch/riscv/include/uapi/asm/vendor/sifive.h @@ -3,3 +3,4 @@ #define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD (1 << 0) #define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ (1 << 1) #define RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF (1 << 2) +#define RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ (1 << 3) diff --git a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c index 2b9505079a9f1d..1f77f630976359 100644 --- a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c +++ b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c @@ -17,5 +17,6 @@ void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cp VENDOR_EXT_KEY(XSFVQMACCDOD); VENDOR_EXT_KEY(XSFVQMACCQOQ); VENDOR_EXT_KEY(XSFVFNRCLIPXFQF); + VENDOR_EXT_KEY(XSFVFWMACCQQQ); }); }