From 863e092fa293172dcc53e4578aa8f9db285eae4e Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 17 Jun 2025 15:01:39 +0800 Subject: [PATCH 1/4] dt-bindings: reset: sophgo: Add CV1800B support Add bindings for the reset generator on the SOPHGO CV1800B RISC-V SoC. Signed-off-by: Inochi Amaoto Signed-off-by: Linux RISC-V bot --- .../devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml index 1d1b84575960c3..08d28313b87083 100644 --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml @@ -16,7 +16,9 @@ properties: - enum: - sophgo,sg2044-reset - const: sophgo,sg2042-reset - - const: sophgo,sg2042-reset + - enum: + - sophgo,cv1800b-reset + - sophgo,sg2042-reset reg: maxItems: 1 From bbcfa986cf6075ba8e8ad79b36714f61cbddb82d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 17 Jun 2025 15:01:40 +0800 Subject: [PATCH 2/4] reset: simple: add support for Sophgo CV1800B Reuse reset-simple driver for the Sophgo CV1800B reset generator. Signed-off-by: Inochi Amaoto Reviewed-by: Alexander Sverdlin Tested-by: Alexander Sverdlin Signed-off-by: Linux RISC-V bot --- drivers/reset/reset-simple.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 27606783983086..79e94ecfe4f553 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = { { .compatible = "snps,dw-high-reset" }, { .compatible = "snps,dw-low-reset", .data = &reset_simple_active_low }, + { .compatible = "sophgo,cv1800b-reset", + .data = &reset_simple_active_low }, { .compatible = "sophgo,sg2042-reset", .data = &reset_simple_active_low }, { /* sentinel */ }, From a5cac8307e28b45ae1801e208b99f7befdfeb445 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 17 Jun 2025 15:01:41 +0800 Subject: [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Add reset generator node for all CV18XX series SoC. Signed-off-by: Inochi Amaoto Reviewed-by: Alexander Sverdlin Tested-by: Junhui Liu Tested-by: Alexander Sverdlin Signed-off-by: Linux RISC-V bot --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 7 ++ arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++ 2 files changed, 105 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index ed06c3609fb223..4c3d1676413151 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include "cv18xx-reset.h" / { #address-cells = <1>; @@ -24,6 +25,12 @@ #size-cells = <1>; ranges; + rst: reset-controller@3003000 { + compatible = "sophgo,cv1800b-reset"; + reg = <0x3003000 0x1000>; + #reset-cells = <1>; + }; + gpio0: gpio@3020000 { compatible = "snps,dw-apb-gpio"; reg = <0x3020000 0x1000>; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h new file mode 100644 index 00000000000000..7e7c5ca2dbbd78 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2025 Inochi Amaoto + */ + +#ifndef _SOPHGO_CV18XX_RESET +#define _SOPHGO_CV18XX_RESET + +#define RST_DDR 2 +#define RST_H264C 3 +#define RST_JPEG 4 +#define RST_H265C 5 +#define RST_VIPSYS 6 +#define RST_TDMA 7 +#define RST_TPU 8 +#define RST_TPUSYS 9 +#define RST_USB 11 +#define RST_ETH0 12 +#define RST_ETH1 13 +#define RST_NAND 14 +#define RST_EMMC 15 +#define RST_SD0 16 +#define RST_SDMA 18 +#define RST_I2S0 19 +#define RST_I2S1 20 +#define RST_I2S2 21 +#define RST_I2S3 22 +#define RST_UART0 23 +#define RST_UART1 24 +#define RST_UART2 25 +#define RST_UART3 26 +#define RST_I2C0 27 +#define RST_I2C1 28 +#define RST_I2C2 29 +#define RST_I2C3 30 +#define RST_I2C4 31 +#define RST_PWM0 32 +#define RST_PWM1 33 +#define RST_PWM2 34 +#define RST_PWM3 35 +#define RST_SPI0 40 +#define RST_SPI1 41 +#define RST_SPI2 42 +#define RST_SPI3 43 +#define RST_GPIO0 44 +#define RST_GPIO1 45 +#define RST_GPIO2 46 +#define RST_EFUSE 47 +#define RST_WDT 48 +#define RST_AHB_ROM 49 +#define RST_SPIC 50 +#define RST_TEMPSEN 51 +#define RST_SARADC 52 +#define RST_COMBO_PHY0 58 +#define RST_SPI_NAND 61 +#define RST_SE 62 +#define RST_UART4 74 +#define RST_GPIO3 75 +#define RST_SYSTEM 76 +#define RST_TIMER 77 +#define RST_TIMER0 78 +#define RST_TIMER1 79 +#define RST_TIMER2 80 +#define RST_TIMER3 81 +#define RST_TIMER4 82 +#define RST_TIMER5 83 +#define RST_TIMER6 84 +#define RST_TIMER7 85 +#define RST_WGN0 86 +#define RST_WGN1 87 +#define RST_WGN2 88 +#define RST_KEYSCAN 89 +#define RST_AUDDAC 91 +#define RST_AUDDAC_APB 92 +#define RST_AUDADC 93 +#define RST_VCSYS 95 +#define RST_ETHPHY 96 +#define RST_ETHPHY_APB 97 +#define RST_AUDSRC 98 +#define RST_VIP_CAM0 99 +#define RST_WDT1 100 +#define RST_WDT2 101 +#define RST_AUTOCLEAR_CPUCORE0 256 +#define RST_AUTOCLEAR_CPUCORE1 257 +#define RST_AUTOCLEAR_CPUCORE2 258 +#define RST_AUTOCLEAR_CPUCORE3 259 +#define RST_AUTOCLEAR_CPUSYS0 260 +#define RST_AUTOCLEAR_CPUSYS1 261 +#define RST_AUTOCLEAR_CPUSYS2 262 +#define RST_CPUCORE0 288 +#define RST_CPUCORE1 289 +#define RST_CPUCORE2 290 +#define RST_CPUCORE3 291 +#define RST_CPUSYS0 292 +#define RST_CPUSYS1 293 +#define RST_CPUSYS2 294 + +#endif /* _SOPHGO_CV18XX_RESET */ From 16fb06234c045059788c15c8c9ba91d056a9d6ee Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 17 Jun 2025 15:01:42 +0800 Subject: [PATCH 4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC Add known reset configuration for existed device. Signed-off-by: Inochi Amaoto Reviewed-by: Alexander Sverdlin Signed-off-by: Linux RISC-V bot --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 4c3d1676413151..e91bb512b099c7 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -36,6 +36,7 @@ reg = <0x3020000 0x1000>; #address-cells = <1>; #size-cells = <0>; + resets = <&rst RST_GPIO0>; porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -54,6 +55,7 @@ reg = <0x3021000 0x1000>; #address-cells = <1>; #size-cells = <0>; + resets = <&rst RST_GPIO1>; portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -72,6 +74,7 @@ reg = <0x3022000 0x1000>; #address-cells = <1>; #size-cells = <0>; + resets = <&rst RST_GPIO2>; portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -90,6 +93,7 @@ reg = <0x3023000 0x1000>; #address-cells = <1>; #size-cells = <0>; + resets = <&rst RST_GPIO3>; portd: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -133,6 +137,7 @@ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C0>; status = "disabled"; }; @@ -144,6 +149,7 @@ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C1>; status = "disabled"; }; @@ -155,6 +161,7 @@ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C2>; status = "disabled"; }; @@ -166,6 +173,7 @@ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C3>; status = "disabled"; }; @@ -177,6 +185,7 @@ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C4>; status = "disabled"; }; @@ -188,6 +197,7 @@ clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART0>; status = "disabled"; }; @@ -199,6 +209,7 @@ clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART1>; status = "disabled"; }; @@ -210,6 +221,7 @@ clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART2>; status = "disabled"; }; @@ -221,6 +233,7 @@ clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART3>; status = "disabled"; }; @@ -232,6 +245,7 @@ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; clock-names = "ssi_clk", "pclk"; interrupts = ; + resets = <&rst RST_SPI0>; status = "disabled"; }; @@ -243,6 +257,7 @@ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; clock-names = "ssi_clk", "pclk"; interrupts = ; + resets = <&rst RST_SPI1>; status = "disabled"; }; @@ -254,6 +269,7 @@ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; clock-names = "ssi_clk", "pclk"; interrupts = ; + resets = <&rst RST_SPI2>; status = "disabled"; }; @@ -265,6 +281,7 @@ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; clock-names = "ssi_clk", "pclk"; interrupts = ; + resets = <&rst RST_SPI3>; status = "disabled"; }; @@ -276,6 +293,7 @@ clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART4>; status = "disabled"; };