diff --git a/clang/include/clang/Basic/BuiltinsAMDGPUDocs.td b/clang/include/clang/Basic/BuiltinsAMDGPUDocs.td index c78c8ec291eef..0b5215381c72a 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPUDocs.td +++ b/clang/include/clang/Basic/BuiltinsAMDGPUDocs.td @@ -718,7 +718,7 @@ value gives an undefined result. def DocCatSBufferLoad : DocumentationCategory<"S-Buffer Load Builtins"> { let Content = [{ -These builtins lower to ``llvm.amdgcn.s.buffer.load`` and issue an +These builtins lower to ``llvm.amdgcn.ptr.s.buffer.load`` and issue an ``s_buffer_load`` when the byte offset is uniform across the wavefront. When the offset is divergent, the backend may lower to a ``buffer_load``. @@ -735,8 +735,7 @@ When the offset is divergent, the backend may lower to a ``buffer_load``. These builtins take the buffer resource as ``__amdgpu_buffer_rsrc_t``, which can be created with ``__builtin_amdgcn_make_buffer_rsrc``. The backend -lowers the resource to the 4-dword SGPR descriptor required by -``llvm.amdgcn.s.buffer.load``. +lowers the resource to the 4-dword SGPR descriptor required by the instruction. The return type selects the load width. Separate builtins are provided for each supported scalar and vector element type. diff --git a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp index 66e4e688e33ee..119cdc7b8ab19 100644 --- a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp @@ -34,17 +34,16 @@ namespace { static Value *emitAMDGPUSBufferLoadBuiltin(CodeGenFunction &CGF, const CallExpr *E) { llvm::Type *RetTy = CGF.ConvertType(E->getType()); - Function *F = CGF.CGM.getIntrinsic(Intrinsic::amdgcn_s_buffer_load, RetTy); + Function *F = + CGF.CGM.getIntrinsic(Intrinsic::amdgcn_ptr_s_buffer_load, RetTy); Value *RsrcPtr = CGF.EmitScalarExpr(E->getArg(0)); - llvm::Type *I128Ty = llvm::IntegerType::get(CGF.getLLVMContext(), 128); - llvm::Type *RsrcVecTy = - llvm::FixedVectorType::get(CGF.Builder.getInt32Ty(), 4); - Value *RsrcInt = CGF.Builder.CreatePtrToInt(RsrcPtr, I128Ty); - Value *Rsrc = CGF.Builder.CreateBitCast(RsrcInt, RsrcVecTy); - - return CGF.Builder.CreateCall(F, {Rsrc, CGF.EmitScalarExpr(E->getArg(1)), - CGF.EmitScalarExpr(E->getArg(2))}); + CallInst *Call = + CGF.Builder.CreateCall(F, {RsrcPtr, CGF.EmitScalarExpr(E->getArg(1)), + CGF.EmitScalarExpr(E->getArg(2))}); + Call->setMetadata(llvm::LLVMContext::MD_invariant_load, + llvm::MDNode::get(CGF.Builder.getContext(), {})); + return Call; } // Has second type mangled argument. diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-s-buffer-load.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-s-buffer-load.cl index 0c640e5020267..570becbf1bf88 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-s-buffer-load.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-s-buffer-load.cl @@ -23,9 +23,7 @@ typedef half v4f16 __attribute__((ext_vector_type(4))); // CHECK-LABEL: @test_amdgcn_s_buffer_load_i32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8:![0-9]+]] // CHECK-NEXT: ret i32 [[TMP0]] // int test_amdgcn_s_buffer_load_i32(__amdgpu_buffer_rsrc_t rsrc) { @@ -34,9 +32,7 @@ int test_amdgcn_s_buffer_load_i32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_i32_non_const_offset( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> [[RSRC_VEC:%.*]], i32 [[OFFSET:%.*]], i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFFSET:%.*]], i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret i32 [[TMP0]] // int test_amdgcn_s_buffer_load_i32_non_const_offset(__amdgpu_buffer_rsrc_t rsrc, int offset) { @@ -45,9 +41,7 @@ int test_amdgcn_s_buffer_load_i32_non_const_offset(__amdgpu_buffer_rsrc_t rsrc, // CHECK-LABEL: @test_amdgcn_s_buffer_load_v2i32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <2 x i32> [[TMP0]] // v2i32 test_amdgcn_s_buffer_load_v2i32(__amdgpu_buffer_rsrc_t rsrc) { @@ -56,9 +50,7 @@ v2i32 test_amdgcn_s_buffer_load_v2i32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v3i32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <3 x i32> [[TMP0]] // v3i32 test_amdgcn_s_buffer_load_v3i32(__amdgpu_buffer_rsrc_t rsrc) { @@ -67,9 +59,7 @@ v3i32 test_amdgcn_s_buffer_load_v3i32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v4i32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <4 x i32> [[TMP0]] // v4i32 test_amdgcn_s_buffer_load_v4i32(__amdgpu_buffer_rsrc_t rsrc) { @@ -78,9 +68,7 @@ v4i32 test_amdgcn_s_buffer_load_v4i32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v8i32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <8 x i32> [[TMP0]] // v8i32 test_amdgcn_s_buffer_load_v8i32(__amdgpu_buffer_rsrc_t rsrc) { @@ -89,9 +77,7 @@ v8i32 test_amdgcn_s_buffer_load_v8i32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v16i32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <16 x i32> [[TMP0]] // v16i32 test_amdgcn_s_buffer_load_v16i32(__amdgpu_buffer_rsrc_t rsrc) { @@ -100,9 +86,7 @@ v16i32 test_amdgcn_s_buffer_load_v16i32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_f32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret float [[TMP0]] // float test_amdgcn_s_buffer_load_f32(__amdgpu_buffer_rsrc_t rsrc) { @@ -111,9 +95,7 @@ float test_amdgcn_s_buffer_load_f32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v2f32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <2 x float> [[TMP0]] // v2f32 test_amdgcn_s_buffer_load_v2f32(__amdgpu_buffer_rsrc_t rsrc) { @@ -122,9 +104,7 @@ v2f32 test_amdgcn_s_buffer_load_v2f32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v3f32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <3 x float> [[TMP0]] // v3f32 test_amdgcn_s_buffer_load_v3f32(__amdgpu_buffer_rsrc_t rsrc) { @@ -133,9 +113,7 @@ v3f32 test_amdgcn_s_buffer_load_v3f32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v4f32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <4 x float> [[TMP0]] // v4f32 test_amdgcn_s_buffer_load_v4f32(__amdgpu_buffer_rsrc_t rsrc) { @@ -144,9 +122,7 @@ v4f32 test_amdgcn_s_buffer_load_v4f32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v8f32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <8 x float> [[TMP0]] // v8f32 test_amdgcn_s_buffer_load_v8f32(__amdgpu_buffer_rsrc_t rsrc) { @@ -155,9 +131,7 @@ v8f32 test_amdgcn_s_buffer_load_v8f32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v16f32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <16 x float> [[TMP0]] // v16f32 test_amdgcn_s_buffer_load_v16f32(__amdgpu_buffer_rsrc_t rsrc) { @@ -166,9 +140,7 @@ v16f32 test_amdgcn_s_buffer_load_v16f32(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_i8( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret i8 [[TMP0]] // char test_amdgcn_s_buffer_load_i8(__amdgpu_buffer_rsrc_t rsrc) { @@ -177,9 +149,7 @@ char test_amdgcn_s_buffer_load_i8(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_u8( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret i8 [[TMP0]] // unsigned char test_amdgcn_s_buffer_load_u8(__amdgpu_buffer_rsrc_t rsrc) { @@ -188,9 +158,7 @@ unsigned char test_amdgcn_s_buffer_load_u8(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_i16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call i16 @llvm.amdgcn.s.buffer.load.i16(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret i16 [[TMP0]] // short test_amdgcn_s_buffer_load_i16(__amdgpu_buffer_rsrc_t rsrc) { @@ -199,9 +167,7 @@ short test_amdgcn_s_buffer_load_i16(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_u16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call i16 @llvm.amdgcn.s.buffer.load.i16(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret i16 [[TMP0]] // unsigned short test_amdgcn_s_buffer_load_u16(__amdgpu_buffer_rsrc_t rsrc) { @@ -210,9 +176,7 @@ unsigned short test_amdgcn_s_buffer_load_u16(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_f16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call half @llvm.amdgcn.s.buffer.load.f16(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret half [[TMP0]] // half test_amdgcn_s_buffer_load_f16(__amdgpu_buffer_rsrc_t rsrc) { @@ -221,9 +185,7 @@ half test_amdgcn_s_buffer_load_f16(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v2f16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <2 x half> @llvm.amdgcn.s.buffer.load.v2f16(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <2 x half> @llvm.amdgcn.ptr.s.buffer.load.v2f16(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <2 x half> [[TMP0]] // v2f16 test_amdgcn_s_buffer_load_v2f16(__amdgpu_buffer_rsrc_t rsrc) { @@ -232,9 +194,7 @@ v2f16 test_amdgcn_s_buffer_load_v2f16(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v3f16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <3 x half> @llvm.amdgcn.s.buffer.load.v3f16(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <3 x half> @llvm.amdgcn.ptr.s.buffer.load.v3f16(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <3 x half> [[TMP0]] // v3f16 test_amdgcn_s_buffer_load_v3f16(__amdgpu_buffer_rsrc_t rsrc) { @@ -243,9 +203,7 @@ v3f16 test_amdgcn_s_buffer_load_v3f16(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v4f16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x half> @llvm.amdgcn.s.buffer.load.v4f16(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x half> @llvm.amdgcn.ptr.s.buffer.load.v4f16(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <4 x half> [[TMP0]] // v4f16 test_amdgcn_s_buffer_load_v4f16(__amdgpu_buffer_rsrc_t rsrc) { @@ -254,9 +212,7 @@ v4f16 test_amdgcn_s_buffer_load_v4f16(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v2i8( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <2 x i8> @llvm.amdgcn.s.buffer.load.v2i8(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <2 x i8> @llvm.amdgcn.ptr.s.buffer.load.v2i8(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <2 x i8> [[TMP0]] // v2i8 test_amdgcn_s_buffer_load_v2i8(__amdgpu_buffer_rsrc_t rsrc) { @@ -265,9 +221,7 @@ v2i8 test_amdgcn_s_buffer_load_v2i8(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v3i8( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <3 x i8> @llvm.amdgcn.s.buffer.load.v3i8(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <3 x i8> @llvm.amdgcn.ptr.s.buffer.load.v3i8(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <3 x i8> [[TMP0]] // v3i8 test_amdgcn_s_buffer_load_v3i8(__amdgpu_buffer_rsrc_t rsrc) { @@ -276,9 +230,7 @@ v3i8 test_amdgcn_s_buffer_load_v3i8(__amdgpu_buffer_rsrc_t rsrc) { // CHECK-LABEL: @test_amdgcn_s_buffer_load_v4i8( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RSRC_INT:%.*]] = ptrtoint ptr addrspace(8) [[RSRC:%.*]] to i128 -// CHECK-NEXT: [[RSRC_VEC:%.*]] = bitcast i128 [[RSRC_INT]] to <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i8> @llvm.amdgcn.s.buffer.load.v4i8(<4 x i32> [[RSRC_VEC:%.*]], i32 0, i32 0) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i8> @llvm.amdgcn.ptr.s.buffer.load.v4i8(ptr addrspace(8) [[RSRC:%.*]], i32 0, i32 0), !invariant.load [[META8]] // CHECK-NEXT: ret <4 x i8> [[TMP0]] // v4i8 test_amdgcn_s_buffer_load_v4i8(__amdgpu_buffer_rsrc_t rsrc) { diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 21882e247c027..44da4277a82b7 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -1485,6 +1485,33 @@ def int_amdgcn_s_buffer_load : DefaultAttrsIntrinsic < [IntrNoMem, ImmArg>]>, AMDGPURsrcIntrinsic<0>; +// Generate an s_buffer_load instruction, falling back to buffer_load if the offset +// is not uniform. This operates like the s.buffer.load intrinsic, but uses a buffer +// resource pointer (`ptr addrspace(8)`) to hold the resource (which should be +// wave-uniform) instead of a `<4 x i32>`. Note that some architectures require +// the offset to be aligned to the width of the type being loaded (or, in some cases +// the shorter of that alignment and 4 bytes). +// +// Also note that this data is loaded via a distinct cache than typical load +// instructions or other buffer_load operations. Therefore, the data pointed to by +// this load *must* be invariant to avoid coherence risks. Frontends emitting +// this intrinsic *should* mark it `!invariant.load`, and the backend may also +// add such markings. +def int_amdgcn_ptr_s_buffer_load : DefaultAttrsIntrinsic < + [llvm_any_ty], + [AMDGPUBufferRsrcTy, // rsrc(SGPR) + llvm_i32_ty, // byte offset + llvm_i32_ty], // auxiliary/cachepolicy(imm): + // bit 0 = glc, bit 1 = slc, bit 2 = dlc (gfx10/gfx11), + // bit 3 = swz, bit 4 = scc (gfx90a) + // gfx942: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1 + // gfx12+: bits [0-2] = th, bits [3-4] = scope, + // bit 6 = swz + // Note: volatile bit is **not** permitted here. + [IntrArgMemOnly, IntrReadMem, ReadOnly>, + NoCapture>, ImmArg>], "", [SDNPMemOperand]>, + AMDGPURsrcIntrinsic<0>; + // Buffer intrinsics with separate raw and struct variants. The raw // variant never has an index. The struct variant always has an index, even if // it is const 0. A struct intrinsic with constant 0 index is different to the diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp index fddc8a3da0b53..991995a0c3d48 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp @@ -323,6 +323,7 @@ void getInterestingMemoryOperands( case Intrinsic::amdgcn_struct_tbuffer_load: case Intrinsic::amdgcn_struct_ptr_tbuffer_load: case Intrinsic::amdgcn_s_buffer_load: + case Intrinsic::amdgcn_ptr_s_buffer_load: case Intrinsic::amdgcn_global_load_tr_b64: case Intrinsic::amdgcn_global_load_tr_b128: { unsigned PtrOpNo = 0; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp index f5d8e43dce9db..d1788f79ba01a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp @@ -2328,6 +2328,7 @@ static Value *simplifyAMDGCNMemoryIntrinsicDemanded(InstCombiner &IC, OffsetIdx = 1; break; case Intrinsic::amdgcn_s_buffer_load: + case Intrinsic::amdgcn_ptr_s_buffer_load: // If resulting type is vec3, there is no point in trimming the // load with updated offset, as the vec3 would most likely be widened to // vec4 anyway during lowering. @@ -2530,6 +2531,7 @@ std::optional GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic( case Intrinsic::amdgcn_raw_tbuffer_load: case Intrinsic::amdgcn_raw_ptr_tbuffer_load: case Intrinsic::amdgcn_s_buffer_load: + case Intrinsic::amdgcn_ptr_s_buffer_load: case Intrinsic::amdgcn_struct_buffer_load: case Intrinsic::amdgcn_struct_ptr_buffer_load: case Intrinsic::amdgcn_struct_buffer_load_format: diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 2180ce67d576f..2ac33fd8760a9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -7665,6 +7665,7 @@ bool AMDGPULegalizerInfo::legalizeSBufferLoad(LegalizerHelper &Helper, LLT Ty = B.getMRI()->getType(OrigDst); unsigned Size = Ty.getSizeInBits(); MachineFunction &MF = B.getMF(); + bool HasMMO = !MI.memoperands_empty(); unsigned Opc = 0; if (Size < 32 && ST.hasScalarSubwordLoads()) { assert(Size == 8 || Size == 16); @@ -7691,22 +7692,23 @@ bool AMDGPULegalizerInfo::legalizeSBufferLoad(LegalizerHelper &Helper, B.setInsertPt(B.getMBB(), MI); } - // FIXME: We don't really need this intermediate instruction. The intrinsic - // should be fixed to have a memory operand. Since it's readnone, we're not - // allowed to add one. MI.setDesc(B.getTII().get(Opc)); - MI.removeOperand(1); // Remove intrinsic ID - - // FIXME: When intrinsic definition is fixed, this should have an MMO already. - const unsigned MemSize = (Size + 7) / 8; - const Align MemAlign = B.getDataLayout().getABITypeAlign( - getTypeForLLT(Ty, MF.getFunction().getContext())); - MachineMemOperand *MMO = MF.getMachineMemOperand( - MachinePointerInfo(), - MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable | - MachineMemOperand::MOInvariant, - MemSize, MemAlign); - MI.addMemOperand(MF, MMO); + MI.removeOperand(1); + castBufferRsrcArgToV4I32(MI, B, 1); + + if (!HasMMO) { + // Legacy intrinsic that doesn't take a pointer and so can't already have an + // MMO. + const unsigned MemSize = (Size + 7) / 8; + const Align MemAlign = B.getDataLayout().getABITypeAlign( + getTypeForLLT(Ty, MF.getFunction().getContext())); + MachineMemOperand *MMO = MF.getMachineMemOperand( + MachinePointerInfo(), + MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable | + MachineMemOperand::MOInvariant, + MemSize, MemAlign); + MI.addMemOperand(MF, MMO); + } if (Dst != OrigDst) { MI.getOperand(0).setReg(Dst); B.setInsertPt(B.getMBB(), ++B.getInsertPt()); @@ -8492,6 +8494,7 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, return true; } case Intrinsic::amdgcn_s_buffer_load: + case Intrinsic::amdgcn_ptr_s_buffer_load: return legalizeSBufferLoad(Helper, MI); case Intrinsic::amdgcn_raw_buffer_store: case Intrinsic::amdgcn_raw_ptr_buffer_store: diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp index 59597e3dd85cc..123d9930fc49e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp @@ -38,6 +38,7 @@ class AMDGPULowerIntrinsicsImpl { private: bool visitBarrier(IntrinsicInst &I); + bool visitPtrSBufferLoad(IntrinsicInst &I); }; class AMDGPULowerIntrinsicsLegacy : public ModulePass { @@ -76,6 +77,10 @@ bool AMDGPULowerIntrinsicsImpl::run() { case Intrinsic::amdgcn_s_cluster_barrier: forEachCall(F, [&](IntrinsicInst *II) { Changed |= visitBarrier(*II); }); break; + case Intrinsic::amdgcn_ptr_s_buffer_load: + forEachCall( + F, [&](IntrinsicInst *II) { Changed |= visitPtrSBufferLoad(*II); }); + break; } } @@ -193,6 +198,17 @@ bool AMDGPULowerIntrinsicsImpl::visitBarrier(IntrinsicInst &I) { return false; } +bool AMDGPULowerIntrinsicsImpl::visitPtrSBufferLoad(IntrinsicInst &I) { + assert(I.getIntrinsicID() == Intrinsic::amdgcn_ptr_s_buffer_load); + + if (I.hasMetadata(LLVMContext::MD_invariant_load)) + return false; + + I.setMetadata(LLVMContext::MD_invariant_load, + MDNode::get(I.getContext(), {})); + return true; +} + PreservedAnalyses AMDGPULowerIntrinsicsPass::run(Module &M, ModuleAnalysisManager &MAM) { AMDGPULowerIntrinsicsImpl Impl(M, TM); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp index 369734004c3c0..39c3db9282e12 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp @@ -644,9 +644,9 @@ bool RegBankLegalizeHelper::lowerSBufToBuf(MachineInstr &MI, NumLoads = LoadSize / 128; Ty = Ty.divide(NumLoads); } - for (int i = 0; i < NumLoads; ++i) - LoadParts.emplace_back(MRI.createVirtualRegister({VgprRB, Ty})); MachineMemOperand *OrigMMO = *MI.memoperands_begin(); + for (int I = 0; I < NumLoads; ++I) + LoadParts.emplace_back(MRI.createVirtualRegister({VgprRB, Ty})); const Align Alignment = OrigMMO->getAlign(); MachineFunction &MF = B.getMF(); Register SOffset; @@ -654,9 +654,6 @@ bool RegBankLegalizeHelper::lowerSBufToBuf(MachineInstr &MI, int64_t ImmOffset = 0; unsigned MMOOffset = setBufferOffsets(B, MI.getOperand(2).getReg(), VOffset, SOffset, ImmOffset, Alignment); - // Use the MMO size from the original instruction rather than the (possibly - // widened) register type. E.g. 96-bit loads are widened to 128-bit during - // legalization but the MMO still reflects the original 96-bit access size. const unsigned MemSize = divideCeil(OrigMMO->getSize().getValue(), NumLoads); MachineMemOperand *BaseMMO = MF.getMachineMemOperand(OrigMMO, 0, MemSize); if (MMOOffset != 0) @@ -665,6 +662,7 @@ bool RegBankLegalizeHelper::lowerSBufToBuf(MachineInstr &MI, // instead. We can assume that the buffer is unswizzled. Register RSrc = MI.getOperand(1).getReg(); Register VIndex = B.buildConstant(VgprRB_I32, 0).getReg(0); + unsigned CachePolicy = MI.getOperand(3).getImm(); unsigned Opc = AMDGPU::G_AMDGPU_BUFFER_LOAD; switch (MI.getOpcode()) { case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SBYTE: @@ -682,17 +680,17 @@ bool RegBankLegalizeHelper::lowerSBufToBuf(MachineInstr &MI, default: break; } - for (int i = 0; i < NumLoads; ++i) { + for (int I = 0; I < NumLoads; ++I) { B.buildInstr(Opc) - .addDef(LoadParts[i]) // vdata + .addDef(LoadParts[I]) // vdata .addUse(RSrc) // rsrc .addUse(VIndex) // vindex .addUse(VOffset) // voffset .addUse(SOffset) // soffset - .addImm(ImmOffset + 16 * i) // offset(imm) - .addImm(0) // cachepolicy, swizzled buffer(imm) + .addImm(ImmOffset + 16 * I) // offset(imm) + .addImm(CachePolicy) // cachepolicy, swizzled buffer(imm) .addImm(0) // idxen(imm) - .addMemOperand(MF.getMachineMemOperand(BaseMMO, 16 * i, MemSize)); + .addMemOperand(MF.getMachineMemOperand(BaseMMO, 16 * I, MemSize)); } if (NumLoads == 1) B.buildCopy(Dst, LoadParts[0]); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 200234c23c886..db4d0ffaf74d1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -385,7 +385,8 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects( const MachineInstr &MI, const MachineRegisterInfo &MRI) const { switch (cast(MI).getIntrinsicID()) { - case Intrinsic::amdgcn_s_buffer_load: { + case Intrinsic::amdgcn_s_buffer_load: + case Intrinsic::amdgcn_ptr_s_buffer_load: { static const OpRegBankEntry<2> Table[4] = { // Perfectly legal. { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 }, @@ -1367,9 +1368,9 @@ bool AMDGPURegisterBankInfo::applyMappingSBufferLoad( LLT Ty = MRI.getType(Dst); const RegisterBank *RSrcBank = - OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; + OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; const RegisterBank *OffsetBank = - OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank; + OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank; if (RSrcBank == &AMDGPU::SGPRRegBank && OffsetBank == &AMDGPU::SGPRRegBank) return true; // Legal mapping @@ -1415,6 +1416,7 @@ bool AMDGPURegisterBankInfo::applyMappingSBufferLoad( Register RSrc = MI.getOperand(1).getReg(); Register VIndex = B.buildConstant(S32, 0).getReg(0); B.getMRI()->setRegBank(VIndex, AMDGPU::VGPRRegBank); + unsigned CachePolicy = MI.getOperand(3).getImm(); SmallVector LoadParts(NumLoads); @@ -1439,7 +1441,7 @@ bool AMDGPURegisterBankInfo::applyMappingSBufferLoad( .addUse(VOffset) // voffset .addUse(SOffset) // soffset .addImm(ImmOffset + 16 * i) // offset(imm) - .addImm(0) // cachepolicy, swizzled buffer(imm) + .addImm(CachePolicy) // cachepolicy, swizzled buffer(imm) .addImm(0) // idxen(imm) .addMemOperand(BaseMMO); } @@ -5464,6 +5466,12 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); break; } + case Intrinsic::amdgcn_ptr_s_buffer_load: { + OpdsMapping[0] = getSGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI); + OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI); + OpdsMapping[3] = getSGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI); + break; + } case Intrinsic::amdgcn_raw_buffer_load: case Intrinsic::amdgcn_raw_ptr_buffer_load: case Intrinsic::amdgcn_raw_atomic_buffer_load: diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 9cf33b4ccbb87..e4b6dc037a11f 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1418,6 +1418,7 @@ void SITargetLowering::getTgtMemIntrinsic(SmallVectorImpl &Infos, if (Aux->getZExtValue() & AMDGPU::CPol::VOLATILE) Flags |= MachineMemOperand::MOVolatile; } + Flags |= MachineMemOperand::MODereferenceable; IntrinsicInfo Info; @@ -8353,11 +8354,12 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N, VT.getStoreSize(), Alignment); SDValue LoadVal; if (!Offset->isDivergent()) { - SDValue Ops[] = {Rsrc, // source register + SDValue Ops[] = {DAG.getEntryNode(), // Chain + Rsrc, // source register Offset, CachePolicy}; - SDValue BufferLoad = - DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD_UBYTE, DL, - DAG.getVTList(MVT::i32), Ops, VT, MMO); + SDValue BufferLoad = DAG.getMemIntrinsicNode( + AMDGPUISD::SBUFFER_LOAD_UBYTE, DL, + DAG.getVTList(MVT::i32, MVT::Other), Ops, VT, MMO); LoadVal = DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad); } else { SDValue Ops[] = { @@ -10705,33 +10707,58 @@ SDValue SITargetLowering::lowerImage(SDValue Op, NumVDataDwords, IsAtomicPacked16Bit, DL); } -SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, +SDValue SITargetLowering::lowerSBuffer(EVT VT, EVT MemVT, SDLoc DL, + SDValue Chain, SDValue Rsrc, SDValue Offset, SDValue CachePolicy, - SelectionDAG &DAG) const { + SelectionDAG &DAG, + MachineMemOperand *MMO) const { MachineFunction &MF = DAG.getMachineFunction(); + bool HasChainResult = MMO != nullptr; - const DataLayout &DataLayout = DAG.getDataLayout(); - Align Alignment = - DataLayout.getABITypeAlign(VT.getTypeForEVT(*DAG.getContext())); + if (!MMO) { + const DataLayout &DataLayout = DAG.getDataLayout(); + Align Alignment = + DataLayout.getABITypeAlign(MemVT.getTypeForEVT(*DAG.getContext())); - MachineMemOperand *MMO = MF.getMachineMemOperand( - MachinePointerInfo(), - MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable | - MachineMemOperand::MOInvariant, - VT.getStoreSize(), Alignment); + MMO = MF.getMachineMemOperand(MachinePointerInfo(), + MachineMemOperand::MOLoad | + MachineMemOperand::MODereferenceable | + MachineMemOperand::MOInvariant, + MemVT.getStoreSize(), Alignment); + } if (!Offset->isDivergent()) { - SDValue Ops[] = {Rsrc, Offset, CachePolicy}; + SDValue Ops[] = {Chain, Rsrc, Offset, CachePolicy}; + + // Lower llvm.amdgcn.*s.buffer.load.(i8, u8) intrinsics. First, generate + // s_buffer_load_u8 for signed and unsigned load instructions. Next, DAG + // combiner tries to merge the s_buffer_load_u8 with a sext instruction + // (performSignExtendInRegCombine()) and it replaces s_buffer_load_u8 with + // s_buffer_load_i8. + if (MemVT == MVT::i8 && Subtarget->hasScalarSubwordLoads()) { + SDValue BufferLoad = DAG.getMemIntrinsicNode( + AMDGPUISD::SBUFFER_LOAD_UBYTE, DL, + DAG.getVTList(MVT::i32, MVT::Other), Ops, MemVT, MMO); + SDValue LoadVal = DAG.getAnyExtOrTrunc( + DAG.getNode(ISD::TRUNCATE, DL, MemVT, BufferLoad), DL, VT); + if (HasChainResult) + return DAG.getMergeValues({LoadVal, BufferLoad.getValue(1)}, DL); + return LoadVal; + } // Lower llvm.amdgcn.s.buffer.load.{i16, u16} intrinsics. Initially, the // s_buffer_load_u16 instruction is emitted for both signed and unsigned // loads. Later, DAG combiner tries to combine s_buffer_load_u16 with sext // and generates s_buffer_load_i16 (performSignExtendInRegCombine). - if (VT == MVT::i16 && Subtarget->hasScalarSubwordLoads()) { - SDValue BufferLoad = - DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD_USHORT, DL, - DAG.getVTList(MVT::i32), Ops, VT, MMO); - return DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad); + if (MemVT == MVT::i16 && Subtarget->hasScalarSubwordLoads()) { + SDValue BufferLoad = DAG.getMemIntrinsicNode( + AMDGPUISD::SBUFFER_LOAD_USHORT, DL, + DAG.getVTList(MVT::i32, MVT::Other), Ops, MemVT, MMO); + SDValue LoadVal = DAG.getAnyExtOrTrunc( + DAG.getNode(ISD::TRUNCATE, DL, MemVT, BufferLoad), DL, VT); + if (HasChainResult) + return DAG.getMergeValues({LoadVal, BufferLoad.getValue(1)}, DL); + return LoadVal; } // Widen vec3 load to vec4. @@ -10740,21 +10767,25 @@ SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, EVT WidenedVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4); auto WidenedOp = DAG.getMemIntrinsicNode( - AMDGPUISD::SBUFFER_LOAD, DL, DAG.getVTList(WidenedVT), Ops, WidenedVT, + AMDGPUISD::SBUFFER_LOAD, DL, DAG.getVTList(WidenedVT, MVT::Other), + Ops, WidenedVT, MF.getMachineMemOperand(MMO, 0, WidenedVT.getStoreSize())); auto Subvector = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp, DAG.getVectorIdxConstant(0, DL)); + if (HasChainResult) + return DAG.getMergeValues({Subvector, WidenedOp.getValue(1)}, DL); return Subvector; } return DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD, DL, - DAG.getVTList(VT), Ops, VT, MMO); + DAG.getVTList(VT, MVT::Other), Ops, MemVT, + MMO); } // We have a divergent offset. Emit a MUBUF buffer load instead. We can // assume that the buffer is unswizzled. SDValue Ops[] = { - DAG.getEntryNode(), // Chain + Chain, // Chain Rsrc, // rsrc DAG.getConstant(0, DL, MVT::i32), // vindex {}, // voffset @@ -10763,9 +10794,14 @@ SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, CachePolicy, // cachepolicy DAG.getTargetConstant(0, DL, MVT::i1), // idxen }; - if (VT == MVT::i16 && Subtarget->hasScalarSubwordLoads()) { + if ((MemVT == MVT::i8 || MemVT == MVT::i16) && + Subtarget->hasScalarSubwordLoads()) { setBufferOffsets(Offset, DAG, &Ops[3], Align(4)); - return handleByteShortBufferLoads(DAG, VT, DL, Ops, MMO); + SDValue Load = handleByteShortBufferLoads(DAG, MemVT, DL, Ops, MMO); + SDValue LoadVal = DAG.getAnyExtOrTrunc(Load.getOperand(0), DL, VT); + if (HasChainResult) + return DAG.getMergeValues({LoadVal, Load.getOperand(1)}, DL); + return LoadVal; } SmallVector Loads; @@ -10796,8 +10832,17 @@ SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, LoadVT, LoadMMO, DAG)); } - if (NumElts == 8 || NumElts == 16) - return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads); + if (NumElts == 8 || NumElts == 16) { + SDValue LoadVal = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads); + if (HasChainResult) { + SmallVector LoadChains; + for (SDValue Load : Loads) + LoadChains.push_back(Load.getValue(1)); + SDValue Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, LoadChains); + return DAG.getMergeValues({LoadVal, Chain}, DL); + } + return LoadVal; + } return Loads[0]; } @@ -11122,8 +11167,8 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12)) return Op; - return lowerSBuffer(VT, DL, Op.getOperand(1), Op.getOperand(2), - Op.getOperand(3), DAG); + return lowerSBuffer(VT, VT, DL, DAG.getEntryNode(), Op.getOperand(1), + Op.getOperand(2), Op.getOperand(3), DAG); } case Intrinsic::amdgcn_fdiv_fast: return lowerFDIV_FAST(Op, DAG); @@ -11554,6 +11599,19 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, M->getVTList(), Ops, M->getMemoryVT(), M->getMemOperand()); } + case Intrinsic::amdgcn_ptr_s_buffer_load: { + unsigned CPol = Op.getConstantOperandVal(4); + if (CPol & ~((Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12) + ? AMDGPU::CPol::ALL + : AMDGPU::CPol::ALL_pregfx12)) + return Op; + + MemSDNode *M = cast(Op); + return lowerSBuffer( + Op.getValueType(), M->getMemoryVT(), DL, Op.getOperand(0), + bufferRsrcPtrToVector(Op.getOperand(2), DAG), Op.getOperand(3), + Op.getOperand(4), DAG, M->getMemOperand()); + } case Intrinsic::amdgcn_raw_buffer_load: case Intrinsic::amdgcn_raw_ptr_buffer_load: case Intrinsic::amdgcn_raw_atomic_buffer_load: @@ -15677,22 +15735,22 @@ SITargetLowering::performSignExtendInRegCombine(SDNode *N, assert(Subtarget->hasScalarSubwordLoads() && "s_buffer_load_{u8, i8} are supported " "in GFX12 (or newer) architectures."); - EVT VT = Src.getValueType(); unsigned Opc = (Src.getOpcode() == AMDGPUISD::SBUFFER_LOAD_UBYTE) ? AMDGPUISD::SBUFFER_LOAD_BYTE : AMDGPUISD::SBUFFER_LOAD_SHORT; SDLoc DL(N); - SDVTList ResList = DCI.DAG.getVTList(MVT::i32); + SDVTList ResList = + DCI.DAG.getVTList(MVT::i32, Src.getOperand(0).getValueType()); SDValue Ops[] = { - Src.getOperand(0), // source register - Src.getOperand(1), // offset - Src.getOperand(2) // cachePolicy + Src.getOperand(0), // Chain + Src.getOperand(1), // source register + Src.getOperand(2), // offset + Src.getOperand(3) // cachePolicy }; auto *M = cast(Src); SDValue BufferLoad = DCI.DAG.getMemIntrinsicNode( Opc, DL, ResList, Ops, M->getMemoryVT(), M->getMemOperand()); - SDValue LoadVal = DCI.DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad); - return LoadVal; + return DCI.DAG.getMergeValues({BufferLoad, BufferLoad.getValue(1)}, DL); } if (((Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_UBYTE && VTSign->getVT() == MVT::i8) || diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index a181fa072d534..a560e34e01912 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -85,8 +85,9 @@ class SITargetLowering final : public AMDGPUTargetLowering { MVT VT, unsigned Offset) const; SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, SelectionDAG &DAG, bool WithChain) const; - SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, - SDValue CachePolicy, SelectionDAG &DAG) const; + SDValue lowerSBuffer(EVT VT, EVT MemVT, SDLoc DL, SDValue Chain, SDValue Rsrc, + SDValue Offset, SDValue CachePolicy, SelectionDAG &DAG, + MachineMemOperand *MMO = nullptr) const; SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, unsigned NewOpcode) const; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 7be067c085b5f..646b3681b49e3 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -66,22 +66,22 @@ def SDTSBufferLoad : SDTypeProfile<1, 3, SDTCisVT<3, i32>]>; // cachepolicy def SIsbuffer_load : SDNode<"AMDGPUISD::SBUFFER_LOAD", SDTSBufferLoad, - [SDNPMayLoad, SDNPMemOperand]>; + [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>; def SIsbuffer_load_byte : SDNode<"AMDGPUISD::SBUFFER_LOAD_BYTE", SDTSBufferLoad, - [SDNPMayLoad, SDNPMemOperand]>; + [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>; def SIsbuffer_load_ubyte : SDNode<"AMDGPUISD::SBUFFER_LOAD_UBYTE", SDTSBufferLoad, - [SDNPMayLoad, SDNPMemOperand]>; + [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>; def SIsbuffer_load_short : SDNode<"AMDGPUISD::SBUFFER_LOAD_SHORT", SDTSBufferLoad, - [SDNPMayLoad, SDNPMemOperand]>; + [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>; def SIsbuffer_load_ushort : SDNode<"AMDGPUISD::SBUFFER_LOAD_USHORT", SDTSBufferLoad, - [SDNPMayLoad, SDNPMemOperand]>; + [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>; def SIds_ordered_count : SDNode<"AMDGPUISD::DS_ORDERED_COUNT", SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i16>]>, diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll index eff96a424e0cf..d3359e95e2b1c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll @@ -65,7 +65,7 @@ define amdgpu_ps void @_amdgpu_ps_main(i1 %arg) { ; CHECK-NEXT: v_mov_b32_e32 v0, s4 ; CHECK-NEXT: s_branch .LBB0_3 bb: - %i = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> zeroinitializer, i32 0, i32 0) + %i = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) null, i32 0, i32 0), !invariant.load !{} %i1 = icmp slt i32 %i, 0 br i1 %i1, label %bb2, label %bb12 @@ -93,4 +93,4 @@ bb12: unreachable } -declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll new file mode 100644 index 0000000000000..72bc174397922 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll @@ -0,0 +1,4058 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX6 %s +; RUN: llc -global-isel -mtriple=amdgpu7.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX7 %s +; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX1200_1250,GFX1200 %s +; RUN: llc -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX1200_1250,GFX1250 %s + +; FIXME: Merge with regbankselect, which mostly overlaps when all types supported. + +; Natural mapping +define amdgpu_ps i32 @ptr_s_buffer_load_i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_glc(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_glc + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_glc + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_glc + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_glc + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 1), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps <2 x i32> @ptr_s_buffer_load_v2i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v2i32 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v2i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v2i32 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v2i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub0 + ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub1 + ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 + %val = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <2 x i32> %val +} + +define amdgpu_ps <3 x i32> @ptr_s_buffer_load_v3i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v3i32 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub3 + ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX6-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v3i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub3 + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX7-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v3i32 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub3 + ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX8-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v3i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM:%[0-9]+]]:sgpr_96 = S_BUFFER_LOAD_DWORDX3_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub0 + ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub1 + ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub2 + ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 + %val = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <3 x i32> %val +} + +define amdgpu_ps <8 x i32> @ptr_s_buffer_load_v8i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v8i32 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3 + ; GFX6-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4 + ; GFX6-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5 + ; GFX6-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7 + ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec + ; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec + ; GFX6-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec + ; GFX6-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] + ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec + ; GFX6-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] + ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec + ; GFX6-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] + ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec + ; GFX6-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] + ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec + ; GFX6-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v8i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3 + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4 + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5 + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7 + ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec + ; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec + ; GFX7-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec + ; GFX7-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] + ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec + ; GFX7-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] + ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec + ; GFX7-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] + ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec + ; GFX7-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] + ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec + ; GFX7-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v8i32 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3 + ; GFX8-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4 + ; GFX8-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec + ; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec + ; GFX8-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec + ; GFX8-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] + ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec + ; GFX8-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] + ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec + ; GFX8-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] + ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec + ; GFX8-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] + ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec + ; GFX8-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v8i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub0 + ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub1 + ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub2 + ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub3 + ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub4 + ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub5 + ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub6 + ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub7 + ; GFX1200_1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX1200_1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX1200_1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] + ; GFX1200_1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] + ; GFX1200_1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] + ; GFX1200_1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] + ; GFX1200_1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 + %val = call <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <8 x i32> %val +} + +define amdgpu_ps <16 x i32> @ptr_s_buffer_load_v16i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v16i32 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3 + ; GFX6-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4 + ; GFX6-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5 + ; GFX6-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7 + ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8 + ; GFX6-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9 + ; GFX6-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10 + ; GFX6-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11 + ; GFX6-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12 + ; GFX6-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13 + ; GFX6-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14 + ; GFX6-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15 + ; GFX6-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec + ; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX6-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec + ; GFX6-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX6-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec + ; GFX6-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] + ; GFX6-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec + ; GFX6-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] + ; GFX6-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec + ; GFX6-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] + ; GFX6-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec + ; GFX6-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] + ; GFX6-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec + ; GFX6-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] + ; GFX6-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec + ; GFX6-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]] + ; GFX6-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec + ; GFX6-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]] + ; GFX6-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec + ; GFX6-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]] + ; GFX6-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec + ; GFX6-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]] + ; GFX6-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec + ; GFX6-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]] + ; GFX6-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec + ; GFX6-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]] + ; GFX6-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec + ; GFX6-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]] + ; GFX6-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec + ; GFX6-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v16i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3 + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4 + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5 + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7 + ; GFX7-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8 + ; GFX7-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9 + ; GFX7-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10 + ; GFX7-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11 + ; GFX7-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12 + ; GFX7-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13 + ; GFX7-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14 + ; GFX7-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15 + ; GFX7-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec + ; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX7-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec + ; GFX7-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX7-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec + ; GFX7-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] + ; GFX7-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec + ; GFX7-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] + ; GFX7-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec + ; GFX7-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] + ; GFX7-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec + ; GFX7-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] + ; GFX7-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec + ; GFX7-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] + ; GFX7-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec + ; GFX7-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]] + ; GFX7-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec + ; GFX7-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]] + ; GFX7-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec + ; GFX7-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]] + ; GFX7-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec + ; GFX7-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]] + ; GFX7-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec + ; GFX7-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]] + ; GFX7-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec + ; GFX7-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]] + ; GFX7-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec + ; GFX7-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]] + ; GFX7-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec + ; GFX7-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v16i32 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3 + ; GFX8-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4 + ; GFX8-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8 + ; GFX8-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9 + ; GFX8-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10 + ; GFX8-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11 + ; GFX8-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12 + ; GFX8-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13 + ; GFX8-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14 + ; GFX8-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15 + ; GFX8-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec + ; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX8-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec + ; GFX8-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX8-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec + ; GFX8-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] + ; GFX8-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec + ; GFX8-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] + ; GFX8-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec + ; GFX8-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] + ; GFX8-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec + ; GFX8-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] + ; GFX8-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec + ; GFX8-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] + ; GFX8-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec + ; GFX8-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]] + ; GFX8-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec + ; GFX8-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]] + ; GFX8-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec + ; GFX8-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]] + ; GFX8-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec + ; GFX8-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]] + ; GFX8-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec + ; GFX8-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]] + ; GFX8-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec + ; GFX8-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]] + ; GFX8-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec + ; GFX8-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]] + ; GFX8-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec + ; GFX8-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v16i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub0 + ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub1 + ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub2 + ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub3 + ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub4 + ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub5 + ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub6 + ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub7 + ; GFX1200_1250-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub8 + ; GFX1200_1250-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub9 + ; GFX1200_1250-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub10 + ; GFX1200_1250-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub11 + ; GFX1200_1250-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub12 + ; GFX1200_1250-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub13 + ; GFX1200_1250-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub14 + ; GFX1200_1250-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub15 + ; GFX1200_1250-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GFX1200_1250-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] + ; GFX1200_1250-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] + ; GFX1200_1250-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] + ; GFX1200_1250-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] + ; GFX1200_1250-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] + ; GFX1200_1250-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] + ; GFX1200_1250-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]] + ; GFX1200_1250-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]] + ; GFX1200_1250-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]] + ; GFX1200_1250-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]] + ; GFX1200_1250-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]] + ; GFX1200_1250-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]] + ; GFX1200_1250-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]] + ; GFX1200_1250-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 + %val = call <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <16 x i32> %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1(ptr addrspace(8) inreg %rsrc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1, i32 0), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_glc_4(ptr addrspace(8) inreg %rsrc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_glc_4 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_glc_4 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_glc_4 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 4, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_glc_4 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 4, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 4, i32 1), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_255(ptr addrspace(8) inreg %rsrc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_255 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 255 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_255 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 255 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_255 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_255 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 255, i32 0), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_256(ptr addrspace(8) inreg %rsrc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_256 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 64, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_256 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 64, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_256 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 256, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_256 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 256, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 256, i32 0), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1020(ptr addrspace(8) inreg %rsrc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1020 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1020 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1020 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1020, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1020 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1020, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1020, i32 0), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1023(ptr addrspace(8) inreg %rsrc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1023 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1023 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1023 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1023, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1023 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1023, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1023, i32 0), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1024(ptr addrspace(8) inreg %rsrc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1024 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1024 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 256, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1024 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1024, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1024 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1024, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1024, i32 0), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1025(ptr addrspace(8) inreg %rsrc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1025 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1025 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1025 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1025 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1025 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1025, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1025 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1025, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1025, i32 0), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg1(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg1 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg1 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg1 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg1 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -1, i32 0), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg4(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg4 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg4 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073741823, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg4 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg4 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -4, i32 0), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg8(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg8 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg8 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073741822, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg8 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg8 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -8, i32 0), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit31(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit31 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit31 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 536870912, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit31 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit31 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -2147483648, i32 0), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_glc_bit30(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_glc_bit30 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 1 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_glc_bit30 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 268435456, 1 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_glc_bit30 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 1 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_glc_bit30 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 1 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 1073741824, i32 1), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit29(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit29 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit29 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 134217728, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit29 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit29 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 536870912, i32 0), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit21(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit21 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2097152 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit21 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 524288, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit21 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2097152 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit21 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 2097152, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 2097152, i32 0), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit20(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit20 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit20 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 262144, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit20 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit20 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1048576, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 1048576, i32 0), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg_bit20(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit20 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit20 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073479680, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit20 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit20 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -1048576, i32 0), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit19(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit19 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 524288 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit19 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 131072, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit19 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 524288, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit19 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 524288, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 524288, i32 0), !invariant.load !0 + ret i32 %load +} + +define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg_bit19(ptr addrspace(8) inreg %desc) { + ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit19 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit19 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073610752, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit19 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit19 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] + ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -524288, i32 0), !invariant.load !0 + ret i32 %load +} + +; Check cases that need to be converted to MUBUF due to the offset being a VGPR. +define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret float %val +} + +define amdgpu_ps <2 x float> @ptr_s_buffer_load_v2f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1 + ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1 + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1 + ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub1 + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub1 + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + %val = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <2 x float> %val +} + +define amdgpu_ps <3 x float> @ptr_s_buffer_load_v3f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 + ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 + ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub0 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub1 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub2 + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96_align2 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub0 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub1 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub2 + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1250-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + %val = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <3 x float> %val +} + +define amdgpu_ps <4 x float> @ptr_s_buffer_load_v4f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 + ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 + ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub0 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub1 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub2 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub3 + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub0 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub1 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub2 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub3 + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1250-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1250-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + %val = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <4 x float> %val +} + +define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1250-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1250-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1250-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX1250-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX1250-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX1250-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <8 x float> %val +} + +define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX6-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX6-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX6-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX6-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX6-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX6-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX6-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX6-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX7-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX7-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX7-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX7-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX7-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX7-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX7-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX7-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX8-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX8-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX8-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX8-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX8-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX8-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX8-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX8-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX1200-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX1200-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX1200-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX1200-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX1200-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX1200-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX1200-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX1200-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX1200-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX1200-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX1200-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX1200-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX1200-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX1200-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX1200-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1250-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1250-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1250-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX1250-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX1250-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX1250-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX1250-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX1250-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX1250-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX1250-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX1250-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX1250-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX1250-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX1250-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <16 x float> %val +} + +define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4092 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %soffset = add i32 %soffset.base, 4092 + %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret float %val +} + +define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4095(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %soffset = add i32 %soffset.base, 4095 + %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret float %val +} + +define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200_1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %soffset = add nuw i32 %soffset.base, 4092 + %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret float %val +} + +define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4096(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4096, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %soffset = add i32 %soffset.base, 4096 + %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret float %val +} + +; Make sure the base offset is added to each split load. +define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4064(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4064 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX1250-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX1250-NEXT: $vgpr2 = COPY [[COPY8]] + ; GFX1250-NEXT: $vgpr3 = COPY [[COPY9]] + ; GFX1250-NEXT: $vgpr4 = COPY [[COPY10]] + ; GFX1250-NEXT: $vgpr5 = COPY [[COPY11]] + ; GFX1250-NEXT: $vgpr6 = COPY [[COPY12]] + ; GFX1250-NEXT: $vgpr7 = COPY [[COPY13]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + %soffset = add i32 %soffset.base, 4064 + %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <8 x float> %val +} + +; Make sure the maximum offset isn't exeeded when splitting this +define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4068(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX1250-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX1250-NEXT: $vgpr2 = COPY [[COPY8]] + ; GFX1250-NEXT: $vgpr3 = COPY [[COPY9]] + ; GFX1250-NEXT: $vgpr4 = COPY [[COPY10]] + ; GFX1250-NEXT: $vgpr5 = COPY [[COPY11]] + ; GFX1250-NEXT: $vgpr6 = COPY [[COPY12]] + ; GFX1250-NEXT: $vgpr7 = COPY [[COPY13]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + %soffset = add i32 %soffset.base, 4068 + %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <8 x float> %val +} + +define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4032(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX6-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX6-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX6-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX6-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX6-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX6-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX6-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX6-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX7-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX7-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX7-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX7-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX7-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX7-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX7-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX7-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX8-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX8-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX8-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX8-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX8-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX8-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX8-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX8-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4048, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX1200-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX1200-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX1200-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX1200-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX1200-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX1200-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX1200-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX1200-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX1200-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX1200-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX1200-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX1200-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX1200-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX1200-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX1200-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4032 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX1250-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX1250-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX1250-NEXT: $vgpr2 = COPY [[COPY8]] + ; GFX1250-NEXT: $vgpr3 = COPY [[COPY9]] + ; GFX1250-NEXT: $vgpr4 = COPY [[COPY10]] + ; GFX1250-NEXT: $vgpr5 = COPY [[COPY11]] + ; GFX1250-NEXT: $vgpr6 = COPY [[COPY12]] + ; GFX1250-NEXT: $vgpr7 = COPY [[COPY13]] + ; GFX1250-NEXT: $vgpr8 = COPY [[COPY14]] + ; GFX1250-NEXT: $vgpr9 = COPY [[COPY15]] + ; GFX1250-NEXT: $vgpr10 = COPY [[COPY16]] + ; GFX1250-NEXT: $vgpr11 = COPY [[COPY17]] + ; GFX1250-NEXT: $vgpr12 = COPY [[COPY18]] + ; GFX1250-NEXT: $vgpr13 = COPY [[COPY19]] + ; GFX1250-NEXT: $vgpr14 = COPY [[COPY20]] + ; GFX1250-NEXT: $vgpr15 = COPY [[COPY21]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + %soffset = add i32 %soffset.base, 4032 + %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <16 x float> %val +} + +define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4036(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX6-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 + ; GFX6: bb.1 (%ir-block.0): + ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX6-NEXT: {{ $}} + ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4052, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX6-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX6-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX6-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX6-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX6-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX6-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX6-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX6-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4052, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX7-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX7-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX7-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX7-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX7-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX7-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX7-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX7-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX8-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 + ; GFX8: bb.1 (%ir-block.0): + ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4052, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX8-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX8-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX8-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX8-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX8-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX8-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX8-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX8-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4052, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX1200-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX1200-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX1200-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX1200-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX1200-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX1200-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX1200-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] + ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] + ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] + ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] + ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] + ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] + ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] + ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] + ; GFX1200-NEXT: $vgpr8 = COPY [[COPY13]] + ; GFX1200-NEXT: $vgpr9 = COPY [[COPY14]] + ; GFX1200-NEXT: $vgpr10 = COPY [[COPY15]] + ; GFX1200-NEXT: $vgpr11 = COPY [[COPY16]] + ; GFX1200-NEXT: $vgpr12 = COPY [[COPY17]] + ; GFX1200-NEXT: $vgpr13 = COPY [[COPY18]] + ; GFX1200-NEXT: $vgpr14 = COPY [[COPY19]] + ; GFX1200-NEXT: $vgpr15 = COPY [[COPY20]] + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 + ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 + ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 + ; GFX1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 + ; GFX1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 + ; GFX1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 + ; GFX1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 + ; GFX1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 + ; GFX1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 + ; GFX1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 + ; GFX1250-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX1250-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX1250-NEXT: $vgpr2 = COPY [[COPY8]] + ; GFX1250-NEXT: $vgpr3 = COPY [[COPY9]] + ; GFX1250-NEXT: $vgpr4 = COPY [[COPY10]] + ; GFX1250-NEXT: $vgpr5 = COPY [[COPY11]] + ; GFX1250-NEXT: $vgpr6 = COPY [[COPY12]] + ; GFX1250-NEXT: $vgpr7 = COPY [[COPY13]] + ; GFX1250-NEXT: $vgpr8 = COPY [[COPY14]] + ; GFX1250-NEXT: $vgpr9 = COPY [[COPY15]] + ; GFX1250-NEXT: $vgpr10 = COPY [[COPY16]] + ; GFX1250-NEXT: $vgpr11 = COPY [[COPY17]] + ; GFX1250-NEXT: $vgpr12 = COPY [[COPY18]] + ; GFX1250-NEXT: $vgpr13 = COPY [[COPY19]] + ; GFX1250-NEXT: $vgpr14 = COPY [[COPY20]] + ; GFX1250-NEXT: $vgpr15 = COPY [[COPY21]] + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + %soffset = add i32 %soffset.base, 4036 + %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <16 x float> %val +} + +; Waterfall loop due to resource being VGPR + +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) +declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8), i32, i32 immarg) +declare <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8), i32, i32 immarg) +declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8), i32, i32 immarg) +declare <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8), i32, i32 immarg) +declare <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8), i32, i32 immarg) + +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32 immarg) +declare <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8), i32, i32 immarg) +declare <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8), i32, i32 immarg) +declare <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8), i32, i32 immarg) +declare <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8), i32, i32 immarg) +declare <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8), i32, i32 immarg) + +declare i256 @llvm.amdgcn.ptr.s.buffer.load.i256(ptr addrspace(8), i32, i32 immarg) +declare i512 @llvm.amdgcn.ptr.s.buffer.load.i512(ptr addrspace(8), i32, i32 immarg) + +declare <16 x i16> @llvm.amdgcn.ptr.s.buffer.load.v16i16(ptr addrspace(8), i32, i32 immarg) +declare <32 x i16> @llvm.amdgcn.ptr.s.buffer.load.v32i16(ptr addrspace(8), i32, i32 immarg) + +declare <4 x i64> @llvm.amdgcn.ptr.s.buffer.load.v4i64(ptr addrspace(8), i32, i32 immarg) +declare <8 x i64> @llvm.amdgcn.ptr.s.buffer.load.v8i64(ptr addrspace(8), i32, i32 immarg) + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll index 4f897c5b39470..90322b71533ca 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll @@ -81,7 +81,7 @@ define amdgpu_kernel void @set_inactive_imm_poison_64(ptr addrspace(1) %out) { ret void } -define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, <4 x i32> inreg %desc) { +define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, ptr addrspace(8) inreg %desc) { ; GCN-LABEL: set_inactive_scc: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 @@ -114,7 +114,7 @@ define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, <4 x ; GCN-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; GCN-NEXT: .LBB4_4: ; %.exit ; GCN-NEXT: s_endpgm - %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0) + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 0, i32 0), !invariant.load !{} %cmp = icmp eq i32 %val, 56 %tmp.0 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0 %tmp = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp.0) @@ -491,7 +491,7 @@ declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0 declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64) #0 declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #1 declare i64 @llvm.amdgcn.strict.wwm.i64(i64) #1 -declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32) +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32) attributes #0 = { convergent readnone } attributes #1 = { convergent nounwind readnone speculatable willreturn } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.ll new file mode 100644 index 0000000000000..dbe4274c39a42 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.ll @@ -0,0 +1,385 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -o - %s | FileCheck %s -check-prefix=GFX10 +; RUN: llc -global-isel -mtriple=amdgpu12.00-amd-amdhsa -o - %s | FileCheck %s -check-prefix=GFX12 +; ---------------------------------------------------------------------------- +; Case 1: Uniform result — SGPR rsrc + SGPR offset +; ---------------------------------------------------------------------------- + +; Case 1a: i32, SGPR rsrc, SGPR offset +define amdgpu_ps void @ptr_s_buffer_load_i32_sgpr_rsrc_sgpr_offset(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_i32_sgpr_rsrc_sgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: s_buffer_load_dword s0, s[0:3], s6 offset:0x0 +; GFX10-NEXT: s_mov_b32 s4, s7 +; GFX10-NEXT: s_mov_b32 s5, s8 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: global_store_dword v1, v0, s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_i32_sgpr_rsrc_sgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_buffer_load_b32 s0, s[0:3], s4 offset:0x0 +; GFX12-NEXT: s_mov_b32 s8, s5 +; GFX12-NEXT: s_mov_b32 s9, s6 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0 +; GFX12-NEXT: global_store_b32 v1, v0, s[8:9] +; GFX12-NEXT: s_endpgm + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + store i32 %val, ptr addrspace(1) %out + ret void +} + +; Case 1b: v2i32, SGPR rsrc, SGPR offset +define amdgpu_ps void @ptr_s_buffer_load_v2i32_sgpr_rsrc_sgpr_offset(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_v2i32_sgpr_rsrc_sgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: s_buffer_load_dwordx2 s[0:1], s[0:3], s6 offset:0x0 +; GFX10-NEXT: s_mov_b32 s4, s7 +; GFX10-NEXT: s_mov_b32 s5, s8 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_v2i32_sgpr_rsrc_sgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_buffer_load_b64 s[0:1], s[0:3], s4 offset:0x0 +; GFX12-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-NEXT: s_mov_b32 s8, s5 +; GFX12-NEXT: s_mov_b32 s9, s6 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[8:9] +; GFX12-NEXT: s_endpgm + %val = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + store <2 x i32> %val, ptr addrspace(1) %out + ret void +} + + +; Case 1d: <4 x i32> (128-bit), SGPR rsrc, SGPR offset +define amdgpu_ps void @ptr_s_buffer_load_v4i32_sgpr_rsrc_sgpr_offset(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_v4i32_sgpr_rsrc_sgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_mov_b32_e32 v4, 0 +; GFX10-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], s6 offset:0x0 +; GFX10-NEXT: s_mov_b32 s4, s7 +; GFX10-NEXT: s_mov_b32 s5, s8 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_v4i32_sgpr_rsrc_sgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_buffer_load_b128 s[0:3], s[0:3], s4 offset:0x0 +; GFX12-NEXT: v_mov_b32_e32 v4, 0 +; GFX12-NEXT: s_mov_b32 s8, s5 +; GFX12-NEXT: s_mov_b32 s9, s6 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: global_store_b128 v4, v[0:3], s[8:9] +; GFX12-NEXT: s_endpgm + %val = call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + store <4 x i32> %val, ptr addrspace(1) %out + ret void +} + +; Case 1e: <8 x i32> (256-bit), SGPR rsrc, SGPR offset +define amdgpu_ps void @ptr_s_buffer_load_v8i32_sgpr_rsrc_sgpr_offset(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_v8i32_sgpr_rsrc_sgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s10, s7 +; GFX10-NEXT: s_buffer_load_dwordx8 s[0:7], s[0:3], s6 offset:0x0 +; GFX10-NEXT: v_mov_b32_e32 v8, 0 +; GFX10-NEXT: s_mov_b32 s11, s8 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-NEXT: v_mov_b32_e32 v6, s6 +; GFX10-NEXT: v_mov_b32_e32 v7, s7 +; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[10:11] +; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[10:11] offset:16 +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_v8i32_sgpr_rsrc_sgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mov_b32 s8, s5 +; GFX12-NEXT: s_mov_b32 s9, s6 +; GFX12-NEXT: s_buffer_load_b256 s[0:7], s[0:3], s4 offset:0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s1 +; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5 +; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7 +; GFX12-NEXT: v_mov_b32_e32 v6, s6 +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: global_store_b128 v8, v[0:3], s[8:9] +; GFX12-NEXT: global_store_b128 v8, v[4:7], s[8:9] offset:16 +; GFX12-NEXT: s_endpgm + %val = call <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + store <8 x i32> %val, ptr addrspace(1) %out + ret void +} + +; Case 1f: <16 x i32> (512-bit), SGPR rsrc, SGPR offset +define amdgpu_ps void @ptr_s_buffer_load_v16i32_sgpr_rsrc_sgpr_offset(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_v16i32_sgpr_rsrc_sgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s16, s7 +; GFX10-NEXT: s_mov_b32 s17, s8 +; GFX10-NEXT: s_buffer_load_dwordx16 s[0:15], s[0:3], s6 offset:0x0 +; GFX10-NEXT: v_mov_b32_e32 v16, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-NEXT: v_mov_b32_e32 v6, s6 +; GFX10-NEXT: v_mov_b32_e32 v7, s7 +; GFX10-NEXT: v_mov_b32_e32 v8, s8 +; GFX10-NEXT: v_mov_b32_e32 v9, s9 +; GFX10-NEXT: v_mov_b32_e32 v10, s10 +; GFX10-NEXT: v_mov_b32_e32 v11, s11 +; GFX10-NEXT: v_mov_b32_e32 v12, s12 +; GFX10-NEXT: v_mov_b32_e32 v13, s13 +; GFX10-NEXT: v_mov_b32_e32 v14, s14 +; GFX10-NEXT: v_mov_b32_e32 v15, s15 +; GFX10-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17] +; GFX10-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16 +; GFX10-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32 +; GFX10-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48 +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_v16i32_sgpr_rsrc_sgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mov_b32 s16, s5 +; GFX12-NEXT: s_mov_b32 s17, s6 +; GFX12-NEXT: s_buffer_load_b512 s[0:15], s[0:3], s4 offset:0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s1 +; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5 +; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7 +; GFX12-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9 +; GFX12-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s11 +; GFX12-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v13, s13 +; GFX12-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v15, s15 +; GFX12-NEXT: v_mov_b32_e32 v14, s14 +; GFX12-NEXT: s_clause 0x3 +; GFX12-NEXT: global_store_b128 v16, v[0:3], s[16:17] +; GFX12-NEXT: global_store_b128 v16, v[4:7], s[16:17] offset:16 +; GFX12-NEXT: global_store_b128 v16, v[8:11], s[16:17] offset:32 +; GFX12-NEXT: global_store_b128 v16, v[12:15], s[16:17] offset:48 +; GFX12-NEXT: s_endpgm + %val = call <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + store <16 x i32> %val, ptr addrspace(1) %out + ret void +} + +; ---------------------------------------------------------------------------- +; Case 2: Divergent offset, SGPR rsrc +; ---------------------------------------------------------------------------- + +; Case 2a: i32, SGPR rsrc, VGPR offset +define amdgpu_ps void @ptr_s_buffer_load_i32_sgpr_rsrc_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_i32_sgpr_rsrc_vgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_store_dword v1, v0, s[6:7] +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_i32_sgpr_rsrc_vgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen +; GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_store_b32 v1, v0, s[4:5] +; GFX12-NEXT: s_endpgm + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i32 %val, ptr addrspace(1) %out + ret void +} + +; Case 2b: v2i32, SGPR rsrc, VGPR offset +define amdgpu_ps void @ptr_s_buffer_load_v2i32_sgpr_rsrc_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_v2i32_sgpr_rsrc_vgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: buffer_load_dwordx2 v[0:1], v0, s[0:3], 0 offen +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_v2i32_sgpr_rsrc_vgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], null offen +; GFX12-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[4:5] +; GFX12-NEXT: s_endpgm + %val = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store <2 x i32> %val, ptr addrspace(1) %out + ret void +} + + +; Case 2d: <4 x i32> (128-bit), SGPR rsrc, VGPR offset +define amdgpu_ps void @ptr_s_buffer_load_v4i32_sgpr_rsrc_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_v4i32_sgpr_rsrc_vgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_mov_b32_e32 v4, 0 +; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_v4i32_sgpr_rsrc_vgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], null offen +; GFX12-NEXT: v_mov_b32_e32 v4, 0 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_store_b128 v4, v[0:3], s[4:5] +; GFX12-NEXT: s_endpgm + %val = call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store <4 x i32> %val, ptr addrspace(1) %out + ret void +} + +; Case 2e: <8 x i32> (256-bit), SGPR rsrc, VGPR offset +define amdgpu_ps void @ptr_s_buffer_load_v8i32_sgpr_rsrc_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_v8i32_sgpr_rsrc_vgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen +; GFX10-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen offset:16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: global_store_dwordx4 v0, v[1:4], s[6:7] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_store_dwordx4 v0, v[5:8], s[6:7] offset:16 +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_v8i32_sgpr_rsrc_vgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: buffer_load_b128 v[1:4], v0, s[0:3], null offen +; GFX12-NEXT: buffer_load_b128 v[5:8], v0, s[0:3], null offen offset:16 +; GFX12-NEXT: v_mov_b32_e32 v0, 0 +; GFX12-NEXT: s_wait_loadcnt 0x1 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[4:5] +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_store_b128 v0, v[5:8], s[4:5] offset:16 +; GFX12-NEXT: s_endpgm + %val = call <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store <8 x i32> %val, ptr addrspace(1) %out + ret void +} + +; Case 2f: <16 x i32> (512-bit), SGPR rsrc, VGPR offset +define amdgpu_ps void @ptr_s_buffer_load_v16i32_sgpr_rsrc_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ptr_s_buffer_load_v16i32_sgpr_rsrc_vgpr_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_clause 0x3 +; GFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen +; GFX10-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen offset:16 +; GFX10-NEXT: buffer_load_dwordx4 v[9:12], v0, s[0:3], 0 offen offset:32 +; GFX10-NEXT: buffer_load_dwordx4 v[13:16], v0, s[0:3], 0 offen offset:48 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_waitcnt vmcnt(3) +; GFX10-NEXT: global_store_dwordx4 v0, v[1:4], s[6:7] +; GFX10-NEXT: s_waitcnt vmcnt(2) +; GFX10-NEXT: global_store_dwordx4 v0, v[5:8], s[6:7] offset:16 +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: global_store_dwordx4 v0, v[9:12], s[6:7] offset:32 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_store_dwordx4 v0, v[13:16], s[6:7] offset:48 +; GFX10-NEXT: s_endpgm +; +; GFX12-LABEL: ptr_s_buffer_load_v16i32_sgpr_rsrc_vgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_clause 0x3 +; GFX12-NEXT: buffer_load_b128 v[1:4], v0, s[0:3], null offen +; GFX12-NEXT: buffer_load_b128 v[5:8], v0, s[0:3], null offen offset:16 +; GFX12-NEXT: buffer_load_b128 v[9:12], v0, s[0:3], null offen offset:32 +; GFX12-NEXT: buffer_load_b128 v[13:16], v0, s[0:3], null offen offset:48 +; GFX12-NEXT: v_mov_b32_e32 v0, 0 +; GFX12-NEXT: s_wait_loadcnt 0x3 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[4:5] +; GFX12-NEXT: s_wait_loadcnt 0x2 +; GFX12-NEXT: global_store_b128 v0, v[5:8], s[4:5] offset:16 +; GFX12-NEXT: s_wait_loadcnt 0x1 +; GFX12-NEXT: global_store_b128 v0, v[9:12], s[4:5] offset:32 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_store_b128 v0, v[13:16], s[4:5] offset:48 +; GFX12-NEXT: s_endpgm + %val = call <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store <16 x i32> %val, ptr addrspace(1) %out + ret void +} + + +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) +declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8), i32, i32 immarg) +declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8), i32, i32 immarg) +declare <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8), i32, i32 immarg) +declare <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8), i32, i32 immarg) + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.subdword.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.subdword.ll new file mode 100644 index 0000000000000..e3f267238dd95 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.subdword.ll @@ -0,0 +1,139 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -global-isel -mtriple=amdgpu12.00-amd-amdhsa -o - %s | FileCheck %s -check-prefix=GFX12 +; ---------------------------------------------------------------------------- +; Case 1: Sub-dword, uniform — SGPR rsrc + SGPR offset +; ---------------------------------------------------------------------------- + +; Case 1a: i8 signed, SGPR rsrc, SGPR offset +define amdgpu_ps void @ptr_s_buffer_load_i8_sgpr_rsrc_sgpr_offset(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset, ptr addrspace(1) inreg %out) { +; GFX12-LABEL: ptr_s_buffer_load_i8_sgpr_rsrc_sgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_buffer_load_u8 s0, s[0:3], s4 offset:0x0 +; GFX12-NEXT: s_mov_b32 s8, s5 +; GFX12-NEXT: s_mov_b32 s9, s6 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0 +; GFX12-NEXT: global_store_b8 v1, v0, s[8:9] +; GFX12-NEXT: s_endpgm + %val = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + store i8 %val, ptr addrspace(1) %out + ret void +} + +; Case 1b: i8 unsigned, SGPR rsrc, SGPR offset +define amdgpu_ps void @ptr_s_buffer_load_u8_sgpr_rsrc_sgpr_offset(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset, ptr addrspace(1) inreg %out) { +; GFX12-LABEL: ptr_s_buffer_load_u8_sgpr_rsrc_sgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_buffer_load_u8 s0, s[0:3], s4 offset:0x0 +; GFX12-NEXT: s_mov_b32 s8, s5 +; GFX12-NEXT: s_mov_b32 s9, s6 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0 +; GFX12-NEXT: global_store_b8 v1, v0, s[8:9] +; GFX12-NEXT: s_endpgm + %val = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + store i8 %val, ptr addrspace(1) %out + ret void +} + +; Case 1c: i16 signed, SGPR rsrc, SGPR offset +define amdgpu_ps void @ptr_s_buffer_load_i16_sgpr_rsrc_sgpr_offset(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset, ptr addrspace(1) inreg %out) { +; GFX12-LABEL: ptr_s_buffer_load_i16_sgpr_rsrc_sgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x0 +; GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GFX12-NEXT: s_mov_b32 s8, s5 +; GFX12-NEXT: s_mov_b32 s9, s6 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mov_b16_e32 v0.l, s0 +; GFX12-NEXT: global_store_b16 v1, v0, s[8:9] +; GFX12-NEXT: s_endpgm + %val = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + store i16 %val, ptr addrspace(1) %out + ret void +} + +; Case 1d: i16 unsigned, SGPR rsrc, SGPR offset +define amdgpu_ps void @ptr_s_buffer_load_u16_sgpr_rsrc_sgpr_offset(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset, ptr addrspace(1) inreg %out) { +; GFX12-LABEL: ptr_s_buffer_load_u16_sgpr_rsrc_sgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x0 +; GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GFX12-NEXT: s_mov_b32 s8, s5 +; GFX12-NEXT: s_mov_b32 s9, s6 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mov_b16_e32 v0.l, s0 +; GFX12-NEXT: global_store_b16 v1, v0, s[8:9] +; GFX12-NEXT: s_endpgm + %val = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + store i16 %val, ptr addrspace(1) %out + ret void +} + +; ---------------------------------------------------------------------------- +; Case 2: Sub-dword, divergent offset, SGPR rsrc +; ---------------------------------------------------------------------------- + +; Case 2a: i8 signed, SGPR rsrc, VGPR offset +define amdgpu_ps void @ptr_s_buffer_load_i8_sgpr_rsrc_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset, ptr addrspace(1) inreg %out) { +; GFX12-LABEL: ptr_s_buffer_load_i8_sgpr_rsrc_vgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: buffer_load_u8 v0, v0, s[0:3], null offen +; GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_store_b8 v1, v0, s[4:5] +; GFX12-NEXT: s_endpgm + %val = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i8 %val, ptr addrspace(1) %out + ret void +} + +; Case 2b: i8 unsigned, SGPR rsrc, VGPR offset +define amdgpu_ps void @ptr_s_buffer_load_u8_sgpr_rsrc_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset, ptr addrspace(1) inreg %out) { +; GFX12-LABEL: ptr_s_buffer_load_u8_sgpr_rsrc_vgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: buffer_load_u8 v0, v0, s[0:3], null offen +; GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_store_b8 v1, v0, s[4:5] +; GFX12-NEXT: s_endpgm + %val = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i8 %val, ptr addrspace(1) %out + ret void +} + +; Case 2c: i16 signed, SGPR rsrc, VGPR offset +define amdgpu_ps void @ptr_s_buffer_load_i16_sgpr_rsrc_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset, ptr addrspace(1) inreg %out) { +; GFX12-LABEL: ptr_s_buffer_load_i16_sgpr_rsrc_vgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: buffer_load_u16 v0, v0, s[0:3], null offen +; GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_store_b16 v1, v0, s[4:5] +; GFX12-NEXT: s_endpgm + %val = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i16 %val, ptr addrspace(1) %out + ret void +} + +; Case 2d: i16 unsigned, SGPR rsrc, VGPR offset +define amdgpu_ps void @ptr_s_buffer_load_u16_sgpr_rsrc_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset, ptr addrspace(1) inreg %out) { +; GFX12-LABEL: ptr_s_buffer_load_u16_sgpr_rsrc_vgpr_offset: +; GFX12: ; %bb.0: +; GFX12-NEXT: buffer_load_u16 v0, v0, s[0:3], null offen +; GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_store_b16 v1, v0, s[4:5] +; GFX12-NEXT: s_endpgm + %val = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i16 %val, ptr addrspace(1) %out + ret void +} + + +declare i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8), i32, i32) +declare i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8), i32, i32) +declare i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8), i32, i32) +declare i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8), i32, i32) + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll new file mode 100644 index 0000000000000..a3aa9d324b07e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll @@ -0,0 +1,1292 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefix=GFX7 +; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200 +; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250 + +; Natural mapping +define amdgpu_ps i32 @ptr_s_buffer_load_i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(i32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[AMDGPU_S_BUFFER_LOAD]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX7-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(i32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[AMDGPU_S_BUFFER_LOAD]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret i32 %val +} + +define amdgpu_ps <2 x i32> @ptr_s_buffer_load_v2i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v2i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x i32>) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX7-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32) + ; GFX7-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v2i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x i32>) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32) + ; GFX1200_1250-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 + %val = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <2 x i32> %val +} + +define amdgpu_ps <3 x i32> @ptr_s_buffer_load_v3i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v3i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<4 x i32>) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX7-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32) + ; GFX7-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32) + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32) + ; GFX7-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v3i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<3 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<3 x i32>) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32) + ; GFX1200_1250-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32) + ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32) + ; GFX1200_1250-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 + %val = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <3 x i32> %val +} + +define amdgpu_ps <8 x i32> @ptr_s_buffer_load_v8i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v8i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x i32>) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX7-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32) + ; GFX7-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32) + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32) + ; GFX7-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32) + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[UV3]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](i32) + ; GFX7-NEXT: $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](i32) + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[UV4]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](i32) + ; GFX7-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT4]](i32) + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[UV5]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](i32) + ; GFX7-NEXT: $sgpr5 = COPY [[INTRINSIC_CONVERGENT5]](i32) + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr(i32) = COPY [[UV6]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT6:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](i32) + ; GFX7-NEXT: $sgpr6 = COPY [[INTRINSIC_CONVERGENT6]](i32) + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr(i32) = COPY [[UV7]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT7:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](i32) + ; GFX7-NEXT: $sgpr7 = COPY [[INTRINSIC_CONVERGENT7]](i32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v8i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x i32>) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32) + ; GFX1200_1250-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32) + ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32) + ; GFX1200_1250-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32) + ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[UV3]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](i32) + ; GFX1200_1250-NEXT: $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](i32) + ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[UV4]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](i32) + ; GFX1200_1250-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT4]](i32) + ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[UV5]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](i32) + ; GFX1200_1250-NEXT: $sgpr5 = COPY [[INTRINSIC_CONVERGENT5]](i32) + ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:vgpr(i32) = COPY [[UV6]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT6:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](i32) + ; GFX1200_1250-NEXT: $sgpr6 = COPY [[INTRINSIC_CONVERGENT6]](i32) + ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:vgpr(i32) = COPY [[UV7]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT7:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](i32) + ; GFX1200_1250-NEXT: $sgpr7 = COPY [[INTRINSIC_CONVERGENT7]](i32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 + %val = call <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <8 x i32> %val +} + +define amdgpu_ps <16 x i32> @ptr_s_buffer_load_v16i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v16i32 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32), [[UV8:%[0-9]+]]:sgpr(i32), [[UV9:%[0-9]+]]:sgpr(i32), [[UV10:%[0-9]+]]:sgpr(i32), [[UV11:%[0-9]+]]:sgpr(i32), [[UV12:%[0-9]+]]:sgpr(i32), [[UV13:%[0-9]+]]:sgpr(i32), [[UV14:%[0-9]+]]:sgpr(i32), [[UV15:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x i32>) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX7-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32) + ; GFX7-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32) + ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32) + ; GFX7-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32) + ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[UV3]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](i32) + ; GFX7-NEXT: $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](i32) + ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[UV4]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](i32) + ; GFX7-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT4]](i32) + ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[UV5]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](i32) + ; GFX7-NEXT: $sgpr5 = COPY [[INTRINSIC_CONVERGENT5]](i32) + ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr(i32) = COPY [[UV6]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT6:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](i32) + ; GFX7-NEXT: $sgpr6 = COPY [[INTRINSIC_CONVERGENT6]](i32) + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr(i32) = COPY [[UV7]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT7:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](i32) + ; GFX7-NEXT: $sgpr7 = COPY [[INTRINSIC_CONVERGENT7]](i32) + ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr(i32) = COPY [[UV8]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT8:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY13]](i32) + ; GFX7-NEXT: $sgpr8 = COPY [[INTRINSIC_CONVERGENT8]](i32) + ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr(i32) = COPY [[UV9]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT9:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32) + ; GFX7-NEXT: $sgpr9 = COPY [[INTRINSIC_CONVERGENT9]](i32) + ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr(i32) = COPY [[UV10]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT10:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32) + ; GFX7-NEXT: $sgpr10 = COPY [[INTRINSIC_CONVERGENT10]](i32) + ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr(i32) = COPY [[UV11]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT11:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY16]](i32) + ; GFX7-NEXT: $sgpr11 = COPY [[INTRINSIC_CONVERGENT11]](i32) + ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr(i32) = COPY [[UV12]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT12:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY17]](i32) + ; GFX7-NEXT: $sgpr12 = COPY [[INTRINSIC_CONVERGENT12]](i32) + ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr(i32) = COPY [[UV13]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT13:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY18]](i32) + ; GFX7-NEXT: $sgpr13 = COPY [[INTRINSIC_CONVERGENT13]](i32) + ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr(i32) = COPY [[UV14]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT14:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY19]](i32) + ; GFX7-NEXT: $sgpr14 = COPY [[INTRINSIC_CONVERGENT14]](i32) + ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr(i32) = COPY [[UV15]](i32) + ; GFX7-NEXT: [[INTRINSIC_CONVERGENT15:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY20]](i32) + ; GFX7-NEXT: $sgpr15 = COPY [[INTRINSIC_CONVERGENT15]](i32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v16i32 + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32), [[UV8:%[0-9]+]]:sgpr(i32), [[UV9:%[0-9]+]]:sgpr(i32), [[UV10:%[0-9]+]]:sgpr(i32), [[UV11:%[0-9]+]]:sgpr(i32), [[UV12:%[0-9]+]]:sgpr(i32), [[UV13:%[0-9]+]]:sgpr(i32), [[UV14:%[0-9]+]]:sgpr(i32), [[UV15:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x i32>) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) + ; GFX1200_1250-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32) + ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32) + ; GFX1200_1250-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32) + ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32) + ; GFX1200_1250-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32) + ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[UV3]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](i32) + ; GFX1200_1250-NEXT: $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](i32) + ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[UV4]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](i32) + ; GFX1200_1250-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT4]](i32) + ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[UV5]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](i32) + ; GFX1200_1250-NEXT: $sgpr5 = COPY [[INTRINSIC_CONVERGENT5]](i32) + ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:vgpr(i32) = COPY [[UV6]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT6:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](i32) + ; GFX1200_1250-NEXT: $sgpr6 = COPY [[INTRINSIC_CONVERGENT6]](i32) + ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:vgpr(i32) = COPY [[UV7]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT7:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](i32) + ; GFX1200_1250-NEXT: $sgpr7 = COPY [[INTRINSIC_CONVERGENT7]](i32) + ; GFX1200_1250-NEXT: [[COPY13:%[0-9]+]]:vgpr(i32) = COPY [[UV8]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT8:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY13]](i32) + ; GFX1200_1250-NEXT: $sgpr8 = COPY [[INTRINSIC_CONVERGENT8]](i32) + ; GFX1200_1250-NEXT: [[COPY14:%[0-9]+]]:vgpr(i32) = COPY [[UV9]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT9:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32) + ; GFX1200_1250-NEXT: $sgpr9 = COPY [[INTRINSIC_CONVERGENT9]](i32) + ; GFX1200_1250-NEXT: [[COPY15:%[0-9]+]]:vgpr(i32) = COPY [[UV10]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT10:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32) + ; GFX1200_1250-NEXT: $sgpr10 = COPY [[INTRINSIC_CONVERGENT10]](i32) + ; GFX1200_1250-NEXT: [[COPY16:%[0-9]+]]:vgpr(i32) = COPY [[UV11]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT11:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY16]](i32) + ; GFX1200_1250-NEXT: $sgpr11 = COPY [[INTRINSIC_CONVERGENT11]](i32) + ; GFX1200_1250-NEXT: [[COPY17:%[0-9]+]]:vgpr(i32) = COPY [[UV12]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT12:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY17]](i32) + ; GFX1200_1250-NEXT: $sgpr12 = COPY [[INTRINSIC_CONVERGENT12]](i32) + ; GFX1200_1250-NEXT: [[COPY18:%[0-9]+]]:vgpr(i32) = COPY [[UV13]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT13:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY18]](i32) + ; GFX1200_1250-NEXT: $sgpr13 = COPY [[INTRINSIC_CONVERGENT13]](i32) + ; GFX1200_1250-NEXT: [[COPY19:%[0-9]+]]:vgpr(i32) = COPY [[UV14]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT14:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY19]](i32) + ; GFX1200_1250-NEXT: $sgpr14 = COPY [[INTRINSIC_CONVERGENT14]](i32) + ; GFX1200_1250-NEXT: [[COPY20:%[0-9]+]]:vgpr(i32) = COPY [[UV15]](i32) + ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT15:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY20]](i32) + ; GFX1200_1250-NEXT: $sgpr15 = COPY [[INTRINSIC_CONVERGENT15]](i32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 + %val = call <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <16 x i32> %val +} + +; Check cases that need to be converted to MUBUF due to the offset being a VGPR. +define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX1200_1250-NEXT: $vgpr0 = COPY [[COPY5]](f32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret float %val +} + +define amdgpu_ps <2 x float> @ptr_s_buffer_load_v2f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(<2 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<2 x f32>) + ; GFX7-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<2 x f32>) + ; GFX7-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX7-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(<2 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<2 x f32>) + ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<2 x f32>) + ; GFX1200_1250-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1200_1250-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + %val = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <2 x float> %val +} + +define amdgpu_ps <3 x float> @ptr_s_buffer_load_v3f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(<4 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<4 x f32>) + ; GFX7-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<4 x f32>) + ; GFX7-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX7-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX7-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<3 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(<3 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<3 x f32>) + ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<3 x f32>) + ; GFX1200_1250-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1200_1250-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1200_1250-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + %val = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <3 x float> %val +} + +define amdgpu_ps <4 x float> @ptr_s_buffer_load_v4f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(<4 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<4 x f32>) + ; GFX7-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<4 x f32>) + ; GFX7-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX7-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX7-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX7-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(<4 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<4 x f32>) + ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<4 x f32>) + ; GFX1200_1250-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1200_1250-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1200_1250-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1200_1250-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + %val = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <4 x float> %val +} + +define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>) + ; GFX7-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>) + ; GFX7-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX7-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX7-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX7-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX7-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX7-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX7-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX7-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>) + ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>) + ; GFX1200_1250-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1200_1250-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1200_1250-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1200_1250-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1200_1250-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1200_1250-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1200_1250-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1200_1250-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <8 x float> %val +} + +define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>) + ; GFX7-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>) + ; GFX7-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX7-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX7-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX7-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX7-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX7-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX7-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX7-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX7-NEXT: $vgpr8 = COPY [[UV8]](f32) + ; GFX7-NEXT: $vgpr9 = COPY [[UV9]](f32) + ; GFX7-NEXT: $vgpr10 = COPY [[UV10]](f32) + ; GFX7-NEXT: $vgpr11 = COPY [[UV11]](f32) + ; GFX7-NEXT: $vgpr12 = COPY [[UV12]](f32) + ; GFX7-NEXT: $vgpr13 = COPY [[UV13]](f32) + ; GFX7-NEXT: $vgpr14 = COPY [[UV14]](f32) + ; GFX7-NEXT: $vgpr15 = COPY [[UV15]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset + ; GFX1200_1250: bb.1 (%ir-block.0): + ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: {{ $}} + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1200_1250-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>) + ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>) + ; GFX1200_1250-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1200_1250-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1200_1250-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1200_1250-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1200_1250-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1200_1250-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1200_1250-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1200_1250-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1200_1250-NEXT: $vgpr8 = COPY [[UV8]](f32) + ; GFX1200_1250-NEXT: $vgpr9 = COPY [[UV9]](f32) + ; GFX1200_1250-NEXT: $vgpr10 = COPY [[UV10]](f32) + ; GFX1200_1250-NEXT: $vgpr11 = COPY [[UV11]](f32) + ; GFX1200_1250-NEXT: $vgpr12 = COPY [[UV12]](f32) + ; GFX1200_1250-NEXT: $vgpr13 = COPY [[UV13]](f32) + ; GFX1200_1250-NEXT: $vgpr14 = COPY [[UV14]](f32) + ; GFX1200_1250-NEXT: $vgpr15 = COPY [[UV15]](f32) + ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <16 x float> %val +} + +define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX7-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX7-NEXT: $vgpr0 = COPY [[COPY6]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY6]](f32) + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1250-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]](f32) + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %soffset = add i32 %soffset.base, 4092 + %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret float %val +} + +define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4095(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX7-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX7-NEXT: $vgpr0 = COPY [[COPY6]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY6]](f32) + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1250-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]](f32) + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %soffset = add i32 %soffset.base, 4095 + %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret float %val +} + +define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4096(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX7-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX7-NEXT: $vgpr0 = COPY [[COPY6]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4096, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX1200-NEXT: $vgpr0 = COPY [[COPY6]](f32) + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1250-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32) + ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]](f32) + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %soffset = add i32 %soffset.base, 4096 + %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret float %val +} + +; Make sure the base offset is added to each split load. +define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4064(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX7-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>) + ; GFX7-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>) + ; GFX7-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX7-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX7-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX7-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX7-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX7-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX7-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX7-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>) + ; GFX1200-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>) + ; GFX1200-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1200-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1200-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1200-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1200-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1200-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1200-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1200-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1250-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>) + ; GFX1250-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>) + ; GFX1250-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1250-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1250-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1250-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1250-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1250-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1250-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1250-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + %soffset = add i32 %soffset.base, 4064 + %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <8 x float> %val +} + +; Make sure the maximum offset isn't exeeded when splitting this +define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4068(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX7-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4068, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4084, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>) + ; GFX7-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>) + ; GFX7-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX7-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX7-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX7-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX7-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX7-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX7-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX7-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4068, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4084, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>) + ; GFX1200-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>) + ; GFX1200-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1200-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1200-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1200-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1200-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1200-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1200-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1200-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1250-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>) + ; GFX1250-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>) + ; GFX1250-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1250-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1250-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1250-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1250-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1250-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1250-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1250-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + %soffset = add i32 %soffset.base, 4068 + %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <8 x float> %val +} + +define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4032(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX7-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>) + ; GFX7-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>) + ; GFX7-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX7-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX7-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX7-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX7-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX7-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX7-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX7-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX7-NEXT: $vgpr8 = COPY [[UV8]](f32) + ; GFX7-NEXT: $vgpr9 = COPY [[UV9]](f32) + ; GFX7-NEXT: $vgpr10 = COPY [[UV10]](f32) + ; GFX7-NEXT: $vgpr11 = COPY [[UV11]](f32) + ; GFX7-NEXT: $vgpr12 = COPY [[UV12]](f32) + ; GFX7-NEXT: $vgpr13 = COPY [[UV13]](f32) + ; GFX7-NEXT: $vgpr14 = COPY [[UV14]](f32) + ; GFX7-NEXT: $vgpr15 = COPY [[UV15]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1200-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>) + ; GFX1200-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>) + ; GFX1200-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1200-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1200-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1200-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1200-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1200-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1200-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1200-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1200-NEXT: $vgpr8 = COPY [[UV8]](f32) + ; GFX1200-NEXT: $vgpr9 = COPY [[UV9]](f32) + ; GFX1200-NEXT: $vgpr10 = COPY [[UV10]](f32) + ; GFX1200-NEXT: $vgpr11 = COPY [[UV11]](f32) + ; GFX1200-NEXT: $vgpr12 = COPY [[UV12]](f32) + ; GFX1200-NEXT: $vgpr13 = COPY [[UV13]](f32) + ; GFX1200-NEXT: $vgpr14 = COPY [[UV14]](f32) + ; GFX1200-NEXT: $vgpr15 = COPY [[UV15]](f32) + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1250-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 32, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 48, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1250-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>) + ; GFX1250-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>) + ; GFX1250-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1250-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1250-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1250-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1250-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1250-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1250-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1250-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1250-NEXT: $vgpr8 = COPY [[UV8]](f32) + ; GFX1250-NEXT: $vgpr9 = COPY [[UV9]](f32) + ; GFX1250-NEXT: $vgpr10 = COPY [[UV10]](f32) + ; GFX1250-NEXT: $vgpr11 = COPY [[UV11]](f32) + ; GFX1250-NEXT: $vgpr12 = COPY [[UV12]](f32) + ; GFX1250-NEXT: $vgpr13 = COPY [[UV13]](f32) + ; GFX1250-NEXT: $vgpr14 = COPY [[UV14]](f32) + ; GFX1250-NEXT: $vgpr15 = COPY [[UV15]](f32) + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + %soffset = add i32 %soffset.base, 4032 + %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <16 x float> %val +} + +define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4036(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { + ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 + ; GFX7: bb.1 (%ir-block.0): + ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036 + ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX7-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX7-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4036, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4052, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4068, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX7-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4084, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>) + ; GFX7-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>) + ; GFX7-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX7-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX7-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX7-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX7-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX7-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX7-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX7-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX7-NEXT: $vgpr8 = COPY [[UV8]](f32) + ; GFX7-NEXT: $vgpr9 = COPY [[UV9]](f32) + ; GFX7-NEXT: $vgpr10 = COPY [[UV10]](f32) + ; GFX7-NEXT: $vgpr11 = COPY [[UV11]](f32) + ; GFX7-NEXT: $vgpr12 = COPY [[UV12]](f32) + ; GFX7-NEXT: $vgpr13 = COPY [[UV13]](f32) + ; GFX7-NEXT: $vgpr14 = COPY [[UV14]](f32) + ; GFX7-NEXT: $vgpr15 = COPY [[UV15]](f32) + ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 + ; GFX1200: bb.1 (%ir-block.0): + ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1200-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4036, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4052, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4068, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1200-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[COPY4]], [[C1]], 4084, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1200-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>) + ; GFX1200-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>) + ; GFX1200-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1200-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1200-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1200-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1200-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1200-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1200-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1200-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1200-NEXT: $vgpr8 = COPY [[UV8]](f32) + ; GFX1200-NEXT: $vgpr9 = COPY [[UV9]](f32) + ; GFX1200-NEXT: $vgpr10 = COPY [[UV10]](f32) + ; GFX1200-NEXT: $vgpr11 = COPY [[UV11]](f32) + ; GFX1200-NEXT: $vgpr12 = COPY [[UV12]](f32) + ; GFX1200-NEXT: $vgpr13 = COPY [[UV13]](f32) + ; GFX1200-NEXT: $vgpr14 = COPY [[UV14]](f32) + ; GFX1200-NEXT: $vgpr15 = COPY [[UV15]](f32) + ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; + ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 + ; GFX1250: bb.1 (%ir-block.0): + ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 + ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) + ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]] + ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) + ; GFX1250-NEXT: [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 32, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; GFX1250-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](i32), [[ADD]], [[C1]], 48, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; GFX1250-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>) + ; GFX1250-NEXT: [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>) + ; GFX1250-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX1250-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX1250-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX1250-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX1250-NEXT: $vgpr4 = COPY [[UV4]](f32) + ; GFX1250-NEXT: $vgpr5 = COPY [[UV5]](f32) + ; GFX1250-NEXT: $vgpr6 = COPY [[UV6]](f32) + ; GFX1250-NEXT: $vgpr7 = COPY [[UV7]](f32) + ; GFX1250-NEXT: $vgpr8 = COPY [[UV8]](f32) + ; GFX1250-NEXT: $vgpr9 = COPY [[UV9]](f32) + ; GFX1250-NEXT: $vgpr10 = COPY [[UV10]](f32) + ; GFX1250-NEXT: $vgpr11 = COPY [[UV11]](f32) + ; GFX1250-NEXT: $vgpr12 = COPY [[UV12]](f32) + ; GFX1250-NEXT: $vgpr13 = COPY [[UV13]](f32) + ; GFX1250-NEXT: $vgpr14 = COPY [[UV14]](f32) + ; GFX1250-NEXT: $vgpr15 = COPY [[UV15]](f32) + ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + %soffset = add i32 %soffset.base, 4036 + %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 + ret <16 x float> %val +} + +; Waterfall loop due to resource being VGPR + +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) +declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8), i32, i32 immarg) +declare <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8), i32, i32 immarg) +declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8), i32, i32 immarg) +declare <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8), i32, i32 immarg) +declare <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8), i32, i32 immarg) + +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32 immarg) +declare <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8), i32, i32 immarg) +declare <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8), i32, i32 immarg) +declare <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8), i32, i32 immarg) +declare <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8), i32, i32 immarg) +declare <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8), i32, i32 immarg) + + + + + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir index 94400c71ba93b..b95fb5b72bac3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir @@ -26,7 +26,7 @@ body: | ; FAST-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY3]], [[COPY2]] ; FAST-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; FAST-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; FAST-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[COPY]](<4 x s32>), [[C2]](s32), [[COPY3]], [[C1]], 256, 0, 0 :: (dereferenceable invariant load (s32)) + ; FAST-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[COPY]](<4 x s32>), [[C2]](s32), [[COPY3]], [[C1]], 256, 1, 0 :: (dereferenceable invariant load (s32)) ; FAST-NEXT: S_ENDPGM 0, implicit [[AMDGPU_BUFFER_LOAD]](s32) ; ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_cross_bank_copy_add_offset @@ -39,13 +39,13 @@ body: | ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY2]], [[C]] ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[COPY]](<4 x s32>), [[C2]](s32), [[COPY2]], [[C1]], 256, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[COPY]](<4 x s32>), [[C2]](s32), [[COPY2]], [[C1]], 256, 1, 0 :: (dereferenceable invariant load (s32)) ; GREEDY-NEXT: S_ENDPGM 0, implicit [[AMDGPU_BUFFER_LOAD]](s32) %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 %1:_(s32) = COPY $sgpr0 %2:vgpr(s32) = G_CONSTANT i32 256 %3:_(s32) = G_ADD %1, %2 - %4:_(s32) = G_AMDGPU_S_BUFFER_LOAD %0, %3, 0 + %4:_(s32) = G_AMDGPU_S_BUFFER_LOAD %0, %3, 1 S_ENDPGM 0, implicit %4 ... diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-wwm-single-lane.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-wwm-single-lane.ll index 0b7451756b9fd..e82544b348a17 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-wwm-single-lane.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-wwm-single-lane.ll @@ -8,11 +8,11 @@ define amdgpu_kernel void @kernel(ptr addrspace(4) %input, ptr addrspace(1) %out ; CHECK: call float @llvm.amdgcn.permlane64.f32 .entry: %element_ptr = getelementptr i8, ptr addrspace(4) %input, i64 16 - %buffer = load <4 x i32>, ptr addrspace(4) %element_ptr, align 16 + %buffer = load ptr addrspace(8), ptr addrspace(4) %element_ptr, align 16 %lane_id_lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) %lane_id = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lane_id_lo) %lane_id_idx = shl i32 %lane_id, 2 - %vals = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %buffer, i32 %lane_id_idx, i32 0) + %vals = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %buffer, i32 %lane_id_idx, i32 0), !invariant.load !{} %vals_inactive_zeroed = call i32 @llvm.amdgcn.set.inactive.i32(i32 %vals, i32 0) %float_vals = bitcast i32 %vals_inactive_zeroed to float %swapped_vals = call float @llvm.amdgcn.permlane64.f32(float %float_vals) diff --git a/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll b/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll index 13270435ebddb..e749960c79bc4 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll +++ b/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll @@ -12,7 +12,7 @@ define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 %descTable2) #0 { %i4 = inttoptr i64 %i2 to ptr addrspace(4) %i159 = call reassoc nnan nsz arcp contract afn <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float poison, float poison, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) %i1540 = shufflevector <4 x float> %i159, <4 x float> poison, <3 x i32> - %i1526 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 2688, i32 0) + %i1526 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 2688, i32 0), !invariant.load !{} %i1746 = load <4 x i32>, ptr addrspace(4) %i4, align 16 br label %bb1750 @@ -24,7 +24,7 @@ bb1750: ; preds = %bb1897, %.entry %i1754 = shufflevector <4 x i32> %__llpc_global_proxy_r10.19291, <4 x i32> poison, <4 x i32> %__llpc_global_proxy_r7.12.vec.extract1953260 = bitcast float %i1751 to i32 %i1760 = or i32 %__llpc_global_proxy_r7.12.vec.extract1953260, %__llpc_global_proxy_r3.12.vec.extract2358295 - %i1786 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 %i1760, i32 0) + %i1786 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 %i1760, i32 0), !invariant.load !{} %__llpc_global_proxy_r11.12.vec.insert1237 = insertelement <4 x i32> %i1754, i32 %i1786, i64 3 %.not2783 = icmp eq i32 %i1786, 0 br i1 %.not2783, label %bb1789, label %bb1787 @@ -44,7 +44,7 @@ bb1789: ; preds = %bb1750 %i1878 = shufflevector <4 x i32> %__llpc_global_proxy_r11.12.vec.insert1245, <4 x i32> poison, <3 x i32> %i1879 = bitcast <3 x i32> %i1878 to <3 x float> %i1881 = fmul reassoc nnan nsz arcp contract afn <3 x float> %i1540, %i1879 - %i1882 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 poison, i32 0) + %i1882 = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) poison, i32 poison, i32 0), !invariant.load !{} %i1883 = shufflevector <3 x i32> %i1882, <3 x i32> poison, <4 x i32> %i1884 = bitcast <4 x i32> %i1883 to <4 x float> %i1885 = shufflevector <4 x float> %i1884, <4 x float> poison, <3 x i32> @@ -84,7 +84,7 @@ bb1897: ; preds = %bb1789, %bb1787 declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 immarg, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) declare float @llvm.amdgcn.fmed3.f32(float, float, float) declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32 immarg) -declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) -declare <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32>, i32, i32 immarg) +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) +declare <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8), i32, i32 immarg) attributes #0 = { "target-features"="+wavefrontsize64,+cumode" } diff --git a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll index 8922f4b3de2b2..00c2029018a3c 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll +++ b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll @@ -50,8 +50,8 @@ define amdgpu_vs float @main(i32 %v) { ; GFX8-NEXT: .LBB0_6: ; %IF63 ; GFX8-NEXT: .LBB0_7: main_body: - %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, i32 0) - %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, i32 0) + %d1 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) poison, i32 960, i32 0), !invariant.load !{} + %d2 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) poison, i32 976, i32 0), !invariant.load !{} br i1 poison, label %ENDIF56, label %IF57 IF57: ; preds = %ENDIF @@ -82,7 +82,7 @@ ENDIF62: ; preds = %ENDIF59 ret float %r } -declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #0 +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32) #0 attributes #0 = { nounwind readnone } attributes #1 = { readnone } diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll index 4b713f66f35b9..433e19f1128ef 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll @@ -43,7 +43,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 { ; GFX10-NEXT: v_sub_f32_e32 v8, s0, v1 ; GFX10-NEXT: v_fma_f32 v7, -s2, v6, s6 ; GFX10-NEXT: v_fma_f32 v5, v6, v5, 1.0 -; GFX10-NEXT: v_mad_f32 v10, s2, v6, v2 +; GFX10-NEXT: v_fma_f32 v10, s2, v6, v2 ; GFX10-NEXT: s_mov_b32 s0, 0x3c23d70a ; GFX10-NEXT: v_fmac_f32_e32 v1, v6, v8 ; GFX10-NEXT: v_fmac_f32_e32 v10, v7, v6 @@ -102,16 +102,16 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 { ; GFX11-NEXT: s_buffer_load_b128 s[16:19], s[0:3], 0x0 ; GFX11-NEXT: s_buffer_load_b128 s[20:23], s[0:3], 0x70 ; GFX11-NEXT: v_fma_f32 v1, v1, v5, s28 -; GFX11-NEXT: v_max_f32_e64 v6, s0, s0 clamp ; GFX11-NEXT: s_buffer_load_b128 s[24:27], s[0:3], 0x10 +; GFX11-NEXT: v_max_f32_e64 v6, s0, s0 clamp ; GFX11-NEXT: v_add_f32_e64 v5, s29, -1.0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_sub_f32_e32 v8, s0, v1 +; GFX11-NEXT: s_mov_b32 s0, 0x3c23d70a ; GFX11-NEXT: v_fma_f32 v7, -s2, v6, s6 -; GFX11-NEXT: v_fma_f32 v10, s2, v6, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_fma_f32 v5, v6, v5, 1.0 -; GFX11-NEXT: s_mov_b32 s0, 0x3c23d70a +; GFX11-NEXT: v_fma_f32 v10, s2, v6, v2 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: v_dual_fmac_f32 v10, v7, v6 :: v_dual_mul_f32 v9, s10, v0 ; GFX11-NEXT: v_fma_f32 v0, -v0, s10, s14 @@ -143,7 +143,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 { .entry: %0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) %.i2243 = extractelement <3 x float> %0, i32 2 - %1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 0, i32 0) + %1 = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) poison, i32 0, i32 0), !invariant.load !0 %2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> %3 = bitcast <4 x i32> %2 to <4 x float> %.i2248 = extractelement <4 x float> %3, i32 2 @@ -156,17 +156,17 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 { %.i1408 = extractelement <2 x float> %7, i32 1 %.i0364 = extractelement <2 x float> %7, i32 0 %8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) - %9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 112, i32 0) + %9 = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) poison, i32 112, i32 0), !invariant.load !0 %10 = shufflevector <3 x i32> %9, <3 x i32> poison, <4 x i32> %11 = bitcast <4 x i32> %10 to <4 x float> %.i2360 = extractelement <4 x float> %11, i32 2 %.i2363 = fmul reassoc nnan nsz arcp contract afn float %.i2360, %8 - %12 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 96, i32 0) + %12 = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) poison, i32 96, i32 0), !invariant.load !0 %13 = shufflevector <3 x i32> %12, <3 x i32> poison, <4 x i32> %14 = bitcast <4 x i32> %13 to <4 x float> %.i2367 = extractelement <4 x float> %14, i32 2 %.i2370 = fmul reassoc nnan nsz arcp contract afn float %.i0364, %.i2367 - %15 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 32, i32 0) + %15 = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) poison, i32 32, i32 0), !invariant.load !0 %16 = shufflevector <3 x i32> %15, <3 x i32> poison, <4 x i32> %17 = bitcast <4 x i32> %16 to <4 x float> %.i2373 = extractelement <4 x float> %17, i32 2 @@ -179,19 +179,19 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 { %.i2397 = fmul reassoc nnan nsz arcp contract afn float %.i2363, %18 %.i2404 = fmul reassoc nnan nsz arcp contract afn float %.i2394, %4 %.i2407 = fadd reassoc nnan nsz arcp contract afn float %.i2397, %.i2404 - %20 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 92, i32 0) + %20 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 92, i32 0), !invariant.load !0 %21 = bitcast i32 %20 to float - %22 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 124, i32 0) + %22 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 124, i32 0), !invariant.load !0 %23 = bitcast i32 %22 to float %24 = fsub reassoc nnan nsz arcp contract afn float %21, %23 %25 = fmul reassoc nnan nsz arcp contract afn float %.i1408, %24 %26 = fadd reassoc nnan nsz arcp contract afn float %25, %23 - %27 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 44, i32 0) + %27 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 44, i32 0), !invariant.load !0 %28 = bitcast i32 %27 to float %29 = fsub reassoc nnan nsz arcp contract afn float %28, %26 %30 = fmul reassoc nnan nsz arcp contract afn float %6, %29 %31 = fadd reassoc nnan nsz arcp contract afn float %26, %30 - %32 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 192, i32 0) + %32 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 192, i32 0), !invariant.load !0 %33 = bitcast i32 %32 to float %34 = fadd reassoc nnan nsz arcp contract afn float %33, -1.000000e+00 %35 = fmul reassoc nnan nsz arcp contract afn float %18, %34 @@ -209,12 +209,12 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 { %.i2465 = extractelement <3 x float> %44, i32 2 %.i2466 = fmul reassoc nnan nsz arcp contract afn float %.i2465, %43 %.i2469 = fmul reassoc nnan nsz arcp contract afn float %.i2415, %.i2466 - %45 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 64, i32 0) + %45 = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) poison, i32 64, i32 0), !invariant.load !0 %46 = shufflevector <3 x i32> %45, <3 x i32> poison, <4 x i32> %47 = bitcast <4 x i32> %46 to <4 x float> %.i2476 = extractelement <4 x float> %47, i32 2 %.i2479 = fmul reassoc nnan nsz arcp contract afn float %.i2476, %18 - %48 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 80, i32 0) + %48 = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) poison, i32 80, i32 0), !invariant.load !0 %49 = shufflevector <3 x i32> %48, <3 x i32> poison, <4 x i32> %50 = bitcast <4 x i32> %49 to <4 x float> %.i2482 = extractelement <4 x float> %50, i32 2 @@ -227,7 +227,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 { %.i2516 = fadd reassoc nnan nsz arcp contract afn float %.i2515, %.i2494 %.i2522 = fadd reassoc nnan nsz arcp contract afn float %.i2521, %.i2516 %.i2525 = fmul reassoc nnan nsz arcp contract afn float %.i2522, %43 - %52 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 16, i32 0) + %52 = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) poison, i32 16, i32 0), !invariant.load !0 %53 = shufflevector <3 x i32> %52, <3 x i32> poison, <4 x i32> %54 = bitcast <4 x i32> %53 to <4 x float> %.i2530 = extractelement <4 x float> %54, i32 2 @@ -432,12 +432,14 @@ declare <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 immarg, float, fl declare <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 ; Function Attrs: nounwind readnone willreturn -declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) #3 +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) #3 ; Function Attrs: nounwind readnone willreturn -declare <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32>, i32, i32 immarg) #3 +declare <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8), i32, i32 immarg) #3 attributes #0 = { denormal_fpenv(float: preservesign) } attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } attributes #2 = { nounwind readnone speculatable willreturn } attributes #3 = { nounwind readonly willreturn } + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll index 07c8dc4dd3b37..27cc4c395bc80 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll @@ -1719,7 +1719,7 @@ define amdgpu_kernel void @fnge_select_f32_multi_use_regression(float %.i2369) { br i1 %.i0721, label %bb5, label %bb bb: ; preds = %.entry - %i2 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> zeroinitializer, i32 1, i32 0) + %i2 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) null, i32 1, i32 0), !invariant.load !{} %i3 = shufflevector <2 x i32> %i2, <2 x i32> zeroinitializer, <4 x i32> %i4 = bitcast <4 x i32> %i3 to <4 x float> %.i0753 = extractelement <4 x float> %i4, i64 0 @@ -1730,6 +1730,6 @@ bb5: ; preds = %bb, %.entry } -declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32 immarg) #0 +declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8), i32, i32 immarg) #0 attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) } diff --git a/llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_ptr_s_buffer_loads.ll b/llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_ptr_s_buffer_loads.ll new file mode 100644 index 0000000000000..015e42200f4e2 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_ptr_s_buffer_loads.ll @@ -0,0 +1,528 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,DAG %s +; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -global-isel=1 < %s | FileCheck -check-prefixes=GCN,GISEL %s + +define amdgpu_ps void @ptr_s_buffer_load_byte_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out) { +; DAG-LABEL: ptr_s_buffer_load_byte_imm_offset: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s7, s5 +; DAG-NEXT: s_mov_b32 s6, s4 +; DAG-NEXT: s_mov_b32 s5, s3 +; DAG-NEXT: s_mov_b32 s4, s2 +; DAG-NEXT: s_buffer_load_i8 s0, s[4:7], 0x4 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_byte_imm_offset: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_i8 s0, s[0:3], 0x4 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %src, i32 4, i32 0), !invariant.load !0 + %sext = sext i8 %ld to i32 + store i32 %sext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_byte_sgpr(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) { +; DAG-LABEL: ptr_s_buffer_load_byte_sgpr: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s11, s5 +; DAG-NEXT: s_mov_b32 s10, s4 +; DAG-NEXT: s_mov_b32 s9, s3 +; DAG-NEXT: s_mov_b32 s8, s2 +; DAG-NEXT: s_buffer_load_i8 s0, s[8:11], s6 offset:0x0 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_byte_sgpr: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_i8 s0, s[0:3], s6 offset:0x0 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 + %sext = sext i8 %ld to i32 + store i32 %sext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_byte_sgpr_or_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) { +; DAG-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s11, s5 +; DAG-NEXT: s_mov_b32 s10, s4 +; DAG-NEXT: s_mov_b32 s9, s3 +; DAG-NEXT: s_mov_b32 s8, s2 +; DAG-NEXT: s_buffer_load_i8 s0, s[8:11], s6 offset:0x64 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_i8 s0, s[0:3], s6 offset:0x64 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %off = add nuw nsw i32 %in, 100 + %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %src, i32 %off, i32 0), !invariant.load !0 + %sext = sext i8 %ld to i32 + store i32 %sext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_byte_sgpr_or_imm_offset_divergent(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) { +; DAG-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset_divergent: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s7, s5 +; DAG-NEXT: s_mov_b32 s6, s4 +; DAG-NEXT: s_mov_b32 s5, s3 +; DAG-NEXT: s_mov_b32 s4, s2 +; DAG-NEXT: buffer_load_i8 v2, v2, s[4:7], null offen +; DAG-NEXT: s_wait_loadcnt 0x0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset_divergent: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: buffer_load_i8 v2, v2, s[0:3], null offen +; GISEL-NEXT: s_wait_loadcnt 0x0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 + %sext = sext i8 %ld to i32 + store i32 %sext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_ubyte_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out) { +; DAG-LABEL: ptr_s_buffer_load_ubyte_imm_offset: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s7, s5 +; DAG-NEXT: s_mov_b32 s6, s4 +; DAG-NEXT: s_mov_b32 s5, s3 +; DAG-NEXT: s_mov_b32 s4, s2 +; DAG-NEXT: s_buffer_load_u8 s0, s[4:7], 0x4 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: s_and_b32 s0, s0, 0xff +; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_ubyte_imm_offset: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_u8 s0, s[0:3], 0x4 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: s_and_b32 s0, s0, 0xff +; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %src, i32 4, i32 0), !invariant.load !0 + %zext = zext i8 %ld to i32 + store i32 %zext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_ubyte_sgpr(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) { +; DAG-LABEL: ptr_s_buffer_load_ubyte_sgpr: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s11, s5 +; DAG-NEXT: s_mov_b32 s10, s4 +; DAG-NEXT: s_mov_b32 s9, s3 +; DAG-NEXT: s_mov_b32 s8, s2 +; DAG-NEXT: s_buffer_load_u8 s0, s[8:11], s6 offset:0x0 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: s_and_b32 s0, s0, 0xff +; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_ubyte_sgpr: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_u8 s0, s[0:3], s6 offset:0x0 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: s_and_b32 s0, s0, 0xff +; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 + %zext = zext i8 %ld to i32 + store i32 %zext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_ubyte_sgpr_or_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) { +; DAG-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s11, s5 +; DAG-NEXT: s_mov_b32 s10, s4 +; DAG-NEXT: s_mov_b32 s9, s3 +; DAG-NEXT: s_mov_b32 s8, s2 +; DAG-NEXT: s_buffer_load_u8 s0, s[8:11], s6 offset:0x64 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: s_and_b32 s0, s0, 0xff +; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_u8 s0, s[0:3], s6 offset:0x64 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: s_and_b32 s0, s0, 0xff +; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %off = add nuw nsw i32 %in, 100 + %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %src, i32 %off, i32 0), !invariant.load !0 + %zext = zext i8 %ld to i32 + store i32 %zext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_ubyte_sgpr_or_imm_offset_divergent(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) { +; DAG-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset_divergent: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s7, s5 +; DAG-NEXT: s_mov_b32 s6, s4 +; DAG-NEXT: s_mov_b32 s5, s3 +; DAG-NEXT: s_mov_b32 s4, s2 +; DAG-NEXT: buffer_load_u8 v2, v2, s[4:7], null offen +; DAG-NEXT: s_wait_loadcnt 0x0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset_divergent: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: buffer_load_u8 v2, v2, s[0:3], null offen +; GISEL-NEXT: s_wait_loadcnt 0x0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 + %zext = zext i8 %ld to i32 + store i32 %zext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_short_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out) { +; DAG-LABEL: ptr_s_buffer_load_short_imm_offset: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s7, s5 +; DAG-NEXT: s_mov_b32 s6, s4 +; DAG-NEXT: s_mov_b32 s5, s3 +; DAG-NEXT: s_mov_b32 s4, s2 +; DAG-NEXT: s_buffer_load_i16 s0, s[4:7], 0x4 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_short_imm_offset: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_i16 s0, s[0:3], 0x4 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %src, i32 4, i32 0), !invariant.load !0 + %sext = sext i16 %ld to i32 + store i32 %sext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_short_sgpr(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) { +; DAG-LABEL: ptr_s_buffer_load_short_sgpr: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s11, s5 +; DAG-NEXT: s_mov_b32 s10, s4 +; DAG-NEXT: s_mov_b32 s9, s3 +; DAG-NEXT: s_mov_b32 s8, s2 +; DAG-NEXT: s_buffer_load_i16 s0, s[8:11], s6 offset:0x0 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_short_sgpr: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_i16 s0, s[0:3], s6 offset:0x0 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 + %sext = sext i16 %ld to i32 + store i32 %sext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_short_sgpr_or_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) { +; DAG-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s11, s5 +; DAG-NEXT: s_mov_b32 s10, s4 +; DAG-NEXT: s_mov_b32 s9, s3 +; DAG-NEXT: s_mov_b32 s8, s2 +; DAG-NEXT: s_buffer_load_i16 s0, s[8:11], s6 offset:0x64 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_i16 s0, s[0:3], s6 offset:0x64 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %off = add nuw nsw i32 %in, 100 + %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %src, i32 %off, i32 0), !invariant.load !0 + %sext = sext i16 %ld to i32 + store i32 %sext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_short_sgpr_or_imm_offset_divergent(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) { +; DAG-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset_divergent: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s7, s5 +; DAG-NEXT: s_mov_b32 s6, s4 +; DAG-NEXT: s_mov_b32 s5, s3 +; DAG-NEXT: s_mov_b32 s4, s2 +; DAG-NEXT: buffer_load_i16 v2, v2, s[4:7], null offen +; DAG-NEXT: s_wait_loadcnt 0x0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset_divergent: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: buffer_load_i16 v2, v2, s[0:3], null offen +; GISEL-NEXT: s_wait_loadcnt 0x0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 + %sext = sext i16 %ld to i32 + store i32 %sext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_ushort_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out) { +; DAG-LABEL: ptr_s_buffer_load_ushort_imm_offset: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s7, s5 +; DAG-NEXT: s_mov_b32 s6, s4 +; DAG-NEXT: s_mov_b32 s5, s3 +; DAG-NEXT: s_mov_b32 s4, s2 +; DAG-NEXT: s_buffer_load_u16 s0, s[4:7], 0x4 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: s_and_b32 s0, s0, 0xffff +; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_ushort_imm_offset: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], 0x4 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: s_and_b32 s0, s0, 0xffff +; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %src, i32 4, i32 0), !invariant.load !0 + %zext = zext i16 %ld to i32 + store i32 %zext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_ushort_sgpr(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) { +; DAG-LABEL: ptr_s_buffer_load_ushort_sgpr: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s11, s5 +; DAG-NEXT: s_mov_b32 s10, s4 +; DAG-NEXT: s_mov_b32 s9, s3 +; DAG-NEXT: s_mov_b32 s8, s2 +; DAG-NEXT: s_buffer_load_u16 s0, s[8:11], s6 offset:0x0 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: s_and_b32 s0, s0, 0xffff +; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_ushort_sgpr: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], s6 offset:0x0 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: s_and_b32 s0, s0, 0xffff +; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 + %zext = zext i16 %ld to i32 + store i32 %zext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_ushort_sgpr_or_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) { +; DAG-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s11, s5 +; DAG-NEXT: s_mov_b32 s10, s4 +; DAG-NEXT: s_mov_b32 s9, s3 +; DAG-NEXT: s_mov_b32 s8, s2 +; DAG-NEXT: s_buffer_load_u16 s0, s[8:11], s6 offset:0x64 +; DAG-NEXT: s_wait_kmcnt 0x0 +; DAG-NEXT: s_and_b32 s0, s0, 0xffff +; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; DAG-NEXT: v_mov_b32_e32 v2, s0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], s6 offset:0x64 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: s_and_b32 s0, s0, 0xffff +; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %off = add nuw nsw i32 %in, 100 + %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %src, i32 %off, i32 0), !invariant.load !0 + %zext = zext i16 %ld to i32 + store i32 %zext, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ptr_s_buffer_load_ushort_sgpr_or_imm_offset_divergent(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) { +; DAG-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset_divergent: +; DAG: ; %bb.0: ; %main_body +; DAG-NEXT: s_mov_b32 s7, s5 +; DAG-NEXT: s_mov_b32 s6, s4 +; DAG-NEXT: s_mov_b32 s5, s3 +; DAG-NEXT: s_mov_b32 s4, s2 +; DAG-NEXT: buffer_load_u16 v2, v2, s[4:7], null offen +; DAG-NEXT: s_wait_loadcnt 0x0 +; DAG-NEXT: global_store_b32 v[0:1], v2, off +; DAG-NEXT: s_endpgm +; +; GISEL-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset_divergent: +; GISEL: ; %bb.0: ; %main_body +; GISEL-NEXT: s_mov_b32 s0, s2 +; GISEL-NEXT: s_mov_b32 s1, s3 +; GISEL-NEXT: s_mov_b32 s2, s4 +; GISEL-NEXT: s_mov_b32 s3, s5 +; GISEL-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen +; GISEL-NEXT: s_wait_loadcnt 0x0 +; GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GISEL-NEXT: s_endpgm +main_body: + %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 + %zext = zext i16 %ld to i32 + store i32 %zext, ptr addrspace(1) %out + ret void +} + +declare i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8), i32, i32) +declare i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8), i32, i32) +declare i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8), i32, i32) +declare i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8), i32, i32) + +!0 = !{} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GCN: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/group-image-instructions.ll b/llvm/test/CodeGen/AMDGPU/group-image-instructions.ll index 34df1a64d8cbb..08d7087a3e946 100644 --- a/llvm/test/CodeGen/AMDGPU/group-image-instructions.ll +++ b/llvm/test/CodeGen/AMDGPU/group-image-instructions.ll @@ -25,10 +25,10 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in ; GFX11-NEXT: v_interp_p10_f32 v0, v3, v0, v3 wait_exp:0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0xf -; GFX11-NEXT: s_buffer_load_b64 s[16:17], s[12:15], 0x10 -; GFX11-NEXT: s_buffer_load_b64 s[18:19], s[12:15], 0x20 -; GFX11-NEXT: s_buffer_load_b64 s[20:21], s[12:15], 0x30 -; GFX11-NEXT: s_buffer_load_b64 s[22:23], s[12:15], 0x40 +; GFX11-NEXT: s_buffer_load_b64 s[22:23], s[12:15], 0x10 +; GFX11-NEXT: s_buffer_load_b64 s[20:21], s[12:15], 0x20 +; GFX11-NEXT: s_buffer_load_b64 s[18:19], s[12:15], 0x30 +; GFX11-NEXT: s_buffer_load_b64 s[16:17], s[12:15], 0x40 ; GFX11-NEXT: s_buffer_load_b64 s[24:25], s[12:15], 0x50 ; GFX11-NEXT: s_buffer_load_b64 s[26:27], s[12:15], 0x60 ; GFX11-NEXT: s_buffer_load_b64 s[28:29], s[12:15], 0x70 @@ -45,14 +45,14 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in ; GFX11-NEXT: v_interp_p2_f32 v0, v3, v1, v0 wait_exp:7 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_f32_e32 v5, s17, v36 -; GFX11-NEXT: v_add_f32_e32 v4, s16, v0 -; GFX11-NEXT: v_add_f32_e32 v8, s18, v0 -; GFX11-NEXT: v_add_f32_e32 v9, s19, v36 -; GFX11-NEXT: v_add_f32_e32 v12, s20, v0 -; GFX11-NEXT: v_add_f32_e32 v13, s21, v36 -; GFX11-NEXT: v_add_f32_e32 v16, s22, v0 -; GFX11-NEXT: v_add_f32_e32 v17, s23, v36 +; GFX11-NEXT: v_add_f32_e32 v5, s23, v36 +; GFX11-NEXT: v_add_f32_e32 v4, s22, v0 +; GFX11-NEXT: v_add_f32_e32 v8, s20, v0 +; GFX11-NEXT: v_add_f32_e32 v9, s21, v36 +; GFX11-NEXT: v_add_f32_e32 v12, s18, v0 +; GFX11-NEXT: v_add_f32_e32 v13, s19, v36 +; GFX11-NEXT: v_add_f32_e32 v16, s16, v0 +; GFX11-NEXT: v_add_f32_e32 v17, s17, v36 ; GFX11-NEXT: v_add_f32_e32 v20, s24, v0 ; GFX11-NEXT: v_add_f32_e32 v21, s25, v36 ; GFX11-NEXT: v_add_f32_e32 v24, s26, v0 @@ -166,7 +166,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %i2 = zext i32 %userdata6 to i64 %i3 = or disjoint i64 %i1, %i2 %i4 = inttoptr i64 %i3 to ptr addrspace(4) - %i5 = load <4 x i32>, ptr addrspace(4) %i4, align 16 + %i5 = load ptr addrspace(8), ptr addrspace(4) %i4, align 16 %i6 = zext i32 %userdata7 to i64 %i7 = or disjoint i64 %i1, %i6 %i8 = inttoptr i64 %i7 to ptr addrspace(4) @@ -183,7 +183,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %i17 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %PrimMask) %i18 = call float @llvm.amdgcn.interp.inreg.p10(float %i17, float %PerspInterpCenter.i0, float %i17) %i19 = call float @llvm.amdgcn.interp.inreg.p2(float %i17, float %PerspInterpCenter.i1, float %i18) - %i20 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 16, i32 0), !invariant.load !0 + %i20 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 16, i32 0), !invariant.load !0 %i21 = shufflevector <2 x i32> %i20, <2 x i32> poison, <4 x i32> %i22 = bitcast <4 x i32> %i21 to <4 x float> %.i0 = extractelement <4 x float> %i22, i64 0 @@ -195,7 +195,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i113 = extractelement <4 x float> %i23, i64 1 %.i215 = extractelement <4 x float> %i23, i64 2 %.i317 = extractelement <4 x float> %i23, i64 3 - %i24 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 32, i32 0), !invariant.load !0 + %i24 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 32, i32 0), !invariant.load !0 %i25 = shufflevector <2 x i32> %i24, <2 x i32> poison, <4 x i32> %i26 = bitcast <4 x i32> %i25 to <4 x float> %.i05 = extractelement <4 x float> %i26, i64 0 @@ -211,7 +211,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i216 = fadd reassoc nnan nsz arcp contract afn float %.i2, %.i215 %.i3 = extractelement <4 x float> %i27, i64 3 %.i318 = fadd reassoc nnan nsz arcp contract afn float %.i3, %.i317 - %i28 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 48, i32 0), !invariant.load !0 + %i28 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 48, i32 0), !invariant.load !0 %i29 = shufflevector <2 x i32> %i28, <2 x i32> poison, <4 x i32> %i30 = bitcast <4 x i32> %i29 to <4 x float> %.i019 = extractelement <4 x float> %i30, i64 0 @@ -227,7 +227,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i228 = fadd reassoc nnan nsz arcp contract afn float %.i227, %.i216 %.i329 = extractelement <4 x float> %i31, i64 3 %.i330 = fadd reassoc nnan nsz arcp contract afn float %.i329, %.i318 - %i32 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 64, i32 0), !invariant.load !0 + %i32 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 64, i32 0), !invariant.load !0 %i33 = shufflevector <2 x i32> %i32, <2 x i32> poison, <4 x i32> %i34 = bitcast <4 x i32> %i33 to <4 x float> %.i031 = extractelement <4 x float> %i34, i64 0 @@ -243,7 +243,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i240 = fadd reassoc nnan nsz arcp contract afn float %.i239, %.i228 %.i341 = extractelement <4 x float> %i35, i64 3 %.i342 = fadd reassoc nnan nsz arcp contract afn float %.i341, %.i330 - %i36 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 80, i32 0), !invariant.load !0 + %i36 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 80, i32 0), !invariant.load !0 %i37 = shufflevector <2 x i32> %i36, <2 x i32> poison, <4 x i32> %i38 = bitcast <4 x i32> %i37 to <4 x float> %.i043 = extractelement <4 x float> %i38, i64 0 @@ -259,7 +259,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i252 = fadd reassoc nnan nsz arcp contract afn float %.i251, %.i240 %.i353 = extractelement <4 x float> %i39, i64 3 %.i354 = fadd reassoc nnan nsz arcp contract afn float %.i353, %.i342 - %i40 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 96, i32 0), !invariant.load !0 + %i40 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 96, i32 0), !invariant.load !0 %i41 = shufflevector <2 x i32> %i40, <2 x i32> poison, <4 x i32> %i42 = bitcast <4 x i32> %i41 to <4 x float> %.i055 = extractelement <4 x float> %i42, i64 0 @@ -275,7 +275,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i264 = fadd reassoc nnan nsz arcp contract afn float %.i263, %.i252 %.i365 = extractelement <4 x float> %i43, i64 3 %.i366 = fadd reassoc nnan nsz arcp contract afn float %.i365, %.i354 - %i44 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 112, i32 0), !invariant.load !0 + %i44 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 112, i32 0), !invariant.load !0 %i45 = shufflevector <2 x i32> %i44, <2 x i32> poison, <4 x i32> %i46 = bitcast <4 x i32> %i45 to <4 x float> %.i067 = extractelement <4 x float> %i46, i64 0 @@ -291,7 +291,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i276 = fadd reassoc nnan nsz arcp contract afn float %.i275, %.i264 %.i377 = extractelement <4 x float> %i47, i64 3 %.i378 = fadd reassoc nnan nsz arcp contract afn float %.i377, %.i366 - %i48 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 128, i32 0), !invariant.load !0 + %i48 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 128, i32 0), !invariant.load !0 %i49 = shufflevector <2 x i32> %i48, <2 x i32> poison, <4 x i32> %i50 = bitcast <4 x i32> %i49 to <4 x float> %.i079 = extractelement <4 x float> %i50, i64 0 @@ -307,7 +307,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i288 = fadd reassoc nnan nsz arcp contract afn float %.i287, %.i276 %.i389 = extractelement <4 x float> %i51, i64 3 %.i390 = fadd reassoc nnan nsz arcp contract afn float %.i389, %.i378 - %i52 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 144, i32 0), !invariant.load !0 + %i52 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 144, i32 0), !invariant.load !0 %i53 = shufflevector <2 x i32> %i52, <2 x i32> poison, <4 x i32> %i54 = bitcast <4 x i32> %i53 to <4 x float> %.i091 = extractelement <4 x float> %i54, i64 0 @@ -323,7 +323,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i2100 = fadd reassoc nnan nsz arcp contract afn float %.i299, %.i288 %.i3101 = extractelement <4 x float> %i55, i64 3 %.i3102 = fadd reassoc nnan nsz arcp contract afn float %.i3101, %.i390 - %i56 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 160, i32 0), !invariant.load !0 + %i56 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 160, i32 0), !invariant.load !0 %i57 = shufflevector <2 x i32> %i56, <2 x i32> poison, <4 x i32> %i58 = bitcast <4 x i32> %i57 to <4 x float> %.i0103 = extractelement <4 x float> %i58, i64 0 @@ -339,7 +339,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i2112 = fadd reassoc nnan nsz arcp contract afn float %.i2111, %.i2100 %.i3113 = extractelement <4 x float> %i59, i64 3 %.i3114 = fadd reassoc nnan nsz arcp contract afn float %.i3113, %.i3102 - %i60 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 176, i32 0), !invariant.load !0 + %i60 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 176, i32 0), !invariant.load !0 %i61 = shufflevector <2 x i32> %i60, <2 x i32> poison, <4 x i32> %i62 = bitcast <4 x i32> %i61 to <4 x float> %.i0115 = extractelement <4 x float> %i62, i64 0 @@ -355,7 +355,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i2124 = fadd reassoc nnan nsz arcp contract afn float %.i2123, %.i2112 %.i3125 = extractelement <4 x float> %i63, i64 3 %.i3126 = fadd reassoc nnan nsz arcp contract afn float %.i3125, %.i3114 - %i64 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 192, i32 0), !invariant.load !0 + %i64 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 192, i32 0), !invariant.load !0 %i65 = shufflevector <2 x i32> %i64, <2 x i32> poison, <4 x i32> %i66 = bitcast <4 x i32> %i65 to <4 x float> %.i0127 = extractelement <4 x float> %i66, i64 0 @@ -371,7 +371,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i2136 = fadd reassoc nnan nsz arcp contract afn float %.i2135, %.i2124 %.i3137 = extractelement <4 x float> %i67, i64 3 %.i3138 = fadd reassoc nnan nsz arcp contract afn float %.i3137, %.i3126 - %i68 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 208, i32 0), !invariant.load !0 + %i68 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 208, i32 0), !invariant.load !0 %i69 = shufflevector <2 x i32> %i68, <2 x i32> poison, <4 x i32> %i70 = bitcast <4 x i32> %i69 to <4 x float> %.i0139 = extractelement <4 x float> %i70, i64 0 @@ -387,7 +387,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i2148 = fadd reassoc nnan nsz arcp contract afn float %.i2147, %.i2136 %.i3149 = extractelement <4 x float> %i71, i64 3 %.i3150 = fadd reassoc nnan nsz arcp contract afn float %.i3149, %.i3138 - %i72 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 224, i32 0), !invariant.load !0 + %i72 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 224, i32 0), !invariant.load !0 %i73 = shufflevector <2 x i32> %i72, <2 x i32> poison, <4 x i32> %i74 = bitcast <4 x i32> %i73 to <4 x float> %.i0151 = extractelement <4 x float> %i74, i64 0 @@ -403,7 +403,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i2160 = fadd reassoc nnan nsz arcp contract afn float %.i2159, %.i2148 %.i3161 = extractelement <4 x float> %i75, i64 3 %.i3162 = fadd reassoc nnan nsz arcp contract afn float %.i3161, %.i3150 - %i76 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 240, i32 0), !invariant.load !0 + %i76 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 240, i32 0), !invariant.load !0 %i77 = shufflevector <2 x i32> %i76, <2 x i32> poison, <4 x i32> %i78 = bitcast <4 x i32> %i77 to <4 x float> %.i0163 = extractelement <4 x float> %i78, i64 0 @@ -419,7 +419,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in %.i2172 = fadd reassoc nnan nsz arcp contract afn float %.i2171, %.i2160 %.i3173 = extractelement <4 x float> %i79, i64 3 %.i3174 = fadd reassoc nnan nsz arcp contract afn float %.i3173, %.i3162 - %i80 = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %i5, i32 256, i32 0), !invariant.load !0 + %i80 = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %i5, i32 256, i32 0), !invariant.load !0 %i81 = shufflevector <2 x i32> %i80, <2 x i32> poison, <4 x i32> %i82 = bitcast <4 x i32> %i81 to <4 x float> %.i0175 = extractelement <4 x float> %i82, i64 0 @@ -450,7 +450,7 @@ declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, f declare float @llvm.amdgcn.lds.param.load(i32 immarg, i32 immarg, i32) #3 declare float @llvm.amdgcn.interp.inreg.p10(float, float, float) #3 declare float @llvm.amdgcn.interp.inreg.p2(float, float, float) #3 -declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32 immarg) #8 +declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8), i32, i32 immarg) #8 attributes #2 = { alwaysinline nounwind memory(readwrite) "amdgpu-sched-strategy"="max-memory-clause" "amdgpu-max-memory-cluster-dwords"="32"} attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } diff --git a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll index faa653d11b52a..ef8c2ea833bff 100644 --- a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll +++ b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll @@ -620,12 +620,12 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) { ret void } -declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32) ; from smrd.ll ; covers s_buffer_load ; -define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offset) #0 { +define amdgpu_ps float @smrd_sgpr_offset(ptr addrspace(8) inreg %desc, i32 inreg %offset) #0 { ; GFX9-LABEL: smrd_sgpr_offset: ; GFX9: ; %bb.0: ; %main_body ; GFX9-NEXT: s_buffer_load_dword s0, s[0:3], s4 offset:0x0 @@ -672,7 +672,7 @@ define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offse ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog main_body: - %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0) + %r = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %desc, i32 %offset, i32 0), !invariant.load !{} ret float %r } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-gfx12.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-gfx12.ll new file mode 100644 index 0000000000000..1e224d7cd2261 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-gfx12.ll @@ -0,0 +1,198 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX1200-SDAG +; RUN: llc -global-isel=1 -mtriple=amdgpu12.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX1200-GISEL +; RUN: llc -global-isel=0 -mtriple=amdgpu12.50-amd-amdhsa -mattr=-wait-xcnt -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX1250-SDAG +; RUN: llc -global-isel=1 -mtriple=amdgpu12.50-amd-amdhsa -mattr=-wait-xcnt -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX1250-GISEL + +define amdgpu_kernel void @ptr_s_buffer_load_i8(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) { +; +; GFX1200-SDAG-LABEL: ptr_s_buffer_load_i8: +; GFX1200-SDAG: ; %bb.0: +; GFX1200-SDAG-NEXT: s_clause 0x1 +; GFX1200-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-SDAG-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: s_buffer_load_u8 s2, s[0:3], s6 offset:0x0 +; GFX1200-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1200-SDAG-NEXT: global_store_b8 v0, v1, s[0:1] +; GFX1200-SDAG-NEXT: s_endpgm +; +; GFX1200-GISEL-LABEL: ptr_s_buffer_load_i8: +; GFX1200-GISEL: ; %bb.0: +; GFX1200-GISEL-NEXT: s_clause 0x2 +; GFX1200-GISEL-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: s_buffer_load_u8 s0, s[0:3], s6 offset:0x0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1200-GISEL-NEXT: global_store_b8 v1, v0, s[4:5] +; GFX1200-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: ptr_s_buffer_load_i8: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-SDAG-NEXT: s_load_b32 s8, s[4:5], 0x20 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: s_buffer_load_u8 s9, s[0:3], s8 offset:0x0 nv +; GFX1250-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s9 +; GFX1250-SDAG-NEXT: global_store_b8 v0, v1, s[6:7] +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: ptr_s_buffer_load_i8: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_clause 0x2 +; GFX1250-GISEL-NEXT: s_load_b32 s8, s[4:5], 0x20 nv +; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: s_buffer_load_u8 s0, s[0:3], s8 offset:0x0 nv +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-GISEL-NEXT: global_store_b8 v1, v0, s[6:7] +; GFX1250-GISEL-NEXT: s_endpgm + %load = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i8 %load, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @ptr_s_buffer_load_i16(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) { +; +; GFX1200-SDAG-LABEL: ptr_s_buffer_load_i16: +; GFX1200-SDAG: ; %bb.0: +; GFX1200-SDAG-NEXT: s_clause 0x1 +; GFX1200-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-SDAG-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: s_buffer_load_u16 s2, s[0:3], s6 offset:0x0 +; GFX1200-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1200-SDAG-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1200-SDAG-NEXT: s_endpgm +; +; GFX1200-GISEL-LABEL: ptr_s_buffer_load_i16: +; GFX1200-GISEL: ; %bb.0: +; GFX1200-GISEL-NEXT: s_clause 0x2 +; GFX1200-GISEL-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], s6 offset:0x0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: v_mov_b16_e32 v0.l, s0 +; GFX1200-GISEL-NEXT: global_store_b16 v1, v0, s[4:5] +; GFX1200-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: ptr_s_buffer_load_i16: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-SDAG-NEXT: s_load_b32 s8, s[4:5], 0x20 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: s_buffer_load_u16 s9, s[0:3], s8 offset:0x0 nv +; GFX1250-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s9 +; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[6:7] +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: ptr_s_buffer_load_i16: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_clause 0x2 +; GFX1250-GISEL-NEXT: s_load_b32 s8, s[4:5], 0x20 nv +; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], s8 offset:0x0 nv +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s0 +; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[6:7] +; GFX1250-GISEL-NEXT: s_endpgm + %load = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i16 %load, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @ptr_s_buffer_load_i8_divergent_offset(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc) { +; +; GFX1200-SDAG-LABEL: ptr_s_buffer_load_i8_divergent_offset: +; GFX1200-SDAG: ; %bb.0: +; GFX1200-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: buffer_load_u8 v0, v0, s[0:3], null offen +; GFX1200-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX1200-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: global_store_b8 v1, v0, s[0:1] +; GFX1200-SDAG-NEXT: s_endpgm +; +; GFX1200-GISEL-LABEL: ptr_s_buffer_load_i8_divergent_offset: +; GFX1200-GISEL: ; %bb.0: +; GFX1200-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0 +; GFX1200-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: buffer_load_u8 v0, v0, s[0:3], null offen +; GFX1200-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX1200-GISEL-NEXT: global_store_b8 v1, v0, s[4:5] +; GFX1200-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: ptr_s_buffer_load_i8_divergent_offset: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: buffer_load_u8 v0, v0, s[0:3], null offen nv +; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv +; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: global_store_b8 v1, v0, s[0:1] +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: ptr_s_buffer_load_i8_divergent_offset: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX1250-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 nv +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: buffer_load_u8 v0, v0, s[0:3], null offen nv +; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX1250-GISEL-NEXT: global_store_b8 v1, v0, s[4:5] +; GFX1250-GISEL-NEXT: s_endpgm + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %load = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %rsrc, i32 %tid, i32 0), !invariant.load !0 + store i8 %load, ptr addrspace(1) %out + ret void +} + +declare i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) nocapture readonly, i32, i32 immarg) +declare i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) nocapture readonly, i32, i32 immarg) +declare i32 @llvm.amdgcn.workitem.id.x() + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-mmo.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-mmo.ll new file mode 100644 index 0000000000000..256d5c59fc64c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-mmo.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -stop-after=amdgpu-isel -o - %s | FileCheck %s --check-prefix=SDAG + +define amdgpu_kernel void @ptr_s_buffer_load_mmo(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) { +; SDAG-LABEL: name: ptr_s_buffer_load_mmo +; SDAG: S_BUFFER_LOAD_DWORD_SGPR_IMM {{.*}} :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) align 1 %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i32 %load, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @ptr_s_buffer_load_mmo_overaligned(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) { +; SDAG-LABEL: name: ptr_s_buffer_load_mmo_overaligned +; SDAG: S_BUFFER_LOAD_DWORD_SGPR_IMM {{.*}} :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) align 8 %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i32 %load, ptr addrspace(1) %out + ret void +} + +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) nocapture readonly, i32, i32 immarg) + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.ll new file mode 100644 index 0000000000000..83a5717f0f11b --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.ll @@ -0,0 +1,1096 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX6 +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX7 +; RUN: llc -global-isel=0 -mtriple=amdgpu8.03-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX8 +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX9 +; RUN: llc -global-isel=0 -mtriple=amdgpu10.10-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX10 +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdhsa -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX11 +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX1200-SDAG +; RUN: llc -global-isel=1 -mtriple=amdgpu12.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX1200-GISEL +; RUN: llc -global-isel=0 -mtriple=amdgpu12.50-amd-amdhsa -mattr=-wait-xcnt -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX1250-SDAG +; RUN: llc -global-isel=1 -mtriple=amdgpu12.50-amd-amdhsa -mattr=-wait-xcnt -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX1250-GISEL + +define amdgpu_kernel void @ptr_s_buffer_load_i32(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) { +; +; GFX6-LABEL: ptr_s_buffer_load_i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX6-NEXT: s_load_dword s4, s[8:9], 0x8 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: s_buffer_load_dword s4, s[0:3], s4 +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX6-NEXT: s_mov_b32 s3, 0x100f000 +; GFX6-NEXT: s_mov_b32 s2, -1 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v0, s4 +; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX6-NEXT: s_endpgm +; +; GFX7-LABEL: ptr_s_buffer_load_i32: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dword s6, s[8:9], 0x8 +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX7-NEXT: s_add_i32 s12, s12, s17 +; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_buffer_load_dword s0, s[0:3], s6 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: v_mov_b32_e32 v2, s0 +; GFX7-NEXT: flat_store_dword v[0:1], v2 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: ptr_s_buffer_load_i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dword s6, s[8:9], 0x20 +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX8-NEXT: s_add_i32 s12, s12, s17 +; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_buffer_load_dword s0, s[0:3], s6 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: ptr_s_buffer_load_i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX9-NEXT: s_load_dword s6, s[8:9], 0x20 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_buffer_load_dword s7, s[0:3], s6 offset:0x0 +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-NEXT: global_store_dword v0, v1, s[4:5] +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: ptr_s_buffer_load_i32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX10-NEXT: s_load_dword s6, s[8:9], 0x20 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_buffer_load_dword s7, s[0:3], s6 offset:0x0 +; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v1, s7 +; GFX10-NEXT: global_store_dword v0, v1, s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: ptr_s_buffer_load_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_buffer_load_b32 s2, s[0:3], s6 offset:0x0 +; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_endpgm +; +; GFX1200-SDAG-LABEL: ptr_s_buffer_load_i32: +; GFX1200-SDAG: ; %bb.0: +; GFX1200-SDAG-NEXT: s_clause 0x1 +; GFX1200-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-SDAG-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: s_buffer_load_b32 s2, s[0:3], s6 offset:0x0 +; GFX1200-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1200-SDAG-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX1200-SDAG-NEXT: s_endpgm +; +; GFX1200-GISEL-LABEL: ptr_s_buffer_load_i32: +; GFX1200-GISEL: ; %bb.0: +; GFX1200-GISEL-NEXT: s_clause 0x2 +; GFX1200-GISEL-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: s_buffer_load_b32 s0, s[0:3], s6 offset:0x0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1200-GISEL-NEXT: global_store_b32 v1, v0, s[4:5] +; GFX1200-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: ptr_s_buffer_load_i32: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-SDAG-NEXT: s_load_b32 s8, s[4:5], 0x20 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: s_buffer_load_b32 s9, s[0:3], s8 offset:0x0 nv +; GFX1250-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s9 +; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[6:7] +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: ptr_s_buffer_load_i32: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_clause 0x2 +; GFX1250-GISEL-NEXT: s_load_b32 s8, s[4:5], 0x20 nv +; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: s_buffer_load_b32 s0, s[0:3], s8 offset:0x0 nv +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[6:7] +; GFX1250-GISEL-NEXT: s_endpgm + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store i32 %load, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @ptr_s_buffer_load_v2i32(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) { +; +; GFX6-LABEL: ptr_s_buffer_load_v2i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX6-NEXT: s_load_dword s4, s[8:9], 0x8 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: s_buffer_load_dwordx2 s[4:5], s[0:3], s4 +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX6-NEXT: s_mov_b32 s3, 0x100f000 +; GFX6-NEXT: s_mov_b32 s2, -1 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v0, s4 +; GFX6-NEXT: v_mov_b32_e32 v1, s5 +; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX6-NEXT: s_endpgm +; +; GFX7-LABEL: ptr_s_buffer_load_v2i32: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dword s6, s[8:9], 0x8 +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX7-NEXT: s_add_i32 s12, s12, s17 +; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_buffer_load_dwordx2 s[0:1], s[0:3], s6 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: v_mov_b32_e32 v3, s1 +; GFX7-NEXT: v_mov_b32_e32 v2, s0 +; GFX7-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: ptr_s_buffer_load_v2i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dword s6, s[8:9], 0x20 +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX8-NEXT: s_add_i32 s12, s12, s17 +; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_buffer_load_dwordx2 s[0:1], s[0:3], s6 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: ptr_s_buffer_load_v2i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX9-NEXT: s_load_dword s10, s[8:9], 0x20 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_buffer_load_dwordx2 s[4:5], s[0:3], s10 offset:0x0 +; GFX9-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: ptr_s_buffer_load_v2i32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX10-NEXT: s_load_dword s10, s[8:9], 0x20 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_buffer_load_dwordx2 s[4:5], s[0:3], s10 offset:0x0 +; GFX10-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: ptr_s_buffer_load_v2i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_buffer_load_b64 s[0:1], s[0:3], s6 offset:0x0 +; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[2:3] +; GFX11-NEXT: s_endpgm +; +; GFX1200-SDAG-LABEL: ptr_s_buffer_load_v2i32: +; GFX1200-SDAG: ; %bb.0: +; GFX1200-SDAG-NEXT: s_clause 0x1 +; GFX1200-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-SDAG-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: s_buffer_load_b64 s[0:1], s[0:3], s6 offset:0x0 +; GFX1200-SDAG-NEXT: s_load_b64 s[2:3], s[4:5], 0x0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1 +; GFX1200-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX1200-SDAG-NEXT: global_store_b64 v2, v[0:1], s[2:3] +; GFX1200-SDAG-NEXT: s_endpgm +; +; GFX1200-GISEL-LABEL: ptr_s_buffer_load_v2i32: +; GFX1200-GISEL: ; %bb.0: +; GFX1200-GISEL-NEXT: s_clause 0x2 +; GFX1200-GISEL-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: s_buffer_load_b64 s[0:1], s[0:3], s6 offset:0x0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX1200-GISEL-NEXT: global_store_b64 v2, v[0:1], s[4:5] +; GFX1200-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: ptr_s_buffer_load_v2i32: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-SDAG-NEXT: s_load_b32 s10, s[4:5], 0x20 nv +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: s_buffer_load_b64 s[6:7], s[0:3], s10 offset:0x0 nv +; GFX1250-SDAG-NEXT: s_load_b64 s[8:9], s[4:5], 0x0 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[6:7] +; GFX1250-SDAG-NEXT: global_store_b64 v2, v[0:1], s[8:9] +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: ptr_s_buffer_load_v2i32: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_clause 0x2 +; GFX1250-GISEL-NEXT: s_load_b32 s8, s[4:5], 0x20 nv +; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: s_buffer_load_b64 s[0:1], s[0:3], s8 offset:0x0 nv +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX1250-GISEL-NEXT: global_store_b64 v2, v[0:1], s[6:7] +; GFX1250-GISEL-NEXT: s_endpgm + %load = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store <2 x i32> %load, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @ptr_s_buffer_load_v4i32(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) { +; +; GFX6-LABEL: ptr_s_buffer_load_v4i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX6-NEXT: s_load_dword s4, s[8:9], 0x8 +; GFX6-NEXT: s_mov_b32 s7, 0x100f000 +; GFX6-NEXT: s_mov_b32 s6, -1 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], s4 +; GFX6-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v0, s0 +; GFX6-NEXT: v_mov_b32_e32 v1, s1 +; GFX6-NEXT: v_mov_b32_e32 v2, s2 +; GFX6-NEXT: v_mov_b32_e32 v3, s3 +; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GFX6-NEXT: s_endpgm +; +; GFX7-LABEL: ptr_s_buffer_load_v4i32: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dword s6, s[8:9], 0x8 +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX7-NEXT: s_add_i32 s12, s12, s17 +; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], s6 +; GFX7-NEXT: v_mov_b32_e32 v4, s4 +; GFX7-NEXT: v_mov_b32_e32 v5, s5 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-NEXT: v_mov_b32_e32 v2, s2 +; GFX7-NEXT: v_mov_b32_e32 v3, s3 +; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: ptr_s_buffer_load_v4i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dword s6, s[8:9], 0x20 +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX8-NEXT: s_add_i32 s12, s12, s17 +; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], s6 +; GFX8-NEXT: v_mov_b32_e32 v4, s4 +; GFX8-NEXT: v_mov_b32_e32 v5, s5 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s2 +; GFX8-NEXT: v_mov_b32_e32 v3, s3 +; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: ptr_s_buffer_load_v4i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX9-NEXT: s_load_dword s12, s[8:9], 0x20 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], s12 offset:0x0 +; GFX9-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: ptr_s_buffer_load_v4i32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX10-NEXT: s_load_dword s12, s[8:9], 0x20 +; GFX10-NEXT: v_mov_b32_e32 v4, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], s12 offset:0x0 +; GFX10-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-NEXT: v_mov_b32_e32 v1, s5 +; GFX10-NEXT: v_mov_b32_e32 v2, s6 +; GFX10-NEXT: v_mov_b32_e32 v3, s7 +; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: ptr_s_buffer_load_v4i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX11-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_buffer_load_b128 s[0:3], s[0:3], s6 offset:0x0 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-NEXT: v_mov_b32_e32 v2, s2 +; GFX11-NEXT: v_mov_b32_e32 v3, s3 +; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5] +; GFX11-NEXT: s_endpgm +; +; GFX1200-SDAG-LABEL: ptr_s_buffer_load_v4i32: +; GFX1200-SDAG: ; %bb.0: +; GFX1200-SDAG-NEXT: s_clause 0x1 +; GFX1200-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-SDAG-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: s_buffer_load_b128 s[0:3], s[0:3], s6 offset:0x0 +; GFX1200-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1 +; GFX1200-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 +; GFX1200-SDAG-NEXT: v_mov_b32_e32 v2, s2 +; GFX1200-SDAG-NEXT: global_store_b128 v4, v[0:3], s[4:5] +; GFX1200-SDAG-NEXT: s_endpgm +; +; GFX1200-GISEL-LABEL: ptr_s_buffer_load_v4i32: +; GFX1200-GISEL: ; %bb.0: +; GFX1200-GISEL-NEXT: s_clause 0x2 +; GFX1200-GISEL-NEXT: s_load_b32 s6, s[4:5], 0x20 +; GFX1200-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: s_buffer_load_b128 s[0:3], s[0:3], s6 offset:0x0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX1200-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX1200-GISEL-NEXT: global_store_b128 v4, v[0:3], s[4:5] +; GFX1200-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: ptr_s_buffer_load_v4i32: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-SDAG-NEXT: s_load_b32 s12, s[4:5], 0x20 nv +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v4, 0 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: s_buffer_load_b128 s[8:11], s[0:3], s12 offset:0x0 nv +; GFX1250-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9] +; GFX1250-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[10:11] +; GFX1250-SDAG-NEXT: global_store_b128 v4, v[0:3], s[6:7] +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: ptr_s_buffer_load_v4i32: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_clause 0x2 +; GFX1250-GISEL-NEXT: s_load_b32 s8, s[4:5], 0x20 nv +; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: s_buffer_load_b128 s[0:3], s[0:3], s8 offset:0x0 nv +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: global_store_b128 v4, v[0:3], s[6:7] +; GFX1250-GISEL-NEXT: s_endpgm + %load = call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + store <4 x i32> %load, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @ptr_s_buffer_load_i32_imm_offset(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc) { +; +; GFX6-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: s_buffer_load_dword s4, s[0:3], 0x4 +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX6-NEXT: s_mov_b32 s3, 0x100f000 +; GFX6-NEXT: s_mov_b32 s2, -1 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v0, s4 +; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX6-NEXT: s_endpgm +; +; GFX7-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX7-NEXT: s_add_i32 s12, s12, s17 +; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_buffer_load_dword s0, s[0:3], 0x4 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: v_mov_b32_e32 v2, s0 +; GFX7-NEXT: flat_store_dword v[0:1], v2 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX8-NEXT: s_add_i32 s12, s12, s17 +; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_buffer_load_dword s0, s[0:3], 0x10 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_buffer_load_dword s6, s[0:3], 0x10 +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: global_store_dword v0, v1, s[4:5] +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_buffer_load_dword s6, s[0:3], 0x10 +; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v1, s6 +; GFX10-NEXT: global_store_dword v0, v1, s[4:5] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_buffer_load_b32 s2, s[0:3], 0x10 +; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_endpgm +; +; GFX1200-SDAG-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX1200-SDAG: ; %bb.0: +; GFX1200-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: s_buffer_load_b32 s2, s[0:3], 0x10 +; GFX1200-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1200-SDAG-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX1200-SDAG-NEXT: s_endpgm +; +; GFX1200-GISEL-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX1200-GISEL: ; %bb.0: +; GFX1200-GISEL-NEXT: s_clause 0x1 +; GFX1200-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: s_buffer_load_b32 s0, s[0:3], 0x10 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1200-GISEL-NEXT: global_store_b32 v1, v0, s[4:5] +; GFX1200-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: s_buffer_load_b32 s8, s[0:3], 0x10 nv +; GFX1250-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s8 +; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[6:7] +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: ptr_s_buffer_load_i32_imm_offset: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_clause 0x1 +; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x0 nv +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: s_buffer_load_b32 s0, s[0:3], 0x10 nv +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[6:7] +; GFX1250-GISEL-NEXT: s_endpgm + %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 16, i32 0), !invariant.load !0 + store i32 %load, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @ptr_s_buffer_load_v8i32_divergent_offset_glc(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc) { +; +; GFX6-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:16 glc +; GFX6-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen glc +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX6-NEXT: s_mov_b32 s3, 0x100f000 +; GFX6-NEXT: s_mov_b32 s2, -1 +; GFX6-NEXT: s_waitcnt vmcnt(1) lgkmcnt(0) +; GFX6-NEXT: buffer_store_dwordx4 v[1:4], off, s[0:3], 0 offset:16 +; GFX6-NEXT: s_waitcnt vmcnt(1) +; GFX6-NEXT: buffer_store_dwordx4 v[5:8], off, s[0:3], 0 +; GFX6-NEXT: s_endpgm +; +; GFX7-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX7-NEXT: s_add_i32 s12, s12, s17 +; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:16 glc +; GFX7-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen glc +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_add_u32 s2, s0, 16 +; GFX7-NEXT: s_addc_u32 s3, s1, 0 +; GFX7-NEXT: v_mov_b32_e32 v12, s3 +; GFX7-NEXT: v_mov_b32_e32 v11, s2 +; GFX7-NEXT: v_mov_b32_e32 v10, s1 +; GFX7-NEXT: v_mov_b32_e32 v9, s0 +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: flat_store_dwordx4 v[11:12], v[1:4] +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: flat_store_dwordx4 v[9:10], v[5:8] +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX8-NEXT: s_add_i32 s12, s12, s17 +; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:16 glc +; GFX8-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen glc +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_add_u32 s2, s0, 16 +; GFX8-NEXT: s_addc_u32 s3, s1, 0 +; GFX8-NEXT: v_mov_b32_e32 v12, s3 +; GFX8-NEXT: v_mov_b32_e32 v11, s2 +; GFX8-NEXT: v_mov_b32_e32 v10, s1 +; GFX8-NEXT: v_mov_b32_e32 v9, s0 +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[1:4] +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[5:8] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:16 glc +; GFX9-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen glc +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt vmcnt(1) lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1] offset:16 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: global_store_dwordx4 v0, v[5:8], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:16 glc +; GFX10-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen glc +; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0) +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_waitcnt vmcnt(1) lgkmcnt(0) +; GFX10-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1] offset:16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_store_dwordx4 v0, v[5:8], s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX11-NEXT: v_and_b32_e32 v4, 0x3ff, v0 +; GFX11-NEXT: v_mov_b32_e32 v8, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], 0 offen offset:16 glc +; GFX11-NEXT: buffer_load_b128 v[4:7], v4, s[0:3], 0 offen glc +; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-NEXT: s_waitcnt vmcnt(1) lgkmcnt(0) +; GFX11-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: global_store_b128 v8, v[4:7], s[0:1] +; GFX11-NEXT: s_endpgm +; +; GFX1200-SDAG-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX1200-SDAG: ; %bb.0: +; GFX1200-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-SDAG-NEXT: v_and_b32_e32 v4, 0x3ff, v0 +; GFX1200-SDAG-NEXT: v_mov_b32_e32 v8, 0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: s_clause 0x1 +; GFX1200-SDAG-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], null offen offset:16 th:TH_LOAD_NT +; GFX1200-SDAG-NEXT: buffer_load_b128 v[4:7], v4, s[0:3], null offen th:TH_LOAD_NT +; GFX1200-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX1200-SDAG-NEXT: s_wait_loadcnt 0x1 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:16 +; GFX1200-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX1200-SDAG-NEXT: global_store_b128 v8, v[4:7], s[0:1] +; GFX1200-SDAG-NEXT: s_endpgm +; +; GFX1200-GISEL-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX1200-GISEL: ; %bb.0: +; GFX1200-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v0 +; GFX1200-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: s_clause 0x1 +; GFX1200-GISEL-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], null offen th:TH_LOAD_NT +; GFX1200-GISEL-NEXT: buffer_load_b128 v[4:7], v4, s[0:3], null offen offset:16 th:TH_LOAD_NT +; GFX1200-GISEL-NEXT: s_wait_loadcnt 0x1 +; GFX1200-GISEL-NEXT: global_store_b128 v8, v[0:3], s[4:5] +; GFX1200-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX1200-GISEL-NEXT: global_store_b128 v8, v[4:7], s[4:5] offset:16 +; GFX1200-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: s_clause 0x1 +; GFX1250-SDAG-NEXT: buffer_load_b128 v[0:3], v8, s[0:3], null offen offset:16 th:TH_LOAD_NT nv +; GFX1250-SDAG-NEXT: buffer_load_b128 v[4:7], v8, s[0:3], null offen th:TH_LOAD_NT nv +; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v8, 0 +; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x1 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:16 +; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-NEXT: global_store_b128 v8, v[4:7], s[0:1] +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: ptr_s_buffer_load_v8i32_divergent_offset_glc: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0 +; GFX1250-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 nv +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: s_clause 0x1 +; GFX1250-GISEL-NEXT: buffer_load_b128 v[0:3], v8, s[0:3], null offen th:TH_LOAD_NT nv +; GFX1250-GISEL-NEXT: buffer_load_b128 v[4:7], v8, s[0:3], null offen offset:16 th:TH_LOAD_NT nv +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x1 +; GFX1250-GISEL-NEXT: global_store_b128 v8, v[0:3], s[4:5] +; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX1250-GISEL-NEXT: global_store_b128 v8, v[4:7], s[4:5] offset:16 +; GFX1250-GISEL-NEXT: s_endpgm + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %load = call <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8) %rsrc, i32 %tid, i32 1), !invariant.load !0 + store <8 x i32> %load, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @ptr_s_buffer_load_v16i32_divergent_offset(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc) { +; +; GFX6-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:48 +; GFX6-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen offset:32 +; GFX6-NEXT: buffer_load_dwordx4 v[9:12], v0, s[0:3], 0 offen offset:16 +; GFX6-NEXT: buffer_load_dwordx4 v[13:16], v0, s[0:3], 0 offen +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX6-NEXT: s_mov_b32 s3, 0x100f000 +; GFX6-NEXT: s_mov_b32 s2, -1 +; GFX6-NEXT: s_waitcnt vmcnt(3) lgkmcnt(0) +; GFX6-NEXT: buffer_store_dwordx4 v[1:4], off, s[0:3], 0 offset:48 +; GFX6-NEXT: s_waitcnt vmcnt(3) +; GFX6-NEXT: buffer_store_dwordx4 v[5:8], off, s[0:3], 0 offset:32 +; GFX6-NEXT: s_waitcnt vmcnt(3) +; GFX6-NEXT: buffer_store_dwordx4 v[9:12], off, s[0:3], 0 offset:16 +; GFX6-NEXT: s_waitcnt vmcnt(3) +; GFX6-NEXT: buffer_store_dwordx4 v[13:16], off, s[0:3], 0 +; GFX6-NEXT: s_endpgm +; +; GFX7-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4 +; GFX7-NEXT: s_add_i32 s12, s12, s17 +; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:48 +; GFX7-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen offset:32 +; GFX7-NEXT: buffer_load_dwordx4 v[9:12], v0, s[0:3], 0 offen offset:16 +; GFX7-NEXT: buffer_load_dwordx4 v[13:16], v0, s[0:3], 0 offen +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_add_u32 s2, s0, 48 +; GFX7-NEXT: s_addc_u32 s3, s1, 0 +; GFX7-NEXT: v_mov_b32_e32 v20, s3 +; GFX7-NEXT: v_mov_b32_e32 v19, s2 +; GFX7-NEXT: s_add_u32 s2, s0, 32 +; GFX7-NEXT: s_addc_u32 s3, s1, 0 +; GFX7-NEXT: v_mov_b32_e32 v18, s1 +; GFX7-NEXT: v_mov_b32_e32 v17, s0 +; GFX7-NEXT: s_add_u32 s0, s0, 16 +; GFX7-NEXT: v_mov_b32_e32 v0, s2 +; GFX7-NEXT: s_addc_u32 s1, s1, 0 +; GFX7-NEXT: s_waitcnt vmcnt(3) +; GFX7-NEXT: flat_store_dwordx4 v[19:20], v[1:4] +; GFX7-NEXT: s_nop 0 +; GFX7-NEXT: v_mov_b32_e32 v1, s3 +; GFX7-NEXT: v_mov_b32_e32 v3, s1 +; GFX7-NEXT: v_mov_b32_e32 v2, s0 +; GFX7-NEXT: s_waitcnt vmcnt(3) +; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[5:8] +; GFX7-NEXT: s_waitcnt vmcnt(3) +; GFX7-NEXT: flat_store_dwordx4 v[2:3], v[9:12] +; GFX7-NEXT: s_waitcnt vmcnt(3) +; GFX7-NEXT: flat_store_dwordx4 v[17:18], v[13:16] +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX8-NEXT: s_add_i32 s12, s12, s17 +; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:48 +; GFX8-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen offset:32 +; GFX8-NEXT: buffer_load_dwordx4 v[9:12], v0, s[0:3], 0 offen offset:16 +; GFX8-NEXT: buffer_load_dwordx4 v[13:16], v0, s[0:3], 0 offen +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_add_u32 s2, s0, 48 +; GFX8-NEXT: s_addc_u32 s3, s1, 0 +; GFX8-NEXT: v_mov_b32_e32 v20, s3 +; GFX8-NEXT: v_mov_b32_e32 v19, s2 +; GFX8-NEXT: s_add_u32 s2, s0, 32 +; GFX8-NEXT: s_addc_u32 s3, s1, 0 +; GFX8-NEXT: v_mov_b32_e32 v18, s1 +; GFX8-NEXT: v_mov_b32_e32 v17, s0 +; GFX8-NEXT: s_add_u32 s0, s0, 16 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: s_addc_u32 s1, s1, 0 +; GFX8-NEXT: s_waitcnt vmcnt(3) +; GFX8-NEXT: flat_store_dwordx4 v[19:20], v[1:4] +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: s_waitcnt vmcnt(3) +; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[5:8] +; GFX8-NEXT: s_waitcnt vmcnt(3) +; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[9:12] +; GFX8-NEXT: s_waitcnt vmcnt(3) +; GFX8-NEXT: flat_store_dwordx4 v[17:18], v[13:16] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:48 +; GFX9-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen offset:32 +; GFX9-NEXT: buffer_load_dwordx4 v[9:12], v0, s[0:3], 0 offen offset:16 +; GFX9-NEXT: buffer_load_dwordx4 v[13:16], v0, s[0:3], 0 offen +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt vmcnt(3) lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1] offset:48 +; GFX9-NEXT: s_waitcnt vmcnt(3) +; GFX9-NEXT: global_store_dwordx4 v0, v[5:8], s[0:1] offset:32 +; GFX9-NEXT: s_waitcnt vmcnt(3) +; GFX9-NEXT: global_store_dwordx4 v0, v[9:12], s[0:1] offset:16 +; GFX9-NEXT: s_waitcnt vmcnt(3) +; GFX9-NEXT: global_store_dwordx4 v0, v[13:16], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_clause 0x3 +; GFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:48 +; GFX10-NEXT: buffer_load_dwordx4 v[5:8], v0, s[0:3], 0 offen offset:32 +; GFX10-NEXT: buffer_load_dwordx4 v[9:12], v0, s[0:3], 0 offen offset:16 +; GFX10-NEXT: buffer_load_dwordx4 v[13:16], v0, s[0:3], 0 offen +; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0) +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(0) +; GFX10-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1] offset:48 +; GFX10-NEXT: s_waitcnt vmcnt(2) +; GFX10-NEXT: global_store_dwordx4 v0, v[5:8], s[0:1] offset:32 +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: global_store_dwordx4 v0, v[9:12], s[0:1] offset:16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_store_dwordx4 v0, v[13:16], s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX11-NEXT: v_and_b32_e32 v12, 0x3ff, v0 +; GFX11-NEXT: v_mov_b32_e32 v16, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: buffer_load_b128 v[0:3], v12, s[0:3], 0 offen offset:48 +; GFX11-NEXT: buffer_load_b128 v[4:7], v12, s[0:3], 0 offen offset:32 +; GFX11-NEXT: buffer_load_b128 v[8:11], v12, s[0:3], 0 offen offset:16 +; GFX11-NEXT: buffer_load_b128 v[12:15], v12, s[0:3], 0 offen +; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-NEXT: s_waitcnt vmcnt(3) lgkmcnt(0) +; GFX11-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48 +; GFX11-NEXT: s_waitcnt vmcnt(2) +; GFX11-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32 +; GFX11-NEXT: s_waitcnt vmcnt(1) +; GFX11-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: global_store_b128 v16, v[12:15], s[0:1] +; GFX11-NEXT: s_endpgm +; +; GFX1200-SDAG-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX1200-SDAG: ; %bb.0: +; GFX1200-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-SDAG-NEXT: v_and_b32_e32 v12, 0x3ff, v0 +; GFX1200-SDAG-NEXT: v_mov_b32_e32 v16, 0 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: s_clause 0x3 +; GFX1200-SDAG-NEXT: buffer_load_b128 v[0:3], v12, s[0:3], null offen offset:48 +; GFX1200-SDAG-NEXT: buffer_load_b128 v[4:7], v12, s[0:3], null offen offset:32 +; GFX1200-SDAG-NEXT: buffer_load_b128 v[8:11], v12, s[0:3], null offen offset:16 +; GFX1200-SDAG-NEXT: buffer_load_b128 v[12:15], v12, s[0:3], null offen +; GFX1200-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX1200-SDAG-NEXT: s_wait_loadcnt 0x3 +; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1200-SDAG-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48 +; GFX1200-SDAG-NEXT: s_wait_loadcnt 0x2 +; GFX1200-SDAG-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32 +; GFX1200-SDAG-NEXT: s_wait_loadcnt 0x1 +; GFX1200-SDAG-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16 +; GFX1200-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX1200-SDAG-NEXT: global_store_b128 v16, v[12:15], s[0:1] +; GFX1200-SDAG-NEXT: s_endpgm +; +; GFX1200-GISEL-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX1200-GISEL: ; %bb.0: +; GFX1200-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 +; GFX1200-GISEL-NEXT: v_and_b32_e32 v12, 0x3ff, v0 +; GFX1200-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 +; GFX1200-GISEL-NEXT: v_mov_b32_e32 v16, 0 +; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1200-GISEL-NEXT: s_clause 0x3 +; GFX1200-GISEL-NEXT: buffer_load_b128 v[0:3], v12, s[0:3], null offen +; GFX1200-GISEL-NEXT: buffer_load_b128 v[4:7], v12, s[0:3], null offen offset:16 +; GFX1200-GISEL-NEXT: buffer_load_b128 v[8:11], v12, s[0:3], null offen offset:32 +; GFX1200-GISEL-NEXT: buffer_load_b128 v[12:15], v12, s[0:3], null offen offset:48 +; GFX1200-GISEL-NEXT: s_wait_loadcnt 0x3 +; GFX1200-GISEL-NEXT: global_store_b128 v16, v[0:3], s[4:5] +; GFX1200-GISEL-NEXT: s_wait_loadcnt 0x2 +; GFX1200-GISEL-NEXT: global_store_b128 v16, v[4:7], s[4:5] offset:16 +; GFX1200-GISEL-NEXT: s_wait_loadcnt 0x1 +; GFX1200-GISEL-NEXT: global_store_b128 v16, v[8:11], s[4:5] offset:32 +; GFX1200-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX1200-GISEL-NEXT: global_store_b128 v16, v[12:15], s[4:5] offset:48 +; GFX1200-GISEL-NEXT: s_endpgm +; +; GFX1250-SDAG-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: global_wb +; GFX1250-SDAG-NEXT: v_nop +; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-SDAG-NEXT: v_and_b32_e32 v16, 0x3ff, v0 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: s_clause 0x3 +; GFX1250-SDAG-NEXT: buffer_load_b128 v[0:3], v16, s[0:3], null offen offset:48 nv +; GFX1250-SDAG-NEXT: buffer_load_b128 v[4:7], v16, s[0:3], null offen offset:32 nv +; GFX1250-SDAG-NEXT: buffer_load_b128 v[8:11], v16, s[0:3], null offen offset:16 nv +; GFX1250-SDAG-NEXT: buffer_load_b128 v[12:15], v16, s[0:3], null offen nv +; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v16, 0 +; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x3 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48 +; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x2 +; GFX1250-SDAG-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32 +; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x1 +; GFX1250-SDAG-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16 +; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-NEXT: global_store_b128 v16, v[12:15], s[0:1] +; GFX1250-SDAG-NEXT: s_endpgm +; +; GFX1250-GISEL-LABEL: ptr_s_buffer_load_v16i32_divergent_offset: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: global_wb +; GFX1250-GISEL-NEXT: v_nop +; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x10 nv +; GFX1250-GISEL-NEXT: v_and_b32_e32 v16, 0x3ff, v0 +; GFX1250-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 nv +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: s_clause 0x3 +; GFX1250-GISEL-NEXT: buffer_load_b128 v[0:3], v16, s[0:3], null offen nv +; GFX1250-GISEL-NEXT: buffer_load_b128 v[4:7], v16, s[0:3], null offen offset:16 nv +; GFX1250-GISEL-NEXT: buffer_load_b128 v[8:11], v16, s[0:3], null offen offset:32 nv +; GFX1250-GISEL-NEXT: buffer_load_b128 v[12:15], v16, s[0:3], null offen offset:48 nv +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v16, 0 +; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x3 +; GFX1250-GISEL-NEXT: global_store_b128 v16, v[0:3], s[4:5] +; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x2 +; GFX1250-GISEL-NEXT: global_store_b128 v16, v[4:7], s[4:5] offset:16 +; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x1 +; GFX1250-GISEL-NEXT: global_store_b128 v16, v[8:11], s[4:5] offset:32 +; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX1250-GISEL-NEXT: global_store_b128 v16, v[12:15], s[4:5] offset:48 +; GFX1250-GISEL-NEXT: s_endpgm + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %load = call <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8) %rsrc, i32 %tid, i32 0), !invariant.load !0 + store <16 x i32> %load, ptr addrspace(1) %out + ret void +} + +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) nocapture readonly, i32, i32 immarg) +declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) nocapture readonly, i32, i32 immarg) +declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) nocapture readonly, i32, i32 immarg) +declare <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8) nocapture readonly, i32, i32 immarg) +declare <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8) nocapture readonly, i32, i32 immarg) +declare i32 @llvm.amdgcn.workitem.id.x() + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll index 219eda3f1c23d..ac8d9350de437 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll @@ -86,7 +86,7 @@ define amdgpu_kernel void @set_inactive_imm_poison_64(ptr addrspace(1) %out) { ret void } -define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, <4 x i32> inreg %desc) { +define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, ptr addrspace(8) inreg %desc) { ; GCN-LABEL: set_inactive_scc: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 @@ -120,7 +120,7 @@ define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, <4 x ; GCN-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; GCN-NEXT: .LBB4_4: ; %.exit ; GCN-NEXT: s_endpgm - %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0) + %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 0, i32 0), !invariant.load !{} %cmp = icmp eq i32 %val, 56 %tmp.0 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0 %tmp = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp.0) @@ -509,7 +509,7 @@ declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0 declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64) #0 declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #1 declare i64 @llvm.amdgcn.strict.wwm.i64(i64) #1 -declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32) +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32) attributes #0 = { convergent readnone } attributes #1 = { convergent nounwind readnone speculatable willreturn } diff --git a/llvm/test/CodeGen/AMDGPU/ptr-s-buffer-load-mmo-offsets.ll b/llvm/test/CodeGen/AMDGPU/ptr-s-buffer-load-mmo-offsets.ll new file mode 100644 index 0000000000000..07b8b7c795f07 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/ptr-s-buffer-load-mmo-offsets.ll @@ -0,0 +1,113 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=finalize-isel -o - %s | FileCheck %s + +; Verify that wide ptr_s_buffer_load with divergent (VGPR) offset correctly splits +; into multiple 128-bit MUBUF chunks, and that each chunk carries the right +; MachineMemOperand size (s128, not the full load size) and offset (+0, +16, ...). + +; 256-bit load with divergent offset splits into 2 x 128-bit MUBUF loads. +; Each chunk must have MMO size s128 and correct offset (+0, +16). +define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset) { + ; CHECK-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr5 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0 + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY3]], %subreg.sub1 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE1]].sub1 + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE1]].sub0 + ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY8]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, killed [[COPY6]], %subreg.sub2, killed [[COPY5]], %subreg.sub3 + ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE2]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE2]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub0 + ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub1 + ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub2 + ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub3 + ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]].sub0 + ; CHECK-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]].sub1 + ; CHECK-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]].sub2 + ; CHECK-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]].sub3 + ; CHECK-NEXT: $vgpr0 = COPY [[COPY9]] + ; CHECK-NEXT: $vgpr1 = COPY [[COPY10]] + ; CHECK-NEXT: $vgpr2 = COPY [[COPY11]] + ; CHECK-NEXT: $vgpr3 = COPY [[COPY12]] + ; CHECK-NEXT: $vgpr4 = COPY [[COPY13]] + ; CHECK-NEXT: $vgpr5 = COPY [[COPY14]] + ; CHECK-NEXT: $vgpr6 = COPY [[COPY15]] + ; CHECK-NEXT: $vgpr7 = COPY [[COPY16]] + ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + ret <8 x float> %val +} + +; 512-bit load with divergent offset splits into 4 x 128-bit MUBUF loads. +; Each chunk must have MMO size s128 and correct offset (+0, +16, +32, +48). +define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset) { + ; CHECK-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr5 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0 + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY3]], %subreg.sub1 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE1]].sub1 + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE1]].sub0 + ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY8]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, killed [[COPY6]], %subreg.sub2, killed [[COPY5]], %subreg.sub3 + ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE2]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) + ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE2]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) + ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE2]], $sgpr_null, 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) + ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE2]], $sgpr_null, 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) + ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub0 + ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub1 + ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub2 + ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub3 + ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]].sub0 + ; CHECK-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]].sub1 + ; CHECK-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]].sub2 + ; CHECK-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]].sub3 + ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]].sub0 + ; CHECK-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]].sub1 + ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]].sub2 + ; CHECK-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]].sub3 + ; CHECK-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]].sub0 + ; CHECK-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]].sub1 + ; CHECK-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]].sub2 + ; CHECK-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]].sub3 + ; CHECK-NEXT: $vgpr0 = COPY [[COPY9]] + ; CHECK-NEXT: $vgpr1 = COPY [[COPY10]] + ; CHECK-NEXT: $vgpr2 = COPY [[COPY11]] + ; CHECK-NEXT: $vgpr3 = COPY [[COPY12]] + ; CHECK-NEXT: $vgpr4 = COPY [[COPY13]] + ; CHECK-NEXT: $vgpr5 = COPY [[COPY14]] + ; CHECK-NEXT: $vgpr6 = COPY [[COPY15]] + ; CHECK-NEXT: $vgpr7 = COPY [[COPY16]] + ; CHECK-NEXT: $vgpr8 = COPY [[COPY17]] + ; CHECK-NEXT: $vgpr9 = COPY [[COPY18]] + ; CHECK-NEXT: $vgpr10 = COPY [[COPY19]] + ; CHECK-NEXT: $vgpr11 = COPY [[COPY20]] + ; CHECK-NEXT: $vgpr12 = COPY [[COPY21]] + ; CHECK-NEXT: $vgpr13 = COPY [[COPY22]] + ; CHECK-NEXT: $vgpr14 = COPY [[COPY23]] + ; CHECK-NEXT: $vgpr15 = COPY [[COPY24]] + ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 + %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0 + ret <16 x float> %val +} + +declare <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8), i32, i32 immarg) +declare <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8), i32, i32 immarg) + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll index f238ea361ba41..40d2be3051252 100644 --- a/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll +++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll @@ -238,16 +238,16 @@ define amdgpu_ps float @_amdgpu_ps_main() { ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog bb: - %i = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> zeroinitializer, i32 0, i32 0) + %i = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) null, i32 0, i32 0), !invariant.load !{} %i1 = bitcast i32 %i to float - %i2 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> zeroinitializer, i32 4, i32 0) + %i2 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) null, i32 4, i32 0), !invariant.load !{} %i3 = bitcast i32 %i2 to float %i4 = fmul contract float %i3, 4.0 %i5 = fadd contract float %i4, %i1 ret float %i5 } -declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) declare float @llvm.minnum.f32(float, float) declare float @llvm.maxnum.f32(float, float) declare half @llvm.minnum.f16(half, half) diff --git a/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll b/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll index 3dba3e87c64c1..ae6408adc940b 100644 --- a/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll @@ -25,9 +25,9 @@ define amdgpu_gs void @main(i32 inreg %arg) #0 { ; CHECK-NEXT: tbuffer_store_format_x v0, off, s[0:3], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_UINT] offset:92 glc slc ; CHECK-NEXT: s_endpgm main_body: - %tmp = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 20, i32 0) - %tmp1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 24, i32 0) - %tmp2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 48, i32 0) + %tmp = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) poison, i32 20, i32 0), !invariant.load !{} + %tmp1 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) poison, i32 24, i32 0), !invariant.load !{} + %tmp2 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) poison, i32 48, i32 0), !invariant.load !{} %array_vector3 = insertelement <4 x float> zeroinitializer, float %tmp2, i32 3 %array_vector5 = insertelement <4 x float> , float %tmp, i32 1 %array_vector6 = insertelement <4 x float> %array_vector5, float poison, i32 2 @@ -55,7 +55,7 @@ main_body: ret void } -declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32 immarg) #1 +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32 immarg) #1 declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32 immarg) #2 declare void @llvm.amdgcn.raw.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg, i32 immarg) #3 diff --git a/llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll b/llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll index 8e6fec0241a72..12b64e4c9a831 100644 --- a/llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll +++ b/llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll @@ -8,7 +8,7 @@ define amdgpu_ps void @_amdgpu_ps_main() { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3 - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM killed [[REG_SEQUENCE]], 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM killed [[REG_SEQUENCE]], 0, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) null`, align 1, addrspace 8) ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 ; CHECK-NEXT: nofpexcept S_CMP_NLT_F32 [[S_BUFFER_LOAD_DWORD_IMM]], [[S_MOV_B32_1]], implicit-def $scc, implicit $mode ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $scc @@ -23,7 +23,7 @@ define amdgpu_ps void @_amdgpu_ps_main() { ; CHECK-NEXT: bb.2.bb2: ; CHECK-NEXT: S_ENDPGM 0 entry: - %i = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> zeroinitializer, i32 0, i32 0) + %i = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) null, i32 0, i32 0), !invariant.load !{} %i1 = bitcast i32 %i to float %i2 = fcmp uge float %i1, 0.000000e+00 call void @llvm.amdgcn.kill(i1 %i2) diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-copy.ll b/llvm/test/CodeGen/AMDGPU/sgpr-copy.ll index e04657c032d1c..a39c81ca45e93 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/sgpr-copy.ll @@ -7,10 +7,10 @@ ; CHECK: s_xor_b32 s{{[0-9]}}, [[DST]] define amdgpu_ps void @phi1(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { main_body: - %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 - %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0) - %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0) - %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0) + %tmp20 = load ptr addrspace(8), ptr addrspace(4) %arg, !tbaa !0 + %tmp21 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 0, i32 0), !invariant.load !{} + %tmp22 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 16, i32 0), !invariant.load !{} + %tmp23 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 32, i32 0), !invariant.load !{} %tmp24 = fptosi float %tmp22 to i32 %tmp25 = icmp ne i32 %tmp24, 0 br i1 %tmp25, label %ENDIF, label %ELSE @@ -30,22 +30,22 @@ ENDIF: ; preds = %ELSE, %main_body ; CHECK-LABEL: {{^}}phi2: define amdgpu_ps void @phi2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 { main_body: - %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 - %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0) - %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0) - %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 36, i32 0) - %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 40, i32 0) - %tmp25 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 48, i32 0) - %tmp26 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 52, i32 0) - %tmp27 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 56, i32 0) - %tmp28 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 64, i32 0) - %tmp29 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 68, i32 0) - %tmp30 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 72, i32 0) - %tmp31 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 76, i32 0) - %tmp32 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 80, i32 0) - %tmp33 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 84, i32 0) - %tmp34 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 88, i32 0) - %tmp35 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 92, i32 0) + %tmp20 = load ptr addrspace(8), ptr addrspace(4) %arg, !tbaa !0 + %tmp21 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 16, i32 0), !invariant.load !{} + %tmp22 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 32, i32 0), !invariant.load !{} + %tmp23 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 36, i32 0), !invariant.load !{} + %tmp24 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 40, i32 0), !invariant.load !{} + %tmp25 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 48, i32 0), !invariant.load !{} + %tmp26 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 52, i32 0), !invariant.load !{} + %tmp27 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 56, i32 0), !invariant.load !{} + %tmp28 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 64, i32 0), !invariant.load !{} + %tmp29 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 68, i32 0), !invariant.load !{} + %tmp30 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 72, i32 0), !invariant.load !{} + %tmp31 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 76, i32 0), !invariant.load !{} + %tmp32 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 80, i32 0), !invariant.load !{} + %tmp33 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 84, i32 0), !invariant.load !{} + %tmp34 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 88, i32 0), !invariant.load !{} + %tmp35 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 92, i32 0), !invariant.load !{} %tmp37 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !0 %tmp39 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !0 %i.i = extractelement <2 x i32> %arg5, i32 0 @@ -167,11 +167,11 @@ ENDIF24: ; preds = %IF25, %ENDIF ; CHECK-LABEL: {{^}}loop: define amdgpu_ps void @loop(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { main_body: - %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 - %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0) - %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 4, i32 0) - %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 8, i32 0) - %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 12, i32 0) + %tmp20 = load ptr addrspace(8), ptr addrspace(4) %arg, !tbaa !0 + %tmp21 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 0, i32 0), !invariant.load !{} + %tmp22 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 4, i32 0), !invariant.load !{} + %tmp23 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 8, i32 0), !invariant.load !{} + %tmp24 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp20, i32 12, i32 0), !invariant.load !{} %tmp25 = fptosi float %tmp24 to i32 %tmp26 = bitcast i32 %tmp25 to float %tmp27 = bitcast float %tmp26 to i32 @@ -218,8 +218,8 @@ ENDIF: ; preds = %LOOP ; CHECK: s_endpgm define amdgpu_ps void @sample_v3(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { entry: - %tmp21 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 - %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 16, i32 0) + %tmp21 = load ptr addrspace(8), ptr addrspace(4) %arg, !tbaa !0 + %tmp22 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 16, i32 0), !invariant.load !{} %tmp24 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !0 %tmp26 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !0 %tmp27 = fcmp oeq float %tmp22, 0.000000e+00 @@ -316,8 +316,8 @@ ENDIF69: ; preds = %LOOP68 ; CHECK: s_endpgm define amdgpu_ps void @sample_rsrc(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { bb: - %tmp22 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !3 - %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp22, i32 16, i32 0) + %tmp22 = load ptr addrspace(8), ptr addrspace(4) %arg1, !tbaa !3 + %tmp23 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp22, i32 16, i32 0), !invariant.load !{} %tmp26 = load <8 x i32>, ptr addrspace(4) %arg3, !tbaa !3 %tmp28 = load <4 x i32>, ptr addrspace(4) %arg2, !tbaa !3 %i.i = extractelement <2 x i32> %arg7, i32 0 @@ -399,7 +399,7 @@ declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1 declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 -declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1 +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32) #1 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/AMDGPU/si-scheduler.ll b/llvm/test/CodeGen/AMDGPU/si-scheduler.ll index 516fabce9c1cb..21f5769ed148c 100644 --- a/llvm/test/CodeGen/AMDGPU/si-scheduler.ll +++ b/llvm/test/CodeGen/AMDGPU/si-scheduler.ll @@ -69,8 +69,8 @@ define amdgpu_ps void @_amdgpu_ps_main(i32 %arg) local_unnamed_addr { %tmp = insertelement <2 x i32> zeroinitializer, i32 %arg, i32 0 %tmp1 = bitcast <2 x i32> %tmp to i64 %tmp2 = inttoptr i64 %tmp1 to ptr addrspace(4) - %tmp3 = load <4 x i32>, ptr addrspace(4) %tmp2, align 16 - %tmp4 = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp3, i32 0, i32 0) #0 + %tmp3 = load ptr addrspace(8), ptr addrspace(4) %tmp2, align 16 + %tmp4 = tail call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %tmp3, i32 0, i32 0) #0, !invariant.load !{} switch i32 %tmp4, label %bb [ i32 0, label %bb5 i32 1, label %bb6 @@ -87,4 +87,4 @@ bb6: ; preds = %.entry } ; Function Attrs: nounwind readnone -declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) #1 +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) #1 diff --git a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll index d564e745f4506..05a9ff3b789b2 100644 --- a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll @@ -34,45 +34,45 @@ define amdgpu_ps void @main(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) { main_body: %lds = inttoptr i32 0 to ptr addrspace(3) - %tmp21 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 - %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 96, i32 0) - %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 100, i32 0) - %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 104, i32 0) - %tmp25 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 112, i32 0) - %tmp26 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 116, i32 0) - %tmp27 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 120, i32 0) - %tmp28 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 128, i32 0) - %tmp29 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 132, i32 0) - %tmp30 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 140, i32 0) - %tmp31 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 144, i32 0) - %tmp32 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 160, i32 0) - %tmp33 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 176, i32 0) - %tmp34 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 180, i32 0) - %tmp35 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 184, i32 0) - %tmp36 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 192, i32 0) - %tmp37 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 196, i32 0) - %tmp38 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 200, i32 0) - %tmp39 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 208, i32 0) - %tmp40 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 212, i32 0) - %tmp41 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 216, i32 0) - %tmp42 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 224, i32 0) - %tmp43 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 240, i32 0) - %tmp44 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 244, i32 0) - %tmp45 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 248, i32 0) - %tmp46 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 256, i32 0) - %tmp47 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 272, i32 0) - %tmp48 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 276, i32 0) - %tmp49 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 280, i32 0) - %tmp50 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 288, i32 0) - %tmp51 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 292, i32 0) - %tmp52 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 296, i32 0) - %tmp53 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 304, i32 0) - %tmp54 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 308, i32 0) - %tmp55 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 312, i32 0) - %tmp56 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 368, i32 0) - %tmp57 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 372, i32 0) - %tmp58 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 376, i32 0) - %tmp59 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 384, i32 0) + %tmp21 = load ptr addrspace(8), ptr addrspace(4) %arg, !tbaa !0 + %tmp22 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 96, i32 0), !invariant.load !{} + %tmp23 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 100, i32 0), !invariant.load !{} + %tmp24 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 104, i32 0), !invariant.load !{} + %tmp25 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 112, i32 0), !invariant.load !{} + %tmp26 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 116, i32 0), !invariant.load !{} + %tmp27 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 120, i32 0), !invariant.load !{} + %tmp28 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 128, i32 0), !invariant.load !{} + %tmp29 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 132, i32 0), !invariant.load !{} + %tmp30 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 140, i32 0), !invariant.load !{} + %tmp31 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 144, i32 0), !invariant.load !{} + %tmp32 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 160, i32 0), !invariant.load !{} + %tmp33 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 176, i32 0), !invariant.load !{} + %tmp34 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 180, i32 0), !invariant.load !{} + %tmp35 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 184, i32 0), !invariant.load !{} + %tmp36 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 192, i32 0), !invariant.load !{} + %tmp37 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 196, i32 0), !invariant.load !{} + %tmp38 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 200, i32 0), !invariant.load !{} + %tmp39 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 208, i32 0), !invariant.load !{} + %tmp40 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 212, i32 0), !invariant.load !{} + %tmp41 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 216, i32 0), !invariant.load !{} + %tmp42 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 224, i32 0), !invariant.load !{} + %tmp43 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 240, i32 0), !invariant.load !{} + %tmp44 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 244, i32 0), !invariant.load !{} + %tmp45 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 248, i32 0), !invariant.load !{} + %tmp46 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 256, i32 0), !invariant.load !{} + %tmp47 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 272, i32 0), !invariant.load !{} + %tmp48 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 276, i32 0), !invariant.load !{} + %tmp49 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 280, i32 0), !invariant.load !{} + %tmp50 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 288, i32 0), !invariant.load !{} + %tmp51 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 292, i32 0), !invariant.load !{} + %tmp52 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 296, i32 0), !invariant.load !{} + %tmp53 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 304, i32 0), !invariant.load !{} + %tmp54 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 308, i32 0), !invariant.load !{} + %tmp55 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 312, i32 0), !invariant.load !{} + %tmp56 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 368, i32 0), !invariant.load !{} + %tmp57 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 372, i32 0), !invariant.load !{} + %tmp58 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 376, i32 0), !invariant.load !{} + %tmp59 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 384, i32 0), !invariant.load !{} %tmp61 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !0 %tmp63 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !0 %tmp63.bc = bitcast <4 x i32> %tmp63 to <4 x i32> @@ -650,110 +650,110 @@ ENDIF66: ; preds = %LOOP65 ; TOVGPR: ScratchSize: 0{{$}} define amdgpu_ps void @main1(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { main_body: - %tmp21 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 - %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 0, i32 0) - %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 4, i32 0) - %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 8, i32 0) - %tmp25 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 12, i32 0) - %tmp26 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 28, i32 0) - %tmp27 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 48, i32 0) - %tmp28 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 52, i32 0) - %tmp29 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 56, i32 0) - %tmp30 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 64, i32 0) - %tmp31 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 68, i32 0) - %tmp32 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 72, i32 0) - %tmp33 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 76, i32 0) - %tmp34 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 128, i32 0) - %tmp35 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 132, i32 0) - %tmp36 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 144, i32 0) - %tmp37 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 148, i32 0) - %tmp38 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 152, i32 0) - %tmp39 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 160, i32 0) - %tmp40 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 164, i32 0) - %tmp41 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 168, i32 0) - %tmp42 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 172, i32 0) - %tmp43 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 176, i32 0) - %tmp44 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 180, i32 0) - %tmp45 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 184, i32 0) - %tmp46 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 192, i32 0) - %tmp47 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 196, i32 0) - %tmp48 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 200, i32 0) - %tmp49 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 208, i32 0) - %tmp50 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 212, i32 0) - %tmp51 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 216, i32 0) - %tmp52 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 220, i32 0) - %tmp53 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 236, i32 0) - %tmp54 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 240, i32 0) - %tmp55 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 244, i32 0) - %tmp56 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 248, i32 0) - %tmp57 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 252, i32 0) - %tmp58 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 256, i32 0) - %tmp59 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 260, i32 0) - %tmp60 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 264, i32 0) - %tmp61 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 268, i32 0) - %tmp62 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 272, i32 0) - %tmp63 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 276, i32 0) - %tmp64 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 280, i32 0) - %tmp65 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 284, i32 0) - %tmp66 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 288, i32 0) - %tmp67 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 292, i32 0) - %tmp68 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 464, i32 0) - %tmp69 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 468, i32 0) - %tmp70 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 472, i32 0) - %tmp71 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 496, i32 0) - %tmp72 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 500, i32 0) - %tmp73 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 504, i32 0) - %tmp74 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 512, i32 0) - %tmp75 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 516, i32 0) - %tmp76 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 524, i32 0) - %tmp77 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 532, i32 0) - %tmp78 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 536, i32 0) - %tmp79 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 540, i32 0) - %tmp80 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 544, i32 0) - %tmp81 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 548, i32 0) - %tmp82 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 552, i32 0) - %tmp83 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 556, i32 0) - %tmp84 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 560, i32 0) - %tmp85 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 564, i32 0) - %tmp86 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 568, i32 0) - %tmp87 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 572, i32 0) - %tmp88 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 576, i32 0) - %tmp89 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 580, i32 0) - %tmp90 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 584, i32 0) - %tmp91 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 588, i32 0) - %tmp92 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 592, i32 0) - %tmp93 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 596, i32 0) - %tmp94 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 600, i32 0) - %tmp95 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 604, i32 0) - %tmp96 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 608, i32 0) - %tmp97 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 612, i32 0) - %tmp98 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 616, i32 0) - %tmp99 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 624, i32 0) - %tmp100 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 628, i32 0) - %tmp101 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 632, i32 0) - %tmp102 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 636, i32 0) - %tmp103 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 640, i32 0) - %tmp104 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 644, i32 0) - %tmp105 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 648, i32 0) - %tmp106 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 652, i32 0) - %tmp107 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 656, i32 0) - %tmp108 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 660, i32 0) - %tmp109 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 664, i32 0) - %tmp110 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 668, i32 0) - %tmp111 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 672, i32 0) - %tmp112 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 676, i32 0) - %tmp113 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 680, i32 0) - %tmp114 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 684, i32 0) - %tmp115 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 688, i32 0) - %tmp116 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 692, i32 0) - %tmp117 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 696, i32 0) - %tmp118 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 700, i32 0) - %tmp119 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 704, i32 0) - %tmp120 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 708, i32 0) - %tmp121 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 712, i32 0) - %tmp122 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 716, i32 0) - %tmp123 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 864, i32 0) - %tmp124 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 868, i32 0) + %tmp21 = load ptr addrspace(8), ptr addrspace(4) %arg, !tbaa !0 + %tmp22 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 0, i32 0), !invariant.load !{} + %tmp23 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 4, i32 0), !invariant.load !{} + %tmp24 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 8, i32 0), !invariant.load !{} + %tmp25 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 12, i32 0), !invariant.load !{} + %tmp26 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 28, i32 0), !invariant.load !{} + %tmp27 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 48, i32 0), !invariant.load !{} + %tmp28 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 52, i32 0), !invariant.load !{} + %tmp29 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 56, i32 0), !invariant.load !{} + %tmp30 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 64, i32 0), !invariant.load !{} + %tmp31 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 68, i32 0), !invariant.load !{} + %tmp32 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 72, i32 0), !invariant.load !{} + %tmp33 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 76, i32 0), !invariant.load !{} + %tmp34 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 128, i32 0), !invariant.load !{} + %tmp35 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 132, i32 0), !invariant.load !{} + %tmp36 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 144, i32 0), !invariant.load !{} + %tmp37 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 148, i32 0), !invariant.load !{} + %tmp38 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 152, i32 0), !invariant.load !{} + %tmp39 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 160, i32 0), !invariant.load !{} + %tmp40 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 164, i32 0), !invariant.load !{} + %tmp41 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 168, i32 0), !invariant.load !{} + %tmp42 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 172, i32 0), !invariant.load !{} + %tmp43 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 176, i32 0), !invariant.load !{} + %tmp44 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 180, i32 0), !invariant.load !{} + %tmp45 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 184, i32 0), !invariant.load !{} + %tmp46 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 192, i32 0), !invariant.load !{} + %tmp47 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 196, i32 0), !invariant.load !{} + %tmp48 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 200, i32 0), !invariant.load !{} + %tmp49 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 208, i32 0), !invariant.load !{} + %tmp50 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 212, i32 0), !invariant.load !{} + %tmp51 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 216, i32 0), !invariant.load !{} + %tmp52 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 220, i32 0), !invariant.load !{} + %tmp53 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 236, i32 0), !invariant.load !{} + %tmp54 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 240, i32 0), !invariant.load !{} + %tmp55 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 244, i32 0), !invariant.load !{} + %tmp56 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 248, i32 0), !invariant.load !{} + %tmp57 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 252, i32 0), !invariant.load !{} + %tmp58 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 256, i32 0), !invariant.load !{} + %tmp59 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 260, i32 0), !invariant.load !{} + %tmp60 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 264, i32 0), !invariant.load !{} + %tmp61 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 268, i32 0), !invariant.load !{} + %tmp62 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 272, i32 0), !invariant.load !{} + %tmp63 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 276, i32 0), !invariant.load !{} + %tmp64 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 280, i32 0), !invariant.load !{} + %tmp65 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 284, i32 0), !invariant.load !{} + %tmp66 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 288, i32 0), !invariant.load !{} + %tmp67 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 292, i32 0), !invariant.load !{} + %tmp68 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 464, i32 0), !invariant.load !{} + %tmp69 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 468, i32 0), !invariant.load !{} + %tmp70 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 472, i32 0), !invariant.load !{} + %tmp71 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 496, i32 0), !invariant.load !{} + %tmp72 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 500, i32 0), !invariant.load !{} + %tmp73 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 504, i32 0), !invariant.load !{} + %tmp74 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 512, i32 0), !invariant.load !{} + %tmp75 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 516, i32 0), !invariant.load !{} + %tmp76 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 524, i32 0), !invariant.load !{} + %tmp77 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 532, i32 0), !invariant.load !{} + %tmp78 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 536, i32 0), !invariant.load !{} + %tmp79 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 540, i32 0), !invariant.load !{} + %tmp80 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 544, i32 0), !invariant.load !{} + %tmp81 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 548, i32 0), !invariant.load !{} + %tmp82 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 552, i32 0), !invariant.load !{} + %tmp83 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 556, i32 0), !invariant.load !{} + %tmp84 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 560, i32 0), !invariant.load !{} + %tmp85 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 564, i32 0), !invariant.load !{} + %tmp86 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 568, i32 0), !invariant.load !{} + %tmp87 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 572, i32 0), !invariant.load !{} + %tmp88 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 576, i32 0), !invariant.load !{} + %tmp89 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 580, i32 0), !invariant.load !{} + %tmp90 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 584, i32 0), !invariant.load !{} + %tmp91 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 588, i32 0), !invariant.load !{} + %tmp92 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 592, i32 0), !invariant.load !{} + %tmp93 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 596, i32 0), !invariant.load !{} + %tmp94 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 600, i32 0), !invariant.load !{} + %tmp95 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 604, i32 0), !invariant.load !{} + %tmp96 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 608, i32 0), !invariant.load !{} + %tmp97 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 612, i32 0), !invariant.load !{} + %tmp98 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 616, i32 0), !invariant.load !{} + %tmp99 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 624, i32 0), !invariant.load !{} + %tmp100 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 628, i32 0), !invariant.load !{} + %tmp101 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 632, i32 0), !invariant.load !{} + %tmp102 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 636, i32 0), !invariant.load !{} + %tmp103 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 640, i32 0), !invariant.load !{} + %tmp104 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 644, i32 0), !invariant.load !{} + %tmp105 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 648, i32 0), !invariant.load !{} + %tmp106 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 652, i32 0), !invariant.load !{} + %tmp107 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 656, i32 0), !invariant.load !{} + %tmp108 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 660, i32 0), !invariant.load !{} + %tmp109 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 664, i32 0), !invariant.load !{} + %tmp110 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 668, i32 0), !invariant.load !{} + %tmp111 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 672, i32 0), !invariant.load !{} + %tmp112 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 676, i32 0), !invariant.load !{} + %tmp113 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 680, i32 0), !invariant.load !{} + %tmp114 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 684, i32 0), !invariant.load !{} + %tmp115 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 688, i32 0), !invariant.load !{} + %tmp116 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 692, i32 0), !invariant.load !{} + %tmp117 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 696, i32 0), !invariant.load !{} + %tmp118 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 700, i32 0), !invariant.load !{} + %tmp119 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 704, i32 0), !invariant.load !{} + %tmp120 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 708, i32 0), !invariant.load !{} + %tmp121 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 712, i32 0), !invariant.load !{} + %tmp122 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 716, i32 0), !invariant.load !{} + %tmp123 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 864, i32 0), !invariant.load !{} + %tmp124 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp21, i32 868, i32 0), !invariant.load !{} %tmp126 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !0 %tmp128 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !0 %tmp129 = getelementptr [16 x <8 x i32>], ptr addrspace(4) %arg2, i64 0, i32 1 @@ -1685,7 +1685,7 @@ declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 declare <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 declare <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 -declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1 +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32) #1 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll b/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll index 25faee2a9b274..f37d15fc0bafa 100644 --- a/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll +++ b/llvm/test/CodeGen/AMDGPU/si-spill-cf.ll @@ -7,75 +7,75 @@ ; SI: s_or_b64 exec, exec, [[SAVED:s\[[0-9]+:[0-9]+\]|[a-z]+]] ; SI-NOT: v_readlane_b32 [[SAVED]] -define amdgpu_ps void @main(<4 x i32> inreg %rsrc) #0 { +define amdgpu_ps void @main(ptr addrspace(8) inreg %rsrc) #0 { main_body: - %tmp = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0) - %tmp1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0) - %tmp2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 80, i32 0) - %tmp3 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 84, i32 0) - %tmp4 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 88, i32 0) - %tmp5 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 96, i32 0) - %tmp6 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 100, i32 0) - %tmp7 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 104, i32 0) - %tmp8 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 112, i32 0) - %tmp9 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 116, i32 0) - %tmp10 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 120, i32 0) - %tmp11 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 128, i32 0) - %tmp12 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 132, i32 0) - %tmp13 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 136, i32 0) - %tmp14 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 144, i32 0) - %tmp15 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 148, i32 0) - %tmp16 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 152, i32 0) - %tmp17 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 160, i32 0) - %tmp18 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 164, i32 0) - %tmp19 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 168, i32 0) - %tmp20 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 176, i32 0) - %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 180, i32 0) - %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 184, i32 0) - %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 192, i32 0) - %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 196, i32 0) - %tmp25 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 200, i32 0) - %tmp26 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 208, i32 0) - %tmp27 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 212, i32 0) - %tmp28 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 216, i32 0) - %tmp29 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 224, i32 0) - %tmp30 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 228, i32 0) - %tmp31 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 232, i32 0) - %tmp32 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 240, i32 0) - %tmp33 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 244, i32 0) - %tmp34 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 248, i32 0) - %tmp35 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 256, i32 0) - %tmp36 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 260, i32 0) - %tmp37 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 264, i32 0) - %tmp38 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 272, i32 0) - %tmp39 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 276, i32 0) - %tmp40 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 280, i32 0) - %tmp41 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 288, i32 0) - %tmp42 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 292, i32 0) - %tmp43 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 296, i32 0) - %tmp44 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 304, i32 0) - %tmp45 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 308, i32 0) - %tmp46 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 312, i32 0) - %tmp47 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 320, i32 0) - %tmp48 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 324, i32 0) - %tmp49 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 328, i32 0) - %tmp50 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 336, i32 0) - %tmp51 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 340, i32 0) - %tmp52 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 344, i32 0) - %tmp53 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 352, i32 0) - %tmp54 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 356, i32 0) - %tmp55 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 360, i32 0) - %tmp56 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 368, i32 0) - %tmp57 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 372, i32 0) - %tmp58 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 376, i32 0) - %tmp59 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 384, i32 0) - %tmp60 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 388, i32 0) - %tmp61 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 392, i32 0) - %tmp62 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 400, i32 0) - %tmp63 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 404, i32 0) - %tmp64 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 408, i32 0) - %tmp65 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 416, i32 0) - %tmp66 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 420, i32 0) + %tmp = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 16, i32 0), !invariant.load !{} + %tmp1 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0), !invariant.load !{} + %tmp2 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 80, i32 0), !invariant.load !{} + %tmp3 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 84, i32 0), !invariant.load !{} + %tmp4 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 88, i32 0), !invariant.load !{} + %tmp5 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 96, i32 0), !invariant.load !{} + %tmp6 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 100, i32 0), !invariant.load !{} + %tmp7 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 104, i32 0), !invariant.load !{} + %tmp8 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 112, i32 0), !invariant.load !{} + %tmp9 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 116, i32 0), !invariant.load !{} + %tmp10 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 120, i32 0), !invariant.load !{} + %tmp11 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 128, i32 0), !invariant.load !{} + %tmp12 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 132, i32 0), !invariant.load !{} + %tmp13 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 136, i32 0), !invariant.load !{} + %tmp14 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 144, i32 0), !invariant.load !{} + %tmp15 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 148, i32 0), !invariant.load !{} + %tmp16 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 152, i32 0), !invariant.load !{} + %tmp17 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 160, i32 0), !invariant.load !{} + %tmp18 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 164, i32 0), !invariant.load !{} + %tmp19 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 168, i32 0), !invariant.load !{} + %tmp20 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 176, i32 0), !invariant.load !{} + %tmp21 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 180, i32 0), !invariant.load !{} + %tmp22 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 184, i32 0), !invariant.load !{} + %tmp23 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 192, i32 0), !invariant.load !{} + %tmp24 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 196, i32 0), !invariant.load !{} + %tmp25 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 200, i32 0), !invariant.load !{} + %tmp26 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 208, i32 0), !invariant.load !{} + %tmp27 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 212, i32 0), !invariant.load !{} + %tmp28 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 216, i32 0), !invariant.load !{} + %tmp29 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 224, i32 0), !invariant.load !{} + %tmp30 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 228, i32 0), !invariant.load !{} + %tmp31 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 232, i32 0), !invariant.load !{} + %tmp32 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 240, i32 0), !invariant.load !{} + %tmp33 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 244, i32 0), !invariant.load !{} + %tmp34 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 248, i32 0), !invariant.load !{} + %tmp35 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 256, i32 0), !invariant.load !{} + %tmp36 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 260, i32 0), !invariant.load !{} + %tmp37 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 264, i32 0), !invariant.load !{} + %tmp38 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 272, i32 0), !invariant.load !{} + %tmp39 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 276, i32 0), !invariant.load !{} + %tmp40 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 280, i32 0), !invariant.load !{} + %tmp41 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 288, i32 0), !invariant.load !{} + %tmp42 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 292, i32 0), !invariant.load !{} + %tmp43 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 296, i32 0), !invariant.load !{} + %tmp44 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 304, i32 0), !invariant.load !{} + %tmp45 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 308, i32 0), !invariant.load !{} + %tmp46 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 312, i32 0), !invariant.load !{} + %tmp47 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 320, i32 0), !invariant.load !{} + %tmp48 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 324, i32 0), !invariant.load !{} + %tmp49 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 328, i32 0), !invariant.load !{} + %tmp50 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 336, i32 0), !invariant.load !{} + %tmp51 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 340, i32 0), !invariant.load !{} + %tmp52 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 344, i32 0), !invariant.load !{} + %tmp53 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 352, i32 0), !invariant.load !{} + %tmp54 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 356, i32 0), !invariant.load !{} + %tmp55 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 360, i32 0), !invariant.load !{} + %tmp56 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 368, i32 0), !invariant.load !{} + %tmp57 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 372, i32 0), !invariant.load !{} + %tmp58 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 376, i32 0), !invariant.load !{} + %tmp59 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 384, i32 0), !invariant.load !{} + %tmp60 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 388, i32 0), !invariant.load !{} + %tmp61 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 392, i32 0), !invariant.load !{} + %tmp62 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 400, i32 0), !invariant.load !{} + %tmp63 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 404, i32 0), !invariant.load !{} + %tmp64 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 408, i32 0), !invariant.load !{} + %tmp65 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 416, i32 0), !invariant.load !{} + %tmp66 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 420, i32 0), !invariant.load !{} br label %LOOP LOOP: ; preds = %ENDIF2795, %main_body @@ -436,7 +436,7 @@ declare float @llvm.minnum.f32(float, float) #1 declare float @llvm.maxnum.f32(float, float) #1 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 -declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1 +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32) #1 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll index c0c1763d54cc0..8a5ff3632da1a 100644 --- a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll +++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll @@ -31,7 +31,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sgpr_32 = COPY $sgpr10 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sgpr_32 = COPY $sgpr8 ; CHECK-NEXT: undef [[S_LOAD_DWORDX2_IMM:%[0-9]+]].sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 232, 0 :: (invariant load (s64) from %ir.39, addrspace 4) - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %130:sgpr_128, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %130:sgpr_128, 0, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) poison`, align 1, addrspace 8) ; CHECK-NEXT: KILL undef %130:sgpr_128 ; CHECK-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY5]], 4, implicit-def dead $scc ; CHECK-NEXT: [[S_LSHL_B32_1:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY4]], 4, implicit-def dead $scc @@ -46,16 +46,18 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %54:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_]], 16, 0 :: (invariant load (s128) from %ir.83, addrspace 4) ; CHECK-NEXT: early-clobber %73:sgpr_256 = S_LOAD_DWORDX8_IMM_ec undef %74:sreg_64, 0, 0 :: (invariant load (s256) from `ptr addrspace(4) poison`, align 16, addrspace 4) - ; CHECK-NEXT: KILL [[S_ADD_U32_]].sub0, [[S_ADD_U32_]].sub1 ; CHECK-NEXT: KILL undef %74:sreg_64 - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_LOAD_DWORDX4_IMM]], 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: KILL [[S_ADD_U32_]].sub0, [[S_ADD_U32_]].sub1 + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_LOAD_DWORDX4_IMM]], 0, 0 :: (dereferenceable invariant load (s32) from %ir.84, align 1, addrspace 8) + ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec - ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 0 ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET undef %123:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = COPY [[S_MOV_B32_]].sub0 ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], undef %94:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], %73.sub0_sub1_sub2_sub3, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: KILL undef %94:sgpr_128 - ; CHECK-NEXT: KILL undef %123:sgpr_128 ; CHECK-NEXT: [[S_SUB_I32_2:%[0-9]+]]:sreg_32 = S_SUB_I32 [[S_BUFFER_LOAD_DWORD_IMM1]], 31, implicit-def dead $scc ; CHECK-NEXT: undef [[S_ADD_U32_1:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY6]], [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_1:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %54:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc @@ -64,18 +66,16 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: undef [[S_ADD_U32_3:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY6]], [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM1:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_1]], 64, 0 :: (invariant load (s128) from %ir.89, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM2:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_2]], 64, 0 :: (invariant load (s128) from %ir.95, addrspace 4) - ; CHECK-NEXT: KILL [[S_ADD_U32_2]].sub0, [[S_ADD_U32_2]].sub1 - ; CHECK-NEXT: KILL [[S_ADD_U32_1]].sub0, [[S_ADD_U32_1]].sub1 ; CHECK-NEXT: [[S_ADD_U32_3:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %54:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc - ; CHECK-NEXT: [[S_ASHR_I32_3:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 undef %174:sreg_32, 31, implicit-def dead $scc - ; CHECK-NEXT: undef [[S_ADD_U32_4:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY6]], undef %174:sreg_32, implicit-def $scc + ; CHECK-NEXT: [[S_ASHR_I32_3:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 undef %176:sreg_32, 31, implicit-def dead $scc + ; CHECK-NEXT: undef [[S_ADD_U32_4:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY6]], undef %176:sreg_32, implicit-def $scc ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM3:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_3]], 64, 0 :: (invariant load (s128) from %ir.101, addrspace 4) ; CHECK-NEXT: [[S_ADD_U32_4:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %54:sreg_32, [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: undef [[S_ADD_U32_5:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY7]].sub0, [[S_LSHL_B32_]], implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_5:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: undef [[S_ADD_U32_6:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY7]].sub0, [[S_LSHL_B32_1]], implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_6:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc - ; CHECK-NEXT: undef [[S_ADD_U32_7:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY7]].sub0, undef %174:sreg_32, implicit-def $scc + ; CHECK-NEXT: undef [[S_ADD_U32_7:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY7]].sub0, undef %176:sreg_32, implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_7:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: undef [[S_ADD_U32_8:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY7]].sub0, [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_8:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc @@ -87,19 +87,19 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[S_ADD_U32_11:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %45:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_LSHL_B32_]], 16, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_LSHL_B32_2]], 16, implicit-def dead $scc - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[S_MOV_B32_]], [[S_ADD_I32_]], 0, 0 :: (dereferenceable invariant load (s32)) - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[S_MOV_B32_]], undef %307:sreg_32, 0, 0 :: (dereferenceable invariant load (s32)) - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[S_MOV_B32_]], [[S_ADD_I32_1]], 0, 0 :: (dereferenceable invariant load (s32)) - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_MOV_B32_]], 16, 0 :: (dereferenceable invariant load (s32)) - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %362:sgpr_128, undef %363:sreg_32, 0, 0 :: (dereferenceable invariant load (s32)) - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %373:sgpr_128, 16, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[S_MOV_B32_]], [[S_ADD_I32_]], 0, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) null`, align 1, addrspace 8) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[S_MOV_B32_]], undef %303:sreg_32, 0, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) null`, align 1, addrspace 8) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[S_MOV_B32_]], [[S_ADD_I32_1]], 0, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) null`, align 1, addrspace 8) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_MOV_B32_]], 16, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) null`, align 1, addrspace 8) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %132:sgpr_128, 16, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) poison`, align 1, addrspace 8) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %358:sgpr_128, undef %359:sreg_32, 0, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) poison`, align 1, addrspace 8) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM4:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_4]], 64, 0 :: (invariant load (s128) from %ir.109, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM5:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_5]], 0, 0 :: (invariant load (s128) from %ir.114, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM6:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_6]], 0, 0 :: (invariant load (s128) from %ir.119, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM7:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_7]], 0, 0 :: (invariant load (s128) from %ir.126, addrspace 4) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM1]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %357:sgpr_128, [[S_ADD_I32_]], 0, 0 :: (dereferenceable invariant load (s32)) - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %368:sgpr_128, [[S_ADD_I32_1]], 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %353:sgpr_128, [[S_ADD_I32_]], 0, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) poison`, align 1, addrspace 8) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %364:sgpr_128, [[S_ADD_I32_1]], 0, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) poison`, align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM2]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN4:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM3]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[S_ADD_I32_2:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM]], -98, implicit-def dead $scc @@ -115,7 +115,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: undef [[S_ADD_U32_15:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY11]], [[S_LSHL_B32_2]], implicit-def $scc ; CHECK-NEXT: [[S_ADD_U32_15:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %39:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc ; CHECK-NEXT: [[S_LSHL4_ADD_U32_:%[0-9]+]]:sreg_32 = S_LSHL4_ADD_U32 [[COPY12]], 16, implicit-def dead $scc - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %388:sgpr_128, [[S_LSHL4_ADD_U32_]], 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %382:sgpr_128, [[S_LSHL4_ADD_U32_]], 0, 0 :: (dereferenceable invariant load (s32) from `ptr addrspace(8) poison`, align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN5:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM4]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM8:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_5]], 224, 0 :: (invariant load (s128) from %ir.131, addrspace 4) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM9:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY7]], 224, 0 :: (invariant load (s128) from %ir.147, addrspace 4) @@ -155,9 +155,9 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 -1 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]] ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM15:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_9]], 0, 0 :: (invariant load (s128) from %ir.172, addrspace 4) - ; CHECK-NEXT: [[COPY15:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub1 + ; CHECK-NEXT: [[COPY15:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 ; CHECK-NEXT: [[COPY15:%[0-9]+]].sub0:sgpr_128 = COPY [[S_LOAD_DWORD_IMM]] - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY15]], 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY15]], 0, 0 :: (dereferenceable invariant load (s32) from %ir.sbuf299.ptr, align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN14:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM14]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN15:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM12]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM16:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_10]], 0, 0 :: (invariant load (s128) from %ir.180, addrspace 4) @@ -180,7 +180,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORDX2_IMM1]].sub1, 65535, implicit-def dead $scc ; CHECK-NEXT: [[COPY16:%[0-9]+]].sub0:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM1]].sub0 ; CHECK-NEXT: [[COPY16:%[0-9]+]].sub1:sgpr_128 = COPY [[S_AND_B32_]] - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY16]], 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY16]], 0, 0 :: (dereferenceable invariant load (s32) from %ir.sbuf308.ptr, align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN17:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM18]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN18:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM19]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN19:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM20]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) @@ -195,7 +195,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORDX2_IMM2]].sub1, 65535, implicit-def dead $scc ; CHECK-NEXT: [[COPY17:%[0-9]+]].sub0:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM2]].sub0 ; CHECK-NEXT: [[COPY17:%[0-9]+]].sub1:sgpr_128 = COPY [[S_AND_B32_1]] - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY17]], 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY17]], 0, 0 :: (dereferenceable invariant load (s32) from %ir.sbuf317.ptr, align 1, addrspace 8) ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM22:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_16]], 160, 0 :: (invariant load (s128) from %ir.259, addrspace 4) ; CHECK-NEXT: [[S_LSHL_B32_7:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY14]], 3, implicit-def dead $scc ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM23:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_17]], 160, 0 :: (invariant load (s128) from %ir.268, addrspace 4) @@ -212,7 +212,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[COPY18:%[0-9]+]]:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]] ; CHECK-NEXT: [[COPY18:%[0-9]+]].sub1:sgpr_128 = COPY [[S_AND_B32_2]] ; CHECK-NEXT: [[COPY18:%[0-9]+]].sub0:sgpr_128 = COPY [[S_LOAD_DWORD_IMM1]] - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM7:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY18]], 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM7:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY18]], 0, 0 :: (dereferenceable invariant load (s32) from %ir.sbuf327.ptr, align 1, addrspace 8) ; CHECK-NEXT: [[S_ADD_I32_17:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM]], -474, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_18:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM3]], -475, implicit-def dead $scc ; CHECK-NEXT: [[S_ADD_I32_19:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM3]], -491, implicit-def dead $scc @@ -231,10 +231,10 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN23:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM24]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN24:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM25]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN25:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM26]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8) - ; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM24]] - ; CHECK-NEXT: KILL [[V_MOV_B32_e32_]] ; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM25]] ; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM26]] + ; CHECK-NEXT: KILL [[V_MOV_B32_e32_]] + ; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM24]] ; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -2, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -1, [[BUFFER_LOAD_FORMAT_X_IDXEN1]], 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -3, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec @@ -339,7 +339,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[V_OR_B32_e64_61:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_60]], [[V_ADD_U32_e64_25]], implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_27:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -575, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_62:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_61]], [[V_ADD_U32_e64_26]], implicit $exec - ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM8:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_LOAD_DWORDX2_IMM]], 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM8:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_LOAD_DWORDX2_IMM]], 0, 0 :: (dereferenceable invariant load (s32) from %ir.sbuf42.ptr, align 1, addrspace 8) ; CHECK-NEXT: [[V_ADD_U32_e64_28:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -576, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec ; CHECK-NEXT: [[V_OR_B32_e64_63:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_62]], [[V_ADD_U32_e64_27]], implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e64_29:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 -577, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec @@ -351,7 +351,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x ; CHECK-NEXT: [[V_OR_B32_e64_67:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_ADD_I32_23]], [[V_OR_B32_e64_66]], implicit $exec ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 0, [[V_OR_B32_e64_67]], implicit $exec ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_:%[0-9]+]].sub3:vreg_128 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec - ; CHECK-NEXT: IMAGE_STORE_V4_V2_nsa_gfx10 [[V_CNDMASK_B32_e64_]], undef %557:vgpr_32, undef %559:vgpr_32, %73, 15, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), addrspace 8) + ; CHECK-NEXT: IMAGE_STORE_V4_V2_nsa_gfx10 [[V_CNDMASK_B32_e64_]], undef %551:vgpr_32, undef %553:vgpr_32, %73, 15, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 .expVert: %0 = extractelement <31 x i32> %userData, i64 2 @@ -400,8 +400,12 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x %40 = and i32 %rootDesc58.ii1.i, 65535 %41 = insertelement <4 x i32> , i32 %rootDesc58.ii0.i, i32 0 %42 = insertelement <4 x i32> %41, i32 %40, i32 1 + %sbuf42.rsrc = bitcast <4 x i32> %42 to i128 + %sbuf42.ptr = inttoptr i128 %sbuf42.rsrc to ptr addrspace(8) %43 = and i32 0, 65535 %44 = insertelement <4 x i32> poison, i32 %43, i32 1 + %sbuf44.rsrc = bitcast <4 x i32> %44 to i128 + %sbuf44.ptr = inttoptr i128 %sbuf44.rsrc to ptr addrspace(8) %45 = load <4 x i32>, ptr addrspace(4) poison, align 16 %46 = call i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32> %45, i32 0, i32 0, i32 0, i32 0) %47 = add i32 %46, -1 @@ -431,21 +435,21 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x %71 = or i32 %68, %70 %72 = call i32 @llvm.amdgcn.readfirstlane(i32 %0) %73 = getelementptr i8, ptr addrspace(4) %35, i64 16 - %74 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 0, i32 0) + %74 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 0, i32 0), !invariant.load !{} %75 = add i32 %74, -29 %76 = or i32 %71, %75 %77 = call i32 @llvm.amdgcn.readfirstlane(i32 %1) %78 = shl i32 %77, 4 %79 = sext i32 %78 to i64 - %80 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 0, i32 0) + %80 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 0, i32 0), !invariant.load !{} %81 = add i32 %80, -30 %82 = or i32 %76, %81 %83 = call i32 @llvm.amdgcn.readfirstlane(i32 %2) %84 = shl i32 %83, 4 %85 = sext i32 %84 to i64 %86 = getelementptr i8, ptr addrspace(4) %73, i64 %85 - %87 = load <4 x i32>, ptr addrspace(4) %86, align 16 - %88 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %87, i32 0, i32 0) + %87 = load ptr addrspace(8), ptr addrspace(4) %86, align 16 + %88 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %87, i32 0, i32 0), !invariant.load !{} %89 = add i32 %88, -31 %90 = or i32 %82, %89 %91 = getelementptr i8, ptr addrspace(4) %35, i64 64 @@ -559,20 +563,20 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x %197 = or i32 %192, %196 %198 = getelementptr <{ [4 x i32], [6 x %llpc.array.element] }>, ptr addrspace(6) null, i32 0, i32 1, i32 %0, i32 0 %199 = ptrtoint ptr addrspace(6) %198 to i32 - %200 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %44, i32 %199, i32 0) + %200 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sbuf44.ptr, i32 %199, i32 0), !invariant.load !{} %201 = add i32 %200, -98 %202 = or i32 %197, %201 - %203 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %44, i32 poison, i32 0) + %203 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sbuf44.ptr, i32 poison, i32 0), !invariant.load !{} %204 = add i32 %203, -114 %205 = or i32 %202, %204 %206 = getelementptr <{ [4 x i32], [6 x %llpc.array.element] }>, ptr addrspace(6) null, i32 0, i32 1, i32 %2, i32 0 %207 = ptrtoint ptr addrspace(6) %206 to i32 - %208 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %44, i32 %207, i32 0) + %208 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sbuf44.ptr, i32 %207, i32 0), !invariant.load !{} %209 = add i32 %208, -130 %210 = or i32 %205, %209 %211 = getelementptr <{ [4 x i32], [6 x %llpc.array.element] }>, ptr addrspace(6) null, i32 0, i32 1, i32 0, i32 0 %212 = ptrtoint ptr addrspace(6) %211 to i32 - %213 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %44, i32 %212, i32 0) + %213 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sbuf44.ptr, i32 %212, i32 0), !invariant.load !{} %214 = add i32 %213, -178 %215 = or i32 %210, %214 %216 = inttoptr i64 %24 to ptr addrspace(4) @@ -602,34 +606,34 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x %240 = or i32 %237, %239 %241 = getelementptr <{ [4 x i32], [6 x %llpc.array.element.2] }>, ptr addrspace(6) null, i32 0, i32 1, i32 %0, i32 0 %242 = ptrtoint ptr addrspace(6) %241 to i32 - %243 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 %242, i32 0) + %243 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 %242, i32 0), !invariant.load !{} %244 = add i32 %243, -217 %245 = or i32 %240, %244 - %246 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 poison, i32 0) + %246 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 poison, i32 0), !invariant.load !{} %247 = add i32 %246, -233 %248 = or i32 %245, %247 %249 = getelementptr <{ [4 x i32], [6 x %llpc.array.element.2] }>, ptr addrspace(6) null, i32 0, i32 1, i32 %2, i32 0 %250 = ptrtoint ptr addrspace(6) %249 to i32 - %251 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 %250, i32 0) + %251 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 %250, i32 0), !invariant.load !{} %252 = add i32 %251, -249 %253 = or i32 %248, %252 %254 = getelementptr <{ [4 x i32], [6 x %llpc.array.element.2] }>, ptr addrspace(6) null, i32 0, i32 1, i32 0, i32 0 %255 = ptrtoint ptr addrspace(6) %254 to i32 - %256 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 %255, i32 0) + %256 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 %255, i32 0), !invariant.load !{} %257 = add i32 %256, -297 %258 = or i32 %253, %257 - %259 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 poison, i32 0) + %259 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 poison, i32 0), !invariant.load !{} %260 = add i32 %259, -313 %261 = or i32 %258, %260 - %262 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 poison, i32 0) + %262 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 poison, i32 0), !invariant.load !{} %263 = add i32 %262, -329 %264 = or i32 %261, %263 - %265 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 poison, i32 0) + %265 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 poison, i32 0), !invariant.load !{} %266 = add i32 %265, -345 %267 = or i32 %264, %266 %268 = getelementptr <{ [4 x i32], [9 x %llpc.array.element.5] }>, ptr addrspace(6) null, i32 0, i32 1, i32 %4, i32 0 %269 = ptrtoint ptr addrspace(6) %268 to i32 - %270 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 %269, i32 0) + %270 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 %269, i32 0), !invariant.load !{} %271 = add i32 %270, -441 %272 = or i32 %267, %271 %273 = getelementptr i8, ptr addrspace(4) %20, i64 160 @@ -660,7 +664,9 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x %297 = and i32 0, 65535 %298 = insertelement <4 x i32> , i32 %.ii0.i, i32 0 %299 = insertelement <4 x i32> %298, i32 %297, i32 1 - %300 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %299, i32 0, i32 0) + %sbuf299.rsrc = bitcast <4 x i32> %299 to i128 + %sbuf299.ptr = inttoptr i128 %sbuf299.rsrc to ptr addrspace(8) + %300 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sbuf299.ptr, i32 0, i32 0), !invariant.load !{} %301 = add i32 %300, -467 %302 = or i32 %292, %301 %303 = shl i32 %77, 3 @@ -672,7 +678,9 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x %306 = and i32 %.ii192.i, 65535 %307 = insertelement <4 x i32> , i32 %.ii090.i, i32 0 %308 = insertelement <4 x i32> %307, i32 %306, i32 1 - %309 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %308, i32 0, i32 0) + %sbuf308.rsrc = bitcast <4 x i32> %308 to i128 + %sbuf308.ptr = inttoptr i128 %sbuf308.rsrc to ptr addrspace(8) + %309 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sbuf308.ptr, i32 0, i32 0), !invariant.load !{} %310 = add i32 %309, -468 %311 = or i32 %302, %310 %312 = shl i32 %83, 3 @@ -684,7 +692,9 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x %315 = and i32 %.ii198.i, 65535 %316 = insertelement <4 x i32> , i32 %.ii096.i, i32 0 %317 = insertelement <4 x i32> %316, i32 %315, i32 1 - %318 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %317, i32 0, i32 0) + %sbuf317.rsrc = bitcast <4 x i32> %317 to i128 + %sbuf317.ptr = inttoptr i128 %sbuf317.rsrc to ptr addrspace(8) + %318 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sbuf317.ptr, i32 0, i32 0), !invariant.load !{} %319 = add i32 %318, -469 %320 = or i32 %311, %319 %321 = call i32 @llvm.amdgcn.readfirstlane(i32 %3) @@ -696,22 +706,24 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x %325 = and i32 %.ii1104.i, 65535 %326 = insertelement <4 x i32> , i32 %.ii0102.i, i32 0 %327 = insertelement <4 x i32> %326, i32 %325, i32 1 - %328 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %327, i32 0, i32 0) + %sbuf327.rsrc = bitcast <4 x i32> %327 to i128 + %sbuf327.ptr = inttoptr i128 %sbuf327.rsrc to ptr addrspace(8) + %328 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sbuf327.ptr, i32 0, i32 0), !invariant.load !{} %329 = add i32 %328, -473 %330 = or i32 %320, %329 - %331 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 0, i32 0) + %331 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 0, i32 0), !invariant.load !{} %332 = add i32 %331, -474 %333 = or i32 %330, %332 - %334 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 poison, i32 0) + %334 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 poison, i32 0), !invariant.load !{} %335 = add i32 %334, -475 %336 = or i32 %333, %335 - %337 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 poison, i32 0) + %337 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 poison, i32 0), !invariant.load !{} %338 = add i32 %337, -491 %339 = or i32 %336, %338 - %340 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 poison, i32 0) + %340 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 poison, i32 0), !invariant.load !{} %341 = add i32 %340, -507 %342 = or i32 %339, %341 - %343 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> poison, i32 poison, i32 0) + %343 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) poison, i32 poison, i32 0), !invariant.load !{} %344 = add i32 %343, -539 %345 = or i32 %342, %344 %346 = getelementptr i8, ptr addrspace(4) %17, i64 96 @@ -745,7 +757,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x %374 = call i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32> poison, i32 0, i32 0, i32 0, i32 0) %375 = add i32 %374, -593 %376 = or i32 %373, %375 - %377 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %42, i32 0, i32 0) + %377 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sbuf42.ptr, i32 0, i32 0), !invariant.load !{} %378 = add i32 %377, -594 %379 = or i32 %376, %378 %.not.i = icmp eq i32 %379, 0 @@ -761,5 +773,5 @@ declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) declare i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32>, i32, i32, i32, i32 immarg) declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32 immarg) -declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll index db49339ea1f78..2185fbbb58c11 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll +++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll @@ -29,10 +29,10 @@ define amdgpu_vs void @main(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, ptr addrspace(4) inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { bb: - %tmp11 = load <4 x i32>, ptr addrspace(4) %arg1, align 16, !tbaa !0 - %tmp12 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp11, i32 0, i32 0) - %tmp13 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp11, i32 16, i32 0) - %tmp14 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp11, i32 32, i32 0) + %tmp11 = load ptr addrspace(8), ptr addrspace(4) %arg1, align 16, !tbaa !0 + %tmp12 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp11, i32 0, i32 0), !invariant.load !{} + %tmp13 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp11, i32 16, i32 0), !invariant.load !{} + %tmp14 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %tmp11, i32 32, i32 0), !invariant.load !{} %tmp16 = load ptr addrspace(8), ptr addrspace(4) %arg4, align 16, !tbaa !0 %tmp17 = add i32 %arg5, %arg7 %tmp16.cast = bitcast ptr addrspace(8) %tmp16 to ptr addrspace(8) @@ -486,7 +486,7 @@ bb157: ; preds = %bb24 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 -declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1 +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32) #1 declare <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8), i32, i32, i32, i32 immarg) #2 attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/wqm.ll b/llvm/test/CodeGen/AMDGPU/wqm.ll index 900f26f413499..801b394c1fc20 100644 --- a/llvm/test/CodeGen/AMDGPU/wqm.ll +++ b/llvm/test/CodeGen/AMDGPU/wqm.ll @@ -3415,7 +3415,9 @@ define amdgpu_ps void @test_for_deactivating_lanes_in_wave32(ptr addrspace(6) in main_body: %1 = ptrtoint ptr addrspace(6) %0 to i32 %2 = insertelement <4 x i32> , i32 %1, i32 0 - %3 = call nsz arcp float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %2, i32 0, i32 0) #3 + %sbuf.rsrc = bitcast <4 x i32> %2 to i128 + %sbuf.ptr = inttoptr i128 %sbuf.rsrc to ptr addrspace(8) + %3 = call nsz arcp float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %sbuf.ptr, i32 0, i32 0) #3, !invariant.load !{} %4 = fcmp nsz arcp ugt float %3, 0.000000e+00 call void @llvm.amdgcn.kill(i1 %4) #1 ret void @@ -3608,7 +3610,9 @@ main_body: if: %idx1 = extractelement <4 x i32> %idx0, i64 0 %idx2 = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %idx1) - %idx3 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %sampler, i32 %idx2, i32 0) + %sampler.rsrc = bitcast <4 x i32> %sampler to i128 + %sampler.ptr = inttoptr i128 %sampler.rsrc to ptr addrspace(8) + %idx3 = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %sampler.ptr, i32 %idx2, i32 0), !invariant.load !{} call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %tex1, <4 x i32> poison, i32 %idx3, i32 0, i32 0, i32 0) br label %endif @@ -3675,7 +3679,9 @@ main_body: %tex2 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %d, <8 x i32> %rsrc, <4 x i32> %sampler, i1 false, i32 0, i32 0) #0 %idx2 = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %idx1) - %idx3 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %sampler, i32 %idx2, i32 0) + %sampler.rsrc = bitcast <4 x i32> %sampler to i128 + %sampler.ptr = inttoptr i128 %sampler.rsrc to ptr addrspace(8) + %idx3 = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %sampler.ptr, i32 %idx2, i32 0), !invariant.load !{} %r0 = extractelement <4 x float> %tex1, i64 1 %r1 = extractelement <4 x float> %tex2, i64 2 @@ -3723,7 +3729,8 @@ declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2 declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) -declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32 immarg) #7 +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32 immarg) #7 +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) #7 declare i32 @llvm.amdgcn.readfirstlane.i32(i32) attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll index 3c8ac9f58b63e..ad781ca4cb399 100644 --- a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll @@ -707,7 +707,7 @@ define amdgpu_gfx void @strict_wwm_call_i64(ptr addrspace(8) inreg %tmp14, i64 i ret void } -define amdgpu_gfx void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) #1 { +define amdgpu_gfx void @strict_wwm_amdgpu_cs_main(ptr addrspace(8) inreg %desc, i32 %index) #1 { ; GFX9-O0-LABEL: strict_wwm_amdgpu_cs_main: ; GFX9-O0: ; %bb.0: ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -718,11 +718,20 @@ define amdgpu_gfx void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %in ; GFX9-O0-NEXT: s_nop 0 ; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[34:35] -; GFX9-O0-NEXT: s_mov_b32 s36, s4 +; GFX9-O0-NEXT: s_mov_b32 s40, s6 +; GFX9-O0-NEXT: s_mov_b32 s34, s4 +; GFX9-O0-NEXT: ; kill: def $sgpr40 killed $sgpr40 def $sgpr40_sgpr41 +; GFX9-O0-NEXT: s_mov_b32 s41, s7 +; GFX9-O0-NEXT: s_mov_b32 s42, s41 +; GFX9-O0-NEXT: s_mov_b32 s43, s40 +; GFX9-O0-NEXT: ; kill: def $sgpr34 killed $sgpr34 def $sgpr34_sgpr35 +; GFX9-O0-NEXT: s_mov_b32 s35, s5 +; GFX9-O0-NEXT: s_mov_b32 s44, s35 +; GFX9-O0-NEXT: s_mov_b32 s36, s34 ; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37_sgpr38_sgpr39 -; GFX9-O0-NEXT: s_mov_b32 s37, s5 -; GFX9-O0-NEXT: s_mov_b32 s38, s6 -; GFX9-O0-NEXT: s_mov_b32 s39, s7 +; GFX9-O0-NEXT: s_mov_b32 s37, s44 +; GFX9-O0-NEXT: s_mov_b32 s38, s43 +; GFX9-O0-NEXT: s_mov_b32 s39, s42 ; GFX9-O0-NEXT: s_mov_b32 s34, 5 ; GFX9-O0-NEXT: v_lshlrev_b32_e64 v0, s34, v0 ; GFX9-O0-NEXT: s_mov_b32 s34, 0 @@ -857,10 +866,10 @@ define amdgpu_gfx void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %in ; GFX9-O3-NEXT: s_waitcnt vmcnt(0) ; GFX9-O3-NEXT: s_setpc_b64 s[30:31] %tmp17 = shl i32 %index, 5 - %tmp18 = tail call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 %tmp17, i32 0) + %tmp18 = tail call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) %desc, i32 %tmp17, i32 0), !invariant.load !{} %.i0.upto1.bc = bitcast <4 x i32> %tmp18 to <2 x i64> %tmp19 = or i32 %tmp17, 16 - %tmp20 = tail call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 %tmp19, i32 0) + %tmp20 = tail call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %desc, i32 %tmp19, i32 0), !invariant.load !{} %.i0.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 0 %tmp22 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i0.upto1.extract, i64 9223372036854775807) %tmp97 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp22) @@ -874,10 +883,8 @@ define amdgpu_gfx void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %in %.cast6 = bitcast i64 %tmp174 to <2 x float> %.cast7 = bitcast i64 %tmp251 to <2 x float> %tmp254 = shufflevector <2 x float> %.cast, <2 x float> %.cast6, <4 x i32> - %desc.int = bitcast <4 x i32> %desc to i128 - %desc.ptr = inttoptr i128 %desc.int to ptr addrspace(8) - tail call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> %tmp254, ptr addrspace(8) %desc.ptr, i32 %tmp17, i32 0, i32 0) - tail call void @llvm.amdgcn.raw.ptr.buffer.store.v2f32(<2 x float> %.cast7, ptr addrspace(8) %desc.ptr, i32 %tmp19, i32 0, i32 0) + tail call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> %tmp254, ptr addrspace(8) %desc, i32 %tmp17, i32 0, i32 0) + tail call void @llvm.amdgcn.raw.ptr.buffer.store.v2f32(<2 x float> %.cast7, ptr addrspace(8) %desc, i32 %tmp19, i32 0, i32 0) ret void } @@ -1240,8 +1247,8 @@ declare void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32, ptr addrspace(8), i32, i declare void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32>, ptr addrspace(8), i32, i32, i32) declare void @llvm.amdgcn.raw.ptr.buffer.store.v2f32(<2 x float>, ptr addrspace(8), i32, i32, i32) declare void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float>, ptr addrspace(8), i32, i32, i32) -declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32) -declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32) +declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8), i32, i32) +declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8), i32, i32) attributes #0 = { "amdgpu-waves-per-eu"="5,5" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll index 9faa8aeb26de1..526605f818613 100644 --- a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll +++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll @@ -723,16 +723,23 @@ define amdgpu_kernel void @call_i64(ptr addrspace(8) %tmp14, i64 %arg) { ret void } -define amdgpu_cs void @_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) { +define amdgpu_cs void @_amdgpu_cs_main(ptr addrspace(8) inreg %desc, i32 %index) { ; GFX9-O0-LABEL: _amdgpu_cs_main: ; GFX9-O0: ; %bb.0: -; GFX9-O0-NEXT: s_mov_b32 s4, s3 -; GFX9-O0-NEXT: s_mov_b32 s5, s2 -; GFX9-O0-NEXT: s_mov_b32 s6, s1 +; GFX9-O0-NEXT: s_mov_b32 s6, s2 +; GFX9-O0-NEXT: s_mov_b32 s4, s0 +; GFX9-O0-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7 +; GFX9-O0-NEXT: s_mov_b32 s7, s3 +; GFX9-O0-NEXT: s_mov_b32 s8, s7 +; GFX9-O0-NEXT: s_mov_b32 s9, s6 +; GFX9-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5 +; GFX9-O0-NEXT: s_mov_b32 s5, s1 +; GFX9-O0-NEXT: s_mov_b32 s10, s5 +; GFX9-O0-NEXT: s_mov_b32 s0, s4 ; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3 -; GFX9-O0-NEXT: s_mov_b32 s1, s6 -; GFX9-O0-NEXT: s_mov_b32 s2, s5 -; GFX9-O0-NEXT: s_mov_b32 s3, s4 +; GFX9-O0-NEXT: s_mov_b32 s1, s10 +; GFX9-O0-NEXT: s_mov_b32 s2, s9 +; GFX9-O0-NEXT: s_mov_b32 s3, s8 ; GFX9-O0-NEXT: s_mov_b32 s4, 5 ; GFX9-O0-NEXT: v_lshlrev_b32_e64 v0, s4, v0 ; GFX9-O0-NEXT: s_mov_b32 s4, 0 @@ -837,10 +844,10 @@ define amdgpu_cs void @_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) { ; GFX9-O3-NEXT: buffer_store_dwordx2 v[12:13], v0, s[0:3], 0 offen offset:16 ; GFX9-O3-NEXT: s_endpgm %tmp17 = shl i32 %index, 5 - %tmp18 = tail call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 %tmp17, i32 0) + %tmp18 = tail call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) %desc, i32 %tmp17, i32 0), !invariant.load !{} %.i0.upto1.bc = bitcast <4 x i32> %tmp18 to <2 x i64> %tmp19 = or i32 %tmp17, 16 - %tmp20 = tail call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 %tmp19, i32 0) + %tmp20 = tail call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %desc, i32 %tmp19, i32 0), !invariant.load !{} %.i0.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 0 %tmp22 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i0.upto1.extract, i64 9223372036854775807) %tmp97 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp22) @@ -854,10 +861,8 @@ define amdgpu_cs void @_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) { %.cast6 = bitcast i64 %tmp174 to <2 x float> %.cast7 = bitcast i64 %tmp251 to <2 x float> %tmp254 = shufflevector <2 x float> %.cast, <2 x float> %.cast6, <4 x i32> - %desc.int = bitcast <4 x i32> %desc to i128 - %desc.ptr = inttoptr i128 %desc.int to ptr addrspace(8) - tail call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> %tmp254, ptr addrspace(8) %desc.ptr, i32 %tmp17, i32 0, i32 0) - tail call void @llvm.amdgcn.raw.ptr.buffer.store.v2f32(<2 x float> %.cast7, ptr addrspace(8) %desc.ptr, i32 %tmp19, i32 0, i32 0) + tail call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> %tmp254, ptr addrspace(8) %desc, i32 %tmp17, i32 0, i32 0) + tail call void @llvm.amdgcn.raw.ptr.buffer.store.v2f32(<2 x float> %.cast7, ptr addrspace(8) %desc, i32 %tmp19, i32 0, i32 0) ret void } @@ -1581,16 +1586,23 @@ define amdgpu_kernel void @strict_wwm_call_i64(ptr addrspace(8) %tmp14, i64 %arg ret void } -define amdgpu_cs void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) { +define amdgpu_cs void @strict_wwm_amdgpu_cs_main(ptr addrspace(8) inreg %desc, i32 %index) { ; GFX9-O0-LABEL: strict_wwm_amdgpu_cs_main: ; GFX9-O0: ; %bb.0: -; GFX9-O0-NEXT: s_mov_b32 s4, s3 -; GFX9-O0-NEXT: s_mov_b32 s5, s2 -; GFX9-O0-NEXT: s_mov_b32 s6, s1 +; GFX9-O0-NEXT: s_mov_b32 s6, s2 +; GFX9-O0-NEXT: s_mov_b32 s4, s0 +; GFX9-O0-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7 +; GFX9-O0-NEXT: s_mov_b32 s7, s3 +; GFX9-O0-NEXT: s_mov_b32 s8, s7 +; GFX9-O0-NEXT: s_mov_b32 s9, s6 +; GFX9-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5 +; GFX9-O0-NEXT: s_mov_b32 s5, s1 +; GFX9-O0-NEXT: s_mov_b32 s10, s5 +; GFX9-O0-NEXT: s_mov_b32 s0, s4 ; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3 -; GFX9-O0-NEXT: s_mov_b32 s1, s6 -; GFX9-O0-NEXT: s_mov_b32 s2, s5 -; GFX9-O0-NEXT: s_mov_b32 s3, s4 +; GFX9-O0-NEXT: s_mov_b32 s1, s10 +; GFX9-O0-NEXT: s_mov_b32 s2, s9 +; GFX9-O0-NEXT: s_mov_b32 s3, s8 ; GFX9-O0-NEXT: s_mov_b32 s4, 5 ; GFX9-O0-NEXT: v_lshlrev_b32_e64 v0, s4, v0 ; GFX9-O0-NEXT: s_mov_b32 s4, 0 @@ -1695,10 +1707,10 @@ define amdgpu_cs void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %ind ; GFX9-O3-NEXT: buffer_store_dwordx2 v[12:13], v0, s[0:3], 0 offen offset:16 ; GFX9-O3-NEXT: s_endpgm %tmp17 = shl i32 %index, 5 - %tmp18 = tail call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 %tmp17, i32 0) + %tmp18 = tail call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) %desc, i32 %tmp17, i32 0), !invariant.load !{} %.i0.upto1.bc = bitcast <4 x i32> %tmp18 to <2 x i64> %tmp19 = or i32 %tmp17, 16 - %tmp20 = tail call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 %tmp19, i32 0) + %tmp20 = tail call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %desc, i32 %tmp19, i32 0), !invariant.load !{} %.i0.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 0 %tmp22 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i0.upto1.extract, i64 9223372036854775807) %tmp97 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp22) @@ -1712,10 +1724,8 @@ define amdgpu_cs void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %ind %.cast6 = bitcast i64 %tmp174 to <2 x float> %.cast7 = bitcast i64 %tmp251 to <2 x float> %tmp254 = shufflevector <2 x float> %.cast, <2 x float> %.cast6, <4 x i32> - %desc.int = bitcast <4 x i32> %desc to i128 - %desc.ptr = inttoptr i128 %desc.int to ptr addrspace(8) - tail call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> %tmp254, ptr addrspace(8) %desc.ptr, i32 %tmp17, i32 0, i32 0) - tail call void @llvm.amdgcn.raw.ptr.buffer.store.v2f32(<2 x float> %.cast7, ptr addrspace(8)%desc.ptr, i32 %tmp19, i32 0, i32 0) + tail call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> %tmp254, ptr addrspace(8) %desc, i32 %tmp17, i32 0, i32 0) + tail call void @llvm.amdgcn.raw.ptr.buffer.store.v2f32(<2 x float> %.cast7, ptr addrspace(8)%desc, i32 %tmp19, i32 0, i32 0) ret void } @@ -1732,6 +1742,6 @@ declare void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32, ptr addrspace(8), i32, i declare void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32>, ptr addrspace(8), i32, i32, i32) declare void @llvm.amdgcn.raw.ptr.buffer.store.v2f32(<2 x float>, ptr addrspace(8), i32, i32, i32) declare void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float>, ptr addrspace(8), i32, i32, i32) -declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32) -declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32) +declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8), i32, i32) +declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8), i32, i32) diff --git a/llvm/test/Transforms/EarlyCSE/AMDGPU/intrinsics.ll b/llvm/test/Transforms/EarlyCSE/AMDGPU/intrinsics.ll index b9837b374facb..2b8de9efe2754 100644 --- a/llvm/test/Transforms/EarlyCSE/AMDGPU/intrinsics.ll +++ b/llvm/test/Transforms/EarlyCSE/AMDGPU/intrinsics.ll @@ -1,9 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 ; RUN: opt < %s -S -mtriple=amdgpu-- -passes=early-cse -earlycse-debug-hash | FileCheck %s -; CHECK-LABEL: @no_cse -; CHECK: call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 0, i32 0) -; CHECK: call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 4, i32 0) define void @no_cse(ptr addrspace(1) %out, <4 x i32> %in) { +; CHECK-LABEL: define void @no_cse( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], <4 x i32> [[IN:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> [[IN]], i32 0, i32 0) +; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> [[IN]], i32 4, i32 0) +; CHECK-NEXT: [[C:%.*]] = add i32 [[A]], [[B]] +; CHECK-NEXT: store i32 [[C]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; %a = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 0, i32 0) %b = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 4, i32 0) %c = add i32 %a, %b @@ -11,10 +17,14 @@ define void @no_cse(ptr addrspace(1) %out, <4 x i32> %in) { ret void } -; CHECK-LABEL: @cse_zero_offset -; CHECK: [[CSE:%[a-z0-9A-Z]+]] = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 0, i32 0) -; CHECK: add i32 [[CSE]], [[CSE]] define void @cse_zero_offset(ptr addrspace(1) %out, <4 x i32> %in) { +; CHECK-LABEL: define void @cse_zero_offset( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], <4 x i32> [[IN:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> [[IN]], i32 0, i32 0) +; CHECK-NEXT: [[C:%.*]] = add i32 [[A]], [[A]] +; CHECK-NEXT: store i32 [[C]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; %a = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 0, i32 0) %b = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 0, i32 0) %c = add i32 %a, %b @@ -22,10 +32,14 @@ define void @cse_zero_offset(ptr addrspace(1) %out, <4 x i32> %in) { ret void } -; CHECK-LABEL: @cse_nonzero_offset -; CHECK: [[CSE:%[a-z0-9A-Z]+]] = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 4, i32 0) -; CHECK: add i32 [[CSE]], [[CSE]] define void @cse_nonzero_offset(ptr addrspace(1) %out, <4 x i32> %in) { +; CHECK-LABEL: define void @cse_nonzero_offset( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], <4 x i32> [[IN:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> [[IN]], i32 4, i32 0) +; CHECK-NEXT: [[C:%.*]] = add i32 [[A]], [[A]] +; CHECK-NEXT: store i32 [[C]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; %a = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 4, i32 0) %b = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 4, i32 0) %c = add i32 %a, %b @@ -33,4 +47,56 @@ define void @cse_nonzero_offset(ptr addrspace(1) %out, <4 x i32> %in) { ret void } +define void @ptr_no_cse(ptr addrspace(1) %out, ptr addrspace(8) %in) { +; CHECK-LABEL: define void @ptr_no_cse( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(8) [[IN:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) [[IN]], i32 0, i32 0), !invariant.load [[META0:![0-9]+]] +; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) [[IN]], i32 4, i32 0), !invariant.load [[META0]] +; CHECK-NEXT: [[C:%.*]] = add i32 [[A]], [[B]] +; CHECK-NEXT: store i32 [[C]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; + %a = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %in, i32 0, i32 0), !invariant.load !0 + %b = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %in, i32 4, i32 0), !invariant.load !0 + %c = add i32 %a, %b + store i32 %c, ptr addrspace(1) %out + ret void +} + +define void @ptr_cse_zero_offset(ptr addrspace(1) %out, ptr addrspace(8) %in) { +; CHECK-LABEL: define void @ptr_cse_zero_offset( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(8) [[IN:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) [[IN]], i32 0, i32 0), !invariant.load [[META0]] +; CHECK-NEXT: [[C:%.*]] = add i32 [[A]], [[A]] +; CHECK-NEXT: store i32 [[C]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; + %a = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %in, i32 0, i32 0), !invariant.load !0 + %b = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %in, i32 0, i32 0), !invariant.load !0 + %c = add i32 %a, %b + store i32 %c, ptr addrspace(1) %out + ret void +} + +define void @ptr_cse_nonzero_offset(ptr addrspace(1) %out, ptr addrspace(8) %in) { +; CHECK-LABEL: define void @ptr_cse_nonzero_offset( +; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(8) [[IN:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) [[IN]], i32 4, i32 0), !invariant.load [[META0]] +; CHECK-NEXT: [[C:%.*]] = add i32 [[A]], [[A]] +; CHECK-NEXT: store i32 [[C]], ptr addrspace(1) [[OUT]], align 4 +; CHECK-NEXT: ret void +; + %a = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %in, i32 4, i32 0), !invariant.load !0 + %b = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %in, i32 4, i32 0), !invariant.load !0 + %c = add i32 %a, %b + store i32 %c, ptr addrspace(1) %out + ret void +} + declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> nocapture, i32, i32) +declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32) + +!0 = !{} +;. +; CHECK: [[META0]] = !{} +;. diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll index 6897f160a500c..73d8f03784014 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll @@ -1196,6 +1196,399 @@ declare <2 x i8> @llvm.amdgcn.s.buffer.load.v2i8(<4 x i32>, i32, i32) #1 declare <3 x i8> @llvm.amdgcn.s.buffer.load.v3i8(<4 x i32>, i32, i32) #1 declare <4 x i8> @llvm.amdgcn.s.buffer.load.v4i8(<4 x i32>, i32, i32) #1 +; -------------------------------------------------------------------- +; llvm.amdgcn.ptr.s.buffer.load +; -------------------------------------------------------------------- + +define amdgpu_ps float @ptr_s_buffer_load_f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @ptr_s_buffer_load_f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1:![0-9]+]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + ret float %data +} + +define amdgpu_ps <2 x float> @ptr_s_buffer_load_v2f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @ptr_s_buffer_load_v2f32( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + ret <2 x float> %data +} + +define amdgpu_ps <4 x float> @ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <4 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + ret <4 x float> %data +} + +define amdgpu_ps float @extract_elt0_ptr_s_buffer_load_v2f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v2f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <2 x float> %data, i32 0 + ret float %elt0 +} + +define amdgpu_ps float @extract_elt1_ptr_s_buffer_load_v2f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v2f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <2 x float> %data, i32 1 + ret float %elt1 +} + +define amdgpu_ps float @extract_elt0_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <4 x float> %data, i32 0 + ret float %elt0 +} + +define amdgpu_ps float @extract_elt1_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x float> %data, i32 1 + ret float %elt1 +} + +define amdgpu_ps float @extract_elt2_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt2_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 8 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x float> %data, i32 2 + ret float %elt1 +} + +define amdgpu_ps float @extract_elt3_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt3_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 12 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x float> %data, i32 3 + ret float %elt1 +} + +define amdgpu_ps <2 x float> @extract_elt0_elt1_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +define amdgpu_ps <2 x float> @extract_elt1_elt2_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_elt2_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +define amdgpu_ps <2 x float> @extract_elt2_elt3_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt2_elt3_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 8 +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_elt2_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <3 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> + ret <3 x float> %shuf +} + +define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt2_elt3_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x float> [[DATA]], <4 x float> poison, <3 x i32> +; CHECK-NEXT: ret <3 x float> [[SHUF]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> + ret <3 x float> %shuf +} + +define amdgpu_ps float @extract_elt0_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <3 x float> %data, i32 0 + ret float %elt0 +} + +define amdgpu_ps float @extract_elt1_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <3 x float> %data, i32 1 + ret float %elt1 +} + +define amdgpu_ps float @extract_elt2_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt2_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 8 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <3 x float> %data, i32 2 + ret float %elt1 +} + +define amdgpu_ps <2 x float> @extract_elt0_elt1_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <3 x float> %data, <3 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +define amdgpu_ps <2 x float> @extract_elt1_elt2_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_elt2_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <3 x float> %data, <3 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +; Do not trim to vec3 ptr_s_buffer_load in instcombine, as the load will most likely be widened +; to vec4 anyway during lowering. +define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_elt2_elt3_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x float> [[DATA]], <4 x float> poison, <3 x i32> +; CHECK-NEXT: ret <3 x float> [[SHUF]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> + ret <3 x float> %shuf +} + +define i32 @extract0_bitcast_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract0_bitcast_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[VAR:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: [[VAR2:%.*]] = bitcast float [[VAR]] to i32 +; CHECK-NEXT: ret i32 [[VAR2]] +; + %var = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %var1 = bitcast <4 x float> %var to <4 x i32> + %var2 = extractelement <4 x i32> %var1, i32 0 + ret i32 %var2 +} + +define float @extract0_bitcast_ptr_s_buffer_load_v4i32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract0_bitcast_ptr_s_buffer_load_v4i32( +; CHECK-NEXT: [[VAR:%.*]] = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: [[VAR2:%.*]] = bitcast i32 [[VAR]] to float +; CHECK-NEXT: ret float [[VAR2]] +; + %var = call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %var1 = bitcast <4 x i32> %var to <4 x float> + %var2 = extractelement <4 x float> %var1, i32 0 + ret float %var2 +} + +define amdgpu_ps float @preserve_metadata_extract_elt0_ptr_s_buffer_load_v2f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @preserve_metadata_extract_elt0_ptr_s_buffer_load_v2f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !fpmath [[META0]], !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !fpmath !0, !invariant.load !1 + %elt0 = extractelement <2 x float> %data, i32 0 + ret float %elt0 +} + +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32) #1 +declare <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8), i32, i32) #1 +declare <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8), i32, i32) #1 +declare <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8), i32, i32) #1 +declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8), i32, i32) #1 + +define amdgpu_ps half @extract_elt0_ptr_s_buffer_load_v2f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v2f16( +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <2 x half> @llvm.amdgcn.ptr.s.buffer.load.v2f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <2 x half> %data, i32 0 + ret half %elt0 +} + +define amdgpu_ps half @extract_elt1_ptr_s_buffer_load_v2f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v2f16( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 2 +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <2 x half> @llvm.amdgcn.ptr.s.buffer.load.v2f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <2 x half> %data, i32 1 + ret half %elt1 +} + +define amdgpu_ps half @extract_elt1_ptr_s_buffer_load_v3f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v3f16( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 2 +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <3 x half> @llvm.amdgcn.ptr.s.buffer.load.v3f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <3 x half> %data, i32 1 + ret half %elt1 +} + +define amdgpu_ps half @extract_elt1_ptr_s_buffer_load_v4f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v4f16( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 2 +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <4 x half> @llvm.amdgcn.ptr.s.buffer.load.v4f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x half> %data, i32 1 + ret half %elt1 +} + + +define amdgpu_ps half @extract_elt3_ptr_s_buffer_load_v4f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt3_ptr_s_buffer_load_v4f16( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 6 +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <4 x half> @llvm.amdgcn.ptr.s.buffer.load.v4f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x half> %data, i32 3 + ret half %elt1 +} + +define amdgpu_ps <2 x half> @extract_elt0_elt1_ptr_s_buffer_load_v4f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_ptr_s_buffer_load_v4f16( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x half> @llvm.amdgcn.ptr.s.buffer.load.v2f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x half> [[DATA]] +; + %data = call <4 x half> @llvm.amdgcn.ptr.s.buffer.load.v4f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x half> %data, <4 x half> poison, <2 x i32> + ret <2 x half> %shuf +} + +declare half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8), i32, i32) #1 +declare <2 x half> @llvm.amdgcn.ptr.s.buffer.load.v2f16(ptr addrspace(8), i32, i32) #1 +declare <3 x half> @llvm.amdgcn.ptr.s.buffer.load.v3f16(ptr addrspace(8), i32, i32) #1 +declare <4 x half> @llvm.amdgcn.ptr.s.buffer.load.v4f16(ptr addrspace(8), i32, i32) #1 + +define amdgpu_ps i8 @extract_elt0_ptr_s_buffer_load_v2i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v2i8( +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <2 x i8> @llvm.amdgcn.ptr.s.buffer.load.v2i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <2 x i8> %data, i32 0 + ret i8 %elt0 +} + +define amdgpu_ps i8 @extract_elt1_ptr_s_buffer_load_v2i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v2i8( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 1 +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <2 x i8> @llvm.amdgcn.ptr.s.buffer.load.v2i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <2 x i8> %data, i32 1 + ret i8 %elt1 +} + +define amdgpu_ps i8 @extract_elt1_ptr_s_buffer_load_v3i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v3i8( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 1 +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <3 x i8> @llvm.amdgcn.ptr.s.buffer.load.v3i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <3 x i8> %data, i32 1 + ret i8 %elt1 +} + +define amdgpu_ps i8 @extract_elt1_ptr_s_buffer_load_v4i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v4i8( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 1 +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <4 x i8> @llvm.amdgcn.ptr.s.buffer.load.v4i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x i8> %data, i32 1 + ret i8 %elt1 +} + +define amdgpu_ps i8 @extract_elt3_ptr_s_buffer_load_v4i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt3_ptr_s_buffer_load_v4i8( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 3 +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <4 x i8> @llvm.amdgcn.ptr.s.buffer.load.v4i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x i8> %data, i32 3 + ret i8 %elt1 +} + +define amdgpu_ps <2 x i8> @extract_elt0_elt1_ptr_s_buffer_load_v4i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_ptr_s_buffer_load_v4i8( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x i8> @llvm.amdgcn.ptr.s.buffer.load.v2i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x i8> [[DATA]] +; + %data = call <4 x i8> @llvm.amdgcn.ptr.s.buffer.load.v4i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x i8> %data, <4 x i8> poison, <2 x i32> + ret <2 x i8> %shuf +} + +declare i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8), i32, i32) #1 +declare <2 x i8> @llvm.amdgcn.ptr.s.buffer.load.v2i8(ptr addrspace(8), i32, i32) #1 +declare <3 x i8> @llvm.amdgcn.ptr.s.buffer.load.v3i8(ptr addrspace(8), i32, i32) #1 +declare <4 x i8> @llvm.amdgcn.ptr.s.buffer.load.v4i8(ptr addrspace(8), i32, i32) #1 + ; -------------------------------------------------------------------- ; llvm.amdgcn.raw.buffer.load.format ; -------------------------------------------------------------------- @@ -5406,3 +5799,4 @@ attributes #0 = { nounwind } attributes #1 = { nounwind readonly } !0 = !{float 2.500000e+00} +!1 = !{} diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll index d0f23250f3177..f8cebe1c42aae 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll @@ -1196,6 +1196,399 @@ declare <2 x i8> @llvm.amdgcn.s.buffer.load.v2i8(<4 x i32>, i32, i32) #1 declare <3 x i8> @llvm.amdgcn.s.buffer.load.v3i8(<4 x i32>, i32, i32) #1 declare <4 x i8> @llvm.amdgcn.s.buffer.load.v4i8(<4 x i32>, i32, i32) #1 +; -------------------------------------------------------------------- +; llvm.amdgcn.ptr.s.buffer.load +; -------------------------------------------------------------------- + +define amdgpu_ps float @ptr_s_buffer_load_f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @ptr_s_buffer_load_f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1:![0-9]+]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + ret float %data +} + +define amdgpu_ps <2 x float> @ptr_s_buffer_load_v2f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @ptr_s_buffer_load_v2f32( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + ret <2 x float> %data +} + +define amdgpu_ps <4 x float> @ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <4 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + ret <4 x float> %data +} + +define amdgpu_ps float @extract_elt0_ptr_s_buffer_load_v2f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v2f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <2 x float> %data, i32 0 + ret float %elt0 +} + +define amdgpu_ps float @extract_elt1_ptr_s_buffer_load_v2f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v2f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <2 x float> %data, i32 1 + ret float %elt1 +} + +define amdgpu_ps float @extract_elt0_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <4 x float> %data, i32 0 + ret float %elt0 +} + +define amdgpu_ps float @extract_elt1_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x float> %data, i32 1 + ret float %elt1 +} + +define amdgpu_ps float @extract_elt2_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt2_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 8 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x float> %data, i32 2 + ret float %elt1 +} + +define amdgpu_ps float @extract_elt3_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt3_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 12 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x float> %data, i32 3 + ret float %elt1 +} + +define amdgpu_ps <2 x float> @extract_elt0_elt1_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +define amdgpu_ps <2 x float> @extract_elt1_elt2_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_elt2_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +define amdgpu_ps <2 x float> @extract_elt2_elt3_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt2_elt3_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 8 +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_elt2_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <3 x float> [[DATA]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> + ret <3 x float> %shuf +} + +define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt2_elt3_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x float> [[DATA]], <4 x float> poison, <3 x i32> +; CHECK-NEXT: ret <3 x float> [[SHUF]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> + ret <3 x float> %shuf +} + +define amdgpu_ps float @extract_elt0_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <3 x float> %data, i32 0 + ret float %elt0 +} + +define amdgpu_ps float @extract_elt1_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <3 x float> %data, i32 1 + ret float %elt1 +} + +define amdgpu_ps float @extract_elt2_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt2_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 8 +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <3 x float> %data, i32 2 + ret float %elt1 +} + +define amdgpu_ps <2 x float> @extract_elt0_elt1_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <3 x float> %data, <3 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +define amdgpu_ps <2 x float> @extract_elt1_elt2_ptr_s_buffer_load_v3f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_elt2_ptr_s_buffer_load_v3f32( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 4 +; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x float> [[DATA]] +; + %data = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <3 x float> %data, <3 x float> poison, <2 x i32> + ret <2 x float> %shuf +} + +; Do not trim to vec3 ptr_s_buffer_load in instcombine, as the load will most likely be widened +; to vec4 anyway during lowering. +define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_elt2_elt3_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[DATA:%.*]] = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x float> [[DATA]], <4 x float> poison, <3 x i32> +; CHECK-NEXT: ret <3 x float> [[SHUF]] +; + %data = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> + ret <3 x float> %shuf +} + +define i32 @extract0_bitcast_ptr_s_buffer_load_v4f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract0_bitcast_ptr_s_buffer_load_v4f32( +; CHECK-NEXT: [[VAR:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: [[VAR2:%.*]] = bitcast float [[VAR]] to i32 +; CHECK-NEXT: ret i32 [[VAR2]] +; + %var = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %var1 = bitcast <4 x float> %var to <4 x i32> + %var2 = extractelement <4 x i32> %var1, i32 0 + ret i32 %var2 +} + +define float @extract0_bitcast_ptr_s_buffer_load_v4i32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract0_bitcast_ptr_s_buffer_load_v4i32( +; CHECK-NEXT: [[VAR:%.*]] = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: [[VAR2:%.*]] = bitcast i32 [[VAR]] to float +; CHECK-NEXT: ret float [[VAR2]] +; + %var = call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %var1 = bitcast <4 x i32> %var to <4 x float> + %var2 = extractelement <4 x float> %var1, i32 0 + ret float %var2 +} + +define amdgpu_ps float @preserve_metadata_extract_elt0_ptr_s_buffer_load_v2f32(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @preserve_metadata_extract_elt0_ptr_s_buffer_load_v2f32( +; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !fpmath [[META0]], !invariant.load [[META1]] +; CHECK-NEXT: ret float [[DATA]] +; + %data = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !fpmath !0, !invariant.load !1 + %elt0 = extractelement <2 x float> %data, i32 0 + ret float %elt0 +} + +declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32) #1 +declare <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8), i32, i32) #1 +declare <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8), i32, i32) #1 +declare <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8), i32, i32) #1 +declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8), i32, i32) #1 + +define amdgpu_ps half @extract_elt0_ptr_s_buffer_load_v2f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v2f16( +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <2 x half> @llvm.amdgcn.ptr.s.buffer.load.v2f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <2 x half> %data, i32 0 + ret half %elt0 +} + +define amdgpu_ps half @extract_elt1_ptr_s_buffer_load_v2f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v2f16( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 2 +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <2 x half> @llvm.amdgcn.ptr.s.buffer.load.v2f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <2 x half> %data, i32 1 + ret half %elt1 +} + +define amdgpu_ps half @extract_elt1_ptr_s_buffer_load_v3f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v3f16( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 2 +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <3 x half> @llvm.amdgcn.ptr.s.buffer.load.v3f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <3 x half> %data, i32 1 + ret half %elt1 +} + +define amdgpu_ps half @extract_elt1_ptr_s_buffer_load_v4f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v4f16( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 2 +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <4 x half> @llvm.amdgcn.ptr.s.buffer.load.v4f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x half> %data, i32 1 + ret half %elt1 +} + + +define amdgpu_ps half @extract_elt3_ptr_s_buffer_load_v4f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt3_ptr_s_buffer_load_v4f16( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 6 +; CHECK-NEXT: [[DATA:%.*]] = call half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret half [[DATA]] +; + %data = call <4 x half> @llvm.amdgcn.ptr.s.buffer.load.v4f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x half> %data, i32 3 + ret half %elt1 +} + +define amdgpu_ps <2 x half> @extract_elt0_elt1_ptr_s_buffer_load_v4f16(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_ptr_s_buffer_load_v4f16( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x half> @llvm.amdgcn.ptr.s.buffer.load.v2f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x half> [[DATA]] +; + %data = call <4 x half> @llvm.amdgcn.ptr.s.buffer.load.v4f16(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x half> %data, <4 x half> poison, <2 x i32> + ret <2 x half> %shuf +} + +declare half @llvm.amdgcn.ptr.s.buffer.load.f16(ptr addrspace(8), i32, i32) #1 +declare <2 x half> @llvm.amdgcn.ptr.s.buffer.load.v2f16(ptr addrspace(8), i32, i32) #1 +declare <3 x half> @llvm.amdgcn.ptr.s.buffer.load.v3f16(ptr addrspace(8), i32, i32) #1 +declare <4 x half> @llvm.amdgcn.ptr.s.buffer.load.v4f16(ptr addrspace(8), i32, i32) #1 + +define amdgpu_ps i8 @extract_elt0_ptr_s_buffer_load_v2i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_ptr_s_buffer_load_v2i8( +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <2 x i8> @llvm.amdgcn.ptr.s.buffer.load.v2i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt0 = extractelement <2 x i8> %data, i32 0 + ret i8 %elt0 +} + +define amdgpu_ps i8 @extract_elt1_ptr_s_buffer_load_v2i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v2i8( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 1 +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <2 x i8> @llvm.amdgcn.ptr.s.buffer.load.v2i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <2 x i8> %data, i32 1 + ret i8 %elt1 +} + +define amdgpu_ps i8 @extract_elt1_ptr_s_buffer_load_v3i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v3i8( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 1 +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <3 x i8> @llvm.amdgcn.ptr.s.buffer.load.v3i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <3 x i8> %data, i32 1 + ret i8 %elt1 +} + +define amdgpu_ps i8 @extract_elt1_ptr_s_buffer_load_v4i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt1_ptr_s_buffer_load_v4i8( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 1 +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <4 x i8> @llvm.amdgcn.ptr.s.buffer.load.v4i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x i8> %data, i32 1 + ret i8 %elt1 +} + +define amdgpu_ps i8 @extract_elt3_ptr_s_buffer_load_v4i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt3_ptr_s_buffer_load_v4i8( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[OFS:%.*]], 3 +; CHECK-NEXT: [[DATA:%.*]] = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[TMP1]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret i8 [[DATA]] +; + %data = call <4 x i8> @llvm.amdgcn.ptr.s.buffer.load.v4i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %elt1 = extractelement <4 x i8> %data, i32 3 + ret i8 %elt1 +} + +define amdgpu_ps <2 x i8> @extract_elt0_elt1_ptr_s_buffer_load_v4i8(ptr addrspace(8) inreg %rsrc, i32 %ofs) #0 { +; CHECK-LABEL: @extract_elt0_elt1_ptr_s_buffer_load_v4i8( +; CHECK-NEXT: [[DATA:%.*]] = call <2 x i8> @llvm.amdgcn.ptr.s.buffer.load.v2i8(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFS:%.*]], i32 0), !invariant.load [[META1]] +; CHECK-NEXT: ret <2 x i8> [[DATA]] +; + %data = call <4 x i8> @llvm.amdgcn.ptr.s.buffer.load.v4i8(ptr addrspace(8) %rsrc, i32 %ofs, i32 0), !invariant.load !1 + %shuf = shufflevector <4 x i8> %data, <4 x i8> poison, <2 x i32> + ret <2 x i8> %shuf +} + +declare i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8), i32, i32) #1 +declare <2 x i8> @llvm.amdgcn.ptr.s.buffer.load.v2i8(ptr addrspace(8), i32, i32) #1 +declare <3 x i8> @llvm.amdgcn.ptr.s.buffer.load.v3i8(ptr addrspace(8), i32, i32) #1 +declare <4 x i8> @llvm.amdgcn.ptr.s.buffer.load.v4i8(ptr addrspace(8), i32, i32) #1 + ; -------------------------------------------------------------------- ; llvm.amdgcn.raw.buffer.load.format ; -------------------------------------------------------------------- @@ -5433,3 +5826,4 @@ attributes #1 = { nounwind readonly } attributes #3 = { "amdgpu-test-callsite-attr" } !0 = !{float 2.500000e+00} +!1 = !{} diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td index ba185dc27dc7e..f1195e9c644d5 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td @@ -1999,6 +1999,24 @@ def ROCDL_RawPtrBufferLoadOp : }]; } +def ROCDL_PtrSBufferLoadOp : + ROCDL_IntrOp<"ptr.s.buffer.load", [0], [], [], 1, 0, 1, 0, [2], ["aux"]> { + dag args = (ins Arg:$rsrc, + I32:$offset, + ROCDL_DefaultCachePolicyAttr:$aux); + let arguments = !con(args, baseArgs); + let assemblyFormat = "$rsrc `,` $offset `,` custom($aux) attr-dict `:` type($res)"; + string llvmBuilder = baseLlvmBuilder # [{ + llvm::MDNode *metadata = llvm::MDNode::get(inst->getContext(), {}); + inst->setMetadata(llvm::LLVMContext::MD_invariant_load, metadata); + }] # setAliasAnalysisMetadataCode # baseLlvmBuilderCoda; + let extraClassDefinition = [{ + ::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() { + return {getRsrc()}; + } + }]; +} + def ROCDL_RawPtrBufferLoadLdsOp : ROCDL_IntrOp<"raw.ptr.buffer.load.lds", [], [], [], 0, 0, 1, 0, [6], ["aux"]> { dag args = (ins Arg:$rsrc, diff --git a/mlir/test/Dialect/LLVMIR/rocdl.mlir b/mlir/test/Dialect/LLVMIR/rocdl.mlir index dd0b00faf7f1f..416f2edca3fbe 100644 --- a/mlir/test/Dialect/LLVMIR/rocdl.mlir +++ b/mlir/test/Dialect/LLVMIR/rocdl.mlir @@ -909,6 +909,17 @@ llvm.func @rocdl.raw.ptr.buffer.f32(%rsrc : !llvm.ptr<8>, llvm.return } +llvm.func @rocdl.ptr.s.buffer(%rsrc : !llvm.ptr<8>, %offset : i32) { + // CHECK-LABEL: rocdl.ptr.s.buffer + // CHECK: %{{.*}} = rocdl.ptr.s.buffer.load %{{.*}}, %{{.*}}, 0 : i32 + // CHECK: %{{.*}} = rocdl.ptr.s.buffer.load %{{.*}}, %{{.*}}, 0 : vector<2xi32> + // CHECK: %{{.*}} = rocdl.ptr.s.buffer.load %{{.*}}, %{{.*}}, 0 : vector<4xi32> + %r1 = rocdl.ptr.s.buffer.load %rsrc, %offset, 0 : i32 + %r2 = rocdl.ptr.s.buffer.load %rsrc, %offset, 0 : vector<2xi32> + %r4 = rocdl.ptr.s.buffer.load %rsrc, %offset, 0 : vector<4xi32> + llvm.return +} + llvm.func @rocdl.raw.ptr.buffer.load.lds(%rsrc : !llvm.ptr<8>, %dstLds : !llvm.ptr<3>, %size: i32, %voffset : i32, %soffset : i32, %offset : i32, %aux : i32) { diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir index 9b767d8574473..2a001fb860c3d 100644 --- a/mlir/test/Target/LLVMIR/rocdl.mlir +++ b/mlir/test/Target/LLVMIR/rocdl.mlir @@ -1544,6 +1544,17 @@ llvm.func @rocdl.raw.ptr.buffer(%rsrc : !llvm.ptr<8>, llvm.return } +llvm.func @rocdl.ptr.s.buffer(%rsrc : !llvm.ptr<8>, %offset : i32) { + // CHECK-LABEL: rocdl.ptr.s.buffer + // CHECK: call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 0){{.*}}!invariant.load + // CHECK: call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 0){{.*}}!invariant.load + // CHECK: call <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 0){{.*}}!invariant.load + %r1 = rocdl.ptr.s.buffer.load %rsrc, %offset, 0 : i32 + %r2 = rocdl.ptr.s.buffer.load %rsrc, %offset, 0 : vector<2xi32> + %r4 = rocdl.ptr.s.buffer.load %rsrc, %offset, 0 : vector<4xi32> + llvm.return +} + llvm.func @rocdl.raw.ptr.buffer.load.lds(%rsrc : !llvm.ptr<8>, %dstLds : !llvm.ptr<3>, %voffset : i32, %soffset : i32) { %size = llvm.mlir.constant(4 : i32) : i32