From 24790a30ace1dd162ba9602475e1c965afe467c7 Mon Sep 17 00:00:00 2001 From: windstormer Date: Sat, 16 Apr 2016 13:25:07 +0800 Subject: [PATCH 01/32] upload project1 code and modified main.c --- pipeline/simulator/Makefile | 13 + pipeline/simulator/function.c | 158 ++++++++ pipeline/simulator/function.h | 17 + pipeline/simulator/main.c | 127 ++++++ pipeline/simulator/main1.c | 740 ++++++++++++++++++++++++++++++++++ 5 files changed, 1055 insertions(+) create mode 100644 pipeline/simulator/Makefile create mode 100644 pipeline/simulator/function.c create mode 100644 pipeline/simulator/function.h create mode 100644 pipeline/simulator/main.c create mode 100644 pipeline/simulator/main1.c diff --git a/pipeline/simulator/Makefile b/pipeline/simulator/Makefile new file mode 100644 index 0000000..19ae75a --- /dev/null +++ b/pipeline/simulator/Makefile @@ -0,0 +1,13 @@ +CC = gcc -Wall +SRCS = ./*.c +OBS = ./*.o + + +single_cycle: SRC + $(CC) -o $@ $(OBS) + +SRC: $(SRCS) + $(CC) -c $(SRCS) + +clean: $(OBS) + rm $(OBS) single_cycle \ No newline at end of file diff --git a/pipeline/simulator/function.c b/pipeline/simulator/function.c new file mode 100644 index 0000000..3f562da --- /dev/null +++ b/pipeline/simulator/function.c @@ -0,0 +1,158 @@ +#include "function.h" +#include + +int overflow_detect(int ans,int a,int b) +{ + + + if((a>0&&b>0&&ans<=0)||(a<0&&b<0&&ans>=0)) + return 1; + else return 0; + +/* + int x=a>>31; + int y=b>>31; + int z=ans>>31; + if(x==y &&x!=z) + return 1; + else return 0; +*/ +} +unsigned char cut_rs(int a) +{ + unsigned char back; + a<<=6; + back=(unsigned)a>>27; + + // printf("%x ",back); + return back; +} +unsigned char cut_rt(int a) +{ + unsigned char back; + a<<=11; + back=(unsigned)a>>27; + + // printf("%x ",back); + return back; +} +unsigned char cut_rd(int a) +{ + unsigned char back; + a<<=16; + back=(unsigned)a>>27; + + // printf("%x ",back); + return back; +} +unsigned char cut_shamt(int a) +{ + unsigned char back; + a<<=21; + back=(unsigned)a>>27; + + //printf("%x ",back); + return back; +} +unsigned char cut_func(int a) +{ + unsigned char back; + a<<=26; + back=(unsigned)a>>26; + + // printf("%x ",back); + return back; +} +short cut_immediate(int a) +{ + short back; + a<<=16; + back=a>>16; + + //printf("%x ",back); + return back; +} + +unsigned short cut_immediate_unsigned(int a) +{ + unsigned short back; + a<<=16; + back=(unsigned)a>>16; + + //printf("%x ",back); + return back; +} +unsigned int cut_address(int a) +{ + unsigned int back; + a<<=6; + back=(unsigned)a>>6; + + //printf("%x ",back); + return back; +} + + +unsigned int combine(unsigned char a,unsigned char b,unsigned char c,unsigned char d) +{ + + unsigned int back=0; + back |= a; + back <<= 8; + back |= b; + back <<= 8; + back |= c; + back <<= 8; + back |= d; + return back; + +} +unsigned short combine_two(unsigned char a, unsigned char b) +{ + unsigned short back=0; + back |= a; + back <<= 8; + back |= b; + return back; +} + +unsigned char* seperate(int in) +{ + unsigned char* back; + back=(unsigned char*)malloc(sizeof(unsigned char)*4); + int a,b,c,d; + a=in,b=in,c=in,d=in; + + a=(unsigned)a>>24; + b=b<<8; + b=(unsigned)b>>24; + c=c<<16; + c=(unsigned)c>>24; + d=d<<24; + d=(unsigned)d>>24; + back[0]=(unsigned char)a; + back[1]=(unsigned char)b; + back[2]=(unsigned char)c; + back[3]=(unsigned char)d; + + return back; +} +unsigned char* seperate_two(int in) +{ + unsigned char* back; + back=(unsigned char*)malloc(sizeof(char)*2); + + in&=0x0000FFFF; + + int c,d; + c=in,d=in; + + c=c<<16; + c=(unsigned)c>>24; + d=d<<24; + d=(unsigned)d>>24; + back[0]=(unsigned char)c; + back[1]=(unsigned char)d; + + return back; +} diff --git a/pipeline/simulator/function.h b/pipeline/simulator/function.h new file mode 100644 index 0000000..526bb48 --- /dev/null +++ b/pipeline/simulator/function.h @@ -0,0 +1,17 @@ +#include +#include + + +int overflow_detect(int ans,int a,int b); +unsigned char cut_rs(int a); +unsigned char cut_rt(int a); +unsigned char cut_rd(int a); +unsigned char cut_shamt(int a); +unsigned char cut_func(int a); +short cut_immediate(int a); +unsigned short cut_immediate_unsigned(int a); +unsigned int cut_address(int a); +unsigned int combine(unsigned char a,unsigned char b,unsigned char c,unsigned char d); +unsigned short combine_two(unsigned char a, unsigned char b); +unsigned char* seperate(int in); +unsigned char* seperate_two(int in); diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c new file mode 100644 index 0000000..bd162b7 --- /dev/null +++ b/pipeline/simulator/main.c @@ -0,0 +1,127 @@ +#include +#include +#include "function.h" + + +typedef struct _IFID{ + int instruction; + int PC; +}IF_ID; + +typedef struct _IDEX{ + int instruction; + int PC; + int read_data1; + int read_data2; + int immediate_ext; +}ID_EX; + +typedef struct _EXDM{ + int instruction; + int PC; + int ALU_result; + int read_data2; +}EX_DM; + +typedef struct _DMWB{ + int instruction; + unsigned int address; + int data; +}DM_WB; + + + + +int reg[32]; +int PC; +int PC_start; +unsigned char ii[1024]; +unsigned char di[1024]; +int iim[256]; +unsigned char dim[1024]; +int temp; + +int main(void) +{ + FILE *iimage = fopen("./iimage.bin","rb"); + FILE *dimage = fopen("./dimage.bin","rb"); + FILE *error = fopen("./error_dump.rpt","w"); + FILE *snapshot = fopen("./snapshot.rpt","w"); + + + + + int sdata=0,sins=0; + int i,j; + + + memset(reg,0,sizeof(reg)); + memset(ii,0,sizeof(ii)); + memset(di,0,sizeof(di)); + memset(iim,0,sizeof(iim)); + memset(dim,0,sizeof(dim)); + PC=0; + + fseek(iimage , 0 , SEEK_END); + + + rewind (iimage); + + fread(ii,sizeof(unsigned char),8,iimage); + + fseek(dimage , 0 , SEEK_END); + + + rewind (dimage); + + fread(di,sizeof(unsigned char),8,dimage); + + /* + for(i=0;i +#include +#include "function.h" + + + + +int reg[32]; +int PC; +int PC_start; +unsigned char ii[1024]; +unsigned char di[1024]; +int iim[256]; +unsigned char dim[1024]; +int temp; + +int main(void) +{ + FILE *iimage = fopen("./iimage.bin","rb"); + FILE *dimage = fopen("./dimage.bin","rb"); + FILE *error = fopen("./error_dump.rpt","w"); + FILE *snapshot = fopen("./snapshot.rpt","w"); + + + + + int sdata=0,sins=0; + int i,j; + + + memset(reg,0,sizeof(reg)); + memset(ii,0,sizeof(ii)); + memset(di,0,sizeof(di)); + memset(iim,0,sizeof(iim)); + memset(dim,0,sizeof(dim)); + PC=0; + + fseek(iimage , 0 , SEEK_END); + + + rewind (iimage); + + fread(ii,sizeof(unsigned char),8,iimage); + + fseek(dimage , 0 , SEEK_END); + + + rewind (dimage); + + fread(di,sizeof(unsigned char),8,dimage); + + /* + for(i=0;i=PC_start) + { + op=(unsigned)iim[i]>>26; + + + + + switch(op) + { + case 0x00: + { + funct=cut_func(iim[i]); + + switch(funct) + { + case 0x20: + { + + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + if(rd==0) + errors[0]=1; + + temp=reg[rs]+reg[rt]; + if(overflow_detect(temp,reg[rs],reg[rt])) + errors[1]=1; + reg[rd]=reg[rs]+reg[rt]; ///need overflow detect + if(rd==0) + reg[rd]=0; + PC+=4; + break; + } + case 0x21: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + if(rd==0) + errors[0]=1; + reg[rd]=reg[rs]+reg[rt]; + if(rd==0) + reg[rd]=0; + PC+=4; + break; + } + case 0x22: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + if(rd==0) + errors[0]=1; + temp=reg[rs]+(-1)*reg[rt]; + + if(overflow_detect(temp,reg[rs],(-1)*reg[rt])) + errors[1]=1; + reg[rd]=reg[rs]+(-1)*reg[rt]; + if(rd==0) + reg[rd]=0; + PC+=4; + break; + } + case 0x24: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + if(rd==0) + errors[0]=1; + else + reg[rd]=reg[rs]®[rt]; + PC+=4; + break; + } + case 0x25: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + if(rd==0) + errors[0]=1; + else + reg[rd]=reg[rs]|reg[rt]; + PC+=4; + break; + } + case 0x26: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + if(rd==0) + errors[0]=1; + else + reg[rd]=reg[rs]^reg[rt]; + PC+=4; + break; + } + case 0x27: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + if(rd==0) + errors[0]=1; + else + reg[rd]=~(reg[rs]|reg[rt]); + PC+=4; + break; + } + case 0x28: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + if(rd==0) + errors[0]=1; + else + reg[rd]=~(reg[rs]®[rt]); + PC+=4; + break; + } + case 0x2A: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + if(rd==0) + errors[0]=1; + else + { + if(reg[rs]>shamt; + PC+=4; + break; + } + case 0x03: + { + rt=cut_rt(iim[i]); + rd=cut_rd(iim[i]); + shamt=cut_shamt(iim[i]); + if(rd==0) + errors[0]=1; + else + reg[rd]=reg[rt]>>shamt; + PC+=4; + break; + } + case 0x08: + { + + rs=cut_rs(iim[i]); + PC=reg[rs]; + break; + } + + } + break; + } + case 0x08: + { + + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + if(rt==0) + errors[0]=1; + temp=reg[rs]+immediate; + + + if(overflow_detect(temp,reg[rs],(int)immediate)) + errors[1]=1; + reg[rt]=reg[rs]+immediate; ///need overflow detect + if(rt==0) + reg[rt]=0; + PC+=4; + break; + } + case 0x09: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + if(rt==0) + errors[0]=1; + else + reg[rt]=reg[rs]+immediate; + PC+=4; + break; + } + case 0x23: + { + + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + if(rt==0) + errors[0]=1; + + read= reg[rs]+immediate; ///need overflow detect && data misaligned + if(overflow_detect(read,reg[rs],(int)immediate)) + errors[1]=1; + if(read>=1021 || read<0) + { + errors[2]=1; + flag=1; + + } + if(read%4!=0) + { + errors[3]=1; + flag=1; + + } + if(flag==1) + break; + reg[rt]=(int)combine(dim[read],dim[read+1],dim[read+2],dim[read+3]); + + if(rt==0) + reg[rt]=0; + + + PC+=4; + break; + } + case 0x21: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + if(rt==0) + errors[0]=1; + read= reg[rs]+immediate; ///need overflow detect && data misaligned + if(overflow_detect(read,reg[rs],(int)immediate)) + errors[1]=1; + if(read>=1023 || read<0) + { + errors[2]=1; + flag=1; + + } + if(read%2!=0) + { + errors[3]=1; + flag=1; + + } + if(flag==1)break; + reg[rt]=(short)combine_two(dim[read],dim[read+1]); + if(rt==0) + reg[rt]=0; + + PC+=4; + break; + } + case 0x25: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + if(rt==0) + errors[0]=1; + + read= reg[rs]+immediate; ///need overflow detect && data misaligned + if(overflow_detect(read,reg[rs],(int)immediate)) + errors[1]=1; + if(read>=1023 || read <0) + { + errors[2]=1; + flag=1; + + } + if(read%2!=0) + { + errors[3]=1; + flag=1; + + } + if(flag==1)break; + reg[rt]=combine_two(dim[read],dim[read+1]); + if(rt==0) + reg[rt]=0; + + PC+=4; + break; + } + case 0x20: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + if(rt==0) + errors[0]=1; + + read= reg[rs]+immediate; ///need overflow detect && data misaligned + if(overflow_detect(read,reg[rs],(int)immediate)) + errors[1]=1; + if(read>=1024 || read<0) + { + errors[2]=1; + flag=1; + + } + if(flag==1)break; + reg[rt]=(char)dim[read]; + if(rt==0) + reg[rt]=0; + + PC+=4; + break; + } + case 0x24: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + if(rt==0) + errors[0]=1; + + read= reg[rs]+immediate; ///need overflow detect && data misaligned + if(overflow_detect(read,reg[rs],(int)immediate)) + errors[1]=1; + if(read>=1024 || read<0) + { + errors[2]=1; + flag=1; + + } + if(flag==1)break; + reg[rt]=(unsigned)dim[read]; + if(rt==0) + reg[rt]=0; + + PC+=4; + break; + } + case 0x2B: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + + getting=seperate(reg[rt]); + read= reg[rs]+immediate; ///need overflow detect && data misaligned + if(overflow_detect(read,reg[rs],(int)immediate)) + errors[1]=1; + if(read>=1021 || read<0) + { + errors[2]=1; + flag=1; + + } + if(read%4!=0) + { + errors[3]=1; + flag=1; + + } + if(flag==1)break; + dim[read]=getting[0]; + dim[read+1]=getting[1]; + dim[read+2]=getting[2]; + dim[read+3]=getting[3]; + + PC+=4; + break; + } + case 0x29: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + getting=seperate_two(reg[rt]); + read= reg[rs]+immediate; ///need overflow detect && data misaligned + if(overflow_detect(read,reg[rs],(int)immediate)) + errors[1]=1; + if(read>=1023 || read<0) + { + errors[2]=1; + flag=1; + + } + if(read%2!=0) + { + errors[3]=1; + flag=1; + + } + if(flag==1)break; + dim[read]=getting[0]; + dim[read+1]=getting[1]; + PC+=4; + break; + } + case 0x28: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + getting[0]=(unsigned char)(reg[rt]&0x000000FF); + read= reg[rs]+immediate; ///need overflow detect && data misaligned + if(overflow_detect(read,reg[rs],(int)immediate)) + errors[1]=1; + if(read>=1024 || read<0) + { + errors[2]=1; + flag=1; + + } + if(flag==1)break; + dim[read]=getting[0]; + PC+=4; + break; + } + case 0x0F: + { + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + if(rt==0) + errors[0]=1; + else + reg[rt]=immediate<<16; + PC+=4; + break; + } + case 0x0C: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + unsigned_immediate=cut_immediate_unsigned(iim[i]); + if(rt==0) + errors[0]=1; + else + reg[rt]=reg[rs]&unsigned_immediate; + PC+=4; + break; + } + case 0x0D: + { + + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + unsigned_immediate=cut_immediate_unsigned(iim[i]); + + if(rt==0) + errors[0]=1; + else + reg[rt]=(reg[rs]|unsigned_immediate); + + PC+=4; + break; + } + case 0x0E: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + unsigned_immediate=cut_immediate_unsigned(iim[i]); + if(rt==0) + errors[0]=1; + else + reg[rt]=~(reg[rs]|unsigned_immediate); + PC+=4; + break; + } + case 0x0A: + { + rs=cut_rs(iim[i]); + rt=cut_rt(iim[i]); + immediate=cut_immediate(iim[i]); + if(rt==0) + errors[0]=1; + else + { + if(reg[rs]0) + { + read=immediate*4+4; ///need overflow detect + if(overflow_detect(read,immediate*4,4)) + errors[1]=1; + PC+=read; + } + else PC+=4; + break; + } + case 0x02: + { + address=cut_address(iim[i]); + address=address<<2; + PC+=4; + PC=(unsigned)PC>>28; + PC=PC<<28; + PC=(unsigned)PC|address; + break; + } + case 0x03: + { + address=cut_address(iim[i]); + address=address<<2; + PC+=4; + reg[31]=PC; + + PC=(unsigned)PC>>28; + PC=PC<<28; + PC=(unsigned)PC|address; + break; + } + case 0x3F: + { + // printf("halt\n"); + flag=1; + break; + } + + + } + if(errors[0]==1)fprintf(error,"In cycle %d: Write $0 Error\n",cycle+1); + if(errors[1]==1)fprintf(error,"In cycle %d: Number Overflow\n",cycle+1); + if(errors[2]==1)fprintf(error,"In cycle %d: Address Overflow\n",cycle+1); + if(errors[3]==1)fprintf(error,"In cycle %d: Misalignment Error\n",cycle+1); + } + else PC+=4; + + i=(PC-PC_start)/4; + + + + cycle++; + + fprintf(snapshot,"\n\n"); + + + if(flag==1) break; + } + + return 0; +} From 3291133ecbafba2064023b03272b8fb1efed07ae Mon Sep 17 00:00:00 2001 From: windstormer Date: Fri, 22 Apr 2016 15:57:18 +0800 Subject: [PATCH 02/32] finish DM state, add state_structure.txt --- pipeline/simulator/main.c | 286 ++++++++++++++++++++++++- pipeline/simulator/state_structure.txt | 196 +++++++++++++++++ 2 files changed, 478 insertions(+), 4 deletions(-) create mode 100644 pipeline/simulator/state_structure.txt diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index bd162b7..187728d 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -14,6 +14,7 @@ typedef struct _IDEX{ int read_data1; int read_data2; int immediate_ext; + int write_reg; }ID_EX; typedef struct _EXDM{ @@ -21,12 +22,14 @@ typedef struct _EXDM{ int PC; int ALU_result; int read_data2; + int write_reg; }EX_DM; typedef struct _DMWB{ int instruction; - unsigned int address; + int address; int data; + int write_reg; }DM_WB; @@ -41,6 +44,283 @@ int iim[256]; unsigned char dim[1024]; int temp; +void DM(){ + unsigned char *getting; + + op=(unsigned)DM_WB.instruction>>26; + + + + + switch(op) + { + case 0x00: + { + funct=cut_func(DM_WB.instruction); + + switch(funct) + { + case 0x20: ///add + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x21: ///addu + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x22: ///sub + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x24: ///and + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x25: ///or + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x26: ///xor + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x27: ///nor + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x28: ///nand + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x2A: ///slt + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x00: ///sll + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x02: ///srl + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x03: ///sra + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x08: ///jr + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + + } + break; + } + case 0x08: ///addi + { + + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x09: ///addiu + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x23: ///lw + { + + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (int)combine(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1],dim[EX_DM.ALU_result+2],dim[EX_DM.ALU_result+3]); + break; + } + case 0x21: ///lh + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); + break; + } + case 0x25: ///lhu + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); + break; + } + case 0x20: ///lb + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (char)dim[EX_DM.ALU_result]; + break; + } + case 0x24: ///lbu + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (unsigned)dim[EX_DM.ALU_result]; + break; + } + case 0x2B: ///sw + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + getting = seperate(EX_DM.read_data2); + dim[EX_DM.ALU_result]=getting[0]; + dim[EX_DM.ALU_result+1]=getting[1]; + dim[EX_DM.ALU_result+2]=getting[2]; + dim[EX_DM.ALU_result+3]=getting[3]; + DM_WB.data = 0; + break; + } + case 0x29: ///sh + { + + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + getting = seperate_two(EX_DM.read_data2); + dim[EX_DM.ALU_result]=getting[0]; + dim[EX_DM.ALU_result+1]=getting[1]; + DM_WB.data = 0; + break; + } + case 0x28: ///sb + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + getting[0] = (unsigned char)(EX_DM.read_data2&0x000000FF); + dim[EX_DM.ALU_result]=getting[0]; + DM_WB.data = 0; + break; + } + case 0x0F: ///lui + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0C: ///andi + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0D: ///ori + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0E: ///nori + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0A: ///slti + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x04: ///beq + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x05: ///bne + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x07: ///bgtz + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x02: ///j + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x03: ///jal + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x3F: ///halt + { + // printf("halt\n"); + + flag=1; + break; + } + + + } + + } + int main(void) { FILE *iimage = fopen("./iimage.bin","rb"); @@ -118,9 +398,7 @@ int main(void) sdata : int of the number of memory (word) **/ - { - - } + WB(); return 0; diff --git a/pipeline/simulator/state_structure.txt b/pipeline/simulator/state_structure.txt new file mode 100644 index 0000000..7968878 --- /dev/null +++ b/pipeline/simulator/state_structure.txt @@ -0,0 +1,196 @@ +op=(unsigned)DM_WB.instruction>>26; + + + + + switch(op) + { + case 0x00: + { + funct=cut_func(DM_WB.instruction); + + switch(funct) + { + case 0x20: ///add + { + + + break; + } + case 0x21: ///addu + { + + break; + } + case 0x22: ///sub + { + + break; + } + case 0x24: ///and + { + + break; + } + case 0x25: ///or + { + + break; + } + case 0x26: ///xor + { + + break; + } + case 0x27: ///nor + { + + break; + } + case 0x28: ///nand + { + + break; + } + case 0x2A: ///slt + { + + break; + } + case 0x00: ///sll + { + + break; + } + case 0x02: ///srl + { + + break; + } + case 0x03: ///sra + { + + break; + } + case 0x08: ///jr + { + + + break; + } + + } + break; + } + case 0x08: ///addi + { + + + break; + } + case 0x09: ///addiu + { + + break; + } + case 0x23: ///lw + { + + + break; + } + case 0x21: ///lh + { + + break; + } + case 0x25: ///lhu + { + + break; + } + case 0x20: ///lb + { + + break; + } + case 0x24: ///lbu + { + + break; + } + case 0x2B: ///sw + { + + break; + } + case 0x29: ///sh + { + + break; + } + case 0x28: ///sb + { + + break; + } + case 0x0F: ///lui + { + + break; + } + case 0x0C: ///andi + { + + break; + } + case 0x0D: ///ori + { + + + break; + } + case 0x0E: ///nori + { + + break; + } + case 0x0A: ///slti + { + + break; + } + case 0x04: ///beq + { + + break; + } + case 0x05: ///bne + { + + break; + } + case 0x07: ///bgtz + { + + break; + } + case 0x02: ///j + { + + break; + } + case 0x03: ///jal + { + + break; + } + case 0x3F: ///halt + { + // printf("halt\n"); + flag=1; + break; + } + + + } \ No newline at end of file From 756a4a9fd446ad74257bce514e3b1480b7ba341f Mon Sep 17 00:00:00 2001 From: windstormer Date: Fri, 22 Apr 2016 17:30:58 +0800 Subject: [PATCH 03/32] divid into state and state_reg --- pipeline/simulator/main.c | 195 ++++++----------------- pipeline/simulator/state.c | 277 +++++++++++++++++++++++++++++++++ pipeline/simulator/state.h | 5 + pipeline/simulator/state_reg.h | 31 ++++ 4 files changed, 358 insertions(+), 150 deletions(-) create mode 100644 pipeline/simulator/state.c create mode 100644 pipeline/simulator/state.h create mode 100644 pipeline/simulator/state_reg.h diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index 187728d..503a6d0 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -1,38 +1,8 @@ #include #include #include "function.h" - - -typedef struct _IFID{ - int instruction; - int PC; -}IF_ID; - -typedef struct _IDEX{ - int instruction; - int PC; - int read_data1; - int read_data2; - int immediate_ext; - int write_reg; -}ID_EX; - -typedef struct _EXDM{ - int instruction; - int PC; - int ALU_result; - int read_data2; - int write_reg; -}EX_DM; - -typedef struct _DMWB{ - int instruction; - int address; - int data; - int write_reg; -}DM_WB; - - +#include "state.h" +#include "state_reg.h" int reg[32]; @@ -44,10 +14,8 @@ int iim[256]; unsigned char dim[1024]; int temp; -void DM(){ - unsigned char *getting; - - op=(unsigned)DM_WB.instruction>>26; +void WB(){ + op=(unsigned)DM_WB.instruction>>26; @@ -62,93 +30,69 @@ void DM(){ { case 0x20: ///add { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + + break; } case 0x21: ///addu { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x22: ///sub { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x24: ///and { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x25: ///or { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x26: ///xor { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x27: ///nor { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x28: ///nand { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x2A: ///slt { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x00: ///sll { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x02: ///srl { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x03: ///sra { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x08: ///jr { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + + break; } @@ -158,168 +102,116 @@ void DM(){ case 0x08: ///addi { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x09: ///addiu { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x23: ///lw { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (int)combine(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1],dim[EX_DM.ALU_result+2],dim[EX_DM.ALU_result+3]); + break; } case 0x21: ///lh { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); + break; } case 0x25: ///lhu { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); + break; } case 0x20: ///lb { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (char)dim[EX_DM.ALU_result]; + break; } case 0x24: ///lbu { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (unsigned)dim[EX_DM.ALU_result]; + break; } case 0x2B: ///sw { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - getting = seperate(EX_DM.read_data2); - dim[EX_DM.ALU_result]=getting[0]; - dim[EX_DM.ALU_result+1]=getting[1]; - dim[EX_DM.ALU_result+2]=getting[2]; - dim[EX_DM.ALU_result+3]=getting[3]; - DM_WB.data = 0; + break; } case 0x29: ///sh { - - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - getting = seperate_two(EX_DM.read_data2); - dim[EX_DM.ALU_result]=getting[0]; - dim[EX_DM.ALU_result+1]=getting[1]; - DM_WB.data = 0; + break; } case 0x28: ///sb { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - getting[0] = (unsigned char)(EX_DM.read_data2&0x000000FF); - dim[EX_DM.ALU_result]=getting[0]; - DM_WB.data = 0; + break; } case 0x0F: ///lui { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x0C: ///andi { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x0D: ///ori { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + + break; } case 0x0E: ///nori { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x0A: ///slti { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x04: ///beq { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x05: ///bne { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x07: ///bgtz { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x02: ///j { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x03: ///jal { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + break; } case 0x3F: ///halt { // printf("halt\n"); - flag=1; break; } } - - } +} int main(void) { @@ -397,8 +289,11 @@ int main(void) sins: int of the number of instruction sdata : int of the number of memory (word) **/ - WB(); + DM(); + EX(); + ID(); + IF(); return 0; diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c new file mode 100644 index 0000000..5600824 --- /dev/null +++ b/pipeline/simulator/state.c @@ -0,0 +1,277 @@ +#include "state.h" +#include "state_reg.h" + +void DM(){ + unsigned char *getting; + + op=(unsigned)EX_DM.instruction>>26; + + + switch(op) + { + case 0x00: + { + funct=cut_func(DM_WB.instruction); + + switch(funct) + { + case 0x20: ///add + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x21: ///addu + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x22: ///sub + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x24: ///and + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x25: ///or + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x26: ///xor + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x27: ///nor + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x28: ///nand + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x2A: ///slt + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x00: ///sll + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x02: ///srl + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x03: ///sra + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x08: ///jr + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + + } + break; + } + case 0x08: ///addi + { + + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x09: ///addiu + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x23: ///lw + { + + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (int)combine(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1],dim[EX_DM.ALU_result+2],dim[EX_DM.ALU_result+3]); + break; + } + case 0x21: ///lh + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); + break; + } + case 0x25: ///lhu + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); + break; + } + case 0x20: ///lb + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (char)dim[EX_DM.ALU_result]; + break; + } + case 0x24: ///lbu + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (unsigned)dim[EX_DM.ALU_result]; + break; + } + case 0x2B: ///sw + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + getting = seperate(EX_DM.read_data2); + dim[EX_DM.ALU_result]=getting[0]; + dim[EX_DM.ALU_result+1]=getting[1]; + dim[EX_DM.ALU_result+2]=getting[2]; + dim[EX_DM.ALU_result+3]=getting[3]; + DM_WB.data = 0; + break; + } + case 0x29: ///sh + { + + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + getting = seperate_two(EX_DM.read_data2); + dim[EX_DM.ALU_result]=getting[0]; + dim[EX_DM.ALU_result+1]=getting[1]; + DM_WB.data = 0; + break; + } + case 0x28: ///sb + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + getting[0] = (unsigned char)(EX_DM.read_data2&0x000000FF); + dim[EX_DM.ALU_result]=getting[0]; + DM_WB.data = 0; + break; + } + case 0x0F: ///lui + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0C: ///andi + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0D: ///ori + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0E: ///nori + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0A: ///slti + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x04: ///beq + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x05: ///bne + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x07: ///bgtz + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x02: ///j + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x03: ///jal + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x3F: ///halt + { + // printf("halt\n"); + + flag=1; + break; + } + + + } + + } \ No newline at end of file diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h new file mode 100644 index 0000000..2d3a977 --- /dev/null +++ b/pipeline/simulator/state.h @@ -0,0 +1,5 @@ +#include +#include + + +void DM(); \ No newline at end of file diff --git a/pipeline/simulator/state_reg.h b/pipeline/simulator/state_reg.h new file mode 100644 index 0000000..7450c4b --- /dev/null +++ b/pipeline/simulator/state_reg.h @@ -0,0 +1,31 @@ +#include +#include + +typedef struct _IFID{ + int instruction; + int PC; +}IF_ID; + +typedef struct _IDEX{ + int instruction; + int PC; + int read_data1; + int read_data2; + int immediate_ext; + int write_reg; +}ID_EX; + +typedef struct _EXDM{ + int instruction; + int PC; + int ALU_result; + int read_data2; + int write_reg; +}EX_DM; + +typedef struct _DMWB{ + int instruction; + int address; + int data; + int write_reg; +}DM_WB; \ No newline at end of file From 3e5a4a4767d6872603344cfe708803d0aa0085fe Mon Sep 17 00:00:00 2001 From: windstormer Date: Sat, 23 Apr 2016 01:29:39 +0800 Subject: [PATCH 04/32] finish DM,WB add halt condition in main --- pipeline/simulator/main.c | 215 ++---------------------- pipeline/simulator/state.c | 216 ++++++++++++++++++++++++- pipeline/simulator/state.h | 2 +- pipeline/simulator/state_structure.txt | 7 +- 4 files changed, 233 insertions(+), 207 deletions(-) diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index 503a6d0..a13650f 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -14,205 +14,8 @@ int iim[256]; unsigned char dim[1024]; int temp; -void WB(){ - op=(unsigned)DM_WB.instruction>>26; - - - switch(op) - { - case 0x00: - { - funct=cut_func(DM_WB.instruction); - - switch(funct) - { - case 0x20: ///add - { - - - break; - } - case 0x21: ///addu - { - - break; - } - case 0x22: ///sub - { - - break; - } - case 0x24: ///and - { - - break; - } - case 0x25: ///or - { - - break; - } - case 0x26: ///xor - { - - break; - } - case 0x27: ///nor - { - - break; - } - case 0x28: ///nand - { - - break; - } - case 0x2A: ///slt - { - - break; - } - case 0x00: ///sll - { - - break; - } - case 0x02: ///srl - { - - break; - } - case 0x03: ///sra - { - - break; - } - case 0x08: ///jr - { - - - break; - } - - } - break; - } - case 0x08: ///addi - { - - - break; - } - case 0x09: ///addiu - { - - break; - } - case 0x23: ///lw - { - - - break; - } - case 0x21: ///lh - { - - break; - } - case 0x25: ///lhu - { - - break; - } - case 0x20: ///lb - { - - break; - } - case 0x24: ///lbu - { - - break; - } - case 0x2B: ///sw - { - - break; - } - case 0x29: ///sh - { - - break; - } - case 0x28: ///sb - { - - break; - } - case 0x0F: ///lui - { - - break; - } - case 0x0C: ///andi - { - - break; - } - case 0x0D: ///ori - { - - - break; - } - case 0x0E: ///nori - { - - break; - } - case 0x0A: ///slti - { - - break; - } - case 0x04: ///beq - { - - break; - } - case 0x05: ///bne - { - - break; - } - case 0x07: ///bgtz - { - - break; - } - case 0x02: ///j - { - - break; - } - case 0x03: ///jal - { - - break; - } - case 0x3F: ///halt - { - // printf("halt\n"); - flag=1; - break; - } - - - } -} - int main(void) { FILE *iimage = fopen("./iimage.bin","rb"); @@ -289,11 +92,19 @@ int main(void) sins: int of the number of instruction sdata : int of the number of memory (word) **/ - WB(); - DM(); - EX(); - ID(); - IF(); + int check[5]={0}; + while(1) + { + check[0]=WB(); + check[1]=DM(); + check[2]=EX(); + check[3]=ID(); + check[4]=IF(); + +if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) + break; + } + return 0; diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 5600824..9ac51e7 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -1,8 +1,218 @@ #include "state.h" #include "state_reg.h" -void DM(){ +int WB(){ + int flag=0; + + if(DM_WB.instruction==0) return 0; + + op=(unsigned)DM_WB.instruction>>26; + + + + + switch(op) + { + case 0x00: + { + funct=cut_func(DM_WB.instruction); + + switch(funct) + { + case 0x20: ///add + { + reg[DM_WB.write_reg] = DM_WB.address; + + break; + } + case 0x21: ///addu + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x22: ///sub + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x24: ///and + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x25: ///or + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x26: ///xor + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x27: ///nor + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x28: ///nand + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x2A: ///slt + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x00: ///sll + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x02: ///srl + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x03: ///sra + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x08: ///jr + { + + break; + } + + } + break; + } + case 0x08: ///addi + { + reg[DM_WB.write_reg] = DM_WB.address; + + break; + } + case 0x09: ///addiu + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x23: ///lw + { + reg[DM_WB.write_reg] = DM_WB.data; + + break; + } + case 0x21: ///lh + { + reg[DM_WB.write_reg] = DM_WB.data; + break; + } + case 0x25: ///lhu + { + reg[DM_WB.write_reg] = DM_WB.data; + break; + } + case 0x20: ///lb + { + reg[DM_WB.write_reg] = DM_WB.data; + break; + } + case 0x24: ///lbu + { + reg[DM_WB.write_reg] = DM_WB.data; + break; + } + case 0x2B: ///sw + { + + break; + } + case 0x29: ///sh + { + + break; + } + case 0x28: ///sb + { + + break; + } + case 0x0F: ///lui + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x0C: ///andi + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x0D: ///ori + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x0E: ///nori + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x0A: ///slti + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x04: ///beq + { + + break; + } + case 0x05: ///bne + { + + break; + } + case 0x07: ///bgtz + { + + break; + } + case 0x02: ///j + { + + break; + } + case 0x03: ///jal + { + + break; + } + case 0x3F: ///halt + { + + flag=1; + break; + } + + + } + + if(flag==1) return 1; + else return 0; +} + +int DM(){ unsigned char *getting; + int flag=0; + if(EX_DM.instruction==0) + { + DM_WB.instruction=0; + return 0; + } op=(unsigned)EX_DM.instruction>>26; @@ -265,7 +475,6 @@ void DM(){ } case 0x3F: ///halt { - // printf("halt\n"); flag=1; break; @@ -273,5 +482,6 @@ void DM(){ } - + if(flag==1)return 1; + else return 0; } \ No newline at end of file diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index 2d3a977..51dc103 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -1,5 +1,5 @@ #include #include - +void WB(); void DM(); \ No newline at end of file diff --git a/pipeline/simulator/state_structure.txt b/pipeline/simulator/state_structure.txt index 7968878..6472a08 100644 --- a/pipeline/simulator/state_structure.txt +++ b/pipeline/simulator/state_structure.txt @@ -1,3 +1,5 @@ + +int flag=0; op=(unsigned)DM_WB.instruction>>26; @@ -193,4 +195,7 @@ op=(unsigned)DM_WB.instruction>>26; } - } \ No newline at end of file + } + + if(flag==1) return 1; + else return 0; \ No newline at end of file From aa4cd91ad9893d9a992a505422936f5a14d21e0d Mon Sep 17 00:00:00 2001 From: windstormer Date: Sat, 23 Apr 2016 11:50:15 +0800 Subject: [PATCH 05/32] correct running --- pipeline/simulator/main.c | 11 ++-- pipeline/simulator/state.c | 96 +++++++++++++++++++++++++++------- pipeline/simulator/state.h | 20 ++++++- pipeline/simulator/state_reg.h | 31 ----------- 4 files changed, 100 insertions(+), 58 deletions(-) delete mode 100644 pipeline/simulator/state_reg.h diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index a13650f..8b422ca 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -2,7 +2,6 @@ #include #include "function.h" #include "state.h" -#include "state_reg.h" int reg[32]; @@ -27,7 +26,7 @@ int main(void) int sdata=0,sins=0; - int i,j; + int i; memset(reg,0,sizeof(reg)); @@ -92,7 +91,7 @@ int main(void) sins: int of the number of instruction sdata : int of the number of memory (word) **/ - int check[5]={0}; +/* int check[5]={0}; while(1) { check[0]=WB(); @@ -101,10 +100,10 @@ int main(void) check[3]=ID(); check[4]=IF(); -if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) +if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) break; - } - + }*/ + return 0; diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 9ac51e7..45893a7 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -1,11 +1,51 @@ #include "state.h" -#include "state_reg.h" + +typedef struct _IFID{ + int instruction; + int PC; +}IFID; + + + +typedef struct _IDEX{ + int instruction; + int PC; + int read_data1; + int read_data2; + int immediate_ext; + int write_reg; +}IDEX; + + + +typedef struct _EXDM{ + int instruction; + int PC; + int ALU_result; + int read_data2; + int write_reg; +}EXDM; + + + +typedef struct _DMWB{ + int instruction; + int address; + int data; + int write_reg; +}DMWB; + +IFID IF_ID; +IDEX ID_EX; +EXDM EX_DM; +DMWB DM_WB; + int WB(){ int flag=0; - + op=0,funct=0; if(DM_WB.instruction==0) return 0; - + op=(unsigned)DM_WB.instruction>>26; @@ -22,7 +62,7 @@ int WB(){ case 0x20: ///add { reg[DM_WB.write_reg] = DM_WB.address; - + break; } case 0x21: ///addu @@ -92,7 +132,7 @@ int WB(){ case 0x08: ///addi { reg[DM_WB.write_reg] = DM_WB.address; - + break; } case 0x09: ///addiu @@ -103,7 +143,7 @@ int WB(){ case 0x23: ///lw { reg[DM_WB.write_reg] = DM_WB.data; - + break; } case 0x21: ///lh @@ -128,17 +168,17 @@ int WB(){ } case 0x2B: ///sw { - + break; } case 0x29: ///sh { - + break; } case 0x28: ///sb { - + break; } case 0x0F: ///lui @@ -168,39 +208,39 @@ int WB(){ } case 0x04: ///beq { - + break; } case 0x05: ///bne { - + break; } case 0x07: ///bgtz { - + break; } case 0x02: ///j { - + break; } case 0x03: ///jal { - + break; } case 0x3F: ///halt { - + flag=1; break; } } - + if(flag==1) return 1; else return 0; } @@ -385,7 +425,7 @@ int DM(){ } case 0x29: ///sh { - + DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; getting = seperate_two(EX_DM.read_data2); @@ -398,6 +438,7 @@ int DM(){ { DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; + getting = malloc(sizeof(unsigned char)); getting[0] = (unsigned char)(EX_DM.read_data2&0x000000FF); dim[EX_DM.ALU_result]=getting[0]; DM_WB.data = 0; @@ -475,7 +516,7 @@ int DM(){ } case 0x3F: ///halt { - + flag=1; break; } @@ -484,4 +525,21 @@ int DM(){ } if(flag==1)return 1; else return 0; - } \ No newline at end of file + } + +int EX() +{ + + return 1; +} + +int ID() +{ + + return 1; +} + +int IF() +{ + return 1; +} diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index 51dc103..e789a7a 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -1,5 +1,21 @@ #include #include -void WB(); -void DM(); \ No newline at end of file + +int WB(); +int DM(); +int EX(); +int ID(); +int IF(); + + + + + +extern int reg[32]; +extern int PC; +extern int PC_start; +extern int iim[256]; +extern unsigned char dim[1024]; + +unsigned char op,funct; diff --git a/pipeline/simulator/state_reg.h b/pipeline/simulator/state_reg.h deleted file mode 100644 index 7450c4b..0000000 --- a/pipeline/simulator/state_reg.h +++ /dev/null @@ -1,31 +0,0 @@ -#include -#include - -typedef struct _IFID{ - int instruction; - int PC; -}IF_ID; - -typedef struct _IDEX{ - int instruction; - int PC; - int read_data1; - int read_data2; - int immediate_ext; - int write_reg; -}ID_EX; - -typedef struct _EXDM{ - int instruction; - int PC; - int ALU_result; - int read_data2; - int write_reg; -}EX_DM; - -typedef struct _DMWB{ - int instruction; - int address; - int data; - int write_reg; -}DM_WB; \ No newline at end of file From 5e5903757e87c859798b7d8f6ac592c5c09acb9d Mon Sep 17 00:00:00 2001 From: windstormer Date: Sat, 23 Apr 2016 20:31:48 +0800 Subject: [PATCH 06/32] finish IF --- pipeline/simulator/main.c | 9 ++++++++- pipeline/simulator/state.c | 37 +++++++++++++++++++++++++++++++++++-- pipeline/simulator/state.h | 3 +-- 3 files changed, 44 insertions(+), 5 deletions(-) diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index 8b422ca..88b97b8 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -15,6 +15,7 @@ int temp; + int main(void) { FILE *iimage = fopen("./iimage.bin","rb"); @@ -92,13 +93,19 @@ int main(void) sdata : int of the number of memory (word) **/ /* int check[5]={0}; +int flags=0; while(1) { check[0]=WB(); check[1]=DM(); check[2]=EX(); check[3]=ID(); - check[4]=IF(); + if(flags==0) + {check[4]=IF(0); + flags=1; + } + else + check[4]=IF(1); if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) break; diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 45893a7..85a8e3b 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -24,6 +24,7 @@ typedef struct _EXDM{ int ALU_result; int read_data2; int write_reg; + int branch; }EXDM; @@ -539,7 +540,39 @@ int ID() return 1; } -int IF() +int IF(int flags) { - return 1; + + int i=0; + int tempPC=0; + + if(flags==0) + { + tempPC = PC; + } + else + { + if(EX_DM.branch==1) + { + tempPC = EX_DM.PC; + }else + tempPC+=4; + + } + + + if(tempPC>=PC_start) + { + i=(tempPC-PC_start)/4; + IF_ID.instruction=iim[i]; + IF_ID.PC=PC; + }else + { + IF_ID.instruction=0; + } + op=(unsigned)iim[i]>>26; + if(op==0x3F) + return 1; + else + return 0; } diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index e789a7a..a3bde67 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -6,8 +6,7 @@ int WB(); int DM(); int EX(); int ID(); -int IF(); - +int IF(int); From f54b3b86ab1ffa0342d001c5d7c8bf10f09d7c67 Mon Sep 17 00:00:00 2001 From: windstormer Date: Sat, 23 Apr 2016 23:28:30 +0800 Subject: [PATCH 07/32] fixed branch in IF --- pipeline/simulator/state.c | 8 +++----- pipeline/simulator/state.h | 2 +- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 85a8e3b..522732e 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -9,7 +9,6 @@ typedef struct _IFID{ typedef struct _IDEX{ int instruction; - int PC; int read_data1; int read_data2; int immediate_ext; @@ -20,11 +19,9 @@ typedef struct _IDEX{ typedef struct _EXDM{ int instruction; - int PC; int ALU_result; int read_data2; int write_reg; - int branch; }EXDM; @@ -552,9 +549,10 @@ int IF(int flags) } else { - if(EX_DM.branch==1) + if(branch==1) { - tempPC = EX_DM.PC; + tempPC = PCback; + branch=0; }else tempPC+=4; diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index a3bde67..a7ef17f 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -9,7 +9,7 @@ int ID(); int IF(int); - +int PCback,branch; extern int reg[32]; extern int PC; From 13f023d3a63077ae54ab53faa7c1b3ebe9a25cbd Mon Sep 17 00:00:00 2001 From: windstormer Date: Sun, 24 Apr 2016 15:42:01 +0800 Subject: [PATCH 08/32] finish ID, rewrite branching --- pipeline/simulator/state.c | 1378 ++++++++++++++++++++++++------------ pipeline/simulator/state.h | 1 + 2 files changed, 929 insertions(+), 450 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 522732e..05bab64 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -1,37 +1,41 @@ #include "state.h" -typedef struct _IFID{ - int instruction; - int PC; -}IFID; +typedef struct _IFID +{ + int instruction; + int PC; +} IFID; -typedef struct _IDEX{ - int instruction; - int read_data1; - int read_data2; - int immediate_ext; - int write_reg; -}IDEX; +typedef struct _IDEX +{ + int instruction; + int read_data1; + int read_data2; + int immediate_ext; + int write_reg; +} IDEX; -typedef struct _EXDM{ - int instruction; - int ALU_result; - int read_data2; - int write_reg; -}EXDM; +typedef struct _EXDM +{ + int instruction; + int ALU_result; + int read_data2; + int write_reg; +} EXDM; -typedef struct _DMWB{ - int instruction; - int address; - int data; - int write_reg; -}DMWB; +typedef struct _DMWB +{ + int instruction; + int address; + int data; + int write_reg; +} DMWB; IFID IF_ID; IDEX ID_EX; @@ -39,501 +43,952 @@ EXDM EX_DM; DMWB DM_WB; -int WB(){ - int flag=0; +int WB() +{ + int flag=0; op=0,funct=0; - if(DM_WB.instruction==0) return 0; + if(DM_WB.instruction==0) return 0; - op=(unsigned)DM_WB.instruction>>26; + op=(unsigned)DM_WB.instruction>>26; - switch(op) - { - case 0x00: - { - funct=cut_func(DM_WB.instruction); - - switch(funct) - { - case 0x20: ///add - { - reg[DM_WB.write_reg] = DM_WB.address; - - break; - } - case 0x21: ///addu - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x22: ///sub - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x24: ///and - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x25: ///or - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x26: ///xor - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x27: ///nor - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x28: ///nand - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x2A: ///slt - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x00: ///sll - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x02: ///srl - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x03: ///sra - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x08: ///jr - { - - break; - } - - } - break; - } - case 0x08: ///addi - { - reg[DM_WB.write_reg] = DM_WB.address; + switch(op) + { + case 0x00: + { + funct=cut_func(DM_WB.instruction); - break; - } - case 0x09: ///addiu - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x23: ///lw - { - reg[DM_WB.write_reg] = DM_WB.data; + switch(funct) + { + case 0x20: ///add + { + reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x21: ///lh - { - reg[DM_WB.write_reg] = DM_WB.data; - break; - } - case 0x25: ///lhu - { - reg[DM_WB.write_reg] = DM_WB.data; - break; - } - case 0x20: ///lb - { - reg[DM_WB.write_reg] = DM_WB.data; - break; - } - case 0x24: ///lbu - { - reg[DM_WB.write_reg] = DM_WB.data; - break; - } - case 0x2B: ///sw - { + break; + } + case 0x21: ///addu + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x22: ///sub + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x24: ///and + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x25: ///or + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x26: ///xor + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x27: ///nor + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x28: ///nand + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x2A: ///slt + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x00: ///sll + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x02: ///srl + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x03: ///sra + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x08: ///jr + { - break; - } - case 0x29: ///sh - { + break; + } - break; - } - case 0x28: ///sb - { + } + break; + } + case 0x08: ///addi + { + reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x0F: ///lui - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x0C: ///andi - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x0D: ///ori - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x0E: ///nori - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x0A: ///slti - { - reg[DM_WB.write_reg] = DM_WB.address; - break; - } - case 0x04: ///beq - { + break; + } + case 0x09: ///addiu + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x23: ///lw + { + reg[DM_WB.write_reg] = DM_WB.data; - break; - } - case 0x05: ///bne - { + break; + } + case 0x21: ///lh + { + reg[DM_WB.write_reg] = DM_WB.data; + break; + } + case 0x25: ///lhu + { + reg[DM_WB.write_reg] = DM_WB.data; + break; + } + case 0x20: ///lb + { + reg[DM_WB.write_reg] = DM_WB.data; + break; + } + case 0x24: ///lbu + { + reg[DM_WB.write_reg] = DM_WB.data; + break; + } + case 0x2B: ///sw + { - break; - } - case 0x07: ///bgtz - { + break; + } + case 0x29: ///sh + { - break; - } - case 0x02: ///j - { + break; + } + case 0x28: ///sb + { - break; - } - case 0x03: ///jal - { + break; + } + case 0x0F: ///lui + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x0C: ///andi + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x0D: ///ori + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x0E: ///nori + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x0A: ///slti + { + reg[DM_WB.write_reg] = DM_WB.address; + break; + } + case 0x04: ///beq + { - break; - } - case 0x3F: ///halt - { + break; + } + case 0x05: ///bne + { - flag=1; - break; - } + break; + } + case 0x07: ///bgtz + { + break; + } + case 0x02: ///j + { - } + break; + } + case 0x03: ///jal + { - if(flag==1) return 1; - else return 0; + break; + } + case 0x3F: ///halt + { + + flag=1; + break; + } + + + } + + if(flag==1) return 1; + else return 0; } -int DM(){ - unsigned char *getting; - int flag=0; - if(EX_DM.instruction==0) - { - DM_WB.instruction=0; - return 0; - } +int DM() +{ + unsigned char *getting; + int flag=0; + if(EX_DM.instruction==0) + { + DM_WB.instruction=0; + return 0; + } - op=(unsigned)EX_DM.instruction>>26; + op=(unsigned)EX_DM.instruction>>26; - switch(op) - { - case 0x00: - { - funct=cut_func(DM_WB.instruction); - - switch(funct) - { - case 0x20: ///add - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x21: ///addu - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x22: ///sub - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x24: ///and - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x25: ///or - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x26: ///xor - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x27: ///nor - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x28: ///nand - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x2A: ///slt - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x00: ///sll - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x02: ///srl - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x03: ///sra - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x08: ///jr - { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - - } - break; - } - case 0x08: ///addi - { + switch(op) + { + case 0x00: + { + funct=cut_func(EX_DM.instruction); - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x09: ///addiu - { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; - } - case 0x23: ///lw - { + switch(funct) + { + case 0x20: ///add + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x21: ///addu + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x22: ///sub + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x24: ///and + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x25: ///or + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x26: ///xor + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x27: ///nor + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x28: ///nand + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x2A: ///slt + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x00: ///sll + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x02: ///srl + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x03: ///sra + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x08: ///jr + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (int)combine(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1],dim[EX_DM.ALU_result+2],dim[EX_DM.ALU_result+3]); - break; - } - case 0x21: ///lh - { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); - break; - } - case 0x25: ///lhu + } + break; + } + case 0x08: ///addi + { + + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x09: ///addiu + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x23: ///lw + { + + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (int)combine(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1],dim[EX_DM.ALU_result+2],dim[EX_DM.ALU_result+3]); + break; + } + case 0x21: ///lh + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); + break; + } + case 0x25: ///lhu + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); + break; + } + case 0x20: ///lb + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (char)dim[EX_DM.ALU_result]; + break; + } + case 0x24: ///lbu + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = (unsigned)dim[EX_DM.ALU_result]; + break; + } + case 0x2B: ///sw + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + getting = seperate(EX_DM.read_data2); + dim[EX_DM.ALU_result]=getting[0]; + dim[EX_DM.ALU_result+1]=getting[1]; + dim[EX_DM.ALU_result+2]=getting[2]; + dim[EX_DM.ALU_result+3]=getting[3]; + DM_WB.data = 0; + break; + } + case 0x29: ///sh + { + + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + getting = seperate_two(EX_DM.read_data2); + dim[EX_DM.ALU_result]=getting[0]; + dim[EX_DM.ALU_result+1]=getting[1]; + DM_WB.data = 0; + break; + } + case 0x28: ///sb + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + getting = malloc(sizeof(unsigned char)); + getting[0] = (unsigned char)(EX_DM.read_data2&0x000000FF); + dim[EX_DM.ALU_result]=getting[0]; + DM_WB.data = 0; + break; + } + case 0x0F: ///lui + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0C: ///andi + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0D: ///ori + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0E: ///nori + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x0A: ///slti + { + DM_WB.address = EX_DM.ALU_result; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x04: ///beq + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x05: ///bne + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x07: ///bgtz + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x02: ///j + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x03: ///jal + { + DM_WB.address = 0; + DM_WB.write_reg = EX_DM.write_reg; + DM_WB.data = 0; + break; + } + case 0x3F: ///halt + { + + flag=1; + break; + } + + + } + if(flag==1)return 1; + else return 0; +} + +int EX() +{ + + return 1; +} + +int ID() +{ + + int flag=0; + op=(unsigned)IF_ID.instruction>>26; + + unsigned char rs=0; + unsigned char rt=0; + unsigned char rd=0; + unsigned char shamt=0; + short immediate=0; + unsigned short unsigned_immediate=0; + unsigned int address=0; + + if(IF_ID.instruction==0) + { + ID_EX.instruction = 0; + return 0; + } + + + + + switch(op) + { + case 0x00: + { + funct=cut_func(IF_ID.instruction); + + switch(funct) { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); - break; - } - case 0x20: ///lb + case 0x20: ///add { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (char)dim[EX_DM.ALU_result]; + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = rd; + break; } - case 0x24: ///lbu + case 0x21: ///addu { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (unsigned)dim[EX_DM.ALU_result]; + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = rd; break; } - case 0x2B: ///sw + case 0x22: ///sub { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - getting = seperate(EX_DM.read_data2); - dim[EX_DM.ALU_result]=getting[0]; - dim[EX_DM.ALU_result+1]=getting[1]; - dim[EX_DM.ALU_result+2]=getting[2]; - dim[EX_DM.ALU_result+3]=getting[3]; - DM_WB.data = 0; + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = rd; break; } - case 0x29: ///sh + case 0x24: ///and { - - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - getting = seperate_two(EX_DM.read_data2); - dim[EX_DM.ALU_result]=getting[0]; - dim[EX_DM.ALU_result+1]=getting[1]; - DM_WB.data = 0; + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = rd; break; } - case 0x28: ///sb + case 0x25: ///or { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - getting = malloc(sizeof(unsigned char)); - getting[0] = (unsigned char)(EX_DM.read_data2&0x000000FF); - dim[EX_DM.ALU_result]=getting[0]; - DM_WB.data = 0; + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = rd; break; } - case 0x0F: ///lui + case 0x26: ///xor { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = rd; break; } - case 0x0C: ///andi + case 0x27: ///nor { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = rd; break; } - case 0x0D: ///ori + case 0x28: ///nand { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = rd; break; } - case 0x0E: ///nori + case 0x2A: ///slt { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = rd; break; } - case 0x0A: ///slti + case 0x00: ///sll { - DM_WB.address = EX_DM.ALU_result; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + shamt = cut_shamt(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = shamt; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rt]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rd; break; } - case 0x04: ///beq + case 0x02: ///srl { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + shamt = cut_shamt(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = shamt; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rt]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rd; break; } - case 0x05: ///bne + case 0x03: ///sra { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + shamt = cut_shamt(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = shamt; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rt]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rd; break; } - case 0x07: ///bgtz + case 0x08: ///jr { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; + rs = cut_rs(IF_ID.instruction); + branch = 1; + PCback = reg[rs]; break; } - case 0x02: ///j - { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; + } - case 0x03: ///jal + break; + } + case 0x08: ///addi + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x09: ///addiu + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x23: ///lw + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x21: ///lh + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x25: ///lhu + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x20: ///lb + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x24: ///lbu + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x2B: ///sw + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = 0; + break; + } + case 0x29: ///sh + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = 0; + break; + } + case 0x28: ///sb + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = reg[rt]; + ID_EX.write_reg = 0; + break; + } + case 0x0F: ///lui + { + immediate = cut_immediate(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = 0;; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x0C: ///andi + { + unsigned_immediate = cut_immediate_unsigned(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = unsigned_immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x0D: ///ori + { + unsigned_immediate = cut_immediate_unsigned(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = unsigned_immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x0E: ///nori + { + unsigned_immediate = cut_immediate_unsigned(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = unsigned_immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x0A: ///slti + { + unsigned_immediate = cut_immediate_unsigned(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + ID_EX.immediate_ext = unsigned_immediate; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = reg[rs]; + ID_EX.read_data2 = 0; + ID_EX.write_reg = rt; + break; + } + case 0x04: ///beq + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + if(reg[rs]==reg[rt]) { - DM_WB.address = 0; - DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = 0; - break; + branch = 1; + PCback = IF_ID.PC + immediate*4; } - case 0x3F: ///halt - { - flag=1; - break; - } + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = 0; + ID_EX.read_data2 = 0; + ID_EX.write_reg = 0; + break; + } + case 0x05: ///bne + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + if(reg[rs]!=reg[rt]) + { + branch = 1; + PCback = IF_ID.PC + immediate*4; } - if(flag==1)return 1; - else return 0; - } -int EX() -{ + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = 0; + ID_EX.read_data2 = 0; + ID_EX.write_reg = 0; + break; + } + case 0x07: ///bgtz + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + if(reg[rs]>0) + { + branch = 1; + PCback = IF_ID.PC + immediate*4; + } - return 1; -} + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = 0; + ID_EX.read_data2 = 0; + ID_EX.write_reg = 0; + break; + } + case 0x02: ///j + { + address = cut_address(IF_ID.instruction); + address=address<<2; + PCback = (unsigned) IF_ID.PC>>28; + PCback = PCback<<28; + PCback = (unsigned)PC|address; + break; + } + case 0x03: ///jal + { + address = cut_address(IF_ID.instruction); + address=address<<2; + reg[31] = IF_ID.PC; + PCback = (unsigned) IF_ID.PC>>28; + PCback = PCback<<28; + PCback = (unsigned)PC|address; + break; + } + case 0x3F: ///halt + { + // printf("halt\n"); + flag=1; + break; + } -int ID() -{ + } + + if(flag==1) return 1; + else return 0; return 1; } @@ -545,26 +1000,49 @@ int IF(int flags) if(flags==0) { - tempPC = PC; + tempPC = PC; + change = 0; } else { - if(branch==1) + if(change==1) { - tempPC = PCback; - branch=0; - }else - tempPC+=4; + tempPC = changePC; + change = 0; + } + else + { + if(branch==1) + { + tempPC +=4; + branch=0; + change=1; + changePC = PCback; + } + else + tempPC+=4; + + } } if(tempPC>=PC_start) { - i=(tempPC-PC_start)/4; - IF_ID.instruction=iim[i]; - IF_ID.PC=PC; - }else + if(branch == 1) + { + i=(tempPC-PC_start)/4; + IF_ID.instruction = 0; ///flush + } + else + { + i=(tempPC-PC_start)/4; + IF_ID.instruction=iim[i]; + IF_ID.PC=tempPC; + } + + } + else { IF_ID.instruction=0; } diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index a7ef17f..955f76a 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -10,6 +10,7 @@ int IF(int); int PCback,branch; +int change; extern int reg[32]; extern int PC; From ed785e30ac5c719b8e21e929b15362e21a81aae2 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 26 Apr 2016 00:56:09 +0800 Subject: [PATCH 09/32] finish 5 states, unchecked --- pipeline/simulator/state.c | 321 ++++++++++++++++++++++++++++++++++++- 1 file changed, 318 insertions(+), 3 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 05bab64..36d798f 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -533,8 +533,320 @@ int DM() int EX() { +int temp=0; +int flag=0; +if(ID_EX.instruction==0) +{ + EX_DM.instruction=0; + return 0; +} + +op=(unsigned)ID_EX.instruction>>26; + + + + + switch(op) + { + case 0x00: + { + funct=cut_func(ID_EX.instruction); + + switch(funct) + { + case 0x20: ///add + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.read_data2; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x21: ///addu + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.read_data2; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x22: ///sub + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+(-1)*ID_EX.read_data2; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x24: ///and + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1&ID_EX.read_data2; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x25: ///or + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1|ID_EX.read_data2; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x26: ///xor + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1^ID_EX.read_data2; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x27: ///nor + { + EX_DM.instruction=ID_EX.instruction; + temp=~(ID_EX.read_data1|ID_EX.read_data2); + + EX_DM.ALU_result=temp; + break; + } + case 0x28: ///nand + { + EX_DM.instruction=ID_EX.instruction; + temp=~(ID_EX.read_data1&ID_EX.read_data2); + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x2A: ///slt + { + EX_DM.instruction=ID_EX.instruction; + if(ID_EX.read_data1>ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x03: ///sra + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1>>ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x08: ///jr + { + EX_DM.instruction=ID_EX.instruction; + break; + } + + } + break; + } + case 0x08: ///addi + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x09: ///addiu + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x23: ///lw + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x21: ///lh + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x25: ///lhu + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x20: ///lb + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x24: ///lbu + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x2B: ///sw + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.read_data2=ID_EX.read_data2; + break; + } + case 0x29: ///sh + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.read_data2=ID_EX.read_data2; + break; + } + case 0x28: ///sb + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.read_data2=ID_EX.read_data2; + break; + } + case 0x0F: ///lui + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.immediate_ext<<16; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x0C: ///andi + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1&ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x0D: ///ori + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1|ID_EX.immediate_ext; + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x0E: ///nori + { + EX_DM.instruction=ID_EX.instruction; + temp=~(ID_EX.read_data1|ID_EX.immediate_ext); + + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x0A: ///slti + { + EX_DM.instruction=ID_EX.instruction; + if(ID_EX.read_data1>28; @@ -969,6 +1283,7 @@ int ID() } case 0x03: ///jal { + ID_EX.instruction = IF_ID.instruction; address = cut_address(IF_ID.instruction); address=address<<2; reg[31] = IF_ID.PC; @@ -989,7 +1304,7 @@ int ID() if(flag==1) return 1; else return 0; - return 1; + } int IF(int flags) From f66494e0519ebb68a9aa872ec679c023eff6f462 Mon Sep 17 00:00:00 2001 From: windstormer Date: Wed, 27 Apr 2016 01:21:02 +0800 Subject: [PATCH 10/32] halt well --- pipeline/simulator/main.c | 8 +++++-- pipeline/simulator/state.c | 49 ++++++++++++++++++++++++++++++++++---- pipeline/simulator/state.h | 1 + 3 files changed, 52 insertions(+), 6 deletions(-) diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index 88b97b8..469321f 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -92,10 +92,12 @@ int main(void) sins: int of the number of instruction sdata : int of the number of memory (word) **/ -/* int check[5]={0}; + int check[5]={0}; int flags=0; +int count=0; while(1) { + printf("cycle %d\n",count); check[0]=WB(); check[1]=DM(); check[2]=EX(); @@ -109,7 +111,9 @@ int flags=0; if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) break; - }*/ + +count++; + } diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 36d798f..d97920a 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -45,6 +45,7 @@ DMWB DM_WB; int WB() { + printf("WB: %X\n",DM_WB.instruction); int flag=0; op=0,funct=0; if(DM_WB.instruction==0) return 0; @@ -250,6 +251,7 @@ int WB() int DM() { + printf("DM: %X\n",EX_DM.instruction); unsigned char *getting; int flag=0; if(EX_DM.instruction==0) @@ -271,6 +273,7 @@ int DM() { case 0x20: ///add { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -278,6 +281,7 @@ int DM() } case 0x21: ///addu { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -285,6 +289,7 @@ int DM() } case 0x22: ///sub { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -292,6 +297,7 @@ int DM() } case 0x24: ///and { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -299,6 +305,7 @@ int DM() } case 0x25: ///or { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -306,6 +313,7 @@ int DM() } case 0x26: ///xor { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -313,6 +321,7 @@ int DM() } case 0x27: ///nor { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -320,6 +329,7 @@ int DM() } case 0x28: ///nand { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -327,6 +337,7 @@ int DM() } case 0x2A: ///slt { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -334,6 +345,7 @@ int DM() } case 0x00: ///sll { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -341,6 +353,7 @@ int DM() } case 0x02: ///srl { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -348,6 +361,7 @@ int DM() } case 0x03: ///sra { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -355,6 +369,7 @@ int DM() } case 0x08: ///jr { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -366,7 +381,7 @@ int DM() } case 0x08: ///addi { - + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -374,6 +389,7 @@ int DM() } case 0x09: ///addiu { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -381,7 +397,7 @@ int DM() } case 0x23: ///lw { - + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (int)combine(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1],dim[EX_DM.ALU_result+2],dim[EX_DM.ALU_result+3]); @@ -389,6 +405,7 @@ int DM() } case 0x21: ///lh { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); @@ -396,6 +413,7 @@ int DM() } case 0x25: ///lhu { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); @@ -403,6 +421,7 @@ int DM() } case 0x20: ///lb { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (char)dim[EX_DM.ALU_result]; @@ -410,6 +429,7 @@ int DM() } case 0x24: ///lbu { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (unsigned)dim[EX_DM.ALU_result]; @@ -417,6 +437,7 @@ int DM() } case 0x2B: ///sw { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; getting = seperate(EX_DM.read_data2); @@ -429,7 +450,7 @@ int DM() } case 0x29: ///sh { - + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; getting = seperate_two(EX_DM.read_data2); @@ -440,6 +461,7 @@ int DM() } case 0x28: ///sb { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; getting = malloc(sizeof(unsigned char)); @@ -450,6 +472,7 @@ int DM() } case 0x0F: ///lui { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -457,6 +480,7 @@ int DM() } case 0x0C: ///andi { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -464,6 +488,7 @@ int DM() } case 0x0D: ///ori { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -471,6 +496,7 @@ int DM() } case 0x0E: ///nori { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -478,6 +504,7 @@ int DM() } case 0x0A: ///slti { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -485,6 +512,7 @@ int DM() } case 0x04: ///beq { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -492,6 +520,7 @@ int DM() } case 0x05: ///bne { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -499,6 +528,7 @@ int DM() } case 0x07: ///bgtz { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -506,6 +536,7 @@ int DM() } case 0x02: ///j { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -513,6 +544,7 @@ int DM() } case 0x03: ///jal { + DM_WB.instruction = EX_DM.instruction; DM_WB.address = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; @@ -520,7 +552,7 @@ int DM() } case 0x3F: ///halt { - + DM_WB.instruction = EX_DM.instruction; flag=1; break; } @@ -533,6 +565,8 @@ int DM() int EX() { + + printf("EX: %X\n",ID_EX.instruction); int temp=0; int flag=0; if(ID_EX.instruction==0) @@ -836,6 +870,7 @@ op=(unsigned)ID_EX.instruction>>26; } case 0x3F: ///halt { + EX_DM.instruction=ID_EX.instruction; // printf("halt\n"); flag=1; break; @@ -852,6 +887,7 @@ op=(unsigned)ID_EX.instruction>>26; int ID() { +printf("ID: %X\n",IF_ID.instruction); int flag=0; op=(unsigned)IF_ID.instruction>>26; @@ -1295,6 +1331,7 @@ int ID() case 0x3F: ///halt { // printf("halt\n"); + ID_EX.instruction = IF_ID.instruction; flag=1; break; } @@ -1361,9 +1398,13 @@ int IF(int flags) { IF_ID.instruction=0; } + + printf("IF: %X\n",IF_ID.instruction); op=(unsigned)iim[i]>>26; if(op==0x3F) + { return 1; + } else return 0; } diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index 955f76a..eb5967f 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -10,6 +10,7 @@ int IF(int); int PCback,branch; +int changePC; int change; extern int reg[32]; From c20ec70b17dd019d3ea22b9f2282a109e1bf477c Mon Sep 17 00:00:00 2001 From: windstormer Date: Fri, 29 Apr 2016 00:38:36 +0800 Subject: [PATCH 11/32] well branch --- pipeline/simulator/main.c | 3 +++ pipeline/simulator/state.c | 19 +++++++++++++------ pipeline/simulator/state.h | 1 + 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index 469321f..5a7628d 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -97,7 +97,9 @@ int flags=0; int count=0; while(1) { + // if(count>4)break; printf("cycle %d\n",count); + check[0]=WB(); check[1]=DM(); check[2]=EX(); @@ -113,6 +115,7 @@ if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) break; count++; +printf("\n"); } diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index d97920a..e644441 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -1260,7 +1260,7 @@ printf("ID: %X\n",IF_ID.instruction); if(reg[rs]==reg[rt]) { branch = 1; - PCback = IF_ID.PC + immediate*4; + PCback = IF_ID.PC + 4 + immediate*4; } ID_EX.immediate_ext = 0; @@ -1280,7 +1280,7 @@ printf("ID: %X\n",IF_ID.instruction); if(reg[rs]!=reg[rt]) { branch = 1; - PCback = IF_ID.PC + immediate*4; + PCback = IF_ID.PC + 4 + immediate*4; } ID_EX.immediate_ext = 0; @@ -1294,10 +1294,11 @@ printf("ID: %X\n",IF_ID.instruction); { immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); + if(reg[rs]>0) { branch = 1; - PCback = IF_ID.PC + immediate*4; + PCback = IF_ID.PC + 4 + immediate*4; } ID_EX.immediate_ext = 0; @@ -1348,12 +1349,13 @@ int IF(int flags) { int i=0; - int tempPC=0; + if(flags==0) { tempPC = PC; change = 0; + branch = 0; } else { @@ -1372,12 +1374,16 @@ int IF(int flags) changePC = PCback; } else - tempPC+=4; + { + tempPC+=4; + + } + } } - + // printf("flags = %d, bramch = %d, change = %d\n",flags,branch,change); if(tempPC>=PC_start) { @@ -1399,6 +1405,7 @@ int IF(int flags) IF_ID.instruction=0; } + printf("PC: %d\n",tempPC); printf("IF: %X\n",IF_ID.instruction); op=(unsigned)iim[i]>>26; if(op==0x3F) diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index eb5967f..fa43143 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -10,6 +10,7 @@ int IF(int); int PCback,branch; +int tempPC; int changePC; int change; From 49e447a472608d1839148c15795deff2079efb57 Mon Sep 17 00:00:00 2001 From: windstormer Date: Fri, 29 Apr 2016 00:57:49 +0800 Subject: [PATCH 12/32] finish flush and print stage inst. in order --- pipeline/simulator/state.c | 30 +++++++++++++++++++++--------- pipeline/simulator/state.h | 5 +++++ 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index e644441..f7622eb 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -45,7 +45,7 @@ DMWB DM_WB; int WB() { - printf("WB: %X\n",DM_WB.instruction); + show_WBi = DM_WB.instruction; int flag=0; op=0,funct=0; if(DM_WB.instruction==0) return 0; @@ -251,7 +251,8 @@ int WB() int DM() { - printf("DM: %X\n",EX_DM.instruction); + + show_DMi = EX_DM.instruction; unsigned char *getting; int flag=0; if(EX_DM.instruction==0) @@ -566,7 +567,7 @@ int DM() int EX() { - printf("EX: %X\n",ID_EX.instruction); + show_EXi = ID_EX.instruction; int temp=0; int flag=0; if(ID_EX.instruction==0) @@ -887,7 +888,8 @@ op=(unsigned)ID_EX.instruction>>26; int ID() { -printf("ID: %X\n",IF_ID.instruction); + + show_IDi = IF_ID.instruction; int flag=0; op=(unsigned)IF_ID.instruction>>26; @@ -1261,6 +1263,7 @@ printf("ID: %X\n",IF_ID.instruction); { branch = 1; PCback = IF_ID.PC + 4 + immediate*4; + } ID_EX.immediate_ext = 0; @@ -1281,6 +1284,7 @@ printf("ID: %X\n",IF_ID.instruction); { branch = 1; PCback = IF_ID.PC + 4 + immediate*4; + } ID_EX.immediate_ext = 0; @@ -1299,6 +1303,7 @@ printf("ID: %X\n",IF_ID.instruction); { branch = 1; PCback = IF_ID.PC + 4 + immediate*4; + } ID_EX.immediate_ext = 0; @@ -1383,14 +1388,14 @@ int IF(int flags) } } - // printf("flags = %d, bramch = %d, change = %d\n",flags,branch,change); + //printf("\nflags = %d, bramch = %d, change = %d\n\n",flags,branch,change); if(tempPC>=PC_start) { - if(branch == 1) + if(change == 1) { i=(tempPC-PC_start)/4; - IF_ID.instruction = 0; ///flush + IF_ID.instruction = iim[i]; } else { @@ -1405,8 +1410,15 @@ int IF(int flags) IF_ID.instruction=0; } - printf("PC: %d\n",tempPC); - printf("IF: %X\n",IF_ID.instruction); + printf("PC: %08X\n",tempPC); + printf("IF: %08X\n",IF_ID.instruction); + printf("ID: %08X\n",show_IDi); + printf("EX: %08X\n",show_EXi); + printf("DM: %08X\n",show_DMi); + printf("WB: %08X\n",show_WBi); + + if(change == 1 ) + IF_ID.instruction = 0; ///flush op=(unsigned)iim[i]>>26; if(op==0x3F) { diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index fa43143..5da0dde 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -20,4 +20,9 @@ extern int PC_start; extern int iim[256]; extern unsigned char dim[1024]; +int show_IDi; +int show_EXi; +int show_DMi; +int show_WBi; + unsigned char op,funct; From 19f3015d7b91f97ffe602030a8ab7b6a33a08f58 Mon Sep 17 00:00:00 2001 From: windstormer Date: Fri, 29 Apr 2016 01:21:51 +0800 Subject: [PATCH 13/32] finish to_be_flushed --- pipeline/simulator/state.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index f7622eb..8dba66c 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -1411,7 +1411,10 @@ int IF(int flags) } printf("PC: %08X\n",tempPC); + if(change == 0) printf("IF: %08X\n",IF_ID.instruction); + else + printf("IF: %08X to_be_flushed\n",IF_ID.instruction); printf("ID: %08X\n",show_IDi); printf("EX: %08X\n",show_EXi); printf("DM: %08X\n",show_DMi); From bc6a536103b1e91515b7fbab4c71f5a2f1e425e0 Mon Sep 17 00:00:00 2001 From: windstormer Date: Fri, 29 Apr 2016 03:13:35 +0800 Subject: [PATCH 14/32] finish forwarding, not checked, write to snapshot --- pipeline/simulator/main.c | 18 +- pipeline/simulator/state.c | 1612 ++++++++++++++++++++++-------------- pipeline/simulator/state.h | 3 + 3 files changed, 1002 insertions(+), 631 deletions(-) diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index 5a7628d..27aaf45 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -12,16 +12,16 @@ unsigned char di[1024]; int iim[256]; unsigned char dim[1024]; int temp; - - +FILE *snapshot; +FILE *error; int main(void) { FILE *iimage = fopen("./iimage.bin","rb"); FILE *dimage = fopen("./dimage.bin","rb"); - FILE *error = fopen("./error_dump.rpt","w"); - FILE *snapshot = fopen("./snapshot.rpt","w"); + error = fopen("./error_dump.rpt","w"); + snapshot = fopen("./snapshot.rpt","w"); @@ -95,11 +95,15 @@ int main(void) int check[5]={0}; int flags=0; int count=0; +int j=0; while(1) { // if(count>4)break; - printf("cycle %d\n",count); - + fprintf(snapshot,"cycle %d\n",count); + for(j=0; j<32; j++) + { + fprintf(snapshot,"$%02d: 0x%08X\n",j,reg[j]); + } check[0]=WB(); check[1]=DM(); check[2]=EX(); @@ -115,7 +119,7 @@ if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) break; count++; -printf("\n"); +fprintf(snapshot,"\n"); } diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 8dba66c..309200d 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -25,6 +25,7 @@ typedef struct _EXDM int ALU_result; int read_data2; int write_reg; + int can_forward; } EXDM; @@ -567,321 +568,328 @@ int DM() int EX() { - show_EXi = ID_EX.instruction; -int temp=0; -int flag=0; -if(ID_EX.instruction==0) -{ - EX_DM.instruction=0; - return 0; -} - -op=(unsigned)ID_EX.instruction>>26; - - - - - switch(op) - { - case 0x00: - { - funct=cut_func(ID_EX.instruction); - - switch(funct) - { - case 0x20: ///add - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.read_data2; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x21: ///addu - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.read_data2; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x22: ///sub - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+(-1)*ID_EX.read_data2; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x24: ///and - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1&ID_EX.read_data2; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x25: ///or - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1|ID_EX.read_data2; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x26: ///xor - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1^ID_EX.read_data2; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x27: ///nor - { - EX_DM.instruction=ID_EX.instruction; - temp=~(ID_EX.read_data1|ID_EX.read_data2); - - EX_DM.ALU_result=temp; - break; - } - case 0x28: ///nand - { - EX_DM.instruction=ID_EX.instruction; - temp=~(ID_EX.read_data1&ID_EX.read_data2); - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x2A: ///slt - { - EX_DM.instruction=ID_EX.instruction; - if(ID_EX.read_data1>ID_EX.immediate_ext; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x03: ///sra - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1>>ID_EX.immediate_ext; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x08: ///jr - { - EX_DM.instruction=ID_EX.instruction; - break; - } - - } - break; - } - case 0x08: ///addi - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x09: ///addiu - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x23: ///lw - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x21: ///lh - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x25: ///lhu - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x20: ///lb - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x24: ///lbu - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; - - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x2B: ///sw - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; + show_EXi = ID_EX.instruction; + int temp=0; + int flag=0; + if(ID_EX.instruction==0) + { + EX_DM.instruction=0; + return 0; + } - EX_DM.ALU_result=temp; - EX_DM.read_data2=ID_EX.read_data2; - break; - } - case 0x29: ///sh - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; + op=(unsigned)ID_EX.instruction>>26; - EX_DM.ALU_result=temp; - EX_DM.read_data2=ID_EX.read_data2; - break; - } - case 0x28: ///sb - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1+ID_EX.immediate_ext; - EX_DM.ALU_result=temp; - EX_DM.read_data2=ID_EX.read_data2; - break; - } - case 0x0F: ///lui - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.immediate_ext<<16; - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x0C: ///andi - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1&ID_EX.immediate_ext; - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x0D: ///ori - { - EX_DM.instruction=ID_EX.instruction; - temp=ID_EX.read_data1|ID_EX.immediate_ext; + switch(op) + { + case 0x00: + { + funct=cut_func(ID_EX.instruction); - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x0E: ///nori - { - EX_DM.instruction=ID_EX.instruction; - temp=~(ID_EX.read_data1|ID_EX.immediate_ext); + switch(funct) + { + case 0x20: ///add + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.read_data2; + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x21: ///addu + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+ID_EX.read_data2; + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x22: ///sub + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1+(-1)*ID_EX.read_data2; + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x24: ///and + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1&ID_EX.read_data2; + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x25: ///or + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1|ID_EX.read_data2; + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x26: ///xor + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1^ID_EX.read_data2; + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x27: ///nor + { + EX_DM.instruction=ID_EX.instruction; + temp=~(ID_EX.read_data1|ID_EX.read_data2); + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + break; + } + case 0x28: ///nand + { + EX_DM.instruction=ID_EX.instruction; + temp=~(ID_EX.read_data1&ID_EX.read_data2); + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x2A: ///slt + { + EX_DM.instruction=ID_EX.instruction; + if(ID_EX.read_data1>ID_EX.immediate_ext; + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x03: ///sra + { + EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.read_data1>>ID_EX.immediate_ext; + EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg=ID_EX.write_reg; + break; + } + case 0x08: ///jr + { + EX_DM.instruction=ID_EX.instruction; + EX_DM.can_forward=0; + break; + } - EX_DM.ALU_result=temp; - EX_DM.write_reg=ID_EX.write_reg; - break; - } - case 0x0A: ///slti - { - EX_DM.instruction=ID_EX.instruction; - if(ID_EX.read_data10) + } + forward[0] = 1; + forward[1] = rt; + } + else { - branch = 1; - PCback = IF_ID.PC + 4 + immediate*4; + if(reg[rs]!=reg[rt]) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + + } + forward[0] = 0; + forward[1] = 0; } - ID_EX.immediate_ext = 0; - ID_EX.instruction = IF_ID.instruction; - ID_EX.read_data1 = 0; - ID_EX.read_data2 = 0; - ID_EX.write_reg = 0; - break; - } - case 0x02: ///j - { - ID_EX.instruction = IF_ID.instruction; - address = cut_address(IF_ID.instruction); - address=address<<2; - PCback = (unsigned) IF_ID.PC>>28; - PCback = PCback<<28; - PCback = (unsigned)PC|address; - break; } - case 0x03: ///jal + + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = 0; + ID_EX.read_data2 = 0; + ID_EX.write_reg = 0; + break; + } + case 0x07: ///bgtz + { + immediate = cut_immediate(IF_ID.instruction); + rs = cut_rs(IF_ID.instruction); + if(rs == EX_DM.write_reg && EX_DM.can_forward==1) { - ID_EX.instruction = IF_ID.instruction; - address = cut_address(IF_ID.instruction); - address=address<<2; - reg[31] = IF_ID.PC; - PCback = (unsigned) IF_ID.PC>>28; - PCback = PCback<<28; - PCback = (unsigned)PC|address; - break; + if(EX_DM.ALU_result>0) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + } + forward[0] = 1; + forward[1] = rs; } - case 0x3F: ///halt + else { - // printf("halt\n"); - ID_EX.instruction = IF_ID.instruction; - flag=1; - break; - } + if(reg[rs]>0) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + } } + + ID_EX.immediate_ext = 0; + ID_EX.instruction = IF_ID.instruction; + ID_EX.read_data1 = 0; + ID_EX.read_data2 = 0; + ID_EX.write_reg = 0; + break; + } + case 0x02: ///j + { + ID_EX.instruction = IF_ID.instruction; + address = cut_address(IF_ID.instruction); + address=address<<2; + PCback = (unsigned) IF_ID.PC>>28; + PCback = PCback<<28; + PCback = (unsigned)PC|address; + break; + } + case 0x03: ///jal + { + ID_EX.instruction = IF_ID.instruction; + address = cut_address(IF_ID.instruction); + address=address<<2; + reg[31] = IF_ID.PC; + PCback = (unsigned) IF_ID.PC>>28; + PCback = PCback<<28; + PCback = (unsigned)PC|address; + break; + } + case 0x3F: ///halt + { + // printf("halt\n"); + ID_EX.instruction = IF_ID.instruction; + flag=1; + break; + } + + + } + if(flag==1) return 1; else return 0; @@ -1353,7 +1715,9 @@ int ID() int IF(int flags) { + int i=0; + int j=0; if(flags==0) @@ -1380,7 +1744,7 @@ int IF(int flags) } else { - tempPC+=4; + tempPC+=4; } @@ -1410,15 +1774,15 @@ int IF(int flags) IF_ID.instruction=0; } - printf("PC: %08X\n",tempPC); + fprintf(snapshot,"PC: %08X\n",tempPC); if(change == 0) - printf("IF: %08X\n",IF_ID.instruction); + fprintf(snapshot,"IF: %08X\n",IF_ID.instruction); else - printf("IF: %08X to_be_flushed\n",IF_ID.instruction); - printf("ID: %08X\n",show_IDi); - printf("EX: %08X\n",show_EXi); - printf("DM: %08X\n",show_DMi); - printf("WB: %08X\n",show_WBi); + fprintf(snapshot,"IF: %08X to_be_flushed\n",IF_ID.instruction); + fprintf(snapshot,"ID: %08X\n",show_IDi); + fprintf(snapshot,"EX: %08X\n",show_EXi); + fprintf(snapshot,"DM: %08X\n",show_DMi); + fprintf(snapshot,"WB: %08X\n",show_WBi); if(change == 1 ) IF_ID.instruction = 0; ///flush diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index 5da0dde..2120b4c 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -8,7 +8,10 @@ int EX(); int ID(); int IF(int); +extern FILE *snapshot; +extern FILE *error; +int forward[2]; int PCback,branch; int tempPC; int changePC; From 61716b533ca6aa17d2731a49f735f24f8875f922 Mon Sep 17 00:00:00 2001 From: windstormer Date: Sun, 1 May 2016 23:33:24 +0800 Subject: [PATCH 15/32] fowarding OK, print fwd OK --- pipeline/simulator/function.c | 213 ++++++++++++++ pipeline/simulator/state.c | 514 ++++++++++++++++++++++------------ pipeline/simulator/state.h | 6 +- 3 files changed, 558 insertions(+), 175 deletions(-) diff --git a/pipeline/simulator/function.c b/pipeline/simulator/function.c index 3f562da..b3067b8 100644 --- a/pipeline/simulator/function.c +++ b/pipeline/simulator/function.c @@ -156,3 +156,216 @@ unsigned char* seperate_two(int in) return back; } + +char* toname(int instruction) +{ +unsigned char op; +unsigned char funct; +unsigned char shamt; +unsigned char rt; +unsigned char rd; +char* out; +if(instruction==0) +{ + out="NOP"; + return out; +} +op=(unsigned)instruction>>26; + + + + + switch(op) + { + case 0x00: + { + funct=cut_func(instruction); + + switch(funct) + { + case 0x20: ///add + { + out = "ADD"; + break; + } + case 0x21: ///addu + { + out = "ADDU"; + break; + } + case 0x22: ///sub + { + out = "SUB"; + break; + } + case 0x24: ///and + { + out = "AND"; + break; + } + case 0x25: ///or + { + out = "OR"; + break; + } + case 0x26: ///xor + { + out = "XOR"; + break; + } + case 0x27: ///nor + { + out = "NOR"; + break; + } + case 0x28: ///nand + { + out = "NAD"; + break; + } + case 0x2A: ///slt + { + out = "SLT"; + break; + } + case 0x00: ///sll + { + shamt = cut_shamt(instruction); + rt = cut_rt(instruction); + rd = cut_rd(instruction); + if(shamt==0&&rt==0&&rd==0) + out = "NOP"; + else + out = "SLL"; + break; + } + case 0x02: ///srl + { + out = "SRL"; + break; + } + case 0x03: ///sra + { + out = "SRA"; + break; + } + case 0x08: ///jr + { + out = "JR"; + break; + } + + } + break; + } + case 0x08: ///addi + { + out = "ADDI"; + break; + } + case 0x09: ///addiu + { + out = "ADDIU"; + break; + } + case 0x23: ///lw + { + out = "LW"; + break; + } + case 0x21: ///lh + { + out = "LH"; + break; + } + case 0x25: ///lhu + { + out = "LHU"; + break; + } + case 0x20: ///lb + { + out = "LB"; + break; + } + case 0x24: ///lbu + { + out = "LBU"; + break; + } + case 0x2B: ///sw + { + out = "SW"; + break; + } + case 0x29: ///sh + { + out = "SH"; + break; + } + case 0x28: ///sb + { + out = "SB"; + break; + } + case 0x0F: ///lui + { + out = "LUI"; + break; + } + case 0x0C: ///andi + { + out = "ANDI"; + break; + } + case 0x0D: ///ori + { + out = "ORI"; + break; + } + case 0x0E: ///nori + { + out = "NORI"; + break; + } + case 0x0A: ///slti + { + out = "SLTI"; + break; + } + case 0x04: ///beq + { + out = "BEQ"; + break; + } + case 0x05: ///bne + { + out = "BNE"; + break; + } + case 0x07: ///bgtz + { + out = "BGTZ"; + break; + } + case 0x02: ///j + { + out = "J"; + break; + } + case 0x03: ///jal + { + out = "JAL"; + break; + } + case 0x3F: ///halt + { + out = "HALT"; + break; + } + + + } + +return out; +} diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 309200d..e1e48ac 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -15,6 +15,21 @@ typedef struct _IDEX int read_data2; int immediate_ext; int write_reg; + int forward[3]; +/* +forward[0]: +0:nope +1:rs +2:rt +3:both + +forward[1]: +reg num of rs,rt + +forward[2]: +0:EX_DM to EX +1:EX_DM to ID +*/ } IDEX; @@ -26,6 +41,21 @@ typedef struct _EXDM int read_data2; int write_reg; int can_forward; + int forward[3]; +/* +forward[0]: +0:nope +1:rs +2:rt +3:both + +forward[1]: +reg num of rs,rt + +forward[2]: +0:EX_DM to EX +1:EX_DM to ID +*/ } EXDM; @@ -33,9 +63,10 @@ typedef struct _EXDM typedef struct _DMWB { int instruction; - int address; + int ALU_result; int data; int write_reg; + int can_forward; } DMWB; IFID IF_ID; @@ -66,63 +97,63 @@ int WB() { case 0x20: ///add { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x21: ///addu { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x22: ///sub { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x24: ///and { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x25: ///or { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x26: ///xor { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x27: ///nor { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x28: ///nand { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x2A: ///slt { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x00: ///sll { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x02: ///srl { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x03: ///sra { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x08: ///jr @@ -136,13 +167,13 @@ int WB() } case 0x08: ///addi { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x09: ///addiu { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x23: ///lw @@ -188,27 +219,27 @@ int WB() } case 0x0F: ///lui { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0C: ///andi { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0D: ///ori { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0E: ///nori { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0A: ///slti { - reg[DM_WB.write_reg] = DM_WB.address; + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x04: ///beq @@ -261,7 +292,7 @@ int DM() DM_WB.instruction=0; return 0; } - + DM_WB.can_forward = EX_DM.can_forward; op=(unsigned)EX_DM.instruction>>26; @@ -276,7 +307,7 @@ int DM() case 0x20: ///add { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -284,7 +315,7 @@ int DM() case 0x21: ///addu { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -292,7 +323,7 @@ int DM() case 0x22: ///sub { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -300,7 +331,7 @@ int DM() case 0x24: ///and { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -308,7 +339,7 @@ int DM() case 0x25: ///or { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -316,7 +347,7 @@ int DM() case 0x26: ///xor { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -324,7 +355,7 @@ int DM() case 0x27: ///nor { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -332,7 +363,7 @@ int DM() case 0x28: ///nand { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -340,7 +371,7 @@ int DM() case 0x2A: ///slt { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -348,7 +379,7 @@ int DM() case 0x00: ///sll { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -356,7 +387,7 @@ int DM() case 0x02: ///srl { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -364,7 +395,7 @@ int DM() case 0x03: ///sra { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -372,7 +403,7 @@ int DM() case 0x08: ///jr { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -384,7 +415,7 @@ int DM() case 0x08: ///addi { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -392,7 +423,7 @@ int DM() case 0x09: ///addiu { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -400,7 +431,7 @@ int DM() case 0x23: ///lw { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (int)combine(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1],dim[EX_DM.ALU_result+2],dim[EX_DM.ALU_result+3]); break; @@ -408,7 +439,7 @@ int DM() case 0x21: ///lh { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); break; @@ -416,7 +447,7 @@ int DM() case 0x25: ///lhu { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); break; @@ -424,7 +455,7 @@ int DM() case 0x20: ///lb { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (char)dim[EX_DM.ALU_result]; break; @@ -432,7 +463,7 @@ int DM() case 0x24: ///lbu { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = (unsigned)dim[EX_DM.ALU_result]; break; @@ -440,7 +471,7 @@ int DM() case 0x2B: ///sw { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; getting = seperate(EX_DM.read_data2); dim[EX_DM.ALU_result]=getting[0]; @@ -453,7 +484,7 @@ int DM() case 0x29: ///sh { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; getting = seperate_two(EX_DM.read_data2); dim[EX_DM.ALU_result]=getting[0]; @@ -464,7 +495,7 @@ int DM() case 0x28: ///sb { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; getting = malloc(sizeof(unsigned char)); getting[0] = (unsigned char)(EX_DM.read_data2&0x000000FF); @@ -475,7 +506,7 @@ int DM() case 0x0F: ///lui { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -483,7 +514,7 @@ int DM() case 0x0C: ///andi { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -491,7 +522,7 @@ int DM() case 0x0D: ///ori { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -499,7 +530,7 @@ int DM() case 0x0E: ///nori { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -507,7 +538,7 @@ int DM() case 0x0A: ///slti { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = EX_DM.ALU_result; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -515,7 +546,7 @@ int DM() case 0x04: ///beq { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -523,7 +554,7 @@ int DM() case 0x05: ///bne { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -531,7 +562,7 @@ int DM() case 0x07: ///bgtz { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -539,7 +570,7 @@ int DM() case 0x02: ///j { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -547,7 +578,7 @@ int DM() case 0x03: ///jal { DM_WB.instruction = EX_DM.instruction; - DM_WB.address = 0; + DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -577,6 +608,10 @@ int EX() return 0; } + + EX_DM.forward[0] = ID_EX.forward[0]; + EX_DM.forward[1] = ID_EX.forward[1]; + EX_DM.forward[2] = ID_EX.forward[2]; op=(unsigned)ID_EX.instruction>>26; @@ -895,16 +930,19 @@ int EX() int ID() { - + unsigned char rs=0; + unsigned char rt=0; + unsigned char rd=0; + unsigned char shamt=0; show_IDi = IF_ID.instruction; int flag=0; op=(unsigned)IF_ID.instruction>>26; + shamt = cut_shamt(IF_ID.instruction); + rt = cut_rt(IF_ID.instruction); + rd = cut_rd(IF_ID.instruction); + - unsigned char rs=0; - unsigned char rt=0; - unsigned char rd=0; - unsigned char shamt=0; short immediate=0; unsigned short unsigned_immediate=0; unsigned int address=0; @@ -914,7 +952,9 @@ int ID() ID_EX.instruction = 0; return 0; } - + ID_EX.forward[0] = 0; + ID_EX.forward[1] = 0; + ID_EX.forward[2] = 0; @@ -936,16 +976,19 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; + } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -963,16 +1006,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -989,16 +1034,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1015,16 +1062,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1041,16 +1090,17 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1067,16 +1117,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1093,16 +1145,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1119,16 +1173,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1145,16 +1201,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1172,8 +1230,9 @@ int ID() if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rt]; @@ -1191,8 +1250,9 @@ int ID() if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rt]; @@ -1210,8 +1270,9 @@ int ID() if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rt]; @@ -1227,8 +1288,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { PCback = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else PCback = reg[rs]; @@ -1248,8 +1310,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1267,8 +1330,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1286,8 +1350,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1305,8 +1370,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1324,8 +1390,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1343,8 +1410,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1362,8 +1430,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1381,16 +1450,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1407,16 +1478,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1433,16 +1506,18 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data2 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 0; } else ID_EX.read_data2 = reg[rt]; @@ -1470,8 +1545,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1489,8 +1565,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1508,8 +1585,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1527,8 +1605,9 @@ int ID() if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 0; } else ID_EX.read_data1 = reg[rs]; @@ -1541,29 +1620,47 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); - if(rs==EX_DM.write_reg && EX_DM.can_forward==1) + if(rs==DM_WB.write_reg && DM_WB.can_forward==1) { - if(EX_DM.ALU_result==reg[rt]) + if(rt==DM_WB.write_reg && DM_WB.can_forward==1) { - branch = 1; - PCback = IF_ID.PC + 4 + immediate*4; + if(DM_WB.ALU_result==DM_WB.ALU_result) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + + } + ID_EX.forward[0] = 3; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 1; + } + else + { + if(DM_WB.ALU_result==reg[rt]) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + } + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 1; } - forward[0] = 1; - forward[1] = rs; + } else { - if(rt==EX_DM.write_reg && EX_DM.can_forward==1) + if(rt==DM_WB.write_reg && DM_WB.can_forward==1) { - if(EX_DM.ALU_result==reg[rs]) + if(DM_WB.ALU_result==reg[rs]) { branch = 1; PCback = IF_ID.PC + 4 + immediate*4; } - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 1; } else { @@ -1573,8 +1670,9 @@ int ID() PCback = IF_ID.PC + 4 + immediate*4; } - forward[0] = 0; - forward[1] = 0; + ID_EX.forward[0] = 0; + ID_EX.forward[1] = 0; + ID_EX.forward[2] = 0; } @@ -1596,29 +1694,47 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); - if(rs==EX_DM.write_reg && EX_DM.can_forward==1) + if(rs==DM_WB.write_reg && DM_WB.can_forward==1) { - if(EX_DM.ALU_result!=reg[rt]) + if(rt==DM_WB.write_reg && DM_WB.can_forward==1) { - branch = 1; - PCback = IF_ID.PC + 4 + immediate*4; + if(DM_WB.ALU_result!=reg[rs]) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + + } + ID_EX.forward[0] = 3; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 1; + } + else + { + if(DM_WB.ALU_result!=reg[rt]) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + } + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 1; } - forward[0] = 1; - forward[1] = rs; + } else { - if(rt==EX_DM.write_reg && EX_DM.can_forward==1) + if(rt==DM_WB.write_reg && DM_WB.can_forward==1) { - if(EX_DM.ALU_result!=reg[rs]) + if(DM_WB.ALU_result!=reg[rs]) { branch = 1; PCback = IF_ID.PC + 4 + immediate*4; } - forward[0] = 1; - forward[1] = rt; + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 1; } else { @@ -1628,13 +1744,16 @@ int ID() PCback = IF_ID.PC + 4 + immediate*4; } - forward[0] = 0; - forward[1] = 0; + ID_EX.forward[0] = 0; + ID_EX.forward[1] = 0; + ID_EX.forward[2] = 0; } } + + ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; ID_EX.read_data1 = 0; @@ -1644,17 +1763,19 @@ int ID() } case 0x07: ///bgtz { + immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); - if(rs == EX_DM.write_reg && EX_DM.can_forward==1) + if(rs == DM_WB.write_reg && DM_WB.can_forward==1) { - if(EX_DM.ALU_result>0) + if(DM_WB.ALU_result>0) { branch = 1; PCback = IF_ID.PC + 4 + immediate*4; } - forward[0] = 1; - forward[1] = rs; + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 1; } else { @@ -1714,7 +1835,9 @@ int ID() int IF(int flags) { - + unsigned char rt=0; + unsigned char rd=0; + unsigned char shamt=0; int i=0; int j=0; @@ -1774,19 +1897,62 @@ int IF(int flags) IF_ID.instruction=0; } - fprintf(snapshot,"PC: %08X\n",tempPC); + fprintf(snapshot,"PC: 0x%08X\n",tempPC); if(change == 0) - fprintf(snapshot,"IF: %08X\n",IF_ID.instruction); + fprintf(snapshot,"IF: 0x%08X",IF_ID.instruction); else - fprintf(snapshot,"IF: %08X to_be_flushed\n",IF_ID.instruction); - fprintf(snapshot,"ID: %08X\n",show_IDi); - fprintf(snapshot,"EX: %08X\n",show_EXi); - fprintf(snapshot,"DM: %08X\n",show_DMi); - fprintf(snapshot,"WB: %08X\n",show_WBi); + fprintf(snapshot,"IF: 0x%08X to_be_flushed",IF_ID.instruction); + fprintf(snapshot,"\n"); + name = toname(show_IDi); + fprintf(snapshot,"ID: %s",name); + if(EX_DM.forward[2]==1&&EX_DM.forward[0]!=0) + { + if(EX_DM.forward[0]==1) + { + fprintf(snapshot," fwd_EX-DM_rs_$%d",EX_DM.forward[1]); + }else if(EX_DM.forward[0]==2) + { + fprintf(snapshot," fwd_EX-DM_rt_$%d",EX_DM.forward[1]); + }else + { + fprintf(snapshot," fwd_EX-DM_rs_$%d fwd_EX-DM_rt_$%d",EX_DM.forward[1],EX_DM.forward[2]); + } + } + fprintf(snapshot,"\n"); + name = toname(show_EXi); + fprintf(snapshot,"EX: %s",name); + if(EX_DM.forward[2]==0&&EX_DM.forward[0]!=0) + { + if(EX_DM.forward[0]==1) + { + fprintf(snapshot," fwd_EX-DM_rs_$%d",EX_DM.forward[1]); + }else if(EX_DM.forward[0]==2) + { + fprintf(snapshot," fwd_EX-DM_rt_$%d",EX_DM.forward[1]); + }else + { + fprintf(snapshot," fwd_EX-DM_rs_$%d fwd_EX-DM_rt_$%d",EX_DM.forward[1],EX_DM.forward[2]); + } + } + + fprintf(snapshot,"\n"); + name = toname(show_DMi); + fprintf(snapshot,"DM: %s",name); + fprintf(snapshot,"\n"); + name = toname(show_WBi); + fprintf(snapshot,"WB: %s",name); + fprintf(snapshot,"\n"); + fprintf(snapshot,"\n"); if(change == 1 ) IF_ID.instruction = 0; ///flush op=(unsigned)iim[i]>>26; + shamt = cut_shamt(iim[i]); + rt = cut_rt(iim[i]); + rd = cut_rd(iim[i]); + + if(op==0&&shamt==0&&rt==0&&rd==0) + IF_ID.instruction=0; if(op==0x3F) { return 1; diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index 2120b4c..eeffdf9 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -11,7 +11,10 @@ int IF(int); extern FILE *snapshot; extern FILE *error; -int forward[2]; +int stall; + + + int PCback,branch; int tempPC; int changePC; @@ -27,5 +30,6 @@ int show_IDi; int show_EXi; int show_DMi; int show_WBi; +char * name; unsigned char op,funct; From 75aa6a487a97f15eb85dbbeb96addef3001cd947 Mon Sep 17 00:00:00 2001 From: windstormer Date: Mon, 2 May 2016 04:22:09 +0800 Subject: [PATCH 16/32] pass open pipeline1.2.3 --- pipeline/simulator/main.c | 7 +- pipeline/simulator/state.c | 656 ++++++++++++++++++++++++++++++------- pipeline/simulator/state.h | 1 + 3 files changed, 540 insertions(+), 124 deletions(-) diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index 27aaf45..8e0560d 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -14,6 +14,7 @@ unsigned char dim[1024]; int temp; FILE *snapshot; FILE *error; +int count=0; int main(void) @@ -94,7 +95,7 @@ int main(void) **/ int check[5]={0}; int flags=0; -int count=0; + int j=0; while(1) { @@ -114,12 +115,12 @@ int j=0; } else check[4]=IF(1); - +fprintf(snapshot,"\n"); if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) break; count++; -fprintf(snapshot,"\n"); + } diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index e1e48ac..41b3501 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -16,20 +16,21 @@ typedef struct _IDEX int immediate_ext; int write_reg; int forward[3]; -/* -forward[0]: -0:nope -1:rs -2:rt -3:both - -forward[1]: -reg num of rs,rt - -forward[2]: -0:EX_DM to EX -1:EX_DM to ID -*/ + /* + forward[0]: + 0:nope + 1:rs + 2:rt + 3:both + + forward[1]: + reg num of rs,rt + + forward[2]: + 0:EX_DM to EX + 1:EX_DM to ID + */ + int stall; } IDEX; @@ -42,20 +43,21 @@ typedef struct _EXDM int write_reg; int can_forward; int forward[3]; -/* -forward[0]: -0:nope -1:rs -2:rt -3:both - -forward[1]: -reg num of rs,rt - -forward[2]: -0:EX_DM to EX -1:EX_DM to ID -*/ + /* + forward[0]: + 0:nope + 1:rs + 2:rt + 3:both + + forward[1]: + reg num of rs,rt + + forward[2]: + 0:EX_DM to EX + 1:EX_DM to ID + */ + int stall; } EXDM; @@ -264,7 +266,7 @@ int WB() } case 0x03: ///jal { - + reg[DM_WB.write_reg]=DM_WB.ALU_result; break; } case 0x3F: ///halt @@ -289,7 +291,11 @@ int DM() int flag=0; if(EX_DM.instruction==0) { + DM_WB.ALU_result=0; + DM_WB.can_forward=0; + DM_WB.data=0; DM_WB.instruction=0; + DM_WB.write_reg=0; return 0; } DM_WB.can_forward = EX_DM.can_forward; @@ -578,7 +584,7 @@ int DM() case 0x03: ///jal { DM_WB.instruction = EX_DM.instruction; - DM_WB.ALU_result = 0; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -602,16 +608,24 @@ int EX() show_EXi = ID_EX.instruction; int temp=0; int flag=0; + EX_DM.stall = ID_EX.stall; + EX_DM.forward[0] = ID_EX.forward[0]; + EX_DM.forward[1] = ID_EX.forward[1]; + EX_DM.forward[2] = ID_EX.forward[2]; + if(ID_EX.instruction==0) { + EX_DM.ALU_result==0; + EX_DM.read_data2=0; + EX_DM.write_reg=0; + EX_DM.can_forward=0; EX_DM.instruction=0; return 0; } - EX_DM.forward[0] = ID_EX.forward[0]; - EX_DM.forward[1] = ID_EX.forward[1]; - EX_DM.forward[2] = ID_EX.forward[2]; + + op=(unsigned)ID_EX.instruction>>26; @@ -907,8 +921,10 @@ int EX() } case 0x03: ///jal { - EX_DM.can_forward=0; + EX_DM.can_forward=1; EX_DM.instruction=ID_EX.instruction; + EX_DM.ALU_result=ID_EX.immediate_ext; + EX_DM.write_reg=ID_EX.write_reg; break; } case 0x3F: ///halt @@ -946,15 +962,21 @@ int ID() short immediate=0; unsigned short unsigned_immediate=0; unsigned int address=0; + ID_EX.forward[0] = 0; + ID_EX.forward[1] = 0; + ID_EX.forward[2] = 0; + ID_EX.stall = 0; if(IF_ID.instruction==0) { + ID_EX.immediate_ext=0; + ID_EX.read_data1=0; + ID_EX.read_data2=0; + ID_EX.write_reg = 0; ID_EX.instruction = 0; return 0; } - ID_EX.forward[0] = 0; - ID_EX.forward[1] = 0; - ID_EX.forward[2] = 0; + @@ -973,6 +995,21 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; + + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1003,6 +1040,20 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1031,6 +1082,20 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1059,6 +1124,20 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1087,6 +1166,23 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1102,7 +1198,7 @@ int ID() ID_EX.forward[1] = rt; ID_EX.forward[2] = 0; } - else + else ID_EX.read_data2 = reg[rt]; ID_EX.write_reg = rd; break; @@ -1114,6 +1210,20 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1142,6 +1252,20 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1170,6 +1294,20 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1198,6 +1336,20 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1227,6 +1379,13 @@ int ID() ID_EX.immediate_ext = shamt; ID_EX.instruction = IF_ID.instruction; + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1247,6 +1406,15 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = shamt; ID_EX.instruction = IF_ID.instruction; + + + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1267,6 +1435,15 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = shamt; ID_EX.instruction = IF_ID.instruction; + + + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rt==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1285,6 +1462,15 @@ int ID() ID_EX.instruction = IF_ID.instruction; rs = cut_rs(IF_ID.instruction); branch = 1; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { PCback = EX_DM.ALU_result; @@ -1307,6 +1493,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1327,6 +1522,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1347,6 +1551,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1367,6 +1580,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1387,6 +1609,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1407,6 +1638,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1427,6 +1667,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1447,6 +1696,21 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1475,6 +1739,21 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1503,6 +1782,20 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1542,6 +1835,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1562,6 +1864,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1582,6 +1893,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1602,6 +1922,15 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==EX_DM.write_reg && EX_DM.can_forward==1) { ID_EX.read_data1 = EX_DM.ALU_result; @@ -1617,9 +1946,26 @@ int ID() } case 0x04: ///beq { + immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + + break; + } + + if(rs==DM_WB.write_reg && DM_WB.can_forward==1) { if(rt==DM_WB.write_reg && DM_WB.can_forward==1) @@ -1650,8 +1996,10 @@ int ID() } else { + if(rt==DM_WB.write_reg && DM_WB.can_forward==1) { + if(DM_WB.ALU_result==reg[rs]) { branch = 1; @@ -1680,6 +2028,8 @@ int ID() + + ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; ID_EX.read_data1 = 0; @@ -1694,66 +2044,85 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); - if(rs==DM_WB.write_reg && DM_WB.can_forward==1) - { - if(rt==DM_WB.write_reg && DM_WB.can_forward==1) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) { - if(DM_WB.ALU_result!=reg[rs]) - { - branch = 1; - PCback = IF_ID.PC + 4 + immediate*4; + ID_EX.stall=1; + ID_EX.instruction=0; - } - ID_EX.forward[0] = 3; - ID_EX.forward[1] = rs; - ID_EX.forward[2] = 1; + break; } - else + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) { - if(DM_WB.ALU_result!=reg[rt]) - { - branch = 1; - PCback = IF_ID.PC + 4 + immediate*4; + ID_EX.stall=1; + ID_EX.instruction=0; - } - ID_EX.forward[0] = 1; - ID_EX.forward[1] = rs; - ID_EX.forward[2] = 1; + break; } - } - else + if(EX_DM.stall!=1) { - if(rt==DM_WB.write_reg && DM_WB.can_forward==1) + if(rs==DM_WB.write_reg && DM_WB.can_forward==1) { - if(DM_WB.ALU_result!=reg[rs]) + if(rt==DM_WB.write_reg && DM_WB.can_forward==1) { - branch = 1; - PCback = IF_ID.PC + 4 + immediate*4; - + if(DM_WB.ALU_result!=reg[rs]) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + + } + ID_EX.forward[0] = 3; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 1; } - ID_EX.forward[0] = 2; - ID_EX.forward[1] = rt; - ID_EX.forward[2] = 1; + else + { + if(DM_WB.ALU_result!=reg[rt]) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + + } + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 1; + } + } else { - if(reg[rs]!=reg[rt]) + if(rt==DM_WB.write_reg && DM_WB.can_forward==1) { - branch = 1; - PCback = IF_ID.PC + 4 + immediate*4; + if(DM_WB.ALU_result!=reg[rs]) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + + } + ID_EX.forward[0] = 2; + ID_EX.forward[1] = rt; + ID_EX.forward[2] = 1; + } + else + { + if(reg[rs]!=reg[rt]) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + + } + ID_EX.forward[0] = 0; + ID_EX.forward[1] = 0; + ID_EX.forward[2] = 0; } - ID_EX.forward[0] = 0; - ID_EX.forward[1] = 0; - ID_EX.forward[2] = 0; } - } + ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; ID_EX.read_data1 = 0; @@ -1766,29 +2135,42 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); - if(rs == DM_WB.write_reg && DM_WB.can_forward==1) - { - if(DM_WB.ALU_result>0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) { - branch = 1; - PCback = IF_ID.PC + 4 + immediate*4; + ID_EX.stall=1; + ID_EX.instruction=0; + + break; } - ID_EX.forward[0] = 1; - ID_EX.forward[1] = rs; - ID_EX.forward[2] = 1; - } - else + + + if(EX_DM.stall!=1) { - if(reg[rs]>0) + if(rs == DM_WB.write_reg && DM_WB.can_forward==1) + { + if(DM_WB.ALU_result>0) + { + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + } + ID_EX.forward[0] = 1; + ID_EX.forward[1] = rs; + ID_EX.forward[2] = 1; + } + else { + if(reg[rs]>0) + { - branch = 1; - PCback = IF_ID.PC + 4 + immediate*4; + branch = 1; + PCback = IF_ID.PC + 4 + immediate*4; + } } } + ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; ID_EX.read_data1 = 0; @@ -1811,7 +2193,7 @@ int ID() ID_EX.instruction = IF_ID.instruction; address = cut_address(IF_ID.instruction); address=address<<2; - reg[31] = IF_ID.PC; + ID_EX.immediate_ext = IF_ID.PC; PCback = (unsigned) IF_ID.PC>>28; PCback = PCback<<28; PCback = (unsigned)PC|address; @@ -1851,46 +2233,63 @@ int IF(int flags) } else { - if(change==1) + if(EX_DM.stall==1) { - tempPC = changePC; - change = 0; + tempPC = tempPC; } else { - if(branch==1) + if(change==1) { - tempPC +=4; - branch=0; - change=1; - changePC = PCback; + tempPC = changePC; + change = 0; } else { - tempPC+=4; + if(branch==1) + { + tempPC +=4; + branch=0; + change=1; + changePC = PCback; + } + else + { + tempPC+=4; - } + } + } } + } //printf("\nflags = %d, bramch = %d, change = %d\n\n",flags,branch,change); if(tempPC>=PC_start) { - if(change == 1) + if(ID_EX.stall==1) { - i=(tempPC-PC_start)/4; - IF_ID.instruction = iim[i]; + i = (tempPC-PC_start)/4; + IF_ID.instruction = IF_ID.instruction; } else { - i=(tempPC-PC_start)/4; - IF_ID.instruction=iim[i]; - IF_ID.PC=tempPC; + if(change == 1) + { + i=(tempPC-PC_start)/4; + IF_ID.instruction = iim[i]; + } + else + { + i=(tempPC-PC_start)/4; + IF_ID.instruction=iim[i]; + IF_ID.PC=tempPC; + } } + } else { @@ -1898,44 +2297,59 @@ int IF(int flags) } fprintf(snapshot,"PC: 0x%08X\n",tempPC); - if(change == 0) - fprintf(snapshot,"IF: 0x%08X",IF_ID.instruction); + if(change == 0&& ID_EX.stall==0) + fprintf(snapshot,"IF: 0x%08X",iim[i]); + else if(change==1&&ID_EX.stall==0) + fprintf(snapshot,"IF: 0x%08X to_be_flushed",iim[i]); else - fprintf(snapshot,"IF: 0x%08X to_be_flushed",IF_ID.instruction); - fprintf(snapshot,"\n"); + fprintf(snapshot,"IF: 0x%08X to_be_stalled",iim[i]); + fprintf(snapshot,"\n"); name = toname(show_IDi); fprintf(snapshot,"ID: %s",name); - if(EX_DM.forward[2]==1&&EX_DM.forward[0]!=0) + if(ID_EX.stall==1) + fprintf(snapshot," to_be_stalled"); + else { - if(EX_DM.forward[0]==1) - { - fprintf(snapshot," fwd_EX-DM_rs_$%d",EX_DM.forward[1]); - }else if(EX_DM.forward[0]==2) + if(ID_EX.forward[2]==1&&ID_EX.forward[0]!=0) { - fprintf(snapshot," fwd_EX-DM_rt_$%d",EX_DM.forward[1]); - }else - { - fprintf(snapshot," fwd_EX-DM_rs_$%d fwd_EX-DM_rt_$%d",EX_DM.forward[1],EX_DM.forward[2]); + if(ID_EX.forward[0]==1) + { + fprintf(snapshot," fwd_EX-DM_rs_$%d",ID_EX.forward[1]); + } + else if(ID_EX.forward[0]==2) + { + fprintf(snapshot," fwd_EX-DM_rt_$%d",ID_EX.forward[1]); + } + else + { + fprintf(snapshot," fwd_EX-DM_rs_$%d fwd_EX-DM_rt_$%d",ID_EX.forward[1],ID_EX.forward[2]); + } } } + fprintf(snapshot,"\n"); name = toname(show_EXi); fprintf(snapshot,"EX: %s",name); + if(EX_DM.forward[2]==0&&EX_DM.forward[0]!=0) { - if(EX_DM.forward[0]==1) + if(EX_DM.forward[0]==1) { fprintf(snapshot," fwd_EX-DM_rs_$%d",EX_DM.forward[1]); - }else if(EX_DM.forward[0]==2) + } + else if(EX_DM.forward[0]==2) { fprintf(snapshot," fwd_EX-DM_rt_$%d",EX_DM.forward[1]); - }else + } + else { fprintf(snapshot," fwd_EX-DM_rs_$%d fwd_EX-DM_rt_$%d",EX_DM.forward[1],EX_DM.forward[2]); } } + + fprintf(snapshot,"\n"); name = toname(show_DMi); fprintf(snapshot,"DM: %s",name); diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index eeffdf9..39c706c 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -12,6 +12,7 @@ extern FILE *snapshot; extern FILE *error; int stall; +extern int count; From 6ba6838e5162c5413b66cfffc0cda6c9038d3460 Mon Sep 17 00:00:00 2001 From: windstormer Date: Mon, 2 May 2016 06:07:31 +0800 Subject: [PATCH 17/32] pass open_testcase --- pipeline/simulator/main.c | 65 +-- pipeline/simulator/main1.c | 740 --------------------------------- pipeline/simulator/state.c | 814 ++++++++++++++++++++++++++----------- pipeline/simulator/state.h | 2 + 4 files changed, 625 insertions(+), 996 deletions(-) delete mode 100644 pipeline/simulator/main1.c diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index 8e0560d..44258d6 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -15,6 +15,7 @@ int temp; FILE *snapshot; FILE *error; int count=0; +extern errors[4]; int main(void) @@ -93,35 +94,47 @@ int main(void) sins: int of the number of instruction sdata : int of the number of memory (word) **/ - int check[5]={0}; -int flags=0; - -int j=0; - while(1) - { - // if(count>4)break; - fprintf(snapshot,"cycle %d\n",count); - for(j=0; j<32; j++) + int check[5]= {0}; + int flags=0; + + int j=0; + while(1) + { + // if(count>4)break; + + errors[0]=0; + errors[1]=0; + errors[2]=0; + errors[3]=0; + + fprintf(snapshot,"cycle %d\n",count); + for(j=0; j<32; j++) { fprintf(snapshot,"$%02d: 0x%08X\n",j,reg[j]); } - check[0]=WB(); - check[1]=DM(); - check[2]=EX(); - check[3]=ID(); - if(flags==0) - {check[4]=IF(0); - flags=1; - } - else - check[4]=IF(1); -fprintf(snapshot,"\n"); -if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) - break; - -count++; - - } + check[0]=WB(); + check[1]=DM(); + check[2]=EX(); + check[3]=ID(); + if(flags==0) + { + check[4]=IF(0); + flags=1; + } + else + check[4]=IF(1); + fprintf(snapshot,"\n"); + if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) + break; + + if(check[1]==2) + { + break; + } + + count++; + + } diff --git a/pipeline/simulator/main1.c b/pipeline/simulator/main1.c deleted file mode 100644 index 174e3fd..0000000 --- a/pipeline/simulator/main1.c +++ /dev/null @@ -1,740 +0,0 @@ -#include -#include -#include "function.h" - - - - -int reg[32]; -int PC; -int PC_start; -unsigned char ii[1024]; -unsigned char di[1024]; -int iim[256]; -unsigned char dim[1024]; -int temp; - -int main(void) -{ - FILE *iimage = fopen("./iimage.bin","rb"); - FILE *dimage = fopen("./dimage.bin","rb"); - FILE *error = fopen("./error_dump.rpt","w"); - FILE *snapshot = fopen("./snapshot.rpt","w"); - - - - - int sdata=0,sins=0; - int i,j; - - - memset(reg,0,sizeof(reg)); - memset(ii,0,sizeof(ii)); - memset(di,0,sizeof(di)); - memset(iim,0,sizeof(iim)); - memset(dim,0,sizeof(dim)); - PC=0; - - fseek(iimage , 0 , SEEK_END); - - - rewind (iimage); - - fread(ii,sizeof(unsigned char),8,iimage); - - fseek(dimage , 0 , SEEK_END); - - - rewind (dimage); - - fread(di,sizeof(unsigned char),8,dimage); - - /* - for(i=0;i=PC_start) - { - op=(unsigned)iim[i]>>26; - - - - - switch(op) - { - case 0x00: - { - funct=cut_func(iim[i]); - - switch(funct) - { - case 0x20: - { - - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - if(rd==0) - errors[0]=1; - - temp=reg[rs]+reg[rt]; - if(overflow_detect(temp,reg[rs],reg[rt])) - errors[1]=1; - reg[rd]=reg[rs]+reg[rt]; ///need overflow detect - if(rd==0) - reg[rd]=0; - PC+=4; - break; - } - case 0x21: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - if(rd==0) - errors[0]=1; - reg[rd]=reg[rs]+reg[rt]; - if(rd==0) - reg[rd]=0; - PC+=4; - break; - } - case 0x22: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - if(rd==0) - errors[0]=1; - temp=reg[rs]+(-1)*reg[rt]; - - if(overflow_detect(temp,reg[rs],(-1)*reg[rt])) - errors[1]=1; - reg[rd]=reg[rs]+(-1)*reg[rt]; - if(rd==0) - reg[rd]=0; - PC+=4; - break; - } - case 0x24: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - if(rd==0) - errors[0]=1; - else - reg[rd]=reg[rs]®[rt]; - PC+=4; - break; - } - case 0x25: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - if(rd==0) - errors[0]=1; - else - reg[rd]=reg[rs]|reg[rt]; - PC+=4; - break; - } - case 0x26: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - if(rd==0) - errors[0]=1; - else - reg[rd]=reg[rs]^reg[rt]; - PC+=4; - break; - } - case 0x27: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - if(rd==0) - errors[0]=1; - else - reg[rd]=~(reg[rs]|reg[rt]); - PC+=4; - break; - } - case 0x28: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - if(rd==0) - errors[0]=1; - else - reg[rd]=~(reg[rs]®[rt]); - PC+=4; - break; - } - case 0x2A: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - if(rd==0) - errors[0]=1; - else - { - if(reg[rs]>shamt; - PC+=4; - break; - } - case 0x03: - { - rt=cut_rt(iim[i]); - rd=cut_rd(iim[i]); - shamt=cut_shamt(iim[i]); - if(rd==0) - errors[0]=1; - else - reg[rd]=reg[rt]>>shamt; - PC+=4; - break; - } - case 0x08: - { - - rs=cut_rs(iim[i]); - PC=reg[rs]; - break; - } - - } - break; - } - case 0x08: - { - - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - if(rt==0) - errors[0]=1; - temp=reg[rs]+immediate; - - - if(overflow_detect(temp,reg[rs],(int)immediate)) - errors[1]=1; - reg[rt]=reg[rs]+immediate; ///need overflow detect - if(rt==0) - reg[rt]=0; - PC+=4; - break; - } - case 0x09: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - if(rt==0) - errors[0]=1; - else - reg[rt]=reg[rs]+immediate; - PC+=4; - break; - } - case 0x23: - { - - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - if(rt==0) - errors[0]=1; - - read= reg[rs]+immediate; ///need overflow detect && data misaligned - if(overflow_detect(read,reg[rs],(int)immediate)) - errors[1]=1; - if(read>=1021 || read<0) - { - errors[2]=1; - flag=1; - - } - if(read%4!=0) - { - errors[3]=1; - flag=1; - - } - if(flag==1) - break; - reg[rt]=(int)combine(dim[read],dim[read+1],dim[read+2],dim[read+3]); - - if(rt==0) - reg[rt]=0; - - - PC+=4; - break; - } - case 0x21: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - if(rt==0) - errors[0]=1; - read= reg[rs]+immediate; ///need overflow detect && data misaligned - if(overflow_detect(read,reg[rs],(int)immediate)) - errors[1]=1; - if(read>=1023 || read<0) - { - errors[2]=1; - flag=1; - - } - if(read%2!=0) - { - errors[3]=1; - flag=1; - - } - if(flag==1)break; - reg[rt]=(short)combine_two(dim[read],dim[read+1]); - if(rt==0) - reg[rt]=0; - - PC+=4; - break; - } - case 0x25: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - if(rt==0) - errors[0]=1; - - read= reg[rs]+immediate; ///need overflow detect && data misaligned - if(overflow_detect(read,reg[rs],(int)immediate)) - errors[1]=1; - if(read>=1023 || read <0) - { - errors[2]=1; - flag=1; - - } - if(read%2!=0) - { - errors[3]=1; - flag=1; - - } - if(flag==1)break; - reg[rt]=combine_two(dim[read],dim[read+1]); - if(rt==0) - reg[rt]=0; - - PC+=4; - break; - } - case 0x20: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - if(rt==0) - errors[0]=1; - - read= reg[rs]+immediate; ///need overflow detect && data misaligned - if(overflow_detect(read,reg[rs],(int)immediate)) - errors[1]=1; - if(read>=1024 || read<0) - { - errors[2]=1; - flag=1; - - } - if(flag==1)break; - reg[rt]=(char)dim[read]; - if(rt==0) - reg[rt]=0; - - PC+=4; - break; - } - case 0x24: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - if(rt==0) - errors[0]=1; - - read= reg[rs]+immediate; ///need overflow detect && data misaligned - if(overflow_detect(read,reg[rs],(int)immediate)) - errors[1]=1; - if(read>=1024 || read<0) - { - errors[2]=1; - flag=1; - - } - if(flag==1)break; - reg[rt]=(unsigned)dim[read]; - if(rt==0) - reg[rt]=0; - - PC+=4; - break; - } - case 0x2B: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - - getting=seperate(reg[rt]); - read= reg[rs]+immediate; ///need overflow detect && data misaligned - if(overflow_detect(read,reg[rs],(int)immediate)) - errors[1]=1; - if(read>=1021 || read<0) - { - errors[2]=1; - flag=1; - - } - if(read%4!=0) - { - errors[3]=1; - flag=1; - - } - if(flag==1)break; - dim[read]=getting[0]; - dim[read+1]=getting[1]; - dim[read+2]=getting[2]; - dim[read+3]=getting[3]; - - PC+=4; - break; - } - case 0x29: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - getting=seperate_two(reg[rt]); - read= reg[rs]+immediate; ///need overflow detect && data misaligned - if(overflow_detect(read,reg[rs],(int)immediate)) - errors[1]=1; - if(read>=1023 || read<0) - { - errors[2]=1; - flag=1; - - } - if(read%2!=0) - { - errors[3]=1; - flag=1; - - } - if(flag==1)break; - dim[read]=getting[0]; - dim[read+1]=getting[1]; - PC+=4; - break; - } - case 0x28: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - getting[0]=(unsigned char)(reg[rt]&0x000000FF); - read= reg[rs]+immediate; ///need overflow detect && data misaligned - if(overflow_detect(read,reg[rs],(int)immediate)) - errors[1]=1; - if(read>=1024 || read<0) - { - errors[2]=1; - flag=1; - - } - if(flag==1)break; - dim[read]=getting[0]; - PC+=4; - break; - } - case 0x0F: - { - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - if(rt==0) - errors[0]=1; - else - reg[rt]=immediate<<16; - PC+=4; - break; - } - case 0x0C: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - unsigned_immediate=cut_immediate_unsigned(iim[i]); - if(rt==0) - errors[0]=1; - else - reg[rt]=reg[rs]&unsigned_immediate; - PC+=4; - break; - } - case 0x0D: - { - - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - unsigned_immediate=cut_immediate_unsigned(iim[i]); - - if(rt==0) - errors[0]=1; - else - reg[rt]=(reg[rs]|unsigned_immediate); - - PC+=4; - break; - } - case 0x0E: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - unsigned_immediate=cut_immediate_unsigned(iim[i]); - if(rt==0) - errors[0]=1; - else - reg[rt]=~(reg[rs]|unsigned_immediate); - PC+=4; - break; - } - case 0x0A: - { - rs=cut_rs(iim[i]); - rt=cut_rt(iim[i]); - immediate=cut_immediate(iim[i]); - if(rt==0) - errors[0]=1; - else - { - if(reg[rs]0) - { - read=immediate*4+4; ///need overflow detect - if(overflow_detect(read,immediate*4,4)) - errors[1]=1; - PC+=read; - } - else PC+=4; - break; - } - case 0x02: - { - address=cut_address(iim[i]); - address=address<<2; - PC+=4; - PC=(unsigned)PC>>28; - PC=PC<<28; - PC=(unsigned)PC|address; - break; - } - case 0x03: - { - address=cut_address(iim[i]); - address=address<<2; - PC+=4; - reg[31]=PC; - - PC=(unsigned)PC>>28; - PC=PC<<28; - PC=(unsigned)PC|address; - break; - } - case 0x3F: - { - // printf("halt\n"); - flag=1; - break; - } - - - } - if(errors[0]==1)fprintf(error,"In cycle %d: Write $0 Error\n",cycle+1); - if(errors[1]==1)fprintf(error,"In cycle %d: Number Overflow\n",cycle+1); - if(errors[2]==1)fprintf(error,"In cycle %d: Address Overflow\n",cycle+1); - if(errors[3]==1)fprintf(error,"In cycle %d: Misalignment Error\n",cycle+1); - } - else PC+=4; - - i=(PC-PC_start)/4; - - - - cycle++; - - fprintf(snapshot,"\n\n"); - - - if(flag==1) break; - } - - return 0; -} diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 41b3501..0d2912f 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -99,63 +99,135 @@ int WB() { case 0x20: ///add { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x21: ///addu { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x22: ///sub { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x24: ///and { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x25: ///or { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x26: ///xor { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x27: ///nor { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x28: ///nand { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x2A: ///slt { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x00: ///sll { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x02: ///srl { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x03: ///sra { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x08: ///jr @@ -169,39 +241,81 @@ int WB() } case 0x08: ///addi { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x09: ///addiu { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x23: ///lw { - reg[DM_WB.write_reg] = DM_WB.data; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.data; break; } case 0x21: ///lh { - reg[DM_WB.write_reg] = DM_WB.data; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.data; break; } case 0x25: ///lhu { - reg[DM_WB.write_reg] = DM_WB.data; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.data; break; } case 0x20: ///lb { - reg[DM_WB.write_reg] = DM_WB.data; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.data; break; } case 0x24: ///lbu { - reg[DM_WB.write_reg] = DM_WB.data; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.data; break; } case 0x2B: ///sw @@ -221,27 +335,57 @@ int WB() } case 0x0F: ///lui { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0C: ///andi { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0D: ///ori { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0E: ///nori { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0A: ///slti { - reg[DM_WB.write_reg] = DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x04: ///beq @@ -266,7 +410,13 @@ int WB() } case 0x03: ///jal { - reg[DM_WB.write_reg]=DM_WB.ALU_result; + if(DM_WB.write_reg==0) + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else + reg[DM_WB.write_reg]=DM_WB.ALU_result; break; } case 0x3F: ///halt @@ -289,6 +439,7 @@ int DM() show_DMi = EX_DM.instruction; unsigned char *getting; int flag=0; + int flags=0; if(EX_DM.instruction==0) { DM_WB.ALU_result=0; @@ -439,6 +590,18 @@ int DM() DM_WB.instruction = EX_DM.instruction; DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; + if(EX_DM.ALU_result>=1021||EX_DM.ALU_result<0) + { + errors[1]=1; + flags=1; + } + if(EX_DM.ALU_result%4!=0) + { + errors[2]=1; + flags=1; + } + if(flags==1) + break; DM_WB.data = (int)combine(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1],dim[EX_DM.ALU_result+2],dim[EX_DM.ALU_result+3]); break; } @@ -447,6 +610,18 @@ int DM() DM_WB.instruction = EX_DM.instruction; DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; + if(EX_DM.ALU_result>=1023||EX_DM.ALU_result<0) + { + errors[1]=1; + flags=1; + } + if(EX_DM.ALU_result%2!=0) + { + errors[2]=1; + flags=1; + } + if(flags==1) + break; DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); break; } @@ -455,7 +630,19 @@ int DM() DM_WB.instruction = EX_DM.instruction; DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; - DM_WB.data = (short)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); + if(EX_DM.ALU_result>=1023||EX_DM.ALU_result<0) + { + errors[1]=1; + flags=1; + } + if(EX_DM.ALU_result%2!=0) + { + errors[2]=1; + flags=1; + } + if(flags==1) + break; + DM_WB.data = (unsigned)combine_two(dim[EX_DM.ALU_result],dim[EX_DM.ALU_result+1]); break; } case 0x20: ///lb @@ -463,6 +650,13 @@ int DM() DM_WB.instruction = EX_DM.instruction; DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; + if(EX_DM.ALU_result>=1024||EX_DM.ALU_result<0) + { + errors[1]=1; + flags=1; + } + if(flags==1) + break; DM_WB.data = (char)dim[EX_DM.ALU_result]; break; } @@ -471,6 +665,13 @@ int DM() DM_WB.instruction = EX_DM.instruction; DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; + if(EX_DM.ALU_result>=1024||EX_DM.ALU_result<0) + { + errors[1]=1; + flags=1; + } + if(flags==1) + break; DM_WB.data = (unsigned)dim[EX_DM.ALU_result]; break; } @@ -480,6 +681,18 @@ int DM() DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; getting = seperate(EX_DM.read_data2); + if(EX_DM.ALU_result>=1021||EX_DM.ALU_result<0) + { + errors[1]=1; + flags=1; + } + if(EX_DM.ALU_result%4!=0) + { + errors[2]=1; + flags=1; + } + if(flags==1) + break; dim[EX_DM.ALU_result]=getting[0]; dim[EX_DM.ALU_result+1]=getting[1]; dim[EX_DM.ALU_result+2]=getting[2]; @@ -493,6 +706,18 @@ int DM() DM_WB.ALU_result = 0; DM_WB.write_reg = EX_DM.write_reg; getting = seperate_two(EX_DM.read_data2); + if(EX_DM.ALU_result>=1023||EX_DM.ALU_result<0) + { + errors[1]=1; + flags=1; + } + if(EX_DM.ALU_result%2!=0) + { + errors[2]=1; + flags=1; + } + if(flags==1) + break; dim[EX_DM.ALU_result]=getting[0]; dim[EX_DM.ALU_result+1]=getting[1]; DM_WB.data = 0; @@ -505,6 +730,14 @@ int DM() DM_WB.write_reg = EX_DM.write_reg; getting = malloc(sizeof(unsigned char)); getting[0] = (unsigned char)(EX_DM.read_data2&0x000000FF); + if(EX_DM.ALU_result>=1024||EX_DM.ALU_result<0) + { + errors[1]=1; + flags=1; + } + if(flags==1) + break; + dim[EX_DM.ALU_result]=getting[0]; DM_WB.data = 0; break; @@ -598,8 +831,13 @@ int DM() } - if(flag==1)return 1; + if(flags==1)return 2; + else + { + if(flag==1)return 1; else return 0; + } + } int EX() @@ -612,6 +850,7 @@ int EX() EX_DM.forward[0] = ID_EX.forward[0]; EX_DM.forward[1] = ID_EX.forward[1]; EX_DM.forward[2] = ID_EX.forward[2]; + EX_DM.ALU_result=0; if(ID_EX.instruction==0) { @@ -641,27 +880,38 @@ int EX() { case 0x20: ///add { + + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.read_data2; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.read_data2)) + errors[3]=1; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; } case 0x21: ///addu { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.read_data2; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; } case 0x22: ///sub { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+(-1)*ID_EX.read_data2; + if(overflow_detect(temp,ID_EX.read_data1,(-1)*ID_EX.read_data2)) + errors[3]=1; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; @@ -671,6 +921,7 @@ int EX() EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1&ID_EX.read_data2; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; @@ -680,6 +931,7 @@ int EX() EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1|ID_EX.read_data2; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; @@ -689,6 +941,7 @@ int EX() EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1^ID_EX.read_data2; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; @@ -698,7 +951,9 @@ int EX() EX_DM.instruction=ID_EX.instruction; temp=~(ID_EX.read_data1|ID_EX.read_data2); EX_DM.can_forward=1; + EX_DM.ALU_result=temp; + EX_DM.write_reg = ID_EX.write_reg; break; } case 0x28: ///nand @@ -706,6 +961,7 @@ int EX() EX_DM.instruction=ID_EX.instruction; temp=~(ID_EX.read_data1&ID_EX.read_data2); EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; @@ -717,6 +973,7 @@ int EX() temp=1; else temp=0; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; @@ -726,6 +983,7 @@ int EX() EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1<>ID_EX.immediate_ext; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; @@ -744,6 +1003,7 @@ int EX() EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1>>ID_EX.immediate_ext; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; @@ -760,9 +1020,13 @@ int EX() } case 0x08: ///addi { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.immediate_ext)) + errors[3]=1; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; @@ -772,59 +1036,91 @@ int EX() EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; EX_DM.can_forward=1; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; } case 0x23: ///lw { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.immediate_ext)) + errors[3]=1; + EX_DM.can_forward=0; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; } case 0x21: ///lh { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.immediate_ext)) + errors[3]=1; + EX_DM.can_forward=0; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; } case 0x25: ///lhu { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.immediate_ext)) + errors[3]=1; + EX_DM.can_forward=0; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; + break; } case 0x20: ///lb { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.immediate_ext)) + errors[3]=1; + EX_DM.can_forward=0; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; + break; } case 0x24: ///lbu { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.immediate_ext)) + errors[3]=1; + EX_DM.can_forward=0; + EX_DM.ALU_result=temp; EX_DM.write_reg=ID_EX.write_reg; break; + break; } case 0x2B: ///sw { EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.immediate_ext)) + errors[3]=1; + EX_DM.can_forward=0; EX_DM.ALU_result=temp; EX_DM.read_data2=ID_EX.read_data2; @@ -834,6 +1130,9 @@ int EX() { EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.immediate_ext)) + errors[3]=1; + EX_DM.can_forward=0; EX_DM.ALU_result=temp; EX_DM.read_data2=ID_EX.read_data2; @@ -843,6 +1142,9 @@ int EX() { EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1+ID_EX.immediate_ext; + if(overflow_detect(temp,ID_EX.read_data1,ID_EX.immediate_ext)) + errors[3]=1; + EX_DM.can_forward=0; EX_DM.ALU_result=temp; EX_DM.read_data2=ID_EX.read_data2; @@ -850,6 +1152,7 @@ int EX() } case 0x0F: ///lui { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.immediate_ext<<16; EX_DM.can_forward=1; @@ -859,6 +1162,7 @@ int EX() } case 0x0C: ///andi { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1&ID_EX.immediate_ext; EX_DM.can_forward=1; @@ -868,6 +1172,7 @@ int EX() } case 0x0D: ///ori { + EX_DM.instruction=ID_EX.instruction; temp=ID_EX.read_data1|ID_EX.immediate_ext; EX_DM.can_forward=1; @@ -877,6 +1182,7 @@ int EX() } case 0x0E: ///nori { + EX_DM.instruction=ID_EX.instruction; temp=~(ID_EX.read_data1|ID_EX.immediate_ext); EX_DM.can_forward=1; @@ -886,6 +1192,7 @@ int EX() } case 0x0A: ///slti { + EX_DM.instruction=ID_EX.instruction; if(ID_EX.read_data10) { @@ -2217,9 +2564,15 @@ int ID() int IF(int flags) { + + if(errors[0]==1)fprintf(error,"In cycle %d: Write $0 Error\n",count+1); + if(errors[1]==1)fprintf(error,"In cycle %d: Address Overflow\n",count+1); + if(errors[2]==1)fprintf(error,"In cycle %d: Misalignment Error\n",count+1); + if(errors[3]==1)fprintf(error,"In cycle %d: Number Overflow\n",count+1); unsigned char rt=0; unsigned char rd=0; unsigned char shamt=0; + unsigned char funct=0; int i=0; int j=0; @@ -2364,8 +2717,9 @@ int IF(int flags) shamt = cut_shamt(iim[i]); rt = cut_rt(iim[i]); rd = cut_rd(iim[i]); + funct = cut_func(iim[i]); - if(op==0&&shamt==0&&rt==0&&rd==0) + if(op==0&&shamt==0&&rt==0&&rd==0&&funct==0) IF_ID.instruction=0; if(op==0x3F) { diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index 39c706c..379e5e4 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -13,6 +13,8 @@ extern FILE *error; int stall; extern int count; +int errors[4]; + From 883f3b8a4190434c9dcf7ad2a48fbdb567befdd1 Mon Sep 17 00:00:00 2001 From: windstormer Date: Mon, 2 May 2016 17:00:41 +0800 Subject: [PATCH 18/32] testcase designed OK --- archiTA/simulator/pipeline | Bin pipeline/testcase/103062137.S | 41 ++++++++++++++++++++++++++++++++++ pipeline/testcase/dimage.bin | Bin 0 -> 16 bytes pipeline/testcase/iimage.bin | Bin 0 -> 100 bytes 4 files changed, 41 insertions(+) mode change 100644 => 100755 archiTA/simulator/pipeline create mode 100644 pipeline/testcase/103062137.S create mode 100644 pipeline/testcase/dimage.bin create mode 100644 pipeline/testcase/iimage.bin diff --git a/archiTA/simulator/pipeline b/archiTA/simulator/pipeline old mode 100644 new mode 100755 diff --git a/pipeline/testcase/103062137.S b/pipeline/testcase/103062137.S new file mode 100644 index 0000000..65e9a04 --- /dev/null +++ b/pipeline/testcase/103062137.S @@ -0,0 +1,41 @@ +addi $1, $0, 0x7FFF + +sll $1, $1, 16 + +ori $1, $1, 0xFFFF #$1 = 7FFFFFFF + +addi $2, $0, 2 #$2 = 2 + +add $3, $1, $2 #overflow + +addu $4, $1, $2 + +addi $5, $1, 0xF #overflow + +addiu $6, $1, 0xF + +bgtz $2, 3 # $2 = 1 > 0, so + +addi $7, $0, 0xFFFF #Line 10~12 should not be executed + +and $1, $1, $2 + +andi $2, $2, 0 + +bgtz $3, 1 #$3 = 0x10000000 < 0, so line 14 will be executed + +add $0, $0, $2 #write to register 0 error +lw $8 4($0) # Mem[0]: 0x7FFFFFFF +add $0 $0 $0 +lw $9, 1025($0) +addi $9, $8, 1 + +halt + +halt + +halt + +halt + +halt diff --git a/pipeline/testcase/dimage.bin b/pipeline/testcase/dimage.bin new file mode 100644 index 0000000000000000000000000000000000000000..383081e0d771ffe26ea02bc0bf0c10d1b74044e4 GIT binary patch literal 16 ScmZQzU||3PrvE@t55xc>HV1zI literal 0 HcmV?d00001 diff --git a/pipeline/testcase/iimage.bin b/pipeline/testcase/iimage.bin new file mode 100644 index 0000000000000000000000000000000000000000..2667d9221988db968140da09e8eac8281944a284 GIT binary patch literal 100 zcmZw9u?c`M7)0UwHDCgQr4}hJAzE8FfH;YpxIlJ3gSB7%c)(|-J%WumlEe-j@ Date: Mon, 2 May 2016 17:13:49 +0800 Subject: [PATCH 19/32] modified Makefile --- pipeline/simulator/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipeline/simulator/Makefile b/pipeline/simulator/Makefile index 19ae75a..16bc4d5 100644 --- a/pipeline/simulator/Makefile +++ b/pipeline/simulator/Makefile @@ -3,11 +3,11 @@ SRCS = ./*.c OBS = ./*.o -single_cycle: SRC +pipeline: SRC $(CC) -o $@ $(OBS) SRC: $(SRCS) $(CC) -c $(SRCS) clean: $(OBS) - rm $(OBS) single_cycle \ No newline at end of file + rm $(OBS) pipeline From 788f37c6129ba6df3ee1c7557af492310e218e4e Mon Sep 17 00:00:00 2001 From: windstormer Date: Mon, 2 May 2016 23:39:38 +0800 Subject: [PATCH 20/32] fixed bug, two hidden left --- pipeline/simulator/function.c | 2 +- pipeline/simulator/main.c | 1 + pipeline/simulator/state.c | 1074 +++++++++++++++++++-------------- 3 files changed, 610 insertions(+), 467 deletions(-) diff --git a/pipeline/simulator/function.c b/pipeline/simulator/function.c index b3067b8..6c73d46 100644 --- a/pipeline/simulator/function.c +++ b/pipeline/simulator/function.c @@ -220,7 +220,7 @@ op=(unsigned)instruction>>26; } case 0x28: ///nand { - out = "NAD"; + out = "NAND"; break; } case 0x2A: ///slt diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index 44258d6..cb59260 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -123,6 +123,7 @@ int main(void) } else check[4]=IF(1); + fprintf(snapshot,"\n"); if(check[0]==1 && check[1]==1 && check[2]==1 && check[3]==1 && check[4]==1) break; diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 0d2912f..7a3f22d 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -111,7 +111,7 @@ int WB() } case 0x21: ///addu { - if(DM_WB.write_reg==0) + if(DM_WB.write_reg==0) { errors[0]=1; reg[DM_WB.write_reg]=0; @@ -199,7 +199,7 @@ int WB() } case 0x00: ///sll { - if(DM_WB.write_reg==0) + if(DM_WB.write_reg==0) { errors[0]=1; reg[DM_WB.write_reg]=0; @@ -242,11 +242,11 @@ int WB() case 0x08: ///addi { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.ALU_result; break; @@ -254,22 +254,22 @@ int WB() case 0x09: ///addiu { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x23: ///lw { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.data; break; @@ -277,44 +277,44 @@ int WB() case 0x21: ///lh { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.data; break; } case 0x25: ///lhu { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.data; break; } case 0x20: ///lb { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.data; break; } case 0x24: ///lbu { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.data; break; } @@ -335,56 +335,58 @@ int WB() } case 0x0F: ///lui { + if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0C: ///andi { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0D: ///ori { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0E: ///nori { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } case 0x0A: ///slti { + if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg] = DM_WB.ALU_result; break; } @@ -411,11 +413,11 @@ int WB() case 0x03: ///jal { if(DM_WB.write_reg==0) - { - errors[0]=1; - reg[DM_WB.write_reg]=0; - } - else + { + errors[0]=1; + reg[DM_WB.write_reg]=0; + } + else reg[DM_WB.write_reg]=DM_WB.ALU_result; break; } @@ -745,7 +747,7 @@ int DM() case 0x0F: ///lui { DM_WB.instruction = EX_DM.instruction; - DM_WB.ALU_result = 0; + DM_WB.ALU_result = EX_DM.ALU_result; DM_WB.write_reg = EX_DM.write_reg; DM_WB.data = 0; break; @@ -835,7 +837,7 @@ int DM() else { if(flag==1)return 1; - else return 0; + else return 0; } } @@ -1154,6 +1156,7 @@ int EX() { EX_DM.instruction=ID_EX.instruction; + temp=ID_EX.immediate_ext<<16; EX_DM.can_forward=1; EX_DM.ALU_result=temp; @@ -1192,7 +1195,6 @@ int EX() } case 0x0A: ///slti { - EX_DM.instruction=ID_EX.instruction; if(ID_EX.read_data1>28; PCback = PCback<<28; - PCback = (unsigned)PC|address; + PCback = (unsigned)IF_ID.PC|address; break; } case 0x03: ///jal { ID_EX.instruction = IF_ID.instruction; address = cut_address(IF_ID.instruction); + branch=1; address=address<<2; + ID_EX.write_reg=31; + IF_ID.PC+=4; ID_EX.immediate_ext = IF_ID.PC; PCback = (unsigned) IF_ID.PC>>28; PCback = PCback<<28; - PCback = (unsigned)PC|address; + PCback = (unsigned)IF_ID.PC|address; break; } case 0x3F: ///halt @@ -2675,7 +2817,7 @@ int IF(int flags) } else { - fprintf(snapshot," fwd_EX-DM_rs_$%d fwd_EX-DM_rt_$%d",ID_EX.forward[1],ID_EX.forward[2]); + fprintf(snapshot," fwd_EX-DM_rs_$%d fwd_EX-DM_rt_$%d",ID_EX.forward[1],ID_EX.forward[1]); } } } @@ -2697,7 +2839,7 @@ int IF(int flags) } else { - fprintf(snapshot," fwd_EX-DM_rs_$%d fwd_EX-DM_rt_$%d",EX_DM.forward[1],EX_DM.forward[2]); + fprintf(snapshot," fwd_EX-DM_rs_$%d fwd_EX-DM_rt_$%d",EX_DM.forward[1],EX_DM.forward[1]); } } From 729c0a05eb4e8ceee793bca9525521073683e8f5 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 03:01:21 +0800 Subject: [PATCH 21/32] bub sort left --- pipeline/simulator/state.c | 167 ++++++++++++++++++++----------------- pipeline/simulator/state.h | 2 +- 2 files changed, 91 insertions(+), 78 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 7a3f22d..16e00b8 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -848,7 +848,6 @@ int EX() show_EXi = ID_EX.instruction; int temp=0; int flag=0; - EX_DM.stall = ID_EX.stall; EX_DM.forward[0] = ID_EX.forward[0]; EX_DM.forward[1] = ID_EX.forward[1]; EX_DM.forward[2] = ID_EX.forward[2]; @@ -1206,19 +1205,19 @@ int EX() } case 0x04: ///beq { - EX_DM.can_forward=0; + EX_DM.can_forward=2; EX_DM.instruction=ID_EX.instruction; break; } case 0x05: ///bne { - EX_DM.can_forward=0; + EX_DM.can_forward=2; EX_DM.instruction=ID_EX.instruction; break; } case 0x07: ///bgtz { - EX_DM.can_forward=0; + EX_DM.can_forward=2; EX_DM.instruction=ID_EX.instruction; break; } @@ -1248,6 +1247,8 @@ int EX() } + + if(flag==1) return 1; else return 0; @@ -1309,7 +1310,7 @@ int ID() ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1317,7 +1318,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1367,7 +1368,7 @@ int ID() ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1375,7 +1376,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1422,7 +1423,7 @@ int ID() ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1430,7 +1431,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1477,7 +1478,7 @@ int ID() ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1485,7 +1486,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1532,7 +1533,7 @@ int ID() ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1540,7 +1541,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1588,7 +1589,7 @@ int ID() ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1596,7 +1597,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1643,7 +1644,7 @@ int ID() ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1651,7 +1652,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1699,7 +1700,7 @@ int ID() ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1707,7 +1708,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1748,21 +1749,24 @@ int ID() } case 0x2A: ///slt { + rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); rd = cut_rd(IF_ID.instruction); + ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { + ID_EX.stall=1; ID_EX.instruction=0; break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1810,7 +1814,7 @@ int ID() ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1839,7 +1843,7 @@ int ID() ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1868,7 +1872,7 @@ int ID() ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1894,7 +1898,7 @@ int ID() rs = cut_rs(IF_ID.instruction); branch = 1; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1926,7 +1930,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1956,7 +1960,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -1986,7 +1990,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2016,7 +2020,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2046,7 +2050,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2076,7 +2080,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2106,7 +2110,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2136,7 +2140,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2144,7 +2148,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2191,7 +2195,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2199,7 +2203,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2246,7 +2250,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2254,7 +2258,7 @@ int ID() break; } if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rt==DM_WB.write_reg)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2314,7 +2318,7 @@ int ID() ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2344,7 +2348,7 @@ int ID() ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2374,7 +2378,7 @@ int ID() ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2404,7 +2408,7 @@ int ID() ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; if(EX_DM.write_reg!=DM_WB.write_reg) - if(((rs==DM_WB.write_reg)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2430,19 +2434,22 @@ int ID() case 0x04: ///beq { + immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); - if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) { + ID_EX.stall=1; ID_EX.instruction=0; break; } - if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&ID_EX.instruction!=0))&&rt!=0) { + ID_EX.stall=1; ID_EX.instruction=0; @@ -2466,8 +2473,10 @@ int ID() } else { + if(DM_WB.ALU_result==reg[rt]) { + branch = 1; PCback = IF_ID.PC + 4 + immediate*4; @@ -2486,9 +2495,11 @@ int ID() if(DM_WB.ALU_result==reg[rs]) { + branch = 1; PCback = IF_ID.PC + 4 + immediate*4; + } ID_EX.forward[0] = 2; ID_EX.forward[1] = rt; @@ -2528,14 +2539,14 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); - if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; break; } - if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2619,7 +2630,7 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); - if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2699,6 +2710,7 @@ int ID() } + if(flag==1) return 1; else return 0; @@ -2725,42 +2737,46 @@ int IF(int flags) tempPC = PC; change = 0; branch = 0; + stalls=0; } else { - if(EX_DM.stall==1) + if(stalls==1) { tempPC = tempPC; + stalls=0; } else { if(change==1) { - tempPC = changePC; - change = 0; + tempPC=changePC; + change=0; } else { - if(branch==1) - { - tempPC +=4; - branch=0; - change=1; - changePC = PCback; - } - else - { - tempPC+=4; - - } + tempPC+=4; } + } } //printf("\nflags = %d, bramch = %d, change = %d\n\n",flags,branch,change); + if(branch==1) + { + changePC = PCback; + + change=1; + } + + + if(ID_EX.stall==1) + { + stalls=1; + } if(tempPC>=PC_start) { @@ -2771,17 +2787,11 @@ int IF(int flags) } else { - if(change == 1) - { - i=(tempPC-PC_start)/4; - IF_ID.instruction = iim[i]; - } - else - { - i=(tempPC-PC_start)/4; - IF_ID.instruction=iim[i]; - IF_ID.PC=tempPC; - } + + i=(tempPC-PC_start)/4; + IF_ID.instruction=iim[i]; + IF_ID.PC=tempPC; + } @@ -2792,9 +2802,9 @@ int IF(int flags) } fprintf(snapshot,"PC: 0x%08X\n",tempPC); - if(change == 0&& ID_EX.stall==0) + if(branch == 0&& ID_EX.stall==0) fprintf(snapshot,"IF: 0x%08X",iim[i]); - else if(change==1&&ID_EX.stall==0) + else if(branch==1&&ID_EX.stall==0) fprintf(snapshot,"IF: 0x%08X to_be_flushed",iim[i]); else fprintf(snapshot,"IF: 0x%08X to_be_stalled",iim[i]); @@ -2853,8 +2863,11 @@ int IF(int flags) fprintf(snapshot,"WB: %s",name); fprintf(snapshot,"\n"); fprintf(snapshot,"\n"); - if(change == 1 ) + if(branch == 1 ) + { IF_ID.instruction = 0; ///flush + branch =0; + } op=(unsigned)iim[i]>>26; shamt = cut_shamt(iim[i]); rt = cut_rt(iim[i]); diff --git a/pipeline/simulator/state.h b/pipeline/simulator/state.h index 379e5e4..81c5095 100644 --- a/pipeline/simulator/state.h +++ b/pipeline/simulator/state.h @@ -17,7 +17,7 @@ int errors[4]; - +int stalls; int PCback,branch; int tempPC; int changePC; From 901e975a22a7e302ff87711a9a78d6d4072a35a3 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 04:00:35 +0800 Subject: [PATCH 22/32] pass all testcase --- pipeline/simulator/state.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 16e00b8..2793e09 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -1012,7 +1012,7 @@ int EX() case 0x08: ///jr { EX_DM.instruction=ID_EX.instruction; - EX_DM.can_forward=0; + EX_DM.can_forward=2; break; } @@ -1223,7 +1223,7 @@ int EX() } case 0x02: ///j { - EX_DM.can_forward=0; + EX_DM.can_forward=2; EX_DM.instruction=ID_EX.instruction; break; } @@ -2675,14 +2675,16 @@ int ID() } case 0x02: ///j { + ID_EX.instruction = IF_ID.instruction; address = cut_address(IF_ID.instruction); + branch=1; IF_ID.PC+=4; address=address<<2; PCback = (unsigned) IF_ID.PC>>28; PCback = PCback<<28; - PCback = (unsigned)IF_ID.PC|address; + PCback = (unsigned)PCback|address; break; } case 0x03: ///jal @@ -2696,7 +2698,7 @@ int ID() ID_EX.immediate_ext = IF_ID.PC; PCback = (unsigned) IF_ID.PC>>28; PCback = PCback<<28; - PCback = (unsigned)IF_ID.PC|address; + PCback = (unsigned)PCback|address; break; } case 0x3F: ///halt From 0c5bee3ae80b1ea959d4a45b727b11a187f3e787 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 16:41:49 +0800 Subject: [PATCH 23/32] fixed save mem ,EX_DM.write_reg=0 --- pipeline/simulator/state.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 2793e09..3cc97c6 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -1125,6 +1125,7 @@ int EX() EX_DM.can_forward=0; EX_DM.ALU_result=temp; EX_DM.read_data2=ID_EX.read_data2; + EX_DM.write_reg=0; break; } case 0x29: ///sh @@ -1137,6 +1138,7 @@ int EX() EX_DM.can_forward=0; EX_DM.ALU_result=temp; EX_DM.read_data2=ID_EX.read_data2; + EX_DM.write_reg=0; break; } case 0x28: ///sb @@ -1149,6 +1151,7 @@ int EX() EX_DM.can_forward=0; EX_DM.ALU_result=temp; EX_DM.read_data2=ID_EX.read_data2; + EX_DM.write_reg=0; break; } case 0x0F: ///lui From 52b919cc649a0f5b185460c11a1e216be56ab433 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 16:54:35 +0800 Subject: [PATCH 24/32] fixed while PC Date: Tue, 3 May 2016 17:19:47 +0800 Subject: [PATCH 25/32] condition fixed as EX_DM.write_reg==DM_WB.write_reg --- pipeline/simulator/state.c | 85 ++++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 41 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 84fe5cc..0ab491f 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -1312,7 +1312,7 @@ int ID() ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1320,7 +1320,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1370,7 +1370,7 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1378,7 +1378,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1425,7 +1425,7 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1433,7 +1433,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1480,7 +1480,7 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1488,7 +1488,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1535,7 +1535,7 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1543,7 +1543,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1591,7 +1591,7 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1599,7 +1599,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1646,7 +1646,7 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1654,7 +1654,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1702,7 +1702,7 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1710,7 +1710,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1759,7 +1759,7 @@ int ID() ID_EX.immediate_ext = 0; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { @@ -1768,7 +1768,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1815,8 +1815,7 @@ int ID() rd = cut_rd(IF_ID.instruction); ID_EX.immediate_ext = shamt; ID_EX.instruction = IF_ID.instruction; - - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1845,7 +1844,7 @@ int ID() ID_EX.immediate_ext = shamt; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1874,7 +1873,7 @@ int ID() ID_EX.immediate_ext = shamt; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -1900,7 +1899,7 @@ int ID() ID_EX.instruction = IF_ID.instruction; rs = cut_rs(IF_ID.instruction); branch = 1; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1932,7 +1931,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1962,7 +1961,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -1992,7 +1991,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2022,7 +2021,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2052,7 +2051,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2082,7 +2081,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2112,7 +2111,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2142,7 +2141,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2150,7 +2149,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -2197,7 +2196,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2205,7 +2204,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -2252,7 +2251,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2260,7 +2259,7 @@ int ID() break; } - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rt==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -2320,7 +2319,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2350,7 +2349,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2380,7 +2379,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = unsigned_immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2410,7 +2409,7 @@ int ID() rt = cut_rt(IF_ID.instruction); ID_EX.immediate_ext = immediate; ID_EX.instruction = IF_ID.instruction; - if(EX_DM.write_reg!=DM_WB.write_reg) + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2441,7 +2440,7 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); - + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) { @@ -2450,6 +2449,7 @@ int ID() break; } + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&ID_EX.instruction!=0))&&rt!=0) { @@ -2542,6 +2542,7 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2549,6 +2550,7 @@ int ID() break; } + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -2633,6 +2635,7 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); + if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; From ac7623846784d57cb3eeb9678cbe79926b76f952 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 17:25:33 +0800 Subject: [PATCH 26/32] remove TA files --- archiTA/simulator/pipeline | Bin 67340 -> 0 bytes .../testcase/open_testcase/error/dimage.bin | Bin 12 -> 0 bytes archiTA/testcase/open_testcase/error/error.S | 9 - .../open_testcase/error/error_dump.rpt | 4 - .../testcase/open_testcase/error/iimage.bin | Bin 44 -> 0 bytes .../testcase/open_testcase/error/snapshot.rpt | 246 ------ .../testcase/open_testcase/error_3/dimage.bin | Bin 12 -> 0 bytes .../testcase/open_testcase/error_3/error_3.S | 37 - .../open_testcase/error_3/error_dump.rpt | 3 - .../testcase/open_testcase/error_3/iimage.bin | Bin 84 -> 0 bytes .../open_testcase/error_3/snapshot.rpt | 779 ------------------ .../open_testcase/pipeline1/dimage.bin | Bin 12 -> 0 bytes .../open_testcase/pipeline1/error_dump.rpt | 0 .../open_testcase/pipeline1/iimage.bin | Bin 44 -> 0 bytes .../open_testcase/pipeline1/pipeline1.S | 9 - .../open_testcase/pipeline1/snapshot.rpt | 410 --------- .../open_testcase/pipeline2/dimage.bin | Bin 8 -> 0 bytes .../open_testcase/pipeline2/error_dump.rpt | 0 .../open_testcase/pipeline2/iimage.bin | Bin 40 -> 0 bytes .../open_testcase/pipeline2/pipeline2.S | 8 - .../open_testcase/pipeline2/snapshot.rpt | 410 --------- .../open_testcase/pipeline3/dimage.bin | Bin 8 -> 0 bytes .../open_testcase/pipeline3/error_dump.rpt | 0 .../open_testcase/pipeline3/iimage.bin | Bin 44 -> 0 bytes .../open_testcase/pipeline3/pipeline3.S | 9 - .../open_testcase/pipeline3/snapshot.rpt | 451 ---------- 26 files changed, 2375 deletions(-) delete mode 100755 archiTA/simulator/pipeline delete mode 100644 archiTA/testcase/open_testcase/error/dimage.bin delete mode 100644 archiTA/testcase/open_testcase/error/error.S delete mode 100644 archiTA/testcase/open_testcase/error/error_dump.rpt delete mode 100644 archiTA/testcase/open_testcase/error/iimage.bin delete mode 100644 archiTA/testcase/open_testcase/error/snapshot.rpt delete mode 100644 archiTA/testcase/open_testcase/error_3/dimage.bin delete mode 100644 archiTA/testcase/open_testcase/error_3/error_3.S delete mode 100644 archiTA/testcase/open_testcase/error_3/error_dump.rpt delete mode 100644 archiTA/testcase/open_testcase/error_3/iimage.bin delete mode 100644 archiTA/testcase/open_testcase/error_3/snapshot.rpt delete mode 100644 archiTA/testcase/open_testcase/pipeline1/dimage.bin delete mode 100644 archiTA/testcase/open_testcase/pipeline1/error_dump.rpt delete mode 100644 archiTA/testcase/open_testcase/pipeline1/iimage.bin delete mode 100644 archiTA/testcase/open_testcase/pipeline1/pipeline1.S delete mode 100644 archiTA/testcase/open_testcase/pipeline1/snapshot.rpt delete mode 100644 archiTA/testcase/open_testcase/pipeline2/dimage.bin delete mode 100644 archiTA/testcase/open_testcase/pipeline2/error_dump.rpt delete mode 100644 archiTA/testcase/open_testcase/pipeline2/iimage.bin delete mode 100644 archiTA/testcase/open_testcase/pipeline2/pipeline2.S delete mode 100644 archiTA/testcase/open_testcase/pipeline2/snapshot.rpt delete mode 100644 archiTA/testcase/open_testcase/pipeline3/dimage.bin delete mode 100644 archiTA/testcase/open_testcase/pipeline3/error_dump.rpt delete mode 100644 archiTA/testcase/open_testcase/pipeline3/iimage.bin delete mode 100644 archiTA/testcase/open_testcase/pipeline3/pipeline3.S delete mode 100644 archiTA/testcase/open_testcase/pipeline3/snapshot.rpt diff --git a/archiTA/simulator/pipeline b/archiTA/simulator/pipeline deleted file mode 100755 index f7aa1f2e923c5c8ac50f4b5157e41de9c40a9439..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 67340 zcmeFa2Yggz_BVd-v`omP2MD1J2#5+PfEWupKmrMbvJ?ed3Yip1+hhg;{?KSZiLrpX zF1k^`wXR~@Rk0Eji6|;oa7E23uoHtTtE^^MH1GF3<+e$p`@Z}BKEL<>_d@PD&uPy& z=PCEOW$wK)J8y=LFWbPG821e7ec*CEN$Hve#- znDFG;tO)31h=ikrpoCKISI{Frf9@711Q&?I1~T=KcEQ&nMn@#h#RwMEiX& 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$2, 0 - -bgtz $3, 1 #$3 = 0x10000000 < 0, so line 14 will be executed - -add $0, $0, $2 #write to register 0 error - -halt - -halt - -halt - -halt - -halt diff --git a/archiTA/testcase/open_testcase/error_3/error_dump.rpt b/archiTA/testcase/open_testcase/error_3/error_dump.rpt deleted file mode 100644 index 47341ef..0000000 --- a/archiTA/testcase/open_testcase/error_3/error_dump.rpt +++ /dev/null @@ -1,3 +0,0 @@ -In cycle 9: Number Overflow -In cycle 11: Number Overflow -In cycle 18: Write $0 Error diff --git a/archiTA/testcase/open_testcase/error_3/iimage.bin b/archiTA/testcase/open_testcase/error_3/iimage.bin deleted file mode 100644 index 46795c68958332326b27527384fe2af97aabff77..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 84 zcmZQz00UtK#`^yZj64h`ivRyBFflMOC`l+VC@Cl^s50=Ys4?)%I503Pu>b$hpv0kK S;KaZnlfb|TRHg7A3jhGesvU3u diff --git a/archiTA/testcase/open_testcase/error_3/snapshot.rpt b/archiTA/testcase/open_testcase/error_3/snapshot.rpt deleted file mode 100644 index 604d014..0000000 --- a/archiTA/testcase/open_testcase/error_3/snapshot.rpt +++ /dev/null @@ -1,779 +0,0 @@ -cycle 0 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000400 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000000 -IF: 0x20017FFF -ID: NOP -EX: NOP -DM: NOP -WB: NOP - - -cycle 1 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000400 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000004 -IF: 0x00010C00 -ID: ADDI -EX: NOP -DM: NOP -WB: NOP - - -cycle 2 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000400 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000008 -IF: 0x3421FFFF -ID: SLL -EX: ADDI -DM: NOP -WB: NOP - - -cycle 3 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000400 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x0000000C -IF: 0x20020002 -ID: ORI -EX: SLL fwd_EX-DM_rt_$1 -DM: ADDI -WB: NOP - - -cycle 4 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000400 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000010 -IF: 0x00221820 -ID: ADDI -EX: ORI fwd_EX-DM_rs_$1 -DM: SLL -WB: ADDI - - -cycle 5 -$00: 0x00000000 -$01: 0x00007FFF -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000400 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000014 -IF: 0x00222021 to_be_stalled -ID: ADD to_be_stalled -EX: ADDI -DM: ORI -WB: SLL - - -cycle 6 -$00: 0x00000000 -$01: 0x7FFF0000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000400 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000014 -IF: 0x00222021 to_be_stalled -ID: ADD to_be_stalled -EX: NOP -DM: ADDI -WB: ORI - - -cycle 7 -$00: 0x00000000 -$01: 0x7FFFFFFF -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 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dcmZQz00YjRBp|IKp(^0az{sG$q4FOK000h`73BZ` diff --git a/archiTA/testcase/open_testcase/pipeline1/pipeline1.S b/archiTA/testcase/open_testcase/pipeline1/pipeline1.S deleted file mode 100644 index 30b502b..0000000 --- a/archiTA/testcase/open_testcase/pipeline1/pipeline1.S +++ /dev/null @@ -1,9 +0,0 @@ - lw $2, 0($3) - or $3, $1, $4 - beq $2, $3, anyway - and $1, $1, $0 -anyway: halt - halt - halt - halt - halt \ No newline at end of file diff --git a/archiTA/testcase/open_testcase/pipeline1/snapshot.rpt b/archiTA/testcase/open_testcase/pipeline1/snapshot.rpt deleted file mode 100644 index c9216b4..0000000 --- a/archiTA/testcase/open_testcase/pipeline1/snapshot.rpt +++ /dev/null @@ -1,410 +0,0 @@ -cycle 0 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 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0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000014 -IF: 0xFFFFFFFF -ID: HALT -EX: AND -DM: BEQ -WB: NOP - - -cycle 7 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x12345678 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000018 -IF: 0xFFFFFFFF -ID: HALT -EX: HALT -DM: AND -WB: BEQ - - -cycle 8 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x12345678 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 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- - diff --git a/archiTA/testcase/open_testcase/pipeline2/dimage.bin b/archiTA/testcase/open_testcase/pipeline2/dimage.bin deleted file mode 100644 index 1b1cb4d44c57c2d7a5122870fa6ac3e62ff7e94e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8 KcmZQzfB*mh2mk>9 diff --git a/archiTA/testcase/open_testcase/pipeline2/error_dump.rpt b/archiTA/testcase/open_testcase/pipeline2/error_dump.rpt deleted file mode 100644 index e69de29..0000000 diff --git a/archiTA/testcase/open_testcase/pipeline2/iimage.bin b/archiTA/testcase/open_testcase/pipeline2/iimage.bin deleted file mode 100644 index 6493d236f136228c14551af1cb0aa2b052107a28..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 40 acmZQz00WL5X9fllWd=ru1p+Gnu>b%BxE0U< diff --git a/archiTA/testcase/open_testcase/pipeline2/pipeline2.S b/archiTA/testcase/open_testcase/pipeline2/pipeline2.S deleted file mode 100644 index d564346..0000000 --- a/archiTA/testcase/open_testcase/pipeline2/pipeline2.S +++ /dev/null @@ -1,8 +0,0 @@ - lw $3, 0($2) - bne $1, $3, anyway - and $2, $5, $0 -anyway: halt - halt - halt - halt - halt \ No newline at end of file diff --git a/archiTA/testcase/open_testcase/pipeline2/snapshot.rpt b/archiTA/testcase/open_testcase/pipeline2/snapshot.rpt deleted file mode 100644 index 72473ba..0000000 --- a/archiTA/testcase/open_testcase/pipeline2/snapshot.rpt +++ /dev/null @@ -1,410 +0,0 @@ -cycle 0 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000000 -IF: 0x8C430000 -ID: NOP -EX: NOP -DM: NOP -WB: NOP - - -cycle 1 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000004 -IF: 0x14230001 -ID: LW -EX: NOP -DM: NOP -WB: NOP - - -cycle 2 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000008 -IF: 0x00A01024 to_be_stalled -ID: BNE to_be_stalled -EX: LW -DM: NOP -WB: NOP - - -cycle 3 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000008 -IF: 0x00A01024 to_be_stalled -ID: BNE to_be_stalled -EX: NOP -DM: LW -WB: NOP - - -cycle 4 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000008 -IF: 0x00A01024 -ID: BNE -EX: NOP -DM: NOP -WB: LW - - -cycle 5 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x0000000C -IF: 0xFFFFFFFF -ID: AND -EX: BNE -DM: NOP -WB: NOP - - -cycle 6 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000010 -IF: 0xFFFFFFFF -ID: HALT -EX: AND -DM: BNE -WB: NOP - - -cycle 7 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000014 -IF: 0xFFFFFFFF -ID: HALT -EX: HALT -DM: AND -WB: BNE - - -cycle 8 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000018 -IF: 0xFFFFFFFF -ID: HALT -EX: HALT -DM: HALT -WB: AND - - -cycle 9 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x0000001C -IF: 0xFFFFFFFF -ID: HALT -EX: HALT -DM: HALT -WB: HALT - - diff --git a/archiTA/testcase/open_testcase/pipeline3/dimage.bin b/archiTA/testcase/open_testcase/pipeline3/dimage.bin deleted file mode 100644 index 1b1cb4d44c57c2d7a5122870fa6ac3e62ff7e94e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8 KcmZQzfB*mh2mk>9 diff --git a/archiTA/testcase/open_testcase/pipeline3/error_dump.rpt b/archiTA/testcase/open_testcase/pipeline3/error_dump.rpt deleted file mode 100644 index e69de29..0000000 diff --git a/archiTA/testcase/open_testcase/pipeline3/iimage.bin b/archiTA/testcase/open_testcase/pipeline3/iimage.bin deleted file mode 100644 index b22eda641bf4523fa4fdba984c88f6427c351d59..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 44 dcmZQz00Yh*XCR%zp~|p8K!uUhLhU~m001AQ7Lot} diff --git a/archiTA/testcase/open_testcase/pipeline3/pipeline3.S b/archiTA/testcase/open_testcase/pipeline3/pipeline3.S deleted file mode 100644 index 629cc21..0000000 --- a/archiTA/testcase/open_testcase/pipeline3/pipeline3.S +++ /dev/null @@ -1,9 +0,0 @@ - lw $3, 0($2) - or $1, $3, $4 - and $2, $5, $0 - xor $7, $8, $9 -halt -halt -halt -halt -halt \ No newline at end of file diff --git a/archiTA/testcase/open_testcase/pipeline3/snapshot.rpt b/archiTA/testcase/open_testcase/pipeline3/snapshot.rpt deleted file mode 100644 index bd464fe..0000000 --- a/archiTA/testcase/open_testcase/pipeline3/snapshot.rpt +++ /dev/null @@ -1,451 +0,0 @@ -cycle 0 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000000 -IF: 0x8C430000 -ID: NOP -EX: NOP -DM: NOP -WB: NOP - - -cycle 1 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000004 -IF: 0x00640825 -ID: LW -EX: NOP -DM: NOP -WB: NOP - - -cycle 2 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000008 -IF: 0x00A01024 to_be_stalled -ID: OR to_be_stalled -EX: LW -DM: NOP -WB: NOP - - -cycle 3 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000008 -IF: 0x00A01024 to_be_stalled -ID: OR to_be_stalled -EX: NOP -DM: LW -WB: NOP - - -cycle 4 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000008 -IF: 0x00A01024 -ID: OR -EX: NOP -DM: NOP -WB: LW - - -cycle 5 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x0000000C -IF: 0x01093826 -ID: AND -EX: OR -DM: NOP -WB: NOP - - -cycle 6 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000010 -IF: 0xFFFFFFFF -ID: XOR -EX: AND -DM: OR -WB: NOP - - -cycle 7 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000014 -IF: 0xFFFFFFFF -ID: HALT -EX: XOR -DM: AND -WB: OR - - -cycle 8 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000018 -IF: 0xFFFFFFFF -ID: HALT -EX: HALT -DM: XOR -WB: AND - - -cycle 9 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x0000001C -IF: 0xFFFFFFFF -ID: HALT -EX: HALT -DM: HALT -WB: XOR - - -cycle 10 -$00: 0x00000000 -$01: 0x00000000 -$02: 0x00000000 -$03: 0x00000000 -$04: 0x00000000 -$05: 0x00000000 -$06: 0x00000000 -$07: 0x00000000 -$08: 0x00000000 -$09: 0x00000000 -$10: 0x00000000 -$11: 0x00000000 -$12: 0x00000000 -$13: 0x00000000 -$14: 0x00000000 -$15: 0x00000000 -$16: 0x00000000 -$17: 0x00000000 -$18: 0x00000000 -$19: 0x00000000 -$20: 0x00000000 -$21: 0x00000000 -$22: 0x00000000 -$23: 0x00000000 -$24: 0x00000000 -$25: 0x00000000 -$26: 0x00000000 -$27: 0x00000000 -$28: 0x00000000 -$29: 0x00000000 -$30: 0x00000000 -$31: 0x00000000 -PC: 0x00000020 -IF: 0xFFFFFFFF -ID: HALT -EX: HALT -DM: HALT -WB: HALT - - From 90c230166540dc6d7626251870996787bd15f4cf Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 19:12:59 +0800 Subject: [PATCH 27/32] fixed while stall and IF is NOP --- pipeline/simulator/state.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 0ab491f..86fb682 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -444,6 +444,7 @@ int DM() int flags=0; if(EX_DM.instruction==0) { + DM_WB.instruction=EX_DM.instruction; DM_WB.ALU_result=0; DM_WB.can_forward=0; DM_WB.data=0; @@ -855,6 +856,7 @@ int EX() if(ID_EX.instruction==0) { + EX_DM.instruction=ID_EX.instruction; EX_DM.ALU_result==0; EX_DM.read_data2=0; EX_DM.write_reg=0; @@ -1285,6 +1287,7 @@ int ID() if(IF_ID.instruction==0) { + ID_EX.instruction=IF_ID.instruction; ID_EX.immediate_ext=0; ID_EX.read_data1=0; ID_EX.read_data2=0; @@ -2801,6 +2804,7 @@ int IF(int flags) IF_ID.PC=tempPC; } + fprintf(snapshot,"PC: 0x%08X\n",tempPC); if(branch == 0&& ID_EX.stall==0) fprintf(snapshot,"IF: 0x%08X",iim[i]); @@ -2812,14 +2816,16 @@ int IF(int flags) } else { - IF_ID.instruction=0; - fprintf(snapshot,"PC: 0x%08X\n",tempPC); + IF_ID.instruction=0; + + fprintf(snapshot,"PC: 0x%08X\n",tempPC); if(branch == 0&& ID_EX.stall==0) fprintf(snapshot,"IF: 0x00000000"); else if(branch==1&&ID_EX.stall==0) fprintf(snapshot,"IF: 0x%00000000 to_be_flushed"); else fprintf(snapshot,"IF: 0x%00000000 to_be_stalled"); + } @@ -2868,8 +2874,6 @@ int IF(int flags) } } - - fprintf(snapshot,"\n"); name = toname(show_DMi); fprintf(snapshot,"DM: %s",name); @@ -2889,7 +2893,7 @@ int IF(int flags) rd = cut_rd(iim[i]); funct = cut_func(iim[i]); - if(op==0&&shamt==0&&rt==0&&rd==0&&funct==0) + if(op==0&&shamt==0&&rt==0&&rd==0&&funct==0&&(ID_EX.stall!=1)) IF_ID.instruction=0; if(op==0x3F) { From d69a2b1164b3cbf738a0b00dacb737bbdc0ecce2 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 19:26:26 +0800 Subject: [PATCH 28/32] fixed when ID_EX.stall==1 & branch=1 error --- pipeline/simulator/main.c | 2 +- pipeline/simulator/state.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/pipeline/simulator/main.c b/pipeline/simulator/main.c index cb59260..a792508 100644 --- a/pipeline/simulator/main.c +++ b/pipeline/simulator/main.c @@ -100,7 +100,7 @@ int main(void) int j=0; while(1) { - // if(count>4)break; + // if(count>12)break; errors[0]=0; errors[1]=0; diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 86fb682..8717e36 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -2816,6 +2816,9 @@ int IF(int flags) } else { + if(ID_EX.stall==1) + IF_ID.instruction=IF_ID.instruction; + else IF_ID.instruction=0; fprintf(snapshot,"PC: 0x%08X\n",tempPC); @@ -2882,7 +2885,7 @@ int IF(int flags) fprintf(snapshot,"WB: %s",name); fprintf(snapshot,"\n"); fprintf(snapshot,"\n"); - if(branch == 1 ) + if(branch == 1 && ID_EX.stall!=1) { IF_ID.instruction = 0; ///flush branch =0; @@ -2895,6 +2898,7 @@ int IF(int flags) if(op==0&&shamt==0&&rt==0&&rd==0&&funct==0&&(ID_EX.stall!=1)) IF_ID.instruction=0; + if(op==0x3F) { return 1; From 8c34bf0e347271a0dd467efc2ef04951ca805c61 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 19:28:45 +0800 Subject: [PATCH 29/32] fixed output 0x%00000000 to 0x00000000 --- pipeline/simulator/state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 8717e36..51d9443 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -2825,9 +2825,9 @@ int IF(int flags) if(branch == 0&& ID_EX.stall==0) fprintf(snapshot,"IF: 0x00000000"); else if(branch==1&&ID_EX.stall==0) - fprintf(snapshot,"IF: 0x%00000000 to_be_flushed"); + fprintf(snapshot,"IF: 0x00000000 to_be_flushed"); else - fprintf(snapshot,"IF: 0x%00000000 to_be_stalled"); + fprintf(snapshot,"IF: 0x00000000 to_be_stalled"); } From e7b73ec46b0700447a24b3f6ee15d91bd3bfe392 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 21:20:07 +0800 Subject: [PATCH 30/32] change jr to EX_DM to ID --- pipeline/simulator/state.c | 48 +++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 51d9443..d1e15e7 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -442,6 +442,7 @@ int DM() unsigned char *getting; int flag=0; int flags=0; + DM_WB.can_forward = EX_DM.can_forward; if(EX_DM.instruction==0) { DM_WB.instruction=EX_DM.instruction; @@ -452,7 +453,7 @@ int DM() DM_WB.write_reg=0; return 0; } - DM_WB.can_forward = EX_DM.can_forward; + op=(unsigned)EX_DM.instruction>>26; @@ -1901,26 +1902,25 @@ int ID() { ID_EX.instruction = IF_ID.instruction; rs = cut_rs(IF_ID.instruction); - branch = 1; - if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) - if(((rs==DM_WB.write_reg&&DM_WB.can_forward!=2)||(rs==EX_DM.write_reg&&EX_DM.can_forward==0&&ID_EX.instruction!=0))&&rs!=0) - { - ID_EX.stall=1; - ID_EX.instruction=0; - - break; - } + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) + { + ID_EX.stall=1; + ID_EX.instruction=0; + break; + } - if(rs==EX_DM.write_reg && EX_DM.can_forward==1&&rs!=0) + if(rs == DM_WB.write_reg && DM_WB.can_forward==1&&rs!=0) { - PCback = EX_DM.ALU_result; + + PCback = DM_WB.ALU_result; ID_EX.forward[0] = 1; ID_EX.forward[1] = rs; - ID_EX.forward[2] = 0; + ID_EX.forward[2] = 1; } else PCback = reg[rs]; +branch = 1; break; } @@ -2443,7 +2443,8 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); - if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) + + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) { @@ -2452,7 +2453,7 @@ int ID() break; } - if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&ID_EX.instruction!=0))&&rt!=0) { @@ -2545,7 +2546,7 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); - if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2553,7 +2554,7 @@ int ID() break; } - if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -2562,8 +2563,7 @@ int ID() break; } - if(EX_DM.stall!=1) - { + if(rs==DM_WB.write_reg && DM_WB.can_forward==1&&rs!=0) { if(rt==DM_WB.write_reg && DM_WB.can_forward==1&&rt!=0) @@ -2621,7 +2621,7 @@ int ID() } } - } + @@ -2638,7 +2638,7 @@ int ID() immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); - if(!((EX_DM.write_reg==DM_WB.write_reg)&&(EX_DM.can_forward==1))) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2648,8 +2648,7 @@ int ID() } - if(EX_DM.stall!=1) - { + if(rs == DM_WB.write_reg && DM_WB.can_forward==1&&rs!=0) { if(DM_WB.ALU_result>0) @@ -2671,7 +2670,7 @@ int ID() } } - } + @@ -2843,6 +2842,7 @@ int IF(int flags) { if(ID_EX.forward[0]==1) { + fprintf(snapshot," fwd_EX-DM_rs_$%d",ID_EX.forward[1]); } else if(ID_EX.forward[0]==2) From 87a845576f83f886c453f0af67bc850982cf9592 Mon Sep 17 00:00:00 2001 From: windstormer Date: Tue, 3 May 2016 21:33:57 +0800 Subject: [PATCH 31/32] all testcases pass --- pipeline/simulator/state.c | 12 +- pipeline/testcase/error_dump.rpt | 7 + pipeline/testcase/snapshot.rpt | 820 +++++++++++++++++++++++++++++++ 3 files changed, 833 insertions(+), 6 deletions(-) create mode 100644 pipeline/testcase/error_dump.rpt create mode 100644 pipeline/testcase/snapshot.rpt diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index d1e15e7..18024c6 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -1902,7 +1902,7 @@ int ID() { ID_EX.instruction = IF_ID.instruction; rs = cut_rs(IF_ID.instruction); - if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward!=2&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2445,7 +2445,7 @@ branch = 1; rt = cut_rt(IF_ID.instruction); - if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward!=2&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; @@ -2454,7 +2454,7 @@ branch = 1; break; } - if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&ID_EX.instruction!=0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward!=2&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; @@ -2547,7 +2547,7 @@ branch = 1; rs = cut_rs(IF_ID.instruction); rt = cut_rt(IF_ID.instruction); - if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward!=2&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2555,7 +2555,7 @@ branch = 1; break; } - if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&ID_EX.instruction!=0))&&rt!=0) + if(((rt==DM_WB.write_reg&&DM_WB.can_forward==0)||(rt==EX_DM.write_reg&&EX_DM.can_forward!=2&&ID_EX.instruction!=0))&&rt!=0) { ID_EX.stall=1; ID_EX.instruction=0; @@ -2639,7 +2639,7 @@ branch = 1; immediate = cut_immediate(IF_ID.instruction); rs = cut_rs(IF_ID.instruction); - if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&ID_EX.instruction!=0))&&rs!=0) + if(((rs==DM_WB.write_reg&&DM_WB.can_forward==0)||(rs==EX_DM.write_reg&&EX_DM.can_forward!=2&&ID_EX.instruction!=0))&&rs!=0) { ID_EX.stall=1; ID_EX.instruction=0; diff --git a/pipeline/testcase/error_dump.rpt b/pipeline/testcase/error_dump.rpt new file mode 100644 index 0000000..b1f61a4 --- /dev/null +++ b/pipeline/testcase/error_dump.rpt @@ -0,0 +1,7 @@ +In cycle 9: Number Overflow +In cycle 11: Number Overflow +In cycle 18: Write $0 Error +In cycle 20: Write $0 Error +In cycle 20: Address Overflow +In cycle 20: Misalignment Error +In cycle 20: Number Overflow diff --git a/pipeline/testcase/snapshot.rpt b/pipeline/testcase/snapshot.rpt new file mode 100644 index 0000000..5e3c5b3 --- /dev/null +++ b/pipeline/testcase/snapshot.rpt @@ -0,0 +1,820 @@ +cycle 0 +$00: 0x00000000 +$01: 0x00000000 +$02: 0x00000000 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000000 +IF: 0x20017FFF +ID: NOP +EX: NOP +DM: NOP +WB: NOP + + +cycle 1 +$00: 0x00000000 +$01: 0x00000000 +$02: 0x00000000 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000004 +IF: 0x00010C00 +ID: ADDI +EX: NOP +DM: NOP +WB: NOP + + +cycle 2 +$00: 0x00000000 +$01: 0x00000000 +$02: 0x00000000 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000008 +IF: 0x3421FFFF +ID: SLL +EX: ADDI +DM: NOP +WB: NOP + + +cycle 3 +$00: 0x00000000 +$01: 0x00000000 +$02: 0x00000000 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x0000000C +IF: 0x20020002 +ID: ORI +EX: SLL fwd_EX-DM_rt_$1 +DM: ADDI +WB: NOP + + +cycle 4 +$00: 0x00000000 +$01: 0x00000000 +$02: 0x00000000 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000010 +IF: 0x00221820 +ID: ADDI +EX: ORI fwd_EX-DM_rs_$1 +DM: SLL +WB: ADDI + + +cycle 5 +$00: 0x00000000 +$01: 0x00007FFF +$02: 0x00000000 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000014 +IF: 0x00222021 to_be_stalled +ID: ADD to_be_stalled +EX: ADDI +DM: ORI +WB: SLL + + +cycle 6 +$00: 0x00000000 +$01: 0x7FFF0000 +$02: 0x00000000 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000014 +IF: 0x00222021 to_be_stalled +ID: ADD to_be_stalled +EX: NOP +DM: ADDI +WB: ORI + + +cycle 7 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000000 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000014 +IF: 0x00222021 +ID: ADD +EX: NOP +DM: NOP +WB: ADDI + + +cycle 8 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000018 +IF: 0x2025000F +ID: ADDU +EX: ADD +DM: NOP +WB: NOP + + +cycle 9 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x0000001C +IF: 0x2426FFFF +ID: ADDI +EX: ADDU +DM: ADD +WB: NOP + + +cycle 10 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x00000000 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000020 +IF: 0x1C400003 +ID: ADDIU +EX: ADDI +DM: ADDU +WB: ADD + + +cycle 11 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x80000001 +$04: 0x00000000 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000024 +IF: 0x2007FFFF to_be_flushed +ID: BGTZ +EX: ADDIU +DM: ADDI +WB: ADDU + + +cycle 12 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x80000001 +$04: 0x80000001 +$05: 0x00000000 +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000030 +IF: 0x1C600001 +ID: NOP +EX: BGTZ +DM: ADDIU +WB: ADDI + + +cycle 13 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x80000001 +$04: 0x80000001 +$05: 0x8000000E +$06: 0x00000000 +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000034 +IF: 0x00020020 +ID: BGTZ +EX: NOP +DM: BGTZ +WB: ADDIU + + +cycle 14 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x80000001 +$04: 0x80000001 +$05: 0x8000000E +$06: 0x7FFFFFFE +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000038 +IF: 0x8C080004 +ID: ADD +EX: BGTZ +DM: NOP +WB: BGTZ + + +cycle 15 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x80000001 +$04: 0x80000001 +$05: 0x8000000E +$06: 0x7FFFFFFE +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x0000003C +IF: 0x00000020 +ID: LW +EX: ADD +DM: BGTZ +WB: NOP + + +cycle 16 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x80000001 +$04: 0x80000001 +$05: 0x8000000E +$06: 0x7FFFFFFE +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000040 +IF: 0x8C090401 +ID: ADD +EX: LW +DM: ADD +WB: BGTZ + + +cycle 17 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x80000001 +$04: 0x80000001 +$05: 0x8000000E +$06: 0x7FFFFFFE +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000044 +IF: 0x21090001 +ID: LW +EX: ADD +DM: LW +WB: ADD + + +cycle 18 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x80000001 +$04: 0x80000001 +$05: 0x8000000E +$06: 0x7FFFFFFE +$07: 0x00000000 +$08: 0x00000000 +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x00000048 +IF: 0xFFFFFFFF +ID: ADDI +EX: LW +DM: ADD +WB: LW + + +cycle 19 +$00: 0x00000000 +$01: 0x7FFFFFFF +$02: 0x00000002 +$03: 0x80000001 +$04: 0x80000001 +$05: 0x8000000E +$06: 0x7FFFFFFE +$07: 0x00000000 +$08: 0x7FFFFFFF +$09: 0x00000000 +$10: 0x00000000 +$11: 0x00000000 +$12: 0x00000000 +$13: 0x00000000 +$14: 0x00000000 +$15: 0x00000000 +$16: 0x00000000 +$17: 0x00000000 +$18: 0x00000000 +$19: 0x00000000 +$20: 0x00000000 +$21: 0x00000000 +$22: 0x00000000 +$23: 0x00000000 +$24: 0x00000000 +$25: 0x00000000 +$26: 0x00000000 +$27: 0x00000000 +$28: 0x00000000 +$29: 0x00000400 +$30: 0x00000000 +$31: 0x00000000 +PC: 0x0000004C +IF: 0xFFFFFFFF +ID: HALT +EX: ADDI +DM: LW +WB: ADD + + From cc2d282673947a0d60182ec398b84f5c88f6018c Mon Sep 17 00:00:00 2001 From: windstormer Date: Thu, 5 May 2016 19:02:54 +0800 Subject: [PATCH 32/32] fixed bne when two forwarding condition --- pipeline/simulator/state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipeline/simulator/state.c b/pipeline/simulator/state.c index 18024c6..ef0c14a 100644 --- a/pipeline/simulator/state.c +++ b/pipeline/simulator/state.c @@ -2568,7 +2568,7 @@ branch = 1; { if(rt==DM_WB.write_reg && DM_WB.can_forward==1&&rt!=0) { - if(DM_WB.ALU_result!=reg[rs]) + if(DM_WB.ALU_result!=DM_WB.ALU_result) { branch = 1; PCback = IF_ID.PC + 4 + immediate*4;