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This repository was archived by the owner on May 19, 2026. It is now read-only.
Could we have some software documentation, such as registers provided and how to send and receive packets on how to interact with the core, for those of us not good at reading verilog.
Could we have some software documentation, such as registers provided and how to send and receive packets on how to interact with the core, for those of us not good at reading verilog.