I2C DV -- Host TX-RX test

[KinzaQamar]

Write SW that configure I2C IP in host mode and transmits / receive n bytes to a reactive UVM agent

[KinzaQamar]

• Created [chip, I2C, DV] Top level I2C host test #473
  • This adds a top level vseq that will start a device seq and a reactive agent
  • Works for multiple reads and writes
  • Requires cleanups in SW and DV
• Created [I2C, hal, SW] Restructured and refactored the functions #535
  • A dependency PR on [chip, I2C, DV] Top level I2C host test #473.
  • This is restructuring and refactor the current read / write functions
  • It requires to test examples/i2c.c on a board as [I2C, hal, SW] Restructured and refactored the functions #535 touches that file as well

[KinzaQamar]

Created #545 (related issue #546). This is a dependency on #535

[KinzaQamar]

• Issue [I2C, SW] Replace MMIO accesses with autogenerated HAL structs #546 --- Done
• [I2C, hal, SW] Restructured and refactored the functions #535 now opened for reveiw
  • Rebased and tested on genesys2

[KinzaQamar]

Make #473 agent adapt SW timing

[KinzaQamar]

Make #473 agent adapt SW timing

Done --- DV changes are reviewable now

[KinzaQamar]

• Looking into why OT's chip level vseq adds an extra cycle of delay in rise cycles and setupbit when CDC instrumentation
• host test fails in verilator -- asumption is that we can't do loop back test with I2C DPI