[rstmgr,dv] Reset Manager DV ported to mocha

hw/top_chip/data/rstmgr_cfg.hjson

@@ -48,7 +48,7 @@
     power_domains:
     [
       Aon
-      "0"
+      Main
     ]
     num_rstreqs: 1
     sw_rsts:
@@ -65,7 +65,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
           Aon
         ]
         shadowed: false
@@ -107,7 +107,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: false
@@ -121,7 +121,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: false
@@ -135,7 +135,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: true
@@ -149,7 +149,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: true
@@ -163,7 +163,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: true
@@ -208,7 +208,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: false
@@ -222,7 +222,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: false
@@ -236,7 +236,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: true
@@ -250,7 +250,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: true
@@ -264,7 +264,7 @@
         type: top
         domains:
         [
-          "0"
+          Main
         ]
         shadowed: false
         sw: true

hw/top_chip/dv/mocha_sim_cfgs.hjson

@@ -30,6 +30,7 @@
     "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/i2c_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/ip_autogen/gpio/dv/gpio_sim_cfg.hjson",
+    "{proj_root}/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson",
     "{proj_root}/hw/vendor/lowrisc_ip/ip/rom_ctrl/dv/rom_ctrl_32kB_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/tmp_sim_cfg/rv_dm_use_jtag_interface_sim_cfg.hjson",
 

hw/top_chip/ip_autogen/alert_handler/dv/README.md

@@ -107,11 +107,11 @@ The alert_handler scoreboard is parameterized to support different number of cla
 * Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
 
 ## Building and running tests
-We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions.
+The [dvsim](https://github.com/lowRISC/dvsim) tool is used for building and running our tests and regressions.
 Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
 Here's how to run a smoke test:
 ```console
-$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/$CHIP/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson -i alert_handler_smoke
+$ dvsim $REPO_TOP/hw/$CHIP/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson -i alert_handler_smoke
 ```
 In this run command, $CHIP can be top_earlgrey, etc.
 

hw/top_chip/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv

@@ -18,9 +18,9 @@ class alert_handler_env_cfg extends cip_base_env_cfg #(.RAL_T(alert_handler_reg_
 
   `uvm_object_new
 
-  virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+  virtual function void initialize();
     num_edn = 1;
-    super.initialize(csr_base_addr);
+    super.initialize();
     shadow_update_err_status_fields[ral.loc_alert_cause[LocalShadowRegUpdateErr].la] = 1;
     shadow_storage_err_status_fields[ral.loc_alert_cause[LocalShadowRegStorageErr].la] = 1;
 

hw/top_chip/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv

@@ -34,6 +34,7 @@ class alert_handler_entropy_stress_vseq extends alert_handler_smoke_vseq;
 
     foreach (cfg.alert_host_cfg[i]) begin
       cfg.alert_host_cfg[i].alert_delay_max = 0;
+      cfg.alert_host_cfg[i].ping_delay_min = 0;
       cfg.alert_host_cfg[i].ping_delay_max = 0;
     end
     super.pre_start();

hw/top_chip/ip_autogen/clkmgr/dv/README.md

@@ -167,12 +167,12 @@ The `jitter_en_o` output is checked to match the `jitter_enable` CSR.
 * Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
 
 ## Building and running tests
-We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions.
+The [dvsim](https://github.com/lowRISC/dvsim) tool is used for building and running our tests and regressions.
 Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
 Here's how to run a smoke test:
 
 ```console
-$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_mocha/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson -i clkmgr_smoke
+$ dvsim $REPO_TOP/hw/top_mocha/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson -i clkmgr_smoke
 ```
 
 ## Testplan

hw/top_chip/ip_autogen/clkmgr/dv/env/clkmgr_env_cfg.sv

@@ -26,9 +26,9 @@ class clkmgr_env_cfg extends cip_base_env_cfg #(
 
   `uvm_object_new
 
-  virtual function void initialize(bit [31:0] csr_base_addr = '1);
+  virtual function void initialize();
     list_of_alerts = clkmgr_env_pkg::LIST_OF_ALERTS;
-    super.initialize(csr_base_addr);
+    super.initialize();
 
     // This is for the integrity error test.
     tl_intg_alert_name = "fatal_fault";

hw/top_chip/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv

@@ -11,16 +11,16 @@ class clkmgr_regwen_vseq extends clkmgr_base_vseq;
 
   task check_jitter_regwen();
     bit enable;
-    mubi4_t prev_value;
-    mubi4_t new_value;
+    logic [3:0] prev_value_bits;
+    mubi4_t     new_value;
 
     `DV_CHECK_STD_RANDOMIZE_FATAL(enable)
     new_value = get_rand_mubi4_val(.t_weight(1), .f_weight(1), .other_weight(2));
     `uvm_info(`gfn, $sformatf("Check jitter_regwen = %b", enable), UVM_MEDIUM)
     csr_wr(.ptr(ral.jitter_regwen), .value(enable));
-    csr_rd(.ptr(ral.jitter_enable), .value(prev_value));
+    csr_rd(.ptr(ral.jitter_enable), .value(prev_value_bits));
     csr_wr(.ptr(ral.jitter_enable), .value(new_value));
-    csr_rd_check(.ptr(ral. jitter_enable), .compare_value(enable ? new_value : prev_value));
+    csr_rd_check(.ptr(ral.jitter_enable), .compare_value(enable ? new_value : prev_value_bits));
     `uvm_info(`gfn, "Check jitter_regwen done", UVM_MEDIUM)
   endtask : check_jitter_regwen
 

hw/top_chip/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv

@@ -609,6 +609,18 @@ module clkmgr_reg_top (
   //   F[hi]: 8:0
   logic async_io_meas_ctrl_shadowed_hi_err_update;
   logic async_io_meas_ctrl_shadowed_hi_err_storage;
+  logic deglitched_io_meas_ctrl_shadowed_hi_err_storage;
+
+  // flop storage error to filter combinational glitches before sending it across CDC
+  prim_flop #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_io_meas_ctrl_shadowed_hi_err_storage_deglitch (
+    .clk_i (clk_io_i),
+    .rst_ni(rst_io_ni),
+    .d_i   (async_io_meas_ctrl_shadowed_hi_err_storage),
+    .q_o   (deglitched_io_meas_ctrl_shadowed_hi_err_storage)
+  );
 
   // storage error is persistent and can be sampled at any time
   prim_flop_2sync #(
@@ -617,7 +629,7 @@ module clkmgr_reg_top (
   ) u_io_meas_ctrl_shadowed_hi_err_storage_sync (
     .clk_i,
     .rst_ni,
-    .d_i(async_io_meas_ctrl_shadowed_hi_err_storage),
+    .d_i(deglitched_io_meas_ctrl_shadowed_hi_err_storage),
     .q_o(io_meas_ctrl_shadowed_hi_storage_err)
   );
 
@@ -668,6 +680,18 @@ module clkmgr_reg_top (
   //   F[lo]: 17:9
   logic async_io_meas_ctrl_shadowed_lo_err_update;
   logic async_io_meas_ctrl_shadowed_lo_err_storage;
+  logic deglitched_io_meas_ctrl_shadowed_lo_err_storage;
+
+  // flop storage error to filter combinational glitches before sending it across CDC
+  prim_flop #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_io_meas_ctrl_shadowed_lo_err_storage_deglitch (
+    .clk_i (clk_io_i),
+    .rst_ni(rst_io_ni),
+    .d_i   (async_io_meas_ctrl_shadowed_lo_err_storage),
+    .q_o   (deglitched_io_meas_ctrl_shadowed_lo_err_storage)
+  );
 
   // storage error is persistent and can be sampled at any time
   prim_flop_2sync #(
@@ -676,7 +700,7 @@ module clkmgr_reg_top (
   ) u_io_meas_ctrl_shadowed_lo_err_storage_sync (
     .clk_i,
     .rst_ni,
-    .d_i(async_io_meas_ctrl_shadowed_lo_err_storage),
+    .d_i(deglitched_io_meas_ctrl_shadowed_lo_err_storage),
     .q_o(io_meas_ctrl_shadowed_lo_storage_err)
   );
 
@@ -767,6 +791,18 @@ module clkmgr_reg_top (
   //   F[hi]: 8:0
   logic async_main_meas_ctrl_shadowed_hi_err_update;
   logic async_main_meas_ctrl_shadowed_hi_err_storage;
+  logic deglitched_main_meas_ctrl_shadowed_hi_err_storage;
+
+  // flop storage error to filter combinational glitches before sending it across CDC
+  prim_flop #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_main_meas_ctrl_shadowed_hi_err_storage_deglitch (
+    .clk_i (clk_main_i),
+    .rst_ni(rst_main_ni),
+    .d_i   (async_main_meas_ctrl_shadowed_hi_err_storage),
+    .q_o   (deglitched_main_meas_ctrl_shadowed_hi_err_storage)
+  );
 
   // storage error is persistent and can be sampled at any time
   prim_flop_2sync #(
@@ -775,7 +811,7 @@ module clkmgr_reg_top (
   ) u_main_meas_ctrl_shadowed_hi_err_storage_sync (
     .clk_i,
     .rst_ni,
-    .d_i(async_main_meas_ctrl_shadowed_hi_err_storage),
+    .d_i(deglitched_main_meas_ctrl_shadowed_hi_err_storage),
     .q_o(main_meas_ctrl_shadowed_hi_storage_err)
   );
 
@@ -826,6 +862,18 @@ module clkmgr_reg_top (
   //   F[lo]: 17:9
   logic async_main_meas_ctrl_shadowed_lo_err_update;
   logic async_main_meas_ctrl_shadowed_lo_err_storage;
+  logic deglitched_main_meas_ctrl_shadowed_lo_err_storage;
+
+  // flop storage error to filter combinational glitches before sending it across CDC
+  prim_flop #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_main_meas_ctrl_shadowed_lo_err_storage_deglitch (
+    .clk_i (clk_main_i),
+    .rst_ni(rst_main_ni),
+    .d_i   (async_main_meas_ctrl_shadowed_lo_err_storage),
+    .q_o   (deglitched_main_meas_ctrl_shadowed_lo_err_storage)
+  );
 
   // storage error is persistent and can be sampled at any time
   prim_flop_2sync #(
@@ -834,7 +882,7 @@ module clkmgr_reg_top (
   ) u_main_meas_ctrl_shadowed_lo_err_storage_sync (
     .clk_i,
     .rst_ni,
-    .d_i(async_main_meas_ctrl_shadowed_lo_err_storage),
+    .d_i(deglitched_main_meas_ctrl_shadowed_lo_err_storage),
     .q_o(main_meas_ctrl_shadowed_lo_storage_err)
   );
 

hw/top_chip/ip_autogen/gpio/dv/README.md

@@ -103,11 +103,11 @@ Any CSR read transaction would check actual read data against predicted value.
 * `CioGpioOKnown`: Checks that GPIO output enable does not have any unknowns
 
 ## Building and running tests
-We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions.
+The [dvsim](https://github.com/lowRISC/dvsim) tool is used for building and running our tests and regressions.
 Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
 Here's how to run a smoke test:
 ```console
-$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_mocha/ip_autogen/gpio/dv/gpio_sim_cfg.hjson -i gpio_smoke
+$ dvsim $REPO_TOP/hw/top_mocha/ip_autogen/gpio/dv/gpio_sim_cfg.hjson -i gpio_smoke
 ```
 
 ## Testplan

hw/top_chip/ip_autogen/gpio/dv/env/gpio_env_cfg.sv

@@ -24,9 +24,9 @@ class gpio_env_cfg extends cip_base_env_cfg #(
     super.new(name);
   endfunction
 
-  virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+  virtual function void initialize();
     list_of_alerts = gpio_env_pkg::LIST_OF_ALERTS;
-    super.initialize(csr_base_addr);
+    super.initialize();
     // set num_interrupts & num_alerts which will be used to create coverage and more
     num_interrupts = ral.intr_state.get_n_used_bits();
 

hw/top_chip/ip_autogen/pwrmgr/dv/README.md

@@ -242,11 +242,11 @@ The [`hw/top_mocha/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv`](https://github.com/
 In addition, the RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
 
 ## Building and running tests
-We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions.
+The [dvsim](https://github.com/lowRISC/dvsim) tool is used for building and running our tests and regressions.
 Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
 Here's how to run a smoke test:
 ```console
-$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_mocha/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_smoke
+$ dvsim $REPO_TOP/hw/top_mocha/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_smoke
 ```
 
 ## Testplan

hw/top_chip/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cfg.sv

@@ -31,9 +31,9 @@ class pwrmgr_env_cfg extends cip_base_env_cfg #(
   // The run_phase object, to deal with objections.
   uvm_phase run_phase;
 
-  virtual function void initialize(bit [31:0] csr_base_addr = '1);
+  virtual function void initialize();
     list_of_alerts = pwrmgr_env_pkg::LIST_OF_ALERTS;
-    super.initialize(csr_base_addr);
+    super.initialize();
     num_interrupts = ral.intr_state.get_n_used_bits();
     `ASSERT_I(NumInstrMatch_A, num_interrupts == NUM_INTERRUPTS)
     `uvm_info(`gfn, $sformatf("num_interrupts = %0d", num_interrupts), UVM_MEDIUM)

hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv

@@ -42,7 +42,6 @@ class pwrmgr_reset_invalid_vseq extends pwrmgr_base_vseq;
 
     wait_for_rom_and_active();
     check_reset_status('0);
-    $assertoff(0, "tb.dut.u_cdc.u_clr_reqack.SyncReqAckHoldReq");
 
     for (int i = 0; i < num_of_target_states; ++i) begin
       `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM)