[pwrmgr, dv] Power manager vendoring

hw/top_chip/dv/mocha_sim_cfgs.hjson

@@ -30,6 +30,7 @@
     "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/i2c_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/ip_autogen/gpio/dv/gpio_sim_cfg.hjson",
+    "{proj_root}/hw/top_chip/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson",
     "{proj_root}/hw/vendor/lowrisc_ip/ip/rom_ctrl/dv/rom_ctrl_32kB_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/tmp_sim_cfg/rv_dm_use_jtag_interface_sim_cfg.hjson",
 

hw/top_chip/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv

@@ -18,9 +18,9 @@ class alert_handler_env_cfg extends cip_base_env_cfg #(.RAL_T(alert_handler_reg_
 
   `uvm_object_new
 
-  virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+  virtual function void initialize();
     num_edn = 1;
-    super.initialize(csr_base_addr);
+    super.initialize();
     shadow_update_err_status_fields[ral.loc_alert_cause[LocalShadowRegUpdateErr].la] = 1;
     shadow_storage_err_status_fields[ral.loc_alert_cause[LocalShadowRegStorageErr].la] = 1;
 

hw/top_chip/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv

@@ -34,6 +34,7 @@ class alert_handler_entropy_stress_vseq extends alert_handler_smoke_vseq;
 
     foreach (cfg.alert_host_cfg[i]) begin
       cfg.alert_host_cfg[i].alert_delay_max = 0;
+      cfg.alert_host_cfg[i].ping_delay_min = 0;
       cfg.alert_host_cfg[i].ping_delay_max = 0;
     end
     super.pre_start();

hw/top_chip/ip_autogen/clkmgr/dv/env/clkmgr_env_cfg.sv

@@ -26,9 +26,9 @@ class clkmgr_env_cfg extends cip_base_env_cfg #(
 
   `uvm_object_new
 
-  virtual function void initialize(bit [31:0] csr_base_addr = '1);
+  virtual function void initialize();
     list_of_alerts = clkmgr_env_pkg::LIST_OF_ALERTS;
-    super.initialize(csr_base_addr);
+    super.initialize();
 
     // This is for the integrity error test.
     tl_intg_alert_name = "fatal_fault";

hw/top_chip/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv

@@ -11,16 +11,16 @@ class clkmgr_regwen_vseq extends clkmgr_base_vseq;
 
   task check_jitter_regwen();
     bit enable;
-    mubi4_t prev_value;
-    mubi4_t new_value;
+    logic [3:0] prev_value_bits;
+    mubi4_t     new_value;
 
     `DV_CHECK_STD_RANDOMIZE_FATAL(enable)
     new_value = get_rand_mubi4_val(.t_weight(1), .f_weight(1), .other_weight(2));
     `uvm_info(`gfn, $sformatf("Check jitter_regwen = %b", enable), UVM_MEDIUM)
     csr_wr(.ptr(ral.jitter_regwen), .value(enable));
-    csr_rd(.ptr(ral.jitter_enable), .value(prev_value));
+    csr_rd(.ptr(ral.jitter_enable), .value(prev_value_bits));
     csr_wr(.ptr(ral.jitter_enable), .value(new_value));
-    csr_rd_check(.ptr(ral. jitter_enable), .compare_value(enable ? new_value : prev_value));
+    csr_rd_check(.ptr(ral.jitter_enable), .compare_value(enable ? new_value : prev_value_bits));
     `uvm_info(`gfn, "Check jitter_regwen done", UVM_MEDIUM)
   endtask : check_jitter_regwen
 

hw/top_chip/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv

@@ -609,6 +609,18 @@ module clkmgr_reg_top (
   //   F[hi]: 8:0
   logic async_io_meas_ctrl_shadowed_hi_err_update;
   logic async_io_meas_ctrl_shadowed_hi_err_storage;
+  logic deglitched_io_meas_ctrl_shadowed_hi_err_storage;
+
+  // flop storage error to filter combinational glitches before sending it across CDC
+  prim_flop #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_io_meas_ctrl_shadowed_hi_err_storage_deglitch (
+    .clk_i (clk_io_i),
+    .rst_ni(rst_io_ni),
+    .d_i   (async_io_meas_ctrl_shadowed_hi_err_storage),
+    .q_o   (deglitched_io_meas_ctrl_shadowed_hi_err_storage)
+  );
 
   // storage error is persistent and can be sampled at any time
   prim_flop_2sync #(
@@ -617,7 +629,7 @@ module clkmgr_reg_top (
   ) u_io_meas_ctrl_shadowed_hi_err_storage_sync (
     .clk_i,
     .rst_ni,
-    .d_i(async_io_meas_ctrl_shadowed_hi_err_storage),
+    .d_i(deglitched_io_meas_ctrl_shadowed_hi_err_storage),
     .q_o(io_meas_ctrl_shadowed_hi_storage_err)
   );
 
@@ -668,6 +680,18 @@ module clkmgr_reg_top (
   //   F[lo]: 17:9
   logic async_io_meas_ctrl_shadowed_lo_err_update;
   logic async_io_meas_ctrl_shadowed_lo_err_storage;
+  logic deglitched_io_meas_ctrl_shadowed_lo_err_storage;
+
+  // flop storage error to filter combinational glitches before sending it across CDC
+  prim_flop #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_io_meas_ctrl_shadowed_lo_err_storage_deglitch (
+    .clk_i (clk_io_i),
+    .rst_ni(rst_io_ni),
+    .d_i   (async_io_meas_ctrl_shadowed_lo_err_storage),
+    .q_o   (deglitched_io_meas_ctrl_shadowed_lo_err_storage)
+  );
 
   // storage error is persistent and can be sampled at any time
   prim_flop_2sync #(
@@ -676,7 +700,7 @@ module clkmgr_reg_top (
   ) u_io_meas_ctrl_shadowed_lo_err_storage_sync (
     .clk_i,
     .rst_ni,
-    .d_i(async_io_meas_ctrl_shadowed_lo_err_storage),
+    .d_i(deglitched_io_meas_ctrl_shadowed_lo_err_storage),
     .q_o(io_meas_ctrl_shadowed_lo_storage_err)
   );
 
@@ -767,6 +791,18 @@ module clkmgr_reg_top (
   //   F[hi]: 8:0
   logic async_main_meas_ctrl_shadowed_hi_err_update;
   logic async_main_meas_ctrl_shadowed_hi_err_storage;
+  logic deglitched_main_meas_ctrl_shadowed_hi_err_storage;
+
+  // flop storage error to filter combinational glitches before sending it across CDC
+  prim_flop #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_main_meas_ctrl_shadowed_hi_err_storage_deglitch (
+    .clk_i (clk_main_i),
+    .rst_ni(rst_main_ni),
+    .d_i   (async_main_meas_ctrl_shadowed_hi_err_storage),
+    .q_o   (deglitched_main_meas_ctrl_shadowed_hi_err_storage)
+  );
 
   // storage error is persistent and can be sampled at any time
   prim_flop_2sync #(
@@ -775,7 +811,7 @@ module clkmgr_reg_top (
   ) u_main_meas_ctrl_shadowed_hi_err_storage_sync (
     .clk_i,
     .rst_ni,
-    .d_i(async_main_meas_ctrl_shadowed_hi_err_storage),
+    .d_i(deglitched_main_meas_ctrl_shadowed_hi_err_storage),
     .q_o(main_meas_ctrl_shadowed_hi_storage_err)
   );
 
@@ -826,6 +862,18 @@ module clkmgr_reg_top (
   //   F[lo]: 17:9
   logic async_main_meas_ctrl_shadowed_lo_err_update;
   logic async_main_meas_ctrl_shadowed_lo_err_storage;
+  logic deglitched_main_meas_ctrl_shadowed_lo_err_storage;
+
+  // flop storage error to filter combinational glitches before sending it across CDC
+  prim_flop #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_main_meas_ctrl_shadowed_lo_err_storage_deglitch (
+    .clk_i (clk_main_i),
+    .rst_ni(rst_main_ni),
+    .d_i   (async_main_meas_ctrl_shadowed_lo_err_storage),
+    .q_o   (deglitched_main_meas_ctrl_shadowed_lo_err_storage)
+  );
 
   // storage error is persistent and can be sampled at any time
   prim_flop_2sync #(
@@ -834,7 +882,7 @@ module clkmgr_reg_top (
   ) u_main_meas_ctrl_shadowed_lo_err_storage_sync (
     .clk_i,
     .rst_ni,
-    .d_i(async_main_meas_ctrl_shadowed_lo_err_storage),
+    .d_i(deglitched_main_meas_ctrl_shadowed_lo_err_storage),
     .q_o(main_meas_ctrl_shadowed_lo_storage_err)
   );
 

hw/top_chip/ip_autogen/gpio/dv/env/gpio_env_cfg.sv

@@ -24,9 +24,9 @@ class gpio_env_cfg extends cip_base_env_cfg #(
     super.new(name);
   endfunction
 
-  virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+  virtual function void initialize();
     list_of_alerts = gpio_env_pkg::LIST_OF_ALERTS;
-    super.initialize(csr_base_addr);
+    super.initialize();
     // set num_interrupts & num_alerts which will be used to create coverage and more
     num_interrupts = ral.intr_state.get_n_used_bits();
 

hw/top_chip/ip_autogen/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson

@@ -68,7 +68,7 @@
               tb.dut.rom_ctrl_i
             '''
       stage: V2S
-      tests: ["pwrmgr_wakeup_reset", "pwrmgr_repeat_wakeup_reset"]
+      tests: ["pwrmgr_wakeup_reset"]
     }
     {
       name: sec_cm_rstmgr_intersig_mubi

hw/top_chip/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson

@@ -3,12 +3,12 @@
 // SPDX-License-Identifier: Apache-2.0
 {
   name: "pwrmgr"
-  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
+  import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
                      "pwrmgr_sec_cm_testplan.hjson"]
   testpoints: [
     {

hw/top_chip/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cfg.sv

@@ -31,9 +31,9 @@ class pwrmgr_env_cfg extends cip_base_env_cfg #(
   // The run_phase object, to deal with objections.
   uvm_phase run_phase;
 
-  virtual function void initialize(bit [31:0] csr_base_addr = '1);
+  virtual function void initialize();
     list_of_alerts = pwrmgr_env_pkg::LIST_OF_ALERTS;
-    super.initialize(csr_base_addr);
+    super.initialize();
     num_interrupts = ral.intr_state.get_n_used_bits();
     `ASSERT_I(NumInstrMatch_A, num_interrupts == NUM_INTERRUPTS)
     `uvm_info(`gfn, $sformatf("num_interrupts = %0d", num_interrupts), UVM_MEDIUM)

hw/top_chip/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv

@@ -87,12 +87,8 @@ interface pwrmgr_if (
   always_comb lowpwr_cfg_wen = `PATH_TO_DUT.lowpwr_cfg_wen;
 
   // reset status
-  always_comb
-    reset_status = {
-      `PATH_TO_DUT.u_reg.reset_status_val_1_qs, `PATH_TO_DUT.u_reg.reset_status_val_0_qs
-    };
-  always_comb
-    reset_en_q = {`PATH_TO_DUT.u_reg.reset_en_en_1_qs, `PATH_TO_DUT.u_reg.reset_en_en_0_qs};
+  always_comb reset_status = `PATH_TO_DUT.u_reg.reset_status_qs;
+  always_comb reset_en_q = `PATH_TO_DUT.u_reg.reset_en_qs;
   always_comb
     wakeup_en = {
       `PATH_TO_DUT.reg2hw.wakeup_en[5].q,

hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv

@@ -30,7 +30,7 @@ class pwrmgr_glitch_vseq extends pwrmgr_base_vseq;
       cfg.clk_rst_vif.wait_clks(cycles_before_reset);
 
       `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep &&
-                        cfg.pwrmgr_vif.pwr_rst_req.rstreqs[2] == 1);, $sformatf(
+                        cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx] == 1);, $sformatf(
                    "checker timeout : fast_state %s, pwr_rst_req 0x%x",
                    cfg.pwrmgr_vif.fast_state.name,
                    cfg.pwrmgr_vif.pwr_rst_req.rstreqs

hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv

@@ -37,7 +37,7 @@ class pwrmgr_global_esc_vseq extends pwrmgr_base_vseq;
     while (trans_cnt < num_trans) begin
       @(cfg.clk_rst_vif.cb);
       wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive &&
-           cfg.pwrmgr_vif.pwr_rst_req.rstreqs[3] == 1'b1);
+           cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx] == 1'b1);
       trans_cnt++;
 
       // Make sure previous dut_init is done

hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv

@@ -42,7 +42,6 @@ class pwrmgr_reset_invalid_vseq extends pwrmgr_base_vseq;
 
     wait_for_rom_and_active();
     check_reset_status('0);
-    $assertoff(0, "tb.dut.u_cdc.u_clr_reqack.SyncReqAckHoldReq");
 
     for (int i = 0; i < num_of_target_states; ++i) begin
       `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM)

hw/top_chip/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson

@@ -12,7 +12,7 @@
   tb: tb
 
   // Simulator used to sign off this block
-  tool: vcs
+  tool: xcelium
 
   // Fusesoc core file used for building the file list.
   fusesoc_core: lowrisc:mocha_dv:pwrmgr_sim:0.1
@@ -22,13 +22,13 @@
 
   // Import additional common sim cfg files.
   import_cfgs: [// Project wide common sim cfg file
-                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
                 // Common CIP test lists
-                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson"]
 
   // Exclusion files
   vcs_cov_excl_files: ["{self_dir}/cov/pwrmgr_cov_manual_excl.el"]

hw/top_chip/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv

@@ -57,8 +57,8 @@ module pwrmgr_bind;
     .io_clk_en(pwr_clk_o.io_ip_clk_en),
     .pwr_rst_o,
     .esc_timeout(esc_timeout_lc_q),
-    .slow_esc_rst_req(slow_peri_reqs.rstreqs[3]),
-    .slow_mp_rst_req(slow_peri_reqs.rstreqs[2]),
+    .slow_esc_rst_req(slow_peri_reqs.rstreqs[pwrmgr_reg_pkg::ResetEscIdx]),
+    .slow_mp_rst_req(slow_peri_reqs.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]),
     .slow_fsm_invalid,
     .fast_fsm_invalid(u_fsm.u_state_regs.unused_err_o),
     .rom_intg_chk_dis(u_fsm.rom_intg_chk_dis),

hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_env_cfg.sv

@@ -23,9 +23,9 @@ class rstmgr_env_cfg extends cip_base_env_cfg #(
   virtual rstmgr_cascading_sva_if rstmgr_cascading_sva_vif;
   virtual rstmgr_if rstmgr_vif;
 
-  virtual function void initialize(bit [31:0] csr_base_addr = '1);
+  virtual function void initialize();
     list_of_alerts = rstmgr_env_pkg::LIST_OF_ALERTS;
-    super.initialize(csr_base_addr);
+    super.initialize();
 
     tl_intg_alert_fields[ral.err_code.reg_intg_err] = 1;
     m_tl_agent_cfg.max_outstanding_req = 1;

hw/top_chip/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv

@@ -119,4 +119,14 @@ module rv_plic_assert_fpv #(parameter int NumSrc = 1,
 
   // When fatal alert happens then only reset can clear it.
   `ASSERT(FatalAlertNeverdrops_A, ##1 !$fell(fatal_alert_i))
+
+  // The interrupt gateway in u_gateway is in charge of making sure that the "set; claim; complete"
+  // flow is followed for each interrupt line. This is done with an ia ("interrupt active") signal.
+  // When interrupt i is asserted, both ip[i] and ia[i] are set. When it is claimed, ip[i] gets
+  // cleared (but ia[i] stays high). Subsequent assertions are ignored until the processor marks the
+  // handling complete, which clears ia[i] again.
+  //
+  // As such, ia[i] should always be true when ip[i] is true.
+  `ASSERT(ActiveIfPending_A, u_gateway.ia | ~u_gateway.ip_o)
+
 endmodule : rv_plic_assert_fpv

hw/top_chip/ip_autogen/rv_plic/rtl/rv_plic.sv

@@ -93,10 +93,6 @@ module rv_plic import rv_plic_reg_pkg::*; #(
   //`ASSERT_PULSE(claimPulse, claim_re[i])
   //`ASSERT_PULSE(completePulse, complete_we[i])
 
-  `ASSERT(onehot0Claim, $onehot0(claim_re))
-
-  `ASSERT(onehot0Complete, $onehot0(complete_we))
-
   //////////////
   // Priority //
   //////////////