diff --git a/doc/proj/checklist_template.md b/doc/proj/checklist_template.md new file mode 100644 index 000000000..f6427147e --- /dev/null +++ b/doc/proj/checklist_template.md @@ -0,0 +1,91 @@ +# BLOCK Checklist + +This checklist covers the [Design and verification stages](stages.md#design-and-verification-stages) sign-off for the `BLOCK` block. + + + + +## Design Checklist + +### D1 + +All checklist items refer to the [D1 design sign-off checklist](stages.md#d1-design-sign-off-checklist). + +Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETED][] | Not Started | +RTL | [CSR_DEFINED][] | Not Started | +RTL | [CLKRST_CONNECTED][] | Not Started | +RTL | [IP_TOP][] | Not Started | +RTL | [IP_INSTANTIABLE][] | Not Started | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started | +RTL | [FUNC_IMPLEMENTED][] | Not Started | +RTL | [ASSERT_KNOWN_ADDED][] | Not Started | +Code Quality | [LINT_SETUP][] | Not Started | + +[SPEC_COMPLETED]: stages.md#d1-design-sign-off-checklist +[CSR_DEFINED]: stages.md#d1-design-sign-off-checklist +[CLKRST_CONNECTED]: stages.md#d1-design-sign-off-checklist +[IP_TOP]: stages.md#d1-design-sign-off-checklist +[IP_INSTANTIABLE]: stages.md#d1-design-sign-off-checklist +[PHYSICAL_MACROS_DEFINED_80]: stages.md#d1-design-sign-off-checklist +[FUNC_IMPLEMENTED]: stages.md#d1-design-sign-off-checklist +[ASSERT_KNOWN_ADDED]: stages.md#d1-design-sign-off-checklist +[LINT_SETUP]: stages.md#d1-design-sign-off-checklist + +### D2 + +*Checklist to be defined — see [stages.md](stages.md#design-stages).* + +### D3 + +*Checklist to be defined — see [stages.md](stages.md#design-stages).* + +## Verification Checklist + +### V1 + +All checklist items refer to the [V1 verification sign-off checklist](stages.md#v1-verification-sign-off-checklist). + +To run V1 tests locally: +``` +dvsim hw/ip/BLOCK/dv/BLOCK_sim_cfg.hjson -i V1 +``` + +Type | Item | Resolution | Note/Collaterals +--------------|----------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | +Documentation | [TESTPLAN_COMPLETED][] | Not Started | +Review | [DESIGN_SPEC_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started | +Integration | [TB_DUT_CONNECTED][] | Not Started | +Simulation | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | +Simulation | [SIM_ASSERTIONS_ADDED][] | Not Started | +Simulation | [SIM_SMOKE_TEST_PASSING][] | Not Started | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | +Formal | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started | +Regression | [FPV_REGRESSION_SETUP][] | Not Started | + +[DV_DOC_DRAFT_COMPLETED]: stages.md#v1-verification-sign-off-checklist +[TESTPLAN_COMPLETED]: stages.md#v1-verification-sign-off-checklist +[DESIGN_SPEC_REVIEWED]: stages.md#v1-verification-sign-off-checklist +[TESTPLAN_REVIEWED]: stages.md#v1-verification-sign-off-checklist +[PRE_VERIFIED_SUB_MODULES_V1]: stages.md#v1-verification-sign-off-checklist +[TB_DUT_CONNECTED]: stages.md#v1-verification-sign-off-checklist +[SIM_COVERAGE_MODEL_ADDED]: stages.md#v1-verification-sign-off-checklist +[SIM_ASSERTIONS_ADDED]: stages.md#v1-verification-sign-off-checklist +[SIM_SMOKE_TEST_PASSING]: stages.md#v1-verification-sign-off-checklist +[SIM_SMOKE_REGRESSION_SETUP]: stages.md#v1-verification-sign-off-checklist +[SIM_NIGHTLY_REGRESSION_SETUP]: stages.md#v1-verification-sign-off-checklist +[FPV_MAIN_ASSERTIONS_PROVEN]: stages.md#v1-verification-sign-off-checklist +[FPV_REGRESSION_SETUP]: stages.md#v1-verification-sign-off-checklist + +### V2 + +*Checklist to be defined — see [stages.md](stages.md#verification-stages).* + +### V3 + +*Checklist to be defined — see [stages.md](stages.md#verification-stages).* diff --git a/doc/proj/stages.md b/doc/proj/stages.md index 7adb3283d..ae474590d 100644 --- a/doc/proj/stages.md +++ b/doc/proj/stages.md @@ -36,6 +36,7 @@ This table shows the current design and verification stage for each block in Moc ## Sign-off procedure To advance a block from one stage to the next you must open a pull request with the checklist in a Markdown file called `doc/proj/BLOCK.md`, where `BLOCK` is replaced by the block's name. +A [checklist template](checklist_template.md) is provided as a starting point. This pull request must be approved by at least three people, one of whom should ideally be someone who has not been involved in the design and the verification of the block. It should also update [the table](#current-status) documenting the current status of each block. @@ -93,6 +94,9 @@ Checklist for signing off a block at V1. | PRE_VERIFIED_SUB_MODULES_V1 | *Both* | Pre-verified sub-modules must also have reached V1. | | DESIGN_SPEC_REVIEWED | *Both* | Review the design specification. | | TESTPLAN_REVIEWED | *Both* | Review the software tests proposed by the testplan. | +| TB_DUT_CONNECTED | *Both* | DUT instantiated in the testbench top with all major interfaces hooked up. | +| SIM_ASSERTIONS_ADDED | *Simulation* | Interface assertion monitors hooked up; X/unknown checks on DUT outputs added. | +| SIM_COVERAGE_MODEL_ADDED | *Simulation* | Initial functional coverage model added to the testbench environment. | | SIM_SMOKE_TEST_PASSING | *Simulation* | Smoketest passing in simulation with a particular seed. | | SIM_SMOKE_REGRESSION_SETUP | *Simulation* | Regression smoke tests selected and defined. | | SIM_NIGHTLY_REGRESSION_SETUP | *Simulation* | Regression nightly tests selected and defined. |