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[doc] Update signoff checklist + add template #572

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91 changes: 91 additions & 0 deletions doc/proj/checklist_template.md
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# BLOCK Checklist

This checklist covers the [Design and verification stages](stages.md#design-and-verification-stages) sign-off for the `BLOCK` block.

<!-- Replace BLOCK with the block name throughout this file. -->
<!-- Link to the block's documentation or briefly describe the block: its purpose, origin (e.g. vendored from OpenTitan, new Mocha IP), key interfaces, and any reused DV infrastructure. -->

## Design Checklist

### D1

All checklist items refer to the [D1 design sign-off checklist](stages.md#d1-design-sign-off-checklist).

Type | Item | Resolution | Note/Collaterals
--------------|-----------------------------------|-------------|------------------
Documentation | [SPEC_COMPLETED][] | Not Started |
RTL | [CSR_DEFINED][] | Not Started |
RTL | [CLKRST_CONNECTED][] | Not Started |
RTL | [IP_TOP][] | Not Started |
RTL | [IP_INSTANTIABLE][] | Not Started |
RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started |
RTL | [FUNC_IMPLEMENTED][] | Not Started |
RTL | [ASSERT_KNOWN_ADDED][] | Not Started |
Code Quality | [LINT_SETUP][] | Not Started |

[SPEC_COMPLETED]: stages.md#d1-design-sign-off-checklist
[CSR_DEFINED]: stages.md#d1-design-sign-off-checklist
[CLKRST_CONNECTED]: stages.md#d1-design-sign-off-checklist
[IP_TOP]: stages.md#d1-design-sign-off-checklist
[IP_INSTANTIABLE]: stages.md#d1-design-sign-off-checklist
[PHYSICAL_MACROS_DEFINED_80]: stages.md#d1-design-sign-off-checklist
[FUNC_IMPLEMENTED]: stages.md#d1-design-sign-off-checklist
[ASSERT_KNOWN_ADDED]: stages.md#d1-design-sign-off-checklist
[LINT_SETUP]: stages.md#d1-design-sign-off-checklist

### D2

*Checklist to be defined — see [stages.md](stages.md#design-stages).*

### D3

*Checklist to be defined — see [stages.md](stages.md#design-stages).*

## Verification Checklist

### V1

All checklist items refer to the [V1 verification sign-off checklist](stages.md#v1-verification-sign-off-checklist).

To run V1 tests locally:
```
dvsim hw/ip/BLOCK/dv/BLOCK_sim_cfg.hjson -i V1
```

Type | Item | Resolution | Note/Collaterals
--------------|----------------------------------|-------------|------------------
Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started |
Documentation | [TESTPLAN_COMPLETED][] | Not Started |
Review | [DESIGN_SPEC_REVIEWED][] | Not Started |
Review | [TESTPLAN_REVIEWED][] | Not Started |
Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started |
Integration | [TB_DUT_CONNECTED][] | Not Started |
Simulation | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | <!-- Set to N/A if FPV-only -->
Simulation | [SIM_ASSERTIONS_ADDED][] | Not Started | <!-- Set to N/A if FPV-only -->
Simulation | [SIM_SMOKE_TEST_PASSING][] | Not Started | <!-- Set to N/A if FPV-only -->
Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started | <!-- Set to N/A if FPV-only -->
Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | <!-- Set to N/A if FPV-only -->
Formal | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started | <!-- Set to N/A if simulation-only -->
Regression | [FPV_REGRESSION_SETUP][] | Not Started | <!-- Set to N/A if simulation-only -->

[DV_DOC_DRAFT_COMPLETED]: stages.md#v1-verification-sign-off-checklist
[TESTPLAN_COMPLETED]: stages.md#v1-verification-sign-off-checklist
[DESIGN_SPEC_REVIEWED]: stages.md#v1-verification-sign-off-checklist
[TESTPLAN_REVIEWED]: stages.md#v1-verification-sign-off-checklist
[PRE_VERIFIED_SUB_MODULES_V1]: stages.md#v1-verification-sign-off-checklist
[TB_DUT_CONNECTED]: stages.md#v1-verification-sign-off-checklist
[SIM_COVERAGE_MODEL_ADDED]: stages.md#v1-verification-sign-off-checklist
[SIM_ASSERTIONS_ADDED]: stages.md#v1-verification-sign-off-checklist
[SIM_SMOKE_TEST_PASSING]: stages.md#v1-verification-sign-off-checklist
[SIM_SMOKE_REGRESSION_SETUP]: stages.md#v1-verification-sign-off-checklist
[SIM_NIGHTLY_REGRESSION_SETUP]: stages.md#v1-verification-sign-off-checklist
[FPV_MAIN_ASSERTIONS_PROVEN]: stages.md#v1-verification-sign-off-checklist
[FPV_REGRESSION_SETUP]: stages.md#v1-verification-sign-off-checklist
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@marnovandermaas marnovandermaas May 20, 2026

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All the same link, I did this differently in the UART D1 sign-off PR.


### V2

*Checklist to be defined — see [stages.md](stages.md#verification-stages).*

### V3

*Checklist to be defined — see [stages.md](stages.md#verification-stages).*
4 changes: 4 additions & 0 deletions doc/proj/stages.md
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Expand Up @@ -36,6 +36,7 @@ This table shows the current design and verification stage for each block in Moc
## Sign-off procedure

To advance a block from one stage to the next you must open a pull request with the checklist in a Markdown file called `doc/proj/BLOCK.md`, where `BLOCK` is replaced by the block's name.
A [checklist template](checklist_template.md) is provided as a starting point.
This pull request must be approved by at least three people, one of whom should ideally be someone who has not been involved in the design and the verification of the block.
It should also update [the table](#current-status) documenting the current status of each block.

Expand Down Expand Up @@ -93,6 +94,9 @@ Checklist for signing off a block at V1.
| PRE_VERIFIED_SUB_MODULES_V1 | *Both* | Pre-verified sub-modules must also have reached V1. |
| DESIGN_SPEC_REVIEWED | *Both* | Review the design specification. |
| TESTPLAN_REVIEWED | *Both* | Review the software tests proposed by the testplan. |
| TB_DUT_CONNECTED | *Both* | DUT instantiated in the testbench top with all major interfaces hooked up. |
| SIM_ASSERTIONS_ADDED | *Simulation* | Interface assertion monitors hooked up; X/unknown checks on DUT outputs added. |
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@marnovandermaas marnovandermaas May 20, 2026

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This should probably be: https://opentitan.org/book/doc/project_governance/checklist/index.html#preliminary_assertion_checks_added

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@marnovandermaas marnovandermaas May 20, 2026

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The output known is part of the D1 sign-off.

| SIM_COVERAGE_MODEL_ADDED | *Simulation* | Initial functional coverage model added to the testbench environment. |
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@marnovandermaas marnovandermaas May 20, 2026

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This is a V2 item.

| SIM_SMOKE_TEST_PASSING | *Simulation* | Smoketest passing in simulation with a particular seed. |
| SIM_SMOKE_REGRESSION_SETUP | *Simulation* | Regression smoke tests selected and defined. |
| SIM_NIGHTLY_REGRESSION_SETUP | *Simulation* | Regression nightly tests selected and defined. |
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