docs: fix grammatical and logical bugs in VerilogCodingStyle.md

[mondalsushant]

• Fix missing space before parenthesis in "UNIX-style line endings" rule
• Fix "With the exceptions of" -> "With the exception of"
• Fix period inside backtick: end. -> end.
• Fix "Conversation" -> "Convention" in constants table header
• Fix "symbolicly" -> "symbolically"
• Fix "Examples;" -> "Examples:"
• Fix "non-block" -> "non-blocking" assignments
• Fix "recommened" -> "recommended"
• Fix "identifed" -> "identified"
• Fix missing closing parenthesis in good code example
• Fix missing semicolon in code example
• Fix "and be implemented" -> "and must be implemented"
• Fix "deferred to case statement" -> "deferred to the case statement"
• Fix "explanations examples" -> "explanations, examples"
• Fix Appendix referencing SystemVerilog-2012 instead of 2017

[mondalsushant]

Hi @rswarbrick and @marnovandermaas,

The changes are ready for inspection. Whenever you have some time, could you please take a look and review this PR?

Thank you!