Working on reorganizing the lcd bus drivers

The remodel of the bus drivers is to allow for better handling of each of the bus types on a per MCU/board basis.
I am also expanding the software rotation in the RGB bus driver to allow its use across all bus types.
I have added RGB888 dithering and RGB565 dithering that will be able to be used with or without rotation. rgb565 byte swap is being added in a manner that will allow only a single iteration over the frame buffer data is either software rotation is being used or dithering is being used or both.

For memory constrained ESP32 boards I have to work out a way to handle the transmitting of the frame buffer without needing to allocate additional buffers. Ideally it is going to be best to create smaller buffers to allow the allocation of at least 1 additional frame buffer. Ideally if 2additional frame buffers are able to be allocated, in DMA memory space it would be best so while one buffer is transmitting the data is able to be copied into the second buffer. If only 1 buffer is able to be allocated, then None of the buffers will need to be allocated in DMA memory. This will at the very least give a performance boost because LVGL is going to be able to render to one of the user supplied buffers without being interrupted at all from ISRs during the sending to a display. This is because the sending to the display is going to be done on the second core even if 1 buffer is used for sending and that buffer is not in DMA memory. I need to put some thought into how to handle the buffer allocation in the best way as I don't want to add anything that can be confusing for the user. If everything works like I am hoping things should actually get a little easier to use because the user is not going to be given the ability to specify the type of memory a buffer has to be allocated in. The user will be able to simply create bytearrays for the frame buffers and pass memoryview instances pointing to those bytearrays to the display driver.

The CI is going to fail for this commit. The code is not finished yet.

Author: kdschlosser

ext_mod/lcd_bus/bitbang/inc/i80.h

@@ -0,0 +1,131 @@
+// Copyright (c) 2024 - 2025 Kevin G. Schlosser
+
+#include "lcd_bus.h"
+#include "lcd_types.h"
+
+// port includes
+#include "mphalport.h"
+
+// micropython includes
+#include "py/obj.h"
+#include "py/objarray.h"
+#include "py/runtime.h"
+
+
+#ifndef __I80_H__
+    #define __I80_H__
+
+    typedef struct {
+        /*
+         * GPIO used for CS line, set to -1 will declaim
+         * exclusively use of I80 bus
+         */
+        mp_hal_pin_obj_t cs_gpio_num;
+
+        /*
+         * User private data, passed directly to
+         * on_color_trans_done's user_ctx
+         */
+        void *user_ctx;
+
+        /* Bit-width of LCD command */
+        int lcd_cmd_bits;
+
+        /* Bit-width of LCD parameter */
+        int lcd_param_bits;
+
+        /* Each i80 device might have its own D/C control logic */
+        struct {
+            /* Level of DC line in IDLE phase */
+            unsigned int dc_idle_level: 1;
+
+            /* Level of DC line in CMD phase */
+            unsigned int dc_cmd_level: 1;
+
+            /* Level of DC line in DUMMY phase */
+            unsigned int dc_dummy_level: 1;
+
+            /* Level of DC line in DATA phase */
+            unsigned int dc_data_level: 1;
+        } dc_levels;
+
+        /* Panel IO config flags */
+        struct {
+            /*
+             * If set, a high level of CS line will select the device,
+             * otherwise, CS line is low level active
+             */
+            unsigned int cs_active_high: 1;
+
+            /* Reverse the data bits, D[N:0] -> D[0:N] */
+            unsigned int reverse_color_bits: 1;
+
+            /* Swap adjacent two color bytes */
+            unsigned int swap_color_bytes: 1;
+
+            /*
+             * The display will write data lines when there's a falling
+             * edge on WR signal (a.k.a the PCLK)
+             */
+            unsigned int pclk_active_neg: 1;
+
+            /*
+             * The WR signal (a.k.a the PCLK)
+             * stays at low level in IDLE phase
+             */
+            unsigned int pclk_idle_low: 1;
+        } flags;
+
+    } lcd_panel_io_i80_config_t;
+
+
+    typedef struct _lcd_i80_bus_handle_t{
+        /* GPIO used for D/C line */
+        mp_hal_pin_obj_t dc_gpio_num;
+
+        /* GPIO used for WR line */
+        mp_hal_pin_obj_t wr_gpio_num;
+
+        /* GPIOs used for data lines */
+        mp_hal_pin_obj_t data_gpio_nums[16];
+
+        /* Number of data lines, 8 or 16 */
+        size_t bus_width;
+
+        /*
+         * Maximum transfer size, this determines
+         * the length of internal DMA link
+         */
+        size_t max_transfer_bytes;
+
+        /* DMA transfer alignment for data allocated from PSRAM */
+        size_t psram_trans_align;
+
+        /* DMA transfer alignment for data allocated from SRAM */
+        size_t sram_trans_align;
+    } lcd_i80_bus_config_t;
+
+    struct _mp_lcd_i80_bus_obj_t {
+        mp_obj_base_t base;
+
+        mp_obj_t callback;
+
+        void *buf1;
+        void *buf2;
+
+        bool trans_done;
+        bool rgb565_byte_swap;
+
+        lcd_panel_io_t panel_io_handle;
+
+        lcd_panel_io_i80_config_t panel_io_config;
+        lcd_i80_bus_config_t bus_config;
+        void *bus_handle;
+
+        uint32_t buffer_size;
+        uint8_t bpp;
+
+        void (*write_color)(mp_lcd_i80_bus_obj_t *self, void *color, size_t color_size);
+    };
+
+#endif