We need a good "Getting Started" guide for the language.
Here are my initial thoughts on some things this should include:
High level overview - what is the language and why would you want to use it
Environment set-up - how to download and set up an environment to go through the code samples. Will initially restrict this to Linux / Windows+WSL, but eventually come back and add MacOS.
First code sample - simple class with a function Add that adds two integers. From there we will expand this to export a class, create a simple Verilog testbench to test it, and then run the whole thing in Verilator.
Expand upon the first sample to showcase the power of the language. One goal is to show how simple it is to add pipeline parallelism and spatial parallelism.
Showcase the power of the standard library by enhancing the (or creating a new) sample that leverages one or more library features.
Start to get into more "advanced" features of the language, starting with things people are almost certainly going to need (like atomic).
???
Somewhere in the above, the concept of callbacks and outbound interfaces needs to be introduced. I'd really like some feedback on this outline, as well as any ideas you might have for the samples in step 4 and 5.
Also in here, we need to cover the target device, and how one would use this with an actual FPGA.
@blakepelton @sapek @jptech
We need a good "Getting Started" guide for the language.
Here are my initial thoughts on some things this should include:
High level overview - what is the language and why would you want to use it
Environment set-up - how to download and set up an environment to go through the code samples. Will initially restrict this to Linux / Windows+WSL, but eventually come back and add MacOS.
First code sample - simple class with a function Add that adds two integers. From there we will expand this to export a class, create a simple Verilog testbench to test it, and then run the whole thing in Verilator.
Expand upon the first sample to showcase the power of the language. One goal is to show how simple it is to add pipeline parallelism and spatial parallelism.
Showcase the power of the standard library by enhancing the (or creating a new) sample that leverages one or more library features.
Start to get into more "advanced" features of the language, starting with things people are almost certainly going to need (like atomic).
???
Somewhere in the above, the concept of callbacks and outbound interfaces needs to be introduced. I'd really like some feedback on this outline, as well as any ideas you might have for the samples in step 4 and 5.
Also in here, we need to cover the target device, and how one would use this with an actual FPGA.
@blakepelton @sapek @jptech