diff --git a/compiler/cpp/circt_util.cpp b/compiler/cpp/circt_util.cpp index d040af3..f4cfa2d 100644 --- a/compiler/cpp/circt_util.cpp +++ b/compiler/cpp/circt_util.cpp @@ -366,7 +366,7 @@ mlir::Value GetPathOp(circt::OpBuilder &opb, const ObjectPath &srcPath, const Ob while (currPath != commonRoot) { - const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(StringToStringAttr(currPath.back())); + const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(ClampedSymAttr(currPath.back())); const mlir::Attribute step = circt::kanagawa::PathStepAttr::get( g_compiler->GetMlirContext(), circt::kanagawa::PathDirection::Parent, @@ -384,7 +384,7 @@ mlir::Value GetPathOp(circt::OpBuilder &opb, const ObjectPath &srcPath, const Ob const std::string stepName = dstPath[currPath.size()]; - const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(StringToStringAttr(stepName)); + const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(ClampedSymAttr(stepName)); const mlir::Attribute step = circt::kanagawa::PathStepAttr::get( g_compiler->GetMlirContext(), circt::kanagawa::PathDirection::Child, @@ -439,6 +439,11 @@ mlir::StringAttr StringToStringAttr(const std::string &str) return mlir::StringAttr::get(g_compiler->GetMlirContext(), str); } +mlir::StringAttr ClampedSymAttr(const std::string &str) +{ + return StringToStringAttr(g_compiler->ClampStringLength(str)); +} + mlir::IntegerType GetIntegerType(const size_t width, mlir::IntegerType::SignednessSemantics signedness) { return mlir::IntegerType::get(g_compiler->GetMlirContext(), width, signedness); @@ -587,7 +592,7 @@ mlir::StringAttr GetFullyQualifiedStringAttr(const ObjectPath &containerPath, co ObjectPath pathWithField = containerPath; pathWithField.push_back("__field__" + fieldName); - return StringToStringAttr(FixupStringCirct(SerializePath(pathWithField, '_'))); + return ClampedSymAttr(FixupStringCirct(SerializePath(pathWithField, '_'))); } circt::hw::InnerSymAttr GetFullyQualifiedInnerSymAttr(const ObjectPath &containerPath, const std::string &fieldName) @@ -2180,7 +2185,7 @@ mlir::Value ModuleDeclarationHelper::GetPort(circt::OpBuilder &opb, const Object while (currPath != commonRoot) { - const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(StringToStringAttr(currPath.back())); + const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(ClampedSymAttr(currPath.back())); const mlir::Attribute step = circt::kanagawa::PathStepAttr::get( g_compiler->GetMlirContext(), circt::kanagawa::PathDirection::Parent, @@ -2198,7 +2203,7 @@ mlir::Value ModuleDeclarationHelper::GetPort(circt::OpBuilder &opb, const Object const std::string stepName = dstPath[currPath.size()]; - const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(StringToStringAttr(stepName)); + const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(ClampedSymAttr(stepName)); const mlir::Attribute step = circt::kanagawa::PathStepAttr::get( g_compiler->GetMlirContext(), circt::kanagawa::PathDirection::Child, diff --git a/compiler/cpp/circt_util.h b/compiler/cpp/circt_util.h index 3272670..faf3aa3 100644 --- a/compiler/cpp/circt_util.h +++ b/compiler/cpp/circt_util.h @@ -69,6 +69,8 @@ mlir::Value LiteralToValue(const Literal& l, circt::OpBuilder& opb, const mlir:: mlir::StringAttr StringToStringAttr(const std::string& str); +mlir::StringAttr ClampedSymAttr(const std::string& str); + size_t GetMlirTypeWidth(const mlir::Type& type); size_t GetMlirValueWidth(const mlir::Value& v); diff --git a/compiler/cpp/verilog.cpp b/compiler/cpp/verilog.cpp index 7e5fb98..62b6755 100644 --- a/compiler/cpp/verilog.cpp +++ b/compiler/cpp/verilog.cpp @@ -495,7 +495,9 @@ std::string GetRegisterBaseName(const Program &program, const size_t registerInd return prefix + std::to_string(registerIndex) + "_" + regDesc._name; } -std::string GetBasicBlockInstanceName(const BasicBlock &basicBlock) { return GetBasicBlockName(basicBlock) + "Impl"; } +std::string GetBasicBlockInstanceName(const BasicBlock &basicBlock) { + return g_compiler->ClampStringLength(GetBasicBlockName(basicBlock) + "Impl"); +} class VerilogCompiler; @@ -1641,7 +1643,8 @@ class VerilogCompiler const mlir::Location location = RegDescToLocation(regDesc); circt::kanagawa::ContainerInstanceOp::create(opb, - location, circt::hw::InnerSymAttr::get(StringToStringAttr(containerInstancePath.back())), + location, + circt::hw::InnerSymAttr::get(ClampedSymAttr(containerInstancePath.back())), circt::hw::InnerRefAttr::get(StringToStringAttr(GetCirctDesignName()), leafContainerNameAttr)); // Write clock and reset ports @@ -2810,7 +2813,8 @@ class VerilogCompiler opb.setInsertionPointToEnd(parentContainer.getBodyBlock()); circt::kanagawa::ContainerInstanceOp::create(opb, - location, circt::hw::InnerSymAttr::get(StringToStringAttr(containerInstancePath.back())), + location, + circt::hw::InnerSymAttr::get(ClampedSymAttr(containerInstancePath.back())), circt::hw::InnerRefAttr::get(StringToStringAttr(GetCirctDesignName()), leafContainerNameAttr)); // Write clock and reset ports @@ -5533,7 +5537,7 @@ class VerilogCompiler str << "global_out_" << regDesc._name << "_" << registerIndex << "_" << writeIndex; - return str.str(); + return g_compiler->ClampStringLength(str.str()); } std::string GetGlobalValidOutName(const size_t registerIndex, const size_t writeIndex) const @@ -5542,7 +5546,7 @@ class VerilogCompiler result += "_valid"; - return result; + return g_compiler->ClampStringLength(result); } std::string GetGlobalInName(const size_t registerIndex) const @@ -5555,7 +5559,7 @@ class VerilogCompiler str << "global_in_" << regDesc._name << "_" << registerIndex; - return str.str(); + return g_compiler->ClampStringLength(str.str()); } std::string GetGlobalInNextName(const size_t registerIndex) const @@ -5568,7 +5572,7 @@ class VerilogCompiler str << "global_in_" << regDesc._name << "_" << registerIndex << "_next"; - return str.str(); + return g_compiler->ClampStringLength(str.str()); } // Returns the name of the variable that holds a global view value @@ -5621,7 +5625,7 @@ class VerilogCompiler ModuleInstanceHelper instance(*this, LocationToCirctLocation(basicBlock._location)); - instance.SetModuleName(GetModuleNamePrefix() + GetBasicBlockName(basicBlock)); + instance.SetModuleName(g_compiler->ClampStringLength(GetModuleNamePrefix() + GetBasicBlockName(basicBlock))); instance.SetInstanceName(GetBasicBlockInstanceName(basicBlock)); instance.AddPort("clk", circt::hw::ModulePort::Direction::Input, GetClockType(), "clk"); @@ -7635,7 +7639,7 @@ class VerilogCompiler const std::set acquiredSemaphores = GetAcquiredSemaphores(basicBlock); const std::set releasedSemaphores = GetReleasedSemaphores(basicBlock); - const std::string fullModuleName = GetModuleNamePrefix() + GetBasicBlockName(basicBlock); + const std::string fullModuleName = g_compiler->ClampStringLength(GetModuleNamePrefix() + GetBasicBlockName(basicBlock)); JsonValue jsonBasicBlock = JsonValue::CreateObject(); JsonValue jsonPorts = JsonValue::CreateArray(); @@ -11426,7 +11430,7 @@ class VerilogCompiler basicBlockPorts.push_back(pi._portInfo); } - const std::string moduleName = GetModuleNamePrefix() + GetBasicBlockName(basicBlock); + const std::string moduleName = g_compiler->ClampStringLength(GetModuleNamePrefix() + GetBasicBlockName(basicBlock)); _compileContext._hwModule = circt::hw::HWModuleOp::create(opb, mlirBbLocation, opb.getStringAttr(moduleName), basicBlockPorts); @@ -11999,7 +12003,8 @@ class VerilogCompiler opb.setInsertionPointToEnd(parentContainer.getBodyBlock()); circt::kanagawa::ContainerInstanceOp instance = circt::kanagawa::ContainerInstanceOp::create(opb, - GetUnknownLocation(), circt::hw::InnerSymAttr::get(StringToStringAttr(path.back())), + GetUnknownLocation(), + circt::hw::InnerSymAttr::get(ClampedSymAttr(path.back())), circt::hw::InnerRefAttr::get(StringToStringAttr(GetCirctDesignName()), containerNameAttr)); SafeInsert(_pathToContainerInstance, path, ContainerAndInstance(container, instance)); @@ -12406,7 +12411,8 @@ void ModuleInstanceHelper::Generate(circt::OpBuilder *const opbIn) // Use a name hint to ensure the wire generated from this verbatim op // doesn't conflict with a name of a variable declared in another verbatim op verbatimOp->setAttr("sv.namehint", - StringToStringAttr(_instanceName + "_" + port.name.str() + "__circt")); + StringToStringAttr(g_compiler->ClampStringLength( + _instanceName + "_" + port.name.str() + "__circt"))); const mlir::Value input = isClockType ? circt::seq::ToClockOp::create(opb, _location, GetClockType(),