diff --git a/artifacts/blogs/flash-attention-4/MANIFEST.yaml b/artifacts/blogs/flash-attention-4/MANIFEST.yaml index e6d2b352f..c52760167 100644 --- a/artifacts/blogs/flash-attention-4/MANIFEST.yaml +++ b/artifacts/blogs/flash-attention-4/MANIFEST.yaml @@ -4,11 +4,12 @@ code_present: true total_blocks: 2 generated_by: scripts/extract_blog_code.py files: -- local_path: code/01-software-exp-cody-waite-horner.cu - heading_path: '## Key Code > ### Software exp (Cody-Waite + Horner)' +- local_path: code/01-software-exp-published-range-reduction-and-rounded-polynomia.cu + heading_path: '## Illustrative Code > ### Software exp (published range reduction + and rounded polynomial)' fence_lang: cuda - sha256: 6fba9c537831bba7b175ee3a050e3adb5ddf99193dee550b7122a4663e3f9164 + sha256: 89c085df18aa5ae9b8693d1085bf43881b8bc3644068761e0312c9ee7628e71c - local_path: code/02-2-cta-cooperative-backward.cu - heading_path: '## Key Code > ### 2-CTA cooperative backward' + heading_path: '## Illustrative Code > ### 2-CTA cooperative backward' fence_lang: cuda - sha256: e089feff40c10ebf42fa1ff878f775c21f4f044fc4b6f2f510b43c2666c7e219 + sha256: 5747bb5ef24ec8a82d9fd80d433d0dc231d0de042af83eeec9414b03a1a53de9 diff --git a/artifacts/blogs/flash-attention-4/code/01-software-exp-cody-waite-horner.cu b/artifacts/blogs/flash-attention-4/code/01-software-exp-cody-waite-horner.cu deleted file mode 100644 index 9f329ce70..000000000 --- a/artifacts/blogs/flash-attention-4/code/01-software-exp-cody-waite-horner.cu +++ /dev/null @@ -1,23 +0,0 @@ -// Extracted from sources/blogs/flash-attention-4.md by scripts/extract_blog_code.py -// Heading: ## Key Code > ### Software exp (Cody-Waite + Horner) -// Original fence language: cuda -// See artifacts/blogs/flash-attention-4/code/PROVENANCE.yaml for origin + license metadata. - -// Software-emulated exp2(x) using Cody-Waite range reduction and a -// Horner-scheme polynomial, Sollya-optimized coefficients. Lets FA-4 -// overlap the exp path with tcgen05.mma because it stays off the SFU. -__device__ __forceinline__ float sw_exp2(float x) { - // Range reduction: x = n + r, with n = round(x), r in [-0.5, 0.5] - int n = __float2int_rn(x); - float r = x - (float)n; - // Horner-scheme polynomial for 2^r, r in [-0.5, 0.5] - float p = 0x1.62e430p-1f; // ~ ln(2) - p = fmaf(p, r, 0x1.ebfc1ep-3f); - p = fmaf(p, r, 0x1.c6af98p-5f); - p = fmaf(p, r, 0x1.3b2c9cp-7f); - p = fmaf(p, r, 0x1.62e43ap-10f); - float y = fmaf(r, p, 1.0f); - // Scale by 2^n via direct FP32 bit manipulation - int bits = __float_as_int(y) + (n << 23); - return __int_as_float(bits); -} diff --git a/artifacts/blogs/flash-attention-4/code/01-software-exp-published-range-reduction-and-rounded-polynomia.cu b/artifacts/blogs/flash-attention-4/code/01-software-exp-published-range-reduction-and-rounded-polynomia.cu new file mode 100644 index 000000000..24483414a --- /dev/null +++ b/artifacts/blogs/flash-attention-4/code/01-software-exp-published-range-reduction-and-rounded-polynomia.cu @@ -0,0 +1,15 @@ +// Extracted from sources/blogs/flash-attention-4.md by scripts/extract_blog_code.py +// Heading: ## Illustrative Code > ### Software exp (published range reduction and rounded polynomial) +// Original fence language: cuda +// See artifacts/blogs/flash-attention-4/code/PROVENANCE.yaml for origin + license metadata. + +// KernelWiki scalar illustration derived from the FA4 blog equations. +// This is not verbatim upstream FA4 code and omits selection and clamping. +#include + +__host__ __device__ inline float fa4_blog_exp2_reference(float x) { + const int n = static_cast(floorf(x)); + const float f = x - static_cast(n); // f in [0, 1) + const float p = 1.0f + f * (0.6951f + f * (0.2276f + f * 0.0771f)); + return ldexpf(p, n); +} diff --git a/artifacts/blogs/flash-attention-4/code/02-2-cta-cooperative-backward.cu b/artifacts/blogs/flash-attention-4/code/02-2-cta-cooperative-backward.cu index 8c4fcaf3a..cbf44c0de 100644 --- a/artifacts/blogs/flash-attention-4/code/02-2-cta-cooperative-backward.cu +++ b/artifacts/blogs/flash-attention-4/code/02-2-cta-cooperative-backward.cu @@ -1,10 +1,14 @@ // Extracted from sources/blogs/flash-attention-4.md by scripts/extract_blog_code.py -// Heading: ## Key Code > ### 2-CTA cooperative backward +// Heading: ## Illustrative Code > ### 2-CTA cooperative backward // Original fence language: cuda // See artifacts/blogs/flash-attention-4/code/PROVENANCE.yaml for origin + license metadata. -// 2-CTA cooperative backward: paired CTAs in a cluster share a single TMEM -// accumulator half, halving SMEM traffic for dK/dV accumulation. -asm volatile( - "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, 1;" - : : "r"(tmem_acc_shared), "l"(desc_a), "l"(desc_b), "r"(0)); +// KernelWiki schematic derived from the FA4 paper/blog dimensions. +// This is not upstream inline PTX or a complete kernel. +struct Fa4TwoCtaBackwardShape { + static constexpr int cta_group = 2; + static constexpr int mma_m = 256; + static constexpr int mma_n = 128; + static constexpr int mma_k = 128; + static constexpr int backward_gemm_count = 5; +}; diff --git a/artifacts/blogs/flash-attention-4/code/PROVENANCE.yaml b/artifacts/blogs/flash-attention-4/code/PROVENANCE.yaml index 2d0e28314..b135da698 100644 --- a/artifacts/blogs/flash-attention-4/code/PROVENANCE.yaml +++ b/artifacts/blogs/flash-attention-4/code/PROVENANCE.yaml @@ -1,21 +1,22 @@ origin_url: https://tridao.me/blog/2026/flash4/ upstream_repo: blog -upstream_sha: c9a560f44002da92d82680036e3482d0ac4939a3 +upstream_sha: none license: inherits-from-source-blog -retrieved_at: 2026-04-27 +retrieved_at: 2026-08-08 asset_mode: extracted generated_by: scripts/extract_blog_code.py size_cap_truncated: false files: -- local_path: 01-software-exp-cody-waite-horner.cu +- local_path: 01-software-exp-published-range-reduction-and-rounded-polynomia.cu role: extracted-block mode: extracted upstream_path: inline-in-blog-markdown - heading_path: '## Key Code > ### Software exp (Cody-Waite + Horner)' - sha256: 6fba9c537831bba7b175ee3a050e3adb5ddf99193dee550b7122a4663e3f9164 + heading_path: '## Illustrative Code > ### Software exp (published range reduction + and rounded polynomial)' + sha256: 89c085df18aa5ae9b8693d1085bf43881b8bc3644068761e0312c9ee7628e71c - local_path: 02-2-cta-cooperative-backward.cu role: extracted-block mode: extracted upstream_path: inline-in-blog-markdown - heading_path: '## Key Code > ### 2-CTA cooperative backward' - sha256: e089feff40c10ebf42fa1ff878f775c21f4f044fc4b6f2f510b43c2666c7e219 + heading_path: '## Illustrative Code > ### 2-CTA cooperative backward' + sha256: 5747bb5ef24ec8a82d9fd80d433d0dc231d0de042af83eeec9414b03a1a53de9 diff --git a/artifacts/blogs/flashmla/MANIFEST.yaml b/artifacts/blogs/flashmla/MANIFEST.yaml index 376f737f1..ff05e28c2 100644 --- a/artifacts/blogs/flashmla/MANIFEST.yaml +++ b/artifacts/blogs/flashmla/MANIFEST.yaml @@ -1,14 +1,15 @@ slug: flashmla -origin_url: https://github.com/deepseek-ai/FlashMLA +origin_url: https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232 code_present: true total_blocks: 2 generated_by: scripts/extract_blog_code.py files: -- local_path: code/01-mla-decode-inner-loop.cu - heading_path: '## Key Code > ### MLA decode inner loop' - fence_lang: cuda - sha256: 4d3950b24b3da7a36e1db9d60a0492ed963d1b49ad6a1b97adeab54abaf4548f -- local_path: code/02-sparse-mla-kv-retrieval-kernel-v3-2.cu - heading_path: '## Key Code > ### Sparse-MLA KV-retrieval kernel (V3.2)' - fence_lang: cuda - sha256: 9b0499c0ddb77a9cebd370e84929d7149ebdc03163768369c95a12ae0b5c4f7f +- local_path: code/01-v3-fp8-sparse-decode-byte-check.py + heading_path: '## Exact V3 FP8 Sparse-Decode Layout > ### V3 FP8 sparse-decode byte + check' + fence_lang: python + sha256: bfc0a6df6b2e04ce4f894a9df04926d4120b4e370354d68e80a55c1645565c7e +- local_path: code/02-decode-page-index-round-trip.py + heading_path: '## Sparse Index Contracts > ### Decode page-index round trip' + fence_lang: python + sha256: a0bbc6f0248adc67b8113e3faa66c1be8924aafce665ebf89b43f0e2f0e4a405 diff --git a/artifacts/blogs/flashmla/code/01-mla-decode-inner-loop.cu b/artifacts/blogs/flashmla/code/01-mla-decode-inner-loop.cu deleted file mode 100644 index 6ca3466b5..000000000 --- a/artifacts/blogs/flashmla/code/01-mla-decode-inner-loop.cu +++ /dev/null @@ -1,31 +0,0 @@ -// Extracted from sources/blogs/flashmla.md by scripts/extract_blog_code.py -// Heading: ## Key Code > ### MLA decode inner loop -// Original fence language: cuda -// See artifacts/blogs/flashmla/code/PROVENANCE.yaml for origin + license metadata. - -// MLA collapses K and V into a shared latent matrix of head-dim Dc=128. -// On decode (one query vector against N KV tokens) we alternate TMA load, -// wgmma/tcgen05 into the q@K^T accumulator, online softmax, and the second -// accumulator against V. -constexpr int Dc = 128; // latent head dim -constexpr int BLOCK_N = 64; // paged KV block size -float acc[Dc] = {0}; -float max_val = -INFINITY; -float l = 0.f; -for (int n0 = 0; n0 < seqlen; n0 += BLOCK_N) { - tma_load(smem_kv, KV_pages + n0); - cp_async_wait(); - float scores[BLOCK_N]; - wgmma_or_tcgen05_mma(scores, q, smem_kv); // q @ K^T - float new_max = warp_reduce_max(scores, BLOCK_N); - float scale = expf(max_val - new_max); - for (int j = 0; j < Dc; j++) acc[j] *= scale; - l *= scale; - for (int j = 0; j < BLOCK_N; j++) { - float p = expf(scores[j] - new_max); - l += p; - for (int d = 0; d < Dc; d++) acc[d] += p * smem_kv[j * Dc + d]; - } - max_val = new_max; -} -for (int d = 0; d < Dc; d++) O[d] = acc[d] / l; diff --git a/artifacts/blogs/flashmla/code/01-v3-fp8-sparse-decode-byte-check.py b/artifacts/blogs/flashmla/code/01-v3-fp8-sparse-decode-byte-check.py new file mode 100644 index 000000000..4fc54a919 --- /dev/null +++ b/artifacts/blogs/flashmla/code/01-v3-fp8-sparse-decode-byte-check.py @@ -0,0 +1,16 @@ +# Extracted from sources/blogs/flashmla.md by scripts/extract_blog_code.py +# Heading: ## Exact V3 FP8 Sparse-Decode Layout > ### V3 FP8 sparse-decode byte check +# Original fence language: python +# See artifacts/blogs/flashmla/code/PROVENANCE.yaml for origin + license metadata. + +# KernelWiki-derived contract check; not upstream FlashMLA code. +NOPE_FP8_VALUES = 512 +GROUPS = 4 +FP32_BYTES = 4 +ROPE_BF16_VALUES = 64 +BF16_BYTES = 2 + +V3_FP8_SPARSE_BYTES = ( + NOPE_FP8_VALUES + GROUPS * FP32_BYTES + ROPE_BF16_VALUES * BF16_BYTES +) +assert V3_FP8_SPARSE_BYTES == 656 diff --git a/artifacts/blogs/flashmla/code/02-decode-page-index-round-trip.py b/artifacts/blogs/flashmla/code/02-decode-page-index-round-trip.py new file mode 100644 index 000000000..3ea60829b --- /dev/null +++ b/artifacts/blogs/flashmla/code/02-decode-page-index-round-trip.py @@ -0,0 +1,15 @@ +# Extracted from sources/blogs/flashmla.md by scripts/extract_blog_code.py +# Heading: ## Sparse Index Contracts > ### Decode page-index round trip +# Original fence language: python +# See artifacts/blogs/flashmla/code/PROVENANCE.yaml for origin + license metadata. + +# KernelWiki-derived contract check; not upstream FlashMLA code. +def encode_page_index(physical_page: int, offset: int, page_size: int) -> int: + assert physical_page >= 0 and 0 <= offset < page_size + return physical_page * page_size + offset + +def decode_page_index(encoded: int, page_size: int) -> tuple[int, int]: + assert encoded >= 0 and page_size > 0 + return divmod(encoded, page_size) + +assert decode_page_index(encode_page_index(7, 13, 64), 64) == (7, 13) diff --git a/artifacts/blogs/flashmla/code/02-sparse-mla-kv-retrieval-kernel-v3-2.cu b/artifacts/blogs/flashmla/code/02-sparse-mla-kv-retrieval-kernel-v3-2.cu deleted file mode 100644 index ce8ec82c2..000000000 --- a/artifacts/blogs/flashmla/code/02-sparse-mla-kv-retrieval-kernel-v3-2.cu +++ /dev/null @@ -1,27 +0,0 @@ -// Extracted from sources/blogs/flashmla.md by scripts/extract_blog_code.py -// Heading: ## Key Code > ### Sparse-MLA KV-retrieval kernel (V3.2) -// Original fence language: cuda -// See artifacts/blogs/flashmla/code/PROVENANCE.yaml for origin + license metadata. - -// Sparse MLA selects top-k KV positions per query before running the dense -// MLA kernel on just those positions. Retrieval uses FP8 dot products with -// per-token scale factors. -__global__ void sparse_mla_topk( - const __nv_fp8_e4m3* Q, const __nv_fp8_e4m3* K, - const float* Q_scale, const float* K_scale, - int* topk_idx, float* topk_score, - int N, int K_DIM, int TOPK) -{ - int q_tile = blockIdx.x; - float scores[N]; - for (int n = 0; n < N; n++) { - float s = 0.f; - for (int k = 0; k < K_DIM; k++) { - s += decode_fp8(Q[q_tile * K_DIM + k]) * Q_scale[q_tile] - * decode_fp8(K[n * K_DIM + k]) * K_scale[n]; - } - scores[n] = s; - } - warp_topk_select(scores, N, topk_idx + q_tile * TOPK, - topk_score + q_tile * TOPK, TOPK); -} diff --git a/artifacts/blogs/flashmla/code/PROVENANCE.yaml b/artifacts/blogs/flashmla/code/PROVENANCE.yaml index fcef8cd20..84a2595b3 100644 --- a/artifacts/blogs/flashmla/code/PROVENANCE.yaml +++ b/artifacts/blogs/flashmla/code/PROVENANCE.yaml @@ -1,21 +1,22 @@ -origin_url: https://github.com/deepseek-ai/FlashMLA +origin_url: https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232 upstream_repo: blog -upstream_sha: 71c737929f2567bd0a094ae140f8f60f390b1232 +upstream_sha: none license: inherits-from-source-blog retrieved_at: 2026-04-27 asset_mode: extracted generated_by: scripts/extract_blog_code.py size_cap_truncated: false files: -- local_path: 01-mla-decode-inner-loop.cu +- local_path: 01-v3-fp8-sparse-decode-byte-check.py role: extracted-block mode: extracted upstream_path: inline-in-blog-markdown - heading_path: '## Key Code > ### MLA decode inner loop' - sha256: 4d3950b24b3da7a36e1db9d60a0492ed963d1b49ad6a1b97adeab54abaf4548f -- local_path: 02-sparse-mla-kv-retrieval-kernel-v3-2.cu + heading_path: '## Exact V3 FP8 Sparse-Decode Layout > ### V3 FP8 sparse-decode byte + check' + sha256: bfc0a6df6b2e04ce4f894a9df04926d4120b4e370354d68e80a55c1645565c7e +- local_path: 02-decode-page-index-round-trip.py role: extracted-block mode: extracted upstream_path: inline-in-blog-markdown - heading_path: '## Key Code > ### Sparse-MLA KV-retrieval kernel (V3.2)' - sha256: 9b0499c0ddb77a9cebd370e84929d7149ebdc03163768369c95a12ae0b5c4f7f + heading_path: '## Sparse Index Contracts > ### Decode page-index round trip' + sha256: a0bbc6f0248adc67b8113e3faa66c1be8924aafce665ebf89b43f0e2f0e4a405 diff --git a/artifacts/blogs/gated-delta-net/MANIFEST.yaml b/artifacts/blogs/gated-delta-net/MANIFEST.yaml index 390694f2d..188abb0e0 100644 --- a/artifacts/blogs/gated-delta-net/MANIFEST.yaml +++ b/artifacts/blogs/gated-delta-net/MANIFEST.yaml @@ -1,14 +1,4 @@ slug: gated-delta-net -origin_url: https://github.com/NVlabs/GatedDeltaNet -code_present: true -total_blocks: 2 -generated_by: scripts/extract_blog_code.py -files: -- local_path: code/01-chunk-parallel-prefill-reference-pytorch.py - heading_path: '## Key Code > ### Chunk-parallel prefill reference (PyTorch)' - fence_lang: python - sha256: 709cd74d72c22e764ffb77d85bbecd0b1c47b52f2cc0c48bab279954d0f24a22 -- local_path: code/02-triton-decode-step-kernel-streaming.py - heading_path: '## Key Code > ### Triton decode-step kernel (streaming)' - fence_lang: python - sha256: 09a1bc93abdf8165a3d7809e485ef17a3d1a980ae579e36ba81b47665ba35b22 +origin_url: https://github.com/NVlabs/GatedDeltaNet/tree/b53d6d3a161267432a79c1c04af69fa52bddc921 +code_present: false +generated_by: KernelWiki verifier remediation diff --git a/artifacts/blogs/gated-delta-net/code/01-chunk-parallel-prefill-reference-pytorch.py b/artifacts/blogs/gated-delta-net/code/01-chunk-parallel-prefill-reference-pytorch.py deleted file mode 100644 index 7708ad9a0..000000000 --- a/artifacts/blogs/gated-delta-net/code/01-chunk-parallel-prefill-reference-pytorch.py +++ /dev/null @@ -1,29 +0,0 @@ -# Extracted from sources/blogs/gated-delta-net.md by scripts/extract_blog_code.py -# Heading: ## Key Code > ### Chunk-parallel prefill reference (PyTorch) -# Original fence language: python -# See artifacts/blogs/gated-delta-net/code/PROVENANCE.yaml for origin + license metadata. - -import torch - -def gated_delta_net_prefill(q, k, v, gate, initial_state, CHUNK_SIZE=64): - """ - Chunk-parallel prefill. Each chunk's state matrix is reused across its - query window, so we pay the O(Dk*Dv) state update once per chunk, not - per token. - q, k: [B, L, Dk] v: [B, L, Dv] gate: [B, L] - """ - B, L, Dk = q.shape - Dv = v.shape[-1] - out = torch.empty(B, L, Dv, device=q.device, dtype=q.dtype) - state = initial_state.clone() # [B, Dk, Dv] - for ci in range(0, L, CHUNK_SIZE): - ce = min(ci + CHUNK_SIZE, L) - k_chunk = k[:, ci:ce] - v_chunk = v[:, ci:ce] - g_chunk = gate[:, ci:ce] - decay = torch.cumprod(g_chunk, dim=1) # adaptive memory decay - for t in range(ce - ci): - state = state * decay[:, t:t+1, None] - state = state + k_chunk[:, t, :, None] * v_chunk[:, t, None, :] - out[:, ci + t] = (q[:, ci + t, :, None] * state).sum(dim=1) - return out, state diff --git a/artifacts/blogs/gated-delta-net/code/02-triton-decode-step-kernel-streaming.py b/artifacts/blogs/gated-delta-net/code/02-triton-decode-step-kernel-streaming.py deleted file mode 100644 index 33a7f7710..000000000 --- a/artifacts/blogs/gated-delta-net/code/02-triton-decode-step-kernel-streaming.py +++ /dev/null @@ -1,33 +0,0 @@ -# Extracted from sources/blogs/gated-delta-net.md by scripts/extract_blog_code.py -# Heading: ## Key Code > ### Triton decode-step kernel (streaming) -# Original fence language: python -# See artifacts/blogs/gated-delta-net/code/PROVENANCE.yaml for origin + license metadata. - -import triton -import triton.language as tl - -@triton.jit -def gdn_decode_step_kernel( - Q, K, V, GATE, STATE, OUT, - stride_qb, stride_kb, stride_vb, - Dk: tl.constexpr, Dv: tl.constexpr): - """ - One-token delta-rule update for decode. STATE is a [Dk, Dv] matrix kept - per sample; we fold in the new (k,v) pair after applying the decay gate. - """ - b = tl.program_id(0) - dk = tl.arange(0, Dk) - dv = tl.arange(0, Dv) - - q = tl.load(Q + b * stride_qb + dk) # [Dk] - k = tl.load(K + b * stride_kb + dk) # [Dk] - v = tl.load(V + b * stride_vb + dv) # [Dv] - g = tl.load(GATE + b) # scalar decay - - state = tl.load(STATE + b * Dk * Dv + dk[:, None] * Dv + dv[None, :]) - state = state * g # apply decay - state = state + k[:, None] * v[None, :] # delta update - tl.store(STATE + b * Dk * Dv + dk[:, None] * Dv + dv[None, :], state) - - out = tl.sum(q[:, None] * state, axis=0) # [Dv] - tl.store(OUT + b * Dv + dv, out) diff --git a/artifacts/blogs/gated-delta-net/code/PROVENANCE.yaml b/artifacts/blogs/gated-delta-net/code/PROVENANCE.yaml deleted file mode 100644 index 8fc34220e..000000000 --- a/artifacts/blogs/gated-delta-net/code/PROVENANCE.yaml +++ /dev/null @@ -1,21 +0,0 @@ -origin_url: https://github.com/NVlabs/GatedDeltaNet -upstream_repo: blog -upstream_sha: none -license: inherits-from-source-blog -retrieved_at: 2026-04-16 -asset_mode: extracted -generated_by: scripts/extract_blog_code.py -size_cap_truncated: false -files: -- local_path: 01-chunk-parallel-prefill-reference-pytorch.py - role: extracted-block - mode: extracted - upstream_path: inline-in-blog-markdown - heading_path: '## Key Code > ### Chunk-parallel prefill reference (PyTorch)' - sha256: 709cd74d72c22e764ffb77d85bbecd0b1c47b52f2cc0c48bab279954d0f24a22 -- local_path: 02-triton-decode-step-kernel-streaming.py - role: extracted-block - mode: extracted - upstream_path: inline-in-blog-markdown - heading_path: '## Key Code > ### Triton decode-step kernel (streaming)' - sha256: 09a1bc93abdf8165a3d7809e485ef17a3d1a980ae579e36ba81b47665ba35b22 diff --git a/artifacts/kernels/flash-attention-4/full/PROVENANCE.yaml b/artifacts/kernels/flash-attention-4/full/PROVENANCE.yaml index c7e7d7be5..429b2680f 100644 --- a/artifacts/kernels/flash-attention-4/full/PROVENANCE.yaml +++ b/artifacts/kernels/flash-attention-4/full/PROVENANCE.yaml @@ -6,6 +6,10 @@ retrieved_at: '2026-04-17' asset_mode: verbatim size_cap_truncated: false generated_by: Phase 3 Round 2 task11 anchor bundle +description: >- + Adjacent NVIDIA CUTLASS SM100 FMHA backward MLA reference. This bundle is + not the Dao-AILab FlashAttention-4 implementation; it is retained only as a + separately pinned comparison implementation. source_pr_id: pr-cutlass-2466 files: - local_path: sm100_fmha_bwd_mla_kernel_tma_warpspecialized.hpp diff --git a/artifacts/kernels/flash-attention-4/variants/01-software-exp-skeleton.cu b/artifacts/kernels/flash-attention-4/variants/01-software-exp-skeleton.cu index 5fac8e365..4faf84947 100644 --- a/artifacts/kernels/flash-attention-4/variants/01-software-exp-skeleton.cu +++ b/artifacts/kernels/flash-attention-4/variants/01-software-exp-skeleton.cu @@ -1,23 +1,13 @@ -// provenance: derived from pr-cutlass-2466, technique-software-exp, kernel-flash-attention-4; not upstream code -// origin: wiki/kernels/flash-attention-4.md Phase 3 variant (software-emulated exponential skeleton) +// KernelWiki-derived scalar reference for the range reduction and rounded +// degree-3 polynomial printed in Tri Dao's FlashAttention-4 blog. +// This is not verbatim FA4 source. The real kernel applies software evaluation +// to only a selected fraction of entries and includes range handling/scheduling. -// FlashAttention-4 software exp trick: exp2f(x * log2(e)) is emitted by -// the compiler as a fused ex2.approx.f32 instruction on SM100, which runs -// on the MUFU (Multi-Function Unit) path and overlaps with the MMA path. -// This avoids the Tensor Core saturation bottleneck that FA-2/FA-3 hit. - -#include #include -__device__ inline float fa4_rescale_exp(float x, float max_old, float max_new) { - // Rescale accumulator when row maximum updates (online softmax). - // exp2f(diff * log2(e)) fuses to ex2.approx.f32 on SM100. - constexpr float LOG2E = 1.44269504088896340736f; - return __expf((max_old - max_new) * 1.0f) * x; - // Equivalent fused form: - // return exp2f((max_old - max_new) * LOG2E) * x; +__host__ __device__ inline float fa4_blog_exp2_reference(float x) { + const int n = static_cast(floorf(x)); + const float f = x - static_cast(n); // f in [0, 1) + const float p = 1.0f + f * (0.6951f + f * (0.2276f + f * 0.0771f)); + return ldexpf(p, n); } - -// See full/ for the upstream FA4-MLA kernel. The ex2-based rescale lives -// inside that kernel's inner softmax loop (grep for 'exp2|ex2' in the -// mainloop collective file). diff --git a/artifacts/kernels/flash-attention-4/variants/PROVENANCE.yaml b/artifacts/kernels/flash-attention-4/variants/PROVENANCE.yaml index 28dbe7621..c92059979 100644 --- a/artifacts/kernels/flash-attention-4/variants/PROVENANCE.yaml +++ b/artifacts/kernels/flash-attention-4/variants/PROVENANCE.yaml @@ -1,16 +1,18 @@ origin_url: derived upstream_repo: derived license: MIT-style-inherited-from-kernelwiki-tooling -retrieved_at: '2026-04-17' +retrieved_at: '2026-08-08' asset_mode: derived derived_from: - - pr-cutlass-2466 - - technique-software-exp + - blog-flash-attention-4 - kernel-flash-attention-4 size_cap_truncated: false -generated_by: Phase 3 Round 2 task11 anchor bundle +generated_by: KernelWiki verifier remediation +description: >- + Scalar teaching reference for the range reduction and rounded polynomial in + the first-party FA4 blog; not upstream FA4 kernel code. files: - local_path: 01-software-exp-skeleton.cu role: derived-source mode: derived - sha256: 91a822a1dedc26daaedfa9432132a30fc2e1b40c0916072a5de0cccf1b4b1074 + sha256: 15df5285418d175ba4bbbfae5a705d49f77b1c7b9fbdfb0542cd0879d1c1dbac diff --git a/artifacts/kernels/flashmla/full/PROVENANCE.yaml b/artifacts/kernels/flashmla/full/PROVENANCE.yaml index d50dc2ab0..779c32a99 100644 --- a/artifacts/kernels/flashmla/full/PROVENANCE.yaml +++ b/artifacts/kernels/flashmla/full/PROVENANCE.yaml @@ -7,11 +7,16 @@ asset_mode: verbatim size_cap_truncated: false generated_by: Phase 3 Round 3 task12 (flashmla anchor) source_pr_id: pr-cutlass-2472 +bundle_scope: adjacent implementations; not deepseek-ai/FlashMLA source +subject_repo: deepseek-ai/FlashMLA files: - local_path: 77_blackwell_mla_fwd.cu sha256: c072ee30b377248e03d6fc0ea56365f0dd6f03874a81f02ff5a2a1686b81023b role: upstream-file mode: verbatim + upstream_repo: NVIDIA/cutlass + upstream_sha: 9baa06dd + origin_url: https://github.com/NVIDIA/cutlass/pull/2472 upstream_path: examples/77_blackwell_fmha/77_blackwell_mla_fwd.cu - local_path: sm100_fmha_mla_tma_warpspecialized.hpp sha256: f35738f40c9092df2ad10c54bd1c51e56165323298713e102995a4cbb29d35ea @@ -19,4 +24,5 @@ files: mode: verbatim upstream_repo: flashinfer-ai/flashinfer upstream_sha: 9a05c92a + origin_url: https://github.com/flashinfer-ai/flashinfer/commit/9a05c92a upstream_path: include/flashinfer/attention/blackwell/kernel/sm100_fmha_mla_tma_warpspecialized.hpp diff --git a/artifacts/kernels/flashmla/variants/01-mla-layout-and-index-contract.cu b/artifacts/kernels/flashmla/variants/01-mla-layout-and-index-contract.cu new file mode 100644 index 000000000..7e3ed3d6e --- /dev/null +++ b/artifacts/kernels/flashmla/variants/01-mla-layout-and-index-contract.cu @@ -0,0 +1,32 @@ +// provenance: derived from blog-flashmla at DeepSeek FlashMLA commit 71c7379; +// not upstream code +// Scope: V3-family FP8 sparse-decode byte layout and encoded page-index arithmetic. + +#include +#include + +namespace kernelwiki_flashmla_contract { + +constexpr int kNopeFp8Bytes = 512; +constexpr int kScaleCount = 4; +constexpr int kFp32Bytes = 4; +constexpr int kRopeBf16Values = 64; +constexpr int kBf16Bytes = 2; +constexpr int kV3Fp8SparseBytes = + kNopeFp8Bytes + kScaleCount * kFp32Bytes + kRopeBf16Values * kBf16Bytes; +static_assert(kV3Fp8SparseBytes == 656); + +// FlashMLA sparse decode consumes this physical page/offset encoding. +// The caller must handle -1 as an invalid entry before decoding it. +constexpr int encode_page_index(int physical_page, int offset, int page_size) { + return physical_page * page_size + offset; +} + +constexpr std::pair decode_page_index(int encoded, int page_size) { + return {encoded / page_size, encoded % page_size}; +} + +static_assert(decode_page_index(encode_page_index(7, 13, 64), 64) == + std::pair{7, 13}); + +} // namespace kernelwiki_flashmla_contract diff --git a/artifacts/kernels/flashmla/variants/PROVENANCE.yaml b/artifacts/kernels/flashmla/variants/PROVENANCE.yaml index 0f725acbe..9d251abcb 100644 --- a/artifacts/kernels/flashmla/variants/PROVENANCE.yaml +++ b/artifacts/kernels/flashmla/variants/PROVENANCE.yaml @@ -5,12 +5,11 @@ retrieved_at: '2026-04-17' asset_mode: derived derived_from: - blog-flashmla -- pr-cutlass-2472 -- hw-tmem size_cap_truncated: false -generated_by: Phase 3 Round 3 task12 (flashmla variants) +generated_by: KernelWiki verifier remediation +bundle_scope: verified layout and index contract only; not an attention kernel files: -- local_path: 01-mla-decode-inner-loop.cu +- local_path: 01-mla-layout-and-index-contract.cu role: derived-source mode: derived - sha256: 4f494dc2d282468966a1e2028bc50d0ef0c364b34d24f75ee881608ddef2df69 + sha256: aa886373129daedc09b9dae7a23960b021256647e1002399db0dca82053c6f96 diff --git a/artifacts/kernels/fused-moe/full/PROVENANCE.yaml b/artifacts/kernels/fused-moe/full/PROVENANCE.yaml index e3579ef9e..6dead4b74 100644 --- a/artifacts/kernels/fused-moe/full/PROVENANCE.yaml +++ b/artifacts/kernels/fused-moe/full/PROVENANCE.yaml @@ -1,29 +1,31 @@ -origin_url: https://github.com/vllm-project/vllm/pull/23696 -upstream_repo: vllm-project/vllm -upstream_sha: 074854b2 -license: inherits-from-upstream -retrieved_at: '2026-04-17' -asset_mode: verbatim +origin_url: https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048 +upstream_repo: multiple-adjacent-references +license: mixed-inherits-from-upstreams-and-kernelwiki-tooling +retrieved_at: '2026-08-08' +asset_mode: extracted size_cap_truncated: false -generated_by: Phase 3 Round 3 task12 (fused-moe anchor) +generated_by: KernelWiki factual remediation source_pr_id: pr-vllm-23696 -notes: 'Mixed-source bundle: vllm gated-dual-GEMM patch + sglang flashinfer-cutedsl - MoE runner + DeepGEMM grouped-GEMM extract.' +notes: >- + Mixed adjacent bundle, not a full implementation of the FlashInfer Track A + FP8 benchmark. The vLLM diff is MXFP4 expert compute, the SGLang file is an + FP4 CuteDSL runner, and the C++ file is local illustrative pseudocode. files: - local_path: vllm-PR-23696-dual-gemm.patch sha256: 033d30b15af4f2050189c2e76ba61959e1e5d4bd049dc901fd56f68890b891a0 role: pr-diff mode: upstream-patch + upstream_repo: vllm-project/vllm + upstream_sha: 074854b24f6e0b1e237a004283e1f46d98c0d73c + upstream_path: aggregate merged diff across the five changed paths - local_path: flashinfer_cutedsl.py sha256: de6bd663382b5bf34dba077d90febc9cc80d9dda908d9947966a3cadbc21bf33 role: upstream-file mode: verbatim upstream_repo: sgl-project/sglang - upstream_sha: c554dc5c + upstream_sha: c554dc5c64b661f2c53225b03a76359eaddc39e4 upstream_path: python/sglang/srt/layers/moe/moe_runner/flashinfer_cutedsl.py - local_path: moe-grouped-gemm-launch.cpp - sha256: e4d1af249fb7054fa2df64b89e24f63735c9daa2c51d4e1af87e3f27b71b7f97 - role: extracted-block - mode: extracted - upstream_path: sources/blogs/deepgemm.md - heading_path: '## Key Code > ### MoE grouped-GEMM launch' + sha256: 1368d01910bce19816daf9af6963a24de3809a0b12162fce1e5dd9d79064e884 + role: derived-source + mode: derived diff --git a/artifacts/kernels/fused-moe/full/moe-grouped-gemm-launch.cpp b/artifacts/kernels/fused-moe/full/moe-grouped-gemm-launch.cpp index 8a21baa45..4e69db269 100644 --- a/artifacts/kernels/fused-moe/full/moe-grouped-gemm-launch.cpp +++ b/artifacts/kernels/fused-moe/full/moe-grouped-gemm-launch.cpp @@ -1,7 +1,6 @@ -// Extracted from sources/blogs/deepgemm.md by scripts/extract_blog_code.py -// Heading: ## Key Code > ### MoE grouped-GEMM launch -// Original fence language: cpp -// See artifacts/blogs/deepgemm/code/PROVENANCE.yaml for origin + license metadata. +// KernelWiki illustrative pseudocode; not upstream DeepGEMM or contest code. +// It documents only the varying-M segmentation used by a grouped GEMM. +// It is intentionally incomplete and is not a compilable or timed kernel. // Grouped-GEMM packs a variable list of per-expert GEMMs into one kernel // launch via a prefix-sum offset array; layouts are contiguous (M-axis), diff --git a/artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py b/artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py index 204b2a38d..25897aae1 100644 --- a/artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py +++ b/artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py @@ -1,31 +1,215 @@ -# provenance: derived from pr-sglang-21339, pr-vllm-23696, blog-deepgemm; not upstream code -# origin: wiki/kernels/fused-moe.md Phase 3 variant - -# Fused MoE skeleton: router logits -> top-k expert selection -> grouped -# GEMM dispatch with contiguous M-axis packing. - -import torch - -def fused_moe_forward(hidden, router_weights, expert_weights_gate, - expert_weights_up, expert_weights_down, top_k=2): - """Reference PyTorch implementation of the dispatch + fused-dual-GEMM path. - Production kernels (vllm+sglang+DeepGEMM) fuse all three stages.""" - B, L, D = hidden.shape - logits = hidden @ router_weights.T # [B, L, E] - top_vals, top_idx = logits.topk(top_k, dim=-1) - weights = torch.softmax(top_vals, dim=-1) # renormalize - # Scatter tokens to their selected experts (grouped M-axis) - E = expert_weights_gate.shape[0] - out = torch.zeros_like(hidden) - for e in range(E): - mask = (top_idx == e).any(dim=-1) # [B, L] - if not mask.any(): - continue - x_e = hidden[mask] # [Ne, D] - gate = x_e @ expert_weights_gate[e].T - up = x_e @ expert_weights_up[e].T - y_e = (torch.nn.functional.silu(gate) * up) @ expert_weights_down[e].T - # Scatter back, weighted by the routing weight for this expert - w_e = weights[mask * (top_idx == e).any(dim=-1)[..., None]].sum(dim=-1) - out[mask] = out[mask] + w_e[:, None] * y_e - return out +# provenance: derived from contest-flashinfer-track-a; not upstream code +# Scope: CPU-checkable semantics only; not an optimized or fused GPU kernel. + +from __future__ import annotations + +import math +import random + + +def _sigmoid(value: float) -> float: + if value >= 0: + return 1.0 / (1.0 + math.exp(-value)) + exp_value = math.exp(value) + return exp_value / (1.0 + exp_value) + + +def deepseek_grouped_topk( + routing_logits: list[list[float]], + routing_bias: list[float], + *, + top_k: int, + n_group: int, + topk_group: int, + routed_scaling_factor: float, +) -> tuple[list[list[int]], list[list[float]]]: + """Return global expert IDs and combine weights for DeepSeek-V3 routing. + + Bias affects expert selection but not the normalized combine weights. + """ + if not routing_logits or not routing_logits[0]: + raise ValueError("routing_logits must have shape [tokens, experts]") + experts = len(routing_logits[0]) + if any(len(row) != experts for row in routing_logits): + raise ValueError("routing_logits rows must have equal length") + if len(routing_bias) != experts: + raise ValueError("routing_bias must have shape [experts]") + if experts % n_group: + raise ValueError("experts must be divisible by n_group") + group_size = experts // n_group + if not (1 <= topk_group <= n_group and 1 <= top_k <= topk_group * group_size): + raise ValueError("invalid grouped top-k parameters") + if group_size < 2: + raise ValueError("DeepSeek group scoring requires at least two experts per group") + + all_ids: list[list[int]] = [] + all_weights: list[list[float]] = [] + for row in routing_logits: + sigmoid_scores = [_sigmoid(value) for value in row] + selection_scores = [ + score + bias for score, bias in zip(sigmoid_scores, routing_bias, strict=True) + ] + group_scores = [] + for group in range(n_group): + begin = group * group_size + two_largest = sorted( + selection_scores[begin : begin + group_size], reverse=True + )[:2] + group_scores.append((sum(two_largest), group)) + kept_groups = { + group + for _, group in sorted(group_scores, reverse=True)[:topk_group] + } + candidates = [ + expert + for expert in range(experts) + if expert // group_size in kept_groups + ] + chosen = sorted( + candidates, key=lambda expert: selection_scores[expert], reverse=True + )[:top_k] + raw_weights = [sigmoid_scores[expert] for expert in chosen] + denominator = sum(raw_weights) + all_ids.append(chosen) + all_weights.append( + [ + weight / denominator * routed_scaling_factor + for weight in raw_weights + ] + ) + return all_ids, all_weights + + +def _matvec(matrix: list[list[float]], vector: list[float]) -> list[float]: + if any(len(row) != len(vector) for row in matrix): + raise ValueError("matrix/vector dimensions do not match") + return [sum(a * b for a, b in zip(row, vector, strict=True)) for row in matrix] + + +def local_expert_reference( + hidden_states: list[list[float]], + topk_ids: list[list[int]], + combine_weights: list[list[float]], + w13: list[list[list[float]]], + w2: list[list[list[float]]], + *, + local_expert_offset: int, +) -> list[list[float]]: + """Compute local W13/SwiGLU/W2 contributions and weighted accumulation. + + Logical shapes are hidden_states[T,H], w13[E_local,2I,H], and + w2[E_local,H,I]. + """ + if not hidden_states or not hidden_states[0] or len(w13) != len(w2): + raise ValueError("empty or mismatched input") + tokens, hidden = len(hidden_states), len(hidden_states[0]) + if len(topk_ids) != tokens or len(combine_weights) != tokens: + raise ValueError("top-k rows must match tokens") + if any(len(ids) != len(weights) for ids, weights in zip(topk_ids, combine_weights, strict=True)): + raise ValueError("top-k IDs and weights must have equal row lengths") + output = [[0.0] * hidden for _ in range(tokens)] + + for local_id, (expert_w13, expert_w2) in enumerate(zip(w13, w2, strict=True)): + if not expert_w13 or len(expert_w13) % 2: + raise ValueError("w13 rows must equal 2 * intermediate") + intermediate = len(expert_w13) // 2 + if len(expert_w2) != hidden or any(len(row) != intermediate for row in expert_w2): + raise ValueError("w2 must have shape [hidden, intermediate]") + global_id = local_expert_offset + local_id + for token, hidden_row in enumerate(hidden_states): + matching_weight = sum( + weight + for expert, weight in zip( + topk_ids[token], combine_weights[token], strict=True + ) + if expert == global_id + ) + if matching_weight == 0.0: + continue + projected = _matvec(expert_w13, hidden_row) + up, gate = projected[:intermediate], projected[intermediate:] + activated = [ + _sigmoid(gate_value) * gate_value * up_value + for gate_value, up_value in zip(gate, up, strict=True) + ] + expert_output = _matvec(expert_w2, activated) + for column, value in enumerate(expert_output): + output[token][column] += matching_weight * value + return output + + +def fused_moe_reference( + hidden_states: list[list[float]], + routing_logits: list[list[float]], + routing_bias: list[float], + w13: list[list[list[float]]], + w2: list[list[list[float]]], + *, + local_expert_offset: int, + top_k: int, + n_group: int, + topk_group: int, + routed_scaling_factor: float, +) -> list[list[float]]: + topk_ids, combine_weights = deepseek_grouped_topk( + routing_logits, + routing_bias, + top_k=top_k, + n_group=n_group, + topk_group=topk_group, + routed_scaling_factor=routed_scaling_factor, + ) + return local_expert_reference( + hidden_states, + topk_ids, + combine_weights, + w13, + w2, + local_expert_offset=local_expert_offset, + ) + + +def _self_test() -> None: + logits = [ + [2.0, 1.0, -1.0, -2.0], + [-1.5, -0.5, 0.5, 1.5], + [0.1, 0.3, 0.2, 0.0], + ] + bias = [0.0, 0.2, 0.4, -0.1] + ids, weights = deepseek_grouped_topk( + logits, + bias, + top_k=2, + n_group=2, + topk_group=1, + routed_scaling_factor=2.5, + ) + assert ids == [[1, 0], [2, 3], [2, 3]] + assert all(math.isclose(sum(row), 2.5, rel_tol=1e-12) for row in weights) + + # Negative control: biased selection scores must not become combine weights. + first_biased = [_sigmoid(value) + delta for value, delta in zip(logits[0], bias, strict=True)] + wrong_denominator = sum(first_biased[expert] for expert in ids[0]) + wrong = [first_biased[expert] / wrong_denominator * 2.5 for expert in ids[0]] + assert any(not math.isclose(a, b) for a, b in zip(weights[0], wrong, strict=True)) + + rng = random.Random(7) + hidden = [[rng.uniform(-1, 1) for _ in range(4)] for _ in range(3)] + w13 = [ + [[rng.uniform(-1, 1) for _ in range(4)] for _ in range(6)] + for _ in range(4) + ] + w2 = [ + [[rng.uniform(-1, 1) for _ in range(3)] for _ in range(4)] + for _ in range(4) + ] + output = local_expert_reference( + hidden, ids, weights, w13, w2, local_expert_offset=0 + ) + assert len(output) == 3 and all(len(row) == 4 for row in output) + assert all(math.isfinite(value) for row in output for value in row) + + +if __name__ == "__main__": + _self_test() + print("fused-moe derived reference: PASS") diff --git a/artifacts/kernels/fused-moe/variants/PROVENANCE.yaml b/artifacts/kernels/fused-moe/variants/PROVENANCE.yaml index eb45a5bea..285ef1367 100644 --- a/artifacts/kernels/fused-moe/variants/PROVENANCE.yaml +++ b/artifacts/kernels/fused-moe/variants/PROVENANCE.yaml @@ -1,17 +1,18 @@ -origin_url: derived +origin_url: https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048 upstream_repo: derived license: MIT-style-inherited-from-kernelwiki-tooling -retrieved_at: '2026-04-17' +retrieved_at: '2026-08-08' asset_mode: derived derived_from: -- pr-sglang-21339 -- pr-vllm-23696 -- blog-deepgemm -- kernel-fused-moe +- contest-flashinfer-track-a size_cap_truncated: false -generated_by: Phase 3 Round 3 task12 (fused-moe variants) +generated_by: KernelWiki factual remediation +notes: >- + Parameterized standard-library reference for the definition's grouped + DeepSeek routing and local W13/SwiGLU/W2 accumulation. It neither dequantizes + FP8 tensors nor models GPU launches, layouts, or performance. files: - local_path: 01-routing-plus-fusion-skeleton.py role: derived-source mode: derived - sha256: 2cc640b1baa1a6cd42718616ffe2cf78a9b6d4eb3317464f059c6fd442439342 + sha256: 6e4e5889347d9783585d5bef8764e55cdc07c4840cbb56ed337db37911586aa1 diff --git a/artifacts/kernels/gated-delta-net/full/PROVENANCE.yaml b/artifacts/kernels/gated-delta-net/full/PROVENANCE.yaml index 98a4ac3e8..6ff073765 100644 --- a/artifacts/kernels/gated-delta-net/full/PROVENANCE.yaml +++ b/artifacts/kernels/gated-delta-net/full/PROVENANCE.yaml @@ -1,12 +1,15 @@ origin_url: https://github.com/sgl-project/sglang/pull/21019 upstream_repo: sgl-project/sglang -upstream_sha: 5bdc07d9 +upstream_sha: 5bdc07d974f6cf236fa765a685453ea5e587a838 license: inherits-from-upstream retrieved_at: '2026-04-17' asset_mode: verbatim size_cap_truncated: false generated_by: Phase 3 Round 3 task12 (gated-delta-net anchor) source_pr_id: pr-sglang-21019 +bundle_scope: >- + Adjacent fused split/reshape/concatenate preprocessing for Qwen3-Next and + Qwen3.5 projection outputs; not a GDN recurrence, prefill, or decode kernel. files: - local_path: gdn_fused_proj.py sha256: c4ef85167eb11065721e76dd5d63d6f346f309f84822578dd4a3874249acef89 diff --git a/artifacts/kernels/gated-delta-net/variants/01-gdn-recurrence-reference.py b/artifacts/kernels/gated-delta-net/variants/01-gdn-recurrence-reference.py new file mode 100644 index 000000000..1992a6ea2 --- /dev/null +++ b/artifacts/kernels/gated-delta-net/variants/01-gdn-recurrence-reference.py @@ -0,0 +1,101 @@ +"""One-head Gated DeltaNet recurrence; derived, not a tuned GPU kernel. + +Reference semantics: FlashInfer commit +7f614b86470180bab2d22e36fd1775791c6bf3e6, trace/templates/gdn.py. +""" + +from __future__ import annotations + +from math import isclose + + +Matrix = list[list[float]] + + +def dot(left: list[float], right: list[float]) -> float: + assert len(left) == len(right) and left + return sum(a * b for a, b in zip(left, right)) + + +def outer(left: list[float], right: list[float]) -> Matrix: + return [[a * b for b in right] for a in left] + + +def add(left: Matrix, right: Matrix) -> Matrix: + assert len(left) == len(right) and len(left[0]) == len(right[0]) + return [[a + b for a, b in zip(x, y)] for x, y in zip(left, right)] + + +def scale_matrix(factor: float, matrix: Matrix) -> Matrix: + return [[factor * value for value in row] for row in matrix] + + +def vector_matrix(vector: list[float], matrix: Matrix) -> list[float]: + assert len(vector) == len(matrix) and matrix + return [ + sum(vector[row] * matrix[row][column] for row in range(len(matrix))) + for column in range(len(matrix[0])) + ] + + +def gdn_step( + state: Matrix, + q: list[float], + k: list[float], + v: list[float], + decay: float, + beta: float, + scale: float, +) -> tuple[list[float], Matrix]: + """Apply the compact gated-delta update to state shaped [K,V].""" + assert 0.0 <= decay <= 1.0 and 0.0 <= beta <= 1.0 + assert len(state) == len(q) == len(k) and len(state[0]) == len(v) + decayed = scale_matrix(decay, state) + retrieved = vector_matrix(k, decayed) + correction = [beta * (target - old) for target, old in zip(v, retrieved)] + new_state = add(decayed, outer(k, correction)) + output = [scale * value for value in vector_matrix(q, new_state)] + return output, new_state + + +def _expanded_reference( + state: Matrix, k: list[float], v: list[float], decay: float, beta: float +) -> Matrix: + decayed = scale_matrix(decay, state) + old_v = vector_matrix(k, decayed) + new_v = [beta * target + (1.0 - beta) * old for target, old in zip(v, old_v)] + removed = scale_matrix(-1.0, outer(k, old_v)) + return add(add(decayed, removed), outer(k, new_v)) + + +def _close(left: Matrix, right: Matrix) -> bool: + return all( + isclose(a, b, rel_tol=1e-12, abs_tol=1e-12) + for x, y in zip(left, right) + for a, b in zip(x, y) + ) + + +def _self_test() -> None: + state = [[0.2, -0.3], [0.4, 0.1]] + q = [0.6, -0.8] + k = [0.8, 0.6] + v = [0.5, -0.25] + decay, beta, output_scale = 0.75, 0.4, 0.5 + + output, compact = gdn_step(state, q, k, v, decay, beta, output_scale) + expanded = _expanded_reference(state, k, v, decay, beta) + assert _close(compact, expanded) + assert all(isclose(a, b, rel_tol=1e-12, abs_tol=1e-12) for a, b in zip( + output, [output_scale * x for x in vector_matrix(q, expanded)] + )) + + additive_only = add(scale_matrix(decay, state), outer(k, v)) + assert not _close(compact, additive_only) + old_output = [output_scale * x for x in vector_matrix(q, scale_matrix(decay, state))] + assert output != old_output + print("gated-delta recurrence reference: PASS") + + +if __name__ == "__main__": + _self_test() diff --git a/artifacts/kernels/gated-delta-net/variants/PROVENANCE.yaml b/artifacts/kernels/gated-delta-net/variants/PROVENANCE.yaml index deb860eb7..78dd439f8 100644 --- a/artifacts/kernels/gated-delta-net/variants/PROVENANCE.yaml +++ b/artifacts/kernels/gated-delta-net/variants/PROVENANCE.yaml @@ -1,20 +1,19 @@ -origin_url: derived +origin_url: https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/trace/templates/gdn.py upstream_repo: derived license: MIT-style-inherited-from-kernelwiki-tooling -retrieved_at: '2026-04-17' +retrieved_at: '2026-08-08' asset_mode: derived derived_from: +- contest-flashinfer-track-c - blog-gated-delta-net -- pr-sglang-21019 -- kernel-gated-delta-net size_cap_truncated: false -generated_by: Phase 3 Round 3 task12 (gated-delta-net variants) +generated_by: KernelWiki factual remediation +notes: >- + Standard-library, one-head semantic recurrence check. It does not model + grouped-value head replication, GPU layouts, numeric precision, launches, + or performance and is not an upstream or tuned GPU kernel. files: -- local_path: 01-chunk-parallel-prefill-reference-pytorch.py +- local_path: 01-gdn-recurrence-reference.py role: derived-source mode: derived - sha256: d7e74b02df4974fb082cacbae8a5182dd2c40cb1c13fd1d74505b51cfb15481b -- local_path: 02-triton-decode-step-kernel-streaming.py - role: derived-source - mode: derived - sha256: d5eef14bdbc44e50784c0ca34e7041dcad2151960a85feddba62b097e20079ad + sha256: 11560c14d805f79dbc1025801beed373c0e17e712e054c6f85231071b8d8b971 diff --git a/artifacts/kernels/gated-dual-gemm/full/PROVENANCE.yaml b/artifacts/kernels/gated-dual-gemm/full/PROVENANCE.yaml index 6237c880b..3f0379e81 100644 --- a/artifacts/kernels/gated-dual-gemm/full/PROVENANCE.yaml +++ b/artifacts/kernels/gated-dual-gemm/full/PROVENANCE.yaml @@ -1,22 +1,15 @@ -origin_url: https://github.com/vllm-project/vllm/pull/23696 -upstream_repo: vllm-project/vllm -upstream_sha: 074854b2 -license: inherits-from-upstream -retrieved_at: '2026-04-17' -asset_mode: extracted +origin_url: https://github.com/gpu-mode/reference-kernels/tree/c5b2f7c062d5015f29c3a1043cfd04954397944c/problems/nvidia/nvfp4_dual_gemm +upstream_repo: gpu-mode/reference-kernels +upstream_sha: c5b2f7c062d5015f29c3a1043cfd04954397944c +license: MIT +retrieved_at: '2026-08-08' +asset_mode: verbatim size_cap_truncated: false -generated_by: Phase 3 Round 3 task12 (gated-dual-gemm anchor) -source_pr_id: pr-vllm-23696 +generated_by: KernelWiki verifier remediation +source_id: contest-gpumode-p3 files: -- local_path: vllm-PR-23696-gated-dual-gemm.patch - sha256: 033d30b15af4f2050189c2e76ba61959e1e5d4bd049dc901fd56f68890b891a0 - role: pr-diff - mode: upstream-patch -- local_path: blackwell-cutlass-schedules-and-tma.cu - sha256: e720037bbdb5ee5054259a331cdaf489e7135a44038d66d1fd9d9e5998b75255 - role: extracted-block - mode: extracted - upstream_path: sources/blogs/tflops-gap-fp4-moe.md - heading_path: '# TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell - > ## Three Key Optimization Techniques > ### 2. Blackwell-Specific CUTLASS Schedules - and TMA' +- local_path: task.yml + sha256: 2bf4e5c04cc8a9c283e519437c8324ca9265d9c12d0dfe2b76dc9f0542ada051 + role: upstream-file + mode: verbatim + upstream_path: problems/nvidia/nvfp4_dual_gemm/task.yml diff --git a/artifacts/kernels/gated-dual-gemm/full/task.yml b/artifacts/kernels/gated-dual-gemm/full/task.yml new file mode 100644 index 000000000..4d36bde62 --- /dev/null +++ b/artifacts/kernels/gated-dual-gemm/full/task.yml @@ -0,0 +1,64 @@ +# name: nvfp4-dual-gemm + +files: + - {"name": "submission.py", "source": "@SUBMISSION@"} + - {"name": "task.py", "source": "task.py"} + - {"name": "utils.py", "source": "../utils.py"} + - {"name": "reference.py", "source": "reference.py"} + - {"name": "eval.py", "source": "../eval_better_bench.py"} + +lang: "py" + +description: | + + You will implement a block scaled dual matrix-matrix multiplication kernel with silu activation optimized for NVIDIA B200. + To be explicit, you will be given a tuple of tensors: + ``` + (a, b1, b2, sfa, sfb1, sfb2, c) + ``` + where: + * `a` is M x K x L in K-major order in nvfp4(e2m1) + * `b1` is N x K x L in K-major order in nvfp4(e2m1) + * `b2` is N x K x L in K-major order in nvfp4(e2m1) + * `sfa` is M x (K // 16) x L in K-major order in fp8(e4m3fnuz) + * `sfb1` is N x (K // 16) x L in K-major order in fp8(e4m3fnuz) + * `sfb2` is N x (K // 16) x L in K-major order in fp8(e4m3fnuz) + * `c` is M x N x L in fp16 + + Matrix sizes `M` is divisible by mma_tiler_mn[0], `N` is divisible by mma_tiler_mn[1], `K` is divisible by 256. + The ranking criteria is the geometric mean of the benchmark results. + For the grand price, your kernel will be evaluated against the speed of light analysis + and the solution closest to the speed of light will be awarded the grand price. + ``` + The speed of light analysis based on the max(FP4 Tensor Core math throughput, DRAM memory throughput) of B200 and tested under 1.5Ghz clock: + M N K L time[us] + 256 4096 7168 1 4.708 + 512 4096 7168 1 8.714 + 256 3072 4096 1 2.125 + 512 3072 7168 1 6.535 + ``` +config: + main: "eval.py" + +templates: + Python: "template.py" + +tests: + - {"m": 1536, "n": 512, "k": 7168, "l": 1, "seed": 1111} + - {"m": 256, "n": 512, "k": 256, "l": 1, "seed": 1111} + - {"m": 1536, "n": 512, "k": 7168, "l": 1, "seed": 1111} + - {"m": 3072, "n": 1024, "k": 1536, "l": 1, "seed": 1111} + - {"m": 7168, "n": 1024, "k": 256, "l": 1, "seed": 1111} + - {"m": 7168, "n": 2304, "k": 2048, "l": 1, "seed": 1111} + - {"m": 4608, "n": 384, "k": 7168, "l": 1, "seed": 1111} + - {"m": 7168, "n": 384, "k": 2304, "l": 1, "seed": 1111} + - {"m": 512, "n": 768, "k": 7168, "l": 1, "seed": 1111} + - {"m": 4096, "n": 768, "k": 512, "l": 1, "seed": 1111} + +benchmarks: + - {"m": 256, "n": 4096, "k": 7168, "l": 1, "seed": 1111} + - {"m": 512, "n": 4096, "k": 7168, "l": 1, "seed": 1111} + - {"m": 256, "n": 3072, "k": 4096, "l": 1, "seed": 1111} + - {"m": 512, "n": 3072, "k": 7168, "l": 1, "seed": 1111} + +ranking_by: "geom" diff --git a/artifacts/kernels/gated-dual-gemm/variants/01-gated-dual-gemm-semantics.py b/artifacts/kernels/gated-dual-gemm/variants/01-gated-dual-gemm-semantics.py new file mode 100644 index 000000000..ec3118bbf --- /dev/null +++ b/artifacts/kernels/gated-dual-gemm/variants/01-gated-dual-gemm-semantics.py @@ -0,0 +1,73 @@ +"""Derived CPU reference for the GPU Mode NVFP4 dual-GEMM result semantics. + +This intentionally does not model NVFP4 encoding, scale layout, or GPU execution. +It checks the two shared-A matrix products and the order of SiLU and multiply. +""" + +from __future__ import annotations + +import math + + +Matrix = list[list[float]] + + +def _sigmoid(value: float) -> float: + if value >= 0.0: + z = math.exp(-value) + return 1.0 / (1.0 + z) + z = math.exp(value) + return z / (1.0 + z) + + +def _project(a: Matrix, b_nk: Matrix) -> Matrix: + if not a or not b_nk or not a[0]: + raise ValueError("matrices must be non-empty") + k = len(a[0]) + if any(len(row) != k for row in a): + raise ValueError("A must be rectangular") + if any(len(row) != k for row in b_nk): + raise ValueError("B must have shape [N,K]") + return [[sum(x * y for x, y in zip(a_row, b_row)) for b_row in b_nk] + for a_row in a] + + +def gated_dual_gemm(a: Matrix, b1_nk: Matrix, b2_nk: Matrix) -> Matrix: + """Return SiLU(A @ B1.T) * (A @ B2.T).""" + if len(b1_nk) != len(b2_nk): + raise ValueError("B1 and B2 must have the same N") + gate = _project(a, b1_nk) + up = _project(a, b2_nk) + return [[g * _sigmoid(g) * u for g, u in zip(g_row, u_row)] + for g_row, u_row in zip(gate, up)] + + +def _assert_close(actual: Matrix, expected: Matrix) -> None: + for actual_row, expected_row in zip(actual, expected): + for actual_value, expected_value in zip(actual_row, expected_row): + assert math.isclose(actual_value, expected_value, rel_tol=1e-12, + abs_tol=1e-12) + + +def _self_test() -> None: + a = [[1.0, -2.0], [0.5, 3.0]] + b1 = [[2.0, 1.0], [-1.0, 0.5]] + b2 = [[0.25, 2.0], [1.0, -3.0]] + + gate = _project(a, b1) + up = _project(a, b2) + expanded = [[g * _sigmoid(g) * u for g, u in zip(g_row, u_row)] + for g_row, u_row in zip(gate, up)] + actual = gated_dual_gemm(a, b1, b2) + _assert_close(actual, expanded) + + wrong_branch = [[u * _sigmoid(u) * g for g, u in zip(g_row, u_row)] + for g_row, u_row in zip(gate, up)] + assert any(not math.isclose(x, y, rel_tol=1e-12, abs_tol=1e-12) + for actual_row, wrong_row in zip(actual, wrong_branch) + for x, y in zip(actual_row, wrong_row)) + + +if __name__ == "__main__": + _self_test() + print("gated dual GEMM semantic reference: PASS") diff --git a/artifacts/kernels/gated-dual-gemm/variants/PROVENANCE.yaml b/artifacts/kernels/gated-dual-gemm/variants/PROVENANCE.yaml index 7fddf037b..d3f4ed189 100644 --- a/artifacts/kernels/gated-dual-gemm/variants/PROVENANCE.yaml +++ b/artifacts/kernels/gated-dual-gemm/variants/PROVENANCE.yaml @@ -1,16 +1,14 @@ origin_url: derived upstream_repo: derived license: MIT-style-inherited-from-kernelwiki-tooling -retrieved_at: '2026-04-17' +retrieved_at: '2026-08-08' asset_mode: derived derived_from: -- pr-vllm-23696 -- kernel-gated-dual-gemm -- technique-epilogue-fusion +- contest-gpumode-p3 size_cap_truncated: false -generated_by: Phase 3 Round 3 task12 (gated-dual-gemm variants) +generated_by: KernelWiki verifier remediation files: -- local_path: 01-fused-epilogue-swiglu-skeleton.cu +- local_path: 01-gated-dual-gemm-semantics.py role: derived-source mode: derived - sha256: 85e158c184546912579ac5270451471a96f135efa3584bafbf45064e5fb7e223 + sha256: ac13383732fc5c946ae1698cc0776131dd399c507736b28a1a7d4f45a976daeb diff --git a/artifacts/prs/vllm/PR-23696/PROVENANCE.yaml b/artifacts/prs/vllm/PR-23696/PROVENANCE.yaml index 8b1ee4fb4..bb3c816ce 100644 --- a/artifacts/prs/vllm/PR-23696/PROVENANCE.yaml +++ b/artifacts/prs/vllm/PR-23696/PROVENANCE.yaml @@ -1,12 +1,16 @@ origin_url: https://github.com/vllm-project/vllm/pull/23696 upstream_repo: vllm-project/vllm -upstream_sha: 074854b2 +upstream_sha: 074854b24f6e0b1e237a004283e1f46d98c0d73c license: inherits-from-upstream retrieved_at: '2026-04-17' asset_mode: verbatim size_cap_truncated: false generated_by: scripts/fetch_pr_diff.py source_pr_id: pr-vllm-23696 +notes: >- + diff.patch is the aggregate merged diff across all five changed paths. The + key-files tree intentionally retains only kernel_warmup.py as a representative + byte-verified file; it is not the complete changed-file set. files: - local_path: diff.patch role: pr-diff diff --git a/data/core-prs.yaml b/data/core-prs.yaml index f124707e8..d7a8d17a4 100644 --- a/data/core-prs.yaml +++ b/data/core-prs.yaml @@ -8,8 +8,8 @@ sources: - cute-dsl-tutorial - triton-in-policy - allowlist -total_captured: 252 -checksum_sha256: 2f30f03bf66bf9f4550949e26e5d805420dca14c74a368a153f0ca145b978465 +total_captured: 246 +checksum_sha256: 6809c0043b75aaf43dbecf1df96509b0605f2759505074bf080b60d5269f64c5 prs: - id: pr-TensorRT-LLM-11697 source_of_inclusion: cute-dsl-tutorial @@ -50,9 +50,9 @@ prs: - id: pr-cutlass-2378 source_of_inclusion: cute-dsl-tutorial - id: pr-cutlass-2466 - source_of_inclusion: cute-dsl-tutorial + source_of_inclusion: wiki-graph-closure - id: pr-cutlass-2472 - source_of_inclusion: cute-dsl-tutorial + source_of_inclusion: wiki-graph-closure - id: pr-cutlass-2492 source_of_inclusion: cute-dsl-tutorial - id: pr-cutlass-2599 @@ -75,8 +75,6 @@ prs: source_of_inclusion: cute-dsl-tutorial - id: pr-deepgemm-304 source_of_inclusion: wiki-graph-closure -- id: pr-flash-attention-1236 - source_of_inclusion: wiki-graph-closure - id: pr-flash-attention-1934 source_of_inclusion: cute-dsl-tutorial - id: pr-flash-attention-1940 @@ -146,8 +144,6 @@ prs: - id: pr-flashinfer-1025 source_of_inclusion: triton-in-policy - id: pr-flashinfer-1039 - source_of_inclusion: triton-in-policy -- id: pr-flashinfer-1117 source_of_inclusion: wiki-graph-closure - id: pr-flashinfer-1331 source_of_inclusion: cute-dsl-tutorial @@ -171,8 +167,6 @@ prs: source_of_inclusion: cute-dsl-tutorial - id: pr-flashinfer-1812 source_of_inclusion: cute-dsl-tutorial -- id: pr-flashinfer-1850 - source_of_inclusion: wiki-graph-closure - id: pr-flashinfer-2149 source_of_inclusion: cute-dsl-tutorial - id: pr-flashinfer-2171 @@ -253,8 +247,6 @@ prs: source_of_inclusion: triton-in-policy - id: pr-pytorch-171129 source_of_inclusion: triton-in-policy -- id: pr-pytorch-175826 - source_of_inclusion: wiki-graph-closure - id: pr-pytorch-176495 source_of_inclusion: triton-in-policy - id: pr-sglang-10403 @@ -429,8 +421,6 @@ prs: source_of_inclusion: triton-in-policy - id: pr-vllm-23666 source_of_inclusion: triton-in-policy -- id: pr-vllm-23696 - source_of_inclusion: wiki-graph-closure - id: pr-vllm-25990 source_of_inclusion: cute-dsl-tutorial - id: pr-vllm-26322 @@ -495,8 +485,6 @@ prs: source_of_inclusion: triton-in-policy - id: pr-vllm-39007 source_of_inclusion: triton-in-policy -- id: pr-vllm-39752 - source_of_inclusion: wiki-graph-closure - id: pr-vllm-40941 source_of_inclusion: triton-in-policy - id: pr-vllm-41428 diff --git a/data/inclusion-policy.yaml b/data/inclusion-policy.yaml index d9bde14f5..c47530c88 100644 --- a/data/inclusion-policy.yaml +++ b/data/inclusion-policy.yaml @@ -2,9 +2,8 @@ ## Consumed by scripts/compute_core_prs.py ## ## Two separate lanes (CuTe DSL and Triton) are classified with different -## criteria because Triton on SM100 has no direct tcgen05/TMEM access -## (see wiki/languages/triton-blackwell.md), so Triton's useful scope is -## narrower than CuTe DSL's. +## criteria because their Blackwell kernel coverage and production maturity +## differ by workload. See wiki/languages/triton-blackwell.md. cute-dsl: description: | @@ -62,20 +61,19 @@ cute-dsl: triton: description: | - Triton is a scoped Blackwell lane. As of Triton 3.6 (released - 2026-01-21), Triton has native SM100 lowering through tcgen05 + TMEM - via descriptor/TMA + warp_specialize, tl.dot_scaled, and Gluon - multi-CTA / 2CTA, but production peak-performance leadership for - compute-bound matmul/attention on Blackwell still favors hand-written - CuTe-DSL / CUTLASS / FA-4 / TRT-LLM kernels for many workloads - (downstream evidence: pr-sglang-5390 measured CUTLASS tcgen05_mla - ~27% faster than the Triton MLA decode baseline; pr-sglang-21595 - moved Blackwell datacenter multimodal attention default away from - triton_attn). We therefore capture Triton PRs in three sub-scopes - that remain genuinely useful on Blackwell rather than mirroring the - full CuTe-DSL lane. + Triton is a scoped Blackwell lane. Native TCGen5/TMEM compiler support + enters between Triton v3.2.0 and v3.3.0. Later releases expand explicit + user surfaces and maturity: v3.5 includes Gluon TCGen5/TMEM and + block-scaled matmul tutorials, while v3.6 adds broader layouts/copies, + warp-specialization work, and initial multi-CTA / 2-CTA Gluon support. + Exact instruction selection remains shape-, dtype-, layout-, target-, and + compiler-configuration-dependent. Production routing also remains + workload-specific: pr-sglang-5390 reports one scoped CUTLASS-over-Triton + MLA result, and pr-sglang-21595 moves one SM100 attention default to FA4. + We therefore capture Triton PRs in three useful Blackwell sub-scopes + rather than mirroring the full CuTe-DSL lane. - See data/version-claims.yaml::vs-triton-3.6-blackwell-tcgen05 for the + See data/version-claims.yaml::vs-triton-3.3-blackwell-tcgen05 for the version-sensitive claim record this rationale references. capture_criteria: diff --git a/data/schemas.yaml b/data/schemas.yaml index 215d8b2c1..847e34c54 100644 --- a/data/schemas.yaml +++ b/data/schemas.yaml @@ -150,7 +150,7 @@ wiki-technique: constraints: type: technique id_prefix: technique- - reproducibility_minimum: snippet + reproducibility_minimum: concept wiki-pattern: required: @@ -165,6 +165,8 @@ wiki-pattern: optional: - architectures - confidence + - reproducibility + - evidence_basis - version_sensitive constraints: type: pattern @@ -199,7 +201,7 @@ wiki-kernel: constraints: type: kernel id_prefix: kernel- - reproducibility_minimum: snippet + reproducibility_minimum: concept wiki-language: required: @@ -237,6 +239,7 @@ wiki-migration: - confidence - reproducibility - prerequisites + - evidence_basis - version_sensitive constraints: type: migration diff --git a/data/tags.yaml b/data/tags.yaml index 114146f0a..1456b3afd 100644 --- a/data/tags.yaml +++ b/data/tags.yaml @@ -57,6 +57,12 @@ techniques: - top-k-selection - parallel-scan - stream-k + - k-dimension-parallelism + - reduction + - occupancy + - launch-bounds + - maxrregcount + - spills kernel_types: - gemm @@ -89,6 +95,7 @@ languages: - ptx - python - jax-pallas + - mojo confidence: - verified diff --git a/data/tool-versions.yaml b/data/tool-versions.yaml index a16ae4707..4ec1738d2 100644 --- a/data/tool-versions.yaml +++ b/data/tool-versions.yaml @@ -18,6 +18,13 @@ tools: - tool: triton releases: + - name: "3.7.1" + released_at: "2026-06-18" + channel: stable + release_notes_url: "https://github.com/triton-lang/triton/releases/tag/v3.7.1" + notes: | + Latest checked stable release as of 2026-08-08. The upstream release + describes two regression fixes and no new API or feature. - name: "3.6.0" released_at: "2026-01-21" channel: stable @@ -27,10 +34,9 @@ tools: - pr-sglang-22079 - pr-sglang-21019 notes: | - First Triton release with native Blackwell tcgen05 + TMEM lowering - infrastructure. Strongest user-visible Blackwell paths: descriptor/TMA - warp-specialized matmul, Gluon multi-CTA / 2CTA, tl.dot_scaled / block - scaled. See data/triton-3.6-evidence.md for the per-pathway breakdown. + Incremental Blackwell release: broader TCGen5/TMEM copies and layouts, + more warp-specialization work, and initial multi-CTA / 2-CTA Gluon + support. Native backend support predates this release. - name: "3.5.1" released_at: "2025-11-12" channel: stable @@ -39,6 +45,25 @@ tools: Last 3.5.x patch before the 3.6 Blackwell story. Pages with version_sensitive claims valid for ">=3.5,<3.6" should pin to this release. + - name: "3.3.0" + released_at: "2025-04-09" + channel: stable + release_notes_url: "https://github.com/triton-lang/triton/releases/tag/v3.3.0" + evidence_source_ids: + - doc-triton-3.3-blackwell + notes: | + First checked tag after v3.2.0 whose tree contains native TCGen5 MMA, + TMEM operations and allocation, MMAv5 lowering, and concrete + Blackwell conversion tests. + - name: "3.2.0" + released_at: "2025-01-22" + channel: stable + release_notes_url: "https://github.com/triton-lang/triton/releases/tag/v3.2.0" + evidence_source_ids: + - doc-triton-3.3-blackwell + notes: | + Checked negative side of the Blackwell backend boundary; corresponding + TCGen5 MMA, TMEM, and MMAv5-lowering symbols are absent from this tag. - tool: cutlass releases: diff --git a/data/triton-3.6-evidence.md b/data/triton-3.6-evidence.md index 54d6e2c94..b8a556f77 100644 --- a/data/triton-3.6-evidence.md +++ b/data/triton-3.6-evidence.md @@ -1,79 +1,41 @@ -# Triton 3.6 Blackwell Evidence Memo +# Triton Blackwell Version Evidence -## Releases of Record -- 2026-01-21: Triton 3.6.0 (`v3.6.0`, release commit `7c56a5e`). Blackwell-relevant items in the official release notes include TMEM encoding/layout work (`#8136`, `#8148`, `#8202`), generic `tcgen05` load/store and copy lowering (`#8225`, `#8421`, `#8495`, `#8102`, `#8338`), `tcgen05.mma` generalization (`#8386`), initial 2CTA Gluon support (`#8644`, `#8653`), `reqnctapercluster` emission (`#8645`), warp-specialization end-to-end aref plumbing (`#8262`, `#7826`, `#8009`), and Gluon `tcgen05 mma scaled` support (`#8393`). -- No subsequent `3.6.x` patch release is visible on the official GitHub releases page as of 2026-04-27; the next older release shown there is 3.5.1 on 2025-11-12. If the wiki wants a machine-checked negative claim rather than a page inspection, mark this needs-verification. +## Releases of record -## Lowering Surfaces -- Pathway: plain `tl.dot` / standard MMA without Blackwell-specific warp specialization or descriptor/TMA structure. - Lowers to `tcgen05` / TMEM on SM100: needs-verification. Triton 3.6 clearly contains native Blackwell `tcgen05` + TMEM infrastructure, but the checked sources do not prove that arbitrary plain `tl.dot` kernels now automatically use that path. - Introducing PRs/commits: needs-verification for this exact user-visible surface. - Caveats: do not replace the old wiki sentence with the opposite blanket claim. The evidence supports “Triton 3.6 has native Blackwell lowering paths,” not “all Triton matmuls on SM100 are now TMEM-backed tcgen05 kernels.” +| Release | Exact revision | Evidence-scoped conclusion | +|---|---|---| +| v3.2.0 | `9641643da6c52000c807b5eeed05edaec4402a67` | Checked negative side: the corresponding TCGen5 MMA, TMEM, and MMAv5-lowering symbols are absent. | +| v3.3.0 | `819e9c8c29ad2ae96cbd93a1d3b8a3a0f4c8f09c` | Adds TCGen5 MMA/scaled-MMA operations, TMEM operations and allocation, MMAv5 lowering, and conversion tests for concrete TCGen5/TMEM output. | +| v3.5.0 | `c3c476f357f1e9768ea4e45aa5c17528449ab9ef` | Includes explicit Gluon TCGen5/TMEM and Blackwell block-scaled matmul tutorials, plus documented warp-specialization work. | +| v3.6.0 | `7c56a5e40f7fd928dfd5c72902d5def0097db73a` | Incremental generalization of copies/layouts and MMA, aref warp-specialization work, and initial multi-CTA/2-CTA Gluon support. | +| v3.7.0 | `5f3f125e8f63c24613f1f73b937442864f263f94` | Further end-to-end 2-CTA, multicast, and TMA work. | +| v3.7.1 | `f797708` | Latest checked stable release on 2026-08-08; a two-regression patch with no advertised new API or feature. | -- Pathway: descriptor/TMA matmul with `tl.range(..., warp_specialize=True)` and `tl.dot`, as documented in the persistent matmul tutorial. - Lowers to `tcgen05` / TMEM on SM100: yes for the Blackwell warp-specialized path; this is the strongest checked `tl.*`-surface evidence. The official tutorial says this warp-specialized mode “only works on Blackwell right now,” while the 3.6 release notes add the Blackwell TMEM/layout, `tcgen05`, and warp-specialization aref plumbing needed to make that path real on SM100. - Introducing PRs/commits: warp-specialization lowering plumbing `#8262`, `#7826`, `#8009`, `#8123`, `#8534`, `#8451`, `#8651`; Blackwell TMEM / `tcgen05` backend work `#8136`, `#8148`, `#8202`, `#8386`, `#8421`, `#8495`, `#8102`, `#8338`, `#8225`. - Caveats: the verified path is descriptor/TMA-oriented and warp-specialized, not generic. It is also Blackwell-targeted in the checked docs, and the tutorial evidence does not prove parity for every non-persistent or non-descriptor `tl.dot` kernel shape. +The discriminating version boundary is therefore v3.2.0 to v3.3.0, not v3.5.x to v3.6.0. See `sources/docs/triton-3.3-blackwell.md` for the pinned files and scope. -- Pathway: fused attention forward kernels using `warp_specialize=True` in the Triton tutorial path. - Lowers to `tcgen05` / TMEM on SM100: likely yes on the Blackwell forward path, but some of this is inference from the shared warp-specialization/aref/TMEM lowering stack rather than an explicit “this emits `tcgen05.mma`” statement in the tutorial, so exact coverage should be treated as partially needs-verification. - Introducing PRs/commits: same core Blackwell and warp-specialization lowering series as above, especially `#8262`, `#7826`, `#8009`, `#8136`, `#8148`, `#8202`, `#8386`, `#8421`, `#8495`, `#8102`, `#8338`. - Caveats: the tutorial explicitly ties some forward-path behavior to Blackwell, including the FP8 non-transposed-`V` case. This is not evidence that all attention modes, backward paths, or production attention kernels are equally mature on SM100. +## What the compiler evidence proves -- Pathway: `tl.dot_scaled` / block-scaled matmul on Blackwell. - Lowers to `tcgen05` / TMEM on SM100: yes for the supported hardware-accelerated Blackwell path. The official block-scaled matmul tutorial says these kernels are hardware-accelerated by fifth-generation Tensor Cores on compute capability 10, and the 3.6 dialect docs expose `ttng.tc_gen5_mma_scaled` with TMEM-token semantics plus `ttng.tmem_copy`. - Introducing PRs/commits: Gluon NVIDIA `tcgen05 mma scaled` support `#8393`; frontend fixes around `dot_scaled` `#8564` and `#8658`; shared TMEM / `tcgen05` backend work `#8136`, `#8148`, `#8202`. - Caveats: this path is format- and layout-constrained. The checked tutorial is centered on NVFP4 / MXFP formats and notes that mixed-precision extensions are still future work. +The exact v3.3.0 tree proves that native Blackwell TCGen5/TMEM compiler machinery and tested lowering exist. The v3.5.0 tutorials prove explicit user-visible examples for Gluon TCGen5/TMEM and `tl.dot_scaled` block-scaled matmul by that tag. The v3.6.0 notes prove additional Blackwell work, not first introduction. -- Pathway: Gluon front-end `gl.warp_specialize`, `num_ctas`, and multi-CTA / 2CTA Blackwell lowering. - Lowers to `tcgen05` / TMEM on SM100: yes. This is the most explicit Blackwell-native surface in the checked 3.6 materials: the release notes call out initial 2CTA support in Gluon, `num_ctas`, multi-CTA support, and `tcgen05 mma scaled` support, while the dialect docs expose TMEM allocation/copy and `tc_gen5_mma` / `tc_gen5_mma_scaled` ops directly. - Introducing PRs/commits: Gluon API and multi-CTA work `#8527`, `#8468`, `#8587`, `#8602`, `#8644`; Blackwell backend 2CTA / cluster work `#8644`, `#8653`, `#8645`; Gluon NVIDIA `tcgen05 mma scaled` `#8393`. - Caveats: the release notes describe this as initial support, so cluster-scope and 2CTA usage should still be treated as early-stage. This is also a Gluon-first story; it is stronger evidence for “Triton can target Blackwell natively” than for “classic `tl.dot` is universally first-class on SM100.” +None of those facts implies that arbitrary plain `tl.dot` kernels select TCGen5 for every dtype, layout, shape, architecture, or compiler configuration. A target-specific selection claim needs inspectable IR or PTX from that configuration. -## Caveats and Open Questions -- The old wiki claim “Triton compiler generates wgmma, not tcgen05” is no longer globally correct for Triton 3.6+, but the replacement should be qualified: native `tcgen05` + TMEM paths exist on SM100, especially through warp-specialized descriptor/TMA and Gluon flows. -- The old wiki claim “No TMEM: accumulators stay in registers” is also outdated as a blanket statement. The checked 3.6 dialect docs explicitly model TMEM allocation/copy/load/store and `tc_gen5_mma` / `tc_gen5_mma_scaled` ops with TMEM-token semantics. -- What remains weaker than CuTe-DSL / CUTLASS hand-written Blackwell kernels is production peak-performance coverage. In SGLang `pr-sglang-5390`, a CUTLASS `tcgen05_mla` backend reports about 27% higher throughput than the Triton baseline on Blackwell for MLA decode. -- Downstream routing decisions still show Triton is not the universal best path on Blackwell. In `pr-sglang-21595`, SGLang changes Blackwell datacenter multimodal attention default from `triton_attn` to `fa4`; in `pr-sglang-21914`, SGLang sets TRT-LLM kernels as the default for Blackwell. -- The clearest generally-available Blackwell story in checked sources is not “plain `tl.dot` everywhere,” but “warp-specialized descriptor/TMA kernels and Gluon multi-CTA/2CTA kernels.” Anything beyond that should be marked needs-verification until backed by PTX/IR or a downstream merged PR. -- A policy update from “narrow” toward “first-class” is justified, but only with qualifiers. Recommended interpretation: Triton 3.6+ is first-class for supported Blackwell-native lowering paths and for serious prototyping on SM100, but it is still not the default peak-performance answer for all compute-bound production kernels. -- Open question: find a downstream merged PR in `pytorch`, `vllm`, `sglang`, or `flashinfer` that explicitly depends on Triton 3.6+ and shows `ttng.tc_gen5_mma` / `tcgen05.*` emission for an SM100 Triton kernel. I could not verify that exact anchor from checked downstream sources, so this remains needs-verification. +## Downstream evidence and limits -## Evidence References +- `pr-vllm-34597`, pinned at merge SHA `a1257fd1`, adds FP8 KV-cache handling to vLLM's generic Triton MLA decode backend. Its kernel contains `tl.dot`; neither the PR nor exact code supplies an SM100 guard, a Triton-version pin, a TCGen5/TMEM symbol, or emitted PTX. The PR specifically motivates the backend as the MLA option available on SM120. +- `pr-vllm-29339`, pinned at `c17610e2`, gates MXFP4 `triton_kernels` dispatch to SM90 and SM100. It changes dispatch code, not a Triton kernel or compiler lowering. +- `pr-sglang-21019`, pinned at `5bdc07d9`, contains a Triton GatedDeltaNet projection rearrangement using loads and stores, with no `tl.dot`. +- `pr-sglang-22079`, pinned at `5638d40f`, contains an extend-attention Triton kernel with real `tl.dot` operations. It still contains no emitted-PTX witness for a particular MMA instruction. -### Primary anchors +These artifacts verify downstream Triton use. They do not independently verify which backend instruction any target selects. -- `doc-triton-3.6-blackwell` — Triton 3.6 release notes / official tutorial and dialect-doc summary covering TMEM, `tcgen05`, `warp_specialize`, `num_ctas`, 2CTA mode, and `tcgen05 mma scaled` on Blackwell. (`source_category: official-doc`, file at `sources/docs/triton-3.6-blackwell.md`.) +## Scoped ecosystem observations -The complete primary-anchor set comprises one official-doc anchor and one **post-refresh** downstream upstream-code anchor (per AC-1.1's "at least one **new** `sources/prs//PR-.md` page" contract — "new" = not present in `data/refresh-cutoff.yaml::previous_pages_manifest`): -- `pr-vllm-34597` — **primary post-refresh downstream upstream-code anchor**: vLLM PR titled "[Kernel] Add FP8 KV cache support to Triton MLA decode attention" (merged `2026-02-16` on `architectures: [sm100]`, post-Triton-3.6.0 release date `2026-01-21`). This PR directly modifies actual Triton kernel files — `vllm/v1/attention/ops/triton_decode_attention.py` (the `@triton.jit`-decorated MLA decode kernel doing `tl.dot(q, k)` / `tl.dot(qpe, kpe)` / `tl.dot(p, v)` matmul) and `vllm/v1/attention/backends/mla/triton_mla.py` (the backend wrapping it). The kernel is shipped verbatim under `artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py` (756 lines, pinned at upstream SHA `a1257fd1`), so the AC-1.1 demonstration is grounded in a checked-in, inspectable Triton kernel rather than inference. Tags: `attention`, `decode`, `fp8`, `mla`. (`source_category: upstream-code`, `languages: [triton]`, `inclusion_reason: kernel file changes`.) -- `pr-vllm-29339` — **secondary post-refresh anchor**: vLLM bugfix that scopes the upstream `triton_kernels` library (the `triton-lang/triton/python/triton_kernels` collection shipped with Triton 3.6) to `architectures: [sm100, sm90]` only for the MXFP4 quantization path, after issues appeared on SM110/SM120. Merged `2025-11-24`. This PR's value is showing the Triton 3.6 SM100 kernel library being explicitly gated to Blackwell production codepaths, but it only modifies a dispatch gate (`vllm/model_executor/layers/quantization/mxfp4.py`) rather than a Triton kernel itself — that is why `pr-vllm-34597` is preferred as primary. Retained as supplementary post-refresh evidence. (`source_category: upstream-code`, `languages: [triton]`.) +SGLang PR 5390 reports one DeepSeek-R1 MLA benchmark in which the CUTLASS run records 10,447.34 total tok/s and the Triton run 8,227.35 total tok/s, a 26.98% difference under the PR's recorded 3,000-prompt, TP8/DP8, float16, 1,000-input/1,000-output-token scope. It is not a universal language comparison. -#### Pre-refresh historical anchors (retained for context, no longer count toward AC-1.1) +SGLang PR 21595 changes the SM100 datacenter multimodal-attention default from `triton_attn` to FA4. This is a scoped routing decision, not evidence about every Blackwell workload. -The following anchors existed before the Round-6 refresh (each appears in `data/refresh-cutoff.yaml::previous_pages_manifest`). They remain useful as substantive evidence but do NOT satisfy AC-1.1's "new tracked-repo PR page" contract on their own: -- `pr-sglang-22079` — pre-refresh secondary anchor: a real Triton attention kernel doing actual `tl.dot(q, k)` / `tl.dot(p, v)` matmul on `architectures: [sm100, sm90]`, merged on `2026-04-03` (well after Triton 3.6.0 released `2026-01-21`). The kernel is the SGLang `extend_attention` Triton kernel for the Gemma4 NVFP4 attention path; tags include `attention`, `nvfp4`, `fp4`, `gemm`, `tcgen05`-relevant block-scaled matmul. Ships verbatim under `artifacts/prs/sglang/PR-22079/key-files/python/sglang/srt/layers/attention/triton_ops/extend_attention.py`. This remains the strongest in-corpus example of a real `tl.dot` Triton matmul kernel landing for SM100 post-3.6 in the *pre-refresh* corpus, but it is pre-refresh per the `previous_pages_manifest`. (`source_category: upstream-code`, `languages: [python, triton]`.) -- `pr-sglang-21019` — pre-refresh secondary anchor: `@triton.jit`-decorated kernel (`fused_qkvzba_split_reshape_cat_kernel` for Qwen3.5 GDN projection) landed for `architectures: [sm100]` on `2026-03-20`. This kernel is `tl.load`/`tl.store` only (memory rearrangement, no `tl.dot`), so it demonstrates "Triton on SM100 post-3.6" but not the matmul lowering surface. Retained as supplementary historical context. +The live FlashInfer-Bench author leaderboard retrieved 2026-08-08 reports Gemini 2.5 Pro at 0.628x and 73.1% resolved, GPT-5 at 0.467x and 92.3%, and Claude Opus 4.1 at 0.456x and 73.1%, each over 660 workloads. The page does not attach those rows to a Triton version or a Triton-only language subset. -### Caveat / ecosystem-readiness anchors +## Open proof obligation -- `pr-sglang-5390` — downstream upstream-code anchor (caveat): CUTLASS `tcgen05_mla` backend outperforming the Triton MLA decode baseline by ~27% on Blackwell. Demonstrates that Triton's Blackwell coverage is not yet at peak parity with hand-written CUTLASS for compute-bound workloads. (`source_category: upstream-code`.) -- `pr-sglang-21595` — downstream upstream-code anchor (caveat): Blackwell multimodal attention default changed from `triton_attn` to FA4 in datacenter SKUs. Demonstrates that production routing decisions still favor non-Triton kernels for some Blackwell paths. (`source_category: upstream-code`.) -- `pr-pytorch-175826` — downstream upstream-code anchor (ecosystem-readiness): PyTorch inductor CI's B200 / SM100 lane moved to CUDA 13.0, reflecting the broader Blackwell toolchain maturation. (`source_category: upstream-code`.) - -### Note on anchor scope - -The plan's AC-1.1 positive test reads "At least one **new** `sources/prs//PR-.md` page demonstrates a kernel that lowers through the Triton 3.6 Blackwell path." This contract has two parts: (a) the page must be *new* (not in `data/refresh-cutoff.yaml::previous_pages_manifest`); (b) the page must *demonstrate a kernel*, not just gate logic. - -Round 6 cited `pr-sglang-22079` etc., which were `tl.dot` kernels but pre-refresh — they failed (a). Round 7 swapped to `pr-vllm-29339`, which was post-refresh but only modifies a dispatch gate (`vllm/model_executor/layers/quantization/mxfp4.py`) — it satisfied (a) but only weakly satisfied (b) by inference about the upstream `triton_kernels` library. **Round 8 promotes `pr-vllm-34597` to primary anchor**: the page is post-refresh AND it directly modifies actual Triton kernel files (`vllm/v1/attention/ops/triton_decode_attention.py` containing `@triton.jit` MLA decode kernel with `tl.dot(q, k)` / `tl.dot(qpe, kpe)` / `tl.dot(p, v)` matmul, plus `vllm/v1/attention/backends/mla/triton_mla.py`). The Triton kernel itself is shipped verbatim under `artifacts/prs/vllm/PR-34597/key-files/...` (pinned at merge SHA `a1257fd1`), so the AC-1.1 demonstration is now grounded in inspectable kernel code rather than dispatch-gate inference. `pr-vllm-29339` is retained as supplementary post-refresh evidence; pre-refresh `pr-sglang-22079` / `pr-sglang-21019` are retained as historical context. - -The strongest possible demonstrations — explicit inspectable PTX showing `tcgen05.mma` emission, or kernels using `tl.dot_scaled` / `warp_specialize` with descriptor/TMA structure — were not found in any tracked-repo PR locally. They currently live in the upstream Triton tutorials. A future refresh round should backfill such an anchor if one becomes available in tracked downstream repos. - -## Recommended wiki rewrite framing -- Triton 3.6 materially changes the Blackwell story. -- The old blanket claim that Triton on SM100 only emits WGMMA with register-resident accumulators is no longer correct. -- Triton 3.6 adds native Blackwell lowering infrastructure for `tcgen05` and TMEM, with the clearest documented path running through warp-specialized descriptor/TMA kernels and newer Gluon multi-CTA / 2CTA support. -- The important qualifier is that this is not yet proof that every plain `tl.dot` kernel on SM100 automatically becomes a TMEM-backed `tcgen05` kernel. -- Treat Triton 3.6+ as a first-class Blackwell language for supported warp-specialized matmul/attention building blocks and block-scaled GEMM. -- Keep CuTe-DSL / CUTLASS / FA4 / TRT-LLM as the expected leaders for many peak-performance production attention and decode kernels. -- Replace “no tcgen05 / no TMEM” with “native `tcgen05` + TMEM paths now exist, but coverage and performance leadership are workload-dependent.” +The checked downstream bundles contain no explicit TCGen5 PTX dump or warp-specialized descriptor/TMA lowering record. Until such evidence is captured for a specific kernel, architecture, dtype, shape, and toolchain, the wiki must not infer exact instruction selection from `tl.dot` source alone. diff --git a/data/triton-universe.yaml b/data/triton-universe.yaml index d548534c7..2e205021c 100644 --- a/data/triton-universe.yaml +++ b/data/triton-universe.yaml @@ -4,8 +4,8 @@ lane: triton generated_by: scripts/compute_core_prs.py total: 267 -captured: 117 -skipped: 150 +captured: 116 +skipped: 151 prs: - id: pr-TensorRT-LLM-10327 captured: false @@ -665,7 +665,8 @@ prs: - id: pr-vllm-33529 captured: true - id: pr-vllm-34597 - captured: true + captured: false + skipped_reason: Triton PR outside the three in-policy sub-scopes - id: pr-vllm-35382 captured: false skipped_reason: Triton PR outside the three in-policy sub-scopes diff --git a/data/version-claims.yaml b/data/version-claims.yaml index 398e76333..0da97a675 100644 --- a/data/version-claims.yaml +++ b/data/version-claims.yaml @@ -19,48 +19,23 @@ ## paths exist + carry the matching pointer. claims: - - id: vs-triton-3.6-blackwell-tcgen05 + - id: vs-triton-3.3-blackwell-tcgen05 tool: triton - claim_valid_for: ">=3.6" - last_verified_release: "3.6.0" - last_verified_at: 2026-04-27 + claim_valid_for: ">=3.3" + last_verified_release: "3.7.1" + last_verified_at: 2026-08-08 applies_to: - wiki/languages/triton-blackwell.md - references/primer.md - references/examples.md - data/inclusion-policy.yaml::triton.description source_ids: + - doc-triton-3.3-blackwell - doc-triton-3.6-blackwell - - pr-vllm-34597 - - pr-vllm-29339 - - pr-sglang-22079 - - pr-sglang-21019 - - pr-sglang-5390 - - pr-sglang-21595 - - pr-pytorch-175826 notes: | - Tracks the claim that Triton 3.6+ has native Blackwell (SM100) lowering - paths through tcgen05.mma + TMEM (descriptor/TMA + warp_specialize on - tl.dot, plus Gluon multi-CTA + 2CTA on tcgen05_mma_scaled), replacing - the obsolete 3.5-era "no tcgen05 / no TMEM" framing. Supporting evidence: - data/triton-3.6-evidence.md memo plus the official release notes - (doc-triton-3.6-blackwell). AC-1.1 "new tracked-repo PR page demonstrates - a kernel" anchor: pr-vllm-34597 (post-refresh; vLLM "[Kernel] Add FP8 KV - cache support to Triton MLA decode attention", merged 2026-02-16, sm100, - directly modifying @triton.jit kernels in vllm/v1/attention/ops/ - triton_decode_attention.py with tl.dot matmul + vllm/v1/attention/ - backends/mla/triton_mla.py; Triton kernel shipped verbatim under - artifacts/prs/vllm/PR-34597/ pinned at SHA a1257fd1). Supplementary - post-refresh anchor: pr-vllm-29339 (Triton 3.6 triton_kernels library - scoped to [sm100, sm90] for MXFP4 dispatch-gate, merged 2025-11-24). - Pre-refresh historical anchors retained as supplementary context (each - appears in data/refresh-cutoff.yaml::previous_pages_manifest): - pr-sglang-22079 (Gemma4 NVFP4 Triton attention kernel doing real tl.dot - matmul on [sm100, sm90], merged 2026-04-03), pr-sglang-21019 - (memory-rearrangement Triton kernel on SM100, merged 2026-03-20, no - tl.dot), pr-sglang-5390, pr-sglang-21595, pr-pytorch-175826 (ecosystem - context). The strongest possible demonstrations of the 3.6 Blackwell- - native paths (descriptor/TMA + warp_specialize, tl.dot_scaled, Gluon - multi-CTA/2CTA) have NOT been found in any tracked-downstream merged - PR locally; future refresh rounds should backfill such an anchor when - one becomes available. + Exact tag comparison places native TCGen5/TMEM compiler support between + v3.2.0 and v3.3.0. Triton v3.6.0 is an incremental expansion of copies, + layouts, warp specialization, and initial multi-CTA/2-CTA Gluon paths; + it is not the introduction boundary. The latest checked stable release + is v3.7.1. This version claim does not assert that every plain tl.dot + shape selects TCGen5; that requires configuration-specific IR or PTX. diff --git a/queries/by-hardware-feature.md b/queries/by-hardware-feature.md index 988772a5a..83d61accb 100644 --- a/queries/by-hardware-feature.md +++ b/queries/by-hardware-feature.md @@ -4,18 +4,20 @@ | Feature | Related Pages | |---------|--------------| -| `2sm-cooperative` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax CUTLASS Tutorial: GEMM Kernels Using Tensor Memory for Blackwell](../sources/blogs/colfax-cutlass-blackwell.md), [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [CUTLASS Cluster Launch Control (CLC) Documentation](../sources/docs/cutlass-clc-documentation.md), [FlashAttention-4: Hardware-Friendly Attention on Blackwell](../sources/docs/flash-attention-4.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [Triton 3.6.0 Release Notes — Blackwell (SM100) Lowering](../sources/docs/triton-3.6-blackwell.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [fix: examples/cute/tutorial/blackwell/04_mma_tma_2sm_sm100.cu GridDim miscalculated](../sources/prs/cutlass/PR-2492.md), [Feat([FA4][CUTE DSL]) Add head_dim=256 support (forward + backward)](../sources/prs/flash-attention/PR-2412.md), [[hd256] Improve forward kernel with exp2 FMA emulation (3% to 9% performance gain)](../sources/prs/flash-attention/PR-2488.md), [[hd256] Add TMA paged KV support to SM100 2CTA forward kernel](../sources/prs/flash-attention/PR-2489.md), [[FA4][hd256] Backward TMA bulk-store epilogue + LSE/dpsum coalesce](../sources/prs/flash-attention/PR-2497.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [Two-SM Cooperative MMA](../wiki/hardware/2sm-cooperative.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [Not Reaching Peak FLOPS](../wiki/patterns/compute-bound.md) | -| `block-scale` | [Twelve Attempts at NVFP4 Batched GEMV](../sources/blogs/amandeep-nvfp4-attempts.md), [DeepGEMM — FP8 GEMM Library](../sources/blogs/deepgemm.md), [NVFP4 Format Details](../sources/blogs/nvfp4-format-details.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Triton 3.6.0 Release Notes — Blackwell (SM100) Lowering](../sources/docs/triton-3.6-blackwell.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [feat: enable deepgemm jit for fp8 block-scale on SM90](../sources/prs/flashinfer/PR-1969.md), [feat: Support unpadded output hidden size for trtllm_fp4_block_scale_moe](../sources/prs/flashinfer/PR-2217.md), [fix: trtllm_mxint4_block_scale_moe unit test to index output list](../sources/prs/flashinfer/PR-2627.md), [int16 Block-Scaled State and Stochastic Rounding for SSU (mamba)](../sources/prs/flashinfer/PR-2645.md), [Support in-place update for `trtllm_fp8_block_scale_moe`](../sources/prs/flashinfer/PR-2739.md), [fix: int32 overflow in `trtllm_fp4_block_scale_moe` causing "Unsupported hidden state scale shape" for EP32+ configs](../sources/prs/flashinfer/PR-2853.md), [fix: snap weight_scale_vec_size to handle block_scale_interleave padding for SM120](../sources/prs/flashinfer/PR-2898.md), [fix: Fix autotuner crash on meta-device tensor in trtllm_fp4_block_scale_routed_moe](../sources/prs/flashinfer/PR-2916.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [[Perf] Eliminate the slice op for Flashinfer `trtllm_fp4_block_scale_moe`](../sources/prs/sglang/PR-15731.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[FEAT] [ROCm]: Add AITER Block-Scaled GEMM Feature](../sources/prs/vllm/PR-14968.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [[Bugfix] Handle num_expert_group=None in flashinfer block-scale FP8 MoE](../sources/prs/vllm/PR-34494.md), [NVFP4 and Block-Scaled Narrow Precision](../wiki/hardware/nvfp4.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [FP8 Block-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [Fused MoE — FP8 Block-Scale Routing + Dual GEMM](../wiki/kernels/fused-moe.md), [NVFP4 GEMM — 4-bit Floating Point Matrix Multiply](../wiki/kernels/nvfp4-gemm.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md), [Fine-Grained FP8/FP4 Quantization](../wiki/techniques/fine-grained-quantization.md) | -| `clc` | [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [CUTLASS Cluster Launch Control (CLC) Documentation](../sources/docs/cutlass-clc-documentation.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [[Cute-DSL] Add option for issue_clc_query without multicast](../sources/prs/cutlass/PR-3021.md), [[Ai-assisted] CLC work stealing](../sources/prs/flash-attention/PR-2218.md), [Add CLC scheduler heuristic](../sources/prs/flash-attention/PR-2455.md), [[V1][P/D]P2pNcclConnector supports flashinfer](../sources/prs/vllm/PR-23536.md), [Cluster Launch Control (CLC)](../wiki/hardware/clc.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Low SM Utilization](../wiki/patterns/low-sm-utilization.md), [MoE Expert Load Imbalance](../wiki/patterns/moe-load-imbalance.md), [Tail Effect — Last Wave Underutilization](../wiki/patterns/tail-effect.md), [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md), [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md) | -| `cluster` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [CUTLASS Cluster Launch Control (CLC) Documentation](../sources/docs/cutlass-clc-documentation.md), [Two-SM Cooperative MMA](../wiki/hardware/2sm-cooperative.md) | -| `fp4` | [Twelve Attempts at NVFP4 Batched GEMV](../sources/blogs/amandeep-nvfp4-attempts.md), [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Anatomy of a Reward Hack](../sources/blogs/gpu-mode-reward-hack.md), [NVFP4 Format Details](../sources/blogs/nvfp4-format-details.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.](../sources/prs/TensorRT-LLM/PR-10339.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[None][feat] Optimize super-v3 nvfp4 for better perf](../sources/prs/TensorRT-LLM/PR-11273.md), [[None][feat] Optimize by fuse nvfp4_quant to layernorm_gated for mamba2_mixer](../sources/prs/TensorRT-LLM/PR-11473.md), [[None][feat] Add support for expert_number<=2048 and K<=32](../sources/prs/TensorRT-LLM/PR-11510.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[None][fix] Fix SM120 issue for rms_norm with nvfp4_quant_fusion](../sources/prs/TensorRT-LLM/PR-11774.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[None][feat] Update rms_norm + fp4_qaunt kernel supporting more dim](../sources/prs/TensorRT-LLM/PR-13033.md), [[None][feat] Add FP4 residual quantization kernel without channel reo…](../sources/prs/TensorRT-LLM/PR-13117.md), [[None][feat] Integrate FP4 indexer for DSA on Blackwell](../sources/prs/TensorRT-LLM/PR-13340.md), [[TRTLLM-11127][feat] add W4A8_MXFP4_FP8 MoE unit test support](../sources/prs/TensorRT-LLM/PR-13401.md), [[TRTLLM-12316][feat] Integrate FP4 indexer for DSv4](../sources/prs/TensorRT-LLM/PR-13575.md), [[TRTLLM-12503][feat] Parallel VAE independent scaling and fix arg passing](../sources/prs/TensorRT-LLM/PR-13873.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[https://nvbugs/6025177][test] rcca tests using kimi k2.5 fp4](../sources/prs/TensorRT-LLM/PR-14172.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[None][feat] add fp4 gemm + allreduce](../sources/prs/TensorRT-LLM/PR-9729.md), [[None][feat] Port fp4 quantization kernel optimization from FlashInfer](../sources/prs/TensorRT-LLM/PR-9854.md), [bugfix: Fix test and output shape of fp4 quantize](../sources/prs/flashinfer/PR-1114.md), [Add fp4 quantization swizzling tests](../sources/prs/flashinfer/PR-1157.md), [Expose fp4 blockscale swizzling kernel](../sources/prs/flashinfer/PR-1176.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [Reduce the JIT compilation time of gen_gemm_sm100_module](../sources/prs/flashinfer/PR-1251.md), [add mm_fp4 use cudnn backend](../sources/prs/flashinfer/PR-1288.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [add cutlass backend for mm_fp4](../sources/prs/flashinfer/PR-1296.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [Support loading autotuned results from json for cutlass fp4 moe backends](../sources/prs/flashinfer/PR-1310.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [feat: masked layout fp4 gemm using cute-dsl](../sources/prs/flashinfer/PR-1331.md), [add torch float4_e2m1fn_x2 check for cudnn fp4 backend](../sources/prs/flashinfer/PR-1333.md), [[Fix] remove torch 2.8 requirement for FP4 GEMM](../sources/prs/flashinfer/PR-1334.md), [feature: add fp4 mm using trtllm backend](../sources/prs/flashinfer/PR-1355.md), [hotfix: update mxfp4 groupwise-scaled gemm unittests](../sources/prs/flashinfer/PR-1359.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Update autotune results for the nvfp4 cutlass moe backends for v0.2.9](../sources/prs/flashinfer/PR-1361.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [bugfix: fixed cutlass fused moe usage of FP4QuantizationSFLayout::SWIZZLED](../sources/prs/flashinfer/PR-1371.md), [bugfix: Add guard for fp4/fp8 related include headers](../sources/prs/flashinfer/PR-1376.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [Add Mxfp4 trtllm-gen moe unit tests](../sources/prs/flashinfer/PR-1399.md), [feature: enable cublas for fp4 gemm when cudnn == 9.11.1 or >= 9.13](../sources/prs/flashinfer/PR-1405.md), [Faster weight processing (moe nvfp4)](../sources/prs/flashinfer/PR-1412.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [tuner: Trtllm-gen Fp4 MoE Autotunner](../sources/prs/flashinfer/PR-1475.md), [fix missing enable_pdl argument in trtllm-gen fp4 moe](../sources/prs/flashinfer/PR-1480.md), [Add python API for masked grouped gemm](../sources/prs/flashinfer/PR-1481.md), [fix: update masked moe gemm fp4 tensor reshape](../sources/prs/flashinfer/PR-1495.md), [feat: scaling at fp4 gemm epilogue](../sources/prs/flashinfer/PR-1498.md), [refactor fp4 masked gemm cute-dsl implementation and add manual cache](../sources/prs/flashinfer/PR-1521.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [fix: separate out fp4 lib into sm90 and sm100 versions, add oob checking in fused moe](../sources/prs/flashinfer/PR-1565.md), [update trtllm-gen fp4 autotuner and routing](../sources/prs/flashinfer/PR-1573.md), [bugfix: Fix test_fp4_quantize test bug](../sources/prs/flashinfer/PR-1585.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [feat: cutlass fp4 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1609.md), [bugfix: fix fp4 quantization with 8x4 scale factor layout](../sources/prs/flashinfer/PR-1611.md), [feat: add support of fp4_batched_quantize](../sources/prs/flashinfer/PR-1633.md), [Added mx_fp4 support using the cudnn backend](../sources/prs/flashinfer/PR-1644.md), [[Hotfix] `test_fp4_quantize.py` failure on sm103](../sources/prs/flashinfer/PR-1666.md), [feat: Benchmark mm_fp4 mxfp4 support and gemm autotune support. Restore mm_fp4 API behavior](../sources/prs/flashinfer/PR-1706.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [Added xfail for mx_fp4 matmul on SM120](../sources/prs/flashinfer/PR-1766.md), [Masked batch nvfp4 quantization](../sources/prs/flashinfer/PR-1774.md), [Support checks PoC](../sources/prs/flashinfer/PR-1809.md), [fix: fp4 moe on sm120](../sources/prs/flashinfer/PR-1817.md), [[Quantization] Add per-expert global scaling factor for fp4 batched quantize](../sources/prs/flashinfer/PR-1835.md), [raise error for group_gemm_fp8_nt_groupwise then num_groups > 1 on sm120/121](../sources/prs/flashinfer/PR-1862.md), [feat: Add FP4 TRTLLM-Gen throughput MOE batched gemms](../sources/prs/flashinfer/PR-1882.md), [silu_and_mul nvfp4 quanization fusion rework](../sources/prs/flashinfer/PR-1927.md), [fix: Add cutlass as an mm_fp4 backend in compute capability 12.0 in benchmark code](../sources/prs/flashinfer/PR-1959.md), [feat: Add backend='auto' to mm_fp4 and enable autotune for backend='cudnn'](../sources/prs/flashinfer/PR-1979.md), [Feature: Support non-gated activation in cutlass fused MoE nvfp4](../sources/prs/flashinfer/PR-2011.md), [fix: Enable SM121 for mm_fp4](../sources/prs/flashinfer/PR-2012.md), [[DSV3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2019.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE](../sources/prs/flashinfer/PR-2025.md), [[BUG] Fix trtllm-gen fp4 moe renormalize routing](../sources/prs/flashinfer/PR-2049.md), [Patch sm103 for 3xfp4 moe generation](../sources/prs/flashinfer/PR-2082.md), [perf: enable pdl for cutlass fp4 gemm](../sources/prs/flashinfer/PR-2095.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [Add data type check for deepseek fp4 moe](../sources/prs/flashinfer/PR-2165.md), [feat: Support unpadded output hidden size for trtllm_fp4_block_scale_moe](../sources/prs/flashinfer/PR-2217.md), [feat: Fused RMSNorm + FP4 Quantization Kernels in CuTe-DSL](../sources/prs/flashinfer/PR-2233.md), [fix: Add global scale support and optional output allocation for RMSNorm+FP4Quant fusion kernels](../sources/prs/flashinfer/PR-2260.md), [[performance]optimize for nvfp4](../sources/prs/flashinfer/PR-2268.md), [[WIP] Refactor: simplify torch -> cute-dsl boilerplate and enable tvm-ffi for cute-dsl kernels](../sources/prs/flashinfer/PR-2279.md), [[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels](../sources/prs/flashinfer/PR-2303.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [Optimize quantization function in large problem size](../sources/prs/flashinfer/PR-2343.md), [fix: In-place Residual Update for add_rmsnorm_fp4quant](../sources/prs/flashinfer/PR-2385.md), [feat: Add output_both_sf_layouts option to add_rmsnorm_fp4quant API](../sources/prs/flashinfer/PR-2395.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [perf: mm_fp4 heuristic prioritizes CUTLASS over cuDNN on SM103](../sources/prs/flashinfer/PR-2404.md), [refactor: simplify fp4 rmsnorm](../sources/prs/flashinfer/PR-2421.md), [refactor: refactoring cuda code to cute-dsl (part 1)](../sources/prs/flashinfer/PR-2428.md), [Add cute-dsl backends to mxfp[8,4]_quantization for future refactor](../sources/prs/flashinfer/PR-2443.md), [perf: add fp4 GEMM tile configs and streamK scheduler for SM120](../sources/prs/flashinfer/PR-2460.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [feat: cute dsl mmfp4 for blackwell](../sources/prs/flashinfer/PR-2540.md), [[Bugfix][comm] Fix FP4 one-shot launch config instability in trtllm_allreduce_fusion](../sources/prs/flashinfer/PR-2557.md), [[Bug] Fix spark unit test failures for test_add_rmsnorm_fp4_quant_cute_dsl](../sources/prs/flashinfer/PR-2573.md), [tests: add bias testing to nvfp4 moe](../sources/prs/flashinfer/PR-2585.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [benchmark: Add MXFP4/MXFP8 quantization mode support to FP4 MoE benchmark](../sources/prs/flashinfer/PR-2635.md), [Enable sm120f compilation](../sources/prs/flashinfer/PR-2650.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [feat: support mxfp4 & mxfp8 entrypoint for blackwell cutedsl dense gemm](../sources/prs/flashinfer/PR-2660.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [fix: Add SM120 (RTX Blackwell desktop) support for NVFP4 MoE kernels](../sources/prs/flashinfer/PR-2725.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [feat: Add FP4 KV cache quant/dequant kernels ](../sources/prs/flashinfer/PR-2757.md), [feat: Add CuTe-DSL backend for NVFP4 quantization](../sources/prs/flashinfer/PR-2838.md), [fix: int32 overflow in `trtllm_fp4_block_scale_moe` causing "Unsupported hidden state scale shape" for EP32+ configs](../sources/prs/flashinfer/PR-2853.md), [fix: snap weight_scale_vec_size to handle block_scale_interleave padding for SM120](../sources/prs/flashinfer/PR-2898.md), [perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels](../sources/prs/flashinfer/PR-2904.md), [fix: Fix autotuner crash on meta-device tensor in trtllm_fp4_block_scale_routed_moe](../sources/prs/flashinfer/PR-2916.md), [CuTe DSL FP4 GEMM Heuristic](../sources/prs/flashinfer/PR-2940.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [ Fix MXFP4/MXFP8 failures in SM120 FAST_BUILD and expand all_tiles[] ](../sources/prs/flashinfer/PR-2994.md), [feat: add PDL support to rmsnorm_fp4quant and add_rmsnorm_fp4quant CuTe DSL kernels](../sources/prs/flashinfer/PR-3008.md), [perf: Port TRT-LLM SM120/SM121 FP4 CUTLASS GEMM optimizations. Add PDL](../sources/prs/flashinfer/PR-3026.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [feat: Add backend="b12x" for mm_fp4 on SM120](../sources/prs/flashinfer/PR-3051.md), [feat: Add b12x CuTe DSL fused MoE for SM120](../sources/prs/flashinfer/PR-3066.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [perf: optimize per-token nvfp4 quantization kernel.](../sources/prs/flashinfer/PR-3237.md), [feat(moe): add SM120 W4A16 b12x kernels](../sources/prs/flashinfer/PR-3271.md), [feat: Add FP4 (E2M1) KV Cache Support with Quantization Utilities for MLA](../sources/prs/sglang/PR-10078.md), [Optimize nvfp4 block scaled gemm kernel when M is small.](../sources/prs/sglang/PR-10101.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [feat: add dsv3 fp4 cutlass moe etp ut](../sources/prs/sglang/PR-10433.md), [Fix bias handling in TritonMoeQuantInfo within quantization/mxfp4.py](../sources/prs/sglang/PR-10579.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [Use cutlass fp4 gemm by default](../sources/prs/sglang/PR-11813.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [Replace [silu_and_mul_]scaled_fp4_group_quant by Flashinfer equivalent](../sources/prs/sglang/PR-12376.md), [Use sgl fp4 quant kernel by default](../sources/prs/sglang/PR-12482.md), [[NVIDIA] Fix CUDA arch requirement in nvfp4 cast](../sources/prs/sglang/PR-12581.md), [feat: Add FP4 (E2M1) KV Cache Support for MHA](../sources/prs/sglang/PR-12612.md), [[NVIDIA] Fix wrong symmetric sizes for fp4 cases](../sources/prs/sglang/PR-12640.md), [[Bugfix] Fix illegal memory access](../sources/prs/sglang/PR-12758.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [Fix EPLB + FP4 Quantization Compatibility Issue](../sources/prs/sglang/PR-13715.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [Fix flashinfer cutlass MoE output shape for non-FP4-packed inputs](../sources/prs/sglang/PR-14028.md), [[FIX] trtllm-moe-fp4-renorm for Qwen series models](../sources/prs/sglang/PR-14350.md), [[CPU] Implement MXFP4 Gemm kernels for intel AMX to support GPT OSS series.](../sources/prs/sglang/PR-14385.md), [Mistral Large 3 NVFP4 support](../sources/prs/sglang/PR-14485.md), [[AMD] Support fused_rms_mxfp4_quant in the prefill stage for DeepSeek-R1-MXFP4](../sources/prs/sglang/PR-14975.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [[NVIDIA] Fixes for NVFP4 all-gather with spec decoding](../sources/prs/sglang/PR-15280.md), [Fix the accuracy issue when running mxfp4 dsv3 model and enable ep](../sources/prs/sglang/PR-15304.md), [Update flashinfer to 0.6.1](../sources/prs/sglang/PR-15551.md), [[Perf] Eliminate the slice op for Flashinfer `trtllm_fp4_block_scale_moe`](../sources/prs/sglang/PR-15731.md), [Tiny fix cannot launch nvfp4 checkpoint with bf16 kv cache](../sources/prs/sglang/PR-15986.md), [[Performance] Force split_k=1 for MXFP4 Triton kernels on Hopper](../sources/prs/sglang/PR-16014.md), [Inclusion of nvfp4 blockscale in EPLB Rebalance](../sources/prs/sglang/PR-17158.md), [[Fix] GLM 4.7 + NVFP4 + MTP](../sources/prs/sglang/PR-17166.md), [[FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/sglang/PR-17300.md), [[feat] Support nvfp4 quantized model of Qwen3-Next](../sources/prs/sglang/PR-17627.md), [fix(quantization): add sgl_kernel fallback for FP4 quantize on Blackwell GPUs](../sources/prs/sglang/PR-17816.md), [[Bugfix] Fix Mistral Large 3 NVFP4 TRTLLM MoE](../sources/prs/sglang/PR-18065.md), [Fix nvfp4 weight update](../sources/prs/sglang/PR-18085.md), [[ModelOpt] Fix broken Qwen3-235B-A22B-Instruct-2507-NVFP4 launch](../sources/prs/sglang/PR-18189.md), [[ModelOPT] Support Qwen 3 Next Coder NVFP4](../sources/prs/sglang/PR-18224.md), [[Kimi-K2.5] Fix NVFP4 Kimi-K2.5 weight mapping and exclude list](../sources/prs/sglang/PR-18370.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[Perf] ~9.5x faster Blackwell MXFP4 MoE weight loading](../sources/prs/sglang/PR-18858.md), [[Qwen3.5] Enable nvfp4 checkpoint](../sources/prs/sglang/PR-18937.md), [feat: Support MXFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-19143.md), [Adjust padding size to improve triton_kernels moe performance](../sources/prs/sglang/PR-19174.md), [Fix nightly Mistral-Large-3 NVFP4 accuracy threshold](../sources/prs/sglang/PR-19402.md), [[AMD] Fix weight load shape mismatch for amd dsr1 0528 mxfp4](../sources/prs/sglang/PR-19425.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Support `triton_kernels` for GPT-OSS on SM120](../sources/prs/sglang/PR-19718.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [Fix SM120 `triton_kernels` MXFP4 `block_k` for GPT-OSS](../sources/prs/sglang/PR-20040.md), [MiniMax-M2.5 - Support dp attention, dp reduce scatter, FP4 all gather, AR fusion in prepare_attn](../sources/prs/sglang/PR-20067.md), [[V32/GLM5] Change default setting of V32 nvfp4 on TP4](../sources/prs/sglang/PR-20086.md), [[diffusion] Support nvfp4 for Flux.2](../sources/prs/sglang/PR-20137.md), [[4/n jit_kernel restruct] speed up CI tests and add benchmark workflow](../sources/prs/sglang/PR-20268.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[Model] Support Nemotron 3 Super NVFP4](../sources/prs/sglang/PR-20407.md), [[JIT Kernel] Fix NVFP4 multi-arch compilation failure](../sources/prs/sglang/PR-20874.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Chore] Clean up JIT compilation flags](../sources/prs/sglang/PR-21022.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[NVIDIA] Enable FP4 flashinfer trtllm routed moe](../sources/prs/sglang/PR-21240.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[Kernel] Support FlashInfer TRTLLM-Gen fused MoE for non-gated FP4 & FP8 (Nemotron)](../sources/prs/sglang/PR-21321.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Add dedicated FlashInferCuteDslMoE layer for standard-path FP4 MoE](../sources/prs/sglang/PR-21339.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [Harden FlashInfer FP4 imports in standard dispatcher](../sources/prs/sglang/PR-21776.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[diffusion] Default NVFP4 to CUTLASS and add all-model shape benchmarks](../sources/prs/sglang/PR-22091.md), [[Diffusion] Add diffusion NVFP4 scaled-mm correctness test](../sources/prs/sglang/PR-22127.md), [[RL] Refactor NVFP4 shuffling/swizzling to in-place replacement](../sources/prs/sglang/PR-22204.md), [:sparkles: [diffusion][npu][quant] Add MXFP4 quantization support for Wan2.2 Diffusion on Ascend NPU](../sources/prs/sglang/PR-22338.md), [GLM-5/5.1 MXFP4 Checkpoint Inference Compatibility Fix](../sources/prs/sglang/PR-22543.md), [[Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22574.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [[Diffusion] Add Wan2.2 ModelOpt NVFP4 support](../sources/prs/sglang/PR-22681.md), [[FlashInfer v0.6.11] [RL] Support FlashInfer per-token NVFP4 MoE](../sources/prs/sglang/PR-22918.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [[MoE] Unify DeepEPMoE+MoriEPMoE through AITER MoeRunner pre/post-permute](../sources/prs/sglang/PR-23760.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [Add FlashInfer SM90 cutlass MXFP4 MoE backend (W4A16) for GPT-OSS + DeepSeek-V4](../sources/prs/sglang/PR-24816.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [perf(nvfp4): free unused source scales after weight processing](../sources/prs/sglang/PR-25107.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[AMD] Enable shared-experts fusion with new KIMI-K2.5-MXFP4 model.](../sources/prs/sglang/PR-25390.md), [[codex] Update Wan2.2 ModelOpt CI checkpoints](../sources/prs/sglang/PR-25483.md), [Add no_combine support to cutlass_moe_fp4](../sources/prs/sglang/PR-25688.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [[Build] Fix cuda12.8 build error in nvfp4_scaled_mm_kernels.cu](../sources/prs/sglang/PR-4953.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [[DeepseekR1-FP4] Add Support for nvidia/DeepSeekR1-FP4 model](../sources/prs/sglang/PR-6853.md), [Fix Deepseek R1 0528 FP4 tensor name mismatch issue during weights loading.](../sources/prs/sglang/PR-7164.md), [Support NVFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-7302.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Fix MTP with Deepseek R1 Fp4](../sources/prs/sglang/PR-7376.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [Qwen FP8/NVFP4 ModelOPT Quantization support](../sources/prs/sglang/PR-7912.md), [[Fix][Ready]Fix register spilling in cutlass nvfp4 gemm kernel on Blackwell](../sources/prs/sglang/PR-8127.md), [[fix] fix modelopt fp4 on b200](../sources/prs/sglang/PR-8195.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [[Perf] Auto enable best flashinfer mxfp4 kernel in b200](../sources/prs/sglang/PR-8898.md), [Fix hopper launch gpt-oss model illegal memory](../sources/prs/sglang/PR-8908.md), [Faster weight processing (trtllm-gen moe nvfp4)](../sources/prs/sglang/PR-9162.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [Fix FP4 inference corruption issue in glm4.5-air model](../sources/prs/sglang/PR-9346.md), [[fix] Fix mxfp4 triton MoE tp bug](../sources/prs/sglang/PR-9473.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[ModelOpt] Fix Weight Loading for DSR1-FP4 Quantization](../sources/prs/sglang/PR-9712.md), [Make fp4_quantize kernels work on sm103](../sources/prs/sglang/PR-9807.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[TMA] Support FP4 TensorMap TMA copies](../sources/prs/tilelang/PR-2107.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[NVIDIA] Support nvfp4 quantization](../sources/prs/vllm/PR-12784.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[Hardware/NVIDIA/Kernel] [Functional Enablement] [1/N] Enable nvidia/DeepSeek-R1-FP4 Model](../sources/prs/vllm/PR-16362.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [[Misc] Add compressed-tensors NVFP4A16 emulation support](../sources/prs/vllm/PR-17914.md), [Use NVFP4 Marlin for CompressedTensorsW4A16Fp4](../sources/prs/vllm/PR-18000.md), [[Quantization] Add compressed-tensors NVFP4 support](../sources/prs/vllm/PR-18312.md), [[V1] Support `LLM.apply_model`](../sources/prs/vllm/PR-18465.md), [[Hardware][NVIDIA] FP4 MoE kernel optimization](../sources/prs/vllm/PR-19110.md), [[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization](../sources/prs/vllm/PR-19500.md), [[Quantization] Add compressed-tensors emulations support for NVFP4](../sources/prs/vllm/PR-19879.md), [[Quantization] Add compressed-tensors NVFP4 MoE Support](../sources/prs/vllm/PR-19990.md), [Add ModelOpt Qwen3 nvfp4 support](../sources/prs/vllm/PR-20101.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [[Kernel][Bugfix] Fixup some warnings in nvfp4_blockwise_moe when CUDA < 12.8](../sources/prs/vllm/PR-20324.md), [Support Llama 4 for cutlass_moe_fp4](../sources/prs/vllm/PR-20453.md), [[Perf] Reuse workspace for FP8+FP4 Marlin MoE](../sources/prs/vllm/PR-20500.md), [Support mnnvl all2allv from Flashinfer](../sources/prs/vllm/PR-21003.md), [[Feature][OCP MX] Support mxfp6 and mixed mxfp6-mxfp4](../sources/prs/vllm/PR-21166.md), [Support CUTLASS NVFP4 (w4a4) for Blackwell Geforce GPUs (SM120)](../sources/prs/vllm/PR-21309.md), [Support Tensorrt-LLM MoE fp4 for low-latency](../sources/prs/vllm/PR-21331.md), [Update flashinfer CUTLASS NVFP4 MoE Kernel to use per expert global scaling factor](../sources/prs/vllm/PR-21408.md), [[Bug] Fix Compressed Tensor NVFP4 `cutlass_fp4_group_mm` illegal memory access](../sources/prs/vllm/PR-21465.md), [[NVIDIA] Fix Llama4 Scout FP4 functionality issues](../sources/prs/vllm/PR-21499.md), [[Feature] Add Flashinfer MoE Support for Compressed Tensor NVFP4](../sources/prs/vllm/PR-21639.md), [[gpt-oss] flashinfer mxfp4](../sources/prs/vllm/PR-22339.md), [[gpt-oss] triton kernel mxfp4](../sources/prs/vllm/PR-22421.md), [Fix Llama4 FlashInfer FP4 MoE issues](../sources/prs/vllm/PR-22511.md), [Quantization: support FP4 quantized models on AMD CDNA2/CDNA3 GPUs](../sources/prs/vllm/PR-22527.md), [Fix torch version check for SM100 mxfp4 ](../sources/prs/vllm/PR-22535.md), [[Quantization] Expand compressed-tensors MoE matching logic to support NFP4 + FP8 MoEs](../sources/prs/vllm/PR-22674.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [Use Blackwell FlashInfer MXFP4 MoE by default if available ](../sources/prs/vllm/PR-23008.md), [Add routed_scaling_factor to MoE grouped topk](../sources/prs/vllm/PR-23123.md), [Fix nvfp4 swizzling](../sources/prs/vllm/PR-23140.md), [[Kernels] Overlap shared experts with send/recv](../sources/prs/vllm/PR-23273.md), [fix incompatibililty with non cuda platform for nvfp4](../sources/prs/vllm/PR-23478.md), [Update Flashinfer to 0.2.14.post1](../sources/prs/vllm/PR-23537.md), [DP/EP Support for gpt-oss with deepep-ht comm kernel on SM100](../sources/prs/vllm/PR-23608.md), [[Bugfix] Fix Marlin NVFP4 for modelopt](../sources/prs/vllm/PR-23659.md), [[NVIDIA] Support SiluMul + NVFP4 quant fusion](../sources/prs/vllm/PR-23671.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [[Bugfix][Misc] Fix silu_and_mul_nvfp4_quant issue and extract common utils for nvfp4 kernel source files](../sources/prs/vllm/PR-23727.md), [[Model][gpt-oss] Support DP+EP for GPT-OSS with FlashInfer trtllm-gen MoE](../sources/prs/vllm/PR-23819.md), [[BUGFIX ] fix undefined silu_and_mul_nvfp4_quant](../sources/prs/vllm/PR-23929.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Transform] [Quantization] Add QuTLASS support to vLLM](../sources/prs/vllm/PR-24440.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [[Bugfix] Fix accuracy issue for silu_mul + nvfp4 quant fusion kernel](../sources/prs/vllm/PR-24833.md), [[Compile] Fix Compile Warning for Ignoring `MIN_BLOCK_PER_SM`](../sources/prs/vllm/PR-25193.md), [[ROCm] Small functional changes for gptoss](../sources/prs/vllm/PR-25201.md), [Enable Fbgemm NVFP4 on Dense models](../sources/prs/vllm/PR-25609.md), [[Bugfix] Enable padded FP4 quantization](../sources/prs/vllm/PR-25947.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Bugfix] Allow skipping MoE in NVFP4 (fix for MTP)](../sources/prs/vllm/PR-25987.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[NVIDIA] Add support for cudnn fp4 gemm via flashinfer](../sources/prs/vllm/PR-26107.md), [[ModelOpt] Load w13/w2_input_scale for all experts, nvfp4](../sources/prs/vllm/PR-26135.md), [[ROCM] MoE fp4 CK kernel](../sources/prs/vllm/PR-26545.md), [support flashinfer_fp4 moe for 5090 gpu](../sources/prs/vllm/PR-26669.md), [[NVIDIA] [Perf] Update to leverage flashinfer trtllm FP4 MOE throughput kernel](../sources/prs/vllm/PR-26714.md), [[Bugfix] Fix gpt-oss w4a8 DP/EP on B200](../sources/prs/vllm/PR-26729.md), [Flashinfer_CUTLASS_MOE fuses quantization for TP](../sources/prs/vllm/PR-27223.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Bugfix] Fix GPT-OSS on AMD after #28603](../sources/prs/vllm/PR-28816.md), [Add TRTLLM MoE NVFP4 kernel to CompressedTensorsW4A4MoeMethod](../sources/prs/vllm/PR-28892.md), [[Feat] Support non-gated activations in NVFP4 modelopt path](../sources/prs/vllm/PR-29004.md), [[Kernel] Add NVFP4 MoE CUTLASS support for SM120](../sources/prs/vllm/PR-29242.md), [[Bugfix] Only use triton_kernels for MXFP4 on SM90 and SM100](../sources/prs/vllm/PR-29339.md), [[Bugfix] Fix mismatched nvfp4 gemm output shape](../sources/prs/vllm/PR-29742.md), [[ROCm][MXFP4] Infer w4a4 quant method in rocm aiter fused moe](../sources/prs/vllm/PR-29775.md), [[EPLB] Support EPLB w/ NVFP4](../sources/prs/vllm/PR-29804.md), [[Perf] Do FP4 quant before All gather on flashinfer trtllmgen MOE ](../sources/prs/vllm/PR-30014.md), [[ROCm][Quantization] GPT OSS Upstream MoE wmxfp4_afp8 with static scales](../sources/prs/vllm/PR-30357.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Perf] Set split_k to 1 for triton_kernels](../sources/prs/vllm/PR-30528.md), [[Perf] Eliminate padding and slicing op for GPT-OSS with Flashinfer MXFP4 MXFP8 MoE](../sources/prs/vllm/PR-30647.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[Compressed-Tensors] Simplify NVFP4 Conditions, enable marlin support for NVFP4A16 MoEs](../sources/prs/vllm/PR-30881.md), [[Kernel][Performance] Enable smaller Scaling Factor tiling for NVFP4 small-batch decoding](../sources/prs/vllm/PR-30885.md), [[NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size](../sources/prs/vllm/PR-30897.md), [ [FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/vllm/PR-31099.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[Perf] Fuse stride preparation for NVFP4 cutlass_moe](../sources/prs/vllm/PR-31837.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [[Perf][Kernel] Optimize FP4 quantization kernels (SM100F)](../sources/prs/vllm/PR-32520.md), [Support compress-tensors with nvfp4 or fp8 weights and modelopt with nvfp4 weights on Turing](../sources/prs/vllm/PR-33076.md), [fix: Add SM120 (RTX Blackwell) support for FlashInfer CUTLASS NVFP4 MoE kernels](../sources/prs/vllm/PR-33417.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [[Bugfix]fix output Nan/Inf in marlin if dtype=float16](../sources/prs/vllm/PR-33972.md), [[ModelBash][DSR1 NVFp4] Avoid Bf16 Bias Cast](../sources/prs/vllm/PR-34298.md), [[Custom Ops] Add functional + out variant for scaled_fp4_quant](../sources/prs/vllm/PR-34389.md), [[BUGFIX] Fix accuracy regression for NVIDIA-Nemotron-3-Nano-30B-A3B-NVFP4 with TP>1](../sources/prs/vllm/PR-34476.md), [[Model] Add NVFP4 quantization support for Step3.5-Flash](../sources/prs/vllm/PR-34478.md), [[Bugfix] Rescale NVFP4 weight scales to fix BF16 dequant underflow](../sources/prs/vllm/PR-34577.md), [[torch.compile] Turn on silu+fp4 quant fusion by default for O1+](../sources/prs/vllm/PR-34718.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [[BugFix] Fix fp4 quant kernel on CUDA 12.8](../sources/prs/vllm/PR-35210.md), [fix(mxfp4): return is_monolithic=False when LoRA is enabled for Triton backend](../sources/prs/vllm/PR-35382.md), [[NVFP4] Support NVFP4 dense models from `modelopt` and `compressed-tensors` on AMD Instinct MI300, MI355X and Hopper through emulation](../sources/prs/vllm/PR-35733.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[Mamba] Flashinfer selective_state_update](../sources/prs/vllm/PR-36162.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [[Bug][MoE] Fix TRTLLM NVFP4 Routing Kernel Precision](../sources/prs/vllm/PR-36725.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[MoE Refactor] Mxfp4 oracle rebased](../sources/prs/vllm/PR-37128.md), [Fix minimax m2.5 nvfp4 kv scales weight loading](../sources/prs/vllm/PR-37214.md), [[MoE/EPLB] Fix FlashInfer nvfp4 experts + EPLB correctness](../sources/prs/vllm/PR-37217.md), [[Kernel] Add non-gated support for NVFP4 CUTLASS MoE](../sources/prs/vllm/PR-37320.md), [[Bugfix] Fix EP weight filter breaking EPLB and NVFP4 accuracy](../sources/prs/vllm/PR-37322.md), [Add nvfp4 support to reshape_and_cache_flash](../sources/prs/vllm/PR-37332.md), [[Kernel] Add MXFP4 W4A4 CUTLASS MoE kernel for SM100](../sources/prs/vllm/PR-37463.md), [[Bugfix] Remove assertion for NVFP4 scale dynamic range](../sources/prs/vllm/PR-37465.md), [[Bugfix] Fix marlin nvfp4 rescaling](../sources/prs/vllm/PR-37502.md), [[4/n] Migrate FP4/W4A8 CUTLASS kernels to torch stable ABI](../sources/prs/vllm/PR-37503.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[Bugfix] Preserve CUDA arch suffix (a/f) for SM12x — fixes NVFP4 NaN on desktop Blackwell](../sources/prs/vllm/PR-37725.md), [[MoE] Move FlashInfer CuteDSL experts into fused_moe/experts/](../sources/prs/vllm/PR-37759.md), [[MoE Kernel] Flashinfer nvfp4 cutedsl moe kernel integration](../sources/prs/vllm/PR-38050.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [Fix NaN from stale FP4 scale padding in create_fp4_scale_tensor](../sources/prs/vllm/PR-38148.md), [[Quantization] Add FlashInfer CuteDSL batched experts backend for NVFP4 MoE](../sources/prs/vllm/PR-38251.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[Compile] Fix nvfp4 compile warning](../sources/prs/vllm/PR-38573.md), [[Bugfix] Fix NVFP4+MTP crash: force unquantized mtp.fc for Qwen3.5](../sources/prs/vllm/PR-38832.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[MoE] Move GPT OSS Triton kernel experts into fused_moe/experts/](../sources/prs/vllm/PR-39007.md), [[Refactor] Move NVFP4 GEMM management into NvFp4LinearKernel](../sources/prs/vllm/PR-39129.md), [[Feature] Batch invariant nvfp4 linear support](../sources/prs/vllm/PR-39322.md), [[Kernel] Support TRTLLM GEN NVFP4 MoE for non-512-aligned hidden dims via weight padding](../sources/prs/vllm/PR-39510.md), [[Bugfix] Reject non-nvfp4 dtypes when using the flashinfer_nvlink_one_sided all2all backend](../sources/prs/vllm/PR-39717.md), [[Bug] Fix batch invariance nvfp4 support](../sources/prs/vllm/PR-39820.md), [[Bugfix] Temporarily disable B200 fp4 MoE layer tests](../sources/prs/vllm/PR-40057.md), [Add nvfp4 kv cache support](../sources/prs/vllm/PR-40177.md), [[Bugfix] Guard mxfp4_experts_quant bindings on ENABLE_NVFP4_SM100](../sources/prs/vllm/PR-40191.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[DSV4] Add BF16 and MXFP8 A2A support for flashinfer a2a one sided](../sources/prs/vllm/PR-40960.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [[ROCm][Quantization][3/N] Refactor quark_moe w4a4 w/ oracle](../sources/prs/vllm/PR-41436.md), [[Quantization] Rework quantization_config to use QuantKey and allow for activation override](../sources/prs/vllm/PR-41566.md), [[MXFP4] Support for linear layers + compressed-tensors integration](../sources/prs/vllm/PR-41664.md), [Add NVFP4 all-gather GEMM fusion for AsyncTP](../sources/prs/vllm/PR-41882.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[Kernel] Pack topk id/weights triton kernel](../sources/prs/vllm/PR-42527.md), [[Bugfix] fix swiglu limit issue for humming backend + deepseek v4](../sources/prs/vllm/PR-42541.md), [[Perf] Padded nvfp4 quant kernel to remove additional copy, 2.4%~5.7% e2e performance improvement](../sources/prs/vllm/PR-42774.md), [[Perf] Re-enable flashinfer autotune by default and cleanup](../sources/prs/vllm/PR-42857.md), [NVFP4 and Block-Scaled Narrow Precision](../wiki/hardware/nvfp4.md), [NVFP4 GEMM — 4-bit Floating Point Matrix Multiply](../wiki/kernels/nvfp4-gemm.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md), [Fine-Grained FP8/FP4 Quantization](../wiki/techniques/fine-grained-quantization.md) | -| `fp6` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [NVFP4 and Block-Scaled Narrow Precision](../wiki/hardware/nvfp4.md) | -| `fp8` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [DeepGEMM — FP8 GEMM Library](../sources/blogs/deepgemm.md), [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Use swizzling instead of padding](../sources/prs/DeepGEMM/PR-86.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [[None][fix] impl fused triton kernel for e8m0 resmooth to reduce memory footprint](../sources/prs/TensorRT-LLM/PR-10327.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[None][feat] Add support for expert_number<=2048 and K<=32](../sources/prs/TensorRT-LLM/PR-11510.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[TRTLLM-10421][perf] Add fused cat+fp8_quantize CUDA kernel for DSA indexer](../sources/prs/TensorRT-LLM/PR-11899.md), [[None][feat] GLM 5 support and DSA MTP fixes](../sources/prs/TensorRT-LLM/PR-11990.md), [[https://nvbugs/5879577][fix] Fix KeyError in DeepSeekV3Lite FP8 MTP weight loading](../sources/prs/TensorRT-LLM/PR-12530.md), [[#12784][feat] AutoDeploy: Optimize DeepSeek-R1 model performance](../sources/prs/TensorRT-LLM/PR-12946.md), [[TRTLLM-34871][feat] Add cute dsl FP8 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13219.md), [[TRTLLM-11127][feat] add W4A8_MXFP4_FP8 MoE unit test support](../sources/prs/TensorRT-LLM/PR-13401.md), [[None][feat] Fuse FP8 1x128 quantize + UE8M0 scale pack on SM100](../sources/prs/TensorRT-LLM/PR-13628.md), [[None][fix] Plumb swiglu_limit through DeepGEMM and TRTLLMGen FP8 fused MoE](../sources/prs/TensorRT-LLM/PR-13767.md), [[TRTLLM-12503][feat] Parallel VAE independent scaling and fix arg passing](../sources/prs/TensorRT-LLM/PR-13873.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] Keep DSv4 o_a_proj as FP8, and port vLLM's fused_inv_rope_fp8_quant](../sources/prs/TensorRT-LLM/PR-13938.md), [[TRTLLM-12462][fix] Fix FP8 block scaling GEMM autotuner cache growth](../sources/prs/TensorRT-LLM/PR-14165.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [[None][feat] TRT-LLM Gen MoE optimize DeepSeek Fp8 activation kernel](../sources/prs/TensorRT-LLM/PR-9175.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [Improve sm90 mixed dtype kernel](../sources/prs/cutlass/PR-1883.md), [Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2037.md), [Improvements for: Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2095.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [hopper-blockwise-generalization-optimization](../sources/prs/cutlass/PR-2270.md), [support fp16 accmulator for sm89 fp8 mma](../sources/prs/cutlass/PR-2378.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [[Cutlass gemm] Fix SM100 FP8 nosmem epilogue-fusion shape_div 'Divisibility Condition' for non-multiple-of-64 N tiles](../sources/prs/cutlass/PR-2946.md), [[Bug Fix]Set NumSplitsM to 1 when TileShapeM < 128 in sm90 fp8 blockwise scaling CollectiveMma](../sources/prs/cutlass/PR-2965.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [perf: accelerate blackwell grouped gemm](../sources/prs/flashinfer/PR-1086.md), [bugfix: fix fp8 attention kernels aot compilation issue](../sources/prs/flashinfer/PR-1087.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [Add DeepGEMM kernels](../sources/prs/flashinfer/PR-1209.md), [Fix test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-1211.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [Patch fp8 cubin availability](../sources/prs/flashinfer/PR-1240.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [Reduce the JIT compilation time of gen_gemm_sm100_module](../sources/prs/flashinfer/PR-1251.md), [init add gemm fp8 using cudnn backend](../sources/prs/flashinfer/PR-1264.md), [feat: add masked deepgemm support and benchmarking](../sources/prs/flashinfer/PR-1266.md), [Unify groupwise fp8 GEMM test](../sources/prs/flashinfer/PR-1281.md), [Bug fix: guard fp8 e8m0 and e2m1 compile ](../sources/prs/flashinfer/PR-1287.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [Make Fp8 MoE routing_bias optional](../sources/prs/flashinfer/PR-1319.md), [Add blockwise-scaled FP8 GEMM via TRTLLM-Gen.](../sources/prs/flashinfer/PR-1320.md), [feat: Fused rope fp8 quantize kernel for MLA](../sources/prs/flashinfer/PR-1339.md), [[fix] remove (view) transpose to keep consistent with majorness MN requirement.](../sources/prs/flashinfer/PR-1358.md), [bugfix: Add guard for fp4/fp8 related include headers](../sources/prs/flashinfer/PR-1376.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Adding FP8 benchmark on attention and matmul testing](../sources/prs/flashinfer/PR-1390.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [feature: add cutlass as bmm_fp8 backend.](../sources/prs/flashinfer/PR-1397.md), [bugfix: fix perf issue by using fp8 graph that can use cublaslt](../sources/prs/flashinfer/PR-1435.md), [Add alignment in MxFP8Quantization](../sources/prs/flashinfer/PR-1445.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [perf: add 1x4x1 cluster shape for fp8 bmm M<16 cases](../sources/prs/flashinfer/PR-1473.md), [refactor: unify autotuner for bmm_fp8](../sources/prs/flashinfer/PR-1479.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [Perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8](../sources/prs/flashinfer/PR-1491.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [bugfix: Fix compile error for undefined swizzle enum.](../sources/prs/flashinfer/PR-1530.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [bugfix: fix unittest test_fp8_quantize](../sources/prs/flashinfer/PR-1599.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [feat: cutlass fp8 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1610.md), [test: pytest.mark.xfail on deepgemm](../sources/prs/flashinfer/PR-1636.md), [Add benchmark for MLARopeQuantize](../sources/prs/flashinfer/PR-1656.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [test: better fp8 quantization init for fused_moe test](../sources/prs/flashinfer/PR-1674.md), [Update deepgemm backend for 103a](../sources/prs/flashinfer/PR-1694.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [TVM: support TVM binding for GroupedGemm](../sources/prs/flashinfer/PR-1725.md), [tests: xfail moe quantization classes mxfp8_bf16 UTs on sm103 ](../sources/prs/flashinfer/PR-1754.md), [tests: skip non SM100/103 for grouped deepgemm](../sources/prs/flashinfer/PR-1767.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [raise error for group_gemm_fp8_nt_groupwise then num_groups > 1 on sm120/121](../sources/prs/flashinfer/PR-1862.md), [misc: fix some B200 GEMM bench](../sources/prs/flashinfer/PR-1883.md), [MLA RoPE + quantization fused kernel: shape generalization for MHA / GQA](../sources/prs/flashinfer/PR-1924.md), [Fix: Verify scales are not None for Cutlass FP8 FusedMoE](../sources/prs/flashinfer/PR-1961.md), [feat: enable deepgemm jit for fp8 block-scale on SM90](../sources/prs/flashinfer/PR-1969.md), [fix: correct PDL parameter handling in RopeQuantize kernel](../sources/prs/flashinfer/PR-1982.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [feat: suitable_auto_backends to prune auto backends, bmm_fp8 refactor, heuristic_func intake](../sources/prs/flashinfer/PR-2029.md), [Enable renormalize(naive) routing for fp8 per-tensor](../sources/prs/flashinfer/PR-2030.md), [Added an initial implementation of Q and KV Cache in fp8 and to use t…](../sources/prs/flashinfer/PR-2035.md), [feat: Add flashinfer.rope.rope_quantize_fp8_append_paged_kv_cache (fused RoPE + Q + KV cache, supports MLA/GQA/MHA) ](../sources/prs/flashinfer/PR-2037.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [test: Skip test_fp8_quantize.py on Hopper](../sources/prs/flashinfer/PR-2052.md), [Fix moe fp8 failure for sm121](../sources/prs/flashinfer/PR-2061.md), [perf: TRT-LLM MoE Block-FP8 activation optimization](../sources/prs/flashinfer/PR-2063.md), [enable xqa fp8 output](../sources/prs/flashinfer/PR-2081.md), [refactor: update dpsk fused_moe test [1]](../sources/prs/flashinfer/PR-2088.md), [refactor: update dpsk fused_moe test [2]](../sources/prs/flashinfer/PR-2097.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [fix: Fix bench_mm_fp8.py](../sources/prs/flashinfer/PR-2129.md), [make DeepGEMM swapAB available for linear gemm SM90](../sources/prs/flashinfer/PR-2131.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [Fp8 attention are now part of cuDNN 9.17.1](../sources/prs/flashinfer/PR-2241.md), [feat: RMSNorm/Fused RMSNorm + FP8 Quantization kernels](../sources/prs/flashinfer/PR-2243.md), [fix: support int64 IdType for RoPE part argument in `rope_quantize_fp8_append_paged_kv_cache`](../sources/prs/flashinfer/PR-2255.md), [feat: Add support for bmm mxfp8](../sources/prs/flashinfer/PR-2256.md), [Fix CUTLASS FP8 gemm correctness issue on SM120/SM121 for shapes where N is not divisible by ScaleGranularityN.](../sources/prs/flashinfer/PR-2261.md), [test: use .float() in in F.cosine_similarity() in bmm_fp8 test](../sources/prs/flashinfer/PR-2266.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32](../sources/prs/flashinfer/PR-2327.md), [fix: guard batchWarpReduceSum with ENABLE_FP8 to fix compilation without FP8](../sources/prs/flashinfer/PR-2328.md), [fix: Fix NaN output in mxfp8_quantize for very small input values](../sources/prs/flashinfer/PR-2441.md), [Add cute-dsl backends to mxfp[8,4]_quantization for future refactor](../sources/prs/flashinfer/PR-2443.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [feat: Add MXFP8 GEMM mm_mxfp8 (cutlass)](../sources/prs/flashinfer/PR-2464.md), [Feat: Trtllm-gen MxFP8 MoE integration](../sources/prs/flashinfer/PR-2505.md), [fix: include fp8_blockscale_gemm_90 in AOT jit-cache](../sources/prs/flashinfer/PR-2533.md), [fallback to fa2 (instead of fa3) for unsupported configuration (bf16 Q, Fp8 KV)](../sources/prs/flashinfer/PR-2536.md), [tests: bmm_fp8 for SM110](../sources/prs/flashinfer/PR-2538.md), [Add gen_gemm_sm100_module_cutlass_mxfp8 to jit-cache](../sources/prs/flashinfer/PR-2549.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [benchmark: Add MXFP4/MXFP8 quantization mode support to FP4 MoE benchmark](../sources/prs/flashinfer/PR-2635.md), [[fp8_blockwise]Fix int32 overflow in TRTLLM fused MoE activation kernel](../sources/prs/flashinfer/PR-2642.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [feat: support mxfp4 & mxfp8 entrypoint for blackwell cutedsl dense gemm](../sources/prs/flashinfer/PR-2660.md), [benchmarks: Add FP8 input / BF16 output in ragged prefill benchmark](../sources/prs/flashinfer/PR-2666.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [feat: Add support for TRTLLM MXFP8 non-gated MoE with ReLU2](../sources/prs/flashinfer/PR-2707.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [Support in-place update for `trtllm_fp8_block_scale_moe`](../sources/prs/flashinfer/PR-2739.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [[Spark unit test debugging] Fix for tests/gemm/test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-2751.md), [feat: FP8 output support for CUTLASS MLA paged attention](../sources/prs/flashinfer/PR-2779.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [Fix silent bug with FP8 per tensor non-gated MoE](../sources/prs/flashinfer/PR-2882.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [feat: add MXFP8 GEMM support for SM120](../sources/prs/flashinfer/PR-2902.md), [perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels](../sources/prs/flashinfer/PR-2904.md), [[NVIDIA] fix(jit): enable GDC for CUTLASS fused MoE PDL — prevent random crashes on SM12x](../sources/prs/flashinfer/PR-2913.md), [feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners](../sources/prs/flashinfer/PR-2914.md), [test: xfail cuDNN FP8 prefill on Blackwell with CUDA <= 12.9](../sources/prs/flashinfer/PR-2963.md), [test: skip unsupported mm_mxfp8 configurations on SM12x](../sources/prs/flashinfer/PR-2974.md), [ Fix MXFP4/MXFP8 failures in SM120 FAST_BUILD and expand all_tiles[] ](../sources/prs/flashinfer/PR-2994.md), [Support Allreduce + Norm + Per-token Group Fp8 Quant Fusion](../sources/prs/flashinfer/PR-3059.md), [feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16](../sources/prs/flashinfer/PR-3129.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [test: enable bmm_mxfp8 cutlass backend coverage on SM12x](../sources/prs/flashinfer/PR-3183.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [Naive Support for Hopper FP8 Prefill Kernel with Per-Head Quantization](../sources/prs/flashinfer/PR-869.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [Update CUTLASS. Refine KernelSchedule for fp8 (grouped) gemm.](../sources/prs/sglang/PR-10491.md), [support qwen3-next-fp8 deepep](../sources/prs/sglang/PR-10622.md), [Fix DSR1 accuracy for flashinfer_trtllm MoE with FP8 quantization](../sources/prs/sglang/PR-11081.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [Change bf16 to fp8 for some gemms in attention for DeepSeek ckpt v2](../sources/prs/sglang/PR-11805.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [[sgl-kernel][4/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12080.md), [[hotfix] missing `w13_weight_fp8` and `w2_weight_fp8` in UE8M0 requantization](../sources/prs/sglang/PR-12259.md), [fix: llama 4 + trtllm gen + fp8 kv cache incompatibility](../sources/prs/sglang/PR-12347.md), [Enable Flashinfer TRTLLM-GEN-MoE FP8 blockwise kernel for Qwen3-Next on Blackwell](../sources/prs/sglang/PR-12543.md), [[sgl-kernel] support custom fp8 flashmla kernel](../sources/prs/sglang/PR-13087.md), [Aiter fp8 kv cache](../sources/prs/sglang/PR-13147.md), [[NVIDIA] Fix broken fp8 MoE of deepseek v3](../sources/prs/sglang/PR-13264.md), [[NVIDIA] Fix use case of SGLANG_ENABLE_FLASHINFER_GEMM](../sources/prs/sglang/PR-13274.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [Feat: GLM-4.6 supports shared experts fusion](../sources/prs/sglang/PR-13873.md), [Fix update weight error for blackwell DeepGEMM](../sources/prs/sglang/PR-13910.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Support checking fp8 params in weight_checker](../sources/prs/sglang/PR-14147.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[CPU] Implement MXFP4 Gemm kernels for intel AMX to support GPT OSS series.](../sources/prs/sglang/PR-14385.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [Add Mistral Large 3 Eagle Support](../sources/prs/sglang/PR-14466.md), [[sgl-kernel][Feat][B200][2/N] Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-14640.md), [[sgl-kernel] Update flashmla to include fp8 sparse_mla optimizations](../sources/prs/sglang/PR-15242.md), [Flashinfer MOE FP8 support for Mistral Large 3.](../sources/prs/sglang/PR-15422.md), [[sgl-kernel][6/7]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-15471.md), [[Perf] Add Flashinfer DeepGEMM SM90 for SwapAB Optimization](../sources/prs/sglang/PR-15514.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [Fix FP8 MoE NaN with DeepGEMM on Blackwell](../sources/prs/sglang/PR-16622.md), [[GLM 4.7] Add RTX 6000 Pro aka sm120](../sources/prs/sglang/PR-17235.md), [Disable mla persistent kernel when not using fp8 kv_cache](../sources/prs/sglang/PR-17327.md), [Add mxfp8 support for online quantization, Triton dense linear, and CUTLASS MoE](../sources/prs/sglang/PR-17449.md), [[ROCm] Optimize Deepseek R1 on MI300X](../sources/prs/sglang/PR-18242.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [Fp8 prefill attn kernel integration](../sources/prs/sglang/PR-18528.md), [[AMD] DSR1/V3 use fp8 bmm in MLA for MI300X](../sources/prs/sglang/PR-18624.md), [[RL] Support per-layer mixed FP8/BF16 serving for FP8 checkpoints](../sources/prs/sglang/PR-18742.md), [Fix NSA FP8 KV cache path for both-trtllm MHA one-shot](../sources/prs/sglang/PR-18931.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [Various SM120 improvements](../sources/prs/sglang/PR-19721.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [Enable modelopt quantized FLUX deployment](../sources/prs/sglang/PR-20082.md), [[AMD] Fp8 prefill integration with radix cache path for dpsk models](../sources/prs/sglang/PR-20187.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[NVIDIA] Enable fp8 flashinfer_trtllm_routed MoE for MiniMax-M2.5](../sources/prs/sglang/PR-20394.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [CUTLASS FP8 Blockwise GEMM improvement of SM120](../sources/prs/sglang/PR-20887.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [ci: run Stage A CUDA tests as stage-a-test-small-1-gpu on 5090](../sources/prs/sglang/PR-20988.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[RL] Support mxfp8 DeepSeek V3](../sources/prs/sglang/PR-21280.md), [[Kernel] Support FlashInfer TRTLLM-Gen fused MoE for non-gated FP4 & FP8 (Nemotron)](../sources/prs/sglang/PR-21321.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [[FlashInver v0.6.7] Integrate flashinfer_trtllm mxfp8 gemm](../sources/prs/sglang/PR-21576.md), [[AMD] Add GLM-5-FP8 nightly performance benchmarks for MI30x and MI35x](../sources/prs/sglang/PR-21710.md), [[Misc] [MXFP8] Drop sm100 mxfp8 warning](../sources/prs/sglang/PR-21881.md), [fix pcg torch dynamo recompile in mxfp8 Triton path](../sources/prs/sglang/PR-21888.md), [Tiny fix trtllm_fp8_per_tensor_scale_moe_wrapper router_logits dtype](../sources/prs/sglang/PR-22006.md), [[AMD][HIP] NSA: bf16 passthrough from RMSNorm to eliminate FP8 dequantization](../sources/prs/sglang/PR-22258.md), [[AMD] Fix GLM-5 fp8 KV quant path dispatch on MI300](../sources/prs/sglang/PR-22314.md), [[Reland] DeepSeek-R1-0528-w4a8: DeepEP Low Latency Dispatch Adopts FP8 Communication](../sources/prs/sglang/PR-22316.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [[AMD] Add GLM-5.1-FP8 nightly accuracy and performance benchmarks for MI30x and MI35x](../sources/prs/sglang/PR-22336.md), [[Diffusion] modelopt diffusion fp8 support for flux1/flux2 and wan2.2](../sources/prs/sglang/PR-22365.md), [[DSA] Hopper FP8 FlashMLA KV padding](../sources/prs/sglang/PR-22372.md), [[RL] Fix weight update for mxfp8 flashinfer_cutlass gemm backend](../sources/prs/sglang/PR-22484.md), [[Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22574.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [[MoE] Unify DeepEPMoE+MoriEPMoE through AITER MoeRunner pre/post-permute](../sources/prs/sglang/PR-23760.md), [Refactor device timer, clean up metrics collector, and add fwd occupancy metric](../sources/prs/sglang/PR-24197.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [[Codex] Opt Mistral Large performace ](../sources/prs/sglang/PR-24611.md), [[Gemma4] Optimize Gemm4 with fused Q/K/V RMSNorm + per-expert FP8 ckpt loader](../sources/prs/sglang/PR-24696.md), [Add FlashInfer SM90 cutlass MXFP4 MoE backend (W4A16) for GPT-OSS + DeepSeek-V4](../sources/prs/sglang/PR-24816.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [[Gemma4]: Fix FP8 Triton scale layout](../sources/prs/sglang/PR-25286.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[fp8] SM90 swap-AB scaled_mm dispatch (~1.16x kernel geomean, +5.8-18.5% end-to-end)](../sources/prs/sglang/PR-25532.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [support w8a8 fp8 kernel with CUTLASS](../sources/prs/sglang/PR-3047.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [Apply sgl w8a8 fp8 kernel](../sources/prs/sglang/PR-3148.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [support blockwise fp8 matmul kernel](../sources/prs/sglang/PR-3267.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [add control for cutlass fp8 blockwise gemm](../sources/prs/sglang/PR-3727.md), [[tools] add fp8 max/min constant in utils](../sources/prs/sglang/PR-3959.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [linear support deepgemm](../sources/prs/sglang/PR-4199.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [Clean up fp8 support](../sources/prs/sglang/PR-4230.md), [fix per_token_group_quant_fp8 illegal memory when num_groups % 16 != 0](../sources/prs/sglang/PR-4231.md), [Support Blackwell Block Scale FP8 Gemm](../sources/prs/sglang/PR-4278.md), [[FIX] fix incorrect output when enable both deepgemm and torch compile](../sources/prs/sglang/PR-4359.md), [[ROCm] fix dtype](../sources/prs/sglang/PR-4510.md), [Create col-major and tma-aligned x_scale for deep_gemm.gemm_fp8_fp8_bf16_nt](../sources/prs/sglang/PR-4515.md), [Support fp8 gemm for blackwell](../sources/prs/sglang/PR-4558.md), [[quantization] fix channelwise conversion with scalar weight scale](../sources/prs/sglang/PR-4596.md), [Set deepgemm to the default value in the hopper architecture.](../sources/prs/sglang/PR-4613.md), [Add DeepSeek V3/R1 shared experts fusion](../sources/prs/sglang/PR-4918.md), [feat: add DeepGEMM build warning](../sources/prs/sglang/PR-5176.md), [[Fix] Turn off DeepGEMM by default](../sources/prs/sglang/PR-5263.md), [[1/2] Add FP8 Blockscale MoE CUTLASS kernel for Blackwell](../sources/prs/sglang/PR-5281.md), [fix: use deepgemm only on hopper](../sources/prs/sglang/PR-5310.md), [[perf] experimental enhance fp8 per-tensor quant](../sources/prs/sglang/PR-5370.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [[feature] enable pre compile jit deep_gemm](../sources/prs/sglang/PR-5580.md), [ DeepEP normal support deepgemm-contiguous](../sources/prs/sglang/PR-5626.md), [[perf] dsv3 bmm fallback to bf16](../sources/prs/sglang/PR-5662.md), [[2/2] Add python wrapper for CUTLASS FP8 Blockscale MoE Kernel. ](../sources/prs/sglang/PR-5694.md), [cutlass 3.9 supported to improve fp8_blockwise_gemm](../sources/prs/sglang/PR-5820.md), [chore: upgrade cutlass 3.9.2](../sources/prs/sglang/PR-6004.md), [Upgrade CUTLASS 4.0](../sources/prs/sglang/PR-6336.md), [Add fp8 fused_experts kernel for CPU in sgl-kernel and add UT](../sources/prs/sglang/PR-6404.md), [Fix bug of deepseek-v3 under DP+EP mode with large batchsize/seqlen](../sources/prs/sglang/PR-6449.md), [[Feature] Support Flashinfer fp8 blockwise GEMM kernel on Blackwell](../sources/prs/sglang/PR-6479.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [[CPU] add optimizations for INT8 and FP8 DeepSeek](../sources/prs/sglang/PR-6769.md), [feat: integrate deepgemm into EPMoE](../sources/prs/sglang/PR-6821.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [Use deepgemm instead of triton for fused_qkv_a_proj_with_mqa](../sources/prs/sglang/PR-6890.md), [Add a CUDA kernel for fusing mapping and weighted sum for MoE.](../sources/prs/sglang/PR-6916.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [Fuse routed scaling factor in deepseek](../sources/prs/sglang/PR-6970.md), [Update default settings for blackwell](../sources/prs/sglang/PR-7023.md), [Fix positional argument](../sources/prs/sglang/PR-7093.md), [fix amd EP MoE FP8 issue](../sources/prs/sglang/PR-7125.md), [Enable ModelOpt Llama4 fp8 checkpoint deployment in SGLang](../sources/prs/sglang/PR-7129.md), [[amd] Opt dsv3 moe](../sources/prs/sglang/PR-7160.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Tiny let DeepGEMM scale checks cover more cases](../sources/prs/sglang/PR-7182.md), [[AMD] Fail gracefully when AITER is unavailable gfx90a GPUs](../sources/prs/sglang/PR-7187.md), [[fix] fix DeepGEMM blackwell input quant & ut & fix style and log](../sources/prs/sglang/PR-7247.md), [Add CUTLASS FP8 Blockscale MoE kernel for Hopper architecture](../sources/prs/sglang/PR-7278.md), [Fix torch compile run](../sources/prs/sglang/PR-7391.md), [[AMD][Quantization] Add `int4fp8_moe` online quantization on ROCm](../sources/prs/sglang/PR-7392.md), [feat: support DeepSeek-R1-W4AFP8 model with ep-moe mode](../sources/prs/sglang/PR-7762.md), [Qwen FP8/NVFP4 ModelOPT Quantization support](../sources/prs/sglang/PR-7912.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [[sgl-kernel] Opt per_token_quant_fp8 with warp reduce](../sources/prs/sglang/PR-8130.md), [[1/N]Support DeepSeek-R1 w4a8 normal deepep](../sources/prs/sglang/PR-8247.md), [[2/N]Support DeepSeek-R1 w4a8 low latency deepep](../sources/prs/sglang/PR-8464.md), [TRTLLM-MLA FP8 path](../sources/prs/sglang/PR-8638.md), [feat: support cutlass_moe_fp8 kernel for fusedmoe in sm90](../sources/prs/sglang/PR-8678.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/sglang/PR-8818.md), [optimize: reduce shulffle and quantization overhead in cutlass_moe sm90](../sources/prs/sglang/PR-8962.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [[sgl-kernel] feat: Support sm120 cutlass fp8 gemm kernel](../sources/prs/sglang/PR-9403.md), [fix: blackwell dsv3 fp8 issue temporary solution](../sources/prs/sglang/PR-9530.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [Make sm100 fp8 kernels available on sm103](../sources/prs/sglang/PR-9789.md), [CUTLASS fp8 blockwise gemm support of sm120](../sources/prs/sglang/PR-9969.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Kernel]: Cutlass 2:4 Sparsity + FP8/Int8 Quant Support](../sources/prs/vllm/PR-10995.md), [[Kernel] Update `cutlass_scaled_mm` to support 2d group (blockwise) scaling](../sources/prs/vllm/PR-11868.md), [Add: Support for Sparse24Bitmask Compressed Models](../sources/prs/vllm/PR-12097.md), [Expert Parallelism (EP) Support for DeepSeek Models](../sources/prs/vllm/PR-12583.md), [[Kernel][Quantization] Integrate block-quantized CUTLASS kernels for DeepSeekV3](../sources/prs/vllm/PR-12587.md), [[Attention] Deepseek v3 MLA support with FP8 compute](../sources/prs/vllm/PR-12601.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [[AMD][ROCm] Enable DeepSeek model on ROCm](../sources/prs/vllm/PR-12662.md), [[Bugfix] Better FP8 supported defaults](../sources/prs/vllm/PR-12796.md), [[Kernel]Add streamK for block-quantized CUTLASS kernels](../sources/prs/vllm/PR-12978.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [[Bugfix][Quantization] Fix FP8 + EP](../sources/prs/vllm/PR-13784.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [[core] moe fp8 block quant tuning support](../sources/prs/vllm/PR-14068.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [Add cutlass support for blackwell fp8 blockwise gemm](../sources/prs/vllm/PR-14383.md), [[BugFix] Illegal Memory Access in the blockwise cutlass fp8 GEMMs](../sources/prs/vllm/PR-14396.md), [[ROCm][Kernel] MoE weights padding](../sources/prs/vllm/PR-14454.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[Attention] Flash Attention 3 - fp8](../sources/prs/vllm/PR-14570.md), [[Quantization][FP8] Adding support for fp8 gemm layer input in fp8](../sources/prs/vllm/PR-14578.md), [[Attention] MLA get rid of materialization](../sources/prs/vllm/PR-14770.md), [[FEAT][ROCm] Integrate Fused MoE Kernels from AITER](../sources/prs/vllm/PR-14967.md), [[FEAT] [ROCm]: Add AITER Block-Scaled GEMM Feature](../sources/prs/vllm/PR-14968.md), [[Quantization] Fp8 Channelwise Dynamic Per Token GroupedGEMM](../sources/prs/vllm/PR-15587.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Kernel] Support W8A8 channel-wise weights and per-token activations in triton fused_moe_kernel](../sources/prs/vllm/PR-16366.md), [Enable PTPC FP8 for CompressedTensorsW8A8Fp8MoEMethod (triton fused_moe)](../sources/prs/vllm/PR-16537.md), [[ROCm] Add aiter tkw1 kernel for Llama4 fp8](../sources/prs/vllm/PR-16727.md), [[Kernel] some optimizations for dense marlin and moe marlin](../sources/prs/vllm/PR-16850.md), [[Kernel] Add expert_map support to Cutlass FP8 MOE](../sources/prs/vllm/PR-16861.md), [[FEAT] [ROCm]: Add AITER CK 2 Stages MoE support](../sources/prs/vllm/PR-17110.md), [[ROCm][FP8][Kernel] FP8 quantization fused into Custom Paged Attention](../sources/prs/vllm/PR-17139.md), [[NVIDIA] Support Cutlass w8a8 FP8 for Blackwell Geforce GPUs (sm120)](../sources/prs/vllm/PR-17280.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [use ceil_div in cutlass block scaling shape check](../sources/prs/vllm/PR-17918.md), [[Feature] Expert Parallelism Load Balancer (EPLB)](../sources/prs/vllm/PR-18343.md), [[V1] Support `LLM.apply_model`](../sources/prs/vllm/PR-18465.md), [Sm100 blockwise fp8 swap ab](../sources/prs/vllm/PR-18564.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-18778.md), [[Kernel] Enable fp8 support for pplx and BatchedTritonExperts.](../sources/prs/vllm/PR-18864.md), [[Kernel] Support deep_gemm for linear methods](../sources/prs/vllm/PR-19085.md), [[Kernels] Add activation chunking logic to FusedMoEModularKernel](../sources/prs/vllm/PR-19168.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [[Feature] Integrate new deepgemm](../sources/prs/vllm/PR-19820.md), [ [Feature] Integrate SM100 DeepGEMM support](../sources/prs/vllm/PR-20087.md), [[Bugfix] Fix topk_ids indices_type for CUTLASS w8a8 FP8 MoE](../sources/prs/vllm/PR-20166.md), [[V1] [ROCm] Enable EP with AITER Fused MoE](../sources/prs/vllm/PR-20270.md), [[Kernel] SM90 CUTLASS FP8 GEMM: add support for swap AB + kernel tuning](../sources/prs/vllm/PR-20396.md), [[feat]: add SM100 support for cutlass FP8 groupGEMM](../sources/prs/vllm/PR-20447.md), [Support Llama 4 for fused_marlin_moe](../sources/prs/vllm/PR-20457.md), [[Perf] Reuse workspace for FP8+FP4 Marlin MoE](../sources/prs/vllm/PR-20500.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [[Perf] Use Triton instead of Torch for DeepGEMM Per Token Group Quant](../sources/prs/vllm/PR-20841.md), [[Perf] Add swap_ab to SM90 FP8 non-block CUTLASS moe grouped gemm](../sources/prs/vllm/PR-20911.md), [[Perf] Cuda Kernel for Per Token Group Quant](../sources/prs/vllm/PR-21083.md), [[perf] Add fused MLA QKV + strided layernorm](../sources/prs/vllm/PR-21116.md), [[Feature][OCP MX] Support mxfp6 and mixed mxfp6-mxfp4](../sources/prs/vllm/PR-21166.md), [[Bug] DeepGemm: Fix TypeError: per_block_cast_to_fp8() missing 1 required positional argument: 'use_ue8m0' for SM100](../sources/prs/vllm/PR-21187.md), [[NVIDIA] Explicitly disable shuffled weights for flashinfer blockscale moe fp8 kernels](../sources/prs/vllm/PR-21411.md), [[Bugfix][CUDA] fixes CUDA FP8 kv cache dtype supported](../sources/prs/vllm/PR-21420.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [[Kernel] Add support for block FP8 on SM120 (NVIDIA 5090 and RTX PRO 6000)](../sources/prs/vllm/PR-22131.md), [Fp8 paged attention update](../sources/prs/vllm/PR-22222.md), [[Bug] Fix B200 DeepGEMM E8M0 Accuracy Issue](../sources/prs/vllm/PR-22399.md), [[Quantization] Expand compressed-tensors MoE matching logic to support NFP4 + FP8 MoEs](../sources/prs/vllm/PR-22674.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [fp8 kv cache support fix for torch.compile](../sources/prs/vllm/PR-22758.md), [[Kernel] Added flashinfer fp8 per-tensor gemms](../sources/prs/vllm/PR-22895.md), [[Bugfix] fix qwen3 moe fp8 accuracy issue](../sources/prs/vllm/PR-23031.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [Add routed_scaling_factor to MoE grouped topk](../sources/prs/vllm/PR-23123.md), [[XPU][Feature] fp8 online quantization support for XPU](../sources/prs/vllm/PR-23148.md), [[kernel] Support W4A8 on Hopper](../sources/prs/vllm/PR-23198.md), [[ROCm][Aiter] Add triton fp8 bmm kernel for mla](../sources/prs/vllm/PR-23264.md), [[Perf] Small optimizations for silu_mul_fp8_quant_deep_gemm](../sources/prs/vllm/PR-23265.md), [[Kernels] Overlap shared experts with send/recv](../sources/prs/vllm/PR-23273.md), [[Perf] Use upstream CUTLASS for SM90 Block FP8 kernel](../sources/prs/vllm/PR-23280.md), [[Bug] Fix R1 Accuracy 0 Bug](../sources/prs/vllm/PR-23294.md), [DP/EP Support for gpt-oss with deepep-ht comm kernel on SM100](../sources/prs/vllm/PR-23608.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[Feature] Add Hopper DeepGEMM E8M0 for DeepSeekV3.1 scale_fmt](../sources/prs/vllm/PR-23666.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Performance] Move apply_w8a8_block_fp8_linear to an op class](../sources/prs/vllm/PR-24666.md), [[NVIDIA] Blackwell Family](../sources/prs/vllm/PR-24673.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [[Flashinfer][gpt-oss] Support FP8-qkv Flashinfer TRTLLM Sinks Attention](../sources/prs/vllm/PR-25674.md), [[Bugfix] Convert untraceable GroupShape to list for AMD impl](../sources/prs/vllm/PR-26535.md), [[Bugfix] Fix gpt-oss w4a8 DP/EP on B200](../sources/prs/vllm/PR-26729.md), [[Feature] Batch Invariant: Support DeepGEMM and Blackwell](../sources/prs/vllm/PR-27127.md), [[Kernels] Enable FlashInfer FP8 Blockscale on SM90 (for TEP DSR1)](../sources/prs/vllm/PR-27134.md), [[torch.compile] Enable silu_mul_fp8_quant fusion without custom ops enabled](../sources/prs/vllm/PR-27146.md), [Bugfix: Cutlass FP8 FusedMoE bad scaling factors](../sources/prs/vllm/PR-27255.md), [Feature: Support Relu2 in FusedMoE fp8 cutlass path](../sources/prs/vllm/PR-27261.md), [[Perf] SM100 - add swap AB optimization to CUTLASS FP8 GEMM](../sources/prs/vllm/PR-27284.md), [[Performance] Support FP8 flashinfer TRTLLM MOE on Qwen3 and Qwen-3next](../sources/prs/vllm/PR-27492.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Feature] Batch invariant torch.compile](../sources/prs/vllm/PR-27660.md), [[Performance] Fused blockwise quant RMS norm](../sources/prs/vllm/PR-27883.md), [[Performance][B200] Fix deepgemm prologue](../sources/prs/vllm/PR-27897.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Performance][B200] silu_mul_quant: pack scales in int32](../sources/prs/vllm/PR-28358.md), [[Performance] Reduce DeepGEMM N dim restriction from 128 to 64 multiplier ](../sources/prs/vllm/PR-28687.md), [[Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op)](../sources/prs/vllm/PR-29213.md), [chore: add RTX_PRO_6000 GLM4.6-FP8 kernel tuning](../sources/prs/vllm/PR-29240.md), [[Perf] Disable DeepGEMM MoE by default when TP=8 is used](../sources/prs/vllm/PR-29346.md), [[Kernel]Support W4A8 Grouped GEMM on Hopper](../sources/prs/vllm/PR-29691.md), [[MoE-FP8-modelopt] Add FlashInfer alignment padding for intermediate dimensions](../sources/prs/vllm/PR-29748.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[Perf] Improve fp8 quant in mla; replace ReduceSum with ReduceScatterSum](../sources/prs/vllm/PR-29795.md), [[Bugfix] Fix FP8 MoE LoRA](../sources/prs/vllm/PR-29890.md), [[Kernel][Quantization][MoE] add marlin kernel support for turing (sm75)](../sources/prs/vllm/PR-29901.md), [[ROCm] add fallback for aiter fp8 decode mla](../sources/prs/vllm/PR-30005.md), [[Quantization] Support Quark int4-fp8 w4a8 for MoE](../sources/prs/vllm/PR-30071.md), [Add llmcompressor fp8 kv-cache quant (per-tensor and per-attn_head)](../sources/prs/vllm/PR-30141.md), [[Bugfix] Fix DeepGEMM after #29546 ](../sources/prs/vllm/PR-30267.md), [[LoRA] Support Quantized Adapters](../sources/prs/vllm/PR-30286.md), [[Bugfix] Fix fp8 DeepGemm compilation issues](../sources/prs/vllm/PR-30336.md), [[ROCm][Quantization] GPT OSS Upstream MoE wmxfp4_afp8 with static scales](../sources/prs/vllm/PR-30357.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Perf] Eliminate padding and slicing op for GPT-OSS with Flashinfer MXFP4 MXFP8 MoE](../sources/prs/vllm/PR-30647.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[Feature]: Support NVIDIA ModelOpt HF FP8 variants FP8_PER_CHANNEL_PER_TOKEN and FP8_PB_WO in vLLM](../sources/prs/vllm/PR-30957.md), [[Bugfix][Hardware][AMD] Consolidate FP8 min/max values helper function](../sources/prs/vllm/PR-31106.md), [[Bugfix][Hardware][AMD] Fix exception types in AITER MLA FP8 check](../sources/prs/vllm/PR-31177.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][ROCm] Fix Static Quant Issue](../sources/prs/vllm/PR-31502.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [[Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper](../sources/prs/vllm/PR-32619.md), [[Bugfix] Fix FP8 MoE EP Weight Loading for ModelOpt Llama4](../sources/prs/vllm/PR-32886.md), [Support compress-tensors with nvfp4 or fp8 weights and modelopt with nvfp4 weights on Turing](../sources/prs/vllm/PR-33076.md), [Add support for Mistral Large 3 inference with Flashinfer MoE](../sources/prs/vllm/PR-33174.md), [[Bugfix] Fix quant RMS norm fusion for quantization with TMA-aligned scales](../sources/prs/vllm/PR-33255.md), [[Bugfix] Register fp8 cutlass_group_gemm as supported for only SM90+SM100](../sources/prs/vllm/PR-33285.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [[Kernel] Add enable_sm120_or_later for SM121 (DGX Spark) CUTLASS support](../sources/prs/vllm/PR-33517.md), [[Perf] Disable clean_logits in deepgemm fp8_mqa_logits kernel](../sources/prs/vllm/PR-33568.md), [enable skipping of SW attention layers when using FP8 KV cache](../sources/prs/vllm/PR-33695.md), [[Kernel] Integrate SM100 MXFP8 blockscaled grouped MM and quant kernels](../sources/prs/vllm/PR-34448.md), [[Bugfix] Handle num_expert_group=None in flashinfer block-scale FP8 MoE](../sources/prs/vllm/PR-34494.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [Integrate flashinfer mm_mxfp8 in ModelOpt MXFP8](../sources/prs/vllm/PR-35053.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[Attention][Perf] Optimize cp_gather_and_upconvert_fp8_kv_cache - DeepSeek-v3.2](../sources/prs/vllm/PR-35290.md), [[Quant][Feature] Support online MXFP8 quantization for MoE and dense models](../sources/prs/vllm/PR-35448.md), [[ROCm] Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5/Linear)](../sources/prs/vllm/PR-35850.md), [[Perf] Support FP8 KV cache for Flashinfer MLA Sparse](../sources/prs/vllm/PR-35891.md), [Add support for ModelOpt MXFP8 MoE models](../sources/prs/vllm/PR-35986.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [[Perf] Add TRTLLM FP8 MoE Modular Kernel](../sources/prs/vllm/PR-36307.md), [[XPU] Support block fp8 moe by fallback to TritonExpert on XPU](../sources/prs/vllm/PR-36458.md), [[Kernel] Fuse FP8 output quantization into merge_attn_states](../sources/prs/vllm/PR-36518.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[Bugfix] Fix KV scales inconsistency in fp8 MLA & FlashInfer kv_cache_dtype "auto" leading to gibberish](../sources/prs/vllm/PR-37054.md), [[XPU] support MLA model on Intel GPU](../sources/prs/vllm/PR-37143.md), [[Perf] Set Flashinfer sparse MLA as default backend for FP8 kv cache](../sources/prs/vllm/PR-37252.md), [[Bugfix] Disable monolithic TRTLLM MoE for Renormalize routing (#37591)](../sources/prs/vllm/PR-37605.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[Bug] Fix fp8 deepgemm batch invariant](../sources/prs/vllm/PR-37718.md), [[Kernel] Optimize SM120 CUTLASS blockwise FP8 GEMM](../sources/prs/vllm/PR-37970.md), [[Perf] FP8 FlashInfer Attn for ViT](../sources/prs/vllm/PR-38065.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [[Kernel] Add swapAB support for SM120 CUTLASS blockwise FP8 GEMM ](../sources/prs/vllm/PR-38325.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[QeRL] Fix online quantized reloading](../sources/prs/vllm/PR-38442.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[XPU] add xpu backend implementation of mxfp8 quant](../sources/prs/vllm/PR-38682.md), [[Quant] add CompressedTensorsW8A8Mxfp8 for linear and MoE layers](../sources/prs/vllm/PR-38815.md), [[Bugfix] Re-enable Renormalize routing for TRT-LLM MoE experts](../sources/prs/vllm/PR-38859.md), [[Bugfix] Fix broken explicit unquantized kv cache dtype support](../sources/prs/vllm/PR-38922.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[Bug] Fix routing bias dtype for trtllm per-block fp8 moe](../sources/prs/vllm/PR-38989.md), [[Perf] Change Trtllm fp8 MoE to use Shuffled Weights and BlockMajorK Layout](../sources/prs/vllm/PR-38993.md), [[Bug] Fix Trtllm Fp8 MoE Weight Shuffle Memory Fragamentation](../sources/prs/vllm/PR-39054.md), [perf(moe): add tuned fused_moe config for RTX PRO 6000 Blackwell Server Edition](../sources/prs/vllm/PR-39183.md), [[Refactor] Move MXFP8 GEMM management into MxFp8LinearKernel](../sources/prs/vllm/PR-39205.md), [[Perf] Fuse Zero Initializer for FP8 DeepGemm Block Quant Kernel](../sources/prs/vllm/PR-39547.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[Perf] Batch invariance with Cutlass fp8 support, 28.9% E2E latency improvement](../sources/prs/vllm/PR-40408.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[Kernel][Helion] Optimize Helion config parsing latency](../sources/prs/vllm/PR-40850.md), [[DSV4] Add BF16 and MXFP8 A2A support for flashinfer a2a one sided](../sources/prs/vllm/PR-40960.md), [Faster per-token fp8 group quant packed kernel for blackwell](../sources/prs/vllm/PR-41326.md), [[Quantization] Rework quantization_config to use QuantKey and allow for activation override](../sources/prs/vllm/PR-41566.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[feat] Add FP8 per-tensor Q scale support to Triton attention backend](../sources/prs/vllm/PR-42080.md), [[Perf] Use 2D-grid to eliminate divmod in W8W8 group quant](../sources/prs/vllm/PR-42153.md), [[Perf] Wire silu_and_mul_per_block_quant into TritonFP8MoE (MiniMax-M2) ](../sources/prs/vllm/PR-42497.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [[Perf] Add do_not_specialize in fused FP8 RoPE kernel](../sources/prs/vllm/PR-42849.md), [add cutedsl dsv4 indexer fp8 kernel](../sources/prs/vllm/PR-42899.md), [[Model Refactoring] Move deepseek_v4_ops to models/deepseek_v4 [3/N]](../sources/prs/vllm/PR-43073.md), [NVFP4 and Block-Scaled Narrow Precision](../wiki/hardware/nvfp4.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [FP8 Block-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [Fused MoE — FP8 Block-Scale Routing + Dual GEMM](../wiki/kernels/fused-moe.md), [Grouped GEMM for MoE](../wiki/kernels/grouped-gemm.md), [Sparse MLA (DeepSeek V3.2)](../wiki/kernels/sparse-mla.md), [Fine-Grained FP8/FP4 Quantization](../wiki/techniques/fine-grained-quantization.md) | +| `2sm-cooperative` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax CUTLASS Tutorial: GEMM Kernels Using Tensor Memory for Blackwell](../sources/blogs/colfax-cutlass-blackwell.md), [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [CUTLASS 4.5.0 Cluster Launch Control Documentation](../sources/docs/cutlass-clc-documentation.md), [FlashAttention-4: Algorithm and Kernel Co-design for Blackwell GPUs](../sources/docs/flash-attention-4.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [Triton v3.6.0 — Incremental Blackwell Changes](../sources/docs/triton-3.6-blackwell.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [fix: examples/cute/tutorial/blackwell/04_mma_tma_2sm_sm100.cu GridDim miscalculated](../sources/prs/cutlass/PR-2492.md), [Feat([FA4][CUTE DSL]) Add head_dim=256 support (forward + backward)](../sources/prs/flash-attention/PR-2412.md), [[hd256] Improve forward kernel with exp2 FMA emulation (3% to 9% performance gain)](../sources/prs/flash-attention/PR-2488.md), [[hd256] Add TMA paged KV support to SM100 2CTA forward kernel](../sources/prs/flash-attention/PR-2489.md), [[FA4][hd256] Backward TMA bulk-store epilogue + LSE/dpsum coalesce](../sources/prs/flash-attention/PR-2497.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [Two-SM Cooperative MMA](../wiki/hardware/2sm-cooperative.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [Not Reaching the Relevant Compute Ceiling](../wiki/patterns/compute-bound.md) | +| `block-scale` | [Twelve Attempts at an FP4 Kernel](../sources/blogs/amandeep-nvfp4-attempts.md), [DeepGEMM — Pinned Upstream Project Summary](../sources/blogs/deepgemm.md), [NVFP4 Format Details](../sources/blogs/nvfp4-format-details.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [FlashInfer MLSys 2026 Track A: FP8 Block-Scale MoE](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [DeepSeek-V3 Technical Report: FP8 Training](../sources/docs/deepseek-v3-fp8.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.5.0 Blackwell Sources](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Transformer Engine 2.13: NVFP4](../sources/docs/nvidia-transformer-engine-2.13-nvfp4.md), [Triton v3.6.0 — Incremental Blackwell Changes](../sources/docs/triton-3.6-blackwell.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [feat: enable deepgemm jit for fp8 block-scale on SM90](../sources/prs/flashinfer/PR-1969.md), [feat: Support unpadded output hidden size for trtllm_fp4_block_scale_moe](../sources/prs/flashinfer/PR-2217.md), [fix: trtllm_mxint4_block_scale_moe unit test to index output list](../sources/prs/flashinfer/PR-2627.md), [int16 Block-Scaled State and Stochastic Rounding for SSU (mamba)](../sources/prs/flashinfer/PR-2645.md), [Support in-place update for `trtllm_fp8_block_scale_moe`](../sources/prs/flashinfer/PR-2739.md), [fix: int32 overflow in `trtllm_fp4_block_scale_moe` causing "Unsupported hidden state scale shape" for EP32+ configs](../sources/prs/flashinfer/PR-2853.md), [fix: snap weight_scale_vec_size to handle block_scale_interleave padding for SM120](../sources/prs/flashinfer/PR-2898.md), [fix: Fix autotuner crash on meta-device tensor in trtllm_fp4_block_scale_routed_moe](../sources/prs/flashinfer/PR-2916.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [[Perf] Eliminate the slice op for Flashinfer `trtllm_fp4_block_scale_moe`](../sources/prs/sglang/PR-15731.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[FEAT] [ROCm]: Add AITER Block-Scaled GEMM Feature](../sources/prs/vllm/PR-14968.md), [[Kernel][B200] mxfp4 fused cutlass moe](../sources/prs/vllm/PR-23696.md), [[Bugfix] Handle num_expert_group=None in flashinfer block-scale FP8 MoE](../sources/prs/vllm/PR-34494.md), [NVFP4 and Block-Scaled Narrow Precision](../wiki/hardware/nvfp4.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [FP8 Fine-Grained-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [FlashInfer Track A FP8 Block-Scale MoE](../wiki/kernels/fused-moe.md), [GPU Mode NVFP4 Gated Dual GEMM](../wiki/kernels/gated-dual-gemm.md), [NVFP4 GEMM — GPU Mode Problem 2 Contract](../wiki/kernels/nvfp4-gemm.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md), [Fine-Grained FP8/FP4 Quantization](../wiki/techniques/fine-grained-quantization.md) | +| `clc` | [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [CUTLASS 4.5.0 Cluster Launch Control Documentation](../sources/docs/cutlass-clc-documentation.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.5.0 Blackwell Sources](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [[Cute-DSL] Add option for issue_clc_query without multicast](../sources/prs/cutlass/PR-3021.md), [[Ai-assisted] CLC work stealing](../sources/prs/flash-attention/PR-2218.md), [Add CLC scheduler heuristic](../sources/prs/flash-attention/PR-2455.md), [[V1][P/D]P2pNcclConnector supports flashinfer](../sources/prs/vllm/PR-23536.md), [Cluster Launch Control (CLC)](../wiki/hardware/clc.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Low SM Utilization](../wiki/patterns/low-sm-utilization.md), [MoE Expert Load Imbalance](../wiki/patterns/moe-load-imbalance.md), [Tail Effect — Last-Wave Underutilization](../wiki/patterns/tail-effect.md), [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md), [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md) | +| `cluster` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [CUTLASS 4.5.0 Cluster Launch Control Documentation](../sources/docs/cutlass-clc-documentation.md), [Two-SM Cooperative MMA](../wiki/hardware/2sm-cooperative.md) | +| `fp4` | [Twelve Attempts at an FP4 Kernel](../sources/blogs/amandeep-nvfp4-attempts.md), [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Anatomy of a Reward Hack](../sources/blogs/gpu-mode-reward-hack.md), [NVFP4 Format Details](../sources/blogs/nvfp4-format-details.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Transformer Engine 2.13: NVFP4](../sources/docs/nvidia-transformer-engine-2.13-nvfp4.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.](../sources/prs/TensorRT-LLM/PR-10339.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[None][feat] Optimize super-v3 nvfp4 for better perf](../sources/prs/TensorRT-LLM/PR-11273.md), [[None][feat] Optimize by fuse nvfp4_quant to layernorm_gated for mamba2_mixer](../sources/prs/TensorRT-LLM/PR-11473.md), [[None][feat] Add support for expert_number<=2048 and K<=32](../sources/prs/TensorRT-LLM/PR-11510.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[None][fix] Fix SM120 issue for rms_norm with nvfp4_quant_fusion](../sources/prs/TensorRT-LLM/PR-11774.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[None][feat] Update rms_norm + fp4_qaunt kernel supporting more dim](../sources/prs/TensorRT-LLM/PR-13033.md), [[None][feat] Add FP4 residual quantization kernel without channel reo…](../sources/prs/TensorRT-LLM/PR-13117.md), [[None][feat] Integrate FP4 indexer for DSA on Blackwell](../sources/prs/TensorRT-LLM/PR-13340.md), [[TRTLLM-11127][feat] add W4A8_MXFP4_FP8 MoE unit test support](../sources/prs/TensorRT-LLM/PR-13401.md), [[TRTLLM-12316][feat] Integrate FP4 indexer for DSv4](../sources/prs/TensorRT-LLM/PR-13575.md), [[TRTLLM-12503][feat] Parallel VAE independent scaling and fix arg passing](../sources/prs/TensorRT-LLM/PR-13873.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[https://nvbugs/6025177][test] rcca tests using kimi k2.5 fp4](../sources/prs/TensorRT-LLM/PR-14172.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[None][feat] add fp4 gemm + allreduce](../sources/prs/TensorRT-LLM/PR-9729.md), [[None][feat] Port fp4 quantization kernel optimization from FlashInfer](../sources/prs/TensorRT-LLM/PR-9854.md), [bugfix: Fix test and output shape of fp4 quantize](../sources/prs/flashinfer/PR-1114.md), [Add fp4 quantization swizzling tests](../sources/prs/flashinfer/PR-1157.md), [Expose fp4 blockscale swizzling kernel](../sources/prs/flashinfer/PR-1176.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [Reduce the JIT compilation time of gen_gemm_sm100_module](../sources/prs/flashinfer/PR-1251.md), [add mm_fp4 use cudnn backend](../sources/prs/flashinfer/PR-1288.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [add cutlass backend for mm_fp4](../sources/prs/flashinfer/PR-1296.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [Support loading autotuned results from json for cutlass fp4 moe backends](../sources/prs/flashinfer/PR-1310.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [feat: masked layout fp4 gemm using cute-dsl](../sources/prs/flashinfer/PR-1331.md), [add torch float4_e2m1fn_x2 check for cudnn fp4 backend](../sources/prs/flashinfer/PR-1333.md), [[Fix] remove torch 2.8 requirement for FP4 GEMM](../sources/prs/flashinfer/PR-1334.md), [feature: add fp4 mm using trtllm backend](../sources/prs/flashinfer/PR-1355.md), [hotfix: update mxfp4 groupwise-scaled gemm unittests](../sources/prs/flashinfer/PR-1359.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Update autotune results for the nvfp4 cutlass moe backends for v0.2.9](../sources/prs/flashinfer/PR-1361.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [bugfix: fixed cutlass fused moe usage of FP4QuantizationSFLayout::SWIZZLED](../sources/prs/flashinfer/PR-1371.md), [bugfix: Add guard for fp4/fp8 related include headers](../sources/prs/flashinfer/PR-1376.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [Add Mxfp4 trtllm-gen moe unit tests](../sources/prs/flashinfer/PR-1399.md), [feature: enable cublas for fp4 gemm when cudnn == 9.11.1 or >= 9.13](../sources/prs/flashinfer/PR-1405.md), [Faster weight processing (moe nvfp4)](../sources/prs/flashinfer/PR-1412.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [tuner: Trtllm-gen Fp4 MoE Autotunner](../sources/prs/flashinfer/PR-1475.md), [fix missing enable_pdl argument in trtllm-gen fp4 moe](../sources/prs/flashinfer/PR-1480.md), [Add python API for masked grouped gemm](../sources/prs/flashinfer/PR-1481.md), [fix: update masked moe gemm fp4 tensor reshape](../sources/prs/flashinfer/PR-1495.md), [feat: scaling at fp4 gemm epilogue](../sources/prs/flashinfer/PR-1498.md), [refactor fp4 masked gemm cute-dsl implementation and add manual cache](../sources/prs/flashinfer/PR-1521.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [fix: separate out fp4 lib into sm90 and sm100 versions, add oob checking in fused moe](../sources/prs/flashinfer/PR-1565.md), [update trtllm-gen fp4 autotuner and routing](../sources/prs/flashinfer/PR-1573.md), [bugfix: Fix test_fp4_quantize test bug](../sources/prs/flashinfer/PR-1585.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [feat: cutlass fp4 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1609.md), [bugfix: fix fp4 quantization with 8x4 scale factor layout](../sources/prs/flashinfer/PR-1611.md), [feat: add support of fp4_batched_quantize](../sources/prs/flashinfer/PR-1633.md), [Added mx_fp4 support using the cudnn backend](../sources/prs/flashinfer/PR-1644.md), [[Hotfix] `test_fp4_quantize.py` failure on sm103](../sources/prs/flashinfer/PR-1666.md), [feat: Benchmark mm_fp4 mxfp4 support and gemm autotune support. Restore mm_fp4 API behavior](../sources/prs/flashinfer/PR-1706.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [Added xfail for mx_fp4 matmul on SM120](../sources/prs/flashinfer/PR-1766.md), [Masked batch nvfp4 quantization](../sources/prs/flashinfer/PR-1774.md), [Support checks PoC](../sources/prs/flashinfer/PR-1809.md), [fix: fp4 moe on sm120](../sources/prs/flashinfer/PR-1817.md), [[Quantization] Add per-expert global scaling factor for fp4 batched quantize](../sources/prs/flashinfer/PR-1835.md), [raise error for group_gemm_fp8_nt_groupwise then num_groups > 1 on sm120/121](../sources/prs/flashinfer/PR-1862.md), [feat: Add FP4 TRTLLM-Gen throughput MOE batched gemms](../sources/prs/flashinfer/PR-1882.md), [silu_and_mul nvfp4 quanization fusion rework](../sources/prs/flashinfer/PR-1927.md), [fix: Add cutlass as an mm_fp4 backend in compute capability 12.0 in benchmark code](../sources/prs/flashinfer/PR-1959.md), [feat: Add backend='auto' to mm_fp4 and enable autotune for backend='cudnn'](../sources/prs/flashinfer/PR-1979.md), [Feature: Support non-gated activation in cutlass fused MoE nvfp4](../sources/prs/flashinfer/PR-2011.md), [fix: Enable SM121 for mm_fp4](../sources/prs/flashinfer/PR-2012.md), [[DSV3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2019.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE](../sources/prs/flashinfer/PR-2025.md), [[BUG] Fix trtllm-gen fp4 moe renormalize routing](../sources/prs/flashinfer/PR-2049.md), [Patch sm103 for 3xfp4 moe generation](../sources/prs/flashinfer/PR-2082.md), [perf: enable pdl for cutlass fp4 gemm](../sources/prs/flashinfer/PR-2095.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [Add data type check for deepseek fp4 moe](../sources/prs/flashinfer/PR-2165.md), [feat: Support unpadded output hidden size for trtllm_fp4_block_scale_moe](../sources/prs/flashinfer/PR-2217.md), [feat: Fused RMSNorm + FP4 Quantization Kernels in CuTe-DSL](../sources/prs/flashinfer/PR-2233.md), [fix: Add global scale support and optional output allocation for RMSNorm+FP4Quant fusion kernels](../sources/prs/flashinfer/PR-2260.md), [[performance]optimize for nvfp4](../sources/prs/flashinfer/PR-2268.md), [[WIP] Refactor: simplify torch -> cute-dsl boilerplate and enable tvm-ffi for cute-dsl kernels](../sources/prs/flashinfer/PR-2279.md), [[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels](../sources/prs/flashinfer/PR-2303.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [Optimize quantization function in large problem size](../sources/prs/flashinfer/PR-2343.md), [fix: In-place Residual Update for add_rmsnorm_fp4quant](../sources/prs/flashinfer/PR-2385.md), [feat: Add output_both_sf_layouts option to add_rmsnorm_fp4quant API](../sources/prs/flashinfer/PR-2395.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [perf: mm_fp4 heuristic prioritizes CUTLASS over cuDNN on SM103](../sources/prs/flashinfer/PR-2404.md), [refactor: simplify fp4 rmsnorm](../sources/prs/flashinfer/PR-2421.md), [refactor: refactoring cuda code to cute-dsl (part 1)](../sources/prs/flashinfer/PR-2428.md), [Add cute-dsl backends to mxfp[8,4]_quantization for future refactor](../sources/prs/flashinfer/PR-2443.md), [perf: add fp4 GEMM tile configs and streamK scheduler for SM120](../sources/prs/flashinfer/PR-2460.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [feat: cute dsl mmfp4 for blackwell](../sources/prs/flashinfer/PR-2540.md), [[Bugfix][comm] Fix FP4 one-shot launch config instability in trtllm_allreduce_fusion](../sources/prs/flashinfer/PR-2557.md), [[Bug] Fix spark unit test failures for test_add_rmsnorm_fp4_quant_cute_dsl](../sources/prs/flashinfer/PR-2573.md), [tests: add bias testing to nvfp4 moe](../sources/prs/flashinfer/PR-2585.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [benchmark: Add MXFP4/MXFP8 quantization mode support to FP4 MoE benchmark](../sources/prs/flashinfer/PR-2635.md), [Enable sm120f compilation](../sources/prs/flashinfer/PR-2650.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [feat: support mxfp4 & mxfp8 entrypoint for blackwell cutedsl dense gemm](../sources/prs/flashinfer/PR-2660.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [fix: Add SM120 (RTX Blackwell desktop) support for NVFP4 MoE kernels](../sources/prs/flashinfer/PR-2725.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [feat: Add FP4 KV cache quant/dequant kernels ](../sources/prs/flashinfer/PR-2757.md), [feat: Add CuTe-DSL backend for NVFP4 quantization](../sources/prs/flashinfer/PR-2838.md), [fix: int32 overflow in `trtllm_fp4_block_scale_moe` causing "Unsupported hidden state scale shape" for EP32+ configs](../sources/prs/flashinfer/PR-2853.md), [fix: snap weight_scale_vec_size to handle block_scale_interleave padding for SM120](../sources/prs/flashinfer/PR-2898.md), [perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels](../sources/prs/flashinfer/PR-2904.md), [fix: Fix autotuner crash on meta-device tensor in trtllm_fp4_block_scale_routed_moe](../sources/prs/flashinfer/PR-2916.md), [CuTe DSL FP4 GEMM Heuristic](../sources/prs/flashinfer/PR-2940.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [ Fix MXFP4/MXFP8 failures in SM120 FAST_BUILD and expand all_tiles[] ](../sources/prs/flashinfer/PR-2994.md), [feat: add PDL support to rmsnorm_fp4quant and add_rmsnorm_fp4quant CuTe DSL kernels](../sources/prs/flashinfer/PR-3008.md), [perf: Port TRT-LLM SM120/SM121 FP4 CUTLASS GEMM optimizations. Add PDL](../sources/prs/flashinfer/PR-3026.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [feat: Add backend="b12x" for mm_fp4 on SM120](../sources/prs/flashinfer/PR-3051.md), [feat: Add b12x CuTe DSL fused MoE for SM120](../sources/prs/flashinfer/PR-3066.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [perf: optimize per-token nvfp4 quantization kernel.](../sources/prs/flashinfer/PR-3237.md), [feat(moe): add SM120 W4A16 b12x kernels](../sources/prs/flashinfer/PR-3271.md), [feat: Add FP4 (E2M1) KV Cache Support with Quantization Utilities for MLA](../sources/prs/sglang/PR-10078.md), [Optimize nvfp4 block scaled gemm kernel when M is small.](../sources/prs/sglang/PR-10101.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [feat: add dsv3 fp4 cutlass moe etp ut](../sources/prs/sglang/PR-10433.md), [Fix bias handling in TritonMoeQuantInfo within quantization/mxfp4.py](../sources/prs/sglang/PR-10579.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [Use cutlass fp4 gemm by default](../sources/prs/sglang/PR-11813.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [Replace [silu_and_mul_]scaled_fp4_group_quant by Flashinfer equivalent](../sources/prs/sglang/PR-12376.md), [Use sgl fp4 quant kernel by default](../sources/prs/sglang/PR-12482.md), [[NVIDIA] Fix CUDA arch requirement in nvfp4 cast](../sources/prs/sglang/PR-12581.md), [feat: Add FP4 (E2M1) KV Cache Support for MHA](../sources/prs/sglang/PR-12612.md), [[NVIDIA] Fix wrong symmetric sizes for fp4 cases](../sources/prs/sglang/PR-12640.md), [[Bugfix] Fix illegal memory access](../sources/prs/sglang/PR-12758.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [Fix EPLB + FP4 Quantization Compatibility Issue](../sources/prs/sglang/PR-13715.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [Fix flashinfer cutlass MoE output shape for non-FP4-packed inputs](../sources/prs/sglang/PR-14028.md), [[FIX] trtllm-moe-fp4-renorm for Qwen series models](../sources/prs/sglang/PR-14350.md), [[CPU] Implement MXFP4 Gemm kernels for intel AMX to support GPT OSS series.](../sources/prs/sglang/PR-14385.md), [Mistral Large 3 NVFP4 support](../sources/prs/sglang/PR-14485.md), [[AMD] Support fused_rms_mxfp4_quant in the prefill stage for DeepSeek-R1-MXFP4](../sources/prs/sglang/PR-14975.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [[NVIDIA] Fixes for NVFP4 all-gather with spec decoding](../sources/prs/sglang/PR-15280.md), [Fix the accuracy issue when running mxfp4 dsv3 model and enable ep](../sources/prs/sglang/PR-15304.md), [Update flashinfer to 0.6.1](../sources/prs/sglang/PR-15551.md), [[Perf] Eliminate the slice op for Flashinfer `trtllm_fp4_block_scale_moe`](../sources/prs/sglang/PR-15731.md), [Tiny fix cannot launch nvfp4 checkpoint with bf16 kv cache](../sources/prs/sglang/PR-15986.md), [[Performance] Force split_k=1 for MXFP4 Triton kernels on Hopper](../sources/prs/sglang/PR-16014.md), [Inclusion of nvfp4 blockscale in EPLB Rebalance](../sources/prs/sglang/PR-17158.md), [[Fix] GLM 4.7 + NVFP4 + MTP](../sources/prs/sglang/PR-17166.md), [[FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/sglang/PR-17300.md), [[feat] Support nvfp4 quantized model of Qwen3-Next](../sources/prs/sglang/PR-17627.md), [fix(quantization): add sgl_kernel fallback for FP4 quantize on Blackwell GPUs](../sources/prs/sglang/PR-17816.md), [[Bugfix] Fix Mistral Large 3 NVFP4 TRTLLM MoE](../sources/prs/sglang/PR-18065.md), [Fix nvfp4 weight update](../sources/prs/sglang/PR-18085.md), [[ModelOpt] Fix broken Qwen3-235B-A22B-Instruct-2507-NVFP4 launch](../sources/prs/sglang/PR-18189.md), [[ModelOPT] Support Qwen 3 Next Coder NVFP4](../sources/prs/sglang/PR-18224.md), [[Kimi-K2.5] Fix NVFP4 Kimi-K2.5 weight mapping and exclude list](../sources/prs/sglang/PR-18370.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[Perf] ~9.5x faster Blackwell MXFP4 MoE weight loading](../sources/prs/sglang/PR-18858.md), [[Qwen3.5] Enable nvfp4 checkpoint](../sources/prs/sglang/PR-18937.md), [feat: Support MXFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-19143.md), [Adjust padding size to improve triton_kernels moe performance](../sources/prs/sglang/PR-19174.md), [Fix nightly Mistral-Large-3 NVFP4 accuracy threshold](../sources/prs/sglang/PR-19402.md), [[AMD] Fix weight load shape mismatch for amd dsr1 0528 mxfp4](../sources/prs/sglang/PR-19425.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Support `triton_kernels` for GPT-OSS on SM120](../sources/prs/sglang/PR-19718.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [Fix SM120 `triton_kernels` MXFP4 `block_k` for GPT-OSS](../sources/prs/sglang/PR-20040.md), [MiniMax-M2.5 - Support dp attention, dp reduce scatter, FP4 all gather, AR fusion in prepare_attn](../sources/prs/sglang/PR-20067.md), [[V32/GLM5] Change default setting of V32 nvfp4 on TP4](../sources/prs/sglang/PR-20086.md), [[diffusion] Support nvfp4 for Flux.2](../sources/prs/sglang/PR-20137.md), [[4/n jit_kernel restruct] speed up CI tests and add benchmark workflow](../sources/prs/sglang/PR-20268.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[Model] Support Nemotron 3 Super NVFP4](../sources/prs/sglang/PR-20407.md), [[JIT Kernel] Fix NVFP4 multi-arch compilation failure](../sources/prs/sglang/PR-20874.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Chore] Clean up JIT compilation flags](../sources/prs/sglang/PR-21022.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[NVIDIA] Enable FP4 flashinfer trtllm routed moe](../sources/prs/sglang/PR-21240.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[Kernel] Support FlashInfer TRTLLM-Gen fused MoE for non-gated FP4 & FP8 (Nemotron)](../sources/prs/sglang/PR-21321.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Add dedicated FlashInferCuteDslMoE layer for standard-path FP4 MoE](../sources/prs/sglang/PR-21339.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [Harden FlashInfer FP4 imports in standard dispatcher](../sources/prs/sglang/PR-21776.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[diffusion] Default NVFP4 to CUTLASS and add all-model shape benchmarks](../sources/prs/sglang/PR-22091.md), [[Diffusion] Add diffusion NVFP4 scaled-mm correctness test](../sources/prs/sglang/PR-22127.md), [[RL] Refactor NVFP4 shuffling/swizzling to in-place replacement](../sources/prs/sglang/PR-22204.md), [:sparkles: [diffusion][npu][quant] Add MXFP4 quantization support for Wan2.2 Diffusion on Ascend NPU](../sources/prs/sglang/PR-22338.md), [GLM-5/5.1 MXFP4 Checkpoint Inference Compatibility Fix](../sources/prs/sglang/PR-22543.md), [[Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22574.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [[Diffusion] Add Wan2.2 ModelOpt NVFP4 support](../sources/prs/sglang/PR-22681.md), [[FlashInfer v0.6.11] [RL] Support FlashInfer per-token NVFP4 MoE](../sources/prs/sglang/PR-22918.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [[MoE] Unify DeepEPMoE+MoriEPMoE through AITER MoeRunner pre/post-permute](../sources/prs/sglang/PR-23760.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [Add FlashInfer SM90 cutlass MXFP4 MoE backend (W4A16) for GPT-OSS + DeepSeek-V4](../sources/prs/sglang/PR-24816.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [perf(nvfp4): free unused source scales after weight processing](../sources/prs/sglang/PR-25107.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[AMD] Enable shared-experts fusion with new KIMI-K2.5-MXFP4 model.](../sources/prs/sglang/PR-25390.md), [[codex] Update Wan2.2 ModelOpt CI checkpoints](../sources/prs/sglang/PR-25483.md), [Add no_combine support to cutlass_moe_fp4](../sources/prs/sglang/PR-25688.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [[Build] Fix cuda12.8 build error in nvfp4_scaled_mm_kernels.cu](../sources/prs/sglang/PR-4953.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [[DeepseekR1-FP4] Add Support for nvidia/DeepSeekR1-FP4 model](../sources/prs/sglang/PR-6853.md), [Fix Deepseek R1 0528 FP4 tensor name mismatch issue during weights loading.](../sources/prs/sglang/PR-7164.md), [Support NVFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-7302.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Fix MTP with Deepseek R1 Fp4](../sources/prs/sglang/PR-7376.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [Qwen FP8/NVFP4 ModelOPT Quantization support](../sources/prs/sglang/PR-7912.md), [[Fix][Ready]Fix register spilling in cutlass nvfp4 gemm kernel on Blackwell](../sources/prs/sglang/PR-8127.md), [[fix] fix modelopt fp4 on b200](../sources/prs/sglang/PR-8195.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [[Perf] Auto enable best flashinfer mxfp4 kernel in b200](../sources/prs/sglang/PR-8898.md), [Fix hopper launch gpt-oss model illegal memory](../sources/prs/sglang/PR-8908.md), [Faster weight processing (trtllm-gen moe nvfp4)](../sources/prs/sglang/PR-9162.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [Fix FP4 inference corruption issue in glm4.5-air model](../sources/prs/sglang/PR-9346.md), [[fix] Fix mxfp4 triton MoE tp bug](../sources/prs/sglang/PR-9473.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[ModelOpt] Fix Weight Loading for DSR1-FP4 Quantization](../sources/prs/sglang/PR-9712.md), [Make fp4_quantize kernels work on sm103](../sources/prs/sglang/PR-9807.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[TMA] Support FP4 TensorMap TMA copies](../sources/prs/tilelang/PR-2107.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[NVIDIA] Support nvfp4 quantization](../sources/prs/vllm/PR-12784.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[Hardware/NVIDIA/Kernel] [Functional Enablement] [1/N] Enable nvidia/DeepSeek-R1-FP4 Model](../sources/prs/vllm/PR-16362.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [[Misc] Add compressed-tensors NVFP4A16 emulation support](../sources/prs/vllm/PR-17914.md), [Use NVFP4 Marlin for CompressedTensorsW4A16Fp4](../sources/prs/vllm/PR-18000.md), [[Quantization] Add compressed-tensors NVFP4 support](../sources/prs/vllm/PR-18312.md), [[V1] Support `LLM.apply_model`](../sources/prs/vllm/PR-18465.md), [[Hardware][NVIDIA] FP4 MoE kernel optimization](../sources/prs/vllm/PR-19110.md), [[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization](../sources/prs/vllm/PR-19500.md), [[Quantization] Add compressed-tensors emulations support for NVFP4](../sources/prs/vllm/PR-19879.md), [[Quantization] Add compressed-tensors NVFP4 MoE Support](../sources/prs/vllm/PR-19990.md), [Add ModelOpt Qwen3 nvfp4 support](../sources/prs/vllm/PR-20101.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [[Kernel][Bugfix] Fixup some warnings in nvfp4_blockwise_moe when CUDA < 12.8](../sources/prs/vllm/PR-20324.md), [Support Llama 4 for cutlass_moe_fp4](../sources/prs/vllm/PR-20453.md), [[Perf] Reuse workspace for FP8+FP4 Marlin MoE](../sources/prs/vllm/PR-20500.md), [Support mnnvl all2allv from Flashinfer](../sources/prs/vllm/PR-21003.md), [[Feature][OCP MX] Support mxfp6 and mixed mxfp6-mxfp4](../sources/prs/vllm/PR-21166.md), [Support CUTLASS NVFP4 (w4a4) for Blackwell Geforce GPUs (SM120)](../sources/prs/vllm/PR-21309.md), [Support Tensorrt-LLM MoE fp4 for low-latency](../sources/prs/vllm/PR-21331.md), [Update flashinfer CUTLASS NVFP4 MoE Kernel to use per expert global scaling factor](../sources/prs/vllm/PR-21408.md), [[Bug] Fix Compressed Tensor NVFP4 `cutlass_fp4_group_mm` illegal memory access](../sources/prs/vllm/PR-21465.md), [[NVIDIA] Fix Llama4 Scout FP4 functionality issues](../sources/prs/vllm/PR-21499.md), [[Feature] Add Flashinfer MoE Support for Compressed Tensor NVFP4](../sources/prs/vllm/PR-21639.md), [[gpt-oss] flashinfer mxfp4](../sources/prs/vllm/PR-22339.md), [[gpt-oss] triton kernel mxfp4](../sources/prs/vllm/PR-22421.md), [Fix Llama4 FlashInfer FP4 MoE issues](../sources/prs/vllm/PR-22511.md), [Quantization: support FP4 quantized models on AMD CDNA2/CDNA3 GPUs](../sources/prs/vllm/PR-22527.md), [Fix torch version check for SM100 mxfp4 ](../sources/prs/vllm/PR-22535.md), [[Quantization] Expand compressed-tensors MoE matching logic to support NFP4 + FP8 MoEs](../sources/prs/vllm/PR-22674.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [Use Blackwell FlashInfer MXFP4 MoE by default if available ](../sources/prs/vllm/PR-23008.md), [Add routed_scaling_factor to MoE grouped topk](../sources/prs/vllm/PR-23123.md), [Fix nvfp4 swizzling](../sources/prs/vllm/PR-23140.md), [[Kernels] Overlap shared experts with send/recv](../sources/prs/vllm/PR-23273.md), [fix incompatibililty with non cuda platform for nvfp4](../sources/prs/vllm/PR-23478.md), [Update Flashinfer to 0.2.14.post1](../sources/prs/vllm/PR-23537.md), [DP/EP Support for gpt-oss with deepep-ht comm kernel on SM100](../sources/prs/vllm/PR-23608.md), [[Bugfix] Fix Marlin NVFP4 for modelopt](../sources/prs/vllm/PR-23659.md), [[NVIDIA] Support SiluMul + NVFP4 quant fusion](../sources/prs/vllm/PR-23671.md), [[Kernel][B200] mxfp4 fused cutlass moe](../sources/prs/vllm/PR-23696.md), [[Bugfix][Misc] Fix silu_and_mul_nvfp4_quant issue and extract common utils for nvfp4 kernel source files](../sources/prs/vllm/PR-23727.md), [[Model][gpt-oss] Support DP+EP for GPT-OSS with FlashInfer trtllm-gen MoE](../sources/prs/vllm/PR-23819.md), [[BUGFIX ] fix undefined silu_and_mul_nvfp4_quant](../sources/prs/vllm/PR-23929.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Transform] [Quantization] Add QuTLASS support to vLLM](../sources/prs/vllm/PR-24440.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [[Bugfix] Fix accuracy issue for silu_mul + nvfp4 quant fusion kernel](../sources/prs/vllm/PR-24833.md), [[Compile] Fix Compile Warning for Ignoring `MIN_BLOCK_PER_SM`](../sources/prs/vllm/PR-25193.md), [[ROCm] Small functional changes for gptoss](../sources/prs/vllm/PR-25201.md), [Enable Fbgemm NVFP4 on Dense models](../sources/prs/vllm/PR-25609.md), [[Bugfix] Enable padded FP4 quantization](../sources/prs/vllm/PR-25947.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Bugfix] Allow skipping MoE in NVFP4 (fix for MTP)](../sources/prs/vllm/PR-25987.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[NVIDIA] Add support for cudnn fp4 gemm via flashinfer](../sources/prs/vllm/PR-26107.md), [[ModelOpt] Load w13/w2_input_scale for all experts, nvfp4](../sources/prs/vllm/PR-26135.md), [[ROCM] MoE fp4 CK kernel](../sources/prs/vllm/PR-26545.md), [support flashinfer_fp4 moe for 5090 gpu](../sources/prs/vllm/PR-26669.md), [[NVIDIA] [Perf] Update to leverage flashinfer trtllm FP4 MOE throughput kernel](../sources/prs/vllm/PR-26714.md), [[Bugfix] Fix gpt-oss w4a8 DP/EP on B200](../sources/prs/vllm/PR-26729.md), [Flashinfer_CUTLASS_MOE fuses quantization for TP](../sources/prs/vllm/PR-27223.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Bugfix] Fix GPT-OSS on AMD after #28603](../sources/prs/vllm/PR-28816.md), [Add TRTLLM MoE NVFP4 kernel to CompressedTensorsW4A4MoeMethod](../sources/prs/vllm/PR-28892.md), [[Feat] Support non-gated activations in NVFP4 modelopt path](../sources/prs/vllm/PR-29004.md), [[Kernel] Add NVFP4 MoE CUTLASS support for SM120](../sources/prs/vllm/PR-29242.md), [[Bugfix] Only use triton_kernels for MXFP4 on SM90 and SM100](../sources/prs/vllm/PR-29339.md), [[Bugfix] Fix mismatched nvfp4 gemm output shape](../sources/prs/vllm/PR-29742.md), [[ROCm][MXFP4] Infer w4a4 quant method in rocm aiter fused moe](../sources/prs/vllm/PR-29775.md), [[EPLB] Support EPLB w/ NVFP4](../sources/prs/vllm/PR-29804.md), [[Perf] Do FP4 quant before All gather on flashinfer trtllmgen MOE ](../sources/prs/vllm/PR-30014.md), [[ROCm][Quantization] GPT OSS Upstream MoE wmxfp4_afp8 with static scales](../sources/prs/vllm/PR-30357.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Perf] Set split_k to 1 for triton_kernels](../sources/prs/vllm/PR-30528.md), [[Perf] Eliminate padding and slicing op for GPT-OSS with Flashinfer MXFP4 MXFP8 MoE](../sources/prs/vllm/PR-30647.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[Compressed-Tensors] Simplify NVFP4 Conditions, enable marlin support for NVFP4A16 MoEs](../sources/prs/vllm/PR-30881.md), [[Kernel][Performance] Enable smaller Scaling Factor tiling for NVFP4 small-batch decoding](../sources/prs/vllm/PR-30885.md), [[NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size](../sources/prs/vllm/PR-30897.md), [ [FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/vllm/PR-31099.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[Perf] Fuse stride preparation for NVFP4 cutlass_moe](../sources/prs/vllm/PR-31837.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [[Perf][Kernel] Optimize FP4 quantization kernels (SM100F)](../sources/prs/vllm/PR-32520.md), [Support compress-tensors with nvfp4 or fp8 weights and modelopt with nvfp4 weights on Turing](../sources/prs/vllm/PR-33076.md), [fix: Add SM120 (RTX Blackwell) support for FlashInfer CUTLASS NVFP4 MoE kernels](../sources/prs/vllm/PR-33417.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [[Bugfix]fix output Nan/Inf in marlin if dtype=float16](../sources/prs/vllm/PR-33972.md), [[ModelBash][DSR1 NVFp4] Avoid Bf16 Bias Cast](../sources/prs/vllm/PR-34298.md), [[Custom Ops] Add functional + out variant for scaled_fp4_quant](../sources/prs/vllm/PR-34389.md), [[BUGFIX] Fix accuracy regression for NVIDIA-Nemotron-3-Nano-30B-A3B-NVFP4 with TP>1](../sources/prs/vllm/PR-34476.md), [[Model] Add NVFP4 quantization support for Step3.5-Flash](../sources/prs/vllm/PR-34478.md), [[Bugfix] Rescale NVFP4 weight scales to fix BF16 dequant underflow](../sources/prs/vllm/PR-34577.md), [[torch.compile] Turn on silu+fp4 quant fusion by default for O1+](../sources/prs/vllm/PR-34718.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [[BugFix] Fix fp4 quant kernel on CUDA 12.8](../sources/prs/vllm/PR-35210.md), [fix(mxfp4): return is_monolithic=False when LoRA is enabled for Triton backend](../sources/prs/vllm/PR-35382.md), [[NVFP4] Support NVFP4 dense models from `modelopt` and `compressed-tensors` on AMD Instinct MI300, MI355X and Hopper through emulation](../sources/prs/vllm/PR-35733.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[Mamba] Flashinfer selective_state_update](../sources/prs/vllm/PR-36162.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [[Bug][MoE] Fix TRTLLM NVFP4 Routing Kernel Precision](../sources/prs/vllm/PR-36725.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[MoE Refactor] Mxfp4 oracle rebased](../sources/prs/vllm/PR-37128.md), [Fix minimax m2.5 nvfp4 kv scales weight loading](../sources/prs/vllm/PR-37214.md), [[MoE/EPLB] Fix FlashInfer nvfp4 experts + EPLB correctness](../sources/prs/vllm/PR-37217.md), [[Kernel] Add non-gated support for NVFP4 CUTLASS MoE](../sources/prs/vllm/PR-37320.md), [[Bugfix] Fix EP weight filter breaking EPLB and NVFP4 accuracy](../sources/prs/vllm/PR-37322.md), [Add nvfp4 support to reshape_and_cache_flash](../sources/prs/vllm/PR-37332.md), [[Kernel] Add MXFP4 W4A4 CUTLASS MoE kernel for SM100](../sources/prs/vllm/PR-37463.md), [[Bugfix] Remove assertion for NVFP4 scale dynamic range](../sources/prs/vllm/PR-37465.md), [[Bugfix] Fix marlin nvfp4 rescaling](../sources/prs/vllm/PR-37502.md), [[4/n] Migrate FP4/W4A8 CUTLASS kernels to torch stable ABI](../sources/prs/vllm/PR-37503.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[Bugfix] Preserve CUDA arch suffix (a/f) for SM12x — fixes NVFP4 NaN on desktop Blackwell](../sources/prs/vllm/PR-37725.md), [[MoE] Move FlashInfer CuteDSL experts into fused_moe/experts/](../sources/prs/vllm/PR-37759.md), [[MoE Kernel] Flashinfer nvfp4 cutedsl moe kernel integration](../sources/prs/vllm/PR-38050.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [Fix NaN from stale FP4 scale padding in create_fp4_scale_tensor](../sources/prs/vllm/PR-38148.md), [[Quantization] Add FlashInfer CuteDSL batched experts backend for NVFP4 MoE](../sources/prs/vllm/PR-38251.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[Compile] Fix nvfp4 compile warning](../sources/prs/vllm/PR-38573.md), [[Bugfix] Fix NVFP4+MTP crash: force unquantized mtp.fc for Qwen3.5](../sources/prs/vllm/PR-38832.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[MoE] Move GPT OSS Triton kernel experts into fused_moe/experts/](../sources/prs/vllm/PR-39007.md), [[Refactor] Move NVFP4 GEMM management into NvFp4LinearKernel](../sources/prs/vllm/PR-39129.md), [[Feature] Batch invariant nvfp4 linear support](../sources/prs/vllm/PR-39322.md), [[Kernel] Support TRTLLM GEN NVFP4 MoE for non-512-aligned hidden dims via weight padding](../sources/prs/vllm/PR-39510.md), [[Bugfix] Reject non-nvfp4 dtypes when using the flashinfer_nvlink_one_sided all2all backend](../sources/prs/vllm/PR-39717.md), [[Bug] Fix batch invariance nvfp4 support](../sources/prs/vllm/PR-39820.md), [[Bugfix] Temporarily disable B200 fp4 MoE layer tests](../sources/prs/vllm/PR-40057.md), [Add nvfp4 kv cache support](../sources/prs/vllm/PR-40177.md), [[Bugfix] Guard mxfp4_experts_quant bindings on ENABLE_NVFP4_SM100](../sources/prs/vllm/PR-40191.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[DSV4] Add BF16 and MXFP8 A2A support for flashinfer a2a one sided](../sources/prs/vllm/PR-40960.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [[ROCm][Quantization][3/N] Refactor quark_moe w4a4 w/ oracle](../sources/prs/vllm/PR-41436.md), [[Quantization] Rework quantization_config to use QuantKey and allow for activation override](../sources/prs/vllm/PR-41566.md), [[MXFP4] Support for linear layers + compressed-tensors integration](../sources/prs/vllm/PR-41664.md), [Add NVFP4 all-gather GEMM fusion for AsyncTP](../sources/prs/vllm/PR-41882.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[Kernel] Pack topk id/weights triton kernel](../sources/prs/vllm/PR-42527.md), [[Bugfix] fix swiglu limit issue for humming backend + deepseek v4](../sources/prs/vllm/PR-42541.md), [[Perf] Padded nvfp4 quant kernel to remove additional copy, 2.4%~5.7% e2e performance improvement](../sources/prs/vllm/PR-42774.md), [[Perf] Re-enable flashinfer autotune by default and cleanup](../sources/prs/vllm/PR-42857.md), [NVFP4 and Block-Scaled Narrow Precision](../wiki/hardware/nvfp4.md), [NVFP4 GEMM — GPU Mode Problem 2 Contract](../wiki/kernels/nvfp4-gemm.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md), [Fine-Grained FP8/FP4 Quantization](../wiki/techniques/fine-grained-quantization.md) | +| `fp6` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md) | +| `fp8` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [DeepGEMM — Pinned Upstream Project Summary](../sources/blogs/deepgemm.md), [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 Track A: FP8 Block-Scale MoE](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [DeepSeek-V3 Technical Report: FP8 Training](../sources/docs/deepseek-v3-fp8.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Use swizzling instead of padding](../sources/prs/DeepGEMM/PR-86.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [[None][fix] impl fused triton kernel for e8m0 resmooth to reduce memory footprint](../sources/prs/TensorRT-LLM/PR-10327.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[None][feat] Add support for expert_number<=2048 and K<=32](../sources/prs/TensorRT-LLM/PR-11510.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[TRTLLM-10421][perf] Add fused cat+fp8_quantize CUDA kernel for DSA indexer](../sources/prs/TensorRT-LLM/PR-11899.md), [[None][feat] GLM 5 support and DSA MTP fixes](../sources/prs/TensorRT-LLM/PR-11990.md), [[https://nvbugs/5879577][fix] Fix KeyError in DeepSeekV3Lite FP8 MTP weight loading](../sources/prs/TensorRT-LLM/PR-12530.md), [[#12784][feat] AutoDeploy: Optimize DeepSeek-R1 model performance](../sources/prs/TensorRT-LLM/PR-12946.md), [[TRTLLM-34871][feat] Add cute dsl FP8 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13219.md), [[TRTLLM-11127][feat] add W4A8_MXFP4_FP8 MoE unit test support](../sources/prs/TensorRT-LLM/PR-13401.md), [[None][feat] Fuse FP8 1x128 quantize + UE8M0 scale pack on SM100](../sources/prs/TensorRT-LLM/PR-13628.md), [[None][fix] Plumb swiglu_limit through DeepGEMM and TRTLLMGen FP8 fused MoE](../sources/prs/TensorRT-LLM/PR-13767.md), [[TRTLLM-12503][feat] Parallel VAE independent scaling and fix arg passing](../sources/prs/TensorRT-LLM/PR-13873.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] Keep DSv4 o_a_proj as FP8, and port vLLM's fused_inv_rope_fp8_quant](../sources/prs/TensorRT-LLM/PR-13938.md), [[TRTLLM-12462][fix] Fix FP8 block scaling GEMM autotuner cache growth](../sources/prs/TensorRT-LLM/PR-14165.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [[None][feat] TRT-LLM Gen MoE optimize DeepSeek Fp8 activation kernel](../sources/prs/TensorRT-LLM/PR-9175.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [Improve sm90 mixed dtype kernel](../sources/prs/cutlass/PR-1883.md), [Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2037.md), [Improvements for: Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2095.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [hopper-blockwise-generalization-optimization](../sources/prs/cutlass/PR-2270.md), [support fp16 accmulator for sm89 fp8 mma](../sources/prs/cutlass/PR-2378.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [[Cutlass gemm] Fix SM100 FP8 nosmem epilogue-fusion shape_div 'Divisibility Condition' for non-multiple-of-64 N tiles](../sources/prs/cutlass/PR-2946.md), [[Bug Fix]Set NumSplitsM to 1 when TileShapeM < 128 in sm90 fp8 blockwise scaling CollectiveMma](../sources/prs/cutlass/PR-2965.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [perf: accelerate blackwell grouped gemm](../sources/prs/flashinfer/PR-1086.md), [bugfix: fix fp8 attention kernels aot compilation issue](../sources/prs/flashinfer/PR-1087.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [Add DeepGEMM kernels](../sources/prs/flashinfer/PR-1209.md), [Fix test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-1211.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [Patch fp8 cubin availability](../sources/prs/flashinfer/PR-1240.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [Reduce the JIT compilation time of gen_gemm_sm100_module](../sources/prs/flashinfer/PR-1251.md), [init add gemm fp8 using cudnn backend](../sources/prs/flashinfer/PR-1264.md), [feat: add masked deepgemm support and benchmarking](../sources/prs/flashinfer/PR-1266.md), [Unify groupwise fp8 GEMM test](../sources/prs/flashinfer/PR-1281.md), [Bug fix: guard fp8 e8m0 and e2m1 compile ](../sources/prs/flashinfer/PR-1287.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [Make Fp8 MoE routing_bias optional](../sources/prs/flashinfer/PR-1319.md), [Add blockwise-scaled FP8 GEMM via TRTLLM-Gen.](../sources/prs/flashinfer/PR-1320.md), [feat: Fused rope fp8 quantize kernel for MLA](../sources/prs/flashinfer/PR-1339.md), [[fix] remove (view) transpose to keep consistent with majorness MN requirement.](../sources/prs/flashinfer/PR-1358.md), [bugfix: Add guard for fp4/fp8 related include headers](../sources/prs/flashinfer/PR-1376.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Adding FP8 benchmark on attention and matmul testing](../sources/prs/flashinfer/PR-1390.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [feature: add cutlass as bmm_fp8 backend.](../sources/prs/flashinfer/PR-1397.md), [bugfix: fix perf issue by using fp8 graph that can use cublaslt](../sources/prs/flashinfer/PR-1435.md), [Add alignment in MxFP8Quantization](../sources/prs/flashinfer/PR-1445.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [perf: add 1x4x1 cluster shape for fp8 bmm M<16 cases](../sources/prs/flashinfer/PR-1473.md), [refactor: unify autotuner for bmm_fp8](../sources/prs/flashinfer/PR-1479.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [Perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8](../sources/prs/flashinfer/PR-1491.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [bugfix: Fix compile error for undefined swizzle enum.](../sources/prs/flashinfer/PR-1530.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [bugfix: fix unittest test_fp8_quantize](../sources/prs/flashinfer/PR-1599.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [feat: cutlass fp8 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1610.md), [test: pytest.mark.xfail on deepgemm](../sources/prs/flashinfer/PR-1636.md), [Add benchmark for MLARopeQuantize](../sources/prs/flashinfer/PR-1656.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [test: better fp8 quantization init for fused_moe test](../sources/prs/flashinfer/PR-1674.md), [Update deepgemm backend for 103a](../sources/prs/flashinfer/PR-1694.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [TVM: support TVM binding for GroupedGemm](../sources/prs/flashinfer/PR-1725.md), [tests: xfail moe quantization classes mxfp8_bf16 UTs on sm103 ](../sources/prs/flashinfer/PR-1754.md), [tests: skip non SM100/103 for grouped deepgemm](../sources/prs/flashinfer/PR-1767.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [raise error for group_gemm_fp8_nt_groupwise then num_groups > 1 on sm120/121](../sources/prs/flashinfer/PR-1862.md), [misc: fix some B200 GEMM bench](../sources/prs/flashinfer/PR-1883.md), [MLA RoPE + quantization fused kernel: shape generalization for MHA / GQA](../sources/prs/flashinfer/PR-1924.md), [Fix: Verify scales are not None for Cutlass FP8 FusedMoE](../sources/prs/flashinfer/PR-1961.md), [feat: enable deepgemm jit for fp8 block-scale on SM90](../sources/prs/flashinfer/PR-1969.md), [fix: correct PDL parameter handling in RopeQuantize kernel](../sources/prs/flashinfer/PR-1982.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [feat: suitable_auto_backends to prune auto backends, bmm_fp8 refactor, heuristic_func intake](../sources/prs/flashinfer/PR-2029.md), [Enable renormalize(naive) routing for fp8 per-tensor](../sources/prs/flashinfer/PR-2030.md), [Added an initial implementation of Q and KV Cache in fp8 and to use t…](../sources/prs/flashinfer/PR-2035.md), [feat: Add flashinfer.rope.rope_quantize_fp8_append_paged_kv_cache (fused RoPE + Q + KV cache, supports MLA/GQA/MHA) ](../sources/prs/flashinfer/PR-2037.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [test: Skip test_fp8_quantize.py on Hopper](../sources/prs/flashinfer/PR-2052.md), [Fix moe fp8 failure for sm121](../sources/prs/flashinfer/PR-2061.md), [perf: TRT-LLM MoE Block-FP8 activation optimization](../sources/prs/flashinfer/PR-2063.md), [enable xqa fp8 output](../sources/prs/flashinfer/PR-2081.md), [refactor: update dpsk fused_moe test [1]](../sources/prs/flashinfer/PR-2088.md), [refactor: update dpsk fused_moe test [2]](../sources/prs/flashinfer/PR-2097.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [fix: Fix bench_mm_fp8.py](../sources/prs/flashinfer/PR-2129.md), [make DeepGEMM swapAB available for linear gemm SM90](../sources/prs/flashinfer/PR-2131.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [Fp8 attention are now part of cuDNN 9.17.1](../sources/prs/flashinfer/PR-2241.md), [feat: RMSNorm/Fused RMSNorm + FP8 Quantization kernels](../sources/prs/flashinfer/PR-2243.md), [fix: support int64 IdType for RoPE part argument in `rope_quantize_fp8_append_paged_kv_cache`](../sources/prs/flashinfer/PR-2255.md), [feat: Add support for bmm mxfp8](../sources/prs/flashinfer/PR-2256.md), [Fix CUTLASS FP8 gemm correctness issue on SM120/SM121 for shapes where N is not divisible by ScaleGranularityN.](../sources/prs/flashinfer/PR-2261.md), [test: use .float() in in F.cosine_similarity() in bmm_fp8 test](../sources/prs/flashinfer/PR-2266.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32](../sources/prs/flashinfer/PR-2327.md), [fix: guard batchWarpReduceSum with ENABLE_FP8 to fix compilation without FP8](../sources/prs/flashinfer/PR-2328.md), [fix: Fix NaN output in mxfp8_quantize for very small input values](../sources/prs/flashinfer/PR-2441.md), [Add cute-dsl backends to mxfp[8,4]_quantization for future refactor](../sources/prs/flashinfer/PR-2443.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [feat: Add MXFP8 GEMM mm_mxfp8 (cutlass)](../sources/prs/flashinfer/PR-2464.md), [Feat: Trtllm-gen MxFP8 MoE integration](../sources/prs/flashinfer/PR-2505.md), [fix: include fp8_blockscale_gemm_90 in AOT jit-cache](../sources/prs/flashinfer/PR-2533.md), [fallback to fa2 (instead of fa3) for unsupported configuration (bf16 Q, Fp8 KV)](../sources/prs/flashinfer/PR-2536.md), [tests: bmm_fp8 for SM110](../sources/prs/flashinfer/PR-2538.md), [Add gen_gemm_sm100_module_cutlass_mxfp8 to jit-cache](../sources/prs/flashinfer/PR-2549.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [benchmark: Add MXFP4/MXFP8 quantization mode support to FP4 MoE benchmark](../sources/prs/flashinfer/PR-2635.md), [[fp8_blockwise]Fix int32 overflow in TRTLLM fused MoE activation kernel](../sources/prs/flashinfer/PR-2642.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [feat: support mxfp4 & mxfp8 entrypoint for blackwell cutedsl dense gemm](../sources/prs/flashinfer/PR-2660.md), [benchmarks: Add FP8 input / BF16 output in ragged prefill benchmark](../sources/prs/flashinfer/PR-2666.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [feat: Add support for TRTLLM MXFP8 non-gated MoE with ReLU2](../sources/prs/flashinfer/PR-2707.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [Support in-place update for `trtllm_fp8_block_scale_moe`](../sources/prs/flashinfer/PR-2739.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [[Spark unit test debugging] Fix for tests/gemm/test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-2751.md), [feat: FP8 output support for CUTLASS MLA paged attention](../sources/prs/flashinfer/PR-2779.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [Fix silent bug with FP8 per tensor non-gated MoE](../sources/prs/flashinfer/PR-2882.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [feat: add MXFP8 GEMM support for SM120](../sources/prs/flashinfer/PR-2902.md), [perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels](../sources/prs/flashinfer/PR-2904.md), [[NVIDIA] fix(jit): enable GDC for CUTLASS fused MoE PDL — prevent random crashes on SM12x](../sources/prs/flashinfer/PR-2913.md), [feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners](../sources/prs/flashinfer/PR-2914.md), [test: xfail cuDNN FP8 prefill on Blackwell with CUDA <= 12.9](../sources/prs/flashinfer/PR-2963.md), [test: skip unsupported mm_mxfp8 configurations on SM12x](../sources/prs/flashinfer/PR-2974.md), [ Fix MXFP4/MXFP8 failures in SM120 FAST_BUILD and expand all_tiles[] ](../sources/prs/flashinfer/PR-2994.md), [Support Allreduce + Norm + Per-token Group Fp8 Quant Fusion](../sources/prs/flashinfer/PR-3059.md), [feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16](../sources/prs/flashinfer/PR-3129.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [test: enable bmm_mxfp8 cutlass backend coverage on SM12x](../sources/prs/flashinfer/PR-3183.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [Naive Support for Hopper FP8 Prefill Kernel with Per-Head Quantization](../sources/prs/flashinfer/PR-869.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [Update CUTLASS. Refine KernelSchedule for fp8 (grouped) gemm.](../sources/prs/sglang/PR-10491.md), [support qwen3-next-fp8 deepep](../sources/prs/sglang/PR-10622.md), [Fix DSR1 accuracy for flashinfer_trtllm MoE with FP8 quantization](../sources/prs/sglang/PR-11081.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [Change bf16 to fp8 for some gemms in attention for DeepSeek ckpt v2](../sources/prs/sglang/PR-11805.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [[sgl-kernel][4/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12080.md), [[hotfix] missing `w13_weight_fp8` and `w2_weight_fp8` in UE8M0 requantization](../sources/prs/sglang/PR-12259.md), [fix: llama 4 + trtllm gen + fp8 kv cache incompatibility](../sources/prs/sglang/PR-12347.md), [Enable Flashinfer TRTLLM-GEN-MoE FP8 blockwise kernel for Qwen3-Next on Blackwell](../sources/prs/sglang/PR-12543.md), [[sgl-kernel] support custom fp8 flashmla kernel](../sources/prs/sglang/PR-13087.md), [Aiter fp8 kv cache](../sources/prs/sglang/PR-13147.md), [[NVIDIA] Fix broken fp8 MoE of deepseek v3](../sources/prs/sglang/PR-13264.md), [[NVIDIA] Fix use case of SGLANG_ENABLE_FLASHINFER_GEMM](../sources/prs/sglang/PR-13274.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [Feat: GLM-4.6 supports shared experts fusion](../sources/prs/sglang/PR-13873.md), [Fix update weight error for blackwell DeepGEMM](../sources/prs/sglang/PR-13910.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Support checking fp8 params in weight_checker](../sources/prs/sglang/PR-14147.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[CPU] Implement MXFP4 Gemm kernels for intel AMX to support GPT OSS series.](../sources/prs/sglang/PR-14385.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [Add Mistral Large 3 Eagle Support](../sources/prs/sglang/PR-14466.md), [[sgl-kernel][Feat][B200][2/N] Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-14640.md), [[sgl-kernel] Update flashmla to include fp8 sparse_mla optimizations](../sources/prs/sglang/PR-15242.md), [Flashinfer MOE FP8 support for Mistral Large 3.](../sources/prs/sglang/PR-15422.md), [[sgl-kernel][6/7]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-15471.md), [[Perf] Add Flashinfer DeepGEMM SM90 for SwapAB Optimization](../sources/prs/sglang/PR-15514.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [Fix FP8 MoE NaN with DeepGEMM on Blackwell](../sources/prs/sglang/PR-16622.md), [[GLM 4.7] Add RTX 6000 Pro aka sm120](../sources/prs/sglang/PR-17235.md), [Disable mla persistent kernel when not using fp8 kv_cache](../sources/prs/sglang/PR-17327.md), [Add mxfp8 support for online quantization, Triton dense linear, and CUTLASS MoE](../sources/prs/sglang/PR-17449.md), [[ROCm] Optimize Deepseek R1 on MI300X](../sources/prs/sglang/PR-18242.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [Fp8 prefill attn kernel integration](../sources/prs/sglang/PR-18528.md), [[AMD] DSR1/V3 use fp8 bmm in MLA for MI300X](../sources/prs/sglang/PR-18624.md), [[RL] Support per-layer mixed FP8/BF16 serving for FP8 checkpoints](../sources/prs/sglang/PR-18742.md), [Fix NSA FP8 KV cache path for both-trtllm MHA one-shot](../sources/prs/sglang/PR-18931.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [Various SM120 improvements](../sources/prs/sglang/PR-19721.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [Enable modelopt quantized FLUX deployment](../sources/prs/sglang/PR-20082.md), [[AMD] Fp8 prefill integration with radix cache path for dpsk models](../sources/prs/sglang/PR-20187.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[NVIDIA] Enable fp8 flashinfer_trtllm_routed MoE for MiniMax-M2.5](../sources/prs/sglang/PR-20394.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [CUTLASS FP8 Blockwise GEMM improvement of SM120](../sources/prs/sglang/PR-20887.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [ci: run Stage A CUDA tests as stage-a-test-small-1-gpu on 5090](../sources/prs/sglang/PR-20988.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[RL] Support mxfp8 DeepSeek V3](../sources/prs/sglang/PR-21280.md), [[Kernel] Support FlashInfer TRTLLM-Gen fused MoE for non-gated FP4 & FP8 (Nemotron)](../sources/prs/sglang/PR-21321.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [[FlashInver v0.6.7] Integrate flashinfer_trtllm mxfp8 gemm](../sources/prs/sglang/PR-21576.md), [[AMD] Add GLM-5-FP8 nightly performance benchmarks for MI30x and MI35x](../sources/prs/sglang/PR-21710.md), [[Misc] [MXFP8] Drop sm100 mxfp8 warning](../sources/prs/sglang/PR-21881.md), [fix pcg torch dynamo recompile in mxfp8 Triton path](../sources/prs/sglang/PR-21888.md), [Tiny fix trtllm_fp8_per_tensor_scale_moe_wrapper router_logits dtype](../sources/prs/sglang/PR-22006.md), [[AMD][HIP] NSA: bf16 passthrough from RMSNorm to eliminate FP8 dequantization](../sources/prs/sglang/PR-22258.md), [[AMD] Fix GLM-5 fp8 KV quant path dispatch on MI300](../sources/prs/sglang/PR-22314.md), [[Reland] DeepSeek-R1-0528-w4a8: DeepEP Low Latency Dispatch Adopts FP8 Communication](../sources/prs/sglang/PR-22316.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [[AMD] Add GLM-5.1-FP8 nightly accuracy and performance benchmarks for MI30x and MI35x](../sources/prs/sglang/PR-22336.md), [[Diffusion] modelopt diffusion fp8 support for flux1/flux2 and wan2.2](../sources/prs/sglang/PR-22365.md), [[DSA] Hopper FP8 FlashMLA KV padding](../sources/prs/sglang/PR-22372.md), [[RL] Fix weight update for mxfp8 flashinfer_cutlass gemm backend](../sources/prs/sglang/PR-22484.md), [[Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22574.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [[MoE] Unify DeepEPMoE+MoriEPMoE through AITER MoeRunner pre/post-permute](../sources/prs/sglang/PR-23760.md), [Refactor device timer, clean up metrics collector, and add fwd occupancy metric](../sources/prs/sglang/PR-24197.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [[Codex] Opt Mistral Large performace ](../sources/prs/sglang/PR-24611.md), [[Gemma4] Optimize Gemm4 with fused Q/K/V RMSNorm + per-expert FP8 ckpt loader](../sources/prs/sglang/PR-24696.md), [Add FlashInfer SM90 cutlass MXFP4 MoE backend (W4A16) for GPT-OSS + DeepSeek-V4](../sources/prs/sglang/PR-24816.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [[Gemma4]: Fix FP8 Triton scale layout](../sources/prs/sglang/PR-25286.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[fp8] SM90 swap-AB scaled_mm dispatch (~1.16x kernel geomean, +5.8-18.5% end-to-end)](../sources/prs/sglang/PR-25532.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [support w8a8 fp8 kernel with CUTLASS](../sources/prs/sglang/PR-3047.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [Apply sgl w8a8 fp8 kernel](../sources/prs/sglang/PR-3148.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [support blockwise fp8 matmul kernel](../sources/prs/sglang/PR-3267.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [add control for cutlass fp8 blockwise gemm](../sources/prs/sglang/PR-3727.md), [[tools] add fp8 max/min constant in utils](../sources/prs/sglang/PR-3959.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [linear support deepgemm](../sources/prs/sglang/PR-4199.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [Clean up fp8 support](../sources/prs/sglang/PR-4230.md), [fix per_token_group_quant_fp8 illegal memory when num_groups % 16 != 0](../sources/prs/sglang/PR-4231.md), [Support Blackwell Block Scale FP8 Gemm](../sources/prs/sglang/PR-4278.md), [[FIX] fix incorrect output when enable both deepgemm and torch compile](../sources/prs/sglang/PR-4359.md), [[ROCm] fix dtype](../sources/prs/sglang/PR-4510.md), [Create col-major and tma-aligned x_scale for deep_gemm.gemm_fp8_fp8_bf16_nt](../sources/prs/sglang/PR-4515.md), [Support fp8 gemm for blackwell](../sources/prs/sglang/PR-4558.md), [[quantization] fix channelwise conversion with scalar weight scale](../sources/prs/sglang/PR-4596.md), [Set deepgemm to the default value in the hopper architecture.](../sources/prs/sglang/PR-4613.md), [Add DeepSeek V3/R1 shared experts fusion](../sources/prs/sglang/PR-4918.md), [feat: add DeepGEMM build warning](../sources/prs/sglang/PR-5176.md), [[Fix] Turn off DeepGEMM by default](../sources/prs/sglang/PR-5263.md), [[1/2] Add FP8 Blockscale MoE CUTLASS kernel for Blackwell](../sources/prs/sglang/PR-5281.md), [fix: use deepgemm only on hopper](../sources/prs/sglang/PR-5310.md), [[perf] experimental enhance fp8 per-tensor quant](../sources/prs/sglang/PR-5370.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [[feature] enable pre compile jit deep_gemm](../sources/prs/sglang/PR-5580.md), [ DeepEP normal support deepgemm-contiguous](../sources/prs/sglang/PR-5626.md), [[perf] dsv3 bmm fallback to bf16](../sources/prs/sglang/PR-5662.md), [[2/2] Add python wrapper for CUTLASS FP8 Blockscale MoE Kernel. ](../sources/prs/sglang/PR-5694.md), [cutlass 3.9 supported to improve fp8_blockwise_gemm](../sources/prs/sglang/PR-5820.md), [chore: upgrade cutlass 3.9.2](../sources/prs/sglang/PR-6004.md), [Upgrade CUTLASS 4.0](../sources/prs/sglang/PR-6336.md), [Add fp8 fused_experts kernel for CPU in sgl-kernel and add UT](../sources/prs/sglang/PR-6404.md), [Fix bug of deepseek-v3 under DP+EP mode with large batchsize/seqlen](../sources/prs/sglang/PR-6449.md), [[Feature] Support Flashinfer fp8 blockwise GEMM kernel on Blackwell](../sources/prs/sglang/PR-6479.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [[CPU] add optimizations for INT8 and FP8 DeepSeek](../sources/prs/sglang/PR-6769.md), [feat: integrate deepgemm into EPMoE](../sources/prs/sglang/PR-6821.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [Use deepgemm instead of triton for fused_qkv_a_proj_with_mqa](../sources/prs/sglang/PR-6890.md), [Add a CUDA kernel for fusing mapping and weighted sum for MoE.](../sources/prs/sglang/PR-6916.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [Fuse routed scaling factor in deepseek](../sources/prs/sglang/PR-6970.md), [Update default settings for blackwell](../sources/prs/sglang/PR-7023.md), [Fix positional argument](../sources/prs/sglang/PR-7093.md), [fix amd EP MoE FP8 issue](../sources/prs/sglang/PR-7125.md), [Enable ModelOpt Llama4 fp8 checkpoint deployment in SGLang](../sources/prs/sglang/PR-7129.md), [[amd] Opt dsv3 moe](../sources/prs/sglang/PR-7160.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Tiny let DeepGEMM scale checks cover more cases](../sources/prs/sglang/PR-7182.md), [[AMD] Fail gracefully when AITER is unavailable gfx90a GPUs](../sources/prs/sglang/PR-7187.md), [[fix] fix DeepGEMM blackwell input quant & ut & fix style and log](../sources/prs/sglang/PR-7247.md), [Add CUTLASS FP8 Blockscale MoE kernel for Hopper architecture](../sources/prs/sglang/PR-7278.md), [Fix torch compile run](../sources/prs/sglang/PR-7391.md), [[AMD][Quantization] Add `int4fp8_moe` online quantization on ROCm](../sources/prs/sglang/PR-7392.md), [feat: support DeepSeek-R1-W4AFP8 model with ep-moe mode](../sources/prs/sglang/PR-7762.md), [Qwen FP8/NVFP4 ModelOPT Quantization support](../sources/prs/sglang/PR-7912.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [[sgl-kernel] Opt per_token_quant_fp8 with warp reduce](../sources/prs/sglang/PR-8130.md), [[1/N]Support DeepSeek-R1 w4a8 normal deepep](../sources/prs/sglang/PR-8247.md), [[2/N]Support DeepSeek-R1 w4a8 low latency deepep](../sources/prs/sglang/PR-8464.md), [TRTLLM-MLA FP8 path](../sources/prs/sglang/PR-8638.md), [feat: support cutlass_moe_fp8 kernel for fusedmoe in sm90](../sources/prs/sglang/PR-8678.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/sglang/PR-8818.md), [optimize: reduce shulffle and quantization overhead in cutlass_moe sm90](../sources/prs/sglang/PR-8962.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [[sgl-kernel] feat: Support sm120 cutlass fp8 gemm kernel](../sources/prs/sglang/PR-9403.md), [fix: blackwell dsv3 fp8 issue temporary solution](../sources/prs/sglang/PR-9530.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [Make sm100 fp8 kernels available on sm103](../sources/prs/sglang/PR-9789.md), [CUTLASS fp8 blockwise gemm support of sm120](../sources/prs/sglang/PR-9969.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Kernel]: Cutlass 2:4 Sparsity + FP8/Int8 Quant Support](../sources/prs/vllm/PR-10995.md), [[Kernel] Update `cutlass_scaled_mm` to support 2d group (blockwise) scaling](../sources/prs/vllm/PR-11868.md), [Add: Support for Sparse24Bitmask Compressed Models](../sources/prs/vllm/PR-12097.md), [Expert Parallelism (EP) Support for DeepSeek Models](../sources/prs/vllm/PR-12583.md), [[Kernel][Quantization] Integrate block-quantized CUTLASS kernels for DeepSeekV3](../sources/prs/vllm/PR-12587.md), [[Attention] Deepseek v3 MLA support with FP8 compute](../sources/prs/vllm/PR-12601.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [[AMD][ROCm] Enable DeepSeek model on ROCm](../sources/prs/vllm/PR-12662.md), [[Bugfix] Better FP8 supported defaults](../sources/prs/vllm/PR-12796.md), [[Kernel]Add streamK for block-quantized CUTLASS kernels](../sources/prs/vllm/PR-12978.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [[Bugfix][Quantization] Fix FP8 + EP](../sources/prs/vllm/PR-13784.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [[core] moe fp8 block quant tuning support](../sources/prs/vllm/PR-14068.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [Add cutlass support for blackwell fp8 blockwise gemm](../sources/prs/vllm/PR-14383.md), [[BugFix] Illegal Memory Access in the blockwise cutlass fp8 GEMMs](../sources/prs/vllm/PR-14396.md), [[ROCm][Kernel] MoE weights padding](../sources/prs/vllm/PR-14454.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[Attention] Flash Attention 3 - fp8](../sources/prs/vllm/PR-14570.md), [[Quantization][FP8] Adding support for fp8 gemm layer input in fp8](../sources/prs/vllm/PR-14578.md), [[Attention] MLA get rid of materialization](../sources/prs/vllm/PR-14770.md), [[FEAT][ROCm] Integrate Fused MoE Kernels from AITER](../sources/prs/vllm/PR-14967.md), [[FEAT] [ROCm]: Add AITER Block-Scaled GEMM Feature](../sources/prs/vllm/PR-14968.md), [[Quantization] Fp8 Channelwise Dynamic Per Token GroupedGEMM](../sources/prs/vllm/PR-15587.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Kernel] Support W8A8 channel-wise weights and per-token activations in triton fused_moe_kernel](../sources/prs/vllm/PR-16366.md), [Enable PTPC FP8 for CompressedTensorsW8A8Fp8MoEMethod (triton fused_moe)](../sources/prs/vllm/PR-16537.md), [[ROCm] Add aiter tkw1 kernel for Llama4 fp8](../sources/prs/vllm/PR-16727.md), [[Kernel] some optimizations for dense marlin and moe marlin](../sources/prs/vllm/PR-16850.md), [[Kernel] Add expert_map support to Cutlass FP8 MOE](../sources/prs/vllm/PR-16861.md), [[FEAT] [ROCm]: Add AITER CK 2 Stages MoE support](../sources/prs/vllm/PR-17110.md), [[ROCm][FP8][Kernel] FP8 quantization fused into Custom Paged Attention](../sources/prs/vllm/PR-17139.md), [[NVIDIA] Support Cutlass w8a8 FP8 for Blackwell Geforce GPUs (sm120)](../sources/prs/vllm/PR-17280.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [use ceil_div in cutlass block scaling shape check](../sources/prs/vllm/PR-17918.md), [[Feature] Expert Parallelism Load Balancer (EPLB)](../sources/prs/vllm/PR-18343.md), [[V1] Support `LLM.apply_model`](../sources/prs/vllm/PR-18465.md), [Sm100 blockwise fp8 swap ab](../sources/prs/vllm/PR-18564.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-18778.md), [[Kernel] Enable fp8 support for pplx and BatchedTritonExperts.](../sources/prs/vllm/PR-18864.md), [[Kernel] Support deep_gemm for linear methods](../sources/prs/vllm/PR-19085.md), [[Kernels] Add activation chunking logic to FusedMoEModularKernel](../sources/prs/vllm/PR-19168.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [[Feature] Integrate new deepgemm](../sources/prs/vllm/PR-19820.md), [ [Feature] Integrate SM100 DeepGEMM support](../sources/prs/vllm/PR-20087.md), [[Bugfix] Fix topk_ids indices_type for CUTLASS w8a8 FP8 MoE](../sources/prs/vllm/PR-20166.md), [[V1] [ROCm] Enable EP with AITER Fused MoE](../sources/prs/vllm/PR-20270.md), [[Kernel] SM90 CUTLASS FP8 GEMM: add support for swap AB + kernel tuning](../sources/prs/vllm/PR-20396.md), [[feat]: add SM100 support for cutlass FP8 groupGEMM](../sources/prs/vllm/PR-20447.md), [Support Llama 4 for fused_marlin_moe](../sources/prs/vllm/PR-20457.md), [[Perf] Reuse workspace for FP8+FP4 Marlin MoE](../sources/prs/vllm/PR-20500.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [[Perf] Use Triton instead of Torch for DeepGEMM Per Token Group Quant](../sources/prs/vllm/PR-20841.md), [[Perf] Add swap_ab to SM90 FP8 non-block CUTLASS moe grouped gemm](../sources/prs/vllm/PR-20911.md), [[Perf] Cuda Kernel for Per Token Group Quant](../sources/prs/vllm/PR-21083.md), [[perf] Add fused MLA QKV + strided layernorm](../sources/prs/vllm/PR-21116.md), [[Feature][OCP MX] Support mxfp6 and mixed mxfp6-mxfp4](../sources/prs/vllm/PR-21166.md), [[Bug] DeepGemm: Fix TypeError: per_block_cast_to_fp8() missing 1 required positional argument: 'use_ue8m0' for SM100](../sources/prs/vllm/PR-21187.md), [[NVIDIA] Explicitly disable shuffled weights for flashinfer blockscale moe fp8 kernels](../sources/prs/vllm/PR-21411.md), [[Bugfix][CUDA] fixes CUDA FP8 kv cache dtype supported](../sources/prs/vllm/PR-21420.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [[Kernel] Add support for block FP8 on SM120 (NVIDIA 5090 and RTX PRO 6000)](../sources/prs/vllm/PR-22131.md), [Fp8 paged attention update](../sources/prs/vllm/PR-22222.md), [[Bug] Fix B200 DeepGEMM E8M0 Accuracy Issue](../sources/prs/vllm/PR-22399.md), [[Quantization] Expand compressed-tensors MoE matching logic to support NFP4 + FP8 MoEs](../sources/prs/vllm/PR-22674.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [fp8 kv cache support fix for torch.compile](../sources/prs/vllm/PR-22758.md), [[Kernel] Added flashinfer fp8 per-tensor gemms](../sources/prs/vllm/PR-22895.md), [[Bugfix] fix qwen3 moe fp8 accuracy issue](../sources/prs/vllm/PR-23031.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [Add routed_scaling_factor to MoE grouped topk](../sources/prs/vllm/PR-23123.md), [[XPU][Feature] fp8 online quantization support for XPU](../sources/prs/vllm/PR-23148.md), [[kernel] Support W4A8 on Hopper](../sources/prs/vllm/PR-23198.md), [[ROCm][Aiter] Add triton fp8 bmm kernel for mla](../sources/prs/vllm/PR-23264.md), [[Perf] Small optimizations for silu_mul_fp8_quant_deep_gemm](../sources/prs/vllm/PR-23265.md), [[Kernels] Overlap shared experts with send/recv](../sources/prs/vllm/PR-23273.md), [[Perf] Use upstream CUTLASS for SM90 Block FP8 kernel](../sources/prs/vllm/PR-23280.md), [[Bug] Fix R1 Accuracy 0 Bug](../sources/prs/vllm/PR-23294.md), [DP/EP Support for gpt-oss with deepep-ht comm kernel on SM100](../sources/prs/vllm/PR-23608.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[Feature] Add Hopper DeepGEMM E8M0 for DeepSeekV3.1 scale_fmt](../sources/prs/vllm/PR-23666.md), [[Kernel][B200] mxfp4 fused cutlass moe](../sources/prs/vllm/PR-23696.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Performance] Move apply_w8a8_block_fp8_linear to an op class](../sources/prs/vllm/PR-24666.md), [[NVIDIA] Blackwell Family](../sources/prs/vllm/PR-24673.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [[Flashinfer][gpt-oss] Support FP8-qkv Flashinfer TRTLLM Sinks Attention](../sources/prs/vllm/PR-25674.md), [[Bugfix] Convert untraceable GroupShape to list for AMD impl](../sources/prs/vllm/PR-26535.md), [[Bugfix] Fix gpt-oss w4a8 DP/EP on B200](../sources/prs/vllm/PR-26729.md), [[Feature] Batch Invariant: Support DeepGEMM and Blackwell](../sources/prs/vllm/PR-27127.md), [[Kernels] Enable FlashInfer FP8 Blockscale on SM90 (for TEP DSR1)](../sources/prs/vllm/PR-27134.md), [[torch.compile] Enable silu_mul_fp8_quant fusion without custom ops enabled](../sources/prs/vllm/PR-27146.md), [Bugfix: Cutlass FP8 FusedMoE bad scaling factors](../sources/prs/vllm/PR-27255.md), [Feature: Support Relu2 in FusedMoE fp8 cutlass path](../sources/prs/vllm/PR-27261.md), [[Perf] SM100 - add swap AB optimization to CUTLASS FP8 GEMM](../sources/prs/vllm/PR-27284.md), [[Performance] Support FP8 flashinfer TRTLLM MOE on Qwen3 and Qwen-3next](../sources/prs/vllm/PR-27492.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Feature] Batch invariant torch.compile](../sources/prs/vllm/PR-27660.md), [[Performance] Fused blockwise quant RMS norm](../sources/prs/vllm/PR-27883.md), [[Performance][B200] Fix deepgemm prologue](../sources/prs/vllm/PR-27897.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Performance][B200] silu_mul_quant: pack scales in int32](../sources/prs/vllm/PR-28358.md), [[Performance] Reduce DeepGEMM N dim restriction from 128 to 64 multiplier ](../sources/prs/vllm/PR-28687.md), [[Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op)](../sources/prs/vllm/PR-29213.md), [chore: add RTX_PRO_6000 GLM4.6-FP8 kernel tuning](../sources/prs/vllm/PR-29240.md), [[Perf] Disable DeepGEMM MoE by default when TP=8 is used](../sources/prs/vllm/PR-29346.md), [[Kernel]Support W4A8 Grouped GEMM on Hopper](../sources/prs/vllm/PR-29691.md), [[MoE-FP8-modelopt] Add FlashInfer alignment padding for intermediate dimensions](../sources/prs/vllm/PR-29748.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[Perf] Improve fp8 quant in mla; replace ReduceSum with ReduceScatterSum](../sources/prs/vllm/PR-29795.md), [[Bugfix] Fix FP8 MoE LoRA](../sources/prs/vllm/PR-29890.md), [[Kernel][Quantization][MoE] add marlin kernel support for turing (sm75)](../sources/prs/vllm/PR-29901.md), [[ROCm] add fallback for aiter fp8 decode mla](../sources/prs/vllm/PR-30005.md), [[Quantization] Support Quark int4-fp8 w4a8 for MoE](../sources/prs/vllm/PR-30071.md), [Add llmcompressor fp8 kv-cache quant (per-tensor and per-attn_head)](../sources/prs/vllm/PR-30141.md), [[Bugfix] Fix DeepGEMM after #29546 ](../sources/prs/vllm/PR-30267.md), [[LoRA] Support Quantized Adapters](../sources/prs/vllm/PR-30286.md), [[Bugfix] Fix fp8 DeepGemm compilation issues](../sources/prs/vllm/PR-30336.md), [[ROCm][Quantization] GPT OSS Upstream MoE wmxfp4_afp8 with static scales](../sources/prs/vllm/PR-30357.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Perf] Eliminate padding and slicing op for GPT-OSS with Flashinfer MXFP4 MXFP8 MoE](../sources/prs/vllm/PR-30647.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[Feature]: Support NVIDIA ModelOpt HF FP8 variants FP8_PER_CHANNEL_PER_TOKEN and FP8_PB_WO in vLLM](../sources/prs/vllm/PR-30957.md), [[Bugfix][Hardware][AMD] Consolidate FP8 min/max values helper function](../sources/prs/vllm/PR-31106.md), [[Bugfix][Hardware][AMD] Fix exception types in AITER MLA FP8 check](../sources/prs/vllm/PR-31177.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][ROCm] Fix Static Quant Issue](../sources/prs/vllm/PR-31502.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [[Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper](../sources/prs/vllm/PR-32619.md), [[Bugfix] Fix FP8 MoE EP Weight Loading for ModelOpt Llama4](../sources/prs/vllm/PR-32886.md), [Support compress-tensors with nvfp4 or fp8 weights and modelopt with nvfp4 weights on Turing](../sources/prs/vllm/PR-33076.md), [Add support for Mistral Large 3 inference with Flashinfer MoE](../sources/prs/vllm/PR-33174.md), [[Bugfix] Fix quant RMS norm fusion for quantization with TMA-aligned scales](../sources/prs/vllm/PR-33255.md), [[Bugfix] Register fp8 cutlass_group_gemm as supported for only SM90+SM100](../sources/prs/vllm/PR-33285.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [[Kernel] Add enable_sm120_or_later for SM121 (DGX Spark) CUTLASS support](../sources/prs/vllm/PR-33517.md), [[Perf] Disable clean_logits in deepgemm fp8_mqa_logits kernel](../sources/prs/vllm/PR-33568.md), [enable skipping of SW attention layers when using FP8 KV cache](../sources/prs/vllm/PR-33695.md), [[Kernel] Integrate SM100 MXFP8 blockscaled grouped MM and quant kernels](../sources/prs/vllm/PR-34448.md), [[Bugfix] Handle num_expert_group=None in flashinfer block-scale FP8 MoE](../sources/prs/vllm/PR-34494.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [Integrate flashinfer mm_mxfp8 in ModelOpt MXFP8](../sources/prs/vllm/PR-35053.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[Attention][Perf] Optimize cp_gather_and_upconvert_fp8_kv_cache - DeepSeek-v3.2](../sources/prs/vllm/PR-35290.md), [[Quant][Feature] Support online MXFP8 quantization for MoE and dense models](../sources/prs/vllm/PR-35448.md), [[ROCm] Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5/Linear)](../sources/prs/vllm/PR-35850.md), [[Perf] Support FP8 KV cache for Flashinfer MLA Sparse](../sources/prs/vllm/PR-35891.md), [Add support for ModelOpt MXFP8 MoE models](../sources/prs/vllm/PR-35986.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [[Perf] Add TRTLLM FP8 MoE Modular Kernel](../sources/prs/vllm/PR-36307.md), [[XPU] Support block fp8 moe by fallback to TritonExpert on XPU](../sources/prs/vllm/PR-36458.md), [[Kernel] Fuse FP8 output quantization into merge_attn_states](../sources/prs/vllm/PR-36518.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[Bugfix] Fix KV scales inconsistency in fp8 MLA & FlashInfer kv_cache_dtype "auto" leading to gibberish](../sources/prs/vllm/PR-37054.md), [[XPU] support MLA model on Intel GPU](../sources/prs/vllm/PR-37143.md), [[Perf] Set Flashinfer sparse MLA as default backend for FP8 kv cache](../sources/prs/vllm/PR-37252.md), [[Bugfix] Disable monolithic TRTLLM MoE for Renormalize routing (#37591)](../sources/prs/vllm/PR-37605.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[Bug] Fix fp8 deepgemm batch invariant](../sources/prs/vllm/PR-37718.md), [[Kernel] Optimize SM120 CUTLASS blockwise FP8 GEMM](../sources/prs/vllm/PR-37970.md), [[Perf] FP8 FlashInfer Attn for ViT](../sources/prs/vllm/PR-38065.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [[Kernel] Add swapAB support for SM120 CUTLASS blockwise FP8 GEMM ](../sources/prs/vllm/PR-38325.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[QeRL] Fix online quantized reloading](../sources/prs/vllm/PR-38442.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[XPU] add xpu backend implementation of mxfp8 quant](../sources/prs/vllm/PR-38682.md), [[Quant] add CompressedTensorsW8A8Mxfp8 for linear and MoE layers](../sources/prs/vllm/PR-38815.md), [[Bugfix] Re-enable Renormalize routing for TRT-LLM MoE experts](../sources/prs/vllm/PR-38859.md), [[Bugfix] Fix broken explicit unquantized kv cache dtype support](../sources/prs/vllm/PR-38922.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[Bug] Fix routing bias dtype for trtllm per-block fp8 moe](../sources/prs/vllm/PR-38989.md), [[Perf] Change Trtllm fp8 MoE to use Shuffled Weights and BlockMajorK Layout](../sources/prs/vllm/PR-38993.md), [[Bug] Fix Trtllm Fp8 MoE Weight Shuffle Memory Fragamentation](../sources/prs/vllm/PR-39054.md), [perf(moe): add tuned fused_moe config for RTX PRO 6000 Blackwell Server Edition](../sources/prs/vllm/PR-39183.md), [[Refactor] Move MXFP8 GEMM management into MxFp8LinearKernel](../sources/prs/vllm/PR-39205.md), [[Perf] Fuse Zero Initializer for FP8 DeepGemm Block Quant Kernel](../sources/prs/vllm/PR-39547.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[Perf] Batch invariance with Cutlass fp8 support, 28.9% E2E latency improvement](../sources/prs/vllm/PR-40408.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[Kernel][Helion] Optimize Helion config parsing latency](../sources/prs/vllm/PR-40850.md), [[DSV4] Add BF16 and MXFP8 A2A support for flashinfer a2a one sided](../sources/prs/vllm/PR-40960.md), [Faster per-token fp8 group quant packed kernel for blackwell](../sources/prs/vllm/PR-41326.md), [[Quantization] Rework quantization_config to use QuantKey and allow for activation override](../sources/prs/vllm/PR-41566.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[feat] Add FP8 per-tensor Q scale support to Triton attention backend](../sources/prs/vllm/PR-42080.md), [[Perf] Use 2D-grid to eliminate divmod in W8W8 group quant](../sources/prs/vllm/PR-42153.md), [[Perf] Wire silu_and_mul_per_block_quant into TritonFP8MoE (MiniMax-M2) ](../sources/prs/vllm/PR-42497.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [[Perf] Add do_not_specialize in fused FP8 RoPE kernel](../sources/prs/vllm/PR-42849.md), [add cutedsl dsv4 indexer fp8 kernel](../sources/prs/vllm/PR-42899.md), [[Model Refactoring] Move deepseek_v4_ops to models/deepseek_v4 [3/N]](../sources/prs/vllm/PR-43073.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [FP8 Fine-Grained-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [FlashInfer Track A FP8 Block-Scale MoE](../wiki/kernels/fused-moe.md), [Grouped GEMM Contracts for MoE and NVFP4](../wiki/kernels/grouped-gemm.md), [DeepSeek Sparse Attention / Sparse MLA](../wiki/kernels/sparse-mla.md), [Fine-Grained FP8/FP4 Quantization](../wiki/techniques/fine-grained-quantization.md) | | `gdc` | [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [Programmatic Dependent Launch / Grid Dependency Control](../wiki/hardware/pdl-gdc.md) | -| `mbarrier` | [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [CUTLASS Cluster Launch Control (CLC) Documentation](../sources/docs/cutlass-clc-documentation.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Vectorize mbarrier initialization in warpspeed scan](../sources/prs/cccl/PR-8423.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [mbarrier (Memory Barrier Primitives)](../wiki/hardware/mbarrier.md), [tcgen05.mma — Blackwell MMA Instruction](../wiki/hardware/tcgen05-mma.md), [Tensor Memory Accelerator (TMA)](../wiki/hardware/tma.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Pipeline Stalls](../wiki/patterns/pipeline-stalls.md), [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md) | -| `nvfp4` | [Twelve Attempts at NVFP4 Batched GEMV](../sources/blogs/amandeep-nvfp4-attempts.md), [Anatomy of a Reward Hack](../sources/blogs/gpu-mode-reward-hack.md), [NVFP4 Format Details](../sources/blogs/nvfp4-format-details.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Triton 3.6.0 Release Notes — Blackwell (SM100) Lowering](../sources/docs/triton-3.6-blackwell.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.](../sources/prs/TensorRT-LLM/PR-10339.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[None][feat] Optimize super-v3 nvfp4 for better perf](../sources/prs/TensorRT-LLM/PR-11273.md), [[None][feat] Optimize by fuse nvfp4_quant to layernorm_gated for mamba2_mixer](../sources/prs/TensorRT-LLM/PR-11473.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[None][fix] Fix SM120 issue for rms_norm with nvfp4_quant_fusion](../sources/prs/TensorRT-LLM/PR-11774.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [Update autotune results for the nvfp4 cutlass moe backends for v0.2.9](../sources/prs/flashinfer/PR-1361.md), [Faster weight processing (moe nvfp4)](../sources/prs/flashinfer/PR-1412.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [Masked batch nvfp4 quantization](../sources/prs/flashinfer/PR-1774.md), [silu_and_mul nvfp4 quanization fusion rework](../sources/prs/flashinfer/PR-1927.md), [Feature: Support non-gated activation in cutlass fused MoE nvfp4](../sources/prs/flashinfer/PR-2011.md), [[performance]optimize for nvfp4](../sources/prs/flashinfer/PR-2268.md), [[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels](../sources/prs/flashinfer/PR-2303.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [tests: add bias testing to nvfp4 moe](../sources/prs/flashinfer/PR-2585.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [fix: Add SM120 (RTX Blackwell desktop) support for NVFP4 MoE kernels](../sources/prs/flashinfer/PR-2725.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [feat: Add CuTe-DSL backend for NVFP4 quantization](../sources/prs/flashinfer/PR-2838.md), [perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels](../sources/prs/flashinfer/PR-2904.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [perf: optimize per-token nvfp4 quantization kernel.](../sources/prs/flashinfer/PR-3237.md), [Optimize nvfp4 block scaled gemm kernel when M is small.](../sources/prs/sglang/PR-10101.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [[NVIDIA] Fix CUDA arch requirement in nvfp4 cast](../sources/prs/sglang/PR-12581.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Mistral Large 3 NVFP4 support](../sources/prs/sglang/PR-14485.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [[NVIDIA] Fixes for NVFP4 all-gather with spec decoding](../sources/prs/sglang/PR-15280.md), [Tiny fix cannot launch nvfp4 checkpoint with bf16 kv cache](../sources/prs/sglang/PR-15986.md), [Inclusion of nvfp4 blockscale in EPLB Rebalance](../sources/prs/sglang/PR-17158.md), [[Fix] GLM 4.7 + NVFP4 + MTP](../sources/prs/sglang/PR-17166.md), [[feat] Support nvfp4 quantized model of Qwen3-Next](../sources/prs/sglang/PR-17627.md), [[Bugfix] Fix Mistral Large 3 NVFP4 TRTLLM MoE](../sources/prs/sglang/PR-18065.md), [Fix nvfp4 weight update](../sources/prs/sglang/PR-18085.md), [[ModelOpt] Fix broken Qwen3-235B-A22B-Instruct-2507-NVFP4 launch](../sources/prs/sglang/PR-18189.md), [[ModelOPT] Support Qwen 3 Next Coder NVFP4](../sources/prs/sglang/PR-18224.md), [[Kimi-K2.5] Fix NVFP4 Kimi-K2.5 weight mapping and exclude list](../sources/prs/sglang/PR-18370.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[Qwen3.5] Enable nvfp4 checkpoint](../sources/prs/sglang/PR-18937.md), [feat: Support MXFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-19143.md), [Fix nightly Mistral-Large-3 NVFP4 accuracy threshold](../sources/prs/sglang/PR-19402.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[V32/GLM5] Change default setting of V32 nvfp4 on TP4](../sources/prs/sglang/PR-20086.md), [[diffusion] Support nvfp4 for Flux.2](../sources/prs/sglang/PR-20137.md), [[4/n jit_kernel restruct] speed up CI tests and add benchmark workflow](../sources/prs/sglang/PR-20268.md), [[Model] Support Nemotron 3 Super NVFP4](../sources/prs/sglang/PR-20407.md), [[JIT Kernel] Fix NVFP4 multi-arch compilation failure](../sources/prs/sglang/PR-20874.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Chore] Clean up JIT compilation flags](../sources/prs/sglang/PR-21022.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[diffusion] Default NVFP4 to CUTLASS and add all-model shape benchmarks](../sources/prs/sglang/PR-22091.md), [[Diffusion] Add diffusion NVFP4 scaled-mm correctness test](../sources/prs/sglang/PR-22127.md), [[RL] Refactor NVFP4 shuffling/swizzling to in-place replacement](../sources/prs/sglang/PR-22204.md), [[Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22574.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [[Diffusion] Add Wan2.2 ModelOpt NVFP4 support](../sources/prs/sglang/PR-22681.md), [[FlashInfer v0.6.11] [RL] Support FlashInfer per-token NVFP4 MoE](../sources/prs/sglang/PR-22918.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [perf(nvfp4): free unused source scales after weight processing](../sources/prs/sglang/PR-25107.md), [[codex] Update Wan2.2 ModelOpt CI checkpoints](../sources/prs/sglang/PR-25483.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [[Build] Fix cuda12.8 build error in nvfp4_scaled_mm_kernels.cu](../sources/prs/sglang/PR-4953.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [Support NVFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-7302.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Qwen FP8/NVFP4 ModelOPT Quantization support](../sources/prs/sglang/PR-7912.md), [[Fix][Ready]Fix register spilling in cutlass nvfp4 gemm kernel on Blackwell](../sources/prs/sglang/PR-8127.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [Faster weight processing (trtllm-gen moe nvfp4)](../sources/prs/sglang/PR-9162.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [Make fp4_quantize kernels work on sm103](../sources/prs/sglang/PR-9807.md), [[NVIDIA] Support nvfp4 quantization](../sources/prs/vllm/PR-12784.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[Hardware/NVIDIA/Kernel] [Functional Enablement] [1/N] Enable nvidia/DeepSeek-R1-FP4 Model](../sources/prs/vllm/PR-16362.md), [[Misc] Add compressed-tensors NVFP4A16 emulation support](../sources/prs/vllm/PR-17914.md), [Use NVFP4 Marlin for CompressedTensorsW4A16Fp4](../sources/prs/vllm/PR-18000.md), [[Quantization] Add compressed-tensors NVFP4 support](../sources/prs/vllm/PR-18312.md), [[Hardware][NVIDIA] FP4 MoE kernel optimization](../sources/prs/vllm/PR-19110.md), [[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization](../sources/prs/vllm/PR-19500.md), [[Quantization] Add compressed-tensors emulations support for NVFP4](../sources/prs/vllm/PR-19879.md), [[Quantization] Add compressed-tensors NVFP4 MoE Support](../sources/prs/vllm/PR-19990.md), [Add ModelOpt Qwen3 nvfp4 support](../sources/prs/vllm/PR-20101.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [[Kernel][Bugfix] Fixup some warnings in nvfp4_blockwise_moe when CUDA < 12.8](../sources/prs/vllm/PR-20324.md), [Support CUTLASS NVFP4 (w4a4) for Blackwell Geforce GPUs (SM120)](../sources/prs/vllm/PR-21309.md), [Support Tensorrt-LLM MoE fp4 for low-latency](../sources/prs/vllm/PR-21331.md), [Update flashinfer CUTLASS NVFP4 MoE Kernel to use per expert global scaling factor](../sources/prs/vllm/PR-21408.md), [[Bug] Fix Compressed Tensor NVFP4 `cutlass_fp4_group_mm` illegal memory access](../sources/prs/vllm/PR-21465.md), [[Feature] Add Flashinfer MoE Support for Compressed Tensor NVFP4](../sources/prs/vllm/PR-21639.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [Fix nvfp4 swizzling](../sources/prs/vllm/PR-23140.md), [fix incompatibililty with non cuda platform for nvfp4](../sources/prs/vllm/PR-23478.md), [[Bugfix] Fix Marlin NVFP4 for modelopt](../sources/prs/vllm/PR-23659.md), [[NVIDIA] Support SiluMul + NVFP4 quant fusion](../sources/prs/vllm/PR-23671.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [[Bugfix][Misc] Fix silu_and_mul_nvfp4_quant issue and extract common utils for nvfp4 kernel source files](../sources/prs/vllm/PR-23727.md), [[BUGFIX ] fix undefined silu_and_mul_nvfp4_quant](../sources/prs/vllm/PR-23929.md), [[Transform] [Quantization] Add QuTLASS support to vLLM](../sources/prs/vllm/PR-24440.md), [[Bugfix] Fix accuracy issue for silu_mul + nvfp4 quant fusion kernel](../sources/prs/vllm/PR-24833.md), [[Compile] Fix Compile Warning for Ignoring `MIN_BLOCK_PER_SM`](../sources/prs/vllm/PR-25193.md), [Enable Fbgemm NVFP4 on Dense models](../sources/prs/vllm/PR-25609.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Bugfix] Allow skipping MoE in NVFP4 (fix for MTP)](../sources/prs/vllm/PR-25987.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[NVIDIA] Add support for cudnn fp4 gemm via flashinfer](../sources/prs/vllm/PR-26107.md), [[ModelOpt] Load w13/w2_input_scale for all experts, nvfp4](../sources/prs/vllm/PR-26135.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [Add TRTLLM MoE NVFP4 kernel to CompressedTensorsW4A4MoeMethod](../sources/prs/vllm/PR-28892.md), [[Feat] Support non-gated activations in NVFP4 modelopt path](../sources/prs/vllm/PR-29004.md), [[Kernel] Add NVFP4 MoE CUTLASS support for SM120](../sources/prs/vllm/PR-29242.md), [[Bugfix] Fix mismatched nvfp4 gemm output shape](../sources/prs/vllm/PR-29742.md), [[EPLB] Support EPLB w/ NVFP4](../sources/prs/vllm/PR-29804.md), [[Compressed-Tensors] Simplify NVFP4 Conditions, enable marlin support for NVFP4A16 MoEs](../sources/prs/vllm/PR-30881.md), [[Kernel][Performance] Enable smaller Scaling Factor tiling for NVFP4 small-batch decoding](../sources/prs/vllm/PR-30885.md), [[NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size](../sources/prs/vllm/PR-30897.md), [ [FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/vllm/PR-31099.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[Perf] Fuse stride preparation for NVFP4 cutlass_moe](../sources/prs/vllm/PR-31837.md), [[Perf][Kernel] Optimize FP4 quantization kernels (SM100F)](../sources/prs/vllm/PR-32520.md), [Support compress-tensors with nvfp4 or fp8 weights and modelopt with nvfp4 weights on Turing](../sources/prs/vllm/PR-33076.md), [fix: Add SM120 (RTX Blackwell) support for FlashInfer CUTLASS NVFP4 MoE kernels](../sources/prs/vllm/PR-33417.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [[ModelBash][DSR1 NVFp4] Avoid Bf16 Bias Cast](../sources/prs/vllm/PR-34298.md), [[Custom Ops] Add functional + out variant for scaled_fp4_quant](../sources/prs/vllm/PR-34389.md), [[BUGFIX] Fix accuracy regression for NVIDIA-Nemotron-3-Nano-30B-A3B-NVFP4 with TP>1](../sources/prs/vllm/PR-34476.md), [[Model] Add NVFP4 quantization support for Step3.5-Flash](../sources/prs/vllm/PR-34478.md), [[Bugfix] Rescale NVFP4 weight scales to fix BF16 dequant underflow](../sources/prs/vllm/PR-34577.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [[BugFix] Fix fp4 quant kernel on CUDA 12.8](../sources/prs/vllm/PR-35210.md), [[NVFP4] Support NVFP4 dense models from `modelopt` and `compressed-tensors` on AMD Instinct MI300, MI355X and Hopper through emulation](../sources/prs/vllm/PR-35733.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[Mamba] Flashinfer selective_state_update](../sources/prs/vllm/PR-36162.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [[Bug][MoE] Fix TRTLLM NVFP4 Routing Kernel Precision](../sources/prs/vllm/PR-36725.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[MoE Refactor] Mxfp4 oracle rebased](../sources/prs/vllm/PR-37128.md), [Fix minimax m2.5 nvfp4 kv scales weight loading](../sources/prs/vllm/PR-37214.md), [[MoE/EPLB] Fix FlashInfer nvfp4 experts + EPLB correctness](../sources/prs/vllm/PR-37217.md), [[Kernel] Add non-gated support for NVFP4 CUTLASS MoE](../sources/prs/vllm/PR-37320.md), [[Bugfix] Fix EP weight filter breaking EPLB and NVFP4 accuracy](../sources/prs/vllm/PR-37322.md), [Add nvfp4 support to reshape_and_cache_flash](../sources/prs/vllm/PR-37332.md), [[Bugfix] Remove assertion for NVFP4 scale dynamic range](../sources/prs/vllm/PR-37465.md), [[Bugfix] Fix marlin nvfp4 rescaling](../sources/prs/vllm/PR-37502.md), [[4/n] Migrate FP4/W4A8 CUTLASS kernels to torch stable ABI](../sources/prs/vllm/PR-37503.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[Bugfix] Preserve CUDA arch suffix (a/f) for SM12x — fixes NVFP4 NaN on desktop Blackwell](../sources/prs/vllm/PR-37725.md), [[MoE] Move FlashInfer CuteDSL experts into fused_moe/experts/](../sources/prs/vllm/PR-37759.md), [[MoE Kernel] Flashinfer nvfp4 cutedsl moe kernel integration](../sources/prs/vllm/PR-38050.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [[Quantization] Add FlashInfer CuteDSL batched experts backend for NVFP4 MoE](../sources/prs/vllm/PR-38251.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[Compile] Fix nvfp4 compile warning](../sources/prs/vllm/PR-38573.md), [[Bugfix] Fix NVFP4+MTP crash: force unquantized mtp.fc for Qwen3.5](../sources/prs/vllm/PR-38832.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[Refactor] Move NVFP4 GEMM management into NvFp4LinearKernel](../sources/prs/vllm/PR-39129.md), [[Feature] Batch invariant nvfp4 linear support](../sources/prs/vllm/PR-39322.md), [[Kernel] Support TRTLLM GEN NVFP4 MoE for non-512-aligned hidden dims via weight padding](../sources/prs/vllm/PR-39510.md), [[Bugfix] Reject non-nvfp4 dtypes when using the flashinfer_nvlink_one_sided all2all backend](../sources/prs/vllm/PR-39717.md), [[Bug] Fix batch invariance nvfp4 support](../sources/prs/vllm/PR-39820.md), [Add nvfp4 kv cache support](../sources/prs/vllm/PR-40177.md), [[Bugfix] Guard mxfp4_experts_quant bindings on ENABLE_NVFP4_SM100](../sources/prs/vllm/PR-40191.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [Add NVFP4 all-gather GEMM fusion for AsyncTP](../sources/prs/vllm/PR-41882.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Perf] Padded nvfp4 quant kernel to remove additional copy, 2.4%~5.7% e2e performance improvement](../sources/prs/vllm/PR-42774.md), [NVFP4 and Block-Scaled Narrow Precision](../wiki/hardware/nvfp4.md), [Gated Dual GEMM (Gate-Up + SwiGLU Fusion)](../wiki/kernels/gated-dual-gemm.md), [Grouped GEMM for MoE](../wiki/kernels/grouped-gemm.md), [NVFP4 GEMM — 4-bit Floating Point Matrix Multiply](../wiki/kernels/nvfp4-gemm.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Fine-Grained FP8/FP4 Quantization](../wiki/techniques/fine-grained-quantization.md) | +| `ldmatrix` | [simveit load_and_store](../sources/blogs/simveit-load-and-store.md) | +| `mbarrier` | [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [CUTLASS 4.5.0 Cluster Launch Control Documentation](../sources/docs/cutlass-clc-documentation.md), [CUDA 13.0.2 TMA Documentation](../sources/docs/nvidia-cuda-13-0-2-tma.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Vectorize mbarrier initialization in warpspeed scan](../sources/prs/cccl/PR-8423.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [mbarrier (Memory Barrier Primitives)](../wiki/hardware/mbarrier.md), [tcgen05.mma — Blackwell MMA Instruction](../wiki/hardware/tcgen05-mma.md), [Tensor Memory Accelerator (TMA)](../wiki/hardware/tma.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Pipeline Stalls](../wiki/patterns/pipeline-stalls.md), [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md) | +| `nvfp4` | [Twelve Attempts at an FP4 Kernel](../sources/blogs/amandeep-nvfp4-attempts.md), [Anatomy of a Reward Hack](../sources/blogs/gpu-mode-reward-hack.md), [NVFP4 Format Details](../sources/blogs/nvfp4-format-details.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.5.0 Blackwell Sources](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Transformer Engine 2.13: NVFP4](../sources/docs/nvidia-transformer-engine-2.13-nvfp4.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.](../sources/prs/TensorRT-LLM/PR-10339.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[None][feat] Optimize super-v3 nvfp4 for better perf](../sources/prs/TensorRT-LLM/PR-11273.md), [[None][feat] Optimize by fuse nvfp4_quant to layernorm_gated for mamba2_mixer](../sources/prs/TensorRT-LLM/PR-11473.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[None][fix] Fix SM120 issue for rms_norm with nvfp4_quant_fusion](../sources/prs/TensorRT-LLM/PR-11774.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [Update autotune results for the nvfp4 cutlass moe backends for v0.2.9](../sources/prs/flashinfer/PR-1361.md), [Faster weight processing (moe nvfp4)](../sources/prs/flashinfer/PR-1412.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [Masked batch nvfp4 quantization](../sources/prs/flashinfer/PR-1774.md), [silu_and_mul nvfp4 quanization fusion rework](../sources/prs/flashinfer/PR-1927.md), [Feature: Support non-gated activation in cutlass fused MoE nvfp4](../sources/prs/flashinfer/PR-2011.md), [[performance]optimize for nvfp4](../sources/prs/flashinfer/PR-2268.md), [[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels](../sources/prs/flashinfer/PR-2303.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [tests: add bias testing to nvfp4 moe](../sources/prs/flashinfer/PR-2585.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [fix: Add SM120 (RTX Blackwell desktop) support for NVFP4 MoE kernels](../sources/prs/flashinfer/PR-2725.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [feat: Add CuTe-DSL backend for NVFP4 quantization](../sources/prs/flashinfer/PR-2838.md), [perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels](../sources/prs/flashinfer/PR-2904.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [perf: optimize per-token nvfp4 quantization kernel.](../sources/prs/flashinfer/PR-3237.md), [Optimize nvfp4 block scaled gemm kernel when M is small.](../sources/prs/sglang/PR-10101.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [[NVIDIA] Fix CUDA arch requirement in nvfp4 cast](../sources/prs/sglang/PR-12581.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Mistral Large 3 NVFP4 support](../sources/prs/sglang/PR-14485.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [[NVIDIA] Fixes for NVFP4 all-gather with spec decoding](../sources/prs/sglang/PR-15280.md), [Tiny fix cannot launch nvfp4 checkpoint with bf16 kv cache](../sources/prs/sglang/PR-15986.md), [Inclusion of nvfp4 blockscale in EPLB Rebalance](../sources/prs/sglang/PR-17158.md), [[Fix] GLM 4.7 + NVFP4 + MTP](../sources/prs/sglang/PR-17166.md), [[feat] Support nvfp4 quantized model of Qwen3-Next](../sources/prs/sglang/PR-17627.md), [[Bugfix] Fix Mistral Large 3 NVFP4 TRTLLM MoE](../sources/prs/sglang/PR-18065.md), [Fix nvfp4 weight update](../sources/prs/sglang/PR-18085.md), [[ModelOpt] Fix broken Qwen3-235B-A22B-Instruct-2507-NVFP4 launch](../sources/prs/sglang/PR-18189.md), [[ModelOPT] Support Qwen 3 Next Coder NVFP4](../sources/prs/sglang/PR-18224.md), [[Kimi-K2.5] Fix NVFP4 Kimi-K2.5 weight mapping and exclude list](../sources/prs/sglang/PR-18370.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[Qwen3.5] Enable nvfp4 checkpoint](../sources/prs/sglang/PR-18937.md), [feat: Support MXFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-19143.md), [Fix nightly Mistral-Large-3 NVFP4 accuracy threshold](../sources/prs/sglang/PR-19402.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[V32/GLM5] Change default setting of V32 nvfp4 on TP4](../sources/prs/sglang/PR-20086.md), [[diffusion] Support nvfp4 for Flux.2](../sources/prs/sglang/PR-20137.md), [[4/n jit_kernel restruct] speed up CI tests and add benchmark workflow](../sources/prs/sglang/PR-20268.md), [[Model] Support Nemotron 3 Super NVFP4](../sources/prs/sglang/PR-20407.md), [[JIT Kernel] Fix NVFP4 multi-arch compilation failure](../sources/prs/sglang/PR-20874.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Chore] Clean up JIT compilation flags](../sources/prs/sglang/PR-21022.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[diffusion] Default NVFP4 to CUTLASS and add all-model shape benchmarks](../sources/prs/sglang/PR-22091.md), [[Diffusion] Add diffusion NVFP4 scaled-mm correctness test](../sources/prs/sglang/PR-22127.md), [[RL] Refactor NVFP4 shuffling/swizzling to in-place replacement](../sources/prs/sglang/PR-22204.md), [[Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22574.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [[Diffusion] Add Wan2.2 ModelOpt NVFP4 support](../sources/prs/sglang/PR-22681.md), [[FlashInfer v0.6.11] [RL] Support FlashInfer per-token NVFP4 MoE](../sources/prs/sglang/PR-22918.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [perf(nvfp4): free unused source scales after weight processing](../sources/prs/sglang/PR-25107.md), [[codex] Update Wan2.2 ModelOpt CI checkpoints](../sources/prs/sglang/PR-25483.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [[Build] Fix cuda12.8 build error in nvfp4_scaled_mm_kernels.cu](../sources/prs/sglang/PR-4953.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [Support NVFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-7302.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Qwen FP8/NVFP4 ModelOPT Quantization support](../sources/prs/sglang/PR-7912.md), [[Fix][Ready]Fix register spilling in cutlass nvfp4 gemm kernel on Blackwell](../sources/prs/sglang/PR-8127.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [Faster weight processing (trtllm-gen moe nvfp4)](../sources/prs/sglang/PR-9162.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [Make fp4_quantize kernels work on sm103](../sources/prs/sglang/PR-9807.md), [[NVIDIA] Support nvfp4 quantization](../sources/prs/vllm/PR-12784.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[Hardware/NVIDIA/Kernel] [Functional Enablement] [1/N] Enable nvidia/DeepSeek-R1-FP4 Model](../sources/prs/vllm/PR-16362.md), [[Misc] Add compressed-tensors NVFP4A16 emulation support](../sources/prs/vllm/PR-17914.md), [Use NVFP4 Marlin for CompressedTensorsW4A16Fp4](../sources/prs/vllm/PR-18000.md), [[Quantization] Add compressed-tensors NVFP4 support](../sources/prs/vllm/PR-18312.md), [[Hardware][NVIDIA] FP4 MoE kernel optimization](../sources/prs/vllm/PR-19110.md), [[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization](../sources/prs/vllm/PR-19500.md), [[Quantization] Add compressed-tensors emulations support for NVFP4](../sources/prs/vllm/PR-19879.md), [[Quantization] Add compressed-tensors NVFP4 MoE Support](../sources/prs/vllm/PR-19990.md), [Add ModelOpt Qwen3 nvfp4 support](../sources/prs/vllm/PR-20101.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [[Kernel][Bugfix] Fixup some warnings in nvfp4_blockwise_moe when CUDA < 12.8](../sources/prs/vllm/PR-20324.md), [Support CUTLASS NVFP4 (w4a4) for Blackwell Geforce GPUs (SM120)](../sources/prs/vllm/PR-21309.md), [Support Tensorrt-LLM MoE fp4 for low-latency](../sources/prs/vllm/PR-21331.md), [Update flashinfer CUTLASS NVFP4 MoE Kernel to use per expert global scaling factor](../sources/prs/vllm/PR-21408.md), [[Bug] Fix Compressed Tensor NVFP4 `cutlass_fp4_group_mm` illegal memory access](../sources/prs/vllm/PR-21465.md), [[Feature] Add Flashinfer MoE Support for Compressed Tensor NVFP4](../sources/prs/vllm/PR-21639.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [Fix nvfp4 swizzling](../sources/prs/vllm/PR-23140.md), [fix incompatibililty with non cuda platform for nvfp4](../sources/prs/vllm/PR-23478.md), [[Bugfix] Fix Marlin NVFP4 for modelopt](../sources/prs/vllm/PR-23659.md), [[NVIDIA] Support SiluMul + NVFP4 quant fusion](../sources/prs/vllm/PR-23671.md), [[Bugfix][Misc] Fix silu_and_mul_nvfp4_quant issue and extract common utils for nvfp4 kernel source files](../sources/prs/vllm/PR-23727.md), [[BUGFIX ] fix undefined silu_and_mul_nvfp4_quant](../sources/prs/vllm/PR-23929.md), [[Transform] [Quantization] Add QuTLASS support to vLLM](../sources/prs/vllm/PR-24440.md), [[Bugfix] Fix accuracy issue for silu_mul + nvfp4 quant fusion kernel](../sources/prs/vllm/PR-24833.md), [[Compile] Fix Compile Warning for Ignoring `MIN_BLOCK_PER_SM`](../sources/prs/vllm/PR-25193.md), [Enable Fbgemm NVFP4 on Dense models](../sources/prs/vllm/PR-25609.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Bugfix] Allow skipping MoE in NVFP4 (fix for MTP)](../sources/prs/vllm/PR-25987.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[NVIDIA] Add support for cudnn fp4 gemm via flashinfer](../sources/prs/vllm/PR-26107.md), [[ModelOpt] Load w13/w2_input_scale for all experts, nvfp4](../sources/prs/vllm/PR-26135.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [Add TRTLLM MoE NVFP4 kernel to CompressedTensorsW4A4MoeMethod](../sources/prs/vllm/PR-28892.md), [[Feat] Support non-gated activations in NVFP4 modelopt path](../sources/prs/vllm/PR-29004.md), [[Kernel] Add NVFP4 MoE CUTLASS support for SM120](../sources/prs/vllm/PR-29242.md), [[Bugfix] Fix mismatched nvfp4 gemm output shape](../sources/prs/vllm/PR-29742.md), [[EPLB] Support EPLB w/ NVFP4](../sources/prs/vllm/PR-29804.md), [[Compressed-Tensors] Simplify NVFP4 Conditions, enable marlin support for NVFP4A16 MoEs](../sources/prs/vllm/PR-30881.md), [[Kernel][Performance] Enable smaller Scaling Factor tiling for NVFP4 small-batch decoding](../sources/prs/vllm/PR-30885.md), [[NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size](../sources/prs/vllm/PR-30897.md), [ [FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/vllm/PR-31099.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[Perf] Fuse stride preparation for NVFP4 cutlass_moe](../sources/prs/vllm/PR-31837.md), [[Perf][Kernel] Optimize FP4 quantization kernels (SM100F)](../sources/prs/vllm/PR-32520.md), [Support compress-tensors with nvfp4 or fp8 weights and modelopt with nvfp4 weights on Turing](../sources/prs/vllm/PR-33076.md), [fix: Add SM120 (RTX Blackwell) support for FlashInfer CUTLASS NVFP4 MoE kernels](../sources/prs/vllm/PR-33417.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [[ModelBash][DSR1 NVFp4] Avoid Bf16 Bias Cast](../sources/prs/vllm/PR-34298.md), [[Custom Ops] Add functional + out variant for scaled_fp4_quant](../sources/prs/vllm/PR-34389.md), [[BUGFIX] Fix accuracy regression for NVIDIA-Nemotron-3-Nano-30B-A3B-NVFP4 with TP>1](../sources/prs/vllm/PR-34476.md), [[Model] Add NVFP4 quantization support for Step3.5-Flash](../sources/prs/vllm/PR-34478.md), [[Bugfix] Rescale NVFP4 weight scales to fix BF16 dequant underflow](../sources/prs/vllm/PR-34577.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [[BugFix] Fix fp4 quant kernel on CUDA 12.8](../sources/prs/vllm/PR-35210.md), [[NVFP4] Support NVFP4 dense models from `modelopt` and `compressed-tensors` on AMD Instinct MI300, MI355X and Hopper through emulation](../sources/prs/vllm/PR-35733.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[Mamba] Flashinfer selective_state_update](../sources/prs/vllm/PR-36162.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [[Bug][MoE] Fix TRTLLM NVFP4 Routing Kernel Precision](../sources/prs/vllm/PR-36725.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[MoE Refactor] Mxfp4 oracle rebased](../sources/prs/vllm/PR-37128.md), [Fix minimax m2.5 nvfp4 kv scales weight loading](../sources/prs/vllm/PR-37214.md), [[MoE/EPLB] Fix FlashInfer nvfp4 experts + EPLB correctness](../sources/prs/vllm/PR-37217.md), [[Kernel] Add non-gated support for NVFP4 CUTLASS MoE](../sources/prs/vllm/PR-37320.md), [[Bugfix] Fix EP weight filter breaking EPLB and NVFP4 accuracy](../sources/prs/vllm/PR-37322.md), [Add nvfp4 support to reshape_and_cache_flash](../sources/prs/vllm/PR-37332.md), [[Bugfix] Remove assertion for NVFP4 scale dynamic range](../sources/prs/vllm/PR-37465.md), [[Bugfix] Fix marlin nvfp4 rescaling](../sources/prs/vllm/PR-37502.md), [[4/n] Migrate FP4/W4A8 CUTLASS kernels to torch stable ABI](../sources/prs/vllm/PR-37503.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[Bugfix] Preserve CUDA arch suffix (a/f) for SM12x — fixes NVFP4 NaN on desktop Blackwell](../sources/prs/vllm/PR-37725.md), [[MoE] Move FlashInfer CuteDSL experts into fused_moe/experts/](../sources/prs/vllm/PR-37759.md), [[MoE Kernel] Flashinfer nvfp4 cutedsl moe kernel integration](../sources/prs/vllm/PR-38050.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [[Quantization] Add FlashInfer CuteDSL batched experts backend for NVFP4 MoE](../sources/prs/vllm/PR-38251.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[Compile] Fix nvfp4 compile warning](../sources/prs/vllm/PR-38573.md), [[Bugfix] Fix NVFP4+MTP crash: force unquantized mtp.fc for Qwen3.5](../sources/prs/vllm/PR-38832.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[Refactor] Move NVFP4 GEMM management into NvFp4LinearKernel](../sources/prs/vllm/PR-39129.md), [[Feature] Batch invariant nvfp4 linear support](../sources/prs/vllm/PR-39322.md), [[Kernel] Support TRTLLM GEN NVFP4 MoE for non-512-aligned hidden dims via weight padding](../sources/prs/vllm/PR-39510.md), [[Bugfix] Reject non-nvfp4 dtypes when using the flashinfer_nvlink_one_sided all2all backend](../sources/prs/vllm/PR-39717.md), [[Bug] Fix batch invariance nvfp4 support](../sources/prs/vllm/PR-39820.md), [Add nvfp4 kv cache support](../sources/prs/vllm/PR-40177.md), [[Bugfix] Guard mxfp4_experts_quant bindings on ENABLE_NVFP4_SM100](../sources/prs/vllm/PR-40191.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [Add NVFP4 all-gather GEMM fusion for AsyncTP](../sources/prs/vllm/PR-41882.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Perf] Padded nvfp4 quant kernel to remove additional copy, 2.4%~5.7% e2e performance improvement](../sources/prs/vllm/PR-42774.md), [NVFP4 and Block-Scaled Narrow Precision](../wiki/hardware/nvfp4.md), [GPU Mode NVFP4 Gated Dual GEMM](../wiki/kernels/gated-dual-gemm.md), [Grouped GEMM Contracts for MoE and NVFP4](../wiki/kernels/grouped-gemm.md), [NVFP4 GEMM — GPU Mode Problem 2 Contract](../wiki/kernels/nvfp4-gemm.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Fine-Grained FP8/FP4 Quantization](../wiki/techniques/fine-grained-quantization.md) | | `pdl` | [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [Programmatic Dependent Launch / Grid Dependency Control](../wiki/hardware/pdl-gdc.md) | -| `tcgen05` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax CUTLASS Tutorial: GEMM Kernels Using Tensor Memory for Blackwell](../sources/blogs/colfax-cutlass-blackwell.md), [DeepGEMM — FP8 GEMM Library](../sources/blogs/deepgemm.md), [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [FlashAttention-4: Hardware-Friendly Attention on Blackwell](../sources/docs/flash-attention-4.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Tiled Flash Linear Attention (TFLA)](../sources/docs/tfla.md), [Triton 3.6.0 Release Notes — Blackwell (SM100) Lowering](../sources/docs/triton-3.6-blackwell.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [[Cutlass gemm] Fix SM100 FP8 nosmem epilogue-fusion shape_div 'Divisibility Condition' for non-multiple-of-64 N tiles](../sources/prs/cutlass/PR-2946.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [Two-SM Cooperative MMA](../wiki/hardware/2sm-cooperative.md), [tcgen05.mma — Blackwell MMA Instruction](../wiki/hardware/tcgen05-mma.md), [Tensor Memory (TMEM)](../wiki/hardware/tmem.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [FP8 Block-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [Grouped GEMM for MoE](../wiki/kernels/grouped-gemm.md), [NVFP4 GEMM — 4-bit Floating Point Matrix Multiply](../wiki/kernels/nvfp4-gemm.md), [CUDA C++ for Blackwell Kernels](../wiki/languages/cuda-cpp.md), [CuTe DSL for Blackwell](../wiki/languages/cute-dsl.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Register Accumulators to TMEM](../wiki/migration/register-to-tmem.md), [Migrating from wgmma to tcgen05](../wiki/migration/wgmma-to-tcgen05.md), [Not Reaching Peak FLOPS](../wiki/patterns/compute-bound.md), [Pipeline Stalls](../wiki/patterns/pipeline-stalls.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md) | -| `tma` | [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Kernels](../sources/blogs/colfax-cutlass-kernels.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [simveit effective_transpose](../sources/blogs/simveit-effective-transpose.md), [simveit load_and_store](../sources/blogs/simveit-load-and-store.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[TRTLLM-10022][feat] Add hopper xqa decode support for skip softmax attention](../sources/prs/TensorRT-LLM/PR-10264.md), [[https://nvbugs/5669671][fix] Support GuidedDecoder with sharded logits (pick #10698)](../sources/prs/TensorRT-LLM/PR-10742.md), [[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth](../sources/prs/TensorRT-LLM/PR-10987.md), [[TRTLLM-11092][feat] add support for visual gen FA4 attention backend](../sources/prs/TensorRT-LLM/PR-11697.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[None][feat] Trtllm-gen FMHA JIT support](../sources/prs/TensorRT-LLM/PR-12612.md), [[TRTLLM-11485][feat] Feature rework: Add SageAttention refreshed kernels (attentionOp only)](../sources/prs/TensorRT-LLM/PR-12937.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[None][feat] Update the logic of FMHA JIT path](../sources/prs/TensorRT-LLM/PR-14291.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [Improve sm90 mixed dtype kernel](../sources/prs/cutlass/PR-1883.md), [[EVT] Add support for Row/Col broadcast PtrArray](../sources/prs/cutlass/PR-2033.md), [Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2037.md), [Improvements for: Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2095.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [Flash MLA support](../sources/prs/cutlass/PR-2130.md), [Flash MLA Support - Step 2](../sources/prs/cutlass/PR-2134.md), [Fix sm100 gemm wrong static constexpr that breaks compilation on Windows](../sources/prs/cutlass/PR-2167.md), [Fix SM90 beta=1 hang and stream-K launch errors](../sources/prs/cutlass/PR-2172.md), [hopper-blockwise-generalization-optimization](../sources/prs/cutlass/PR-2270.md), [[ex77] fix mla split; add fwd lse; add bwd varlen](../sources/prs/cutlass/PR-2366.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [fix: examples/cute/tutorial/blackwell/04_mma_tma_2sm_sm100.cu GridDim miscalculated](../sources/prs/cutlass/PR-2492.md), [Support PDL for SM90 Array TMA GEMM](../sources/prs/cutlass/PR-2719.md), [[Bug Fix]Bypass launch grids for SM120 Kernel with SM90 Mainloop & SM100 TileScheduler](../sources/prs/cutlass/PR-2865.md), [new example with TMA prefetch feature targeting for DRAM latency boun…](../sources/prs/cutlass/PR-2881.md), [[Bug Fix]Set NumSplitsM to 1 when TileShapeM < 128 in sm90 fp8 blockwise scaling CollectiveMma](../sources/prs/cutlass/PR-2965.md), [Replace std::min with cute::min in sm120 blockwise scaling device functions](../sources/prs/cutlass/PR-3055.md), [Small Tile N BlockScaled GEMM + Grouped GEMM on SM12x](../sources/prs/cutlass/PR-3176.md), [Add var-seq-len to FA3 fp16 / bf16 fwd](../sources/prs/flash-attention/PR-1072.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [Add seqused_q in fwd / bwd and seqused_k in bwd in hopper FA.](../sources/prs/flash-attention/PR-1182.md), [Add local attention in Hopper FAv3](../sources/prs/flash-attention/PR-1233.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [Paged Attention support for FA3](../sources/prs/flash-attention/PR-1268.md), [FA3 paged attention: Readiness for Cutlass 3.6 / default value for block_table](../sources/prs/flash-attention/PR-1331.md), [Fix FA3 Varlen Performance regression](../sources/prs/flash-attention/PR-1361.md), [Support hdimQK != hdimV backward](../sources/prs/flash-attention/PR-1604.md), [Improve causal backward determinism perf with SPT schedule](../sources/prs/flash-attention/PR-1893.md), [[Cute,Sm100,Fwd] use correction warps for epi when not using TMA](../sources/prs/flash-attention/PR-2014.md), [[Cute,Fwd,Sm100] don't pass mask_fn to softmax_step generically](../sources/prs/flash-attention/PR-2026.md), [[Cute,Fwd] Extend score_mod to variable sequence length](../sources/prs/flash-attention/PR-2043.md), [Add score-mod bwd support ](../sources/prs/flash-attention/PR-2070.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [[Fwd,Sm90] Add paged KV attention support (tma and cp.async)](../sources/prs/flash-attention/PR-2360.md), [[Cute,Sm100,Fwd] add MLA 64/512 with topk sparsity for MQA 128 heads](../sources/prs/flash-attention/PR-2441.md), [[hd256] Add TMA paged KV support to SM100 2CTA forward kernel](../sources/prs/flash-attention/PR-2489.md), [[FA4][hd256] Backward TMA bulk-store epilogue + LSE/dpsum coalesce](../sources/prs/flash-attention/PR-2497.md), [feat: Softmax free sampling](../sources/prs/flashinfer/PR-1035.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [bugfix: adding lse output to blackwell fmha kernels](../sources/prs/flashinfer/PR-1071.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [feat: Fused temperature online softmax kernel](../sources/prs/flashinfer/PR-1153.md), [feat: logits processor fustion rule for temperature softmax](../sources/prs/flashinfer/PR-1170.md), [bugfix: softmax NaN results caused by large -inf masks](../sources/prs/flashinfer/PR-1178.md), [bugfix: fix blackwell fmha hanging issue for empty kv_len](../sources/prs/flashinfer/PR-1198.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [Add blockwise-scaled FP8 GEMM via TRTLLM-Gen.](../sources/prs/flashinfer/PR-1320.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [bugfix: fix fused-temperature softmax IMA issue](../sources/prs/flashinfer/PR-1596.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [Tune kernel compilation parameters for https://github.com/flashinfer-ai/flashinfer/pull/1850 ](../sources/prs/flashinfer/PR-1878.md), [Update trtllm-gen fused moe routing kernel and add more kernels](../sources/prs/flashinfer/PR-1955.md), [Feature: Add support for L40 FusedMoE in cutlass path](../sources/prs/flashinfer/PR-1973.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [perf: improve sampling/mask/softmax performance (part 1/2)](../sources/prs/flashinfer/PR-2044.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [update xqa license](../sources/prs/flashinfer/PR-2117.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [refactor: pull trtllm-gen batch-gemm/gemm headers from artifactory; update tma descriptor shape init](../sources/prs/flashinfer/PR-2235.md), [feat: add GDN Attention](../sources/prs/flashinfer/PR-2276.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [feat: update trtllm-gen MoE cubins](../sources/prs/flashinfer/PR-2416.md), [refactor: reduce hopper's gdn prefill compilation time and fix docstring.](../sources/prs/flashinfer/PR-2422.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [misc: Update gemm/batched gemm cubins from trtllm-gen, gemm header refactor](../sources/prs/flashinfer/PR-2740.md), [Upgrade cutlass 4.2.1 -> 4.4.2](../sources/prs/flashinfer/PR-2798.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [feat(gdn): state checkpointing in chunk_gated_delta_rule](../sources/prs/flashinfer/PR-2908.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [[inductor][triton 3.3] Fix cpp_wrapper w/ TMA in triton 3.3](../sources/prs/pytorch/PR-149993.md), [[user triton] AOT inductor support for device-side TMA](../sources/prs/pytorch/PR-157241.md), [[kernel][moe] add moe topk fast](../sources/prs/sglang/PR-13969.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [Support skip-softmax attention](../sources/prs/sglang/PR-19089.md), [[Kernel] Fuse temperature + softmax in sampling for decode speedup](../sources/prs/sglang/PR-20501.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [support blockwise fp8 matmul kernel](../sources/prs/sglang/PR-3267.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [Create col-major and tma-aligned x_scale for deep_gemm.gemm_fp8_fp8_bf16_nt](../sources/prs/sglang/PR-4515.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [[NVIDIA] Fix missing `get_col_major_tma_aligned_tensor` for Blackwell deepgemm in EpMoE](../sources/prs/sglang/PR-8955.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[BugFix] Fix Hopper TMA lowering without warp specialization](../sources/prs/tilelang/PR-1840.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add T.copy_cluster to support TMA multicast and SM-to-SM cluster copy](../sources/prs/tilelang/PR-1908.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[Bugfix] Enable `.shared::cta` in TMA copy paths only on CUDA 12.8+](../sources/prs/tilelang/PR-2087.md), [[TMA] Support FP4 TensorMap TMA copies](../sources/prs/tilelang/PR-2107.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[Kernel] Update `cutlass_scaled_mm` to support 2d group (blockwise) scaling](../sources/prs/vllm/PR-11868.md), [Add: Support for Sparse24Bitmask Compressed Models](../sources/prs/vllm/PR-12097.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[BugFix] Illegal Memory Access in the blockwise cutlass fp8 GEMMs](../sources/prs/vllm/PR-14396.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [Fix `numel()` downcast in vllm/csrc/moe/moe_align_sum_kernels.cu +2](../sources/prs/vllm/PR-17082.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[Perf] Use upstream CUTLASS for SM90 Block FP8 kernel](../sources/prs/vllm/PR-23280.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [[Kernel] Add topk_sigmoid kernel](../sources/prs/vllm/PR-31246.md), [Add TMA support to fused_moe_lora kernel](../sources/prs/vllm/PR-32195.md), [[Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper](../sources/prs/vllm/PR-32619.md), [[Bugfix] Fix quant RMS norm fusion for quantization with TMA-aligned scales](../sources/prs/vllm/PR-33255.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[Perf][GDN] Align TMA usage with upstream FLA](../sources/prs/vllm/PR-38981.md), [fix: clamp NaN/Inf in topk_softmax to prevent duplicate expert IDs](../sources/prs/vllm/PR-39391.md), [mbarrier (Memory Barrier Primitives)](../wiki/hardware/mbarrier.md), [Tensor Memory Accelerator (TMA)](../wiki/hardware/tma.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [CuTe DSL for Blackwell](../wiki/languages/cute-dsl.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Pipeline Stalls](../wiki/patterns/pipeline-stalls.md), [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md), [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md), [Shared Memory Swizzling](../wiki/techniques/swizzling.md) | -| `tmem` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax CUTLASS Tutorial: GEMM Kernels Using Tensor Memory for Blackwell](../sources/blogs/colfax-cutlass-blackwell.md), [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [FlashAttention-4: Hardware-Friendly Attention on Blackwell](../sources/docs/flash-attention-4.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Triton 3.6.0 Release Notes — Blackwell (SM100) Lowering](../sources/docs/triton-3.6-blackwell.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [tcgen05.mma — Blackwell MMA Instruction](../wiki/hardware/tcgen05-mma.md), [Tensor Memory (TMEM)](../wiki/hardware/tmem.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [Gated Dual GEMM (Gate-Up + SwiGLU Fusion)](../wiki/kernels/gated-dual-gemm.md), [NVFP4 GEMM — 4-bit Floating Point Matrix Multiply](../wiki/kernels/nvfp4-gemm.md), [CUDA C++ for Blackwell Kernels](../wiki/languages/cuda-cpp.md), [CuTe DSL for Blackwell](../wiki/languages/cute-dsl.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Register Accumulators to TMEM](../wiki/migration/register-to-tmem.md), [Migrating from wgmma to tcgen05](../wiki/migration/wgmma-to-tcgen05.md), [Register Pressure — Low Occupancy](../wiki/patterns/register-pressure.md), [Double/Multi-Buffering Patterns](../wiki/techniques/double-buffering.md), [Epilogue Fusion](../wiki/techniques/epilogue-fusion.md), [Kernel Fusion](../wiki/techniques/kernel-fusion.md), [Ping-Pong Scheduling](../wiki/techniques/ping-pong-scheduling.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md) | -| `wgmma` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Kernels](../sources/blogs/colfax-cutlass-kernels.md), [DeepGEMM — FP8 GEMM Library](../sources/blogs/deepgemm.md), [simveit load_and_store](../sources/blogs/simveit-load-and-store.md), [Tiled Flash Linear Attention (TFLA)](../sources/docs/tfla.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Add swizzle layout detection and automatic merging for layout conflicts](../sources/prs/tilelang/PR-1736.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [FP8 Block-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [Migrating from wgmma to tcgen05](../wiki/migration/wgmma-to-tcgen05.md), [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md) | +| `stmatrix` | [simveit load_and_store](../sources/blogs/simveit-load-and-store.md) | +| `tcgen05` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax CUTLASS Tutorial: GEMM Kernels Using Tensor Memory for Blackwell](../sources/blogs/colfax-cutlass-blackwell.md), [DeepGEMM — Pinned Upstream Project Summary](../sources/blogs/deepgemm.md), [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [FlashAttention-4: Algorithm and Kernel Co-design for Blackwell GPUs](../sources/docs/flash-attention-4.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.5.0 Blackwell Sources](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Triton v3.3.0 — Blackwell TCGen5/TMEM Boundary](../sources/docs/triton-3.3-blackwell.md), [Triton v3.6.0 — Incremental Blackwell Changes](../sources/docs/triton-3.6-blackwell.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [[Cutlass gemm] Fix SM100 FP8 nosmem epilogue-fusion shape_div 'Divisibility Condition' for non-multiple-of-64 N tiles](../sources/prs/cutlass/PR-2946.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [Two-SM Cooperative MMA](../wiki/hardware/2sm-cooperative.md), [mbarrier (Memory Barrier Primitives)](../wiki/hardware/mbarrier.md), [tcgen05.mma — Blackwell MMA Instruction](../wiki/hardware/tcgen05-mma.md), [Tensor Memory (TMEM)](../wiki/hardware/tmem.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [FP8 Fine-Grained-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [NVFP4 GEMM — GPU Mode Problem 2 Contract](../wiki/kernels/nvfp4-gemm.md), [CUDA C++ for Blackwell Kernels](../wiki/languages/cuda-cpp.md), [CuTe DSL for Blackwell](../wiki/languages/cute-dsl.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Register Accumulators to TMEM](../wiki/migration/register-to-tmem.md), [Migrating from wgmma to tcgen05](../wiki/migration/wgmma-to-tcgen05.md), [Not Reaching the Relevant Compute Ceiling](../wiki/patterns/compute-bound.md), [Pipeline Stalls](../wiki/patterns/pipeline-stalls.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md) | +| `tma` | [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Kernels](../sources/blogs/colfax-cutlass-kernels.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [simveit effective_transpose](../sources/blogs/simveit-effective-transpose.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [CUDA 13.0.2 TMA Documentation](../sources/docs/nvidia-cuda-13-0-2-tma.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.5.0 Blackwell Sources](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[TRTLLM-10022][feat] Add hopper xqa decode support for skip softmax attention](../sources/prs/TensorRT-LLM/PR-10264.md), [[https://nvbugs/5669671][fix] Support GuidedDecoder with sharded logits (pick #10698)](../sources/prs/TensorRT-LLM/PR-10742.md), [[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth](../sources/prs/TensorRT-LLM/PR-10987.md), [[TRTLLM-11092][feat] add support for visual gen FA4 attention backend](../sources/prs/TensorRT-LLM/PR-11697.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[None][feat] Trtllm-gen FMHA JIT support](../sources/prs/TensorRT-LLM/PR-12612.md), [[TRTLLM-11485][feat] Feature rework: Add SageAttention refreshed kernels (attentionOp only)](../sources/prs/TensorRT-LLM/PR-12937.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[None][feat] Update the logic of FMHA JIT path](../sources/prs/TensorRT-LLM/PR-14291.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [Improve sm90 mixed dtype kernel](../sources/prs/cutlass/PR-1883.md), [[EVT] Add support for Row/Col broadcast PtrArray](../sources/prs/cutlass/PR-2033.md), [Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2037.md), [Improvements for: Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2095.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [Flash MLA support](../sources/prs/cutlass/PR-2130.md), [Flash MLA Support - Step 2](../sources/prs/cutlass/PR-2134.md), [Fix sm100 gemm wrong static constexpr that breaks compilation on Windows](../sources/prs/cutlass/PR-2167.md), [Fix SM90 beta=1 hang and stream-K launch errors](../sources/prs/cutlass/PR-2172.md), [hopper-blockwise-generalization-optimization](../sources/prs/cutlass/PR-2270.md), [[ex77] fix mla split; add fwd lse; add bwd varlen](../sources/prs/cutlass/PR-2366.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [fix: examples/cute/tutorial/blackwell/04_mma_tma_2sm_sm100.cu GridDim miscalculated](../sources/prs/cutlass/PR-2492.md), [Support PDL for SM90 Array TMA GEMM](../sources/prs/cutlass/PR-2719.md), [[Bug Fix]Bypass launch grids for SM120 Kernel with SM90 Mainloop & SM100 TileScheduler](../sources/prs/cutlass/PR-2865.md), [new example with TMA prefetch feature targeting for DRAM latency boun…](../sources/prs/cutlass/PR-2881.md), [[Bug Fix]Set NumSplitsM to 1 when TileShapeM < 128 in sm90 fp8 blockwise scaling CollectiveMma](../sources/prs/cutlass/PR-2965.md), [Replace std::min with cute::min in sm120 blockwise scaling device functions](../sources/prs/cutlass/PR-3055.md), [Small Tile N BlockScaled GEMM + Grouped GEMM on SM12x](../sources/prs/cutlass/PR-3176.md), [Add var-seq-len to FA3 fp16 / bf16 fwd](../sources/prs/flash-attention/PR-1072.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [Add seqused_q in fwd / bwd and seqused_k in bwd in hopper FA.](../sources/prs/flash-attention/PR-1182.md), [Add local attention in Hopper FAv3](../sources/prs/flash-attention/PR-1233.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [Paged Attention support for FA3](../sources/prs/flash-attention/PR-1268.md), [FA3 paged attention: Readiness for Cutlass 3.6 / default value for block_table](../sources/prs/flash-attention/PR-1331.md), [Fix FA3 Varlen Performance regression](../sources/prs/flash-attention/PR-1361.md), [Support hdimQK != hdimV backward](../sources/prs/flash-attention/PR-1604.md), [Improve causal backward determinism perf with SPT schedule](../sources/prs/flash-attention/PR-1893.md), [[Cute,Sm100,Fwd] use correction warps for epi when not using TMA](../sources/prs/flash-attention/PR-2014.md), [[Cute,Fwd,Sm100] don't pass mask_fn to softmax_step generically](../sources/prs/flash-attention/PR-2026.md), [[Cute,Fwd] Extend score_mod to variable sequence length](../sources/prs/flash-attention/PR-2043.md), [Add score-mod bwd support ](../sources/prs/flash-attention/PR-2070.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [[Fwd,Sm90] Add paged KV attention support (tma and cp.async)](../sources/prs/flash-attention/PR-2360.md), [[Cute,Sm100,Fwd] add MLA 64/512 with topk sparsity for MQA 128 heads](../sources/prs/flash-attention/PR-2441.md), [[hd256] Add TMA paged KV support to SM100 2CTA forward kernel](../sources/prs/flash-attention/PR-2489.md), [[FA4][hd256] Backward TMA bulk-store epilogue + LSE/dpsum coalesce](../sources/prs/flash-attention/PR-2497.md), [feat: Softmax free sampling](../sources/prs/flashinfer/PR-1035.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [bugfix: adding lse output to blackwell fmha kernels](../sources/prs/flashinfer/PR-1071.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [feat: Fused temperature online softmax kernel](../sources/prs/flashinfer/PR-1153.md), [feat: logits processor fustion rule for temperature softmax](../sources/prs/flashinfer/PR-1170.md), [bugfix: softmax NaN results caused by large -inf masks](../sources/prs/flashinfer/PR-1178.md), [bugfix: fix blackwell fmha hanging issue for empty kv_len](../sources/prs/flashinfer/PR-1198.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [Add blockwise-scaled FP8 GEMM via TRTLLM-Gen.](../sources/prs/flashinfer/PR-1320.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [bugfix: fix fused-temperature softmax IMA issue](../sources/prs/flashinfer/PR-1596.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [Tune kernel compilation parameters for https://github.com/flashinfer-ai/flashinfer/pull/1850 ](../sources/prs/flashinfer/PR-1878.md), [Update trtllm-gen fused moe routing kernel and add more kernels](../sources/prs/flashinfer/PR-1955.md), [Feature: Add support for L40 FusedMoE in cutlass path](../sources/prs/flashinfer/PR-1973.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [perf: improve sampling/mask/softmax performance (part 1/2)](../sources/prs/flashinfer/PR-2044.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [update xqa license](../sources/prs/flashinfer/PR-2117.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [refactor: pull trtllm-gen batch-gemm/gemm headers from artifactory; update tma descriptor shape init](../sources/prs/flashinfer/PR-2235.md), [feat: add GDN Attention](../sources/prs/flashinfer/PR-2276.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [feat: update trtllm-gen MoE cubins](../sources/prs/flashinfer/PR-2416.md), [refactor: reduce hopper's gdn prefill compilation time and fix docstring.](../sources/prs/flashinfer/PR-2422.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [misc: Update gemm/batched gemm cubins from trtllm-gen, gemm header refactor](../sources/prs/flashinfer/PR-2740.md), [Upgrade cutlass 4.2.1 -> 4.4.2](../sources/prs/flashinfer/PR-2798.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [feat(gdn): state checkpointing in chunk_gated_delta_rule](../sources/prs/flashinfer/PR-2908.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [[inductor][triton 3.3] Fix cpp_wrapper w/ TMA in triton 3.3](../sources/prs/pytorch/PR-149993.md), [[user triton] AOT inductor support for device-side TMA](../sources/prs/pytorch/PR-157241.md), [[kernel][moe] add moe topk fast](../sources/prs/sglang/PR-13969.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [Support skip-softmax attention](../sources/prs/sglang/PR-19089.md), [[Kernel] Fuse temperature + softmax in sampling for decode speedup](../sources/prs/sglang/PR-20501.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [support blockwise fp8 matmul kernel](../sources/prs/sglang/PR-3267.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [Create col-major and tma-aligned x_scale for deep_gemm.gemm_fp8_fp8_bf16_nt](../sources/prs/sglang/PR-4515.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [[NVIDIA] Fix missing `get_col_major_tma_aligned_tensor` for Blackwell deepgemm in EpMoE](../sources/prs/sglang/PR-8955.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[BugFix] Fix Hopper TMA lowering without warp specialization](../sources/prs/tilelang/PR-1840.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add T.copy_cluster to support TMA multicast and SM-to-SM cluster copy](../sources/prs/tilelang/PR-1908.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[Bugfix] Enable `.shared::cta` in TMA copy paths only on CUDA 12.8+](../sources/prs/tilelang/PR-2087.md), [[TMA] Support FP4 TensorMap TMA copies](../sources/prs/tilelang/PR-2107.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[Kernel] Update `cutlass_scaled_mm` to support 2d group (blockwise) scaling](../sources/prs/vllm/PR-11868.md), [Add: Support for Sparse24Bitmask Compressed Models](../sources/prs/vllm/PR-12097.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[BugFix] Illegal Memory Access in the blockwise cutlass fp8 GEMMs](../sources/prs/vllm/PR-14396.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [Fix `numel()` downcast in vllm/csrc/moe/moe_align_sum_kernels.cu +2](../sources/prs/vllm/PR-17082.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[Perf] Use upstream CUTLASS for SM90 Block FP8 kernel](../sources/prs/vllm/PR-23280.md), [[Kernel] Add topk_sigmoid kernel](../sources/prs/vllm/PR-31246.md), [Add TMA support to fused_moe_lora kernel](../sources/prs/vllm/PR-32195.md), [[Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper](../sources/prs/vllm/PR-32619.md), [[Bugfix] Fix quant RMS norm fusion for quantization with TMA-aligned scales](../sources/prs/vllm/PR-33255.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[Perf][GDN] Align TMA usage with upstream FLA](../sources/prs/vllm/PR-38981.md), [fix: clamp NaN/Inf in topk_softmax to prevent duplicate expert IDs](../sources/prs/vllm/PR-39391.md), [mbarrier (Memory Barrier Primitives)](../wiki/hardware/mbarrier.md), [Tensor Memory Accelerator (TMA)](../wiki/hardware/tma.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [NVFP4 GEMM — GPU Mode Problem 2 Contract](../wiki/kernels/nvfp4-gemm.md), [CuTe DSL for Blackwell](../wiki/languages/cute-dsl.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Pipeline Stalls](../wiki/patterns/pipeline-stalls.md), [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md), [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md), [Shared Memory Swizzling](../wiki/techniques/swizzling.md) | +| `tmem` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax CUTLASS Tutorial: GEMM Kernels Using Tensor Memory for Blackwell](../sources/blogs/colfax-cutlass-blackwell.md), [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [FlashAttention-4: Algorithm and Kernel Co-design for Blackwell GPUs](../sources/docs/flash-attention-4.md), [NVIDIA Blackwell Tuning Guide](../sources/docs/nvidia-blackwell-tuning-guide.md), [NVIDIA CUDA Toolkit 13.x for Blackwell](../sources/docs/nvidia-cuda-13.md), [NVIDIA CUTLASS 4.5.0 Blackwell Sources](../sources/docs/nvidia-cutlass-blackwell.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [Triton v3.3.0 — Blackwell TCGen5/TMEM Boundary](../sources/docs/triton-3.3-blackwell.md), [Triton v3.6.0 — Incremental Blackwell Changes](../sources/docs/triton-3.6-blackwell.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [tcgen05.mma — Blackwell MMA Instruction](../wiki/hardware/tcgen05-mma.md), [Tensor Memory (TMEM)](../wiki/hardware/tmem.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [NVFP4 GEMM — GPU Mode Problem 2 Contract](../wiki/kernels/nvfp4-gemm.md), [CUDA C++ for Blackwell Kernels](../wiki/languages/cuda-cpp.md), [CuTe DSL for Blackwell](../wiki/languages/cute-dsl.md), [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md), [Register Accumulators to TMEM](../wiki/migration/register-to-tmem.md), [Migrating from wgmma to tcgen05](../wiki/migration/wgmma-to-tcgen05.md), [Register Pressure and Residency](../wiki/patterns/register-pressure.md), [Double/Multi-Buffering Patterns](../wiki/techniques/double-buffering.md), [Epilogue Fusion](../wiki/techniques/epilogue-fusion.md), [Kernel Fusion](../wiki/techniques/kernel-fusion.md), [Ping-Pong Scheduling](../wiki/techniques/ping-pong-scheduling.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md) | +| `wgmma` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Kernels](../sources/blogs/colfax-cutlass-kernels.md), [DeepGEMM — Pinned Upstream Project Summary](../sources/blogs/deepgemm.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Add swizzle layout detection and automatic merging for layout conflicts](../sources/prs/tilelang/PR-1736.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [FP8 Fine-Grained-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [Migrating from wgmma to tcgen05](../wiki/migration/wgmma-to-tcgen05.md), [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md) | diff --git a/queries/by-kernel-type.md b/queries/by-kernel-type.md index a2d3a0295..b03a4b030 100644 --- a/queries/by-kernel-type.md +++ b/queries/by-kernel-type.md @@ -4,20 +4,21 @@ | Kernel Type | Pages | |-------------|-------| -| `attention` | [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Gated Delta Networks](../sources/blogs/gated-delta-net.md), [K-Search: LLM Kernel Generation via Co-Evolving Intrinsic World Model](../sources/blogs/k-search-kernel-generation.md), [Native Sparse Attention (NSA)](../sources/blogs/nsa.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [FlashAttention-4: Hardware-Friendly Attention on Blackwell](../sources/docs/flash-attention-4.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [[TRTLLM-9798][feat] Change to use new DeepGEMM MQA sm100 kernel for MTP-3](../sources/prs/TensorRT-LLM/PR-10226.md), [[TRTLLM-10022][feat] Add hopper xqa decode support for skip softmax attention](../sources/prs/TensorRT-LLM/PR-10264.md), [[None][feat] Remove non flash attetnion style fmha_v2 kernel for hopper](../sources/prs/TensorRT-LLM/PR-11381.md), [[TRTLLM-11092][feat] add support for visual gen FA4 attention backend](../sources/prs/TensorRT-LLM/PR-11697.md), [[TRTLLM-11119][feat] Blackwell SageAttention, Integrate into AttentionOp API](../sources/prs/TensorRT-LLM/PR-11718.md), [[None][feat] Add fused DiT QK Norm + RoPE CUDA kernel for FLUX](../sources/prs/TensorRT-LLM/PR-11869.md), [[TRTLLM-10421][perf] Add fused cat+fp8_quantize CUDA kernel for DSA indexer](../sources/prs/TensorRT-LLM/PR-11899.md), [[None][feat] GLM 5 support and DSA MTP fixes](../sources/prs/TensorRT-LLM/PR-11990.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[TRTLLM-11285][feat] Fuse indexer wk + weights_proj into single GEMM in TF32 for DS-V3.2](../sources/prs/TensorRT-LLM/PR-12055.md), [[TRTLLM-11540][feat] Add EAGLE3 dynamic tree speculative decoding support](../sources/prs/TensorRT-LLM/PR-12062.md), [[TRTLLM-11289][feat] Integrate CuteDSL's bf16 dense GEMMs](../sources/prs/TensorRT-LLM/PR-12074.md), [[TRTLLM-10407][perf] Enable CuteDSL indexer_top_k in model](../sources/prs/TensorRT-LLM/PR-12236.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[https://nvbugs/5983390][perf] Kernel fusions in _gather_k_cache_for_chunk of Indexer in DSA](../sources/prs/TensorRT-LLM/PR-12322.md), [[None][feat] Temporally-Correlated Heuristic-guided Indexer TopK for Sparse Attention](../sources/prs/TensorRT-LLM/PR-12385.md), [[https://nvbugs/5983390][fix] Remove redundant D2H sync to optimize perf](../sources/prs/TensorRT-LLM/PR-12445.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[https://nvbugs/5983390][perf] Split MLA DSA custom op for piecewise CUDA graph capture](../sources/prs/TensorRT-LLM/PR-12503.md), [[https://nvbugs/5983390][perf] Multiple host perf optimizations for DSA part](../sources/prs/TensorRT-LLM/PR-12581.md), [[None][feat] Add triton paged attention for AutoDeploy](../sources/prs/TensorRT-LLM/PR-12642.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[TRTLLM-11485][feat] Feature rework: Add SageAttention refreshed kernels (attentionOp only)](../sources/prs/TensorRT-LLM/PR-12937.md), [[#12716][feat] Fused cross-head QK Norm + RoPE kernel for WAN](../sources/prs/TensorRT-LLM/PR-13052.md), [[TRTLLM-34871][feat] Add cute dsl FP8 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13219.md), [[None][feat] Integrate FP4 indexer for DSA on Blackwell](../sources/prs/TensorRT-LLM/PR-13340.md), [[TRTLLM-11285][perf] Force enable TF32 tensor cores for DSA indexer fused GEMM](../sources/prs/TensorRT-LLM/PR-13452.md), [[None][perf] Scheme X L2-aware dispatcher and PDL launchers for sparse-attention GVR Top-K](../sources/prs/TensorRT-LLM/PR-13477.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[TRTLLM-12128][feat] enable SageAttention for Wan/FLUX (new commits)](../sources/prs/TensorRT-LLM/PR-13570.md), [[TRTLLM-12316][feat] Integrate FP4 indexer for DSv4](../sources/prs/TensorRT-LLM/PR-13575.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[None][perf] Optimize DeepSeek-V4 compressor BF16 input](../sources/prs/TensorRT-LLM/PR-13761.md), [[None][fix] Use compressed lengths for DeepSeek-V4 indexer](../sources/prs/TensorRT-LLM/PR-13802.md), [[None][feat] Update FMHA cubins for head_dim 80](../sources/prs/TensorRT-LLM/PR-13808.md), [[TRTLLM-12503][feat] Parallel VAE independent scaling and fix arg passing](../sources/prs/TensorRT-LLM/PR-13873.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] Keep DSv4 o_a_proj as FP8, and port vLLM's fused_inv_rope_fp8_quant](../sources/prs/TensorRT-LLM/PR-13938.md), [[None][perf] Add CUDA q_b norm for DeepSeek V4](../sources/prs/TensorRT-LLM/PR-13975.md), [[None][feat] Enable 2 DSv4 perf optimizations by default](../sources/prs/TensorRT-LLM/PR-14120.md), [[None][feat] Add chunked prefill support for Gemma4 (text + vision multimodal)](../sources/prs/TensorRT-LLM/PR-14134.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][feat] DSv4: enable GVR Heuristic Top-K for compress_ratio=4](../sources/prs/TensorRT-LLM/PR-14219.md), [[None][refactor] clean up AttentionForwardArgs](../sources/prs/TensorRT-LLM/PR-14244.md), [[None][fix] Handle unset attention_dp_relax in ADP routers](../sources/prs/TensorRT-LLM/PR-14276.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [Add seqused_q in fwd / bwd and seqused_k in bwd in hopper FA.](../sources/prs/flash-attention/PR-1182.md), [Add local attention in Hopper FAv3](../sources/prs/flash-attention/PR-1233.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [Paged Attention support for FA3](../sources/prs/flash-attention/PR-1268.md), [FA3 paged attention: Readiness for Cutlass 3.6 / default value for block_table](../sources/prs/flash-attention/PR-1331.md), [Blackwell FlashAttention-BWD (v1.0)](../sources/prs/flash-attention/PR-1945.md), [[Cute,Fwd,Sm100] Support paged attention](../sources/prs/flash-attention/PR-1999.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [Add SM120 varlen attention support](../sources/prs/flash-attention/PR-2333.md), [[Fwd,Sm90] Add paged KV attention support (tma and cp.async)](../sources/prs/flash-attention/PR-2360.md), [feat: update decode attention APIs](../sources/prs/flashinfer/PR-1007.md), [misc: fix instrument code for mla profiler](../sources/prs/flashinfer/PR-1014.md), [add multi-item scoring](../sources/prs/flashinfer/PR-1015.md), [fix: add zero init for KV tiled copy](../sources/prs/flashinfer/PR-1029.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [[nvidia] Add Blackwell FMHA decode kernel from TRT-LLM](../sources/prs/flashinfer/PR-1051.md), [Fix KV chunking for POD. ](../sources/prs/flashinfer/PR-1054.md), [bugfix: temporally disable split-kv in blackwell mla](../sources/prs/flashinfer/PR-1055.md), [Parameterize prefix mask call (needed by POD-Attention)](../sources/prs/flashinfer/PR-1059.md), [bugfix: adding lse output to blackwell fmha kernels](../sources/prs/flashinfer/PR-1071.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [bugfix: fix fp8 attention kernels aot compilation issue](../sources/prs/flashinfer/PR-1087.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [hotfix: fix the blackwell fmha stream](../sources/prs/flashinfer/PR-1116.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [[feat] add unified batch attention w/ correctness tests.](../sources/prs/flashinfer/PR-1137.md), [Fix FA2 and FA3 multi-item scoring and cuda illegal memory access error](../sources/prs/flashinfer/PR-1140.md), [[feat] support block sparse attention w/ variable block sizes and head-wise sparse patterns](../sources/prs/flashinfer/PR-1177.md), [update trtllm-gen decode attention kernel launcher](../sources/prs/flashinfer/PR-1189.md), [bugfix: fix blackwell fmha hanging issue for empty kv_len](../sources/prs/flashinfer/PR-1198.md), [[feat] optimize persistent batch attention perf.](../sources/prs/flashinfer/PR-1200.md), [[fix] fix BatchAttention CTA_TILE_KV mask issue](../sources/prs/flashinfer/PR-1206.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [Bug fix: fix duplicate launch in POD](../sources/prs/flashinfer/PR-1267.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [[fix] fix integer overflow in FA2 customized_mask & add buffer overflow warning.](../sources/prs/flashinfer/PR-1290.md), [feat: Add k_scale and v_scale to persistent attention ](../sources/prs/flashinfer/PR-1322.md), [feat: Support logits_soft_cap for Persistent attn; fix kv split limit](../sources/prs/flashinfer/PR-1324.md), [Support passing kv_data_type to MultiLevelCascadeAttentionWrapper.plan()](../sources/prs/flashinfer/PR-1350.md), [Allow BatchPrefillPagedWrapper to call cudnn API](../sources/prs/flashinfer/PR-1384.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Adding FP8 benchmark on attention and matmul testing](../sources/prs/flashinfer/PR-1390.md), [benchmark: trtllm-gen mha with sink, add benchmark args](../sources/prs/flashinfer/PR-1415.md), [refactor: Sink attention AoT](../sources/prs/flashinfer/PR-1427.md), [feat: enable trtllm-gen attn speculative decoding verify by decode](../sources/prs/flashinfer/PR-1453.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [feat: integrate xqa attention backend](../sources/prs/flashinfer/PR-1503.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [bugfix: Fix Persistent kernel precision for masked output ](../sources/prs/flashinfer/PR-1533.md), [feat: Integrate TRTLLM varlen kernel for deepseek R1 prefill ](../sources/prs/flashinfer/PR-1537.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [bugfix: fix persistent attention kernel correctness on blackwell](../sources/prs/flashinfer/PR-1559.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [feat: Support for inferring out_dtype from out.dtype for TRTLLM attention kernel](../sources/prs/flashinfer/PR-1578.md), [fix: semaphoress must be at the fixed range in workspace buffer on trtllm_gen attention](../sources/prs/flashinfer/PR-1584.md), [fix: Improve TRTLLM attention kernel out_dtype unit test](../sources/prs/flashinfer/PR-1590.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: fix merge_attention_state in BatchAttention w/ gqa-group-size in Qwen family](../sources/prs/flashinfer/PR-1614.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [fix: pass workspace for trtllm-gen attention](../sources/prs/flashinfer/PR-1635.md), [fix: zero-init workspace buffer for trtllm-gen fmha](../sources/prs/flashinfer/PR-1643.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [Refactor Blackwell unit test scripts](../sources/prs/flashinfer/PR-1667.md), [feat: Add `variant.OutputTransform()` to decode kernels](../sources/prs/flashinfer/PR-1670.md), [feat: Batch-size invariant FA2 Prefill & Decode](../sources/prs/flashinfer/PR-1675.md), [[misc] add a wrapper class for attention sink jit args](../sources/prs/flashinfer/PR-1679.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [perf: Port the separate reduce kernel mode from trtllm.](../sources/prs/flashinfer/PR-1685.md), [bugfix: increase workspace to make trtllm gen attention unit test pass](../sources/prs/flashinfer/PR-1707.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [tests: xfail attention sink UT for sliding window + non causal case](../sources/prs/flashinfer/PR-1752.md), [Fix tests/test_trtllm_gen_attention.py::test_trtllm_batch_prefill, ::test_trtllm_batch_decode mismatch error](../sources/prs/flashinfer/PR-1755.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [Bugfix: Fix data hazard in persistent reduce](../sources/prs/flashinfer/PR-1826.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [Bugfix: fix o_strides in persistent kernel ](../sources/prs/flashinfer/PR-1865.md), [Tune kernel compilation parameters for https://github.com/flashinfer-ai/flashinfer/pull/1850 ](../sources/prs/flashinfer/PR-1878.md), [fix: Fix trtllm-gen prefill IMA when batch_size==1](../sources/prs/flashinfer/PR-1912.md), [MLA RoPE + quantization fused kernel: shape generalization for MHA / GQA](../sources/prs/flashinfer/PR-1924.md), [Add realistic bench for persistent kernel ](../sources/prs/flashinfer/PR-1942.md), [fix: Make attention microbenchmark correctly use page table](../sources/prs/flashinfer/PR-1976.md), [fix: Skipping attention sink Blackwell test outside of Blackwell](../sources/prs/flashinfer/PR-1978.md), [fix: correct PDL parameter handling in RopeQuantize kernel](../sources/prs/flashinfer/PR-1982.md), [minor fix for xqa](../sources/prs/flashinfer/PR-1994.md), [unittest: Add head dim 256 test cases and mark as xfail](../sources/prs/flashinfer/PR-1999.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Fix trtllm-gen attention illegal memory access](../sources/prs/flashinfer/PR-2002.md), [use scalar for kv_scale in xqa](../sources/prs/flashinfer/PR-2033.md), [Added an initial implementation of Q and KV Cache in fp8 and to use t…](../sources/prs/flashinfer/PR-2035.md), [feat: Add flashinfer.rope.rope_quantize_fp8_append_paged_kv_cache (fused RoPE + Q + KV cache, supports MLA/GQA/MHA) ](../sources/prs/flashinfer/PR-2037.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [feat: add xqa mla backend](../sources/prs/flashinfer/PR-2053.md), [misc: Add XQA decode to microbenchmark for sm90 and sm120](../sources/prs/flashinfer/PR-2055.md), [Fix: several bugs/issues with trtllm-gen attention kernels. ](../sources/prs/flashinfer/PR-2062.md), [unittest: improve the efficiency of xqa unittests](../sources/prs/flashinfer/PR-2075.md), [fix: fix test_trtllm_gen_attention when max_seq_len < page_size](../sources/prs/flashinfer/PR-2076.md), [[Feature] Support batch prefill for POD Attention](../sources/prs/flashinfer/PR-2079.md), [enable xqa fp8 output](../sources/prs/flashinfer/PR-2081.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [[DSR1] Added MLA test](../sources/prs/flashinfer/PR-2100.md), [enable xqa speculative decoding](../sources/prs/flashinfer/PR-2105.md), [feat: support more head dim in RoPE kernel](../sources/prs/flashinfer/PR-2109.md), [add tensor scale input for xqa](../sources/prs/flashinfer/PR-2110.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [feature: make the LSE returned by MLA support base 2 or e #2113](../sources/prs/flashinfer/PR-2114.md), [perf: bunch of features and optimizations for top-k (sampling + sparse attention)](../sources/prs/flashinfer/PR-2119.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [fix flaky xqa test](../sources/prs/flashinfer/PR-2126.md), [fix(trtllm): reset negative strideBatch to 0 for ragged KV layout to …](../sources/prs/flashinfer/PR-2134.md), [fix: some bugs of headDim 256 trtllm-gen fmha kernels. ](../sources/prs/flashinfer/PR-2137.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [refactor: Move mla code from decode.py to mla.py and add to documentation](../sources/prs/flashinfer/PR-2163.md), [fix: compile flags for trtllm fmha_v2 ](../sources/prs/flashinfer/PR-2175.md), [Permute page table in benchmarking](../sources/prs/flashinfer/PR-2194.md), [Fp8 attention are now part of cuDNN 9.17.1](../sources/prs/flashinfer/PR-2241.md), [feat: support non-contiguous query for trtllm-gen attention backend](../sources/prs/flashinfer/PR-2254.md), [fix: support int64 IdType for RoPE part argument in `rope_quantize_fp8_append_paged_kv_cache`](../sources/prs/flashinfer/PR-2255.md), [[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding](../sources/prs/flashinfer/PR-2265.md), [feat: add GDN Attention](../sources/prs/flashinfer/PR-2276.md), [fix: Decode benchmark's fa2_tc uses backend=fa2 in wrapper](../sources/prs/flashinfer/PR-2302.md), [Added the cudnn backend Ragged KV Cache wrapper](../sources/prs/flashinfer/PR-2352.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [fix: Fix memory bandwidth calculation in MLA benchmarks](../sources/prs/flashinfer/PR-2479.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [pick fa2 for BatchDecodeWithPagedKVCacheWrapper auto backend](../sources/prs/flashinfer/PR-2530.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [fix: allow fmha_v2_prefill_deepseek on SM121 (DGX Spark)](../sources/prs/flashinfer/PR-2559.md), [fix: guard CUTLASS FMHA against SM12x and fix fmha_v2 SM121a check](../sources/prs/flashinfer/PR-2560.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [support qk_nope_head_dim for 192 check for GLM-5](../sources/prs/flashinfer/PR-2607.md), [benchmark: Enable speculative decode microbenchmarking for paged decode](../sources/prs/flashinfer/PR-2628.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [benchmarks: Add FP8 input / BF16 output in ragged prefill benchmark](../sources/prs/flashinfer/PR-2666.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [feat: Add DiT-oriented kernels where Qk (Bmm1) type can be reinterpreted into Int8 or BFloat16](../sources/prs/flashinfer/PR-2711.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [[Spark unit test debugging] Fix for tests/attention/test_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-2750.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [feat: FP8 output support for CUTLASS MLA paged attention](../sources/prs/flashinfer/PR-2779.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [feat: Support padding tokens with seqlen=0 for rope+quant+kv cache update fusion kernel](../sources/prs/flashinfer/PR-2792.md), [[fmha-v2] Support HND and NHD paged KV cache layouts with conditional stride handling](../sources/prs/flashinfer/PR-2799.md), [[fix] Bugfix 1367: fix VariableBlockSparseAttention buffer overflow by dynamically resizing kv_lens_buffer](../sources/prs/flashinfer/PR-2802.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [[Spark unit test] Adjust tolerance for test_xqa, test_logits_processor](../sources/prs/flashinfer/PR-2828.md), [[Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D](../sources/prs/flashinfer/PR-2841.md), [[fix] bugfix 2856: Fix pre-allocated out shape check in trtllm_batch_decode_with_kv_cache_mla for q_len_per_req > 1](../sources/prs/flashinfer/PR-2876.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [test: xfail cuDNN FP8 prefill on Blackwell with CUDA <= 12.9](../sources/prs/flashinfer/PR-2963.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [cute-dsl fmha prefill (cubin integration): remove front-padding, add attention_sink, and pdl support](../sources/prs/flashinfer/PR-3181.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [Add dynamic tokens-per-page TRTLLM-GEN GQA kernels](../sources/prs/flashinfer/PR-3259.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [perf: fix the iteration bound of SWA in FA2 prefill template](../sources/prs/flashinfer/PR-714.md), [Align KV chunk size binary search with actual KV chunk splitting.](../sources/prs/flashinfer/PR-728.md), [feat: support deepseek prefill attention shape](../sources/prs/flashinfer/PR-765.md), [perf: refactor fa2 prefill template](../sources/prs/flashinfer/PR-776.md), [bugfix: fix batch prefill attention kernel unittests](../sources/prs/flashinfer/PR-781.md), [bugfix: MLA decode should multiply sm_scale by math::log2e](../sources/prs/flashinfer/PR-787.md), [fix rope logic in mla decoding](../sources/prs/flashinfer/PR-793.md), [feat: support f32 attention output in FA2 template](../sources/prs/flashinfer/PR-799.md), [feat: apply sm_scale at logits instead of q in FA2 template](../sources/prs/flashinfer/PR-801.md), [perf: memory efficient deepseek mla fused page-attention kernel](../sources/prs/flashinfer/PR-804.md), [bugfix: mla page-attention kernel for different page sizes](../sources/prs/flashinfer/PR-810.md), [feat: unlocking MLA for A100](../sources/prs/flashinfer/PR-812.md), [feat: unlock MLA attention for sm89 (L40/L40s/4090)](../sources/prs/flashinfer/PR-814.md), [bugfix: bugfix on sm89 MLA](../sources/prs/flashinfer/PR-821.md), [perf: MLA decode kernel implemented by CuTe targeted to SM80](../sources/prs/flashinfer/PR-844.md), [Add POD-Attention to FlashInfer](../sources/prs/flashinfer/PR-858.md), [perf: dynamic split-k for MLA](../sources/prs/flashinfer/PR-863.md), [bugfix: fix the behavior of MLA kernel when kv-length is 0](../sources/prs/flashinfer/PR-868.md), [Naive Support for Hopper FP8 Prefill Kernel with Per-Head Quantization](../sources/prs/flashinfer/PR-869.md), [perf: FlashAttention-3 style MLA PageAttention](../sources/prs/flashinfer/PR-887.md), [perf: fix MLA split-k performance bug](../sources/prs/flashinfer/PR-898.md), [perf: tweak the pipeline design of mla kernel](../sources/prs/flashinfer/PR-901.md), [feat: flashinfer intra-kernel profiler](../sources/prs/flashinfer/PR-913.md), [bugfix: fix potential issues of FA3 template loading nans for PageAttention](../sources/prs/flashinfer/PR-945.md), [perf: Use 2WG pipeline design for MLA implementation on Hopper](../sources/prs/flashinfer/PR-952.md), [[TVM] Added tvm binding for sampling kernel](../sources/prs/flashinfer/PR-958.md), [perf: prefetch page indices for mla kernel](../sources/prs/flashinfer/PR-991.md), [3rdparty: upgrade cutlass to 3.9](../sources/prs/flashinfer/PR-997.md), [[FlexAttention] Remove Old Constraint on lastdim strides](../sources/prs/pytorch/PR-153104.md), [[FlexAttention] explicilty create grad_q w/ strides](../sources/prs/pytorch/PR-153641.md), [[SDPA] [MPS] Fixes regression in 2.8.0 for scaled_dot_product_attention using mps](../sources/prs/pytorch/PR-164364.md), [[Flex attention] Fix flex attention head broadcast](../sources/prs/pytorch/PR-164368.md), [[flex_attention] adds support for low precision K/V inputs in compiled mode with GPU](../sources/prs/pytorch/PR-170486.md), [[cherry-pick] Fix vllm issue for flex (#170499)](../sources/prs/pytorch/PR-170555.md), [[RELEASE 2.11] Release only changes](../sources/prs/pytorch/PR-175091.md), [[MPS] Fix 2-pass SDPA memory corruption by forcing float accumulators](../sources/prs/pytorch/PR-175580.md), [[release 2.12] Apply Release only changes to 2.12 branch](../sources/prs/pytorch/PR-180470.md), [Disable kernel cutlass_mla_decode on SM103](../sources/prs/sglang/PR-10058.md), [feat: Add FP4 (E2M1) KV Cache Support with Quantization Utilities for MLA](../sources/prs/sglang/PR-10078.md), [[Feature] Add MLAProcess for DeepSeek MLA on NPU](../sources/prs/sglang/PR-10130.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [support qwen3_next blackwell](../sources/prs/sglang/PR-10403.md), [Fix cutlass moe accuracy drop caused by attention UB from DP padding mode](../sources/prs/sglang/PR-10414.md), [Enable trtllm mla prefix extend](../sources/prs/sglang/PR-10526.md), [Fuse quantize and rope in trtllm_mla MTP](../sources/prs/sglang/PR-10779.md), [[2/2] Support MHA prefill with FlashAttention 4.](../sources/prs/sglang/PR-10937.md), [[NVIDIA] FA3/FA4 Fix ](../sources/prs/sglang/PR-11606.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [Use trtllm_mla decode kernel for draft extend in speculative decoding](../sources/prs/sglang/PR-11664.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [Change bf16 to fp8 for some gemms in attention for DeepSeek ckpt v2](../sources/prs/sglang/PR-11805.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [DeepSeek-V3.2: Add Adaptive MHA Attention Pathway for Short-Sequence Prefill](../sources/prs/sglang/PR-11892.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [(1/n)support context parallel with deepseekv3.2-DSA](../sources/prs/sglang/PR-12065.md), [[Ascend] qwen optimization](../sources/prs/sglang/PR-12078.md), [[Ascend][feature] support L1+ L2 radixcache on ascend](../sources/prs/sglang/PR-12214.md), [[DeepseekV32]: use `_concat_mla_absorb_q_general` to replace `torch.cat`](../sources/prs/sglang/PR-12215.md), [[Deepseek V3.2] Enable flashmla_auto with MTP](../sources/prs/sglang/PR-12294.md), [fix seqlen bug for trtllm_mla's draft_extend](../sources/prs/sglang/PR-12295.md), [perf: trtllm mla performance minor improvements](../sources/prs/sglang/PR-12435.md), [[Ascend] Support enable-mixed-chunk in non-MLA scenarios](../sources/prs/sglang/PR-12491.md), [[DeepSeek-V3.2][NSA] Enable MHA Pathway for Short Sequence Prefill on B200 (SM100)](../sources/prs/sglang/PR-12788.md), [[Deepseek V3.2] Only skip Indexer logits computation when is_extend_without_speculative](../sources/prs/sglang/PR-12816.md), [[Deepseek V3.2] Use torch.compile to speed up torch.cat in nsa](../sources/prs/sglang/PR-13022.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Aiter fp8 kv cache](../sources/prs/sglang/PR-13147.md), [Support internvl on Blackwell (which doesn't support fa3): add `SingletonCache` support to Vision{Sdpa|Triton|Ascend}Attention](../sources/prs/sglang/PR-13151.md), [diffusion: enable fa4 for blackwell](../sources/prs/sglang/PR-13263.md), [[BugFix] fix prefixcache performance and accuracy on ascend](../sources/prs/sglang/PR-13573.md), [[DeepSeekV3.2] Enable pure TP & Partial DP Attention](../sources/prs/sglang/PR-13646.md), [fix trtllm mla spec](../sources/prs/sglang/PR-13738.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Use trtllm mha decode kernel for target_verify in speculative decoding](../sources/prs/sglang/PR-13976.md), [fix: Increase FlashInfer workspace size for Qwen3VL models](../sources/prs/sglang/PR-14173.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [Tiny use trtllm_mha as default when possible](../sources/prs/sglang/PR-14291.md), [[Fix] add block size logic for sm120 smem size](../sources/prs/sglang/PR-14311.md), [sync attention, deepseek doc](../sources/prs/sglang/PR-14335.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [[NPU] perf update with kvcache nz & w4a8 quant](../sources/prs/sglang/PR-14423.md), [Add Mistral Large 3 Eagle Support](../sources/prs/sglang/PR-14466.md), [[NPU][eagle3] support qwen eagle3 on NPU](../sources/prs/sglang/PR-14820.md), [fix: trtllm mha attention auto-selection on sm120](../sources/prs/sglang/PR-14842.md), [Fix dsv3 dp accuracy issue when using bf16-kv](../sources/prs/sglang/PR-14897.md), [Fix accuracy issue when using a16w16 mla_decode_fwd](../sources/prs/sglang/PR-14936.md), [fix(attention): Prevent trtllm_mha auto-selection with eagle3 speculative decoding](../sources/prs/sglang/PR-15127.md), [[NVIDIA] upstream FA4](../sources/prs/sglang/PR-15182.md), [[NPU]DeepSeek-V3.2 support npu mlaprolog](../sources/prs/sglang/PR-15381.md), [[diffusion] Add Sage Attention 3 Support for sm 120 (RTX5090)](../sources/prs/sglang/PR-15382.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [Fix BatchMLAPagedAttentionWrapper query/qo_inptr mismatch for EAGLE](../sources/prs/sglang/PR-15601.md), [[jit-kernel] Add CuTe DSL GDN Decode Kernel](../sources/prs/sglang/PR-15631.md), [[diffusion] model: support TurboWan2.1-T2V-1.3B/14B SLA](../sources/prs/sglang/PR-15888.md), [Bugfix for ds-vl2](../sources/prs/sglang/PR-15894.md), [Support fa4 decoding](../sources/prs/sglang/PR-16034.md), [optimize get_topk_ragged by fusing get k and k_scale triton kernel](../sources/prs/sglang/PR-16043.md), [enhance accuracy for model kimi-vl-instruct-a3b](../sources/prs/sglang/PR-16076.md), [[VLM] Adopt jit qk_norm kernel in VLM](../sources/prs/sglang/PR-16171.md), [[diffusion] Fix RuntimeError in SageAttention3 on Nvidia Blackwell with Qwen-Image](../sources/prs/sglang/PR-16335.md), [[Fix]Fix FA3 Performance in Diffusion Model ](../sources/prs/sglang/PR-16382.md), [[DeepSeek v3.2] Opt MTP decode cuda batch sizes and nsa implementation](../sources/prs/sglang/PR-16961.md), [[NPU]bugfix: fix for dsv3.2 and dsvl2](../sources/prs/sglang/PR-17007.md), [Optimize GDN decode for Qwen3 Next](../sources/prs/sglang/PR-17094.md), [[diffusion] fix: fix using upstream flash_attn on blackwell](../sources/prs/sglang/PR-17111.md), [Enable XQA for SM90 and SM120](../sources/prs/sglang/PR-17115.md), [[New Model] GLM4.7-Flash](../sources/prs/sglang/PR-17247.md), [Disable mla persistent kernel when not using fp8 kv_cache](../sources/prs/sglang/PR-17327.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [[NPU] enhance accuracy for model kimi-vl-a3b-instruct](../sources/prs/sglang/PR-17480.md), [Kernel: optimize decoding metadata in NSA multi-spec backend with fused kernels](../sources/prs/sglang/PR-17554.md), [Feat/add fi selective state update kernel call](../sources/prs/sglang/PR-18070.md), [Support Qwen3 MoE context parallel](../sources/prs/sglang/PR-18233.md), [[ROCm] Optimize Deepseek R1 on MI300X](../sources/prs/sglang/PR-18242.md), [[AMD] Support Qwen3-Coder-Next on AMD platform](../sources/prs/sglang/PR-18355.md), [feat(gdn): add FlashInfer K-last SSM layout support for GDN prefill and decode for Hopper](../sources/prs/sglang/PR-18361.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [feat: add FA4 SM90 paged KV decode support & update attention docs](../sources/prs/sglang/PR-18442.md), [Tilelang sparse decode fwd for dsv32 mi355](../sources/prs/sglang/PR-18488.md), [Fp8 prefill attn kernel integration](../sources/prs/sglang/PR-18528.md), [[AMD] Fix accuracy issue when running TP4 dsv3 model with mtp](../sources/prs/sglang/PR-18607.md), [[sgl-kernel] rebase FlashMLA 0217](../sources/prs/sglang/PR-18902.md), [Fix NSA FP8 KV cache path for both-trtllm MHA one-shot](../sources/prs/sglang/PR-18931.md), [Support skip-softmax attention](../sources/prs/sglang/PR-19089.md), [[DeepSeek-V3.2][JIT-kernel] Support nsa fuse store indexer k cache](../sources/prs/sglang/PR-19148.md), [[NVIDIA] Integrate FlashInfer decode kernel (Blackwell) for Qwen3.5](../sources/prs/sglang/PR-19150.md), [[AMD] Fix accuracy while using --enable-dp-attention](../sources/prs/sglang/PR-19247.md), [[Feature] add feature mla_ag_after_qlora for dsv3.2](../sources/prs/sglang/PR-19428.md), [[NPU] bugs fix for Deepseek models](../sources/prs/sglang/PR-19544.md), [[miles] fix for glm5](../sources/prs/sglang/PR-19634.md), [Fix MLA decode path returning unwritten (padded) rows](../sources/prs/sglang/PR-19902.md), [[AMD] Fix Tensor Memory Aliasing ](../sources/prs/sglang/PR-19928.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [[AMD] Tilelang sparse fwd for dsv32 mi355/mi300](../sources/prs/sglang/PR-19945.md), [MiniMax-M2.5 - Support dp attention, dp reduce scatter, FP4 all gather, AR fusion in prepare_attn](../sources/prs/sglang/PR-20067.md), [[AMD] Fp8 prefill integration with radix cache path for dpsk models](../sources/prs/sglang/PR-20187.md), [[AMD] Add 4-GPU test suite for MI325 runners](../sources/prs/sglang/PR-20294.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[AMD][Bug-fix] Fix gpu fault when run the test with dp-attention-enabled and max-concurrency is over 256](../sources/prs/sglang/PR-20399.md), [[AMD][AITER] Guard _use_mla_ps_kernel with self.use_mla in draft_extend_v2 paths](../sources/prs/sglang/PR-20409.md), [[GDN] Add benchmark for sglang gdn prefill](../sources/prs/sglang/PR-20428.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [[Diffusion] Clean upstream fa3 in hopper](../sources/prs/sglang/PR-20576.md), [Use Flashinfer for target_verify in GDN model for SM120](../sources/prs/sglang/PR-20604.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [ci: run Stage A CUDA tests as stage-a-test-small-1-gpu on 5090](../sources/prs/sglang/PR-20988.md), [perf: precompute FA3 scheduler_metadata to eliminate per-layer prepare_varlen_num_blocks](../sources/prs/sglang/PR-21104.md), [[Not-Merge][AMD] GLM-5 performance optimization](../sources/prs/sglang/PR-21166.md), [[Whisper] Enable CUDA graph support and timestamp for whisper model](../sources/prs/sglang/PR-21190.md), [[KDA] Support CuTeDSL KDA decode kernel](../sources/prs/sglang/PR-21203.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [[GDN] Fuse GDN kkt + solve_tril into one kernel](../sources/prs/sglang/PR-21411.md), [[Bugfix] Lazy-import CuteDSL KDA kernel to fix AMD/ROCm startup crash](../sources/prs/sglang/PR-21428.md), [fix nemotron capture for non attention layers](../sources/prs/sglang/PR-21436.md), [fix: piecewise_cuda_graph get correct qo_indptr](../sources/prs/sglang/PR-21452.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [Change default mm-attention backend from triton_attn to fa4](../sources/prs/sglang/PR-21595.md), [fix: TRT-LLM MHA CUDA illegal address with EAGLE v2 + DP attention](../sources/prs/sglang/PR-21649.md), [[XPU] Enable qwen3.5 on XPU](../sources/prs/sglang/PR-21668.md), [[DSA] Support trtllm sparse mla kernel for prefill batches ](../sources/prs/sglang/PR-21783.md), [[Bugfix] Temporarily skip TRTLLM attention on (G)B300 (SM103) to avoid high-concurrency hang](../sources/prs/sglang/PR-21906.md), [[Bugfix] Fix CUDA graph replay issues in trtllm_mla draft_extend](../sources/prs/sglang/PR-21987.md), [[NPU] enable mla prepare fused kernel only when being mla attn](../sources/prs/sglang/PR-22024.md), [[MUSA][9/N] Add FA3 attention backend support through MATE (MUSA AI Tensor Engine)](../sources/prs/sglang/PR-22051.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [Reduce unnecessary kernels and copies in the NSA indexer](../sources/prs/sglang/PR-22232.md), [[AMD][HIP] NSA: bf16 passthrough from RMSNorm to eliminate FP8 dequantization](../sources/prs/sglang/PR-22258.md), [Lazy import flash_attention_v4 to avoid loading flash_attn.cute at startup](../sources/prs/sglang/PR-22306.md), [[DSA] Hopper FP8 FlashMLA KV padding](../sources/prs/sglang/PR-22372.md), [[AMD] Use aiter CK layernorm2d for LayerNorm to reduce NSA indexer kernel launches](../sources/prs/sglang/PR-22424.md), [[Fix] Fix several bugs on DSA models](../sources/prs/sglang/PR-22430.md), [[BugFix] Resolve adaptive speculative decoding conflicts for Qwen3.5 (hybrid GDN)](../sources/prs/sglang/PR-23331.md), [[Diffusion][NPU]Add attention backends for diffusion models for Ascend NPU](../sources/prs/sglang/PR-23482.md), [[feat] Init true on policy with qwen_dense](../sources/prs/sglang/PR-23961.md), [Enable PDL for various kernels in DSV32/GLM5](../sources/prs/sglang/PR-23965.md), [[KDA] Optimize prefill kernels with diagonal and recompute fuse](../sources/prs/sglang/PR-24271.md), [Support spec v2 for FlashMLA speculative decoding](../sources/prs/sglang/PR-24640.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [Fix AMX GQA extend attention](../sources/prs/sglang/PR-25180.md), [[NSA] Avoid repeated NSA MQA logits memory queries](../sources/prs/sglang/PR-25299.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [Support draft extend cuda graph for tokenspeed_mla attention backend](../sources/prs/sglang/PR-25489.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [Use triton_attn as default vision attention on B300 (SM103)](../sources/prs/sglang/PR-25570.md), [Introduce SchedulerDPAttnAdapter to own DP-attention state](../sources/prs/sglang/PR-25611.md), [Move DP-attention adapter methods to SchedulerDPAttnAdapter](../sources/prs/sglang/PR-25612.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [feat: support flashinfer mla attention for deepseek v3](../sources/prs/sglang/PR-3550.md), [feat: support flashinfer mla with prefix cache](../sources/prs/sglang/PR-3643.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [Support overlapping two batches](../sources/prs/sglang/PR-4068.md), [avoid cudaStreamSynchronize in DeepSeekV2AttentionMLA](../sources/prs/sglang/PR-4577.md), [Fix loading KV quantization scale; Enable modelopt kv cache](../sources/prs/sglang/PR-4686.md), [[Model] Adding Qwen3 and Qwen3MoE](../sources/prs/sglang/PR-4693.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [Support (1 <= dp < tp) in the dp attention in DeepEP](../sources/prs/sglang/PR-4770.md), [Feat/support encoder model (like bert)](../sources/prs/sglang/PR-4887.md), [Support MHA with chunked prefix cache for DeepSeek chunked prefill](../sources/prs/sglang/PR-5113.md), [Blackwell Cutlass MLA kernel](../sources/prs/sglang/PR-5142.md), [feat: use fa3 mla by default on hopper](../sources/prs/sglang/PR-5210.md), [Add Speculative Decoding Eagle3 topk > 1](../sources/prs/sglang/PR-5318.md), [fix: solve cu118 issue for cutlass mla](../sources/prs/sglang/PR-5331.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[Feat] upgrade pytorch2.6](../sources/prs/sglang/PR-5417.md), [BLackwell cutlass mla: Add check for bad page size/block num combinations](../sources/prs/sglang/PR-5431.md), [Avoid computing lse in Ragged Prefill when there's no prefix.](../sources/prs/sglang/PR-5476.md), [[PP] Add pipeline parallelism](../sources/prs/sglang/PR-5724.md), [Fuse MLA set kv cache kernel](../sources/prs/sglang/PR-5748.md), [opt flashinfer mla cat](../sources/prs/sglang/PR-5822.md), [Cutlass MLA decode - fix dtype error](../sources/prs/sglang/PR-5868.md), [[Fix] Fix a bug for flashmla to run R1 model](../sources/prs/sglang/PR-5875.md), [Improve dp attention port assignment scheme](../sources/prs/sglang/PR-5889.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [Cutlass MLA: Disable split kv due to https://github.com/NVIDIA/cutlass/issues/2274](../sources/prs/sglang/PR-6101.md), [feat: add dp attention support for Qwen 2/3 MoE models, fixes #6088](../sources/prs/sglang/PR-6121.md), [Enable FlashInfer support encoder models and add head_dim padding workaround](../sources/prs/sglang/PR-6230.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [[CPU] support the case where num_attention_heads or intermediate_size is not divisible by the TP size](../sources/prs/sglang/PR-6771.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [Fix cutlass MLA gets almost zero accuracy](../sources/prs/sglang/PR-6998.md), [Tiny fix cutlass_mla_get_workspace_size stub incorrect signature](../sources/prs/sglang/PR-7057.md), [chore: upgrade sgl-kernel v0.1.8.post2](../sources/prs/sglang/PR-7186.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [feat: support compatibility between MTP and two-batch-overlap](../sources/prs/sglang/PR-7225.md), [Minor style and doc fix](../sources/prs/sglang/PR-7228.md), [Support non-contiguous query input for extend/decode attention](../sources/prs/sglang/PR-7462.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [TRTLLM-MLA FP8 path](../sources/prs/sglang/PR-8638.md), [feat: add trtllm-gen mha from direct call](../sources/prs/sglang/PR-8782.md), [Support DP attention with GPT-OSS](../sources/prs/sglang/PR-9359.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [support using fa4 on deepseek on blackwell](../sources/prs/sglang/PR-9928.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Kernel] Flash Attention 3 Support](../sources/prs/vllm/PR-12093.md), [[Core] Optimizing cross-attention `QKVParallelLinear` computation](../sources/prs/vllm/PR-12325.md), [[ROCm] Faster Custom Paged Attention kernels](../sources/prs/vllm/PR-12348.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Attention] Deepseek v3 MLA support with FP8 compute](../sources/prs/vllm/PR-12601.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [[AMD][ROCm] Enable DeepSeek model on ROCm](../sources/prs/vllm/PR-12662.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [[VLM] Add MLA with pure RoPE support for deepseek-vl2 models](../sources/prs/vllm/PR-12729.md), [[Kernel] Make rotary_embedding ops more flexible with input shape](../sources/prs/vllm/PR-12777.md), [[Attention] Use FA3 for MLA on Hopper](../sources/prs/vllm/PR-12807.md), [Expand MLA to support most types of quantization](../sources/prs/vllm/PR-13181.md), [[Bugfix] Massage MLA's usage of flash attn for RoCM](../sources/prs/vllm/PR-13310.md), [[ROCM] fix native attention function call](../sources/prs/vllm/PR-13650.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[Bugfix] Support MLA for CompressedTensorsWNA16](../sources/prs/vllm/PR-13725.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [[Kernel] FlashMLA integration](../sources/prs/vllm/PR-13747.md), [[Attention] MLA support for V1](../sources/prs/vllm/PR-13789.md), [[ROCm] Disable chunked prefill/prefix caching when running MLA on non-cuda platforms](../sources/prs/vllm/PR-13844.md), [[Attention] Flash MLA for V1](../sources/prs/vllm/PR-13867.md), [Fix mla prefill context performance](../sources/prs/vllm/PR-13897.md), [[V1] EP/TP MoE + DP Attention](../sources/prs/vllm/PR-13931.md), [[V1] Implement sliding window attention in kv_cache_manager](../sources/prs/vllm/PR-14097.md), [[v1] Add comments to the new ragged paged attention Pallas kernel](../sources/prs/vllm/PR-14155.md), [[V1][TPU] TPU multimodal model support for ragged attention](../sources/prs/vllm/PR-14158.md), [[V1][TPU] Support V1 Sampler for ragged attention](../sources/prs/vllm/PR-14227.md), [[Hardware] Update the flash attn tag to support Blackwell](../sources/prs/vllm/PR-14244.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[BugFix] MLA + V1, illegal memory access and accuracy issues](../sources/prs/vllm/PR-14253.md), [[BugFix] Fix prefix caching V0 MLA](../sources/prs/vllm/PR-14255.md), [[Attention] FlashAttn MLA](../sources/prs/vllm/PR-14258.md), [[Hardware][TPU]Enable ragged paged attention kernel and resolve recompilation issue](../sources/prs/vllm/PR-14310.md), [[Bug] Fix Attention when ignored in by quant_method](../sources/prs/vllm/PR-14313.md), [[ROCm] Enable chunked prefill/paged attention in MLA on ROCm](../sources/prs/vllm/PR-14316.md), [[Perf] Reduce MLA CPU overheads in V1](../sources/prs/vllm/PR-14384.md), [[Bugfix] DeepSeek Accuracy](../sources/prs/vllm/PR-14476.md), [[Perf] Improve MLA on V1](../sources/prs/vllm/PR-14540.md), [[Attention] Flash Attention 3 - fp8](../sources/prs/vllm/PR-14570.md), [[Kernel][CPU] CPU MLA](../sources/prs/vllm/PR-14744.md), [[Attention] MLA get rid of materialization](../sources/prs/vllm/PR-14770.md), [[Attention] Get rid of mla cache alignment](../sources/prs/vllm/PR-14842.md), [[V1][BugFix] Detect interleaved sliding window attention](../sources/prs/vllm/PR-14896.md), [[FEAT][ROCm] Integrate Paged Attention Kernel from AITER](../sources/prs/vllm/PR-15001.md), [[Bugfix] Fix incorrect qwen2.5-vl attention mask pre-computation](../sources/prs/vllm/PR-15200.md), [[Bugfix] Fix use_cascade_attention handling for Alibi-based models on vllm/v1](../sources/prs/vllm/PR-15211.md), [[Misc] Add attention mask pre-computation optimization back to Qwen2.5-VL](../sources/prs/vllm/PR-15273.md), [[BugFix] Fix nightly MLA failure (FA2 + MLA chunked prefill, i.e. V1, producing bad results)](../sources/prs/vllm/PR-15492.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [[TPU] Support sliding window and logit soft capping in the paged attention kernel for TPU.](../sources/prs/vllm/PR-15732.md), [[FEAT][ROCm]: Support AITER MLA](../sources/prs/vllm/PR-15893.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[ROCM] Add gfx950 to the custom attention archs](../sources/prs/vllm/PR-16034.md), [Add FlexAttention to V1](../sources/prs/vllm/PR-16078.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Kernel] support merge_attn_states CUDA kernel, 3x speedup](../sources/prs/vllm/PR-16173.md), [[Bug] [ROCm] Fix Llama 4 Enablement Bug on ROCm: V0 ROCmFlashAttentionImpl and Triton Fused MoE bugs](../sources/prs/vllm/PR-16198.md), [[Llama4] Enable attention temperature tuning by default for long context (>32k)](../sources/prs/vllm/PR-16439.md), [Allocate kv_cache with stride order](../sources/prs/vllm/PR-16605.md), [[MLA] Simplification to batch P/D reordering](../sources/prs/vllm/PR-16673.md), [[V1] V1 FlashInfer Attention](../sources/prs/vllm/PR-16684.md), [[torch.compile][ROCm] Fuse quantization onto attention using a torch.compile pass](../sources/prs/vllm/PR-16756.md), [[Kernel] Unified Triton kernel that doesn't distinguish between prefill + decode](../sources/prs/vllm/PR-16828.md), [Update PyTorch to 2.7.0](../sources/prs/vllm/PR-16859.md), [[Attention] FA3 decode perf improvement - single mma warp group support for head dim 128](../sources/prs/vllm/PR-16864.md), [[Bugfix] Triton FA function takes no keyword arguments](../sources/prs/vllm/PR-16902.md), [[ROCm][Kernel][V1] Enable AMD Radeon GPU Custom Paged Attention on v1](../sources/prs/vllm/PR-17004.md), [[Bugfix] Add contiguous call inside rope kernel wrapper](../sources/prs/vllm/PR-17091.md), [[ROCm][FP8][Kernel] FP8 quantization fused into Custom Paged Attention](../sources/prs/vllm/PR-17139.md), [[Bugfix] gemma[2,3] interleaved attention when sliding window is disabled](../sources/prs/vllm/PR-17180.md), [[Bugfix] Get a specific type of layer from forward context](../sources/prs/vllm/PR-17222.md), [[BugFix] Fix vllm_flash_attn install issues](../sources/prs/vllm/PR-17267.md), [[BugFix] Fix cascade attention - RuntimeError: scheduler_metadata must have shape (metadata_size)](../sources/prs/vllm/PR-17283.md), [[v1] AttentionMetadata for each layer](../sources/prs/vllm/PR-17394.md), [[v1] Pass BlockTable and KVCacheSpec to AttentionMetadataBuilders](../sources/prs/vllm/PR-17483.md), [[Attention] MLA move o_proj q_proj into cuda-graph region](../sources/prs/vllm/PR-17484.md), [[BugFix] Fix mla cpu - missing 3 required positional arguments](../sources/prs/vllm/PR-17494.md), [[FEAT][ROCm]: Support AITER MLA on V1 Engine](../sources/prs/vllm/PR-17523.md), [[Attention] MLA move rotary embedding to cuda-graph region](../sources/prs/vllm/PR-17668.md), [fix amd triton mla path](../sources/prs/vllm/PR-17871.md), [[Bugfix][ROCm] Fix AITER MLA V1](../sources/prs/vllm/PR-17880.md), [[BugFix][AMD] Compatible patch for AITER lib after 04/20](../sources/prs/vllm/PR-17912.md), [[v1] Support multiple KV cache groups in GPU model runner](../sources/prs/vllm/PR-17945.md), [[BUG] [ROCm] [MLA] Fix variable name bug due to change in variable name in PR #17483](../sources/prs/vllm/PR-17961.md), [[Bugfix][ROCm] Use `chunked_prefill_paged_decode` as fallback for V1 attention on ROCm](../sources/prs/vllm/PR-18093.md), [[Hardware][AMD] integrate aiter chunked prefill into vllm](../sources/prs/vllm/PR-18596.md), [[BugFix] FA2 MLA Accuracy Issue](../sources/prs/vllm/PR-18807.md), [[P/D] Heterogeneous TP](../sources/prs/vllm/PR-18833.md), [[Kernel] Apply torch.Tag.needs_fixed_stride_order only for torch==2.6.0](../sources/prs/vllm/PR-19346.md), [[Core] Support Local Chunked Attention for Hybrid KV Cache](../sources/prs/vllm/PR-19351.md), [[Bugfix][V1] Allow manual FlashAttention for Blackwell](../sources/prs/vllm/PR-19492.md), [[Bugfix] Enable PP with AITER+V1](../sources/prs/vllm/PR-19822.md), [Enable V1 for Hybrid SSM/Attention Models](../sources/prs/vllm/PR-20016.md), [[Attention] MLA - Flashinfer Ragged Prefill](../sources/prs/vllm/PR-20034.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [[Kernel] Optimize Prefill Attention in Unified Triton Attention Kernel](../sources/prs/vllm/PR-20308.md), [Update PyTorch to 2.8.0](../sources/prs/vllm/PR-20358.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[v1][core] Support for attention free models](../sources/prs/vllm/PR-20811.md), [[Bugfix] Voxtral on Blackwell GPUs (RTX 50 series)](../sources/prs/vllm/PR-21077.md), [[Kernel] Flashinfer MLA (trtllm-gen) decode kernel integration](../sources/prs/vllm/PR-21078.md), [[v1] Add Whisper model support (encoder-decoder)](../sources/prs/vllm/PR-21088.md), [[Attention] Optimize FlashInfer MetadataBuilder Build call](../sources/prs/vllm/PR-21137.md), [[Attention][DBO] Add support for "splitting" the CommonAttentionMetadata](../sources/prs/vllm/PR-21153.md), [[Attention] Clean up iRoPE in V1](../sources/prs/vllm/PR-21188.md), [[Kernel] Enable Hybrid Model Support in Triton Unified Attention Kernel](../sources/prs/vllm/PR-21197.md), [[v1] - Mamba1 Attention Metadata](../sources/prs/vllm/PR-21249.md), [Support encoder-only models without KV-Cache](../sources/prs/vllm/PR-21270.md), [[v1][attention] Support Hybrid Allocator + FlashInfer](../sources/prs/vllm/PR-21412.md), [Updates to Flex + VLLm integration](../sources/prs/vllm/PR-21416.md), [[V1] Fix local chunked attention always disabled](../sources/prs/vllm/PR-21419.md), [[BugFix] Fix shared storage connector load kv only load attention layer](../sources/prs/vllm/PR-21428.md), [update flashinfer to v0.2.9rc1](../sources/prs/vllm/PR-21485.md), [[Attention] Support multiple attention metadata builders per kv_cache_spec + proper local attention no hybrid kv cache fix](../sources/prs/vllm/PR-21588.md), [Override attention metadata for fast prefill in some KV sharing setups](../sources/prs/vllm/PR-21590.md), [[BugFix] Fix IMA FlashMLA full cuda-graph and DP + Update FlashMLA](../sources/prs/vllm/PR-21691.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [[Perf] Disable chunked local attention by default with llama4](../sources/prs/vllm/PR-21761.md), [[Bugfix] Check NVIDIA artifactory is accessible before using flashinfer cubin kernels](../sources/prs/vllm/PR-21893.md), [[Qwen3] Enable dual-chunk-attention support for Qwen3 models.](../sources/prs/vllm/PR-21924.md), [[NVIDIA] Support Flashinfer TRT-LLM Prefill Attention Kernel](../sources/prs/vllm/PR-22095.md), [[fix] fix correct assertion syntax error in attention utils.](../sources/prs/vllm/PR-22154.md), [Fp8 paged attention update](../sources/prs/vllm/PR-22222.md), [Support encoder_only attention for FlexAttention](../sources/prs/vllm/PR-22273.md), [Upgrade FA3 for attention sink](../sources/prs/vllm/PR-22313.md), [[Bugfix] Add proper comparison for package versions](../sources/prs/vllm/PR-22314.md), [[ROCm] Add attention sink to use_rocm_custom_paged_attention](../sources/prs/vllm/PR-22329.md), [[BugFix] Fix triton compile error in `kernel_unified_attention_2/3d` caused by attention sinks](../sources/prs/vllm/PR-22368.md), [[bugfix] Fix Llama3/4 issues caused by FlashInfer 0.2.10](../sources/prs/vllm/PR-22426.md), [[Attention] FA3 Attention Sinks Perf Boost](../sources/prs/vllm/PR-22478.md), [[Bugfix] Fix ModernBert load & Enable sliding window attention for bidirectional attention.](../sources/prs/vllm/PR-22637.md), [Support multiple attention groups for KV sharing](../sources/prs/vllm/PR-22672.md), [Force TRTLLM attention for gpt-oss on SM100](../sources/prs/vllm/PR-22678.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [fp8 kv cache support fix for torch.compile](../sources/prs/vllm/PR-22758.md), [[Bugfix gpt-oss] Fix float32 convert for flashinfer sink support](../sources/prs/vllm/PR-23016.md), [[V1] address post issues related to #20059 (part 1); cascade attention reenable by default](../sources/prs/vllm/PR-23046.md), [[Misc] Add @tdoublep as a maintainer of hybrid model and Triton-attention related code](../sources/prs/vllm/PR-23122.md), [[Log] Warning Once for Cutlass MLA ](../sources/prs/vllm/PR-23137.md), [Optimize input preparation for FlashInfer [2/N]](../sources/prs/vllm/PR-23174.md), [[Attention] Optimize make_local_attention_virtual_batches for Flash Attention](../sources/prs/vllm/PR-23185.md), [[Misc][qwen2_5_vl][torch.compile] Enable `supports_torch_compile` on generic nn.Module and demonstrate speedup on Qwen Vision model](../sources/prs/vllm/PR-23207.md), [[Core] Always use tensor cores for Flashinfer Decode Wrapper](../sources/prs/vllm/PR-23214.md), [[ROCm][Aiter] Add triton fp8 bmm kernel for mla](../sources/prs/vllm/PR-23264.md), [[Compile] Fix Compile Warning SM100 Cutlass MLA](../sources/prs/vllm/PR-23287.md), [[Attention] Allow V1 flash_attn to support cross-attention](../sources/prs/vllm/PR-23297.md), [[Bugfix] Fixing division by zero in triton_attn if query_heads/kv_heads > 16 ](../sources/prs/vllm/PR-23424.md), [[Perf] Warmup FlashInfer attention during startup](../sources/prs/vllm/PR-23439.md), [[Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-23465.md), [fix(v1/kv_cache): resolve async KV transfer bug in cascade attention](../sources/prs/vllm/PR-23485.md), [[Misc] Simplify FlashInfer attention metadata](../sources/prs/vllm/PR-23585.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[v1] Add cross-attention KV cache support for encoder-decoder models](../sources/prs/vllm/PR-23664.md), [[Core/DBO][1/N] Add Dual-Batch Overlap mechanism to VLLM](../sources/prs/vllm/PR-23693.md), [[FlashInfer] Cache hyper params in metadata builder](../sources/prs/vllm/PR-23732.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[BugFix][FlashInfer] Fix potential race condition for paged_kv_indptr_cpu](../sources/prs/vllm/PR-23737.md), [[Kernel] cuda kernels for upcoming decode context parallel feature](../sources/prs/vllm/PR-23791.md), [[Misc] add reorder_batch AttentionMetadataBuilder](../sources/prs/vllm/PR-23798.md), [Feature/vit attention unification# 23880](../sources/prs/vllm/PR-23978.md), [[Kernel] Support decode context parallelism on Blackwell with CUTLASS MLA](../sources/prs/vllm/PR-24385.md), [[Feature] Disallow FlashMLA on Blackwell](../sources/prs/vllm/PR-24521.md), [[Bug] Fix `is_flashmla_supported` Check Error](../sources/prs/vllm/PR-24774.md), [[DCP] Support Decode Context Parallel (DCP) for GQA with FlashAttention](../sources/prs/vllm/PR-24864.md), [[Bugfix][B200] Fix `cutlass_mla` hang](../sources/prs/vllm/PR-24966.md), [[Attention][DCP] Support DCP with query length > 1 (MTP) with FA3](../sources/prs/vllm/PR-25049.md), [[Bug] Fix `returned_lse` not Defined issue](../sources/prs/vllm/PR-25106.md), [[BugFix] Fix MLA assert with CUTLASS MLA](../sources/prs/vllm/PR-25478.md), [[Bugfix] [B200] cutlass_mla - ensure kv_split == 1 for batch size > 1](../sources/prs/vllm/PR-25509.md), [[Flashinfer][gpt-oss] Support FP8-qkv Flashinfer TRTLLM Sinks Attention](../sources/prs/vllm/PR-25674.md), [[Performance] Split FlashAttn attention and cache update](../sources/prs/vllm/PR-25954.md), [[Spec Decode] Enable efficient speculative decoding with FlashInfer-MLA](../sources/prs/vllm/PR-25984.md), [Move query quantization to attention layer for Flashinfer & Triton.](../sources/prs/vllm/PR-26534.md), [[Attention] Tune CUTLASS MLA num_splits](../sources/prs/vllm/PR-26846.md), [[BUGFIX][ROCM] ViT FlashAttention on ROCm (no GFX9) and contiguous on qwen3vl ROCm TORCH_SDPA](../sources/prs/vllm/PR-27190.md), [[Bugfix] Ensure calculated KV scales are applied in attention.](../sources/prs/vllm/PR-27232.md), [Prefer FlashAttention MLA as default over FlashMLA](../sources/prs/vllm/PR-27363.md), [[Misc] Make reorder batch also separate extends](../sources/prs/vllm/PR-27367.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[AMD] Use Decoupled Kernel Block Size to Support AITER MLA block_size=1](../sources/prs/vllm/PR-27715.md), [[Bug] Batch invariant: Fix flash attn MLA `RuntimeError: scheduler_metadata must have shape (metadata_size)`](../sources/prs/vllm/PR-27884.md), [Update Flashinfer from `v0.4.1` to `v0.5.2`](../sources/prs/vllm/PR-27952.md), [[FlashInfer] Avoid FlashInfer block_size 16 + head_size 256 on blackwell](../sources/prs/vllm/PR-27994.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Mamba] - Consolidate Mambas Attention Logic](../sources/prs/vllm/PR-28133.md), [fix cross attention](../sources/prs/vllm/PR-28346.md), [[ROCm] Support for Whisper v1 with Aiter Unified Attention and Aiter Flash Attention](../sources/prs/vllm/PR-28376.md), [[Bugfix] Fix SM100 gpt-oss regression due to faulty attn sink support](../sources/prs/vllm/PR-28561.md), [[Attention][Bugfix] Fix FA sink support](../sources/prs/vllm/PR-28660.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [[Model] Add support for openPangu moe model](../sources/prs/vllm/PR-28775.md), [bugfix: correct attn output with base 2 or e](../sources/prs/vllm/PR-28840.md), [[BugFix] Fix async-scheduling + FlashAttn MLA](../sources/prs/vllm/PR-28990.md), [[Feature] Batch invariant: Enable `TRITON_MLA` without prefix-caching](../sources/prs/vllm/PR-29125.md), [[Attention] Cache attention metadata builds across hybrid KV-cache groups](../sources/prs/vllm/PR-29627.md), [[Attention] Make `split_decodes_and_prefills(..., require_uniform=True)` support padding](../sources/prs/vllm/PR-29644.md), [[perf] Use direct copy (broadcast) instead of cat for k_nope/k_pe in MLA prefill](../sources/prs/vllm/PR-29710.md), [[Perf] Improve fp8 quant in mla; replace ReduceSum with ReduceScatterSum](../sources/prs/vllm/PR-29795.md), [[SpecDecode] Simplified alternative padded-speculation acceptance rate fix](../sources/prs/vllm/PR-29845.md), [[Quantization] fix: overflow with static per-tensor scaling](../sources/prs/vllm/PR-29867.md), [[BugFix] Fix DBO assert `assert B_block_table == B_q`](../sources/prs/vllm/PR-29933.md), [Add llmcompressor fp8 kv-cache quant (per-tensor and per-attn_head)](../sources/prs/vllm/PR-30141.md), [[ROCm][Bugfix] Add MLACommonMetadata to allowed attention types for speculative decoding](../sources/prs/vllm/PR-30430.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Bugfix] Pass FA version in `MultiHeadAttention`](../sources/prs/vllm/PR-30575.md), [Triton Attention: Support cross-layers blocks](../sources/prs/vllm/PR-30687.md), [OffloadingConnector: Support kernel_block_size != block_size](../sources/prs/vllm/PR-30692.md), [[Misc][LLaMa4] Compile LLaMa Vision Encoder](../sources/prs/vllm/PR-30709.md), [Update note comment for flashinfer attention warmup](../sources/prs/vllm/PR-30711.md), [[Bugfix] Fix broken ViT attention selection for Blackwell device](../sources/prs/vllm/PR-30731.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[Kernels][FI] Skip trtllm attention when num_kv_heads=1](../sources/prs/vllm/PR-30842.md), [[Bugfix] [Kernel] Triton attention kernels: mask out V blocks that fall outside sliding window](../sources/prs/vllm/PR-30887.md), [[Bugfix] Fix incorrect tiles creation for mm prefix triton attention](../sources/prs/vllm/PR-30974.md), [[Misc] Fix grammar errors in comments and messages](../sources/prs/vllm/PR-31115.md), [[perf] Integrate flashinfer concat_mla_k](../sources/prs/vllm/PR-31171.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][Hardware][AMD] Fix last_page_len calculation in AITER MLA decode](../sources/prs/vllm/PR-31282.md), [fix(rocm): add early return in get_flash_attn_version for ROCm](../sources/prs/vllm/PR-31286.md), [[Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten](../sources/prs/vllm/PR-31380.md), [fixed mypy warnings for files vllm/v1/attention with TEMPORARY workaround](../sources/prs/vllm/PR-31465.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[MISC] Add strict contiguity check for FlashInfer attention tensors](../sources/prs/vllm/PR-32008.md), [[4/N][Attention] Move MLA common to model_executor](../sources/prs/vllm/PR-32060.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [fix: Add glm4_moe_lite to MLA detection](../sources/prs/vllm/PR-32614.md), [[Bugfix][Attention] Explicitly report support for kv_cache_dtype bfloat16](../sources/prs/vllm/PR-32795.md), [[Spec Decode] Unified Parallel Drafting](../sources/prs/vllm/PR-32887.md), [[ROCm][perf] Shuffle KV cache to use paged_attention_common](../sources/prs/vllm/PR-32914.md), [[Attention] FA4 integration](../sources/prs/vllm/PR-32974.md), [[Attention] Use `has_flashinfer` helper](../sources/prs/vllm/PR-33177.md), [[Bugfix] Disable TRTLLM attention when KV transfer is enabled](../sources/prs/vllm/PR-33192.md), [[PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K]](../sources/prs/vllm/PR-33291.md), [Triton MLA perf fixes](../sources/prs/vllm/PR-33529.md), [[Perf] Disable clean_logits in deepgemm fp8_mqa_logits kernel](../sources/prs/vllm/PR-33568.md), [[Bugfix] Fix sparse MLA metadata building](../sources/prs/vllm/PR-33579.md), [[Bugfix] fix DeepSeek R1 with CUTLASS MLA Broken on B200](../sources/prs/vllm/PR-33637.md), [enable skipping of SW attention layers when using FP8 KV cache](../sources/prs/vllm/PR-33695.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [Reapply [Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-34043.md), [[Bugfix] Relax TRTLLM KV cache contiguity assertion for cross-layer layout](../sources/prs/vllm/PR-34158.md), [[Bugfix] Fix DP Attention Padding in Dummy Run](../sources/prs/vllm/PR-34187.md), [[CPU][Perf] Accelerate Attention head for s390x using vector intrinsics](../sources/prs/vllm/PR-34434.md), [[BugFix] Add support for MTP num_speculative_tokens > 1 with sparse MLA](../sources/prs/vllm/PR-34552.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [[Update] Use FlashInfer fast_decode_plan directly instead of replication](../sources/prs/vllm/PR-34687.md), [[Bugfix] Fix MLA attention crash with AWQ/GPTQ quantized models](../sources/prs/vllm/PR-34695.md), [[Attention] Use FA4 for MLA prefill](../sources/prs/vllm/PR-34732.md), [[Bugfix] Fix GDN attention crash with mixed decode/spec-decode batches](../sources/prs/vllm/PR-34871.md), [[Model Bash][DSR1] Add selective dynamic shape marking for CustomOp](../sources/prs/vllm/PR-34900.md), [[Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2](../sources/prs/vllm/PR-34917.md), [[Model Runner V2] Support attention group](../sources/prs/vllm/PR-35036.md), [[Bug][DSV3.2] Always prepare metadata for DeepGEMM Sparse Attention](../sources/prs/vllm/PR-35075.md), [[Linear Attention] fix bug for linear attention + prefix caching + reset_prefix_cache](../sources/prs/vllm/PR-35157.md), [[BUGFIX][Mamba][Qwen3.5] Zero freed SSM cache blocks on GPU](../sources/prs/vllm/PR-35219.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[Attention][Perf] Optimize cp_gather_and_upconvert_fp8_kv_cache - DeepSeek-v3.2](../sources/prs/vllm/PR-35290.md), [[Performance] Extract KV cache update op from flashinfer forward](../sources/prs/vllm/PR-35422.md), [Fix routed experts capture for hybrid models (Mamba + Attention)](../sources/prs/vllm/PR-35744.md), [[ROCm] Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5/Linear)](../sources/prs/vllm/PR-35850.md), [[Perf] Support FP8 KV cache for Flashinfer MLA Sparse](../sources/prs/vllm/PR-35891.md), [[BugFix] Fallback from FA4->FA2 for Batch Invariance](../sources/prs/vllm/PR-36059.md), [Add 320 dimension size support to MLA](../sources/prs/vllm/PR-36161.md), [[Bugfix][MLA] Add logits size budget to sparse indexer prefill chunking](../sources/prs/vllm/PR-36178.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [mla: don't update kv cache on dummy forwards](../sources/prs/vllm/PR-36282.md), [Disable cascade attention by default](../sources/prs/vllm/PR-36318.md), [feat(attention): extract KV-cache update from FlashAttentionDiffKV ba…](../sources/prs/vllm/PR-36466.md), [[Kernel] Fuse FP8 output quantization into merge_attn_states](../sources/prs/vllm/PR-36518.md), [[Bugfix][Sparse MLA] report indexer CG support properly](../sources/prs/vllm/PR-36519.md), [[ROCm] Utilize persistent MLA kernel from AITER](../sources/prs/vllm/PR-36574.md), [[Misc][Attention] Clean up unused method in `CPU_ATTN`](../sources/prs/vllm/PR-36673.md), [fix(kv-cache): increase hybrid attention grouping threshold from 1.25 to 1.5](../sources/prs/vllm/PR-36684.md), [[ROCm] Attention selector reordering](../sources/prs/vllm/PR-36702.md), [[DSV3.2][MTP] Optimize Indexer MTP handling](../sources/prs/vllm/PR-36723.md), [[ROCm] Fix KV copy methods and auto-select attention backend for ROCm](../sources/prs/vllm/PR-36845.md), [[ROCm] Validate block_size for explicitly selected attention backends](../sources/prs/vllm/PR-36846.md), [[Feat][Spec Decode] DFlash](../sources/prs/vllm/PR-36847.md), [[Feat][Bugfix] Enable additional dimension for Flashinfer MLA and fix routing dtype](../sources/prs/vllm/PR-36931.md), [[MTP][Sparse MLA] Take advantage of native MTP support in indexer when possible](../sources/prs/vllm/PR-36982.md), [[Bugfix] Fix KV scales inconsistency in fp8 MLA & FlashInfer kv_cache_dtype "auto" leading to gibberish](../sources/prs/vllm/PR-37054.md), [[Bugfix] Disable cross-layer KV cache for MLA attention backends](../sources/prs/vllm/PR-37090.md), [[Benchmark] Improvements to attention benchmark script](../sources/prs/vllm/PR-37115.md), [[XPU] support MLA model on Intel GPU](../sources/prs/vllm/PR-37143.md), [[Misc] Add `float16` to `CacheDType`](../sources/prs/vllm/PR-37199.md), [[ROCM][Bugfix] Use correct stride in cp_mha_gather_cache_kernel for hybrid model (#37228)](../sources/prs/vllm/PR-37228.md), [[Perf] Set Flashinfer sparse MLA as default backend for FP8 kv cache](../sources/prs/vllm/PR-37252.md), [[Attention] Support distinguishing between short extends and decodes](../sources/prs/vllm/PR-37303.md), [Add nvfp4 support to reshape_and_cache_flash](../sources/prs/vllm/PR-37332.md), [[Model Runner V2] fix draft attention metadata generation](../sources/prs/vllm/PR-37364.md), [[torch.compile] Refactor Attention Quant Fusion Pass and Remove Boilerplate](../sources/prs/vllm/PR-37373.md), [[Perf][Kernel] Persistent TopK scheduler: unified CUDAGraph-safe kernel with dynamic per-row dispatch - DeepSeek-V3.2 DSA decode](../sources/prs/vllm/PR-37421.md), [[BugFix] Allow qk_nope_head_dim=192 in FlashInfer MLA backend checks](../sources/prs/vllm/PR-37475.md), [[Performance] Remove unnecessary zero-fill of MLA decode output tensor in Aiter backend](../sources/prs/vllm/PR-37539.md), [[Bugfix][ROCm] Fix lru_cache on paged_mqa_logits_module](../sources/prs/vllm/PR-37547.md), [[Bugfix] Disable --calculate-kv-scales for hybrid GDN/Mamba+Attention…](../sources/prs/vllm/PR-37565.md), [[ROCm][Bugfix] fix cache block size mismatch for aiter unified attention](../sources/prs/vllm/PR-37606.md), [[NIXL][BUG] Fix Triton heterogeneous TP](../sources/prs/vllm/PR-37940.md), [[Perf] FP8 FlashInfer Attn for ViT](../sources/prs/vllm/PR-38065.md), [[Model Runner V2] Rebuild attention metadata before eagle decode full…](../sources/prs/vllm/PR-38311.md), [[GDN] Eliminate GPU->CPU sync in prepare_chunk_indices during prefill](../sources/prs/vllm/PR-38361.md), [[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity](../sources/prs/vllm/PR-38479.md), [[Bugfix][MLA] Change default SM100 MLA prefill backend back to TRT-LLM](../sources/prs/vllm/PR-38562.md), [[ROCm] Fix aiter persistent mode mla with q/o nhead<16 for kimi-k2.5 tp8](../sources/prs/vllm/PR-38615.md), [Fix MLA runs when use_inductor_graph_partition=True](../sources/prs/vllm/PR-38631.md), [[FA4] Update flash-attention to latest upstream FA4](../sources/prs/vllm/PR-38690.md), [[Bugfix] Restrict TRTLLM attention to SM100, fixing GB300 (SM103) hang](../sources/prs/vllm/PR-38730.md), [[Bugfix] Fix test mocks after SM100 restriction in #38730](../sources/prs/vllm/PR-38791.md), [[Perf] Reduce H2D pageable memory copies](../sources/prs/vllm/PR-38794.md), [[FlashAttention] Symlink FA4 instead of copying when using `VLLM_FLASH_ATTN_SRC_DIR`](../sources/prs/vllm/PR-38814.md), [[Attention][MLA] Re-enable FA4 as default MLA prefill backend](../sources/prs/vllm/PR-38819.md), [[Attention] relax the head dim 512 and paged kv for sm90+FA4](../sources/prs/vllm/PR-38835.md), [[Refactor] Improve indexer decode path metadata preparation](../sources/prs/vllm/PR-38865.md), [[Bugfix] Fix broken explicit unquantized kv cache dtype support](../sources/prs/vllm/PR-38922.md), [[Quantization] - Layerwise reloading of Attention/KV quantized models](../sources/prs/vllm/PR-38995.md), [[Bugfix] Fix FlashInfer crash with kv_cache_dtype_skip_layers](../sources/prs/vllm/PR-39002.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [[ROCm] Align AiterFlashAttentionImpl attn_type check with backend](../sources/prs/vllm/PR-39119.md), [[Bug] Fix rocm sparse attn indexer issue](../sources/prs/vllm/PR-39225.md), [[Model Runner V2] Fix flex attention kv blocks calculation issue](../sources/prs/vllm/PR-39353.md), [[MLA] Optimize mla indexer prepare uniform decode for MTP > 1](../sources/prs/vllm/PR-39458.md), [[Bugfix] Fix tensor shape mismatch in sparse attention with speculative decoding](../sources/prs/vllm/PR-39542.md), [[XPU] properly handle q_descale on XPU as quant query input not supported](../sources/prs/vllm/PR-39676.md), [[Bugfix] Fix mismatch between global and local attention heads in tensor-parallel mode for param2moe model](../sources/prs/vllm/PR-39707.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[Bugfix] add support for 'num_attention_groups' in ModelArchConfigConvertorBase for Step3p5](../sources/prs/vllm/PR-39796.md), [[Attention] use diff kv backend for mimo v2 flash](../sources/prs/vllm/PR-40045.md), [Add nvfp4 kv cache support](../sources/prs/vllm/PR-40177.md), [[Attention][TurboQuant] Share dequant buffers, eliminate float16_copy](../sources/prs/vllm/PR-40941.md), [[Bugfix][Hybrid][NemotronH] Fix mamba_cache_mode=all + speculative decoding crash](../sources/prs/vllm/PR-41233.md), [[DSv4] Improved fused Indexer Q quant kernel](../sources/prs/vllm/PR-41428.md), [fix: remove unused norm for dpskv4](../sources/prs/vllm/PR-41710.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[feat] Add FP8 per-tensor Q scale support to Triton attention backend](../sources/prs/vllm/PR-42080.md), [[Bugfix] Fix TRTLLM ragged MLA prefill workspace warmup](../sources/prs/vllm/PR-42112.md), [[DSv4] Improved dequant gather K cache kernel](../sources/prs/vllm/PR-42236.md), [[Bugfix] mamba: run single-token extends as decodes](../sources/prs/vllm/PR-42430.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [[CPU] Add fused GDN support for AMX CPU platform](../sources/prs/vllm/PR-42707.md), [[CPU] Specify required KV cache layout for CPU attention backend](../sources/prs/vllm/PR-42740.md), [[Refactor] Remove dead cuda kernels](../sources/prs/vllm/PR-42767.md), [[ROCm] [Bugfix] Fix DeepSeek V4 Functionality and Accuracy](../sources/prs/vllm/PR-42810.md), [[Perf] Add do_not_specialize in fused FP8 RoPE kernel](../sources/prs/vllm/PR-42849.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [add cutedsl dsv4 indexer fp8 kernel](../sources/prs/vllm/PR-42899.md), [[XPU] update xpu graph usage](../sources/prs/vllm/PR-43043.md), [[Model Refactoring] Move deepseek_v4_ops to models/deepseek_v4 [3/N]](../sources/prs/vllm/PR-43073.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [Native Sparse Attention (NSA)](../wiki/kernels/nsa.md), [Sparse MLA (DeepSeek V3.2)](../wiki/kernels/sparse-mla.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md) | -| `batched-gemv` | [Twelve Attempts at NVFP4 Batched GEMV](../sources/blogs/amandeep-nvfp4-attempts.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md) | -| `decode` | [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [[TRTLLM-10022][feat] Add hopper xqa decode support for skip softmax attention](../sources/prs/TensorRT-LLM/PR-10264.md), [[https://nvbugs/5669671][fix] Support GuidedDecoder with sharded logits (pick #10698)](../sources/prs/TensorRT-LLM/PR-10742.md), [[TRTLLM-10407][feat] Integrate CuTE DSL top-k kernel for Blackwell](../sources/prs/TensorRT-LLM/PR-11900.md), [[TRTLLM-11540][feat] Add EAGLE3 dynamic tree speculative decoding support](../sources/prs/TensorRT-LLM/PR-12062.md), [[None][feat] Temporally-Correlated Heuristic-guided Indexer TopK for Sparse Attention](../sources/prs/TensorRT-LLM/PR-12385.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[None][feat] Add PDL support to CuTE DSL top-k kernels](../sources/prs/TensorRT-LLM/PR-12506.md), [[None][feat] Optimize causal_conv1d prefill and decode kernels](../sources/prs/TensorRT-LLM/PR-13103.md), [[TRTLLM-34871][feat] Add cute dsl FP8 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13219.md), [[None][perf] Scheme X L2-aware dispatcher and PDL launchers for sparse-attention GVR Top-K](../sources/prs/TensorRT-LLM/PR-13477.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] DSv4: enable GVR Heuristic Top-K for compress_ratio=4](../sources/prs/TensorRT-LLM/PR-14219.md), [feat: update decode attention APIs](../sources/prs/flashinfer/PR-1007.md), [bugfix: import wrapper of mla decode](../sources/prs/flashinfer/PR-1013.md), [add multi-item scoring](../sources/prs/flashinfer/PR-1015.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [[nvidia] Add Blackwell FMHA decode kernel from TRT-LLM](../sources/prs/flashinfer/PR-1051.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [update trtllm-gen decode attention kernel launcher](../sources/prs/flashinfer/PR-1189.md), [Enable cudnn decode and add tests for the cudnn decode kernel](../sources/prs/flashinfer/PR-1221.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [feat: enable trtllm-gen mla MTP](../sources/prs/flashinfer/PR-1258.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [refactor: Improved metainfo for trtllm-gen fmha](../sources/prs/flashinfer/PR-1292.md), [test qkvo quantization not equal to 1.](../sources/prs/flashinfer/PR-1314.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [fix: fix trtllm-gen mla error on new interface](../sources/prs/flashinfer/PR-1348.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Add Mxfp4 trtllm-gen moe unit tests](../sources/prs/flashinfer/PR-1399.md), [benchmark: trtllm-gen mha with sink, add benchmark args](../sources/prs/flashinfer/PR-1415.md), [fix: remote redundant zero_init from trtllm-gen attn](../sources/prs/flashinfer/PR-1444.md), [feat: enable trtllm-gen attn speculative decoding verify by decode](../sources/prs/flashinfer/PR-1453.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [feat: Support for inferring out_dtype from out.dtype for TRTLLM attention kernel](../sources/prs/flashinfer/PR-1578.md), [fix: Improve TRTLLM attention kernel out_dtype unit test](../sources/prs/flashinfer/PR-1590.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [fix: pass workspace for trtllm-gen attention](../sources/prs/flashinfer/PR-1635.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [feat: Add `variant.OutputTransform()` to decode kernels](../sources/prs/flashinfer/PR-1670.md), [feat: Batch-size invariant FA2 Prefill & Decode](../sources/prs/flashinfer/PR-1675.md), [feat: port fast_decode_plan from sgl](../sources/prs/flashinfer/PR-1745.md), [Fix tests/test_trtllm_gen_attention.py::test_trtllm_batch_prefill, ::test_trtllm_batch_decode mismatch error](../sources/prs/flashinfer/PR-1755.md), [fix: should pass global_override_indptr_cpu in fast_decode_plan param list](../sources/prs/flashinfer/PR-1757.md), [Waive / disable test_mla_decode_kernel.py::test_mla_decode_kernel for not sm80 ](../sources/prs/flashinfer/PR-1771.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Fix trtllm-gen attention illegal memory access](../sources/prs/flashinfer/PR-2002.md), [use scalar for kv_scale in xqa](../sources/prs/flashinfer/PR-2033.md), [feat: add xqa mla backend](../sources/prs/flashinfer/PR-2053.md), [misc: Add XQA decode to microbenchmark for sm90 and sm120](../sources/prs/flashinfer/PR-2055.md), [unittest: improve the efficiency of xqa unittests](../sources/prs/flashinfer/PR-2075.md), [[Feature] Support batch prefill for POD Attention](../sources/prs/flashinfer/PR-2079.md), [enable xqa fp8 output](../sources/prs/flashinfer/PR-2081.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [enable xqa speculative decoding](../sources/prs/flashinfer/PR-2105.md), [add tensor scale input for xqa](../sources/prs/flashinfer/PR-2110.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [refactor: Move mla code from decode.py to mla.py and add to documentation](../sources/prs/flashinfer/PR-2163.md), [[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding](../sources/prs/flashinfer/PR-2265.md), [fix: Decode benchmark's fa2_tc uses backend=fa2 in wrapper](../sources/prs/flashinfer/PR-2302.md), [feat: [Qwen3-Next] Add Cute DSL GDN decode kernel and tests](../sources/prs/flashinfer/PR-2370.md), [fix: ensure each CTA processes full numHeadsQPerKv for trtllm decode kernel](../sources/prs/flashinfer/PR-2380.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [perf: improve gdn decode cute-dsl kernels](../sources/prs/flashinfer/PR-2405.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [Ameyn/gdn decode cutedsl kernel](../sources/prs/flashinfer/PR-2498.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [Feat/gdn decode pooled](../sources/prs/flashinfer/PR-2521.md), [pick fa2 for BatchDecodeWithPagedKVCacheWrapper auto backend](../sources/prs/flashinfer/PR-2530.md), [Perf: Optimize GDN decode pretranspose kernel for all batch sizes](../sources/prs/flashinfer/PR-2588.md), [Ameyn/gdn bf16 tolerance parallel reduction](../sources/prs/flashinfer/PR-2610.md), [perf(gdn): optimize MTP kernel with ILP rows and SMEM v caching](../sources/prs/flashinfer/PR-2618.md), [feat: add pool+indices support to gated_delta_rule_decode_pretranspose (bf16 path) ](../sources/prs/flashinfer/PR-2619.md), [benchmark: Enable speculative decode microbenchmarking for paged decode](../sources/prs/flashinfer/PR-2628.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [feat(gdn): add BF16 state kernel with MTP support beyond T>4 with intermediate caching.](../sources/prs/flashinfer/PR-2679.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [[gdn] support non-contiguous state for decoding](../sources/prs/flashinfer/PR-2727.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [[fix] Bugfix 1367: fix VariableBlockSparseAttention buffer overflow by dynamically resizing kv_lens_buffer](../sources/prs/flashinfer/PR-2802.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [feat(gdn): add padding index guard for bf16 decode kernel](../sources/prs/flashinfer/PR-2810.md), [[Fmha] Sparse MLA decode kernel selection heuristics](../sources/prs/flashinfer/PR-2836.md), [perf: Optimize GDN MTP decode kernel (v15) — eliminate ilp=1 fallback…](../sources/prs/flashinfer/PR-2842.md), [read real strides for kv and block scale](../sources/prs/flashinfer/PR-2844.md), [[fix] bugfix 2856: Fix pre-allocated out shape check in trtllm_batch_decode_with_kv_cache_mla for q_len_per_req > 1](../sources/prs/flashinfer/PR-2876.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [perf: Optimize CUTLASS MoE helper kernels for small-batch decode workloads](../sources/prs/flashinfer/PR-3014.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [Ameyn/gdn bf16 dispatcher and 4d pool](../sources/prs/flashinfer/PR-3268.md), [feat: support deepseek prefill attention shape](../sources/prs/flashinfer/PR-765.md), [bugfix: MLA decode should multiply sm_scale by math::log2e](../sources/prs/flashinfer/PR-787.md), [fix rope logic in mla decoding](../sources/prs/flashinfer/PR-793.md), [feat: apply sm_scale at logits instead of q in FA2 template](../sources/prs/flashinfer/PR-801.md), [perf: MLA decode kernel implemented by CuTe targeted to SM80](../sources/prs/flashinfer/PR-844.md), [Add POD-Attention to FlashInfer](../sources/prs/flashinfer/PR-858.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [Disable kernel cutlass_mla_decode on SM103](../sources/prs/sglang/PR-10058.md), [Use trtllm_mla decode kernel for draft extend in speculative decoding](../sources/prs/sglang/PR-11664.md), [Use trtllm mha decode kernel for target_verify in speculative decoding](../sources/prs/sglang/PR-13976.md), [Fix accuracy issue when using a16w16 mla_decode_fwd](../sources/prs/sglang/PR-14936.md), [[jit-kernel] Add CuTe DSL GDN Decode Kernel](../sources/prs/sglang/PR-15631.md), [[DeepSeek v3.2] Opt MTP decode cuda batch sizes and nsa implementation](../sources/prs/sglang/PR-16961.md), [Optimize GDN decode for Qwen3 Next](../sources/prs/sglang/PR-17094.md), [feat(gdn): add FlashInfer K-last SSM layout support for GDN prefill and decode for Hopper](../sources/prs/sglang/PR-18361.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [feat: add FA4 SM90 paged KV decode support & update attention docs](../sources/prs/sglang/PR-18442.md), [Tilelang sparse decode fwd for dsv32 mi355](../sources/prs/sglang/PR-18488.md), [[NVIDIA] Integrate FlashInfer decode kernel (Blackwell) for Qwen3.5](../sources/prs/sglang/PR-19150.md), [Fix MLA decode path returning unwritten (padded) rows](../sources/prs/sglang/PR-19902.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [[Kernel] Fuse temperature + softmax in sampling for decode speedup](../sources/prs/sglang/PR-20501.md), [[KDA] Support CuTeDSL KDA decode kernel](../sources/prs/sglang/PR-21203.md), [ [GDN] Remove FlashInfer GDN decode + no_buffer guard and default to FlashInfer on SM100+ ](../sources/prs/sglang/PR-21861.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [Introduce SchedulerDPAttnAdapter to own DP-attention state](../sources/prs/sglang/PR-25611.md), [Move DP-attention adapter methods to SchedulerDPAttnAdapter](../sources/prs/sglang/PR-25612.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [Add optimized native kernels in sgl-kernel](../sources/prs/sglang/PR-5150.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[PD] Fix dynamic port support and MLA buffer for Mooncake](../sources/prs/sglang/PR-5415.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Cutlass MLA decode - fix dtype error](../sources/prs/sglang/PR-5868.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [Support non-contiguous query input for extend/decode attention](../sources/prs/sglang/PR-7462.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [[Kernel][CPU] CPU MLA](../sources/prs/vllm/PR-14744.md), [[FEAT][ROCm] Integrate Fused MoE Kernels from AITER](../sources/prs/vllm/PR-14967.md), [[Bugfix] Fix incorrect qwen2.5-vl attention mask pre-computation](../sources/prs/vllm/PR-15200.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Kernel] Unified Triton kernel that doesn't distinguish between prefill + decode](../sources/prs/vllm/PR-16828.md), [[Attention] FA3 decode perf improvement - single mma warp group support for head dim 128](../sources/prs/vllm/PR-16864.md), [[ROCm][Kernel][V1] Enable AMD Radeon GPU Custom Paged Attention on v1](../sources/prs/vllm/PR-17004.md), [[Misc][ROCm] Exclude `cutlass_mla_decode` for ROCm build](../sources/prs/vllm/PR-17289.md), [[v1] AttentionMetadata for each layer](../sources/prs/vllm/PR-17394.md), [[Bugfix][ROCm] Use `chunked_prefill_paged_decode` as fallback for V1 attention on ROCm](../sources/prs/vllm/PR-18093.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[Kernel] Flashinfer MLA (trtllm-gen) decode kernel integration](../sources/prs/vllm/PR-21078.md), [[v1] Add Whisper model support (encoder-decoder)](../sources/prs/vllm/PR-21088.md), [Support encoder-only models without KV-Cache](../sources/prs/vllm/PR-21270.md), [[v1][attention] Support Hybrid Allocator + FlashInfer](../sources/prs/vllm/PR-21412.md), [[Attention] Support multiple attention metadata builders per kv_cache_spec + proper local attention no hybrid kv cache fix](../sources/prs/vllm/PR-21588.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [[NVIDIA] Support Flashinfer TRT-LLM Prefill Attention Kernel](../sources/prs/vllm/PR-22095.md), [[Bugfix] Add proper comparison for package versions](../sources/prs/vllm/PR-22314.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [[Core] Always use tensor cores for Flashinfer Decode Wrapper](../sources/prs/vllm/PR-23214.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[v1] Add cross-attention KV cache support for encoder-decoder models](../sources/prs/vllm/PR-23664.md), [[Core/DBO][1/N] Add Dual-Batch Overlap mechanism to VLLM](../sources/prs/vllm/PR-23693.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[Kernel] cuda kernels for upcoming decode context parallel feature](../sources/prs/vllm/PR-23791.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Kernel] Support decode context parallelism on Blackwell with CUTLASS MLA](../sources/prs/vllm/PR-24385.md), [[DCP] Support Decode Context Parallel (DCP) for GQA with FlashAttention](../sources/prs/vllm/PR-24864.md), [[Attention][DCP] Support DCP with query length > 1 (MTP) with FA3](../sources/prs/vllm/PR-25049.md), [[Performance] Split FlashAttn attention and cache update](../sources/prs/vllm/PR-25954.md), [[Spec Decode] Enable efficient speculative decoding with FlashInfer-MLA](../sources/prs/vllm/PR-25984.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Attention] Make `split_decodes_and_prefills(..., require_uniform=True)` support padding](../sources/prs/vllm/PR-29644.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[SpecDecode] Simplified alternative padded-speculation acceptance rate fix](../sources/prs/vllm/PR-29845.md), [[BugFix] Fix DBO assert `assert B_block_table == B_q`](../sources/prs/vllm/PR-29933.md), [[ROCm] add fallback for aiter fp8 decode mla](../sources/prs/vllm/PR-30005.md), [[ROCm][Bugfix] Add MLACommonMetadata to allowed attention types for speculative decoding](../sources/prs/vllm/PR-30430.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Bugfix][Hardware][AMD] Fix last_page_len calculation in AITER MLA decode](../sources/prs/vllm/PR-31282.md), [[Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten](../sources/prs/vllm/PR-31380.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[4/N][Attention] Move MLA common to model_executor](../sources/prs/vllm/PR-32060.md), [[Spec Decode] Unified Parallel Drafting](../sources/prs/vllm/PR-32887.md), [Triton MLA perf fixes](../sources/prs/vllm/PR-33529.md), [fix(cpu): fix mla_decode compilation on x86 without AVX512](../sources/prs/vllm/PR-34052.md), [[BugFix] Add support for MTP num_speculative_tokens > 1 with sparse MLA](../sources/prs/vllm/PR-34552.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [[Update] Use FlashInfer fast_decode_plan directly instead of replication](../sources/prs/vllm/PR-34687.md), [[Bugfix] Fix GDN attention crash with mixed decode/spec-decode batches](../sources/prs/vllm/PR-34871.md), [[Model Runner V2] Support attention group](../sources/prs/vllm/PR-35036.md), [Kimi k2.5 MLA based eagle3](../sources/prs/vllm/PR-36361.md), [[ROCm][Perf] Allow MTP lens > 1 in Sparse MLA](../sources/prs/vllm/PR-36681.md), [[ROCm] Attention selector reordering](../sources/prs/vllm/PR-36702.md), [[ROCm] Fix KV copy methods and auto-select attention backend for ROCm](../sources/prs/vllm/PR-36845.md), [[Feat][Spec Decode] DFlash](../sources/prs/vllm/PR-36847.md), [[Benchmark] Improvements to attention benchmark script](../sources/prs/vllm/PR-37115.md), [[Attention] Support distinguishing between short extends and decodes](../sources/prs/vllm/PR-37303.md), [[Model Runner V2] fix draft attention metadata generation](../sources/prs/vllm/PR-37364.md), [[Perf][Kernel] Persistent TopK scheduler: unified CUDAGraph-safe kernel with dynamic per-row dispatch - DeepSeek-V3.2 DSA decode](../sources/prs/vllm/PR-37421.md), [[Performance] Remove unnecessary zero-fill of MLA decode output tensor in Aiter backend](../sources/prs/vllm/PR-37539.md), [[Feature] Support per-draft-model MoE backend via `--speculative-config`](../sources/prs/vllm/PR-37880.md), [[ROCm][perf] fix Aiter sparse MLA with MTP>1](../sources/prs/vllm/PR-37887.md), [[Model Runner V2] Rebuild attention metadata before eagle decode full…](../sources/prs/vllm/PR-38311.md), [[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity](../sources/prs/vllm/PR-38479.md), [[XPU] Fix spec-decode UTs under tests/v1/spec_decode](../sources/prs/vllm/PR-38491.md), [[Refactor] Improve indexer decode path metadata preparation](../sources/prs/vllm/PR-38865.md), [[Bugfix][MoE] Fix 6-8% decode regression: prefer multi-stream shared expert overlap](../sources/prs/vllm/PR-38990.md), [[MLA] Optimize mla indexer prepare uniform decode for MTP > 1](../sources/prs/vllm/PR-39458.md), [[Attention][TurboQuant] Share dequant buffers, eliminate float16_copy](../sources/prs/vllm/PR-40941.md), [[Spec Decode] Add Gemma4 MTP speculative decoding support](../sources/prs/vllm/PR-41745.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[Bugfix] mamba: run single-token extends as decodes](../sources/prs/vllm/PR-42430.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [Sparse MLA (DeepSeek V3.2)](../wiki/kernels/sparse-mla.md) | -| `flash-attention` | [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashAttention-4: Hardware-Friendly Attention on Blackwell](../sources/docs/flash-attention-4.md), [[None][feat] Remove non flash attetnion style fmha_v2 kernel for hopper](../sources/prs/TensorRT-LLM/PR-11381.md), [[TRTLLM-11092][feat] add support for visual gen FA4 attention backend](../sources/prs/TensorRT-LLM/PR-11697.md), [[TRTLLM-11119][feat] Blackwell SageAttention, Integrate into AttentionOp API](../sources/prs/TensorRT-LLM/PR-11718.md), [[TRTLLM-11540][feat] Add EAGLE3 dynamic tree speculative decoding support](../sources/prs/TensorRT-LLM/PR-12062.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[None][feat] Trtllm-gen FMHA JIT support](../sources/prs/TensorRT-LLM/PR-12612.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[TRTLLM-11485][feat] Feature rework: Add SageAttention refreshed kernels (attentionOp only)](../sources/prs/TensorRT-LLM/PR-12937.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[None][feat] Update FMHA cubins for head_dim 80](../sources/prs/TensorRT-LLM/PR-13808.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] Update the logic of FMHA JIT path](../sources/prs/TensorRT-LLM/PR-14291.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [Correct divmod order in example 77 (blackwell fmha)](../sources/prs/cutlass/PR-2291.md), [Handle get_masked_trip_count for small length in fmha example](../sources/prs/cutlass/PR-2292.md), [[ex77] fix mla split; add fwd lse; add bwd varlen](../sources/prs/cutlass/PR-2366.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [fix gqa issue for blackwell fmha.py](../sources/prs/cutlass/PR-2599.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [Feat([FA4][CUTE DSL]) Add head_dim=256 support (forward + backward)](../sources/prs/flash-attention/PR-2412.md), [[hd256] Improve forward kernel with exp2 FMA emulation (3% to 9% performance gain)](../sources/prs/flash-attention/PR-2488.md), [[hd256] Add TMA paged KV support to SM100 2CTA forward kernel](../sources/prs/flash-attention/PR-2489.md), [[FA4][hd256] Backward TMA bulk-store epilogue + LSE/dpsum coalesce](../sources/prs/flash-attention/PR-2497.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [[nvidia] Add Blackwell FMHA decode kernel from TRT-LLM](../sources/prs/flashinfer/PR-1051.md), [bugfix: adding lse output to blackwell fmha kernels](../sources/prs/flashinfer/PR-1071.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [hotfix: fix the blackwell fmha stream](../sources/prs/flashinfer/PR-1116.md), [Add more logging to TRTLLM-GEN debug trace (NFC)](../sources/prs/flashinfer/PR-1158.md), [bugfix: fix invalid blackwell fmha unittests](../sources/prs/flashinfer/PR-1181.md), [update trtllm-gen decode attention kernel launcher](../sources/prs/flashinfer/PR-1189.md), [bugfix: fix blackwell fmha hanging issue for empty kv_len](../sources/prs/flashinfer/PR-1198.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [feat: enable trtllm-gen mla MTP](../sources/prs/flashinfer/PR-1258.md), [fix: update trtllm-gen fmha benchmark](../sources/prs/flashinfer/PR-1280.md), [fix multiCtasKvScratchPtr misalignment issue (new one)](../sources/prs/flashinfer/PR-1286.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [refactor: Improved metainfo for trtllm-gen fmha](../sources/prs/flashinfer/PR-1292.md), [Fix the bug of the kernel-selection heuristic in trtllm-gen](../sources/prs/flashinfer/PR-1307.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [fix: fix trtllm-gen mla error on new interface](../sources/prs/flashinfer/PR-1348.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [benchmark: trtllm-gen mha with sink, add benchmark args](../sources/prs/flashinfer/PR-1415.md), [fix: remote redundant zero_init from trtllm-gen attn](../sources/prs/flashinfer/PR-1444.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [feat: Integrate TRTLLM varlen kernel for deepseek R1 prefill ](../sources/prs/flashinfer/PR-1537.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [fix: semaphoress must be at the fixed range in workspace buffer on trtllm_gen attention](../sources/prs/flashinfer/PR-1584.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: trtllm-gen fmha sm101 and sm100 compatibility](../sources/prs/flashinfer/PR-1631.md), [fix: zero-init workspace buffer for trtllm-gen fmha](../sources/prs/flashinfer/PR-1643.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [perf: Port the separate reduce kernel mode from trtllm.](../sources/prs/flashinfer/PR-1685.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [Tune kernel compilation parameters for https://github.com/flashinfer-ai/flashinfer/pull/1850 ](../sources/prs/flashinfer/PR-1878.md), [fix: Fix trtllm-gen prefill IMA when batch_size==1](../sources/prs/flashinfer/PR-1912.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [Fix: several bugs/issues with trtllm-gen attention kernels. ](../sources/prs/flashinfer/PR-2062.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [fix(trtllm): reset negative strideBatch to 0 for ragged KV layout to …](../sources/prs/flashinfer/PR-2134.md), [fix: some bugs of headDim 256 trtllm-gen fmha kernels. ](../sources/prs/flashinfer/PR-2137.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [fix: compile flags for trtllm fmha_v2 ](../sources/prs/flashinfer/PR-2175.md), [feat: support non-contiguous query for trtllm-gen attention backend](../sources/prs/flashinfer/PR-2254.md), [[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding](../sources/prs/flashinfer/PR-2265.md), [fix: ensure each CTA processes full numHeadsQPerKv for trtllm decode kernel](../sources/prs/flashinfer/PR-2380.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [fix: allow fmha_v2_prefill_deepseek on SM121 (DGX Spark)](../sources/prs/flashinfer/PR-2559.md), [fix: guard CUTLASS FMHA against SM12x and fix fmha_v2 SM121a check](../sources/prs/flashinfer/PR-2560.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [feat: Add DiT-oriented kernels where Qk (Bmm1) type can be reinterpreted into Int8 or BFloat16](../sources/prs/flashinfer/PR-2711.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [[fmha-v2] Support HND and NHD paged KV cache layouts with conditional stride handling](../sources/prs/flashinfer/PR-2799.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [[Fmha] Sparse MLA decode kernel selection heuristics](../sources/prs/flashinfer/PR-2836.md), [[Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D](../sources/prs/flashinfer/PR-2841.md), [read real strides for kv and block scale](../sources/prs/flashinfer/PR-2844.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [cute-dsl fmha prefill (cubin integration): remove front-padding, add attention_sink, and pdl support](../sources/prs/flashinfer/PR-3181.md), [Add dynamic tokens-per-page TRTLLM-GEN GQA kernels](../sources/prs/flashinfer/PR-3259.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [Update trtllm FMHA cubins](../sources/prs/flashinfer/PR-3317.md), [[flex_attention] adds support for low precision K/V inputs in compiled mode with GPU](../sources/prs/pytorch/PR-170486.md), [[RELEASE 2.11] Release only changes](../sources/prs/pytorch/PR-175091.md), [[release 2.12] Apply Release only changes to 2.12 branch](../sources/prs/pytorch/PR-180470.md), [[NVIDIA] FA3/FA4 Fix ](../sources/prs/sglang/PR-11606.md), [Tiny use trtllm_mha as default when possible](../sources/prs/sglang/PR-14291.md), [[NVIDIA] upstream FA4](../sources/prs/sglang/PR-15182.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [feat: add FA4 SM90 paged KV decode support & update attention docs](../sources/prs/sglang/PR-18442.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Lazy import flash_attention_v4 to avoid loading flash_attn.cute at startup](../sources/prs/sglang/PR-22306.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[FA4] Update flash-attention to latest upstream FA4](../sources/prs/vllm/PR-38690.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md) | -| `fused-kernel` | [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [Fused MoE — FP8 Block-Scale Routing + Dual GEMM](../wiki/kernels/fused-moe.md), [Gated Dual GEMM (Gate-Up + SwiGLU Fusion)](../wiki/kernels/gated-dual-gemm.md) | -| `gated-delta-net` | [Gated Delta Networks](../sources/blogs/gated-delta-net.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [Tiled Flash Linear Attention (TFLA)](../sources/docs/tfla.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][fix] Update the OSS headers in derived FLA ops and AD modeling code](../sources/prs/TensorRT-LLM/PR-14281.md), [feat: add pool+indices support to gated_delta_rule_decode_pretranspose (bf16 path) ](../sources/prs/flashinfer/PR-2619.md), [feat(gdn): state checkpointing in chunk_gated_delta_rule](../sources/prs/flashinfer/PR-2908.md), [[feat] Add blackwell GDN prefill kernel](../sources/prs/flashinfer/PR-3001.md), [[XPU] Enable qwen3.5 on XPU](../sources/prs/sglang/PR-21668.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md) | -| `gated-dual-gemm` | [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [Fused MoE — FP8 Block-Scale Routing + Dual GEMM](../wiki/kernels/fused-moe.md), [Gated Dual GEMM (Gate-Up + SwiGLU Fusion)](../wiki/kernels/gated-dual-gemm.md) | -| `gemm` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Kernels](../sources/blogs/colfax-cutlass-kernels.md), [DeepGEMM — FP8 GEMM Library](../sources/blogs/deepgemm.md), [Anatomy of a Reward Hack](../sources/blogs/gpu-mode-reward-hack.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [K-Search: LLM Kernel Generation via Co-Evolving Intrinsic World Model](../sources/blogs/k-search-kernel-generation.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [NVIDIA Developer Code Samples](../sources/blogs/nvidia-code-samples.md), [simveit effective_transpose](../sources/blogs/simveit-effective-transpose.md), [simveit load_and_store](../sources/blogs/simveit-load-and-store.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [CUTLASS Cluster Launch Control (CLC) Documentation](../sources/docs/cutlass-clc-documentation.md), [Fix performance issue of m-grouped contiguous GEMMs.](../sources/prs/DeepGEMM/PR-168.md), [Fix multicast bug and optimize masked GEMM](../sources/prs/DeepGEMM/PR-193.md), [fix: use SM90ArchSpec instead of SM100ArchSpec in sm90_bf16_k_grouped_gemm](../sources/prs/DeepGEMM/PR-270.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [Performance: reducing the percentage of FFMA interleaving yields a sight performance gain, roughly 0.5%](../sources/prs/DeepGEMM/PR-42.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Use swizzling instead of padding](../sources/prs/DeepGEMM/PR-86.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[None][perf] Add more optimization options for MOE CuteDSL finalized kernel](../sources/prs/TensorRT-LLM/PR-10042.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [[None][feat] CuteDSL MOE FC1 Enhancement](../sources/prs/TensorRT-LLM/PR-10088.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [[None][feat] sm100 weight-only kernel](../sources/prs/TensorRT-LLM/PR-10190.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [[TRTLLM-9798][feat] Change to use new DeepGEMM MQA sm100 kernel for MTP-3](../sources/prs/TensorRT-LLM/PR-10226.md), [[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.](../sources/prs/TensorRT-LLM/PR-10339.md), [[None] [feat] Add test script and raster M for gather fc1 kernel](../sources/prs/TensorRT-LLM/PR-10429.md), [[TRTLLM-10276][feat] Integrate cutedsl argmax kernel](../sources/prs/TensorRT-LLM/PR-10476.md), [[None] [feat] Add densegemm backend for MoE](../sources/prs/TensorRT-LLM/PR-10479.md), [[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth](../sources/prs/TensorRT-LLM/PR-10987.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[https://nvbugs/5854860][fix] Fix cutedsl argmax on sm120](../sources/prs/TensorRT-LLM/PR-11181.md), [[None][fix] Fix int4 awq for sm120/121](../sources/prs/TensorRT-LLM/PR-11561.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[TRTLLM-10990][feat] Fuse SwiGLU and quant into shared expert](../sources/prs/TensorRT-LLM/PR-11897.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[TRTLLM-11285][feat] Fuse indexer wk + weights_proj into single GEMM in TF32 for DS-V3.2](../sources/prs/TensorRT-LLM/PR-12055.md), [[TRTLLM-11289][feat] Integrate CuteDSL's bf16 dense GEMMs](../sources/prs/TensorRT-LLM/PR-12074.md), [[None][feat] CuteDSL MOE: Add raster along M/N support for blockscaled contiguous backbone kernel](../sources/prs/TensorRT-LLM/PR-12079.md), [[None][feat] Add DWDP (Distributed Weight Data Parallelism) support for MoE inference](../sources/prs/TensorRT-LLM/PR-12136.md), [[None][feat] Minimax RMS norm optimization](../sources/prs/TensorRT-LLM/PR-12163.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[TRTLLM-10407][perf] Add cute dsl single pass multi cta cluster topk](../sources/prs/TensorRT-LLM/PR-12354.md), [[None][feat] Add Mamba2 MTP SSM cache CUDA kernel for tree-based speculative decoding](../sources/prs/TensorRT-LLM/PR-12537.md), [[TRTLLM-11585][feat] Add CUTEDSL moe backend for nemotron-h](../sources/prs/TensorRT-LLM/PR-12884.md), [[#12784][feat] AutoDeploy: Optimize DeepSeek-R1 model performance](../sources/prs/TensorRT-LLM/PR-12946.md), [[None][fix] Propagate init_load_balancer to DeepGemmFusedMoE in create_moe_backend](../sources/prs/TensorRT-LLM/PR-13207.md), [[None][feat] Integrate FP4 indexer for DSA on Blackwell](../sources/prs/TensorRT-LLM/PR-13340.md), [[TRTLLM-11285][perf] Force enable TF32 tensor cores for DSA indexer fused GEMM](../sources/prs/TensorRT-LLM/PR-13452.md), [[None][feat] Fuse FP8 1x128 quantize + UE8M0 scale pack on SM100](../sources/prs/TensorRT-LLM/PR-13628.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[https://nvbugs/6108841][fix] add hidden_dim=6144 router GEMM instantiation for GLM-5](../sources/prs/TensorRT-LLM/PR-13740.md), [[None][fix] Plumb swiglu_limit through DeepGEMM and TRTLLMGen FP8 fused MoE](../sources/prs/TensorRT-LLM/PR-13767.md), [[None][feat] Indexer topk opt](../sources/prs/TensorRT-LLM/PR-13811.md), [[None][perf] FC2 DenseGEMM autotune: split-K, swap_ab, fine-grained tuning buckets](../sources/prs/TensorRT-LLM/PR-13833.md), [[None][perf] mHC fused_hc kernel optimizations + DS-V4 entry-boundary RMSNorm fold-in](../sources/prs/TensorRT-LLM/PR-13892.md), [[None][feat] Add chunked prefill support for Gemma4 (text + vision multimodal)](../sources/prs/TensorRT-LLM/PR-14134.md), [[TRTLLM-12462][fix] Fix FP8 block scaling GEMM autotuner cache growth](../sources/prs/TensorRT-LLM/PR-14165.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][fix] Avoid dp_size x ep_size double-count in MegaMoEDeepGemm SymmBuffer](../sources/prs/TensorRT-LLM/PR-14213.md), [[None][fix] Update the OSS headers in derived FLA ops and AD modeling code](../sources/prs/TensorRT-LLM/PR-14281.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[TRTLLM-8958][feat] and [TRTLLM-8960]: create ConfigurableMoE and support TRTLLMGenFusedMoE as backend](../sources/prs/TensorRT-LLM/PR-9486.md), [[TRTLLM-9685] [feat] Add gather fc1 kernel by cuteDSL](../sources/prs/TensorRT-LLM/PR-9618.md), [[None][feat] add fp4 gemm + allreduce](../sources/prs/TensorRT-LLM/PR-9729.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [[TRTLLM-9493][feat] Add helixPostProcessNative kernel for cp_dim=2](../sources/prs/TensorRT-LLM/PR-9924.md), [Experimental Python cooperative algorithms](../sources/prs/cccl/PR-1973.md), [fix thread-reduce performance regression](../sources/prs/cccl/PR-2944.md), [Fix scan / sm90 perf regression ](../sources/prs/cccl/PR-3236.md), [Fix the vectorized loading of BlockLoad](../sources/prs/cccl/PR-3517.md), [Add b200 tunings for scan.exclusive.sum](../sources/prs/cccl/PR-3559.md), [Fix SM100 histogram tunings](../sources/prs/cccl/PR-3691.md), [Split Optimize Warp Reduce PR - CUB part](../sources/prs/cccl/PR-4716.md), [Add nondeterministic reduce that uses atomics](../sources/prs/cccl/PR-4961.md), [CUB - Add internal integer utils and tests (Split `WarpReduce` PR)](../sources/prs/cccl/PR-5314.md), [Combine `block_reduce_warp_reduction_nondeterministic.cuh` specialization with original deterministic one ](../sources/prs/cccl/PR-5408.md), [Add dynamic CUB dispatch for segmented_sort](../sources/prs/cccl/PR-6069.md), [[CUB] Use `BlockLoadToShared` in `DeviceMerge`](../sources/prs/cccl/PR-6077.md), [Fix debug section around line 390 of dispatch_topk](../sources/prs/cccl/PR-6152.md), [Split fixed-size segmented reduce dispatch header](../sources/prs/cccl/PR-6597.md), [Integrate decoupled lookahead warpspeed scan](../sources/prs/cccl/PR-6811.md), [Use integer promotion for `warp_reduce`](../sources/prs/cccl/PR-6819.md), [Implement new tuning API arch dispatching](../sources/prs/cccl/PR-7093.md), [Two-phase reduction for fixed size segmented reduction for very large segment sizes](../sources/prs/cccl/PR-7114.md), [Implement the new tuning API for deterministic (rfa) reduce dispatch](../sources/prs/cccl/PR-7346.md), [Radix-selection based `BlockTopK` specialization](../sources/prs/cccl/PR-7384.md), [Implement the new tuning API for `DeviceRleDispatch`](../sources/prs/cccl/PR-7669.md), [Optimize non fixed size segmented reduce for small segments using max_segment_size](../sources/prs/cccl/PR-7718.md), [Add env SegmentedReduce (non fixed-size overloads)](../sources/prs/cccl/PR-7795.md), [Forward policy hub from `dispatch_streaming_arg_reduce_t` to `reduce::dispatch`](../sources/prs/cccl/PR-7805.md), [Implement the new tuning API for `detail::reduce::dispatch_streaming_arg_reduce_t`](../sources/prs/cccl/PR-7807.md), [Use the new tuning API internally for `detail::transform::dispatch`](../sources/prs/cccl/PR-7810.md), [[Backport branch/3.3.x] Forward policy hub from `dispatch_streaming_arg_reduce_t` to `reduce::dispatch`](../sources/prs/cccl/PR-7814.md), [Optimized Device-to-Device Tensor Copy (`cudax`)](../sources/prs/cccl/PR-7823.md), [Implement the new tuning API for `DispatchSegmentedRadixSort`](../sources/prs/cccl/PR-7844.md), [Implement the new tuning API for `DispatchSegmentedSort`](../sources/prs/cccl/PR-7874.md), [Implement the new tuning API for `DispatchTopK`](../sources/prs/cccl/PR-7928.md), [[cuda.compute]: Fix faulty pointer arithmetic calculation in CUB dispatch](../sources/prs/cccl/PR-7940.md), [Reduce usage of `cub::DispatchReduce`](../sources/prs/cccl/PR-7944.md), [Use the new tuning API for `detail::radix_sort::dispatch`](../sources/prs/cccl/PR-7949.md), [Adds support for non-fundamental types via decomposer to `DeviceTopK` ](../sources/prs/cccl/PR-8040.md), [Optimized Device-to-Device Tensor Copy (cudax) - Transpose Case](../sources/prs/cccl/PR-8125.md), [Avoid passing uninitialized values to scan_op](../sources/prs/cccl/PR-8184.md), [[STF] Move unstable_unique from STF to generic cudax utility](../sources/prs/cccl/PR-8190.md), [Expose `max_segment_size` guarantee in cuda.compute](../sources/prs/cccl/PR-8284.md), [Port `thrust::min|max_element` to CUB](../sources/prs/cccl/PR-8291.md), [Implement the new tuning API for `DispatchSelectIf`](../sources/prs/cccl/PR-8311.md), [simplify dispatch segmented reduce to use latest dispatch and new tunings API](../sources/prs/cccl/PR-8332.md), [Apply some random warpspeed tunings](../sources/prs/cccl/PR-8352.md), [[cub]: implement utilities for policy selection](../sources/prs/cccl/PR-8355.md), [Replace `detail::merge::dispatch` by CUB's public API](../sources/prs/cccl/PR-8381.md), [[CUB] Replace `Shuffle(Up|Down|Index)` with cuda::device::warp_shuffle - RadixSort only](../sources/prs/cccl/PR-8395.md), [[thrust] Single-pass `is_partitioned` via adjacent zip_iterator](../sources/prs/cccl/PR-8427.md), [Replace `detail::merge_sort::dispatch` by CUB's public API](../sources/prs/cccl/PR-8473.md), [Replace `detail::scan::dispatch` by CUB's public API](../sources/prs/cccl/PR-8495.md), [Implement the new tuning API for `detail::batched_topk::dispatch_batched_topk`](../sources/prs/cccl/PR-8538.md), [Replace `detail::for_each::dispatch` by CUB's public API](../sources/prs/cccl/PR-8565.md), [Replace `detail::segmented_reduce::dispatch` by the public API](../sources/prs/cccl/PR-8695.md), [Use the new tuning API internally for `detail::topk::dispatch`](../sources/prs/cccl/PR-8742.md), [Use the new tuning API internally for `detail::reduce_by_key::dispatch`](../sources/prs/cccl/PR-8756.md), [Use the new tuning API internally for `detail::reduce[_nd]::dispatch[_nd]`](../sources/prs/cccl/PR-8826.md), [Fix Warpspeed scan shifted output store](../sources/prs/cccl/PR-8839.md), [[cub] Simplify arch dispatch](../sources/prs/cccl/PR-8861.md), [Use the new tuning API internally for `detail::select::dispatch` and `DeviceSelect`](../sources/prs/cccl/PR-8880.md), [[STF] Add per-handle exec_place stream resources](../sources/prs/cccl/PR-8905.md), [Use the new tuning API internally for `detail::select|three_way_partition::dispatch` and `DevicePartition`](../sources/prs/cccl/PR-8925.md), [Use the new tuning API internally for `detail::segmented_radix_sort::dispatch`](../sources/prs/cccl/PR-8927.md), [Fix segmented radix sort benchmark segment size type](../sources/prs/cccl/PR-9039.md), [[libcu++] Fix default make_shared_resource construction](../sources/prs/cccl/PR-9044.md), [Vectorize contiguous iterators in `cub::BlockLoad`/`Store`](../sources/prs/cccl/PR-9056.md), [Improve sm90 mixed dtype kernel](../sources/prs/cutlass/PR-1883.md), [Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2037.md), [Improvements for: Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2095.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Fix sm100 gemm wrong static constexpr that breaks compilation on Windows](../sources/prs/cutlass/PR-2167.md), [Fix SM90 beta=1 hang and stream-K launch errors](../sources/prs/cutlass/PR-2172.md), [Use cudaMemcpyAsync in gemm grouped with kRequiresPrecomputation sche…](../sources/prs/cutlass/PR-2256.md), [war to fix blackwell grouped groupwise hang](../sources/prs/cutlass/PR-2267.md), [hopper-blockwise-generalization-optimization](../sources/prs/cutlass/PR-2270.md), [support fp16 accmulator for sm89 fp8 mma](../sources/prs/cutlass/PR-2378.md), [DistGEMM bug fixes](../sources/prs/cutlass/PR-2713.md), [Support PDL for SM90 Array TMA GEMM](../sources/prs/cutlass/PR-2719.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [Add tutorial fp16_gemm_1](../sources/prs/cutlass/PR-2750.md), [Blockscaled Ragged Contiguous Grouped Gemm for MoEs](../sources/prs/cutlass/PR-2790.md), [[Bug Fix]Bypass launch grids for SM120 Kernel with SM90 Mainloop & SM100 TileScheduler](../sources/prs/cutlass/PR-2865.md), [[cute] Add constexpr specifier to make_tiled_copy](../sources/prs/cutlass/PR-2875.md), [new example with TMA prefetch feature targeting for DRAM latency boun…](../sources/prs/cutlass/PR-2881.md), [Fix incorrect tensor layout strides in Blackwell MMA tutorial comments](../sources/prs/cutlass/PR-2921.md), [[Cutlass gemm] Fix SM100 FP8 nosmem epilogue-fusion shape_div 'Divisibility Condition' for non-multiple-of-64 N tiles](../sources/prs/cutlass/PR-2946.md), [[Bug Fix]Set NumSplitsM to 1 when TileShapeM < 128 in sm90 fp8 blockwise scaling CollectiveMma](../sources/prs/cutlass/PR-2965.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [Replace std::min with cute::min in sm120 blockwise scaling device functions](../sources/prs/cutlass/PR-3055.md), [[Hopper CuTeDSL] Add grouped GEMM kernel example](../sources/prs/cutlass/PR-3091.md), [Support for Group GEMM in CUTLASS Profiler for GeForce and Spark](../sources/prs/cutlass/PR-3092.md), [[CLI] add cutedsl fp16 gemm tutorial from 2 to 6](../sources/prs/cutlass/PR-3106.md), [Update blackwell tutorial to be compatible with 4.5-dev version](../sources/prs/cutlass/PR-3130.md), [Small Tile N BlockScaled GEMM + Grouped GEMM on SM12x](../sources/prs/cutlass/PR-3176.md), [feat: Adding varlen support to cute-dsl sm80 bwd](../sources/prs/flash-attention/PR-1934.md), [[Cute] Block sparse support Sm100](../sources/prs/flash-attention/PR-1985.md), [[Cute,Fwd,Sm100] Support `q_stage=1` for inference](../sources/prs/flash-attention/PR-1993.md), [Add blocksparse support for bwd on blackwell](../sources/prs/flash-attention/PR-2085.md), [Fix IMA in fwd on m boundary](../sources/prs/flash-attention/PR-2091.md), [Add pack-gqa fwd support for sparse impl w/ broadcasted H dim](../sources/prs/flash-attention/PR-2098.md), [[Cute,Fwd,Sm100] distributed offset calculation for paged KV](../sources/prs/flash-attention/PR-2104.md), [[NVIDIA] Enable Jetson Thor FA4](../sources/prs/flash-attention/PR-2108.md), [[CUTE][SM90]Enable pack-gqa with broadcasted maskmods](../sources/prs/flash-attention/PR-2145.md), [[Cute][Flex]Add pack-gqa divmod](../sources/prs/flash-attention/PR-2180.md), [[Cute,Fwd,Sm100] support irregular qhead / kvhead ratios](../sources/prs/flash-attention/PR-2186.md), [[Cute,Flex,Fwd] Allow vectorized score_mod definitions](../sources/prs/flash-attention/PR-2236.md), [[Bwd,Sm120] Add SM120 backward pass support](../sources/prs/flash-attention/PR-2330.md), [Fix ZeroDivisionError in num_splits_heuristic for empty Q workloads](../sources/prs/flash-attention/PR-2515.md), [feat: ragged tensor padding kernel for blackwell kernel alignment](../sources/prs/flashinfer/PR-1025.md), [fix: top_k_mask_logits hangs on -inf inputs](../sources/prs/flashinfer/PR-1050.md), [perf: accelerate blackwell grouped gemm](../sources/prs/flashinfer/PR-1086.md), [comm: refactor and initialize `flashinfer.comm` module](../sources/prs/flashinfer/PR-1089.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [bugfix: Fix test and output shape of fp4 quantize](../sources/prs/flashinfer/PR-1114.md), [Fix pointer dtype bug in rope](../sources/prs/flashinfer/PR-1129.md), [fix: negative zero by type trait --> binary value](../sources/prs/flashinfer/PR-1136.md), [feat: nvshmem python bindings](../sources/prs/flashinfer/PR-1160.md), [Add DeepGEMM kernels](../sources/prs/flashinfer/PR-1209.md), [Fix test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-1211.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [[comm] TRT-LLM's Multi-Node NVLink All-Reduce Kernel](../sources/prs/flashinfer/PR-1213.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [Fix missing hash in the cudnn cubin path](../sources/prs/flashinfer/PR-1227.md), [bugfix: support uint8_t for vec_t class template](../sources/prs/flashinfer/PR-1234.md), [Patch fp8 cubin availability](../sources/prs/flashinfer/PR-1240.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [Reduce the JIT compilation time of gen_gemm_sm100_module](../sources/prs/flashinfer/PR-1251.md), [init add gemm fp8 using cudnn backend](../sources/prs/flashinfer/PR-1264.md), [Made AR output optional + esthetic changes](../sources/prs/flashinfer/PR-1265.md), [feat: add masked deepgemm support and benchmarking](../sources/prs/flashinfer/PR-1266.md), [Add shuffle matrix flag](../sources/prs/flashinfer/PR-1272.md), [hotfix: fix deepgemm artifactory hash](../sources/prs/flashinfer/PR-1278.md), [Unify groupwise fp8 GEMM test](../sources/prs/flashinfer/PR-1281.md), [add mm_fp4 use cudnn backend](../sources/prs/flashinfer/PR-1288.md), [Remove FAST_BUILD FLAG for MOE](../sources/prs/flashinfer/PR-1291.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [add cutlass backend for mm_fp4](../sources/prs/flashinfer/PR-1296.md), [feat: Add weight layout option for trtllm-gen fused moe](../sources/prs/flashinfer/PR-1297.md), [[Feature] SM level profiler ](../sources/prs/flashinfer/PR-1305.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [Add blockwise-scaled FP8 GEMM via TRTLLM-Gen.](../sources/prs/flashinfer/PR-1320.md), [Optimizations for TRTLLM MNNVL Allreduce](../sources/prs/flashinfer/PR-1321.md), [refactor: Improved metainfo for trtllm-gen kernels](../sources/prs/flashinfer/PR-1328.md), [feat: masked layout fp4 gemm using cute-dsl](../sources/prs/flashinfer/PR-1331.md), [add torch float4_e2m1fn_x2 check for cudnn fp4 backend](../sources/prs/flashinfer/PR-1333.md), [[Fix] remove torch 2.8 requirement for FP4 GEMM](../sources/prs/flashinfer/PR-1334.md), [Fix bench deepgemm setting](../sources/prs/flashinfer/PR-1344.md), [feature: add fp4 mm using trtllm backend](../sources/prs/flashinfer/PR-1355.md), [[fix] remove (view) transpose to keep consistent with majorness MN requirement.](../sources/prs/flashinfer/PR-1358.md), [hotfix: update mxfp4 groupwise-scaled gemm unittests](../sources/prs/flashinfer/PR-1359.md), [refactor: download trtllm gemm metadata from server](../sources/prs/flashinfer/PR-1378.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Adding FP8 benchmark on attention and matmul testing](../sources/prs/flashinfer/PR-1390.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [feature: add cutlass as bmm_fp8 backend.](../sources/prs/flashinfer/PR-1397.md), [fix shared memory alignment conflict in sampling.cuh](../sources/prs/flashinfer/PR-1402.md), [feature: enable cublas for fp4 gemm when cudnn == 9.11.1 or >= 9.13](../sources/prs/flashinfer/PR-1405.md), [Fixes for Blackwell Tests](../sources/prs/flashinfer/PR-1434.md), [bugfix: fix perf issue by using fp8 graph that can use cublaslt](../sources/prs/flashinfer/PR-1435.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [perf: add 1x4x1 cluster shape for fp8 bmm M<16 cases](../sources/prs/flashinfer/PR-1473.md), [tuner: Trtllm-gen Fp4 MoE Autotunner](../sources/prs/flashinfer/PR-1475.md), [refactor: unify autotuner for bmm_fp8](../sources/prs/flashinfer/PR-1479.md), [Add python API for masked grouped gemm](../sources/prs/flashinfer/PR-1481.md), [perf: add fast path to TopPRenormProbKernel for top_p >= 1.0, significantly boosting SGLang workloads](../sources/prs/flashinfer/PR-1483.md), [fix: update cutedsl masked moe gemm](../sources/prs/flashinfer/PR-1488.md), [Perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8](../sources/prs/flashinfer/PR-1491.md), [fix: update masked moe gemm fp4 tensor reshape](../sources/prs/flashinfer/PR-1495.md), [feat: scaling at fp4 gemm epilogue](../sources/prs/flashinfer/PR-1498.md), [fix: Replace cub Max/Min with cuda::maximum/minimum for cuda 13 compatibility](../sources/prs/flashinfer/PR-1500.md), [Add benchmark for cutedsl gemm](../sources/prs/flashinfer/PR-1502.md), [bugfix: Fix stream handling in cutedsl gemm](../sources/prs/flashinfer/PR-1509.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [refactor fp4 masked gemm cute-dsl implementation and add manual cache](../sources/prs/flashinfer/PR-1521.md), [Fix linking errors with CUDA 13](../sources/prs/flashinfer/PR-1523.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [Remove cuda-python from dependency and check at runtime](../sources/prs/flashinfer/PR-1534.md), [Add sm check for sm100 only cutlass/trtllm kernel](../sources/prs/flashinfer/PR-1535.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [bugfix: update trtllm-gen gemm kernel names](../sources/prs/flashinfer/PR-1577.md), [bugfix: Fix arg passing to TORCH_CHECK and TORCH_WARN macros](../sources/prs/flashinfer/PR-1582.md), [fix: limit the number of nvcc threads for each kernel](../sources/prs/flashinfer/PR-1589.md), [bugfix: fix the register overflow issue for topk renorm kernels on blackwell](../sources/prs/flashinfer/PR-1597.md), [feat: Enable MnnvlMemory (for alltoallv) on B200](../sources/prs/flashinfer/PR-1601.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [feat: cutlass fp4 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1609.md), [feat: cutlass fp8 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1610.md), [perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices](../sources/prs/flashinfer/PR-1615.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [test: pytest.mark.xfail on deepgemm](../sources/prs/flashinfer/PR-1636.md), [Added mx_fp4 support using the cudnn backend](../sources/prs/flashinfer/PR-1644.md), [Refactor Blackwell unit test scripts](../sources/prs/flashinfer/PR-1667.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [Support output signals for overlapping for cutedsl gemm](../sources/prs/flashinfer/PR-1677.md), [Update TGV GEMM default kernel and TGV code cleanup.](../sources/prs/flashinfer/PR-1682.md), [Update deepgemm backend for 103a](../sources/prs/flashinfer/PR-1694.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [hotfix: Hotfix for `test_pod_kernels.py` on B300](../sources/prs/flashinfer/PR-1698.md), [feat: Benchmark mm_fp4 mxfp4 support and gemm autotune support. Restore mm_fp4 API behavior](../sources/prs/flashinfer/PR-1706.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [TVM: support TVM binding for GroupedGemm](../sources/prs/flashinfer/PR-1725.md), [fix: put sampling kernel launch into macro](../sources/prs/flashinfer/PR-1727.md), [fix: fix cannot import name 'cuda' from 'cuda' in CUDA13](../sources/prs/flashinfer/PR-1764.md), [Added xfail for mx_fp4 matmul on SM120](../sources/prs/flashinfer/PR-1766.md), [tests: skip non SM100/103 for grouped deepgemm](../sources/prs/flashinfer/PR-1767.md), [Support checks PoC](../sources/prs/flashinfer/PR-1809.md), [tests: Update support for tgv_gemm to SM100 only and add to ut](../sources/prs/flashinfer/PR-1810.md), [tests: upgrade cutlass, fix import and skip non-SM100 cutedsl two shot allreduce](../sources/prs/flashinfer/PR-1812.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [raise error for group_gemm_fp8_nt_groupwise then num_groups > 1 on sm120/121](../sources/prs/flashinfer/PR-1862.md), [feat: Add FP4 TRTLLM-Gen throughput MOE batched gemms](../sources/prs/flashinfer/PR-1882.md), [misc: fix some B200 GEMM bench](../sources/prs/flashinfer/PR-1883.md), [Add layernorm op for inputs of mixed dtype](../sources/prs/flashinfer/PR-1926.md), [Feature: Support Relu2 activation in fused MoE](../sources/prs/flashinfer/PR-1954.md), [Update trtllm-gen fused moe routing kernel and add more kernels](../sources/prs/flashinfer/PR-1955.md), [fix: ensure SM120/121 SFA/SFB contiguity](../sources/prs/flashinfer/PR-1963.md), [feat: enable deepgemm jit for fp8 block-scale on SM90](../sources/prs/flashinfer/PR-1969.md), [Feature: Add support for L40 FusedMoE in cutlass path](../sources/prs/flashinfer/PR-1973.md), [feat: Add backend='auto' to mm_fp4 and enable autotune for backend='cudnn'](../sources/prs/flashinfer/PR-1979.md), [fix: Enable SM121 for mm_fp4](../sources/prs/flashinfer/PR-2012.md), [[feat] Refactor trtllmgen MOE and add Bf16 trtllmgen moe](../sources/prs/flashinfer/PR-2014.md), [[DSV3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2019.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [[NVIDIA] Thor & Spark Support](../sources/prs/flashinfer/PR-2028.md), [feat: suitable_auto_backends to prune auto backends, bmm_fp8 refactor, heuristic_func intake](../sources/prs/flashinfer/PR-2029.md), [perf: Optimize helper max/minmax function in sampling.cuh](../sources/prs/flashinfer/PR-2058.md), [feat: BF16 GEMM using CUTLASS backend for SM100](../sources/prs/flashinfer/PR-2070.md), [refactor: pass hopper deepgemm include directory through python](../sources/prs/flashinfer/PR-2090.md), [perf: enable pdl for cutlass fp4 gemm](../sources/prs/flashinfer/PR-2095.md), [Refactor trtllm_mnnvl_allreduce](../sources/prs/flashinfer/PR-2118.md), [make DeepGEMM swapAB available for linear gemm SM90](../sources/prs/flashinfer/PR-2131.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [enable sm103 moe dsl backend](../sources/prs/flashinfer/PR-2149.md), [fix xqa mha_sm90.cu](../sources/prs/flashinfer/PR-2157.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [Fix gemm allreduce two shot](../sources/prs/flashinfer/PR-2171.md), [Fix for moe on sm110](../sources/prs/flashinfer/PR-2190.md), [feat: unit-test and api change, w4a8 grouped-gemm fused MoE for SM90](../sources/prs/flashinfer/PR-2193.md), [Move the run function definition out of BatchedGemmInterface](../sources/prs/flashinfer/PR-2211.md), [misc: support checks for gemm](../sources/prs/flashinfer/PR-2214.md), [refactor: pull trtllm-gen batch-gemm/gemm headers from artifactory; update tma descriptor shape init](../sources/prs/flashinfer/PR-2235.md), [Remove cudaStreamSynchronize from gemm_groupwise_sm120.cuh for CUDA graph compatibility](../sources/prs/flashinfer/PR-2244.md), [feat: Add support for bmm mxfp8](../sources/prs/flashinfer/PR-2256.md), [Fix CUTLASS FP8 gemm correctness issue on SM120/SM121 for shapes where N is not divisible by ScaleGranularityN.](../sources/prs/flashinfer/PR-2261.md), [test: use .float() in in F.cosine_similarity() in bmm_fp8 test](../sources/prs/flashinfer/PR-2266.md), [Tiny fix bench tgv gemm](../sources/prs/flashinfer/PR-2277.md), [feat: IdType indices in sampling kernels](../sources/prs/flashinfer/PR-2281.md), [Selective State Update kernel (mamba)](../sources/prs/flashinfer/PR-2301.md), [[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels](../sources/prs/flashinfer/PR-2303.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [Fix: FilteredTopKUnifiedKernel read value out of length](../sources/prs/flashinfer/PR-2308.md), [[ML3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2323.md), [bugfix: fix multi-cta top-k implementation when k value is different for different row](../sources/prs/flashinfer/PR-2325.md), [[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32](../sources/prs/flashinfer/PR-2327.md), [Enable fp16/bf16/f32 support for selective_state_update (mamba)](../sources/prs/flashinfer/PR-2366.md), [feat: BF16 GEMM using cuDNN backend](../sources/prs/flashinfer/PR-2376.md), [bugfix: hotfix of PR 2366 (mamba kernel)](../sources/prs/flashinfer/PR-2378.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [perf: mm_fp4 heuristic prioritizes CUTLASS over cuDNN on SM103](../sources/prs/flashinfer/PR-2404.md), [feat: update trtllm-gen MoE cubins](../sources/prs/flashinfer/PR-2416.md), [fix: Sampling: CUDA Graph fix](../sources/prs/flashinfer/PR-2432.md), [MTP for mamba ](../sources/prs/flashinfer/PR-2444.md), [fix: fix illegal memory access for NaN input in sampling kernels](../sources/prs/flashinfer/PR-2456.md), [perf: add fp4 GEMM tile configs and streamK scheduler for SM120](../sources/prs/flashinfer/PR-2460.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [feat: Add MXFP8 GEMM mm_mxfp8 (cutlass)](../sources/prs/flashinfer/PR-2464.md), [fix: add support check for gemm config for cutlass moe](../sources/prs/flashinfer/PR-2495.md), [refactor: Port upstream CUTLASS fixes and refactor grouped_gemm_nt_masked GEMM module location](../sources/prs/flashinfer/PR-2503.md), [Feat: Trtllm-gen MxFP8 MoE integration](../sources/prs/flashinfer/PR-2505.md), [feat: BF16 GEMM benchmarking support](../sources/prs/flashinfer/PR-2525.md), [fix: include fp8_blockscale_gemm_90 in AOT jit-cache](../sources/prs/flashinfer/PR-2533.md), [tests: bmm_fp8 for SM110](../sources/prs/flashinfer/PR-2538.md), [feat: cute dsl mmfp4 for blackwell](../sources/prs/flashinfer/PR-2540.md), [misc: point triton blackwell-ptxas to local cuda ptxas](../sources/prs/flashinfer/PR-2543.md), [Add gen_gemm_sm100_module_cutlass_mxfp8 to jit-cache](../sources/prs/flashinfer/PR-2549.md), [Add support for the combinations of allreduce, allgather, and reducescatter](../sources/prs/flashinfer/PR-2563.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [feat: trtllm tinygemm2 in flashinfer as bf16 routergemm](../sources/prs/flashinfer/PR-2587.md), [Mamba SSU: better automatic kernel selection + algorithm selection optionally exposed to the user.](../sources/prs/flashinfer/PR-2591.md), [[bugfix] Fix FilteredTopK overflow correctness](../sources/prs/flashinfer/PR-2605.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [feat: FP32 dtype output for BF16 matmuls (CUTLASS & cuDNN)](../sources/prs/flashinfer/PR-2644.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [fix: Add fused MOE and GEMM AOT modules for SM121](../sources/prs/flashinfer/PR-2654.md), [feat: support mxfp4 & mxfp8 entrypoint for blackwell cutedsl dense gemm](../sources/prs/flashinfer/PR-2660.md), [feat: implement deterministic topk](../sources/prs/flashinfer/PR-2661.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [fix: reduce smem allocation for tinygemm2 kernel in SM120](../sources/prs/flashinfer/PR-2670.md), [Add varlen and speculative decoding support to selective state update](../sources/prs/flashinfer/PR-2700.md), [fix(jit): GEMM kernels produce NaN under concurrency — missing GDC flags cause PDL synchronization barriers to compile as no-ops](../sources/prs/flashinfer/PR-2716.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [misc: Update gemm/batched gemm cubins from trtllm-gen, gemm header refactor](../sources/prs/flashinfer/PR-2740.md), [[Spark unit test debugging] Fix for tests/gemm/test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-2751.md), [[feat] Add air top-p algorithm](../sources/prs/flashinfer/PR-2752.md), [fix(jit): enable GDC for CUTLASS GEMM PDL — SM100 flag only](../sources/prs/flashinfer/PR-2780.md), [Upgrade cutlass 4.2.1 -> 4.4.2](../sources/prs/flashinfer/PR-2798.md), [CuteDSL MoE fix redundant output buffer zeroing](../sources/prs/flashinfer/PR-2811.md), [Add support for Relu2 in BF16 fused MoE](../sources/prs/flashinfer/PR-2864.md), [Mamba SSU: horizontal MTP kernel (+ DSTATE=96 support)](../sources/prs/flashinfer/PR-2865.md), [fix: fix cute dsl swap_ab tactic failure](../sources/prs/flashinfer/PR-2870.md), [feat: add MXFP8 GEMM support for SM120](../sources/prs/flashinfer/PR-2902.md), [[NVIDIA] fix(jit): enable GDC for CUTLASS fused MoE PDL — prevent random crashes on SM12x](../sources/prs/flashinfer/PR-2913.md), [feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners](../sources/prs/flashinfer/PR-2914.md), [feat: add Relu2 (squared ReLU) activation support in CUTLASS MoE backend](../sources/prs/flashinfer/PR-2926.md), [feat: SM121 (GB10) tile filtering and autotuner robustness](../sources/prs/flashinfer/PR-2927.md), [CuTe DSL FP4 GEMM Heuristic](../sources/prs/flashinfer/PR-2940.md), [feat: Add CuTe DSL grouped-gemm + combine fusion support](../sources/prs/flashinfer/PR-2944.md), [fix: use float instead of double in sampling binary search to avoid FP64 bottleneck on SM103](../sources/prs/flashinfer/PR-2945.md), [Update NVSHMEM interface to use NVSHMEM4Py instead of custom bindings](../sources/prs/flashinfer/PR-2960.md), [Improved `simple` mamba SSU kernel ](../sources/prs/flashinfer/PR-2962.md), [test: skip unsupported mm_mxfp8 configurations on SM12x](../sources/prs/flashinfer/PR-2974.md), [fix: tinygemm2 hang issue due to barrier sync](../sources/prs/flashinfer/PR-2996.md), [[chore] Install nvidia-cutlass-dsl[cu13] for cu130+](../sources/prs/flashinfer/PR-3017.md), [perf: Port TRT-LLM SM120/SM121 FP4 CUTLASS GEMM optimizations. Add PDL](../sources/prs/flashinfer/PR-3026.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [fused_moe: pre-filter SM89 tactics with zero occupancy on SM120 Blackwell (fix review feedback on #2764)](../sources/prs/flashinfer/PR-3032.md), [feat: Add backend="b12x" for mm_fp4 on SM120](../sources/prs/flashinfer/PR-3051.md), [perf: Add no-bias path for tinygemm_bf16](../sources/prs/flashinfer/PR-3151.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [Fix/3170 dense blockscaled sm12x](../sources/prs/flashinfer/PR-3180.md), [test: enable bmm_mxfp8 cutlass backend coverage on SM12x](../sources/prs/flashinfer/PR-3183.md), [feat: enable glm5 router gemm](../sources/prs/flashinfer/PR-3185.md), [Include TinyGEMM into BF16 autotuner](../sources/prs/flashinfer/PR-3203.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [[Bugfix] Fix fused MoE autotuning correctness issues by filtering clusterDimZ](../sources/prs/flashinfer/PR-3227.md), [Update moe gemm](../sources/prs/flashinfer/PR-3239.md), [[feat] Add gemma RMS AR fusion](../sources/prs/flashinfer/PR-3322.md), [Change `apply_rope_with_cos_sin_cache` to accept `cos_sin_cache`](../sources/prs/flashinfer/PR-754.md), [bugfix: Ensure Loop Termination by Enforcing IEEE-754 Compliance in Sampling Kernels](../sources/prs/flashinfer/PR-774.md), [bugfix: fix the signature of `CutlassSegmentGEMMSM90`](../sources/prs/flashinfer/PR-827.md), [feat: experimenta support of PDL](../sources/prs/flashinfer/PR-930.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [perf: dual pivot top-p/top-k renorm](../sources/prs/flashinfer/PR-974.md), [SM-constraint-GEMM by triton persistent kernel](../sources/prs/flashinfer/PR-982.md), [Triton `rms_norm` kernels](../sources/prs/flashinfer/PR-983.md), [feat: SM-constraint Communication Kernels](../sources/prs/flashinfer/PR-994.md), [Update torch-xpu-ops commit pin](../sources/prs/pytorch/PR-144209.md), [[inductor][cpu] Fix bmm b_index for dynamic expressions in inductor autotuner](../sources/prs/pytorch/PR-144248.md), [Fix PythonMod printing](../sources/prs/pytorch/PR-144335.md), [ROCm SDPA: Ensure attn_mask has the same dtype with q](../sources/prs/pytorch/PR-144398.md), [[inductor] Fix profiler tests with latest Triton](../sources/prs/pytorch/PR-149059.md), [Remove runtime dependency on packaging](../sources/prs/pytorch/PR-149125.md), [op should NOT be static in aoti_torch_call_dispatcher](../sources/prs/pytorch/PR-149644.md), [Add release branch push triggers to inductor-rocm-mi300.yml](../sources/prs/pytorch/PR-149871.md), [[inductor] Fix inductor windows linker error](../sources/prs/pytorch/PR-150447.md), [[Windows][inductor] fix blank space break windows file path](../sources/prs/pytorch/PR-150448.md), [[CUDA][avgpool2d] Fix backward launch bounds again for `sm100`, `sm120`](../sources/prs/pytorch/PR-150676.md), [[dynamo][super variable] Fix bug to use correct source](../sources/prs/pytorch/PR-152774.md), [[ATen][CUDA] Optimize 128 bit vectorization](../sources/prs/pytorch/PR-152967.md), [Mark auto_functionalized HOPs as cacheable (#151194)](../sources/prs/pytorch/PR-153304.md), [Fix uint view copy (#151598)](../sources/prs/pytorch/PR-154121.md), [Fix macOS build with `USE_MPS=OFF`](../sources/prs/pytorch/PR-156932.md), [[PowerPC] Fixed build issue for vsx vec256 complexfloat and scaled_mm_out_cpu ](../sources/prs/pytorch/PR-157422.md), [[release] Triton pin update to 3.4](../sources/prs/pytorch/PR-157752.md), [[MPS] Switch Cholesky decomp to column wise](../sources/prs/pytorch/PR-158237.md), [[cherry-pick][inductor][triton] Update HAS_WARP_SPEC to check triton.Config params. Update Triton Hash to top of release/3.4.x stack](../sources/prs/pytorch/PR-158646.md), [CUDA 13.0 Windows Nvidia Driver Update to 580.88](../sources/prs/pytorch/PR-162501.md), [[Cherry Pick][Graph Partition] allow sharing default device context](../sources/prs/pytorch/PR-163097.md), [[Release 2.9] [cuDNN][SDPA][submodule] Roll-back cuDNN frontend upgrade, update Met…](../sources/prs/pytorch/PR-163265.md), [[Graph Partition] improve custom op output alias](../sources/prs/pytorch/PR-163380.md), [[Inductor][Intel GPU] Save `threads_per_warp` from tirton compiled kernel for launching kernel correctly in cpp wrapper.](../sources/prs/pytorch/PR-163388.md), [[graph partition] Add way to register custom rule (#163310)](../sources/prs/pytorch/PR-163395.md), [[2.9 cherry pick][triton] update 3.5 pin to bbb06c0334a6772b92d24bde54956e675c8c6604 (#163382)](../sources/prs/pytorch/PR-163583.md), [CUDA 13.0 Warning update for supported architectures](../sources/prs/pytorch/PR-163633.md), [[Cherry-Pick] [CD] CUDA 13 specific followup changes. Remove sm50-70 From CUDA 12.6 and CUDA 12.8 builds (#162455)](../sources/prs/pytorch/PR-163764.md), [[CD] CUDA 13.0 fix preload logic to include nvidia/cu13/lib/](../sources/prs/pytorch/PR-163766.md), [fix pickling for BitwiseFn](../sources/prs/pytorch/PR-163861.md), [Move inductor jobs 3.9->3.10](../sources/prs/pytorch/PR-163954.md), [[cuDNN][SDPA] Disable dropout for cuDNN SDPA on 9.11 - 9.13](../sources/prs/pytorch/PR-164026.md), [[AARCH64][CD][CUDA13][Triton][PTXAS] Turn on BUILD_BUNDLE_PTXAS=1 ](../sources/prs/pytorch/PR-164236.md), [CUDA 13.0 builds fix on Amazon Linux 2023](../sources/prs/pytorch/PR-164893.md), [[inductor] don't try to reorder loops for template](../sources/prs/pytorch/PR-166910.md), [[Dynamo] Don't guard data ptrs by default with mark_static_address](../sources/prs/pytorch/PR-166913.md), [[Inductor] No longer throw error in bmm out_dtype lowering due to tem…](../sources/prs/pytorch/PR-166922.md), [[Graph Partition] move custom rules to inductor config (#166458)](../sources/prs/pytorch/PR-166967.md), [[Graph Partition] fix graph partition input signature for fallback kernels](../sources/prs/pytorch/PR-166985.md), [[GraphPartition] cache get_free_symbol_uses (#166338)](../sources/prs/pytorch/PR-166994.md), [[Minor][Inductor] move some combo kernel log from warning to debug](../sources/prs/pytorch/PR-167020.md), [[cuDNN][SDPA] Check-in test for #166211](../sources/prs/pytorch/PR-167121.md), [[cuDNN][SDPA][Convolution] Expose cuDNN runtime version in CUDA hooks](../sources/prs/pytorch/PR-167327.md), [[ROCm] Enable shared memory based pruning for Triton configs](../sources/prs/pytorch/PR-170190.md), [[Inductor] ExternKernelBenchmarkRequest best attempt](../sources/prs/pytorch/PR-170246.md), [[inductor] Fix cudagraph skip for index_put_ with boolean indices, gr…](../sources/prs/pytorch/PR-170884.md), [[Inductor] Fix constants handling for Triton constexpr (triton#8248)](../sources/prs/pytorch/PR-171129.md), [[ROCm] Make grouped GEMM CK opt‑in via env and default to fallback path](../sources/prs/pytorch/PR-171140.md), [Avoid closing random file handles in Inductor](../sources/prs/pytorch/PR-171150.md), [[cherry-pick][CUDA] Upgrade cuDNN to 9.15.1 for CUDA 13 builds ](../sources/prs/pytorch/PR-171189.md), [[xpu][fix][inductor] fallback bfloat16 atomics to eager](../sources/prs/pytorch/PR-171247.md), [[cherry-pick][cuDNN][SDPA] cuDNN SDPA off-by-default for cuDNN versions < 12.9 (#171627)](../sources/prs/pytorch/PR-171895.md), [Skip modded_nanogpt model in TorchInductor benchmark](../sources/prs/pytorch/PR-172141.md), [[Graph Partition] Improve support for mutation ops](../sources/prs/pytorch/PR-172577.md), [Update inductor expected accuracy files](../sources/prs/pytorch/PR-175096.md), [[benchmark] Skip pytorch_CycleGAN_and_pix2pix from inductor benchmarks](../sources/prs/pytorch/PR-175299.md), [[release-only] Remove +ptx from cuda 13.0 builds](../sources/prs/pytorch/PR-175567.md), [[inductor] avoid multi-stage for mix-order-red by default (#176228)](../sources/prs/pytorch/PR-176495.md), [[inductor] Fix Identity comparability and evalf recursion](../sources/prs/pytorch/PR-176783.md), [[Inductor] Don't unfuse addmm for bf16/fp16 to avoid precision loss](../sources/prs/pytorch/PR-177144.md), [[Inductor][MPS] Fix half-precision type mismatches in Metal shader codegen (#176436)](../sources/prs/pytorch/PR-177193.md), [[MPS] fix compiling of SDPA producing nan results](../sources/prs/pytorch/PR-178009.md), [Optimize nvfp4 block scaled gemm kernel when M is small.](../sources/prs/sglang/PR-10101.md), [fix: resolve gb200 image link](../sources/prs/sglang/PR-10343.md), [Update CUTLASS. Refine KernelSchedule for fp8 (grouped) gemm.](../sources/prs/sglang/PR-10491.md), [Cache the result of `is_blackwell` platform check](../sources/prs/sglang/PR-10498.md), [Unify SGL Kernel Releases](../sources/prs/sglang/PR-10701.md), [Optimize cutlass int8 gemm kernel for large M on SM89 Ada GPU](../sources/prs/sglang/PR-10714.md), [chore: upgrade sgl-kernel 0.3.13](../sources/prs/sglang/PR-11056.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [Improve Kernel Build Time](../sources/prs/sglang/PR-11508.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [Change bf16 to fp8 for some gemms in attention for DeepSeek ckpt v2](../sources/prs/sglang/PR-11805.md), [Use cutlass fp4 gemm by default](../sources/prs/sglang/PR-11813.md), [chore: upgrade flashinfer 0.4.1](../sources/prs/sglang/PR-11933.md), [[sgl-kernel][4/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12080.md), [[hotfix] missing `w13_weight_fp8` and `w2_weight_fp8` in UE8M0 requantization](../sources/prs/sglang/PR-12259.md), [fix: Llama 4 BF16 load on Blackwell](../sources/prs/sglang/PR-12308.md), [[sgl-kernel] clean up fa fetch in CMakeLists.txt](../sources/prs/sglang/PR-12392.md), [chore: upgrade flashinfer 0.5.0](../sources/prs/sglang/PR-12523.md), [[NVIDIA] Fix CUDA arch requirement in nvfp4 cast](../sources/prs/sglang/PR-12581.md), [[sgl-kernel][5/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12666.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [[NVIDIA] Fix use case of SGLANG_ENABLE_FLASHINFER_GEMM](../sources/prs/sglang/PR-13274.md), [Support weight update for blackwell DeepGEMM](../sources/prs/sglang/PR-13324.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [[chore]Upgrade flashinfer to 0.5.3](../sources/prs/sglang/PR-13751.md), [update flashinfer_cubin==0.5.3](../sources/prs/sglang/PR-13848.md), [Fix update weight error for blackwell DeepGEMM](../sources/prs/sglang/PR-13910.md), [Add new moe wna16 marlin gemm](../sources/prs/sglang/PR-14122.md), [Apply new moe wna16 marlin gemm](../sources/prs/sglang/PR-14125.md), [[CPU] Implement MXFP4 Gemm kernels for intel AMX to support GPT OSS series.](../sources/prs/sglang/PR-14385.md), [Add CUDA kernel size analysis tool for sgl-kernel optimization](../sources/prs/sglang/PR-14544.md), [[sgl-kernel][Feat][B200][2/N] Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-14640.md), [Add cache for flashinfer installation](../sources/prs/sglang/PR-15153.md), [[Tiny]Add warning for deepgemm on Blackwell](../sources/prs/sglang/PR-15352.md), [[sgl-kernel][6/7]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-15471.md), [[Perf] Add Flashinfer DeepGEMM SM90 for SwapAB Optimization](../sources/prs/sglang/PR-15514.md), [[sgl-kernel] Streamline kernel size report (Top 20 only) and clean up](../sources/prs/sglang/PR-15552.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [[fix]deepgemm precompile when warmup](../sources/prs/sglang/PR-15891.md), [[Feature] add aligned_vector type for JIT kernel](../sources/prs/sglang/PR-16162.md), [Fix sgl-kernel jobs to skip when target_stage is specified](../sources/prs/sglang/PR-16308.md), [[Fix]Pin mooncake version to 0.3.7.post2 in grace blackwell](../sources/prs/sglang/PR-16502.md), [Fix FP8 MoE NaN with DeepGEMM on Blackwell](../sources/prs/sglang/PR-16622.md), [Support mxint4 flashinfer_trtllm moe gemm](../sources/prs/sglang/PR-16892.md), [[MUSA][2/N] sgl-kernel build](../sources/prs/sglang/PR-17053.md), [[FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/sglang/PR-17300.md), [Upgrade transformers==5.3.0](../sources/prs/sglang/PR-17784.md), [Feature/support longcat flash lite](../sources/prs/sglang/PR-17838.md), [Skipped warning on sm100](../sources/prs/sglang/PR-18000.md), [[Diffsuion & JIT_kernel] QKNorm cross heads kernel](../sources/prs/sglang/PR-18073.md), [[Blackwell] Make mxint4 flashinfer_trtllm moe gemm set by default on blackwell](../sources/prs/sglang/PR-18136.md), [[FIX] Correct JIT kernel compilation on newer GPUs with outdated driver metadata.](../sources/prs/sglang/PR-18496.md), [use flashinfer.sampling](../sources/prs/sglang/PR-18696.md), [fix: update Blackwell log/error messages to include SM12x](../sources/prs/sglang/PR-18751.md), [fix: add SM110 (Jetson AGX Thor) to Blackwell capability check](../sources/prs/sglang/PR-18787.md), [Migrate renorm kernels from sgl-kernel to FlashInfer JIT](../sources/prs/sglang/PR-18854.md), [Add claude skills for sgl-kernel and jit-kernel](../sources/prs/sglang/PR-18855.md), [Migrate norm kernels to FlashInfer JIT implementation](../sources/prs/sglang/PR-18871.md), [Use single mma warp group for short q_len in FA to optimize decoding performance](../sources/prs/sglang/PR-18985.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [[JIT Kernel][Feature] Support JIT custom all reduce (rewrite as v2)](../sources/prs/sglang/PR-19880.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [fix ci by removing nvidia-cutlass-dsl-libs-base and force reinstall n…](../sources/prs/sglang/PR-20380.md), [Fix(jit): support rmsnorm for hidden_size in {64, 128, 256}](../sources/prs/sglang/PR-20661.md), [Use FlashInfer tinygemm for GPT-OSS MoE router on SM90+](../sources/prs/sglang/PR-20755.md), [fix: guard configure_deep_gemm_num_sms when JIT disabled](../sources/prs/sglang/PR-20868.md), [CUTLASS FP8 Blockwise GEMM improvement of SM120](../sources/prs/sglang/PR-20887.md), [[Tiny Fix] Fix IS_BLACKWELL env var empty string warning in rerun-ut workflow](../sources/prs/sglang/PR-20957.md), [fix: wrap _import_static_state in inference_mode to fix resume on Blackwell](../sources/prs/sglang/PR-21035.md), [ci: remove IS_BLACKWELL env var; auto-detect Blackwell](../sources/prs/sglang/PR-21118.md), [[NPU] bugfix for import sgl-kernel error](../sources/prs/sglang/PR-21200.md), [Split pr-test.yml: extract sgl-kernel, jit-kernel, and multimodal-gen tests into separate workflow files](../sources/prs/sglang/PR-21219.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[MUSA] apply_vocab_mask support musa device](../sources/prs/sglang/PR-21296.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[FlashInver v0.6.7] Integrate flashinfer_trtllm mxfp8 gemm](../sources/prs/sglang/PR-21576.md), [[AMD] Use tgemm.mm for MoEGate router gemm in deepseek_v2.py](../sources/prs/sglang/PR-21657.md), [Remove flashinfer wheel cache cleanup that deletes other versions](../sources/prs/sglang/PR-21711.md), [[DSA] Set trtllm kernels as default for Blackwell](../sources/prs/sglang/PR-21914.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[Hotfix] Fix router gemm on sm103](../sources/prs/sglang/PR-22134.md), [[hisparse]: Adding ci for hisparse kvcache-swap-in jit-kernel](../sources/prs/sglang/PR-22155.md), [[HiSparse]: Add benchmark for hisparse kernel](../sources/prs/sglang/PR-22187.md), [[Docker] Fix Trivy CVEs, cubin download 403s, and kernels command order](../sources/prs/sglang/PR-22322.md), [Upgrade sglang-torch-profiler-analysis SKILLS](../sources/prs/sglang/PR-22440.md), [[RL] Fix weight update for mxfp8 flashinfer_cutlass gemm backend](../sources/prs/sglang/PR-22484.md), [[CI/Docker] Clean up redundant flashinfer cubin downloads](../sources/prs/sglang/PR-22491.md), [[Docker] Remove flashinfer cache copy](../sources/prs/sglang/PR-22653.md), [[Fix/Kernel] Add JIT rmsnorm_hf kernel to fix transformers backend MMLU accuracy regression ](../sources/prs/sglang/PR-22931.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [feat: port SGLANG_JIT_DEEPGEMM_FAST_WARMUP to deepseek_v4 branch](../sources/prs/sglang/PR-23756.md), [Enable PDL for various kernels in DSV32/GLM5](../sources/prs/sglang/PR-23965.md), [[VLM] Optimize Gemma4 VLM with PCG and fuse RMSNorm + residual add + scalar](../sources/prs/sglang/PR-24048.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [[Gemma4] Optimize Gemm4 with fused Q/K/V RMSNorm + per-expert FP8 ckpt loader](../sources/prs/sglang/PR-24696.md), [[codex] Optimize hidden-size 512 RMSNorm dispatch](../sources/prs/sglang/PR-24710.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [Support Gemma4 Pipeline Parallelism](../sources/prs/sglang/PR-25284.md), [[Gemma4]: Fix FP8 Triton scale layout](../sources/prs/sglang/PR-25286.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[fp8] SM90 swap-AB scaled_mm dispatch (~1.16x kernel geomean, +5.8-18.5% end-to-end)](../sources/prs/sglang/PR-25532.md), [Use DeepGEMM BF16 for unquantized DeepEP LL MoE](../sources/prs/sglang/PR-25540.md), [fix (jit kernel): elementwise activation C++ error](../sources/prs/sglang/PR-25695.md), [[Codex] Remove stale DeepSeek V4 JIT kernels](../sources/prs/sglang/PR-25764.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Support cutlass Int8 gemm](../sources/prs/sglang/PR-2752.md), [upgrade cutlass v3.7.0](../sources/prs/sglang/PR-2967.md), [feat: add flashinfer as 3rdparty and use rmsnorm as example](../sources/prs/sglang/PR-3033.md), [Support sm90 Int8 gemm](../sources/prs/sglang/PR-3035.md), [Allow local cutlass directory to be used in sgl-kernel build](../sources/prs/sglang/PR-3037.md), [support w8a8 fp8 kernel with CUTLASS](../sources/prs/sglang/PR-3047.md), [sync the upstream updates of flashinfer](../sources/prs/sglang/PR-3051.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [support blockwise fp8 matmul kernel](../sources/prs/sglang/PR-3267.md), [fix undefined symbol cudaGetDriverEntryPointByVersion](../sources/prs/sglang/PR-3372.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [update flashinfer-python](../sources/prs/sglang/PR-3557.md), [[Feature] Apply Cublas Grouped Gemm kernel](../sources/prs/sglang/PR-3629.md), [add control for cutlass fp8 blockwise gemm](../sources/prs/sglang/PR-3727.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [upgrade flashinfer v0.2.2.post1](../sources/prs/sglang/PR-3934.md), [Support overlapping two batches](../sources/prs/sglang/PR-4068.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [linear support deepgemm](../sources/prs/sglang/PR-4199.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [fix per_token_group_quant_fp8 illegal memory when num_groups % 16 != 0](../sources/prs/sglang/PR-4231.md), [add THIRDPARTYNOTICES for DeepGEMM](../sources/prs/sglang/PR-4272.md), [Support Blackwell Block Scale FP8 Gemm](../sources/prs/sglang/PR-4278.md), [update deepgemm](../sources/prs/sglang/PR-4284.md), [upgrade flashinfer 0.2.3](../sources/prs/sglang/PR-4317.md), [[FIX] fix incorrect output when enable both deepgemm and torch compile](../sources/prs/sglang/PR-4359.md), [Create col-major and tma-aligned x_scale for deep_gemm.gemm_fp8_fp8_bf16_nt](../sources/prs/sglang/PR-4515.md), [Support fp8 gemm for blackwell](../sources/prs/sglang/PR-4558.md), [Set deepgemm to the default value in the hopper architecture.](../sources/prs/sglang/PR-4613.md), [Fix loading KV quantization scale; Enable modelopt kv cache](../sources/prs/sglang/PR-4686.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [[Feat] support deepgemm for cmake](../sources/prs/sglang/PR-4864.md), [[Build] Fix cuda12.8 build error in nvfp4_scaled_mm_kernels.cu](../sources/prs/sglang/PR-4953.md), [update cutlass tag](../sources/prs/sglang/PR-5011.md), [fix deepgemm as well](../sources/prs/sglang/PR-5030.md), [support sgl-kernel on blackwell](../sources/prs/sglang/PR-5074.md), [Add optimized native kernels in sgl-kernel](../sources/prs/sglang/PR-5150.md), [feat: add DeepGEMM build warning](../sources/prs/sglang/PR-5176.md), [[Fix] Turn off DeepGEMM by default](../sources/prs/sglang/PR-5263.md), [fix: use deepgemm only on hopper](../sources/prs/sglang/PR-5310.md), [fix: determine if flashinfer is installed](../sources/prs/sglang/PR-5336.md), [Fix DeepGEMM masked cannot be run on groups not being multiple or 4](../sources/prs/sglang/PR-5340.md), [chore: upgrade DeepGEMM](../sources/prs/sglang/PR-5395.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Fix sampler nan check when calling top_k_top_p_sampling_from_probs](../sources/prs/sglang/PR-5546.md), [feat: use flashinfer jit package](../sources/prs/sglang/PR-5547.md), [[feature] enable pre compile jit deep_gemm](../sources/prs/sglang/PR-5580.md), [[fix] force use deepgemm in compile_deep_gemm](../sources/prs/sglang/PR-5618.md), [ DeepEP normal support deepgemm-contiguous](../sources/prs/sglang/PR-5626.md), [Turn on DeepGemm By Default and Update Doc](../sources/prs/sglang/PR-5628.md), [cutlass 3.9 supported to improve fp8_blockwise_gemm](../sources/prs/sglang/PR-5820.md), [Add sm_120 for blackwell](../sources/prs/sglang/PR-5903.md), [[Feat] Enable PDL automatically on Hopper architecture](../sources/prs/sglang/PR-5981.md), [chore: upgrade cutlass 3.9.2](../sources/prs/sglang/PR-6004.md), [chore: upgrade deepgemm](../sources/prs/sglang/PR-6073.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [[Fix] Improve dependencies for Blackwell image](../sources/prs/sglang/PR-6334.md), [Upgrade CUTLASS 4.0](../sources/prs/sglang/PR-6336.md), [Add fp8 fused_experts kernel for CPU in sgl-kernel and add UT](../sources/prs/sglang/PR-6404.md), [Fix bug of deepseek-v3 under DP+EP mode with large batchsize/seqlen](../sources/prs/sglang/PR-6449.md), [[Feature] Support Flashinfer fp8 blockwise GEMM kernel on Blackwell](../sources/prs/sglang/PR-6479.md), [[CPU] [BF16] Call fused_experts_cpu, weight_packed_linear and bmm_cpu kernel in DeepSeek model](../sources/prs/sglang/PR-6641.md), [Correctly abort the failed grammar requests & Improve the handling of abort](../sources/prs/sglang/PR-6803.md), [feat: integrate deepgemm into EPMoE](../sources/prs/sglang/PR-6821.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [Fix AWQ Dequant and Weight Loading of deepseek v2](../sources/prs/sglang/PR-6842.md), [Use deepgemm instead of triton for fused_qkv_a_proj_with_mqa](../sources/prs/sglang/PR-6890.md), [[sgl-kernel] update deepgemm](../sources/prs/sglang/PR-6942.md), [Fix torchvision version for Blackwell](../sources/prs/sglang/PR-7015.md), [Clean up server_args.py](../sources/prs/sglang/PR-7037.md), [feat: update blackwell setup](../sources/prs/sglang/PR-7119.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Tiny let DeepGEMM scale checks cover more cases](../sources/prs/sglang/PR-7182.md), [chore: upgrade sgl-kernel v0.1.8.post2](../sources/prs/sglang/PR-7186.md), [Fix a minor bug related to DeepGEMM upgrade](../sources/prs/sglang/PR-7191.md), [Fix error when disabling new DeepGEMM](../sources/prs/sglang/PR-7198.md), [[fix] fix DeepGEMM blackwell input quant & ut & fix style and log](../sources/prs/sglang/PR-7247.md), [Add CUTLASS FP8 Blockscale MoE kernel for Hopper architecture](../sources/prs/sglang/PR-7278.md), [Let EP prefill support new DeepGEMM](../sources/prs/sglang/PR-7310.md), [Kernels for efficient KV cache IO](../sources/prs/sglang/PR-7313.md), [fix: resolve blackwell deepep image issue](../sources/prs/sglang/PR-7331.md), [Quick fix for DeepGemm requant to also cover MTP.](../sources/prs/sglang/PR-7378.md), [[CMake] Fix sgl-kernel CMakeLists for Blackwell](../sources/prs/sglang/PR-7543.md), [Add dsv3 router gemm kernel](../sources/prs/sglang/PR-7627.md), [Add dsv3 fused a gemm to sgl-kernel](../sources/prs/sglang/PR-7630.md), [[Feature] Layer-wise Prefill](../sources/prs/sglang/PR-7634.md), [Apply dsv3_fused_a_gemm kernel](../sources/prs/sglang/PR-7635.md), [[Feature] CUDA Green Context Support](../sources/prs/sglang/PR-7649.md), [chore: upgrade flashinfer v0.2.7 jit](../sources/prs/sglang/PR-7663.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [[Fix][Ready]Fix register spilling in cutlass nvfp4 gemm kernel on Blackwell](../sources/prs/sglang/PR-8127.md), [[sgl-kernel] Opt per_token_quant_fp8 with warp reduce](../sources/prs/sglang/PR-8130.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/sglang/PR-8818.md), [chore: support blackwell cu129 image](../sources/prs/sglang/PR-8928.md), [[NVIDIA] Fix missing `get_col_major_tma_aligned_tensor` for Blackwell deepgemm in EpMoE](../sources/prs/sglang/PR-8955.md), [[fix] fix enable_pdl for blackwell](../sources/prs/sglang/PR-9011.md), [[sgl-kernel] Support FlashInfer top_k_top_p_sampling_from_logits](../sources/prs/sglang/PR-9060.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [Fix FP4 inference corruption issue in glm4.5-air model](../sources/prs/sglang/PR-9346.md), [[sgl-kernel] feat: Support sm120 cutlass fp8 gemm kernel](../sources/prs/sglang/PR-9403.md), [fix: blackwell dsv3 fp8 issue temporary solution](../sources/prs/sglang/PR-9530.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [Single Batch Overlap for MoE Models](../sources/prs/sglang/PR-9660.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [Make sm100 fp8 kernels available on sm103](../sources/prs/sglang/PR-9789.md), [Make fp4_quantize kernels work on sm103](../sources/prs/sglang/PR-9807.md), [perf: Avoid unnecessary data type conversions for DeepSeek-V3 on Blackwell](../sources/prs/sglang/PR-9834.md), [[Fix] DeepSeek EP accuracy issue on B200 GPUs](../sources/prs/sglang/PR-9946.md), [CUTLASS fp8 blockwise gemm support of sm120](../sources/prs/sglang/PR-9969.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feat] profiler support cudagraph backend](../sources/prs/tilelang/PR-1658.md), [Add swizzle layout detection and automatic merging for layout conflicts](../sources/prs/tilelang/PR-1736.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [fix(intrinsics): add missing _legalize_to_buffer_region in SM70 emitter](../sources/prs/tilelang/PR-1786.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Bugfix] Fix CuTeDSL autotune cache invalid ELF header (#1967)](../sources/prs/tilelang/PR-1972.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[CUDA] Improve int4 GEMM lowering and packed codegen support](../sources/prs/tilelang/PR-2073.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[CUDA] Add native SM75 MMA GEMM support for FP16, INT8 and INT4](../sources/prs/tilelang/PR-2198.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[Kernel] Update `cutlass_scaled_mm` to support 2d group (blockwise) scaling](../sources/prs/vllm/PR-11868.md), [[Build] Only build 9.0a for scaled_mm and sparse kernels](../sources/prs/vllm/PR-12339.md), [[Core][AMD] Migrate fully transparent sleep mode to ROCm platform](../sources/prs/vllm/PR-12695.md), [[Misc][Kernel]: Add GPTQAllSpark Quantization](../sources/prs/vllm/PR-12931.md), [[Kernel]Add streamK for block-quantized CUTLASS kernels](../sources/prs/vllm/PR-12978.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [[Kernel] optimize performance of gptq marlin kernel when n is small](../sources/prs/vllm/PR-14138.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [fix minor miscalled method](../sources/prs/vllm/PR-14327.md), [Add cutlass support for blackwell fp8 blockwise gemm](../sources/prs/vllm/PR-14383.md), [[BugFix] Illegal Memory Access in the blockwise cutlass fp8 GEMMs](../sources/prs/vllm/PR-14396.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[BugFix/Build] Fix sparse kernels not getting built on hopper](../sources/prs/vllm/PR-14572.md), [[Quantization][FP8] Adding support for fp8 gemm layer input in fp8](../sources/prs/vllm/PR-14578.md), [[Kernel] allow non-contiguous input for marlin kernel](../sources/prs/vllm/PR-14658.md), [[Model] Add support for Gemma 3](../sources/prs/vllm/PR-14660.md), [[Bugfix][Kernel][CPU] Fix num_tokens in CPU rotary embedding kernel](../sources/prs/vllm/PR-14667.md), [[FEAT] [ROCm]: Add AITER Block-Scaled GEMM Feature](../sources/prs/vllm/PR-14968.md), [[FEAT] [ROCm] Add AITER int8 scaled gemm kernel](../sources/prs/vllm/PR-15433.md), [[Quantization] Fp8 Channelwise Dynamic Per Token GroupedGEMM](../sources/prs/vllm/PR-15587.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[Perf]Optimize rotary_emb implementation to use Triton operator for improved inference performance](../sources/prs/vllm/PR-16457.md), [[Kernel] some optimizations for dense marlin and moe marlin](../sources/prs/vllm/PR-16850.md), [[Bugfix] gemma[2,3] interleaved attention when sliding window is disabled](../sources/prs/vllm/PR-17180.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [[Kernel] Have rotary embeddings support tensors](../sources/prs/vllm/PR-18046.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Kernel] Enable fp8 support for pplx and BatchedTritonExperts.](../sources/prs/vllm/PR-18864.md), [[Kernel] Support deep_gemm for linear methods](../sources/prs/vllm/PR-19085.md), [[V1] Use FlashInfer by default on Blackwell GPUs](../sources/prs/vllm/PR-19118.md), [[Kernels] Add activation chunking logic to FusedMoEModularKernel](../sources/prs/vllm/PR-19168.md), [[Bugfix] Don't attempt to use triton if no driver is active](../sources/prs/vllm/PR-19561.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [Fix FA2 fallback for Blackwell V1](../sources/prs/vllm/PR-19781.md), [[Feature] Integrate new deepgemm](../sources/prs/vllm/PR-19820.md), [ [Feature] Integrate SM100 DeepGEMM support](../sources/prs/vllm/PR-20087.md), [[Nixl] Heterogeneous TP support FlashInfer](../sources/prs/vllm/PR-20189.md), [[Misc] DP : Add ExpertTokensMetadata](../sources/prs/vllm/PR-20332.md), [[Kernel] SM90 CUTLASS FP8 GEMM: add support for swap AB + kernel tuning](../sources/prs/vllm/PR-20396.md), [[feat]: add SM100 support for cutlass FP8 groupGEMM](../sources/prs/vllm/PR-20447.md), [[feat] enable SM100 CUTLASS block scaled group gemm for smaller batch sizes](../sources/prs/vllm/PR-20640.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [[fix]: disable cutlass block scaled group gemm for EP](../sources/prs/vllm/PR-20781.md), [[Bug] Fix DeepGemm for EP low latency case](../sources/prs/vllm/PR-20833.md), [[Perf] Use Triton instead of Torch for DeepGEMM Per Token Group Quant](../sources/prs/vllm/PR-20841.md), [[Kernel] DeepGemm MoE : Integrate triton permute / unpermute kernels ](../sources/prs/vllm/PR-20903.md), [[Perf] Add swap_ab to SM90 FP8 non-block CUTLASS moe grouped gemm](../sources/prs/vllm/PR-20911.md), [[Model] Pooling models default to using chunked prefill & prefix caching if supported.](../sources/prs/vllm/PR-20930.md), [[Bugfix] Switch bailout logic for kv-cache-dtype with SM100 Flashinfer](../sources/prs/vllm/PR-20934.md), [[Bugfix] Fix Mistral3 support on SM100/SM120](../sources/prs/vllm/PR-20998.md), [[Perf] Use FlashInfer RoPE for RotaryEmbedding.forward_cuda when available](../sources/prs/vllm/PR-21126.md), [[Bug] DeepGemm: Fix TypeError: per_block_cast_to_fp8() missing 1 required positional argument: 'use_ue8m0' for SM100](../sources/prs/vllm/PR-21187.md), [Override attention metadata for fast prefill in some KV sharing setups](../sources/prs/vllm/PR-21590.md), [update flashinfer to v0.2.9rc2](../sources/prs/vllm/PR-21701.md), [[Logs] Change flashinfer sampler logs to once](../sources/prs/vllm/PR-21759.md), [[bugfix] fix blackwell deepep installation](../sources/prs/vllm/PR-22255.md), [[Bugfix] Fix 3D input passed into cutlass_scaled_mm](../sources/prs/vllm/PR-22278.md), [Update `flashinfer-python==0.2.10`](../sources/prs/vllm/PR-22389.md), [[Bug] Fix B200 DeepGEMM E8M0 Accuracy Issue](../sources/prs/vllm/PR-22399.md), [Upgrade FlashInfer to v0.2.11](../sources/prs/vllm/PR-22613.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [[Kernel] Added flashinfer fp8 per-tensor gemms](../sources/prs/vllm/PR-22895.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [[Perf] Small optimizations for silu_mul_fp8_quant_deep_gemm](../sources/prs/vllm/PR-23265.md), [[Perf] Use upstream CUTLASS for SM90 Block FP8 kernel](../sources/prs/vllm/PR-23280.md), [[Feature] Add Hopper DeepGEMM E8M0 for DeepSeekV3.1 scale_fmt](../sources/prs/vllm/PR-23666.md), [[Performance] Move apply_w8a8_block_fp8_linear to an op class](../sources/prs/vllm/PR-24666.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [Enable Fbgemm NVFP4 on Dense models](../sources/prs/vllm/PR-25609.md), [Update launch_bounds_utils.h for correct compile on Multiple Cuda Arch - PTXAS out of range Warning](../sources/prs/vllm/PR-25843.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[NVIDIA] Add support for cudnn fp4 gemm via flashinfer](../sources/prs/vllm/PR-26107.md), [[Bug] Fix Shape Validation for Fallback while Enabling E8M0 for DeepGEMM](../sources/prs/vllm/PR-26322.md), [Disable FlashInfer sampler by default](../sources/prs/vllm/PR-26859.md), [[Feature] Batch Invariant: Support DeepGEMM and Blackwell](../sources/prs/vllm/PR-27127.md), [[Feature] Batch Invariant for R1 TP 8 on Blackwell](../sources/prs/vllm/PR-27229.md), [[Perf] SM100 - add swap AB optimization to CUTLASS FP8 GEMM](../sources/prs/vllm/PR-27284.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Feature] Extend batch invariant torch.compile to B200](../sources/prs/vllm/PR-27856.md), [[Performance] Fused blockwise quant RMS norm](../sources/prs/vllm/PR-27883.md), [[Performance][B200] Fix deepgemm prologue](../sources/prs/vllm/PR-27897.md), [[Kernel] Optimize rms_norm kernel](../sources/prs/vllm/PR-27931.md), [[flashinfer][fix] do not check nvcc availability when using pre-downloaded cubins](../sources/prs/vllm/PR-27990.md), [[Performance][B200] silu_mul_quant: pack scales in int32](../sources/prs/vllm/PR-28358.md), [[Bugfix][Nixl] Fix kernel physical<>logical block_size issue ](../sources/prs/vllm/PR-28677.md), [[Performance] Reduce DeepGEMM N dim restriction from 128 to 64 multiplier ](../sources/prs/vllm/PR-28687.md), [[Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op)](../sources/prs/vllm/PR-29213.md), [[Perf] Disable DeepGEMM MoE by default when TP=8 is used](../sources/prs/vllm/PR-29346.md), [[Bugfix] Defunctionalize TRTLLM AR+Norm op for avoiding extra clone kernel before it](../sources/prs/vllm/PR-29631.md), [[Kernel]Support W4A8 Grouped GEMM on Hopper](../sources/prs/vllm/PR-29691.md), [[Bugfix] Fix mismatched nvfp4 gemm output shape](../sources/prs/vllm/PR-29742.md), [[Bugfix] Fix flashinfer ar+norm kernel not available issue](../sources/prs/vllm/PR-29960.md), [[Bugfix] Fix DeepGEMM after #29546 ](../sources/prs/vllm/PR-30267.md), [[Bugfix] Fix fp8 DeepGemm compilation issues](../sources/prs/vllm/PR-30336.md), [[BugFix] Fix `AttributeError: 'MergedColumnParallelLinear' object has no attribute 'weight_scale'`](../sources/prs/vllm/PR-30399.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Perf] enable flashinfer rotary_embedding custom ops in DeepSeek rotary](../sources/prs/vllm/PR-30729.md), [ [FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/vllm/PR-31099.md), [[Bugfix][Hardware][AMD] Consolidate FP8 min/max values helper function](../sources/prs/vllm/PR-31106.md), [[BugFix] add select_gemm_impl on CompressedTensorsWNA16MoEMethod to support LoRA](../sources/prs/vllm/PR-31453.md), [[FIX] Add NO_MUL activation support for modular kernel path](../sources/prs/vllm/PR-31528.md), [[Perf] Add opt-in SM100 Oink RMSNorm custom-op path](../sources/prs/vllm/PR-31828.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [[BugFix] Fix DeepSeek-V3.1 + DeepGEMM incompatible scale shapes](../sources/prs/vllm/PR-32361.md), [[Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper](../sources/prs/vllm/PR-32619.md), [[Performance] Tune Mamba selective scan kernel for B200](../sources/prs/vllm/PR-32873.md), [[Feature] Support CPU Offloading without Pytorch Pinned Memory that leads to doubled allocation](../sources/prs/vllm/PR-32993.md), [[Kernel] Apply 256bit LDG/STG To Activation Kernels](../sources/prs/vllm/PR-33022.md), [[Bugfix] Fix quant RMS norm fusion for quantization with TMA-aligned scales](../sources/prs/vllm/PR-33255.md), [[Bugfix] Register fp8 cutlass_group_gemm as supported for only SM90+SM100](../sources/prs/vllm/PR-33285.md), [[Feature][Core] Support Fabric detection to adapt the MNNVL protocol for the GB series](../sources/prs/vllm/PR-33540.md), [[Perf] Disable clean_logits in deepgemm fp8_mqa_logits kernel](../sources/prs/vllm/PR-33568.md), [[ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup)](../sources/prs/vllm/PR-34302.md), [[Bugfix] Enforce DeepGEMM when using sparse_attn_indexer on CUDA](../sources/prs/vllm/PR-34374.md), [[Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup)](../sources/prs/vllm/PR-34758.md), [[Bugfix] Gate 256-bit instructions to CUDA 12.9+](../sources/prs/vllm/PR-34791.md), [[Perf] Enable FlashInfer DeepGEMM swapAB on SM90 by default](../sources/prs/vllm/PR-34924.md), [[Bug][DSV3.2] Always prepare metadata for DeepGEMM Sparse Attention](../sources/prs/vllm/PR-35075.md), [[Performance] Cublas Bf16 Gate with Fp32 Output](../sources/prs/vllm/PR-35121.md), [[Bugfix] Fix DSV3 kernels breaking _C and _moe_C on unsupported arches](../sources/prs/vllm/PR-35123.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[MoE][Perf] Wrap DSV3 QKVAProj GEMM in custom op for torch.compile](../sources/prs/vllm/PR-35751.md), [[Mamba] Add stochastic rounding support](../sources/prs/vllm/PR-35753.md), [[MoE] Move PF Methods to Folder](../sources/prs/vllm/PR-35927.md), [[Kernel] Add FlashInfer MoE A2A Kernel](../sources/prs/vllm/PR-36022.md), [[Bugfix] Warm up Triton autotuner for GDN layers during V1 profiling](../sources/prs/vllm/PR-36599.md), [[GDN] add a config for gdn kernel selection](../sources/prs/vllm/PR-36647.md), [[Bug] Fix FlashInfer MNNVL socket collisions under concurrent vLLM jobs](../sources/prs/vllm/PR-36674.md), [Update Flashinfer to 0.6.6](../sources/prs/vllm/PR-36768.md), [[Bugfix] Fix FlashInfer GDN warmup ValueError on SM90 GPUs](../sources/prs/vllm/PR-36876.md), [[Kernel] Add gpt-oss Router GEMM kernel](../sources/prs/vllm/PR-37205.md), [[UX] Add flashinfer-cubin as CUDA default dep](../sources/prs/vllm/PR-37233.md), [refactor: abstract deepgemm support into platform](../sources/prs/vllm/PR-37519.md), [[Bug] Fix fp8 deepgemm batch invariant](../sources/prs/vllm/PR-37718.md), [[Perf] triton bilinear_pos_embed kernel for ViT](../sources/prs/vllm/PR-37948.md), [[Kernel] Optimize SM120 CUTLASS blockwise FP8 GEMM](../sources/prs/vllm/PR-37970.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [[Kernel] Add swapAB support for SM120 CUTLASS blockwise FP8 GEMM ](../sources/prs/vllm/PR-38325.md), [[CI Bugfix] Pre-download missing FlashInfer headers in Docker build](../sources/prs/vllm/PR-38391.md), [[Bugfix] Enable batch-invariant Triton matmul on all Ampere GPUs (SM 8x) ](../sources/prs/vllm/PR-38427.md), [[Perf] Batch KV cache swap copies via cuMemcpyBatchAsync](../sources/prs/vllm/PR-38460.md), [[Gemma4] Enable Fast Prefill Optimization](../sources/prs/vllm/PR-38879.md), [[Perf] Change Trtllm fp8 MoE to use Shuffled Weights and BlockMajorK Layout](../sources/prs/vllm/PR-38993.md), [[Gemma4] Support quantized MoE ](../sources/prs/vllm/PR-39045.md), [[Refactor] Move NVFP4 GEMM management into NvFp4LinearKernel](../sources/prs/vllm/PR-39129.md), [[Refactor] Move MXFP8 GEMM management into MxFp8LinearKernel](../sources/prs/vllm/PR-39205.md), [Use CU_MEMCPY_SRC_ACCESS_ORDER_ANY for batch KV cache swaps](../sources/prs/vllm/PR-39306.md), [Fix NUMA binding on non-CDMM Grace-Blackwell systems](../sources/prs/vllm/PR-39361.md), [[Perf] Fuse Zero Initializer for FP8 DeepGemm Block Quant Kernel](../sources/prs/vllm/PR-39547.md), [[Bugfix][NIXL] Fix `_logical_to_kernel_block_ids` conversion for non-mamba models](../sources/prs/vllm/PR-39724.md), [[Bugfix] Add Marlin kernel in block scaled mm kernel selection.](../sources/prs/vllm/PR-40105.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [[DSV4] Fuse norm and router for low latency scenario](../sources/prs/vllm/PR-41263.md), [[Spec Decode] Add Gemma4 MTP speculative decoding support](../sources/prs/vllm/PR-41745.md), [Add NVFP4 all-gather GEMM fusion for AsyncTP](../sources/prs/vllm/PR-41882.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [[Kernel] (1/N) Machete - Hopper Optimized Mixed Precision Linear Kernel ](../sources/prs/vllm/PR-7174.md), [[Kernel] (2/N) Machete - Integrate into CompressedTensorsWNA16 and GPTQMarlin](../sources/prs/vllm/PR-7701.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [FP8 Block-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [Gated Dual GEMM (Gate-Up + SwiGLU Fusion)](../wiki/kernels/gated-dual-gemm.md), [Grouped GEMM for MoE](../wiki/kernels/grouped-gemm.md), [NVFP4 GEMM — 4-bit Floating Point Matrix Multiply](../wiki/kernels/nvfp4-gemm.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md) | -| `gemv` | [Twelve Attempts at NVFP4 Batched GEMV](../sources/blogs/amandeep-nvfp4-attempts.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [[None][feat] sm100 weight-only kernel](../sources/prs/TensorRT-LLM/PR-10190.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md) | -| `grouped-gemm` | [Anatomy of a Reward Hack](../sources/blogs/gpu-mode-reward-hack.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [fix: use SM90ArchSpec instead of SM100ArchSpec in sm90_bf16_k_grouped_gemm](../sources/prs/DeepGEMM/PR-270.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Use swizzling instead of padding](../sources/prs/DeepGEMM/PR-86.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[None][perf] Add more optimization options for MOE CuteDSL finalized kernel](../sources/prs/TensorRT-LLM/PR-10042.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [[None][feat] CuteDSL MOE FC1 Enhancement](../sources/prs/TensorRT-LLM/PR-10088.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [[None] [feat] Add test script and raster M for gather fc1 kernel](../sources/prs/TensorRT-LLM/PR-10429.md), [[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth](../sources/prs/TensorRT-LLM/PR-10987.md), [[None][feat] CuteDSL MOE: Add raster along M/N support for blockscaled contiguous backbone kernel](../sources/prs/TensorRT-LLM/PR-12079.md), [[None][feat] Add DWDP (Distributed Weight Data Parallelism) support for MoE inference](../sources/prs/TensorRT-LLM/PR-12136.md), [[TRTLLM-11585][feat] Add CUTEDSL moe backend for nemotron-h](../sources/prs/TensorRT-LLM/PR-12884.md), [[TRTLLM-9685] [feat] Add gather fc1 kernel by cuteDSL](../sources/prs/TensorRT-LLM/PR-9618.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [[Hopper CuTeDSL] Add grouped GEMM kernel example](../sources/prs/cutlass/PR-3091.md), [Support for Group GEMM in CUTLASS Profiler for GeForce and Spark](../sources/prs/cutlass/PR-3092.md), [perf: accelerate blackwell grouped gemm](../sources/prs/flashinfer/PR-1086.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [TVM: support TVM binding for GroupedGemm](../sources/prs/flashinfer/PR-1725.md), [feat: unit-test and api change, w4a8 grouped-gemm fused MoE for SM90](../sources/prs/flashinfer/PR-2193.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [refactor: Port upstream CUTLASS fixes and refactor grouped_gemm_nt_masked GEMM module location](../sources/prs/flashinfer/PR-2503.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [CuteDSL MoE fix redundant output buffer zeroing](../sources/prs/flashinfer/PR-2811.md), [feat: Add CuTe DSL grouped-gemm + combine fusion support](../sources/prs/flashinfer/PR-2944.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [[sgl-kernel][6/7]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-15471.md), [[Feature] Apply Cublas Grouped Gemm kernel](../sources/prs/sglang/PR-3629.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [Fused MoE — FP8 Block-Scale Routing + Dual GEMM](../wiki/kernels/fused-moe.md), [Grouped GEMM for MoE](../wiki/kernels/grouped-gemm.md) | -| `linear-attention` | [Gated Delta Networks](../sources/blogs/gated-delta-net.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [Tiled Flash Linear Attention (TFLA)](../sources/docs/tfla.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md) | -| `mla` | [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [K-Search: LLM Kernel Generation via Co-Evolving Intrinsic World Model](../sources/blogs/k-search-kernel-generation.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[TRTLLM-11285][feat] Fuse indexer wk + weights_proj into single GEMM in TF32 for DS-V3.2](../sources/prs/TensorRT-LLM/PR-12055.md), [[https://nvbugs/5983390][perf] Split MLA DSA custom op for piecewise CUDA graph capture](../sources/prs/TensorRT-LLM/PR-12503.md), [[#12634][feat] AutoDeploy: Support rank 256 MLA in flashinfer_mla](../sources/prs/TensorRT-LLM/PR-12519.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [Flash MLA support](../sources/prs/cutlass/PR-2130.md), [Flash MLA Support - Step 2](../sources/prs/cutlass/PR-2134.md), [[ex77] fix mla split; add fwd lse; add bwd varlen](../sources/prs/cutlass/PR-2366.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [[Cute,Sm100,Fwd] add MLA 64/512 with topk sparsity for MQA 128 heads](../sources/prs/flash-attention/PR-2441.md), [bugfix: import wrapper of mla decode](../sources/prs/flashinfer/PR-1013.md), [misc: fix instrument code for mla profiler](../sources/prs/flashinfer/PR-1014.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [bugfix: temporally disable split-kv in blackwell mla](../sources/prs/flashinfer/PR-1055.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [feat: enable trtllm-gen mla MTP](../sources/prs/flashinfer/PR-1258.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [minor: add trtllm_gen_mla benchmark](../sources/prs/flashinfer/PR-1316.md), [feat: Fused rope fp8 quantize kernel for MLA](../sources/prs/flashinfer/PR-1339.md), [fix: fix trtllm-gen mla error on new interface](../sources/prs/flashinfer/PR-1348.md), [feat: enable trtllm-gen attn speculative decoding verify by decode](../sources/prs/flashinfer/PR-1453.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: Fix FLOPS calculation for bench_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-1640.md), [fix: zero-init workspace buffer for trtllm-gen fmha](../sources/prs/flashinfer/PR-1643.md), [Add benchmark for MLARopeQuantize](../sources/prs/flashinfer/PR-1656.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [Waive / disable test_mla_decode_kernel.py::test_mla_decode_kernel for not sm80 ](../sources/prs/flashinfer/PR-1771.md), [MLA RoPE + quantization fused kernel: shape generalization for MHA / GQA](../sources/prs/flashinfer/PR-1924.md), [minor fix for xqa](../sources/prs/flashinfer/PR-1994.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [use scalar for kv_scale in xqa](../sources/prs/flashinfer/PR-2033.md), [feat: Add flashinfer.rope.rope_quantize_fp8_append_paged_kv_cache (fused RoPE + Q + KV cache, supports MLA/GQA/MHA) ](../sources/prs/flashinfer/PR-2037.md), [feat: add xqa mla backend](../sources/prs/flashinfer/PR-2053.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [[DSR1] Added MLA test](../sources/prs/flashinfer/PR-2100.md), [add tensor scale input for xqa](../sources/prs/flashinfer/PR-2110.md), [feature: make the LSE returned by MLA support base 2 or e #2113](../sources/prs/flashinfer/PR-2114.md), [update xqa license](../sources/prs/flashinfer/PR-2117.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [fix flaky xqa test](../sources/prs/flashinfer/PR-2126.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [refactor: Move mla code from decode.py to mla.py and add to documentation](../sources/prs/flashinfer/PR-2163.md), [[feat] Integrate SGLang concat_mla_k kernel into flashinfer](../sources/prs/flashinfer/PR-2237.md), [Support both 3D and 4D kv_cache shapes in MLA APIs](../sources/prs/flashinfer/PR-2334.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [fix: Fix memory bandwidth calculation in MLA benchmarks](../sources/prs/flashinfer/PR-2479.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [support qk_nope_head_dim for 192 check for GLM-5](../sources/prs/flashinfer/PR-2607.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [[Spark unit test debugging] Fix for tests/attention/test_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-2750.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [feat: FP8 output support for CUTLASS MLA paged attention](../sources/prs/flashinfer/PR-2779.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [[Fmha] Sparse MLA decode kernel selection heuristics](../sources/prs/flashinfer/PR-2836.md), [[fix] bugfix 2856: Fix pre-allocated out shape check in trtllm_batch_decode_with_kv_cache_mla for q_len_per_req > 1](../sources/prs/flashinfer/PR-2876.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16](../sources/prs/flashinfer/PR-3129.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [bugfix: MLA decode should multiply sm_scale by math::log2e](../sources/prs/flashinfer/PR-787.md), [fix rope logic in mla decoding](../sources/prs/flashinfer/PR-793.md), [perf: memory efficient deepseek mla fused page-attention kernel](../sources/prs/flashinfer/PR-804.md), [bugfix: mla page-attention kernel for different page sizes](../sources/prs/flashinfer/PR-810.md), [feat: unlocking MLA for A100](../sources/prs/flashinfer/PR-812.md), [feat: unlock MLA attention for sm89 (L40/L40s/4090)](../sources/prs/flashinfer/PR-814.md), [bugfix: fix the behavior of mla plan function when provided with host tensors](../sources/prs/flashinfer/PR-816.md), [bugfix: bugfix on sm89 MLA](../sources/prs/flashinfer/PR-821.md), [perf: MLA decode kernel implemented by CuTe targeted to SM80](../sources/prs/flashinfer/PR-844.md), [misc: Remove duplicate param set in MLA kernel](../sources/prs/flashinfer/PR-850.md), [unittest: add MLA test cases where kv_len is evenly divided by page_size.](../sources/prs/flashinfer/PR-861.md), [perf: dynamic split-k for MLA](../sources/prs/flashinfer/PR-863.md), [bugfix: fix the behavior of MLA kernel when kv-length is 0](../sources/prs/flashinfer/PR-868.md), [perf: FlashAttention-3 style MLA PageAttention](../sources/prs/flashinfer/PR-887.md), [feat - support mla kvcache store](../sources/prs/flashinfer/PR-888.md), [perf: fix MLA split-k performance bug](../sources/prs/flashinfer/PR-898.md), [perf: tweak the pipeline design of mla kernel](../sources/prs/flashinfer/PR-901.md), [feat: flashinfer intra-kernel profiler](../sources/prs/flashinfer/PR-913.md), [bugfix: fix potential issues of FA3 template loading nans for PageAttention](../sources/prs/flashinfer/PR-945.md), [perf: Use 2WG pipeline design for MLA implementation on Hopper](../sources/prs/flashinfer/PR-952.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [perf: prefetch page indices for mla kernel](../sources/prs/flashinfer/PR-991.md), [3rdparty: upgrade cutlass to 3.9](../sources/prs/flashinfer/PR-997.md), [Disable kernel cutlass_mla_decode on SM103](../sources/prs/sglang/PR-10058.md), [feat: Add FP4 (E2M1) KV Cache Support with Quantization Utilities for MLA](../sources/prs/sglang/PR-10078.md), [[Feature] Add MLAProcess for DeepSeek MLA on NPU](../sources/prs/sglang/PR-10130.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [Enable trtllm mla prefix extend](../sources/prs/sglang/PR-10526.md), [[sgl-kernel] Optimize concat_mla_k kernel](../sources/prs/sglang/PR-10543.md), [Fuse quantize and rope in trtllm_mla MTP](../sources/prs/sglang/PR-10779.md), [disable sm100 for FlashMLA and fast-hadamard-transform in cuda12.6.1](../sources/prs/sglang/PR-11274.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [Use trtllm_mla decode kernel for draft extend in speculative decoding](../sources/prs/sglang/PR-11664.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [[sgl-kernel] support flashmla libtorch](../sources/prs/sglang/PR-11717.md), [Fixed aarch64 flash-mla](../sources/prs/sglang/PR-12009.md), [[DeepseekV32]: use `_concat_mla_absorb_q_general` to replace `torch.cat`](../sources/prs/sglang/PR-12215.md), [[Deepseek V3.2] Enable flashmla_auto with MTP](../sources/prs/sglang/PR-12294.md), [fix seqlen bug for trtllm_mla's draft_extend](../sources/prs/sglang/PR-12295.md), [perf: trtllm mla performance minor improvements](../sources/prs/sglang/PR-12435.md), [[Fix] `concat_mla_absorb_q_kernel` fails for long inputs](../sources/prs/sglang/PR-12453.md), [[Ascend] Support enable-mixed-chunk in non-MLA scenarios](../sources/prs/sglang/PR-12491.md), [[sgl-kernel] support custom fp8 flashmla kernel](../sources/prs/sglang/PR-13087.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Fix target MLA with eagle3 support for PD disaggregation](../sources/prs/sglang/PR-13555.md), [[BugFix] fix prefixcache performance and accuracy on ascend](../sources/prs/sglang/PR-13573.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [fix trtllm mla spec](../sources/prs/sglang/PR-13738.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[bug fix] fix ima with get_mla_kv_buffer_kernel overflow](../sources/prs/sglang/PR-14224.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [[NPU] perf update with kvcache nz & w4a8 quant](../sources/prs/sglang/PR-14423.md), [Add Mistral Large 3 Eagle Support](../sources/prs/sglang/PR-14466.md), [Fix accuracy issue when using a16w16 mla_decode_fwd](../sources/prs/sglang/PR-14936.md), [[sgl-kernel] Update flashmla to include fp8 sparse_mla optimizations](../sources/prs/sglang/PR-15242.md), [[NPU]DeepSeek-V3.2 support npu mlaprolog](../sources/prs/sglang/PR-15381.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [Fix BatchMLAPagedAttentionWrapper query/qo_inptr mismatch for EAGLE](../sources/prs/sglang/PR-15601.md), [Bugfix for ds-vl2](../sources/prs/sglang/PR-15894.md), [enhance accuracy for model kimi-vl-instruct-a3b](../sources/prs/sglang/PR-16076.md), [[NPU]bugfix: fix for dsv3.2 and dsvl2](../sources/prs/sglang/PR-17007.md), [Disable mla persistent kernel when not using fp8 kv_cache](../sources/prs/sglang/PR-17327.md), [[NPU] enhance accuracy for model kimi-vl-a3b-instruct](../sources/prs/sglang/PR-17480.md), [Make flashMLA work on: Cu13, B300](../sources/prs/sglang/PR-17600.md), [[Move sgl-kernel Kernel to JIT] Add JIT concat MLA kernels](../sources/prs/sglang/PR-17889.md), [[Hicache & JIT_kernel] Support page first layout & mla jit kernel](../sources/prs/sglang/PR-18311.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [[AMD] DSR1/V3 use fp8 bmm in MLA for MI300X](../sources/prs/sglang/PR-18624.md), [[sgl-kernel] rebase FlashMLA 0217](../sources/prs/sglang/PR-18902.md), [Support skip-softmax attention](../sources/prs/sglang/PR-19089.md), [[Feature] add feature mla_ag_after_qlora for dsv3.2](../sources/prs/sglang/PR-19428.md), [[NPU] bugs fix for Deepseek models](../sources/prs/sglang/PR-19544.md), [Fix MLA decode path returning unwritten (padded) rows](../sources/prs/sglang/PR-19902.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [Fix streaming session with paged KV cache (SWA/MLA)](../sources/prs/sglang/PR-20070.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[AMD][AITER] Guard _use_mla_ps_kernel with self.use_mla in draft_extend_v2 paths](../sources/prs/sglang/PR-20409.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [test: point DSV3 int8 MLA CI models to lmsys Hugging Face org](../sources/prs/sglang/PR-21561.md), [[DSA] Support trtllm sparse mla kernel for prefill batches ](../sources/prs/sglang/PR-21783.md), [[Bugfix] Fix CUDA graph replay issues in trtllm_mla draft_extend](../sources/prs/sglang/PR-21987.md), [[NPU] enable mla prepare fused kernel only when being mla attn](../sources/prs/sglang/PR-22024.md), [[Disagg][NIXL] Fix heterogeneous TP KV transfer for non-MLA models (same logic with mooncake, Step 1/2 for Qwen3.5 support)](../sources/prs/sglang/PR-22145.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [[DSA] Hopper FP8 FlashMLA KV padding](../sources/prs/sglang/PR-22372.md), [[Fix] Fix accuracy bug in Flashmla sparse MLA kernel](../sources/prs/sglang/PR-22723.md), [Support spec v2 for FlashMLA speculative decoding](../sources/prs/sglang/PR-24640.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [Support draft extend cuda graph for tokenspeed_mla attention backend](../sources/prs/sglang/PR-25489.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [feat: support flashinfer mla attention for deepseek v3](../sources/prs/sglang/PR-3550.md), [feat: support flashinfer mla with prefix cache](../sources/prs/sglang/PR-3643.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [Hierarchical Caching supports MLA](../sources/prs/sglang/PR-4009.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [[Fix] Fix raw_bs bug when using flashinfer mla and eagle](../sources/prs/sglang/PR-4557.md), [avoid cudaStreamSynchronize in DeepSeekV2AttentionMLA](../sources/prs/sglang/PR-4577.md), [Blackwell Cutlass MLA kernel](../sources/prs/sglang/PR-5142.md), [feat: use fa3 mla by default on hopper](../sources/prs/sglang/PR-5210.md), [fix: solve cu118 issue for cutlass mla](../sources/prs/sglang/PR-5331.md), [[PD Bug] fix MLA get_contiguous_buf_infos error](../sources/prs/sglang/PR-5384.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[PD] Fix dynamic port support and MLA buffer for Mooncake](../sources/prs/sglang/PR-5415.md), [BLackwell cutlass mla: Add check for bad page size/block num combinations](../sources/prs/sglang/PR-5431.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Avoid computing lse in Ragged Prefill when there's no prefix.](../sources/prs/sglang/PR-5476.md), [Fuse MLA set kv cache kernel](../sources/prs/sglang/PR-5748.md), [opt flashinfer mla cat](../sources/prs/sglang/PR-5822.md), [Cutlass MLA decode - fix dtype error](../sources/prs/sglang/PR-5868.md), [[Fix] Fix a bug for flashmla to run R1 model](../sources/prs/sglang/PR-5875.md), [KV‑Cache (MHA, MLA): add missing start_layer / end_layer fields to MHATokenToKVPoolHost and MLATokenToKVPoolHost](../sources/prs/sglang/PR-6016.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [Cutlass MLA: Disable split kv due to https://github.com/NVIDIA/cutlass/issues/2274](../sources/prs/sglang/PR-6101.md), [fix: fix MLA for ShardedModelLoader/RemoteModelLoader](../sources/prs/sglang/PR-6287.md), [[PD] Add different TP sizes support for no-MLA models](../sources/prs/sglang/PR-6793.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [Fix cutlass MLA gets almost zero accuracy](../sources/prs/sglang/PR-6998.md), [Tiny fix cutlass_mla_get_workspace_size stub incorrect signature](../sources/prs/sglang/PR-7057.md), [chore: upgrade sgl-kernel v0.1.8.post2](../sources/prs/sglang/PR-7186.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [Minor style and doc fix](../sources/prs/sglang/PR-7228.md), [Fix CPU offloading for MLA memory pool](../sources/prs/sglang/PR-7409.md), [TRTLLM-MLA FP8 path](../sources/prs/sglang/PR-8638.md), [fix mooncake store mla zero copy meta](../sources/prs/sglang/PR-9678.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[Perf] Enable fast math in sparse MLA example](../sources/prs/tilelang/PR-2219.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Attention] Deepseek v3 MLA support with FP8 compute](../sources/prs/vllm/PR-12601.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [Disable chunked prefill and/or prefix caching when MLA is enabled ](../sources/prs/vllm/PR-12642.md), [[AMD][ROCm] Enable DeepSeek model on ROCm](../sources/prs/vllm/PR-12662.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [Squelch MLA warning for Compressed-Tensors Models](../sources/prs/vllm/PR-12704.md), [[VLM] Add MLA with pure RoPE support for deepseek-vl2 models](../sources/prs/vllm/PR-12729.md), [[Kernel] Make rotary_embedding ops more flexible with input shape](../sources/prs/vllm/PR-12777.md), [[Attention] Use FA3 for MLA on Hopper](../sources/prs/vllm/PR-12807.md), [Expand MLA to support most types of quantization](../sources/prs/vllm/PR-13181.md), [[Bugfix] Massage MLA's usage of flash attn for RoCM](../sources/prs/vllm/PR-13310.md), [[Bugfix] Fix max_num_batched_tokens for MLA](../sources/prs/vllm/PR-13620.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[Bugfix] Support MLA for CompressedTensorsWNA16](../sources/prs/vllm/PR-13725.md), [[Kernel] FlashMLA integration](../sources/prs/vllm/PR-13747.md), [[Attention] MLA support for V1](../sources/prs/vllm/PR-13789.md), [[ROCm] Disable chunked prefill/prefix caching when running MLA on non-cuda platforms](../sources/prs/vllm/PR-13844.md), [[Attention] Flash MLA for V1](../sources/prs/vllm/PR-13867.md), [Fix mla prefill context performance](../sources/prs/vllm/PR-13897.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[BugFix] MLA + V1, illegal memory access and accuracy issues](../sources/prs/vllm/PR-14253.md), [[BugFix] Fix prefix caching V0 MLA](../sources/prs/vllm/PR-14255.md), [[Attention] FlashAttn MLA](../sources/prs/vllm/PR-14258.md), [[ROCm] Enable chunked prefill/paged attention in MLA on ROCm](../sources/prs/vllm/PR-14316.md), [[Perf] Reduce MLA CPU overheads in V1](../sources/prs/vllm/PR-14384.md), [[Bugfix] DeepSeek Accuracy](../sources/prs/vllm/PR-14476.md), [[Perf] Improve MLA on V1](../sources/prs/vllm/PR-14540.md), [[BugFix][TritonMLA] Process weights after model loading for GGUF](../sources/prs/vllm/PR-14555.md), [[Attention] Flash Attention 3 - fp8](../sources/prs/vllm/PR-14570.md), [[Kernel][CPU] CPU MLA](../sources/prs/vllm/PR-14744.md), [[Attention] MLA get rid of materialization](../sources/prs/vllm/PR-14770.md), [[Attention] Get rid of mla cache alignment](../sources/prs/vllm/PR-14842.md), [[V1] Default MLA to V1](../sources/prs/vllm/PR-14921.md), [[BugFix] Fix nightly MLA failure (FA2 + MLA chunked prefill, i.e. V1, producing bad results)](../sources/prs/vllm/PR-15492.md), [[Bugfix] Fix cache block size calculation for CPU MLA](../sources/prs/vllm/PR-15848.md), [[FEAT][ROCm]: Support AITER MLA](../sources/prs/vllm/PR-15893.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[Kernel] support merge_attn_states CUDA kernel, 3x speedup](../sources/prs/vllm/PR-16173.md), [[MLA] Simplification to batch P/D reordering](../sources/prs/vllm/PR-16673.md), [[V1] V1 FlashInfer Attention](../sources/prs/vllm/PR-16684.md), [[torch.compile][ROCm] Fuse quantization onto attention using a torch.compile pass](../sources/prs/vllm/PR-16756.md), [[Bugfix] Triton FA function takes no keyword arguments](../sources/prs/vllm/PR-16902.md), [[Bugfix] Add contiguous call inside rope kernel wrapper](../sources/prs/vllm/PR-17091.md), [[BugFix] Fix vllm_flash_attn install issues](../sources/prs/vllm/PR-17267.md), [[Misc][ROCm] Exclude `cutlass_mla_decode` for ROCm build](../sources/prs/vllm/PR-17289.md), [[v1] AttentionMetadata for each layer](../sources/prs/vllm/PR-17394.md), [[v1] Pass BlockTable and KVCacheSpec to AttentionMetadataBuilders](../sources/prs/vllm/PR-17483.md), [[Attention] MLA move o_proj q_proj into cuda-graph region](../sources/prs/vllm/PR-17484.md), [[BugFix] Fix mla cpu - missing 3 required positional arguments](../sources/prs/vllm/PR-17494.md), [[FEAT][ROCm]: Support AITER MLA on V1 Engine](../sources/prs/vllm/PR-17523.md), [[Attention] MLA move rotary embedding to cuda-graph region](../sources/prs/vllm/PR-17668.md), [fix amd triton mla path](../sources/prs/vllm/PR-17871.md), [[Bugfix][ROCm] Fix AITER MLA V1](../sources/prs/vllm/PR-17880.md), [[BugFix][AMD] Compatible patch for AITER lib after 04/20](../sources/prs/vllm/PR-17912.md), [[v1] Support multiple KV cache groups in GPU model runner](../sources/prs/vllm/PR-17945.md), [[BUG] [ROCm] [MLA] Fix variable name bug due to change in variable name in PR #17483](../sources/prs/vllm/PR-17961.md), [[BugFix] FA2 MLA Accuracy Issue](../sources/prs/vllm/PR-18807.md), [[Kernel] Apply torch.Tag.needs_fixed_stride_order only for torch==2.6.0](../sources/prs/vllm/PR-19346.md), [[Bugfix] Enable PP with AITER+V1](../sources/prs/vllm/PR-19822.md), [[Attention] MLA - Flashinfer Ragged Prefill](../sources/prs/vllm/PR-20034.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[Kernel] Flashinfer MLA (trtllm-gen) decode kernel integration](../sources/prs/vllm/PR-21078.md), [[perf] Add fused MLA QKV + strided layernorm](../sources/prs/vllm/PR-21116.md), [[v1][attention] Support Hybrid Allocator + FlashInfer](../sources/prs/vllm/PR-21412.md), [[BugFix] Fix IMA FlashMLA full cuda-graph and DP + Update FlashMLA](../sources/prs/vllm/PR-21691.md), [[Bugfix] Check NVIDIA artifactory is accessible before using flashinfer cubin kernels](../sources/prs/vllm/PR-21893.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [[Log] Warning Once for Cutlass MLA ](../sources/prs/vllm/PR-23137.md), [[ROCm][Aiter] Add triton fp8 bmm kernel for mla](../sources/prs/vllm/PR-23264.md), [[Compile] Fix Compile Warning SM100 Cutlass MLA](../sources/prs/vllm/PR-23287.md), [[Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-23465.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Kernel] Support decode context parallelism on Blackwell with CUTLASS MLA](../sources/prs/vllm/PR-24385.md), [[Feature] Disallow FlashMLA on Blackwell](../sources/prs/vllm/PR-24521.md), [[Bug] Fix `is_flashmla_supported` Check Error](../sources/prs/vllm/PR-24774.md), [[Bugfix][B200] Fix `cutlass_mla` hang](../sources/prs/vllm/PR-24966.md), [[Attention][DCP] Support DCP with query length > 1 (MTP) with FA3](../sources/prs/vllm/PR-25049.md), [[Bug] Fix `returned_lse` not Defined issue](../sources/prs/vllm/PR-25106.md), [[BugFix] Fix MLA assert with CUTLASS MLA](../sources/prs/vllm/PR-25478.md), [[Bugfix] [B200] cutlass_mla - ensure kv_split == 1 for batch size > 1](../sources/prs/vllm/PR-25509.md), [Fuse RoPE and MLA KV-cache write](../sources/prs/vllm/PR-25774.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Spec Decode] Enable efficient speculative decoding with FlashInfer-MLA](../sources/prs/vllm/PR-25984.md), [[Attention] Tune CUTLASS MLA num_splits](../sources/prs/vllm/PR-26846.md), [Prefer FlashAttention MLA as default over FlashMLA](../sources/prs/vllm/PR-27363.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[AMD] Use Decoupled Kernel Block Size to Support AITER MLA block_size=1](../sources/prs/vllm/PR-27715.md), [[Bug] Batch invariant: Fix flash attn MLA `RuntimeError: scheduler_metadata must have shape (metadata_size)`](../sources/prs/vllm/PR-27884.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [bugfix: correct attn output with base 2 or e](../sources/prs/vllm/PR-28840.md), [[BugFix] Fix async-scheduling + FlashAttn MLA](../sources/prs/vllm/PR-28990.md), [[DeepSeek + LMCache Multiprocess] handle MLA for deepseek model + LMCache Multiprocess connector](../sources/prs/vllm/PR-29039.md), [[Feature] Batch invariant: Enable `TRITON_MLA` without prefix-caching](../sources/prs/vllm/PR-29125.md), [[perf] Use direct copy (broadcast) instead of cat for k_nope/k_pe in MLA prefill](../sources/prs/vllm/PR-29710.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[Perf] Improve fp8 quant in mla; replace ReduceSum with ReduceScatterSum](../sources/prs/vllm/PR-29795.md), [[SpecDecode] Simplified alternative padded-speculation acceptance rate fix](../sources/prs/vllm/PR-29845.md), [[Quantization] fix: overflow with static per-tensor scaling](../sources/prs/vllm/PR-29867.md), [[ROCm] add fallback for aiter fp8 decode mla](../sources/prs/vllm/PR-30005.md), [[ROCm][Bugfix] Add MLACommonMetadata to allowed attention types for speculative decoding](../sources/prs/vllm/PR-30430.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[perf] Integrate flashinfer concat_mla_k](../sources/prs/vllm/PR-31171.md), [[Bugfix][Hardware][AMD] Fix exception types in AITER MLA FP8 check](../sources/prs/vllm/PR-31177.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][Hardware][AMD] Fix last_page_len calculation in AITER MLA decode](../sources/prs/vllm/PR-31282.md), [fixed mypy warnings for files vllm/v1/attention with TEMPORARY workaround](../sources/prs/vllm/PR-31465.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[4/N][Attention] Move MLA common to model_executor](../sources/prs/vllm/PR-32060.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [fix: Add glm4_moe_lite to MLA detection](../sources/prs/vllm/PR-32614.md), [[Bugfix][Attention] Explicitly report support for kv_cache_dtype bfloat16](../sources/prs/vllm/PR-32795.md), [[Attention] FA4 integration](../sources/prs/vllm/PR-32974.md), [[Attention] Use `has_flashinfer` helper](../sources/prs/vllm/PR-33177.md), [Triton MLA perf fixes](../sources/prs/vllm/PR-33529.md), [[Bugfix] Fix sparse MLA metadata building](../sources/prs/vllm/PR-33579.md), [[Bugfix] fix DeepSeek R1 with CUTLASS MLA Broken on B200](../sources/prs/vllm/PR-33637.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [Reapply [Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-34043.md), [fix(cpu): fix mla_decode compilation on x86 without AVX512](../sources/prs/vllm/PR-34052.md), [[BugFix] Add support for MTP num_speculative_tokens > 1 with sparse MLA](../sources/prs/vllm/PR-34552.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [[Bugfix] Fix MLA attention crash with AWQ/GPTQ quantized models](../sources/prs/vllm/PR-34695.md), [[Attention] Use FA4 for MLA prefill](../sources/prs/vllm/PR-34732.md), [[Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup)](../sources/prs/vllm/PR-34758.md), [[Model Bash][DSR1] Add selective dynamic shape marking for CustomOp](../sources/prs/vllm/PR-34900.md), [[Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2](../sources/prs/vllm/PR-34917.md), [[Bug][DSV3.2] Always prepare metadata for DeepGEMM Sparse Attention](../sources/prs/vllm/PR-35075.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[Bugfix] Fix KV Scale loading for MLA Models](../sources/prs/vllm/PR-35430.md), [[ROCm] Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5/Linear)](../sources/prs/vllm/PR-35850.md), [[Perf] Support FP8 KV cache for Flashinfer MLA Sparse](../sources/prs/vllm/PR-35891.md), [[LMCache] Pass TP size in lookup for MLA multi-reader locking](../sources/prs/vllm/PR-36129.md), [Add 320 dimension size support to MLA](../sources/prs/vllm/PR-36161.md), [[Bugfix][MLA] Add logits size budget to sparse indexer prefill chunking](../sources/prs/vllm/PR-36178.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [mla: don't update kv cache on dummy forwards](../sources/prs/vllm/PR-36282.md), [Kimi k2.5 MLA based eagle3](../sources/prs/vllm/PR-36361.md), [[Bugfix][Sparse MLA] report indexer CG support properly](../sources/prs/vllm/PR-36519.md), [[ROCm] Utilize persistent MLA kernel from AITER](../sources/prs/vllm/PR-36574.md), [[ROCm][Perf] Allow MTP lens > 1 in Sparse MLA](../sources/prs/vllm/PR-36681.md), [[DSV3.2][MTP] Optimize Indexer MTP handling](../sources/prs/vllm/PR-36723.md), [[Feat][Bugfix] Enable additional dimension for Flashinfer MLA and fix routing dtype](../sources/prs/vllm/PR-36931.md), [[MTP][Sparse MLA] Take advantage of native MTP support in indexer when possible](../sources/prs/vllm/PR-36982.md), [[Bugfix] Fix KV scales inconsistency in fp8 MLA & FlashInfer kv_cache_dtype "auto" leading to gibberish](../sources/prs/vllm/PR-37054.md), [[Bugfix] Disable cross-layer KV cache for MLA attention backends](../sources/prs/vllm/PR-37090.md), [[Benchmark] Improvements to attention benchmark script](../sources/prs/vllm/PR-37115.md), [[XPU] support MLA model on Intel GPU](../sources/prs/vllm/PR-37143.md), [[Misc] Add `float16` to `CacheDType`](../sources/prs/vllm/PR-37199.md), [[Perf] Set Flashinfer sparse MLA as default backend for FP8 kv cache](../sources/prs/vllm/PR-37252.md), [[Perf][Kernel] Persistent TopK scheduler: unified CUDAGraph-safe kernel with dynamic per-row dispatch - DeepSeek-V3.2 DSA decode](../sources/prs/vllm/PR-37421.md), [[BugFix] Allow qk_nope_head_dim=192 in FlashInfer MLA backend checks](../sources/prs/vllm/PR-37475.md), [Fix KV Offloading + MLA AssertionError by using num_kv_heads=1 in cpu…](../sources/prs/vllm/PR-37536.md), [[Performance] Remove unnecessary zero-fill of MLA decode output tensor in Aiter backend](../sources/prs/vllm/PR-37539.md), [[Bugfix][ROCm] Fix lru_cache on paged_mqa_logits_module](../sources/prs/vllm/PR-37547.md), [[Test] Only Run MLA model when user explicitly set for batch invariance](../sources/prs/vllm/PR-37719.md), [[ROCm][perf] fix Aiter sparse MLA with MTP>1](../sources/prs/vllm/PR-37887.md), [[Bugfix][MLA] Change default SM100 MLA prefill backend back to TRT-LLM](../sources/prs/vllm/PR-38562.md), [[ROCm] Fix aiter persistent mode mla with q/o nhead<16 for kimi-k2.5 tp8](../sources/prs/vllm/PR-38615.md), [Fix MLA runs when use_inductor_graph_partition=True](../sources/prs/vllm/PR-38631.md), [[LMCache][MP] optimize save when mla enabled](../sources/prs/vllm/PR-38810.md), [[Attention][MLA] Re-enable FA4 as default MLA prefill backend](../sources/prs/vllm/PR-38819.md), [[Refactor] Improve indexer decode path metadata preparation](../sources/prs/vllm/PR-38865.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [[Bug] Fix rocm sparse attn indexer issue](../sources/prs/vllm/PR-39225.md), [[MLA] Optimize mla indexer prepare uniform decode for MTP > 1](../sources/prs/vllm/PR-39458.md), [[Mooncake] Fix mixed MLA+Eagle block-size validation](../sources/prs/vllm/PR-39596.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[Performance][DSR1]: Fused RoPE+KVCache+q_concat for MLA](../sources/prs/vllm/PR-40392.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[Bugfix] Fix TRTLLM ragged MLA prefill workspace warmup](../sources/prs/vllm/PR-42112.md), [[ROCm] [Bugfix] Fix DeepSeek V4 Functionality and Accuracy](../sources/prs/vllm/PR-42810.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [[Model Refactoring] Move deepseek_v4_ops to models/deepseek_v4 [3/N]](../sources/prs/vllm/PR-43073.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [Sparse MLA (DeepSeek V3.2)](../wiki/kernels/sparse-mla.md) | -| `moe` | [K-Search: LLM Kernel Generation via Co-Evolving Intrinsic World Model](../sources/blogs/k-search-kernel-generation.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [[None][perf] Add more optimization options for MOE CuteDSL finalized kernel](../sources/prs/TensorRT-LLM/PR-10042.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [[None][feat] CuteDSL MOE FC1 Enhancement](../sources/prs/TensorRT-LLM/PR-10088.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [[TRTLLM-10147][perf] Balanced random MoE workload generator for CuteDSL kernel UT, autotuner and layerwise benchmark](../sources/prs/TensorRT-LLM/PR-10279.md), [[None] [feat] Add densegemm backend for MoE](../sources/prs/TensorRT-LLM/PR-10479.md), [[None][feat] MiniMax M2 support](../sources/prs/TensorRT-LLM/PR-10532.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[None][feat] TRT-LLM Gen MoE finalize kernel optimization](../sources/prs/TensorRT-LLM/PR-11501.md), [[None][feat] Add support for expert_number<=2048 and K<=32](../sources/prs/TensorRT-LLM/PR-11510.md), [[None][fix] Fix int4 awq for sm120/121](../sources/prs/TensorRT-LLM/PR-11561.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[https://nvbugs/5885070][fix] fix deepeplowlatency with cutedsl moe backend](../sources/prs/TensorRT-LLM/PR-11769.md), [[TRTLLM-10990][feat] Fuse SwiGLU and quant into shared expert](../sources/prs/TensorRT-LLM/PR-11897.md), [[None][feat] GLM 5 support and DSA MTP fixes](../sources/prs/TensorRT-LLM/PR-11990.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[https://nvbugs/5955188][fix] Fix harmony parsers and WAR routing PDL for agentic coding use cases](../sources/prs/TensorRT-LLM/PR-12046.md), [[None][feat] CuteDSL MOE: Add raster along M/N support for blockscaled contiguous backbone kernel](../sources/prs/TensorRT-LLM/PR-12079.md), [[None][feat] Add DWDP (Distributed Weight Data Parallelism) support for MoE inference](../sources/prs/TensorRT-LLM/PR-12136.md), [[None][feat] Add fused allreduce+RMSNorm op and optional residual in …](../sources/prs/TensorRT-LLM/PR-12201.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[None][perf] add Dynamic SMEM block routing in MOE](../sources/prs/TensorRT-LLM/PR-12456.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[None][feat] Add bf16 trtllm-gen moe support through flashinfer.](../sources/prs/TensorRT-LLM/PR-12738.md), [[TRTLLM-11797][feat] Add cutedsl moe backend supporting for qwen3.5.](../sources/prs/TensorRT-LLM/PR-12799.md), [[TRTLLM-11585][feat] Add CUTEDSL moe backend for nemotron-h](../sources/prs/TensorRT-LLM/PR-12884.md), [[#12784][feat] AutoDeploy: Optimize DeepSeek-R1 model performance](../sources/prs/TensorRT-LLM/PR-12946.md), [[None][fix] Propagate init_load_balancer to DeepGemmFusedMoE in create_moe_backend](../sources/prs/TensorRT-LLM/PR-13207.md), [[TRTLLM-11127][feat] add W4A8_MXFP4_FP8 MoE unit test support](../sources/prs/TensorRT-LLM/PR-13401.md), [[None][perf] Extend customMoeRouting kernel to support Qwen3.5](../sources/prs/TensorRT-LLM/PR-13433.md), [[None][feat] Enable EPLB for DeepSeek-V4](../sources/prs/TensorRT-LLM/PR-13595.md), [[None][feat] Add bf16 trtllm moe through flashinfer.](../sources/prs/TensorRT-LLM/PR-13689.md), [[None][fix] Plumb swiglu_limit through DeepGEMM and TRTLLMGen FP8 fused MoE](../sources/prs/TensorRT-LLM/PR-13767.md), [[None][perf] FC2 DenseGEMM autotune: split-K, swap_ab, fine-grained tuning buckets](../sources/prs/TensorRT-LLM/PR-13833.md), [[None][feat] enable TRTLLM-Gen internal routing](../sources/prs/TensorRT-LLM/PR-13997.md), [[https://nvbugs/6152892][fix] Fix Triton MOE memory free when no swizzling enabled](../sources/prs/TensorRT-LLM/PR-14069.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][fix] Avoid dp_size x ep_size double-count in MegaMoEDeepGemm SymmBuffer](../sources/prs/TensorRT-LLM/PR-14213.md), [[None][fix] Update the OSS headers in derived FLA ops and AD modeling code](../sources/prs/TensorRT-LLM/PR-14281.md), [[https://nvbugs/6095421][fix] Update resolve_moe_backend](../sources/prs/TensorRT-LLM/PR-14282.md), [[None][chore] Update Claude Code agents and skills](../sources/prs/TensorRT-LLM/PR-14344.md), [[None][chore] Fix kernel launch param and add TRTLLM MoE backend test](../sources/prs/TensorRT-LLM/PR-7524.md), [[None][fix] Fix and add test for TRTLLM MoE backend](../sources/prs/TensorRT-LLM/PR-7755.md), [[TRTLLM-8637][feat] Optimize the routing kernel for DeepseekV3 (MoE CUTLASS backend); Add support for 384 experts (MoE TRTLLM backend)](../sources/prs/TensorRT-LLM/PR-7761.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [[TRTLLM-8827] [feat] Enable low precision alltoall for Cutlass and TRTLLMGen backends](../sources/prs/TensorRT-LLM/PR-8675.md), [[None][feat] Enable EPLB for trtllm-gen and cutlass backend](../sources/prs/TensorRT-LLM/PR-8886.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[None][fix] support topk autotuner input for expert slot per group larger than 32](../sources/prs/TensorRT-LLM/PR-9087.md), [[None][feat] TRT-LLM Gen MoE optimize DeepSeek Fp8 activation kernel](../sources/prs/TensorRT-LLM/PR-9175.md), [[TRTLLM-8958][feat] and [TRTLLM-8960]: create ConfigurableMoE and support TRTLLMGenFusedMoE as backend](../sources/prs/TensorRT-LLM/PR-9486.md), [[TRTLLM-9685] [feat] Add gather fc1 kernel by cuteDSL](../sources/prs/TensorRT-LLM/PR-9618.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [[None][feat] Fused kernels (qknormrope + moe routing) and two-model MTP support for glm4moe](../sources/prs/TensorRT-LLM/PR-9852.md), [Blockscaled Ragged Contiguous Grouped Gemm for MoEs](../sources/prs/cutlass/PR-2790.md), [feat: add trtllm all-reduce (non-MoE)](../sources/prs/flashinfer/PR-1096.md), [feat: add trtllm moe_allreduce_fusion](../sources/prs/flashinfer/PR-1108.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [bugfix: Fix test and output shape of fp4 quantize](../sources/prs/flashinfer/PR-1114.md), [feat: add trtllm all-reduce fusion](../sources/prs/flashinfer/PR-1131.md), [MNNVL MoE All-to-All Support](../sources/prs/flashinfer/PR-1134.md), [feat: add finalize_moe_allreduce from trtllm](../sources/prs/flashinfer/PR-1159.md), [feat: update non-fused moe](../sources/prs/flashinfer/PR-1161.md), [feat: enable and update all-reduce fused quantization](../sources/prs/flashinfer/PR-1164.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [Patch fp8 cubin availability](../sources/prs/flashinfer/PR-1240.md), [Remove sm100+ requirment for trtllm allreduce kernels](../sources/prs/flashinfer/PR-1249.md), [Add shuffle matrix flag](../sources/prs/flashinfer/PR-1272.md), [Bug fix: guard fp8 e8m0 and e2m1 compile ](../sources/prs/flashinfer/PR-1287.md), [Remove FAST_BUILD FLAG for MOE](../sources/prs/flashinfer/PR-1291.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [feat: Add weight layout option for trtllm-gen fused moe](../sources/prs/flashinfer/PR-1297.md), [perfix: use lightweight API to query device property](../sources/prs/flashinfer/PR-1298.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [Support loading autotuned results from json for cutlass fp4 moe backends](../sources/prs/flashinfer/PR-1310.md), [Make Fp8 MoE routing_bias optional](../sources/prs/flashinfer/PR-1319.md), [refactor: Improved metainfo for trtllm-gen kernels](../sources/prs/flashinfer/PR-1328.md), [feature: add fp4 mm using trtllm backend](../sources/prs/flashinfer/PR-1355.md), [Update autotune results for the nvfp4 cutlass moe backends for v0.2.9](../sources/prs/flashinfer/PR-1361.md), [bugfix: fixed cutlass fused moe usage of FP4QuantizationSFLayout::SWIZZLED](../sources/prs/flashinfer/PR-1371.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [Fix trtllm moe launcher local_num_experts](../sources/prs/flashinfer/PR-1398.md), [Add Mxfp4 trtllm-gen moe unit tests](../sources/prs/flashinfer/PR-1399.md), [[bugfix] Fix compilation failure when compiling csrc/trtllm_moe_allreduce_fusion.cu](../sources/prs/flashinfer/PR-1410.md), [Faster weight processing (moe nvfp4)](../sources/prs/flashinfer/PR-1412.md), [Fix redundant kernels in moe](../sources/prs/flashinfer/PR-1428.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [bugfix: Verify num_experts greater or equal to local_experts + offset](../sources/prs/flashinfer/PR-1469.md), [feat: Enable multiple fused-moe backends](../sources/prs/flashinfer/PR-1472.md), [tuner: Trtllm-gen Fp4 MoE Autotunner](../sources/prs/flashinfer/PR-1475.md), [fix missing enable_pdl argument in trtllm-gen fp4 moe](../sources/prs/flashinfer/PR-1480.md), [fix: update cutedsl masked moe gemm](../sources/prs/flashinfer/PR-1488.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [fix: update masked moe gemm fp4 tensor reshape](../sources/prs/flashinfer/PR-1495.md), [Support cuda<12.8 built for trtllm_allreduce_fusion.](../sources/prs/flashinfer/PR-1508.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [bugfix: Fix compile error for undefined swizzle enum.](../sources/prs/flashinfer/PR-1530.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute](../sources/prs/flashinfer/PR-1547.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [Add mnnvl_moe_alltoallv_prepare_without_allgather](../sources/prs/flashinfer/PR-1550.md), [fix: separate out fp4 lib into sm90 and sm100 versions, add oob checking in fused moe](../sources/prs/flashinfer/PR-1565.md), [bugfix: fix cuda version guard macros](../sources/prs/flashinfer/PR-1571.md), [update trtllm-gen fp4 autotuner and routing](../sources/prs/flashinfer/PR-1573.md), [refactor: Expose calculate_tile_tokens_dim function](../sources/prs/flashinfer/PR-1581.md), [bugfix: Fix arg passing to TORCH_CHECK and TORCH_WARN macros](../sources/prs/flashinfer/PR-1582.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [test: update fused_moe test to random scale factor](../sources/prs/flashinfer/PR-1665.md), [Refactor Blackwell unit test scripts](../sources/prs/flashinfer/PR-1667.md), [test: better fp8 quantization init for fused_moe test](../sources/prs/flashinfer/PR-1674.md), [Support Kimi-K2 for TRT: templatize number of experts](../sources/prs/flashinfer/PR-1696.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [perf: Add tuning config for cutlass moe for a hardware](../sources/prs/flashinfer/PR-1716.md), [Fix DeepSeek quality for TRTLLM fused MoE routing](../sources/prs/flashinfer/PR-1723.md), [bugfix: partially fix tests/test_trtllm_gen_fused_moe.py unit test failure](../sources/prs/flashinfer/PR-1724.md), [tests: xfail moe quantization classes mxfp8_bf16 UTs on sm103 ](../sources/prs/flashinfer/PR-1754.md), [add test case for trtllm gen fused moe with kimi k2 problem sizes](../sources/prs/flashinfer/PR-1768.md), [fix: fp4 moe on sm120](../sources/prs/flashinfer/PR-1817.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [Update the routing for TRTLLMGEN to support kimi k2 and qwen](../sources/prs/flashinfer/PR-1831.md), [feat: Add FP4 TRTLLM-Gen throughput MOE batched gemms](../sources/prs/flashinfer/PR-1882.md), [Feature: Support Relu2 activation in fused MoE](../sources/prs/flashinfer/PR-1954.md), [Update trtllm-gen fused moe routing kernel and add more kernels](../sources/prs/flashinfer/PR-1955.md), [Fix: Verify scales are not None for Cutlass FP8 FusedMoE](../sources/prs/flashinfer/PR-1961.md), [Feature: Add support for L40 FusedMoE in cutlass path](../sources/prs/flashinfer/PR-1973.md), [feat: autotune tile_tokens_dim in trtllm-gen MOE](../sources/prs/flashinfer/PR-1980.md), [Bugfix: Change get() -> GetDLTensorPtr() in cutlass FusedMoE validations](../sources/prs/flashinfer/PR-1995.md), [Feature: Support non-gated activation in cutlass fused MoE nvfp4](../sources/prs/flashinfer/PR-2011.md), [[feat] Refactor trtllmgen MOE and add Bf16 trtllmgen moe](../sources/prs/flashinfer/PR-2014.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE](../sources/prs/flashinfer/PR-2025.md), [Enable renormalize(naive) routing for fp8 per-tensor](../sources/prs/flashinfer/PR-2030.md), [Fix dtype of output scales from mnnvl_moe_alltoallv_prepare_without_allgather](../sources/prs/flashinfer/PR-2048.md), [[BUG] Fix trtllm-gen fp4 moe renormalize routing](../sources/prs/flashinfer/PR-2049.md), [Add support for topkPacked input in block-level renormalize](../sources/prs/flashinfer/PR-2051.md), [Fix moe fp8 failure for sm121](../sources/prs/flashinfer/PR-2061.md), [perf: TRT-LLM MoE Block-FP8 activation optimization](../sources/prs/flashinfer/PR-2063.md), [[Test] Optimize test_trtllm_gen_fused_moe.py](../sources/prs/flashinfer/PR-2072.md), [Patch sm103 for 3xfp4 moe generation](../sources/prs/flashinfer/PR-2082.md), [refactor: update dpsk fused_moe test [1]](../sources/prs/flashinfer/PR-2088.md), [refactor: pass hopper deepgemm include directory through python](../sources/prs/flashinfer/PR-2090.md), [perf: TRT-LLM Gen finalize kernel optimization](../sources/prs/flashinfer/PR-2092.md), [refactor: update dpsk fused_moe test [2]](../sources/prs/flashinfer/PR-2097.md), [Port TRT-LLM communication kernels to flashinfer](../sources/prs/flashinfer/PR-2102.md), [enable sm103 moe dsl backend](../sources/prs/flashinfer/PR-2149.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [Add data type check for deepseek fp4 moe](../sources/prs/flashinfer/PR-2165.md), [Rename noauxtc to fused_topk_deepseek](../sources/prs/flashinfer/PR-2181.md), [Fix for moe on sm110](../sources/prs/flashinfer/PR-2190.md), [feat: unit-test and api change, w4a8 grouped-gemm fused MoE for SM90](../sources/prs/flashinfer/PR-2193.md), [feat: Support unpadded output hidden size for trtllm_fp4_block_scale_moe](../sources/prs/flashinfer/PR-2217.md), [fix: add DeepSeek routing for Bf16xBf16 and MxIntxBf16 TRT-LLM Gen MoE](../sources/prs/flashinfer/PR-2234.md), [refactor: pull trtllm-gen batch-gemm/gemm headers from artifactory; update tma descriptor shape init](../sources/prs/flashinfer/PR-2235.md), [test: Fix MNNVL tests to skip when container lacks SYS_PTRACE capability](../sources/prs/flashinfer/PR-2245.md), [feat: Support numLocalTokens=0 for moe All-to-all](../sources/prs/flashinfer/PR-2247.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [feat: expose swizzled_input_sf parameter for CUTLASS fused MOE](../sources/prs/flashinfer/PR-2330.md), [Optimize quantization function in large problem size](../sources/prs/flashinfer/PR-2343.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [feat: update trtllm-gen MoE cubins](../sources/prs/flashinfer/PR-2416.md), [bugfix: fix stub generation directory in fused_moe module](../sources/prs/flashinfer/PR-2445.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [fix: blockscale moe routine supports non-DS routing](../sources/prs/flashinfer/PR-2476.md), [fix: add support check for gemm config for cutlass moe](../sources/prs/flashinfer/PR-2495.md), [Feat: Trtllm-gen MxFP8 MoE integration](../sources/prs/flashinfer/PR-2505.md), [fix: W4A8 autotune crash in cutlass_fused_moe profiler workspace](../sources/prs/flashinfer/PR-2564.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [tests: add bias testing to nvfp4 moe](../sources/prs/flashinfer/PR-2585.md), [fix: trtllm_mxint4_block_scale_moe unit test to index output list](../sources/prs/flashinfer/PR-2627.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [benchmark: Add MXFP4/MXFP8 quantization mode support to FP4 MoE benchmark](../sources/prs/flashinfer/PR-2635.md), [[fp8_blockwise]Fix int32 overflow in TRTLLM fused MoE activation kernel](../sources/prs/flashinfer/PR-2642.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [fix: Add fused MOE and GEMM AOT modules for SM121](../sources/prs/flashinfer/PR-2654.md), [feat: Add support for TRTLLM MXFP8 non-gated MoE with ReLU2](../sources/prs/flashinfer/PR-2707.md), [fix: Add SM120 (RTX Blackwell desktop) support for NVFP4 MoE kernels](../sources/prs/flashinfer/PR-2725.md), [Support in-place update for `trtllm_fp8_block_scale_moe`](../sources/prs/flashinfer/PR-2739.md), [misc: Update gemm/batched gemm cubins from trtllm-gen, gemm header refactor](../sources/prs/flashinfer/PR-2740.md), [[feat] Add 2048 experts and 32 Top K ](../sources/prs/flashinfer/PR-2744.md), [Upgrade cutlass 4.2.1 -> 4.4.2](../sources/prs/flashinfer/PR-2798.md), [CuteDSL MoE fix redundant output buffer zeroing](../sources/prs/flashinfer/PR-2811.md), [fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE](../sources/prs/flashinfer/PR-2821.md), [fix: int32 overflow in `trtllm_fp4_block_scale_moe` causing "Unsupported hidden state scale shape" for EP32+ configs](../sources/prs/flashinfer/PR-2853.md), [Add support for Relu2 in BF16 fused MoE](../sources/prs/flashinfer/PR-2864.md), [fix: add cute dsl moe utils to AOT](../sources/prs/flashinfer/PR-2872.md), [Fix silent bug with FP8 per tensor non-gated MoE](../sources/prs/flashinfer/PR-2882.md), [fix: snap weight_scale_vec_size to handle block_scale_interleave padding for SM120](../sources/prs/flashinfer/PR-2898.md), [[NVIDIA] fix(jit): enable GDC for CUTLASS fused MoE PDL — prevent random crashes on SM12x](../sources/prs/flashinfer/PR-2913.md), [fix: Fix autotuner crash on meta-device tensor in trtllm_fp4_block_scale_routed_moe](../sources/prs/flashinfer/PR-2916.md), [feat: add Relu2 (squared ReLU) activation support in CUTLASS MoE backend](../sources/prs/flashinfer/PR-2926.md), [[Perf] Refactor MoE autotuning to set valid topk ids in routed MoE tuning](../sources/prs/flashinfer/PR-2942.md), [Fused moe all-reduce routed scaling factor + quant support](../sources/prs/flashinfer/PR-2966.md), [feat(comm): add MOE Finalize/Reduction patterns to unified allreduce_fusion API](../sources/prs/flashinfer/PR-2982.md), [fix: restore SM120 CUTLASS MoE tile candidate removed by #2927 (test_trtllm_cutlass_fused_moe.py)](../sources/prs/flashinfer/PR-2984.md), [perf: Optimize CUTLASS MoE helper kernels for small-batch decode workloads](../sources/prs/flashinfer/PR-3014.md), [fix: extend moe alltoall top-k specializations](../sources/prs/flashinfer/PR-3021.md), [[feat] Add routing_replay_out support to MoE kernels and Python API](../sources/prs/flashinfer/PR-3024.md), [Prevent MoE autotuner buffer overflow on large token buckets](../sources/prs/flashinfer/PR-3025.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [fused_moe: pre-filter SM89 tactics with zero occupancy on SM120 Blackwell (fix review feedback on #2764)](../sources/prs/flashinfer/PR-3032.md), [feat: Add b12x CuTe DSL fused MoE for SM120](../sources/prs/flashinfer/PR-3066.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [fix(sm12x): fix micro-kernel workspace sizing when routed_rows > num_local_experts](../sources/prs/flashinfer/PR-3191.md), [fix(cute_dsl/moe): make autotuner bucket configuration adapt to runtime input](../sources/prs/flashinfer/PR-3216.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [[Bugfix] Fix fused MoE autotuning correctness issues by filtering clusterDimZ](../sources/prs/flashinfer/PR-3227.md), [Update moe gemm](../sources/prs/flashinfer/PR-3239.md), [fix(cute_dsl/moe): unbias autotuner profiling for tile_size enumeration](../sources/prs/flashinfer/PR-3252.md), [feat(moe): add SM120 W4A16 b12x kernels](../sources/prs/flashinfer/PR-3271.md), [feat(cute_dsl/moe): deterministic balanced autotune profile inputs](../sources/prs/flashinfer/PR-3286.md), [Ep api design - Build Infra dependencies](../sources/prs/flashinfer/PR-3315.md), [[feat] Add gemma RMS AR fusion](../sources/prs/flashinfer/PR-3322.md), [feat(cute_dsl/moe): add `moe_output_memset_inplace` dense memset wrapper](../sources/prs/flashinfer/PR-3328.md), [Add support for bf16 x bf16 cutlass fused MoE](../sources/prs/sglang/PR-10275.md), [Fix cutlass moe accuracy drop caused by attention UB from DP padding mode](../sources/prs/sglang/PR-10414.md), [Support single batch overlap](../sources/prs/sglang/PR-10422.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [feat: add dsv3 fp4 cutlass moe etp ut](../sources/prs/sglang/PR-10433.md), [Update CUTLASS. Refine KernelSchedule for fp8 (grouped) gemm.](../sources/prs/sglang/PR-10491.md), [Fix bias handling in TritonMoeQuantInfo within quantization/mxfp4.py](../sources/prs/sglang/PR-10579.md), [support qwen3-next-fp8 deepep](../sources/prs/sglang/PR-10622.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [Quick Fix: fix Qwen3-VL launch failure caused by MRotaryEmbedding arg](../sources/prs/sglang/PR-10985.md), [Fix DSR1 accuracy for flashinfer_trtllm MoE with FP8 quantization](../sources/prs/sglang/PR-11081.md), [[AMD] Clean up vllm dependencies in moe_runner/triton.py](../sources/prs/sglang/PR-11349.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [Support shared experts overlap in cutlass moe](../sources/prs/sglang/PR-11611.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [[Ascend] qwen optimization](../sources/prs/sglang/PR-12078.md), [[hotfix] missing `w13_weight_fp8` and `w2_weight_fp8` in UE8M0 requantization](../sources/prs/sglang/PR-12259.md), [Replace [silu_and_mul_]scaled_fp4_group_quant by Flashinfer equivalent](../sources/prs/sglang/PR-12376.md), [Enable Flashinfer TRTLLM-GEN-MoE FP8 blockwise kernel for Qwen3-Next on Blackwell](../sources/prs/sglang/PR-12543.md), [[CPU] Fix MoE layer support for DeepSeek-OCR models](../sources/prs/sglang/PR-12555.md), [[sgl-kernel][5/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12666.md), [[Bugfix] Fix illegal memory access](../sources/prs/sglang/PR-12758.md), [[Ascend] support Kimi-K2-Thinking](../sources/prs/sglang/PR-12759.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [Apply moe_reduce_sum kernel for fused_marlin_moe](../sources/prs/sglang/PR-12888.md), [Support moe topk sigmoid kernel](../sources/prs/sglang/PR-13049.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [[NPU]Optimization of `forward_npu` for `UnquantizedFusedMoEMethod`](../sources/prs/sglang/PR-13158.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [[NVIDIA] Fix broken fp8 MoE of deepseek v3](../sources/prs/sglang/PR-13264.md), [Flashinfer TRTLLM-GEN-MoE + Qwen3](../sources/prs/sglang/PR-13489.md), [Fix EPLB + FP4 Quantization Compatibility Issue](../sources/prs/sglang/PR-13715.md), [[bugfix] fix TBO crashes when attn_tp_size > 1](../sources/prs/sglang/PR-13730.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [[NVIDIA] Enable TRTLLM BF16 MoE on Blackwell GPUs](../sources/prs/sglang/PR-13798.md), [[BugFix] fix outplace_fused_experts missing is_gated](../sources/prs/sglang/PR-13864.md), [Feat: GLM-4.6 supports shared experts fusion](../sources/prs/sglang/PR-13873.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [[kernel][moe] add moe topk fast](../sources/prs/sglang/PR-13969.md), [Support KTransformers for Qwen3-VL moe](../sources/prs/sglang/PR-13983.md), [Fix flashinfer cutlass MoE output shape for non-FP4-packed inputs](../sources/prs/sglang/PR-14028.md), [[LoRA][III] Add LoRA support for MoE layers and enable TP](../sources/prs/sglang/PR-14105.md), [Add new moe wna16 marlin gemm](../sources/prs/sglang/PR-14122.md), [Apply new moe wna16 marlin gemm](../sources/prs/sglang/PR-14125.md), [Opt moe align block size kernel](../sources/prs/sglang/PR-14133.md), [Apply new moe align block size kernel](../sources/prs/sglang/PR-14134.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[FIX] trtllm-moe-fp4-renorm for Qwen series models](../sources/prs/sglang/PR-14350.md), [[NPU] perf update with kvcache nz & w4a8 quant](../sources/prs/sglang/PR-14423.md), [Mistral Large 3 NVFP4 support](../sources/prs/sglang/PR-14485.md), [Apply back moe_sum_reduce for fused_marlin_moe](../sources/prs/sglang/PR-14829.md), [add transformers version validation for glm-4.6v moe models](../sources/prs/sglang/PR-14998.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [[sgl-kernel][1/2] Fused qk_norm_rope for GLM4.6](../sources/prs/sglang/PR-15141.md), [[NVIDIA] Fixes for NVFP4 all-gather with spec decoding](../sources/prs/sglang/PR-15280.md), [[Fix] A followup fix for TRTLLM BF16 MoE](../sources/prs/sglang/PR-15303.md), [Fix the accuracy issue when running mxfp4 dsv3 model and enable ep](../sources/prs/sglang/PR-15304.md), [Fix warp illegal instruction in kimi k2 thinking PCG](../sources/prs/sglang/PR-15306.md), [[distributed] Clean up MoE groups in destroy_model_parallel](../sources/prs/sglang/PR-15345.md), [[NPU]mindspore model support moe](../sources/prs/sglang/PR-15363.md), [Super tiny add moe_ep_rank to prometheus labels](../sources/prs/sglang/PR-15407.md), [Flashinfer MOE FP8 support for Mistral Large 3.](../sources/prs/sglang/PR-15422.md), [Optimize Bailing-MoE with FlashInfer Fused All-Reduce](../sources/prs/sglang/PR-15526.md), [MoE: Skip SiLU/GELU activation for masked experts](../sources/prs/sglang/PR-15539.md), [Update flashinfer to 0.6.1](../sources/prs/sglang/PR-15551.md), [Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-15712.md), [[Perf] Eliminate the slice op for Flashinfer `trtllm_fp4_block_scale_moe`](../sources/prs/sglang/PR-15731.md), [Fix GLM-4.7 MoE Detector complex JSON Schema type parsing](../sources/prs/sglang/PR-15753.md), [Fix: Handle empty func_name and None values in GLM MoE detectors](../sources/prs/sglang/PR-15754.md), [[Feature] JIT Fused QK norm + qk norm clean up](../sources/prs/sglang/PR-15835.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [[NPU] NZ for non-quantized MOE, Qwen3 MOE double memory consumption fix](../sources/prs/sglang/PR-15904.md), [ Add tuned triton==3.5.1 h200 tp2, tp4 for qwen 3 next](../sources/prs/sglang/PR-15948.md), [enhance accuracy for model kimi-vl-instruct-a3b](../sources/prs/sglang/PR-16076.md), [fix layer intermediate size](../sources/prs/sglang/PR-16084.md), [[NemotronH] Add latent MoE support](../sources/prs/sglang/PR-16227.md), [Fix FP8 MoE NaN with DeepGEMM on Blackwell](../sources/prs/sglang/PR-16622.md), [[Rework] Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-16723.md), [[AMD] Support redundant expert with a2a moe in gfx95x.](../sources/prs/sglang/PR-16791.md), [[Fix] `flashinfer_trtllm` `intermediate_size` assertion with Qwen3 + TP=8](../sources/prs/sglang/PR-16824.md), [Support mxint4 flashinfer_trtllm moe gemm](../sources/prs/sglang/PR-16892.md), [Inclusion of nvfp4 blockscale in EPLB Rebalance](../sources/prs/sglang/PR-17158.md), [[Fix] GLM 4.7 + NVFP4 + MTP](../sources/prs/sglang/PR-17166.md), [[GLM 4.7] Add RTX 6000 Pro aka sm120](../sources/prs/sglang/PR-17235.md), [[New Model] GLM4.7-Flash](../sources/prs/sglang/PR-17247.md), [Add mxfp8 support for online quantization, Triton dense linear, and CUTLASS MoE](../sources/prs/sglang/PR-17449.md), [Upgrade transformers==5.3.0](../sources/prs/sglang/PR-17784.md), [[Bugfix] Fix Mistral Large 3 NVFP4 TRTLLM MoE](../sources/prs/sglang/PR-18065.md), [Fix nvfp4 weight update](../sources/prs/sglang/PR-18085.md), [[Blackwell] Make mxint4 flashinfer_trtllm moe gemm set by default on blackwell](../sources/prs/sglang/PR-18136.md), [[ModelOpt] Fix broken Qwen3-235B-A22B-Instruct-2507-NVFP4 launch](../sources/prs/sglang/PR-18189.md), [Support Qwen3 MoE context parallel](../sources/prs/sglang/PR-18233.md), [[sglang-miles] True on-policy training support for FSDP2](../sources/prs/sglang/PR-18639.md), [[Perf] ~9.5x faster Blackwell MXFP4 MoE weight loading](../sources/prs/sglang/PR-18858.md), [[Sarvam] Add inference support for Sarvam MoE LLMs](../sources/prs/sglang/PR-18938.md), [[jit_kernel] Add fused_qknorm_rope JIT kernel](../sources/prs/sglang/PR-19059.md), [Adjust padding size to improve triton_kernels moe performance](../sources/prs/sglang/PR-19174.md), [Fix/nemotron mtp quantaized](../sources/prs/sglang/PR-19433.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Use TRTLLM allreduce fusion for Qwen 3.5](../sources/prs/sglang/PR-19889.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[4/n jit_kernel restruct] speed up CI tests and add benchmark workflow](../sources/prs/sglang/PR-20268.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[NVIDIA] Enable fp8 flashinfer_trtllm_routed MoE for MiniMax-M2.5](../sources/prs/sglang/PR-20394.md), [Add Mistral Small 4 (Pixtral) support](../sources/prs/sglang/PR-20708.md), [Use FlashInfer tinygemm for GPT-OSS MoE router on SM90+](../sources/prs/sglang/PR-20755.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[refactor] Clean up duplicate flashinfer trtllm moe code](../sources/prs/sglang/PR-21233.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[NVIDIA] Enable FP4 flashinfer trtllm routed moe](../sources/prs/sglang/PR-21240.md), [P2P Weight Update features for miles ](../sources/prs/sglang/PR-21278.md), [[RL] Support mxfp8 DeepSeek V3](../sources/prs/sglang/PR-21280.md), [[Kernel] Support FlashInfer TRTLLM-Gen fused MoE for non-gated FP4 & FP8 (Nemotron)](../sources/prs/sglang/PR-21321.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Add dedicated FlashInferCuteDslMoE layer for standard-path FP4 MoE](../sources/prs/sglang/PR-21339.md), [[jit_kernel] Optimize fused_qknorm_rope: deduplicate sincosf for interleave RoPE ](../sources/prs/sglang/PR-21654.md), [[AMD] Use tgemm.mm for MoEGate router gemm in deepseek_v2.py](../sources/prs/sglang/PR-21657.md), [Harden FlashInfer FP4 imports in standard dispatcher](../sources/prs/sglang/PR-21776.md), [[Fix] Fall back to triton MOE for GPT-OSS on Blackwell with driver >= 595](../sources/prs/sglang/PR-21780.md), [Remove redundant test_moe_eval_accuracy_large](../sources/prs/sglang/PR-21787.md), [Tiny fix trtllm_fp8_per_tensor_scale_moe_wrapper router_logits dtype](../sources/prs/sglang/PR-22006.md), [[RL] Refactor NVFP4 shuffling/swizzling to in-place replacement](../sources/prs/sglang/PR-22204.md), [[Reland] DeepSeek-R1-0528-w4a8: DeepEP Low Latency Dispatch Adopts FP8 Communication](../sources/prs/sglang/PR-22316.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [[Lora] Lora kimi support](../sources/prs/sglang/PR-22381.md), [feat: Support flashinfer_cutedsl MoE runner with flashinfer alltoall backend](../sources/prs/sglang/PR-22669.md), [[Step3p5] Optimize allreduce in MoE layers ](../sources/prs/sglang/PR-22773.md), [Dual MoE CUDA graph capture for lora/nolora batches](../sources/prs/sglang/PR-22809.md), [[Refactor] Refactor DeepEP dispatcher](../sources/prs/sglang/PR-22822.md), [[FlashInfer v0.6.11] [RL] Support FlashInfer per-token NVFP4 MoE](../sources/prs/sglang/PR-22918.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [[MoE] Unify DeepEPMoE+MoriEPMoE through AITER MoeRunner pre/post-permute](../sources/prs/sglang/PR-23760.md), [[feat] Init true on policy with qwen_dense](../sources/prs/sglang/PR-23961.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [Fix performance regression on Deepseek V3 on `moe-runner-backend=triton` on SM90](../sources/prs/sglang/PR-24562.md), [[Codex] Opt Mistral Large performace ](../sources/prs/sglang/PR-24611.md), [Add FlashInfer SM90 cutlass MXFP4 MoE backend (W4A16) for GPT-OSS + DeepSeek-V4](../sources/prs/sglang/PR-24816.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [Fix EPLB mapping for TopK paths](../sources/prs/sglang/PR-25285.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[AMD] test(sgl-kernel): seed RNG on ROCm in test_moe_topk_sigmoid to fix tie-break flake](../sources/prs/sglang/PR-25356.md), [Update logging for inplace setting in MoE layer](../sources/prs/sglang/PR-25499.md), [[misc] Throw error when single batch overlap is enabled on Hopper ](../sources/prs/sglang/PR-25509.md), [Fix logging for inplace setting in the flashInfer-trtllm backend](../sources/prs/sglang/PR-25522.md), [[Bug Fix] Align glm4_moe_nextn NPU MTP loading with qwen3 MTP](../sources/prs/sglang/PR-25524.md), [[MoE Refactor] Migrate flashinfer_cutedsl + DeepEP to MoeRunner](../sources/prs/sglang/PR-25525.md), [Use DeepGEMM BF16 for unquantized DeepEP LL MoE](../sources/prs/sglang/PR-25540.md), [Add DeepSeekV4 fused MoE Triton autotune support](../sources/prs/sglang/PR-25569.md), [[Benchmark] Add SGLANG_SIMULATE_UNIFORM_EXPERTS for balanced expert routing with dummy weights](../sources/prs/sglang/PR-25571.md), [[SP] Fix runtime_max_tokens_per_rank for sequence parallelism](../sources/prs/sglang/PR-25685.md), [Add no_combine support to cutlass_moe_fp4](../sources/prs/sglang/PR-25688.md), [[Refactor] Pass PP start_layer via model constructor instead of forward_batch.token_to_kv_pool](../sources/prs/sglang/PR-25825.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [Feature DeepSeek V3/R1 INT8 Quantization (block-wise)](../sources/prs/sglang/PR-3730.md), [[Feature] DeepSeek V3/R1 INT8 Quantization (channel-wise) ](../sources/prs/sglang/PR-3888.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [[Feature] Integrate DeepEP into SGLang](../sources/prs/sglang/PR-4232.md), [Add deepseek style fused moe group gate selection kernel](../sources/prs/sglang/PR-4530.md), [Optimize Permute Kernel in DeepEP](../sources/prs/sglang/PR-4643.md), [Fix loading KV quantization scale; Enable modelopt kv cache](../sources/prs/sglang/PR-4686.md), [[Model] Adding Qwen3 and Qwen3MoE](../sources/prs/sglang/PR-4693.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [[Feature] Support DeepEP Low Latency](../sources/prs/sglang/PR-4767.md), [Support (1 <= dp < tp) in the dp attention in DeepEP](../sources/prs/sglang/PR-4770.md), [Introduce moe_dense_tp_size to fix dense layer errors in DeepSeek V3 + 4x8xH100](../sources/prs/sglang/PR-4836.md), [Add DeepSeek V3/R1 shared experts fusion](../sources/prs/sglang/PR-4918.md), [[Fix] DeepEP Compatibility with Low Latency](../sources/prs/sglang/PR-5068.md), [reduce moe_align_block_size_kernel small batch mode overhead](../sources/prs/sglang/PR-5086.md), [Add optimized native kernels in sgl-kernel](../sources/prs/sglang/PR-5150.md), [[1/2] Add FP8 Blockscale MoE CUTLASS kernel for Blackwell](../sources/prs/sglang/PR-5281.md), [Fix DeepGEMM masked cannot be run on groups not being multiple or 4](../sources/prs/sglang/PR-5340.md), [apply fused moe gate in ds v3/r1](../sources/prs/sglang/PR-5371.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [ DeepEP normal support deepgemm-contiguous](../sources/prs/sglang/PR-5626.md), [[2/2] Add python wrapper for CUTLASS FP8 Blockscale MoE Kernel. ](../sources/prs/sglang/PR-5694.md), [[qwen3] support qwen3 ep moe](../sources/prs/sglang/PR-5917.md), [Support tuning moe for llama 4 model](../sources/prs/sglang/PR-6042.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [feat: add dp attention support for Qwen 2/3 MoE models, fixes #6088](../sources/prs/sglang/PR-6121.md), [Reduce MoE memory usage](../sources/prs/sglang/PR-6147.md), [enable auto-round quantization model](../sources/prs/sglang/PR-6226.md), [fix: enable multi-GPU Triton fused MoE tuning](../sources/prs/sglang/PR-6295.md), [reduce torch.zeros overhead in moe align block size kernel](../sources/prs/sglang/PR-6369.md), [Add fp8 fused_experts kernel for CPU in sgl-kernel and add UT](../sources/prs/sglang/PR-6404.md), [Fix topk inference performance reduce](../sources/prs/sglang/PR-6474.md), [qwen3moe support two batch overlap](../sources/prs/sglang/PR-6598.md), [Refine pre_reorder_triton_kernel slightly to improve performance](../sources/prs/sglang/PR-6627.md), [[CPU] [BF16] Call fused_experts_cpu, weight_packed_linear and bmm_cpu kernel in DeepSeek model](../sources/prs/sglang/PR-6641.md), [Fix DeepEP error in Qwen 3 MoE models](../sources/prs/sglang/PR-6673.md), [[EP] Add cuda kernel for moe_ep_pre_reorder](../sources/prs/sglang/PR-6699.md), [Fix PP for Qwen3 MoE](../sources/prs/sglang/PR-6709.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [[CPU] add optimizations for INT8 and FP8 DeepSeek](../sources/prs/sglang/PR-6769.md), [[CPU] support the case where num_attention_heads or intermediate_size is not divisible by the TP size](../sources/prs/sglang/PR-6771.md), [Support token-level quantization for EP MoE](../sources/prs/sglang/PR-6782.md), [feat: integrate deepgemm into EPMoE](../sources/prs/sglang/PR-6821.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [[EP] Add cuda kernel for moe_ep_post_reorder](../sources/prs/sglang/PR-6837.md), [[DeepseekR1-FP4] Add Support for nvidia/DeepSeekR1-FP4 model](../sources/prs/sglang/PR-6853.md), [fix ep_moe_reorder kernel bugs](../sources/prs/sglang/PR-6858.md), [Add a CUDA kernel for fusing mapping and weighted sum for MoE.](../sources/prs/sglang/PR-6916.md), [[sgl-kernel] Add cuda kernel for moe_ep_silu_and_mul](../sources/prs/sglang/PR-6919.md), [chore: upgrade flashinfer v0.2.6.post1 jit](../sources/prs/sglang/PR-6958.md), [Fuse routed scaling factor in deepseek](../sources/prs/sglang/PR-6970.md), [Update default settings for blackwell](../sources/prs/sglang/PR-7023.md), [Fix positional argument](../sources/prs/sglang/PR-7093.md), [fix amd EP MoE FP8 issue](../sources/prs/sglang/PR-7125.md), [Enable ModelOpt Llama4 fp8 checkpoint deployment in SGLang](../sources/prs/sglang/PR-7129.md), [[amd] Opt dsv3 moe](../sources/prs/sglang/PR-7160.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Fix error when disabling new DeepGEMM](../sources/prs/sglang/PR-7198.md), [[fix] fix DeepGEMM blackwell input quant & ut & fix style and log](../sources/prs/sglang/PR-7247.md), [[AMD] add aiter fused moe in DeepEP path](../sources/prs/sglang/PR-7268.md), [Add CUTLASS FP8 Blockscale MoE kernel for Hopper architecture](../sources/prs/sglang/PR-7278.md), [Let EP prefill support new DeepGEMM](../sources/prs/sglang/PR-7310.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Fix MTP with Deepseek R1 Fp4](../sources/prs/sglang/PR-7376.md), [Fix torch compile run](../sources/prs/sglang/PR-7391.md), [[AMD][Quantization] Add `int4fp8_moe` online quantization on ROCm](../sources/prs/sglang/PR-7392.md), [Fuse sorted_token_ids padding to moe_align_block_size kernel](../sources/prs/sglang/PR-7437.md), [fix: fix apply_shuffle_mul_sum](../sources/prs/sglang/PR-7444.md), [Add Tencent HunYuanMoEV1 model support](../sources/prs/sglang/PR-7549.md), [[Feature] Layer-wise Prefill](../sources/prs/sglang/PR-7634.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [Integrate triton moe kernel](../sources/prs/sglang/PR-7689.md), [feat: support DeepSeek-R1-W4AFP8 model with ep-moe mode](../sources/prs/sglang/PR-7762.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [[kernel] opt moe align block kernel by block/warp scan algorithm](../sources/prs/sglang/PR-7884.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [[1/N]Support DeepSeek-R1 w4a8 normal deepep](../sources/prs/sglang/PR-8247.md), [Support triton kernels v3.4.0 for fused_moe](../sources/prs/sglang/PR-8258.md), [[2/N]Support DeepSeek-R1 w4a8 low latency deepep](../sources/prs/sglang/PR-8464.md), [Update cutlass_moe.py](../sources/prs/sglang/PR-8535.md), [Update cutlass_moe.py](../sources/prs/sglang/PR-8545.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [feat: support cutlass_moe_fp8 kernel for fusedmoe in sm90](../sources/prs/sglang/PR-8678.md), [fuse allreduce and residual_rmsnorm](../sources/prs/sglang/PR-8731.md), [[Perf] Auto enable best flashinfer mxfp4 kernel in b200](../sources/prs/sglang/PR-8898.md), [[NVIDIA] Fix missing `get_col_major_tma_aligned_tensor` for Blackwell deepgemm in EpMoE](../sources/prs/sglang/PR-8955.md), [optimize: reduce shulffle and quantization overhead in cutlass_moe sm90](../sources/prs/sglang/PR-8962.md), [Faster weight processing (trtllm-gen moe nvfp4)](../sources/prs/sglang/PR-9162.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [[fix] Fix mxfp4 triton MoE tp bug](../sources/prs/sglang/PR-9473.md), [Optimize moe_sum_reduce_kernel](../sources/prs/sglang/PR-9477.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [Single Batch Overlap for MoE Models](../sources/prs/sglang/PR-9660.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [Make sm100 fp8 kernels available on sm103](../sources/prs/sglang/PR-9789.md), [[Model] Support Meituan LongCat-Flash && LongCat-Flash-MTP](../sources/prs/sglang/PR-9824.md), [[ROCm][MoE] moe tuning support for rocm](../sources/prs/vllm/PR-12049.md), [[Kernel] add triton fused moe kernel for gptq/awq](../sources/prs/vllm/PR-12185.md), [[Hardware][Gaudi][Feature] Enable Dynamic MoE for Mixtral](../sources/prs/vllm/PR-12303.md), [[Misc][MoE] add Deepseek-V3 moe tuning support](../sources/prs/vllm/PR-12558.md), [[Kernel] port sgl moe_align_block_size kernels](../sources/prs/vllm/PR-12574.md), [Expert Parallelism (EP) Support for DeepSeek Models](../sources/prs/vllm/PR-12583.md), [Apply torch.compile to fused_moe/grouped_topk](../sources/prs/vllm/PR-12637.md), [[Misc] Update w2 scale loading for GPTQMarlinMoE](../sources/prs/vllm/PR-12757.md), [Optimize moe_align_block_size for deepseek_v3](../sources/prs/vllm/PR-12850.md), [[Model] Deepseek GGUF support ](../sources/prs/vllm/PR-13167.md), [[Quant][Perf] Use moe_wna16 kernel by default for MoEs with many experts](../sources/prs/vllm/PR-13236.md), [[Kernel] moe wna16 cuda kernel](../sources/prs/vllm/PR-13321.md), [[ROCm][MoE] mi300 mixtral8x7B perf for specific BS](../sources/prs/vllm/PR-13577.md), [[Kernel] Optimize moe intermediate_cache usage](../sources/prs/vllm/PR-13625.md), [[BugFix] Illegal memory access for MoE On H20](../sources/prs/vllm/PR-13693.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [Fix CompressedTensorsWNA16MoE with grouped scales](../sources/prs/vllm/PR-13769.md), [Fix precommit fail in fused_moe intermediate_cache2 chunking](../sources/prs/vllm/PR-13772.md), [[Bugfix][Quantization] Fix FP8 + EP](../sources/prs/vllm/PR-13784.md), [[V1] EP/TP MoE + DP Attention](../sources/prs/vllm/PR-13931.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [[Misc] Print FusedMoE detail info](../sources/prs/vllm/PR-13974.md), [[core] moe fp8 block quant tuning support](../sources/prs/vllm/PR-14068.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[Misc] Add Qwen2MoeForCausalLM moe tuning support ](../sources/prs/vllm/PR-14276.md), [[Kernel] moe wna16 marlin kernel](../sources/prs/vllm/PR-14447.md), [[ROCm][Kernel] MoE weights padding](../sources/prs/vllm/PR-14454.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[Kernel] GGUF MoE kernel](../sources/prs/vllm/PR-14613.md), [[Bugfix][IPEX] Add `VLLM_CPU_MOE_PREPACK` to allow disabling MoE prepack when CPU does not support it](../sources/prs/vllm/PR-14681.md), [[FEAT][ROCm] Integrate Fused MoE Kernels from AITER](../sources/prs/vllm/PR-14967.md), [[Model] Add Qwen3 and Qwen3MoE](../sources/prs/vllm/PR-15289.md), [[Kernel] Fix conflicting macro names for gguf kernels](../sources/prs/vllm/PR-15456.md), [Use Cache Hinting for fused_moe kernel](../sources/prs/vllm/PR-15511.md), [[moe][quant] add weight name case for offset](../sources/prs/vllm/PR-15515.md), [[Quantization] Fp8 Channelwise Dynamic Per Token GroupedGEMM](../sources/prs/vllm/PR-15587.md), [[V1] TPU - Fix fused MOE](../sources/prs/vllm/PR-15834.md), [[Hardware][Gaudi][BugFix] fix arguments of hpu fused moe](../sources/prs/vllm/PR-15945.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[Kernel] Use moe_wna16 kernel for compressed tensors wna16 moe models](../sources/prs/vllm/PR-16038.md), [[Kernel][Bugfix] Re-fuse triton moe weight application](../sources/prs/vllm/PR-16071.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Bug] [ROCm] Fix Llama 4 Enablement Bug on ROCm: V0 ROCmFlashAttentionImpl and Triton Fused MoE bugs](../sources/prs/vllm/PR-16198.md), [[Model] use AutoWeightsLoader for phimoe,qwen2_moe,qwen3_moe](../sources/prs/vllm/PR-16203.md), [[Hardware][AMD] Improve OAM device ID + llama4 Maverick MOE tuning](../sources/prs/vllm/PR-16263.md), [[Hardware/NVIDIA/Kernel] [Functional Enablement] [1/N] Enable nvidia/DeepSeek-R1-FP4 Model](../sources/prs/vllm/PR-16362.md), [[Kernel] Support W8A8 channel-wise weights and per-token activations in triton fused_moe_kernel](../sources/prs/vllm/PR-16366.md), [Enable PTPC FP8 for CompressedTensorsW8A8Fp8MoEMethod (triton fused_moe)](../sources/prs/vllm/PR-16537.md), [[ROCM] enable aiter fused moe kernel for llama4 bf16 checkpoints](../sources/prs/vllm/PR-16674.md), [[ROCm] Add aiter tkw1 kernel for Llama4 fp8](../sources/prs/vllm/PR-16727.md), [Support W8A8 INT8 MoE for compressed-tensors](../sources/prs/vllm/PR-16745.md), [[FEAT] [ROCm]: AITER Fused MOE V1 Support](../sources/prs/vllm/PR-16752.md), [[misc] ignore marlin_moe_wna16 local gen codes](../sources/prs/vllm/PR-16760.md), [[Kernel] GGUF MoeVec kernel](../sources/prs/vllm/PR-16780.md), [[BugFix] Accuracy fix for llama4 int4 - improperly casted scales](../sources/prs/vllm/PR-16801.md), [[Kernel] some optimizations for dense marlin and moe marlin](../sources/prs/vllm/PR-16850.md), [[Bugfix] Fix moe weight losing all extra attrs after `process_weights_after_loading`.](../sources/prs/vllm/PR-16854.md), [[Kernel] Add expert_map support to Cutlass FP8 MOE](../sources/prs/vllm/PR-16861.md), [Update Qwen1.5-MoE-W4A16-compressed-tensors.yaml](../sources/prs/vllm/PR-16946.md), [Fix `numel()` downcast in vllm/csrc/moe/moe_align_sum_kernels.cu +2](../sources/prs/vllm/PR-17082.md), [[FEAT] [ROCm]: Add AITER CK 2 Stages MoE support](../sources/prs/vllm/PR-17110.md), [[FEAT][ROCm]: Support AITER MLA on V1 Engine](../sources/prs/vllm/PR-17523.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [[BugFix][AMD] Compatible patch for AITER lib after 04/20](../sources/prs/vllm/PR-17912.md), [Fix Broken macro for cutlass moe](../sources/prs/vllm/PR-18049.md), [[Model]: Fused MoE for nomic-embed-text-v2-moe](../sources/prs/vllm/PR-18321.md), [[Feature] Expert Parallelism Load Balancer (EPLB)](../sources/prs/vllm/PR-18343.md), [[Bug] Fix moe_sum signature](../sources/prs/vllm/PR-18440.md), [[V1] Support `LLM.apply_model`](../sources/prs/vllm/PR-18465.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Kernel] Enable fp8 support for pplx and BatchedTritonExperts.](../sources/prs/vllm/PR-18864.md), [[ROCm] [AITER] [Bugfix] Patch for AITER commit `648764942e552a8bb5fe16026703716a81f05374`](../sources/prs/vllm/PR-18990.md), [[Hardware][NVIDIA] FP4 MoE kernel optimization](../sources/prs/vllm/PR-19110.md), [[Kernels] Add activation chunking logic to FusedMoEModularKernel](../sources/prs/vllm/PR-19168.md), [[Kernel] Apply torch.Tag.needs_fixed_stride_order only for torch==2.6.0](../sources/prs/vllm/PR-19346.md), [[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization](../sources/prs/vllm/PR-19500.md), [Only build CUTLASS MoE kernels on Hopper](../sources/prs/vllm/PR-19648.md), [[Kernels] Use empty for modular MoE workspaces](../sources/prs/vllm/PR-19667.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [[Feature] Integrate new deepgemm](../sources/prs/vllm/PR-19820.md), [[Quantization] Add compressed-tensors NVFP4 MoE Support](../sources/prs/vllm/PR-19990.md), [Enable V1 for Hybrid SSM/Attention Models](../sources/prs/vllm/PR-20016.md), [[Bugfix] Build moe_data for both sm100 and sm90](../sources/prs/vllm/PR-20086.md), [ [Feature] Integrate SM100 DeepGEMM support](../sources/prs/vllm/PR-20087.md), [Add ModelOpt Qwen3 nvfp4 support](../sources/prs/vllm/PR-20101.md), [[Bugfix] Mark 'hidden_states' as mutable in moe_forward registration.](../sources/prs/vllm/PR-20152.md), [[Bugfix] Fix topk_ids indices_type for CUTLASS w8a8 FP8 MoE](../sources/prs/vllm/PR-20166.md), [[Bugfix] Fix Maverick correctness by filling zero to cache space in cutlass_moe](../sources/prs/vllm/PR-20167.md), [[V1] [ROCm] Enable EP with AITER Fused MoE](../sources/prs/vllm/PR-20270.md), [[Kernel][Bugfix] Fixup some warnings in nvfp4_blockwise_moe when CUDA < 12.8](../sources/prs/vllm/PR-20324.md), [[Misc] DP : Add ExpertTokensMetadata](../sources/prs/vllm/PR-20332.md), [[feat]: add SM100 support for cutlass FP8 groupGEMM](../sources/prs/vllm/PR-20447.md), [Support Llama 4 for cutlass_moe_fp4](../sources/prs/vllm/PR-20453.md), [Support Llama 4 for fused_marlin_moe](../sources/prs/vllm/PR-20457.md), [[Perf] Reuse workspace for FP8+FP4 Marlin MoE](../sources/prs/vllm/PR-20500.md), [[Bugfix] Fix missing per_act_token parameter in compressed_tensors_moe](../sources/prs/vllm/PR-20509.md), [[feat] enable SM100 CUTLASS block scaled group gemm for smaller batch sizes](../sources/prs/vllm/PR-20640.md), [GLM-4.5 Model Support](../sources/prs/vllm/PR-20736.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [[fix]: disable cutlass block scaled group gemm for EP](../sources/prs/vllm/PR-20781.md), [[Feature][EPLB] Add eplb support for Qwen3](../sources/prs/vllm/PR-20815.md), [[Bugfix] Fix a couple PPLX+CUTLASS MoE bugs](../sources/prs/vllm/PR-20825.md), [[Bug] Fix DeepGemm for EP low latency case](../sources/prs/vllm/PR-20833.md), [[Perf] Use Triton instead of Torch for DeepGEMM Per Token Group Quant](../sources/prs/vllm/PR-20841.md), [[Kernel] DeepGemm MoE : Integrate triton permute / unpermute kernels ](../sources/prs/vllm/PR-20903.md), [[Perf] Add swap_ab to SM90 FP8 non-block CUTLASS moe grouped gemm](../sources/prs/vllm/PR-20911.md), [[Misc] Qwen MoE model supports LoRA](../sources/prs/vllm/PR-20932.md), [Support mnnvl all2allv from Flashinfer](../sources/prs/vllm/PR-21003.md), [[Bugfix] Allocate less memory in non-batched CUTLASS MoE](../sources/prs/vllm/PR-21121.md), [[Feature][OCP MX] Support mxfp6 and mixed mxfp6-mxfp4](../sources/prs/vllm/PR-21166.md), [[Feature][Kernel]FusedMoE LoRA](../sources/prs/vllm/PR-21229.md), [[v1] - Mamba1 Attention Metadata](../sources/prs/vllm/PR-21249.md), [Support CUTLASS NVFP4 (w4a4) for Blackwell Geforce GPUs (SM120)](../sources/prs/vllm/PR-21309.md), [Support Tensorrt-LLM MoE fp4 for low-latency](../sources/prs/vllm/PR-21331.md), [[TPU][Bugfix] fix moe layer](../sources/prs/vllm/PR-21340.md), [[Quantization] Enable BNB support for more MoE models](../sources/prs/vllm/PR-21370.md), [Update flashinfer CUTLASS NVFP4 MoE Kernel to use per expert global scaling factor](../sources/prs/vllm/PR-21408.md), [[NVIDIA] Explicitly disable shuffled weights for flashinfer blockscale moe fp8 kernels](../sources/prs/vllm/PR-21411.md), [[Bug] Fix Compressed Tensor NVFP4 `cutlass_fp4_group_mm` illegal memory access](../sources/prs/vllm/PR-21465.md), [[MoE] More balanced expert sharding](../sources/prs/vllm/PR-21497.md), [[NVIDIA] Fix Llama4 Scout FP4 functionality issues](../sources/prs/vllm/PR-21499.md), [Enable 4bit bnb prequant MOE](../sources/prs/vllm/PR-21548.md), [[Feature] Add Flashinfer MoE Support for Compressed Tensor NVFP4](../sources/prs/vllm/PR-21639.md), [[xpu]support moe models on XPU platform](../sources/prs/vllm/PR-21643.md), [support `torch.compile` for bailing moe](../sources/prs/vllm/PR-21664.md), [feat: Add Support GPTQ Quantization MOE on ROCM vllm serve](../sources/prs/vllm/PR-21733.md), [[Qwen3] Enable dual-chunk-attention support for Qwen3 models.](../sources/prs/vllm/PR-21924.md), [Fix Flashinfer CUTLASS MOE Allgather](../sources/prs/vllm/PR-21963.md), [[BUGFIX] KeyError 'layers.14.mlp.gate.g_idx' for Qwen3-MoE with GPTQ on ROCm](../sources/prs/vllm/PR-22017.md), [[EPLB] Support ernie4.5-moe](../sources/prs/vllm/PR-22100.md), [[Bugfix] Fix MoE BNB version](../sources/prs/vllm/PR-22260.md), [[gpt-oss] flashinfer mxfp4](../sources/prs/vllm/PR-22339.md), [[gpt-oss] triton kernel mxfp4](../sources/prs/vllm/PR-22421.md), [Fix Llama4 FlashInfer FP4 MoE issues](../sources/prs/vllm/PR-22511.md), [[Model] Add Ernie4.5 VL Model Support](../sources/prs/vllm/PR-22514.md), [Fix torch version check for SM100 mxfp4 ](../sources/prs/vllm/PR-22535.md), [[Quantization] Expand compressed-tensors MoE matching logic to support NFP4 + FP8 MoEs](../sources/prs/vllm/PR-22674.md), [Fix GGUF loader for Qwen3 MoE.](../sources/prs/vllm/PR-22785.md), [[FIXBUG] Add return_success parameter to moe_wna16_weight_loader function](../sources/prs/vllm/PR-22797.md), [[Model] Modify the gate implementation of glm4_moe](../sources/prs/vllm/PR-22832.md), [[XPU] support data parallel for MoE models on XPU](../sources/prs/vllm/PR-22887.md), [[Bugfix] Fix DeepSeek MTP](../sources/prs/vllm/PR-22934.md), [[Fix] enable swap_ab for pplx problem size computation](../sources/prs/vllm/PR-22991.md), [Use Blackwell FlashInfer MXFP4 MoE by default if available ](../sources/prs/vllm/PR-23008.md), [[Bugfix] fix qwen3 moe fp8 accuracy issue](../sources/prs/vllm/PR-23031.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [Add routed_scaling_factor to MoE grouped topk](../sources/prs/vllm/PR-23123.md), [[Bugfix] Fix accuracy issue when using flashinfer cutlass moe, TP=1 and modelopt.](../sources/prs/vllm/PR-23125.md), [[CPU] add cpu fused moe pytorch native implementation](../sources/prs/vllm/PR-23146.md), [[Perf] Small optimizations for silu_mul_fp8_quant_deep_gemm](../sources/prs/vllm/PR-23265.md), [[Kernels] Overlap shared experts with send/recv](../sources/prs/vllm/PR-23273.md), [[Kernel] Add fused grouped_topk kernel for MoE](../sources/prs/vllm/PR-23274.md), [[Bugfix] Fix Qwen3 MoE GPTQ inference](../sources/prs/vllm/PR-23490.md), [DP/EP Support for gpt-oss with deepep-ht comm kernel on SM100](../sources/prs/vllm/PR-23608.md), [[Feature] Add Hopper DeepGEMM E8M0 for DeepSeekV3.1 scale_fmt](../sources/prs/vllm/PR-23666.md), [[Core/DBO][1/N] Add Dual-Batch Overlap mechanism to VLLM](../sources/prs/vllm/PR-23693.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [[Bugfix][Misc] Fix silu_and_mul_nvfp4_quant issue and extract common utils for nvfp4 kernel source files](../sources/prs/vllm/PR-23727.md), [[Feat][EPLB] A novel static EPLB placement strategy for MoE models.](../sources/prs/vllm/PR-23745.md), [[fix]: add Arm 4bit fused moe support](../sources/prs/vllm/PR-23809.md), [[Model][gpt-oss] Support DP+EP for GPT-OSS with FlashInfer trtllm-gen MoE](../sources/prs/vllm/PR-23819.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[BUGFIX] GPTQ quantization compatibility for Qwen3 MOE models (AutoGPTQ and AutoRound-GPTQ)](../sources/prs/vllm/PR-23994.md), [[PERF] Allreduce fusion. Support torch native matching. Tuning of the thresholds](../sources/prs/vllm/PR-24248.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [[Model] Support Qwen3-VL Model Series](../sources/prs/vllm/PR-24727.md), [feat: BF16 FlashInfer Fused Cutlass MOE for Hopper and Blackwell Expert Parallel](../sources/prs/vllm/PR-25503.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Bugfix] Allow skipping MoE in NVFP4 (fix for MTP)](../sources/prs/vllm/PR-25987.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [Fix undefined symbol: cutlass_moe_mm_sm100](../sources/prs/vllm/PR-26098.md), [[ModelOpt] Load w13/w2_input_scale for all experts, nvfp4](../sources/prs/vllm/PR-26135.md), [[Bug] Fix Shape Validation for Fallback while Enabling E8M0 for DeepGEMM](../sources/prs/vllm/PR-26322.md), [[Performance] Dual stream execution of "shared_experts" and "selected_experts" inside FusedMoE](../sources/prs/vllm/PR-26440.md), [[ROCM] MoE fp4 CK kernel](../sources/prs/vllm/PR-26545.md), [support flashinfer_fp4 moe for 5090 gpu](../sources/prs/vllm/PR-26669.md), [[NVIDIA] [Perf] Update to leverage flashinfer trtllm FP4 MOE throughput kernel](../sources/prs/vllm/PR-26714.md), [[Bugfix] Fix gpt-oss w4a8 DP/EP on B200](../sources/prs/vllm/PR-26729.md), [[Kernels] Enable FlashInfer FP8 Blockscale on SM90 (for TEP DSR1)](../sources/prs/vllm/PR-27134.md), [[ROCM] Enable CompressedTensorsWNA16](../sources/prs/vllm/PR-27187.md), [Flashinfer_CUTLASS_MOE fuses quantization for TP](../sources/prs/vllm/PR-27223.md), [Bugfix: Cutlass FP8 FusedMoE bad scaling factors](../sources/prs/vllm/PR-27255.md), [Feature: Support Relu2 in FusedMoE fp8 cutlass path](../sources/prs/vllm/PR-27261.md), [[Performance] Support FP8 flashinfer TRTLLM MOE on Qwen3 and Qwen-3next](../sources/prs/vllm/PR-27492.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Performance][B200] Fix deepgemm prologue](../sources/prs/vllm/PR-27897.md), [[Model] Consolidate Deepseek-MoE implementation with DeepSeek-v2](../sources/prs/vllm/PR-28101.md), [[Perf][DeepSeek] Add sigmoid+bias fusion to fused_grouped_topk from TRTLLM](../sources/prs/vllm/PR-28124.md), [[flashinfer] fix FI all2all with FI cutlass moe](../sources/prs/vllm/PR-28166.md), [[Feature] Support recording expert indices for rollout router replay](../sources/prs/vllm/PR-28284.md), [[Performance][B200] silu_mul_quant: pack scales in int32](../sources/prs/vllm/PR-28358.md), [[Bugfix][EPLB] Disabled shared expert overlap when EPLB is enabled](../sources/prs/vllm/PR-28377.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [[Model] Add support for openPangu moe model](../sources/prs/vllm/PR-28775.md), [[Bugfix] Fix GPT-OSS AR+NORM fusion](../sources/prs/vllm/PR-28841.md), [[Bugfix] Make compressed-tensors MoEs respect ignored layers](../sources/prs/vllm/PR-28878.md), [Add TRTLLM MoE NVFP4 kernel to CompressedTensorsW4A4MoeMethod](../sources/prs/vllm/PR-28892.md), [[NVIDIA] Guard SM100 CUTLASS MoE macro to SM100 builds v2](../sources/prs/vllm/PR-28938.md), [[Feat] Support non-gated activations in NVFP4 modelopt path](../sources/prs/vllm/PR-29004.md), [[LoRA] Optimize 3D MoE logic](../sources/prs/vllm/PR-29222.md), [chore: add RTX_PRO_6000 GLM4.6-FP8 kernel tuning](../sources/prs/vllm/PR-29240.md), [[Kernel] Add NVFP4 MoE CUTLASS support for SM120](../sources/prs/vllm/PR-29242.md), [Lora MoE Align Improvements](../sources/prs/vllm/PR-29257.md), [[Perf] Disable DeepGEMM MoE by default when TP=8 is used](../sources/prs/vllm/PR-29346.md), [Add unpermute-aware fused MoE path and small-batch fallback](../sources/prs/vllm/PR-29354.md), [[Bugfix] Fix grouped_topk pytorch impl when num_experts can't be grouped properly](../sources/prs/vllm/PR-29439.md), [[Kernel][MoE] optimize `moe_align_block_size`](../sources/prs/vllm/PR-29642.md), [[Kernel]Support W4A8 Grouped GEMM on Hopper](../sources/prs/vllm/PR-29691.md), [[MoE-FP8-modelopt] Add FlashInfer alignment padding for intermediate dimensions](../sources/prs/vllm/PR-29748.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[ROCm] [Fused Moe EP] Use binary expert mask for aiter fused moe kernel](../sources/prs/vllm/PR-29773.md), [[ROCm][MXFP4] Infer w4a4 quant method in rocm aiter fused moe](../sources/prs/vllm/PR-29775.md), [[EPLB] Support EPLB w/ NVFP4](../sources/prs/vllm/PR-29804.md), [[Bugfix][Model] Support LoRA on Qwen3 Output Embedding](../sources/prs/vllm/PR-29816.md), [[Bugfix] Fix FP8 MoE LoRA](../sources/prs/vllm/PR-29890.md), [[Kernel][Quantization][MoE] add marlin kernel support for turing (sm75)](../sources/prs/vllm/PR-29901.md), [[moe] Use enable_chunking func (to support disabling chunking)](../sources/prs/vllm/PR-29935.md), [[moe] Allow disabling DP chunking](../sources/prs/vllm/PR-29936.md), [[Perf] Do FP4 quant before All gather on flashinfer trtllmgen MOE ](../sources/prs/vllm/PR-30014.md), [[Quantization] Support Quark int4-fp8 w4a8 for MoE](../sources/prs/vllm/PR-30071.md), [[Model][Quantization] Restore MoE + GGUF models support (incl. Qwen3 MoE) by allowing Sideload Parameters](../sources/prs/vllm/PR-30116.md), [[Model][Quantization] Override HF defaults to GGUF ones (incl. Qwen3 MoE)](../sources/prs/vllm/PR-30118.md), [Add latent MoE support](../sources/prs/vllm/PR-30203.md), [[Bugfix]: Fix glm46 awq marlin moe wna16 compatibility](../sources/prs/vllm/PR-30210.md), [[LoRA] Reduce the loading time of MoE LoRA](../sources/prs/vllm/PR-30243.md), [gptq marlin quantization support for fused moe with lora](../sources/prs/vllm/PR-30254.md), [[LoRA] Support Quantized Adapters](../sources/prs/vllm/PR-30286.md), [[Model][Quantization] Fix / Add GGUF support for Qwen2 MoE models](../sources/prs/vllm/PR-30307.md), [[bugfix][quantization] fix quark qwen3 kv_cache quantization](../sources/prs/vllm/PR-30308.md), [[fix] fix SM check for Flashinfer TRTLLM MOE](../sources/prs/vllm/PR-30314.md), [[ROCm][Quantization] GPT OSS Upstream MoE wmxfp4_afp8 with static scales](../sources/prs/vllm/PR-30357.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Bugfix] Fix Triton FusedMoE LoRA](../sources/prs/vllm/PR-30585.md), [[Perf] Eliminate padding and slicing op for GPT-OSS with Flashinfer MXFP4 MXFP8 MoE](../sources/prs/vllm/PR-30647.md), [fused_moe_lora PDL improvements](../sources/prs/vllm/PR-30716.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [Add support for LoRA adapters in Nemotron-H models](../sources/prs/vllm/PR-30802.md), [[Compressed-Tensors] Simplify NVFP4 Conditions, enable marlin support for NVFP4A16 MoEs](../sources/prs/vllm/PR-30881.md), [[Mics] add pcp basic support to MoE model](../sources/prs/vllm/PR-31003.md), [[Bugfix] Fix GLM-4 MoE router logits dtype for data parallel chunking](../sources/prs/vllm/PR-31055.md), [[BugFix] LoRA: Support loading base_layer of experts](../sources/prs/vllm/PR-31104.md), [[Bugfix] Fix MoE LoRA bin/pt loading](../sources/prs/vllm/PR-31161.md), [[Kernel] Add topk_sigmoid kernel](../sources/prs/vllm/PR-31246.md), [pin lora_b moe weights on cpu](../sources/prs/vllm/PR-31317.md), [[Misc] Fix Qwen2-MoE shared_expert_gate](../sources/prs/vllm/PR-31339.md), [[BugFix] add select_gemm_impl on CompressedTensorsWNA16MoEMethod to support LoRA](../sources/prs/vllm/PR-31453.md), [[Bugfix][ROCm] Fix Static Quant Issue](../sources/prs/vllm/PR-31502.md), [[ROCm][Bugfix] Fix accuracy issue on fmoe when `VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS` enabled](../sources/prs/vllm/PR-31523.md), [[FIX] Add NO_MUL activation support for modular kernel path](../sources/prs/vllm/PR-31528.md), [Use the same memory for workspace13 and fused_output.](../sources/prs/vllm/PR-31531.md), [[Fix] Align fused moe lora_b shape with peft](../sources/prs/vllm/PR-31534.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[LoRA]Disable linear LoRA kernel PDL](../sources/prs/vllm/PR-31777.md), [[Perf] Fuse stride preparation for NVFP4 cutlass_moe](../sources/prs/vllm/PR-31837.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [Add TMA support to fused_moe_lora kernel](../sources/prs/vllm/PR-32195.md), [[Hardware][SM100] Add TRTLLM Kernel for INT4 W4A16 Kernel.](../sources/prs/vllm/PR-32437.md), [[Perf][Kernel] Optimize FP4 quantization kernels (SM100F)](../sources/prs/vllm/PR-32520.md), [fix: Add glm4_moe_lite to MLA detection](../sources/prs/vllm/PR-32614.md), [[Bugfix] Fix FP8 MoE EP Weight Loading for ModelOpt Llama4](../sources/prs/vllm/PR-32886.md), [[NVIDIA] [feat] Integrate flashinfer Trtllmgen bf16 moe](../sources/prs/vllm/PR-32954.md), [Add support for Mistral Large 3 inference with Flashinfer MoE](../sources/prs/vllm/PR-33174.md), [fix: Add SM120 (RTX Blackwell) support for FlashInfer CUTLASS NVFP4 MoE kernels](../sources/prs/vllm/PR-33417.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [Adding support to Sarvam's MoE models](../sources/prs/vllm/PR-33942.md), [[Bugfix]fix output Nan/Inf in marlin if dtype=float16](../sources/prs/vllm/PR-33972.md), [[Kernel] Optimize grouped topk kernel](../sources/prs/vllm/PR-34206.md), [[ModelBash][DSR1 NVFp4] Avoid Bf16 Bias Cast](../sources/prs/vllm/PR-34298.md), [[ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup)](../sources/prs/vllm/PR-34302.md), [[Kernel] Integrate SM100 MXFP8 blockscaled grouped MM and quant kernels](../sources/prs/vllm/PR-34448.md), [[Model] Add NVFP4 quantization support for Step3.5-Flash](../sources/prs/vllm/PR-34478.md), [[Bugfix] Handle num_expert_group=None in flashinfer block-scale FP8 MoE](../sources/prs/vllm/PR-34494.md), [[Quantization] add humming quantization kernel](../sources/prs/vllm/PR-34556.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [[Performance] Cublas Bf16 Gate with Fp32 Output](../sources/prs/vllm/PR-35121.md), [[Bugfix] Fix DSV3 kernels breaking _C and _moe_C on unsupported arches](../sources/prs/vllm/PR-35123.md), [[Bugfix] Fix expert_ids padding values in moe_align_block_size kernel](../sources/prs/vllm/PR-35161.md), [[Quant][Feature] Support online MXFP8 quantization for MoE and dense models](../sources/prs/vllm/PR-35448.md), [[MoE][Perf] Wrap DSV3 QKVAProj GEMM in custom op for torch.compile](../sources/prs/vllm/PR-35751.md), [[MoE] Move PF Methods to Folder](../sources/prs/vllm/PR-35927.md), [Add support for ModelOpt MXFP8 MoE models](../sources/prs/vllm/PR-35986.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[Kernel] Add FlashInfer MoE A2A Kernel](../sources/prs/vllm/PR-36022.md), [[Bugfix] Disable FlashInfer TRTLLM BF16 path for non-gated MoE](../sources/prs/vllm/PR-36146.md), [[Perf] Add TRTLLM FP8 MoE Modular Kernel](../sources/prs/vllm/PR-36307.md), [[XPU] Support block fp8 moe by fallback to TritonExpert on XPU](../sources/prs/vllm/PR-36458.md), [[Bug][MoE] Fix TRTLLM NVFP4 Routing Kernel Precision](../sources/prs/vllm/PR-36725.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[MoE Refactor] Mxfp4 oracle rebased](../sources/prs/vllm/PR-37128.md), [[Kernel] Add gpt-oss Router GEMM kernel](../sources/prs/vllm/PR-37205.md), [[MoE/EPLB] Fix FlashInfer nvfp4 experts + EPLB correctness](../sources/prs/vllm/PR-37217.md), [[Kernel] Add non-gated support for NVFP4 CUTLASS MoE](../sources/prs/vllm/PR-37320.md), [[Kernel] Add MXFP4 W4A4 CUTLASS MoE kernel for SM100](../sources/prs/vllm/PR-37463.md), [[4/n] Migrate FP4/W4A8 CUTLASS kernels to torch stable ABI](../sources/prs/vllm/PR-37503.md), [[Bugfix] Disable monolithic TRTLLM MoE for Renormalize routing (#37591)](../sources/prs/vllm/PR-37605.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[MoE] Move FlashInfer CuteDSL experts into fused_moe/experts/](../sources/prs/vllm/PR-37759.md), [[Feature] Support per-draft-model MoE backend via `--speculative-config`](../sources/prs/vllm/PR-37880.md), [[MoE Kernel] Flashinfer nvfp4 cutedsl moe kernel integration](../sources/prs/vllm/PR-38050.md), [[Quantization] Add FlashInfer CuteDSL batched experts backend for NVFP4 MoE](../sources/prs/vllm/PR-38251.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[Quant] add CompressedTensorsW8A8Mxfp8 for linear and MoE layers](../sources/prs/vllm/PR-38815.md), [[Bugfix] Re-enable Renormalize routing for TRT-LLM MoE experts](../sources/prs/vllm/PR-38859.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[Bug] Fix routing bias dtype for trtllm per-block fp8 moe](../sources/prs/vllm/PR-38989.md), [[Bugfix][MoE] Fix 6-8% decode regression: prefer multi-stream shared expert overlap](../sources/prs/vllm/PR-38990.md), [[Perf] Change Trtllm fp8 MoE to use Shuffled Weights and BlockMajorK Layout](../sources/prs/vllm/PR-38993.md), [[MoE] Move GPT OSS Triton kernel experts into fused_moe/experts/](../sources/prs/vllm/PR-39007.md), [[Gemma4] Support quantized MoE ](../sources/prs/vllm/PR-39045.md), [[Bug] Fix Trtllm Fp8 MoE Weight Shuffle Memory Fragamentation](../sources/prs/vllm/PR-39054.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [perf(moe): add tuned fused_moe config for RTX PRO 6000 Blackwell Server Edition](../sources/prs/vllm/PR-39183.md), [[Bugfix] FlashInfer MXINT4 MoE crashes, missing do_finalize](../sources/prs/vllm/PR-39315.md), [fix: clamp NaN/Inf in topk_softmax to prevent duplicate expert IDs](../sources/prs/vllm/PR-39391.md), [[Kernel] Support TRTLLM GEN NVFP4 MoE for non-512-aligned hidden dims via weight padding](../sources/prs/vllm/PR-39510.md), [[Bugfix] [Tests] Enforce `out` tensor device in `kernel/moe/test_cutedsl_moe.py`](../sources/prs/vllm/PR-39644.md), [[Bugfix] Fix mismatch between global and local attention heads in tensor-parallel mode for param2moe model](../sources/prs/vllm/PR-39707.md), [[Bugfix] Reject non-nvfp4 dtypes when using the flashinfer_nvlink_one_sided all2all backend](../sources/prs/vllm/PR-39717.md), [[Bugfix] Disable FlashInfer CUTLASS MoE on SM121 (DGX Spark)](../sources/prs/vllm/PR-39825.md), [[Core] Replace routing replay with device cache and async D2H pipeline](../sources/prs/vllm/PR-39917.md), [[Bugfix] Temporarily disable B200 fp4 MoE layer tests](../sources/prs/vllm/PR-40057.md), [[Bugfix] moe lora align kernel grid](../sources/prs/vllm/PR-40131.md), [Fix MoE backend selection for LoRA (unquantized MoE)](../sources/prs/vllm/PR-40273.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[DSV4] Add silu clamp limit to shared expert](../sources/prs/vllm/PR-40950.md), [[DSV4] Add BF16 and MXFP8 A2A support for flashinfer a2a one sided](../sources/prs/vllm/PR-40960.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [[DSV4] Fuse norm and router for low latency scenario](../sources/prs/vllm/PR-41263.md), [[ROCm][Quantization][3/N] Refactor quark_moe w4a4 w/ oracle](../sources/prs/vllm/PR-41436.md), [[Quantization] Rework quantization_config to use QuantKey and allow for activation override](../sources/prs/vllm/PR-41566.md), [[MXFP4] Support for linear layers + compressed-tensors integration](../sources/prs/vllm/PR-41664.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[LoRA] Support 2D and 3D MoE LoRA adapter at the same time](../sources/prs/vllm/PR-42242.md), [Refactor AWQ Marlin MoE onto modular WNA16 oracle](../sources/prs/vllm/PR-42483.md), [[Perf] Wire silu_and_mul_per_block_quant into TritonFP8MoE (MiniMax-M2) ](../sources/prs/vllm/PR-42497.md), [[Kernel] Pack topk id/weights triton kernel](../sources/prs/vllm/PR-42527.md), [[Bugfix] fix swiglu limit issue for humming backend + deepseek v4](../sources/prs/vllm/PR-42541.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [Fix Weight loading for Qwen3.5-MTP and Qwen3-VL using runai_streamer](../sources/prs/vllm/PR-42716.md), [[Refactor] Remove dead cuda kernels](../sources/prs/vllm/PR-42767.md), [[Perf] Re-enable flashinfer autotune by default and cleanup](../sources/prs/vllm/PR-42857.md), [[Model Refactoring] Migrate DeepSeek V4 to vllm/models/ [1/N] ](../sources/prs/vllm/PR-43004.md), [[Kernel] (2/N) Machete - Integrate into CompressedTensorsWNA16 and GPTQMarlin](../sources/prs/vllm/PR-7701.md), [Fused MoE — FP8 Block-Scale Routing + Dual GEMM](../wiki/kernels/fused-moe.md), [Grouped GEMM for MoE](../wiki/kernels/grouped-gemm.md) | -| `prefill` | [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[None][feat] Optimize causal_conv1d prefill and decode kernels](../sources/prs/TensorRT-LLM/PR-13103.md), [[None][feat] Add chunked prefill support for Gemma4 (text + vision multimodal)](../sources/prs/TensorRT-LLM/PR-14134.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [feat: update decode attention APIs](../sources/prs/flashinfer/PR-1007.md), [add multi-item scoring](../sources/prs/flashinfer/PR-1015.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [Parameterize prefix mask call (needed by POD-Attention)](../sources/prs/flashinfer/PR-1059.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [bugfix: fix fp8 attention kernels aot compilation issue](../sources/prs/flashinfer/PR-1087.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [[feat] add unified batch attention w/ correctness tests.](../sources/prs/flashinfer/PR-1137.md), [Fix FA2 and FA3 multi-item scoring and cuda illegal memory access error](../sources/prs/flashinfer/PR-1140.md), [Fix the issue with auxillary kernel launch and grid dim calculation](../sources/prs/flashinfer/PR-1208.md), [feat: Add non-causal cudnn prefill kernels](../sources/prs/flashinfer/PR-1230.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [Allow cudnn prefill kernels to be called natively](../sources/prs/flashinfer/PR-1317.md), [feat: Support logits_soft_cap for Persistent attn; fix kv split limit](../sources/prs/flashinfer/PR-1324.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [Allow BatchPrefillPagedWrapper to call cudnn API](../sources/prs/flashinfer/PR-1384.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [bugfix: Fix Persistent kernel precision for masked output ](../sources/prs/flashinfer/PR-1533.md), [feat: Integrate TRTLLM varlen kernel for deepseek R1 prefill ](../sources/prs/flashinfer/PR-1537.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [feat: Support for inferring out_dtype from out.dtype for TRTLLM attention kernel](../sources/prs/flashinfer/PR-1578.md), [fix: Improve TRTLLM attention kernel out_dtype unit test](../sources/prs/flashinfer/PR-1590.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [fix: pass workspace for trtllm-gen attention](../sources/prs/flashinfer/PR-1635.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [feat: Batch-size invariant FA2 Prefill & Decode](../sources/prs/flashinfer/PR-1675.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [Fix tests/test_trtllm_gen_attention.py::test_trtllm_batch_prefill, ::test_trtllm_batch_decode mismatch error](../sources/prs/flashinfer/PR-1755.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [fix: Fix trtllm-gen prefill IMA when batch_size==1](../sources/prs/flashinfer/PR-1912.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Added an initial implementation of Q and KV Cache in fp8 and to use t…](../sources/prs/flashinfer/PR-2035.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [[Feature] Support batch prefill for POD Attention](../sources/prs/flashinfer/PR-2079.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [fix: compile flags for trtllm fmha_v2 ](../sources/prs/flashinfer/PR-2175.md), [Fp8 attention are now part of cuDNN 9.17.1](../sources/prs/flashinfer/PR-2241.md), [feat: add GDN Attention](../sources/prs/flashinfer/PR-2276.md), [Added the cudnn backend Ragged KV Cache wrapper](../sources/prs/flashinfer/PR-2352.md), [feat: [Qwen3-Next] Add Cute DSL GDN decode kernel and tests](../sources/prs/flashinfer/PR-2370.md), [Remove cudaMalloc/Free in GDN prefill kernel](../sources/prs/flashinfer/PR-2415.md), [refactor: reduce hopper's gdn prefill compilation time and fix docstring.](../sources/prs/flashinfer/PR-2422.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [Ameyn/gdn decode cutedsl kernel](../sources/prs/flashinfer/PR-2498.md), [perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead](../sources/prs/flashinfer/PR-2509.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [fix: allow fmha_v2_prefill_deepseek on SM121 (DGX Spark)](../sources/prs/flashinfer/PR-2559.md), [fix: guard CUTLASS FMHA against SM12x and fix fmha_v2 SM121a check](../sources/prs/flashinfer/PR-2560.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [benchmarks: Add FP8 input / BF16 output in ragged prefill benchmark](../sources/prs/flashinfer/PR-2666.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [feat: Add DiT-oriented kernels where Qk (Bmm1) type can be reinterpreted into Int8 or BFloat16](../sources/prs/flashinfer/PR-2711.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [[fmha-v2] Support HND and NHD paged KV cache layouts with conditional stride handling](../sources/prs/flashinfer/PR-2799.md), [[fix] Bugfix 1367: fix VariableBlockSparseAttention buffer overflow by dynamically resizing kv_lens_buffer](../sources/prs/flashinfer/PR-2802.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [[Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D](../sources/prs/flashinfer/PR-2841.md), [read real strides for kv and block scale](../sources/prs/flashinfer/PR-2844.md), [feat(gdn): state checkpointing in chunk_gated_delta_rule](../sources/prs/flashinfer/PR-2908.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [test: xfail cuDNN FP8 prefill on Blackwell with CUDA <= 12.9](../sources/prs/flashinfer/PR-2963.md), [[feat] Add blackwell GDN prefill kernel](../sources/prs/flashinfer/PR-3001.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16](../sources/prs/flashinfer/PR-3129.md), [cute-dsl fmha prefill (cubin integration): remove front-padding, add attention_sink, and pdl support](../sources/prs/flashinfer/PR-3181.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [perf: fix the iteration bound of SWA in FA2 prefill template](../sources/prs/flashinfer/PR-714.md), [feat: support deepseek prefill attention shape](../sources/prs/flashinfer/PR-765.md), [perf: refactor fa2 prefill template](../sources/prs/flashinfer/PR-776.md), [feat: Separate QK/VO head dim dispatch for sm90 AOT](../sources/prs/flashinfer/PR-778.md), [bugfix: fix batch prefill attention kernel unittests](../sources/prs/flashinfer/PR-781.md), [bugfix: drop CTA_TILE_Q=32](../sources/prs/flashinfer/PR-785.md), [feat: support f32 attention output in FA2 template](../sources/prs/flashinfer/PR-799.md), [feat: apply sm_scale at logits instead of q in FA2 template](../sources/prs/flashinfer/PR-801.md), [perf: memory efficient deepseek mla fused page-attention kernel](../sources/prs/flashinfer/PR-804.md), [Add POD-Attention to FlashInfer](../sources/prs/flashinfer/PR-858.md), [Naive Support for Hopper FP8 Prefill Kernel with Per-Head Quantization](../sources/prs/flashinfer/PR-869.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [[2/2] Support MHA prefill with FlashAttention 4.](../sources/prs/sglang/PR-10937.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [DeepSeek-V3.2: Add Adaptive MHA Attention Pathway for Short-Sequence Prefill](../sources/prs/sglang/PR-11892.md), [[DeepSeek-V3.2][NSA] Enable MHA Pathway for Short Sequence Prefill on B200 (SM100)](../sources/prs/sglang/PR-12788.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [[AMD] Support fused_rms_mxfp4_quant in the prefill stage for DeepSeek-R1-MXFP4](../sources/prs/sglang/PR-14975.md), [Support Qwen3 MoE context parallel](../sources/prs/sglang/PR-18233.md), [feat(gdn): add FlashInfer K-last SSM layout support for GDN prefill and decode for Hopper](../sources/prs/sglang/PR-18361.md), [Fp8 prefill attn kernel integration](../sources/prs/sglang/PR-18528.md), [[AMD] Fp8 prefill integration with radix cache path for dpsk models](../sources/prs/sglang/PR-20187.md), [[GDN] Add benchmark for sglang gdn prefill](../sources/prs/sglang/PR-20428.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [[DSA] Support trtllm sparse mla kernel for prefill batches ](../sources/prs/sglang/PR-21783.md), [[KDA] Optimize prefill kernels with diagonal and recompute fuse](../sources/prs/sglang/PR-24271.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Introduce SchedulerDPAttnAdapter to own DP-attention state](../sources/prs/sglang/PR-25611.md), [Move DP-attention adapter methods to SchedulerDPAttnAdapter](../sources/prs/sglang/PR-25612.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [Support MHA with chunked prefix cache for DeepSeek chunked prefill](../sources/prs/sglang/PR-5113.md), [[PD] Fix dynamic port support and MLA buffer for Mooncake](../sources/prs/sglang/PR-5415.md), [Avoid computing lse in Ragged Prefill when there's no prefix.](../sources/prs/sglang/PR-5476.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [[PD] Add different TP sizes support for no-MLA models](../sources/prs/sglang/PR-6793.md), [Let EP prefill support new DeepGEMM](../sources/prs/sglang/PR-7310.md), [[Feature] Layer-wise Prefill](../sources/prs/sglang/PR-7634.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [Disable chunked prefill and/or prefix caching when MLA is enabled ](../sources/prs/vllm/PR-12642.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [[ROCm] Disable chunked prefill/prefix caching when running MLA on non-cuda platforms](../sources/prs/vllm/PR-13844.md), [Fix mla prefill context performance](../sources/prs/vllm/PR-13897.md), [[ROCm] Enable chunked prefill/paged attention in MLA on ROCm](../sources/prs/vllm/PR-14316.md), [[BugFix] Fix nightly MLA failure (FA2 + MLA chunked prefill, i.e. V1, producing bad results)](../sources/prs/vllm/PR-15492.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [[Kernel] Unified Triton kernel that doesn't distinguish between prefill + decode](../sources/prs/vllm/PR-16828.md), [[ROCm][Kernel][V1] Enable AMD Radeon GPU Custom Paged Attention on v1](../sources/prs/vllm/PR-17004.md), [[Bugfix][ROCm] Use `chunked_prefill_paged_decode` as fallback for V1 attention on ROCm](../sources/prs/vllm/PR-18093.md), [[Hardware][AMD] integrate aiter chunked prefill into vllm](../sources/prs/vllm/PR-18596.md), [[Attention] MLA - Flashinfer Ragged Prefill](../sources/prs/vllm/PR-20034.md), [[Kernel] Optimize Prefill Attention in Unified Triton Attention Kernel](../sources/prs/vllm/PR-20308.md), [[Model] Pooling models default to using chunked prefill & prefix caching if supported.](../sources/prs/vllm/PR-20930.md), [Override attention metadata for fast prefill in some KV sharing setups](../sources/prs/vllm/PR-21590.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [[NVIDIA] Support Flashinfer TRT-LLM Prefill Attention Kernel](../sources/prs/vllm/PR-22095.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [[Attention] Make `split_decodes_and_prefills(..., require_uniform=True)` support padding](../sources/prs/vllm/PR-29644.md), [[perf] Use direct copy (broadcast) instead of cat for k_nope/k_pe in MLA prefill](../sources/prs/vllm/PR-29710.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten](../sources/prs/vllm/PR-31380.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[Kernel] use flashinfer for gdn prefill](../sources/prs/vllm/PR-32846.md), [[Attention] Use FA4 for MLA prefill](../sources/prs/vllm/PR-34732.md), [[Bugfix][MLA] Add logits size budget to sparse indexer prefill chunking](../sources/prs/vllm/PR-36178.md), [[ROCm] Attention selector reordering](../sources/prs/vllm/PR-36702.md), [[Attention] Support distinguishing between short extends and decodes](../sources/prs/vllm/PR-37303.md), [[GDN] Eliminate GPU->CPU sync in prepare_chunk_indices during prefill](../sources/prs/vllm/PR-38361.md), [[Bugfix][MLA] Change default SM100 MLA prefill backend back to TRT-LLM](../sources/prs/vllm/PR-38562.md), [[Attention][MLA] Re-enable FA4 as default MLA prefill backend](../sources/prs/vllm/PR-38819.md), [[Gemma4] Enable Fast Prefill Optimization](../sources/prs/vllm/PR-38879.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[GDN] Enable FI Blackwell GDN prefill kernel](../sources/prs/vllm/PR-40717.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[Bugfix] Fix TRTLLM ragged MLA prefill workspace warmup](../sources/prs/vllm/PR-42112.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [Sparse MLA (DeepSeek V3.2)](../wiki/kernels/sparse-mla.md) | +| `attention` | [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Gated Delta Networks](../sources/blogs/gated-delta-net.md), [K-Search: LLM Kernel Generation via Co-Evolving Intrinsic World Model](../sources/blogs/k-search-kernel-generation.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [DeepSeek-V2: A Strong, Economical, and Efficient Mixture-of-Experts Language Model](../sources/docs/deepseek-v2-mla.md), [FlashAttention-4: Algorithm and Kernel Co-design for Blackwell GPUs](../sources/docs/flash-attention-4.md), [Native Sparse Attention: Hardware-Aligned and Natively Trainable Sparse Attention](../sources/docs/nsa.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [[TRTLLM-9798][feat] Change to use new DeepGEMM MQA sm100 kernel for MTP-3](../sources/prs/TensorRT-LLM/PR-10226.md), [[TRTLLM-10022][feat] Add hopper xqa decode support for skip softmax attention](../sources/prs/TensorRT-LLM/PR-10264.md), [[None][feat] Remove non flash attetnion style fmha_v2 kernel for hopper](../sources/prs/TensorRT-LLM/PR-11381.md), [[TRTLLM-11092][feat] add support for visual gen FA4 attention backend](../sources/prs/TensorRT-LLM/PR-11697.md), [[TRTLLM-11119][feat] Blackwell SageAttention, Integrate into AttentionOp API](../sources/prs/TensorRT-LLM/PR-11718.md), [[None][feat] Add fused DiT QK Norm + RoPE CUDA kernel for FLUX](../sources/prs/TensorRT-LLM/PR-11869.md), [[TRTLLM-10421][perf] Add fused cat+fp8_quantize CUDA kernel for DSA indexer](../sources/prs/TensorRT-LLM/PR-11899.md), [[None][feat] GLM 5 support and DSA MTP fixes](../sources/prs/TensorRT-LLM/PR-11990.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[TRTLLM-11285][feat] Fuse indexer wk + weights_proj into single GEMM in TF32 for DS-V3.2](../sources/prs/TensorRT-LLM/PR-12055.md), [[TRTLLM-11540][feat] Add EAGLE3 dynamic tree speculative decoding support](../sources/prs/TensorRT-LLM/PR-12062.md), [[TRTLLM-11289][feat] Integrate CuteDSL's bf16 dense GEMMs](../sources/prs/TensorRT-LLM/PR-12074.md), [[TRTLLM-10407][perf] Enable CuteDSL indexer_top_k in model](../sources/prs/TensorRT-LLM/PR-12236.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[https://nvbugs/5983390][perf] Kernel fusions in _gather_k_cache_for_chunk of Indexer in DSA](../sources/prs/TensorRT-LLM/PR-12322.md), [[None][feat] Temporally-Correlated Heuristic-guided Indexer TopK for Sparse Attention](../sources/prs/TensorRT-LLM/PR-12385.md), [[https://nvbugs/5983390][fix] Remove redundant D2H sync to optimize perf](../sources/prs/TensorRT-LLM/PR-12445.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[https://nvbugs/5983390][perf] Split MLA DSA custom op for piecewise CUDA graph capture](../sources/prs/TensorRT-LLM/PR-12503.md), [[https://nvbugs/5983390][perf] Multiple host perf optimizations for DSA part](../sources/prs/TensorRT-LLM/PR-12581.md), [[None][feat] Add triton paged attention for AutoDeploy](../sources/prs/TensorRT-LLM/PR-12642.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[TRTLLM-11485][feat] Feature rework: Add SageAttention refreshed kernels (attentionOp only)](../sources/prs/TensorRT-LLM/PR-12937.md), [[#12716][feat] Fused cross-head QK Norm + RoPE kernel for WAN](../sources/prs/TensorRT-LLM/PR-13052.md), [[TRTLLM-34871][feat] Add cute dsl FP8 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13219.md), [[None][feat] Integrate FP4 indexer for DSA on Blackwell](../sources/prs/TensorRT-LLM/PR-13340.md), [[TRTLLM-11285][perf] Force enable TF32 tensor cores for DSA indexer fused GEMM](../sources/prs/TensorRT-LLM/PR-13452.md), [[None][perf] Scheme X L2-aware dispatcher and PDL launchers for sparse-attention GVR Top-K](../sources/prs/TensorRT-LLM/PR-13477.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[TRTLLM-12128][feat] enable SageAttention for Wan/FLUX (new commits)](../sources/prs/TensorRT-LLM/PR-13570.md), [[TRTLLM-12316][feat] Integrate FP4 indexer for DSv4](../sources/prs/TensorRT-LLM/PR-13575.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[None][perf] Optimize DeepSeek-V4 compressor BF16 input](../sources/prs/TensorRT-LLM/PR-13761.md), [[None][fix] Use compressed lengths for DeepSeek-V4 indexer](../sources/prs/TensorRT-LLM/PR-13802.md), [[None][feat] Update FMHA cubins for head_dim 80](../sources/prs/TensorRT-LLM/PR-13808.md), [[TRTLLM-12503][feat] Parallel VAE independent scaling and fix arg passing](../sources/prs/TensorRT-LLM/PR-13873.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] Keep DSv4 o_a_proj as FP8, and port vLLM's fused_inv_rope_fp8_quant](../sources/prs/TensorRT-LLM/PR-13938.md), [[None][perf] Add CUDA q_b norm for DeepSeek V4](../sources/prs/TensorRT-LLM/PR-13975.md), [[None][feat] Enable 2 DSv4 perf optimizations by default](../sources/prs/TensorRT-LLM/PR-14120.md), [[None][feat] Add chunked prefill support for Gemma4 (text + vision multimodal)](../sources/prs/TensorRT-LLM/PR-14134.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][feat] DSv4: enable GVR Heuristic Top-K for compress_ratio=4](../sources/prs/TensorRT-LLM/PR-14219.md), [[None][refactor] clean up AttentionForwardArgs](../sources/prs/TensorRT-LLM/PR-14244.md), [[None][fix] Handle unset attention_dp_relax in ADP routers](../sources/prs/TensorRT-LLM/PR-14276.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [Add seqused_q in fwd / bwd and seqused_k in bwd in hopper FA.](../sources/prs/flash-attention/PR-1182.md), [Add local attention in Hopper FAv3](../sources/prs/flash-attention/PR-1233.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [Paged Attention support for FA3](../sources/prs/flash-attention/PR-1268.md), [FA3 paged attention: Readiness for Cutlass 3.6 / default value for block_table](../sources/prs/flash-attention/PR-1331.md), [Blackwell FlashAttention-BWD (v1.0)](../sources/prs/flash-attention/PR-1945.md), [[Cute,Fwd,Sm100] Support paged attention](../sources/prs/flash-attention/PR-1999.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [Add SM120 varlen attention support](../sources/prs/flash-attention/PR-2333.md), [[Fwd,Sm90] Add paged KV attention support (tma and cp.async)](../sources/prs/flash-attention/PR-2360.md), [feat: update decode attention APIs](../sources/prs/flashinfer/PR-1007.md), [misc: fix instrument code for mla profiler](../sources/prs/flashinfer/PR-1014.md), [add multi-item scoring](../sources/prs/flashinfer/PR-1015.md), [fix: add zero init for KV tiled copy](../sources/prs/flashinfer/PR-1029.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [[nvidia] Add Blackwell FMHA decode kernel from TRT-LLM](../sources/prs/flashinfer/PR-1051.md), [Fix KV chunking for POD. ](../sources/prs/flashinfer/PR-1054.md), [bugfix: temporally disable split-kv in blackwell mla](../sources/prs/flashinfer/PR-1055.md), [Parameterize prefix mask call (needed by POD-Attention)](../sources/prs/flashinfer/PR-1059.md), [bugfix: adding lse output to blackwell fmha kernels](../sources/prs/flashinfer/PR-1071.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [bugfix: fix fp8 attention kernels aot compilation issue](../sources/prs/flashinfer/PR-1087.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [hotfix: fix the blackwell fmha stream](../sources/prs/flashinfer/PR-1116.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [[feat] add unified batch attention w/ correctness tests.](../sources/prs/flashinfer/PR-1137.md), [Fix FA2 and FA3 multi-item scoring and cuda illegal memory access error](../sources/prs/flashinfer/PR-1140.md), [[feat] support block sparse attention w/ variable block sizes and head-wise sparse patterns](../sources/prs/flashinfer/PR-1177.md), [update trtllm-gen decode attention kernel launcher](../sources/prs/flashinfer/PR-1189.md), [bugfix: fix blackwell fmha hanging issue for empty kv_len](../sources/prs/flashinfer/PR-1198.md), [[feat] optimize persistent batch attention perf.](../sources/prs/flashinfer/PR-1200.md), [[fix] fix BatchAttention CTA_TILE_KV mask issue](../sources/prs/flashinfer/PR-1206.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [Bug fix: fix duplicate launch in POD](../sources/prs/flashinfer/PR-1267.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [[fix] fix integer overflow in FA2 customized_mask & add buffer overflow warning.](../sources/prs/flashinfer/PR-1290.md), [feat: Add k_scale and v_scale to persistent attention ](../sources/prs/flashinfer/PR-1322.md), [feat: Support logits_soft_cap for Persistent attn; fix kv split limit](../sources/prs/flashinfer/PR-1324.md), [Support passing kv_data_type to MultiLevelCascadeAttentionWrapper.plan()](../sources/prs/flashinfer/PR-1350.md), [Allow BatchPrefillPagedWrapper to call cudnn API](../sources/prs/flashinfer/PR-1384.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Adding FP8 benchmark on attention and matmul testing](../sources/prs/flashinfer/PR-1390.md), [benchmark: trtllm-gen mha with sink, add benchmark args](../sources/prs/flashinfer/PR-1415.md), [refactor: Sink attention AoT](../sources/prs/flashinfer/PR-1427.md), [feat: enable trtllm-gen attn speculative decoding verify by decode](../sources/prs/flashinfer/PR-1453.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [feat: integrate xqa attention backend](../sources/prs/flashinfer/PR-1503.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [bugfix: Fix Persistent kernel precision for masked output ](../sources/prs/flashinfer/PR-1533.md), [feat: Integrate TRTLLM varlen kernel for deepseek R1 prefill ](../sources/prs/flashinfer/PR-1537.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [bugfix: fix persistent attention kernel correctness on blackwell](../sources/prs/flashinfer/PR-1559.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [feat: Support for inferring out_dtype from out.dtype for TRTLLM attention kernel](../sources/prs/flashinfer/PR-1578.md), [fix: semaphoress must be at the fixed range in workspace buffer on trtllm_gen attention](../sources/prs/flashinfer/PR-1584.md), [fix: Improve TRTLLM attention kernel out_dtype unit test](../sources/prs/flashinfer/PR-1590.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: fix merge_attention_state in BatchAttention w/ gqa-group-size in Qwen family](../sources/prs/flashinfer/PR-1614.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [fix: pass workspace for trtllm-gen attention](../sources/prs/flashinfer/PR-1635.md), [fix: zero-init workspace buffer for trtllm-gen fmha](../sources/prs/flashinfer/PR-1643.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [Refactor Blackwell unit test scripts](../sources/prs/flashinfer/PR-1667.md), [feat: Add `variant.OutputTransform()` to decode kernels](../sources/prs/flashinfer/PR-1670.md), [feat: Batch-size invariant FA2 Prefill & Decode](../sources/prs/flashinfer/PR-1675.md), [[misc] add a wrapper class for attention sink jit args](../sources/prs/flashinfer/PR-1679.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [perf: Port the separate reduce kernel mode from trtllm.](../sources/prs/flashinfer/PR-1685.md), [bugfix: increase workspace to make trtllm gen attention unit test pass](../sources/prs/flashinfer/PR-1707.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [tests: xfail attention sink UT for sliding window + non causal case](../sources/prs/flashinfer/PR-1752.md), [Fix tests/test_trtllm_gen_attention.py::test_trtllm_batch_prefill, ::test_trtllm_batch_decode mismatch error](../sources/prs/flashinfer/PR-1755.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [Bugfix: Fix data hazard in persistent reduce](../sources/prs/flashinfer/PR-1826.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [Bugfix: fix o_strides in persistent kernel ](../sources/prs/flashinfer/PR-1865.md), [Tune kernel compilation parameters for https://github.com/flashinfer-ai/flashinfer/pull/1850 ](../sources/prs/flashinfer/PR-1878.md), [fix: Fix trtllm-gen prefill IMA when batch_size==1](../sources/prs/flashinfer/PR-1912.md), [MLA RoPE + quantization fused kernel: shape generalization for MHA / GQA](../sources/prs/flashinfer/PR-1924.md), [Add realistic bench for persistent kernel ](../sources/prs/flashinfer/PR-1942.md), [fix: Make attention microbenchmark correctly use page table](../sources/prs/flashinfer/PR-1976.md), [fix: Skipping attention sink Blackwell test outside of Blackwell](../sources/prs/flashinfer/PR-1978.md), [fix: correct PDL parameter handling in RopeQuantize kernel](../sources/prs/flashinfer/PR-1982.md), [minor fix for xqa](../sources/prs/flashinfer/PR-1994.md), [unittest: Add head dim 256 test cases and mark as xfail](../sources/prs/flashinfer/PR-1999.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Fix trtllm-gen attention illegal memory access](../sources/prs/flashinfer/PR-2002.md), [use scalar for kv_scale in xqa](../sources/prs/flashinfer/PR-2033.md), [Added an initial implementation of Q and KV Cache in fp8 and to use t…](../sources/prs/flashinfer/PR-2035.md), [feat: Add flashinfer.rope.rope_quantize_fp8_append_paged_kv_cache (fused RoPE + Q + KV cache, supports MLA/GQA/MHA) ](../sources/prs/flashinfer/PR-2037.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [feat: add xqa mla backend](../sources/prs/flashinfer/PR-2053.md), [misc: Add XQA decode to microbenchmark for sm90 and sm120](../sources/prs/flashinfer/PR-2055.md), [Fix: several bugs/issues with trtllm-gen attention kernels. ](../sources/prs/flashinfer/PR-2062.md), [unittest: improve the efficiency of xqa unittests](../sources/prs/flashinfer/PR-2075.md), [fix: fix test_trtllm_gen_attention when max_seq_len < page_size](../sources/prs/flashinfer/PR-2076.md), [[Feature] Support batch prefill for POD Attention](../sources/prs/flashinfer/PR-2079.md), [enable xqa fp8 output](../sources/prs/flashinfer/PR-2081.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [[DSR1] Added MLA test](../sources/prs/flashinfer/PR-2100.md), [enable xqa speculative decoding](../sources/prs/flashinfer/PR-2105.md), [feat: support more head dim in RoPE kernel](../sources/prs/flashinfer/PR-2109.md), [add tensor scale input for xqa](../sources/prs/flashinfer/PR-2110.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [feature: make the LSE returned by MLA support base 2 or e #2113](../sources/prs/flashinfer/PR-2114.md), [perf: bunch of features and optimizations for top-k (sampling + sparse attention)](../sources/prs/flashinfer/PR-2119.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [fix flaky xqa test](../sources/prs/flashinfer/PR-2126.md), [fix(trtllm): reset negative strideBatch to 0 for ragged KV layout to …](../sources/prs/flashinfer/PR-2134.md), [fix: some bugs of headDim 256 trtllm-gen fmha kernels. ](../sources/prs/flashinfer/PR-2137.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [refactor: Move mla code from decode.py to mla.py and add to documentation](../sources/prs/flashinfer/PR-2163.md), [fix: compile flags for trtllm fmha_v2 ](../sources/prs/flashinfer/PR-2175.md), [Permute page table in benchmarking](../sources/prs/flashinfer/PR-2194.md), [Fp8 attention are now part of cuDNN 9.17.1](../sources/prs/flashinfer/PR-2241.md), [feat: support non-contiguous query for trtllm-gen attention backend](../sources/prs/flashinfer/PR-2254.md), [fix: support int64 IdType for RoPE part argument in `rope_quantize_fp8_append_paged_kv_cache`](../sources/prs/flashinfer/PR-2255.md), [[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding](../sources/prs/flashinfer/PR-2265.md), [feat: add GDN Attention](../sources/prs/flashinfer/PR-2276.md), [fix: Decode benchmark's fa2_tc uses backend=fa2 in wrapper](../sources/prs/flashinfer/PR-2302.md), [Added the cudnn backend Ragged KV Cache wrapper](../sources/prs/flashinfer/PR-2352.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [fix: Fix memory bandwidth calculation in MLA benchmarks](../sources/prs/flashinfer/PR-2479.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [pick fa2 for BatchDecodeWithPagedKVCacheWrapper auto backend](../sources/prs/flashinfer/PR-2530.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [fix: allow fmha_v2_prefill_deepseek on SM121 (DGX Spark)](../sources/prs/flashinfer/PR-2559.md), [fix: guard CUTLASS FMHA against SM12x and fix fmha_v2 SM121a check](../sources/prs/flashinfer/PR-2560.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [support qk_nope_head_dim for 192 check for GLM-5](../sources/prs/flashinfer/PR-2607.md), [benchmark: Enable speculative decode microbenchmarking for paged decode](../sources/prs/flashinfer/PR-2628.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [benchmarks: Add FP8 input / BF16 output in ragged prefill benchmark](../sources/prs/flashinfer/PR-2666.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [feat: Add DiT-oriented kernels where Qk (Bmm1) type can be reinterpreted into Int8 or BFloat16](../sources/prs/flashinfer/PR-2711.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [[Spark unit test debugging] Fix for tests/attention/test_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-2750.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [feat: FP8 output support for CUTLASS MLA paged attention](../sources/prs/flashinfer/PR-2779.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [feat: Support padding tokens with seqlen=0 for rope+quant+kv cache update fusion kernel](../sources/prs/flashinfer/PR-2792.md), [[fmha-v2] Support HND and NHD paged KV cache layouts with conditional stride handling](../sources/prs/flashinfer/PR-2799.md), [[fix] Bugfix 1367: fix VariableBlockSparseAttention buffer overflow by dynamically resizing kv_lens_buffer](../sources/prs/flashinfer/PR-2802.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [[Spark unit test] Adjust tolerance for test_xqa, test_logits_processor](../sources/prs/flashinfer/PR-2828.md), [[Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D](../sources/prs/flashinfer/PR-2841.md), [[fix] bugfix 2856: Fix pre-allocated out shape check in trtllm_batch_decode_with_kv_cache_mla for q_len_per_req > 1](../sources/prs/flashinfer/PR-2876.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [test: xfail cuDNN FP8 prefill on Blackwell with CUDA <= 12.9](../sources/prs/flashinfer/PR-2963.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [cute-dsl fmha prefill (cubin integration): remove front-padding, add attention_sink, and pdl support](../sources/prs/flashinfer/PR-3181.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [Add dynamic tokens-per-page TRTLLM-GEN GQA kernels](../sources/prs/flashinfer/PR-3259.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [perf: fix the iteration bound of SWA in FA2 prefill template](../sources/prs/flashinfer/PR-714.md), [Align KV chunk size binary search with actual KV chunk splitting.](../sources/prs/flashinfer/PR-728.md), [feat: support deepseek prefill attention shape](../sources/prs/flashinfer/PR-765.md), [perf: refactor fa2 prefill template](../sources/prs/flashinfer/PR-776.md), [bugfix: fix batch prefill attention kernel unittests](../sources/prs/flashinfer/PR-781.md), [bugfix: MLA decode should multiply sm_scale by math::log2e](../sources/prs/flashinfer/PR-787.md), [fix rope logic in mla decoding](../sources/prs/flashinfer/PR-793.md), [feat: support f32 attention output in FA2 template](../sources/prs/flashinfer/PR-799.md), [feat: apply sm_scale at logits instead of q in FA2 template](../sources/prs/flashinfer/PR-801.md), [perf: memory efficient deepseek mla fused page-attention kernel](../sources/prs/flashinfer/PR-804.md), [bugfix: mla page-attention kernel for different page sizes](../sources/prs/flashinfer/PR-810.md), [feat: unlocking MLA for A100](../sources/prs/flashinfer/PR-812.md), [feat: unlock MLA attention for sm89 (L40/L40s/4090)](../sources/prs/flashinfer/PR-814.md), [bugfix: bugfix on sm89 MLA](../sources/prs/flashinfer/PR-821.md), [perf: MLA decode kernel implemented by CuTe targeted to SM80](../sources/prs/flashinfer/PR-844.md), [Add POD-Attention to FlashInfer](../sources/prs/flashinfer/PR-858.md), [perf: dynamic split-k for MLA](../sources/prs/flashinfer/PR-863.md), [bugfix: fix the behavior of MLA kernel when kv-length is 0](../sources/prs/flashinfer/PR-868.md), [Naive Support for Hopper FP8 Prefill Kernel with Per-Head Quantization](../sources/prs/flashinfer/PR-869.md), [perf: FlashAttention-3 style MLA PageAttention](../sources/prs/flashinfer/PR-887.md), [perf: fix MLA split-k performance bug](../sources/prs/flashinfer/PR-898.md), [perf: tweak the pipeline design of mla kernel](../sources/prs/flashinfer/PR-901.md), [feat: flashinfer intra-kernel profiler](../sources/prs/flashinfer/PR-913.md), [bugfix: fix potential issues of FA3 template loading nans for PageAttention](../sources/prs/flashinfer/PR-945.md), [perf: Use 2WG pipeline design for MLA implementation on Hopper](../sources/prs/flashinfer/PR-952.md), [[TVM] Added tvm binding for sampling kernel](../sources/prs/flashinfer/PR-958.md), [perf: prefetch page indices for mla kernel](../sources/prs/flashinfer/PR-991.md), [3rdparty: upgrade cutlass to 3.9](../sources/prs/flashinfer/PR-997.md), [[FlexAttention] Remove Old Constraint on lastdim strides](../sources/prs/pytorch/PR-153104.md), [[FlexAttention] explicilty create grad_q w/ strides](../sources/prs/pytorch/PR-153641.md), [[SDPA] [MPS] Fixes regression in 2.8.0 for scaled_dot_product_attention using mps](../sources/prs/pytorch/PR-164364.md), [[Flex attention] Fix flex attention head broadcast](../sources/prs/pytorch/PR-164368.md), [[flex_attention] adds support for low precision K/V inputs in compiled mode with GPU](../sources/prs/pytorch/PR-170486.md), [[cherry-pick] Fix vllm issue for flex (#170499)](../sources/prs/pytorch/PR-170555.md), [[RELEASE 2.11] Release only changes](../sources/prs/pytorch/PR-175091.md), [[MPS] Fix 2-pass SDPA memory corruption by forcing float accumulators](../sources/prs/pytorch/PR-175580.md), [[release 2.12] Apply Release only changes to 2.12 branch](../sources/prs/pytorch/PR-180470.md), [Disable kernel cutlass_mla_decode on SM103](../sources/prs/sglang/PR-10058.md), [feat: Add FP4 (E2M1) KV Cache Support with Quantization Utilities for MLA](../sources/prs/sglang/PR-10078.md), [[Feature] Add MLAProcess for DeepSeek MLA on NPU](../sources/prs/sglang/PR-10130.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [support qwen3_next blackwell](../sources/prs/sglang/PR-10403.md), [Fix cutlass moe accuracy drop caused by attention UB from DP padding mode](../sources/prs/sglang/PR-10414.md), [Enable trtllm mla prefix extend](../sources/prs/sglang/PR-10526.md), [Fuse quantize and rope in trtllm_mla MTP](../sources/prs/sglang/PR-10779.md), [[2/2] Support MHA prefill with FlashAttention 4.](../sources/prs/sglang/PR-10937.md), [[NVIDIA] FA3/FA4 Fix ](../sources/prs/sglang/PR-11606.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [Use trtllm_mla decode kernel for draft extend in speculative decoding](../sources/prs/sglang/PR-11664.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [Change bf16 to fp8 for some gemms in attention for DeepSeek ckpt v2](../sources/prs/sglang/PR-11805.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [DeepSeek-V3.2: Add Adaptive MHA Attention Pathway for Short-Sequence Prefill](../sources/prs/sglang/PR-11892.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [(1/n)support context parallel with deepseekv3.2-DSA](../sources/prs/sglang/PR-12065.md), [[Ascend] qwen optimization](../sources/prs/sglang/PR-12078.md), [[Ascend][feature] support L1+ L2 radixcache on ascend](../sources/prs/sglang/PR-12214.md), [[DeepseekV32]: use `_concat_mla_absorb_q_general` to replace `torch.cat`](../sources/prs/sglang/PR-12215.md), [[Deepseek V3.2] Enable flashmla_auto with MTP](../sources/prs/sglang/PR-12294.md), [fix seqlen bug for trtllm_mla's draft_extend](../sources/prs/sglang/PR-12295.md), [perf: trtllm mla performance minor improvements](../sources/prs/sglang/PR-12435.md), [[Ascend] Support enable-mixed-chunk in non-MLA scenarios](../sources/prs/sglang/PR-12491.md), [[DeepSeek-V3.2][NSA] Enable MHA Pathway for Short Sequence Prefill on B200 (SM100)](../sources/prs/sglang/PR-12788.md), [[Deepseek V3.2] Only skip Indexer logits computation when is_extend_without_speculative](../sources/prs/sglang/PR-12816.md), [[Deepseek V3.2] Use torch.compile to speed up torch.cat in nsa](../sources/prs/sglang/PR-13022.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Aiter fp8 kv cache](../sources/prs/sglang/PR-13147.md), [Support internvl on Blackwell (which doesn't support fa3): add `SingletonCache` support to Vision{Sdpa|Triton|Ascend}Attention](../sources/prs/sglang/PR-13151.md), [diffusion: enable fa4 for blackwell](../sources/prs/sglang/PR-13263.md), [[BugFix] fix prefixcache performance and accuracy on ascend](../sources/prs/sglang/PR-13573.md), [[DeepSeekV3.2] Enable pure TP & Partial DP Attention](../sources/prs/sglang/PR-13646.md), [fix trtllm mla spec](../sources/prs/sglang/PR-13738.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Use trtllm mha decode kernel for target_verify in speculative decoding](../sources/prs/sglang/PR-13976.md), [fix: Increase FlashInfer workspace size for Qwen3VL models](../sources/prs/sglang/PR-14173.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [Tiny use trtllm_mha as default when possible](../sources/prs/sglang/PR-14291.md), [[Fix] add block size logic for sm120 smem size](../sources/prs/sglang/PR-14311.md), [sync attention, deepseek doc](../sources/prs/sglang/PR-14335.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [[NPU] perf update with kvcache nz & w4a8 quant](../sources/prs/sglang/PR-14423.md), [Add Mistral Large 3 Eagle Support](../sources/prs/sglang/PR-14466.md), [[NPU][eagle3] support qwen eagle3 on NPU](../sources/prs/sglang/PR-14820.md), [fix: trtllm mha attention auto-selection on sm120](../sources/prs/sglang/PR-14842.md), [Fix dsv3 dp accuracy issue when using bf16-kv](../sources/prs/sglang/PR-14897.md), [Fix accuracy issue when using a16w16 mla_decode_fwd](../sources/prs/sglang/PR-14936.md), [fix(attention): Prevent trtllm_mha auto-selection with eagle3 speculative decoding](../sources/prs/sglang/PR-15127.md), [[NVIDIA] upstream FA4](../sources/prs/sglang/PR-15182.md), [[NPU]DeepSeek-V3.2 support npu mlaprolog](../sources/prs/sglang/PR-15381.md), [[diffusion] Add Sage Attention 3 Support for sm 120 (RTX5090)](../sources/prs/sglang/PR-15382.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [Fix BatchMLAPagedAttentionWrapper query/qo_inptr mismatch for EAGLE](../sources/prs/sglang/PR-15601.md), [[jit-kernel] Add CuTe DSL GDN Decode Kernel](../sources/prs/sglang/PR-15631.md), [[diffusion] model: support TurboWan2.1-T2V-1.3B/14B SLA](../sources/prs/sglang/PR-15888.md), [Bugfix for ds-vl2](../sources/prs/sglang/PR-15894.md), [Support fa4 decoding](../sources/prs/sglang/PR-16034.md), [optimize get_topk_ragged by fusing get k and k_scale triton kernel](../sources/prs/sglang/PR-16043.md), [enhance accuracy for model kimi-vl-instruct-a3b](../sources/prs/sglang/PR-16076.md), [[VLM] Adopt jit qk_norm kernel in VLM](../sources/prs/sglang/PR-16171.md), [[diffusion] Fix RuntimeError in SageAttention3 on Nvidia Blackwell with Qwen-Image](../sources/prs/sglang/PR-16335.md), [[Fix]Fix FA3 Performance in Diffusion Model ](../sources/prs/sglang/PR-16382.md), [[DeepSeek v3.2] Opt MTP decode cuda batch sizes and nsa implementation](../sources/prs/sglang/PR-16961.md), [[NPU]bugfix: fix for dsv3.2 and dsvl2](../sources/prs/sglang/PR-17007.md), [Optimize GDN decode for Qwen3 Next](../sources/prs/sglang/PR-17094.md), [[diffusion] fix: fix using upstream flash_attn on blackwell](../sources/prs/sglang/PR-17111.md), [Enable XQA for SM90 and SM120](../sources/prs/sglang/PR-17115.md), [[New Model] GLM4.7-Flash](../sources/prs/sglang/PR-17247.md), [Disable mla persistent kernel when not using fp8 kv_cache](../sources/prs/sglang/PR-17327.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [[NPU] enhance accuracy for model kimi-vl-a3b-instruct](../sources/prs/sglang/PR-17480.md), [Kernel: optimize decoding metadata in NSA multi-spec backend with fused kernels](../sources/prs/sglang/PR-17554.md), [Feat/add fi selective state update kernel call](../sources/prs/sglang/PR-18070.md), [Support Qwen3 MoE context parallel](../sources/prs/sglang/PR-18233.md), [[ROCm] Optimize Deepseek R1 on MI300X](../sources/prs/sglang/PR-18242.md), [[AMD] Support Qwen3-Coder-Next on AMD platform](../sources/prs/sglang/PR-18355.md), [feat(gdn): add FlashInfer K-last SSM layout support for GDN prefill and decode for Hopper](../sources/prs/sglang/PR-18361.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [feat: add FA4 SM90 paged KV decode support & update attention docs](../sources/prs/sglang/PR-18442.md), [Tilelang sparse decode fwd for dsv32 mi355](../sources/prs/sglang/PR-18488.md), [Fp8 prefill attn kernel integration](../sources/prs/sglang/PR-18528.md), [[AMD] Fix accuracy issue when running TP4 dsv3 model with mtp](../sources/prs/sglang/PR-18607.md), [[sgl-kernel] rebase FlashMLA 0217](../sources/prs/sglang/PR-18902.md), [Fix NSA FP8 KV cache path for both-trtllm MHA one-shot](../sources/prs/sglang/PR-18931.md), [Support skip-softmax attention](../sources/prs/sglang/PR-19089.md), [[DeepSeek-V3.2][JIT-kernel] Support nsa fuse store indexer k cache](../sources/prs/sglang/PR-19148.md), [[NVIDIA] Integrate FlashInfer decode kernel (Blackwell) for Qwen3.5](../sources/prs/sglang/PR-19150.md), [[AMD] Fix accuracy while using --enable-dp-attention](../sources/prs/sglang/PR-19247.md), [[Feature] add feature mla_ag_after_qlora for dsv3.2](../sources/prs/sglang/PR-19428.md), [[NPU] bugs fix for Deepseek models](../sources/prs/sglang/PR-19544.md), [[miles] fix for glm5](../sources/prs/sglang/PR-19634.md), [Fix MLA decode path returning unwritten (padded) rows](../sources/prs/sglang/PR-19902.md), [[AMD] Fix Tensor Memory Aliasing ](../sources/prs/sglang/PR-19928.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [[AMD] Tilelang sparse fwd for dsv32 mi355/mi300](../sources/prs/sglang/PR-19945.md), [MiniMax-M2.5 - Support dp attention, dp reduce scatter, FP4 all gather, AR fusion in prepare_attn](../sources/prs/sglang/PR-20067.md), [[AMD] Fp8 prefill integration with radix cache path for dpsk models](../sources/prs/sglang/PR-20187.md), [[AMD] Add 4-GPU test suite for MI325 runners](../sources/prs/sglang/PR-20294.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[AMD][Bug-fix] Fix gpu fault when run the test with dp-attention-enabled and max-concurrency is over 256](../sources/prs/sglang/PR-20399.md), [[AMD][AITER] Guard _use_mla_ps_kernel with self.use_mla in draft_extend_v2 paths](../sources/prs/sglang/PR-20409.md), [[GDN] Add benchmark for sglang gdn prefill](../sources/prs/sglang/PR-20428.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [[Diffusion] Clean upstream fa3 in hopper](../sources/prs/sglang/PR-20576.md), [Use Flashinfer for target_verify in GDN model for SM120](../sources/prs/sglang/PR-20604.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [ci: run Stage A CUDA tests as stage-a-test-small-1-gpu on 5090](../sources/prs/sglang/PR-20988.md), [perf: precompute FA3 scheduler_metadata to eliminate per-layer prepare_varlen_num_blocks](../sources/prs/sglang/PR-21104.md), [[Not-Merge][AMD] GLM-5 performance optimization](../sources/prs/sglang/PR-21166.md), [[Whisper] Enable CUDA graph support and timestamp for whisper model](../sources/prs/sglang/PR-21190.md), [[KDA] Support CuTeDSL KDA decode kernel](../sources/prs/sglang/PR-21203.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [[GDN] Fuse GDN kkt + solve_tril into one kernel](../sources/prs/sglang/PR-21411.md), [[Bugfix] Lazy-import CuteDSL KDA kernel to fix AMD/ROCm startup crash](../sources/prs/sglang/PR-21428.md), [fix nemotron capture for non attention layers](../sources/prs/sglang/PR-21436.md), [fix: piecewise_cuda_graph get correct qo_indptr](../sources/prs/sglang/PR-21452.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [Change default mm-attention backend from triton_attn to fa4](../sources/prs/sglang/PR-21595.md), [fix: TRT-LLM MHA CUDA illegal address with EAGLE v2 + DP attention](../sources/prs/sglang/PR-21649.md), [[XPU] Enable qwen3.5 on XPU](../sources/prs/sglang/PR-21668.md), [[DSA] Support trtllm sparse mla kernel for prefill batches ](../sources/prs/sglang/PR-21783.md), [[Bugfix] Temporarily skip TRTLLM attention on (G)B300 (SM103) to avoid high-concurrency hang](../sources/prs/sglang/PR-21906.md), [[Bugfix] Fix CUDA graph replay issues in trtllm_mla draft_extend](../sources/prs/sglang/PR-21987.md), [[NPU] enable mla prepare fused kernel only when being mla attn](../sources/prs/sglang/PR-22024.md), [[MUSA][9/N] Add FA3 attention backend support through MATE (MUSA AI Tensor Engine)](../sources/prs/sglang/PR-22051.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [Reduce unnecessary kernels and copies in the NSA indexer](../sources/prs/sglang/PR-22232.md), [[AMD][HIP] NSA: bf16 passthrough from RMSNorm to eliminate FP8 dequantization](../sources/prs/sglang/PR-22258.md), [Lazy import flash_attention_v4 to avoid loading flash_attn.cute at startup](../sources/prs/sglang/PR-22306.md), [[DSA] Hopper FP8 FlashMLA KV padding](../sources/prs/sglang/PR-22372.md), [[AMD] Use aiter CK layernorm2d for LayerNorm to reduce NSA indexer kernel launches](../sources/prs/sglang/PR-22424.md), [[Fix] Fix several bugs on DSA models](../sources/prs/sglang/PR-22430.md), [[BugFix] Resolve adaptive speculative decoding conflicts for Qwen3.5 (hybrid GDN)](../sources/prs/sglang/PR-23331.md), [[Diffusion][NPU]Add attention backends for diffusion models for Ascend NPU](../sources/prs/sglang/PR-23482.md), [[feat] Init true on policy with qwen_dense](../sources/prs/sglang/PR-23961.md), [Enable PDL for various kernels in DSV32/GLM5](../sources/prs/sglang/PR-23965.md), [[KDA] Optimize prefill kernels with diagonal and recompute fuse](../sources/prs/sglang/PR-24271.md), [Support spec v2 for FlashMLA speculative decoding](../sources/prs/sglang/PR-24640.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [Fix AMX GQA extend attention](../sources/prs/sglang/PR-25180.md), [[NSA] Avoid repeated NSA MQA logits memory queries](../sources/prs/sglang/PR-25299.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [Support draft extend cuda graph for tokenspeed_mla attention backend](../sources/prs/sglang/PR-25489.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [Use triton_attn as default vision attention on B300 (SM103)](../sources/prs/sglang/PR-25570.md), [Introduce SchedulerDPAttnAdapter to own DP-attention state](../sources/prs/sglang/PR-25611.md), [Move DP-attention adapter methods to SchedulerDPAttnAdapter](../sources/prs/sglang/PR-25612.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [feat: support flashinfer mla attention for deepseek v3](../sources/prs/sglang/PR-3550.md), [feat: support flashinfer mla with prefix cache](../sources/prs/sglang/PR-3643.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [Support overlapping two batches](../sources/prs/sglang/PR-4068.md), [avoid cudaStreamSynchronize in DeepSeekV2AttentionMLA](../sources/prs/sglang/PR-4577.md), [Fix loading KV quantization scale; Enable modelopt kv cache](../sources/prs/sglang/PR-4686.md), [[Model] Adding Qwen3 and Qwen3MoE](../sources/prs/sglang/PR-4693.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [Support (1 <= dp < tp) in the dp attention in DeepEP](../sources/prs/sglang/PR-4770.md), [Feat/support encoder model (like bert)](../sources/prs/sglang/PR-4887.md), [Support MHA with chunked prefix cache for DeepSeek chunked prefill](../sources/prs/sglang/PR-5113.md), [Blackwell Cutlass MLA kernel](../sources/prs/sglang/PR-5142.md), [feat: use fa3 mla by default on hopper](../sources/prs/sglang/PR-5210.md), [Add Speculative Decoding Eagle3 topk > 1](../sources/prs/sglang/PR-5318.md), [fix: solve cu118 issue for cutlass mla](../sources/prs/sglang/PR-5331.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[Feat] upgrade pytorch2.6](../sources/prs/sglang/PR-5417.md), [BLackwell cutlass mla: Add check for bad page size/block num combinations](../sources/prs/sglang/PR-5431.md), [Avoid computing lse in Ragged Prefill when there's no prefix.](../sources/prs/sglang/PR-5476.md), [[PP] Add pipeline parallelism](../sources/prs/sglang/PR-5724.md), [Fuse MLA set kv cache kernel](../sources/prs/sglang/PR-5748.md), [opt flashinfer mla cat](../sources/prs/sglang/PR-5822.md), [Cutlass MLA decode - fix dtype error](../sources/prs/sglang/PR-5868.md), [[Fix] Fix a bug for flashmla to run R1 model](../sources/prs/sglang/PR-5875.md), [Improve dp attention port assignment scheme](../sources/prs/sglang/PR-5889.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [Cutlass MLA: Disable split kv due to https://github.com/NVIDIA/cutlass/issues/2274](../sources/prs/sglang/PR-6101.md), [feat: add dp attention support for Qwen 2/3 MoE models, fixes #6088](../sources/prs/sglang/PR-6121.md), [Enable FlashInfer support encoder models and add head_dim padding workaround](../sources/prs/sglang/PR-6230.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [[CPU] support the case where num_attention_heads or intermediate_size is not divisible by the TP size](../sources/prs/sglang/PR-6771.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [Fix cutlass MLA gets almost zero accuracy](../sources/prs/sglang/PR-6998.md), [Tiny fix cutlass_mla_get_workspace_size stub incorrect signature](../sources/prs/sglang/PR-7057.md), [chore: upgrade sgl-kernel v0.1.8.post2](../sources/prs/sglang/PR-7186.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [feat: support compatibility between MTP and two-batch-overlap](../sources/prs/sglang/PR-7225.md), [Minor style and doc fix](../sources/prs/sglang/PR-7228.md), [Support non-contiguous query input for extend/decode attention](../sources/prs/sglang/PR-7462.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [TRTLLM-MLA FP8 path](../sources/prs/sglang/PR-8638.md), [feat: add trtllm-gen mha from direct call](../sources/prs/sglang/PR-8782.md), [Support DP attention with GPT-OSS](../sources/prs/sglang/PR-9359.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [support using fa4 on deepseek on blackwell](../sources/prs/sglang/PR-9928.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Kernel] Flash Attention 3 Support](../sources/prs/vllm/PR-12093.md), [[Core] Optimizing cross-attention `QKVParallelLinear` computation](../sources/prs/vllm/PR-12325.md), [[ROCm] Faster Custom Paged Attention kernels](../sources/prs/vllm/PR-12348.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Attention] Deepseek v3 MLA support with FP8 compute](../sources/prs/vllm/PR-12601.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [[AMD][ROCm] Enable DeepSeek model on ROCm](../sources/prs/vllm/PR-12662.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [[VLM] Add MLA with pure RoPE support for deepseek-vl2 models](../sources/prs/vllm/PR-12729.md), [[Kernel] Make rotary_embedding ops more flexible with input shape](../sources/prs/vllm/PR-12777.md), [[Attention] Use FA3 for MLA on Hopper](../sources/prs/vllm/PR-12807.md), [Expand MLA to support most types of quantization](../sources/prs/vllm/PR-13181.md), [[Bugfix] Massage MLA's usage of flash attn for RoCM](../sources/prs/vllm/PR-13310.md), [[ROCM] fix native attention function call](../sources/prs/vllm/PR-13650.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[Bugfix] Support MLA for CompressedTensorsWNA16](../sources/prs/vllm/PR-13725.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [[Kernel] FlashMLA integration](../sources/prs/vllm/PR-13747.md), [[Attention] MLA support for V1](../sources/prs/vllm/PR-13789.md), [[ROCm] Disable chunked prefill/prefix caching when running MLA on non-cuda platforms](../sources/prs/vllm/PR-13844.md), [[Attention] Flash MLA for V1](../sources/prs/vllm/PR-13867.md), [Fix mla prefill context performance](../sources/prs/vllm/PR-13897.md), [[V1] EP/TP MoE + DP Attention](../sources/prs/vllm/PR-13931.md), [[V1] Implement sliding window attention in kv_cache_manager](../sources/prs/vllm/PR-14097.md), [[v1] Add comments to the new ragged paged attention Pallas kernel](../sources/prs/vllm/PR-14155.md), [[V1][TPU] TPU multimodal model support for ragged attention](../sources/prs/vllm/PR-14158.md), [[V1][TPU] Support V1 Sampler for ragged attention](../sources/prs/vllm/PR-14227.md), [[Hardware] Update the flash attn tag to support Blackwell](../sources/prs/vllm/PR-14244.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[BugFix] MLA + V1, illegal memory access and accuracy issues](../sources/prs/vllm/PR-14253.md), [[BugFix] Fix prefix caching V0 MLA](../sources/prs/vllm/PR-14255.md), [[Attention] FlashAttn MLA](../sources/prs/vllm/PR-14258.md), [[Hardware][TPU]Enable ragged paged attention kernel and resolve recompilation issue](../sources/prs/vllm/PR-14310.md), [[Bug] Fix Attention when ignored in by quant_method](../sources/prs/vllm/PR-14313.md), [[ROCm] Enable chunked prefill/paged attention in MLA on ROCm](../sources/prs/vllm/PR-14316.md), [[Perf] Reduce MLA CPU overheads in V1](../sources/prs/vllm/PR-14384.md), [[Bugfix] DeepSeek Accuracy](../sources/prs/vllm/PR-14476.md), [[Perf] Improve MLA on V1](../sources/prs/vllm/PR-14540.md), [[Attention] Flash Attention 3 - fp8](../sources/prs/vllm/PR-14570.md), [[Kernel][CPU] CPU MLA](../sources/prs/vllm/PR-14744.md), [[Attention] MLA get rid of materialization](../sources/prs/vllm/PR-14770.md), [[Attention] Get rid of mla cache alignment](../sources/prs/vllm/PR-14842.md), [[V1][BugFix] Detect interleaved sliding window attention](../sources/prs/vllm/PR-14896.md), [[FEAT][ROCm] Integrate Paged Attention Kernel from AITER](../sources/prs/vllm/PR-15001.md), [[Bugfix] Fix incorrect qwen2.5-vl attention mask pre-computation](../sources/prs/vllm/PR-15200.md), [[Bugfix] Fix use_cascade_attention handling for Alibi-based models on vllm/v1](../sources/prs/vllm/PR-15211.md), [[Misc] Add attention mask pre-computation optimization back to Qwen2.5-VL](../sources/prs/vllm/PR-15273.md), [[BugFix] Fix nightly MLA failure (FA2 + MLA chunked prefill, i.e. V1, producing bad results)](../sources/prs/vllm/PR-15492.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [[TPU] Support sliding window and logit soft capping in the paged attention kernel for TPU.](../sources/prs/vllm/PR-15732.md), [[FEAT][ROCm]: Support AITER MLA](../sources/prs/vllm/PR-15893.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[ROCM] Add gfx950 to the custom attention archs](../sources/prs/vllm/PR-16034.md), [Add FlexAttention to V1](../sources/prs/vllm/PR-16078.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Kernel] support merge_attn_states CUDA kernel, 3x speedup](../sources/prs/vllm/PR-16173.md), [[Bug] [ROCm] Fix Llama 4 Enablement Bug on ROCm: V0 ROCmFlashAttentionImpl and Triton Fused MoE bugs](../sources/prs/vllm/PR-16198.md), [[Llama4] Enable attention temperature tuning by default for long context (>32k)](../sources/prs/vllm/PR-16439.md), [Allocate kv_cache with stride order](../sources/prs/vllm/PR-16605.md), [[MLA] Simplification to batch P/D reordering](../sources/prs/vllm/PR-16673.md), [[V1] V1 FlashInfer Attention](../sources/prs/vllm/PR-16684.md), [[torch.compile][ROCm] Fuse quantization onto attention using a torch.compile pass](../sources/prs/vllm/PR-16756.md), [[Kernel] Unified Triton kernel that doesn't distinguish between prefill + decode](../sources/prs/vllm/PR-16828.md), [Update PyTorch to 2.7.0](../sources/prs/vllm/PR-16859.md), [[Attention] FA3 decode perf improvement - single mma warp group support for head dim 128](../sources/prs/vllm/PR-16864.md), [[Bugfix] Triton FA function takes no keyword arguments](../sources/prs/vllm/PR-16902.md), [[ROCm][Kernel][V1] Enable AMD Radeon GPU Custom Paged Attention on v1](../sources/prs/vllm/PR-17004.md), [[Bugfix] Add contiguous call inside rope kernel wrapper](../sources/prs/vllm/PR-17091.md), [[ROCm][FP8][Kernel] FP8 quantization fused into Custom Paged Attention](../sources/prs/vllm/PR-17139.md), [[Bugfix] gemma[2,3] interleaved attention when sliding window is disabled](../sources/prs/vllm/PR-17180.md), [[Bugfix] Get a specific type of layer from forward context](../sources/prs/vllm/PR-17222.md), [[BugFix] Fix vllm_flash_attn install issues](../sources/prs/vllm/PR-17267.md), [[BugFix] Fix cascade attention - RuntimeError: scheduler_metadata must have shape (metadata_size)](../sources/prs/vllm/PR-17283.md), [[v1] AttentionMetadata for each layer](../sources/prs/vllm/PR-17394.md), [[v1] Pass BlockTable and KVCacheSpec to AttentionMetadataBuilders](../sources/prs/vllm/PR-17483.md), [[Attention] MLA move o_proj q_proj into cuda-graph region](../sources/prs/vllm/PR-17484.md), [[BugFix] Fix mla cpu - missing 3 required positional arguments](../sources/prs/vllm/PR-17494.md), [[FEAT][ROCm]: Support AITER MLA on V1 Engine](../sources/prs/vllm/PR-17523.md), [[Attention] MLA move rotary embedding to cuda-graph region](../sources/prs/vllm/PR-17668.md), [fix amd triton mla path](../sources/prs/vllm/PR-17871.md), [[Bugfix][ROCm] Fix AITER MLA V1](../sources/prs/vllm/PR-17880.md), [[BugFix][AMD] Compatible patch for AITER lib after 04/20](../sources/prs/vllm/PR-17912.md), [[v1] Support multiple KV cache groups in GPU model runner](../sources/prs/vllm/PR-17945.md), [[BUG] [ROCm] [MLA] Fix variable name bug due to change in variable name in PR #17483](../sources/prs/vllm/PR-17961.md), [[Bugfix][ROCm] Use `chunked_prefill_paged_decode` as fallback for V1 attention on ROCm](../sources/prs/vllm/PR-18093.md), [[Hardware][AMD] integrate aiter chunked prefill into vllm](../sources/prs/vllm/PR-18596.md), [[BugFix] FA2 MLA Accuracy Issue](../sources/prs/vllm/PR-18807.md), [[P/D] Heterogeneous TP](../sources/prs/vllm/PR-18833.md), [[Kernel] Apply torch.Tag.needs_fixed_stride_order only for torch==2.6.0](../sources/prs/vllm/PR-19346.md), [[Core] Support Local Chunked Attention for Hybrid KV Cache](../sources/prs/vllm/PR-19351.md), [[Bugfix][V1] Allow manual FlashAttention for Blackwell](../sources/prs/vllm/PR-19492.md), [[Bugfix] Enable PP with AITER+V1](../sources/prs/vllm/PR-19822.md), [Enable V1 for Hybrid SSM/Attention Models](../sources/prs/vllm/PR-20016.md), [[Attention] MLA - Flashinfer Ragged Prefill](../sources/prs/vllm/PR-20034.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [[Kernel] Optimize Prefill Attention in Unified Triton Attention Kernel](../sources/prs/vllm/PR-20308.md), [Update PyTorch to 2.8.0](../sources/prs/vllm/PR-20358.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[v1][core] Support for attention free models](../sources/prs/vllm/PR-20811.md), [[Bugfix] Voxtral on Blackwell GPUs (RTX 50 series)](../sources/prs/vllm/PR-21077.md), [[Kernel] Flashinfer MLA (trtllm-gen) decode kernel integration](../sources/prs/vllm/PR-21078.md), [[v1] Add Whisper model support (encoder-decoder)](../sources/prs/vllm/PR-21088.md), [[Attention] Optimize FlashInfer MetadataBuilder Build call](../sources/prs/vllm/PR-21137.md), [[Attention][DBO] Add support for "splitting" the CommonAttentionMetadata](../sources/prs/vllm/PR-21153.md), [[Attention] Clean up iRoPE in V1](../sources/prs/vllm/PR-21188.md), [[Kernel] Enable Hybrid Model Support in Triton Unified Attention Kernel](../sources/prs/vllm/PR-21197.md), [[v1] - Mamba1 Attention Metadata](../sources/prs/vllm/PR-21249.md), [Support encoder-only models without KV-Cache](../sources/prs/vllm/PR-21270.md), [[v1][attention] Support Hybrid Allocator + FlashInfer](../sources/prs/vllm/PR-21412.md), [Updates to Flex + VLLm integration](../sources/prs/vllm/PR-21416.md), [[V1] Fix local chunked attention always disabled](../sources/prs/vllm/PR-21419.md), [[BugFix] Fix shared storage connector load kv only load attention layer](../sources/prs/vllm/PR-21428.md), [update flashinfer to v0.2.9rc1](../sources/prs/vllm/PR-21485.md), [[Attention] Support multiple attention metadata builders per kv_cache_spec + proper local attention no hybrid kv cache fix](../sources/prs/vllm/PR-21588.md), [Override attention metadata for fast prefill in some KV sharing setups](../sources/prs/vllm/PR-21590.md), [[BugFix] Fix IMA FlashMLA full cuda-graph and DP + Update FlashMLA](../sources/prs/vllm/PR-21691.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [[Perf] Disable chunked local attention by default with llama4](../sources/prs/vllm/PR-21761.md), [[Bugfix] Check NVIDIA artifactory is accessible before using flashinfer cubin kernels](../sources/prs/vllm/PR-21893.md), [[Qwen3] Enable dual-chunk-attention support for Qwen3 models.](../sources/prs/vllm/PR-21924.md), [[NVIDIA] Support Flashinfer TRT-LLM Prefill Attention Kernel](../sources/prs/vllm/PR-22095.md), [[fix] fix correct assertion syntax error in attention utils.](../sources/prs/vllm/PR-22154.md), [Fp8 paged attention update](../sources/prs/vllm/PR-22222.md), [Support encoder_only attention for FlexAttention](../sources/prs/vllm/PR-22273.md), [Upgrade FA3 for attention sink](../sources/prs/vllm/PR-22313.md), [[Bugfix] Add proper comparison for package versions](../sources/prs/vllm/PR-22314.md), [[ROCm] Add attention sink to use_rocm_custom_paged_attention](../sources/prs/vllm/PR-22329.md), [[BugFix] Fix triton compile error in `kernel_unified_attention_2/3d` caused by attention sinks](../sources/prs/vllm/PR-22368.md), [[bugfix] Fix Llama3/4 issues caused by FlashInfer 0.2.10](../sources/prs/vllm/PR-22426.md), [[Attention] FA3 Attention Sinks Perf Boost](../sources/prs/vllm/PR-22478.md), [[Bugfix] Fix ModernBert load & Enable sliding window attention for bidirectional attention.](../sources/prs/vllm/PR-22637.md), [Support multiple attention groups for KV sharing](../sources/prs/vllm/PR-22672.md), [Force TRTLLM attention for gpt-oss on SM100](../sources/prs/vllm/PR-22678.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [fp8 kv cache support fix for torch.compile](../sources/prs/vllm/PR-22758.md), [[Bugfix gpt-oss] Fix float32 convert for flashinfer sink support](../sources/prs/vllm/PR-23016.md), [[V1] address post issues related to #20059 (part 1); cascade attention reenable by default](../sources/prs/vllm/PR-23046.md), [[Misc] Add @tdoublep as a maintainer of hybrid model and Triton-attention related code](../sources/prs/vllm/PR-23122.md), [[Log] Warning Once for Cutlass MLA ](../sources/prs/vllm/PR-23137.md), [Optimize input preparation for FlashInfer [2/N]](../sources/prs/vllm/PR-23174.md), [[Attention] Optimize make_local_attention_virtual_batches for Flash Attention](../sources/prs/vllm/PR-23185.md), [[Misc][qwen2_5_vl][torch.compile] Enable `supports_torch_compile` on generic nn.Module and demonstrate speedup on Qwen Vision model](../sources/prs/vllm/PR-23207.md), [[Core] Always use tensor cores for Flashinfer Decode Wrapper](../sources/prs/vllm/PR-23214.md), [[ROCm][Aiter] Add triton fp8 bmm kernel for mla](../sources/prs/vllm/PR-23264.md), [[Compile] Fix Compile Warning SM100 Cutlass MLA](../sources/prs/vllm/PR-23287.md), [[Attention] Allow V1 flash_attn to support cross-attention](../sources/prs/vllm/PR-23297.md), [[Bugfix] Fixing division by zero in triton_attn if query_heads/kv_heads > 16 ](../sources/prs/vllm/PR-23424.md), [[Perf] Warmup FlashInfer attention during startup](../sources/prs/vllm/PR-23439.md), [[Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-23465.md), [fix(v1/kv_cache): resolve async KV transfer bug in cascade attention](../sources/prs/vllm/PR-23485.md), [[Misc] Simplify FlashInfer attention metadata](../sources/prs/vllm/PR-23585.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[v1] Add cross-attention KV cache support for encoder-decoder models](../sources/prs/vllm/PR-23664.md), [[Core/DBO][1/N] Add Dual-Batch Overlap mechanism to VLLM](../sources/prs/vllm/PR-23693.md), [[FlashInfer] Cache hyper params in metadata builder](../sources/prs/vllm/PR-23732.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[BugFix][FlashInfer] Fix potential race condition for paged_kv_indptr_cpu](../sources/prs/vllm/PR-23737.md), [[Kernel] cuda kernels for upcoming decode context parallel feature](../sources/prs/vllm/PR-23791.md), [[Misc] add reorder_batch AttentionMetadataBuilder](../sources/prs/vllm/PR-23798.md), [Feature/vit attention unification# 23880](../sources/prs/vllm/PR-23978.md), [[Kernel] Support decode context parallelism on Blackwell with CUTLASS MLA](../sources/prs/vllm/PR-24385.md), [[Feature] Disallow FlashMLA on Blackwell](../sources/prs/vllm/PR-24521.md), [[Bug] Fix `is_flashmla_supported` Check Error](../sources/prs/vllm/PR-24774.md), [[DCP] Support Decode Context Parallel (DCP) for GQA with FlashAttention](../sources/prs/vllm/PR-24864.md), [[Bugfix][B200] Fix `cutlass_mla` hang](../sources/prs/vllm/PR-24966.md), [[Attention][DCP] Support DCP with query length > 1 (MTP) with FA3](../sources/prs/vllm/PR-25049.md), [[Bug] Fix `returned_lse` not Defined issue](../sources/prs/vllm/PR-25106.md), [[BugFix] Fix MLA assert with CUTLASS MLA](../sources/prs/vllm/PR-25478.md), [[Bugfix] [B200] cutlass_mla - ensure kv_split == 1 for batch size > 1](../sources/prs/vllm/PR-25509.md), [[Flashinfer][gpt-oss] Support FP8-qkv Flashinfer TRTLLM Sinks Attention](../sources/prs/vllm/PR-25674.md), [[Performance] Split FlashAttn attention and cache update](../sources/prs/vllm/PR-25954.md), [[Spec Decode] Enable efficient speculative decoding with FlashInfer-MLA](../sources/prs/vllm/PR-25984.md), [Move query quantization to attention layer for Flashinfer & Triton.](../sources/prs/vllm/PR-26534.md), [[Attention] Tune CUTLASS MLA num_splits](../sources/prs/vllm/PR-26846.md), [[BUGFIX][ROCM] ViT FlashAttention on ROCm (no GFX9) and contiguous on qwen3vl ROCm TORCH_SDPA](../sources/prs/vllm/PR-27190.md), [[Bugfix] Ensure calculated KV scales are applied in attention.](../sources/prs/vllm/PR-27232.md), [Prefer FlashAttention MLA as default over FlashMLA](../sources/prs/vllm/PR-27363.md), [[Misc] Make reorder batch also separate extends](../sources/prs/vllm/PR-27367.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[AMD] Use Decoupled Kernel Block Size to Support AITER MLA block_size=1](../sources/prs/vllm/PR-27715.md), [[Bug] Batch invariant: Fix flash attn MLA `RuntimeError: scheduler_metadata must have shape (metadata_size)`](../sources/prs/vllm/PR-27884.md), [Update Flashinfer from `v0.4.1` to `v0.5.2`](../sources/prs/vllm/PR-27952.md), [[FlashInfer] Avoid FlashInfer block_size 16 + head_size 256 on blackwell](../sources/prs/vllm/PR-27994.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Mamba] - Consolidate Mambas Attention Logic](../sources/prs/vllm/PR-28133.md), [fix cross attention](../sources/prs/vllm/PR-28346.md), [[ROCm] Support for Whisper v1 with Aiter Unified Attention and Aiter Flash Attention](../sources/prs/vllm/PR-28376.md), [[Bugfix] Fix SM100 gpt-oss regression due to faulty attn sink support](../sources/prs/vllm/PR-28561.md), [[Attention][Bugfix] Fix FA sink support](../sources/prs/vllm/PR-28660.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [[Model] Add support for openPangu moe model](../sources/prs/vllm/PR-28775.md), [bugfix: correct attn output with base 2 or e](../sources/prs/vllm/PR-28840.md), [[BugFix] Fix async-scheduling + FlashAttn MLA](../sources/prs/vllm/PR-28990.md), [[Feature] Batch invariant: Enable `TRITON_MLA` without prefix-caching](../sources/prs/vllm/PR-29125.md), [[Attention] Cache attention metadata builds across hybrid KV-cache groups](../sources/prs/vllm/PR-29627.md), [[Attention] Make `split_decodes_and_prefills(..., require_uniform=True)` support padding](../sources/prs/vllm/PR-29644.md), [[perf] Use direct copy (broadcast) instead of cat for k_nope/k_pe in MLA prefill](../sources/prs/vllm/PR-29710.md), [[Perf] Improve fp8 quant in mla; replace ReduceSum with ReduceScatterSum](../sources/prs/vllm/PR-29795.md), [[SpecDecode] Simplified alternative padded-speculation acceptance rate fix](../sources/prs/vllm/PR-29845.md), [[Quantization] fix: overflow with static per-tensor scaling](../sources/prs/vllm/PR-29867.md), [[BugFix] Fix DBO assert `assert B_block_table == B_q`](../sources/prs/vllm/PR-29933.md), [Add llmcompressor fp8 kv-cache quant (per-tensor and per-attn_head)](../sources/prs/vllm/PR-30141.md), [[ROCm][Bugfix] Add MLACommonMetadata to allowed attention types for speculative decoding](../sources/prs/vllm/PR-30430.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Bugfix] Pass FA version in `MultiHeadAttention`](../sources/prs/vllm/PR-30575.md), [Triton Attention: Support cross-layers blocks](../sources/prs/vllm/PR-30687.md), [OffloadingConnector: Support kernel_block_size != block_size](../sources/prs/vllm/PR-30692.md), [[Misc][LLaMa4] Compile LLaMa Vision Encoder](../sources/prs/vllm/PR-30709.md), [Update note comment for flashinfer attention warmup](../sources/prs/vllm/PR-30711.md), [[Bugfix] Fix broken ViT attention selection for Blackwell device](../sources/prs/vllm/PR-30731.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[Kernels][FI] Skip trtllm attention when num_kv_heads=1](../sources/prs/vllm/PR-30842.md), [[Bugfix] [Kernel] Triton attention kernels: mask out V blocks that fall outside sliding window](../sources/prs/vllm/PR-30887.md), [[Bugfix] Fix incorrect tiles creation for mm prefix triton attention](../sources/prs/vllm/PR-30974.md), [[Misc] Fix grammar errors in comments and messages](../sources/prs/vllm/PR-31115.md), [[perf] Integrate flashinfer concat_mla_k](../sources/prs/vllm/PR-31171.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][Hardware][AMD] Fix last_page_len calculation in AITER MLA decode](../sources/prs/vllm/PR-31282.md), [fix(rocm): add early return in get_flash_attn_version for ROCm](../sources/prs/vllm/PR-31286.md), [[Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten](../sources/prs/vllm/PR-31380.md), [fixed mypy warnings for files vllm/v1/attention with TEMPORARY workaround](../sources/prs/vllm/PR-31465.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[MISC] Add strict contiguity check for FlashInfer attention tensors](../sources/prs/vllm/PR-32008.md), [[4/N][Attention] Move MLA common to model_executor](../sources/prs/vllm/PR-32060.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [fix: Add glm4_moe_lite to MLA detection](../sources/prs/vllm/PR-32614.md), [[Bugfix][Attention] Explicitly report support for kv_cache_dtype bfloat16](../sources/prs/vllm/PR-32795.md), [[Spec Decode] Unified Parallel Drafting](../sources/prs/vllm/PR-32887.md), [[ROCm][perf] Shuffle KV cache to use paged_attention_common](../sources/prs/vllm/PR-32914.md), [[Attention] FA4 integration](../sources/prs/vllm/PR-32974.md), [[Attention] Use `has_flashinfer` helper](../sources/prs/vllm/PR-33177.md), [[Bugfix] Disable TRTLLM attention when KV transfer is enabled](../sources/prs/vllm/PR-33192.md), [[PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K]](../sources/prs/vllm/PR-33291.md), [Triton MLA perf fixes](../sources/prs/vllm/PR-33529.md), [[Perf] Disable clean_logits in deepgemm fp8_mqa_logits kernel](../sources/prs/vllm/PR-33568.md), [[Bugfix] Fix sparse MLA metadata building](../sources/prs/vllm/PR-33579.md), [[Bugfix] fix DeepSeek R1 with CUTLASS MLA Broken on B200](../sources/prs/vllm/PR-33637.md), [enable skipping of SW attention layers when using FP8 KV cache](../sources/prs/vllm/PR-33695.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [Reapply [Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-34043.md), [[Bugfix] Relax TRTLLM KV cache contiguity assertion for cross-layer layout](../sources/prs/vllm/PR-34158.md), [[Bugfix] Fix DP Attention Padding in Dummy Run](../sources/prs/vllm/PR-34187.md), [[CPU][Perf] Accelerate Attention head for s390x using vector intrinsics](../sources/prs/vllm/PR-34434.md), [[BugFix] Add support for MTP num_speculative_tokens > 1 with sparse MLA](../sources/prs/vllm/PR-34552.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [[Update] Use FlashInfer fast_decode_plan directly instead of replication](../sources/prs/vllm/PR-34687.md), [[Bugfix] Fix MLA attention crash with AWQ/GPTQ quantized models](../sources/prs/vllm/PR-34695.md), [[Attention] Use FA4 for MLA prefill](../sources/prs/vllm/PR-34732.md), [[Bugfix] Fix GDN attention crash with mixed decode/spec-decode batches](../sources/prs/vllm/PR-34871.md), [[Model Bash][DSR1] Add selective dynamic shape marking for CustomOp](../sources/prs/vllm/PR-34900.md), [[Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2](../sources/prs/vllm/PR-34917.md), [[Model Runner V2] Support attention group](../sources/prs/vllm/PR-35036.md), [[Bug][DSV3.2] Always prepare metadata for DeepGEMM Sparse Attention](../sources/prs/vllm/PR-35075.md), [[Linear Attention] fix bug for linear attention + prefix caching + reset_prefix_cache](../sources/prs/vllm/PR-35157.md), [[BUGFIX][Mamba][Qwen3.5] Zero freed SSM cache blocks on GPU](../sources/prs/vllm/PR-35219.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[Attention][Perf] Optimize cp_gather_and_upconvert_fp8_kv_cache - DeepSeek-v3.2](../sources/prs/vllm/PR-35290.md), [[Performance] Extract KV cache update op from flashinfer forward](../sources/prs/vllm/PR-35422.md), [Fix routed experts capture for hybrid models (Mamba + Attention)](../sources/prs/vllm/PR-35744.md), [[ROCm] Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5/Linear)](../sources/prs/vllm/PR-35850.md), [[Perf] Support FP8 KV cache for Flashinfer MLA Sparse](../sources/prs/vllm/PR-35891.md), [[BugFix] Fallback from FA4->FA2 for Batch Invariance](../sources/prs/vllm/PR-36059.md), [Add 320 dimension size support to MLA](../sources/prs/vllm/PR-36161.md), [[Bugfix][MLA] Add logits size budget to sparse indexer prefill chunking](../sources/prs/vllm/PR-36178.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [mla: don't update kv cache on dummy forwards](../sources/prs/vllm/PR-36282.md), [Disable cascade attention by default](../sources/prs/vllm/PR-36318.md), [feat(attention): extract KV-cache update from FlashAttentionDiffKV ba…](../sources/prs/vllm/PR-36466.md), [[Kernel] Fuse FP8 output quantization into merge_attn_states](../sources/prs/vllm/PR-36518.md), [[Bugfix][Sparse MLA] report indexer CG support properly](../sources/prs/vllm/PR-36519.md), [[ROCm] Utilize persistent MLA kernel from AITER](../sources/prs/vllm/PR-36574.md), [[Misc][Attention] Clean up unused method in `CPU_ATTN`](../sources/prs/vllm/PR-36673.md), [fix(kv-cache): increase hybrid attention grouping threshold from 1.25 to 1.5](../sources/prs/vllm/PR-36684.md), [[ROCm] Attention selector reordering](../sources/prs/vllm/PR-36702.md), [[DSV3.2][MTP] Optimize Indexer MTP handling](../sources/prs/vllm/PR-36723.md), [[ROCm] Fix KV copy methods and auto-select attention backend for ROCm](../sources/prs/vllm/PR-36845.md), [[ROCm] Validate block_size for explicitly selected attention backends](../sources/prs/vllm/PR-36846.md), [[Feat][Spec Decode] DFlash](../sources/prs/vllm/PR-36847.md), [[Feat][Bugfix] Enable additional dimension for Flashinfer MLA and fix routing dtype](../sources/prs/vllm/PR-36931.md), [[MTP][Sparse MLA] Take advantage of native MTP support in indexer when possible](../sources/prs/vllm/PR-36982.md), [[Bugfix] Fix KV scales inconsistency in fp8 MLA & FlashInfer kv_cache_dtype "auto" leading to gibberish](../sources/prs/vllm/PR-37054.md), [[Bugfix] Disable cross-layer KV cache for MLA attention backends](../sources/prs/vllm/PR-37090.md), [[Benchmark] Improvements to attention benchmark script](../sources/prs/vllm/PR-37115.md), [[XPU] support MLA model on Intel GPU](../sources/prs/vllm/PR-37143.md), [[Misc] Add `float16` to `CacheDType`](../sources/prs/vllm/PR-37199.md), [[ROCM][Bugfix] Use correct stride in cp_mha_gather_cache_kernel for hybrid model (#37228)](../sources/prs/vllm/PR-37228.md), [[Perf] Set Flashinfer sparse MLA as default backend for FP8 kv cache](../sources/prs/vllm/PR-37252.md), [[Attention] Support distinguishing between short extends and decodes](../sources/prs/vllm/PR-37303.md), [Add nvfp4 support to reshape_and_cache_flash](../sources/prs/vllm/PR-37332.md), [[Model Runner V2] fix draft attention metadata generation](../sources/prs/vllm/PR-37364.md), [[torch.compile] Refactor Attention Quant Fusion Pass and Remove Boilerplate](../sources/prs/vllm/PR-37373.md), [[Perf][Kernel] Persistent TopK scheduler: unified CUDAGraph-safe kernel with dynamic per-row dispatch - DeepSeek-V3.2 DSA decode](../sources/prs/vllm/PR-37421.md), [[BugFix] Allow qk_nope_head_dim=192 in FlashInfer MLA backend checks](../sources/prs/vllm/PR-37475.md), [[Performance] Remove unnecessary zero-fill of MLA decode output tensor in Aiter backend](../sources/prs/vllm/PR-37539.md), [[Bugfix][ROCm] Fix lru_cache on paged_mqa_logits_module](../sources/prs/vllm/PR-37547.md), [[Bugfix] Disable --calculate-kv-scales for hybrid GDN/Mamba+Attention…](../sources/prs/vllm/PR-37565.md), [[ROCm][Bugfix] fix cache block size mismatch for aiter unified attention](../sources/prs/vllm/PR-37606.md), [[NIXL][BUG] Fix Triton heterogeneous TP](../sources/prs/vllm/PR-37940.md), [[Perf] FP8 FlashInfer Attn for ViT](../sources/prs/vllm/PR-38065.md), [[Model Runner V2] Rebuild attention metadata before eagle decode full…](../sources/prs/vllm/PR-38311.md), [[GDN] Eliminate GPU->CPU sync in prepare_chunk_indices during prefill](../sources/prs/vllm/PR-38361.md), [[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity](../sources/prs/vllm/PR-38479.md), [[Bugfix][MLA] Change default SM100 MLA prefill backend back to TRT-LLM](../sources/prs/vllm/PR-38562.md), [[ROCm] Fix aiter persistent mode mla with q/o nhead<16 for kimi-k2.5 tp8](../sources/prs/vllm/PR-38615.md), [Fix MLA runs when use_inductor_graph_partition=True](../sources/prs/vllm/PR-38631.md), [[FA4] Update flash-attention to latest upstream FA4](../sources/prs/vllm/PR-38690.md), [[Bugfix] Restrict TRTLLM attention to SM100, fixing GB300 (SM103) hang](../sources/prs/vllm/PR-38730.md), [[Bugfix] Fix test mocks after SM100 restriction in #38730](../sources/prs/vllm/PR-38791.md), [[Perf] Reduce H2D pageable memory copies](../sources/prs/vllm/PR-38794.md), [[FlashAttention] Symlink FA4 instead of copying when using `VLLM_FLASH_ATTN_SRC_DIR`](../sources/prs/vllm/PR-38814.md), [[Attention][MLA] Re-enable FA4 as default MLA prefill backend](../sources/prs/vllm/PR-38819.md), [[Attention] relax the head dim 512 and paged kv for sm90+FA4](../sources/prs/vllm/PR-38835.md), [[Refactor] Improve indexer decode path metadata preparation](../sources/prs/vllm/PR-38865.md), [[Bugfix] Fix broken explicit unquantized kv cache dtype support](../sources/prs/vllm/PR-38922.md), [[Quantization] - Layerwise reloading of Attention/KV quantized models](../sources/prs/vllm/PR-38995.md), [[Bugfix] Fix FlashInfer crash with kv_cache_dtype_skip_layers](../sources/prs/vllm/PR-39002.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [[ROCm] Align AiterFlashAttentionImpl attn_type check with backend](../sources/prs/vllm/PR-39119.md), [[Bug] Fix rocm sparse attn indexer issue](../sources/prs/vllm/PR-39225.md), [[Model Runner V2] Fix flex attention kv blocks calculation issue](../sources/prs/vllm/PR-39353.md), [[MLA] Optimize mla indexer prepare uniform decode for MTP > 1](../sources/prs/vllm/PR-39458.md), [[Bugfix] Fix tensor shape mismatch in sparse attention with speculative decoding](../sources/prs/vllm/PR-39542.md), [[XPU] properly handle q_descale on XPU as quant query input not supported](../sources/prs/vllm/PR-39676.md), [[Bugfix] Fix mismatch between global and local attention heads in tensor-parallel mode for param2moe model](../sources/prs/vllm/PR-39707.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[Bugfix] add support for 'num_attention_groups' in ModelArchConfigConvertorBase for Step3p5](../sources/prs/vllm/PR-39796.md), [[Attention] use diff kv backend for mimo v2 flash](../sources/prs/vllm/PR-40045.md), [Add nvfp4 kv cache support](../sources/prs/vllm/PR-40177.md), [[Attention][TurboQuant] Share dequant buffers, eliminate float16_copy](../sources/prs/vllm/PR-40941.md), [[Bugfix][Hybrid][NemotronH] Fix mamba_cache_mode=all + speculative decoding crash](../sources/prs/vllm/PR-41233.md), [[DSv4] Improved fused Indexer Q quant kernel](../sources/prs/vllm/PR-41428.md), [fix: remove unused norm for dpskv4](../sources/prs/vllm/PR-41710.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[feat] Add FP8 per-tensor Q scale support to Triton attention backend](../sources/prs/vllm/PR-42080.md), [[Bugfix] Fix TRTLLM ragged MLA prefill workspace warmup](../sources/prs/vllm/PR-42112.md), [[DSv4] Improved dequant gather K cache kernel](../sources/prs/vllm/PR-42236.md), [[Bugfix] mamba: run single-token extends as decodes](../sources/prs/vllm/PR-42430.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [[CPU] Add fused GDN support for AMX CPU platform](../sources/prs/vllm/PR-42707.md), [[CPU] Specify required KV cache layout for CPU attention backend](../sources/prs/vllm/PR-42740.md), [[Refactor] Remove dead cuda kernels](../sources/prs/vllm/PR-42767.md), [[ROCm] [Bugfix] Fix DeepSeek V4 Functionality and Accuracy](../sources/prs/vllm/PR-42810.md), [[Perf] Add do_not_specialize in fused FP8 RoPE kernel](../sources/prs/vllm/PR-42849.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [add cutedsl dsv4 indexer fp8 kernel](../sources/prs/vllm/PR-42899.md), [[XPU] update xpu graph usage](../sources/prs/vllm/PR-43043.md), [[Model Refactoring] Move deepseek_v4_ops to models/deepseek_v4 [3/N]](../sources/prs/vllm/PR-43073.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [Native Sparse Attention (NSA)](../wiki/kernels/nsa.md), [DeepSeek Sparse Attention / Sparse MLA](../wiki/kernels/sparse-mla.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md) | +| `batched-gemv` | [Twelve Attempts at an FP4 Kernel](../sources/blogs/amandeep-nvfp4-attempts.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md) | +| `decode` | [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [[TRTLLM-10022][feat] Add hopper xqa decode support for skip softmax attention](../sources/prs/TensorRT-LLM/PR-10264.md), [[https://nvbugs/5669671][fix] Support GuidedDecoder with sharded logits (pick #10698)](../sources/prs/TensorRT-LLM/PR-10742.md), [[TRTLLM-10407][feat] Integrate CuTE DSL top-k kernel for Blackwell](../sources/prs/TensorRT-LLM/PR-11900.md), [[TRTLLM-11540][feat] Add EAGLE3 dynamic tree speculative decoding support](../sources/prs/TensorRT-LLM/PR-12062.md), [[None][feat] Temporally-Correlated Heuristic-guided Indexer TopK for Sparse Attention](../sources/prs/TensorRT-LLM/PR-12385.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[None][feat] Add PDL support to CuTE DSL top-k kernels](../sources/prs/TensorRT-LLM/PR-12506.md), [[None][feat] Optimize causal_conv1d prefill and decode kernels](../sources/prs/TensorRT-LLM/PR-13103.md), [[TRTLLM-34871][feat] Add cute dsl FP8 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13219.md), [[None][perf] Scheme X L2-aware dispatcher and PDL launchers for sparse-attention GVR Top-K](../sources/prs/TensorRT-LLM/PR-13477.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] DSv4: enable GVR Heuristic Top-K for compress_ratio=4](../sources/prs/TensorRT-LLM/PR-14219.md), [feat: update decode attention APIs](../sources/prs/flashinfer/PR-1007.md), [bugfix: import wrapper of mla decode](../sources/prs/flashinfer/PR-1013.md), [add multi-item scoring](../sources/prs/flashinfer/PR-1015.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [[nvidia] Add Blackwell FMHA decode kernel from TRT-LLM](../sources/prs/flashinfer/PR-1051.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [update trtllm-gen decode attention kernel launcher](../sources/prs/flashinfer/PR-1189.md), [Enable cudnn decode and add tests for the cudnn decode kernel](../sources/prs/flashinfer/PR-1221.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [feat: enable trtllm-gen mla MTP](../sources/prs/flashinfer/PR-1258.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [refactor: Improved metainfo for trtllm-gen fmha](../sources/prs/flashinfer/PR-1292.md), [test qkvo quantization not equal to 1.](../sources/prs/flashinfer/PR-1314.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [fix: fix trtllm-gen mla error on new interface](../sources/prs/flashinfer/PR-1348.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Add Mxfp4 trtllm-gen moe unit tests](../sources/prs/flashinfer/PR-1399.md), [benchmark: trtllm-gen mha with sink, add benchmark args](../sources/prs/flashinfer/PR-1415.md), [fix: remote redundant zero_init from trtllm-gen attn](../sources/prs/flashinfer/PR-1444.md), [feat: enable trtllm-gen attn speculative decoding verify by decode](../sources/prs/flashinfer/PR-1453.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [feat: Support for inferring out_dtype from out.dtype for TRTLLM attention kernel](../sources/prs/flashinfer/PR-1578.md), [fix: Improve TRTLLM attention kernel out_dtype unit test](../sources/prs/flashinfer/PR-1590.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [fix: pass workspace for trtllm-gen attention](../sources/prs/flashinfer/PR-1635.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [feat: Add `variant.OutputTransform()` to decode kernels](../sources/prs/flashinfer/PR-1670.md), [feat: Batch-size invariant FA2 Prefill & Decode](../sources/prs/flashinfer/PR-1675.md), [feat: port fast_decode_plan from sgl](../sources/prs/flashinfer/PR-1745.md), [Fix tests/test_trtllm_gen_attention.py::test_trtllm_batch_prefill, ::test_trtllm_batch_decode mismatch error](../sources/prs/flashinfer/PR-1755.md), [fix: should pass global_override_indptr_cpu in fast_decode_plan param list](../sources/prs/flashinfer/PR-1757.md), [Waive / disable test_mla_decode_kernel.py::test_mla_decode_kernel for not sm80 ](../sources/prs/flashinfer/PR-1771.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Fix trtllm-gen attention illegal memory access](../sources/prs/flashinfer/PR-2002.md), [use scalar for kv_scale in xqa](../sources/prs/flashinfer/PR-2033.md), [feat: add xqa mla backend](../sources/prs/flashinfer/PR-2053.md), [misc: Add XQA decode to microbenchmark for sm90 and sm120](../sources/prs/flashinfer/PR-2055.md), [unittest: improve the efficiency of xqa unittests](../sources/prs/flashinfer/PR-2075.md), [[Feature] Support batch prefill for POD Attention](../sources/prs/flashinfer/PR-2079.md), [enable xqa fp8 output](../sources/prs/flashinfer/PR-2081.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [enable xqa speculative decoding](../sources/prs/flashinfer/PR-2105.md), [add tensor scale input for xqa](../sources/prs/flashinfer/PR-2110.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [refactor: Move mla code from decode.py to mla.py and add to documentation](../sources/prs/flashinfer/PR-2163.md), [[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding](../sources/prs/flashinfer/PR-2265.md), [fix: Decode benchmark's fa2_tc uses backend=fa2 in wrapper](../sources/prs/flashinfer/PR-2302.md), [feat: [Qwen3-Next] Add Cute DSL GDN decode kernel and tests](../sources/prs/flashinfer/PR-2370.md), [fix: ensure each CTA processes full numHeadsQPerKv for trtllm decode kernel](../sources/prs/flashinfer/PR-2380.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [perf: improve gdn decode cute-dsl kernels](../sources/prs/flashinfer/PR-2405.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [Ameyn/gdn decode cutedsl kernel](../sources/prs/flashinfer/PR-2498.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [Feat/gdn decode pooled](../sources/prs/flashinfer/PR-2521.md), [pick fa2 for BatchDecodeWithPagedKVCacheWrapper auto backend](../sources/prs/flashinfer/PR-2530.md), [Perf: Optimize GDN decode pretranspose kernel for all batch sizes](../sources/prs/flashinfer/PR-2588.md), [Ameyn/gdn bf16 tolerance parallel reduction](../sources/prs/flashinfer/PR-2610.md), [perf(gdn): optimize MTP kernel with ILP rows and SMEM v caching](../sources/prs/flashinfer/PR-2618.md), [feat: add pool+indices support to gated_delta_rule_decode_pretranspose (bf16 path) ](../sources/prs/flashinfer/PR-2619.md), [benchmark: Enable speculative decode microbenchmarking for paged decode](../sources/prs/flashinfer/PR-2628.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [feat(gdn): add BF16 state kernel with MTP support beyond T>4 with intermediate caching.](../sources/prs/flashinfer/PR-2679.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [[gdn] support non-contiguous state for decoding](../sources/prs/flashinfer/PR-2727.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [[fix] Bugfix 1367: fix VariableBlockSparseAttention buffer overflow by dynamically resizing kv_lens_buffer](../sources/prs/flashinfer/PR-2802.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [feat(gdn): add padding index guard for bf16 decode kernel](../sources/prs/flashinfer/PR-2810.md), [[Fmha] Sparse MLA decode kernel selection heuristics](../sources/prs/flashinfer/PR-2836.md), [perf: Optimize GDN MTP decode kernel (v15) — eliminate ilp=1 fallback…](../sources/prs/flashinfer/PR-2842.md), [read real strides for kv and block scale](../sources/prs/flashinfer/PR-2844.md), [[fix] bugfix 2856: Fix pre-allocated out shape check in trtllm_batch_decode_with_kv_cache_mla for q_len_per_req > 1](../sources/prs/flashinfer/PR-2876.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [perf: Optimize CUTLASS MoE helper kernels for small-batch decode workloads](../sources/prs/flashinfer/PR-3014.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [Ameyn/gdn bf16 dispatcher and 4d pool](../sources/prs/flashinfer/PR-3268.md), [feat: support deepseek prefill attention shape](../sources/prs/flashinfer/PR-765.md), [bugfix: MLA decode should multiply sm_scale by math::log2e](../sources/prs/flashinfer/PR-787.md), [fix rope logic in mla decoding](../sources/prs/flashinfer/PR-793.md), [feat: apply sm_scale at logits instead of q in FA2 template](../sources/prs/flashinfer/PR-801.md), [perf: MLA decode kernel implemented by CuTe targeted to SM80](../sources/prs/flashinfer/PR-844.md), [Add POD-Attention to FlashInfer](../sources/prs/flashinfer/PR-858.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [Disable kernel cutlass_mla_decode on SM103](../sources/prs/sglang/PR-10058.md), [Use trtllm_mla decode kernel for draft extend in speculative decoding](../sources/prs/sglang/PR-11664.md), [Use trtllm mha decode kernel for target_verify in speculative decoding](../sources/prs/sglang/PR-13976.md), [Fix accuracy issue when using a16w16 mla_decode_fwd](../sources/prs/sglang/PR-14936.md), [[jit-kernel] Add CuTe DSL GDN Decode Kernel](../sources/prs/sglang/PR-15631.md), [[DeepSeek v3.2] Opt MTP decode cuda batch sizes and nsa implementation](../sources/prs/sglang/PR-16961.md), [Optimize GDN decode for Qwen3 Next](../sources/prs/sglang/PR-17094.md), [feat(gdn): add FlashInfer K-last SSM layout support for GDN prefill and decode for Hopper](../sources/prs/sglang/PR-18361.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [feat: add FA4 SM90 paged KV decode support & update attention docs](../sources/prs/sglang/PR-18442.md), [Tilelang sparse decode fwd for dsv32 mi355](../sources/prs/sglang/PR-18488.md), [[NVIDIA] Integrate FlashInfer decode kernel (Blackwell) for Qwen3.5](../sources/prs/sglang/PR-19150.md), [Fix MLA decode path returning unwritten (padded) rows](../sources/prs/sglang/PR-19902.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [[Kernel] Fuse temperature + softmax in sampling for decode speedup](../sources/prs/sglang/PR-20501.md), [[KDA] Support CuTeDSL KDA decode kernel](../sources/prs/sglang/PR-21203.md), [ [GDN] Remove FlashInfer GDN decode + no_buffer guard and default to FlashInfer on SM100+ ](../sources/prs/sglang/PR-21861.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [Introduce SchedulerDPAttnAdapter to own DP-attention state](../sources/prs/sglang/PR-25611.md), [Move DP-attention adapter methods to SchedulerDPAttnAdapter](../sources/prs/sglang/PR-25612.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [Add optimized native kernels in sgl-kernel](../sources/prs/sglang/PR-5150.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[PD] Fix dynamic port support and MLA buffer for Mooncake](../sources/prs/sglang/PR-5415.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Cutlass MLA decode - fix dtype error](../sources/prs/sglang/PR-5868.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [Support non-contiguous query input for extend/decode attention](../sources/prs/sglang/PR-7462.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [[Kernel][CPU] CPU MLA](../sources/prs/vllm/PR-14744.md), [[FEAT][ROCm] Integrate Fused MoE Kernels from AITER](../sources/prs/vllm/PR-14967.md), [[Bugfix] Fix incorrect qwen2.5-vl attention mask pre-computation](../sources/prs/vllm/PR-15200.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Kernel] Unified Triton kernel that doesn't distinguish between prefill + decode](../sources/prs/vllm/PR-16828.md), [[Attention] FA3 decode perf improvement - single mma warp group support for head dim 128](../sources/prs/vllm/PR-16864.md), [[ROCm][Kernel][V1] Enable AMD Radeon GPU Custom Paged Attention on v1](../sources/prs/vllm/PR-17004.md), [[Misc][ROCm] Exclude `cutlass_mla_decode` for ROCm build](../sources/prs/vllm/PR-17289.md), [[v1] AttentionMetadata for each layer](../sources/prs/vllm/PR-17394.md), [[Bugfix][ROCm] Use `chunked_prefill_paged_decode` as fallback for V1 attention on ROCm](../sources/prs/vllm/PR-18093.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[Kernel] Flashinfer MLA (trtllm-gen) decode kernel integration](../sources/prs/vllm/PR-21078.md), [[v1] Add Whisper model support (encoder-decoder)](../sources/prs/vllm/PR-21088.md), [Support encoder-only models without KV-Cache](../sources/prs/vllm/PR-21270.md), [[v1][attention] Support Hybrid Allocator + FlashInfer](../sources/prs/vllm/PR-21412.md), [[Attention] Support multiple attention metadata builders per kv_cache_spec + proper local attention no hybrid kv cache fix](../sources/prs/vllm/PR-21588.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [[NVIDIA] Support Flashinfer TRT-LLM Prefill Attention Kernel](../sources/prs/vllm/PR-22095.md), [[Bugfix] Add proper comparison for package versions](../sources/prs/vllm/PR-22314.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [[Core] Always use tensor cores for Flashinfer Decode Wrapper](../sources/prs/vllm/PR-23214.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[v1] Add cross-attention KV cache support for encoder-decoder models](../sources/prs/vllm/PR-23664.md), [[Core/DBO][1/N] Add Dual-Batch Overlap mechanism to VLLM](../sources/prs/vllm/PR-23693.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[Kernel] cuda kernels for upcoming decode context parallel feature](../sources/prs/vllm/PR-23791.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Kernel] Support decode context parallelism on Blackwell with CUTLASS MLA](../sources/prs/vllm/PR-24385.md), [[DCP] Support Decode Context Parallel (DCP) for GQA with FlashAttention](../sources/prs/vllm/PR-24864.md), [[Attention][DCP] Support DCP with query length > 1 (MTP) with FA3](../sources/prs/vllm/PR-25049.md), [[Performance] Split FlashAttn attention and cache update](../sources/prs/vllm/PR-25954.md), [[Spec Decode] Enable efficient speculative decoding with FlashInfer-MLA](../sources/prs/vllm/PR-25984.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Attention] Make `split_decodes_and_prefills(..., require_uniform=True)` support padding](../sources/prs/vllm/PR-29644.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[SpecDecode] Simplified alternative padded-speculation acceptance rate fix](../sources/prs/vllm/PR-29845.md), [[BugFix] Fix DBO assert `assert B_block_table == B_q`](../sources/prs/vllm/PR-29933.md), [[ROCm] add fallback for aiter fp8 decode mla](../sources/prs/vllm/PR-30005.md), [[ROCm][Bugfix] Add MLACommonMetadata to allowed attention types for speculative decoding](../sources/prs/vllm/PR-30430.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Bugfix][Hardware][AMD] Fix last_page_len calculation in AITER MLA decode](../sources/prs/vllm/PR-31282.md), [[Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten](../sources/prs/vllm/PR-31380.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[4/N][Attention] Move MLA common to model_executor](../sources/prs/vllm/PR-32060.md), [[Spec Decode] Unified Parallel Drafting](../sources/prs/vllm/PR-32887.md), [Triton MLA perf fixes](../sources/prs/vllm/PR-33529.md), [fix(cpu): fix mla_decode compilation on x86 without AVX512](../sources/prs/vllm/PR-34052.md), [[BugFix] Add support for MTP num_speculative_tokens > 1 with sparse MLA](../sources/prs/vllm/PR-34552.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [[Update] Use FlashInfer fast_decode_plan directly instead of replication](../sources/prs/vllm/PR-34687.md), [[Bugfix] Fix GDN attention crash with mixed decode/spec-decode batches](../sources/prs/vllm/PR-34871.md), [[Model Runner V2] Support attention group](../sources/prs/vllm/PR-35036.md), [Kimi k2.5 MLA based eagle3](../sources/prs/vllm/PR-36361.md), [[ROCm][Perf] Allow MTP lens > 1 in Sparse MLA](../sources/prs/vllm/PR-36681.md), [[ROCm] Attention selector reordering](../sources/prs/vllm/PR-36702.md), [[ROCm] Fix KV copy methods and auto-select attention backend for ROCm](../sources/prs/vllm/PR-36845.md), [[Feat][Spec Decode] DFlash](../sources/prs/vllm/PR-36847.md), [[Benchmark] Improvements to attention benchmark script](../sources/prs/vllm/PR-37115.md), [[Attention] Support distinguishing between short extends and decodes](../sources/prs/vllm/PR-37303.md), [[Model Runner V2] fix draft attention metadata generation](../sources/prs/vllm/PR-37364.md), [[Perf][Kernel] Persistent TopK scheduler: unified CUDAGraph-safe kernel with dynamic per-row dispatch - DeepSeek-V3.2 DSA decode](../sources/prs/vllm/PR-37421.md), [[Performance] Remove unnecessary zero-fill of MLA decode output tensor in Aiter backend](../sources/prs/vllm/PR-37539.md), [[Feature] Support per-draft-model MoE backend via `--speculative-config`](../sources/prs/vllm/PR-37880.md), [[ROCm][perf] fix Aiter sparse MLA with MTP>1](../sources/prs/vllm/PR-37887.md), [[Model Runner V2] Rebuild attention metadata before eagle decode full…](../sources/prs/vllm/PR-38311.md), [[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity](../sources/prs/vllm/PR-38479.md), [[XPU] Fix spec-decode UTs under tests/v1/spec_decode](../sources/prs/vllm/PR-38491.md), [[Refactor] Improve indexer decode path metadata preparation](../sources/prs/vllm/PR-38865.md), [[Bugfix][MoE] Fix 6-8% decode regression: prefer multi-stream shared expert overlap](../sources/prs/vllm/PR-38990.md), [[MLA] Optimize mla indexer prepare uniform decode for MTP > 1](../sources/prs/vllm/PR-39458.md), [[Attention][TurboQuant] Share dequant buffers, eliminate float16_copy](../sources/prs/vllm/PR-40941.md), [[Spec Decode] Add Gemma4 MTP speculative decoding support](../sources/prs/vllm/PR-41745.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[Bugfix] mamba: run single-token extends as decodes](../sources/prs/vllm/PR-42430.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [DeepSeek Sparse Attention / Sparse MLA](../wiki/kernels/sparse-mla.md) | +| `flash-attention` | [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashAttention-4: Algorithm and Kernel Co-design for Blackwell GPUs](../sources/docs/flash-attention-4.md), [[None][feat] Remove non flash attetnion style fmha_v2 kernel for hopper](../sources/prs/TensorRT-LLM/PR-11381.md), [[TRTLLM-11092][feat] add support for visual gen FA4 attention backend](../sources/prs/TensorRT-LLM/PR-11697.md), [[TRTLLM-11119][feat] Blackwell SageAttention, Integrate into AttentionOp API](../sources/prs/TensorRT-LLM/PR-11718.md), [[TRTLLM-11540][feat] Add EAGLE3 dynamic tree speculative decoding support](../sources/prs/TensorRT-LLM/PR-12062.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[None][feat] Trtllm-gen FMHA JIT support](../sources/prs/TensorRT-LLM/PR-12612.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[TRTLLM-11485][feat] Feature rework: Add SageAttention refreshed kernels (attentionOp only)](../sources/prs/TensorRT-LLM/PR-12937.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[None][feat] Update FMHA cubins for head_dim 80](../sources/prs/TensorRT-LLM/PR-13808.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] Update the logic of FMHA JIT path](../sources/prs/TensorRT-LLM/PR-14291.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [Correct divmod order in example 77 (blackwell fmha)](../sources/prs/cutlass/PR-2291.md), [Handle get_masked_trip_count for small length in fmha example](../sources/prs/cutlass/PR-2292.md), [[ex77] fix mla split; add fwd lse; add bwd varlen](../sources/prs/cutlass/PR-2366.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [fix gqa issue for blackwell fmha.py](../sources/prs/cutlass/PR-2599.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [Feat([FA4][CUTE DSL]) Add head_dim=256 support (forward + backward)](../sources/prs/flash-attention/PR-2412.md), [[hd256] Improve forward kernel with exp2 FMA emulation (3% to 9% performance gain)](../sources/prs/flash-attention/PR-2488.md), [[hd256] Add TMA paged KV support to SM100 2CTA forward kernel](../sources/prs/flash-attention/PR-2489.md), [[FA4][hd256] Backward TMA bulk-store epilogue + LSE/dpsum coalesce](../sources/prs/flash-attention/PR-2497.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [[nvidia] Add Blackwell FMHA decode kernel from TRT-LLM](../sources/prs/flashinfer/PR-1051.md), [bugfix: adding lse output to blackwell fmha kernels](../sources/prs/flashinfer/PR-1071.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [hotfix: fix the blackwell fmha stream](../sources/prs/flashinfer/PR-1116.md), [Add more logging to TRTLLM-GEN debug trace (NFC)](../sources/prs/flashinfer/PR-1158.md), [bugfix: fix invalid blackwell fmha unittests](../sources/prs/flashinfer/PR-1181.md), [update trtllm-gen decode attention kernel launcher](../sources/prs/flashinfer/PR-1189.md), [bugfix: fix blackwell fmha hanging issue for empty kv_len](../sources/prs/flashinfer/PR-1198.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [feat: enable trtllm-gen mla MTP](../sources/prs/flashinfer/PR-1258.md), [fix: update trtllm-gen fmha benchmark](../sources/prs/flashinfer/PR-1280.md), [fix multiCtasKvScratchPtr misalignment issue (new one)](../sources/prs/flashinfer/PR-1286.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [refactor: Improved metainfo for trtllm-gen fmha](../sources/prs/flashinfer/PR-1292.md), [Fix the bug of the kernel-selection heuristic in trtllm-gen](../sources/prs/flashinfer/PR-1307.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [fix: fix trtllm-gen mla error on new interface](../sources/prs/flashinfer/PR-1348.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [benchmark: trtllm-gen mha with sink, add benchmark args](../sources/prs/flashinfer/PR-1415.md), [fix: remote redundant zero_init from trtllm-gen attn](../sources/prs/flashinfer/PR-1444.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [feat: Integrate TRTLLM varlen kernel for deepseek R1 prefill ](../sources/prs/flashinfer/PR-1537.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [fix: semaphoress must be at the fixed range in workspace buffer on trtllm_gen attention](../sources/prs/flashinfer/PR-1584.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: trtllm-gen fmha sm101 and sm100 compatibility](../sources/prs/flashinfer/PR-1631.md), [fix: zero-init workspace buffer for trtllm-gen fmha](../sources/prs/flashinfer/PR-1643.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [perf: Port the separate reduce kernel mode from trtllm.](../sources/prs/flashinfer/PR-1685.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [Tune kernel compilation parameters for https://github.com/flashinfer-ai/flashinfer/pull/1850 ](../sources/prs/flashinfer/PR-1878.md), [fix: Fix trtllm-gen prefill IMA when batch_size==1](../sources/prs/flashinfer/PR-1912.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [Fix: several bugs/issues with trtllm-gen attention kernels. ](../sources/prs/flashinfer/PR-2062.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [fix(trtllm): reset negative strideBatch to 0 for ragged KV layout to …](../sources/prs/flashinfer/PR-2134.md), [fix: some bugs of headDim 256 trtllm-gen fmha kernels. ](../sources/prs/flashinfer/PR-2137.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [fix: compile flags for trtllm fmha_v2 ](../sources/prs/flashinfer/PR-2175.md), [feat: support non-contiguous query for trtllm-gen attention backend](../sources/prs/flashinfer/PR-2254.md), [[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding](../sources/prs/flashinfer/PR-2265.md), [fix: ensure each CTA processes full numHeadsQPerKv for trtllm decode kernel](../sources/prs/flashinfer/PR-2380.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [fix: allow fmha_v2_prefill_deepseek on SM121 (DGX Spark)](../sources/prs/flashinfer/PR-2559.md), [fix: guard CUTLASS FMHA against SM12x and fix fmha_v2 SM121a check](../sources/prs/flashinfer/PR-2560.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [feat: Add DiT-oriented kernels where Qk (Bmm1) type can be reinterpreted into Int8 or BFloat16](../sources/prs/flashinfer/PR-2711.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [[fmha-v2] Support HND and NHD paged KV cache layouts with conditional stride handling](../sources/prs/flashinfer/PR-2799.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [[Fmha] Sparse MLA decode kernel selection heuristics](../sources/prs/flashinfer/PR-2836.md), [[Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D](../sources/prs/flashinfer/PR-2841.md), [read real strides for kv and block scale](../sources/prs/flashinfer/PR-2844.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [cute-dsl fmha prefill (cubin integration): remove front-padding, add attention_sink, and pdl support](../sources/prs/flashinfer/PR-3181.md), [Add dynamic tokens-per-page TRTLLM-GEN GQA kernels](../sources/prs/flashinfer/PR-3259.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [Update trtllm FMHA cubins](../sources/prs/flashinfer/PR-3317.md), [[flex_attention] adds support for low precision K/V inputs in compiled mode with GPU](../sources/prs/pytorch/PR-170486.md), [[RELEASE 2.11] Release only changes](../sources/prs/pytorch/PR-175091.md), [[release 2.12] Apply Release only changes to 2.12 branch](../sources/prs/pytorch/PR-180470.md), [[NVIDIA] FA3/FA4 Fix ](../sources/prs/sglang/PR-11606.md), [Tiny use trtllm_mha as default when possible](../sources/prs/sglang/PR-14291.md), [[NVIDIA] upstream FA4](../sources/prs/sglang/PR-15182.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [feat: add FA4 SM90 paged KV decode support & update attention docs](../sources/prs/sglang/PR-18442.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Lazy import flash_attention_v4 to avoid loading flash_attn.cute at startup](../sources/prs/sglang/PR-22306.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[FA4] Update flash-attention to latest upstream FA4](../sources/prs/vllm/PR-38690.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md) | +| `fused-kernel` | [FlashInfer MLSys 2026 Track A: FP8 Block-Scale MoE](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [[Kernel][B200] mxfp4 fused cutlass moe](../sources/prs/vllm/PR-23696.md), [FlashInfer Track A FP8 Block-Scale MoE](../wiki/kernels/fused-moe.md), [GPU Mode NVFP4 Gated Dual GEMM](../wiki/kernels/gated-dual-gemm.md) | +| `gated-delta-net` | [Gated Delta Networks](../sources/blogs/gated-delta-net.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [FlashInfer MLSys 2026 Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][fix] Update the OSS headers in derived FLA ops and AD modeling code](../sources/prs/TensorRT-LLM/PR-14281.md), [feat: add pool+indices support to gated_delta_rule_decode_pretranspose (bf16 path) ](../sources/prs/flashinfer/PR-2619.md), [feat(gdn): state checkpointing in chunk_gated_delta_rule](../sources/prs/flashinfer/PR-2908.md), [[feat] Add blackwell GDN prefill kernel](../sources/prs/flashinfer/PR-3001.md), [[XPU] Enable qwen3.5 on XPU](../sources/prs/sglang/PR-21668.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md) | +| `gated-dual-gemm` | [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Gated Dual GEMM](../wiki/kernels/gated-dual-gemm.md) | +| `gemm` | [Microbenchmarking NVIDIA's Blackwell Architecture](../sources/blogs/blackwell-microbenchmarking.md), [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Kernels](../sources/blogs/colfax-cutlass-kernels.md), [DeepGEMM — Pinned Upstream Project Summary](../sources/blogs/deepgemm.md), [Anatomy of a Reward Hack](../sources/blogs/gpu-mode-reward-hack.md), [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md), [K-Search: LLM Kernel Generation via Co-Evolving Intrinsic World Model](../sources/blogs/k-search-kernel-generation.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [NVIDIA Developer Code Samples](../sources/blogs/nvidia-code-samples.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [CUTLASS 4.5.0 Cluster Launch Control Documentation](../sources/docs/cutlass-clc-documentation.md), [DeepSeek-V3 Technical Report: FP8 Training](../sources/docs/deepseek-v3-fp8.md), [Fix performance issue of m-grouped contiguous GEMMs.](../sources/prs/DeepGEMM/PR-168.md), [Fix multicast bug and optimize masked GEMM](../sources/prs/DeepGEMM/PR-193.md), [fix: use SM90ArchSpec instead of SM100ArchSpec in sm90_bf16_k_grouped_gemm](../sources/prs/DeepGEMM/PR-270.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [Performance: reducing the percentage of FFMA interleaving yields a sight performance gain, roughly 0.5%](../sources/prs/DeepGEMM/PR-42.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Use swizzling instead of padding](../sources/prs/DeepGEMM/PR-86.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[None][perf] Add more optimization options for MOE CuteDSL finalized kernel](../sources/prs/TensorRT-LLM/PR-10042.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [[None][feat] CuteDSL MOE FC1 Enhancement](../sources/prs/TensorRT-LLM/PR-10088.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [[None][feat] sm100 weight-only kernel](../sources/prs/TensorRT-LLM/PR-10190.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [[TRTLLM-9798][feat] Change to use new DeepGEMM MQA sm100 kernel for MTP-3](../sources/prs/TensorRT-LLM/PR-10226.md), [[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.](../sources/prs/TensorRT-LLM/PR-10339.md), [[None] [feat] Add test script and raster M for gather fc1 kernel](../sources/prs/TensorRT-LLM/PR-10429.md), [[TRTLLM-10276][feat] Integrate cutedsl argmax kernel](../sources/prs/TensorRT-LLM/PR-10476.md), [[None] [feat] Add densegemm backend for MoE](../sources/prs/TensorRT-LLM/PR-10479.md), [[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth](../sources/prs/TensorRT-LLM/PR-10987.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[https://nvbugs/5854860][fix] Fix cutedsl argmax on sm120](../sources/prs/TensorRT-LLM/PR-11181.md), [[None][fix] Fix int4 awq for sm120/121](../sources/prs/TensorRT-LLM/PR-11561.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[TRTLLM-10990][feat] Fuse SwiGLU and quant into shared expert](../sources/prs/TensorRT-LLM/PR-11897.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[TRTLLM-11285][feat] Fuse indexer wk + weights_proj into single GEMM in TF32 for DS-V3.2](../sources/prs/TensorRT-LLM/PR-12055.md), [[TRTLLM-11289][feat] Integrate CuteDSL's bf16 dense GEMMs](../sources/prs/TensorRT-LLM/PR-12074.md), [[None][feat] CuteDSL MOE: Add raster along M/N support for blockscaled contiguous backbone kernel](../sources/prs/TensorRT-LLM/PR-12079.md), [[None][feat] Add DWDP (Distributed Weight Data Parallelism) support for MoE inference](../sources/prs/TensorRT-LLM/PR-12136.md), [[None][feat] Minimax RMS norm optimization](../sources/prs/TensorRT-LLM/PR-12163.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[TRTLLM-10407][perf] Add cute dsl single pass multi cta cluster topk](../sources/prs/TensorRT-LLM/PR-12354.md), [[None][feat] Add Mamba2 MTP SSM cache CUDA kernel for tree-based speculative decoding](../sources/prs/TensorRT-LLM/PR-12537.md), [[TRTLLM-11585][feat] Add CUTEDSL moe backend for nemotron-h](../sources/prs/TensorRT-LLM/PR-12884.md), [[#12784][feat] AutoDeploy: Optimize DeepSeek-R1 model performance](../sources/prs/TensorRT-LLM/PR-12946.md), [[None][fix] Propagate init_load_balancer to DeepGemmFusedMoE in create_moe_backend](../sources/prs/TensorRT-LLM/PR-13207.md), [[None][feat] Integrate FP4 indexer for DSA on Blackwell](../sources/prs/TensorRT-LLM/PR-13340.md), [[TRTLLM-11285][perf] Force enable TF32 tensor cores for DSA indexer fused GEMM](../sources/prs/TensorRT-LLM/PR-13452.md), [[None][feat] Fuse FP8 1x128 quantize + UE8M0 scale pack on SM100](../sources/prs/TensorRT-LLM/PR-13628.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[https://nvbugs/6108841][fix] add hidden_dim=6144 router GEMM instantiation for GLM-5](../sources/prs/TensorRT-LLM/PR-13740.md), [[None][fix] Plumb swiglu_limit through DeepGEMM and TRTLLMGen FP8 fused MoE](../sources/prs/TensorRT-LLM/PR-13767.md), [[None][feat] Indexer topk opt](../sources/prs/TensorRT-LLM/PR-13811.md), [[None][perf] FC2 DenseGEMM autotune: split-K, swap_ab, fine-grained tuning buckets](../sources/prs/TensorRT-LLM/PR-13833.md), [[None][perf] mHC fused_hc kernel optimizations + DS-V4 entry-boundary RMSNorm fold-in](../sources/prs/TensorRT-LLM/PR-13892.md), [[None][feat] Add chunked prefill support for Gemma4 (text + vision multimodal)](../sources/prs/TensorRT-LLM/PR-14134.md), [[TRTLLM-12462][fix] Fix FP8 block scaling GEMM autotuner cache growth](../sources/prs/TensorRT-LLM/PR-14165.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][fix] Avoid dp_size x ep_size double-count in MegaMoEDeepGemm SymmBuffer](../sources/prs/TensorRT-LLM/PR-14213.md), [[None][fix] Update the OSS headers in derived FLA ops and AD modeling code](../sources/prs/TensorRT-LLM/PR-14281.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[TRTLLM-8958][feat] and [TRTLLM-8960]: create ConfigurableMoE and support TRTLLMGenFusedMoE as backend](../sources/prs/TensorRT-LLM/PR-9486.md), [[TRTLLM-9685] [feat] Add gather fc1 kernel by cuteDSL](../sources/prs/TensorRT-LLM/PR-9618.md), [[None][feat] add fp4 gemm + allreduce](../sources/prs/TensorRT-LLM/PR-9729.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [[TRTLLM-9493][feat] Add helixPostProcessNative kernel for cp_dim=2](../sources/prs/TensorRT-LLM/PR-9924.md), [Experimental Python cooperative algorithms](../sources/prs/cccl/PR-1973.md), [fix thread-reduce performance regression](../sources/prs/cccl/PR-2944.md), [Fix scan / sm90 perf regression ](../sources/prs/cccl/PR-3236.md), [Fix the vectorized loading of BlockLoad](../sources/prs/cccl/PR-3517.md), [Fix SM100 histogram tunings](../sources/prs/cccl/PR-3691.md), [Split Optimize Warp Reduce PR - CUB part](../sources/prs/cccl/PR-4716.md), [Add nondeterministic reduce that uses atomics](../sources/prs/cccl/PR-4961.md), [CUB - Add internal integer utils and tests (Split `WarpReduce` PR)](../sources/prs/cccl/PR-5314.md), [Combine `block_reduce_warp_reduction_nondeterministic.cuh` specialization with original deterministic one ](../sources/prs/cccl/PR-5408.md), [Add dynamic CUB dispatch for segmented_sort](../sources/prs/cccl/PR-6069.md), [[CUB] Use `BlockLoadToShared` in `DeviceMerge`](../sources/prs/cccl/PR-6077.md), [Split fixed-size segmented reduce dispatch header](../sources/prs/cccl/PR-6597.md), [Integrate decoupled lookahead warpspeed scan](../sources/prs/cccl/PR-6811.md), [Use integer promotion for `warp_reduce`](../sources/prs/cccl/PR-6819.md), [Implement new tuning API arch dispatching](../sources/prs/cccl/PR-7093.md), [Two-phase reduction for fixed size segmented reduction for very large segment sizes](../sources/prs/cccl/PR-7114.md), [Implement the new tuning API for deterministic (rfa) reduce dispatch](../sources/prs/cccl/PR-7346.md), [Radix-selection based `BlockTopK` specialization](../sources/prs/cccl/PR-7384.md), [Implement the new tuning API for `DeviceRleDispatch`](../sources/prs/cccl/PR-7669.md), [Optimize non fixed size segmented reduce for small segments using max_segment_size](../sources/prs/cccl/PR-7718.md), [Add env SegmentedReduce (non fixed-size overloads)](../sources/prs/cccl/PR-7795.md), [Forward policy hub from `dispatch_streaming_arg_reduce_t` to `reduce::dispatch`](../sources/prs/cccl/PR-7805.md), [Implement the new tuning API for `detail::reduce::dispatch_streaming_arg_reduce_t`](../sources/prs/cccl/PR-7807.md), [Use the new tuning API internally for `detail::transform::dispatch`](../sources/prs/cccl/PR-7810.md), [[Backport branch/3.3.x] Forward policy hub from `dispatch_streaming_arg_reduce_t` to `reduce::dispatch`](../sources/prs/cccl/PR-7814.md), [Optimized Device-to-Device Tensor Copy (`cudax`)](../sources/prs/cccl/PR-7823.md), [Implement the new tuning API for `DispatchSegmentedRadixSort`](../sources/prs/cccl/PR-7844.md), [Implement the new tuning API for `DispatchSegmentedSort`](../sources/prs/cccl/PR-7874.md), [Implement the new tuning API for `DispatchTopK`](../sources/prs/cccl/PR-7928.md), [[cuda.compute]: Fix faulty pointer arithmetic calculation in CUB dispatch](../sources/prs/cccl/PR-7940.md), [Reduce usage of `cub::DispatchReduce`](../sources/prs/cccl/PR-7944.md), [Use the new tuning API for `detail::radix_sort::dispatch`](../sources/prs/cccl/PR-7949.md), [Adds support for non-fundamental types via decomposer to `DeviceTopK` ](../sources/prs/cccl/PR-8040.md), [Optimized Device-to-Device Tensor Copy (cudax) - Transpose Case](../sources/prs/cccl/PR-8125.md), [Avoid passing uninitialized values to scan_op](../sources/prs/cccl/PR-8184.md), [[STF] Move unstable_unique from STF to generic cudax utility](../sources/prs/cccl/PR-8190.md), [Expose `max_segment_size` guarantee in cuda.compute](../sources/prs/cccl/PR-8284.md), [Port `thrust::min|max_element` to CUB](../sources/prs/cccl/PR-8291.md), [Implement the new tuning API for `DispatchSelectIf`](../sources/prs/cccl/PR-8311.md), [simplify dispatch segmented reduce to use latest dispatch and new tunings API](../sources/prs/cccl/PR-8332.md), [Apply some random warpspeed tunings](../sources/prs/cccl/PR-8352.md), [[cub]: implement utilities for policy selection](../sources/prs/cccl/PR-8355.md), [Replace `detail::merge::dispatch` by CUB's public API](../sources/prs/cccl/PR-8381.md), [[CUB] Replace `Shuffle(Up|Down|Index)` with cuda::device::warp_shuffle - RadixSort only](../sources/prs/cccl/PR-8395.md), [[thrust] Single-pass `is_partitioned` via adjacent zip_iterator](../sources/prs/cccl/PR-8427.md), [Replace `detail::merge_sort::dispatch` by CUB's public API](../sources/prs/cccl/PR-8473.md), [Replace `detail::scan::dispatch` by CUB's public API](../sources/prs/cccl/PR-8495.md), [Implement the new tuning API for `detail::batched_topk::dispatch_batched_topk`](../sources/prs/cccl/PR-8538.md), [Replace `detail::for_each::dispatch` by CUB's public API](../sources/prs/cccl/PR-8565.md), [Replace `detail::segmented_reduce::dispatch` by the public API](../sources/prs/cccl/PR-8695.md), [Use the new tuning API internally for `detail::topk::dispatch`](../sources/prs/cccl/PR-8742.md), [Use the new tuning API internally for `detail::reduce_by_key::dispatch`](../sources/prs/cccl/PR-8756.md), [Use the new tuning API internally for `detail::reduce[_nd]::dispatch[_nd]`](../sources/prs/cccl/PR-8826.md), [Fix Warpspeed scan shifted output store](../sources/prs/cccl/PR-8839.md), [[cub] Simplify arch dispatch](../sources/prs/cccl/PR-8861.md), [Use the new tuning API internally for `detail::select::dispatch` and `DeviceSelect`](../sources/prs/cccl/PR-8880.md), [[STF] Add per-handle exec_place stream resources](../sources/prs/cccl/PR-8905.md), [Use the new tuning API internally for `detail::select|three_way_partition::dispatch` and `DevicePartition`](../sources/prs/cccl/PR-8925.md), [Use the new tuning API internally for `detail::segmented_radix_sort::dispatch`](../sources/prs/cccl/PR-8927.md), [Fix segmented radix sort benchmark segment size type](../sources/prs/cccl/PR-9039.md), [[libcu++] Fix default make_shared_resource construction](../sources/prs/cccl/PR-9044.md), [Vectorize contiguous iterators in `cub::BlockLoad`/`Store`](../sources/prs/cccl/PR-9056.md), [Improve sm90 mixed dtype kernel](../sources/prs/cutlass/PR-1883.md), [Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2037.md), [Improvements for: Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2095.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Fix sm100 gemm wrong static constexpr that breaks compilation on Windows](../sources/prs/cutlass/PR-2167.md), [Fix SM90 beta=1 hang and stream-K launch errors](../sources/prs/cutlass/PR-2172.md), [Use cudaMemcpyAsync in gemm grouped with kRequiresPrecomputation sche…](../sources/prs/cutlass/PR-2256.md), [war to fix blackwell grouped groupwise hang](../sources/prs/cutlass/PR-2267.md), [hopper-blockwise-generalization-optimization](../sources/prs/cutlass/PR-2270.md), [support fp16 accmulator for sm89 fp8 mma](../sources/prs/cutlass/PR-2378.md), [DistGEMM bug fixes](../sources/prs/cutlass/PR-2713.md), [Support PDL for SM90 Array TMA GEMM](../sources/prs/cutlass/PR-2719.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [Add tutorial fp16_gemm_1](../sources/prs/cutlass/PR-2750.md), [Blockscaled Ragged Contiguous Grouped Gemm for MoEs](../sources/prs/cutlass/PR-2790.md), [[Bug Fix]Bypass launch grids for SM120 Kernel with SM90 Mainloop & SM100 TileScheduler](../sources/prs/cutlass/PR-2865.md), [[cute] Add constexpr specifier to make_tiled_copy](../sources/prs/cutlass/PR-2875.md), [new example with TMA prefetch feature targeting for DRAM latency boun…](../sources/prs/cutlass/PR-2881.md), [Fix incorrect tensor layout strides in Blackwell MMA tutorial comments](../sources/prs/cutlass/PR-2921.md), [[Cutlass gemm] Fix SM100 FP8 nosmem epilogue-fusion shape_div 'Divisibility Condition' for non-multiple-of-64 N tiles](../sources/prs/cutlass/PR-2946.md), [[Bug Fix]Set NumSplitsM to 1 when TileShapeM < 128 in sm90 fp8 blockwise scaling CollectiveMma](../sources/prs/cutlass/PR-2965.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [Replace std::min with cute::min in sm120 blockwise scaling device functions](../sources/prs/cutlass/PR-3055.md), [[Hopper CuTeDSL] Add grouped GEMM kernel example](../sources/prs/cutlass/PR-3091.md), [Support for Group GEMM in CUTLASS Profiler for GeForce and Spark](../sources/prs/cutlass/PR-3092.md), [[CLI] add cutedsl fp16 gemm tutorial from 2 to 6](../sources/prs/cutlass/PR-3106.md), [Update blackwell tutorial to be compatible with 4.5-dev version](../sources/prs/cutlass/PR-3130.md), [Small Tile N BlockScaled GEMM + Grouped GEMM on SM12x](../sources/prs/cutlass/PR-3176.md), [feat: Adding varlen support to cute-dsl sm80 bwd](../sources/prs/flash-attention/PR-1934.md), [[Cute] Block sparse support Sm100](../sources/prs/flash-attention/PR-1985.md), [[Cute,Fwd,Sm100] Support `q_stage=1` for inference](../sources/prs/flash-attention/PR-1993.md), [Add blocksparse support for bwd on blackwell](../sources/prs/flash-attention/PR-2085.md), [Fix IMA in fwd on m boundary](../sources/prs/flash-attention/PR-2091.md), [Add pack-gqa fwd support for sparse impl w/ broadcasted H dim](../sources/prs/flash-attention/PR-2098.md), [[Cute,Fwd,Sm100] distributed offset calculation for paged KV](../sources/prs/flash-attention/PR-2104.md), [[NVIDIA] Enable Jetson Thor FA4](../sources/prs/flash-attention/PR-2108.md), [[CUTE][SM90]Enable pack-gqa with broadcasted maskmods](../sources/prs/flash-attention/PR-2145.md), [[Cute][Flex]Add pack-gqa divmod](../sources/prs/flash-attention/PR-2180.md), [[Cute,Fwd,Sm100] support irregular qhead / kvhead ratios](../sources/prs/flash-attention/PR-2186.md), [[Cute,Flex,Fwd] Allow vectorized score_mod definitions](../sources/prs/flash-attention/PR-2236.md), [[Bwd,Sm120] Add SM120 backward pass support](../sources/prs/flash-attention/PR-2330.md), [Fix ZeroDivisionError in num_splits_heuristic for empty Q workloads](../sources/prs/flash-attention/PR-2515.md), [feat: ragged tensor padding kernel for blackwell kernel alignment](../sources/prs/flashinfer/PR-1025.md), [fix: top_k_mask_logits hangs on -inf inputs](../sources/prs/flashinfer/PR-1050.md), [perf: accelerate blackwell grouped gemm](../sources/prs/flashinfer/PR-1086.md), [comm: refactor and initialize `flashinfer.comm` module](../sources/prs/flashinfer/PR-1089.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [bugfix: Fix test and output shape of fp4 quantize](../sources/prs/flashinfer/PR-1114.md), [Fix pointer dtype bug in rope](../sources/prs/flashinfer/PR-1129.md), [fix: negative zero by type trait --> binary value](../sources/prs/flashinfer/PR-1136.md), [feat: nvshmem python bindings](../sources/prs/flashinfer/PR-1160.md), [Add DeepGEMM kernels](../sources/prs/flashinfer/PR-1209.md), [Fix test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-1211.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [[comm] TRT-LLM's Multi-Node NVLink All-Reduce Kernel](../sources/prs/flashinfer/PR-1213.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [Fix missing hash in the cudnn cubin path](../sources/prs/flashinfer/PR-1227.md), [bugfix: support uint8_t for vec_t class template](../sources/prs/flashinfer/PR-1234.md), [Patch fp8 cubin availability](../sources/prs/flashinfer/PR-1240.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [Reduce the JIT compilation time of gen_gemm_sm100_module](../sources/prs/flashinfer/PR-1251.md), [init add gemm fp8 using cudnn backend](../sources/prs/flashinfer/PR-1264.md), [Made AR output optional + esthetic changes](../sources/prs/flashinfer/PR-1265.md), [feat: add masked deepgemm support and benchmarking](../sources/prs/flashinfer/PR-1266.md), [Add shuffle matrix flag](../sources/prs/flashinfer/PR-1272.md), [hotfix: fix deepgemm artifactory hash](../sources/prs/flashinfer/PR-1278.md), [Unify groupwise fp8 GEMM test](../sources/prs/flashinfer/PR-1281.md), [add mm_fp4 use cudnn backend](../sources/prs/flashinfer/PR-1288.md), [Remove FAST_BUILD FLAG for MOE](../sources/prs/flashinfer/PR-1291.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [add cutlass backend for mm_fp4](../sources/prs/flashinfer/PR-1296.md), [feat: Add weight layout option for trtllm-gen fused moe](../sources/prs/flashinfer/PR-1297.md), [[Feature] SM level profiler ](../sources/prs/flashinfer/PR-1305.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [Add blockwise-scaled FP8 GEMM via TRTLLM-Gen.](../sources/prs/flashinfer/PR-1320.md), [Optimizations for TRTLLM MNNVL Allreduce](../sources/prs/flashinfer/PR-1321.md), [refactor: Improved metainfo for trtllm-gen kernels](../sources/prs/flashinfer/PR-1328.md), [feat: masked layout fp4 gemm using cute-dsl](../sources/prs/flashinfer/PR-1331.md), [add torch float4_e2m1fn_x2 check for cudnn fp4 backend](../sources/prs/flashinfer/PR-1333.md), [[Fix] remove torch 2.8 requirement for FP4 GEMM](../sources/prs/flashinfer/PR-1334.md), [Fix bench deepgemm setting](../sources/prs/flashinfer/PR-1344.md), [feature: add fp4 mm using trtllm backend](../sources/prs/flashinfer/PR-1355.md), [[fix] remove (view) transpose to keep consistent with majorness MN requirement.](../sources/prs/flashinfer/PR-1358.md), [hotfix: update mxfp4 groupwise-scaled gemm unittests](../sources/prs/flashinfer/PR-1359.md), [refactor: download trtllm gemm metadata from server](../sources/prs/flashinfer/PR-1378.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Adding FP8 benchmark on attention and matmul testing](../sources/prs/flashinfer/PR-1390.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [feature: add cutlass as bmm_fp8 backend.](../sources/prs/flashinfer/PR-1397.md), [fix shared memory alignment conflict in sampling.cuh](../sources/prs/flashinfer/PR-1402.md), [feature: enable cublas for fp4 gemm when cudnn == 9.11.1 or >= 9.13](../sources/prs/flashinfer/PR-1405.md), [Fixes for Blackwell Tests](../sources/prs/flashinfer/PR-1434.md), [bugfix: fix perf issue by using fp8 graph that can use cublaslt](../sources/prs/flashinfer/PR-1435.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [perf: add 1x4x1 cluster shape for fp8 bmm M<16 cases](../sources/prs/flashinfer/PR-1473.md), [tuner: Trtllm-gen Fp4 MoE Autotunner](../sources/prs/flashinfer/PR-1475.md), [refactor: unify autotuner for bmm_fp8](../sources/prs/flashinfer/PR-1479.md), [Add python API for masked grouped gemm](../sources/prs/flashinfer/PR-1481.md), [perf: add fast path to TopPRenormProbKernel for top_p >= 1.0, significantly boosting SGLang workloads](../sources/prs/flashinfer/PR-1483.md), [fix: update cutedsl masked moe gemm](../sources/prs/flashinfer/PR-1488.md), [Perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8](../sources/prs/flashinfer/PR-1491.md), [fix: update masked moe gemm fp4 tensor reshape](../sources/prs/flashinfer/PR-1495.md), [feat: scaling at fp4 gemm epilogue](../sources/prs/flashinfer/PR-1498.md), [fix: Replace cub Max/Min with cuda::maximum/minimum for cuda 13 compatibility](../sources/prs/flashinfer/PR-1500.md), [Add benchmark for cutedsl gemm](../sources/prs/flashinfer/PR-1502.md), [bugfix: Fix stream handling in cutedsl gemm](../sources/prs/flashinfer/PR-1509.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [refactor fp4 masked gemm cute-dsl implementation and add manual cache](../sources/prs/flashinfer/PR-1521.md), [Fix linking errors with CUDA 13](../sources/prs/flashinfer/PR-1523.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [Remove cuda-python from dependency and check at runtime](../sources/prs/flashinfer/PR-1534.md), [Add sm check for sm100 only cutlass/trtllm kernel](../sources/prs/flashinfer/PR-1535.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [bugfix: update trtllm-gen gemm kernel names](../sources/prs/flashinfer/PR-1577.md), [bugfix: Fix arg passing to TORCH_CHECK and TORCH_WARN macros](../sources/prs/flashinfer/PR-1582.md), [fix: limit the number of nvcc threads for each kernel](../sources/prs/flashinfer/PR-1589.md), [bugfix: fix the register overflow issue for topk renorm kernels on blackwell](../sources/prs/flashinfer/PR-1597.md), [feat: Enable MnnvlMemory (for alltoallv) on B200](../sources/prs/flashinfer/PR-1601.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [feat: cutlass fp4 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1609.md), [feat: cutlass fp8 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1610.md), [perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices](../sources/prs/flashinfer/PR-1615.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [test: pytest.mark.xfail on deepgemm](../sources/prs/flashinfer/PR-1636.md), [Added mx_fp4 support using the cudnn backend](../sources/prs/flashinfer/PR-1644.md), [Refactor Blackwell unit test scripts](../sources/prs/flashinfer/PR-1667.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [Support output signals for overlapping for cutedsl gemm](../sources/prs/flashinfer/PR-1677.md), [Update TGV GEMM default kernel and TGV code cleanup.](../sources/prs/flashinfer/PR-1682.md), [Update deepgemm backend for 103a](../sources/prs/flashinfer/PR-1694.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [hotfix: Hotfix for `test_pod_kernels.py` on B300](../sources/prs/flashinfer/PR-1698.md), [feat: Benchmark mm_fp4 mxfp4 support and gemm autotune support. Restore mm_fp4 API behavior](../sources/prs/flashinfer/PR-1706.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [TVM: support TVM binding for GroupedGemm](../sources/prs/flashinfer/PR-1725.md), [fix: put sampling kernel launch into macro](../sources/prs/flashinfer/PR-1727.md), [fix: fix cannot import name 'cuda' from 'cuda' in CUDA13](../sources/prs/flashinfer/PR-1764.md), [Added xfail for mx_fp4 matmul on SM120](../sources/prs/flashinfer/PR-1766.md), [tests: skip non SM100/103 for grouped deepgemm](../sources/prs/flashinfer/PR-1767.md), [Support checks PoC](../sources/prs/flashinfer/PR-1809.md), [tests: Update support for tgv_gemm to SM100 only and add to ut](../sources/prs/flashinfer/PR-1810.md), [tests: upgrade cutlass, fix import and skip non-SM100 cutedsl two shot allreduce](../sources/prs/flashinfer/PR-1812.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [raise error for group_gemm_fp8_nt_groupwise then num_groups > 1 on sm120/121](../sources/prs/flashinfer/PR-1862.md), [feat: Add FP4 TRTLLM-Gen throughput MOE batched gemms](../sources/prs/flashinfer/PR-1882.md), [misc: fix some B200 GEMM bench](../sources/prs/flashinfer/PR-1883.md), [Add layernorm op for inputs of mixed dtype](../sources/prs/flashinfer/PR-1926.md), [Feature: Support Relu2 activation in fused MoE](../sources/prs/flashinfer/PR-1954.md), [Update trtllm-gen fused moe routing kernel and add more kernels](../sources/prs/flashinfer/PR-1955.md), [fix: ensure SM120/121 SFA/SFB contiguity](../sources/prs/flashinfer/PR-1963.md), [feat: enable deepgemm jit for fp8 block-scale on SM90](../sources/prs/flashinfer/PR-1969.md), [Feature: Add support for L40 FusedMoE in cutlass path](../sources/prs/flashinfer/PR-1973.md), [feat: Add backend='auto' to mm_fp4 and enable autotune for backend='cudnn'](../sources/prs/flashinfer/PR-1979.md), [fix: Enable SM121 for mm_fp4](../sources/prs/flashinfer/PR-2012.md), [[feat] Refactor trtllmgen MOE and add Bf16 trtllmgen moe](../sources/prs/flashinfer/PR-2014.md), [[DSV3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2019.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [[NVIDIA] Thor & Spark Support](../sources/prs/flashinfer/PR-2028.md), [feat: suitable_auto_backends to prune auto backends, bmm_fp8 refactor, heuristic_func intake](../sources/prs/flashinfer/PR-2029.md), [perf: Optimize helper max/minmax function in sampling.cuh](../sources/prs/flashinfer/PR-2058.md), [feat: BF16 GEMM using CUTLASS backend for SM100](../sources/prs/flashinfer/PR-2070.md), [refactor: pass hopper deepgemm include directory through python](../sources/prs/flashinfer/PR-2090.md), [perf: enable pdl for cutlass fp4 gemm](../sources/prs/flashinfer/PR-2095.md), [Refactor trtllm_mnnvl_allreduce](../sources/prs/flashinfer/PR-2118.md), [make DeepGEMM swapAB available for linear gemm SM90](../sources/prs/flashinfer/PR-2131.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [enable sm103 moe dsl backend](../sources/prs/flashinfer/PR-2149.md), [fix xqa mha_sm90.cu](../sources/prs/flashinfer/PR-2157.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [Fix gemm allreduce two shot](../sources/prs/flashinfer/PR-2171.md), [Fix for moe on sm110](../sources/prs/flashinfer/PR-2190.md), [feat: unit-test and api change, w4a8 grouped-gemm fused MoE for SM90](../sources/prs/flashinfer/PR-2193.md), [Move the run function definition out of BatchedGemmInterface](../sources/prs/flashinfer/PR-2211.md), [misc: support checks for gemm](../sources/prs/flashinfer/PR-2214.md), [refactor: pull trtllm-gen batch-gemm/gemm headers from artifactory; update tma descriptor shape init](../sources/prs/flashinfer/PR-2235.md), [Remove cudaStreamSynchronize from gemm_groupwise_sm120.cuh for CUDA graph compatibility](../sources/prs/flashinfer/PR-2244.md), [feat: Add support for bmm mxfp8](../sources/prs/flashinfer/PR-2256.md), [Fix CUTLASS FP8 gemm correctness issue on SM120/SM121 for shapes where N is not divisible by ScaleGranularityN.](../sources/prs/flashinfer/PR-2261.md), [test: use .float() in in F.cosine_similarity() in bmm_fp8 test](../sources/prs/flashinfer/PR-2266.md), [Tiny fix bench tgv gemm](../sources/prs/flashinfer/PR-2277.md), [feat: IdType indices in sampling kernels](../sources/prs/flashinfer/PR-2281.md), [Selective State Update kernel (mamba)](../sources/prs/flashinfer/PR-2301.md), [[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels](../sources/prs/flashinfer/PR-2303.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [Fix: FilteredTopKUnifiedKernel read value out of length](../sources/prs/flashinfer/PR-2308.md), [[ML3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2323.md), [bugfix: fix multi-cta top-k implementation when k value is different for different row](../sources/prs/flashinfer/PR-2325.md), [[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32](../sources/prs/flashinfer/PR-2327.md), [Enable fp16/bf16/f32 support for selective_state_update (mamba)](../sources/prs/flashinfer/PR-2366.md), [feat: BF16 GEMM using cuDNN backend](../sources/prs/flashinfer/PR-2376.md), [bugfix: hotfix of PR 2366 (mamba kernel)](../sources/prs/flashinfer/PR-2378.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [perf: mm_fp4 heuristic prioritizes CUTLASS over cuDNN on SM103](../sources/prs/flashinfer/PR-2404.md), [feat: update trtllm-gen MoE cubins](../sources/prs/flashinfer/PR-2416.md), [fix: Sampling: CUDA Graph fix](../sources/prs/flashinfer/PR-2432.md), [MTP for mamba ](../sources/prs/flashinfer/PR-2444.md), [fix: fix illegal memory access for NaN input in sampling kernels](../sources/prs/flashinfer/PR-2456.md), [perf: add fp4 GEMM tile configs and streamK scheduler for SM120](../sources/prs/flashinfer/PR-2460.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [feat: Add MXFP8 GEMM mm_mxfp8 (cutlass)](../sources/prs/flashinfer/PR-2464.md), [fix: add support check for gemm config for cutlass moe](../sources/prs/flashinfer/PR-2495.md), [refactor: Port upstream CUTLASS fixes and refactor grouped_gemm_nt_masked GEMM module location](../sources/prs/flashinfer/PR-2503.md), [Feat: Trtllm-gen MxFP8 MoE integration](../sources/prs/flashinfer/PR-2505.md), [feat: BF16 GEMM benchmarking support](../sources/prs/flashinfer/PR-2525.md), [fix: include fp8_blockscale_gemm_90 in AOT jit-cache](../sources/prs/flashinfer/PR-2533.md), [tests: bmm_fp8 for SM110](../sources/prs/flashinfer/PR-2538.md), [feat: cute dsl mmfp4 for blackwell](../sources/prs/flashinfer/PR-2540.md), [misc: point triton blackwell-ptxas to local cuda ptxas](../sources/prs/flashinfer/PR-2543.md), [Add gen_gemm_sm100_module_cutlass_mxfp8 to jit-cache](../sources/prs/flashinfer/PR-2549.md), [Add support for the combinations of allreduce, allgather, and reducescatter](../sources/prs/flashinfer/PR-2563.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [feat: trtllm tinygemm2 in flashinfer as bf16 routergemm](../sources/prs/flashinfer/PR-2587.md), [Mamba SSU: better automatic kernel selection + algorithm selection optionally exposed to the user.](../sources/prs/flashinfer/PR-2591.md), [[bugfix] Fix FilteredTopK overflow correctness](../sources/prs/flashinfer/PR-2605.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [feat: FP32 dtype output for BF16 matmuls (CUTLASS & cuDNN)](../sources/prs/flashinfer/PR-2644.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [fix: Add fused MOE and GEMM AOT modules for SM121](../sources/prs/flashinfer/PR-2654.md), [feat: support mxfp4 & mxfp8 entrypoint for blackwell cutedsl dense gemm](../sources/prs/flashinfer/PR-2660.md), [feat: implement deterministic topk](../sources/prs/flashinfer/PR-2661.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [fix: reduce smem allocation for tinygemm2 kernel in SM120](../sources/prs/flashinfer/PR-2670.md), [Add varlen and speculative decoding support to selective state update](../sources/prs/flashinfer/PR-2700.md), [fix(jit): GEMM kernels produce NaN under concurrency — missing GDC flags cause PDL synchronization barriers to compile as no-ops](../sources/prs/flashinfer/PR-2716.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [misc: Update gemm/batched gemm cubins from trtllm-gen, gemm header refactor](../sources/prs/flashinfer/PR-2740.md), [[Spark unit test debugging] Fix for tests/gemm/test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-2751.md), [[feat] Add air top-p algorithm](../sources/prs/flashinfer/PR-2752.md), [fix(jit): enable GDC for CUTLASS GEMM PDL — SM100 flag only](../sources/prs/flashinfer/PR-2780.md), [Upgrade cutlass 4.2.1 -> 4.4.2](../sources/prs/flashinfer/PR-2798.md), [CuteDSL MoE fix redundant output buffer zeroing](../sources/prs/flashinfer/PR-2811.md), [Add support for Relu2 in BF16 fused MoE](../sources/prs/flashinfer/PR-2864.md), [Mamba SSU: horizontal MTP kernel (+ DSTATE=96 support)](../sources/prs/flashinfer/PR-2865.md), [fix: fix cute dsl swap_ab tactic failure](../sources/prs/flashinfer/PR-2870.md), [feat: add MXFP8 GEMM support for SM120](../sources/prs/flashinfer/PR-2902.md), [[NVIDIA] fix(jit): enable GDC for CUTLASS fused MoE PDL — prevent random crashes on SM12x](../sources/prs/flashinfer/PR-2913.md), [feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners](../sources/prs/flashinfer/PR-2914.md), [feat: add Relu2 (squared ReLU) activation support in CUTLASS MoE backend](../sources/prs/flashinfer/PR-2926.md), [feat: SM121 (GB10) tile filtering and autotuner robustness](../sources/prs/flashinfer/PR-2927.md), [CuTe DSL FP4 GEMM Heuristic](../sources/prs/flashinfer/PR-2940.md), [feat: Add CuTe DSL grouped-gemm + combine fusion support](../sources/prs/flashinfer/PR-2944.md), [fix: use float instead of double in sampling binary search to avoid FP64 bottleneck on SM103](../sources/prs/flashinfer/PR-2945.md), [Update NVSHMEM interface to use NVSHMEM4Py instead of custom bindings](../sources/prs/flashinfer/PR-2960.md), [Improved `simple` mamba SSU kernel ](../sources/prs/flashinfer/PR-2962.md), [test: skip unsupported mm_mxfp8 configurations on SM12x](../sources/prs/flashinfer/PR-2974.md), [fix: tinygemm2 hang issue due to barrier sync](../sources/prs/flashinfer/PR-2996.md), [[chore] Install nvidia-cutlass-dsl[cu13] for cu130+](../sources/prs/flashinfer/PR-3017.md), [perf: Port TRT-LLM SM120/SM121 FP4 CUTLASS GEMM optimizations. Add PDL](../sources/prs/flashinfer/PR-3026.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [fused_moe: pre-filter SM89 tactics with zero occupancy on SM120 Blackwell (fix review feedback on #2764)](../sources/prs/flashinfer/PR-3032.md), [feat: Add backend="b12x" for mm_fp4 on SM120](../sources/prs/flashinfer/PR-3051.md), [perf: Add no-bias path for tinygemm_bf16](../sources/prs/flashinfer/PR-3151.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [Fix/3170 dense blockscaled sm12x](../sources/prs/flashinfer/PR-3180.md), [test: enable bmm_mxfp8 cutlass backend coverage on SM12x](../sources/prs/flashinfer/PR-3183.md), [feat: enable glm5 router gemm](../sources/prs/flashinfer/PR-3185.md), [Include TinyGEMM into BF16 autotuner](../sources/prs/flashinfer/PR-3203.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [[Bugfix] Fix fused MoE autotuning correctness issues by filtering clusterDimZ](../sources/prs/flashinfer/PR-3227.md), [Update moe gemm](../sources/prs/flashinfer/PR-3239.md), [[feat] Add gemma RMS AR fusion](../sources/prs/flashinfer/PR-3322.md), [Change `apply_rope_with_cos_sin_cache` to accept `cos_sin_cache`](../sources/prs/flashinfer/PR-754.md), [bugfix: Ensure Loop Termination by Enforcing IEEE-754 Compliance in Sampling Kernels](../sources/prs/flashinfer/PR-774.md), [bugfix: fix the signature of `CutlassSegmentGEMMSM90`](../sources/prs/flashinfer/PR-827.md), [feat: experimenta support of PDL](../sources/prs/flashinfer/PR-930.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [perf: dual pivot top-p/top-k renorm](../sources/prs/flashinfer/PR-974.md), [SM-constraint-GEMM by triton persistent kernel](../sources/prs/flashinfer/PR-982.md), [Triton `rms_norm` kernels](../sources/prs/flashinfer/PR-983.md), [feat: SM-constraint Communication Kernels](../sources/prs/flashinfer/PR-994.md), [Update torch-xpu-ops commit pin](../sources/prs/pytorch/PR-144209.md), [[inductor][cpu] Fix bmm b_index for dynamic expressions in inductor autotuner](../sources/prs/pytorch/PR-144248.md), [Fix PythonMod printing](../sources/prs/pytorch/PR-144335.md), [ROCm SDPA: Ensure attn_mask has the same dtype with q](../sources/prs/pytorch/PR-144398.md), [[inductor] Fix profiler tests with latest Triton](../sources/prs/pytorch/PR-149059.md), [Remove runtime dependency on packaging](../sources/prs/pytorch/PR-149125.md), [op should NOT be static in aoti_torch_call_dispatcher](../sources/prs/pytorch/PR-149644.md), [Add release branch push triggers to inductor-rocm-mi300.yml](../sources/prs/pytorch/PR-149871.md), [[inductor] Fix inductor windows linker error](../sources/prs/pytorch/PR-150447.md), [[Windows][inductor] fix blank space break windows file path](../sources/prs/pytorch/PR-150448.md), [[CUDA][avgpool2d] Fix backward launch bounds again for `sm100`, `sm120`](../sources/prs/pytorch/PR-150676.md), [[dynamo][super variable] Fix bug to use correct source](../sources/prs/pytorch/PR-152774.md), [[ATen][CUDA] Optimize 128 bit vectorization](../sources/prs/pytorch/PR-152967.md), [Mark auto_functionalized HOPs as cacheable (#151194)](../sources/prs/pytorch/PR-153304.md), [Fix uint view copy (#151598)](../sources/prs/pytorch/PR-154121.md), [Fix macOS build with `USE_MPS=OFF`](../sources/prs/pytorch/PR-156932.md), [[PowerPC] Fixed build issue for vsx vec256 complexfloat and scaled_mm_out_cpu ](../sources/prs/pytorch/PR-157422.md), [[release] Triton pin update to 3.4](../sources/prs/pytorch/PR-157752.md), [[MPS] Switch Cholesky decomp to column wise](../sources/prs/pytorch/PR-158237.md), [[cherry-pick][inductor][triton] Update HAS_WARP_SPEC to check triton.Config params. Update Triton Hash to top of release/3.4.x stack](../sources/prs/pytorch/PR-158646.md), [CUDA 13.0 Windows Nvidia Driver Update to 580.88](../sources/prs/pytorch/PR-162501.md), [[Cherry Pick][Graph Partition] allow sharing default device context](../sources/prs/pytorch/PR-163097.md), [[Release 2.9] [cuDNN][SDPA][submodule] Roll-back cuDNN frontend upgrade, update Met…](../sources/prs/pytorch/PR-163265.md), [[Graph Partition] improve custom op output alias](../sources/prs/pytorch/PR-163380.md), [[Inductor][Intel GPU] Save `threads_per_warp` from tirton compiled kernel for launching kernel correctly in cpp wrapper.](../sources/prs/pytorch/PR-163388.md), [[graph partition] Add way to register custom rule (#163310)](../sources/prs/pytorch/PR-163395.md), [[2.9 cherry pick][triton] update 3.5 pin to bbb06c0334a6772b92d24bde54956e675c8c6604 (#163382)](../sources/prs/pytorch/PR-163583.md), [CUDA 13.0 Warning update for supported architectures](../sources/prs/pytorch/PR-163633.md), [[Cherry-Pick] [CD] CUDA 13 specific followup changes. Remove sm50-70 From CUDA 12.6 and CUDA 12.8 builds (#162455)](../sources/prs/pytorch/PR-163764.md), [[CD] CUDA 13.0 fix preload logic to include nvidia/cu13/lib/](../sources/prs/pytorch/PR-163766.md), [fix pickling for BitwiseFn](../sources/prs/pytorch/PR-163861.md), [Move inductor jobs 3.9->3.10](../sources/prs/pytorch/PR-163954.md), [[cuDNN][SDPA] Disable dropout for cuDNN SDPA on 9.11 - 9.13](../sources/prs/pytorch/PR-164026.md), [[AARCH64][CD][CUDA13][Triton][PTXAS] Turn on BUILD_BUNDLE_PTXAS=1 ](../sources/prs/pytorch/PR-164236.md), [CUDA 13.0 builds fix on Amazon Linux 2023](../sources/prs/pytorch/PR-164893.md), [[inductor] don't try to reorder loops for template](../sources/prs/pytorch/PR-166910.md), [[Dynamo] Don't guard data ptrs by default with mark_static_address](../sources/prs/pytorch/PR-166913.md), [[Inductor] No longer throw error in bmm out_dtype lowering due to tem…](../sources/prs/pytorch/PR-166922.md), [[Graph Partition] move custom rules to inductor config (#166458)](../sources/prs/pytorch/PR-166967.md), [[Graph Partition] fix graph partition input signature for fallback kernels](../sources/prs/pytorch/PR-166985.md), [[GraphPartition] cache get_free_symbol_uses (#166338)](../sources/prs/pytorch/PR-166994.md), [[Minor][Inductor] move some combo kernel log from warning to debug](../sources/prs/pytorch/PR-167020.md), [[cuDNN][SDPA] Check-in test for #166211](../sources/prs/pytorch/PR-167121.md), [[cuDNN][SDPA][Convolution] Expose cuDNN runtime version in CUDA hooks](../sources/prs/pytorch/PR-167327.md), [[ROCm] Enable shared memory based pruning for Triton configs](../sources/prs/pytorch/PR-170190.md), [[Inductor] ExternKernelBenchmarkRequest best attempt](../sources/prs/pytorch/PR-170246.md), [[inductor] Fix cudagraph skip for index_put_ with boolean indices, gr…](../sources/prs/pytorch/PR-170884.md), [[Inductor] Fix constants handling for Triton constexpr (triton#8248)](../sources/prs/pytorch/PR-171129.md), [[ROCm] Make grouped GEMM CK opt‑in via env and default to fallback path](../sources/prs/pytorch/PR-171140.md), [Avoid closing random file handles in Inductor](../sources/prs/pytorch/PR-171150.md), [[cherry-pick][CUDA] Upgrade cuDNN to 9.15.1 for CUDA 13 builds ](../sources/prs/pytorch/PR-171189.md), [[xpu][fix][inductor] fallback bfloat16 atomics to eager](../sources/prs/pytorch/PR-171247.md), [[cherry-pick][cuDNN][SDPA] cuDNN SDPA off-by-default for cuDNN versions < 12.9 (#171627)](../sources/prs/pytorch/PR-171895.md), [Skip modded_nanogpt model in TorchInductor benchmark](../sources/prs/pytorch/PR-172141.md), [[Graph Partition] Improve support for mutation ops](../sources/prs/pytorch/PR-172577.md), [Update inductor expected accuracy files](../sources/prs/pytorch/PR-175096.md), [[benchmark] Skip pytorch_CycleGAN_and_pix2pix from inductor benchmarks](../sources/prs/pytorch/PR-175299.md), [[release-only] Remove +ptx from cuda 13.0 builds](../sources/prs/pytorch/PR-175567.md), [[inductor] avoid multi-stage for mix-order-red by default (#176228)](../sources/prs/pytorch/PR-176495.md), [[inductor] Fix Identity comparability and evalf recursion](../sources/prs/pytorch/PR-176783.md), [[Inductor] Don't unfuse addmm for bf16/fp16 to avoid precision loss](../sources/prs/pytorch/PR-177144.md), [[Inductor][MPS] Fix half-precision type mismatches in Metal shader codegen (#176436)](../sources/prs/pytorch/PR-177193.md), [[MPS] fix compiling of SDPA producing nan results](../sources/prs/pytorch/PR-178009.md), [Optimize nvfp4 block scaled gemm kernel when M is small.](../sources/prs/sglang/PR-10101.md), [fix: resolve gb200 image link](../sources/prs/sglang/PR-10343.md), [Update CUTLASS. Refine KernelSchedule for fp8 (grouped) gemm.](../sources/prs/sglang/PR-10491.md), [Cache the result of `is_blackwell` platform check](../sources/prs/sglang/PR-10498.md), [Unify SGL Kernel Releases](../sources/prs/sglang/PR-10701.md), [Optimize cutlass int8 gemm kernel for large M on SM89 Ada GPU](../sources/prs/sglang/PR-10714.md), [chore: upgrade sgl-kernel 0.3.13](../sources/prs/sglang/PR-11056.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [Improve Kernel Build Time](../sources/prs/sglang/PR-11508.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [Change bf16 to fp8 for some gemms in attention for DeepSeek ckpt v2](../sources/prs/sglang/PR-11805.md), [Use cutlass fp4 gemm by default](../sources/prs/sglang/PR-11813.md), [chore: upgrade flashinfer 0.4.1](../sources/prs/sglang/PR-11933.md), [[sgl-kernel][4/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12080.md), [[hotfix] missing `w13_weight_fp8` and `w2_weight_fp8` in UE8M0 requantization](../sources/prs/sglang/PR-12259.md), [fix: Llama 4 BF16 load on Blackwell](../sources/prs/sglang/PR-12308.md), [[sgl-kernel] clean up fa fetch in CMakeLists.txt](../sources/prs/sglang/PR-12392.md), [chore: upgrade flashinfer 0.5.0](../sources/prs/sglang/PR-12523.md), [[NVIDIA] Fix CUDA arch requirement in nvfp4 cast](../sources/prs/sglang/PR-12581.md), [[sgl-kernel][5/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12666.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [[NVIDIA] Fix use case of SGLANG_ENABLE_FLASHINFER_GEMM](../sources/prs/sglang/PR-13274.md), [Support weight update for blackwell DeepGEMM](../sources/prs/sglang/PR-13324.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [[chore]Upgrade flashinfer to 0.5.3](../sources/prs/sglang/PR-13751.md), [update flashinfer_cubin==0.5.3](../sources/prs/sglang/PR-13848.md), [Fix update weight error for blackwell DeepGEMM](../sources/prs/sglang/PR-13910.md), [Add new moe wna16 marlin gemm](../sources/prs/sglang/PR-14122.md), [Apply new moe wna16 marlin gemm](../sources/prs/sglang/PR-14125.md), [[CPU] Implement MXFP4 Gemm kernels for intel AMX to support GPT OSS series.](../sources/prs/sglang/PR-14385.md), [Add CUDA kernel size analysis tool for sgl-kernel optimization](../sources/prs/sglang/PR-14544.md), [[sgl-kernel][Feat][B200][2/N] Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-14640.md), [Add cache for flashinfer installation](../sources/prs/sglang/PR-15153.md), [[Tiny]Add warning for deepgemm on Blackwell](../sources/prs/sglang/PR-15352.md), [[sgl-kernel][6/7]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-15471.md), [[Perf] Add Flashinfer DeepGEMM SM90 for SwapAB Optimization](../sources/prs/sglang/PR-15514.md), [[sgl-kernel] Streamline kernel size report (Top 20 only) and clean up](../sources/prs/sglang/PR-15552.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [[fix]deepgemm precompile when warmup](../sources/prs/sglang/PR-15891.md), [[Feature] add aligned_vector type for JIT kernel](../sources/prs/sglang/PR-16162.md), [Fix sgl-kernel jobs to skip when target_stage is specified](../sources/prs/sglang/PR-16308.md), [[Fix]Pin mooncake version to 0.3.7.post2 in grace blackwell](../sources/prs/sglang/PR-16502.md), [Fix FP8 MoE NaN with DeepGEMM on Blackwell](../sources/prs/sglang/PR-16622.md), [Support mxint4 flashinfer_trtllm moe gemm](../sources/prs/sglang/PR-16892.md), [[MUSA][2/N] sgl-kernel build](../sources/prs/sglang/PR-17053.md), [[FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/sglang/PR-17300.md), [Upgrade transformers==5.3.0](../sources/prs/sglang/PR-17784.md), [Feature/support longcat flash lite](../sources/prs/sglang/PR-17838.md), [Skipped warning on sm100](../sources/prs/sglang/PR-18000.md), [[Diffsuion & JIT_kernel] QKNorm cross heads kernel](../sources/prs/sglang/PR-18073.md), [[Blackwell] Make mxint4 flashinfer_trtllm moe gemm set by default on blackwell](../sources/prs/sglang/PR-18136.md), [[FIX] Correct JIT kernel compilation on newer GPUs with outdated driver metadata.](../sources/prs/sglang/PR-18496.md), [use flashinfer.sampling](../sources/prs/sglang/PR-18696.md), [fix: update Blackwell log/error messages to include SM12x](../sources/prs/sglang/PR-18751.md), [fix: add SM110 (Jetson AGX Thor) to Blackwell capability check](../sources/prs/sglang/PR-18787.md), [Migrate renorm kernels from sgl-kernel to FlashInfer JIT](../sources/prs/sglang/PR-18854.md), [Add claude skills for sgl-kernel and jit-kernel](../sources/prs/sglang/PR-18855.md), [Migrate norm kernels to FlashInfer JIT implementation](../sources/prs/sglang/PR-18871.md), [Use single mma warp group for short q_len in FA to optimize decoding performance](../sources/prs/sglang/PR-18985.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [[JIT Kernel][Feature] Support JIT custom all reduce (rewrite as v2)](../sources/prs/sglang/PR-19880.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [fix ci by removing nvidia-cutlass-dsl-libs-base and force reinstall n…](../sources/prs/sglang/PR-20380.md), [Fix(jit): support rmsnorm for hidden_size in {64, 128, 256}](../sources/prs/sglang/PR-20661.md), [Use FlashInfer tinygemm for GPT-OSS MoE router on SM90+](../sources/prs/sglang/PR-20755.md), [fix: guard configure_deep_gemm_num_sms when JIT disabled](../sources/prs/sglang/PR-20868.md), [CUTLASS FP8 Blockwise GEMM improvement of SM120](../sources/prs/sglang/PR-20887.md), [[Tiny Fix] Fix IS_BLACKWELL env var empty string warning in rerun-ut workflow](../sources/prs/sglang/PR-20957.md), [fix: wrap _import_static_state in inference_mode to fix resume on Blackwell](../sources/prs/sglang/PR-21035.md), [ci: remove IS_BLACKWELL env var; auto-detect Blackwell](../sources/prs/sglang/PR-21118.md), [[NPU] bugfix for import sgl-kernel error](../sources/prs/sglang/PR-21200.md), [Split pr-test.yml: extract sgl-kernel, jit-kernel, and multimodal-gen tests into separate workflow files](../sources/prs/sglang/PR-21219.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[MUSA] apply_vocab_mask support musa device](../sources/prs/sglang/PR-21296.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[FlashInver v0.6.7] Integrate flashinfer_trtllm mxfp8 gemm](../sources/prs/sglang/PR-21576.md), [[AMD] Use tgemm.mm for MoEGate router gemm in deepseek_v2.py](../sources/prs/sglang/PR-21657.md), [Remove flashinfer wheel cache cleanup that deletes other versions](../sources/prs/sglang/PR-21711.md), [[DSA] Set trtllm kernels as default for Blackwell](../sources/prs/sglang/PR-21914.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[Hotfix] Fix router gemm on sm103](../sources/prs/sglang/PR-22134.md), [[hisparse]: Adding ci for hisparse kvcache-swap-in jit-kernel](../sources/prs/sglang/PR-22155.md), [[HiSparse]: Add benchmark for hisparse kernel](../sources/prs/sglang/PR-22187.md), [[Docker] Fix Trivy CVEs, cubin download 403s, and kernels command order](../sources/prs/sglang/PR-22322.md), [Upgrade sglang-torch-profiler-analysis SKILLS](../sources/prs/sglang/PR-22440.md), [[RL] Fix weight update for mxfp8 flashinfer_cutlass gemm backend](../sources/prs/sglang/PR-22484.md), [[CI/Docker] Clean up redundant flashinfer cubin downloads](../sources/prs/sglang/PR-22491.md), [[Docker] Remove flashinfer cache copy](../sources/prs/sglang/PR-22653.md), [[Fix/Kernel] Add JIT rmsnorm_hf kernel to fix transformers backend MMLU accuracy regression ](../sources/prs/sglang/PR-22931.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [feat: port SGLANG_JIT_DEEPGEMM_FAST_WARMUP to deepseek_v4 branch](../sources/prs/sglang/PR-23756.md), [Enable PDL for various kernels in DSV32/GLM5](../sources/prs/sglang/PR-23965.md), [[VLM] Optimize Gemma4 VLM with PCG and fuse RMSNorm + residual add + scalar](../sources/prs/sglang/PR-24048.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [[Gemma4] Optimize Gemm4 with fused Q/K/V RMSNorm + per-expert FP8 ckpt loader](../sources/prs/sglang/PR-24696.md), [[codex] Optimize hidden-size 512 RMSNorm dispatch](../sources/prs/sglang/PR-24710.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [Support Gemma4 Pipeline Parallelism](../sources/prs/sglang/PR-25284.md), [[Gemma4]: Fix FP8 Triton scale layout](../sources/prs/sglang/PR-25286.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[fp8] SM90 swap-AB scaled_mm dispatch (~1.16x kernel geomean, +5.8-18.5% end-to-end)](../sources/prs/sglang/PR-25532.md), [Use DeepGEMM BF16 for unquantized DeepEP LL MoE](../sources/prs/sglang/PR-25540.md), [fix (jit kernel): elementwise activation C++ error](../sources/prs/sglang/PR-25695.md), [[Codex] Remove stale DeepSeek V4 JIT kernels](../sources/prs/sglang/PR-25764.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Support cutlass Int8 gemm](../sources/prs/sglang/PR-2752.md), [upgrade cutlass v3.7.0](../sources/prs/sglang/PR-2967.md), [feat: add flashinfer as 3rdparty and use rmsnorm as example](../sources/prs/sglang/PR-3033.md), [Support sm90 Int8 gemm](../sources/prs/sglang/PR-3035.md), [Allow local cutlass directory to be used in sgl-kernel build](../sources/prs/sglang/PR-3037.md), [support w8a8 fp8 kernel with CUTLASS](../sources/prs/sglang/PR-3047.md), [sync the upstream updates of flashinfer](../sources/prs/sglang/PR-3051.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [support blockwise fp8 matmul kernel](../sources/prs/sglang/PR-3267.md), [fix undefined symbol cudaGetDriverEntryPointByVersion](../sources/prs/sglang/PR-3372.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [update flashinfer-python](../sources/prs/sglang/PR-3557.md), [[Feature] Apply Cublas Grouped Gemm kernel](../sources/prs/sglang/PR-3629.md), [add control for cutlass fp8 blockwise gemm](../sources/prs/sglang/PR-3727.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [upgrade flashinfer v0.2.2.post1](../sources/prs/sglang/PR-3934.md), [Support overlapping two batches](../sources/prs/sglang/PR-4068.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [linear support deepgemm](../sources/prs/sglang/PR-4199.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [fix per_token_group_quant_fp8 illegal memory when num_groups % 16 != 0](../sources/prs/sglang/PR-4231.md), [add THIRDPARTYNOTICES for DeepGEMM](../sources/prs/sglang/PR-4272.md), [Support Blackwell Block Scale FP8 Gemm](../sources/prs/sglang/PR-4278.md), [update deepgemm](../sources/prs/sglang/PR-4284.md), [upgrade flashinfer 0.2.3](../sources/prs/sglang/PR-4317.md), [[FIX] fix incorrect output when enable both deepgemm and torch compile](../sources/prs/sglang/PR-4359.md), [Create col-major and tma-aligned x_scale for deep_gemm.gemm_fp8_fp8_bf16_nt](../sources/prs/sglang/PR-4515.md), [Support fp8 gemm for blackwell](../sources/prs/sglang/PR-4558.md), [Set deepgemm to the default value in the hopper architecture.](../sources/prs/sglang/PR-4613.md), [Fix loading KV quantization scale; Enable modelopt kv cache](../sources/prs/sglang/PR-4686.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [[Feat] support deepgemm for cmake](../sources/prs/sglang/PR-4864.md), [[Build] Fix cuda12.8 build error in nvfp4_scaled_mm_kernels.cu](../sources/prs/sglang/PR-4953.md), [update cutlass tag](../sources/prs/sglang/PR-5011.md), [fix deepgemm as well](../sources/prs/sglang/PR-5030.md), [support sgl-kernel on blackwell](../sources/prs/sglang/PR-5074.md), [Add optimized native kernels in sgl-kernel](../sources/prs/sglang/PR-5150.md), [feat: add DeepGEMM build warning](../sources/prs/sglang/PR-5176.md), [[Fix] Turn off DeepGEMM by default](../sources/prs/sglang/PR-5263.md), [fix: use deepgemm only on hopper](../sources/prs/sglang/PR-5310.md), [fix: determine if flashinfer is installed](../sources/prs/sglang/PR-5336.md), [Fix DeepGEMM masked cannot be run on groups not being multiple or 4](../sources/prs/sglang/PR-5340.md), [chore: upgrade DeepGEMM](../sources/prs/sglang/PR-5395.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Fix sampler nan check when calling top_k_top_p_sampling_from_probs](../sources/prs/sglang/PR-5546.md), [feat: use flashinfer jit package](../sources/prs/sglang/PR-5547.md), [[feature] enable pre compile jit deep_gemm](../sources/prs/sglang/PR-5580.md), [[fix] force use deepgemm in compile_deep_gemm](../sources/prs/sglang/PR-5618.md), [ DeepEP normal support deepgemm-contiguous](../sources/prs/sglang/PR-5626.md), [Turn on DeepGemm By Default and Update Doc](../sources/prs/sglang/PR-5628.md), [cutlass 3.9 supported to improve fp8_blockwise_gemm](../sources/prs/sglang/PR-5820.md), [Add sm_120 for blackwell](../sources/prs/sglang/PR-5903.md), [[Feat] Enable PDL automatically on Hopper architecture](../sources/prs/sglang/PR-5981.md), [chore: upgrade cutlass 3.9.2](../sources/prs/sglang/PR-6004.md), [chore: upgrade deepgemm](../sources/prs/sglang/PR-6073.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [[Fix] Improve dependencies for Blackwell image](../sources/prs/sglang/PR-6334.md), [Upgrade CUTLASS 4.0](../sources/prs/sglang/PR-6336.md), [Add fp8 fused_experts kernel for CPU in sgl-kernel and add UT](../sources/prs/sglang/PR-6404.md), [Fix bug of deepseek-v3 under DP+EP mode with large batchsize/seqlen](../sources/prs/sglang/PR-6449.md), [[Feature] Support Flashinfer fp8 blockwise GEMM kernel on Blackwell](../sources/prs/sglang/PR-6479.md), [[CPU] [BF16] Call fused_experts_cpu, weight_packed_linear and bmm_cpu kernel in DeepSeek model](../sources/prs/sglang/PR-6641.md), [Correctly abort the failed grammar requests & Improve the handling of abort](../sources/prs/sglang/PR-6803.md), [feat: integrate deepgemm into EPMoE](../sources/prs/sglang/PR-6821.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [Fix AWQ Dequant and Weight Loading of deepseek v2](../sources/prs/sglang/PR-6842.md), [Use deepgemm instead of triton for fused_qkv_a_proj_with_mqa](../sources/prs/sglang/PR-6890.md), [[sgl-kernel] update deepgemm](../sources/prs/sglang/PR-6942.md), [Fix torchvision version for Blackwell](../sources/prs/sglang/PR-7015.md), [Clean up server_args.py](../sources/prs/sglang/PR-7037.md), [feat: update blackwell setup](../sources/prs/sglang/PR-7119.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Tiny let DeepGEMM scale checks cover more cases](../sources/prs/sglang/PR-7182.md), [chore: upgrade sgl-kernel v0.1.8.post2](../sources/prs/sglang/PR-7186.md), [Fix a minor bug related to DeepGEMM upgrade](../sources/prs/sglang/PR-7191.md), [Fix error when disabling new DeepGEMM](../sources/prs/sglang/PR-7198.md), [[fix] fix DeepGEMM blackwell input quant & ut & fix style and log](../sources/prs/sglang/PR-7247.md), [Add CUTLASS FP8 Blockscale MoE kernel for Hopper architecture](../sources/prs/sglang/PR-7278.md), [Let EP prefill support new DeepGEMM](../sources/prs/sglang/PR-7310.md), [Kernels for efficient KV cache IO](../sources/prs/sglang/PR-7313.md), [fix: resolve blackwell deepep image issue](../sources/prs/sglang/PR-7331.md), [Quick fix for DeepGemm requant to also cover MTP.](../sources/prs/sglang/PR-7378.md), [[CMake] Fix sgl-kernel CMakeLists for Blackwell](../sources/prs/sglang/PR-7543.md), [Add dsv3 router gemm kernel](../sources/prs/sglang/PR-7627.md), [Add dsv3 fused a gemm to sgl-kernel](../sources/prs/sglang/PR-7630.md), [[Feature] Layer-wise Prefill](../sources/prs/sglang/PR-7634.md), [Apply dsv3_fused_a_gemm kernel](../sources/prs/sglang/PR-7635.md), [[Feature] CUDA Green Context Support](../sources/prs/sglang/PR-7649.md), [chore: upgrade flashinfer v0.2.7 jit](../sources/prs/sglang/PR-7663.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [[Fix][Ready]Fix register spilling in cutlass nvfp4 gemm kernel on Blackwell](../sources/prs/sglang/PR-8127.md), [[sgl-kernel] Opt per_token_quant_fp8 with warp reduce](../sources/prs/sglang/PR-8130.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/sglang/PR-8818.md), [chore: support blackwell cu129 image](../sources/prs/sglang/PR-8928.md), [[NVIDIA] Fix missing `get_col_major_tma_aligned_tensor` for Blackwell deepgemm in EpMoE](../sources/prs/sglang/PR-8955.md), [[fix] fix enable_pdl for blackwell](../sources/prs/sglang/PR-9011.md), [[sgl-kernel] Support FlashInfer top_k_top_p_sampling_from_logits](../sources/prs/sglang/PR-9060.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [Fix FP4 inference corruption issue in glm4.5-air model](../sources/prs/sglang/PR-9346.md), [[sgl-kernel] feat: Support sm120 cutlass fp8 gemm kernel](../sources/prs/sglang/PR-9403.md), [fix: blackwell dsv3 fp8 issue temporary solution](../sources/prs/sglang/PR-9530.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [Single Batch Overlap for MoE Models](../sources/prs/sglang/PR-9660.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [Make sm100 fp8 kernels available on sm103](../sources/prs/sglang/PR-9789.md), [Make fp4_quantize kernels work on sm103](../sources/prs/sglang/PR-9807.md), [perf: Avoid unnecessary data type conversions for DeepSeek-V3 on Blackwell](../sources/prs/sglang/PR-9834.md), [[Fix] DeepSeek EP accuracy issue on B200 GPUs](../sources/prs/sglang/PR-9946.md), [CUTLASS fp8 blockwise gemm support of sm120](../sources/prs/sglang/PR-9969.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feat] profiler support cudagraph backend](../sources/prs/tilelang/PR-1658.md), [Add swizzle layout detection and automatic merging for layout conflicts](../sources/prs/tilelang/PR-1736.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [fix(intrinsics): add missing _legalize_to_buffer_region in SM70 emitter](../sources/prs/tilelang/PR-1786.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Bugfix] Fix CuTeDSL autotune cache invalid ELF header (#1967)](../sources/prs/tilelang/PR-1972.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[CUDA] Improve int4 GEMM lowering and packed codegen support](../sources/prs/tilelang/PR-2073.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[CUDA] Add native SM75 MMA GEMM support for FP16, INT8 and INT4](../sources/prs/tilelang/PR-2198.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[Kernel] Update `cutlass_scaled_mm` to support 2d group (blockwise) scaling](../sources/prs/vllm/PR-11868.md), [[Build] Only build 9.0a for scaled_mm and sparse kernels](../sources/prs/vllm/PR-12339.md), [[Core][AMD] Migrate fully transparent sleep mode to ROCm platform](../sources/prs/vllm/PR-12695.md), [[Misc][Kernel]: Add GPTQAllSpark Quantization](../sources/prs/vllm/PR-12931.md), [[Kernel]Add streamK for block-quantized CUTLASS kernels](../sources/prs/vllm/PR-12978.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [[Kernel] optimize performance of gptq marlin kernel when n is small](../sources/prs/vllm/PR-14138.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [fix minor miscalled method](../sources/prs/vllm/PR-14327.md), [Add cutlass support for blackwell fp8 blockwise gemm](../sources/prs/vllm/PR-14383.md), [[BugFix] Illegal Memory Access in the blockwise cutlass fp8 GEMMs](../sources/prs/vllm/PR-14396.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[BugFix/Build] Fix sparse kernels not getting built on hopper](../sources/prs/vllm/PR-14572.md), [[Quantization][FP8] Adding support for fp8 gemm layer input in fp8](../sources/prs/vllm/PR-14578.md), [[Kernel] allow non-contiguous input for marlin kernel](../sources/prs/vllm/PR-14658.md), [[Model] Add support for Gemma 3](../sources/prs/vllm/PR-14660.md), [[Bugfix][Kernel][CPU] Fix num_tokens in CPU rotary embedding kernel](../sources/prs/vllm/PR-14667.md), [[FEAT] [ROCm]: Add AITER Block-Scaled GEMM Feature](../sources/prs/vllm/PR-14968.md), [[FEAT] [ROCm] Add AITER int8 scaled gemm kernel](../sources/prs/vllm/PR-15433.md), [[Quantization] Fp8 Channelwise Dynamic Per Token GroupedGEMM](../sources/prs/vllm/PR-15587.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[Perf]Optimize rotary_emb implementation to use Triton operator for improved inference performance](../sources/prs/vllm/PR-16457.md), [[Kernel] some optimizations for dense marlin and moe marlin](../sources/prs/vllm/PR-16850.md), [[Bugfix] gemma[2,3] interleaved attention when sliding window is disabled](../sources/prs/vllm/PR-17180.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [[Kernel] Have rotary embeddings support tensors](../sources/prs/vllm/PR-18046.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Kernel] Enable fp8 support for pplx and BatchedTritonExperts.](../sources/prs/vllm/PR-18864.md), [[Kernel] Support deep_gemm for linear methods](../sources/prs/vllm/PR-19085.md), [[V1] Use FlashInfer by default on Blackwell GPUs](../sources/prs/vllm/PR-19118.md), [[Kernels] Add activation chunking logic to FusedMoEModularKernel](../sources/prs/vllm/PR-19168.md), [[Bugfix] Don't attempt to use triton if no driver is active](../sources/prs/vllm/PR-19561.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [Fix FA2 fallback for Blackwell V1](../sources/prs/vllm/PR-19781.md), [[Feature] Integrate new deepgemm](../sources/prs/vllm/PR-19820.md), [ [Feature] Integrate SM100 DeepGEMM support](../sources/prs/vllm/PR-20087.md), [[Nixl] Heterogeneous TP support FlashInfer](../sources/prs/vllm/PR-20189.md), [[Misc] DP : Add ExpertTokensMetadata](../sources/prs/vllm/PR-20332.md), [[Kernel] SM90 CUTLASS FP8 GEMM: add support for swap AB + kernel tuning](../sources/prs/vllm/PR-20396.md), [[feat]: add SM100 support for cutlass FP8 groupGEMM](../sources/prs/vllm/PR-20447.md), [[feat] enable SM100 CUTLASS block scaled group gemm for smaller batch sizes](../sources/prs/vllm/PR-20640.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [[fix]: disable cutlass block scaled group gemm for EP](../sources/prs/vllm/PR-20781.md), [[Bug] Fix DeepGemm for EP low latency case](../sources/prs/vllm/PR-20833.md), [[Perf] Use Triton instead of Torch for DeepGEMM Per Token Group Quant](../sources/prs/vllm/PR-20841.md), [[Kernel] DeepGemm MoE : Integrate triton permute / unpermute kernels ](../sources/prs/vllm/PR-20903.md), [[Perf] Add swap_ab to SM90 FP8 non-block CUTLASS moe grouped gemm](../sources/prs/vllm/PR-20911.md), [[Model] Pooling models default to using chunked prefill & prefix caching if supported.](../sources/prs/vllm/PR-20930.md), [[Bugfix] Switch bailout logic for kv-cache-dtype with SM100 Flashinfer](../sources/prs/vllm/PR-20934.md), [[Bugfix] Fix Mistral3 support on SM100/SM120](../sources/prs/vllm/PR-20998.md), [[Perf] Use FlashInfer RoPE for RotaryEmbedding.forward_cuda when available](../sources/prs/vllm/PR-21126.md), [[Bug] DeepGemm: Fix TypeError: per_block_cast_to_fp8() missing 1 required positional argument: 'use_ue8m0' for SM100](../sources/prs/vllm/PR-21187.md), [Override attention metadata for fast prefill in some KV sharing setups](../sources/prs/vllm/PR-21590.md), [update flashinfer to v0.2.9rc2](../sources/prs/vllm/PR-21701.md), [[Logs] Change flashinfer sampler logs to once](../sources/prs/vllm/PR-21759.md), [[bugfix] fix blackwell deepep installation](../sources/prs/vllm/PR-22255.md), [[Bugfix] Fix 3D input passed into cutlass_scaled_mm](../sources/prs/vllm/PR-22278.md), [Update `flashinfer-python==0.2.10`](../sources/prs/vllm/PR-22389.md), [[Bug] Fix B200 DeepGEMM E8M0 Accuracy Issue](../sources/prs/vllm/PR-22399.md), [Upgrade FlashInfer to v0.2.11](../sources/prs/vllm/PR-22613.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [[Kernel] Added flashinfer fp8 per-tensor gemms](../sources/prs/vllm/PR-22895.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [[Perf] Small optimizations for silu_mul_fp8_quant_deep_gemm](../sources/prs/vllm/PR-23265.md), [[Perf] Use upstream CUTLASS for SM90 Block FP8 kernel](../sources/prs/vllm/PR-23280.md), [[Feature] Add Hopper DeepGEMM E8M0 for DeepSeekV3.1 scale_fmt](../sources/prs/vllm/PR-23666.md), [[Performance] Move apply_w8a8_block_fp8_linear to an op class](../sources/prs/vllm/PR-24666.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [Enable Fbgemm NVFP4 on Dense models](../sources/prs/vllm/PR-25609.md), [Update launch_bounds_utils.h for correct compile on Multiple Cuda Arch - PTXAS out of range Warning](../sources/prs/vllm/PR-25843.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[NVIDIA] Add support for cudnn fp4 gemm via flashinfer](../sources/prs/vllm/PR-26107.md), [[Bug] Fix Shape Validation for Fallback while Enabling E8M0 for DeepGEMM](../sources/prs/vllm/PR-26322.md), [Disable FlashInfer sampler by default](../sources/prs/vllm/PR-26859.md), [[Feature] Batch Invariant: Support DeepGEMM and Blackwell](../sources/prs/vllm/PR-27127.md), [[Feature] Batch Invariant for R1 TP 8 on Blackwell](../sources/prs/vllm/PR-27229.md), [[Perf] SM100 - add swap AB optimization to CUTLASS FP8 GEMM](../sources/prs/vllm/PR-27284.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Feature] Extend batch invariant torch.compile to B200](../sources/prs/vllm/PR-27856.md), [[Performance] Fused blockwise quant RMS norm](../sources/prs/vllm/PR-27883.md), [[Performance][B200] Fix deepgemm prologue](../sources/prs/vllm/PR-27897.md), [[Kernel] Optimize rms_norm kernel](../sources/prs/vllm/PR-27931.md), [[flashinfer][fix] do not check nvcc availability when using pre-downloaded cubins](../sources/prs/vllm/PR-27990.md), [[Performance][B200] silu_mul_quant: pack scales in int32](../sources/prs/vllm/PR-28358.md), [[Bugfix][Nixl] Fix kernel physical<>logical block_size issue ](../sources/prs/vllm/PR-28677.md), [[Performance] Reduce DeepGEMM N dim restriction from 128 to 64 multiplier ](../sources/prs/vllm/PR-28687.md), [[Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op)](../sources/prs/vllm/PR-29213.md), [[Perf] Disable DeepGEMM MoE by default when TP=8 is used](../sources/prs/vllm/PR-29346.md), [[Bugfix] Defunctionalize TRTLLM AR+Norm op for avoiding extra clone kernel before it](../sources/prs/vllm/PR-29631.md), [[Kernel]Support W4A8 Grouped GEMM on Hopper](../sources/prs/vllm/PR-29691.md), [[Bugfix] Fix mismatched nvfp4 gemm output shape](../sources/prs/vllm/PR-29742.md), [[Bugfix] Fix flashinfer ar+norm kernel not available issue](../sources/prs/vllm/PR-29960.md), [[Bugfix] Fix DeepGEMM after #29546 ](../sources/prs/vllm/PR-30267.md), [[Bugfix] Fix fp8 DeepGemm compilation issues](../sources/prs/vllm/PR-30336.md), [[BugFix] Fix `AttributeError: 'MergedColumnParallelLinear' object has no attribute 'weight_scale'`](../sources/prs/vllm/PR-30399.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Perf] enable flashinfer rotary_embedding custom ops in DeepSeek rotary](../sources/prs/vllm/PR-30729.md), [ [FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/vllm/PR-31099.md), [[Bugfix][Hardware][AMD] Consolidate FP8 min/max values helper function](../sources/prs/vllm/PR-31106.md), [[BugFix] add select_gemm_impl on CompressedTensorsWNA16MoEMethod to support LoRA](../sources/prs/vllm/PR-31453.md), [[FIX] Add NO_MUL activation support for modular kernel path](../sources/prs/vllm/PR-31528.md), [[Perf] Add opt-in SM100 Oink RMSNorm custom-op path](../sources/prs/vllm/PR-31828.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [[BugFix] Fix DeepSeek-V3.1 + DeepGEMM incompatible scale shapes](../sources/prs/vllm/PR-32361.md), [[Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper](../sources/prs/vllm/PR-32619.md), [[Performance] Tune Mamba selective scan kernel for B200](../sources/prs/vllm/PR-32873.md), [[Feature] Support CPU Offloading without Pytorch Pinned Memory that leads to doubled allocation](../sources/prs/vllm/PR-32993.md), [[Kernel] Apply 256bit LDG/STG To Activation Kernels](../sources/prs/vllm/PR-33022.md), [[Bugfix] Fix quant RMS norm fusion for quantization with TMA-aligned scales](../sources/prs/vllm/PR-33255.md), [[Bugfix] Register fp8 cutlass_group_gemm as supported for only SM90+SM100](../sources/prs/vllm/PR-33285.md), [[Feature][Core] Support Fabric detection to adapt the MNNVL protocol for the GB series](../sources/prs/vllm/PR-33540.md), [[Perf] Disable clean_logits in deepgemm fp8_mqa_logits kernel](../sources/prs/vllm/PR-33568.md), [[ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup)](../sources/prs/vllm/PR-34302.md), [[Bugfix] Enforce DeepGEMM when using sparse_attn_indexer on CUDA](../sources/prs/vllm/PR-34374.md), [[Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup)](../sources/prs/vllm/PR-34758.md), [[Bugfix] Gate 256-bit instructions to CUDA 12.9+](../sources/prs/vllm/PR-34791.md), [[Perf] Enable FlashInfer DeepGEMM swapAB on SM90 by default](../sources/prs/vllm/PR-34924.md), [[Bug][DSV3.2] Always prepare metadata for DeepGEMM Sparse Attention](../sources/prs/vllm/PR-35075.md), [[Performance] Cublas Bf16 Gate with Fp32 Output](../sources/prs/vllm/PR-35121.md), [[Bugfix] Fix DSV3 kernels breaking _C and _moe_C on unsupported arches](../sources/prs/vllm/PR-35123.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[MoE][Perf] Wrap DSV3 QKVAProj GEMM in custom op for torch.compile](../sources/prs/vllm/PR-35751.md), [[Mamba] Add stochastic rounding support](../sources/prs/vllm/PR-35753.md), [[MoE] Move PF Methods to Folder](../sources/prs/vllm/PR-35927.md), [[Kernel] Add FlashInfer MoE A2A Kernel](../sources/prs/vllm/PR-36022.md), [[Bugfix] Warm up Triton autotuner for GDN layers during V1 profiling](../sources/prs/vllm/PR-36599.md), [[GDN] add a config for gdn kernel selection](../sources/prs/vllm/PR-36647.md), [[Bug] Fix FlashInfer MNNVL socket collisions under concurrent vLLM jobs](../sources/prs/vllm/PR-36674.md), [Update Flashinfer to 0.6.6](../sources/prs/vllm/PR-36768.md), [[Bugfix] Fix FlashInfer GDN warmup ValueError on SM90 GPUs](../sources/prs/vllm/PR-36876.md), [[Kernel] Add gpt-oss Router GEMM kernel](../sources/prs/vllm/PR-37205.md), [[UX] Add flashinfer-cubin as CUDA default dep](../sources/prs/vllm/PR-37233.md), [refactor: abstract deepgemm support into platform](../sources/prs/vllm/PR-37519.md), [[Bug] Fix fp8 deepgemm batch invariant](../sources/prs/vllm/PR-37718.md), [[Perf] triton bilinear_pos_embed kernel for ViT](../sources/prs/vllm/PR-37948.md), [[Kernel] Optimize SM120 CUTLASS blockwise FP8 GEMM](../sources/prs/vllm/PR-37970.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [[Kernel] Add swapAB support for SM120 CUTLASS blockwise FP8 GEMM ](../sources/prs/vllm/PR-38325.md), [[CI Bugfix] Pre-download missing FlashInfer headers in Docker build](../sources/prs/vllm/PR-38391.md), [[Bugfix] Enable batch-invariant Triton matmul on all Ampere GPUs (SM 8x) ](../sources/prs/vllm/PR-38427.md), [[Perf] Batch KV cache swap copies via cuMemcpyBatchAsync](../sources/prs/vllm/PR-38460.md), [[Gemma4] Enable Fast Prefill Optimization](../sources/prs/vllm/PR-38879.md), [[Perf] Change Trtllm fp8 MoE to use Shuffled Weights and BlockMajorK Layout](../sources/prs/vllm/PR-38993.md), [[Gemma4] Support quantized MoE ](../sources/prs/vllm/PR-39045.md), [[Refactor] Move NVFP4 GEMM management into NvFp4LinearKernel](../sources/prs/vllm/PR-39129.md), [[Refactor] Move MXFP8 GEMM management into MxFp8LinearKernel](../sources/prs/vllm/PR-39205.md), [Use CU_MEMCPY_SRC_ACCESS_ORDER_ANY for batch KV cache swaps](../sources/prs/vllm/PR-39306.md), [Fix NUMA binding on non-CDMM Grace-Blackwell systems](../sources/prs/vllm/PR-39361.md), [[Perf] Fuse Zero Initializer for FP8 DeepGemm Block Quant Kernel](../sources/prs/vllm/PR-39547.md), [[Bugfix][NIXL] Fix `_logical_to_kernel_block_ids` conversion for non-mamba models](../sources/prs/vllm/PR-39724.md), [[Bugfix] Add Marlin kernel in block scaled mm kernel selection.](../sources/prs/vllm/PR-40105.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [[DSV4] Fuse norm and router for low latency scenario](../sources/prs/vllm/PR-41263.md), [[Spec Decode] Add Gemma4 MTP speculative decoding support](../sources/prs/vllm/PR-41745.md), [Add NVFP4 all-gather GEMM fusion for AsyncTP](../sources/prs/vllm/PR-41882.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [[Kernel] (1/N) Machete - Hopper Optimized Mixed Precision Linear Kernel ](../sources/prs/vllm/PR-7174.md), [[Kernel] (2/N) Machete - Integrate into CompressedTensorsWNA16 and GPTQMarlin](../sources/prs/vllm/PR-7701.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [FP8 Fine-Grained-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [GPU Mode NVFP4 Gated Dual GEMM](../wiki/kernels/gated-dual-gemm.md), [Grouped GEMM Contracts for MoE and NVFP4](../wiki/kernels/grouped-gemm.md), [NVFP4 GEMM — GPU Mode Problem 2 Contract](../wiki/kernels/nvfp4-gemm.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md) | +| `gemv` | [Twelve Attempts at an FP4 Kernel](../sources/blogs/amandeep-nvfp4-attempts.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [[None][feat] sm100 weight-only kernel](../sources/prs/TensorRT-LLM/PR-10190.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md) | +| `grouped-gemm` | [Anatomy of a Reward Hack](../sources/blogs/gpu-mode-reward-hack.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [FlashInfer MLSys 2026 Track A: FP8 Block-Scale MoE](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [fix: use SM90ArchSpec instead of SM100ArchSpec in sm90_bf16_k_grouped_gemm](../sources/prs/DeepGEMM/PR-270.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Use swizzling instead of padding](../sources/prs/DeepGEMM/PR-86.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[None][perf] Add more optimization options for MOE CuteDSL finalized kernel](../sources/prs/TensorRT-LLM/PR-10042.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [[None][feat] CuteDSL MOE FC1 Enhancement](../sources/prs/TensorRT-LLM/PR-10088.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [[None] [feat] Add test script and raster M for gather fc1 kernel](../sources/prs/TensorRT-LLM/PR-10429.md), [[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth](../sources/prs/TensorRT-LLM/PR-10987.md), [[None][feat] CuteDSL MOE: Add raster along M/N support for blockscaled contiguous backbone kernel](../sources/prs/TensorRT-LLM/PR-12079.md), [[None][feat] Add DWDP (Distributed Weight Data Parallelism) support for MoE inference](../sources/prs/TensorRT-LLM/PR-12136.md), [[TRTLLM-11585][feat] Add CUTEDSL moe backend for nemotron-h](../sources/prs/TensorRT-LLM/PR-12884.md), [[TRTLLM-9685] [feat] Add gather fc1 kernel by cuteDSL](../sources/prs/TensorRT-LLM/PR-9618.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [[Hopper CuTeDSL] Add grouped GEMM kernel example](../sources/prs/cutlass/PR-3091.md), [Support for Group GEMM in CUTLASS Profiler for GeForce and Spark](../sources/prs/cutlass/PR-3092.md), [perf: accelerate blackwell grouped gemm](../sources/prs/flashinfer/PR-1086.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [TVM: support TVM binding for GroupedGemm](../sources/prs/flashinfer/PR-1725.md), [feat: unit-test and api change, w4a8 grouped-gemm fused MoE for SM90](../sources/prs/flashinfer/PR-2193.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [refactor: Port upstream CUTLASS fixes and refactor grouped_gemm_nt_masked GEMM module location](../sources/prs/flashinfer/PR-2503.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [CuteDSL MoE fix redundant output buffer zeroing](../sources/prs/flashinfer/PR-2811.md), [feat: Add CuTe DSL grouped-gemm + combine fusion support](../sources/prs/flashinfer/PR-2944.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [[sgl-kernel][6/7]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-15471.md), [[Feature] Apply Cublas Grouped Gemm kernel](../sources/prs/sglang/PR-3629.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [[Kernel][B200] mxfp4 fused cutlass moe](../sources/prs/vllm/PR-23696.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [FlashInfer Track A FP8 Block-Scale MoE](../wiki/kernels/fused-moe.md), [Grouped GEMM Contracts for MoE and NVFP4](../wiki/kernels/grouped-gemm.md) | +| `linear-attention` | [Gated Delta Networks](../sources/blogs/gated-delta-net.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [FlashInfer MLSys 2026 Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [Tiled Flash Linear Attention (TFLA)](../sources/docs/tfla.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md) | +| `mla` | [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [K-Search: LLM Kernel Generation via Co-Evolving Intrinsic World Model](../sources/blogs/k-search-kernel-generation.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [DeepSeek-V2: A Strong, Economical, and Efficient Mixture-of-Experts Language Model](../sources/docs/deepseek-v2-mla.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[TRTLLM-11285][feat] Fuse indexer wk + weights_proj into single GEMM in TF32 for DS-V3.2](../sources/prs/TensorRT-LLM/PR-12055.md), [[https://nvbugs/5983390][perf] Split MLA DSA custom op for piecewise CUDA graph capture](../sources/prs/TensorRT-LLM/PR-12503.md), [[#12634][feat] AutoDeploy: Support rank 256 MLA in flashinfer_mla](../sources/prs/TensorRT-LLM/PR-12519.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [Flash MLA support](../sources/prs/cutlass/PR-2130.md), [Flash MLA Support - Step 2](../sources/prs/cutlass/PR-2134.md), [[ex77] fix mla split; add fwd lse; add bwd varlen](../sources/prs/cutlass/PR-2366.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [[Cute,Sm100,Fwd] add MLA 64/512 with topk sparsity for MQA 128 heads](../sources/prs/flash-attention/PR-2441.md), [bugfix: import wrapper of mla decode](../sources/prs/flashinfer/PR-1013.md), [misc: fix instrument code for mla profiler](../sources/prs/flashinfer/PR-1014.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [bugfix: temporally disable split-kv in blackwell mla](../sources/prs/flashinfer/PR-1055.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [feat: enable trtllm-gen mla MTP](../sources/prs/flashinfer/PR-1258.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [minor: add trtllm_gen_mla benchmark](../sources/prs/flashinfer/PR-1316.md), [feat: Fused rope fp8 quantize kernel for MLA](../sources/prs/flashinfer/PR-1339.md), [fix: fix trtllm-gen mla error on new interface](../sources/prs/flashinfer/PR-1348.md), [feat: enable trtllm-gen attn speculative decoding verify by decode](../sources/prs/flashinfer/PR-1453.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: Fix FLOPS calculation for bench_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-1640.md), [fix: zero-init workspace buffer for trtllm-gen fmha](../sources/prs/flashinfer/PR-1643.md), [Add benchmark for MLARopeQuantize](../sources/prs/flashinfer/PR-1656.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [Waive / disable test_mla_decode_kernel.py::test_mla_decode_kernel for not sm80 ](../sources/prs/flashinfer/PR-1771.md), [MLA RoPE + quantization fused kernel: shape generalization for MHA / GQA](../sources/prs/flashinfer/PR-1924.md), [minor fix for xqa](../sources/prs/flashinfer/PR-1994.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [use scalar for kv_scale in xqa](../sources/prs/flashinfer/PR-2033.md), [feat: Add flashinfer.rope.rope_quantize_fp8_append_paged_kv_cache (fused RoPE + Q + KV cache, supports MLA/GQA/MHA) ](../sources/prs/flashinfer/PR-2037.md), [feat: add xqa mla backend](../sources/prs/flashinfer/PR-2053.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [[DSR1] Added MLA test](../sources/prs/flashinfer/PR-2100.md), [add tensor scale input for xqa](../sources/prs/flashinfer/PR-2110.md), [feature: make the LSE returned by MLA support base 2 or e #2113](../sources/prs/flashinfer/PR-2114.md), [update xqa license](../sources/prs/flashinfer/PR-2117.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [fix flaky xqa test](../sources/prs/flashinfer/PR-2126.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [refactor: Move mla code from decode.py to mla.py and add to documentation](../sources/prs/flashinfer/PR-2163.md), [[feat] Integrate SGLang concat_mla_k kernel into flashinfer](../sources/prs/flashinfer/PR-2237.md), [Support both 3D and 4D kv_cache shapes in MLA APIs](../sources/prs/flashinfer/PR-2334.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [fix: Fix memory bandwidth calculation in MLA benchmarks](../sources/prs/flashinfer/PR-2479.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [support qk_nope_head_dim for 192 check for GLM-5](../sources/prs/flashinfer/PR-2607.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [[Spark unit test debugging] Fix for tests/attention/test_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-2750.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [feat: FP8 output support for CUTLASS MLA paged attention](../sources/prs/flashinfer/PR-2779.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [[Fmha] Sparse MLA decode kernel selection heuristics](../sources/prs/flashinfer/PR-2836.md), [[fix] bugfix 2856: Fix pre-allocated out shape check in trtllm_batch_decode_with_kv_cache_mla for q_len_per_req > 1](../sources/prs/flashinfer/PR-2876.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16](../sources/prs/flashinfer/PR-3129.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [bugfix: MLA decode should multiply sm_scale by math::log2e](../sources/prs/flashinfer/PR-787.md), [fix rope logic in mla decoding](../sources/prs/flashinfer/PR-793.md), [perf: memory efficient deepseek mla fused page-attention kernel](../sources/prs/flashinfer/PR-804.md), [bugfix: mla page-attention kernel for different page sizes](../sources/prs/flashinfer/PR-810.md), [feat: unlocking MLA for A100](../sources/prs/flashinfer/PR-812.md), [feat: unlock MLA attention for sm89 (L40/L40s/4090)](../sources/prs/flashinfer/PR-814.md), [bugfix: fix the behavior of mla plan function when provided with host tensors](../sources/prs/flashinfer/PR-816.md), [bugfix: bugfix on sm89 MLA](../sources/prs/flashinfer/PR-821.md), [perf: MLA decode kernel implemented by CuTe targeted to SM80](../sources/prs/flashinfer/PR-844.md), [misc: Remove duplicate param set in MLA kernel](../sources/prs/flashinfer/PR-850.md), [unittest: add MLA test cases where kv_len is evenly divided by page_size.](../sources/prs/flashinfer/PR-861.md), [perf: dynamic split-k for MLA](../sources/prs/flashinfer/PR-863.md), [bugfix: fix the behavior of MLA kernel when kv-length is 0](../sources/prs/flashinfer/PR-868.md), [perf: FlashAttention-3 style MLA PageAttention](../sources/prs/flashinfer/PR-887.md), [feat - support mla kvcache store](../sources/prs/flashinfer/PR-888.md), [perf: fix MLA split-k performance bug](../sources/prs/flashinfer/PR-898.md), [perf: tweak the pipeline design of mla kernel](../sources/prs/flashinfer/PR-901.md), [feat: flashinfer intra-kernel profiler](../sources/prs/flashinfer/PR-913.md), [bugfix: fix potential issues of FA3 template loading nans for PageAttention](../sources/prs/flashinfer/PR-945.md), [perf: Use 2WG pipeline design for MLA implementation on Hopper](../sources/prs/flashinfer/PR-952.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [perf: prefetch page indices for mla kernel](../sources/prs/flashinfer/PR-991.md), [3rdparty: upgrade cutlass to 3.9](../sources/prs/flashinfer/PR-997.md), [Disable kernel cutlass_mla_decode on SM103](../sources/prs/sglang/PR-10058.md), [feat: Add FP4 (E2M1) KV Cache Support with Quantization Utilities for MLA](../sources/prs/sglang/PR-10078.md), [[Feature] Add MLAProcess for DeepSeek MLA on NPU](../sources/prs/sglang/PR-10130.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [Enable trtllm mla prefix extend](../sources/prs/sglang/PR-10526.md), [[sgl-kernel] Optimize concat_mla_k kernel](../sources/prs/sglang/PR-10543.md), [Fuse quantize and rope in trtllm_mla MTP](../sources/prs/sglang/PR-10779.md), [disable sm100 for FlashMLA and fast-hadamard-transform in cuda12.6.1](../sources/prs/sglang/PR-11274.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [Use trtllm_mla decode kernel for draft extend in speculative decoding](../sources/prs/sglang/PR-11664.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [[sgl-kernel] support flashmla libtorch](../sources/prs/sglang/PR-11717.md), [Fixed aarch64 flash-mla](../sources/prs/sglang/PR-12009.md), [[DeepseekV32]: use `_concat_mla_absorb_q_general` to replace `torch.cat`](../sources/prs/sglang/PR-12215.md), [[Deepseek V3.2] Enable flashmla_auto with MTP](../sources/prs/sglang/PR-12294.md), [fix seqlen bug for trtllm_mla's draft_extend](../sources/prs/sglang/PR-12295.md), [perf: trtllm mla performance minor improvements](../sources/prs/sglang/PR-12435.md), [[Fix] `concat_mla_absorb_q_kernel` fails for long inputs](../sources/prs/sglang/PR-12453.md), [[Ascend] Support enable-mixed-chunk in non-MLA scenarios](../sources/prs/sglang/PR-12491.md), [[sgl-kernel] support custom fp8 flashmla kernel](../sources/prs/sglang/PR-13087.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Fix target MLA with eagle3 support for PD disaggregation](../sources/prs/sglang/PR-13555.md), [[BugFix] fix prefixcache performance and accuracy on ascend](../sources/prs/sglang/PR-13573.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [fix trtllm mla spec](../sources/prs/sglang/PR-13738.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[bug fix] fix ima with get_mla_kv_buffer_kernel overflow](../sources/prs/sglang/PR-14224.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [[NPU] perf update with kvcache nz & w4a8 quant](../sources/prs/sglang/PR-14423.md), [Add Mistral Large 3 Eagle Support](../sources/prs/sglang/PR-14466.md), [Fix accuracy issue when using a16w16 mla_decode_fwd](../sources/prs/sglang/PR-14936.md), [[sgl-kernel] Update flashmla to include fp8 sparse_mla optimizations](../sources/prs/sglang/PR-15242.md), [[NPU]DeepSeek-V3.2 support npu mlaprolog](../sources/prs/sglang/PR-15381.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [Fix BatchMLAPagedAttentionWrapper query/qo_inptr mismatch for EAGLE](../sources/prs/sglang/PR-15601.md), [Bugfix for ds-vl2](../sources/prs/sglang/PR-15894.md), [enhance accuracy for model kimi-vl-instruct-a3b](../sources/prs/sglang/PR-16076.md), [[NPU]bugfix: fix for dsv3.2 and dsvl2](../sources/prs/sglang/PR-17007.md), [Disable mla persistent kernel when not using fp8 kv_cache](../sources/prs/sglang/PR-17327.md), [[NPU] enhance accuracy for model kimi-vl-a3b-instruct](../sources/prs/sglang/PR-17480.md), [Make flashMLA work on: Cu13, B300](../sources/prs/sglang/PR-17600.md), [[Move sgl-kernel Kernel to JIT] Add JIT concat MLA kernels](../sources/prs/sglang/PR-17889.md), [[Hicache & JIT_kernel] Support page first layout & mla jit kernel](../sources/prs/sglang/PR-18311.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [[AMD] DSR1/V3 use fp8 bmm in MLA for MI300X](../sources/prs/sglang/PR-18624.md), [[sgl-kernel] rebase FlashMLA 0217](../sources/prs/sglang/PR-18902.md), [Support skip-softmax attention](../sources/prs/sglang/PR-19089.md), [[Feature] add feature mla_ag_after_qlora for dsv3.2](../sources/prs/sglang/PR-19428.md), [[NPU] bugs fix for Deepseek models](../sources/prs/sglang/PR-19544.md), [Fix MLA decode path returning unwritten (padded) rows](../sources/prs/sglang/PR-19902.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [Fix streaming session with paged KV cache (SWA/MLA)](../sources/prs/sglang/PR-20070.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[AMD][AITER] Guard _use_mla_ps_kernel with self.use_mla in draft_extend_v2 paths](../sources/prs/sglang/PR-20409.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [test: point DSV3 int8 MLA CI models to lmsys Hugging Face org](../sources/prs/sglang/PR-21561.md), [[DSA] Support trtllm sparse mla kernel for prefill batches ](../sources/prs/sglang/PR-21783.md), [[Bugfix] Fix CUDA graph replay issues in trtllm_mla draft_extend](../sources/prs/sglang/PR-21987.md), [[NPU] enable mla prepare fused kernel only when being mla attn](../sources/prs/sglang/PR-22024.md), [[Disagg][NIXL] Fix heterogeneous TP KV transfer for non-MLA models (same logic with mooncake, Step 1/2 for Qwen3.5 support)](../sources/prs/sglang/PR-22145.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [[DSA] Hopper FP8 FlashMLA KV padding](../sources/prs/sglang/PR-22372.md), [[Fix] Fix accuracy bug in Flashmla sparse MLA kernel](../sources/prs/sglang/PR-22723.md), [Support spec v2 for FlashMLA speculative decoding](../sources/prs/sglang/PR-24640.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [Support draft extend cuda graph for tokenspeed_mla attention backend](../sources/prs/sglang/PR-25489.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [feat: support flashinfer mla attention for deepseek v3](../sources/prs/sglang/PR-3550.md), [feat: support flashinfer mla with prefix cache](../sources/prs/sglang/PR-3643.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [Hierarchical Caching supports MLA](../sources/prs/sglang/PR-4009.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [[Fix] Fix raw_bs bug when using flashinfer mla and eagle](../sources/prs/sglang/PR-4557.md), [avoid cudaStreamSynchronize in DeepSeekV2AttentionMLA](../sources/prs/sglang/PR-4577.md), [Blackwell Cutlass MLA kernel](../sources/prs/sglang/PR-5142.md), [feat: use fa3 mla by default on hopper](../sources/prs/sglang/PR-5210.md), [fix: solve cu118 issue for cutlass mla](../sources/prs/sglang/PR-5331.md), [[PD Bug] fix MLA get_contiguous_buf_infos error](../sources/prs/sglang/PR-5384.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[PD] Fix dynamic port support and MLA buffer for Mooncake](../sources/prs/sglang/PR-5415.md), [BLackwell cutlass mla: Add check for bad page size/block num combinations](../sources/prs/sglang/PR-5431.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Avoid computing lse in Ragged Prefill when there's no prefix.](../sources/prs/sglang/PR-5476.md), [Fuse MLA set kv cache kernel](../sources/prs/sglang/PR-5748.md), [opt flashinfer mla cat](../sources/prs/sglang/PR-5822.md), [Cutlass MLA decode - fix dtype error](../sources/prs/sglang/PR-5868.md), [[Fix] Fix a bug for flashmla to run R1 model](../sources/prs/sglang/PR-5875.md), [KV‑Cache (MHA, MLA): add missing start_layer / end_layer fields to MHATokenToKVPoolHost and MLATokenToKVPoolHost](../sources/prs/sglang/PR-6016.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [Cutlass MLA: Disable split kv due to https://github.com/NVIDIA/cutlass/issues/2274](../sources/prs/sglang/PR-6101.md), [fix: fix MLA for ShardedModelLoader/RemoteModelLoader](../sources/prs/sglang/PR-6287.md), [[PD] Add different TP sizes support for no-MLA models](../sources/prs/sglang/PR-6793.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [Fix cutlass MLA gets almost zero accuracy](../sources/prs/sglang/PR-6998.md), [Tiny fix cutlass_mla_get_workspace_size stub incorrect signature](../sources/prs/sglang/PR-7057.md), [chore: upgrade sgl-kernel v0.1.8.post2](../sources/prs/sglang/PR-7186.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [Minor style and doc fix](../sources/prs/sglang/PR-7228.md), [Fix CPU offloading for MLA memory pool](../sources/prs/sglang/PR-7409.md), [TRTLLM-MLA FP8 path](../sources/prs/sglang/PR-8638.md), [fix mooncake store mla zero copy meta](../sources/prs/sglang/PR-9678.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[Perf] Enable fast math in sparse MLA example](../sources/prs/tilelang/PR-2219.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Attention] Deepseek v3 MLA support with FP8 compute](../sources/prs/vllm/PR-12601.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [Disable chunked prefill and/or prefix caching when MLA is enabled ](../sources/prs/vllm/PR-12642.md), [[AMD][ROCm] Enable DeepSeek model on ROCm](../sources/prs/vllm/PR-12662.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [Squelch MLA warning for Compressed-Tensors Models](../sources/prs/vllm/PR-12704.md), [[VLM] Add MLA with pure RoPE support for deepseek-vl2 models](../sources/prs/vllm/PR-12729.md), [[Kernel] Make rotary_embedding ops more flexible with input shape](../sources/prs/vllm/PR-12777.md), [[Attention] Use FA3 for MLA on Hopper](../sources/prs/vllm/PR-12807.md), [Expand MLA to support most types of quantization](../sources/prs/vllm/PR-13181.md), [[Bugfix] Massage MLA's usage of flash attn for RoCM](../sources/prs/vllm/PR-13310.md), [[Bugfix] Fix max_num_batched_tokens for MLA](../sources/prs/vllm/PR-13620.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[Bugfix] Support MLA for CompressedTensorsWNA16](../sources/prs/vllm/PR-13725.md), [[Kernel] FlashMLA integration](../sources/prs/vllm/PR-13747.md), [[Attention] MLA support for V1](../sources/prs/vllm/PR-13789.md), [[ROCm] Disable chunked prefill/prefix caching when running MLA on non-cuda platforms](../sources/prs/vllm/PR-13844.md), [[Attention] Flash MLA for V1](../sources/prs/vllm/PR-13867.md), [Fix mla prefill context performance](../sources/prs/vllm/PR-13897.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[BugFix] MLA + V1, illegal memory access and accuracy issues](../sources/prs/vllm/PR-14253.md), [[BugFix] Fix prefix caching V0 MLA](../sources/prs/vllm/PR-14255.md), [[Attention] FlashAttn MLA](../sources/prs/vllm/PR-14258.md), [[ROCm] Enable chunked prefill/paged attention in MLA on ROCm](../sources/prs/vllm/PR-14316.md), [[Perf] Reduce MLA CPU overheads in V1](../sources/prs/vllm/PR-14384.md), [[Bugfix] DeepSeek Accuracy](../sources/prs/vllm/PR-14476.md), [[Perf] Improve MLA on V1](../sources/prs/vllm/PR-14540.md), [[BugFix][TritonMLA] Process weights after model loading for GGUF](../sources/prs/vllm/PR-14555.md), [[Attention] Flash Attention 3 - fp8](../sources/prs/vllm/PR-14570.md), [[Kernel][CPU] CPU MLA](../sources/prs/vllm/PR-14744.md), [[Attention] MLA get rid of materialization](../sources/prs/vllm/PR-14770.md), [[Attention] Get rid of mla cache alignment](../sources/prs/vllm/PR-14842.md), [[V1] Default MLA to V1](../sources/prs/vllm/PR-14921.md), [[BugFix] Fix nightly MLA failure (FA2 + MLA chunked prefill, i.e. V1, producing bad results)](../sources/prs/vllm/PR-15492.md), [[Bugfix] Fix cache block size calculation for CPU MLA](../sources/prs/vllm/PR-15848.md), [[FEAT][ROCm]: Support AITER MLA](../sources/prs/vllm/PR-15893.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[Kernel] support merge_attn_states CUDA kernel, 3x speedup](../sources/prs/vllm/PR-16173.md), [[MLA] Simplification to batch P/D reordering](../sources/prs/vllm/PR-16673.md), [[V1] V1 FlashInfer Attention](../sources/prs/vllm/PR-16684.md), [[torch.compile][ROCm] Fuse quantization onto attention using a torch.compile pass](../sources/prs/vllm/PR-16756.md), [[Bugfix] Triton FA function takes no keyword arguments](../sources/prs/vllm/PR-16902.md), [[Bugfix] Add contiguous call inside rope kernel wrapper](../sources/prs/vllm/PR-17091.md), [[BugFix] Fix vllm_flash_attn install issues](../sources/prs/vllm/PR-17267.md), [[Misc][ROCm] Exclude `cutlass_mla_decode` for ROCm build](../sources/prs/vllm/PR-17289.md), [[v1] AttentionMetadata for each layer](../sources/prs/vllm/PR-17394.md), [[v1] Pass BlockTable and KVCacheSpec to AttentionMetadataBuilders](../sources/prs/vllm/PR-17483.md), [[Attention] MLA move o_proj q_proj into cuda-graph region](../sources/prs/vllm/PR-17484.md), [[BugFix] Fix mla cpu - missing 3 required positional arguments](../sources/prs/vllm/PR-17494.md), [[FEAT][ROCm]: Support AITER MLA on V1 Engine](../sources/prs/vllm/PR-17523.md), [[Attention] MLA move rotary embedding to cuda-graph region](../sources/prs/vllm/PR-17668.md), [fix amd triton mla path](../sources/prs/vllm/PR-17871.md), [[Bugfix][ROCm] Fix AITER MLA V1](../sources/prs/vllm/PR-17880.md), [[BugFix][AMD] Compatible patch for AITER lib after 04/20](../sources/prs/vllm/PR-17912.md), [[v1] Support multiple KV cache groups in GPU model runner](../sources/prs/vllm/PR-17945.md), [[BUG] [ROCm] [MLA] Fix variable name bug due to change in variable name in PR #17483](../sources/prs/vllm/PR-17961.md), [[BugFix] FA2 MLA Accuracy Issue](../sources/prs/vllm/PR-18807.md), [[Kernel] Apply torch.Tag.needs_fixed_stride_order only for torch==2.6.0](../sources/prs/vllm/PR-19346.md), [[Bugfix] Enable PP with AITER+V1](../sources/prs/vllm/PR-19822.md), [[Attention] MLA - Flashinfer Ragged Prefill](../sources/prs/vllm/PR-20034.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[Kernel] Flashinfer MLA (trtllm-gen) decode kernel integration](../sources/prs/vllm/PR-21078.md), [[perf] Add fused MLA QKV + strided layernorm](../sources/prs/vllm/PR-21116.md), [[v1][attention] Support Hybrid Allocator + FlashInfer](../sources/prs/vllm/PR-21412.md), [[BugFix] Fix IMA FlashMLA full cuda-graph and DP + Update FlashMLA](../sources/prs/vllm/PR-21691.md), [[Bugfix] Check NVIDIA artifactory is accessible before using flashinfer cubin kernels](../sources/prs/vllm/PR-21893.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [[Log] Warning Once for Cutlass MLA ](../sources/prs/vllm/PR-23137.md), [[ROCm][Aiter] Add triton fp8 bmm kernel for mla](../sources/prs/vllm/PR-23264.md), [[Compile] Fix Compile Warning SM100 Cutlass MLA](../sources/prs/vllm/PR-23287.md), [[Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-23465.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Kernel] Support decode context parallelism on Blackwell with CUTLASS MLA](../sources/prs/vllm/PR-24385.md), [[Feature] Disallow FlashMLA on Blackwell](../sources/prs/vllm/PR-24521.md), [[Bug] Fix `is_flashmla_supported` Check Error](../sources/prs/vllm/PR-24774.md), [[Bugfix][B200] Fix `cutlass_mla` hang](../sources/prs/vllm/PR-24966.md), [[Attention][DCP] Support DCP with query length > 1 (MTP) with FA3](../sources/prs/vllm/PR-25049.md), [[Bug] Fix `returned_lse` not Defined issue](../sources/prs/vllm/PR-25106.md), [[BugFix] Fix MLA assert with CUTLASS MLA](../sources/prs/vllm/PR-25478.md), [[Bugfix] [B200] cutlass_mla - ensure kv_split == 1 for batch size > 1](../sources/prs/vllm/PR-25509.md), [Fuse RoPE and MLA KV-cache write](../sources/prs/vllm/PR-25774.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Spec Decode] Enable efficient speculative decoding with FlashInfer-MLA](../sources/prs/vllm/PR-25984.md), [[Attention] Tune CUTLASS MLA num_splits](../sources/prs/vllm/PR-26846.md), [Prefer FlashAttention MLA as default over FlashMLA](../sources/prs/vllm/PR-27363.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[AMD] Use Decoupled Kernel Block Size to Support AITER MLA block_size=1](../sources/prs/vllm/PR-27715.md), [[Bug] Batch invariant: Fix flash attn MLA `RuntimeError: scheduler_metadata must have shape (metadata_size)`](../sources/prs/vllm/PR-27884.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [bugfix: correct attn output with base 2 or e](../sources/prs/vllm/PR-28840.md), [[BugFix] Fix async-scheduling + FlashAttn MLA](../sources/prs/vllm/PR-28990.md), [[DeepSeek + LMCache Multiprocess] handle MLA for deepseek model + LMCache Multiprocess connector](../sources/prs/vllm/PR-29039.md), [[Feature] Batch invariant: Enable `TRITON_MLA` without prefix-caching](../sources/prs/vllm/PR-29125.md), [[perf] Use direct copy (broadcast) instead of cat for k_nope/k_pe in MLA prefill](../sources/prs/vllm/PR-29710.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[Perf] Improve fp8 quant in mla; replace ReduceSum with ReduceScatterSum](../sources/prs/vllm/PR-29795.md), [[SpecDecode] Simplified alternative padded-speculation acceptance rate fix](../sources/prs/vllm/PR-29845.md), [[Quantization] fix: overflow with static per-tensor scaling](../sources/prs/vllm/PR-29867.md), [[ROCm] add fallback for aiter fp8 decode mla](../sources/prs/vllm/PR-30005.md), [[ROCm][Bugfix] Add MLACommonMetadata to allowed attention types for speculative decoding](../sources/prs/vllm/PR-30430.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[perf] Integrate flashinfer concat_mla_k](../sources/prs/vllm/PR-31171.md), [[Bugfix][Hardware][AMD] Fix exception types in AITER MLA FP8 check](../sources/prs/vllm/PR-31177.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][Hardware][AMD] Fix last_page_len calculation in AITER MLA decode](../sources/prs/vllm/PR-31282.md), [fixed mypy warnings for files vllm/v1/attention with TEMPORARY workaround](../sources/prs/vllm/PR-31465.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[4/N][Attention] Move MLA common to model_executor](../sources/prs/vllm/PR-32060.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [fix: Add glm4_moe_lite to MLA detection](../sources/prs/vllm/PR-32614.md), [[Bugfix][Attention] Explicitly report support for kv_cache_dtype bfloat16](../sources/prs/vllm/PR-32795.md), [[Attention] FA4 integration](../sources/prs/vllm/PR-32974.md), [[Attention] Use `has_flashinfer` helper](../sources/prs/vllm/PR-33177.md), [Triton MLA perf fixes](../sources/prs/vllm/PR-33529.md), [[Bugfix] Fix sparse MLA metadata building](../sources/prs/vllm/PR-33579.md), [[Bugfix] fix DeepSeek R1 with CUTLASS MLA Broken on B200](../sources/prs/vllm/PR-33637.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [Reapply [Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-34043.md), [fix(cpu): fix mla_decode compilation on x86 without AVX512](../sources/prs/vllm/PR-34052.md), [[BugFix] Add support for MTP num_speculative_tokens > 1 with sparse MLA](../sources/prs/vllm/PR-34552.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [[Bugfix] Fix MLA attention crash with AWQ/GPTQ quantized models](../sources/prs/vllm/PR-34695.md), [[Attention] Use FA4 for MLA prefill](../sources/prs/vllm/PR-34732.md), [[Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup)](../sources/prs/vllm/PR-34758.md), [[Model Bash][DSR1] Add selective dynamic shape marking for CustomOp](../sources/prs/vllm/PR-34900.md), [[Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2](../sources/prs/vllm/PR-34917.md), [[Bug][DSV3.2] Always prepare metadata for DeepGEMM Sparse Attention](../sources/prs/vllm/PR-35075.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[Bugfix] Fix KV Scale loading for MLA Models](../sources/prs/vllm/PR-35430.md), [[ROCm] Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5/Linear)](../sources/prs/vllm/PR-35850.md), [[Perf] Support FP8 KV cache for Flashinfer MLA Sparse](../sources/prs/vllm/PR-35891.md), [[LMCache] Pass TP size in lookup for MLA multi-reader locking](../sources/prs/vllm/PR-36129.md), [Add 320 dimension size support to MLA](../sources/prs/vllm/PR-36161.md), [[Bugfix][MLA] Add logits size budget to sparse indexer prefill chunking](../sources/prs/vllm/PR-36178.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [mla: don't update kv cache on dummy forwards](../sources/prs/vllm/PR-36282.md), [Kimi k2.5 MLA based eagle3](../sources/prs/vllm/PR-36361.md), [[Bugfix][Sparse MLA] report indexer CG support properly](../sources/prs/vllm/PR-36519.md), [[ROCm] Utilize persistent MLA kernel from AITER](../sources/prs/vllm/PR-36574.md), [[ROCm][Perf] Allow MTP lens > 1 in Sparse MLA](../sources/prs/vllm/PR-36681.md), [[DSV3.2][MTP] Optimize Indexer MTP handling](../sources/prs/vllm/PR-36723.md), [[Feat][Bugfix] Enable additional dimension for Flashinfer MLA and fix routing dtype](../sources/prs/vllm/PR-36931.md), [[MTP][Sparse MLA] Take advantage of native MTP support in indexer when possible](../sources/prs/vllm/PR-36982.md), [[Bugfix] Fix KV scales inconsistency in fp8 MLA & FlashInfer kv_cache_dtype "auto" leading to gibberish](../sources/prs/vllm/PR-37054.md), [[Bugfix] Disable cross-layer KV cache for MLA attention backends](../sources/prs/vllm/PR-37090.md), [[Benchmark] Improvements to attention benchmark script](../sources/prs/vllm/PR-37115.md), [[XPU] support MLA model on Intel GPU](../sources/prs/vllm/PR-37143.md), [[Misc] Add `float16` to `CacheDType`](../sources/prs/vllm/PR-37199.md), [[Perf] Set Flashinfer sparse MLA as default backend for FP8 kv cache](../sources/prs/vllm/PR-37252.md), [[Perf][Kernel] Persistent TopK scheduler: unified CUDAGraph-safe kernel with dynamic per-row dispatch - DeepSeek-V3.2 DSA decode](../sources/prs/vllm/PR-37421.md), [[BugFix] Allow qk_nope_head_dim=192 in FlashInfer MLA backend checks](../sources/prs/vllm/PR-37475.md), [Fix KV Offloading + MLA AssertionError by using num_kv_heads=1 in cpu…](../sources/prs/vllm/PR-37536.md), [[Performance] Remove unnecessary zero-fill of MLA decode output tensor in Aiter backend](../sources/prs/vllm/PR-37539.md), [[Bugfix][ROCm] Fix lru_cache on paged_mqa_logits_module](../sources/prs/vllm/PR-37547.md), [[Test] Only Run MLA model when user explicitly set for batch invariance](../sources/prs/vllm/PR-37719.md), [[ROCm][perf] fix Aiter sparse MLA with MTP>1](../sources/prs/vllm/PR-37887.md), [[Bugfix][MLA] Change default SM100 MLA prefill backend back to TRT-LLM](../sources/prs/vllm/PR-38562.md), [[ROCm] Fix aiter persistent mode mla with q/o nhead<16 for kimi-k2.5 tp8](../sources/prs/vllm/PR-38615.md), [Fix MLA runs when use_inductor_graph_partition=True](../sources/prs/vllm/PR-38631.md), [[LMCache][MP] optimize save when mla enabled](../sources/prs/vllm/PR-38810.md), [[Attention][MLA] Re-enable FA4 as default MLA prefill backend](../sources/prs/vllm/PR-38819.md), [[Refactor] Improve indexer decode path metadata preparation](../sources/prs/vllm/PR-38865.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [[Bug] Fix rocm sparse attn indexer issue](../sources/prs/vllm/PR-39225.md), [[MLA] Optimize mla indexer prepare uniform decode for MTP > 1](../sources/prs/vllm/PR-39458.md), [[Mooncake] Fix mixed MLA+Eagle block-size validation](../sources/prs/vllm/PR-39596.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[Performance][DSR1]: Fused RoPE+KVCache+q_concat for MLA](../sources/prs/vllm/PR-40392.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[Bugfix] Fix TRTLLM ragged MLA prefill workspace warmup](../sources/prs/vllm/PR-42112.md), [[ROCm] [Bugfix] Fix DeepSeek V4 Functionality and Accuracy](../sources/prs/vllm/PR-42810.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [[Model Refactoring] Move deepseek_v4_ops to models/deepseek_v4 [3/N]](../sources/prs/vllm/PR-43073.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [DeepSeek Sparse Attention / Sparse MLA](../wiki/kernels/sparse-mla.md) | +| `moe` | [K-Search: LLM Kernel Generation via Co-Evolving Intrinsic World Model](../sources/blogs/k-search-kernel-generation.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [TFLOPS Gap: Why FP4 MoE Kernel Engineering Matters on Blackwell](../sources/blogs/tflops-gap-fp4-moe.md), [FlashInfer MLSys 2026 Track A: FP8 Block-Scale MoE](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [[None][perf] Add more optimization options for MOE CuteDSL finalized kernel](../sources/prs/TensorRT-LLM/PR-10042.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [[None][feat] CuteDSL MOE FC1 Enhancement](../sources/prs/TensorRT-LLM/PR-10088.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [[TRTLLM-10147][perf] Balanced random MoE workload generator for CuteDSL kernel UT, autotuner and layerwise benchmark](../sources/prs/TensorRT-LLM/PR-10279.md), [[None] [feat] Add densegemm backend for MoE](../sources/prs/TensorRT-LLM/PR-10479.md), [[None][feat] MiniMax M2 support](../sources/prs/TensorRT-LLM/PR-10532.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[None][feat] TRT-LLM Gen MoE finalize kernel optimization](../sources/prs/TensorRT-LLM/PR-11501.md), [[None][feat] Add support for expert_number<=2048 and K<=32](../sources/prs/TensorRT-LLM/PR-11510.md), [[None][fix] Fix int4 awq for sm120/121](../sources/prs/TensorRT-LLM/PR-11561.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[https://nvbugs/5885070][fix] fix deepeplowlatency with cutedsl moe backend](../sources/prs/TensorRT-LLM/PR-11769.md), [[TRTLLM-10990][feat] Fuse SwiGLU and quant into shared expert](../sources/prs/TensorRT-LLM/PR-11897.md), [[None][feat] GLM 5 support and DSA MTP fixes](../sources/prs/TensorRT-LLM/PR-11990.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[https://nvbugs/5955188][fix] Fix harmony parsers and WAR routing PDL for agentic coding use cases](../sources/prs/TensorRT-LLM/PR-12046.md), [[None][feat] CuteDSL MOE: Add raster along M/N support for blockscaled contiguous backbone kernel](../sources/prs/TensorRT-LLM/PR-12079.md), [[None][feat] Add DWDP (Distributed Weight Data Parallelism) support for MoE inference](../sources/prs/TensorRT-LLM/PR-12136.md), [[None][feat] Add fused allreduce+RMSNorm op and optional residual in …](../sources/prs/TensorRT-LLM/PR-12201.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[None][perf] add Dynamic SMEM block routing in MOE](../sources/prs/TensorRT-LLM/PR-12456.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[None][feat] Add bf16 trtllm-gen moe support through flashinfer.](../sources/prs/TensorRT-LLM/PR-12738.md), [[TRTLLM-11797][feat] Add cutedsl moe backend supporting for qwen3.5.](../sources/prs/TensorRT-LLM/PR-12799.md), [[TRTLLM-11585][feat] Add CUTEDSL moe backend for nemotron-h](../sources/prs/TensorRT-LLM/PR-12884.md), [[#12784][feat] AutoDeploy: Optimize DeepSeek-R1 model performance](../sources/prs/TensorRT-LLM/PR-12946.md), [[None][fix] Propagate init_load_balancer to DeepGemmFusedMoE in create_moe_backend](../sources/prs/TensorRT-LLM/PR-13207.md), [[TRTLLM-11127][feat] add W4A8_MXFP4_FP8 MoE unit test support](../sources/prs/TensorRT-LLM/PR-13401.md), [[None][perf] Extend customMoeRouting kernel to support Qwen3.5](../sources/prs/TensorRT-LLM/PR-13433.md), [[None][feat] Enable EPLB for DeepSeek-V4](../sources/prs/TensorRT-LLM/PR-13595.md), [[None][feat] Add bf16 trtllm moe through flashinfer.](../sources/prs/TensorRT-LLM/PR-13689.md), [[None][fix] Plumb swiglu_limit through DeepGEMM and TRTLLMGen FP8 fused MoE](../sources/prs/TensorRT-LLM/PR-13767.md), [[None][perf] FC2 DenseGEMM autotune: split-K, swap_ab, fine-grained tuning buckets](../sources/prs/TensorRT-LLM/PR-13833.md), [[None][feat] enable TRTLLM-Gen internal routing](../sources/prs/TensorRT-LLM/PR-13997.md), [[https://nvbugs/6152892][fix] Fix Triton MOE memory free when no swizzling enabled](../sources/prs/TensorRT-LLM/PR-14069.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][fix] Avoid dp_size x ep_size double-count in MegaMoEDeepGemm SymmBuffer](../sources/prs/TensorRT-LLM/PR-14213.md), [[None][fix] Update the OSS headers in derived FLA ops and AD modeling code](../sources/prs/TensorRT-LLM/PR-14281.md), [[https://nvbugs/6095421][fix] Update resolve_moe_backend](../sources/prs/TensorRT-LLM/PR-14282.md), [[None][chore] Update Claude Code agents and skills](../sources/prs/TensorRT-LLM/PR-14344.md), [[None][chore] Fix kernel launch param and add TRTLLM MoE backend test](../sources/prs/TensorRT-LLM/PR-7524.md), [[None][fix] Fix and add test for TRTLLM MoE backend](../sources/prs/TensorRT-LLM/PR-7755.md), [[TRTLLM-8637][feat] Optimize the routing kernel for DeepseekV3 (MoE CUTLASS backend); Add support for 384 experts (MoE TRTLLM backend)](../sources/prs/TensorRT-LLM/PR-7761.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [[TRTLLM-8827] [feat] Enable low precision alltoall for Cutlass and TRTLLMGen backends](../sources/prs/TensorRT-LLM/PR-8675.md), [[None][feat] Enable EPLB for trtllm-gen and cutlass backend](../sources/prs/TensorRT-LLM/PR-8886.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[None][fix] support topk autotuner input for expert slot per group larger than 32](../sources/prs/TensorRT-LLM/PR-9087.md), [[None][feat] TRT-LLM Gen MoE optimize DeepSeek Fp8 activation kernel](../sources/prs/TensorRT-LLM/PR-9175.md), [[TRTLLM-8958][feat] and [TRTLLM-8960]: create ConfigurableMoE and support TRTLLMGenFusedMoE as backend](../sources/prs/TensorRT-LLM/PR-9486.md), [[TRTLLM-9685] [feat] Add gather fc1 kernel by cuteDSL](../sources/prs/TensorRT-LLM/PR-9618.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [[None][feat] Fused kernels (qknormrope + moe routing) and two-model MTP support for glm4moe](../sources/prs/TensorRT-LLM/PR-9852.md), [Blockscaled Ragged Contiguous Grouped Gemm for MoEs](../sources/prs/cutlass/PR-2790.md), [feat: add trtllm all-reduce (non-MoE)](../sources/prs/flashinfer/PR-1096.md), [feat: add trtllm moe_allreduce_fusion](../sources/prs/flashinfer/PR-1108.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [bugfix: Fix test and output shape of fp4 quantize](../sources/prs/flashinfer/PR-1114.md), [feat: add trtllm all-reduce fusion](../sources/prs/flashinfer/PR-1131.md), [MNNVL MoE All-to-All Support](../sources/prs/flashinfer/PR-1134.md), [feat: add finalize_moe_allreduce from trtllm](../sources/prs/flashinfer/PR-1159.md), [feat: update non-fused moe](../sources/prs/flashinfer/PR-1161.md), [feat: enable and update all-reduce fused quantization](../sources/prs/flashinfer/PR-1164.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [Patch fp8 cubin availability](../sources/prs/flashinfer/PR-1240.md), [Remove sm100+ requirment for trtllm allreduce kernels](../sources/prs/flashinfer/PR-1249.md), [Add shuffle matrix flag](../sources/prs/flashinfer/PR-1272.md), [Bug fix: guard fp8 e8m0 and e2m1 compile ](../sources/prs/flashinfer/PR-1287.md), [Remove FAST_BUILD FLAG for MOE](../sources/prs/flashinfer/PR-1291.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [feat: Add weight layout option for trtllm-gen fused moe](../sources/prs/flashinfer/PR-1297.md), [perfix: use lightweight API to query device property](../sources/prs/flashinfer/PR-1298.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [Support loading autotuned results from json for cutlass fp4 moe backends](../sources/prs/flashinfer/PR-1310.md), [Make Fp8 MoE routing_bias optional](../sources/prs/flashinfer/PR-1319.md), [refactor: Improved metainfo for trtllm-gen kernels](../sources/prs/flashinfer/PR-1328.md), [feature: add fp4 mm using trtllm backend](../sources/prs/flashinfer/PR-1355.md), [Update autotune results for the nvfp4 cutlass moe backends for v0.2.9](../sources/prs/flashinfer/PR-1361.md), [bugfix: fixed cutlass fused moe usage of FP4QuantizationSFLayout::SWIZZLED](../sources/prs/flashinfer/PR-1371.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [Fix trtllm moe launcher local_num_experts](../sources/prs/flashinfer/PR-1398.md), [Add Mxfp4 trtllm-gen moe unit tests](../sources/prs/flashinfer/PR-1399.md), [[bugfix] Fix compilation failure when compiling csrc/trtllm_moe_allreduce_fusion.cu](../sources/prs/flashinfer/PR-1410.md), [Faster weight processing (moe nvfp4)](../sources/prs/flashinfer/PR-1412.md), [Fix redundant kernels in moe](../sources/prs/flashinfer/PR-1428.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [bugfix: Verify num_experts greater or equal to local_experts + offset](../sources/prs/flashinfer/PR-1469.md), [feat: Enable multiple fused-moe backends](../sources/prs/flashinfer/PR-1472.md), [tuner: Trtllm-gen Fp4 MoE Autotunner](../sources/prs/flashinfer/PR-1475.md), [fix missing enable_pdl argument in trtllm-gen fp4 moe](../sources/prs/flashinfer/PR-1480.md), [fix: update cutedsl masked moe gemm](../sources/prs/flashinfer/PR-1488.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [fix: update masked moe gemm fp4 tensor reshape](../sources/prs/flashinfer/PR-1495.md), [Support cuda<12.8 built for trtllm_allreduce_fusion.](../sources/prs/flashinfer/PR-1508.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [bugfix: Fix compile error for undefined swizzle enum.](../sources/prs/flashinfer/PR-1530.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute](../sources/prs/flashinfer/PR-1547.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [Add mnnvl_moe_alltoallv_prepare_without_allgather](../sources/prs/flashinfer/PR-1550.md), [fix: separate out fp4 lib into sm90 and sm100 versions, add oob checking in fused moe](../sources/prs/flashinfer/PR-1565.md), [bugfix: fix cuda version guard macros](../sources/prs/flashinfer/PR-1571.md), [update trtllm-gen fp4 autotuner and routing](../sources/prs/flashinfer/PR-1573.md), [refactor: Expose calculate_tile_tokens_dim function](../sources/prs/flashinfer/PR-1581.md), [bugfix: Fix arg passing to TORCH_CHECK and TORCH_WARN macros](../sources/prs/flashinfer/PR-1582.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [test: update fused_moe test to random scale factor](../sources/prs/flashinfer/PR-1665.md), [Refactor Blackwell unit test scripts](../sources/prs/flashinfer/PR-1667.md), [test: better fp8 quantization init for fused_moe test](../sources/prs/flashinfer/PR-1674.md), [Support Kimi-K2 for TRT: templatize number of experts](../sources/prs/flashinfer/PR-1696.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [perf: Add tuning config for cutlass moe for a hardware](../sources/prs/flashinfer/PR-1716.md), [Fix DeepSeek quality for TRTLLM fused MoE routing](../sources/prs/flashinfer/PR-1723.md), [bugfix: partially fix tests/test_trtllm_gen_fused_moe.py unit test failure](../sources/prs/flashinfer/PR-1724.md), [tests: xfail moe quantization classes mxfp8_bf16 UTs on sm103 ](../sources/prs/flashinfer/PR-1754.md), [add test case for trtllm gen fused moe with kimi k2 problem sizes](../sources/prs/flashinfer/PR-1768.md), [fix: fp4 moe on sm120](../sources/prs/flashinfer/PR-1817.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [Update the routing for TRTLLMGEN to support kimi k2 and qwen](../sources/prs/flashinfer/PR-1831.md), [feat: Add FP4 TRTLLM-Gen throughput MOE batched gemms](../sources/prs/flashinfer/PR-1882.md), [Feature: Support Relu2 activation in fused MoE](../sources/prs/flashinfer/PR-1954.md), [Update trtllm-gen fused moe routing kernel and add more kernels](../sources/prs/flashinfer/PR-1955.md), [Fix: Verify scales are not None for Cutlass FP8 FusedMoE](../sources/prs/flashinfer/PR-1961.md), [Feature: Add support for L40 FusedMoE in cutlass path](../sources/prs/flashinfer/PR-1973.md), [feat: autotune tile_tokens_dim in trtllm-gen MOE](../sources/prs/flashinfer/PR-1980.md), [Bugfix: Change get() -> GetDLTensorPtr() in cutlass FusedMoE validations](../sources/prs/flashinfer/PR-1995.md), [Feature: Support non-gated activation in cutlass fused MoE nvfp4](../sources/prs/flashinfer/PR-2011.md), [[feat] Refactor trtllmgen MOE and add Bf16 trtllmgen moe](../sources/prs/flashinfer/PR-2014.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE](../sources/prs/flashinfer/PR-2025.md), [Enable renormalize(naive) routing for fp8 per-tensor](../sources/prs/flashinfer/PR-2030.md), [Fix dtype of output scales from mnnvl_moe_alltoallv_prepare_without_allgather](../sources/prs/flashinfer/PR-2048.md), [[BUG] Fix trtllm-gen fp4 moe renormalize routing](../sources/prs/flashinfer/PR-2049.md), [Add support for topkPacked input in block-level renormalize](../sources/prs/flashinfer/PR-2051.md), [Fix moe fp8 failure for sm121](../sources/prs/flashinfer/PR-2061.md), [perf: TRT-LLM MoE Block-FP8 activation optimization](../sources/prs/flashinfer/PR-2063.md), [[Test] Optimize test_trtllm_gen_fused_moe.py](../sources/prs/flashinfer/PR-2072.md), [Patch sm103 for 3xfp4 moe generation](../sources/prs/flashinfer/PR-2082.md), [refactor: update dpsk fused_moe test [1]](../sources/prs/flashinfer/PR-2088.md), [refactor: pass hopper deepgemm include directory through python](../sources/prs/flashinfer/PR-2090.md), [perf: TRT-LLM Gen finalize kernel optimization](../sources/prs/flashinfer/PR-2092.md), [refactor: update dpsk fused_moe test [2]](../sources/prs/flashinfer/PR-2097.md), [Port TRT-LLM communication kernels to flashinfer](../sources/prs/flashinfer/PR-2102.md), [enable sm103 moe dsl backend](../sources/prs/flashinfer/PR-2149.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [Add data type check for deepseek fp4 moe](../sources/prs/flashinfer/PR-2165.md), [Rename noauxtc to fused_topk_deepseek](../sources/prs/flashinfer/PR-2181.md), [Fix for moe on sm110](../sources/prs/flashinfer/PR-2190.md), [feat: unit-test and api change, w4a8 grouped-gemm fused MoE for SM90](../sources/prs/flashinfer/PR-2193.md), [feat: Support unpadded output hidden size for trtllm_fp4_block_scale_moe](../sources/prs/flashinfer/PR-2217.md), [fix: add DeepSeek routing for Bf16xBf16 and MxIntxBf16 TRT-LLM Gen MoE](../sources/prs/flashinfer/PR-2234.md), [refactor: pull trtllm-gen batch-gemm/gemm headers from artifactory; update tma descriptor shape init](../sources/prs/flashinfer/PR-2235.md), [test: Fix MNNVL tests to skip when container lacks SYS_PTRACE capability](../sources/prs/flashinfer/PR-2245.md), [feat: Support numLocalTokens=0 for moe All-to-all](../sources/prs/flashinfer/PR-2247.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [feat: expose swizzled_input_sf parameter for CUTLASS fused MOE](../sources/prs/flashinfer/PR-2330.md), [Optimize quantization function in large problem size](../sources/prs/flashinfer/PR-2343.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [feat: update trtllm-gen MoE cubins](../sources/prs/flashinfer/PR-2416.md), [bugfix: fix stub generation directory in fused_moe module](../sources/prs/flashinfer/PR-2445.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [fix: blockscale moe routine supports non-DS routing](../sources/prs/flashinfer/PR-2476.md), [fix: add support check for gemm config for cutlass moe](../sources/prs/flashinfer/PR-2495.md), [Feat: Trtllm-gen MxFP8 MoE integration](../sources/prs/flashinfer/PR-2505.md), [fix: W4A8 autotune crash in cutlass_fused_moe profiler workspace](../sources/prs/flashinfer/PR-2564.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [tests: add bias testing to nvfp4 moe](../sources/prs/flashinfer/PR-2585.md), [fix: trtllm_mxint4_block_scale_moe unit test to index output list](../sources/prs/flashinfer/PR-2627.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [benchmark: Add MXFP4/MXFP8 quantization mode support to FP4 MoE benchmark](../sources/prs/flashinfer/PR-2635.md), [[fp8_blockwise]Fix int32 overflow in TRTLLM fused MoE activation kernel](../sources/prs/flashinfer/PR-2642.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [fix: Add fused MOE and GEMM AOT modules for SM121](../sources/prs/flashinfer/PR-2654.md), [feat: Add support for TRTLLM MXFP8 non-gated MoE with ReLU2](../sources/prs/flashinfer/PR-2707.md), [fix: Add SM120 (RTX Blackwell desktop) support for NVFP4 MoE kernels](../sources/prs/flashinfer/PR-2725.md), [Support in-place update for `trtllm_fp8_block_scale_moe`](../sources/prs/flashinfer/PR-2739.md), [misc: Update gemm/batched gemm cubins from trtllm-gen, gemm header refactor](../sources/prs/flashinfer/PR-2740.md), [[feat] Add 2048 experts and 32 Top K ](../sources/prs/flashinfer/PR-2744.md), [Upgrade cutlass 4.2.1 -> 4.4.2](../sources/prs/flashinfer/PR-2798.md), [CuteDSL MoE fix redundant output buffer zeroing](../sources/prs/flashinfer/PR-2811.md), [fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE](../sources/prs/flashinfer/PR-2821.md), [fix: int32 overflow in `trtllm_fp4_block_scale_moe` causing "Unsupported hidden state scale shape" for EP32+ configs](../sources/prs/flashinfer/PR-2853.md), [Add support for Relu2 in BF16 fused MoE](../sources/prs/flashinfer/PR-2864.md), [fix: add cute dsl moe utils to AOT](../sources/prs/flashinfer/PR-2872.md), [Fix silent bug with FP8 per tensor non-gated MoE](../sources/prs/flashinfer/PR-2882.md), [fix: snap weight_scale_vec_size to handle block_scale_interleave padding for SM120](../sources/prs/flashinfer/PR-2898.md), [[NVIDIA] fix(jit): enable GDC for CUTLASS fused MoE PDL — prevent random crashes on SM12x](../sources/prs/flashinfer/PR-2913.md), [fix: Fix autotuner crash on meta-device tensor in trtllm_fp4_block_scale_routed_moe](../sources/prs/flashinfer/PR-2916.md), [feat: add Relu2 (squared ReLU) activation support in CUTLASS MoE backend](../sources/prs/flashinfer/PR-2926.md), [[Perf] Refactor MoE autotuning to set valid topk ids in routed MoE tuning](../sources/prs/flashinfer/PR-2942.md), [Fused moe all-reduce routed scaling factor + quant support](../sources/prs/flashinfer/PR-2966.md), [feat(comm): add MOE Finalize/Reduction patterns to unified allreduce_fusion API](../sources/prs/flashinfer/PR-2982.md), [fix: restore SM120 CUTLASS MoE tile candidate removed by #2927 (test_trtllm_cutlass_fused_moe.py)](../sources/prs/flashinfer/PR-2984.md), [perf: Optimize CUTLASS MoE helper kernels for small-batch decode workloads](../sources/prs/flashinfer/PR-3014.md), [fix: extend moe alltoall top-k specializations](../sources/prs/flashinfer/PR-3021.md), [[feat] Add routing_replay_out support to MoE kernels and Python API](../sources/prs/flashinfer/PR-3024.md), [Prevent MoE autotuner buffer overflow on large token buckets](../sources/prs/flashinfer/PR-3025.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [fused_moe: pre-filter SM89 tactics with zero occupancy on SM120 Blackwell (fix review feedback on #2764)](../sources/prs/flashinfer/PR-3032.md), [feat: Add b12x CuTe DSL fused MoE for SM120](../sources/prs/flashinfer/PR-3066.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [fix(sm12x): fix micro-kernel workspace sizing when routed_rows > num_local_experts](../sources/prs/flashinfer/PR-3191.md), [fix(cute_dsl/moe): make autotuner bucket configuration adapt to runtime input](../sources/prs/flashinfer/PR-3216.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [[Bugfix] Fix fused MoE autotuning correctness issues by filtering clusterDimZ](../sources/prs/flashinfer/PR-3227.md), [Update moe gemm](../sources/prs/flashinfer/PR-3239.md), [fix(cute_dsl/moe): unbias autotuner profiling for tile_size enumeration](../sources/prs/flashinfer/PR-3252.md), [feat(moe): add SM120 W4A16 b12x kernels](../sources/prs/flashinfer/PR-3271.md), [feat(cute_dsl/moe): deterministic balanced autotune profile inputs](../sources/prs/flashinfer/PR-3286.md), [Ep api design - Build Infra dependencies](../sources/prs/flashinfer/PR-3315.md), [[feat] Add gemma RMS AR fusion](../sources/prs/flashinfer/PR-3322.md), [feat(cute_dsl/moe): add `moe_output_memset_inplace` dense memset wrapper](../sources/prs/flashinfer/PR-3328.md), [Add support for bf16 x bf16 cutlass fused MoE](../sources/prs/sglang/PR-10275.md), [Fix cutlass moe accuracy drop caused by attention UB from DP padding mode](../sources/prs/sglang/PR-10414.md), [Support single batch overlap](../sources/prs/sglang/PR-10422.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [feat: add dsv3 fp4 cutlass moe etp ut](../sources/prs/sglang/PR-10433.md), [Update CUTLASS. Refine KernelSchedule for fp8 (grouped) gemm.](../sources/prs/sglang/PR-10491.md), [Fix bias handling in TritonMoeQuantInfo within quantization/mxfp4.py](../sources/prs/sglang/PR-10579.md), [support qwen3-next-fp8 deepep](../sources/prs/sglang/PR-10622.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [Quick Fix: fix Qwen3-VL launch failure caused by MRotaryEmbedding arg](../sources/prs/sglang/PR-10985.md), [Fix DSR1 accuracy for flashinfer_trtllm MoE with FP8 quantization](../sources/prs/sglang/PR-11081.md), [[AMD] Clean up vllm dependencies in moe_runner/triton.py](../sources/prs/sglang/PR-11349.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [Support shared experts overlap in cutlass moe](../sources/prs/sglang/PR-11611.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [[Ascend] qwen optimization](../sources/prs/sglang/PR-12078.md), [[hotfix] missing `w13_weight_fp8` and `w2_weight_fp8` in UE8M0 requantization](../sources/prs/sglang/PR-12259.md), [Replace [silu_and_mul_]scaled_fp4_group_quant by Flashinfer equivalent](../sources/prs/sglang/PR-12376.md), [Enable Flashinfer TRTLLM-GEN-MoE FP8 blockwise kernel for Qwen3-Next on Blackwell](../sources/prs/sglang/PR-12543.md), [[CPU] Fix MoE layer support for DeepSeek-OCR models](../sources/prs/sglang/PR-12555.md), [[sgl-kernel][5/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12666.md), [[Bugfix] Fix illegal memory access](../sources/prs/sglang/PR-12758.md), [[Ascend] support Kimi-K2-Thinking](../sources/prs/sglang/PR-12759.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [Apply moe_reduce_sum kernel for fused_marlin_moe](../sources/prs/sglang/PR-12888.md), [Support moe topk sigmoid kernel](../sources/prs/sglang/PR-13049.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [[NPU]Optimization of `forward_npu` for `UnquantizedFusedMoEMethod`](../sources/prs/sglang/PR-13158.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [[NVIDIA] Fix broken fp8 MoE of deepseek v3](../sources/prs/sglang/PR-13264.md), [Flashinfer TRTLLM-GEN-MoE + Qwen3](../sources/prs/sglang/PR-13489.md), [Fix EPLB + FP4 Quantization Compatibility Issue](../sources/prs/sglang/PR-13715.md), [[bugfix] fix TBO crashes when attn_tp_size > 1](../sources/prs/sglang/PR-13730.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [[NVIDIA] Enable TRTLLM BF16 MoE on Blackwell GPUs](../sources/prs/sglang/PR-13798.md), [[BugFix] fix outplace_fused_experts missing is_gated](../sources/prs/sglang/PR-13864.md), [Feat: GLM-4.6 supports shared experts fusion](../sources/prs/sglang/PR-13873.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [[kernel][moe] add moe topk fast](../sources/prs/sglang/PR-13969.md), [Support KTransformers for Qwen3-VL moe](../sources/prs/sglang/PR-13983.md), [Fix flashinfer cutlass MoE output shape for non-FP4-packed inputs](../sources/prs/sglang/PR-14028.md), [[LoRA][III] Add LoRA support for MoE layers and enable TP](../sources/prs/sglang/PR-14105.md), [Add new moe wna16 marlin gemm](../sources/prs/sglang/PR-14122.md), [Apply new moe wna16 marlin gemm](../sources/prs/sglang/PR-14125.md), [Opt moe align block size kernel](../sources/prs/sglang/PR-14133.md), [Apply new moe align block size kernel](../sources/prs/sglang/PR-14134.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[FIX] trtllm-moe-fp4-renorm for Qwen series models](../sources/prs/sglang/PR-14350.md), [[NPU] perf update with kvcache nz & w4a8 quant](../sources/prs/sglang/PR-14423.md), [Mistral Large 3 NVFP4 support](../sources/prs/sglang/PR-14485.md), [Apply back moe_sum_reduce for fused_marlin_moe](../sources/prs/sglang/PR-14829.md), [add transformers version validation for glm-4.6v moe models](../sources/prs/sglang/PR-14998.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [[sgl-kernel][1/2] Fused qk_norm_rope for GLM4.6](../sources/prs/sglang/PR-15141.md), [[NVIDIA] Fixes for NVFP4 all-gather with spec decoding](../sources/prs/sglang/PR-15280.md), [[Fix] A followup fix for TRTLLM BF16 MoE](../sources/prs/sglang/PR-15303.md), [Fix the accuracy issue when running mxfp4 dsv3 model and enable ep](../sources/prs/sglang/PR-15304.md), [Fix warp illegal instruction in kimi k2 thinking PCG](../sources/prs/sglang/PR-15306.md), [[distributed] Clean up MoE groups in destroy_model_parallel](../sources/prs/sglang/PR-15345.md), [[NPU]mindspore model support moe](../sources/prs/sglang/PR-15363.md), [Super tiny add moe_ep_rank to prometheus labels](../sources/prs/sglang/PR-15407.md), [Flashinfer MOE FP8 support for Mistral Large 3.](../sources/prs/sglang/PR-15422.md), [Optimize Bailing-MoE with FlashInfer Fused All-Reduce](../sources/prs/sglang/PR-15526.md), [MoE: Skip SiLU/GELU activation for masked experts](../sources/prs/sglang/PR-15539.md), [Update flashinfer to 0.6.1](../sources/prs/sglang/PR-15551.md), [Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-15712.md), [[Perf] Eliminate the slice op for Flashinfer `trtllm_fp4_block_scale_moe`](../sources/prs/sglang/PR-15731.md), [Fix GLM-4.7 MoE Detector complex JSON Schema type parsing](../sources/prs/sglang/PR-15753.md), [Fix: Handle empty func_name and None values in GLM MoE detectors](../sources/prs/sglang/PR-15754.md), [[Feature] JIT Fused QK norm + qk norm clean up](../sources/prs/sglang/PR-15835.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [[NPU] NZ for non-quantized MOE, Qwen3 MOE double memory consumption fix](../sources/prs/sglang/PR-15904.md), [ Add tuned triton==3.5.1 h200 tp2, tp4 for qwen 3 next](../sources/prs/sglang/PR-15948.md), [enhance accuracy for model kimi-vl-instruct-a3b](../sources/prs/sglang/PR-16076.md), [fix layer intermediate size](../sources/prs/sglang/PR-16084.md), [[NemotronH] Add latent MoE support](../sources/prs/sglang/PR-16227.md), [Fix FP8 MoE NaN with DeepGEMM on Blackwell](../sources/prs/sglang/PR-16622.md), [[Rework] Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-16723.md), [[AMD] Support redundant expert with a2a moe in gfx95x.](../sources/prs/sglang/PR-16791.md), [[Fix] `flashinfer_trtllm` `intermediate_size` assertion with Qwen3 + TP=8](../sources/prs/sglang/PR-16824.md), [Support mxint4 flashinfer_trtllm moe gemm](../sources/prs/sglang/PR-16892.md), [Inclusion of nvfp4 blockscale in EPLB Rebalance](../sources/prs/sglang/PR-17158.md), [[Fix] GLM 4.7 + NVFP4 + MTP](../sources/prs/sglang/PR-17166.md), [[GLM 4.7] Add RTX 6000 Pro aka sm120](../sources/prs/sglang/PR-17235.md), [[New Model] GLM4.7-Flash](../sources/prs/sglang/PR-17247.md), [Add mxfp8 support for online quantization, Triton dense linear, and CUTLASS MoE](../sources/prs/sglang/PR-17449.md), [Upgrade transformers==5.3.0](../sources/prs/sglang/PR-17784.md), [[Bugfix] Fix Mistral Large 3 NVFP4 TRTLLM MoE](../sources/prs/sglang/PR-18065.md), [Fix nvfp4 weight update](../sources/prs/sglang/PR-18085.md), [[Blackwell] Make mxint4 flashinfer_trtllm moe gemm set by default on blackwell](../sources/prs/sglang/PR-18136.md), [[ModelOpt] Fix broken Qwen3-235B-A22B-Instruct-2507-NVFP4 launch](../sources/prs/sglang/PR-18189.md), [Support Qwen3 MoE context parallel](../sources/prs/sglang/PR-18233.md), [[sglang-miles] True on-policy training support for FSDP2](../sources/prs/sglang/PR-18639.md), [[Perf] ~9.5x faster Blackwell MXFP4 MoE weight loading](../sources/prs/sglang/PR-18858.md), [[Sarvam] Add inference support for Sarvam MoE LLMs](../sources/prs/sglang/PR-18938.md), [[jit_kernel] Add fused_qknorm_rope JIT kernel](../sources/prs/sglang/PR-19059.md), [Adjust padding size to improve triton_kernels moe performance](../sources/prs/sglang/PR-19174.md), [Fix/nemotron mtp quantaized](../sources/prs/sglang/PR-19433.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Use TRTLLM allreduce fusion for Qwen 3.5](../sources/prs/sglang/PR-19889.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[4/n jit_kernel restruct] speed up CI tests and add benchmark workflow](../sources/prs/sglang/PR-20268.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[NVIDIA] Enable fp8 flashinfer_trtllm_routed MoE for MiniMax-M2.5](../sources/prs/sglang/PR-20394.md), [Add Mistral Small 4 (Pixtral) support](../sources/prs/sglang/PR-20708.md), [Use FlashInfer tinygemm for GPT-OSS MoE router on SM90+](../sources/prs/sglang/PR-20755.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[refactor] Clean up duplicate flashinfer trtllm moe code](../sources/prs/sglang/PR-21233.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[NVIDIA] Enable FP4 flashinfer trtllm routed moe](../sources/prs/sglang/PR-21240.md), [P2P Weight Update features for miles ](../sources/prs/sglang/PR-21278.md), [[RL] Support mxfp8 DeepSeek V3](../sources/prs/sglang/PR-21280.md), [[Kernel] Support FlashInfer TRTLLM-Gen fused MoE for non-gated FP4 & FP8 (Nemotron)](../sources/prs/sglang/PR-21321.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Add dedicated FlashInferCuteDslMoE layer for standard-path FP4 MoE](../sources/prs/sglang/PR-21339.md), [[jit_kernel] Optimize fused_qknorm_rope: deduplicate sincosf for interleave RoPE ](../sources/prs/sglang/PR-21654.md), [[AMD] Use tgemm.mm for MoEGate router gemm in deepseek_v2.py](../sources/prs/sglang/PR-21657.md), [Harden FlashInfer FP4 imports in standard dispatcher](../sources/prs/sglang/PR-21776.md), [[Fix] Fall back to triton MOE for GPT-OSS on Blackwell with driver >= 595](../sources/prs/sglang/PR-21780.md), [Remove redundant test_moe_eval_accuracy_large](../sources/prs/sglang/PR-21787.md), [Tiny fix trtllm_fp8_per_tensor_scale_moe_wrapper router_logits dtype](../sources/prs/sglang/PR-22006.md), [[RL] Refactor NVFP4 shuffling/swizzling to in-place replacement](../sources/prs/sglang/PR-22204.md), [[Reland] DeepSeek-R1-0528-w4a8: DeepEP Low Latency Dispatch Adopts FP8 Communication](../sources/prs/sglang/PR-22316.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [[Lora] Lora kimi support](../sources/prs/sglang/PR-22381.md), [feat: Support flashinfer_cutedsl MoE runner with flashinfer alltoall backend](../sources/prs/sglang/PR-22669.md), [[Step3p5] Optimize allreduce in MoE layers ](../sources/prs/sglang/PR-22773.md), [Dual MoE CUDA graph capture for lora/nolora batches](../sources/prs/sglang/PR-22809.md), [[Refactor] Refactor DeepEP dispatcher](../sources/prs/sglang/PR-22822.md), [[FlashInfer v0.6.11] [RL] Support FlashInfer per-token NVFP4 MoE](../sources/prs/sglang/PR-22918.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [[MoE] Unify DeepEPMoE+MoriEPMoE through AITER MoeRunner pre/post-permute](../sources/prs/sglang/PR-23760.md), [[feat] Init true on policy with qwen_dense](../sources/prs/sglang/PR-23961.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [Fix performance regression on Deepseek V3 on `moe-runner-backend=triton` on SM90](../sources/prs/sglang/PR-24562.md), [[Codex] Opt Mistral Large performace ](../sources/prs/sglang/PR-24611.md), [Add FlashInfer SM90 cutlass MXFP4 MoE backend (W4A16) for GPT-OSS + DeepSeek-V4](../sources/prs/sglang/PR-24816.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [Fix EPLB mapping for TopK paths](../sources/prs/sglang/PR-25285.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[AMD] test(sgl-kernel): seed RNG on ROCm in test_moe_topk_sigmoid to fix tie-break flake](../sources/prs/sglang/PR-25356.md), [Update logging for inplace setting in MoE layer](../sources/prs/sglang/PR-25499.md), [[misc] Throw error when single batch overlap is enabled on Hopper ](../sources/prs/sglang/PR-25509.md), [Fix logging for inplace setting in the flashInfer-trtllm backend](../sources/prs/sglang/PR-25522.md), [[Bug Fix] Align glm4_moe_nextn NPU MTP loading with qwen3 MTP](../sources/prs/sglang/PR-25524.md), [[MoE Refactor] Migrate flashinfer_cutedsl + DeepEP to MoeRunner](../sources/prs/sglang/PR-25525.md), [Use DeepGEMM BF16 for unquantized DeepEP LL MoE](../sources/prs/sglang/PR-25540.md), [Add DeepSeekV4 fused MoE Triton autotune support](../sources/prs/sglang/PR-25569.md), [[Benchmark] Add SGLANG_SIMULATE_UNIFORM_EXPERTS for balanced expert routing with dummy weights](../sources/prs/sglang/PR-25571.md), [[SP] Fix runtime_max_tokens_per_rank for sequence parallelism](../sources/prs/sglang/PR-25685.md), [Add no_combine support to cutlass_moe_fp4](../sources/prs/sglang/PR-25688.md), [[Refactor] Pass PP start_layer via model constructor instead of forward_batch.token_to_kv_pool](../sources/prs/sglang/PR-25825.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [Feature DeepSeek V3/R1 INT8 Quantization (block-wise)](../sources/prs/sglang/PR-3730.md), [[Feature] DeepSeek V3/R1 INT8 Quantization (channel-wise) ](../sources/prs/sglang/PR-3888.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [[Feature] Integrate DeepEP into SGLang](../sources/prs/sglang/PR-4232.md), [Add deepseek style fused moe group gate selection kernel](../sources/prs/sglang/PR-4530.md), [Optimize Permute Kernel in DeepEP](../sources/prs/sglang/PR-4643.md), [Fix loading KV quantization scale; Enable modelopt kv cache](../sources/prs/sglang/PR-4686.md), [[Model] Adding Qwen3 and Qwen3MoE](../sources/prs/sglang/PR-4693.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [[Feature] Support DeepEP Low Latency](../sources/prs/sglang/PR-4767.md), [Support (1 <= dp < tp) in the dp attention in DeepEP](../sources/prs/sglang/PR-4770.md), [Introduce moe_dense_tp_size to fix dense layer errors in DeepSeek V3 + 4x8xH100](../sources/prs/sglang/PR-4836.md), [Add DeepSeek V3/R1 shared experts fusion](../sources/prs/sglang/PR-4918.md), [[Fix] DeepEP Compatibility with Low Latency](../sources/prs/sglang/PR-5068.md), [reduce moe_align_block_size_kernel small batch mode overhead](../sources/prs/sglang/PR-5086.md), [Add optimized native kernels in sgl-kernel](../sources/prs/sglang/PR-5150.md), [[1/2] Add FP8 Blockscale MoE CUTLASS kernel for Blackwell](../sources/prs/sglang/PR-5281.md), [Fix DeepGEMM masked cannot be run on groups not being multiple or 4](../sources/prs/sglang/PR-5340.md), [apply fused moe gate in ds v3/r1](../sources/prs/sglang/PR-5371.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [ DeepEP normal support deepgemm-contiguous](../sources/prs/sglang/PR-5626.md), [[2/2] Add python wrapper for CUTLASS FP8 Blockscale MoE Kernel. ](../sources/prs/sglang/PR-5694.md), [[qwen3] support qwen3 ep moe](../sources/prs/sglang/PR-5917.md), [Support tuning moe for llama 4 model](../sources/prs/sglang/PR-6042.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [feat: add dp attention support for Qwen 2/3 MoE models, fixes #6088](../sources/prs/sglang/PR-6121.md), [Reduce MoE memory usage](../sources/prs/sglang/PR-6147.md), [enable auto-round quantization model](../sources/prs/sglang/PR-6226.md), [fix: enable multi-GPU Triton fused MoE tuning](../sources/prs/sglang/PR-6295.md), [reduce torch.zeros overhead in moe align block size kernel](../sources/prs/sglang/PR-6369.md), [Add fp8 fused_experts kernel for CPU in sgl-kernel and add UT](../sources/prs/sglang/PR-6404.md), [Fix topk inference performance reduce](../sources/prs/sglang/PR-6474.md), [qwen3moe support two batch overlap](../sources/prs/sglang/PR-6598.md), [Refine pre_reorder_triton_kernel slightly to improve performance](../sources/prs/sglang/PR-6627.md), [[CPU] [BF16] Call fused_experts_cpu, weight_packed_linear and bmm_cpu kernel in DeepSeek model](../sources/prs/sglang/PR-6641.md), [Fix DeepEP error in Qwen 3 MoE models](../sources/prs/sglang/PR-6673.md), [[EP] Add cuda kernel for moe_ep_pre_reorder](../sources/prs/sglang/PR-6699.md), [Fix PP for Qwen3 MoE](../sources/prs/sglang/PR-6709.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [[CPU] add optimizations for INT8 and FP8 DeepSeek](../sources/prs/sglang/PR-6769.md), [[CPU] support the case where num_attention_heads or intermediate_size is not divisible by the TP size](../sources/prs/sglang/PR-6771.md), [Support token-level quantization for EP MoE](../sources/prs/sglang/PR-6782.md), [feat: integrate deepgemm into EPMoE](../sources/prs/sglang/PR-6821.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [[EP] Add cuda kernel for moe_ep_post_reorder](../sources/prs/sglang/PR-6837.md), [[DeepseekR1-FP4] Add Support for nvidia/DeepSeekR1-FP4 model](../sources/prs/sglang/PR-6853.md), [fix ep_moe_reorder kernel bugs](../sources/prs/sglang/PR-6858.md), [Add a CUDA kernel for fusing mapping and weighted sum for MoE.](../sources/prs/sglang/PR-6916.md), [[sgl-kernel] Add cuda kernel for moe_ep_silu_and_mul](../sources/prs/sglang/PR-6919.md), [chore: upgrade flashinfer v0.2.6.post1 jit](../sources/prs/sglang/PR-6958.md), [Fuse routed scaling factor in deepseek](../sources/prs/sglang/PR-6970.md), [Update default settings for blackwell](../sources/prs/sglang/PR-7023.md), [Fix positional argument](../sources/prs/sglang/PR-7093.md), [fix amd EP MoE FP8 issue](../sources/prs/sglang/PR-7125.md), [Enable ModelOpt Llama4 fp8 checkpoint deployment in SGLang](../sources/prs/sglang/PR-7129.md), [[amd] Opt dsv3 moe](../sources/prs/sglang/PR-7160.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Fix error when disabling new DeepGEMM](../sources/prs/sglang/PR-7198.md), [[fix] fix DeepGEMM blackwell input quant & ut & fix style and log](../sources/prs/sglang/PR-7247.md), [[AMD] add aiter fused moe in DeepEP path](../sources/prs/sglang/PR-7268.md), [Add CUTLASS FP8 Blockscale MoE kernel for Hopper architecture](../sources/prs/sglang/PR-7278.md), [Let EP prefill support new DeepGEMM](../sources/prs/sglang/PR-7310.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Fix MTP with Deepseek R1 Fp4](../sources/prs/sglang/PR-7376.md), [Fix torch compile run](../sources/prs/sglang/PR-7391.md), [[AMD][Quantization] Add `int4fp8_moe` online quantization on ROCm](../sources/prs/sglang/PR-7392.md), [Fuse sorted_token_ids padding to moe_align_block_size kernel](../sources/prs/sglang/PR-7437.md), [fix: fix apply_shuffle_mul_sum](../sources/prs/sglang/PR-7444.md), [Add Tencent HunYuanMoEV1 model support](../sources/prs/sglang/PR-7549.md), [[Feature] Layer-wise Prefill](../sources/prs/sglang/PR-7634.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [Integrate triton moe kernel](../sources/prs/sglang/PR-7689.md), [feat: support DeepSeek-R1-W4AFP8 model with ep-moe mode](../sources/prs/sglang/PR-7762.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [[kernel] opt moe align block kernel by block/warp scan algorithm](../sources/prs/sglang/PR-7884.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [[1/N]Support DeepSeek-R1 w4a8 normal deepep](../sources/prs/sglang/PR-8247.md), [Support triton kernels v3.4.0 for fused_moe](../sources/prs/sglang/PR-8258.md), [[2/N]Support DeepSeek-R1 w4a8 low latency deepep](../sources/prs/sglang/PR-8464.md), [Update cutlass_moe.py](../sources/prs/sglang/PR-8535.md), [Update cutlass_moe.py](../sources/prs/sglang/PR-8545.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [feat: support cutlass_moe_fp8 kernel for fusedmoe in sm90](../sources/prs/sglang/PR-8678.md), [fuse allreduce and residual_rmsnorm](../sources/prs/sglang/PR-8731.md), [[Perf] Auto enable best flashinfer mxfp4 kernel in b200](../sources/prs/sglang/PR-8898.md), [[NVIDIA] Fix missing `get_col_major_tma_aligned_tensor` for Blackwell deepgemm in EpMoE](../sources/prs/sglang/PR-8955.md), [optimize: reduce shulffle and quantization overhead in cutlass_moe sm90](../sources/prs/sglang/PR-8962.md), [Faster weight processing (trtllm-gen moe nvfp4)](../sources/prs/sglang/PR-9162.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [[fix] Fix mxfp4 triton MoE tp bug](../sources/prs/sglang/PR-9473.md), [Optimize moe_sum_reduce_kernel](../sources/prs/sglang/PR-9477.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [Single Batch Overlap for MoE Models](../sources/prs/sglang/PR-9660.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [Make sm100 fp8 kernels available on sm103](../sources/prs/sglang/PR-9789.md), [[Model] Support Meituan LongCat-Flash && LongCat-Flash-MTP](../sources/prs/sglang/PR-9824.md), [[ROCm][MoE] moe tuning support for rocm](../sources/prs/vllm/PR-12049.md), [[Kernel] add triton fused moe kernel for gptq/awq](../sources/prs/vllm/PR-12185.md), [[Hardware][Gaudi][Feature] Enable Dynamic MoE for Mixtral](../sources/prs/vllm/PR-12303.md), [[Misc][MoE] add Deepseek-V3 moe tuning support](../sources/prs/vllm/PR-12558.md), [[Kernel] port sgl moe_align_block_size kernels](../sources/prs/vllm/PR-12574.md), [Expert Parallelism (EP) Support for DeepSeek Models](../sources/prs/vllm/PR-12583.md), [Apply torch.compile to fused_moe/grouped_topk](../sources/prs/vllm/PR-12637.md), [[Misc] Update w2 scale loading for GPTQMarlinMoE](../sources/prs/vllm/PR-12757.md), [Optimize moe_align_block_size for deepseek_v3](../sources/prs/vllm/PR-12850.md), [[Model] Deepseek GGUF support ](../sources/prs/vllm/PR-13167.md), [[Quant][Perf] Use moe_wna16 kernel by default for MoEs with many experts](../sources/prs/vllm/PR-13236.md), [[Kernel] moe wna16 cuda kernel](../sources/prs/vllm/PR-13321.md), [[ROCm][MoE] mi300 mixtral8x7B perf for specific BS](../sources/prs/vllm/PR-13577.md), [[Kernel] Optimize moe intermediate_cache usage](../sources/prs/vllm/PR-13625.md), [[BugFix] Illegal memory access for MoE On H20](../sources/prs/vllm/PR-13693.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [Fix CompressedTensorsWNA16MoE with grouped scales](../sources/prs/vllm/PR-13769.md), [Fix precommit fail in fused_moe intermediate_cache2 chunking](../sources/prs/vllm/PR-13772.md), [[Bugfix][Quantization] Fix FP8 + EP](../sources/prs/vllm/PR-13784.md), [[V1] EP/TP MoE + DP Attention](../sources/prs/vllm/PR-13931.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [[Misc] Print FusedMoE detail info](../sources/prs/vllm/PR-13974.md), [[core] moe fp8 block quant tuning support](../sources/prs/vllm/PR-14068.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[Misc] Add Qwen2MoeForCausalLM moe tuning support ](../sources/prs/vllm/PR-14276.md), [[Kernel] moe wna16 marlin kernel](../sources/prs/vllm/PR-14447.md), [[ROCm][Kernel] MoE weights padding](../sources/prs/vllm/PR-14454.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[Kernel] GGUF MoE kernel](../sources/prs/vllm/PR-14613.md), [[Bugfix][IPEX] Add `VLLM_CPU_MOE_PREPACK` to allow disabling MoE prepack when CPU does not support it](../sources/prs/vllm/PR-14681.md), [[FEAT][ROCm] Integrate Fused MoE Kernels from AITER](../sources/prs/vllm/PR-14967.md), [[Model] Add Qwen3 and Qwen3MoE](../sources/prs/vllm/PR-15289.md), [[Kernel] Fix conflicting macro names for gguf kernels](../sources/prs/vllm/PR-15456.md), [Use Cache Hinting for fused_moe kernel](../sources/prs/vllm/PR-15511.md), [[moe][quant] add weight name case for offset](../sources/prs/vllm/PR-15515.md), [[Quantization] Fp8 Channelwise Dynamic Per Token GroupedGEMM](../sources/prs/vllm/PR-15587.md), [[V1] TPU - Fix fused MOE](../sources/prs/vllm/PR-15834.md), [[Hardware][Gaudi][BugFix] fix arguments of hpu fused moe](../sources/prs/vllm/PR-15945.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[Kernel] Use moe_wna16 kernel for compressed tensors wna16 moe models](../sources/prs/vllm/PR-16038.md), [[Kernel][Bugfix] Re-fuse triton moe weight application](../sources/prs/vllm/PR-16071.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Bug] [ROCm] Fix Llama 4 Enablement Bug on ROCm: V0 ROCmFlashAttentionImpl and Triton Fused MoE bugs](../sources/prs/vllm/PR-16198.md), [[Model] use AutoWeightsLoader for phimoe,qwen2_moe,qwen3_moe](../sources/prs/vllm/PR-16203.md), [[Hardware][AMD] Improve OAM device ID + llama4 Maverick MOE tuning](../sources/prs/vllm/PR-16263.md), [[Hardware/NVIDIA/Kernel] [Functional Enablement] [1/N] Enable nvidia/DeepSeek-R1-FP4 Model](../sources/prs/vllm/PR-16362.md), [[Kernel] Support W8A8 channel-wise weights and per-token activations in triton fused_moe_kernel](../sources/prs/vllm/PR-16366.md), [Enable PTPC FP8 for CompressedTensorsW8A8Fp8MoEMethod (triton fused_moe)](../sources/prs/vllm/PR-16537.md), [[ROCM] enable aiter fused moe kernel for llama4 bf16 checkpoints](../sources/prs/vllm/PR-16674.md), [[ROCm] Add aiter tkw1 kernel for Llama4 fp8](../sources/prs/vllm/PR-16727.md), [Support W8A8 INT8 MoE for compressed-tensors](../sources/prs/vllm/PR-16745.md), [[FEAT] [ROCm]: AITER Fused MOE V1 Support](../sources/prs/vllm/PR-16752.md), [[misc] ignore marlin_moe_wna16 local gen codes](../sources/prs/vllm/PR-16760.md), [[Kernel] GGUF MoeVec kernel](../sources/prs/vllm/PR-16780.md), [[BugFix] Accuracy fix for llama4 int4 - improperly casted scales](../sources/prs/vllm/PR-16801.md), [[Kernel] some optimizations for dense marlin and moe marlin](../sources/prs/vllm/PR-16850.md), [[Bugfix] Fix moe weight losing all extra attrs after `process_weights_after_loading`.](../sources/prs/vllm/PR-16854.md), [[Kernel] Add expert_map support to Cutlass FP8 MOE](../sources/prs/vllm/PR-16861.md), [Update Qwen1.5-MoE-W4A16-compressed-tensors.yaml](../sources/prs/vllm/PR-16946.md), [Fix `numel()` downcast in vllm/csrc/moe/moe_align_sum_kernels.cu +2](../sources/prs/vllm/PR-17082.md), [[FEAT] [ROCm]: Add AITER CK 2 Stages MoE support](../sources/prs/vllm/PR-17110.md), [[FEAT][ROCm]: Support AITER MLA on V1 Engine](../sources/prs/vllm/PR-17523.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [[BugFix][AMD] Compatible patch for AITER lib after 04/20](../sources/prs/vllm/PR-17912.md), [Fix Broken macro for cutlass moe](../sources/prs/vllm/PR-18049.md), [[Model]: Fused MoE for nomic-embed-text-v2-moe](../sources/prs/vllm/PR-18321.md), [[Feature] Expert Parallelism Load Balancer (EPLB)](../sources/prs/vllm/PR-18343.md), [[Bug] Fix moe_sum signature](../sources/prs/vllm/PR-18440.md), [[V1] Support `LLM.apply_model`](../sources/prs/vllm/PR-18465.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Kernel] Enable fp8 support for pplx and BatchedTritonExperts.](../sources/prs/vllm/PR-18864.md), [[ROCm] [AITER] [Bugfix] Patch for AITER commit `648764942e552a8bb5fe16026703716a81f05374`](../sources/prs/vllm/PR-18990.md), [[Hardware][NVIDIA] FP4 MoE kernel optimization](../sources/prs/vllm/PR-19110.md), [[Kernels] Add activation chunking logic to FusedMoEModularKernel](../sources/prs/vllm/PR-19168.md), [[Kernel] Apply torch.Tag.needs_fixed_stride_order only for torch==2.6.0](../sources/prs/vllm/PR-19346.md), [[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization](../sources/prs/vllm/PR-19500.md), [Only build CUTLASS MoE kernels on Hopper](../sources/prs/vllm/PR-19648.md), [[Kernels] Use empty for modular MoE workspaces](../sources/prs/vllm/PR-19667.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [[Feature] Integrate new deepgemm](../sources/prs/vllm/PR-19820.md), [[Quantization] Add compressed-tensors NVFP4 MoE Support](../sources/prs/vllm/PR-19990.md), [Enable V1 for Hybrid SSM/Attention Models](../sources/prs/vllm/PR-20016.md), [[Bugfix] Build moe_data for both sm100 and sm90](../sources/prs/vllm/PR-20086.md), [ [Feature] Integrate SM100 DeepGEMM support](../sources/prs/vllm/PR-20087.md), [Add ModelOpt Qwen3 nvfp4 support](../sources/prs/vllm/PR-20101.md), [[Bugfix] Mark 'hidden_states' as mutable in moe_forward registration.](../sources/prs/vllm/PR-20152.md), [[Bugfix] Fix topk_ids indices_type for CUTLASS w8a8 FP8 MoE](../sources/prs/vllm/PR-20166.md), [[Bugfix] Fix Maverick correctness by filling zero to cache space in cutlass_moe](../sources/prs/vllm/PR-20167.md), [[V1] [ROCm] Enable EP with AITER Fused MoE](../sources/prs/vllm/PR-20270.md), [[Kernel][Bugfix] Fixup some warnings in nvfp4_blockwise_moe when CUDA < 12.8](../sources/prs/vllm/PR-20324.md), [[Misc] DP : Add ExpertTokensMetadata](../sources/prs/vllm/PR-20332.md), [[feat]: add SM100 support for cutlass FP8 groupGEMM](../sources/prs/vllm/PR-20447.md), [Support Llama 4 for cutlass_moe_fp4](../sources/prs/vllm/PR-20453.md), [Support Llama 4 for fused_marlin_moe](../sources/prs/vllm/PR-20457.md), [[Perf] Reuse workspace for FP8+FP4 Marlin MoE](../sources/prs/vllm/PR-20500.md), [[Bugfix] Fix missing per_act_token parameter in compressed_tensors_moe](../sources/prs/vllm/PR-20509.md), [[feat] enable SM100 CUTLASS block scaled group gemm for smaller batch sizes](../sources/prs/vllm/PR-20640.md), [GLM-4.5 Model Support](../sources/prs/vllm/PR-20736.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [[fix]: disable cutlass block scaled group gemm for EP](../sources/prs/vllm/PR-20781.md), [[Feature][EPLB] Add eplb support for Qwen3](../sources/prs/vllm/PR-20815.md), [[Bugfix] Fix a couple PPLX+CUTLASS MoE bugs](../sources/prs/vllm/PR-20825.md), [[Bug] Fix DeepGemm for EP low latency case](../sources/prs/vllm/PR-20833.md), [[Perf] Use Triton instead of Torch for DeepGEMM Per Token Group Quant](../sources/prs/vllm/PR-20841.md), [[Kernel] DeepGemm MoE : Integrate triton permute / unpermute kernels ](../sources/prs/vllm/PR-20903.md), [[Perf] Add swap_ab to SM90 FP8 non-block CUTLASS moe grouped gemm](../sources/prs/vllm/PR-20911.md), [[Misc] Qwen MoE model supports LoRA](../sources/prs/vllm/PR-20932.md), [Support mnnvl all2allv from Flashinfer](../sources/prs/vllm/PR-21003.md), [[Bugfix] Allocate less memory in non-batched CUTLASS MoE](../sources/prs/vllm/PR-21121.md), [[Feature][OCP MX] Support mxfp6 and mixed mxfp6-mxfp4](../sources/prs/vllm/PR-21166.md), [[Feature][Kernel]FusedMoE LoRA](../sources/prs/vllm/PR-21229.md), [[v1] - Mamba1 Attention Metadata](../sources/prs/vllm/PR-21249.md), [Support CUTLASS NVFP4 (w4a4) for Blackwell Geforce GPUs (SM120)](../sources/prs/vllm/PR-21309.md), [Support Tensorrt-LLM MoE fp4 for low-latency](../sources/prs/vllm/PR-21331.md), [[TPU][Bugfix] fix moe layer](../sources/prs/vllm/PR-21340.md), [[Quantization] Enable BNB support for more MoE models](../sources/prs/vllm/PR-21370.md), [Update flashinfer CUTLASS NVFP4 MoE Kernel to use per expert global scaling factor](../sources/prs/vllm/PR-21408.md), [[NVIDIA] Explicitly disable shuffled weights for flashinfer blockscale moe fp8 kernels](../sources/prs/vllm/PR-21411.md), [[Bug] Fix Compressed Tensor NVFP4 `cutlass_fp4_group_mm` illegal memory access](../sources/prs/vllm/PR-21465.md), [[MoE] More balanced expert sharding](../sources/prs/vllm/PR-21497.md), [[NVIDIA] Fix Llama4 Scout FP4 functionality issues](../sources/prs/vllm/PR-21499.md), [Enable 4bit bnb prequant MOE](../sources/prs/vllm/PR-21548.md), [[Feature] Add Flashinfer MoE Support for Compressed Tensor NVFP4](../sources/prs/vllm/PR-21639.md), [[xpu]support moe models on XPU platform](../sources/prs/vllm/PR-21643.md), [support `torch.compile` for bailing moe](../sources/prs/vllm/PR-21664.md), [feat: Add Support GPTQ Quantization MOE on ROCM vllm serve](../sources/prs/vllm/PR-21733.md), [[Qwen3] Enable dual-chunk-attention support for Qwen3 models.](../sources/prs/vllm/PR-21924.md), [Fix Flashinfer CUTLASS MOE Allgather](../sources/prs/vllm/PR-21963.md), [[BUGFIX] KeyError 'layers.14.mlp.gate.g_idx' for Qwen3-MoE with GPTQ on ROCm](../sources/prs/vllm/PR-22017.md), [[EPLB] Support ernie4.5-moe](../sources/prs/vllm/PR-22100.md), [[Bugfix] Fix MoE BNB version](../sources/prs/vllm/PR-22260.md), [[gpt-oss] flashinfer mxfp4](../sources/prs/vllm/PR-22339.md), [[gpt-oss] triton kernel mxfp4](../sources/prs/vllm/PR-22421.md), [Fix Llama4 FlashInfer FP4 MoE issues](../sources/prs/vllm/PR-22511.md), [[Model] Add Ernie4.5 VL Model Support](../sources/prs/vllm/PR-22514.md), [Fix torch version check for SM100 mxfp4 ](../sources/prs/vllm/PR-22535.md), [[Quantization] Expand compressed-tensors MoE matching logic to support NFP4 + FP8 MoEs](../sources/prs/vllm/PR-22674.md), [Fix GGUF loader for Qwen3 MoE.](../sources/prs/vllm/PR-22785.md), [[FIXBUG] Add return_success parameter to moe_wna16_weight_loader function](../sources/prs/vllm/PR-22797.md), [[Model] Modify the gate implementation of glm4_moe](../sources/prs/vllm/PR-22832.md), [[XPU] support data parallel for MoE models on XPU](../sources/prs/vllm/PR-22887.md), [[Bugfix] Fix DeepSeek MTP](../sources/prs/vllm/PR-22934.md), [[Fix] enable swap_ab for pplx problem size computation](../sources/prs/vllm/PR-22991.md), [Use Blackwell FlashInfer MXFP4 MoE by default if available ](../sources/prs/vllm/PR-23008.md), [[Bugfix] fix qwen3 moe fp8 accuracy issue](../sources/prs/vllm/PR-23031.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [Add routed_scaling_factor to MoE grouped topk](../sources/prs/vllm/PR-23123.md), [[Bugfix] Fix accuracy issue when using flashinfer cutlass moe, TP=1 and modelopt.](../sources/prs/vllm/PR-23125.md), [[CPU] add cpu fused moe pytorch native implementation](../sources/prs/vllm/PR-23146.md), [[Perf] Small optimizations for silu_mul_fp8_quant_deep_gemm](../sources/prs/vllm/PR-23265.md), [[Kernels] Overlap shared experts with send/recv](../sources/prs/vllm/PR-23273.md), [[Kernel] Add fused grouped_topk kernel for MoE](../sources/prs/vllm/PR-23274.md), [[Bugfix] Fix Qwen3 MoE GPTQ inference](../sources/prs/vllm/PR-23490.md), [DP/EP Support for gpt-oss with deepep-ht comm kernel on SM100](../sources/prs/vllm/PR-23608.md), [[Feature] Add Hopper DeepGEMM E8M0 for DeepSeekV3.1 scale_fmt](../sources/prs/vllm/PR-23666.md), [[Core/DBO][1/N] Add Dual-Batch Overlap mechanism to VLLM](../sources/prs/vllm/PR-23693.md), [[Kernel][B200] mxfp4 fused cutlass moe](../sources/prs/vllm/PR-23696.md), [[Bugfix][Misc] Fix silu_and_mul_nvfp4_quant issue and extract common utils for nvfp4 kernel source files](../sources/prs/vllm/PR-23727.md), [[Feat][EPLB] A novel static EPLB placement strategy for MoE models.](../sources/prs/vllm/PR-23745.md), [[fix]: add Arm 4bit fused moe support](../sources/prs/vllm/PR-23809.md), [[Model][gpt-oss] Support DP+EP for GPT-OSS with FlashInfer trtllm-gen MoE](../sources/prs/vllm/PR-23819.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[BUGFIX] GPTQ quantization compatibility for Qwen3 MOE models (AutoGPTQ and AutoRound-GPTQ)](../sources/prs/vllm/PR-23994.md), [[PERF] Allreduce fusion. Support torch native matching. Tuning of the thresholds](../sources/prs/vllm/PR-24248.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [[Model] Support Qwen3-VL Model Series](../sources/prs/vllm/PR-24727.md), [feat: BF16 FlashInfer Fused Cutlass MOE for Hopper and Blackwell Expert Parallel](../sources/prs/vllm/PR-25503.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Bugfix] Allow skipping MoE in NVFP4 (fix for MTP)](../sources/prs/vllm/PR-25987.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [Fix undefined symbol: cutlass_moe_mm_sm100](../sources/prs/vllm/PR-26098.md), [[ModelOpt] Load w13/w2_input_scale for all experts, nvfp4](../sources/prs/vllm/PR-26135.md), [[Bug] Fix Shape Validation for Fallback while Enabling E8M0 for DeepGEMM](../sources/prs/vllm/PR-26322.md), [[Performance] Dual stream execution of "shared_experts" and "selected_experts" inside FusedMoE](../sources/prs/vllm/PR-26440.md), [[ROCM] MoE fp4 CK kernel](../sources/prs/vllm/PR-26545.md), [support flashinfer_fp4 moe for 5090 gpu](../sources/prs/vllm/PR-26669.md), [[NVIDIA] [Perf] Update to leverage flashinfer trtllm FP4 MOE throughput kernel](../sources/prs/vllm/PR-26714.md), [[Bugfix] Fix gpt-oss w4a8 DP/EP on B200](../sources/prs/vllm/PR-26729.md), [[Kernels] Enable FlashInfer FP8 Blockscale on SM90 (for TEP DSR1)](../sources/prs/vllm/PR-27134.md), [[ROCM] Enable CompressedTensorsWNA16](../sources/prs/vllm/PR-27187.md), [Flashinfer_CUTLASS_MOE fuses quantization for TP](../sources/prs/vllm/PR-27223.md), [Bugfix: Cutlass FP8 FusedMoE bad scaling factors](../sources/prs/vllm/PR-27255.md), [Feature: Support Relu2 in FusedMoE fp8 cutlass path](../sources/prs/vllm/PR-27261.md), [[Performance] Support FP8 flashinfer TRTLLM MOE on Qwen3 and Qwen-3next](../sources/prs/vllm/PR-27492.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Performance][B200] Fix deepgemm prologue](../sources/prs/vllm/PR-27897.md), [[Model] Consolidate Deepseek-MoE implementation with DeepSeek-v2](../sources/prs/vllm/PR-28101.md), [[Perf][DeepSeek] Add sigmoid+bias fusion to fused_grouped_topk from TRTLLM](../sources/prs/vllm/PR-28124.md), [[flashinfer] fix FI all2all with FI cutlass moe](../sources/prs/vllm/PR-28166.md), [[Feature] Support recording expert indices for rollout router replay](../sources/prs/vllm/PR-28284.md), [[Performance][B200] silu_mul_quant: pack scales in int32](../sources/prs/vllm/PR-28358.md), [[Bugfix][EPLB] Disabled shared expert overlap when EPLB is enabled](../sources/prs/vllm/PR-28377.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [[Model] Add support for openPangu moe model](../sources/prs/vllm/PR-28775.md), [[Bugfix] Fix GPT-OSS AR+NORM fusion](../sources/prs/vllm/PR-28841.md), [[Bugfix] Make compressed-tensors MoEs respect ignored layers](../sources/prs/vllm/PR-28878.md), [Add TRTLLM MoE NVFP4 kernel to CompressedTensorsW4A4MoeMethod](../sources/prs/vllm/PR-28892.md), [[NVIDIA] Guard SM100 CUTLASS MoE macro to SM100 builds v2](../sources/prs/vllm/PR-28938.md), [[Feat] Support non-gated activations in NVFP4 modelopt path](../sources/prs/vllm/PR-29004.md), [[LoRA] Optimize 3D MoE logic](../sources/prs/vllm/PR-29222.md), [chore: add RTX_PRO_6000 GLM4.6-FP8 kernel tuning](../sources/prs/vllm/PR-29240.md), [[Kernel] Add NVFP4 MoE CUTLASS support for SM120](../sources/prs/vllm/PR-29242.md), [Lora MoE Align Improvements](../sources/prs/vllm/PR-29257.md), [[Perf] Disable DeepGEMM MoE by default when TP=8 is used](../sources/prs/vllm/PR-29346.md), [Add unpermute-aware fused MoE path and small-batch fallback](../sources/prs/vllm/PR-29354.md), [[Bugfix] Fix grouped_topk pytorch impl when num_experts can't be grouped properly](../sources/prs/vllm/PR-29439.md), [[Kernel][MoE] optimize `moe_align_block_size`](../sources/prs/vllm/PR-29642.md), [[Kernel]Support W4A8 Grouped GEMM on Hopper](../sources/prs/vllm/PR-29691.md), [[MoE-FP8-modelopt] Add FlashInfer alignment padding for intermediate dimensions](../sources/prs/vllm/PR-29748.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[ROCm] [Fused Moe EP] Use binary expert mask for aiter fused moe kernel](../sources/prs/vllm/PR-29773.md), [[ROCm][MXFP4] Infer w4a4 quant method in rocm aiter fused moe](../sources/prs/vllm/PR-29775.md), [[EPLB] Support EPLB w/ NVFP4](../sources/prs/vllm/PR-29804.md), [[Bugfix][Model] Support LoRA on Qwen3 Output Embedding](../sources/prs/vllm/PR-29816.md), [[Bugfix] Fix FP8 MoE LoRA](../sources/prs/vllm/PR-29890.md), [[Kernel][Quantization][MoE] add marlin kernel support for turing (sm75)](../sources/prs/vllm/PR-29901.md), [[moe] Use enable_chunking func (to support disabling chunking)](../sources/prs/vllm/PR-29935.md), [[moe] Allow disabling DP chunking](../sources/prs/vllm/PR-29936.md), [[Perf] Do FP4 quant before All gather on flashinfer trtllmgen MOE ](../sources/prs/vllm/PR-30014.md), [[Quantization] Support Quark int4-fp8 w4a8 for MoE](../sources/prs/vllm/PR-30071.md), [[Model][Quantization] Restore MoE + GGUF models support (incl. Qwen3 MoE) by allowing Sideload Parameters](../sources/prs/vllm/PR-30116.md), [[Model][Quantization] Override HF defaults to GGUF ones (incl. Qwen3 MoE)](../sources/prs/vllm/PR-30118.md), [Add latent MoE support](../sources/prs/vllm/PR-30203.md), [[Bugfix]: Fix glm46 awq marlin moe wna16 compatibility](../sources/prs/vllm/PR-30210.md), [[LoRA] Reduce the loading time of MoE LoRA](../sources/prs/vllm/PR-30243.md), [gptq marlin quantization support for fused moe with lora](../sources/prs/vllm/PR-30254.md), [[LoRA] Support Quantized Adapters](../sources/prs/vllm/PR-30286.md), [[Model][Quantization] Fix / Add GGUF support for Qwen2 MoE models](../sources/prs/vllm/PR-30307.md), [[bugfix][quantization] fix quark qwen3 kv_cache quantization](../sources/prs/vllm/PR-30308.md), [[fix] fix SM check for Flashinfer TRTLLM MOE](../sources/prs/vllm/PR-30314.md), [[ROCm][Quantization] GPT OSS Upstream MoE wmxfp4_afp8 with static scales](../sources/prs/vllm/PR-30357.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Bugfix] Fix Triton FusedMoE LoRA](../sources/prs/vllm/PR-30585.md), [[Perf] Eliminate padding and slicing op for GPT-OSS with Flashinfer MXFP4 MXFP8 MoE](../sources/prs/vllm/PR-30647.md), [fused_moe_lora PDL improvements](../sources/prs/vllm/PR-30716.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [Add support for LoRA adapters in Nemotron-H models](../sources/prs/vllm/PR-30802.md), [[Compressed-Tensors] Simplify NVFP4 Conditions, enable marlin support for NVFP4A16 MoEs](../sources/prs/vllm/PR-30881.md), [[Mics] add pcp basic support to MoE model](../sources/prs/vllm/PR-31003.md), [[Bugfix] Fix GLM-4 MoE router logits dtype for data parallel chunking](../sources/prs/vllm/PR-31055.md), [[BugFix] LoRA: Support loading base_layer of experts](../sources/prs/vllm/PR-31104.md), [[Bugfix] Fix MoE LoRA bin/pt loading](../sources/prs/vllm/PR-31161.md), [[Kernel] Add topk_sigmoid kernel](../sources/prs/vllm/PR-31246.md), [pin lora_b moe weights on cpu](../sources/prs/vllm/PR-31317.md), [[Misc] Fix Qwen2-MoE shared_expert_gate](../sources/prs/vllm/PR-31339.md), [[BugFix] add select_gemm_impl on CompressedTensorsWNA16MoEMethod to support LoRA](../sources/prs/vllm/PR-31453.md), [[Bugfix][ROCm] Fix Static Quant Issue](../sources/prs/vllm/PR-31502.md), [[ROCm][Bugfix] Fix accuracy issue on fmoe when `VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS` enabled](../sources/prs/vllm/PR-31523.md), [[FIX] Add NO_MUL activation support for modular kernel path](../sources/prs/vllm/PR-31528.md), [Use the same memory for workspace13 and fused_output.](../sources/prs/vllm/PR-31531.md), [[Fix] Align fused moe lora_b shape with peft](../sources/prs/vllm/PR-31534.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[LoRA]Disable linear LoRA kernel PDL](../sources/prs/vllm/PR-31777.md), [[Perf] Fuse stride preparation for NVFP4 cutlass_moe](../sources/prs/vllm/PR-31837.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [Add TMA support to fused_moe_lora kernel](../sources/prs/vllm/PR-32195.md), [[Hardware][SM100] Add TRTLLM Kernel for INT4 W4A16 Kernel.](../sources/prs/vllm/PR-32437.md), [[Perf][Kernel] Optimize FP4 quantization kernels (SM100F)](../sources/prs/vllm/PR-32520.md), [fix: Add glm4_moe_lite to MLA detection](../sources/prs/vllm/PR-32614.md), [[Bugfix] Fix FP8 MoE EP Weight Loading for ModelOpt Llama4](../sources/prs/vllm/PR-32886.md), [[NVIDIA] [feat] Integrate flashinfer Trtllmgen bf16 moe](../sources/prs/vllm/PR-32954.md), [Add support for Mistral Large 3 inference with Flashinfer MoE](../sources/prs/vllm/PR-33174.md), [fix: Add SM120 (RTX Blackwell) support for FlashInfer CUTLASS NVFP4 MoE kernels](../sources/prs/vllm/PR-33417.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [Adding support to Sarvam's MoE models](../sources/prs/vllm/PR-33942.md), [[Bugfix]fix output Nan/Inf in marlin if dtype=float16](../sources/prs/vllm/PR-33972.md), [[Kernel] Optimize grouped topk kernel](../sources/prs/vllm/PR-34206.md), [[ModelBash][DSR1 NVFp4] Avoid Bf16 Bias Cast](../sources/prs/vllm/PR-34298.md), [[ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup)](../sources/prs/vllm/PR-34302.md), [[Kernel] Integrate SM100 MXFP8 blockscaled grouped MM and quant kernels](../sources/prs/vllm/PR-34448.md), [[Model] Add NVFP4 quantization support for Step3.5-Flash](../sources/prs/vllm/PR-34478.md), [[Bugfix] Handle num_expert_group=None in flashinfer block-scale FP8 MoE](../sources/prs/vllm/PR-34494.md), [[Quantization] add humming quantization kernel](../sources/prs/vllm/PR-34556.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [[Performance] Cublas Bf16 Gate with Fp32 Output](../sources/prs/vllm/PR-35121.md), [[Bugfix] Fix DSV3 kernels breaking _C and _moe_C on unsupported arches](../sources/prs/vllm/PR-35123.md), [[Bugfix] Fix expert_ids padding values in moe_align_block_size kernel](../sources/prs/vllm/PR-35161.md), [[Quant][Feature] Support online MXFP8 quantization for MoE and dense models](../sources/prs/vllm/PR-35448.md), [[MoE][Perf] Wrap DSV3 QKVAProj GEMM in custom op for torch.compile](../sources/prs/vllm/PR-35751.md), [[MoE] Move PF Methods to Folder](../sources/prs/vllm/PR-35927.md), [Add support for ModelOpt MXFP8 MoE models](../sources/prs/vllm/PR-35986.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[Kernel] Add FlashInfer MoE A2A Kernel](../sources/prs/vllm/PR-36022.md), [[Bugfix] Disable FlashInfer TRTLLM BF16 path for non-gated MoE](../sources/prs/vllm/PR-36146.md), [[Perf] Add TRTLLM FP8 MoE Modular Kernel](../sources/prs/vllm/PR-36307.md), [[XPU] Support block fp8 moe by fallback to TritonExpert on XPU](../sources/prs/vllm/PR-36458.md), [[Bug][MoE] Fix TRTLLM NVFP4 Routing Kernel Precision](../sources/prs/vllm/PR-36725.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[MoE Refactor] Mxfp4 oracle rebased](../sources/prs/vllm/PR-37128.md), [[Kernel] Add gpt-oss Router GEMM kernel](../sources/prs/vllm/PR-37205.md), [[MoE/EPLB] Fix FlashInfer nvfp4 experts + EPLB correctness](../sources/prs/vllm/PR-37217.md), [[Kernel] Add non-gated support for NVFP4 CUTLASS MoE](../sources/prs/vllm/PR-37320.md), [[Kernel] Add MXFP4 W4A4 CUTLASS MoE kernel for SM100](../sources/prs/vllm/PR-37463.md), [[4/n] Migrate FP4/W4A8 CUTLASS kernels to torch stable ABI](../sources/prs/vllm/PR-37503.md), [[Bugfix] Disable monolithic TRTLLM MoE for Renormalize routing (#37591)](../sources/prs/vllm/PR-37605.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[MoE] Move FlashInfer CuteDSL experts into fused_moe/experts/](../sources/prs/vllm/PR-37759.md), [[Feature] Support per-draft-model MoE backend via `--speculative-config`](../sources/prs/vllm/PR-37880.md), [[MoE Kernel] Flashinfer nvfp4 cutedsl moe kernel integration](../sources/prs/vllm/PR-38050.md), [[Quantization] Add FlashInfer CuteDSL batched experts backend for NVFP4 MoE](../sources/prs/vllm/PR-38251.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[Quant] add CompressedTensorsW8A8Mxfp8 for linear and MoE layers](../sources/prs/vllm/PR-38815.md), [[Bugfix] Re-enable Renormalize routing for TRT-LLM MoE experts](../sources/prs/vllm/PR-38859.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[Bug] Fix routing bias dtype for trtllm per-block fp8 moe](../sources/prs/vllm/PR-38989.md), [[Bugfix][MoE] Fix 6-8% decode regression: prefer multi-stream shared expert overlap](../sources/prs/vllm/PR-38990.md), [[Perf] Change Trtllm fp8 MoE to use Shuffled Weights and BlockMajorK Layout](../sources/prs/vllm/PR-38993.md), [[MoE] Move GPT OSS Triton kernel experts into fused_moe/experts/](../sources/prs/vllm/PR-39007.md), [[Gemma4] Support quantized MoE ](../sources/prs/vllm/PR-39045.md), [[Bug] Fix Trtllm Fp8 MoE Weight Shuffle Memory Fragamentation](../sources/prs/vllm/PR-39054.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [perf(moe): add tuned fused_moe config for RTX PRO 6000 Blackwell Server Edition](../sources/prs/vllm/PR-39183.md), [[Bugfix] FlashInfer MXINT4 MoE crashes, missing do_finalize](../sources/prs/vllm/PR-39315.md), [fix: clamp NaN/Inf in topk_softmax to prevent duplicate expert IDs](../sources/prs/vllm/PR-39391.md), [[Kernel] Support TRTLLM GEN NVFP4 MoE for non-512-aligned hidden dims via weight padding](../sources/prs/vllm/PR-39510.md), [[Bugfix] [Tests] Enforce `out` tensor device in `kernel/moe/test_cutedsl_moe.py`](../sources/prs/vllm/PR-39644.md), [[Bugfix] Fix mismatch between global and local attention heads in tensor-parallel mode for param2moe model](../sources/prs/vllm/PR-39707.md), [[Bugfix] Reject non-nvfp4 dtypes when using the flashinfer_nvlink_one_sided all2all backend](../sources/prs/vllm/PR-39717.md), [[Bugfix] Disable FlashInfer CUTLASS MoE on SM121 (DGX Spark)](../sources/prs/vllm/PR-39825.md), [[Core] Replace routing replay with device cache and async D2H pipeline](../sources/prs/vllm/PR-39917.md), [[Bugfix] Temporarily disable B200 fp4 MoE layer tests](../sources/prs/vllm/PR-40057.md), [[Bugfix] moe lora align kernel grid](../sources/prs/vllm/PR-40131.md), [Fix MoE backend selection for LoRA (unquantized MoE)](../sources/prs/vllm/PR-40273.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[DSV4] Add silu clamp limit to shared expert](../sources/prs/vllm/PR-40950.md), [[DSV4] Add BF16 and MXFP8 A2A support for flashinfer a2a one sided](../sources/prs/vllm/PR-40960.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [[DSV4] Fuse norm and router for low latency scenario](../sources/prs/vllm/PR-41263.md), [[ROCm][Quantization][3/N] Refactor quark_moe w4a4 w/ oracle](../sources/prs/vllm/PR-41436.md), [[Quantization] Rework quantization_config to use QuantKey and allow for activation override](../sources/prs/vllm/PR-41566.md), [[MXFP4] Support for linear layers + compressed-tensors integration](../sources/prs/vllm/PR-41664.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[LoRA] Support 2D and 3D MoE LoRA adapter at the same time](../sources/prs/vllm/PR-42242.md), [Refactor AWQ Marlin MoE onto modular WNA16 oracle](../sources/prs/vllm/PR-42483.md), [[Perf] Wire silu_and_mul_per_block_quant into TritonFP8MoE (MiniMax-M2) ](../sources/prs/vllm/PR-42497.md), [[Kernel] Pack topk id/weights triton kernel](../sources/prs/vllm/PR-42527.md), [[Bugfix] fix swiglu limit issue for humming backend + deepseek v4](../sources/prs/vllm/PR-42541.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [Fix Weight loading for Qwen3.5-MTP and Qwen3-VL using runai_streamer](../sources/prs/vllm/PR-42716.md), [[Refactor] Remove dead cuda kernels](../sources/prs/vllm/PR-42767.md), [[Perf] Re-enable flashinfer autotune by default and cleanup](../sources/prs/vllm/PR-42857.md), [[Model Refactoring] Migrate DeepSeek V4 to vllm/models/ [1/N] ](../sources/prs/vllm/PR-43004.md), [[Kernel] (2/N) Machete - Integrate into CompressedTensorsWNA16 and GPTQMarlin](../sources/prs/vllm/PR-7701.md), [FlashInfer Track A FP8 Block-Scale MoE](../wiki/kernels/fused-moe.md), [Grouped GEMM Contracts for MoE and NVFP4](../wiki/kernels/grouped-gemm.md) | +| `prefill` | [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[None][feat] Optimize causal_conv1d prefill and decode kernels](../sources/prs/TensorRT-LLM/PR-13103.md), [[None][feat] Add chunked prefill support for Gemma4 (text + vision multimodal)](../sources/prs/TensorRT-LLM/PR-14134.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [feat: update decode attention APIs](../sources/prs/flashinfer/PR-1007.md), [add multi-item scoring](../sources/prs/flashinfer/PR-1015.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [Parameterize prefix mask call (needed by POD-Attention)](../sources/prs/flashinfer/PR-1059.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [bugfix: fix fp8 attention kernels aot compilation issue](../sources/prs/flashinfer/PR-1087.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [[feat] add unified batch attention w/ correctness tests.](../sources/prs/flashinfer/PR-1137.md), [Fix FA2 and FA3 multi-item scoring and cuda illegal memory access error](../sources/prs/flashinfer/PR-1140.md), [Fix the issue with auxillary kernel launch and grid dim calculation](../sources/prs/flashinfer/PR-1208.md), [feat: Add non-causal cudnn prefill kernels](../sources/prs/flashinfer/PR-1230.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [Allow cudnn prefill kernels to be called natively](../sources/prs/flashinfer/PR-1317.md), [feat: Support logits_soft_cap for Persistent attn; fix kv split limit](../sources/prs/flashinfer/PR-1324.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [Allow BatchPrefillPagedWrapper to call cudnn API](../sources/prs/flashinfer/PR-1384.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [bugfix: Fix Persistent kernel precision for masked output ](../sources/prs/flashinfer/PR-1533.md), [feat: Integrate TRTLLM varlen kernel for deepseek R1 prefill ](../sources/prs/flashinfer/PR-1537.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [feat: Support for inferring out_dtype from out.dtype for TRTLLM attention kernel](../sources/prs/flashinfer/PR-1578.md), [fix: Improve TRTLLM attention kernel out_dtype unit test](../sources/prs/flashinfer/PR-1590.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [fix: pass workspace for trtllm-gen attention](../sources/prs/flashinfer/PR-1635.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [feat: Batch-size invariant FA2 Prefill & Decode](../sources/prs/flashinfer/PR-1675.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [Fix tests/test_trtllm_gen_attention.py::test_trtllm_batch_prefill, ::test_trtllm_batch_decode mismatch error](../sources/prs/flashinfer/PR-1755.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [fix: Fix trtllm-gen prefill IMA when batch_size==1](../sources/prs/flashinfer/PR-1912.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Added an initial implementation of Q and KV Cache in fp8 and to use t…](../sources/prs/flashinfer/PR-2035.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [[Feature] Support batch prefill for POD Attention](../sources/prs/flashinfer/PR-2079.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [fix: compile flags for trtllm fmha_v2 ](../sources/prs/flashinfer/PR-2175.md), [Fp8 attention are now part of cuDNN 9.17.1](../sources/prs/flashinfer/PR-2241.md), [feat: add GDN Attention](../sources/prs/flashinfer/PR-2276.md), [Added the cudnn backend Ragged KV Cache wrapper](../sources/prs/flashinfer/PR-2352.md), [feat: [Qwen3-Next] Add Cute DSL GDN decode kernel and tests](../sources/prs/flashinfer/PR-2370.md), [Remove cudaMalloc/Free in GDN prefill kernel](../sources/prs/flashinfer/PR-2415.md), [refactor: reduce hopper's gdn prefill compilation time and fix docstring.](../sources/prs/flashinfer/PR-2422.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [Ameyn/gdn decode cutedsl kernel](../sources/prs/flashinfer/PR-2498.md), [perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead](../sources/prs/flashinfer/PR-2509.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [fix: allow fmha_v2_prefill_deepseek on SM121 (DGX Spark)](../sources/prs/flashinfer/PR-2559.md), [fix: guard CUTLASS FMHA against SM12x and fix fmha_v2 SM121a check](../sources/prs/flashinfer/PR-2560.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [benchmarks: Add FP8 input / BF16 output in ragged prefill benchmark](../sources/prs/flashinfer/PR-2666.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [feat: Add DiT-oriented kernels where Qk (Bmm1) type can be reinterpreted into Int8 or BFloat16](../sources/prs/flashinfer/PR-2711.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [[fmha-v2] Support HND and NHD paged KV cache layouts with conditional stride handling](../sources/prs/flashinfer/PR-2799.md), [[fix] Bugfix 1367: fix VariableBlockSparseAttention buffer overflow by dynamically resizing kv_lens_buffer](../sources/prs/flashinfer/PR-2802.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [[Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D](../sources/prs/flashinfer/PR-2841.md), [read real strides for kv and block scale](../sources/prs/flashinfer/PR-2844.md), [feat(gdn): state checkpointing in chunk_gated_delta_rule](../sources/prs/flashinfer/PR-2908.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [test: xfail cuDNN FP8 prefill on Blackwell with CUDA <= 12.9](../sources/prs/flashinfer/PR-2963.md), [[feat] Add blackwell GDN prefill kernel](../sources/prs/flashinfer/PR-3001.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16](../sources/prs/flashinfer/PR-3129.md), [cute-dsl fmha prefill (cubin integration): remove front-padding, add attention_sink, and pdl support](../sources/prs/flashinfer/PR-3181.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [perf: fix the iteration bound of SWA in FA2 prefill template](../sources/prs/flashinfer/PR-714.md), [feat: support deepseek prefill attention shape](../sources/prs/flashinfer/PR-765.md), [perf: refactor fa2 prefill template](../sources/prs/flashinfer/PR-776.md), [feat: Separate QK/VO head dim dispatch for sm90 AOT](../sources/prs/flashinfer/PR-778.md), [bugfix: fix batch prefill attention kernel unittests](../sources/prs/flashinfer/PR-781.md), [bugfix: drop CTA_TILE_Q=32](../sources/prs/flashinfer/PR-785.md), [feat: support f32 attention output in FA2 template](../sources/prs/flashinfer/PR-799.md), [feat: apply sm_scale at logits instead of q in FA2 template](../sources/prs/flashinfer/PR-801.md), [perf: memory efficient deepseek mla fused page-attention kernel](../sources/prs/flashinfer/PR-804.md), [Add POD-Attention to FlashInfer](../sources/prs/flashinfer/PR-858.md), [Naive Support for Hopper FP8 Prefill Kernel with Per-Head Quantization](../sources/prs/flashinfer/PR-869.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [[2/2] Support MHA prefill with FlashAttention 4.](../sources/prs/sglang/PR-10937.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [DeepSeek-V3.2: Add Adaptive MHA Attention Pathway for Short-Sequence Prefill](../sources/prs/sglang/PR-11892.md), [[DeepSeek-V3.2][NSA] Enable MHA Pathway for Short Sequence Prefill on B200 (SM100)](../sources/prs/sglang/PR-12788.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [[AMD] Support fused_rms_mxfp4_quant in the prefill stage for DeepSeek-R1-MXFP4](../sources/prs/sglang/PR-14975.md), [Support Qwen3 MoE context parallel](../sources/prs/sglang/PR-18233.md), [feat(gdn): add FlashInfer K-last SSM layout support for GDN prefill and decode for Hopper](../sources/prs/sglang/PR-18361.md), [Fp8 prefill attn kernel integration](../sources/prs/sglang/PR-18528.md), [[AMD] Fp8 prefill integration with radix cache path for dpsk models](../sources/prs/sglang/PR-20187.md), [[GDN] Add benchmark for sglang gdn prefill](../sources/prs/sglang/PR-20428.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [[DSA] Support trtllm sparse mla kernel for prefill batches ](../sources/prs/sglang/PR-21783.md), [[KDA] Optimize prefill kernels with diagonal and recompute fuse](../sources/prs/sglang/PR-24271.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Introduce SchedulerDPAttnAdapter to own DP-attention state](../sources/prs/sglang/PR-25611.md), [Move DP-attention adapter methods to SchedulerDPAttnAdapter](../sources/prs/sglang/PR-25612.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [Support MHA with chunked prefix cache for DeepSeek chunked prefill](../sources/prs/sglang/PR-5113.md), [[PD] Fix dynamic port support and MLA buffer for Mooncake](../sources/prs/sglang/PR-5415.md), [Avoid computing lse in Ragged Prefill when there's no prefix.](../sources/prs/sglang/PR-5476.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [[PD] Add different TP sizes support for no-MLA models](../sources/prs/sglang/PR-6793.md), [Let EP prefill support new DeepGEMM](../sources/prs/sglang/PR-7310.md), [[Feature] Layer-wise Prefill](../sources/prs/sglang/PR-7634.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [Disable chunked prefill and/or prefix caching when MLA is enabled ](../sources/prs/vllm/PR-12642.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [[ROCm] Disable chunked prefill/prefix caching when running MLA on non-cuda platforms](../sources/prs/vllm/PR-13844.md), [Fix mla prefill context performance](../sources/prs/vllm/PR-13897.md), [[ROCm] Enable chunked prefill/paged attention in MLA on ROCm](../sources/prs/vllm/PR-14316.md), [[BugFix] Fix nightly MLA failure (FA2 + MLA chunked prefill, i.e. V1, producing bad results)](../sources/prs/vllm/PR-15492.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [[Kernel] Unified Triton kernel that doesn't distinguish between prefill + decode](../sources/prs/vllm/PR-16828.md), [[ROCm][Kernel][V1] Enable AMD Radeon GPU Custom Paged Attention on v1](../sources/prs/vllm/PR-17004.md), [[Bugfix][ROCm] Use `chunked_prefill_paged_decode` as fallback for V1 attention on ROCm](../sources/prs/vllm/PR-18093.md), [[Hardware][AMD] integrate aiter chunked prefill into vllm](../sources/prs/vllm/PR-18596.md), [[Attention] MLA - Flashinfer Ragged Prefill](../sources/prs/vllm/PR-20034.md), [[Kernel] Optimize Prefill Attention in Unified Triton Attention Kernel](../sources/prs/vllm/PR-20308.md), [[Model] Pooling models default to using chunked prefill & prefix caching if supported.](../sources/prs/vllm/PR-20930.md), [Override attention metadata for fast prefill in some KV sharing setups](../sources/prs/vllm/PR-21590.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [[NVIDIA] Support Flashinfer TRT-LLM Prefill Attention Kernel](../sources/prs/vllm/PR-22095.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [[Attention] Make `split_decodes_and_prefills(..., require_uniform=True)` support padding](../sources/prs/vllm/PR-29644.md), [[perf] Use direct copy (broadcast) instead of cat for k_nope/k_pe in MLA prefill](../sources/prs/vllm/PR-29710.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten](../sources/prs/vllm/PR-31380.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[Kernel] use flashinfer for gdn prefill](../sources/prs/vllm/PR-32846.md), [[Attention] Use FA4 for MLA prefill](../sources/prs/vllm/PR-34732.md), [[Bugfix][MLA] Add logits size budget to sparse indexer prefill chunking](../sources/prs/vllm/PR-36178.md), [[ROCm] Attention selector reordering](../sources/prs/vllm/PR-36702.md), [[Attention] Support distinguishing between short extends and decodes](../sources/prs/vllm/PR-37303.md), [[GDN] Eliminate GPU->CPU sync in prepare_chunk_indices during prefill](../sources/prs/vllm/PR-38361.md), [[Bugfix][MLA] Change default SM100 MLA prefill backend back to TRT-LLM](../sources/prs/vllm/PR-38562.md), [[Attention][MLA] Re-enable FA4 as default MLA prefill backend](../sources/prs/vllm/PR-38819.md), [[Gemma4] Enable Fast Prefill Optimization](../sources/prs/vllm/PR-38879.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[GDN] Enable FI Blackwell GDN prefill kernel](../sources/prs/vllm/PR-40717.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[Bugfix] Fix TRTLLM ragged MLA prefill workspace warmup](../sources/prs/vllm/PR-42112.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [DeepSeek Sparse Attention / Sparse MLA](../wiki/kernels/sparse-mla.md) | | `quantization` | [NVFP4 Format Details](../sources/blogs/nvfp4-format-details.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [[None][feat] sm100 weight-only kernel](../sources/prs/TensorRT-LLM/PR-10190.md), [[None][fix] impl fused triton kernel for e8m0 resmooth to reduce memory footprint](../sources/prs/TensorRT-LLM/PR-10327.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[None][fix] Fix int4 awq for sm120/121](../sources/prs/TensorRT-LLM/PR-11561.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[TRTLLM-10421][perf] Add fused cat+fp8_quantize CUDA kernel for DSA indexer](../sources/prs/TensorRT-LLM/PR-11899.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[None][feat] Add bf16 trtllm-gen moe support through flashinfer.](../sources/prs/TensorRT-LLM/PR-12738.md), [[TRTLLM-11585][feat] Add CUTEDSL moe backend for nemotron-h](../sources/prs/TensorRT-LLM/PR-12884.md), [[#12784][feat] AutoDeploy: Optimize DeepSeek-R1 model performance](../sources/prs/TensorRT-LLM/PR-12946.md), [[None][feat] Add FP4 residual quantization kernel without channel reo…](../sources/prs/TensorRT-LLM/PR-13117.md), [[TRTLLM-11127][feat] add W4A8_MXFP4_FP8 MoE unit test support](../sources/prs/TensorRT-LLM/PR-13401.md), [[None][feat] Fuse FP8 1x128 quantize + UE8M0 scale pack on SM100](../sources/prs/TensorRT-LLM/PR-13628.md), [[None][feat] Add bf16 trtllm moe through flashinfer.](../sources/prs/TensorRT-LLM/PR-13689.md), [[None][fix] Plumb swiglu_limit through DeepGEMM and TRTLLMGen FP8 fused MoE](../sources/prs/TensorRT-LLM/PR-13767.md), [[https://nvbugs/6163147][fix] swap layer.mlp in place for Mixtral modelopt export](../sources/prs/TensorRT-LLM/PR-14179.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][fix] Update the OSS headers in derived FLA ops and AD modeling code](../sources/prs/TensorRT-LLM/PR-14281.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[None][feat] Enable EPLB for trtllm-gen and cutlass backend](../sources/prs/TensorRT-LLM/PR-8886.md), [[None][feat] Port fp4 quantization kernel optimization from FlashInfer](../sources/prs/TensorRT-LLM/PR-9854.md), [add multi-item scoring](../sources/prs/flashinfer/PR-1015.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [bugfix: fix fp8 attention kernels aot compilation issue](../sources/prs/flashinfer/PR-1087.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [bugfix: Fix test and output shape of fp4 quantize](../sources/prs/flashinfer/PR-1114.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [Add fp4 quantization swizzling tests](../sources/prs/flashinfer/PR-1157.md), [feat: enable and update all-reduce fused quantization](../sources/prs/flashinfer/PR-1164.md), [Expose fp4 blockscale swizzling kernel](../sources/prs/flashinfer/PR-1176.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [Bug fix: guard fp8 e8m0 and e2m1 compile ](../sources/prs/flashinfer/PR-1287.md), [add mm_fp4 use cudnn backend](../sources/prs/flashinfer/PR-1288.md), [[fix] fix integer overflow in FA2 customized_mask & add buffer overflow warning.](../sources/prs/flashinfer/PR-1290.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [test qkvo quantization not equal to 1.](../sources/prs/flashinfer/PR-1314.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [feat: Fused rope fp8 quantize kernel for MLA](../sources/prs/flashinfer/PR-1339.md), [feature: add fp4 mm using trtllm backend](../sources/prs/flashinfer/PR-1355.md), [bugfix: fixed cutlass fused moe usage of FP4QuantizationSFLayout::SWIZZLED](../sources/prs/flashinfer/PR-1371.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [Add Mxfp4 trtllm-gen moe unit tests](../sources/prs/flashinfer/PR-1399.md), [Add alignment in MxFP8Quantization](../sources/prs/flashinfer/PR-1445.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [bugfix: Fix compile error for undefined swizzle enum.](../sources/prs/flashinfer/PR-1530.md), [fix: separate out fp4 lib into sm90 and sm100 versions, add oob checking in fused moe](../sources/prs/flashinfer/PR-1565.md), [bugfix: Fix test_fp4_quantize test bug](../sources/prs/flashinfer/PR-1585.md), [bugfix: fix unittest test_fp8_quantize](../sources/prs/flashinfer/PR-1599.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [feat: cutlass fp4 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1609.md), [bugfix: fix fp4 quantization with 8x4 scale factor layout](../sources/prs/flashinfer/PR-1611.md), [feat: add support of fp4_batched_quantize](../sources/prs/flashinfer/PR-1633.md), [Add benchmark for MLARopeQuantize](../sources/prs/flashinfer/PR-1656.md), [[Hotfix] `test_fp4_quantize.py` failure on sm103](../sources/prs/flashinfer/PR-1666.md), [test: better fp8 quantization init for fused_moe test](../sources/prs/flashinfer/PR-1674.md), [tests: xfail moe quantization classes mxfp8_bf16 UTs on sm103 ](../sources/prs/flashinfer/PR-1754.md), [Masked batch nvfp4 quantization](../sources/prs/flashinfer/PR-1774.md), [[Quantization] Add per-expert global scaling factor for fp4 batched quantize](../sources/prs/flashinfer/PR-1835.md), [MLA RoPE + quantization fused kernel: shape generalization for MHA / GQA](../sources/prs/flashinfer/PR-1924.md), [silu_and_mul nvfp4 quanization fusion rework](../sources/prs/flashinfer/PR-1927.md), [fix: correct PDL parameter handling in RopeQuantize kernel](../sources/prs/flashinfer/PR-1982.md), [perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE](../sources/prs/flashinfer/PR-2025.md), [feat: Add flashinfer.rope.rope_quantize_fp8_append_paged_kv_cache (fused RoPE + Q + KV cache, supports MLA/GQA/MHA) ](../sources/prs/flashinfer/PR-2037.md), [test: Skip test_fp8_quantize.py on Hopper](../sources/prs/flashinfer/PR-2052.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [feat: Fused RMSNorm + FP4 Quantization Kernels in CuTe-DSL](../sources/prs/flashinfer/PR-2233.md), [feat: RMSNorm/Fused RMSNorm + FP8 Quantization kernels](../sources/prs/flashinfer/PR-2243.md), [fix: support int64 IdType for RoPE part argument in `rope_quantize_fp8_append_paged_kv_cache`](../sources/prs/flashinfer/PR-2255.md), [Optimize quantization function in large problem size](../sources/prs/flashinfer/PR-2343.md), [benchmarks: Add norm and quantization routines to microbenchmark harness.](../sources/prs/flashinfer/PR-2362.md), [fix: Fix NaN output in mxfp8_quantize for very small input values](../sources/prs/flashinfer/PR-2441.md), [Add cute-dsl backends to mxfp[8,4]_quantization for future refactor](../sources/prs/flashinfer/PR-2443.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [benchmark: Add MXFP4/MXFP8 quantization mode support to FP4 MoE benchmark](../sources/prs/flashinfer/PR-2635.md), [Enable sm120f compilation](../sources/prs/flashinfer/PR-2650.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [feat: Add FP4 KV cache quant/dequant kernels ](../sources/prs/flashinfer/PR-2757.md), [feat: Add CuTe-DSL backend for NVFP4 quantization](../sources/prs/flashinfer/PR-2838.md), [fix: snap weight_scale_vec_size to handle block_scale_interleave padding for SM120](../sources/prs/flashinfer/PR-2898.md), [perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels](../sources/prs/flashinfer/PR-2904.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [perf: optimize per-token nvfp4 quantization kernel.](../sources/prs/flashinfer/PR-3237.md), [Naive Support for Hopper FP8 Prefill Kernel with Per-Head Quantization](../sources/prs/flashinfer/PR-869.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [Add AOTI shim for _weight_int4pack_mm_cpu_tensor (#149031)](../sources/prs/pytorch/PR-149386.md), [[RELEASE 2.10] Release only changes](../sources/prs/pytorch/PR-170112.md), [[RELEASE 2.11] Release only changes](../sources/prs/pytorch/PR-175091.md), [[release 2.12] Apply Release only changes to 2.12 branch](../sources/prs/pytorch/PR-180470.md), [feat: Add FP4 (E2M1) KV Cache Support with Quantization Utilities for MLA](../sources/prs/sglang/PR-10078.md), [Enable native ModelOpt quantization support (3/3)](../sources/prs/sglang/PR-10154.md), [Add support for bf16 x bf16 cutlass fused MoE](../sources/prs/sglang/PR-10275.md), [Support single batch overlap](../sources/prs/sglang/PR-10422.md), [Cache the result of `is_blackwell` platform check](../sources/prs/sglang/PR-10498.md), [Fix bias handling in TritonMoeQuantInfo within quantization/mxfp4.py](../sources/prs/sglang/PR-10579.md), [[Auto Sync] Update modelopt_quant.py (20250920)](../sources/prs/sglang/PR-10688.md), [Fuse quantize and rope in trtllm_mla MTP](../sources/prs/sglang/PR-10779.md), [Fix DSR1 accuracy for flashinfer_trtllm MoE with FP8 quantization](../sources/prs/sglang/PR-11081.md), [Support shared experts overlap in cutlass moe](../sources/prs/sglang/PR-11611.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [Change bf16 to fp8 for some gemms in attention for DeepSeek ckpt v2](../sources/prs/sglang/PR-11805.md), [Use cutlass fp4 gemm by default](../sources/prs/sglang/PR-11813.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [[Ascend] qwen optimization](../sources/prs/sglang/PR-12078.md), [[hotfix] missing `w13_weight_fp8` and `w2_weight_fp8` in UE8M0 requantization](../sources/prs/sglang/PR-12259.md), [Replace [silu_and_mul_]scaled_fp4_group_quant by Flashinfer equivalent](../sources/prs/sglang/PR-12376.md), [Use sgl fp4 quant kernel by default](../sources/prs/sglang/PR-12482.md), [Enable Flashinfer TRTLLM-GEN-MoE FP8 blockwise kernel for Qwen3-Next on Blackwell](../sources/prs/sglang/PR-12543.md), [[NVIDIA] Fix wrong symmetric sizes for fp4 cases](../sources/prs/sglang/PR-12640.md), [[Bugfix] Fix illegal memory access](../sources/prs/sglang/PR-12758.md), [[Ascend] support Kimi-K2-Thinking](../sources/prs/sglang/PR-12759.md), [Update dsv3 quantization auto setting for sm100](../sources/prs/sglang/PR-12778.md), [Aiter fp8 kv cache](../sources/prs/sglang/PR-13147.md), [[NPU]Optimization of `forward_npu` for `UnquantizedFusedMoEMethod`](../sources/prs/sglang/PR-13158.md), [[NVIDIA] Fix broken fp8 MoE of deepseek v3](../sources/prs/sglang/PR-13264.md), [[NVIDIA] Fix use case of SGLANG_ENABLE_FLASHINFER_GEMM](../sources/prs/sglang/PR-13274.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [Fix EPLB + FP4 Quantization Compatibility Issue](../sources/prs/sglang/PR-13715.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [[NVIDIA] Enable TRTLLM BF16 MoE on Blackwell GPUs](../sources/prs/sglang/PR-13798.md), [Fix update weight error for blackwell DeepGEMM](../sources/prs/sglang/PR-13910.md), [Fix flashinfer cutlass MoE output shape for non-FP4-packed inputs](../sources/prs/sglang/PR-14028.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[NPU] perf update with kvcache nz & w4a8 quant](../sources/prs/sglang/PR-14423.md), [Add Mistral Large 3 Eagle Support](../sources/prs/sglang/PR-14466.md), [Mistral Large 3 NVFP4 support](../sources/prs/sglang/PR-14485.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [[NVIDIA] Fixes for NVFP4 all-gather with spec decoding](../sources/prs/sglang/PR-15280.md), [Fix the accuracy issue when running mxfp4 dsv3 model and enable ep](../sources/prs/sglang/PR-15304.md), [feat: support bitsandbytes quantization algorithm](../sources/prs/sglang/PR-15325.md), [[NPU]DeepSeek-V3.2 support npu mlaprolog](../sources/prs/sglang/PR-15381.md), [Flashinfer MOE FP8 support for Mistral Large 3.](../sources/prs/sglang/PR-15422.md), [[Perf] Add Flashinfer DeepGEMM SM90 for SwapAB Optimization](../sources/prs/sglang/PR-15514.md), [Update flashinfer to 0.6.1](../sources/prs/sglang/PR-15551.md), [[Perf] Eliminate the slice op for Flashinfer `trtllm_fp4_block_scale_moe`](../sources/prs/sglang/PR-15731.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [[NPU] NZ for non-quantized MOE, Qwen3 MOE double memory consumption fix](../sources/prs/sglang/PR-15904.md), [[Performance] Force split_k=1 for MXFP4 Triton kernels on Hopper](../sources/prs/sglang/PR-16014.md), [Fix FP8 MoE NaN with DeepGEMM on Blackwell](../sources/prs/sglang/PR-16622.md), [Support mxint4 flashinfer_trtllm moe gemm](../sources/prs/sglang/PR-16892.md), [[FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/sglang/PR-17300.md), [Add mxfp8 support for online quantization, Triton dense linear, and CUTLASS MoE](../sources/prs/sglang/PR-17449.md), [[feat] Support nvfp4 quantized model of Qwen3-Next](../sources/prs/sglang/PR-17627.md), [fix(quantization): add sgl_kernel fallback for FP4 quantize on Blackwell GPUs](../sources/prs/sglang/PR-17816.md), [[Bugfix] Fix Mistral Large 3 NVFP4 TRTLLM MoE](../sources/prs/sglang/PR-18065.md), [Fix nvfp4 weight update](../sources/prs/sglang/PR-18085.md), [[ROCm] Optimize Deepseek R1 on MI300X](../sources/prs/sglang/PR-18242.md), [[MUSA][10/N] Add GGUF support](../sources/prs/sglang/PR-18357.md), [[Kimi-K2.5] Fix NVFP4 Kimi-K2.5 weight mapping and exclude list](../sources/prs/sglang/PR-18370.md), [docs: expand and update modelopt documentation](../sources/prs/sglang/PR-18479.md), [[sglang-miles] True on-policy training support for FSDP2](../sources/prs/sglang/PR-18639.md), [[RL] Support per-layer mixed FP8/BF16 serving for FP8 checkpoints](../sources/prs/sglang/PR-18742.md), [[Perf] ~9.5x faster Blackwell MXFP4 MoE weight loading](../sources/prs/sglang/PR-18858.md), [feat: Support MXFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-19143.md), [Adjust padding size to improve triton_kernels moe performance](../sources/prs/sglang/PR-19174.md), [[AMD] Fix weight load shape mismatch for amd dsr1 0528 mxfp4](../sources/prs/sglang/PR-19425.md), [Fix/nemotron mtp quantaized](../sources/prs/sglang/PR-19433.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Support `triton_kernels` for GPT-OSS on SM120](../sources/prs/sglang/PR-19718.md), [Various SM120 improvements](../sources/prs/sglang/PR-19721.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [Fix SM120 `triton_kernels` MXFP4 `block_k` for GPT-OSS](../sources/prs/sglang/PR-20040.md), [Enable modelopt quantized FLUX deployment](../sources/prs/sglang/PR-20082.md), [[diffusion] Support nvfp4 for Flux.2](../sources/prs/sglang/PR-20137.md), [[4/n jit_kernel restruct] speed up CI tests and add benchmark workflow](../sources/prs/sglang/PR-20268.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[NVIDIA] Enable fp8 flashinfer_trtllm_routed MoE for MiniMax-M2.5](../sources/prs/sglang/PR-20394.md), [[Model] Support Nemotron 3 Super NVFP4](../sources/prs/sglang/PR-20407.md), [fix(docs): correct quantization documentation (#20301)](../sources/prs/sglang/PR-20619.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[refactor] Clean up duplicate flashinfer trtllm moe code](../sources/prs/sglang/PR-21233.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[NVIDIA] Enable FP4 flashinfer trtllm routed moe](../sources/prs/sglang/PR-21240.md), [[RL] Support mxfp8 DeepSeek V3](../sources/prs/sglang/PR-21280.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[Kernel] Support FlashInfer TRTLLM-Gen fused MoE for non-gated FP4 & FP8 (Nemotron)](../sources/prs/sglang/PR-21321.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Add dedicated FlashInferCuteDslMoE layer for standard-path FP4 MoE](../sources/prs/sglang/PR-21339.md), [[FlashInver v0.6.7] Integrate flashinfer_trtllm mxfp8 gemm](../sources/prs/sglang/PR-21576.md), [[server] Add --quantization unquant to explicitly opt out of quantization](../sources/prs/sglang/PR-21863.md), [fix pcg torch dynamo recompile in mxfp8 Triton path](../sources/prs/sglang/PR-21888.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[RL] Refactor NVFP4 shuffling/swizzling to in-place replacement](../sources/prs/sglang/PR-22204.md), [[AMD][HIP] NSA: bf16 passthrough from RMSNorm to eliminate FP8 dequantization](../sources/prs/sglang/PR-22258.md), [[Reland] DeepSeek-R1-0528-w4a8: DeepEP Low Latency Dispatch Adopts FP8 Communication](../sources/prs/sglang/PR-22316.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [:sparkles: [diffusion][npu][quant] Add MXFP4 quantization support for Wan2.2 Diffusion on Ascend NPU](../sources/prs/sglang/PR-22338.md), [[Diffusion] modelopt diffusion fp8 support for flux1/flux2 and wan2.2](../sources/prs/sglang/PR-22365.md), [[Lora] Lora kimi support](../sources/prs/sglang/PR-22381.md), [[RL] Fix weight update for mxfp8 flashinfer_cutlass gemm backend](../sources/prs/sglang/PR-22484.md), [[Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22574.md), [diffusion: fix layerwise offload for ModelOpt quantized DiTs](../sources/prs/sglang/PR-22594.md), [feat: Support flashinfer_cutedsl MoE runner with flashinfer alltoall backend](../sources/prs/sglang/PR-22669.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [[Diffusion] Add Wan2.2 ModelOpt NVFP4 support](../sources/prs/sglang/PR-22681.md), [[Refactor] Refactor DeepEP dispatcher](../sources/prs/sglang/PR-22822.md), [[FlashInfer v0.6.11] [RL] Support FlashInfer per-token NVFP4 MoE](../sources/prs/sglang/PR-22918.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [[MoE] Unify DeepEPMoE+MoriEPMoE through AITER MoeRunner pre/post-permute](../sources/prs/sglang/PR-23760.md), [Refactor device timer, clean up metrics collector, and add fwd occupancy metric](../sources/prs/sglang/PR-24197.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [Add FlashInfer SM90 cutlass MXFP4 MoE backend (W4A16) for GPT-OSS + DeepSeek-V4](../sources/prs/sglang/PR-24816.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [perf(nvfp4): free unused source scales after weight processing](../sources/prs/sglang/PR-25107.md), [[Gemma4]: Fix FP8 Triton scale layout](../sources/prs/sglang/PR-25286.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[AMD] Enable shared-experts fusion with new KIMI-K2.5-MXFP4 model.](../sources/prs/sglang/PR-25390.md), [[codex] Update Wan2.2 ModelOpt CI checkpoints](../sources/prs/sglang/PR-25483.md), [[MoE Refactor] Migrate flashinfer_cutedsl + DeepEP to MoeRunner](../sources/prs/sglang/PR-25525.md), [Use DeepGEMM BF16 for unquantized DeepEP LL MoE](../sources/prs/sglang/PR-25540.md), [Add no_combine support to cutlass_moe_fp4](../sources/prs/sglang/PR-25688.md), [Apply sgl w8a8 fp8 kernel](../sources/prs/sglang/PR-3148.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [add control for cutlass fp8 blockwise gemm](../sources/prs/sglang/PR-3727.md), [Feature DeepSeek V3/R1 INT8 Quantization (block-wise)](../sources/prs/sglang/PR-3730.md), [[Feature] DeepSeek V3/R1 INT8 Quantization (channel-wise) ](../sources/prs/sglang/PR-3888.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [Support overlapping two batches](../sources/prs/sglang/PR-4068.md), [linear support deepgemm](../sources/prs/sglang/PR-4199.md), [Clean up fp8 support](../sources/prs/sglang/PR-4230.md), [[FIX] fix incorrect output when enable both deepgemm and torch compile](../sources/prs/sglang/PR-4359.md), [[ROCm] fix dtype](../sources/prs/sglang/PR-4510.md), [Create col-major and tma-aligned x_scale for deep_gemm.gemm_fp8_fp8_bf16_nt](../sources/prs/sglang/PR-4515.md), [[quantization] fix channelwise conversion with scalar weight scale](../sources/prs/sglang/PR-4596.md), [Set deepgemm to the default value in the hopper architecture.](../sources/prs/sglang/PR-4613.md), [Fix loading KV quantization scale; Enable modelopt kv cache](../sources/prs/sglang/PR-4686.md), [Add DeepSeek V3/R1 shared experts fusion](../sources/prs/sglang/PR-4918.md), [feat: add DeepGEMM build warning](../sources/prs/sglang/PR-5176.md), [[Fix] Turn off DeepGEMM by default](../sources/prs/sglang/PR-5263.md), [fix: use deepgemm only on hopper](../sources/prs/sglang/PR-5310.md), [[perf] experimental enhance fp8 per-tensor quant](../sources/prs/sglang/PR-5370.md), [[feature] enable pre compile jit deep_gemm](../sources/prs/sglang/PR-5580.md), [ DeepEP normal support deepgemm-contiguous](../sources/prs/sglang/PR-5626.md), [Turn on DeepGemm By Default and Update Doc](../sources/prs/sglang/PR-5628.md), [[perf] dsv3 bmm fallback to bf16](../sources/prs/sglang/PR-5662.md), [[2/2] Add python wrapper for CUTLASS FP8 Blockscale MoE Kernel. ](../sources/prs/sglang/PR-5694.md), [enable auto-round quantization model](../sources/prs/sglang/PR-6226.md), [Fix bug of deepseek-v3 under DP+EP mode with large batchsize/seqlen](../sources/prs/sglang/PR-6449.md), [[Feature] Support Flashinfer fp8 blockwise GEMM kernel on Blackwell](../sources/prs/sglang/PR-6479.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [[CPU] add optimizations for INT8 and FP8 DeepSeek](../sources/prs/sglang/PR-6769.md), [Support token-level quantization for EP MoE](../sources/prs/sglang/PR-6782.md), [[DeepseekR1-FP4] Add Support for nvidia/DeepSeekR1-FP4 model](../sources/prs/sglang/PR-6853.md), [Use deepgemm instead of triton for fused_qkv_a_proj_with_mqa](../sources/prs/sglang/PR-6890.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [chore: upgrade flashinfer v0.2.6.post1 jit](../sources/prs/sglang/PR-6958.md), [Fuse routed scaling factor in deepseek](../sources/prs/sglang/PR-6970.md), [Clean up server_args.py](../sources/prs/sglang/PR-7037.md), [Enable ModelOpt Llama4 fp8 checkpoint deployment in SGLang](../sources/prs/sglang/PR-7129.md), [Enable native ModelOpt quantization support (1/3) ](../sources/prs/sglang/PR-7149.md), [[amd] Opt dsv3 moe](../sources/prs/sglang/PR-7160.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Tiny let DeepGEMM scale checks cover more cases](../sources/prs/sglang/PR-7182.md), [chore: upgrade sgl-kernel v0.1.8.post2](../sources/prs/sglang/PR-7186.md), [[AMD] Fail gracefully when AITER is unavailable gfx90a GPUs](../sources/prs/sglang/PR-7187.md), [Fix a minor bug related to DeepGEMM upgrade](../sources/prs/sglang/PR-7191.md), [[fix] fix DeepGEMM blackwell input quant & ut & fix style and log](../sources/prs/sglang/PR-7247.md), [Support NVFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-7302.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Fix torch compile run](../sources/prs/sglang/PR-7391.md), [[AMD][Quantization] Add `int4fp8_moe` online quantization on ROCm](../sources/prs/sglang/PR-7392.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [feat: support DeepSeek-R1-W4AFP8 model with ep-moe mode](../sources/prs/sglang/PR-7762.md), [Qwen FP8/NVFP4 ModelOPT Quantization support](../sources/prs/sglang/PR-7912.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [[fix] fix modelopt fp4 on b200](../sources/prs/sglang/PR-8195.md), [[1/N]Support DeepSeek-R1 w4a8 normal deepep](../sources/prs/sglang/PR-8247.md), [Support triton kernels v3.4.0 for fused_moe](../sources/prs/sglang/PR-8258.md), [[2/N]Support DeepSeek-R1 w4a8 low latency deepep](../sources/prs/sglang/PR-8464.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [feat: support cutlass_moe_fp8 kernel for fusedmoe in sm90](../sources/prs/sglang/PR-8678.md), [Fix mismatch between padded_scales shape and reshape dimensions in modelopt quantization](../sources/prs/sglang/PR-8766.md), [[Perf] Auto enable best flashinfer mxfp4 kernel in b200](../sources/prs/sglang/PR-8898.md), [Fix hopper launch gpt-oss model illegal memory](../sources/prs/sglang/PR-8908.md), [optimize: reduce shulffle and quantization overhead in cutlass_moe sm90](../sources/prs/sglang/PR-8962.md), [Faster weight processing (trtllm-gen moe nvfp4)](../sources/prs/sglang/PR-9162.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [[fix] Fix mxfp4 triton MoE tp bug](../sources/prs/sglang/PR-9473.md), [fix: blackwell dsv3 fp8 issue temporary solution](../sources/prs/sglang/PR-9530.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [Tiny fix wrong comments](../sources/prs/sglang/PR-9589.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[ModelOpt] Fix Weight Loading for DSR1-FP4 Quantization](../sources/prs/sglang/PR-9712.md), [Make fp4_quantize kernels work on sm103](../sources/prs/sglang/PR-9807.md), [[Model] Support Meituan LongCat-Flash && LongCat-Flash-MTP](../sources/prs/sglang/PR-9824.md), [[Fix] DeepSeek EP accuracy issue on B200 GPUs](../sources/prs/sglang/PR-9946.md), [Enable native ModelOpt quantization support (2/3)](../sources/prs/sglang/PR-9991.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Kernel]: Cutlass 2:4 Sparsity + FP8/Int8 Quant Support](../sources/prs/vllm/PR-10995.md), [[Kernel] Update `cutlass_scaled_mm` to support 2d group (blockwise) scaling](../sources/prs/vllm/PR-11868.md), [Add: Support for Sparse24Bitmask Compressed Models](../sources/prs/vllm/PR-12097.md), [[Kernel] add triton fused moe kernel for gptq/awq](../sources/prs/vllm/PR-12185.md), [[AMD][Quantization] Add TritonScaledMMLinearKernel since int8 is broken for AMD](../sources/prs/vllm/PR-12282.md), [[Bugfix] Disable w16a16 2of4 sparse CompressedTensors24](../sources/prs/vllm/PR-12417.md), [Expert Parallelism (EP) Support for DeepSeek Models](../sources/prs/vllm/PR-12583.md), [[Kernel][Quantization] Integrate block-quantized CUTLASS kernels for DeepSeekV3](../sources/prs/vllm/PR-12587.md), [[Attention] Deepseek v3 MLA support with FP8 compute](../sources/prs/vllm/PR-12601.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [[AMD][ROCm] Enable DeepSeek model on ROCm](../sources/prs/vllm/PR-12662.md), [[Bugfix][Kernel] Fix per-token/per-channel quantization for Hopper scaled mm](../sources/prs/vllm/PR-12696.md), [[Misc] Update w2 scale loading for GPTQMarlinMoE](../sources/prs/vllm/PR-12757.md), [[NVIDIA] Support nvfp4 quantization](../sources/prs/vllm/PR-12784.md), [[Bugfix] Better FP8 supported defaults](../sources/prs/vllm/PR-12796.md), [[Misc][Kernel]: Add GPTQAllSpark Quantization](../sources/prs/vllm/PR-12931.md), [[Kernel]Add streamK for block-quantized CUTLASS kernels](../sources/prs/vllm/PR-12978.md), [[Model] Deepseek GGUF support ](../sources/prs/vllm/PR-13167.md), [Expand MLA to support most types of quantization](../sources/prs/vllm/PR-13181.md), [[Quant][Perf] Use moe_wna16 kernel by default for MoEs with many experts](../sources/prs/vllm/PR-13236.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [Fix CompressedTensorsWNA16MoE with grouped scales](../sources/prs/vllm/PR-13769.md), [[Bugfix][Quantization] Fix FP8 + EP](../sources/prs/vllm/PR-13784.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [[Kernel] optimize performance of gptq marlin kernel when n is small](../sources/prs/vllm/PR-14138.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[Build/BugFix] Fix hopper 12.8 build](../sources/prs/vllm/PR-14354.md), [Add cutlass support for blackwell fp8 blockwise gemm](../sources/prs/vllm/PR-14383.md), [[Kernel] moe wna16 marlin kernel](../sources/prs/vllm/PR-14447.md), [[ROCm][Kernel] MoE weights padding](../sources/prs/vllm/PR-14454.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[Attention] Flash Attention 3 - fp8](../sources/prs/vllm/PR-14570.md), [[Quantization][FP8] Adding support for fp8 gemm layer input in fp8](../sources/prs/vllm/PR-14578.md), [[Kernel] GGUF MoE kernel](../sources/prs/vllm/PR-14613.md), [[Kernel] allow non-contiguous input for marlin kernel](../sources/prs/vllm/PR-14658.md), [[Attention] MLA get rid of materialization](../sources/prs/vllm/PR-14770.md), [[FEAT][ROCm] Integrate Fused MoE Kernels from AITER](../sources/prs/vllm/PR-14967.md), [[FEAT] [ROCm]: Add AITER Block-Scaled GEMM Feature](../sources/prs/vllm/PR-14968.md), [Fix non-contiguous input passed to Marlin kernel](../sources/prs/vllm/PR-15319.md), [[V1] Fully Transparent Implementation of CPU Offloading](../sources/prs/vllm/PR-15354.md), [[FEAT] [ROCm] Add AITER int8 scaled gemm kernel](../sources/prs/vllm/PR-15433.md), [[Kernel] Fix conflicting macro names for gguf kernels](../sources/prs/vllm/PR-15456.md), [[Quantization] Fp8 Channelwise Dynamic Per Token GroupedGEMM](../sources/prs/vllm/PR-15587.md), [[Bugfix] fix use_atomic_add support of marlin kernel when using v1 engine](../sources/prs/vllm/PR-15946.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [Add support to modelopt quantization of Mixtral model](../sources/prs/vllm/PR-15961.md), [[Kernel] Use moe_wna16 kernel for compressed tensors wna16 moe models](../sources/prs/vllm/PR-16038.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Hardware/NVIDIA/Kernel] [Functional Enablement] [1/N] Enable nvidia/DeepSeek-R1-FP4 Model](../sources/prs/vllm/PR-16362.md), [[Kernel] Support W8A8 channel-wise weights and per-token activations in triton fused_moe_kernel](../sources/prs/vllm/PR-16366.md), [Enable PTPC FP8 for CompressedTensorsW8A8Fp8MoEMethod (triton fused_moe)](../sources/prs/vllm/PR-16537.md), [[ROCm] Add aiter tkw1 kernel for Llama4 fp8](../sources/prs/vllm/PR-16727.md), [Support W8A8 INT8 MoE for compressed-tensors](../sources/prs/vllm/PR-16745.md), [[FEAT] [ROCm]: AITER Fused MOE V1 Support](../sources/prs/vllm/PR-16752.md), [[torch.compile][ROCm] Fuse quantization onto attention using a torch.compile pass](../sources/prs/vllm/PR-16756.md), [[Kernel] GGUF MoeVec kernel](../sources/prs/vllm/PR-16780.md), [[Kernel] some optimizations for dense marlin and moe marlin](../sources/prs/vllm/PR-16850.md), [[Bugfix] Fix moe weight losing all extra attrs after `process_weights_after_loading`.](../sources/prs/vllm/PR-16854.md), [[Kernel] Add expert_map support to Cutlass FP8 MOE](../sources/prs/vllm/PR-16861.md), [[FEAT] [ROCm]: Add AITER CK 2 Stages MoE support](../sources/prs/vllm/PR-17110.md), [[ROCm][FP8][Kernel] FP8 quantization fused into Custom Paged Attention](../sources/prs/vllm/PR-17139.md), [[NVIDIA] Support Cutlass w8a8 FP8 for Blackwell Geforce GPUs (sm120)](../sources/prs/vllm/PR-17280.md), [Fix noisy warning for uncalibrated q_scale/p_scale](../sources/prs/vllm/PR-17414.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [[Misc] Add compressed-tensors NVFP4A16 emulation support](../sources/prs/vllm/PR-17914.md), [use ceil_div in cutlass block scaling shape check](../sources/prs/vllm/PR-17918.md), [Use NVFP4 Marlin for CompressedTensorsW4A16Fp4](../sources/prs/vllm/PR-18000.md), [Fix Broken macro for cutlass moe](../sources/prs/vllm/PR-18049.md), [[Quantization] Add compressed-tensors NVFP4 support](../sources/prs/vllm/PR-18312.md), [[Feature] Expert Parallelism Load Balancer (EPLB)](../sources/prs/vllm/PR-18343.md), [[V1] Support `LLM.apply_model`](../sources/prs/vllm/PR-18465.md), [Sm100 blockwise fp8 swap ab](../sources/prs/vllm/PR-18564.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-18778.md), [[Kernel] Enable fp8 support for pplx and BatchedTritonExperts.](../sources/prs/vllm/PR-18864.md), [[Kernel] Support deep_gemm for linear methods](../sources/prs/vllm/PR-19085.md), [[Hardware][NVIDIA] FP4 MoE kernel optimization](../sources/prs/vllm/PR-19110.md), [[Kernels] Add activation chunking logic to FusedMoEModularKernel](../sources/prs/vllm/PR-19168.md), [[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization](../sources/prs/vllm/PR-19500.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [[Feature] Integrate new deepgemm](../sources/prs/vllm/PR-19820.md), [[Quantization] Add compressed-tensors emulations support for NVFP4](../sources/prs/vllm/PR-19879.md), [[Quantization] Add compressed-tensors NVFP4 MoE Support](../sources/prs/vllm/PR-19990.md), [[Bugfix] Build moe_data for both sm100 and sm90](../sources/prs/vllm/PR-20086.md), [ [Feature] Integrate SM100 DeepGEMM support](../sources/prs/vllm/PR-20087.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [[Bugfix] Fix topk_ids indices_type for CUTLASS w8a8 FP8 MoE](../sources/prs/vllm/PR-20166.md), [[V1] [ROCm] Enable EP with AITER Fused MoE](../sources/prs/vllm/PR-20270.md), [[Kernel][Bugfix] Fixup some warnings in nvfp4_blockwise_moe when CUDA < 12.8](../sources/prs/vllm/PR-20324.md), [[Kernel] SM90 CUTLASS FP8 GEMM: add support for swap AB + kernel tuning](../sources/prs/vllm/PR-20396.md), [[feat]: add SM100 support for cutlass FP8 groupGEMM](../sources/prs/vllm/PR-20447.md), [Support Llama 4 for cutlass_moe_fp4](../sources/prs/vllm/PR-20453.md), [Support Llama 4 for fused_marlin_moe](../sources/prs/vllm/PR-20457.md), [[Perf] Reuse workspace for FP8+FP4 Marlin MoE](../sources/prs/vllm/PR-20500.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [[fix]: disable cutlass block scaled group gemm for EP](../sources/prs/vllm/PR-20781.md), [[Bugfix] Fix a couple PPLX+CUTLASS MoE bugs](../sources/prs/vllm/PR-20825.md), [[Perf] Use Triton instead of Torch for DeepGEMM Per Token Group Quant](../sources/prs/vllm/PR-20841.md), [[Perf] Add swap_ab to SM90 FP8 non-block CUTLASS moe grouped gemm](../sources/prs/vllm/PR-20911.md), [Support mnnvl all2allv from Flashinfer](../sources/prs/vllm/PR-21003.md), [[Perf] Cuda Kernel for Per Token Group Quant](../sources/prs/vllm/PR-21083.md), [[perf] Add fused MLA QKV + strided layernorm](../sources/prs/vllm/PR-21116.md), [[Feature][OCP MX] Support mxfp6 and mixed mxfp6-mxfp4](../sources/prs/vllm/PR-21166.md), [Support CUTLASS NVFP4 (w4a4) for Blackwell Geforce GPUs (SM120)](../sources/prs/vllm/PR-21309.md), [Support Tensorrt-LLM MoE fp4 for low-latency](../sources/prs/vllm/PR-21331.md), [[Quantization] Enable BNB support for more MoE models](../sources/prs/vllm/PR-21370.md), [Update flashinfer CUTLASS NVFP4 MoE Kernel to use per expert global scaling factor](../sources/prs/vllm/PR-21408.md), [[Bug] Fix Compressed Tensor NVFP4 `cutlass_fp4_group_mm` illegal memory access](../sources/prs/vllm/PR-21465.md), [[NVIDIA] Fix Llama4 Scout FP4 functionality issues](../sources/prs/vllm/PR-21499.md), [[Kernel] Improve machete memory bound perf](../sources/prs/vllm/PR-21556.md), [[Feature] Add Flashinfer MoE Support for Compressed Tensor NVFP4](../sources/prs/vllm/PR-21639.md), [feat: Add Support GPTQ Quantization MOE on ROCM vllm serve](../sources/prs/vllm/PR-21733.md), [[Kernel] Add support for block FP8 on SM120 (NVIDIA 5090 and RTX PRO 6000)](../sources/prs/vllm/PR-22131.md), [[Bugfix] Fix MoE BNB version](../sources/prs/vllm/PR-22260.md), [[Bugfix] Add proper comparison for package versions](../sources/prs/vllm/PR-22314.md), [[gpt-oss] flashinfer mxfp4](../sources/prs/vllm/PR-22339.md), [[Bug] Fix B200 DeepGEMM E8M0 Accuracy Issue](../sources/prs/vllm/PR-22399.md), [[gpt-oss] triton kernel mxfp4](../sources/prs/vllm/PR-22421.md), [[bugfix] Fix Llama3/4 issues caused by FlashInfer 0.2.10](../sources/prs/vllm/PR-22426.md), [[Quantization]: Support compressed-tensors mixed-precision model loading](../sources/prs/vllm/PR-22468.md), [Fix Llama4 FlashInfer FP4 MoE issues](../sources/prs/vllm/PR-22511.md), [Quantization: support FP4 quantized models on AMD CDNA2/CDNA3 GPUs](../sources/prs/vllm/PR-22527.md), [[Quantization] Expand compressed-tensors MoE matching logic to support NFP4 + FP8 MoEs](../sources/prs/vllm/PR-22674.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [fp8 kv cache support fix for torch.compile](../sources/prs/vllm/PR-22758.md), [[FIXBUG] Add return_success parameter to moe_wna16_weight_loader function](../sources/prs/vllm/PR-22797.md), [[Kernel] Added flashinfer fp8 per-tensor gemms](../sources/prs/vllm/PR-22895.md), [[Fix] enable swap_ab for pplx problem size computation](../sources/prs/vllm/PR-22991.md), [Use Blackwell FlashInfer MXFP4 MoE by default if available ](../sources/prs/vllm/PR-23008.md), [[Bugfix] fix qwen3 moe fp8 accuracy issue](../sources/prs/vllm/PR-23031.md), [[Core] Support weight_loader_v2 for `UnquantizedLinearMethod`](../sources/prs/vllm/PR-23036.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [Add routed_scaling_factor to MoE grouped topk](../sources/prs/vllm/PR-23123.md), [[Bugfix] Fix accuracy issue when using flashinfer cutlass moe, TP=1 and modelopt.](../sources/prs/vllm/PR-23125.md), [Fix nvfp4 swizzling](../sources/prs/vllm/PR-23140.md), [[XPU][Feature] fp8 online quantization support for XPU](../sources/prs/vllm/PR-23148.md), [[kernel] Support W4A8 on Hopper](../sources/prs/vllm/PR-23198.md), [[Kernels] Overlap shared experts with send/recv](../sources/prs/vllm/PR-23273.md), [[Perf] Use upstream CUTLASS for SM90 Block FP8 kernel](../sources/prs/vllm/PR-23280.md), [[Bug] Fix R1 Accuracy 0 Bug](../sources/prs/vllm/PR-23294.md), [Update Flashinfer to 0.2.14.post1](../sources/prs/vllm/PR-23537.md), [DP/EP Support for gpt-oss with deepep-ht comm kernel on SM100](../sources/prs/vllm/PR-23608.md), [[Bugfix] Fix Marlin NVFP4 for modelopt](../sources/prs/vllm/PR-23659.md), [[Compile] Fix Compile Warning for `w4a8_mm_entry.cu`](../sources/prs/vllm/PR-23660.md), [[Feature] Add Hopper DeepGEMM E8M0 for DeepSeekV3.1 scale_fmt](../sources/prs/vllm/PR-23666.md), [[NVIDIA] Support SiluMul + NVFP4 quant fusion](../sources/prs/vllm/PR-23671.md), [[Bugfix][Misc] Fix silu_and_mul_nvfp4_quant issue and extract common utils for nvfp4 kernel source files](../sources/prs/vllm/PR-23727.md), [[fix]: add Arm 4bit fused moe support](../sources/prs/vllm/PR-23809.md), [[Model][gpt-oss] Support DP+EP for GPT-OSS with FlashInfer trtllm-gen MoE](../sources/prs/vllm/PR-23819.md), [[Kernel] Faster pre-processing time for W4A8](../sources/prs/vllm/PR-23972.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[BUGFIX] GPTQ quantization compatibility for Qwen3 MOE models (AutoGPTQ and AutoRound-GPTQ)](../sources/prs/vllm/PR-23994.md), [[Transform] [Quantization] Add QuTLASS support to vLLM](../sources/prs/vllm/PR-24440.md), [[Performance] Move apply_w8a8_block_fp8_linear to an op class](../sources/prs/vllm/PR-24666.md), [[NVIDIA] Blackwell Family](../sources/prs/vllm/PR-24673.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [[Bugfix] Fix accuracy issue for silu_mul + nvfp4 quant fusion kernel](../sources/prs/vllm/PR-24833.md), [[Compile] Fix Compile Warning for Ignoring `MIN_BLOCK_PER_SM`](../sources/prs/vllm/PR-25193.md), [[ROCm] Small functional changes for gptoss](../sources/prs/vllm/PR-25201.md), [Enable Fbgemm NVFP4 on Dense models](../sources/prs/vllm/PR-25609.md), [Fix INT8 quantization error on Blackwell GPUs (SM100+)](../sources/prs/vllm/PR-25935.md), [[Bugfix] Enable padded FP4 quantization](../sources/prs/vllm/PR-25947.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Bugfix] Allow skipping MoE in NVFP4 (fix for MTP)](../sources/prs/vllm/PR-25987.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [Fix undefined symbol: cutlass_moe_mm_sm100](../sources/prs/vllm/PR-26098.md), [[NVIDIA] Add support for cudnn fp4 gemm via flashinfer](../sources/prs/vllm/PR-26107.md), [[ModelOpt] Load w13/w2_input_scale for all experts, nvfp4](../sources/prs/vllm/PR-26135.md), [Move query quantization to attention layer for Flashinfer & Triton.](../sources/prs/vllm/PR-26534.md), [[Bugfix] Convert untraceable GroupShape to list for AMD impl](../sources/prs/vllm/PR-26535.md), [[ROCM] MoE fp4 CK kernel](../sources/prs/vllm/PR-26545.md), [support flashinfer_fp4 moe for 5090 gpu](../sources/prs/vllm/PR-26669.md), [[NVIDIA] [Perf] Update to leverage flashinfer trtllm FP4 MOE throughput kernel](../sources/prs/vllm/PR-26714.md), [[Bugfix] Fix gpt-oss w4a8 DP/EP on B200](../sources/prs/vllm/PR-26729.md), [[Feature] Batch Invariant: Support DeepGEMM and Blackwell](../sources/prs/vllm/PR-27127.md), [[Kernels] Enable FlashInfer FP8 Blockscale on SM90 (for TEP DSR1)](../sources/prs/vllm/PR-27134.md), [[ROCM] Enable CompressedTensorsWNA16](../sources/prs/vllm/PR-27187.md), [Flashinfer_CUTLASS_MOE fuses quantization for TP](../sources/prs/vllm/PR-27223.md), [Bugfix: Cutlass FP8 FusedMoE bad scaling factors](../sources/prs/vllm/PR-27255.md), [Feature: Support Relu2 in FusedMoE fp8 cutlass path](../sources/prs/vllm/PR-27261.md), [[Perf] SM100 - add swap AB optimization to CUTLASS FP8 GEMM](../sources/prs/vllm/PR-27284.md), [[Performance] Support FP8 flashinfer TRTLLM MOE on Qwen3 and Qwen-3next](../sources/prs/vllm/PR-27492.md), [[Feature] Batch invariant torch.compile](../sources/prs/vllm/PR-27660.md), [[Performance] Fused blockwise quant RMS norm](../sources/prs/vllm/PR-27883.md), [[Performance][B200] Fix deepgemm prologue](../sources/prs/vllm/PR-27897.md), [[Performance][B200] silu_mul_quant: pack scales in int32](../sources/prs/vllm/PR-28358.md), [[Performance] Reduce DeepGEMM N dim restriction from 128 to 64 multiplier ](../sources/prs/vllm/PR-28687.md), [[Bugfix] Fix GPT-OSS on AMD after #28603](../sources/prs/vllm/PR-28816.md), [[Bugfix] Make compressed-tensors MoEs respect ignored layers](../sources/prs/vllm/PR-28878.md), [Add TRTLLM MoE NVFP4 kernel to CompressedTensorsW4A4MoeMethod](../sources/prs/vllm/PR-28892.md), [[Feat] Support non-gated activations in NVFP4 modelopt path](../sources/prs/vllm/PR-29004.md), [[Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op)](../sources/prs/vllm/PR-29213.md), [[Kernel] Add NVFP4 MoE CUTLASS support for SM120](../sources/prs/vllm/PR-29242.md), [[Bugfix] Only use triton_kernels for MXFP4 on SM90 and SM100](../sources/prs/vllm/PR-29339.md), [[Perf] Disable DeepGEMM MoE by default when TP=8 is used](../sources/prs/vllm/PR-29346.md), [[Kernel]Support W4A8 Grouped GEMM on Hopper](../sources/prs/vllm/PR-29691.md), [[Quantization] Enable compressed-tensors AWQ for Turing GPU](../sources/prs/vllm/PR-29732.md), [[Bugfix] Fix mismatched nvfp4 gemm output shape](../sources/prs/vllm/PR-29742.md), [[MoE-FP8-modelopt] Add FlashInfer alignment padding for intermediate dimensions](../sources/prs/vllm/PR-29748.md), [[ROCm] [Fused Moe EP] Use binary expert mask for aiter fused moe kernel](../sources/prs/vllm/PR-29773.md), [[EPLB] Support EPLB w/ NVFP4](../sources/prs/vllm/PR-29804.md), [[Quantization] fix: overflow with static per-tensor scaling](../sources/prs/vllm/PR-29867.md), [[Bugfix] Fix FP8 MoE LoRA](../sources/prs/vllm/PR-29890.md), [[Kernel][Quantization][MoE] add marlin kernel support for turing (sm75)](../sources/prs/vllm/PR-29901.md), [[Perf] Do FP4 quant before All gather on flashinfer trtllmgen MOE ](../sources/prs/vllm/PR-30014.md), [[Quantization] Support Quark int4-fp8 w4a8 for MoE](../sources/prs/vllm/PR-30071.md), [[Model][Quantization] Restore MoE + GGUF models support (incl. Qwen3 MoE) by allowing Sideload Parameters](../sources/prs/vllm/PR-30116.md), [[Model][Quantization] Override HF defaults to GGUF ones (incl. Qwen3 MoE)](../sources/prs/vllm/PR-30118.md), [Add llmcompressor fp8 kv-cache quant (per-tensor and per-attn_head)](../sources/prs/vllm/PR-30141.md), [Nvidia ModelOpt workaround for issue 28072](../sources/prs/vllm/PR-30164.md), [[Bugfix]: Fix glm46 awq marlin moe wna16 compatibility](../sources/prs/vllm/PR-30210.md), [gptq marlin quantization support for fused moe with lora](../sources/prs/vllm/PR-30254.md), [[Bugfix] Fix DeepGEMM after #29546 ](../sources/prs/vllm/PR-30267.md), [[LoRA] Support Quantized Adapters](../sources/prs/vllm/PR-30286.md), [[Model][Quantization] Fix / Add GGUF support for Qwen2 MoE models](../sources/prs/vllm/PR-30307.md), [[bugfix][quantization] fix quark qwen3 kv_cache quantization](../sources/prs/vllm/PR-30308.md), [[fix] fix SM check for Flashinfer TRTLLM MOE](../sources/prs/vllm/PR-30314.md), [[Bugfix] Fix fp8 DeepGemm compilation issues](../sources/prs/vllm/PR-30336.md), [[ROCm][Quantization] GPT OSS Upstream MoE wmxfp4_afp8 with static scales](../sources/prs/vllm/PR-30357.md), [fix(gguf): Disable bfloat16 for GGUF on blackwell device](../sources/prs/vllm/PR-30408.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [[Perf] Set split_k to 1 for triton_kernels](../sources/prs/vllm/PR-30528.md), [[Perf] Eliminate padding and slicing op for GPT-OSS with Flashinfer MXFP4 MXFP8 MoE](../sources/prs/vllm/PR-30647.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [[Compressed-Tensors] Simplify NVFP4 Conditions, enable marlin support for NVFP4A16 MoEs](../sources/prs/vllm/PR-30881.md), [[Kernel][Performance] Enable smaller Scaling Factor tiling for NVFP4 small-batch decoding](../sources/prs/vllm/PR-30885.md), [[NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size](../sources/prs/vllm/PR-30897.md), [[Feature]: Support NVIDIA ModelOpt HF FP8 variants FP8_PER_CHANNEL_PER_TOKEN and FP8_PB_WO in vLLM](../sources/prs/vllm/PR-30957.md), [ [FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/vllm/PR-31099.md), [[Bugfix][Hardware][AMD] Consolidate FP8 min/max values helper function](../sources/prs/vllm/PR-31106.md), [[Misc] Fix grammar errors in comments and messages](../sources/prs/vllm/PR-31115.md), [[BugFix] add select_gemm_impl on CompressedTensorsWNA16MoEMethod to support LoRA](../sources/prs/vllm/PR-31453.md), [[Bugfix][ROCm] Fix Static Quant Issue](../sources/prs/vllm/PR-31502.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[Perf] Fuse stride preparation for NVFP4 cutlass_moe](../sources/prs/vllm/PR-31837.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [[BugFix] Fix DeepSeek-V3.1 + DeepGEMM incompatible scale shapes](../sources/prs/vllm/PR-32361.md), [[Model] Molmo2: Enable quantized weight mapping for vision backbone](../sources/prs/vllm/PR-32385.md), [[Hardware][SM100] Add TRTLLM Kernel for INT4 W4A16 Kernel.](../sources/prs/vllm/PR-32437.md), [[Perf][Kernel] Optimize FP4 quantization kernels (SM100F)](../sources/prs/vllm/PR-32520.md), [[Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper](../sources/prs/vllm/PR-32619.md), [[Bugfix][Attention] Explicitly report support for kv_cache_dtype bfloat16](../sources/prs/vllm/PR-32795.md), [[NVIDIA] [feat] Integrate flashinfer Trtllmgen bf16 moe](../sources/prs/vllm/PR-32954.md), [Support compress-tensors with nvfp4 or fp8 weights and modelopt with nvfp4 weights on Turing](../sources/prs/vllm/PR-33076.md), [Add support for Mistral Large 3 inference with Flashinfer MoE](../sources/prs/vllm/PR-33174.md), [[Bugfix] Fix quant RMS norm fusion for quantization with TMA-aligned scales](../sources/prs/vllm/PR-33255.md), [fix: Add SM120 (RTX Blackwell) support for FlashInfer CUTLASS NVFP4 MoE kernels](../sources/prs/vllm/PR-33417.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [[Kernel] Add enable_sm120_or_later for SM121 (DGX Spark) CUTLASS support](../sources/prs/vllm/PR-33517.md), [enable skipping of SW attention layers when using FP8 KV cache](../sources/prs/vllm/PR-33695.md), [[Bugfix]fix output Nan/Inf in marlin if dtype=float16](../sources/prs/vllm/PR-33972.md), [[ModelBash][DSR1 NVFp4] Avoid Bf16 Bias Cast](../sources/prs/vllm/PR-34298.md), [[Custom Ops] Add functional + out variant for scaled_fp4_quant](../sources/prs/vllm/PR-34389.md), [[Llama4,Quantization] Simplify and generalize logic for Q/K permutations in quantized self-attn layers ](../sources/prs/vllm/PR-34471.md), [[Model] Add NVFP4 quantization support for Step3.5-Flash](../sources/prs/vllm/PR-34478.md), [[Quantization] add humming quantization kernel](../sources/prs/vllm/PR-34556.md), [[Bugfix] Rescale NVFP4 weight scales to fix BF16 dequant underflow](../sources/prs/vllm/PR-34577.md), [[Bugfix] Fix MLA attention crash with AWQ/GPTQ quantized models](../sources/prs/vllm/PR-34695.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [add mixed precision support for modelopt](../sources/prs/vllm/PR-35047.md), [Integrate flashinfer mm_mxfp8 in ModelOpt MXFP8](../sources/prs/vllm/PR-35053.md), [[BUGFIX][Qwen3.5] Hardcode `mlp.gate` as not quantizable ](../sources/prs/vllm/PR-35156.md), [[BugFix] Fix fp4 quant kernel on CUDA 12.8](../sources/prs/vllm/PR-35210.md), [fix(mxfp4): return is_monolithic=False when LoRA is enabled for Triton backend](../sources/prs/vllm/PR-35382.md), [[Bugfix] Fix KV Scale loading for MLA Models](../sources/prs/vllm/PR-35430.md), [[Quant][Feature] Support online MXFP8 quantization for MoE and dense models](../sources/prs/vllm/PR-35448.md), [[NVFP4] Support NVFP4 dense models from `modelopt` and `compressed-tensors` on AMD Instinct MI300, MI355X and Hopper through emulation](../sources/prs/vllm/PR-35733.md), [[Bugfix] Fix score layer quantization for sequence classification models - Qwen3 (VL) Reranker](../sources/prs/vllm/PR-35849.md), [Add support for ModelOpt MXFP8 MoE models](../sources/prs/vllm/PR-35986.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [docs: fix wrong cc in int8.md](../sources/prs/vllm/PR-36209.md), [[Kernel] Fuse FP8 output quantization into merge_attn_states](../sources/prs/vllm/PR-36518.md), [[MoE Refactor] Mxfp4 oracle rebased](../sources/prs/vllm/PR-37128.md), [[XPU] support MLA model on Intel GPU](../sources/prs/vllm/PR-37143.md), [[MoE/EPLB] Fix FlashInfer nvfp4 experts + EPLB correctness](../sources/prs/vllm/PR-37217.md), [[Bugfix] Expand quantization method support in perf metrics](../sources/prs/vllm/PR-37231.md), [[Kernel] Add non-gated support for NVFP4 CUTLASS MoE](../sources/prs/vllm/PR-37320.md), [Add nvfp4 support to reshape_and_cache_flash](../sources/prs/vllm/PR-37332.md), [[Kernel] Add MXFP4 W4A4 CUTLASS MoE kernel for SM100](../sources/prs/vllm/PR-37463.md), [[Bugfix] Remove assertion for NVFP4 scale dynamic range](../sources/prs/vllm/PR-37465.md), [[Bugfix] Fix marlin nvfp4 rescaling](../sources/prs/vllm/PR-37502.md), [[4/n] Migrate FP4/W4A8 CUTLASS kernels to torch stable ABI](../sources/prs/vllm/PR-37503.md), [[Bug] Fix fp8 deepgemm batch invariant](../sources/prs/vllm/PR-37718.md), [[XPU] add gptq(int4) support](../sources/prs/vllm/PR-37844.md), [[Kernel] Optimize SM120 CUTLASS blockwise FP8 GEMM](../sources/prs/vllm/PR-37970.md), [[MoE Kernel] Flashinfer nvfp4 cutedsl moe kernel integration](../sources/prs/vllm/PR-38050.md), [[Perf] FP8 FlashInfer Attn for ViT](../sources/prs/vllm/PR-38065.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [[Quantization] Add FlashInfer CuteDSL batched experts backend for NVFP4 MoE](../sources/prs/vllm/PR-38251.md), [[Kernel] Add swapAB support for SM120 CUTLASS blockwise FP8 GEMM ](../sources/prs/vllm/PR-38325.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[QeRL] Fix online quantized reloading](../sources/prs/vllm/PR-38442.md), [[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity](../sources/prs/vllm/PR-38479.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[Compile] Fix nvfp4 compile warning](../sources/prs/vllm/PR-38573.md), [[Bugfix] Fix AWQ models batch invariance issues](../sources/prs/vllm/PR-38670.md), [[XPU] add xpu backend implementation of mxfp8 quant](../sources/prs/vllm/PR-38682.md), [[Quant] add CompressedTensorsW8A8Mxfp8 for linear and MoE layers](../sources/prs/vllm/PR-38815.md), [[Bugfix] Fix NVFP4+MTP crash: force unquantized mtp.fc for Qwen3.5](../sources/prs/vllm/PR-38832.md), [[Bugfix] Fix broken explicit unquantized kv cache dtype support](../sources/prs/vllm/PR-38922.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[Perf] Change Trtllm fp8 MoE to use Shuffled Weights and BlockMajorK Layout](../sources/prs/vllm/PR-38993.md), [[Quantization] - Layerwise reloading of Attention/KV quantized models](../sources/prs/vllm/PR-38995.md), [[MoE] Move GPT OSS Triton kernel experts into fused_moe/experts/](../sources/prs/vllm/PR-39007.md), [[Gemma4] Support quantized MoE ](../sources/prs/vllm/PR-39045.md), [[Bug] Fix Trtllm Fp8 MoE Weight Shuffle Memory Fragamentation](../sources/prs/vllm/PR-39054.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [[Refactor] Move NVFP4 GEMM management into NvFp4LinearKernel](../sources/prs/vllm/PR-39129.md), [[Refactor] Move MXFP8 GEMM management into MxFp8LinearKernel](../sources/prs/vllm/PR-39205.md), [[Bugfix] FlashInfer MXINT4 MoE crashes, missing do_finalize](../sources/prs/vllm/PR-39315.md), [[Feature] Batch invariant nvfp4 linear support](../sources/prs/vllm/PR-39322.md), [[Bugfix][CT] Fix KV cache scale handling](../sources/prs/vllm/PR-39418.md), [[Kernel] Support TRTLLM GEN NVFP4 MoE for non-512-aligned hidden dims via weight padding](../sources/prs/vllm/PR-39510.md), [[Perf] Fuse Zero Initializer for FP8 DeepGemm Block Quant Kernel](../sources/prs/vllm/PR-39547.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [Add nvfp4 kv cache support](../sources/prs/vllm/PR-40177.md), [[Bugfix] Guard mxfp4_experts_quant bindings on ENABLE_NVFP4_SM100](../sources/prs/vllm/PR-40191.md), [Fix MoE backend selection for LoRA (unquantized MoE)](../sources/prs/vllm/PR-40273.md), [[Perf] Batch invariance with Cutlass fp8 support, 28.9% E2E latency improvement](../sources/prs/vllm/PR-40408.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[DSV4] Add BF16 and MXFP8 A2A support for flashinfer a2a one sided](../sources/prs/vllm/PR-40960.md), [Faster per-token fp8 group quant packed kernel for blackwell](../sources/prs/vllm/PR-41326.md), [[ROCm][Quantization][3/N] Refactor quark_moe w4a4 w/ oracle](../sources/prs/vllm/PR-41436.md), [[Quantization] Rework quantization_config to use QuantKey and allow for activation override](../sources/prs/vllm/PR-41566.md), [[MXFP4] Support for linear layers + compressed-tensors integration](../sources/prs/vllm/PR-41664.md), [[CUDA][CUTLASS] Enable cutlass scaled mm for non-compatible sizes ](../sources/prs/vllm/PR-41868.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[Perf] Use 2D-grid to eliminate divmod in W8W8 group quant](../sources/prs/vllm/PR-42153.md), [Refactor AWQ Marlin MoE onto modular WNA16 oracle](../sources/prs/vllm/PR-42483.md), [[Misc] add humming to dependencies](../sources/prs/vllm/PR-42540.md), [[Bugfix] fix swiglu limit issue for humming backend + deepseek v4](../sources/prs/vllm/PR-42541.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [[Perf] Padded nvfp4 quant kernel to remove additional copy, 2.4%~5.7% e2e performance improvement](../sources/prs/vllm/PR-42774.md), [[Model Refactoring] Migrate DeepSeek V4 to vllm/models/ [1/N] ](../sources/prs/vllm/PR-43004.md), [[Kernel] (1/N) Machete - Hopper Optimized Mixed Precision Linear Kernel ](../sources/prs/vllm/PR-7174.md), [[Kernel] (2/N) Machete - Integrate into CompressedTensorsWNA16 and GPTQMarlin](../sources/prs/vllm/PR-7701.md), [[Bugfix] Fix Machete unittests failing with `NotImplementedError`](../sources/prs/vllm/PR-9218.md) | -| `sparse-attention` | [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Native Sparse Attention (NSA)](../sources/blogs/nsa.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [[None][perf] Scheme X L2-aware dispatcher and PDL launchers for sparse-attention GVR Top-K](../sources/prs/TensorRT-LLM/PR-13477.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [Add seqused_q in fwd / bwd and seqused_k in bwd in hopper FA.](../sources/prs/flash-attention/PR-1182.md), [[feat] support block sparse attention w/ variable block sizes and head-wise sparse patterns](../sources/prs/flashinfer/PR-1177.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [Native Sparse Attention (NSA)](../wiki/kernels/nsa.md), [Sparse MLA (DeepSeek V3.2)](../wiki/kernels/sparse-mla.md) | -| `topk` | [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md) | +| `scan` | [Add b200 tunings for scan.exclusive.sum](../sources/prs/cccl/PR-3559.md) | +| `sparse-attention` | [FlashMLA — Multi-head Latent Attention](../sources/blogs/flashmla.md), [Qwen3-Next: Hybrid GDN+MoE Architecture on NVIDIA Blackwell](../sources/blogs/qwen3-next-architecture.md), [DeepSeek-V3.2-Exp in vLLM: Fine-Grained Sparse Attention in Action](../sources/blogs/vllm-deepseek-v3-sparse-attention.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [Native Sparse Attention: Hardware-Aligned and Natively Trainable Sparse Attention](../sources/docs/nsa.md), [[None][perf] Scheme X L2-aware dispatcher and PDL launchers for sparse-attention GVR Top-K](../sources/prs/TensorRT-LLM/PR-13477.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [Add seqused_q in fwd / bwd and seqused_k in bwd in hopper FA.](../sources/prs/flash-attention/PR-1182.md), [[feat] support block sparse attention w/ variable block sizes and head-wise sparse patterns](../sources/prs/flashinfer/PR-1177.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [Native Sparse Attention (NSA)](../wiki/kernels/nsa.md), [DeepSeek Sparse Attention / Sparse MLA](../wiki/kernels/sparse-mla.md) | +| `topk` | [Fix debug section around line 390 of dispatch_topk](../sources/prs/cccl/PR-6152.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md) | diff --git a/queries/by-language.md b/queries/by-language.md index 7864341e7..31da8c019 100644 --- a/queries/by-language.md +++ b/queries/by-language.md @@ -4,11 +4,12 @@ | Language | Guide | Related Pages | |----------|-------|--------------| -| `cuda-cpp` | [CUDA C++ for Blackwell Kernels](../wiki/languages/cuda-cpp.md) | [Twelve Attempts at NVFP4 Batched GEMV](../sources/blogs/amandeep-nvfp4-attempts.md), [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Kernels](../sources/blogs/colfax-cutlass-kernels.md), [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md), [NVIDIA Developer Code Samples](../sources/blogs/nvidia-code-samples.md), [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [NVIDIA Blackwell Compatibility Guide](../sources/docs/blackwell-compatibility-guide.md), [Fix performance issue of m-grouped contiguous GEMMs.](../sources/prs/DeepGEMM/PR-168.md), [Fix multicast bug and optimize masked GEMM](../sources/prs/DeepGEMM/PR-193.md), [fix: use SM90ArchSpec instead of SM100ArchSpec in sm90_bf16_k_grouped_gemm](../sources/prs/DeepGEMM/PR-270.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Use swizzling instead of padding](../sources/prs/DeepGEMM/PR-86.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[None][feat] sm100 weight-only kernel](../sources/prs/TensorRT-LLM/PR-10190.md), [[TRTLLM-10022][feat] Add hopper xqa decode support for skip softmax attention](../sources/prs/TensorRT-LLM/PR-10264.md), [[https://nvbugs/5669671][fix] Support GuidedDecoder with sharded logits (pick #10698)](../sources/prs/TensorRT-LLM/PR-10742.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[None][feat] Optimize super-v3 nvfp4 for better perf](../sources/prs/TensorRT-LLM/PR-11273.md), [[None][feat] Optimize by fuse nvfp4_quant to layernorm_gated for mamba2_mixer](../sources/prs/TensorRT-LLM/PR-11473.md), [[None][feat] TRT-LLM Gen MoE finalize kernel optimization](../sources/prs/TensorRT-LLM/PR-11501.md), [[None][feat] Add support for expert_number<=2048 and K<=32](../sources/prs/TensorRT-LLM/PR-11510.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[TRTLLM-11119][feat] Blackwell SageAttention, Integrate into AttentionOp API](../sources/prs/TensorRT-LLM/PR-11718.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[None][feat] Add fused DiT QK Norm + RoPE CUDA kernel for FLUX](../sources/prs/TensorRT-LLM/PR-11869.md), [[TRTLLM-10421][perf] Add fused cat+fp8_quantize CUDA kernel for DSA indexer](../sources/prs/TensorRT-LLM/PR-11899.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[https://nvbugs/5955188][fix] Fix harmony parsers and WAR routing PDL for agentic coding use cases](../sources/prs/TensorRT-LLM/PR-12046.md), [[TRTLLM-11540][feat] Add EAGLE3 dynamic tree speculative decoding support](../sources/prs/TensorRT-LLM/PR-12062.md), [[None][feat] Minimax RMS norm optimization](../sources/prs/TensorRT-LLM/PR-12163.md), [[None][feat] Add fused allreduce+RMSNorm op and optional residual in …](../sources/prs/TensorRT-LLM/PR-12201.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[None][feat] Temporally-Correlated Heuristic-guided Indexer TopK for Sparse Attention](../sources/prs/TensorRT-LLM/PR-12385.md), [[None][perf] add Dynamic SMEM block routing in MOE](../sources/prs/TensorRT-LLM/PR-12456.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[https://nvbugs/5983390][perf] Split MLA DSA custom op for piecewise CUDA graph capture](../sources/prs/TensorRT-LLM/PR-12503.md), [[None][feat] Add Mamba2 MTP SSM cache CUDA kernel for tree-based speculative decoding](../sources/prs/TensorRT-LLM/PR-12537.md), [[https://nvbugs/5983390][perf] Multiple host perf optimizations for DSA part](../sources/prs/TensorRT-LLM/PR-12581.md), [[None][feat] Trtllm-gen FMHA JIT support](../sources/prs/TensorRT-LLM/PR-12612.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[TRTLLM-11485][feat] Feature rework: Add SageAttention refreshed kernels (attentionOp only)](../sources/prs/TensorRT-LLM/PR-12937.md), [[None][feat] Update rms_norm + fp4_qaunt kernel supporting more dim](../sources/prs/TensorRT-LLM/PR-13033.md), [[#12716][feat] Fused cross-head QK Norm + RoPE kernel for WAN](../sources/prs/TensorRT-LLM/PR-13052.md), [[None][feat] Optimize causal_conv1d prefill and decode kernels](../sources/prs/TensorRT-LLM/PR-13103.md), [[None][feat] Add FP4 residual quantization kernel without channel reo…](../sources/prs/TensorRT-LLM/PR-13117.md), [[https://nvbugs/5945047][fix] Fix cluster launch enablement for SM120 GPUs in allReduce fusion](../sources/prs/TensorRT-LLM/PR-13169.md), [[None][feat] Integrate FP4 indexer for DSA on Blackwell](../sources/prs/TensorRT-LLM/PR-13340.md), [[None][perf] Extend customMoeRouting kernel to support Qwen3.5](../sources/prs/TensorRT-LLM/PR-13433.md), [[None][perf] Scheme X L2-aware dispatcher and PDL launchers for sparse-attention GVR Top-K](../sources/prs/TensorRT-LLM/PR-13477.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[None][feat] Fuse FP8 1x128 quantize + UE8M0 scale pack on SM100](../sources/prs/TensorRT-LLM/PR-13628.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[https://nvbugs/6108841][fix] add hidden_dim=6144 router GEMM instantiation for GLM-5](../sources/prs/TensorRT-LLM/PR-13740.md), [[None][perf] Optimize DeepSeek-V4 compressor BF16 input](../sources/prs/TensorRT-LLM/PR-13761.md), [[None][fix] Plumb swiglu_limit through DeepGEMM and TRTLLMGen FP8 fused MoE](../sources/prs/TensorRT-LLM/PR-13767.md), [[None][fix] Fix fused MHC for DeepSeek-V4-Pro hidden size](../sources/prs/TensorRT-LLM/PR-13771.md), [[None][feat] Indexer topk opt](../sources/prs/TensorRT-LLM/PR-13811.md), [[None][perf] mHC fused_hc kernel optimizations + DS-V4 entry-boundary RMSNorm fold-in](../sources/prs/TensorRT-LLM/PR-13892.md), [[None][perf] Add CUDA q_b norm for DeepSeek V4](../sources/prs/TensorRT-LLM/PR-13975.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][feat] DSv4: enable GVR Heuristic Top-K for compress_ratio=4](../sources/prs/TensorRT-LLM/PR-14219.md), [[None][feat] Update the logic of FMHA JIT path](../sources/prs/TensorRT-LLM/PR-14291.md), [[None][chore] Update Claude Code agents and skills](../sources/prs/TensorRT-LLM/PR-14344.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[None][chore] Fix kernel launch param and add TRTLLM MoE backend test](../sources/prs/TensorRT-LLM/PR-7524.md), [[None][fix] Fix and add test for TRTLLM MoE backend](../sources/prs/TensorRT-LLM/PR-7755.md), [[TRTLLM-8637][feat] Optimize the routing kernel for DeepseekV3 (MoE CUTLASS backend); Add support for 384 experts (MoE TRTLLM backend)](../sources/prs/TensorRT-LLM/PR-7761.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[None][fix] support topk autotuner input for expert slot per group larger than 32](../sources/prs/TensorRT-LLM/PR-9087.md), [[None][feat] TRT-LLM Gen MoE optimize DeepSeek Fp8 activation kernel](../sources/prs/TensorRT-LLM/PR-9175.md), [[None][feat] add fp4 gemm + allreduce](../sources/prs/TensorRT-LLM/PR-9729.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [[None][feat] Fused kernels (qknormrope + moe routing) and two-model MTP support for glm4moe](../sources/prs/TensorRT-LLM/PR-9852.md), [[None][feat] Port fp4 quantization kernel optimization from FlashInfer](../sources/prs/TensorRT-LLM/PR-9854.md), [[None][feat] Adding torch ext API for FusedAddRMSNormQuant kernel](../sources/prs/TensorRT-LLM/PR-9905.md), [[TRTLLM-9493][feat] Add helixPostProcessNative kernel for cp_dim=2](../sources/prs/TensorRT-LLM/PR-9924.md), [Experimental Python cooperative algorithms](../sources/prs/cccl/PR-1973.md), [fix thread-reduce performance regression](../sources/prs/cccl/PR-2944.md), [Fix scan / sm90 perf regression ](../sources/prs/cccl/PR-3236.md), [Fix the vectorized loading of BlockLoad](../sources/prs/cccl/PR-3517.md), [Add b200 tunings for scan.exclusive.sum](../sources/prs/cccl/PR-3559.md), [Fix SM100 histogram tunings](../sources/prs/cccl/PR-3691.md), [Split Optimize Warp Reduce PR - CUB part](../sources/prs/cccl/PR-4716.md), [Add nondeterministic reduce that uses atomics](../sources/prs/cccl/PR-4961.md), [CUB - Add internal integer utils and tests (Split `WarpReduce` PR)](../sources/prs/cccl/PR-5314.md), [Combine `block_reduce_warp_reduction_nondeterministic.cuh` specialization with original deterministic one ](../sources/prs/cccl/PR-5408.md), [Add dynamic CUB dispatch for segmented_sort](../sources/prs/cccl/PR-6069.md), [[CUB] Use `BlockLoadToShared` in `DeviceMerge`](../sources/prs/cccl/PR-6077.md), [Fix debug section around line 390 of dispatch_topk](../sources/prs/cccl/PR-6152.md), [Split fixed-size segmented reduce dispatch header](../sources/prs/cccl/PR-6597.md), [Integrate decoupled lookahead warpspeed scan](../sources/prs/cccl/PR-6811.md), [Use integer promotion for `warp_reduce`](../sources/prs/cccl/PR-6819.md), [Implement new tuning API arch dispatching](../sources/prs/cccl/PR-7093.md), [Two-phase reduction for fixed size segmented reduction for very large segment sizes](../sources/prs/cccl/PR-7114.md), [Implement the new tuning API for deterministic (rfa) reduce dispatch](../sources/prs/cccl/PR-7346.md), [Radix-selection based `BlockTopK` specialization](../sources/prs/cccl/PR-7384.md), [Implement the new tuning API for `DeviceRleDispatch`](../sources/prs/cccl/PR-7669.md), [Optimize non fixed size segmented reduce for small segments using max_segment_size](../sources/prs/cccl/PR-7718.md), [Add env SegmentedReduce (non fixed-size overloads)](../sources/prs/cccl/PR-7795.md), [Forward policy hub from `dispatch_streaming_arg_reduce_t` to `reduce::dispatch`](../sources/prs/cccl/PR-7805.md), [Implement the new tuning API for `detail::reduce::dispatch_streaming_arg_reduce_t`](../sources/prs/cccl/PR-7807.md), [Use the new tuning API internally for `detail::transform::dispatch`](../sources/prs/cccl/PR-7810.md), [[Backport branch/3.3.x] Forward policy hub from `dispatch_streaming_arg_reduce_t` to `reduce::dispatch`](../sources/prs/cccl/PR-7814.md), [Optimized Device-to-Device Tensor Copy (`cudax`)](../sources/prs/cccl/PR-7823.md), [Implement the new tuning API for `DispatchSegmentedRadixSort`](../sources/prs/cccl/PR-7844.md), [Implement the new tuning API for `DispatchSegmentedSort`](../sources/prs/cccl/PR-7874.md), [Implement the new tuning API for `DispatchTopK`](../sources/prs/cccl/PR-7928.md), [[cuda.compute]: Fix faulty pointer arithmetic calculation in CUB dispatch](../sources/prs/cccl/PR-7940.md), [Reduce usage of `cub::DispatchReduce`](../sources/prs/cccl/PR-7944.md), [Use the new tuning API for `detail::radix_sort::dispatch`](../sources/prs/cccl/PR-7949.md), [Adds support for non-fundamental types via decomposer to `DeviceTopK` ](../sources/prs/cccl/PR-8040.md), [Optimized Device-to-Device Tensor Copy (cudax) - Transpose Case](../sources/prs/cccl/PR-8125.md), [Avoid passing uninitialized values to scan_op](../sources/prs/cccl/PR-8184.md), [[STF] Move unstable_unique from STF to generic cudax utility](../sources/prs/cccl/PR-8190.md), [Expose `max_segment_size` guarantee in cuda.compute](../sources/prs/cccl/PR-8284.md), [Port `thrust::min|max_element` to CUB](../sources/prs/cccl/PR-8291.md), [Implement the new tuning API for `DispatchSelectIf`](../sources/prs/cccl/PR-8311.md), [simplify dispatch segmented reduce to use latest dispatch and new tunings API](../sources/prs/cccl/PR-8332.md), [Apply some random warpspeed tunings](../sources/prs/cccl/PR-8352.md), [[cub]: implement utilities for policy selection](../sources/prs/cccl/PR-8355.md), [Replace `detail::merge::dispatch` by CUB's public API](../sources/prs/cccl/PR-8381.md), [[CUB] Replace `Shuffle(Up|Down|Index)` with cuda::device::warp_shuffle - RadixSort only](../sources/prs/cccl/PR-8395.md), [Vectorize mbarrier initialization in warpspeed scan](../sources/prs/cccl/PR-8423.md), [[thrust] Single-pass `is_partitioned` via adjacent zip_iterator](../sources/prs/cccl/PR-8427.md), [Replace `detail::merge_sort::dispatch` by CUB's public API](../sources/prs/cccl/PR-8473.md), [Replace `detail::scan::dispatch` by CUB's public API](../sources/prs/cccl/PR-8495.md), [Implement the new tuning API for `detail::batched_topk::dispatch_batched_topk`](../sources/prs/cccl/PR-8538.md), [Replace `detail::for_each::dispatch` by CUB's public API](../sources/prs/cccl/PR-8565.md), [Replace `detail::segmented_reduce::dispatch` by the public API](../sources/prs/cccl/PR-8695.md), [Use the new tuning API internally for `detail::topk::dispatch`](../sources/prs/cccl/PR-8742.md), [Use the new tuning API internally for `detail::reduce_by_key::dispatch`](../sources/prs/cccl/PR-8756.md), [Use the new tuning API internally for `detail::reduce[_nd]::dispatch[_nd]`](../sources/prs/cccl/PR-8826.md), [Fix Warpspeed scan shifted output store](../sources/prs/cccl/PR-8839.md), [[cub] Simplify arch dispatch](../sources/prs/cccl/PR-8861.md), [Use the new tuning API internally for `detail::select::dispatch` and `DeviceSelect`](../sources/prs/cccl/PR-8880.md), [[STF] Add per-handle exec_place stream resources](../sources/prs/cccl/PR-8905.md), [Use the new tuning API internally for `detail::select|three_way_partition::dispatch` and `DevicePartition`](../sources/prs/cccl/PR-8925.md), [Use the new tuning API internally for `detail::segmented_radix_sort::dispatch`](../sources/prs/cccl/PR-8927.md), [[libcu++] Always suppress C++ extensions warnings in prologue](../sources/prs/cccl/PR-9019.md), [Fix segmented radix sort benchmark segment size type](../sources/prs/cccl/PR-9039.md), [[libcu++] Fix default make_shared_resource construction](../sources/prs/cccl/PR-9044.md), [Vectorize contiguous iterators in `cub::BlockLoad`/`Store`](../sources/prs/cccl/PR-9056.md), [Improve sm90 mixed dtype kernel](../sources/prs/cutlass/PR-1883.md), [[EVT] Add support for Row/Col broadcast PtrArray](../sources/prs/cutlass/PR-2033.md), [Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2037.md), [Improvements for: Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2095.md), [Flash MLA support](../sources/prs/cutlass/PR-2130.md), [Flash MLA Support - Step 2](../sources/prs/cutlass/PR-2134.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Fix sm100 gemm wrong static constexpr that breaks compilation on Windows](../sources/prs/cutlass/PR-2167.md), [Fix SM90 beta=1 hang and stream-K launch errors](../sources/prs/cutlass/PR-2172.md), [Set EpiTile correctly when TileN is not divisible by 32](../sources/prs/cutlass/PR-2220.md), [Use cudaMemcpyAsync in gemm grouped with kRequiresPrecomputation sche…](../sources/prs/cutlass/PR-2256.md), [war to fix blackwell grouped groupwise hang](../sources/prs/cutlass/PR-2267.md), [hopper-blockwise-generalization-optimization](../sources/prs/cutlass/PR-2270.md), [Correct divmod order in example 77 (blackwell fmha)](../sources/prs/cutlass/PR-2291.md), [Handle get_masked_trip_count for small length in fmha example](../sources/prs/cutlass/PR-2292.md), [Fix epilogue::thread::Convert cannot be used with DefaultEpilogue](../sources/prs/cutlass/PR-2333.md), [[ex77] fix mla split; add fwd lse; add bwd varlen](../sources/prs/cutlass/PR-2366.md), [support fp16 accmulator for sm89 fp8 mma](../sources/prs/cutlass/PR-2378.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [fix: examples/cute/tutorial/blackwell/04_mma_tma_2sm_sm100.cu GridDim miscalculated](../sources/prs/cutlass/PR-2492.md), [DistGEMM bug fixes](../sources/prs/cutlass/PR-2713.md), [Support PDL for SM90 Array TMA GEMM](../sources/prs/cutlass/PR-2719.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [Blockscaled Ragged Contiguous Grouped Gemm for MoEs](../sources/prs/cutlass/PR-2790.md), [[Bug Fix]Bypass launch grids for SM120 Kernel with SM90 Mainloop & SM100 TileScheduler](../sources/prs/cutlass/PR-2865.md), [[cute] Add constexpr specifier to make_tiled_copy](../sources/prs/cutlass/PR-2875.md), [Fix incorrect tensor layout strides in Blackwell MMA tutorial comments](../sources/prs/cutlass/PR-2921.md), [[Cutlass gemm] Fix SM100 FP8 nosmem epilogue-fusion shape_div 'Divisibility Condition' for non-multiple-of-64 N tiles](../sources/prs/cutlass/PR-2946.md), [[Bug Fix]Set NumSplitsM to 1 when TileShapeM < 128 in sm90 fp8 blockwise scaling CollectiveMma](../sources/prs/cutlass/PR-2965.md), [Replace std::min with cute::min in sm120 blockwise scaling device functions](../sources/prs/cutlass/PR-3055.md), [Small Tile N BlockScaled GEMM + Grouped GEMM on SM12x](../sources/prs/cutlass/PR-3176.md), [Add Snake activation functor for EVT](../sources/prs/cutlass/PR-3184.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [Fix FA3 Varlen Performance regression](../sources/prs/flash-attention/PR-1361.md), [Add sorting and head swizzle to varlen scheduler](../sources/prs/flash-attention/PR-1823.md), [feat: update decode attention APIs](../sources/prs/flashinfer/PR-1007.md), [misc: fix instrument code for mla profiler](../sources/prs/flashinfer/PR-1014.md), [add multi-item scoring](../sources/prs/flashinfer/PR-1015.md), [fix: add zero init for KV tiled copy](../sources/prs/flashinfer/PR-1029.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [feat: Softmax free sampling](../sources/prs/flashinfer/PR-1035.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [fix: top_k_mask_logits hangs on -inf inputs](../sources/prs/flashinfer/PR-1050.md), [[nvidia] Add Blackwell FMHA decode kernel from TRT-LLM](../sources/prs/flashinfer/PR-1051.md), [Fix KV chunking for POD. ](../sources/prs/flashinfer/PR-1054.md), [bugfix: temporally disable split-kv in blackwell mla](../sources/prs/flashinfer/PR-1055.md), [Parameterize prefix mask call (needed by POD-Attention)](../sources/prs/flashinfer/PR-1059.md), [bugfix: adding lse output to blackwell fmha kernels](../sources/prs/flashinfer/PR-1071.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [perf: accelerate blackwell grouped gemm](../sources/prs/flashinfer/PR-1086.md), [bugfix: fix fp8 attention kernels aot compilation issue](../sources/prs/flashinfer/PR-1087.md), [comm: refactor and initialize `flashinfer.comm` module](../sources/prs/flashinfer/PR-1089.md), [feat: add trtllm all-reduce (non-MoE)](../sources/prs/flashinfer/PR-1096.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [feat: add trtllm moe_allreduce_fusion](../sources/prs/flashinfer/PR-1108.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [bugfix: Fix test and output shape of fp4 quantize](../sources/prs/flashinfer/PR-1114.md), [hotfix: fix the blackwell fmha stream](../sources/prs/flashinfer/PR-1116.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [Fix pointer dtype bug in rope](../sources/prs/flashinfer/PR-1129.md), [feat: add trtllm all-reduce fusion](../sources/prs/flashinfer/PR-1131.md), [MNNVL MoE All-to-All Support](../sources/prs/flashinfer/PR-1134.md), [fix: negative zero by type trait --> binary value](../sources/prs/flashinfer/PR-1136.md), [[feat] add unified batch attention w/ correctness tests.](../sources/prs/flashinfer/PR-1137.md), [Fix FA2 and FA3 multi-item scoring and cuda illegal memory access error](../sources/prs/flashinfer/PR-1140.md), [feat: Fused temperature online softmax kernel](../sources/prs/flashinfer/PR-1153.md), [Add more logging to TRTLLM-GEN debug trace (NFC)](../sources/prs/flashinfer/PR-1158.md), [feat: add finalize_moe_allreduce from trtllm](../sources/prs/flashinfer/PR-1159.md), [feat: nvshmem python bindings](../sources/prs/flashinfer/PR-1160.md), [feat: update non-fused moe](../sources/prs/flashinfer/PR-1161.md), [feat: enable and update all-reduce fused quantization](../sources/prs/flashinfer/PR-1164.md), [bugfix: softmax NaN results caused by large -inf masks](../sources/prs/flashinfer/PR-1178.md), [update trtllm-gen decode attention kernel launcher](../sources/prs/flashinfer/PR-1189.md), [[feat] optimize persistent batch attention perf.](../sources/prs/flashinfer/PR-1200.md), [[fix] fix BatchAttention CTA_TILE_KV mask issue](../sources/prs/flashinfer/PR-1206.md), [Fix the issue with auxillary kernel launch and grid dim calculation](../sources/prs/flashinfer/PR-1208.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [[comm] TRT-LLM's Multi-Node NVLink All-Reduce Kernel](../sources/prs/flashinfer/PR-1213.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [Enable cudnn decode and add tests for the cudnn decode kernel](../sources/prs/flashinfer/PR-1221.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [Fix missing hash in the cudnn cubin path](../sources/prs/flashinfer/PR-1227.md), [feat: Add non-causal cudnn prefill kernels](../sources/prs/flashinfer/PR-1230.md), [bugfix: support uint8_t for vec_t class template](../sources/prs/flashinfer/PR-1234.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [Patch fp8 cubin availability](../sources/prs/flashinfer/PR-1240.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [Remove sm100+ requirment for trtllm allreduce kernels](../sources/prs/flashinfer/PR-1249.md), [Reduce the JIT compilation time of gen_gemm_sm100_module](../sources/prs/flashinfer/PR-1251.md), [TRT-LLM's Multi-Node NVLink AR + fused RMSNorm kernel](../sources/prs/flashinfer/PR-1255.md), [feat: enable trtllm-gen mla MTP](../sources/prs/flashinfer/PR-1258.md), [Made AR output optional + esthetic changes](../sources/prs/flashinfer/PR-1265.md), [Bug fix: fix duplicate launch in POD](../sources/prs/flashinfer/PR-1267.md), [Add shuffle matrix flag](../sources/prs/flashinfer/PR-1272.md), [Convert scale_factor from scalar to Tensor in trt_allreduce_fusion](../sources/prs/flashinfer/PR-1284.md), [fix multiCtasKvScratchPtr misalignment issue (new one)](../sources/prs/flashinfer/PR-1286.md), [Bug fix: guard fp8 e8m0 and e2m1 compile ](../sources/prs/flashinfer/PR-1287.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [[fix] fix integer overflow in FA2 customized_mask & add buffer overflow warning.](../sources/prs/flashinfer/PR-1290.md), [refactor: Improved metainfo for trtllm-gen fmha](../sources/prs/flashinfer/PR-1292.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [add cutlass backend for mm_fp4](../sources/prs/flashinfer/PR-1296.md), [feat: Add weight layout option for trtllm-gen fused moe](../sources/prs/flashinfer/PR-1297.md), [perfix: use lightweight API to query device property](../sources/prs/flashinfer/PR-1298.md), [[Feature] SM level profiler ](../sources/prs/flashinfer/PR-1305.md), [Fix the bug of the kernel-selection heuristic in trtllm-gen](../sources/prs/flashinfer/PR-1307.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [Make Fp8 MoE routing_bias optional](../sources/prs/flashinfer/PR-1319.md), [Add blockwise-scaled FP8 GEMM via TRTLLM-Gen.](../sources/prs/flashinfer/PR-1320.md), [Optimizations for TRTLLM MNNVL Allreduce](../sources/prs/flashinfer/PR-1321.md), [feat: Add k_scale and v_scale to persistent attention ](../sources/prs/flashinfer/PR-1322.md), [feat: Support logits_soft_cap for Persistent attn; fix kv split limit](../sources/prs/flashinfer/PR-1324.md), [feat: Fused rope fp8 quantize kernel for MLA](../sources/prs/flashinfer/PR-1339.md), [fix: fix trtllm-gen mla error on new interface](../sources/prs/flashinfer/PR-1348.md), [feature: add fp4 mm using trtllm backend](../sources/prs/flashinfer/PR-1355.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [bugfix: fixed cutlass fused moe usage of FP4QuantizationSFLayout::SWIZZLED](../sources/prs/flashinfer/PR-1371.md), [bugfix: Add guard for fp4/fp8 related include headers](../sources/prs/flashinfer/PR-1376.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [feature: add cutlass as bmm_fp8 backend.](../sources/prs/flashinfer/PR-1397.md), [Fix trtllm moe launcher local_num_experts](../sources/prs/flashinfer/PR-1398.md), [fix shared memory alignment conflict in sampling.cuh](../sources/prs/flashinfer/PR-1402.md), [[bugfix] Fix compilation failure when compiling csrc/trtllm_moe_allreduce_fusion.cu](../sources/prs/flashinfer/PR-1410.md), [Fixes for Blackwell Tests](../sources/prs/flashinfer/PR-1434.md), [fix: remote redundant zero_init from trtllm-gen attn](../sources/prs/flashinfer/PR-1444.md), [Add alignment in MxFP8Quantization](../sources/prs/flashinfer/PR-1445.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [bugfix: Verify num_experts greater or equal to local_experts + offset](../sources/prs/flashinfer/PR-1469.md), [perf: add 1x4x1 cluster shape for fp8 bmm M<16 cases](../sources/prs/flashinfer/PR-1473.md), [tuner: Trtllm-gen Fp4 MoE Autotunner](../sources/prs/flashinfer/PR-1475.md), [perf: add fast path to TopPRenormProbKernel for top_p >= 1.0, significantly boosting SGLang workloads](../sources/prs/flashinfer/PR-1483.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [Perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8](../sources/prs/flashinfer/PR-1491.md), [fix: Replace cub Max/Min with cuda::maximum/minimum for cuda 13 compatibility](../sources/prs/flashinfer/PR-1500.md), [feat: integrate xqa attention backend](../sources/prs/flashinfer/PR-1503.md), [update allreduce to match trtllm](../sources/prs/flashinfer/PR-1507.md), [Support cuda<12.8 built for trtllm_allreduce_fusion.](../sources/prs/flashinfer/PR-1508.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [Fix linking errors with CUDA 13](../sources/prs/flashinfer/PR-1523.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [bugfix: Fix compile error for undefined swizzle enum.](../sources/prs/flashinfer/PR-1530.md), [bugfix: Fix Persistent kernel precision for masked output ](../sources/prs/flashinfer/PR-1533.md), [Remove cuda-python from dependency and check at runtime](../sources/prs/flashinfer/PR-1534.md), [feat: Integrate TRTLLM varlen kernel for deepseek R1 prefill ](../sources/prs/flashinfer/PR-1537.md), [fix trtllm_allreduce_fusion twoshot register problem.](../sources/prs/flashinfer/PR-1545.md), [perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute](../sources/prs/flashinfer/PR-1547.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [Add mnnvl_moe_alltoallv_prepare_without_allgather](../sources/prs/flashinfer/PR-1550.md), [bugfix: fix persistent attention kernel correctness on blackwell](../sources/prs/flashinfer/PR-1559.md), [fix: separate out fp4 lib into sm90 and sm100 versions, add oob checking in fused moe](../sources/prs/flashinfer/PR-1565.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [bugfix: fix cuda version guard macros](../sources/prs/flashinfer/PR-1571.md), [update trtllm-gen fp4 autotuner and routing](../sources/prs/flashinfer/PR-1573.md), [bugfix: update trtllm-gen gemm kernel names](../sources/prs/flashinfer/PR-1577.md), [bugfix: Fix arg passing to TORCH_CHECK and TORCH_WARN macros](../sources/prs/flashinfer/PR-1582.md), [fix: semaphoress must be at the fixed range in workspace buffer on trtllm_gen attention](../sources/prs/flashinfer/PR-1584.md), [bugfix: fix fused-temperature softmax IMA issue](../sources/prs/flashinfer/PR-1596.md), [bugfix: fix the register overflow issue for topk renorm kernels on blackwell](../sources/prs/flashinfer/PR-1597.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [feat: cutlass fp4 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1609.md), [feat: cutlass fp8 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1610.md), [bugfix: fix fp4 quantization with 8x4 scale factor layout](../sources/prs/flashinfer/PR-1611.md), [bugfix: fix merge_attention_state in BatchAttention w/ gqa-group-size in Qwen family](../sources/prs/flashinfer/PR-1614.md), [perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices](../sources/prs/flashinfer/PR-1615.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [bugfix: trtllm-gen fmha sm101 and sm100 compatibility](../sources/prs/flashinfer/PR-1631.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [Refactor Blackwell unit test scripts](../sources/prs/flashinfer/PR-1667.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [feat: Add `variant.OutputTransform()` to decode kernels](../sources/prs/flashinfer/PR-1670.md), [feat: Batch-size invariant FA2 Prefill & Decode](../sources/prs/flashinfer/PR-1675.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [Update TGV GEMM default kernel and TGV code cleanup.](../sources/prs/flashinfer/PR-1682.md), [perf: Port the separate reduce kernel mode from trtllm.](../sources/prs/flashinfer/PR-1685.md), [Support Kimi-K2 for TRT: templatize number of experts](../sources/prs/flashinfer/PR-1696.md), [Fix DeepSeek quality for TRTLLM fused MoE routing](../sources/prs/flashinfer/PR-1723.md), [bugfix: partially fix tests/test_trtllm_gen_fused_moe.py unit test failure](../sources/prs/flashinfer/PR-1724.md), [TVM: support TVM binding for GroupedGemm](../sources/prs/flashinfer/PR-1725.md), [fix: put sampling kernel launch into macro](../sources/prs/flashinfer/PR-1727.md), [fix: fix cannot import name 'cuda' from 'cuda' in CUDA13](../sources/prs/flashinfer/PR-1764.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [Masked batch nvfp4 quantization](../sources/prs/flashinfer/PR-1774.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [Bugfix: Fix data hazard in persistent reduce](../sources/prs/flashinfer/PR-1826.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [Update the routing for TRTLLMGEN to support kimi k2 and qwen](../sources/prs/flashinfer/PR-1831.md), [[Quantization] Add per-expert global scaling factor for fp4 batched quantize](../sources/prs/flashinfer/PR-1835.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [Bugfix: fix o_strides in persistent kernel ](../sources/prs/flashinfer/PR-1865.md), [Tune kernel compilation parameters for https://github.com/flashinfer-ai/flashinfer/pull/1850 ](../sources/prs/flashinfer/PR-1878.md), [feat: Add FP4 TRTLLM-Gen throughput MOE batched gemms](../sources/prs/flashinfer/PR-1882.md), [MLA RoPE + quantization fused kernel: shape generalization for MHA / GQA](../sources/prs/flashinfer/PR-1924.md), [Add layernorm op for inputs of mixed dtype](../sources/prs/flashinfer/PR-1926.md), [silu_and_mul nvfp4 quanization fusion rework](../sources/prs/flashinfer/PR-1927.md), [Feature: Support Relu2 activation in fused MoE](../sources/prs/flashinfer/PR-1954.md), [Update trtllm-gen fused moe routing kernel and add more kernels](../sources/prs/flashinfer/PR-1955.md), [Fix: Verify scales are not None for Cutlass FP8 FusedMoE](../sources/prs/flashinfer/PR-1961.md), [feat: enable deepgemm jit for fp8 block-scale on SM90](../sources/prs/flashinfer/PR-1969.md), [feat: autotune tile_tokens_dim in trtllm-gen MOE](../sources/prs/flashinfer/PR-1980.md), [fix: correct PDL parameter handling in RopeQuantize kernel](../sources/prs/flashinfer/PR-1982.md), [minor fix for xqa](../sources/prs/flashinfer/PR-1994.md), [Bugfix: Change get() -> GetDLTensorPtr() in cutlass FusedMoE validations](../sources/prs/flashinfer/PR-1995.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Feature: Support non-gated activation in cutlass fused MoE nvfp4](../sources/prs/flashinfer/PR-2011.md), [[feat] Refactor trtllmgen MOE and add Bf16 trtllmgen moe](../sources/prs/flashinfer/PR-2014.md), [[DSV3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2019.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE](../sources/prs/flashinfer/PR-2025.md), [[NVIDIA] Thor & Spark Support](../sources/prs/flashinfer/PR-2028.md), [Enable renormalize(naive) routing for fp8 per-tensor](../sources/prs/flashinfer/PR-2030.md), [use scalar for kv_scale in xqa](../sources/prs/flashinfer/PR-2033.md), [feat: Add flashinfer.rope.rope_quantize_fp8_append_paged_kv_cache (fused RoPE + Q + KV cache, supports MLA/GQA/MHA) ](../sources/prs/flashinfer/PR-2037.md), [perf: improve sampling/mask/softmax performance (part 1/2)](../sources/prs/flashinfer/PR-2044.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [Fix dtype of output scales from mnnvl_moe_alltoallv_prepare_without_allgather](../sources/prs/flashinfer/PR-2048.md), [[BUG] Fix trtllm-gen fp4 moe renormalize routing](../sources/prs/flashinfer/PR-2049.md), [Add support for topkPacked input in block-level renormalize](../sources/prs/flashinfer/PR-2051.md), [feat: add xqa mla backend](../sources/prs/flashinfer/PR-2053.md), [perf: Optimize helper max/minmax function in sampling.cuh](../sources/prs/flashinfer/PR-2058.md), [Fix moe fp8 failure for sm121](../sources/prs/flashinfer/PR-2061.md), [Fix: several bugs/issues with trtllm-gen attention kernels. ](../sources/prs/flashinfer/PR-2062.md), [perf: TRT-LLM MoE Block-FP8 activation optimization](../sources/prs/flashinfer/PR-2063.md), [feat: BF16 GEMM using CUTLASS backend for SM100](../sources/prs/flashinfer/PR-2070.md), [[Feature] Support batch prefill for POD Attention](../sources/prs/flashinfer/PR-2079.md), [enable xqa fp8 output](../sources/prs/flashinfer/PR-2081.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [refactor: pass hopper deepgemm include directory through python](../sources/prs/flashinfer/PR-2090.md), [perf: TRT-LLM Gen finalize kernel optimization](../sources/prs/flashinfer/PR-2092.md), [perf: enable pdl for cutlass fp4 gemm](../sources/prs/flashinfer/PR-2095.md), [Port TRT-LLM communication kernels to flashinfer](../sources/prs/flashinfer/PR-2102.md), [enable xqa speculative decoding](../sources/prs/flashinfer/PR-2105.md), [feat: support more head dim in RoPE kernel](../sources/prs/flashinfer/PR-2109.md), [add tensor scale input for xqa](../sources/prs/flashinfer/PR-2110.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [feature: make the LSE returned by MLA support base 2 or e #2113](../sources/prs/flashinfer/PR-2114.md), [update xqa license](../sources/prs/flashinfer/PR-2117.md), [Refactor trtllm_mnnvl_allreduce](../sources/prs/flashinfer/PR-2118.md), [perf: bunch of features and optimizations for top-k (sampling + sparse attention)](../sources/prs/flashinfer/PR-2119.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [fix flaky xqa test](../sources/prs/flashinfer/PR-2126.md), [make DeepGEMM swapAB available for linear gemm SM90](../sources/prs/flashinfer/PR-2131.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [fix xqa mha_sm90.cu](../sources/prs/flashinfer/PR-2157.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [Add data type check for deepseek fp4 moe](../sources/prs/flashinfer/PR-2165.md), [Fix for moe on sm110](../sources/prs/flashinfer/PR-2190.md), [feat: unit-test and api change, w4a8 grouped-gemm fused MoE for SM90](../sources/prs/flashinfer/PR-2193.md), [Move the run function definition out of BatchedGemmInterface](../sources/prs/flashinfer/PR-2211.md), [feat: further optimize top-k and add fused top-k page construction kernels for DSA](../sources/prs/flashinfer/PR-2215.md), [feat: Support unpadded output hidden size for trtllm_fp4_block_scale_moe](../sources/prs/flashinfer/PR-2217.md), [fix: add DeepSeek routing for Bf16xBf16 and MxIntxBf16 TRT-LLM Gen MoE](../sources/prs/flashinfer/PR-2234.md), [refactor: pull trtllm-gen batch-gemm/gemm headers from artifactory; update tma descriptor shape init](../sources/prs/flashinfer/PR-2235.md), [[feat] Integrate SGLang concat_mla_k kernel into flashinfer](../sources/prs/flashinfer/PR-2237.md), [feat: RMSNorm/Fused RMSNorm + FP8 Quantization kernels](../sources/prs/flashinfer/PR-2243.md), [Remove cudaStreamSynchronize from gemm_groupwise_sm120.cuh for CUDA graph compatibility](../sources/prs/flashinfer/PR-2244.md), [feat: Support numLocalTokens=0 for moe All-to-all](../sources/prs/flashinfer/PR-2247.md), [feat: support non-contiguous query for trtllm-gen attention backend](../sources/prs/flashinfer/PR-2254.md), [fix: support int64 IdType for RoPE part argument in `rope_quantize_fp8_append_paged_kv_cache`](../sources/prs/flashinfer/PR-2255.md), [[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding](../sources/prs/flashinfer/PR-2265.md), [[performance]optimize for nvfp4](../sources/prs/flashinfer/PR-2268.md), [feat: add GDN Attention](../sources/prs/flashinfer/PR-2276.md), [feat: IdType indices in sampling kernels](../sources/prs/flashinfer/PR-2281.md), [Selective State Update kernel (mamba)](../sources/prs/flashinfer/PR-2301.md), [[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels](../sources/prs/flashinfer/PR-2303.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [Fix: FilteredTopKUnifiedKernel read value out of length](../sources/prs/flashinfer/PR-2308.md), [[ML3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2323.md), [bugfix: fix multi-cta top-k implementation when k value is different for different row](../sources/prs/flashinfer/PR-2325.md), [[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32](../sources/prs/flashinfer/PR-2327.md), [fix: guard batchWarpReduceSum with ENABLE_FP8 to fix compilation without FP8](../sources/prs/flashinfer/PR-2328.md), [feat: expose swizzled_input_sf parameter for CUTLASS fused MOE](../sources/prs/flashinfer/PR-2330.md), [Optimize quantization function in large problem size](../sources/prs/flashinfer/PR-2343.md), [Enable fp16/bf16/f32 support for selective_state_update (mamba)](../sources/prs/flashinfer/PR-2366.md), [bugfix: hotfix of PR 2366 (mamba kernel)](../sources/prs/flashinfer/PR-2378.md), [fix: ensure each CTA processes full numHeadsQPerKv for trtllm decode kernel](../sources/prs/flashinfer/PR-2380.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [Remove cudaMalloc/Free in GDN prefill kernel](../sources/prs/flashinfer/PR-2415.md), [feat: update trtllm-gen MoE cubins](../sources/prs/flashinfer/PR-2416.md), [refactor: reduce hopper's gdn prefill compilation time and fix docstring.](../sources/prs/flashinfer/PR-2422.md), [refactor: refactoring cuda code to cute-dsl (part 1)](../sources/prs/flashinfer/PR-2428.md), [fix: Sampling: CUDA Graph fix](../sources/prs/flashinfer/PR-2432.md), [fix: Fix NaN output in mxfp8_quantize for very small input values](../sources/prs/flashinfer/PR-2441.md), [MTP for mamba ](../sources/prs/flashinfer/PR-2444.md), [bugfix: fix stub generation directory in fused_moe module](../sources/prs/flashinfer/PR-2445.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [fix: fix illegal memory access for NaN input in sampling kernels](../sources/prs/flashinfer/PR-2456.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [feat: Add MXFP8 GEMM mm_mxfp8 (cutlass)](../sources/prs/flashinfer/PR-2464.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [fix: add support check for gemm config for cutlass moe](../sources/prs/flashinfer/PR-2495.md), [Feat: Trtllm-gen MxFP8 MoE integration](../sources/prs/flashinfer/PR-2505.md), [perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead](../sources/prs/flashinfer/PR-2509.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [misc: point triton blackwell-ptxas to local cuda ptxas](../sources/prs/flashinfer/PR-2543.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [[Bugfix][comm] Fix FP4 one-shot launch config instability in trtllm_allreduce_fusion](../sources/prs/flashinfer/PR-2557.md), [Add support for the combinations of allreduce, allgather, and reducescatter](../sources/prs/flashinfer/PR-2563.md), [fix: W4A8 autotune crash in cutlass_fused_moe profiler workspace](../sources/prs/flashinfer/PR-2564.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [feat: trtllm tinygemm2 in flashinfer as bf16 routergemm](../sources/prs/flashinfer/PR-2587.md), [Mamba SSU: better automatic kernel selection + algorithm selection optionally exposed to the user.](../sources/prs/flashinfer/PR-2591.md), [[bugfix] Fix FilteredTopK overflow correctness](../sources/prs/flashinfer/PR-2605.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [[fp8_blockwise]Fix int32 overflow in TRTLLM fused MoE activation kernel](../sources/prs/flashinfer/PR-2642.md), [feat: FP32 dtype output for BF16 matmuls (CUTLASS & cuDNN)](../sources/prs/flashinfer/PR-2644.md), [int16 Block-Scaled State and Stochastic Rounding for SSU (mamba)](../sources/prs/flashinfer/PR-2645.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [feat: implement deterministic topk](../sources/prs/flashinfer/PR-2661.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [fix: reduce smem allocation for tinygemm2 kernel in SM120](../sources/prs/flashinfer/PR-2670.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add varlen and speculative decoding support to selective state update](../sources/prs/flashinfer/PR-2700.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [feat: Add support for TRTLLM MXFP8 non-gated MoE with ReLU2](../sources/prs/flashinfer/PR-2707.md), [Mamba2 SSD Combined Forward Pass (Blackwell CuTe DSL Kernel)](../sources/prs/flashinfer/PR-2709.md), [feat: Add DiT-oriented kernels where Qk (Bmm1) type can be reinterpreted into Int8 or BFloat16](../sources/prs/flashinfer/PR-2711.md), [fix: Add SM120 (RTX Blackwell desktop) support for NVFP4 MoE kernels](../sources/prs/flashinfer/PR-2725.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [misc: Update gemm/batched gemm cubins from trtllm-gen, gemm header refactor](../sources/prs/flashinfer/PR-2740.md), [[feat] Add 2048 experts and 32 Top K ](../sources/prs/flashinfer/PR-2744.md), [[feat] Add air top-p algorithm](../sources/prs/flashinfer/PR-2752.md), [feat: Add FP4 KV cache quant/dequant kernels ](../sources/prs/flashinfer/PR-2757.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [feat: FP8 output support for CUTLASS MLA paged attention](../sources/prs/flashinfer/PR-2779.md), [feat: Support padding tokens with seqlen=0 for rope+quant+kv cache update fusion kernel](../sources/prs/flashinfer/PR-2792.md), [Upgrade cutlass 4.2.1 -> 4.4.2](../sources/prs/flashinfer/PR-2798.md), [[fmha-v2] Support HND and NHD paged KV cache layouts with conditional stride handling](../sources/prs/flashinfer/PR-2799.md), [fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE](../sources/prs/flashinfer/PR-2821.md), [[Fmha] Sparse MLA decode kernel selection heuristics](../sources/prs/flashinfer/PR-2836.md), [[Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D](../sources/prs/flashinfer/PR-2841.md), [read real strides for kv and block scale](../sources/prs/flashinfer/PR-2844.md), [fix: int32 overflow in `trtllm_fp4_block_scale_moe` causing "Unsupported hidden state scale shape" for EP32+ configs](../sources/prs/flashinfer/PR-2853.md), [Add support for Relu2 in BF16 fused MoE](../sources/prs/flashinfer/PR-2864.md), [Mamba SSU: horizontal MTP kernel (+ DSTATE=96 support)](../sources/prs/flashinfer/PR-2865.md), [Fix silent bug with FP8 per tensor non-gated MoE](../sources/prs/flashinfer/PR-2882.md), [fix: snap weight_scale_vec_size to handle block_scale_interleave padding for SM120](../sources/prs/flashinfer/PR-2898.md), [feat: add MXFP8 GEMM support for SM120](../sources/prs/flashinfer/PR-2902.md), [feat(gdn): state checkpointing in chunk_gated_delta_rule](../sources/prs/flashinfer/PR-2908.md), [feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners](../sources/prs/flashinfer/PR-2914.md), [feat: add Relu2 (squared ReLU) activation support in CUTLASS MoE backend](../sources/prs/flashinfer/PR-2926.md), [fix: use float instead of double in sampling binary search to avoid FP64 bottleneck on SM103](../sources/prs/flashinfer/PR-2945.md), [Update NVSHMEM interface to use NVSHMEM4Py instead of custom bindings](../sources/prs/flashinfer/PR-2960.md), [Improved `simple` mamba SSU kernel ](../sources/prs/flashinfer/PR-2962.md), [test: xfail cuDNN FP8 prefill on Blackwell with CUDA <= 12.9](../sources/prs/flashinfer/PR-2963.md), [Add flashinfer.fused_rmsnorm_silu() with native kernel backend](../sources/prs/flashinfer/PR-2965.md), [Fused moe all-reduce routed scaling factor + quant support](../sources/prs/flashinfer/PR-2966.md), [fix: restore SM120 CUTLASS MoE tile candidate removed by #2927 (test_trtllm_cutlass_fused_moe.py)](../sources/prs/flashinfer/PR-2984.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [fix: tinygemm2 hang issue due to barrier sync](../sources/prs/flashinfer/PR-2996.md), [perf: Optimize CUTLASS MoE helper kernels for small-batch decode workloads](../sources/prs/flashinfer/PR-3014.md), [fix: extend moe alltoall top-k specializations](../sources/prs/flashinfer/PR-3021.md), [[feat] Add routing_replay_out support to MoE kernels and Python API](../sources/prs/flashinfer/PR-3024.md), [perf: Port TRT-LLM SM120/SM121 FP4 CUTLASS GEMM optimizations. Add PDL](../sources/prs/flashinfer/PR-3026.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [fused_moe: pre-filter SM89 tactics with zero occupancy on SM120 Blackwell (fix review feedback on #2764)](../sources/prs/flashinfer/PR-3032.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [Support Allreduce + Norm + Per-token Group Fp8 Quant Fusion](../sources/prs/flashinfer/PR-3059.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16](../sources/prs/flashinfer/PR-3129.md), [perf: Add no-bias path for tinygemm_bf16](../sources/prs/flashinfer/PR-3151.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [feat: DiT layer norm fusions for WAN: flashinfer.diffusion_ops](../sources/prs/flashinfer/PR-3157.md), [feat: enable glm5 router gemm](../sources/prs/flashinfer/PR-3185.md), [[Bugfix] Fix fused MoE autotuning correctness issues by filtering clusterDimZ](../sources/prs/flashinfer/PR-3227.md), [perf: optimize per-token nvfp4 quantization kernel.](../sources/prs/flashinfer/PR-3237.md), [Update moe gemm](../sources/prs/flashinfer/PR-3239.md), [Add dynamic tokens-per-page TRTLLM-GEN GQA kernels](../sources/prs/flashinfer/PR-3259.md), [Update trtllm FMHA cubins](../sources/prs/flashinfer/PR-3317.md), [[feat] Add gemma RMS AR fusion](../sources/prs/flashinfer/PR-3322.md), [checkpointing_ssu kernel: fused replay + conditional state-write for Mamba2](../sources/prs/flashinfer/PR-3324.md), [feat(cute_dsl/moe): add `moe_output_memset_inplace` dense memset wrapper](../sources/prs/flashinfer/PR-3328.md), [perf: fix the iteration bound of SWA in FA2 prefill template](../sources/prs/flashinfer/PR-714.md), [bugfix: FusedAddRMSNorm kernels might require more than 48KB shared memory when d is large.](../sources/prs/flashinfer/PR-718.md), [Align KV chunk size binary search with actual KV chunk splitting.](../sources/prs/flashinfer/PR-728.md), [Change `apply_rope_with_cos_sin_cache` to accept `cos_sin_cache`](../sources/prs/flashinfer/PR-754.md), [feat: support deepseek prefill attention shape](../sources/prs/flashinfer/PR-765.md), [bugfix: Ensure Loop Termination by Enforcing IEEE-754 Compliance in Sampling Kernels](../sources/prs/flashinfer/PR-774.md), [perf: refactor fa2 prefill template](../sources/prs/flashinfer/PR-776.md), [bugfix: drop CTA_TILE_Q=32](../sources/prs/flashinfer/PR-785.md), [bugfix: MLA decode should multiply sm_scale by math::log2e](../sources/prs/flashinfer/PR-787.md), [fix rope logic in mla decoding](../sources/prs/flashinfer/PR-793.md), [feat: support f32 attention output in FA2 template](../sources/prs/flashinfer/PR-799.md), [feat: apply sm_scale at logits instead of q in FA2 template](../sources/prs/flashinfer/PR-801.md), [perf: memory efficient deepseek mla fused page-attention kernel](../sources/prs/flashinfer/PR-804.md), [bugfix: mla page-attention kernel for different page sizes](../sources/prs/flashinfer/PR-810.md), [feat: unlocking MLA for A100](../sources/prs/flashinfer/PR-812.md), [feat: unlock MLA attention for sm89 (L40/L40s/4090)](../sources/prs/flashinfer/PR-814.md), [bugfix: bugfix on sm89 MLA](../sources/prs/flashinfer/PR-821.md), [bugfix: fix the signature of `CutlassSegmentGEMMSM90`](../sources/prs/flashinfer/PR-827.md), [perf: MLA decode kernel implemented by CuTe targeted to SM80](../sources/prs/flashinfer/PR-844.md), [misc: Remove duplicate param set in MLA kernel](../sources/prs/flashinfer/PR-850.md), [Add POD-Attention to FlashInfer](../sources/prs/flashinfer/PR-858.md), [perf: dynamic split-k for MLA](../sources/prs/flashinfer/PR-863.md), [bugfix: fix the behavior of MLA kernel when kv-length is 0](../sources/prs/flashinfer/PR-868.md), [Naive Support for Hopper FP8 Prefill Kernel with Per-Head Quantization](../sources/prs/flashinfer/PR-869.md), [perf: FlashAttention-3 style MLA PageAttention](../sources/prs/flashinfer/PR-887.md), [feat - support mla kvcache store](../sources/prs/flashinfer/PR-888.md), [perf: fix MLA split-k performance bug](../sources/prs/flashinfer/PR-898.md), [perf: tweak the pipeline design of mla kernel](../sources/prs/flashinfer/PR-901.md), [feat: flashinfer intra-kernel profiler](../sources/prs/flashinfer/PR-913.md), [feat: experimenta support of PDL](../sources/prs/flashinfer/PR-930.md), [bugfix: fix potential issues of FA3 template loading nans for PageAttention](../sources/prs/flashinfer/PR-945.md), [perf: Use 2WG pipeline design for MLA implementation on Hopper](../sources/prs/flashinfer/PR-952.md), [[TVM] Added tvm binding for sampling kernel](../sources/prs/flashinfer/PR-958.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [perf: dual pivot top-p/top-k renorm](../sources/prs/flashinfer/PR-974.md), [perf: prefetch page indices for mla kernel](../sources/prs/flashinfer/PR-991.md), [feat: SM-constraint Communication Kernels](../sources/prs/flashinfer/PR-994.md), [3rdparty: upgrade cutlass to 3.9](../sources/prs/flashinfer/PR-997.md), [ROCm SDPA: Ensure attn_mask has the same dtype with q](../sources/prs/pytorch/PR-144398.md), [Add release branch push triggers to inductor-rocm-mi300.yml](../sources/prs/pytorch/PR-149871.md), [[CUDA][avgpool2d] Fix backward launch bounds again for sm100, sm120](../sources/prs/pytorch/PR-150640.md), [[CUDA][avgpool2d] Fix backward launch bounds again for `sm100`, `sm120`](../sources/prs/pytorch/PR-150676.md), [[CUDA] Only use vec128 if CUDA version is newer than 12.8](../sources/prs/pytorch/PR-150705.md), [[ATen][CUDA] Optimize 128 bit vectorization](../sources/prs/pytorch/PR-152967.md), [Fix uint view copy (#151598)](../sources/prs/pytorch/PR-154121.md), [Fix macOS build with `USE_MPS=OFF`](../sources/prs/pytorch/PR-156932.md), [[user triton] AOT inductor support for device-side TMA](../sources/prs/pytorch/PR-157241.md), [[PowerPC] Fixed build issue for vsx vec256 complexfloat and scaled_mm_out_cpu ](../sources/prs/pytorch/PR-157422.md), [[cherry-pick][inductor][triton] Update HAS_WARP_SPEC to check triton.Config params. Update Triton Hash to top of release/3.4.x stack](../sources/prs/pytorch/PR-158646.md), [CUDA 13.0 Windows Nvidia Driver Update to 580.88](../sources/prs/pytorch/PR-162501.md), [fix cpp extension distributed warning spew](../sources/prs/pytorch/PR-162764.md), [[Graph Partition] improve custom op output alias](../sources/prs/pytorch/PR-163380.md), [[graph partition] Add way to register custom rule (#163310)](../sources/prs/pytorch/PR-163395.md), [CUDA 13.0 Warning update for supported architectures](../sources/prs/pytorch/PR-163633.md), [[Cherry-Pick] [CD] CUDA 13 specific followup changes. Remove sm50-70 From CUDA 12.6 and CUDA 12.8 builds (#162455)](../sources/prs/pytorch/PR-163764.md), [[CD] CUDA 13.0 fix preload logic to include nvidia/cu13/lib/](../sources/prs/pytorch/PR-163766.md), [Move inductor jobs 3.9->3.10](../sources/prs/pytorch/PR-163954.md), [[cuDNN][SDPA] Disable dropout for cuDNN SDPA on 9.11 - 9.13](../sources/prs/pytorch/PR-164026.md), [[AARCH64][CD][CUDA13][Triton][PTXAS] Turn on BUILD_BUNDLE_PTXAS=1 ](../sources/prs/pytorch/PR-164236.md), [CUDA 13.0 builds fix on Amazon Linux 2023](../sources/prs/pytorch/PR-164893.md), [[Graph Partition] move custom rules to inductor config (#166458)](../sources/prs/pytorch/PR-166967.md), [[Graph Partition] fix graph partition input signature for fallback kernels](../sources/prs/pytorch/PR-166985.md), [[cuDNN][SDPA][Convolution] Expose cuDNN runtime version in CUDA hooks](../sources/prs/pytorch/PR-167327.md), [[ROCm] Enable shared memory based pruning for Triton configs](../sources/prs/pytorch/PR-170190.md), [[inductor] Fix cudagraph skip for index_put_ with boolean indices, gr…](../sources/prs/pytorch/PR-170884.md), [[ROCm] Make grouped GEMM CK opt‑in via env and default to fallback path](../sources/prs/pytorch/PR-171140.md), [[cherry-pick][CUDA] Upgrade cuDNN to 9.15.1 for CUDA 13 builds ](../sources/prs/pytorch/PR-171189.md), [[cherry-pick][cuDNN][SDPA] cuDNN SDPA off-by-default for cuDNN versions < 12.9 (#171627)](../sources/prs/pytorch/PR-171895.md), [Skip modded_nanogpt model in TorchInductor benchmark](../sources/prs/pytorch/PR-172141.md), [[Graph Partition] Improve support for mutation ops](../sources/prs/pytorch/PR-172577.md), [Update inductor expected accuracy files](../sources/prs/pytorch/PR-175096.md), [[benchmark] Skip pytorch_CycleGAN_and_pix2pix from inductor benchmarks](../sources/prs/pytorch/PR-175299.md), [[release-only] Remove +ptx from cuda 13.0 builds](../sources/prs/pytorch/PR-175567.md), [[release 2.12] Apply Release only changes to 2.12 branch](../sources/prs/pytorch/PR-180470.md), [Disable kernel cutlass_mla_decode on SM103](../sources/prs/sglang/PR-10058.md), [Optimize nvfp4 block scaled gemm kernel when M is small.](../sources/prs/sglang/PR-10101.md), [fix: resolve gb200 image link](../sources/prs/sglang/PR-10343.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [Update CUTLASS. Refine KernelSchedule for fp8 (grouped) gemm.](../sources/prs/sglang/PR-10491.md), [[sgl-kernel] Optimize concat_mla_k kernel](../sources/prs/sglang/PR-10543.md), [Optimize cutlass int8 gemm kernel for large M on SM89 Ada GPU](../sources/prs/sglang/PR-10714.md), [disable sm100 for FlashMLA and fast-hadamard-transform in cuda12.6.1](../sources/prs/sglang/PR-11274.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [Improve Kernel Build Time](../sources/prs/sglang/PR-11508.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [Fixed aarch64 flash-mla](../sources/prs/sglang/PR-12009.md), [(1/n)support context parallel with deepseekv3.2-DSA](../sources/prs/sglang/PR-12065.md), [[sgl-kernel][4/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12080.md), [[sgl-kernel] clean up fa fetch in CMakeLists.txt](../sources/prs/sglang/PR-12392.md), [[Fix] `concat_mla_absorb_q_kernel` fails for long inputs](../sources/prs/sglang/PR-12453.md), [[NVIDIA] Fix CUDA arch requirement in nvfp4 cast](../sources/prs/sglang/PR-12581.md), [Support moe topk sigmoid kernel](../sources/prs/sglang/PR-13049.md), [diffusion: enable fa4 for blackwell](../sources/prs/sglang/PR-13263.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [[kernel][moe] add moe topk fast](../sources/prs/sglang/PR-13969.md), [Add new moe wna16 marlin gemm](../sources/prs/sglang/PR-14122.md), [Opt moe align block size kernel](../sources/prs/sglang/PR-14133.md), [sync attention, deepseek doc](../sources/prs/sglang/PR-14335.md), [[CPU] Implement MXFP4 Gemm kernels for intel AMX to support GPT OSS series.](../sources/prs/sglang/PR-14385.md), [Add CUDA kernel size analysis tool for sgl-kernel optimization](../sources/prs/sglang/PR-14544.md), [[sgl-kernel][Feat][B200][2/N] Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-14640.md), [[NPU][eagle3] support qwen eagle3 on NPU](../sources/prs/sglang/PR-14820.md), [[sgl-kernel][1/2] Fused qk_norm_rope for GLM4.6](../sources/prs/sglang/PR-15141.md), [Add cache for flashinfer installation](../sources/prs/sglang/PR-15153.md), [[sgl-kernel] Update flashmla to include fp8 sparse_mla optimizations](../sources/prs/sglang/PR-15242.md), [Fix warp illegal instruction in kimi k2 thinking PCG](../sources/prs/sglang/PR-15306.md), [[diffusion] Add Sage Attention 3 Support for sm 120 (RTX5090)](../sources/prs/sglang/PR-15382.md), [[sgl-kernel][6/7]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-15471.md), [[Feature] JIT Fused QK norm + qk norm clean up](../sources/prs/sglang/PR-15835.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [[Feature] add aligned_vector type for JIT kernel](../sources/prs/sglang/PR-16162.md), [Fix sgl-kernel jobs to skip when target_stage is specified](../sources/prs/sglang/PR-16308.md), [[diffusion] Fix RuntimeError in SageAttention3 on Nvidia Blackwell with Qwen-Image](../sources/prs/sglang/PR-16335.md), [[Fix]Pin mooncake version to 0.3.7.post2 in grace blackwell](../sources/prs/sglang/PR-16502.md), [[DeepSeek v3.2] Opt MTP decode cuda batch sizes and nsa implementation](../sources/prs/sglang/PR-16961.md), [Kernel: optimize decoding metadata in NSA multi-spec backend with fused kernels](../sources/prs/sglang/PR-17554.md), [Make flashMLA work on: Cu13, B300](../sources/prs/sglang/PR-17600.md), [Feature/support longcat flash lite](../sources/prs/sglang/PR-17838.md), [[Move sgl-kernel Kernel to JIT] Add JIT concat MLA kernels](../sources/prs/sglang/PR-17889.md), [[Diffsuion & JIT_kernel] QKNorm cross heads kernel](../sources/prs/sglang/PR-18073.md), [[Hicache & JIT_kernel] Support page first layout & mla jit kernel](../sources/prs/sglang/PR-18311.md), [docs: expand and update modelopt documentation](../sources/prs/sglang/PR-18479.md), [[FIX] Correct JIT kernel compilation on newer GPUs with outdated driver metadata.](../sources/prs/sglang/PR-18496.md), [Add claude skills for sgl-kernel and jit-kernel](../sources/prs/sglang/PR-18855.md), [Use single mma warp group for short q_len in FA to optimize decoding performance](../sources/prs/sglang/PR-18985.md), [[jit_kernel] Add fused_qknorm_rope JIT kernel](../sources/prs/sglang/PR-19059.md), [[DeepSeek-V3.2][JIT-kernel] Support nsa fuse store indexer k cache](../sources/prs/sglang/PR-19148.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Add compile-time 256-bit vector guard for pre-Blackwell](../sources/prs/sglang/PR-19794.md), [[JIT Kernel][Feature] Support JIT custom all reduce (rewrite as v2)](../sources/prs/sglang/PR-19880.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[diffusion] Support nvfp4 for Flux.2](../sources/prs/sglang/PR-20137.md), [fix ci by removing nvidia-cutlass-dsl-libs-base and force reinstall n…](../sources/prs/sglang/PR-20380.md), [fix(docs): correct quantization documentation (#20301)](../sources/prs/sglang/PR-20619.md), [Fix(jit): support rmsnorm for hidden_size in {64, 128, 256}](../sources/prs/sglang/PR-20661.md), [[Feature][JIT Kernel] Fused TP QK norm For Minimax](../sources/prs/sglang/PR-20673.md), [CUTLASS FP8 Blockwise GEMM improvement of SM120](../sources/prs/sglang/PR-20887.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Tiny Fix] Fix IS_BLACKWELL env var empty string warning in rerun-ut workflow](../sources/prs/sglang/PR-20957.md), [ci: run Stage A CUDA tests as stage-a-test-small-1-gpu on 5090](../sources/prs/sglang/PR-20988.md), [[Whisper] Enable CUDA graph support and timestamp for whisper model](../sources/prs/sglang/PR-21190.md), [Split pr-test.yml: extract sgl-kernel, jit-kernel, and multimodal-gen tests into separate workflow files](../sources/prs/sglang/PR-21219.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[Diffusion] Add qknorm rope fuse kernel](../sources/prs/sglang/PR-21440.md), [fix: piecewise_cuda_graph get correct qo_indptr](../sources/prs/sglang/PR-21452.md), [fix: TRT-LLM MHA CUDA illegal address with EAGLE v2 + DP attention](../sources/prs/sglang/PR-21649.md), [[jit_kernel] Optimize fused_qknorm_rope: deduplicate sincosf for interleave RoPE ](../sources/prs/sglang/PR-21654.md), [Remove flashinfer wheel cache cleanup that deletes other versions](../sources/prs/sglang/PR-21711.md), [[Feature] JIT rmsnorm update (with claude)](../sources/prs/sglang/PR-21834.md), [[Bugfix] Fix CUDA graph replay issues in trtllm_mla draft_extend](../sources/prs/sglang/PR-21987.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[diffusion] Default NVFP4 to CUTLASS and add all-model shape benchmarks](../sources/prs/sglang/PR-22091.md), [Lazy import flash_attention_v4 to avoid loading flash_attn.cute at startup](../sources/prs/sglang/PR-22306.md), [[Docker] Fix Trivy CVEs, cubin download 403s, and kernels command order](../sources/prs/sglang/PR-22322.md), [[CI/Docker] Clean up redundant flashinfer cubin downloads](../sources/prs/sglang/PR-22491.md), [[Docker] Remove flashinfer cache copy](../sources/prs/sglang/PR-22653.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [[Diffusion] Add Wan2.2 ModelOpt NVFP4 support](../sources/prs/sglang/PR-22681.md), [[Fix] Fix accuracy bug in Flashmla sparse MLA kernel](../sources/prs/sglang/PR-22723.md), [Dual MoE CUDA graph capture for lora/nolora batches](../sources/prs/sglang/PR-22809.md), [[Fix/Kernel] Add JIT rmsnorm_hf kernel to fix transformers backend MMLU accuracy regression ](../sources/prs/sglang/PR-22931.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [[feat] Init true on policy with qwen_dense](../sources/prs/sglang/PR-23961.md), [Enable PDL for various kernels in DSV32/GLM5](../sources/prs/sglang/PR-23965.md), [[VLM] Optimize Gemma4 VLM with PCG and fuse RMSNorm + residual add + scalar](../sources/prs/sglang/PR-24048.md), [Refactor device timer, clean up metrics collector, and add fwd occupancy metric](../sources/prs/sglang/PR-24197.md), [[codex] Optimize hidden-size 512 RMSNorm dispatch](../sources/prs/sglang/PR-24710.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [Support draft extend cuda graph for tokenspeed_mla attention backend](../sources/prs/sglang/PR-25489.md), [[fp8] SM90 swap-AB scaled_mm dispatch (~1.16x kernel geomean, +5.8-18.5% end-to-end)](../sources/prs/sglang/PR-25532.md), [fix (jit kernel): elementwise activation C++ error](../sources/prs/sglang/PR-25695.md), [[Codex] Remove stale DeepSeek V4 JIT kernels](../sources/prs/sglang/PR-25764.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Support cutlass Int8 gemm](../sources/prs/sglang/PR-2752.md), [upgrade cutlass v3.7.0](../sources/prs/sglang/PR-2967.md), [feat: add flashinfer as 3rdparty and use rmsnorm as example](../sources/prs/sglang/PR-3033.md), [Support sm90 Int8 gemm](../sources/prs/sglang/PR-3035.md), [support w8a8 fp8 kernel with CUTLASS](../sources/prs/sglang/PR-3047.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [support blockwise fp8 matmul kernel](../sources/prs/sglang/PR-3267.md), [fix undefined symbol cudaGetDriverEntryPointByVersion](../sources/prs/sglang/PR-3372.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [[Feature] Apply Cublas Grouped Gemm kernel](../sources/prs/sglang/PR-3629.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [Support overlapping two batches](../sources/prs/sglang/PR-4068.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [fix per_token_group_quant_fp8 illegal memory when num_groups % 16 != 0](../sources/prs/sglang/PR-4231.md), [add THIRDPARTYNOTICES for DeepGEMM](../sources/prs/sglang/PR-4272.md), [Support Blackwell Block Scale FP8 Gemm](../sources/prs/sglang/PR-4278.md), [update deepgemm](../sources/prs/sglang/PR-4284.md), [Add deepseek style fused moe group gate selection kernel](../sources/prs/sglang/PR-4530.md), [[Fix] Fix raw_bs bug when using flashinfer mla and eagle](../sources/prs/sglang/PR-4557.md), [Support fp8 gemm for blackwell](../sources/prs/sglang/PR-4558.md), [avoid cudaStreamSynchronize in DeepSeekV2AttentionMLA](../sources/prs/sglang/PR-4577.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [Support (1 <= dp < tp) in the dp attention in DeepEP](../sources/prs/sglang/PR-4770.md), [[Feat] support deepgemm for cmake](../sources/prs/sglang/PR-4864.md), [[Build] Fix cuda12.8 build error in nvfp4_scaled_mm_kernels.cu](../sources/prs/sglang/PR-4953.md), [update cutlass tag](../sources/prs/sglang/PR-5011.md), [fix deepgemm as well](../sources/prs/sglang/PR-5030.md), [support sgl-kernel on blackwell](../sources/prs/sglang/PR-5074.md), [reduce moe_align_block_size_kernel small batch mode overhead](../sources/prs/sglang/PR-5086.md), [Blackwell Cutlass MLA kernel](../sources/prs/sglang/PR-5142.md), [[1/2] Add FP8 Blockscale MoE CUTLASS kernel for Blackwell](../sources/prs/sglang/PR-5281.md), [fix: solve cu118 issue for cutlass mla](../sources/prs/sglang/PR-5331.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [chore: upgrade DeepGEMM](../sources/prs/sglang/PR-5395.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [feat: use flashinfer jit package](../sources/prs/sglang/PR-5547.md), [[2/2] Add python wrapper for CUTLASS FP8 Blockscale MoE Kernel. ](../sources/prs/sglang/PR-5694.md), [[PP] Add pipeline parallelism](../sources/prs/sglang/PR-5724.md), [cutlass 3.9 supported to improve fp8_blockwise_gemm](../sources/prs/sglang/PR-5820.md), [Add sm_120 for blackwell](../sources/prs/sglang/PR-5903.md), [chore: upgrade cutlass 3.9.2](../sources/prs/sglang/PR-6004.md), [chore: upgrade deepgemm](../sources/prs/sglang/PR-6073.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [Cutlass MLA: Disable split kv due to https://github.com/NVIDIA/cutlass/issues/2274](../sources/prs/sglang/PR-6101.md), [Upgrade CUTLASS 4.0](../sources/prs/sglang/PR-6336.md), [reduce torch.zeros overhead in moe align block size kernel](../sources/prs/sglang/PR-6369.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [Fix bug of deepseek-v3 under DP+EP mode with large batchsize/seqlen](../sources/prs/sglang/PR-6449.md), [[EP] Add cuda kernel for moe_ep_pre_reorder](../sources/prs/sglang/PR-6699.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [Correctly abort the failed grammar requests & Improve the handling of abort](../sources/prs/sglang/PR-6803.md), [[EP] Add cuda kernel for moe_ep_post_reorder](../sources/prs/sglang/PR-6837.md), [Fix AWQ Dequant and Weight Loading of deepseek v2](../sources/prs/sglang/PR-6842.md), [fix ep_moe_reorder kernel bugs](../sources/prs/sglang/PR-6858.md), [Add a CUDA kernel for fusing mapping and weighted sum for MoE.](../sources/prs/sglang/PR-6916.md), [[sgl-kernel] Add cuda kernel for moe_ep_silu_and_mul](../sources/prs/sglang/PR-6919.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [Clean up server_args.py](../sources/prs/sglang/PR-7037.md), [Tiny fix cutlass_mla_get_workspace_size stub incorrect signature](../sources/prs/sglang/PR-7057.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [feat: support compatibility between MTP and two-batch-overlap](../sources/prs/sglang/PR-7225.md), [Add CUTLASS FP8 Blockscale MoE kernel for Hopper architecture](../sources/prs/sglang/PR-7278.md), [fix: resolve blackwell deepep image issue](../sources/prs/sglang/PR-7331.md), [Fuse sorted_token_ids padding to moe_align_block_size kernel](../sources/prs/sglang/PR-7437.md), [fix: fix apply_shuffle_mul_sum](../sources/prs/sglang/PR-7444.md), [[CMake] Fix sgl-kernel CMakeLists for Blackwell](../sources/prs/sglang/PR-7543.md), [Add dsv3 router gemm kernel](../sources/prs/sglang/PR-7627.md), [Add dsv3 fused a gemm to sgl-kernel](../sources/prs/sglang/PR-7630.md), [[Feature] CUDA Green Context Support](../sources/prs/sglang/PR-7649.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [[kernel] opt moe align block kernel by block/warp scan algorithm](../sources/prs/sglang/PR-7884.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [[Fix][Ready]Fix register spilling in cutlass nvfp4 gemm kernel on Blackwell](../sources/prs/sglang/PR-8127.md), [[sgl-kernel] Opt per_token_quant_fp8 with warp reduce](../sources/prs/sglang/PR-8130.md), [[2/N]Support DeepSeek-R1 w4a8 low latency deepep](../sources/prs/sglang/PR-8464.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/sglang/PR-8818.md), [chore: support blackwell cu129 image](../sources/prs/sglang/PR-8928.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [Support trtllm_allreduce_fusion in flashinfer for cuda<12.8](../sources/prs/sglang/PR-9339.md), [[sgl-kernel] feat: Support sm120 cutlass fp8 gemm kernel](../sources/prs/sglang/PR-9403.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [Make sm100 fp8 kernels available on sm103](../sources/prs/sglang/PR-9789.md), [Make fp4_quantize kernels work on sm103](../sources/prs/sglang/PR-9807.md), [CUTLASS fp8 blockwise gemm support of sm120](../sources/prs/sglang/PR-9969.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feat] profiler support cudagraph backend](../sources/prs/tilelang/PR-1658.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add T.copy_cluster to support TMA multicast and SM-to-SM cluster copy](../sources/prs/tilelang/PR-1908.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[CUDA] Improve int4 GEMM lowering and packed codegen support](../sources/prs/tilelang/PR-2073.md), [[Bugfix] Enable `.shared::cta` in TMA copy paths only on CUDA 12.8+](../sources/prs/tilelang/PR-2087.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[CUDA] Add native SM75 MMA GEMM support for FP16, INT8 and INT4](../sources/prs/tilelang/PR-2198.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[Kernel]: Cutlass 2:4 Sparsity + FP8/Int8 Quant Support](../sources/prs/vllm/PR-10995.md), [[Kernel] Update `cutlass_scaled_mm` to support 2d group (blockwise) scaling](../sources/prs/vllm/PR-11868.md), [[Build] Only build 9.0a for scaled_mm and sparse kernels](../sources/prs/vllm/PR-12339.md), [[ROCm] Faster Custom Paged Attention kernels](../sources/prs/vllm/PR-12348.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Kernel] port sgl moe_align_block_size kernels](../sources/prs/vllm/PR-12574.md), [[Kernel][Quantization] Integrate block-quantized CUTLASS kernels for DeepSeekV3](../sources/prs/vllm/PR-12587.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [[Core][AMD] Migrate fully transparent sleep mode to ROCm platform](../sources/prs/vllm/PR-12695.md), [[Bugfix][Kernel] Fix per-token/per-channel quantization for Hopper scaled mm](../sources/prs/vllm/PR-12696.md), [[Kernel] Make rotary_embedding ops more flexible with input shape](../sources/prs/vllm/PR-12777.md), [[NVIDIA] Support nvfp4 quantization](../sources/prs/vllm/PR-12784.md), [Optimize moe_align_block_size for deepseek_v3](../sources/prs/vllm/PR-12850.md), [[Misc][Kernel]: Add GPTQAllSpark Quantization](../sources/prs/vllm/PR-12931.md), [[Kernel]Add streamK for block-quantized CUTLASS kernels](../sources/prs/vllm/PR-12978.md), [[Kernel] moe wna16 cuda kernel](../sources/prs/vllm/PR-13321.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[ROCm][MoE] mi300 mixtral8x7B perf for specific BS](../sources/prs/vllm/PR-13577.md), [[Kernel] FlashMLA integration](../sources/prs/vllm/PR-13747.md), [[Attention] MLA support for V1](../sources/prs/vllm/PR-13789.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[ROCm] Disable chunked prefill/prefix caching when running MLA on non-cuda platforms](../sources/prs/vllm/PR-13844.md), [[Attention] Flash MLA for V1](../sources/prs/vllm/PR-13867.md), [[V1] EP/TP MoE + DP Attention](../sources/prs/vllm/PR-13931.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [[Kernel] optimize performance of gptq marlin kernel when n is small](../sources/prs/vllm/PR-14138.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[Attention] FlashAttn MLA](../sources/prs/vllm/PR-14258.md), [fix minor miscalled method](../sources/prs/vllm/PR-14327.md), [[Build/BugFix] Fix hopper 12.8 build](../sources/prs/vllm/PR-14354.md), [Add cutlass support for blackwell fp8 blockwise gemm](../sources/prs/vllm/PR-14383.md), [[BugFix] Illegal Memory Access in the blockwise cutlass fp8 GEMMs](../sources/prs/vllm/PR-14396.md), [[Kernel] moe wna16 marlin kernel](../sources/prs/vllm/PR-14447.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[Attention] Flash Attention 3 - fp8](../sources/prs/vllm/PR-14570.md), [[BugFix/Build] Fix sparse kernels not getting built on hopper](../sources/prs/vllm/PR-14572.md), [[Kernel] GGUF MoE kernel](../sources/prs/vllm/PR-14613.md), [[Kernel] allow non-contiguous input for marlin kernel](../sources/prs/vllm/PR-14658.md), [[Bugfix][Kernel][CPU] Fix num_tokens in CPU rotary embedding kernel](../sources/prs/vllm/PR-14667.md), [[V1] Fully Transparent Implementation of CPU Offloading](../sources/prs/vllm/PR-15354.md), [[Kernel] Fix conflicting macro names for gguf kernels](../sources/prs/vllm/PR-15456.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [[Bugfix] fix use_atomic_add support of marlin kernel when using v1 engine](../sources/prs/vllm/PR-15946.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[ROCM] Add gfx950 to the custom attention archs](../sources/prs/vllm/PR-16034.md), [Add FlexAttention to V1](../sources/prs/vllm/PR-16078.md), [[Kernel] support merge_attn_states CUDA kernel, 3x speedup](../sources/prs/vllm/PR-16173.md), [[Hardware/NVIDIA/Kernel] [Functional Enablement] [1/N] Enable nvidia/DeepSeek-R1-FP4 Model](../sources/prs/vllm/PR-16362.md), [Allocate kv_cache with stride order](../sources/prs/vllm/PR-16605.md), [[V1] V1 FlashInfer Attention](../sources/prs/vllm/PR-16684.md), [[misc] ignore marlin_moe_wna16 local gen codes](../sources/prs/vllm/PR-16760.md), [[Kernel] GGUF MoeVec kernel](../sources/prs/vllm/PR-16780.md), [[BugFix] Accuracy fix for llama4 int4 - improperly casted scales](../sources/prs/vllm/PR-16801.md), [[Kernel] some optimizations for dense marlin and moe marlin](../sources/prs/vllm/PR-16850.md), [Update PyTorch to 2.7.0](../sources/prs/vllm/PR-16859.md), [[Kernel] Add expert_map support to Cutlass FP8 MOE](../sources/prs/vllm/PR-16861.md), [[Attention] FA3 decode perf improvement - single mma warp group support for head dim 128](../sources/prs/vllm/PR-16864.md), [Update Qwen1.5-MoE-W4A16-compressed-tensors.yaml](../sources/prs/vllm/PR-16946.md), [[ROCm][Kernel][V1] Enable AMD Radeon GPU Custom Paged Attention on v1](../sources/prs/vllm/PR-17004.md), [Fix `numel()` downcast in vllm/csrc/moe/moe_align_sum_kernels.cu +2](../sources/prs/vllm/PR-17082.md), [[ROCm][FP8][Kernel] FP8 quantization fused into Custom Paged Attention](../sources/prs/vllm/PR-17139.md), [[NVIDIA] Support Cutlass w8a8 FP8 for Blackwell Geforce GPUs (sm120)](../sources/prs/vllm/PR-17280.md), [[Misc][ROCm] Exclude `cutlass_mla_decode` for ROCm build](../sources/prs/vllm/PR-17289.md), [[Attention] MLA move o_proj q_proj into cuda-graph region](../sources/prs/vllm/PR-17484.md), [[Attention] MLA move rotary embedding to cuda-graph region](../sources/prs/vllm/PR-17668.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [[Kernel] Have rotary embeddings support tensors](../sources/prs/vllm/PR-18046.md), [Fix Broken macro for cutlass moe](../sources/prs/vllm/PR-18049.md), [[Build] Supports CUDA 12.6 and 11.8 after Blackwell Update](../sources/prs/vllm/PR-18316.md), [Sm100 blockwise fp8 swap ab](../sources/prs/vllm/PR-18564.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-18778.md), [[BugFix] FA2 MLA Accuracy Issue](../sources/prs/vllm/PR-18807.md), [[Hardware][NVIDIA] FP4 MoE kernel optimization](../sources/prs/vllm/PR-19110.md), [[V1] Use FlashInfer by default on Blackwell GPUs](../sources/prs/vllm/PR-19118.md), [[Bugfix][V1] Allow manual FlashAttention for Blackwell](../sources/prs/vllm/PR-19492.md), [[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization](../sources/prs/vllm/PR-19500.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [Only build CUTLASS MoE kernels on Hopper](../sources/prs/vllm/PR-19648.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [Fix FA2 fallback for Blackwell V1](../sources/prs/vllm/PR-19781.md), [[Bugfix] Build moe_data for both sm100 and sm90](../sources/prs/vllm/PR-20086.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [Replace `multiply_add` with `homogeneous_multiply_add` to Address Clang Template Parameter Issue](../sources/prs/vllm/PR-20142.md), [[Bugfix] Fix topk_ids indices_type for CUTLASS w8a8 FP8 MoE](../sources/prs/vllm/PR-20166.md), [[Kernel][Bugfix] Fixup some warnings in nvfp4_blockwise_moe when CUDA < 12.8](../sources/prs/vllm/PR-20324.md), [Update PyTorch to 2.8.0](../sources/prs/vllm/PR-20358.md), [[Kernel] SM90 CUTLASS FP8 GEMM: add support for swap AB + kernel tuning](../sources/prs/vllm/PR-20396.md), [[feat]: add SM100 support for cutlass FP8 groupGEMM](../sources/prs/vllm/PR-20447.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[fix]: disable cutlass block scaled group gemm for EP](../sources/prs/vllm/PR-20781.md), [[Perf] Add swap_ab to SM90 FP8 non-block CUTLASS moe grouped gemm](../sources/prs/vllm/PR-20911.md), [Support mnnvl all2allv from Flashinfer](../sources/prs/vllm/PR-21003.md), [[Kernel] Flashinfer MLA (trtllm-gen) decode kernel integration](../sources/prs/vllm/PR-21078.md), [[Perf] Cuda Kernel for Per Token Group Quant](../sources/prs/vllm/PR-21083.md), [[perf] Add fused MLA QKV + strided layernorm](../sources/prs/vllm/PR-21116.md), [[Perf] Use FlashInfer RoPE for RotaryEmbedding.forward_cuda when available](../sources/prs/vllm/PR-21126.md), [[Feature][Kernel]FusedMoE LoRA](../sources/prs/vllm/PR-21229.md), [[v1] - Mamba1 Attention Metadata](../sources/prs/vllm/PR-21249.md), [Support CUTLASS NVFP4 (w4a4) for Blackwell Geforce GPUs (SM120)](../sources/prs/vllm/PR-21309.md), [[Bugfix][CUDA] fixes CUDA FP8 kv cache dtype supported](../sources/prs/vllm/PR-21420.md), [[Bug] Fix Compressed Tensor NVFP4 `cutlass_fp4_group_mm` illegal memory access](../sources/prs/vllm/PR-21465.md), [[Kernel] Improve machete memory bound perf](../sources/prs/vllm/PR-21556.md), [[BugFix] Fix IMA FlashMLA full cuda-graph and DP + Update FlashMLA](../sources/prs/vllm/PR-21691.md), [update flashinfer to v0.2.9rc2](../sources/prs/vllm/PR-21701.md), [Fix Flashinfer CUTLASS MOE Allgather](../sources/prs/vllm/PR-21963.md), [[Kernel] Add support for block FP8 on SM120 (NVIDIA 5090 and RTX PRO 6000)](../sources/prs/vllm/PR-22131.md), [Fp8 paged attention update](../sources/prs/vllm/PR-22222.md), [Upgrade FA3 for attention sink](../sources/prs/vllm/PR-22313.md), [[Attention] FA3 Attention Sinks Perf Boost](../sources/prs/vllm/PR-22478.md), [[Fix] enable swap_ab for pplx problem size computation](../sources/prs/vllm/PR-22991.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [[V1] address post issues related to #20059 (part 1); cascade attention reenable by default](../sources/prs/vllm/PR-23046.md), [[kernel] Support W4A8 on Hopper](../sources/prs/vllm/PR-23198.md), [[Kernel] Add fused grouped_topk kernel for MoE](../sources/prs/vllm/PR-23274.md), [[Perf] Use upstream CUTLASS for SM90 Block FP8 kernel](../sources/prs/vllm/PR-23280.md), [[Compile] Fix Compile Warning SM100 Cutlass MLA](../sources/prs/vllm/PR-23287.md), [fix incompatibililty with non cuda platform for nvfp4](../sources/prs/vllm/PR-23478.md), [[Compile] Fix Compile Warning for `w4a8_mm_entry.cu`](../sources/prs/vllm/PR-23660.md), [[NVIDIA] Support SiluMul + NVFP4 quant fusion](../sources/prs/vllm/PR-23671.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [[Bugfix][Misc] Fix silu_and_mul_nvfp4_quant issue and extract common utils for nvfp4 kernel source files](../sources/prs/vllm/PR-23727.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[Kernel] cuda kernels for upcoming decode context parallel feature](../sources/prs/vllm/PR-23791.md), [[Kernel] Faster pre-processing time for W4A8](../sources/prs/vllm/PR-23972.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Kernel] Support decode context parallelism on Blackwell with CUTLASS MLA](../sources/prs/vllm/PR-24385.md), [[NVIDIA] Blackwell Family](../sources/prs/vllm/PR-24673.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [[Bugfix] Fix accuracy issue for silu_mul + nvfp4 quant fusion kernel](../sources/prs/vllm/PR-24833.md), [[Bugfix][B200] Fix `cutlass_mla` hang](../sources/prs/vllm/PR-24966.md), [Disable failing GPT-OSS Eval (Blackwell) for now](../sources/prs/vllm/PR-25107.md), [[Compile] Fix Compile Warning for Ignoring `MIN_BLOCK_PER_SM`](../sources/prs/vllm/PR-25193.md), [[Bugfix] [B200] cutlass_mla - ensure kv_split == 1 for batch size > 1](../sources/prs/vllm/PR-25509.md), [Fuse RoPE and MLA KV-cache write](../sources/prs/vllm/PR-25774.md), [Update launch_bounds_utils.h for correct compile on Multiple Cuda Arch - PTXAS out of range Warning](../sources/prs/vllm/PR-25843.md), [Fix INT8 quantization error on Blackwell GPUs (SM100+)](../sources/prs/vllm/PR-25935.md), [[Performance] Split FlashAttn attention and cache update](../sources/prs/vllm/PR-25954.md), [Fix undefined symbol: cutlass_moe_mm_sm100](../sources/prs/vllm/PR-26098.md), [[NVIDIA] [Perf] Update to leverage flashinfer trtllm FP4 MOE throughput kernel](../sources/prs/vllm/PR-26714.md), [[Attention] Tune CUTLASS MLA num_splits](../sources/prs/vllm/PR-26846.md), [[Perf] SM100 - add swap AB optimization to CUTLASS FP8 GEMM](../sources/prs/vllm/PR-27284.md), [Prefer FlashAttention MLA as default over FlashMLA](../sources/prs/vllm/PR-27363.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Performance] Fused blockwise quant RMS norm](../sources/prs/vllm/PR-27883.md), [[Kernel] Optimize rms_norm kernel](../sources/prs/vllm/PR-27931.md), [Update Flashinfer from `v0.4.1` to `v0.5.2`](../sources/prs/vllm/PR-27952.md), [[Perf][DeepSeek] Add sigmoid+bias fusion to fused_grouped_topk from TRTLLM](../sources/prs/vllm/PR-28124.md), [[Performance][B200] silu_mul_quant: pack scales in int32](../sources/prs/vllm/PR-28358.md), [[NVIDIA] Guard SM100 CUTLASS MoE macro to SM100 builds v2](../sources/prs/vllm/PR-28938.md), [chore: add RTX_PRO_6000 GLM4.6-FP8 kernel tuning](../sources/prs/vllm/PR-29240.md), [[Kernel] Add NVFP4 MoE CUTLASS support for SM120](../sources/prs/vllm/PR-29242.md), [Lora MoE Align Improvements](../sources/prs/vllm/PR-29257.md), [[Kernel][MoE] optimize `moe_align_block_size`](../sources/prs/vllm/PR-29642.md), [[Kernel]Support W4A8 Grouped GEMM on Hopper](../sources/prs/vllm/PR-29691.md), [[Perf] Improve fp8 quant in mla; replace ReduceSum with ReduceScatterSum](../sources/prs/vllm/PR-29795.md), [[Kernel][Quantization][MoE] add marlin kernel support for turing (sm75)](../sources/prs/vllm/PR-29901.md), [[Perf] Do FP4 quant before All gather on flashinfer trtllmgen MOE ](../sources/prs/vllm/PR-30014.md), [Add llmcompressor fp8 kv-cache quant (per-tensor and per-attn_head)](../sources/prs/vllm/PR-30141.md), [gptq marlin quantization support for fused moe with lora](../sources/prs/vllm/PR-30254.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [OffloadingConnector: Support kernel_block_size != block_size](../sources/prs/vllm/PR-30692.md), [[NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size](../sources/prs/vllm/PR-30897.md), [[Kernel] Add topk_sigmoid kernel](../sources/prs/vllm/PR-31246.md), [[Perf] Fuse stride preparation for NVFP4 cutlass_moe](../sources/prs/vllm/PR-31837.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[Perf][Kernel] Optimize FP4 quantization kernels (SM100F)](../sources/prs/vllm/PR-32520.md), [fix: Add glm4_moe_lite to MLA detection](../sources/prs/vllm/PR-32614.md), [[Attention] FA4 integration](../sources/prs/vllm/PR-32974.md), [[Feature] Support CPU Offloading without Pytorch Pinned Memory that leads to doubled allocation](../sources/prs/vllm/PR-32993.md), [[Kernel] Apply 256bit LDG/STG To Activation Kernels](../sources/prs/vllm/PR-33022.md), [Add support for Mistral Large 3 inference with Flashinfer MoE](../sources/prs/vllm/PR-33174.md), [[Bugfix] Fix quant RMS norm fusion for quantization with TMA-aligned scales](../sources/prs/vllm/PR-33255.md), [[Kernel] Add enable_sm120_or_later for SM121 (DGX Spark) CUTLASS support](../sources/prs/vllm/PR-33517.md), [[Feature][Core] Support Fabric detection to adapt the MNNVL protocol for the GB series](../sources/prs/vllm/PR-33540.md), [[Bugfix]fix output Nan/Inf in marlin if dtype=float16](../sources/prs/vllm/PR-33972.md), [Reapply [Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-34043.md), [fix(cpu): fix mla_decode compilation on x86 without AVX512](../sources/prs/vllm/PR-34052.md), [[Kernel] Optimize grouped topk kernel](../sources/prs/vllm/PR-34206.md), [[ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup)](../sources/prs/vllm/PR-34302.md), [[Bugfix] Enforce DeepGEMM when using sparse_attn_indexer on CUDA](../sources/prs/vllm/PR-34374.md), [[Custom Ops] Add functional + out variant for scaled_fp4_quant](../sources/prs/vllm/PR-34389.md), [[Kernel] Integrate SM100 MXFP8 blockscaled grouped MM and quant kernels](../sources/prs/vllm/PR-34448.md), [[Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup)](../sources/prs/vllm/PR-34758.md), [[Bugfix] Gate 256-bit instructions to CUDA 12.9+](../sources/prs/vllm/PR-34791.md), [[Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2](../sources/prs/vllm/PR-34917.md), [[Model Runner V2] Support attention group](../sources/prs/vllm/PR-35036.md), [[Performance] Cublas Bf16 Gate with Fp32 Output](../sources/prs/vllm/PR-35121.md), [[Bugfix] Fix DSV3 kernels breaking _C and _moe_C on unsupported arches](../sources/prs/vllm/PR-35123.md), [[Bugfix] Fix expert_ids padding values in moe_align_block_size kernel](../sources/prs/vllm/PR-35161.md), [[BugFix] Fix fp4 quant kernel on CUDA 12.8](../sources/prs/vllm/PR-35210.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[Attention][Perf] Optimize cp_gather_and_upconvert_fp8_kv_cache - DeepSeek-v3.2](../sources/prs/vllm/PR-35290.md), [[Kernel] Add FlashInfer MoE A2A Kernel](../sources/prs/vllm/PR-36022.md), [Add 320 dimension size support to MLA](../sources/prs/vllm/PR-36161.md), [docs: fix wrong cc in int8.md](../sources/prs/vllm/PR-36209.md), [[Kernel] Fuse FP8 output quantization into merge_attn_states](../sources/prs/vllm/PR-36518.md), [Update Flashinfer to 0.6.6](../sources/prs/vllm/PR-36768.md), [[MTP][Sparse MLA] Take advantage of native MTP support in indexer when possible](../sources/prs/vllm/PR-36982.md), [[Kernel] Add gpt-oss Router GEMM kernel](../sources/prs/vllm/PR-37205.md), [[UX] Add flashinfer-cubin as CUDA default dep](../sources/prs/vllm/PR-37233.md), [[Perf] Set Flashinfer sparse MLA as default backend for FP8 kv cache](../sources/prs/vllm/PR-37252.md), [[Kernel] Add non-gated support for NVFP4 CUTLASS MoE](../sources/prs/vllm/PR-37320.md), [Add nvfp4 support to reshape_and_cache_flash](../sources/prs/vllm/PR-37332.md), [[torch.compile] Refactor Attention Quant Fusion Pass and Remove Boilerplate](../sources/prs/vllm/PR-37373.md), [[Perf][Kernel] Persistent TopK scheduler: unified CUDAGraph-safe kernel with dynamic per-row dispatch - DeepSeek-V3.2 DSA decode](../sources/prs/vllm/PR-37421.md), [[Kernel] Add MXFP4 W4A4 CUTLASS MoE kernel for SM100](../sources/prs/vllm/PR-37463.md), [[4/n] Migrate FP4/W4A8 CUTLASS kernels to torch stable ABI](../sources/prs/vllm/PR-37503.md), [refactor: abstract deepgemm support into platform](../sources/prs/vllm/PR-37519.md), [[Bugfix] Preserve CUDA arch suffix (a/f) for SM12x — fixes NVFP4 NaN on desktop Blackwell](../sources/prs/vllm/PR-37725.md), [[Kernel] Optimize SM120 CUTLASS blockwise FP8 GEMM](../sources/prs/vllm/PR-37970.md), [[Kernel] Add swapAB support for SM120 CUTLASS blockwise FP8 GEMM ](../sources/prs/vllm/PR-38325.md), [[CI Bugfix] Pre-download missing FlashInfer headers in Docker build](../sources/prs/vllm/PR-38391.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[Perf] Batch KV cache swap copies via cuMemcpyBatchAsync](../sources/prs/vllm/PR-38460.md), [[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity](../sources/prs/vllm/PR-38479.md), [[Compile] Fix nvfp4 compile warning](../sources/prs/vllm/PR-38573.md), [[FA4] Update flash-attention to latest upstream FA4](../sources/prs/vllm/PR-38690.md), [[Refactor] Improve indexer decode path metadata preparation](../sources/prs/vllm/PR-38865.md), [[Bugfix] Fix broken explicit unquantized kv cache dtype support](../sources/prs/vllm/PR-38922.md), [[Bugfix] Fix GDN FLA kernel crashes with NULL_BLOCK_ID=0 CUDA graph padding](../sources/prs/vllm/PR-39064.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [perf(moe): add tuned fused_moe config for RTX PRO 6000 Blackwell Server Edition](../sources/prs/vllm/PR-39183.md), [Use CU_MEMCPY_SRC_ACCESS_ORDER_ANY for batch KV cache swaps](../sources/prs/vllm/PR-39306.md), [Fix NUMA binding on non-CDMM Grace-Blackwell systems](../sources/prs/vllm/PR-39361.md), [fix: clamp NaN/Inf in topk_softmax to prevent duplicate expert IDs](../sources/prs/vllm/PR-39391.md), [[Perf] Fuse Zero Initializer for FP8 DeepGemm Block Quant Kernel](../sources/prs/vllm/PR-39547.md), [[Bugfix] Add Marlin kernel in block scaled mm kernel selection.](../sources/prs/vllm/PR-40105.md), [[Bugfix] moe lora align kernel grid](../sources/prs/vllm/PR-40131.md), [[Bugfix] Guard mxfp4_experts_quant bindings on ENABLE_NVFP4_SM100](../sources/prs/vllm/PR-40191.md), [[Performance][DSR1]: Fused RoPE+KVCache+q_concat for MLA](../sources/prs/vllm/PR-40392.md), [[Perf] Batch invariance with Cutlass fp8 support, 28.9% E2E latency improvement](../sources/prs/vllm/PR-40408.md), [[GDN] Enable FI Blackwell GDN prefill kernel](../sources/prs/vllm/PR-40717.md), [[DSV4] Add silu clamp limit to shared expert](../sources/prs/vllm/PR-40950.md), [[DSV4] Fuse norm and router for low latency scenario](../sources/prs/vllm/PR-41263.md), [Faster per-token fp8 group quant packed kernel for blackwell](../sources/prs/vllm/PR-41326.md), [[Bugfix] Fix condition to clear persistent topk so that it can be captured regardless](../sources/prs/vllm/PR-41665.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[CUDA][CUTLASS] Enable cutlass scaled mm for non-compatible sizes ](../sources/prs/vllm/PR-41868.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Perf] Use 2D-grid to eliminate divmod in W8W8 group quant](../sources/prs/vllm/PR-42153.md), [[Misc] add humming to dependencies](../sources/prs/vllm/PR-42540.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [[Refactor] Remove dead cuda kernels](../sources/prs/vllm/PR-42767.md), [[Perf] Padded nvfp4 quant kernel to remove additional copy, 2.4%~5.7% e2e performance improvement](../sources/prs/vllm/PR-42774.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [[Kernel] (1/N) Machete - Hopper Optimized Mixed Precision Linear Kernel ](../sources/prs/vllm/PR-7174.md), [[Kernel] (2/N) Machete - Integrate into CompressedTensorsWNA16 and GPTQMarlin](../sources/prs/vllm/PR-7701.md), [[Bugfix] Fix Machete unittests failing with `NotImplementedError`](../sources/prs/vllm/PR-9218.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [FP8 Block-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [Fused MoE — FP8 Block-Scale Routing + Dual GEMM](../wiki/kernels/fused-moe.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [Gated Dual GEMM (Gate-Up + SwiGLU Fusion)](../wiki/kernels/gated-dual-gemm.md), [Grouped GEMM for MoE](../wiki/kernels/grouped-gemm.md), [NVFP4 GEMM — 4-bit Floating Point Matrix Multiply](../wiki/kernels/nvfp4-gemm.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md), [Sparse MLA (DeepSeek V3.2)](../wiki/kernels/sparse-mla.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md), [CCCL CUB Memory Primitives For Selection And Scan](../wiki/techniques/cccl-memory-primitives.md), [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md) | -| `cute-dsl` | [CuTe DSL for Blackwell](../wiki/languages/cute-dsl.md) | [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Tutorial: GEMM Kernels Using Tensor Memory for Blackwell](../sources/blogs/colfax-cutlass-blackwell.md), [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [simveit effective_transpose](../sources/blogs/simveit-effective-transpose.md), [simveit load_and_store](../sources/blogs/simveit-load-and-store.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA CUTLASS 4.x Blackwell Support](../sources/docs/nvidia-cutlass-blackwell.md), [[None][perf] Add more optimization options for MOE CuteDSL finalized kernel](../sources/prs/TensorRT-LLM/PR-10042.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [[None][feat] CuteDSL MOE FC1 Enhancement](../sources/prs/TensorRT-LLM/PR-10088.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [[TRTLLM-10147][perf] Balanced random MoE workload generator for CuteDSL kernel UT, autotuner and layerwise benchmark](../sources/prs/TensorRT-LLM/PR-10279.md), [[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.](../sources/prs/TensorRT-LLM/PR-10339.md), [[None] [feat] Add test script and raster M for gather fc1 kernel](../sources/prs/TensorRT-LLM/PR-10429.md), [[TRTLLM-10276][feat] Integrate cutedsl argmax kernel](../sources/prs/TensorRT-LLM/PR-10476.md), [[None] [feat] Add densegemm backend for MoE](../sources/prs/TensorRT-LLM/PR-10479.md), [[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth](../sources/prs/TensorRT-LLM/PR-10987.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[https://nvbugs/5854860][fix] Fix cutedsl argmax on sm120](../sources/prs/TensorRT-LLM/PR-11181.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[TRTLLM-11092][feat] add support for visual gen FA4 attention backend](../sources/prs/TensorRT-LLM/PR-11697.md), [[https://nvbugs/5885070][fix] fix deepeplowlatency with cutedsl moe backend](../sources/prs/TensorRT-LLM/PR-11769.md), [[TRTLLM-10990][feat] Fuse SwiGLU and quant into shared expert](../sources/prs/TensorRT-LLM/PR-11897.md), [[TRTLLM-10407][feat] Integrate CuTE DSL top-k kernel for Blackwell](../sources/prs/TensorRT-LLM/PR-11900.md), [[TRTLLM-11289][feat] Integrate CuteDSL's bf16 dense GEMMs](../sources/prs/TensorRT-LLM/PR-12074.md), [[None][feat] CuteDSL MOE: Add raster along M/N support for blockscaled contiguous backbone kernel](../sources/prs/TensorRT-LLM/PR-12079.md), [[None][feat] Add DWDP (Distributed Weight Data Parallelism) support for MoE inference](../sources/prs/TensorRT-LLM/PR-12136.md), [[TRTLLM-10407][perf] Enable CuteDSL indexer_top_k in model](../sources/prs/TensorRT-LLM/PR-12236.md), [[TRTLLM-10407][perf] Add cute dsl single pass multi cta cluster topk](../sources/prs/TensorRT-LLM/PR-12354.md), [[None][feat] Add PDL support to CuTE DSL top-k kernels](../sources/prs/TensorRT-LLM/PR-12506.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[TRTLLM-11797][feat] Add cutedsl moe backend supporting for qwen3.5.](../sources/prs/TensorRT-LLM/PR-12799.md), [[TRTLLM-11585][feat] Add CUTEDSL moe backend for nemotron-h](../sources/prs/TensorRT-LLM/PR-12884.md), [[TRTLLM-34871][feat] Add cute dsl FP8 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13219.md), [[None][perf] FC2 DenseGEMM autotune: split-K, swap_ab, fine-grained tuning buckets](../sources/prs/TensorRT-LLM/PR-13833.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] Enable EPLB for trtllm-gen and cutlass backend](../sources/prs/TensorRT-LLM/PR-8886.md), [[TRTLLM-9685] [feat] Add gather fc1 kernel by cuteDSL](../sources/prs/TensorRT-LLM/PR-9618.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [fix gqa issue for blackwell fmha.py](../sources/prs/cutlass/PR-2599.md), [Add tutorial fp16_gemm_1](../sources/prs/cutlass/PR-2750.md), [new example with TMA prefetch feature targeting for DRAM latency boun…](../sources/prs/cutlass/PR-2881.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [[Cute-DSL] Add option for issue_clc_query without multicast](../sources/prs/cutlass/PR-3021.md), [[Hopper CuTeDSL] Add grouped GEMM kernel example](../sources/prs/cutlass/PR-3091.md), [[CLI] add cutedsl fp16 gemm tutorial from 2 to 6](../sources/prs/cutlass/PR-3106.md), [Update blackwell tutorial to be compatible with 4.5-dev version](../sources/prs/cutlass/PR-3130.md), [feat: Adding varlen support to cute-dsl sm80 bwd](../sources/prs/flash-attention/PR-1934.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [[Cute,Flex,Fwd] Allow vectorized score_mod definitions](../sources/prs/flash-attention/PR-2236.md), [[Cute,Sm100,Fwd] add MLA 64/512 with topk sparsity for MQA 128 heads](../sources/prs/flash-attention/PR-2441.md), [feat: masked layout fp4 gemm using cute-dsl](../sources/prs/flashinfer/PR-1331.md), [Add python API for masked grouped gemm](../sources/prs/flashinfer/PR-1481.md), [fix: update cutedsl masked moe gemm](../sources/prs/flashinfer/PR-1488.md), [fix: update masked moe gemm fp4 tensor reshape](../sources/prs/flashinfer/PR-1495.md), [feat: scaling at fp4 gemm epilogue](../sources/prs/flashinfer/PR-1498.md), [Add benchmark for cutedsl gemm](../sources/prs/flashinfer/PR-1502.md), [bugfix: Fix stream handling in cutedsl gemm](../sources/prs/flashinfer/PR-1509.md), [refactor fp4 masked gemm cute-dsl implementation and add manual cache](../sources/prs/flashinfer/PR-1521.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [Support output signals for overlapping for cutedsl gemm](../sources/prs/flashinfer/PR-1677.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [fix: fix cannot import name 'cuda' from 'cuda' in CUDA13](../sources/prs/flashinfer/PR-1764.md), [tests: upgrade cutlass, fix import and skip non-SM100 cutedsl two shot allreduce](../sources/prs/flashinfer/PR-1812.md), [raise error for group_gemm_fp8_nt_groupwise then num_groups > 1 on sm120/121](../sources/prs/flashinfer/PR-1862.md), [enable sm103 moe dsl backend](../sources/prs/flashinfer/PR-2149.md), [Fix gemm allreduce two shot](../sources/prs/flashinfer/PR-2171.md), [feat: Fused RMSNorm + FP4 Quantization Kernels in CuTe-DSL](../sources/prs/flashinfer/PR-2233.md), [fix: Add global scale support and optional output allocation for RMSNorm+FP4Quant fusion kernels](../sources/prs/flashinfer/PR-2260.md), [[WIP] Refactor: simplify torch -> cute-dsl boilerplate and enable tvm-ffi for cute-dsl kernels](../sources/prs/flashinfer/PR-2279.md), [fix: In-place Residual Update for add_rmsnorm_fp4quant](../sources/prs/flashinfer/PR-2385.md), [feat: Add output_both_sf_layouts option to add_rmsnorm_fp4quant API](../sources/prs/flashinfer/PR-2395.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [perf: improve gdn decode cute-dsl kernels](../sources/prs/flashinfer/PR-2405.md), [refactor: simplify fp4 rmsnorm](../sources/prs/flashinfer/PR-2421.md), [refactor: refactoring cuda code to cute-dsl (part 1)](../sources/prs/flashinfer/PR-2428.md), [Add cute-dsl backends to mxfp[8,4]_quantization for future refactor](../sources/prs/flashinfer/PR-2443.md), [Ameyn/gdn decode cutedsl kernel](../sources/prs/flashinfer/PR-2498.md), [refactor: Port upstream CUTLASS fixes and refactor grouped_gemm_nt_masked GEMM module location](../sources/prs/flashinfer/PR-2503.md), [[Bug] Fix spark unit test failures for test_add_rmsnorm_fp4_quant_cute_dsl](../sources/prs/flashinfer/PR-2573.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [feat: support mxfp4 & mxfp8 entrypoint for blackwell cutedsl dense gemm](../sources/prs/flashinfer/PR-2660.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [CuteDSL MoE fix redundant output buffer zeroing](../sources/prs/flashinfer/PR-2811.md), [feat: Add CuTe-DSL backend for NVFP4 quantization](../sources/prs/flashinfer/PR-2838.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels](../sources/prs/flashinfer/PR-2904.md), [feat: Add CuTe DSL grouped-gemm + combine fusion support](../sources/prs/flashinfer/PR-2944.md), [feat: add PDL support to rmsnorm_fp4quant and add_rmsnorm_fp4quant CuTe DSL kernels](../sources/prs/flashinfer/PR-3008.md), [Prevent MoE autotuner buffer overflow on large token buckets](../sources/prs/flashinfer/PR-3025.md), [feat: Add backend="b12x" for mm_fp4 on SM120](../sources/prs/flashinfer/PR-3051.md), [feat: Add b12x CuTe DSL fused MoE for SM120](../sources/prs/flashinfer/PR-3066.md), [cute-dsl fmha prefill (cubin integration): remove front-padding, add attention_sink, and pdl support](../sources/prs/flashinfer/PR-3181.md), [fix(sm12x): fix micro-kernel workspace sizing when routed_rows > num_local_experts](../sources/prs/flashinfer/PR-3191.md), [fix(cute_dsl/moe): make autotuner bucket configuration adapt to runtime input](../sources/prs/flashinfer/PR-3216.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [fix(cute_dsl/moe): unbias autotuner profiling for tile_size enumeration](../sources/prs/flashinfer/PR-3252.md), [feat(moe): add SM120 W4A16 b12x kernels](../sources/prs/flashinfer/PR-3271.md), [feat(cute_dsl/moe): deterministic balanced autotune profile inputs](../sources/prs/flashinfer/PR-3286.md), [feat(cute_dsl/moe): add `moe_output_memset_inplace` dense memset wrapper](../sources/prs/flashinfer/PR-3328.md), [Support single batch overlap](../sources/prs/sglang/PR-10422.md), [Replace [silu_and_mul_]scaled_fp4_group_quant by Flashinfer equivalent](../sources/prs/sglang/PR-12376.md), [[diffusion] kernel fusion: gated residual layernorm scale shift and layernorm scale shift kernel fusion for Qwen-Image, WAN and HunyuanVideo](../sources/prs/sglang/PR-14717.md), [[jit-kernel] Add CuTe DSL GDN Decode Kernel](../sources/prs/sglang/PR-15631.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [[diffusion] Diffusion norm fusion for z-image](../sources/prs/sglang/PR-18762.md), [[SGLang-Diffusion] Fix custom op fake impl missing eps default for torch.compile](../sources/prs/sglang/PR-19725.md), [[diffusion] fix bug of copy_if](../sources/prs/sglang/PR-20094.md), [[KDA] Support CuTeDSL KDA decode kernel](../sources/prs/sglang/PR-21203.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [Add dedicated FlashInferCuteDslMoE layer for standard-path FP4 MoE](../sources/prs/sglang/PR-21339.md), [[Bugfix] Lazy-import CuteDSL KDA kernel to fix AMD/ROCm startup crash](../sources/prs/sglang/PR-21428.md), [feat: Support flashinfer_cutedsl MoE runner with flashinfer alltoall backend](../sources/prs/sglang/PR-22669.md), [[Refactor] Refactor DeepEP dispatcher](../sources/prs/sglang/PR-22822.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [[MoE Refactor] Migrate flashinfer_cutedsl + DeepEP to MoeRunner](../sources/prs/sglang/PR-25525.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Bugfix] Fix CuTeDSL autotune cache invalid ELF header (#1967)](../sources/prs/tilelang/PR-1972.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[FIX] Add NO_MUL activation support for modular kernel path](../sources/prs/vllm/PR-31528.md), [fix: Add SM120 (RTX Blackwell) support for FlashInfer CUTLASS NVFP4 MoE kernels](../sources/prs/vllm/PR-33417.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[MoE/EPLB] Fix FlashInfer nvfp4 experts + EPLB correctness](../sources/prs/vllm/PR-37217.md), [[MoE] Move FlashInfer CuteDSL experts into fused_moe/experts/](../sources/prs/vllm/PR-37759.md), [[MoE Kernel] Flashinfer nvfp4 cutedsl moe kernel integration](../sources/prs/vllm/PR-38050.md), [[Quantization] Add FlashInfer CuteDSL batched experts backend for NVFP4 MoE](../sources/prs/vllm/PR-38251.md), [[Bugfix] [Tests] Enforce `out` tensor device in `kernel/moe/test_cutedsl_moe.py`](../sources/prs/vllm/PR-39644.md), [[DSv4] Improved fused Indexer Q quant kernel](../sources/prs/vllm/PR-41428.md), [[DSv4] Improved dequant gather K cache kernel](../sources/prs/vllm/PR-42236.md), [[Perf] Re-enable flashinfer autotune by default and cleanup](../sources/prs/vllm/PR-42857.md), [add cutedsl dsv4 indexer fp8 kernel](../sources/prs/vllm/PR-42899.md), [[Model Refactoring] Move deepseek_v4_ops to models/deepseek_v4 [3/N]](../sources/prs/vllm/PR-43073.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [FP8 Block-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [Fused MoE — FP8 Block-Scale Routing + Dual GEMM](../wiki/kernels/fused-moe.md), [Gated Dual GEMM (Gate-Up + SwiGLU Fusion)](../wiki/kernels/gated-dual-gemm.md), [Grouped GEMM for MoE](../wiki/kernels/grouped-gemm.md), [NVFP4 GEMM — 4-bit Floating Point Matrix Multiply](../wiki/kernels/nvfp4-gemm.md), [Sparse MLA (DeepSeek V3.2)](../wiki/kernels/sparse-mla.md), [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md) | +| `cuda-cpp` | [CUDA C++ for Blackwell Kernels](../wiki/languages/cuda-cpp.md) | [Twelve Attempts at an FP4 Kernel](../sources/blogs/amandeep-nvfp4-attempts.md), [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Kernels](../sources/blogs/colfax-cutlass-kernels.md), [NVIDIA Developer Code Samples](../sources/blogs/nvidia-code-samples.md), [simveit effective_transpose](../sources/blogs/simveit-effective-transpose.md), [simveit load_and_store](../sources/blogs/simveit-load-and-store.md), [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [FlashInfer MLSys 2026 Track A: FP8 Block-Scale MoE](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [NVIDIA Blackwell Compatibility Guide](../sources/docs/blackwell-compatibility-guide.md), [Fix performance issue of m-grouped contiguous GEMMs.](../sources/prs/DeepGEMM/PR-168.md), [Fix multicast bug and optimize masked GEMM](../sources/prs/DeepGEMM/PR-193.md), [fix: use SM90ArchSpec instead of SM100ArchSpec in sm90_bf16_k_grouped_gemm](../sources/prs/DeepGEMM/PR-270.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [ Solving bank conflict via padding and TMA 3D store](../sources/prs/DeepGEMM/PR-78.md), [Use 1D TMA store instead of 3D](../sources/prs/DeepGEMM/PR-83.md), [Use swizzling instead of padding](../sources/prs/DeepGEMM/PR-86.md), [Support TMA multicast on B with m_grouped_gemm_contiguous.](../sources/prs/DeepGEMM/PR-88.md), [[None][feat] sm100 weight-only kernel](../sources/prs/TensorRT-LLM/PR-10190.md), [[TRTLLM-10022][feat] Add hopper xqa decode support for skip softmax attention](../sources/prs/TensorRT-LLM/PR-10264.md), [[https://nvbugs/5669671][fix] Support GuidedDecoder with sharded logits (pick #10698)](../sources/prs/TensorRT-LLM/PR-10742.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11165.md), [[None][feat] Optimize super-v3 nvfp4 for better perf](../sources/prs/TensorRT-LLM/PR-11273.md), [[None][feat] Optimize by fuse nvfp4_quant to layernorm_gated for mamba2_mixer](../sources/prs/TensorRT-LLM/PR-11473.md), [[None][feat] TRT-LLM Gen MoE finalize kernel optimization](../sources/prs/TensorRT-LLM/PR-11501.md), [[None][feat] Add support for expert_number<=2048 and K<=32](../sources/prs/TensorRT-LLM/PR-11510.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[TRTLLM-11119][feat] Blackwell SageAttention, Integrate into AttentionOp API](../sources/prs/TensorRT-LLM/PR-11718.md), [[https://nvbugs/5799917][fix] Recover from CUTLASS MoE doActivation perf regression for MXFP4/NVFP4 dtype](../sources/prs/TensorRT-LLM/PR-11733.md), [[None][feat] Add fused DiT QK Norm + RoPE CUDA kernel for FLUX](../sources/prs/TensorRT-LLM/PR-11869.md), [[TRTLLM-10421][perf] Add fused cat+fp8_quantize CUDA kernel for DSA indexer](../sources/prs/TensorRT-LLM/PR-11899.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[https://nvbugs/5955188][fix] Fix harmony parsers and WAR routing PDL for agentic coding use cases](../sources/prs/TensorRT-LLM/PR-12046.md), [[TRTLLM-11540][feat] Add EAGLE3 dynamic tree speculative decoding support](../sources/prs/TensorRT-LLM/PR-12062.md), [[None][feat] Minimax RMS norm optimization](../sources/prs/TensorRT-LLM/PR-12163.md), [[None][feat] Add fused allreduce+RMSNorm op and optional residual in …](../sources/prs/TensorRT-LLM/PR-12201.md), [[None][feat] Support update weight for nvfp4](../sources/prs/TensorRT-LLM/PR-12320.md), [[None][feat] Temporally-Correlated Heuristic-guided Indexer TopK for Sparse Attention](../sources/prs/TensorRT-LLM/PR-12385.md), [[None][perf] add Dynamic SMEM block routing in MOE](../sources/prs/TensorRT-LLM/PR-12456.md), [[None][feat] Support sparse mqa/gqa attention](../sources/prs/TensorRT-LLM/PR-12470.md), [[https://nvbugs/5983390][perf] Split MLA DSA custom op for piecewise CUDA graph capture](../sources/prs/TensorRT-LLM/PR-12503.md), [[None][feat] Add Mamba2 MTP SSM cache CUDA kernel for tree-based speculative decoding](../sources/prs/TensorRT-LLM/PR-12537.md), [[https://nvbugs/5983390][perf] Multiple host perf optimizations for DSA part](../sources/prs/TensorRT-LLM/PR-12581.md), [[None][feat] Trtllm-gen FMHA JIT support](../sources/prs/TensorRT-LLM/PR-12612.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[TRTLLM-11485][feat] Feature rework: Add SageAttention refreshed kernels (attentionOp only)](../sources/prs/TensorRT-LLM/PR-12937.md), [[None][feat] Update rms_norm + fp4_qaunt kernel supporting more dim](../sources/prs/TensorRT-LLM/PR-13033.md), [[#12716][feat] Fused cross-head QK Norm + RoPE kernel for WAN](../sources/prs/TensorRT-LLM/PR-13052.md), [[None][feat] Optimize causal_conv1d prefill and decode kernels](../sources/prs/TensorRT-LLM/PR-13103.md), [[None][feat] Add FP4 residual quantization kernel without channel reo…](../sources/prs/TensorRT-LLM/PR-13117.md), [[https://nvbugs/5945047][fix] Fix cluster launch enablement for SM120 GPUs in allReduce fusion](../sources/prs/TensorRT-LLM/PR-13169.md), [[None][feat] Integrate FP4 indexer for DSA on Blackwell](../sources/prs/TensorRT-LLM/PR-13340.md), [[None][perf] Extend customMoeRouting kernel to support Qwen3.5](../sources/prs/TensorRT-LLM/PR-13433.md), [[None][perf] Scheme X L2-aware dispatcher and PDL launchers for sparse-attention GVR Top-K](../sources/prs/TensorRT-LLM/PR-13477.md), [[None][perf] Drop cubin and Eliminate ~6s FMHA JIT recompile in eager generation by aligning kernel selection with CUDA graph warmup](../sources/prs/TensorRT-LLM/PR-13505.md), [[None][feat] Fuse FP8 1x128 quantize + UE8M0 scale pack on SM100](../sources/prs/TensorRT-LLM/PR-13628.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[None][feat] Add DeepSeekV4 attention kernels](../sources/prs/TensorRT-LLM/PR-13652.md), [[https://nvbugs/6108841][fix] add hidden_dim=6144 router GEMM instantiation for GLM-5](../sources/prs/TensorRT-LLM/PR-13740.md), [[None][perf] Optimize DeepSeek-V4 compressor BF16 input](../sources/prs/TensorRT-LLM/PR-13761.md), [[None][fix] Plumb swiglu_limit through DeepGEMM and TRTLLMGen FP8 fused MoE](../sources/prs/TensorRT-LLM/PR-13767.md), [[None][fix] Fix fused MHC for DeepSeek-V4-Pro hidden size](../sources/prs/TensorRT-LLM/PR-13771.md), [[None][feat] Indexer topk opt](../sources/prs/TensorRT-LLM/PR-13811.md), [[None][perf] mHC fused_hc kernel optimizations + DS-V4 entry-boundary RMSNorm fold-in](../sources/prs/TensorRT-LLM/PR-13892.md), [[None][perf] Add CUDA q_b norm for DeepSeek V4](../sources/prs/TensorRT-LLM/PR-13975.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][feat] DSv4: enable GVR Heuristic Top-K for compress_ratio=4](../sources/prs/TensorRT-LLM/PR-14219.md), [[None][feat] Update the logic of FMHA JIT path](../sources/prs/TensorRT-LLM/PR-14291.md), [[None][chore] Update Claude Code agents and skills](../sources/prs/TensorRT-LLM/PR-14344.md), [feat: Add w4a8_mxfp4_fp8 quantization recipe.](../sources/prs/TensorRT-LLM/PR-4867.md), [[OMNIML-2336][feat] Add NVFP4 x FP8](../sources/prs/TensorRT-LLM/PR-6809.md), [[None][chore] Fix kernel launch param and add TRTLLM MoE backend test](../sources/prs/TensorRT-LLM/PR-7524.md), [[None][fix] Fix and add test for TRTLLM MoE backend](../sources/prs/TensorRT-LLM/PR-7755.md), [[TRTLLM-8637][feat] Optimize the routing kernel for DeepseekV3 (MoE CUTLASS backend); Add support for 384 experts (MoE TRTLLM backend)](../sources/prs/TensorRT-LLM/PR-7761.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[None][fix] Fix the performance issue of FP8 blockwise grouped GEMM when using attention DP](../sources/prs/TensorRT-LLM/PR-8501.md), [[None][feat] Enable nvfp4 cuda core for sm120](../sources/prs/TensorRT-LLM/PR-8620.md), [[None][feat] Update TRTLLM MoE cubins; reduce mxfp4 weight padding requirement; tighten TMA bound](../sources/prs/TensorRT-LLM/PR-9025.md), [[None][fix] support topk autotuner input for expert slot per group larger than 32](../sources/prs/TensorRT-LLM/PR-9087.md), [[None][feat] TRT-LLM Gen MoE optimize DeepSeek Fp8 activation kernel](../sources/prs/TensorRT-LLM/PR-9175.md), [[None][feat] add fp4 gemm + allreduce](../sources/prs/TensorRT-LLM/PR-9729.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [[None][feat] Fused kernels (qknormrope + moe routing) and two-model MTP support for glm4moe](../sources/prs/TensorRT-LLM/PR-9852.md), [[None][feat] Port fp4 quantization kernel optimization from FlashInfer](../sources/prs/TensorRT-LLM/PR-9854.md), [[None][feat] Adding torch ext API for FusedAddRMSNormQuant kernel](../sources/prs/TensorRT-LLM/PR-9905.md), [[TRTLLM-9493][feat] Add helixPostProcessNative kernel for cp_dim=2](../sources/prs/TensorRT-LLM/PR-9924.md), [Experimental Python cooperative algorithms](../sources/prs/cccl/PR-1973.md), [fix thread-reduce performance regression](../sources/prs/cccl/PR-2944.md), [Fix scan / sm90 perf regression ](../sources/prs/cccl/PR-3236.md), [Fix the vectorized loading of BlockLoad](../sources/prs/cccl/PR-3517.md), [Add b200 tunings for scan.exclusive.sum](../sources/prs/cccl/PR-3559.md), [Fix SM100 histogram tunings](../sources/prs/cccl/PR-3691.md), [Split Optimize Warp Reduce PR - CUB part](../sources/prs/cccl/PR-4716.md), [Add nondeterministic reduce that uses atomics](../sources/prs/cccl/PR-4961.md), [CUB - Add internal integer utils and tests (Split `WarpReduce` PR)](../sources/prs/cccl/PR-5314.md), [Combine `block_reduce_warp_reduction_nondeterministic.cuh` specialization with original deterministic one ](../sources/prs/cccl/PR-5408.md), [Add dynamic CUB dispatch for segmented_sort](../sources/prs/cccl/PR-6069.md), [[CUB] Use `BlockLoadToShared` in `DeviceMerge`](../sources/prs/cccl/PR-6077.md), [Fix debug section around line 390 of dispatch_topk](../sources/prs/cccl/PR-6152.md), [Split fixed-size segmented reduce dispatch header](../sources/prs/cccl/PR-6597.md), [Integrate decoupled lookahead warpspeed scan](../sources/prs/cccl/PR-6811.md), [Use integer promotion for `warp_reduce`](../sources/prs/cccl/PR-6819.md), [Implement new tuning API arch dispatching](../sources/prs/cccl/PR-7093.md), [Two-phase reduction for fixed size segmented reduction for very large segment sizes](../sources/prs/cccl/PR-7114.md), [Implement the new tuning API for deterministic (rfa) reduce dispatch](../sources/prs/cccl/PR-7346.md), [Radix-selection based `BlockTopK` specialization](../sources/prs/cccl/PR-7384.md), [Implement the new tuning API for `DeviceRleDispatch`](../sources/prs/cccl/PR-7669.md), [Optimize non fixed size segmented reduce for small segments using max_segment_size](../sources/prs/cccl/PR-7718.md), [Add env SegmentedReduce (non fixed-size overloads)](../sources/prs/cccl/PR-7795.md), [Forward policy hub from `dispatch_streaming_arg_reduce_t` to `reduce::dispatch`](../sources/prs/cccl/PR-7805.md), [Implement the new tuning API for `detail::reduce::dispatch_streaming_arg_reduce_t`](../sources/prs/cccl/PR-7807.md), [Use the new tuning API internally for `detail::transform::dispatch`](../sources/prs/cccl/PR-7810.md), [[Backport branch/3.3.x] Forward policy hub from `dispatch_streaming_arg_reduce_t` to `reduce::dispatch`](../sources/prs/cccl/PR-7814.md), [Optimized Device-to-Device Tensor Copy (`cudax`)](../sources/prs/cccl/PR-7823.md), [Implement the new tuning API for `DispatchSegmentedRadixSort`](../sources/prs/cccl/PR-7844.md), [Implement the new tuning API for `DispatchSegmentedSort`](../sources/prs/cccl/PR-7874.md), [Implement the new tuning API for `DispatchTopK`](../sources/prs/cccl/PR-7928.md), [[cuda.compute]: Fix faulty pointer arithmetic calculation in CUB dispatch](../sources/prs/cccl/PR-7940.md), [Reduce usage of `cub::DispatchReduce`](../sources/prs/cccl/PR-7944.md), [Use the new tuning API for `detail::radix_sort::dispatch`](../sources/prs/cccl/PR-7949.md), [Adds support for non-fundamental types via decomposer to `DeviceTopK` ](../sources/prs/cccl/PR-8040.md), [Optimized Device-to-Device Tensor Copy (cudax) - Transpose Case](../sources/prs/cccl/PR-8125.md), [Avoid passing uninitialized values to scan_op](../sources/prs/cccl/PR-8184.md), [[STF] Move unstable_unique from STF to generic cudax utility](../sources/prs/cccl/PR-8190.md), [Expose `max_segment_size` guarantee in cuda.compute](../sources/prs/cccl/PR-8284.md), [Port `thrust::min|max_element` to CUB](../sources/prs/cccl/PR-8291.md), [Implement the new tuning API for `DispatchSelectIf`](../sources/prs/cccl/PR-8311.md), [simplify dispatch segmented reduce to use latest dispatch and new tunings API](../sources/prs/cccl/PR-8332.md), [Apply some random warpspeed tunings](../sources/prs/cccl/PR-8352.md), [[cub]: implement utilities for policy selection](../sources/prs/cccl/PR-8355.md), [Replace `detail::merge::dispatch` by CUB's public API](../sources/prs/cccl/PR-8381.md), [[CUB] Replace `Shuffle(Up|Down|Index)` with cuda::device::warp_shuffle - RadixSort only](../sources/prs/cccl/PR-8395.md), [Vectorize mbarrier initialization in warpspeed scan](../sources/prs/cccl/PR-8423.md), [[thrust] Single-pass `is_partitioned` via adjacent zip_iterator](../sources/prs/cccl/PR-8427.md), [Replace `detail::merge_sort::dispatch` by CUB's public API](../sources/prs/cccl/PR-8473.md), [Replace `detail::scan::dispatch` by CUB's public API](../sources/prs/cccl/PR-8495.md), [Implement the new tuning API for `detail::batched_topk::dispatch_batched_topk`](../sources/prs/cccl/PR-8538.md), [Replace `detail::for_each::dispatch` by CUB's public API](../sources/prs/cccl/PR-8565.md), [Replace `detail::segmented_reduce::dispatch` by the public API](../sources/prs/cccl/PR-8695.md), [Use the new tuning API internally for `detail::topk::dispatch`](../sources/prs/cccl/PR-8742.md), [Use the new tuning API internally for `detail::reduce_by_key::dispatch`](../sources/prs/cccl/PR-8756.md), [Use the new tuning API internally for `detail::reduce[_nd]::dispatch[_nd]`](../sources/prs/cccl/PR-8826.md), [Fix Warpspeed scan shifted output store](../sources/prs/cccl/PR-8839.md), [[cub] Simplify arch dispatch](../sources/prs/cccl/PR-8861.md), [Use the new tuning API internally for `detail::select::dispatch` and `DeviceSelect`](../sources/prs/cccl/PR-8880.md), [[STF] Add per-handle exec_place stream resources](../sources/prs/cccl/PR-8905.md), [Use the new tuning API internally for `detail::select|three_way_partition::dispatch` and `DevicePartition`](../sources/prs/cccl/PR-8925.md), [Use the new tuning API internally for `detail::segmented_radix_sort::dispatch`](../sources/prs/cccl/PR-8927.md), [[libcu++] Always suppress C++ extensions warnings in prologue](../sources/prs/cccl/PR-9019.md), [Fix segmented radix sort benchmark segment size type](../sources/prs/cccl/PR-9039.md), [[libcu++] Fix default make_shared_resource construction](../sources/prs/cccl/PR-9044.md), [Vectorize contiguous iterators in `cub::BlockLoad`/`Store`](../sources/prs/cccl/PR-9056.md), [Improve sm90 mixed dtype kernel](../sources/prs/cutlass/PR-1883.md), [[EVT] Add support for Row/Col broadcast PtrArray](../sources/prs/cutlass/PR-2033.md), [Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2037.md), [Improvements for: Groupwise scaling along M for FP8 gemm](../sources/prs/cutlass/PR-2095.md), [Flash MLA support](../sources/prs/cutlass/PR-2130.md), [Flash MLA Support - Step 2](../sources/prs/cutlass/PR-2134.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Blockwise Improvement and Programmatic Dependent Launch](../sources/prs/cutlass/PR-2161.md), [Fix sm100 gemm wrong static constexpr that breaks compilation on Windows](../sources/prs/cutlass/PR-2167.md), [Fix SM90 beta=1 hang and stream-K launch errors](../sources/prs/cutlass/PR-2172.md), [Set EpiTile correctly when TileN is not divisible by 32](../sources/prs/cutlass/PR-2220.md), [Use cudaMemcpyAsync in gemm grouped with kRequiresPrecomputation sche…](../sources/prs/cutlass/PR-2256.md), [war to fix blackwell grouped groupwise hang](../sources/prs/cutlass/PR-2267.md), [hopper-blockwise-generalization-optimization](../sources/prs/cutlass/PR-2270.md), [Correct divmod order in example 77 (blackwell fmha)](../sources/prs/cutlass/PR-2291.md), [Handle get_masked_trip_count for small length in fmha example](../sources/prs/cutlass/PR-2292.md), [Fix epilogue::thread::Convert cannot be used with DefaultEpilogue](../sources/prs/cutlass/PR-2333.md), [[ex77] fix mla split; add fwd lse; add bwd varlen](../sources/prs/cutlass/PR-2366.md), [support fp16 accmulator for sm89 fp8 mma](../sources/prs/cutlass/PR-2378.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [fix: examples/cute/tutorial/blackwell/04_mma_tma_2sm_sm100.cu GridDim miscalculated](../sources/prs/cutlass/PR-2492.md), [DistGEMM bug fixes](../sources/prs/cutlass/PR-2713.md), [Support PDL for SM90 Array TMA GEMM](../sources/prs/cutlass/PR-2719.md), [Support for GEMM-K=0 for Blackwell Grouped GEMMs](../sources/prs/cutlass/PR-2746.md), [Blockscaled Ragged Contiguous Grouped Gemm for MoEs](../sources/prs/cutlass/PR-2790.md), [[Bug Fix]Bypass launch grids for SM120 Kernel with SM90 Mainloop & SM100 TileScheduler](../sources/prs/cutlass/PR-2865.md), [[cute] Add constexpr specifier to make_tiled_copy](../sources/prs/cutlass/PR-2875.md), [Fix incorrect tensor layout strides in Blackwell MMA tutorial comments](../sources/prs/cutlass/PR-2921.md), [[Cutlass gemm] Fix SM100 FP8 nosmem epilogue-fusion shape_div 'Divisibility Condition' for non-multiple-of-64 N tiles](../sources/prs/cutlass/PR-2946.md), [[Bug Fix]Set NumSplitsM to 1 when TileShapeM < 128 in sm90 fp8 blockwise scaling CollectiveMma](../sources/prs/cutlass/PR-2965.md), [Replace std::min with cute::min in sm120 blockwise scaling device functions](../sources/prs/cutlass/PR-3055.md), [Small Tile N BlockScaled GEMM + Grouped GEMM on SM12x](../sources/prs/cutlass/PR-3176.md), [Add Snake activation functor for EVT](../sources/prs/cutlass/PR-3184.md), [Fp8 kernel with "in-kernel" transpose of V in producer](../sources/prs/flash-attention/PR-1100.md), [FA3 kvcache + split kv + gqa parallelization](../sources/prs/flash-attention/PR-1236.md), [Fix FA3 Varlen Performance regression](../sources/prs/flash-attention/PR-1361.md), [Add sorting and head swizzle to varlen scheduler](../sources/prs/flash-attention/PR-1823.md), [feat: update decode attention APIs](../sources/prs/flashinfer/PR-1007.md), [misc: fix instrument code for mla profiler](../sources/prs/flashinfer/PR-1014.md), [add multi-item scoring](../sources/prs/flashinfer/PR-1015.md), [fix: add zero init for KV tiled copy](../sources/prs/flashinfer/PR-1029.md), [feat: add functional per-head FP8 quantization for FA3](../sources/prs/flashinfer/PR-1033.md), [feat: Softmax free sampling](../sources/prs/flashinfer/PR-1035.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [fix: top_k_mask_logits hangs on -inf inputs](../sources/prs/flashinfer/PR-1050.md), [[nvidia] Add Blackwell FMHA decode kernel from TRT-LLM](../sources/prs/flashinfer/PR-1051.md), [Fix KV chunking for POD. ](../sources/prs/flashinfer/PR-1054.md), [bugfix: temporally disable split-kv in blackwell mla](../sources/prs/flashinfer/PR-1055.md), [Parameterize prefix mask call (needed by POD-Attention)](../sources/prs/flashinfer/PR-1059.md), [bugfix: adding lse output to blackwell fmha kernels](../sources/prs/flashinfer/PR-1071.md), [bugfix: follow user-specified sm_scale for blackwell cutlass fmha](../sources/prs/flashinfer/PR-1072.md), [perf: accelerate blackwell grouped gemm](../sources/prs/flashinfer/PR-1086.md), [bugfix: fix fp8 attention kernels aot compilation issue](../sources/prs/flashinfer/PR-1087.md), [comm: refactor and initialize `flashinfer.comm` module](../sources/prs/flashinfer/PR-1089.md), [feat: add trtllm all-reduce (non-MoE)](../sources/prs/flashinfer/PR-1096.md), [bugfix: host-precomuted plan function for blackwell fmha](../sources/prs/flashinfer/PR-1106.md), [feat: add trtllm moe_allreduce_fusion](../sources/prs/flashinfer/PR-1108.md), [Add CUTLASS fused moe kernels from TensorRT-LLM.](../sources/prs/flashinfer/PR-1113.md), [bugfix: Fix test and output shape of fp4 quantize](../sources/prs/flashinfer/PR-1114.md), [hotfix: fix the blackwell fmha stream](../sources/prs/flashinfer/PR-1116.md), [[Feature] Support PDL for batch Prefill and Decode](../sources/prs/flashinfer/PR-1117.md), [Fix pointer dtype bug in rope](../sources/prs/flashinfer/PR-1129.md), [feat: add trtllm all-reduce fusion](../sources/prs/flashinfer/PR-1131.md), [MNNVL MoE All-to-All Support](../sources/prs/flashinfer/PR-1134.md), [fix: negative zero by type trait --> binary value](../sources/prs/flashinfer/PR-1136.md), [[feat] add unified batch attention w/ correctness tests.](../sources/prs/flashinfer/PR-1137.md), [Fix FA2 and FA3 multi-item scoring and cuda illegal memory access error](../sources/prs/flashinfer/PR-1140.md), [feat: Fused temperature online softmax kernel](../sources/prs/flashinfer/PR-1153.md), [Add more logging to TRTLLM-GEN debug trace (NFC)](../sources/prs/flashinfer/PR-1158.md), [feat: add finalize_moe_allreduce from trtllm](../sources/prs/flashinfer/PR-1159.md), [feat: nvshmem python bindings](../sources/prs/flashinfer/PR-1160.md), [feat: update non-fused moe](../sources/prs/flashinfer/PR-1161.md), [feat: enable and update all-reduce fused quantization](../sources/prs/flashinfer/PR-1164.md), [bugfix: softmax NaN results caused by large -inf masks](../sources/prs/flashinfer/PR-1178.md), [update trtllm-gen decode attention kernel launcher](../sources/prs/flashinfer/PR-1189.md), [[feat] optimize persistent batch attention perf.](../sources/prs/flashinfer/PR-1200.md), [[fix] fix BatchAttention CTA_TILE_KV mask issue](../sources/prs/flashinfer/PR-1206.md), [Fix the issue with auxillary kernel launch and grid dim calculation](../sources/prs/flashinfer/PR-1208.md), [feat: trtllm-gen fp8 moe kernels](../sources/prs/flashinfer/PR-1212.md), [[comm] TRT-LLM's Multi-Node NVLink All-Reduce Kernel](../sources/prs/flashinfer/PR-1213.md), [Feature/sm100 low latency nvfp4 kernels](../sources/prs/flashinfer/PR-1214.md), [Enable cudnn decode and add tests for the cudnn decode kernel](../sources/prs/flashinfer/PR-1221.md), [feat: add trtllm-gen mla cubin](../sources/prs/flashinfer/PR-1222.md), [Fix missing hash in the cudnn cubin path](../sources/prs/flashinfer/PR-1227.md), [feat: Add non-causal cudnn prefill kernels](../sources/prs/flashinfer/PR-1230.md), [bugfix: support uint8_t for vec_t class template](../sources/prs/flashinfer/PR-1234.md), [add trtllm-gen context attention](../sources/prs/flashinfer/PR-1239.md), [Patch fp8 cubin availability](../sources/prs/flashinfer/PR-1240.md), [feat: Support MXFP8 x MXFP4 CUTLASS grouped GEMM](../sources/prs/flashinfer/PR-1241.md), [Add trtllm-gen attention mha kernel with FP8 Q/K/V and FP8 output](../sources/prs/flashinfer/PR-1242.md), [Remove sm100+ requirment for trtllm allreduce kernels](../sources/prs/flashinfer/PR-1249.md), [Reduce the JIT compilation time of gen_gemm_sm100_module](../sources/prs/flashinfer/PR-1251.md), [TRT-LLM's Multi-Node NVLink AR + fused RMSNorm kernel](../sources/prs/flashinfer/PR-1255.md), [feat: enable trtllm-gen mla MTP](../sources/prs/flashinfer/PR-1258.md), [Made AR output optional + esthetic changes](../sources/prs/flashinfer/PR-1265.md), [Bug fix: fix duplicate launch in POD](../sources/prs/flashinfer/PR-1267.md), [Add shuffle matrix flag](../sources/prs/flashinfer/PR-1272.md), [Convert scale_factor from scalar to Tensor in trt_allreduce_fusion](../sources/prs/flashinfer/PR-1284.md), [fix multiCtasKvScratchPtr misalignment issue (new one)](../sources/prs/flashinfer/PR-1286.md), [Bug fix: guard fp8 e8m0 and e2m1 compile ](../sources/prs/flashinfer/PR-1287.md), [refactor: refactor trtllm-gen attention kernel integration code](../sources/prs/flashinfer/PR-1289.md), [[fix] fix integer overflow in FA2 customized_mask & add buffer overflow warning.](../sources/prs/flashinfer/PR-1290.md), [refactor: Improved metainfo for trtllm-gen fmha](../sources/prs/flashinfer/PR-1292.md), [Update cutlass fp4 moe kernels](../sources/prs/flashinfer/PR-1294.md), [add cutlass backend for mm_fp4](../sources/prs/flashinfer/PR-1296.md), [feat: Add weight layout option for trtllm-gen fused moe](../sources/prs/flashinfer/PR-1297.md), [perfix: use lightweight API to query device property](../sources/prs/flashinfer/PR-1298.md), [[Feature] SM level profiler ](../sources/prs/flashinfer/PR-1305.md), [Fix the bug of the kernel-selection heuristic in trtllm-gen](../sources/prs/flashinfer/PR-1307.md), [Refactor Fused Moe Module](../sources/prs/flashinfer/PR-1309.md), [feat: support output nvfp4 in trtllm-gen function call.](../sources/prs/flashinfer/PR-1318.md), [Make Fp8 MoE routing_bias optional](../sources/prs/flashinfer/PR-1319.md), [Add blockwise-scaled FP8 GEMM via TRTLLM-Gen.](../sources/prs/flashinfer/PR-1320.md), [Optimizations for TRTLLM MNNVL Allreduce](../sources/prs/flashinfer/PR-1321.md), [feat: Add k_scale and v_scale to persistent attention ](../sources/prs/flashinfer/PR-1322.md), [feat: Support logits_soft_cap for Persistent attn; fix kv split limit](../sources/prs/flashinfer/PR-1324.md), [feat: Fused rope fp8 quantize kernel for MLA](../sources/prs/flashinfer/PR-1339.md), [fix: fix trtllm-gen mla error on new interface](../sources/prs/flashinfer/PR-1348.md), [feature: add fp4 mm using trtllm backend](../sources/prs/flashinfer/PR-1355.md), [support trtllm-gen prefill fp4 output](../sources/prs/flashinfer/PR-1360.md), [Support scale factor start index for fp4 mha prefill/decode](../sources/prs/flashinfer/PR-1363.md), [bugfix: fixed cutlass fused moe usage of FP4QuantizationSFLayout::SWIZZLED](../sources/prs/flashinfer/PR-1371.md), [bugfix: Add guard for fp4/fp8 related include headers](../sources/prs/flashinfer/PR-1376.md), [GPT-OSS Support: Add Blackwell MoE mxfp4 implementation from TRTLLM and Attention Sink](../sources/prs/flashinfer/PR-1389.md), [gpt-oss: Add MXFP8 x MXFP4 CUTLASS MOE for SM100 and BF16 x MXFP4 CUTLASS for SM90 + SwigluBias Activation](../sources/prs/flashinfer/PR-1396.md), [feature: add cutlass as bmm_fp8 backend.](../sources/prs/flashinfer/PR-1397.md), [Fix trtllm moe launcher local_num_experts](../sources/prs/flashinfer/PR-1398.md), [fix shared memory alignment conflict in sampling.cuh](../sources/prs/flashinfer/PR-1402.md), [[bugfix] Fix compilation failure when compiling csrc/trtllm_moe_allreduce_fusion.cu](../sources/prs/flashinfer/PR-1410.md), [Fixes for Blackwell Tests](../sources/prs/flashinfer/PR-1434.md), [fix: remote redundant zero_init from trtllm-gen attn](../sources/prs/flashinfer/PR-1444.md), [Add alignment in MxFP8Quantization](../sources/prs/flashinfer/PR-1445.md), [Remove getEnvEnablePDL in favor of enable_pdl parameter](../sources/prs/flashinfer/PR-1446.md), [bugfix: Verify num_experts greater or equal to local_experts + offset](../sources/prs/flashinfer/PR-1469.md), [perf: add 1x4x1 cluster shape for fp8 bmm M<16 cases](../sources/prs/flashinfer/PR-1473.md), [tuner: Trtllm-gen Fp4 MoE Autotunner](../sources/prs/flashinfer/PR-1475.md), [perf: add fast path to TopPRenormProbKernel for top_p >= 1.0, significantly boosting SGLang workloads](../sources/prs/flashinfer/PR-1483.md), [feat: add pdl for trtllm-gen attn](../sources/prs/flashinfer/PR-1484.md), [feat: Support fp8 qkv, fp16/bf16 out MHA for trtllm-gen.](../sources/prs/flashinfer/PR-1490.md), [Perf: support scale_a/scale_b instead of combined scale in cutlass bmm_fp8](../sources/prs/flashinfer/PR-1491.md), [fix: Replace cub Max/Min with cuda::maximum/minimum for cuda 13 compatibility](../sources/prs/flashinfer/PR-1500.md), [feat: integrate xqa attention backend](../sources/prs/flashinfer/PR-1503.md), [update allreduce to match trtllm](../sources/prs/flashinfer/PR-1507.md), [Support cuda<12.8 built for trtllm_allreduce_fusion.](../sources/prs/flashinfer/PR-1508.md), [backend: Refactor trtllm-gen fmha metainfo loading](../sources/prs/flashinfer/PR-1518.md), [Fix linking errors with CUDA 13](../sources/prs/flashinfer/PR-1523.md), [Add GeGLU support to trtllm-gen NVFP4 Fused MoE Kernel](../sources/prs/flashinfer/PR-1525.md), [bugfix: Fix compile error for undefined swizzle enum.](../sources/prs/flashinfer/PR-1530.md), [bugfix: Fix Persistent kernel precision for masked output ](../sources/prs/flashinfer/PR-1533.md), [Remove cuda-python from dependency and check at runtime](../sources/prs/flashinfer/PR-1534.md), [feat: Integrate TRTLLM varlen kernel for deepseek R1 prefill ](../sources/prs/flashinfer/PR-1537.md), [fix trtllm_allreduce_fusion twoshot register problem.](../sources/prs/flashinfer/PR-1545.md), [perf: replace cudaGetDeviceProperties with cudaDeviceGetAttribute](../sources/prs/flashinfer/PR-1547.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [Add mnnvl_moe_alltoallv_prepare_without_allgather](../sources/prs/flashinfer/PR-1550.md), [bugfix: fix persistent attention kernel correctness on blackwell](../sources/prs/flashinfer/PR-1559.md), [fix: separate out fp4 lib into sm90 and sm100 versions, add oob checking in fused moe](../sources/prs/flashinfer/PR-1565.md), [Backend: downgrade trtllm-gen kernel to cuda-12](../sources/prs/flashinfer/PR-1567.md), [bugfix: fix cuda version guard macros](../sources/prs/flashinfer/PR-1571.md), [update trtllm-gen fp4 autotuner and routing](../sources/prs/flashinfer/PR-1573.md), [bugfix: update trtllm-gen gemm kernel names](../sources/prs/flashinfer/PR-1577.md), [bugfix: Fix arg passing to TORCH_CHECK and TORCH_WARN macros](../sources/prs/flashinfer/PR-1582.md), [fix: semaphoress must be at the fixed range in workspace buffer on trtllm_gen attention](../sources/prs/flashinfer/PR-1584.md), [bugfix: fix fused-temperature softmax IMA issue](../sources/prs/flashinfer/PR-1596.md), [bugfix: fix the register overflow issue for topk renorm kernels on blackwell](../sources/prs/flashinfer/PR-1597.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [feat: cutlass fp4 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1609.md), [feat: cutlass fp8 gemm bringup for SM120 & SM121](../sources/prs/flashinfer/PR-1610.md), [bugfix: fix fp4 quantization with 8x4 scale factor layout](../sources/prs/flashinfer/PR-1611.md), [bugfix: fix merge_attention_state in BatchAttention w/ gqa-group-size in Qwen family](../sources/prs/flashinfer/PR-1614.md), [perf: Fix the tactic sorting in TrtllmGenBatchedGemmRunner::getValidConfigIndices](../sources/prs/flashinfer/PR-1615.md), [bugfix: collect all modules to aot](../sources/prs/flashinfer/PR-1622.md), [bugfix: trtllm-gen fmha sm101 and sm100 compatibility](../sources/prs/flashinfer/PR-1631.md), [perf&bugfix: skip kv-tile computation out of sliding window in FA2; fix __syncthreads in mergestate](../sources/prs/flashinfer/PR-1661.md), [Refactor Blackwell unit test scripts](../sources/prs/flashinfer/PR-1667.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [feat: Add `variant.OutputTransform()` to decode kernels](../sources/prs/flashinfer/PR-1670.md), [feat: Batch-size invariant FA2 Prefill & Decode](../sources/prs/flashinfer/PR-1675.md), [perf: improve attention of tcgen05 flash-attention](../sources/prs/flashinfer/PR-1681.md), [Update TGV GEMM default kernel and TGV code cleanup.](../sources/prs/flashinfer/PR-1682.md), [perf: Port the separate reduce kernel mode from trtllm.](../sources/prs/flashinfer/PR-1685.md), [Support Kimi-K2 for TRT: templatize number of experts](../sources/prs/flashinfer/PR-1696.md), [Fix DeepSeek quality for TRTLLM fused MoE routing](../sources/prs/flashinfer/PR-1723.md), [bugfix: partially fix tests/test_trtllm_gen_fused_moe.py unit test failure](../sources/prs/flashinfer/PR-1724.md), [TVM: support TVM binding for GroupedGemm](../sources/prs/flashinfer/PR-1725.md), [fix: put sampling kernel launch into macro](../sources/prs/flashinfer/PR-1727.md), [fix: fix cannot import name 'cuda' from 'cuda' in CUDA13](../sources/prs/flashinfer/PR-1764.md), [feat: add xqa fp8 mha and fp8 kv cache](../sources/prs/flashinfer/PR-1769.md), [Masked batch nvfp4 quantization](../sources/prs/flashinfer/PR-1774.md), [feat:enable fp8 blockscale moe for fused cultass for sm90](../sources/prs/flashinfer/PR-1819.md), [Bugfix: Fix data hazard in persistent reduce](../sources/prs/flashinfer/PR-1826.md), [feat: trtrllm-gen global scaled FP8 GEMMs](../sources/prs/flashinfer/PR-1829.md), [Update the routing for TRTLLMGEN to support kimi k2 and qwen](../sources/prs/flashinfer/PR-1831.md), [[Quantization] Add per-expert global scaling factor for fp4 batched quantize](../sources/prs/flashinfer/PR-1835.md), [Add head_dim=64 for tcgen05 tcgen05 flash-attention implementation](../sources/prs/flashinfer/PR-1850.md), [Bugfix: fix o_strides in persistent kernel ](../sources/prs/flashinfer/PR-1865.md), [Tune kernel compilation parameters for https://github.com/flashinfer-ai/flashinfer/pull/1850 ](../sources/prs/flashinfer/PR-1878.md), [feat: Add FP4 TRTLLM-Gen throughput MOE batched gemms](../sources/prs/flashinfer/PR-1882.md), [MLA RoPE + quantization fused kernel: shape generalization for MHA / GQA](../sources/prs/flashinfer/PR-1924.md), [Add layernorm op for inputs of mixed dtype](../sources/prs/flashinfer/PR-1926.md), [silu_and_mul nvfp4 quanization fusion rework](../sources/prs/flashinfer/PR-1927.md), [Feature: Support Relu2 activation in fused MoE](../sources/prs/flashinfer/PR-1954.md), [Update trtllm-gen fused moe routing kernel and add more kernels](../sources/prs/flashinfer/PR-1955.md), [Fix: Verify scales are not None for Cutlass FP8 FusedMoE](../sources/prs/flashinfer/PR-1961.md), [feat: enable deepgemm jit for fp8 block-scale on SM90](../sources/prs/flashinfer/PR-1969.md), [feat: autotune tile_tokens_dim in trtllm-gen MOE](../sources/prs/flashinfer/PR-1980.md), [fix: correct PDL parameter handling in RopeQuantize kernel](../sources/prs/flashinfer/PR-1982.md), [minor fix for xqa](../sources/prs/flashinfer/PR-1994.md), [Bugfix: Change get() -> GetDLTensorPtr() in cutlass FusedMoE validations](../sources/prs/flashinfer/PR-1995.md), [feat: add xqa backend and completes NHD/HND coverage for trtllm-gen/xqa backend](../sources/prs/flashinfer/PR-2001.md), [Feature: Support non-gated activation in cutlass fused MoE nvfp4](../sources/prs/flashinfer/PR-2011.md), [[feat] Refactor trtllmgen MOE and add Bf16 trtllmgen moe](../sources/prs/flashinfer/PR-2014.md), [[DSV3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2019.md), [update trtllm cutlass moe ](../sources/prs/flashinfer/PR-2020.md), [perf: Speed up fp4 quantization for small batch with swizzling for cutlass MoE](../sources/prs/flashinfer/PR-2025.md), [[NVIDIA] Thor & Spark Support](../sources/prs/flashinfer/PR-2028.md), [Enable renormalize(naive) routing for fp8 per-tensor](../sources/prs/flashinfer/PR-2030.md), [use scalar for kv_scale in xqa](../sources/prs/flashinfer/PR-2033.md), [feat: Add flashinfer.rope.rope_quantize_fp8_append_paged_kv_cache (fused RoPE + Q + KV cache, supports MLA/GQA/MHA) ](../sources/prs/flashinfer/PR-2037.md), [perf: improve sampling/mask/softmax performance (part 1/2)](../sources/prs/flashinfer/PR-2044.md), [Rebase FP8 SM100 Cutlass FMHA Attention to main (original PR#1238)](../sources/prs/flashinfer/PR-2047.md), [Fix dtype of output scales from mnnvl_moe_alltoallv_prepare_without_allgather](../sources/prs/flashinfer/PR-2048.md), [[BUG] Fix trtllm-gen fp4 moe renormalize routing](../sources/prs/flashinfer/PR-2049.md), [Add support for topkPacked input in block-level renormalize](../sources/prs/flashinfer/PR-2051.md), [feat: add xqa mla backend](../sources/prs/flashinfer/PR-2053.md), [perf: Optimize helper max/minmax function in sampling.cuh](../sources/prs/flashinfer/PR-2058.md), [Fix moe fp8 failure for sm121](../sources/prs/flashinfer/PR-2061.md), [Fix: several bugs/issues with trtllm-gen attention kernels. ](../sources/prs/flashinfer/PR-2062.md), [perf: TRT-LLM MoE Block-FP8 activation optimization](../sources/prs/flashinfer/PR-2063.md), [feat: BF16 GEMM using CUTLASS backend for SM100](../sources/prs/flashinfer/PR-2070.md), [[Feature] Support batch prefill for POD Attention](../sources/prs/flashinfer/PR-2079.md), [enable xqa fp8 output](../sources/prs/flashinfer/PR-2081.md), [[API change] Allow using torch.Tensor for scales for trtllm-gen attention](../sources/prs/flashinfer/PR-2084.md), [refactor: pass hopper deepgemm include directory through python](../sources/prs/flashinfer/PR-2090.md), [perf: TRT-LLM Gen finalize kernel optimization](../sources/prs/flashinfer/PR-2092.md), [perf: enable pdl for cutlass fp4 gemm](../sources/prs/flashinfer/PR-2095.md), [Port TRT-LLM communication kernels to flashinfer](../sources/prs/flashinfer/PR-2102.md), [enable xqa speculative decoding](../sources/prs/flashinfer/PR-2105.md), [feat: support more head dim in RoPE kernel](../sources/prs/flashinfer/PR-2109.md), [add tensor scale input for xqa](../sources/prs/flashinfer/PR-2110.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [feature: make the LSE returned by MLA support base 2 or e #2113](../sources/prs/flashinfer/PR-2114.md), [update xqa license](../sources/prs/flashinfer/PR-2117.md), [Refactor trtllm_mnnvl_allreduce](../sources/prs/flashinfer/PR-2118.md), [perf: bunch of features and optimizations for top-k (sampling + sparse attention)](../sources/prs/flashinfer/PR-2119.md), [feat: support variable sequence length in decode kernel of trtllm-gen attention](../sources/prs/flashinfer/PR-2125.md), [fix flaky xqa test](../sources/prs/flashinfer/PR-2126.md), [make DeepGEMM swapAB available for linear gemm SM90](../sources/prs/flashinfer/PR-2131.md), [feat: add trtllm-gen per-tensor sparseMla kernels.](../sources/prs/flashinfer/PR-2138.md), [feat: TRTLLM FMHAv2 backend for ctx attention](../sources/prs/flashinfer/PR-2142.md), [fix xqa mha_sm90.cu](../sources/prs/flashinfer/PR-2157.md), [feat: MxInt4 x Bf16 TRT-LLM Gen MoE support](../sources/prs/flashinfer/PR-2159.md), [Add data type check for deepseek fp4 moe](../sources/prs/flashinfer/PR-2165.md), [Fix for moe on sm110](../sources/prs/flashinfer/PR-2190.md), [feat: unit-test and api change, w4a8 grouped-gemm fused MoE for SM90](../sources/prs/flashinfer/PR-2193.md), [Move the run function definition out of BatchedGemmInterface](../sources/prs/flashinfer/PR-2211.md), [feat: further optimize top-k and add fused top-k page construction kernels for DSA](../sources/prs/flashinfer/PR-2215.md), [feat: Support unpadded output hidden size for trtllm_fp4_block_scale_moe](../sources/prs/flashinfer/PR-2217.md), [fix: add DeepSeek routing for Bf16xBf16 and MxIntxBf16 TRT-LLM Gen MoE](../sources/prs/flashinfer/PR-2234.md), [refactor: pull trtllm-gen batch-gemm/gemm headers from artifactory; update tma descriptor shape init](../sources/prs/flashinfer/PR-2235.md), [[feat] Integrate SGLang concat_mla_k kernel into flashinfer](../sources/prs/flashinfer/PR-2237.md), [feat: RMSNorm/Fused RMSNorm + FP8 Quantization kernels](../sources/prs/flashinfer/PR-2243.md), [Remove cudaStreamSynchronize from gemm_groupwise_sm120.cuh for CUDA graph compatibility](../sources/prs/flashinfer/PR-2244.md), [feat: Support numLocalTokens=0 for moe All-to-all](../sources/prs/flashinfer/PR-2247.md), [feat: support non-contiguous query for trtllm-gen attention backend](../sources/prs/flashinfer/PR-2254.md), [fix: support int64 IdType for RoPE part argument in `rope_quantize_fp8_append_paged_kv_cache`](../sources/prs/flashinfer/PR-2255.md), [[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding](../sources/prs/flashinfer/PR-2265.md), [[performance]optimize for nvfp4](../sources/prs/flashinfer/PR-2268.md), [feat: add GDN Attention](../sources/prs/flashinfer/PR-2276.md), [feat: IdType indices in sampling kernels](../sources/prs/flashinfer/PR-2281.md), [Selective State Update kernel (mamba)](../sources/prs/flashinfer/PR-2301.md), [[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels](../sources/prs/flashinfer/PR-2303.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron](../sources/prs/flashinfer/PR-2304.md), [Fix: FilteredTopKUnifiedKernel read value out of length](../sources/prs/flashinfer/PR-2308.md), [[ML3] Optimized Router Gemm](../sources/prs/flashinfer/PR-2323.md), [bugfix: fix multi-cta top-k implementation when k value is different for different row](../sources/prs/flashinfer/PR-2325.md), [[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32](../sources/prs/flashinfer/PR-2327.md), [fix: guard batchWarpReduceSum with ENABLE_FP8 to fix compilation without FP8](../sources/prs/flashinfer/PR-2328.md), [feat: expose swizzled_input_sf parameter for CUTLASS fused MOE](../sources/prs/flashinfer/PR-2330.md), [Optimize quantization function in large problem size](../sources/prs/flashinfer/PR-2343.md), [Enable fp16/bf16/f32 support for selective_state_update (mamba)](../sources/prs/flashinfer/PR-2366.md), [bugfix: hotfix of PR 2366 (mamba kernel)](../sources/prs/flashinfer/PR-2378.md), [fix: ensure each CTA processes full numHeadsQPerKv for trtllm decode kernel](../sources/prs/flashinfer/PR-2380.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [Remove cudaMalloc/Free in GDN prefill kernel](../sources/prs/flashinfer/PR-2415.md), [feat: update trtllm-gen MoE cubins](../sources/prs/flashinfer/PR-2416.md), [refactor: reduce hopper's gdn prefill compilation time and fix docstring.](../sources/prs/flashinfer/PR-2422.md), [refactor: refactoring cuda code to cute-dsl (part 1)](../sources/prs/flashinfer/PR-2428.md), [fix: Sampling: CUDA Graph fix](../sources/prs/flashinfer/PR-2432.md), [fix: Fix NaN output in mxfp8_quantize for very small input values](../sources/prs/flashinfer/PR-2441.md), [MTP for mamba ](../sources/prs/flashinfer/PR-2444.md), [bugfix: fix stub generation directory in fused_moe module](../sources/prs/flashinfer/PR-2445.md), [feat: Add TRTLLM fmha_v2 library for SM90 attention with Skip-Softmax ](../sources/prs/flashinfer/PR-2446.md), [fix: fix illegal memory access for NaN input in sampling kernels](../sources/prs/flashinfer/PR-2456.md), [feat: Support Fused MoE non gated Relu2 NVFP4 & FP8 and support Nemotron, fixed](../sources/prs/flashinfer/PR-2462.md), [feat: Add MXFP8 GEMM mm_mxfp8 (cutlass)](../sources/prs/flashinfer/PR-2464.md), [feat: Add TRTLLM-Gen Skip-Softmax kernels for prefill and decode](../sources/prs/flashinfer/PR-2477.md), [fix: add support check for gemm config for cutlass moe](../sources/prs/flashinfer/PR-2495.md), [Feat: Trtllm-gen MxFP8 MoE integration](../sources/prs/flashinfer/PR-2505.md), [perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead](../sources/prs/flashinfer/PR-2509.md), [Support NVFP4 KV cache decode on SM120](../sources/prs/flashinfer/PR-2520.md), [misc: point triton blackwell-ptxas to local cuda ptxas](../sources/prs/flashinfer/PR-2543.md), [feat: Enable TRTLLM-Gen Skip-Softmax attention for MLA](../sources/prs/flashinfer/PR-2547.md), [[Bugfix][comm] Fix FP4 one-shot launch config instability in trtllm_allreduce_fusion](../sources/prs/flashinfer/PR-2557.md), [Add support for the combinations of allreduce, allgather, and reducescatter](../sources/prs/flashinfer/PR-2563.md), [fix: W4A8 autotune crash in cutlass_fused_moe profiler workspace](../sources/prs/flashinfer/PR-2564.md), [Implement `cutlass_fused_moe` mxfp8](../sources/prs/flashinfer/PR-2581.md), [feat: trtllm tinygemm2 in flashinfer as bf16 routergemm](../sources/prs/flashinfer/PR-2587.md), [Mamba SSU: better automatic kernel selection + algorithm selection optionally exposed to the user.](../sources/prs/flashinfer/PR-2591.md), [[bugfix] Fix FilteredTopK overflow correctness](../sources/prs/flashinfer/PR-2605.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [fix: add SM121 support to SM120 version guards](../sources/prs/flashinfer/PR-2631.md), [[fp8_blockwise]Fix int32 overflow in TRTLLM fused MoE activation kernel](../sources/prs/flashinfer/PR-2642.md), [feat: FP32 dtype output for BF16 matmuls (CUTLASS & cuDNN)](../sources/prs/flashinfer/PR-2644.md), [int16 Block-Scaled State and Stochastic Rounding for SSU (mamba)](../sources/prs/flashinfer/PR-2645.md), [[feat] trtllm-gen mxfp8 gemm](../sources/prs/flashinfer/PR-2653.md), [feat: implement deterministic topk](../sources/prs/flashinfer/PR-2661.md), [perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act](../sources/prs/flashinfer/PR-2667.md), [fix: reduce smem allocation for tinygemm2 kernel in SM120](../sources/prs/flashinfer/PR-2670.md), [feat: add support for more MLA head dimensions](../sources/prs/flashinfer/PR-2677.md), [Add varlen and speculative decoding support to selective state update](../sources/prs/flashinfer/PR-2700.md), [Add NVFP4 KV cache quantization support for SM100](../sources/prs/flashinfer/PR-2702.md), [feat: Add support for TRTLLM MXFP8 non-gated MoE with ReLU2](../sources/prs/flashinfer/PR-2707.md), [Mamba2 SSD Combined Forward Pass (Blackwell CuTe DSL Kernel)](../sources/prs/flashinfer/PR-2709.md), [feat: Add DiT-oriented kernels where Qk (Bmm1) type can be reinterpreted into Int8 or BFloat16](../sources/prs/flashinfer/PR-2711.md), [fix: Add SM120 (RTX Blackwell desktop) support for NVFP4 MoE kernels](../sources/prs/flashinfer/PR-2725.md), [Support for MXFP4 and NVFP4 group GEMMs on GeForce and Spark](../sources/prs/flashinfer/PR-2738.md), [misc: Update gemm/batched gemm cubins from trtllm-gen, gemm header refactor](../sources/prs/flashinfer/PR-2740.md), [[feat] Add 2048 experts and 32 Top K ](../sources/prs/flashinfer/PR-2744.md), [[feat] Add air top-p algorithm](../sources/prs/flashinfer/PR-2752.md), [feat: Add FP4 KV cache quant/dequant kernels ](../sources/prs/flashinfer/PR-2757.md), [feat: Expose TRT-LLM FMHA style paged KV Cache and page table layout](../sources/prs/flashinfer/PR-2770.md), [feat: FP8 output support for CUTLASS MLA paged attention](../sources/prs/flashinfer/PR-2779.md), [feat: Support padding tokens with seqlen=0 for rope+quant+kv cache update fusion kernel](../sources/prs/flashinfer/PR-2792.md), [Upgrade cutlass 4.2.1 -> 4.4.2](../sources/prs/flashinfer/PR-2798.md), [[fmha-v2] Support HND and NHD paged KV cache layouts with conditional stride handling](../sources/prs/flashinfer/PR-2799.md), [fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE](../sources/prs/flashinfer/PR-2821.md), [[Fmha] Sparse MLA decode kernel selection heuristics](../sources/prs/flashinfer/PR-2836.md), [[Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D](../sources/prs/flashinfer/PR-2841.md), [read real strides for kv and block scale](../sources/prs/flashinfer/PR-2844.md), [fix: int32 overflow in `trtllm_fp4_block_scale_moe` causing "Unsupported hidden state scale shape" for EP32+ configs](../sources/prs/flashinfer/PR-2853.md), [Add support for Relu2 in BF16 fused MoE](../sources/prs/flashinfer/PR-2864.md), [Mamba SSU: horizontal MTP kernel (+ DSTATE=96 support)](../sources/prs/flashinfer/PR-2865.md), [Fix silent bug with FP8 per tensor non-gated MoE](../sources/prs/flashinfer/PR-2882.md), [fix: snap weight_scale_vec_size to handle block_scale_interleave padding for SM120](../sources/prs/flashinfer/PR-2898.md), [feat: add MXFP8 GEMM support for SM120](../sources/prs/flashinfer/PR-2902.md), [feat(gdn): state checkpointing in chunk_gated_delta_rule](../sources/prs/flashinfer/PR-2908.md), [feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners](../sources/prs/flashinfer/PR-2914.md), [feat: add Relu2 (squared ReLU) activation support in CUTLASS MoE backend](../sources/prs/flashinfer/PR-2926.md), [fix: use float instead of double in sampling binary search to avoid FP64 bottleneck on SM103](../sources/prs/flashinfer/PR-2945.md), [Update NVSHMEM interface to use NVSHMEM4Py instead of custom bindings](../sources/prs/flashinfer/PR-2960.md), [Improved `simple` mamba SSU kernel ](../sources/prs/flashinfer/PR-2962.md), [test: xfail cuDNN FP8 prefill on Blackwell with CUDA <= 12.9](../sources/prs/flashinfer/PR-2963.md), [Add flashinfer.fused_rmsnorm_silu() with native kernel backend](../sources/prs/flashinfer/PR-2965.md), [Fused moe all-reduce routed scaling factor + quant support](../sources/prs/flashinfer/PR-2966.md), [fix: restore SM120 CUTLASS MoE tile candidate removed by #2927 (test_trtllm_cutlass_fused_moe.py)](../sources/prs/flashinfer/PR-2984.md), [[Fmha] support nvfp4 output keepsMmaAb generation kernels](../sources/prs/flashinfer/PR-2988.md), [fix: tinygemm2 hang issue due to barrier sync](../sources/prs/flashinfer/PR-2996.md), [perf: Optimize CUTLASS MoE helper kernels for small-batch decode workloads](../sources/prs/flashinfer/PR-3014.md), [fix: extend moe alltoall top-k specializations](../sources/prs/flashinfer/PR-3021.md), [[feat] Add routing_replay_out support to MoE kernels and Python API](../sources/prs/flashinfer/PR-3024.md), [perf: Port TRT-LLM SM120/SM121 FP4 CUTLASS GEMM optimizations. Add PDL](../sources/prs/flashinfer/PR-3026.md), [[feat] Trtllm-gen Per-token Nvfp4 MoE](../sources/prs/flashinfer/PR-3027.md), [fused_moe: pre-filter SM89 tactics with zero occupancy on SM120 Blackwell (fix review feedback on #2764)](../sources/prs/flashinfer/PR-3032.md), [Support lse in trtllm paged attn kernels](../sources/prs/flashinfer/PR-3058.md), [Support Allreduce + Norm + Per-token Group Fp8 Quant Fusion](../sources/prs/flashinfer/PR-3059.md), [Support NVFP4 KV for prefill and batch attention kernels](../sources/prs/flashinfer/PR-3097.md), [feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16](../sources/prs/flashinfer/PR-3129.md), [perf: Add no-bias path for tinygemm_bf16](../sources/prs/flashinfer/PR-3151.md), [Integrate CUTLASS Small Tile N Blockscaled GEMMs/Grouped GEMMs for SM120 and SM121](../sources/prs/flashinfer/PR-3152.md), [feat: DiT layer norm fusions for WAN: flashinfer.diffusion_ops](../sources/prs/flashinfer/PR-3157.md), [feat: enable glm5 router gemm](../sources/prs/flashinfer/PR-3185.md), [[Bugfix] Fix fused MoE autotuning correctness issues by filtering clusterDimZ](../sources/prs/flashinfer/PR-3227.md), [perf: optimize per-token nvfp4 quantization kernel.](../sources/prs/flashinfer/PR-3237.md), [Update moe gemm](../sources/prs/flashinfer/PR-3239.md), [Add dynamic tokens-per-page TRTLLM-GEN GQA kernels](../sources/prs/flashinfer/PR-3259.md), [Update trtllm FMHA cubins](../sources/prs/flashinfer/PR-3317.md), [[feat] Add gemma RMS AR fusion](../sources/prs/flashinfer/PR-3322.md), [checkpointing_ssu kernel: fused replay + conditional state-write for Mamba2](../sources/prs/flashinfer/PR-3324.md), [feat(cute_dsl/moe): add `moe_output_memset_inplace` dense memset wrapper](../sources/prs/flashinfer/PR-3328.md), [perf: fix the iteration bound of SWA in FA2 prefill template](../sources/prs/flashinfer/PR-714.md), [bugfix: FusedAddRMSNorm kernels might require more than 48KB shared memory when d is large.](../sources/prs/flashinfer/PR-718.md), [Align KV chunk size binary search with actual KV chunk splitting.](../sources/prs/flashinfer/PR-728.md), [Change `apply_rope_with_cos_sin_cache` to accept `cos_sin_cache`](../sources/prs/flashinfer/PR-754.md), [feat: support deepseek prefill attention shape](../sources/prs/flashinfer/PR-765.md), [bugfix: Ensure Loop Termination by Enforcing IEEE-754 Compliance in Sampling Kernels](../sources/prs/flashinfer/PR-774.md), [perf: refactor fa2 prefill template](../sources/prs/flashinfer/PR-776.md), [bugfix: drop CTA_TILE_Q=32](../sources/prs/flashinfer/PR-785.md), [bugfix: MLA decode should multiply sm_scale by math::log2e](../sources/prs/flashinfer/PR-787.md), [fix rope logic in mla decoding](../sources/prs/flashinfer/PR-793.md), [feat: support f32 attention output in FA2 template](../sources/prs/flashinfer/PR-799.md), [feat: apply sm_scale at logits instead of q in FA2 template](../sources/prs/flashinfer/PR-801.md), [perf: memory efficient deepseek mla fused page-attention kernel](../sources/prs/flashinfer/PR-804.md), [bugfix: mla page-attention kernel for different page sizes](../sources/prs/flashinfer/PR-810.md), [feat: unlocking MLA for A100](../sources/prs/flashinfer/PR-812.md), [feat: unlock MLA attention for sm89 (L40/L40s/4090)](../sources/prs/flashinfer/PR-814.md), [bugfix: bugfix on sm89 MLA](../sources/prs/flashinfer/PR-821.md), [bugfix: fix the signature of `CutlassSegmentGEMMSM90`](../sources/prs/flashinfer/PR-827.md), [perf: MLA decode kernel implemented by CuTe targeted to SM80](../sources/prs/flashinfer/PR-844.md), [misc: Remove duplicate param set in MLA kernel](../sources/prs/flashinfer/PR-850.md), [Add POD-Attention to FlashInfer](../sources/prs/flashinfer/PR-858.md), [perf: dynamic split-k for MLA](../sources/prs/flashinfer/PR-863.md), [bugfix: fix the behavior of MLA kernel when kv-length is 0](../sources/prs/flashinfer/PR-868.md), [Naive Support for Hopper FP8 Prefill Kernel with Per-Head Quantization](../sources/prs/flashinfer/PR-869.md), [perf: FlashAttention-3 style MLA PageAttention](../sources/prs/flashinfer/PR-887.md), [feat - support mla kvcache store](../sources/prs/flashinfer/PR-888.md), [perf: fix MLA split-k performance bug](../sources/prs/flashinfer/PR-898.md), [perf: tweak the pipeline design of mla kernel](../sources/prs/flashinfer/PR-901.md), [feat: flashinfer intra-kernel profiler](../sources/prs/flashinfer/PR-913.md), [feat: experimenta support of PDL](../sources/prs/flashinfer/PR-930.md), [bugfix: fix potential issues of FA3 template loading nans for PageAttention](../sources/prs/flashinfer/PR-945.md), [perf: Use 2WG pipeline design for MLA implementation on Hopper](../sources/prs/flashinfer/PR-952.md), [[TVM] Added tvm binding for sampling kernel](../sources/prs/flashinfer/PR-958.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [perf: dual pivot top-p/top-k renorm](../sources/prs/flashinfer/PR-974.md), [perf: prefetch page indices for mla kernel](../sources/prs/flashinfer/PR-991.md), [feat: SM-constraint Communication Kernels](../sources/prs/flashinfer/PR-994.md), [3rdparty: upgrade cutlass to 3.9](../sources/prs/flashinfer/PR-997.md), [ROCm SDPA: Ensure attn_mask has the same dtype with q](../sources/prs/pytorch/PR-144398.md), [Add release branch push triggers to inductor-rocm-mi300.yml](../sources/prs/pytorch/PR-149871.md), [[CUDA][avgpool2d] Fix backward launch bounds again for sm100, sm120](../sources/prs/pytorch/PR-150640.md), [[CUDA][avgpool2d] Fix backward launch bounds again for `sm100`, `sm120`](../sources/prs/pytorch/PR-150676.md), [[CUDA] Only use vec128 if CUDA version is newer than 12.8](../sources/prs/pytorch/PR-150705.md), [[ATen][CUDA] Optimize 128 bit vectorization](../sources/prs/pytorch/PR-152967.md), [Fix uint view copy (#151598)](../sources/prs/pytorch/PR-154121.md), [Fix macOS build with `USE_MPS=OFF`](../sources/prs/pytorch/PR-156932.md), [[user triton] AOT inductor support for device-side TMA](../sources/prs/pytorch/PR-157241.md), [[PowerPC] Fixed build issue for vsx vec256 complexfloat and scaled_mm_out_cpu ](../sources/prs/pytorch/PR-157422.md), [[cherry-pick][inductor][triton] Update HAS_WARP_SPEC to check triton.Config params. Update Triton Hash to top of release/3.4.x stack](../sources/prs/pytorch/PR-158646.md), [CUDA 13.0 Windows Nvidia Driver Update to 580.88](../sources/prs/pytorch/PR-162501.md), [fix cpp extension distributed warning spew](../sources/prs/pytorch/PR-162764.md), [[Graph Partition] improve custom op output alias](../sources/prs/pytorch/PR-163380.md), [[graph partition] Add way to register custom rule (#163310)](../sources/prs/pytorch/PR-163395.md), [CUDA 13.0 Warning update for supported architectures](../sources/prs/pytorch/PR-163633.md), [[Cherry-Pick] [CD] CUDA 13 specific followup changes. Remove sm50-70 From CUDA 12.6 and CUDA 12.8 builds (#162455)](../sources/prs/pytorch/PR-163764.md), [[CD] CUDA 13.0 fix preload logic to include nvidia/cu13/lib/](../sources/prs/pytorch/PR-163766.md), [Move inductor jobs 3.9->3.10](../sources/prs/pytorch/PR-163954.md), [[cuDNN][SDPA] Disable dropout for cuDNN SDPA on 9.11 - 9.13](../sources/prs/pytorch/PR-164026.md), [[AARCH64][CD][CUDA13][Triton][PTXAS] Turn on BUILD_BUNDLE_PTXAS=1 ](../sources/prs/pytorch/PR-164236.md), [CUDA 13.0 builds fix on Amazon Linux 2023](../sources/prs/pytorch/PR-164893.md), [[Graph Partition] move custom rules to inductor config (#166458)](../sources/prs/pytorch/PR-166967.md), [[Graph Partition] fix graph partition input signature for fallback kernels](../sources/prs/pytorch/PR-166985.md), [[cuDNN][SDPA][Convolution] Expose cuDNN runtime version in CUDA hooks](../sources/prs/pytorch/PR-167327.md), [[ROCm] Enable shared memory based pruning for Triton configs](../sources/prs/pytorch/PR-170190.md), [[inductor] Fix cudagraph skip for index_put_ with boolean indices, gr…](../sources/prs/pytorch/PR-170884.md), [[ROCm] Make grouped GEMM CK opt‑in via env and default to fallback path](../sources/prs/pytorch/PR-171140.md), [[cherry-pick][CUDA] Upgrade cuDNN to 9.15.1 for CUDA 13 builds ](../sources/prs/pytorch/PR-171189.md), [[cherry-pick][cuDNN][SDPA] cuDNN SDPA off-by-default for cuDNN versions < 12.9 (#171627)](../sources/prs/pytorch/PR-171895.md), [Skip modded_nanogpt model in TorchInductor benchmark](../sources/prs/pytorch/PR-172141.md), [[Graph Partition] Improve support for mutation ops](../sources/prs/pytorch/PR-172577.md), [Update inductor expected accuracy files](../sources/prs/pytorch/PR-175096.md), [[benchmark] Skip pytorch_CycleGAN_and_pix2pix from inductor benchmarks](../sources/prs/pytorch/PR-175299.md), [[release-only] Remove +ptx from cuda 13.0 builds](../sources/prs/pytorch/PR-175567.md), [[release 2.12] Apply Release only changes to 2.12 branch](../sources/prs/pytorch/PR-180470.md), [Disable kernel cutlass_mla_decode on SM103](../sources/prs/sglang/PR-10058.md), [Optimize nvfp4 block scaled gemm kernel when M is small.](../sources/prs/sglang/PR-10101.md), [fix: resolve gb200 image link](../sources/prs/sglang/PR-10343.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [Update CUTLASS. Refine KernelSchedule for fp8 (grouped) gemm.](../sources/prs/sglang/PR-10491.md), [[sgl-kernel] Optimize concat_mla_k kernel](../sources/prs/sglang/PR-10543.md), [Optimize cutlass int8 gemm kernel for large M on SM89 Ada GPU](../sources/prs/sglang/PR-10714.md), [disable sm100 for FlashMLA and fast-hadamard-transform in cuda12.6.1](../sources/prs/sglang/PR-11274.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [Improve Kernel Build Time](../sources/prs/sglang/PR-11508.md), [support cutlass fp4 kernel in sm120](../sources/prs/sglang/PR-11737.md), [Fixed aarch64 flash-mla](../sources/prs/sglang/PR-12009.md), [(1/n)support context parallel with deepseekv3.2-DSA](../sources/prs/sglang/PR-12065.md), [[sgl-kernel][4/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12080.md), [[sgl-kernel] clean up fa fetch in CMakeLists.txt](../sources/prs/sglang/PR-12392.md), [[Fix] `concat_mla_absorb_q_kernel` fails for long inputs](../sources/prs/sglang/PR-12453.md), [[NVIDIA] Fix CUDA arch requirement in nvfp4 cast](../sources/prs/sglang/PR-12581.md), [Support moe topk sigmoid kernel](../sources/prs/sglang/PR-13049.md), [diffusion: enable fa4 for blackwell](../sources/prs/sglang/PR-13263.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [[kernel][moe] add moe topk fast](../sources/prs/sglang/PR-13969.md), [Add new moe wna16 marlin gemm](../sources/prs/sglang/PR-14122.md), [Opt moe align block size kernel](../sources/prs/sglang/PR-14133.md), [sync attention, deepseek doc](../sources/prs/sglang/PR-14335.md), [[CPU] Implement MXFP4 Gemm kernels for intel AMX to support GPT OSS series.](../sources/prs/sglang/PR-14385.md), [Add CUDA kernel size analysis tool for sgl-kernel optimization](../sources/prs/sglang/PR-14544.md), [[sgl-kernel][Feat][B200][2/N] Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-14640.md), [[NPU][eagle3] support qwen eagle3 on NPU](../sources/prs/sglang/PR-14820.md), [[sgl-kernel][1/2] Fused qk_norm_rope for GLM4.6](../sources/prs/sglang/PR-15141.md), [Add cache for flashinfer installation](../sources/prs/sglang/PR-15153.md), [[sgl-kernel] Update flashmla to include fp8 sparse_mla optimizations](../sources/prs/sglang/PR-15242.md), [Fix warp illegal instruction in kimi k2 thinking PCG](../sources/prs/sglang/PR-15306.md), [[diffusion] Add Sage Attention 3 Support for sm 120 (RTX5090)](../sources/prs/sglang/PR-15382.md), [[sgl-kernel][6/7]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-15471.md), [[Feature] JIT Fused QK norm + qk norm clean up](../sources/prs/sglang/PR-15835.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [[Feature] add aligned_vector type for JIT kernel](../sources/prs/sglang/PR-16162.md), [Fix sgl-kernel jobs to skip when target_stage is specified](../sources/prs/sglang/PR-16308.md), [[diffusion] Fix RuntimeError in SageAttention3 on Nvidia Blackwell with Qwen-Image](../sources/prs/sglang/PR-16335.md), [[Fix]Pin mooncake version to 0.3.7.post2 in grace blackwell](../sources/prs/sglang/PR-16502.md), [[DeepSeek v3.2] Opt MTP decode cuda batch sizes and nsa implementation](../sources/prs/sglang/PR-16961.md), [Kernel: optimize decoding metadata in NSA multi-spec backend with fused kernels](../sources/prs/sglang/PR-17554.md), [Make flashMLA work on: Cu13, B300](../sources/prs/sglang/PR-17600.md), [Feature/support longcat flash lite](../sources/prs/sglang/PR-17838.md), [[Move sgl-kernel Kernel to JIT] Add JIT concat MLA kernels](../sources/prs/sglang/PR-17889.md), [[Diffsuion & JIT_kernel] QKNorm cross heads kernel](../sources/prs/sglang/PR-18073.md), [[Hicache & JIT_kernel] Support page first layout & mla jit kernel](../sources/prs/sglang/PR-18311.md), [docs: expand and update modelopt documentation](../sources/prs/sglang/PR-18479.md), [[FIX] Correct JIT kernel compilation on newer GPUs with outdated driver metadata.](../sources/prs/sglang/PR-18496.md), [Add claude skills for sgl-kernel and jit-kernel](../sources/prs/sglang/PR-18855.md), [Use single mma warp group for short q_len in FA to optimize decoding performance](../sources/prs/sglang/PR-18985.md), [[jit_kernel] Add fused_qknorm_rope JIT kernel](../sources/prs/sglang/PR-19059.md), [[DeepSeek-V3.2][JIT-kernel] Support nsa fuse store indexer k cache](../sources/prs/sglang/PR-19148.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Add compile-time 256-bit vector guard for pre-Blackwell](../sources/prs/sglang/PR-19794.md), [[JIT Kernel][Feature] Support JIT custom all reduce (rewrite as v2)](../sources/prs/sglang/PR-19880.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[diffusion] Support nvfp4 for Flux.2](../sources/prs/sglang/PR-20137.md), [fix ci by removing nvidia-cutlass-dsl-libs-base and force reinstall n…](../sources/prs/sglang/PR-20380.md), [fix(docs): correct quantization documentation (#20301)](../sources/prs/sglang/PR-20619.md), [Fix(jit): support rmsnorm for hidden_size in {64, 128, 256}](../sources/prs/sglang/PR-20661.md), [[Feature][JIT Kernel] Fused TP QK norm For Minimax](../sources/prs/sglang/PR-20673.md), [CUTLASS FP8 Blockwise GEMM improvement of SM120](../sources/prs/sglang/PR-20887.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Tiny Fix] Fix IS_BLACKWELL env var empty string warning in rerun-ut workflow](../sources/prs/sglang/PR-20957.md), [ci: run Stage A CUDA tests as stage-a-test-small-1-gpu on 5090](../sources/prs/sglang/PR-20988.md), [[Whisper] Enable CUDA graph support and timestamp for whisper model](../sources/prs/sglang/PR-21190.md), [Split pr-test.yml: extract sgl-kernel, jit-kernel, and multimodal-gen tests into separate workflow files](../sources/prs/sglang/PR-21219.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[Diffusion] Add qknorm rope fuse kernel](../sources/prs/sglang/PR-21440.md), [fix: piecewise_cuda_graph get correct qo_indptr](../sources/prs/sglang/PR-21452.md), [fix: TRT-LLM MHA CUDA illegal address with EAGLE v2 + DP attention](../sources/prs/sglang/PR-21649.md), [[jit_kernel] Optimize fused_qknorm_rope: deduplicate sincosf for interleave RoPE ](../sources/prs/sglang/PR-21654.md), [Remove flashinfer wheel cache cleanup that deletes other versions](../sources/prs/sglang/PR-21711.md), [[Feature] JIT rmsnorm update (with claude)](../sources/prs/sglang/PR-21834.md), [[Bugfix] Fix CUDA graph replay issues in trtllm_mla draft_extend](../sources/prs/sglang/PR-21987.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[diffusion] Default NVFP4 to CUTLASS and add all-model shape benchmarks](../sources/prs/sglang/PR-22091.md), [Lazy import flash_attention_v4 to avoid loading flash_attn.cute at startup](../sources/prs/sglang/PR-22306.md), [[Docker] Fix Trivy CVEs, cubin download 403s, and kernels command order](../sources/prs/sglang/PR-22322.md), [[CI/Docker] Clean up redundant flashinfer cubin downloads](../sources/prs/sglang/PR-22491.md), [[Docker] Remove flashinfer cache copy](../sources/prs/sglang/PR-22653.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [[Diffusion] Add Wan2.2 ModelOpt NVFP4 support](../sources/prs/sglang/PR-22681.md), [[Fix] Fix accuracy bug in Flashmla sparse MLA kernel](../sources/prs/sglang/PR-22723.md), [Dual MoE CUDA graph capture for lora/nolora batches](../sources/prs/sglang/PR-22809.md), [[Fix/Kernel] Add JIT rmsnorm_hf kernel to fix transformers backend MMLU accuracy regression ](../sources/prs/sglang/PR-22931.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [[feat] Init true on policy with qwen_dense](../sources/prs/sglang/PR-23961.md), [Enable PDL for various kernels in DSV32/GLM5](../sources/prs/sglang/PR-23965.md), [[VLM] Optimize Gemma4 VLM with PCG and fuse RMSNorm + residual add + scalar](../sources/prs/sglang/PR-24048.md), [Refactor device timer, clean up metrics collector, and add fwd occupancy metric](../sources/prs/sglang/PR-24197.md), [[codex] Optimize hidden-size 512 RMSNorm dispatch](../sources/prs/sglang/PR-24710.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [Support draft extend cuda graph for tokenspeed_mla attention backend](../sources/prs/sglang/PR-25489.md), [[fp8] SM90 swap-AB scaled_mm dispatch (~1.16x kernel geomean, +5.8-18.5% end-to-end)](../sources/prs/sglang/PR-25532.md), [fix (jit kernel): elementwise activation C++ error](../sources/prs/sglang/PR-25695.md), [[Codex] Remove stale DeepSeek V4 JIT kernels](../sources/prs/sglang/PR-25764.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Support cutlass Int8 gemm](../sources/prs/sglang/PR-2752.md), [upgrade cutlass v3.7.0](../sources/prs/sglang/PR-2967.md), [feat: add flashinfer as 3rdparty and use rmsnorm as example](../sources/prs/sglang/PR-3033.md), [Support sm90 Int8 gemm](../sources/prs/sglang/PR-3035.md), [support w8a8 fp8 kernel with CUTLASS](../sources/prs/sglang/PR-3047.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [add tensorrt_llm common and cutlass_extensions as 3rdparty](../sources/prs/sglang/PR-3216.md), [support blockwise fp8 matmul kernel](../sources/prs/sglang/PR-3267.md), [fix undefined symbol cudaGetDriverEntryPointByVersion](../sources/prs/sglang/PR-3372.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [[Feature] Apply Cublas Grouped Gemm kernel](../sources/prs/sglang/PR-3629.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [Support overlapping two batches](../sources/prs/sglang/PR-4068.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [fix per_token_group_quant_fp8 illegal memory when num_groups % 16 != 0](../sources/prs/sglang/PR-4231.md), [add THIRDPARTYNOTICES for DeepGEMM](../sources/prs/sglang/PR-4272.md), [Support Blackwell Block Scale FP8 Gemm](../sources/prs/sglang/PR-4278.md), [update deepgemm](../sources/prs/sglang/PR-4284.md), [Add deepseek style fused moe group gate selection kernel](../sources/prs/sglang/PR-4530.md), [[Fix] Fix raw_bs bug when using flashinfer mla and eagle](../sources/prs/sglang/PR-4557.md), [Support fp8 gemm for blackwell](../sources/prs/sglang/PR-4558.md), [avoid cudaStreamSynchronize in DeepSeekV2AttentionMLA](../sources/prs/sglang/PR-4577.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [Support (1 <= dp < tp) in the dp attention in DeepEP](../sources/prs/sglang/PR-4770.md), [[Feat] support deepgemm for cmake](../sources/prs/sglang/PR-4864.md), [[Build] Fix cuda12.8 build error in nvfp4_scaled_mm_kernels.cu](../sources/prs/sglang/PR-4953.md), [update cutlass tag](../sources/prs/sglang/PR-5011.md), [fix deepgemm as well](../sources/prs/sglang/PR-5030.md), [support sgl-kernel on blackwell](../sources/prs/sglang/PR-5074.md), [reduce moe_align_block_size_kernel small batch mode overhead](../sources/prs/sglang/PR-5086.md), [Blackwell Cutlass MLA kernel](../sources/prs/sglang/PR-5142.md), [[1/2] Add FP8 Blockscale MoE CUTLASS kernel for Blackwell](../sources/prs/sglang/PR-5281.md), [fix: solve cu118 issue for cutlass mla](../sources/prs/sglang/PR-5331.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [chore: upgrade DeepGEMM](../sources/prs/sglang/PR-5395.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [feat: use flashinfer jit package](../sources/prs/sglang/PR-5547.md), [[2/2] Add python wrapper for CUTLASS FP8 Blockscale MoE Kernel. ](../sources/prs/sglang/PR-5694.md), [[PP] Add pipeline parallelism](../sources/prs/sglang/PR-5724.md), [cutlass 3.9 supported to improve fp8_blockwise_gemm](../sources/prs/sglang/PR-5820.md), [Add sm_120 for blackwell](../sources/prs/sglang/PR-5903.md), [chore: upgrade cutlass 3.9.2](../sources/prs/sglang/PR-6004.md), [chore: upgrade deepgemm](../sources/prs/sglang/PR-6073.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [Cutlass MLA: Disable split kv due to https://github.com/NVIDIA/cutlass/issues/2274](../sources/prs/sglang/PR-6101.md), [Upgrade CUTLASS 4.0](../sources/prs/sglang/PR-6336.md), [reduce torch.zeros overhead in moe align block size kernel](../sources/prs/sglang/PR-6369.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [Fix bug of deepseek-v3 under DP+EP mode with large batchsize/seqlen](../sources/prs/sglang/PR-6449.md), [[EP] Add cuda kernel for moe_ep_pre_reorder](../sources/prs/sglang/PR-6699.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [Correctly abort the failed grammar requests & Improve the handling of abort](../sources/prs/sglang/PR-6803.md), [[EP] Add cuda kernel for moe_ep_post_reorder](../sources/prs/sglang/PR-6837.md), [Fix AWQ Dequant and Weight Loading of deepseek v2](../sources/prs/sglang/PR-6842.md), [fix ep_moe_reorder kernel bugs](../sources/prs/sglang/PR-6858.md), [Add a CUDA kernel for fusing mapping and weighted sum for MoE.](../sources/prs/sglang/PR-6916.md), [[sgl-kernel] Add cuda kernel for moe_ep_silu_and_mul](../sources/prs/sglang/PR-6919.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [Clean up server_args.py](../sources/prs/sglang/PR-7037.md), [Tiny fix cutlass_mla_get_workspace_size stub incorrect signature](../sources/prs/sglang/PR-7057.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [feat: support compatibility between MTP and two-batch-overlap](../sources/prs/sglang/PR-7225.md), [Add CUTLASS FP8 Blockscale MoE kernel for Hopper architecture](../sources/prs/sglang/PR-7278.md), [fix: resolve blackwell deepep image issue](../sources/prs/sglang/PR-7331.md), [Fuse sorted_token_ids padding to moe_align_block_size kernel](../sources/prs/sglang/PR-7437.md), [fix: fix apply_shuffle_mul_sum](../sources/prs/sglang/PR-7444.md), [[CMake] Fix sgl-kernel CMakeLists for Blackwell](../sources/prs/sglang/PR-7543.md), [Add dsv3 router gemm kernel](../sources/prs/sglang/PR-7627.md), [Add dsv3 fused a gemm to sgl-kernel](../sources/prs/sglang/PR-7630.md), [[Feature] CUDA Green Context Support](../sources/prs/sglang/PR-7649.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [[kernel] opt moe align block kernel by block/warp scan algorithm](../sources/prs/sglang/PR-7884.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [[Fix][Ready]Fix register spilling in cutlass nvfp4 gemm kernel on Blackwell](../sources/prs/sglang/PR-8127.md), [[sgl-kernel] Opt per_token_quant_fp8 with warp reduce](../sources/prs/sglang/PR-8130.md), [[2/N]Support DeepSeek-R1 w4a8 low latency deepep](../sources/prs/sglang/PR-8464.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/sglang/PR-8818.md), [chore: support blackwell cu129 image](../sources/prs/sglang/PR-8928.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [Support trtllm_allreduce_fusion in flashinfer for cuda<12.8](../sources/prs/sglang/PR-9339.md), [[sgl-kernel] feat: Support sm120 cutlass fp8 gemm kernel](../sources/prs/sglang/PR-9403.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [Make sm100 fp8 kernels available on sm103](../sources/prs/sglang/PR-9789.md), [Make fp4_quantize kernels work on sm103](../sources/prs/sglang/PR-9807.md), [CUTLASS fp8 blockwise gemm support of sm120](../sources/prs/sglang/PR-9969.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feat] profiler support cudagraph backend](../sources/prs/tilelang/PR-1658.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add T.copy_cluster to support TMA multicast and SM-to-SM cluster copy](../sources/prs/tilelang/PR-1908.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[CUDA] Improve int4 GEMM lowering and packed codegen support](../sources/prs/tilelang/PR-2073.md), [[Bugfix] Enable `.shared::cta` in TMA copy paths only on CUDA 12.8+](../sources/prs/tilelang/PR-2087.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[CUDA] Add native SM75 MMA GEMM support for FP16, INT8 and INT4](../sources/prs/tilelang/PR-2198.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[Kernel]: Cutlass 2:4 Sparsity + FP8/Int8 Quant Support](../sources/prs/vllm/PR-10995.md), [[Kernel] Update `cutlass_scaled_mm` to support 2d group (blockwise) scaling](../sources/prs/vllm/PR-11868.md), [[Build] Only build 9.0a for scaled_mm and sparse kernels](../sources/prs/vllm/PR-12339.md), [[ROCm] Faster Custom Paged Attention kernels](../sources/prs/vllm/PR-12348.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Kernel] port sgl moe_align_block_size kernels](../sources/prs/vllm/PR-12574.md), [[Kernel][Quantization] Integrate block-quantized CUTLASS kernels for DeepSeekV3](../sources/prs/vllm/PR-12587.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [[Core][AMD] Migrate fully transparent sleep mode to ROCm platform](../sources/prs/vllm/PR-12695.md), [[Bugfix][Kernel] Fix per-token/per-channel quantization for Hopper scaled mm](../sources/prs/vllm/PR-12696.md), [[Kernel] Make rotary_embedding ops more flexible with input shape](../sources/prs/vllm/PR-12777.md), [[NVIDIA] Support nvfp4 quantization](../sources/prs/vllm/PR-12784.md), [Optimize moe_align_block_size for deepseek_v3](../sources/prs/vllm/PR-12850.md), [[Misc][Kernel]: Add GPTQAllSpark Quantization](../sources/prs/vllm/PR-12931.md), [[Kernel]Add streamK for block-quantized CUTLASS kernels](../sources/prs/vllm/PR-12978.md), [[Kernel] moe wna16 cuda kernel](../sources/prs/vllm/PR-13321.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[ROCm][MoE] mi300 mixtral8x7B perf for specific BS](../sources/prs/vllm/PR-13577.md), [[Kernel] FlashMLA integration](../sources/prs/vllm/PR-13747.md), [[Attention] MLA support for V1](../sources/prs/vllm/PR-13789.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [[ROCm] Disable chunked prefill/prefix caching when running MLA on non-cuda platforms](../sources/prs/vllm/PR-13844.md), [[Attention] Flash MLA for V1](../sources/prs/vllm/PR-13867.md), [[V1] EP/TP MoE + DP Attention](../sources/prs/vllm/PR-13931.md), [[Kernel] CUTLASS grouped gemm fp8 MoE kernel](../sources/prs/vllm/PR-13972.md), [[Kernel] optimize performance of gptq marlin kernel when n is small](../sources/prs/vllm/PR-14138.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[Attention] FlashAttn MLA](../sources/prs/vllm/PR-14258.md), [fix minor miscalled method](../sources/prs/vllm/PR-14327.md), [[Build/BugFix] Fix hopper 12.8 build](../sources/prs/vllm/PR-14354.md), [Add cutlass support for blackwell fp8 blockwise gemm](../sources/prs/vllm/PR-14383.md), [[BugFix] Illegal Memory Access in the blockwise cutlass fp8 GEMMs](../sources/prs/vllm/PR-14396.md), [[Kernel] moe wna16 marlin kernel](../sources/prs/vllm/PR-14447.md), [permute/unpermute kernel for moe optimization](../sources/prs/vllm/PR-14568.md), [[Attention] Flash Attention 3 - fp8](../sources/prs/vllm/PR-14570.md), [[BugFix/Build] Fix sparse kernels not getting built on hopper](../sources/prs/vllm/PR-14572.md), [[Kernel] GGUF MoE kernel](../sources/prs/vllm/PR-14613.md), [[Kernel] allow non-contiguous input for marlin kernel](../sources/prs/vllm/PR-14658.md), [[Bugfix][Kernel][CPU] Fix num_tokens in CPU rotary embedding kernel](../sources/prs/vllm/PR-14667.md), [[V1] Fully Transparent Implementation of CPU Offloading](../sources/prs/vllm/PR-15354.md), [[Kernel] Fix conflicting macro names for gguf kernels](../sources/prs/vllm/PR-15456.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [[Bugfix] fix use_atomic_add support of marlin kernel when using v1 engine](../sources/prs/vllm/PR-15946.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[ROCM] Add gfx950 to the custom attention archs](../sources/prs/vllm/PR-16034.md), [Add FlexAttention to V1](../sources/prs/vllm/PR-16078.md), [[Kernel] support merge_attn_states CUDA kernel, 3x speedup](../sources/prs/vllm/PR-16173.md), [[Hardware/NVIDIA/Kernel] [Functional Enablement] [1/N] Enable nvidia/DeepSeek-R1-FP4 Model](../sources/prs/vllm/PR-16362.md), [Allocate kv_cache with stride order](../sources/prs/vllm/PR-16605.md), [[V1] V1 FlashInfer Attention](../sources/prs/vllm/PR-16684.md), [[misc] ignore marlin_moe_wna16 local gen codes](../sources/prs/vllm/PR-16760.md), [[Kernel] GGUF MoeVec kernel](../sources/prs/vllm/PR-16780.md), [[BugFix] Accuracy fix for llama4 int4 - improperly casted scales](../sources/prs/vllm/PR-16801.md), [[Kernel] some optimizations for dense marlin and moe marlin](../sources/prs/vllm/PR-16850.md), [Update PyTorch to 2.7.0](../sources/prs/vllm/PR-16859.md), [[Kernel] Add expert_map support to Cutlass FP8 MOE](../sources/prs/vllm/PR-16861.md), [[Attention] FA3 decode perf improvement - single mma warp group support for head dim 128](../sources/prs/vllm/PR-16864.md), [Update Qwen1.5-MoE-W4A16-compressed-tensors.yaml](../sources/prs/vllm/PR-16946.md), [[ROCm][Kernel][V1] Enable AMD Radeon GPU Custom Paged Attention on v1](../sources/prs/vllm/PR-17004.md), [Fix `numel()` downcast in vllm/csrc/moe/moe_align_sum_kernels.cu +2](../sources/prs/vllm/PR-17082.md), [[ROCm][FP8][Kernel] FP8 quantization fused into Custom Paged Attention](../sources/prs/vllm/PR-17139.md), [[NVIDIA] Support Cutlass w8a8 FP8 for Blackwell Geforce GPUs (sm120)](../sources/prs/vllm/PR-17280.md), [[Misc][ROCm] Exclude `cutlass_mla_decode` for ROCm build](../sources/prs/vllm/PR-17289.md), [[Attention] MLA move o_proj q_proj into cuda-graph region](../sources/prs/vllm/PR-17484.md), [[Attention] MLA move rotary embedding to cuda-graph region](../sources/prs/vllm/PR-17668.md), [[Kernel] fp4 marlin kernel](../sources/prs/vllm/PR-17687.md), [[Kernel] Have rotary embeddings support tensors](../sources/prs/vllm/PR-18046.md), [Fix Broken macro for cutlass moe](../sources/prs/vllm/PR-18049.md), [[Build] Supports CUDA 12.6 and 11.8 after Blackwell Update](../sources/prs/vllm/PR-18316.md), [Sm100 blockwise fp8 swap ab](../sources/prs/vllm/PR-18564.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Perf] Tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-18778.md), [[BugFix] FA2 MLA Accuracy Issue](../sources/prs/vllm/PR-18807.md), [[Hardware][NVIDIA] FP4 MoE kernel optimization](../sources/prs/vllm/PR-19110.md), [[V1] Use FlashInfer by default on Blackwell GPUs](../sources/prs/vllm/PR-19118.md), [[Bugfix][V1] Allow manual FlashAttention for Blackwell](../sources/prs/vllm/PR-19492.md), [[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization](../sources/prs/vllm/PR-19500.md), [[Perf] Further tunings for SM100 FP8 CUTLASS kernel](../sources/prs/vllm/PR-19566.md), [Only build CUTLASS MoE kernels on Hopper](../sources/prs/vllm/PR-19648.md), [[feat]: CUTLASS block scaled group gemm for SM100](../sources/prs/vllm/PR-19757.md), [Fix FA2 fallback for Blackwell V1](../sources/prs/vllm/PR-19781.md), [[Bugfix] Build moe_data for both sm100 and sm90](../sources/prs/vllm/PR-20086.md), [[Bugfix] Fix some narrowing conversion warnings](../sources/prs/vllm/PR-20141.md), [Replace `multiply_add` with `homogeneous_multiply_add` to Address Clang Template Parameter Issue](../sources/prs/vllm/PR-20142.md), [[Bugfix] Fix topk_ids indices_type for CUTLASS w8a8 FP8 MoE](../sources/prs/vllm/PR-20166.md), [[Kernel][Bugfix] Fixup some warnings in nvfp4_blockwise_moe when CUDA < 12.8](../sources/prs/vllm/PR-20324.md), [Update PyTorch to 2.8.0](../sources/prs/vllm/PR-20358.md), [[Kernel] SM90 CUTLASS FP8 GEMM: add support for swap AB + kernel tuning](../sources/prs/vllm/PR-20396.md), [[feat]: add SM100 support for cutlass FP8 groupGEMM](../sources/prs/vllm/PR-20447.md), [[Performance] Performance improvements in non-blockwise fp8 CUTLASS MoE](../sources/prs/vllm/PR-20762.md), [SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP](../sources/prs/vllm/PR-20769.md), [[fix]: disable cutlass block scaled group gemm for EP](../sources/prs/vllm/PR-20781.md), [[Perf] Add swap_ab to SM90 FP8 non-block CUTLASS moe grouped gemm](../sources/prs/vllm/PR-20911.md), [Support mnnvl all2allv from Flashinfer](../sources/prs/vllm/PR-21003.md), [[Kernel] Flashinfer MLA (trtllm-gen) decode kernel integration](../sources/prs/vllm/PR-21078.md), [[Perf] Cuda Kernel for Per Token Group Quant](../sources/prs/vllm/PR-21083.md), [[perf] Add fused MLA QKV + strided layernorm](../sources/prs/vllm/PR-21116.md), [[Perf] Use FlashInfer RoPE for RotaryEmbedding.forward_cuda when available](../sources/prs/vllm/PR-21126.md), [[Feature][Kernel]FusedMoE LoRA](../sources/prs/vllm/PR-21229.md), [[v1] - Mamba1 Attention Metadata](../sources/prs/vllm/PR-21249.md), [Support CUTLASS NVFP4 (w4a4) for Blackwell Geforce GPUs (SM120)](../sources/prs/vllm/PR-21309.md), [[Bugfix][CUDA] fixes CUDA FP8 kv cache dtype supported](../sources/prs/vllm/PR-21420.md), [[Bug] Fix Compressed Tensor NVFP4 `cutlass_fp4_group_mm` illegal memory access](../sources/prs/vllm/PR-21465.md), [[Kernel] Improve machete memory bound perf](../sources/prs/vllm/PR-21556.md), [[BugFix] Fix IMA FlashMLA full cuda-graph and DP + Update FlashMLA](../sources/prs/vllm/PR-21691.md), [update flashinfer to v0.2.9rc2](../sources/prs/vllm/PR-21701.md), [Fix Flashinfer CUTLASS MOE Allgather](../sources/prs/vllm/PR-21963.md), [[Kernel] Add support for block FP8 on SM120 (NVIDIA 5090 and RTX PRO 6000)](../sources/prs/vllm/PR-22131.md), [Fp8 paged attention update](../sources/prs/vllm/PR-22222.md), [Upgrade FA3 for attention sink](../sources/prs/vllm/PR-22313.md), [[Attention] FA3 Attention Sinks Perf Boost](../sources/prs/vllm/PR-22478.md), [[Fix] enable swap_ab for pplx problem size computation](../sources/prs/vllm/PR-22991.md), [[Kernel] CUTLASS MoE FP8: Integrate cuda moe permute/unpermute](../sources/prs/vllm/PR-23045.md), [[V1] address post issues related to #20059 (part 1); cascade attention reenable by default](../sources/prs/vllm/PR-23046.md), [[kernel] Support W4A8 on Hopper](../sources/prs/vllm/PR-23198.md), [[Kernel] Add fused grouped_topk kernel for MoE](../sources/prs/vllm/PR-23274.md), [[Perf] Use upstream CUTLASS for SM90 Block FP8 kernel](../sources/prs/vllm/PR-23280.md), [[Compile] Fix Compile Warning SM100 Cutlass MLA](../sources/prs/vllm/PR-23287.md), [fix incompatibililty with non cuda platform for nvfp4](../sources/prs/vllm/PR-23478.md), [[Compile] Fix Compile Warning for `w4a8_mm_entry.cu`](../sources/prs/vllm/PR-23660.md), [[NVIDIA] Support SiluMul + NVFP4 quant fusion](../sources/prs/vllm/PR-23671.md), [[Kernel][B200] mxfp4 fused cutlass moe](../sources/prs/vllm/PR-23696.md), [[Bugfix][Misc] Fix silu_and_mul_nvfp4_quant issue and extract common utils for nvfp4 kernel source files](../sources/prs/vllm/PR-23727.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[Kernel] cuda kernels for upcoming decode context parallel feature](../sources/prs/vllm/PR-23791.md), [[Kernel] Faster pre-processing time for W4A8](../sources/prs/vllm/PR-23972.md), [[Model] Add LongCat-Flash ](../sources/prs/vllm/PR-23991.md), [[Kernel] Support decode context parallelism on Blackwell with CUTLASS MLA](../sources/prs/vllm/PR-24385.md), [[NVIDIA] Blackwell Family](../sources/prs/vllm/PR-24673.md), [[Kernel][Quantization] add w4a8 support for marlin kernel](../sources/prs/vllm/PR-24722.md), [[Bugfix] Fix accuracy issue for silu_mul + nvfp4 quant fusion kernel](../sources/prs/vllm/PR-24833.md), [[Bugfix][B200] Fix `cutlass_mla` hang](../sources/prs/vllm/PR-24966.md), [Disable failing GPT-OSS Eval (Blackwell) for now](../sources/prs/vllm/PR-25107.md), [[Compile] Fix Compile Warning for Ignoring `MIN_BLOCK_PER_SM`](../sources/prs/vllm/PR-25193.md), [[Bugfix] [B200] cutlass_mla - ensure kv_split == 1 for batch size > 1](../sources/prs/vllm/PR-25509.md), [Fuse RoPE and MLA KV-cache write](../sources/prs/vllm/PR-25774.md), [Update launch_bounds_utils.h for correct compile on Multiple Cuda Arch - PTXAS out of range Warning](../sources/prs/vllm/PR-25843.md), [Fix INT8 quantization error on Blackwell GPUs (SM100+)](../sources/prs/vllm/PR-25935.md), [[Performance] Split FlashAttn attention and cache update](../sources/prs/vllm/PR-25954.md), [Fix undefined symbol: cutlass_moe_mm_sm100](../sources/prs/vllm/PR-26098.md), [[NVIDIA] [Perf] Update to leverage flashinfer trtllm FP4 MOE throughput kernel](../sources/prs/vllm/PR-26714.md), [[Attention] Tune CUTLASS MLA num_splits](../sources/prs/vllm/PR-26846.md), [[Perf] SM100 - add swap AB optimization to CUTLASS FP8 GEMM](../sources/prs/vllm/PR-27284.md), [Prefer FlashAttention MLA as default over FlashMLA](../sources/prs/vllm/PR-27363.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [[Performance] Fused blockwise quant RMS norm](../sources/prs/vllm/PR-27883.md), [[Kernel] Optimize rms_norm kernel](../sources/prs/vllm/PR-27931.md), [Update Flashinfer from `v0.4.1` to `v0.5.2`](../sources/prs/vllm/PR-27952.md), [[Perf][DeepSeek] Add sigmoid+bias fusion to fused_grouped_topk from TRTLLM](../sources/prs/vllm/PR-28124.md), [[Performance][B200] silu_mul_quant: pack scales in int32](../sources/prs/vllm/PR-28358.md), [[NVIDIA] Guard SM100 CUTLASS MoE macro to SM100 builds v2](../sources/prs/vllm/PR-28938.md), [chore: add RTX_PRO_6000 GLM4.6-FP8 kernel tuning](../sources/prs/vllm/PR-29240.md), [[Kernel] Add NVFP4 MoE CUTLASS support for SM120](../sources/prs/vllm/PR-29242.md), [Lora MoE Align Improvements](../sources/prs/vllm/PR-29257.md), [[Kernel][MoE] optimize `moe_align_block_size`](../sources/prs/vllm/PR-29642.md), [[Kernel]Support W4A8 Grouped GEMM on Hopper](../sources/prs/vllm/PR-29691.md), [[Perf] Improve fp8 quant in mla; replace ReduceSum with ReduceScatterSum](../sources/prs/vllm/PR-29795.md), [[Kernel][Quantization][MoE] add marlin kernel support for turing (sm75)](../sources/prs/vllm/PR-29901.md), [[Perf] Do FP4 quant before All gather on flashinfer trtllmgen MOE ](../sources/prs/vllm/PR-30014.md), [Add llmcompressor fp8 kv-cache quant (per-tensor and per-attn_head)](../sources/prs/vllm/PR-30141.md), [gptq marlin quantization support for fused moe with lora](../sources/prs/vllm/PR-30254.md), [[Feature] Add SM103 (Blackwell Ultra) Support to vLLM](../sources/prs/vllm/PR-30484.md), [OffloadingConnector: Support kernel_block_size != block_size](../sources/prs/vllm/PR-30692.md), [[NVFP4][Perf] Tune NVFP4 input quant kernel for small batch size](../sources/prs/vllm/PR-30897.md), [[Kernel] Add topk_sigmoid kernel](../sources/prs/vllm/PR-31246.md), [[Perf] Fuse stride preparation for NVFP4 cutlass_moe](../sources/prs/vllm/PR-31837.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[Perf][Kernel] Optimize FP4 quantization kernels (SM100F)](../sources/prs/vllm/PR-32520.md), [fix: Add glm4_moe_lite to MLA detection](../sources/prs/vllm/PR-32614.md), [[Attention] FA4 integration](../sources/prs/vllm/PR-32974.md), [[Feature] Support CPU Offloading without Pytorch Pinned Memory that leads to doubled allocation](../sources/prs/vllm/PR-32993.md), [[Kernel] Apply 256bit LDG/STG To Activation Kernels](../sources/prs/vllm/PR-33022.md), [Add support for Mistral Large 3 inference with Flashinfer MoE](../sources/prs/vllm/PR-33174.md), [[Bugfix] Fix quant RMS norm fusion for quantization with TMA-aligned scales](../sources/prs/vllm/PR-33255.md), [[Kernel] Add enable_sm120_or_later for SM121 (DGX Spark) CUTLASS support](../sources/prs/vllm/PR-33517.md), [[Feature][Core] Support Fabric detection to adapt the MNNVL protocol for the GB series](../sources/prs/vllm/PR-33540.md), [[Bugfix]fix output Nan/Inf in marlin if dtype=float16](../sources/prs/vllm/PR-33972.md), [Reapply [Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-34043.md), [fix(cpu): fix mla_decode compilation on x86 without AVX512](../sources/prs/vllm/PR-34052.md), [[Kernel] Optimize grouped topk kernel](../sources/prs/vllm/PR-34206.md), [[ModelBash][DSV3] Add TRTLLM DSV3 Router GEMM kernel (6% B1 Speedup)](../sources/prs/vllm/PR-34302.md), [[Bugfix] Enforce DeepGEMM when using sparse_attn_indexer on CUDA](../sources/prs/vllm/PR-34374.md), [[Custom Ops] Add functional + out variant for scaled_fp4_quant](../sources/prs/vllm/PR-34389.md), [[Kernel] Integrate SM100 MXFP8 blockscaled grouped MM and quant kernels](../sources/prs/vllm/PR-34448.md), [[Model Bash] DeepSeek R1 BF16 Min Latency QKV A GEMM (0.5% E2E Speedup)](../sources/prs/vllm/PR-34758.md), [[Bugfix] Gate 256-bit instructions to CUDA 12.9+](../sources/prs/vllm/PR-34791.md), [[Attention][Perf][Kernel] Replace torch.cat with vectorized CUDA kernel MLA query concat - DeepSeek-V3.2](../sources/prs/vllm/PR-34917.md), [[Model Runner V2] Support attention group](../sources/prs/vllm/PR-35036.md), [[Performance] Cublas Bf16 Gate with Fp32 Output](../sources/prs/vllm/PR-35121.md), [[Bugfix] Fix DSV3 kernels breaking _C and _moe_C on unsupported arches](../sources/prs/vllm/PR-35123.md), [[Bugfix] Fix expert_ids padding values in moe_align_block_size kernel](../sources/prs/vllm/PR-35161.md), [[BugFix] Fix fp4 quant kernel on CUDA 12.8](../sources/prs/vllm/PR-35210.md), [[Feat] Add CUDA torch fallbacks for fp8_mqa_logits/fp8_paged_mqa_logits_torch function](../sources/prs/vllm/PR-35271.md), [[Attention][Perf] Optimize cp_gather_and_upconvert_fp8_kv_cache - DeepSeek-v3.2](../sources/prs/vllm/PR-35290.md), [[Kernel] Add FlashInfer MoE A2A Kernel](../sources/prs/vllm/PR-36022.md), [Add 320 dimension size support to MLA](../sources/prs/vllm/PR-36161.md), [docs: fix wrong cc in int8.md](../sources/prs/vllm/PR-36209.md), [[Kernel] Fuse FP8 output quantization into merge_attn_states](../sources/prs/vllm/PR-36518.md), [Update Flashinfer to 0.6.6](../sources/prs/vllm/PR-36768.md), [[MTP][Sparse MLA] Take advantage of native MTP support in indexer when possible](../sources/prs/vllm/PR-36982.md), [[Kernel] Add gpt-oss Router GEMM kernel](../sources/prs/vllm/PR-37205.md), [[UX] Add flashinfer-cubin as CUDA default dep](../sources/prs/vllm/PR-37233.md), [[Perf] Set Flashinfer sparse MLA as default backend for FP8 kv cache](../sources/prs/vllm/PR-37252.md), [[Kernel] Add non-gated support for NVFP4 CUTLASS MoE](../sources/prs/vllm/PR-37320.md), [Add nvfp4 support to reshape_and_cache_flash](../sources/prs/vllm/PR-37332.md), [[torch.compile] Refactor Attention Quant Fusion Pass and Remove Boilerplate](../sources/prs/vllm/PR-37373.md), [[Perf][Kernel] Persistent TopK scheduler: unified CUDAGraph-safe kernel with dynamic per-row dispatch - DeepSeek-V3.2 DSA decode](../sources/prs/vllm/PR-37421.md), [[Kernel] Add MXFP4 W4A4 CUTLASS MoE kernel for SM100](../sources/prs/vllm/PR-37463.md), [[4/n] Migrate FP4/W4A8 CUTLASS kernels to torch stable ABI](../sources/prs/vllm/PR-37503.md), [refactor: abstract deepgemm support into platform](../sources/prs/vllm/PR-37519.md), [[Bugfix] Preserve CUDA arch suffix (a/f) for SM12x — fixes NVFP4 NaN on desktop Blackwell](../sources/prs/vllm/PR-37725.md), [[Kernel] Optimize SM120 CUTLASS blockwise FP8 GEMM](../sources/prs/vllm/PR-37970.md), [[Kernel] Add swapAB support for SM120 CUTLASS blockwise FP8 GEMM ](../sources/prs/vllm/PR-38325.md), [[CI Bugfix] Pre-download missing FlashInfer headers in Docker build](../sources/prs/vllm/PR-38391.md), [[NVIDIA] Bugfix NVFP4 DGX Spark and RTX50](../sources/prs/vllm/PR-38423.md), [[Perf] Batch KV cache swap copies via cuMemcpyBatchAsync](../sources/prs/vllm/PR-38460.md), [[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity](../sources/prs/vllm/PR-38479.md), [[Compile] Fix nvfp4 compile warning](../sources/prs/vllm/PR-38573.md), [[FA4] Update flash-attention to latest upstream FA4](../sources/prs/vllm/PR-38690.md), [[Refactor] Improve indexer decode path metadata preparation](../sources/prs/vllm/PR-38865.md), [[Bugfix] Fix broken explicit unquantized kv cache dtype support](../sources/prs/vllm/PR-38922.md), [[Bugfix] Fix GDN FLA kernel crashes with NULL_BLOCK_ID=0 CUDA graph padding](../sources/prs/vllm/PR-39064.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [perf(moe): add tuned fused_moe config for RTX PRO 6000 Blackwell Server Edition](../sources/prs/vllm/PR-39183.md), [Use CU_MEMCPY_SRC_ACCESS_ORDER_ANY for batch KV cache swaps](../sources/prs/vllm/PR-39306.md), [Fix NUMA binding on non-CDMM Grace-Blackwell systems](../sources/prs/vllm/PR-39361.md), [fix: clamp NaN/Inf in topk_softmax to prevent duplicate expert IDs](../sources/prs/vllm/PR-39391.md), [[Perf] Fuse Zero Initializer for FP8 DeepGemm Block Quant Kernel](../sources/prs/vllm/PR-39547.md), [[Bugfix] Add Marlin kernel in block scaled mm kernel selection.](../sources/prs/vllm/PR-40105.md), [[Bugfix] moe lora align kernel grid](../sources/prs/vllm/PR-40131.md), [[Bugfix] Guard mxfp4_experts_quant bindings on ENABLE_NVFP4_SM100](../sources/prs/vllm/PR-40191.md), [[Performance][DSR1]: Fused RoPE+KVCache+q_concat for MLA](../sources/prs/vllm/PR-40392.md), [[Perf] Batch invariance with Cutlass fp8 support, 28.9% E2E latency improvement](../sources/prs/vllm/PR-40408.md), [[GDN] Enable FI Blackwell GDN prefill kernel](../sources/prs/vllm/PR-40717.md), [[DSV4] Add silu clamp limit to shared expert](../sources/prs/vllm/PR-40950.md), [[DSV4] Fuse norm and router for low latency scenario](../sources/prs/vllm/PR-41263.md), [Faster per-token fp8 group quant packed kernel for blackwell](../sources/prs/vllm/PR-41326.md), [[Bugfix] Fix condition to clear persistent topk so that it can be captured regardless](../sources/prs/vllm/PR-41665.md), [[MLA Attention Backend] Add TOKENSPEED_MLA backend for DSR1/Kimi K25 prefill + decode on Blackwell](../sources/prs/vllm/PR-41778.md), [[CUDA][CUTLASS] Enable cutlass scaled mm for non-compatible sizes ](../sources/prs/vllm/PR-41868.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[Perf] Use 2D-grid to eliminate divmod in W8W8 group quant](../sources/prs/vllm/PR-42153.md), [[Misc] add humming to dependencies](../sources/prs/vllm/PR-42540.md), [[6/n] Migrate activation kernels, gptq, gguf, non cutlass w8a8 to libtorch stable ABI (continued)](../sources/prs/vllm/PR-42663.md), [[Refactor] Remove dead cuda kernels](../sources/prs/vllm/PR-42767.md), [[Perf] Padded nvfp4 quant kernel to remove additional copy, 2.4%~5.7% e2e performance improvement](../sources/prs/vllm/PR-42774.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [[Kernel] (1/N) Machete - Hopper Optimized Mixed Precision Linear Kernel ](../sources/prs/vllm/PR-7174.md), [[Kernel] (2/N) Machete - Integrate into CompressedTensorsWNA16 and GPTQMarlin](../sources/prs/vllm/PR-7701.md), [[Bugfix] Fix Machete unittests failing with `NotImplementedError`](../sources/prs/vllm/PR-9218.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [FP8 Fine-Grained-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [FlashInfer Track A FP8 Block-Scale MoE](../wiki/kernels/fused-moe.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md), [DeepSeek Sparse Attention / Sparse MLA](../wiki/kernels/sparse-mla.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md), [CCCL CUB Memory Primitives For Selection And Scan](../wiki/techniques/cccl-memory-primitives.md), [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md) | +| `cute-dsl` | [CuTe DSL for Blackwell](../wiki/languages/cute-dsl.md) | [Twelve Attempts at an FP4 Kernel](../sources/blogs/amandeep-nvfp4-attempts.md), [Colfax Article Source Kernels](../sources/blogs/colfax-article-source-kernels.md), [Colfax CUTLASS Tutorial: GEMM Kernels Using Tensor Memory for Blackwell](../sources/blogs/colfax-cutlass-blackwell.md), [Colfax CUTLASS Kernels](../sources/blogs/colfax-cutlass-kernels.md), [FlashAttention-4 Blog](../sources/blogs/flash-attention-4.md), [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [FlashInfer MLSys 2026 Track A: FP8 Block-Scale MoE](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [CUTLASS Changelog: SM100/Blackwell Entries](../sources/docs/cutlass-changelog-sm100.md), [NVIDIA CUTLASS 4.5.0 Blackwell Sources](../sources/docs/nvidia-cutlass-blackwell.md), [[None][perf] Add more optimization options for MOE CuteDSL finalized kernel](../sources/prs/TensorRT-LLM/PR-10042.md), [[TRTLLM-9992][perf] Enable PDL for CuteDSL kernels and overlap MoeOutputMemset](../sources/prs/TensorRT-LLM/PR-10043.md), [[None][feat] CuteDSL MOE FC1 Enhancement](../sources/prs/TensorRT-LLM/PR-10088.md), [[TRTLLM-9457][feat] Add cute dsl fp8 gemm for Blackwell](../sources/prs/TensorRT-LLM/PR-10130.md), [[TRTLLM-9831][perf] Enable 2CTA with autotune for CuteDSL MoE and Grouped GEMM optimizations](../sources/prs/TensorRT-LLM/PR-10201.md), [[TRTLLM-10147][perf] Balanced random MoE workload generator for CuteDSL kernel UT, autotuner and layerwise benchmark](../sources/prs/TensorRT-LLM/PR-10279.md), [[TRTLLM-9661][chore] Further reduce tuning time for cuteDSL nvFP4 dense gemm.](../sources/prs/TensorRT-LLM/PR-10339.md), [[None] [feat] Add test script and raster M for gather fc1 kernel](../sources/prs/TensorRT-LLM/PR-10429.md), [[TRTLLM-10276][feat] Integrate cutedsl argmax kernel](../sources/prs/TensorRT-LLM/PR-10476.md), [[None] [feat] Add densegemm backend for MoE](../sources/prs/TensorRT-LLM/PR-10479.md), [[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth](../sources/prs/TensorRT-LLM/PR-10987.md), [[None][feat] fuse shared to sparse experts in TRT-LLM Gen MoE](../sources/prs/TensorRT-LLM/PR-11143.md), [[https://nvbugs/5854860][fix] Fix cutedsl argmax on sm120](../sources/prs/TensorRT-LLM/PR-11181.md), [[TRTLLM-10004][feat] Enable GEMM -> AR with GEMM output in registered buffers](../sources/prs/TensorRT-LLM/PR-11589.md), [[TRTLLM-11092][feat] add support for visual gen FA4 attention backend](../sources/prs/TensorRT-LLM/PR-11697.md), [[https://nvbugs/5885070][fix] fix deepeplowlatency with cutedsl moe backend](../sources/prs/TensorRT-LLM/PR-11769.md), [[TRTLLM-10990][feat] Fuse SwiGLU and quant into shared expert](../sources/prs/TensorRT-LLM/PR-11897.md), [[TRTLLM-10407][feat] Integrate CuTE DSL top-k kernel for Blackwell](../sources/prs/TensorRT-LLM/PR-11900.md), [[TRTLLM-11289][feat] Integrate CuteDSL's bf16 dense GEMMs](../sources/prs/TensorRT-LLM/PR-12074.md), [[None][feat] CuteDSL MOE: Add raster along M/N support for blockscaled contiguous backbone kernel](../sources/prs/TensorRT-LLM/PR-12079.md), [[None][feat] Add DWDP (Distributed Weight Data Parallelism) support for MoE inference](../sources/prs/TensorRT-LLM/PR-12136.md), [[TRTLLM-10407][perf] Enable CuteDSL indexer_top_k in model](../sources/prs/TensorRT-LLM/PR-12236.md), [[TRTLLM-10407][perf] Add cute dsl single pass multi cta cluster topk](../sources/prs/TensorRT-LLM/PR-12354.md), [[None][feat] Add PDL support to CuTE DSL top-k kernels](../sources/prs/TensorRT-LLM/PR-12506.md), [[None][feat] Optimize mamba SSD prefill and extend flashinfer dispatch](../sources/prs/TensorRT-LLM/PR-12731.md), [[TRTLLM-11797][feat] Add cutedsl moe backend supporting for qwen3.5.](../sources/prs/TensorRT-LLM/PR-12799.md), [[TRTLLM-11585][feat] Add CUTEDSL moe backend for nemotron-h](../sources/prs/TensorRT-LLM/PR-12884.md), [[TRTLLM-34871][feat] Add cute dsl FP8 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13219.md), [[None][perf] FC2 DenseGEMM autotune: split-K, swap_ab, fine-grained tuning buckets](../sources/prs/TensorRT-LLM/PR-13833.md), [[TRTLLM-35237][feat] Add cute dsl FP4 paged MQA logits decode kernel](../sources/prs/TensorRT-LLM/PR-13929.md), [[None][feat] Enable EPLB for trtllm-gen and cutlass backend](../sources/prs/TensorRT-LLM/PR-8886.md), [[TRTLLM-9685] [feat] Add gather fc1 kernel by cuteDSL](../sources/prs/TensorRT-LLM/PR-9618.md), [Blockwise and Groupwise GEMM for Blackwell and Improvements for Hopper](../sources/prs/cutlass/PR-2139.md), [Example 77 add blackwell flash-attention bwd for MLA shape](../sources/prs/cutlass/PR-2466.md), [Add Blackwell MLA forward (shape: d=192, dv=128) implementation](../sources/prs/cutlass/PR-2472.md), [fix gqa issue for blackwell fmha.py](../sources/prs/cutlass/PR-2599.md), [Add tutorial fp16_gemm_1](../sources/prs/cutlass/PR-2750.md), [new example with TMA prefetch feature targeting for DRAM latency boun…](../sources/prs/cutlass/PR-2881.md), [[CuTeDSL] Fix: SM100 block-scale gemm overlapping accumulator](../sources/prs/cutlass/PR-2995.md), [[Cute-DSL] Add option for issue_clc_query without multicast](../sources/prs/cutlass/PR-3021.md), [[Hopper CuTeDSL] Add grouped GEMM kernel example](../sources/prs/cutlass/PR-3091.md), [[CLI] add cutedsl fp16 gemm tutorial from 2 to 6](../sources/prs/cutlass/PR-3106.md), [Update blackwell tutorial to be compatible with 4.5-dev version](../sources/prs/cutlass/PR-3130.md), [feat: Adding varlen support to cute-dsl sm80 bwd](../sources/prs/flash-attention/PR-1934.md), [[Cute,Fwd,Sm100] fp8 e4m3 and e5m2 support](../sources/prs/flash-attention/PR-2109.md), [[Cute,Flex,Fwd] Allow vectorized score_mod definitions](../sources/prs/flash-attention/PR-2236.md), [[Cute,Sm100,Fwd] add MLA 64/512 with topk sparsity for MQA 128 heads](../sources/prs/flash-attention/PR-2441.md), [feat: masked layout fp4 gemm using cute-dsl](../sources/prs/flashinfer/PR-1331.md), [Add python API for masked grouped gemm](../sources/prs/flashinfer/PR-1481.md), [fix: update cutedsl masked moe gemm](../sources/prs/flashinfer/PR-1488.md), [fix: update masked moe gemm fp4 tensor reshape](../sources/prs/flashinfer/PR-1495.md), [feat: scaling at fp4 gemm epilogue](../sources/prs/flashinfer/PR-1498.md), [Add benchmark for cutedsl gemm](../sources/prs/flashinfer/PR-1502.md), [bugfix: Fix stream handling in cutedsl gemm](../sources/prs/flashinfer/PR-1509.md), [refactor fp4 masked gemm cute-dsl implementation and add manual cache](../sources/prs/flashinfer/PR-1521.md), [feat: initial support for SM103, SM110, SM120, SM121](../sources/prs/flashinfer/PR-1608.md), [Support output signals for overlapping for cutedsl gemm](../sources/prs/flashinfer/PR-1677.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [fix: fix cannot import name 'cuda' from 'cuda' in CUDA13](../sources/prs/flashinfer/PR-1764.md), [tests: upgrade cutlass, fix import and skip non-SM100 cutedsl two shot allreduce](../sources/prs/flashinfer/PR-1812.md), [raise error for group_gemm_fp8_nt_groupwise then num_groups > 1 on sm120/121](../sources/prs/flashinfer/PR-1862.md), [enable sm103 moe dsl backend](../sources/prs/flashinfer/PR-2149.md), [Fix gemm allreduce two shot](../sources/prs/flashinfer/PR-2171.md), [feat: Fused RMSNorm + FP4 Quantization Kernels in CuTe-DSL](../sources/prs/flashinfer/PR-2233.md), [fix: Add global scale support and optional output allocation for RMSNorm+FP4Quant fusion kernels](../sources/prs/flashinfer/PR-2260.md), [[WIP] Refactor: simplify torch -> cute-dsl boilerplate and enable tvm-ffi for cute-dsl kernels](../sources/prs/flashinfer/PR-2279.md), [fix: In-place Residual Update for add_rmsnorm_fp4quant](../sources/prs/flashinfer/PR-2385.md), [feat: Add output_both_sf_layouts option to add_rmsnorm_fp4quant API](../sources/prs/flashinfer/PR-2395.md), [feat: cuteDSL fp4 moe for better DSR1 performance.](../sources/prs/flashinfer/PR-2398.md), [perf: improve gdn decode cute-dsl kernels](../sources/prs/flashinfer/PR-2405.md), [refactor: simplify fp4 rmsnorm](../sources/prs/flashinfer/PR-2421.md), [refactor: refactoring cuda code to cute-dsl (part 1)](../sources/prs/flashinfer/PR-2428.md), [Add cute-dsl backends to mxfp[8,4]_quantization for future refactor](../sources/prs/flashinfer/PR-2443.md), [Ameyn/gdn decode cutedsl kernel](../sources/prs/flashinfer/PR-2498.md), [refactor: Port upstream CUTLASS fixes and refactor grouped_gemm_nt_masked GEMM module location](../sources/prs/flashinfer/PR-2503.md), [[Bug] Fix spark unit test failures for test_add_rmsnorm_fp4_quant_cute_dsl](../sources/prs/flashinfer/PR-2573.md), [fix: cute dsl nvfp4 moe routing index error](../sources/prs/flashinfer/PR-2629.md), [feat: support mxfp4 & mxfp8 entrypoint for blackwell cutedsl dense gemm](../sources/prs/flashinfer/PR-2660.md), [Add cute dsl mla decode op](../sources/prs/flashinfer/PR-2743.md), [[CuTe DSL] Add modular FMHA prefill and MLA decode attention kernels](../sources/prs/flashinfer/PR-2805.md), [CuteDSL MoE fix redundant output buffer zeroing](../sources/prs/flashinfer/PR-2811.md), [feat: Add CuTe-DSL backend for NVFP4 quantization](../sources/prs/flashinfer/PR-2838.md), [feat: add pdl support for cute dsl mla decode kernel support](../sources/prs/flashinfer/PR-2901.md), [perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels](../sources/prs/flashinfer/PR-2904.md), [feat: Add CuTe DSL grouped-gemm + combine fusion support](../sources/prs/flashinfer/PR-2944.md), [feat: add PDL support to rmsnorm_fp4quant and add_rmsnorm_fp4quant CuTe DSL kernels](../sources/prs/flashinfer/PR-3008.md), [Prevent MoE autotuner buffer overflow on large token buckets](../sources/prs/flashinfer/PR-3025.md), [feat: Add backend="b12x" for mm_fp4 on SM120](../sources/prs/flashinfer/PR-3051.md), [feat: Add b12x CuTe DSL fused MoE for SM120](../sources/prs/flashinfer/PR-3066.md), [cute-dsl fmha prefill (cubin integration): remove front-padding, add attention_sink, and pdl support](../sources/prs/flashinfer/PR-3181.md), [fix(sm12x): fix micro-kernel workspace sizing when routed_rows > num_local_experts](../sources/prs/flashinfer/PR-3191.md), [fix(cute_dsl/moe): make autotuner bucket configuration adapt to runtime input](../sources/prs/flashinfer/PR-3216.md), [Support Kimi K2.5 H64 CuTe DSL MLA decode](../sources/prs/flashinfer/PR-3235.md), [fix(cute_dsl/moe): unbias autotuner profiling for tile_size enumeration](../sources/prs/flashinfer/PR-3252.md), [feat(moe): add SM120 W4A16 b12x kernels](../sources/prs/flashinfer/PR-3271.md), [feat(cute_dsl/moe): deterministic balanced autotune profile inputs](../sources/prs/flashinfer/PR-3286.md), [feat(cute_dsl/moe): add `moe_output_memset_inplace` dense memset wrapper](../sources/prs/flashinfer/PR-3328.md), [Support single batch overlap](../sources/prs/sglang/PR-10422.md), [Replace [silu_and_mul_]scaled_fp4_group_quant by Flashinfer equivalent](../sources/prs/sglang/PR-12376.md), [[diffusion] kernel fusion: gated residual layernorm scale shift and layernorm scale shift kernel fusion for Qwen-Image, WAN and HunyuanVideo](../sources/prs/sglang/PR-14717.md), [[jit-kernel] Add CuTe DSL GDN Decode Kernel](../sources/prs/sglang/PR-15631.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [[diffusion] Diffusion norm fusion for z-image](../sources/prs/sglang/PR-18762.md), [[SGLang-Diffusion] Fix custom op fake impl missing eps default for torch.compile](../sources/prs/sglang/PR-19725.md), [[diffusion] fix bug of copy_if](../sources/prs/sglang/PR-20094.md), [[KDA] Support CuTeDSL KDA decode kernel](../sources/prs/sglang/PR-21203.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [Add dedicated FlashInferCuteDslMoE layer for standard-path FP4 MoE](../sources/prs/sglang/PR-21339.md), [[Bugfix] Lazy-import CuteDSL KDA kernel to fix AMD/ROCm startup crash](../sources/prs/sglang/PR-21428.md), [feat: Support flashinfer_cutedsl MoE runner with flashinfer alltoall backend](../sources/prs/sglang/PR-22669.md), [[Refactor] Refactor DeepEP dispatcher](../sources/prs/sglang/PR-22822.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [[MoE Refactor] Migrate flashinfer_cutedsl + DeepEP to MoeRunner](../sources/prs/sglang/PR-25525.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Bugfix] Fix CuTeDSL autotune cache invalid ELF header (#1967)](../sources/prs/tilelang/PR-1972.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[MoE] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked](../sources/prs/vllm/PR-25990.md), [[FIX] Add NO_MUL activation support for modular kernel path](../sources/prs/vllm/PR-31528.md), [fix: Add SM120 (RTX Blackwell) support for FlashInfer CUTLASS NVFP4 MoE kernels](../sources/prs/vllm/PR-33417.md), [[Bug][MoE] Strengthen _supports_current_device() checks in the TRTLLM FP8, NVFP4, and FlashInfer CuteDSL MoE experts](../sources/prs/vllm/PR-36728.md), [[MoE/EPLB] Fix FlashInfer nvfp4 experts + EPLB correctness](../sources/prs/vllm/PR-37217.md), [[MoE] Move FlashInfer CuteDSL experts into fused_moe/experts/](../sources/prs/vllm/PR-37759.md), [[MoE Kernel] Flashinfer nvfp4 cutedsl moe kernel integration](../sources/prs/vllm/PR-38050.md), [[Quantization] Add FlashInfer CuteDSL batched experts backend for NVFP4 MoE](../sources/prs/vllm/PR-38251.md), [[Bugfix] [Tests] Enforce `out` tensor device in `kernel/moe/test_cutedsl_moe.py`](../sources/prs/vllm/PR-39644.md), [[DSv4] Improved fused Indexer Q quant kernel](../sources/prs/vllm/PR-41428.md), [[DSv4] Improved dequant gather K cache kernel](../sources/prs/vllm/PR-42236.md), [[Perf] Re-enable flashinfer autotune by default and cleanup](../sources/prs/vllm/PR-42857.md), [add cutedsl dsv4 indexer fp8 kernel](../sources/prs/vllm/PR-42899.md), [[Model Refactoring] Move deepseek_v4_ops to models/deepseek_v4 [3/N]](../sources/prs/vllm/PR-43073.md), [FlashAttention-4](../wiki/kernels/flash-attention-4.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [FP8 Fine-Grained-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [FlashInfer Track A FP8 Block-Scale MoE](../wiki/kernels/fused-moe.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md), [DeepSeek Sparse Attention / Sparse MLA](../wiki/kernels/sparse-mla.md), [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md) | | `cutile` | | [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md) | | `jax-pallas` | | [Writing High-Performance Matrix Multiplication Kernels for Blackwell with JAX Pallas](../sources/blogs/jax-pallas-blackwell-matmul.md) | -| `ptx` | [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md) | [Twelve Attempts at NVFP4 Batched GEMV](../sources/blogs/amandeep-nvfp4-attempts.md), [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [NVIDIA Blackwell Compatibility Guide](../sources/docs/blackwell-compatibility-guide.md), [PTX ISA SM100 Instructions Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [misc: point triton blackwell-ptxas to local cuda ptxas](../sources/prs/flashinfer/PR-2543.md), [[AARCH64][CD][CUDA13][Triton][PTXAS] Turn on BUILD_BUNDLE_PTXAS=1 ](../sources/prs/pytorch/PR-164236.md), [[release-only] Remove +ptx from cuda 13.0 builds](../sources/prs/pytorch/PR-175567.md), [Add swizzle layout detection and automatic merging for layout conflicts](../sources/prs/tilelang/PR-1736.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[Bugfix] Enable `.shared::cta` in TMA copy paths only on CUDA 12.8+](../sources/prs/tilelang/PR-2087.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [Update launch_bounds_utils.h for correct compile on Multiple Cuda Arch - PTXAS out of range Warning](../sources/prs/vllm/PR-25843.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [NVFP4 GEMM — 4-bit Floating Point Matrix Multiply](../wiki/kernels/nvfp4-gemm.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md) | -| `python` | | [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [Performance: reducing the percentage of FFMA interleaving yields a sight performance gain, roughly 0.5%](../sources/prs/DeepGEMM/PR-42.md), [[None][feat] sm100 weight-only kernel](../sources/prs/TensorRT-LLM/PR-10190.md), [[TRTLLM-9798][feat] Change to use new DeepGEMM MQA sm100 kernel for MTP-3](../sources/prs/TensorRT-LLM/PR-10226.md), [[None][feat] MiniMax M2 support](../sources/prs/TensorRT-LLM/PR-10532.md), [[None][feat] Remove non flash attetnion style fmha_v2 kernel for hopper](../sources/prs/TensorRT-LLM/PR-11381.md), [[None][fix] Fix int4 awq for sm120/121](../sources/prs/TensorRT-LLM/PR-11561.md), [[None][fix] Fix SM120 issue for rms_norm with nvfp4_quant_fusion](../sources/prs/TensorRT-LLM/PR-11774.md), [[None][feat] GLM 5 support and DSA MTP fixes](../sources/prs/TensorRT-LLM/PR-11990.md), [[TRTLLM-11285][feat] Fuse indexer wk + weights_proj into single GEMM in TF32 for DS-V3.2](../sources/prs/TensorRT-LLM/PR-12055.md), [[https://nvbugs/5983390][fix] Remove redundant D2H sync to optimize perf](../sources/prs/TensorRT-LLM/PR-12445.md), [[#12634][feat] AutoDeploy: Support rank 256 MLA in flashinfer_mla](../sources/prs/TensorRT-LLM/PR-12519.md), [[https://nvbugs/5879577][fix] Fix KeyError in DeepSeekV3Lite FP8 MTP weight loading](../sources/prs/TensorRT-LLM/PR-12530.md), [[None][feat] Add bf16 trtllm-gen moe support through flashinfer.](../sources/prs/TensorRT-LLM/PR-12738.md), [[None][fix] Propagate init_load_balancer to DeepGemmFusedMoE in create_moe_backend](../sources/prs/TensorRT-LLM/PR-13207.md), [[TRTLLM-11127][feat] add W4A8_MXFP4_FP8 MoE unit test support](../sources/prs/TensorRT-LLM/PR-13401.md), [[TRTLLM-11285][perf] Force enable TF32 tensor cores for DSA indexer fused GEMM](../sources/prs/TensorRT-LLM/PR-13452.md), [[TRTLLM-12128][feat] enable SageAttention for Wan/FLUX (new commits)](../sources/prs/TensorRT-LLM/PR-13570.md), [[TRTLLM-12316][feat] Integrate FP4 indexer for DSv4](../sources/prs/TensorRT-LLM/PR-13575.md), [[None][feat] Enable EPLB for DeepSeek-V4](../sources/prs/TensorRT-LLM/PR-13595.md), [[None][feat] Add bf16 trtllm moe through flashinfer.](../sources/prs/TensorRT-LLM/PR-13689.md), [[None][fix] Use compressed lengths for DeepSeek-V4 indexer](../sources/prs/TensorRT-LLM/PR-13802.md), [[None][feat] Update FMHA cubins for head_dim 80](../sources/prs/TensorRT-LLM/PR-13808.md), [[TRTLLM-12503][feat] Parallel VAE independent scaling and fix arg passing](../sources/prs/TensorRT-LLM/PR-13873.md), [[None][feat] enable TRTLLM-Gen internal routing](../sources/prs/TensorRT-LLM/PR-13997.md), [[None][feat] Enable 2 DSv4 perf optimizations by default](../sources/prs/TensorRT-LLM/PR-14120.md), [[TRTLLM-12462][fix] Fix FP8 block scaling GEMM autotuner cache growth](../sources/prs/TensorRT-LLM/PR-14165.md), [[https://nvbugs/6025177][test] rcca tests using kimi k2.5 fp4](../sources/prs/TensorRT-LLM/PR-14172.md), [[https://nvbugs/6163147][fix] swap layer.mlp in place for Mixtral modelopt export](../sources/prs/TensorRT-LLM/PR-14179.md), [[None][fix] Avoid dp_size x ep_size double-count in MegaMoEDeepGemm SymmBuffer](../sources/prs/TensorRT-LLM/PR-14213.md), [[None][refactor] clean up AttentionForwardArgs](../sources/prs/TensorRT-LLM/PR-14244.md), [[None][fix] Handle unset attention_dp_relax in ADP routers](../sources/prs/TensorRT-LLM/PR-14276.md), [[https://nvbugs/6095421][fix] Update resolve_moe_backend](../sources/prs/TensorRT-LLM/PR-14282.md), [[None][chore] Update Claude Code agents and skills](../sources/prs/TensorRT-LLM/PR-14344.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[TRTLLM-8827] [feat] Enable low precision alltoall for Cutlass and TRTLLMGen backends](../sources/prs/TensorRT-LLM/PR-8675.md), [[TRTLLM-8958][feat] and [TRTLLM-8960]: create ConfigurableMoE and support TRTLLMGenFusedMoE as backend](../sources/prs/TensorRT-LLM/PR-9486.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [Experimental Python cooperative algorithms](../sources/prs/cccl/PR-1973.md), [[cuda.compute]: Fix faulty pointer arithmetic calculation in CUB dispatch](../sources/prs/cccl/PR-7940.md), [Expose `max_segment_size` guarantee in cuda.compute](../sources/prs/cccl/PR-8284.md), [[cub]: implement utilities for policy selection](../sources/prs/cccl/PR-8355.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [fix gqa issue for blackwell fmha.py](../sources/prs/cutlass/PR-2599.md), [Add tutorial fp16_gemm_1](../sources/prs/cutlass/PR-2750.md), [new example with TMA prefetch feature targeting for DRAM latency boun…](../sources/prs/cutlass/PR-2881.md), [[Cute-DSL] Add option for issue_clc_query without multicast](../sources/prs/cutlass/PR-3021.md), [[Hopper CuTeDSL] Add grouped GEMM kernel example](../sources/prs/cutlass/PR-3091.md), [Support for Group GEMM in CUTLASS Profiler for GeForce and Spark](../sources/prs/cutlass/PR-3092.md), [[CLI] add cutedsl fp16 gemm tutorial from 2 to 6](../sources/prs/cutlass/PR-3106.md), [Update blackwell tutorial to be compatible with 4.5-dev version](../sources/prs/cutlass/PR-3130.md), [Small Tile N BlockScaled GEMM + Grouped GEMM on SM12x](../sources/prs/cutlass/PR-3176.md), [Add var-seq-len to FA3 fp16 / bf16 fwd](../sources/prs/flash-attention/PR-1072.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [Add seqused_q in fwd / bwd and seqused_k in bwd in hopper FA.](../sources/prs/flash-attention/PR-1182.md), [Add local attention in Hopper FAv3](../sources/prs/flash-attention/PR-1233.md), [Paged Attention support for FA3](../sources/prs/flash-attention/PR-1268.md), [FA3 paged attention: Readiness for Cutlass 3.6 / default value for block_table](../sources/prs/flash-attention/PR-1331.md), [Support hdimQK != hdimV backward](../sources/prs/flash-attention/PR-1604.md), [Improve causal backward determinism perf with SPT schedule](../sources/prs/flash-attention/PR-1893.md), [[Cute,Fwd,Sm100] Implement SplitKV](../sources/prs/flash-attention/PR-1940.md), [Blackwell FlashAttention-BWD (v1.0)](../sources/prs/flash-attention/PR-1945.md), [[Cute] Block sparse support Sm100](../sources/prs/flash-attention/PR-1985.md), [[Cute,Fwd,Sm100] Support `q_stage=1` for inference](../sources/prs/flash-attention/PR-1993.md), [[Cute,Fwd,Sm100] Support paged attention](../sources/prs/flash-attention/PR-1999.md), [[Cute,Sm100,Fwd] use correction warps for epi when not using TMA](../sources/prs/flash-attention/PR-2014.md), [[Cute,Fwd,Sm100] don't pass mask_fn to softmax_step generically](../sources/prs/flash-attention/PR-2026.md), [[Cute,Bwd,Sm100] enable deterministic mode for sm100 bwd and fix race conditions](../sources/prs/flash-attention/PR-2033.md), [[Cute,Fwd] Extend score_mod to variable sequence length](../sources/prs/flash-attention/PR-2043.md), [Add score-mod bwd support ](../sources/prs/flash-attention/PR-2070.md), [Add blocksparse support for bwd on blackwell](../sources/prs/flash-attention/PR-2085.md), [Fix IMA in fwd on m boundary](../sources/prs/flash-attention/PR-2091.md), [Add pack-gqa fwd support for sparse impl w/ broadcasted H dim](../sources/prs/flash-attention/PR-2098.md), [[Cute,Fwd,Sm100] distributed offset calculation for paged KV](../sources/prs/flash-attention/PR-2104.md), [[NVIDIA] Enable Jetson Thor FA4](../sources/prs/flash-attention/PR-2108.md), [[CUTE][SM90]Enable pack-gqa with broadcasted maskmods](../sources/prs/flash-attention/PR-2145.md), [[Cute][Flex]Add pack-gqa divmod](../sources/prs/flash-attention/PR-2180.md), [[Cute,Fwd,Sm100] support irregular qhead / kvhead ratios](../sources/prs/flash-attention/PR-2186.md), [[Ai-assisted] CLC work stealing](../sources/prs/flash-attention/PR-2218.md), [[Bwd,Sm120] Add SM120 backward pass support](../sources/prs/flash-attention/PR-2330.md), [Add SM120 varlen attention support](../sources/prs/flash-attention/PR-2333.md), [[Fwd,Sm90] Add paged KV attention support (tma and cp.async)](../sources/prs/flash-attention/PR-2360.md), [[Cute,Sm100,Bwd] refine bwd swizzle for deterministic](../sources/prs/flash-attention/PR-2390.md), [Feat([FA4][CUTE DSL]) Add head_dim=256 support (forward + backward)](../sources/prs/flash-attention/PR-2412.md), [Add CLC scheduler heuristic](../sources/prs/flash-attention/PR-2455.md), [[hd256] Improve forward kernel with exp2 FMA emulation (3% to 9% performance gain)](../sources/prs/flash-attention/PR-2488.md), [[hd256] Add TMA paged KV support to SM100 2CTA forward kernel](../sources/prs/flash-attention/PR-2489.md), [[FA4][hd256] Backward TMA bulk-store epilogue + LSE/dpsum coalesce](../sources/prs/flash-attention/PR-2497.md), [Fix ZeroDivisionError in num_splits_heuristic for empty Q workloads](../sources/prs/flash-attention/PR-2515.md), [bugfix: import wrapper of mla decode](../sources/prs/flashinfer/PR-1013.md), [Add fp4 quantization swizzling tests](../sources/prs/flashinfer/PR-1157.md), [feat: nvshmem python bindings](../sources/prs/flashinfer/PR-1160.md), [feat: logits processor fustion rule for temperature softmax](../sources/prs/flashinfer/PR-1170.md), [Expose fp4 blockscale swizzling kernel](../sources/prs/flashinfer/PR-1176.md), [[feat] support block sparse attention w/ variable block sizes and head-wise sparse patterns](../sources/prs/flashinfer/PR-1177.md), [bugfix: fix invalid blackwell fmha unittests](../sources/prs/flashinfer/PR-1181.md), [bugfix: fix blackwell fmha hanging issue for empty kv_len](../sources/prs/flashinfer/PR-1198.md), [Add DeepGEMM kernels](../sources/prs/flashinfer/PR-1209.md), [Fix test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-1211.md), [init add gemm fp8 using cudnn backend](../sources/prs/flashinfer/PR-1264.md), [feat: add masked deepgemm support and benchmarking](../sources/prs/flashinfer/PR-1266.md), [hotfix: fix deepgemm artifactory hash](../sources/prs/flashinfer/PR-1278.md), [fix: update trtllm-gen fmha benchmark](../sources/prs/flashinfer/PR-1280.md), [Unify groupwise fp8 GEMM test](../sources/prs/flashinfer/PR-1281.md), [add mm_fp4 use cudnn backend](../sources/prs/flashinfer/PR-1288.md), [Remove FAST_BUILD FLAG for MOE](../sources/prs/flashinfer/PR-1291.md), [Support loading autotuned results from json for cutlass fp4 moe backends](../sources/prs/flashinfer/PR-1310.md), [test qkvo quantization not equal to 1.](../sources/prs/flashinfer/PR-1314.md), [minor: add trtllm_gen_mla benchmark](../sources/prs/flashinfer/PR-1316.md), [Allow cudnn prefill kernels to be called natively](../sources/prs/flashinfer/PR-1317.md), [refactor: Improved metainfo for trtllm-gen kernels](../sources/prs/flashinfer/PR-1328.md), [add torch float4_e2m1fn_x2 check for cudnn fp4 backend](../sources/prs/flashinfer/PR-1333.md), [[Fix] remove torch 2.8 requirement for FP4 GEMM](../sources/prs/flashinfer/PR-1334.md), [Fix bench deepgemm setting](../sources/prs/flashinfer/PR-1344.md), [Support passing kv_data_type to MultiLevelCascadeAttentionWrapper.plan()](../sources/prs/flashinfer/PR-1350.md), [[fix] remove (view) transpose to keep consistent with majorness MN requirement.](../sources/prs/flashinfer/PR-1358.md), [hotfix: update mxfp4 groupwise-scaled gemm unittests](../sources/prs/flashinfer/PR-1359.md), [Update autotune results for the nvfp4 cutlass moe backends for v0.2.9](../sources/prs/flashinfer/PR-1361.md), [refactor: download trtllm gemm metadata from server](../sources/prs/flashinfer/PR-1378.md), [Allow BatchPrefillPagedWrapper to call cudnn API](../sources/prs/flashinfer/PR-1384.md), [Adding FP8 benchmark on attention and matmul testing](../sources/prs/flashinfer/PR-1390.md), [Add Mxfp4 trtllm-gen moe unit tests](../sources/prs/flashinfer/PR-1399.md), [feature: enable cublas for fp4 gemm when cudnn == 9.11.1 or >= 9.13](../sources/prs/flashinfer/PR-1405.md), [Faster weight processing (moe nvfp4)](../sources/prs/flashinfer/PR-1412.md), [refactor: Sink attention AoT](../sources/prs/flashinfer/PR-1427.md), [Fix redundant kernels in moe](../sources/prs/flashinfer/PR-1428.md), [bugfix: fix perf issue by using fp8 graph that can use cublaslt](../sources/prs/flashinfer/PR-1435.md), [feat: enable trtllm-gen attn speculative decoding verify by decode](../sources/prs/flashinfer/PR-1453.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [feat: Enable multiple fused-moe backends](../sources/prs/flashinfer/PR-1472.md), [refactor: unify autotuner for bmm_fp8](../sources/prs/flashinfer/PR-1479.md), [fix missing enable_pdl argument in trtllm-gen fp4 moe](../sources/prs/flashinfer/PR-1480.md), [Add python API for masked grouped gemm](../sources/prs/flashinfer/PR-1481.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [Remove cuda-python from dependency and check at runtime](../sources/prs/flashinfer/PR-1534.md), [Add sm check for sm100 only cutlass/trtllm kernel](../sources/prs/flashinfer/PR-1535.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [feat: Support for inferring out_dtype from out.dtype for TRTLLM attention kernel](../sources/prs/flashinfer/PR-1578.md), [refactor: Expose calculate_tile_tokens_dim function](../sources/prs/flashinfer/PR-1581.md), [bugfix: Fix test_fp4_quantize test bug](../sources/prs/flashinfer/PR-1585.md), [fix: limit the number of nvcc threads for each kernel](../sources/prs/flashinfer/PR-1589.md), [fix: Improve TRTLLM attention kernel out_dtype unit test](../sources/prs/flashinfer/PR-1590.md), [bugfix: fix unittest test_fp8_quantize](../sources/prs/flashinfer/PR-1599.md), [feat: Enable MnnvlMemory (for alltoallv) on B200](../sources/prs/flashinfer/PR-1601.md), [feat: add support of fp4_batched_quantize](../sources/prs/flashinfer/PR-1633.md), [fix: pass workspace for trtllm-gen attention](../sources/prs/flashinfer/PR-1635.md), [test: pytest.mark.xfail on deepgemm](../sources/prs/flashinfer/PR-1636.md), [bugfix: Fix FLOPS calculation for bench_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-1640.md), [fix: zero-init workspace buffer for trtllm-gen fmha](../sources/prs/flashinfer/PR-1643.md), [Added mx_fp4 support using the cudnn backend](../sources/prs/flashinfer/PR-1644.md), [Add benchmark for MLARopeQuantize](../sources/prs/flashinfer/PR-1656.md), [test: update fused_moe test to random scale factor](../sources/prs/flashinfer/PR-1665.md), [[Hotfix] `test_fp4_quantize.py` failure on sm103](../sources/prs/flashinfer/PR-1666.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [test: better fp8 quantization init for fused_moe test](../sources/prs/flashinfer/PR-1674.md), [[misc] add a wrapper class for attention sink jit args](../sources/prs/flashinfer/PR-1679.md), [Update deepgemm backend for 103a](../sources/prs/flashinfer/PR-1694.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [hotfix: Hotfix for `test_pod_kernels.py` on B300](../sources/prs/flashinfer/PR-1698.md), [feat: Benchmark mm_fp4 mxfp4 support and gemm autotune support. Restore mm_fp4 API behavior](../sources/prs/flashinfer/PR-1706.md), [bugfix: increase workspace to make trtllm gen attention unit test pass](../sources/prs/flashinfer/PR-1707.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [perf: Add tuning config for cutlass moe for a hardware](../sources/prs/flashinfer/PR-1716.md), [feat: port fast_decode_plan from sgl](../sources/prs/flashinfer/PR-1745.md), [tests: xfail attention sink UT for sliding window + non causal case](../sources/prs/flashinfer/PR-1752.md), [tests: xfail moe quantization classes mxfp8_bf16 UTs on sm103 ](../sources/prs/flashinfer/PR-1754.md), [Fix tests/test_trtllm_gen_attention.py::test_trtllm_batch_prefill, ::test_trtllm_batch_decode mismatch error](../sources/prs/flashinfer/PR-1755.md), [fix: should pass global_override_indptr_cpu in fast_decode_plan param list](../sources/prs/flashinfer/PR-1757.md), [Added xfail for mx_fp4 matmul on SM120](../sources/prs/flashinfer/PR-1766.md), [tests: skip non SM100/103 for grouped deepgemm](../sources/prs/flashinfer/PR-1767.md), [add test case for trtllm gen fused moe with kimi k2 problem sizes](../sources/prs/flashinfer/PR-1768.md), [Waive / disable test_mla_decode_kernel.py::test_mla_decode_kernel for not sm80 ](../sources/prs/flashinfer/PR-1771.md), [Support checks PoC](../sources/prs/flashinfer/PR-1809.md), [tests: Update support for tgv_gemm to SM100 only and add to ut](../sources/prs/flashinfer/PR-1810.md), [fix: fp4 moe on sm120](../sources/prs/flashinfer/PR-1817.md), [misc: fix some B200 GEMM bench](../sources/prs/flashinfer/PR-1883.md), [fix: Fix trtllm-gen prefill IMA when batch_size==1](../sources/prs/flashinfer/PR-1912.md), [Add realistic bench for persistent kernel ](../sources/prs/flashinfer/PR-1942.md), [fix: Add cutlass as an mm_fp4 backend in compute capability 12.0 in benchmark code](../sources/prs/flashinfer/PR-1959.md), [fix: ensure SM120/121 SFA/SFB contiguity](../sources/prs/flashinfer/PR-1963.md), [Feature: Add support for L40 FusedMoE in cutlass path](../sources/prs/flashinfer/PR-1973.md), [fix: Make attention microbenchmark correctly use page table](../sources/prs/flashinfer/PR-1976.md), [fix: Skipping attention sink Blackwell test outside of Blackwell](../sources/prs/flashinfer/PR-1978.md), [feat: Add backend='auto' to mm_fp4 and enable autotune for backend='cudnn'](../sources/prs/flashinfer/PR-1979.md), [unittest: Add head dim 256 test cases and mark as xfail](../sources/prs/flashinfer/PR-1999.md), [Fix trtllm-gen attention illegal memory access](../sources/prs/flashinfer/PR-2002.md), [fix: Enable SM121 for mm_fp4](../sources/prs/flashinfer/PR-2012.md), [feat: suitable_auto_backends to prune auto backends, bmm_fp8 refactor, heuristic_func intake](../sources/prs/flashinfer/PR-2029.md), [Added an initial implementation of Q and KV Cache in fp8 and to use t…](../sources/prs/flashinfer/PR-2035.md), [test: Skip test_fp8_quantize.py on Hopper](../sources/prs/flashinfer/PR-2052.md), [misc: Add XQA decode to microbenchmark for sm90 and sm120](../sources/prs/flashinfer/PR-2055.md), [[Test] Optimize test_trtllm_gen_fused_moe.py](../sources/prs/flashinfer/PR-2072.md), [unittest: improve the efficiency of xqa unittests](../sources/prs/flashinfer/PR-2075.md), [fix: fix test_trtllm_gen_attention when max_seq_len < page_size](../sources/prs/flashinfer/PR-2076.md), [Patch sm103 for 3xfp4 moe generation](../sources/prs/flashinfer/PR-2082.md), [refactor: update dpsk fused_moe test [1]](../sources/prs/flashinfer/PR-2088.md), [refactor: pass hopper deepgemm include directory through python](../sources/prs/flashinfer/PR-2090.md), [refactor: update dpsk fused_moe test [2]](../sources/prs/flashinfer/PR-2097.md), [[DSR1] Added MLA test](../sources/prs/flashinfer/PR-2100.md), [fix: Fix bench_mm_fp8.py](../sources/prs/flashinfer/PR-2129.md), [A unified API for the MNNVL and single-node/multi-GPU AllReduce kernels.](../sources/prs/flashinfer/PR-2130.md), [fix(trtllm): reset negative strideBatch to 0 for ragged KV layout to …](../sources/prs/flashinfer/PR-2134.md), [fix: some bugs of headDim 256 trtllm-gen fmha kernels. ](../sources/prs/flashinfer/PR-2137.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [refactor: Move mla code from decode.py to mla.py and add to documentation](../sources/prs/flashinfer/PR-2163.md), [fix: compile flags for trtllm fmha_v2 ](../sources/prs/flashinfer/PR-2175.md), [Rename noauxtc to fused_topk_deepseek](../sources/prs/flashinfer/PR-2181.md), [Permute page table in benchmarking](../sources/prs/flashinfer/PR-2194.md), [misc: support checks for gemm](../sources/prs/flashinfer/PR-2214.md), [Fp8 attention are now part of cuDNN 9.17.1](../sources/prs/flashinfer/PR-2241.md), [test: Fix MNNVL tests to skip when container lacks SYS_PTRACE capability](../sources/prs/flashinfer/PR-2245.md), [feat: Add support for bmm mxfp8](../sources/prs/flashinfer/PR-2256.md), [Fix CUTLASS FP8 gemm correctness issue on SM120/SM121 for shapes where N is not divisible by ScaleGranularityN.](../sources/prs/flashinfer/PR-2261.md), [test: use .float() in in F.cosine_similarity() in bmm_fp8 test](../sources/prs/flashinfer/PR-2266.md), [Tiny fix bench tgv gemm](../sources/prs/flashinfer/PR-2277.md), [fix: Decode benchmark's fa2_tc uses backend=fa2 in wrapper](../sources/prs/flashinfer/PR-2302.md), [Support both 3D and 4D kv_cache shapes in MLA APIs](../sources/prs/flashinfer/PR-2334.md), [Added the cudnn backend Ragged KV Cache wrapper](../sources/prs/flashinfer/PR-2352.md), [benchmarks: Add norm and quantization routines to microbenchmark harness.](../sources/prs/flashinfer/PR-2362.md), [feat: [Qwen3-Next] Add Cute DSL GDN decode kernel and tests](../sources/prs/flashinfer/PR-2370.md), [feat: BF16 GEMM using cuDNN backend](../sources/prs/flashinfer/PR-2376.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [perf: mm_fp4 heuristic prioritizes CUTLASS over cuDNN on SM103](../sources/prs/flashinfer/PR-2404.md), [perf: add fp4 GEMM tile configs and streamK scheduler for SM120](../sources/prs/flashinfer/PR-2460.md), [fix: blockscale moe routine supports non-DS routing](../sources/prs/flashinfer/PR-2476.md), [fix: Fix memory bandwidth calculation in MLA benchmarks](../sources/prs/flashinfer/PR-2479.md), [Feat/gdn decode pooled](../sources/prs/flashinfer/PR-2521.md), [feat: BF16 GEMM benchmarking support](../sources/prs/flashinfer/PR-2525.md), [pick fa2 for BatchDecodeWithPagedKVCacheWrapper auto backend](../sources/prs/flashinfer/PR-2530.md), [fix: include fp8_blockscale_gemm_90 in AOT jit-cache](../sources/prs/flashinfer/PR-2533.md), [fallback to fa2 (instead of fa3) for unsupported configuration (bf16 Q, Fp8 KV)](../sources/prs/flashinfer/PR-2536.md), [tests: bmm_fp8 for SM110](../sources/prs/flashinfer/PR-2538.md), [feat: cute dsl mmfp4 for blackwell](../sources/prs/flashinfer/PR-2540.md), [Add gen_gemm_sm100_module_cutlass_mxfp8 to jit-cache](../sources/prs/flashinfer/PR-2549.md), [fix: allow fmha_v2_prefill_deepseek on SM121 (DGX Spark)](../sources/prs/flashinfer/PR-2559.md), [fix: guard CUTLASS FMHA against SM12x and fix fmha_v2 SM121a check](../sources/prs/flashinfer/PR-2560.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [tests: add bias testing to nvfp4 moe](../sources/prs/flashinfer/PR-2585.md), [Perf: Optimize GDN decode pretranspose kernel for all batch sizes](../sources/prs/flashinfer/PR-2588.md), [support qk_nope_head_dim for 192 check for GLM-5](../sources/prs/flashinfer/PR-2607.md), [Ameyn/gdn bf16 tolerance parallel reduction](../sources/prs/flashinfer/PR-2610.md), [perf(gdn): optimize MTP kernel with ILP rows and SMEM v caching](../sources/prs/flashinfer/PR-2618.md), [feat: add pool+indices support to gated_delta_rule_decode_pretranspose (bf16 path) ](../sources/prs/flashinfer/PR-2619.md), [fix: trtllm_mxint4_block_scale_moe unit test to index output list](../sources/prs/flashinfer/PR-2627.md), [benchmark: Enable speculative decode microbenchmarking for paged decode](../sources/prs/flashinfer/PR-2628.md), [benchmark: Add MXFP4/MXFP8 quantization mode support to FP4 MoE benchmark](../sources/prs/flashinfer/PR-2635.md), [Enable sm120f compilation](../sources/prs/flashinfer/PR-2650.md), [fix: Add fused MOE and GEMM AOT modules for SM121](../sources/prs/flashinfer/PR-2654.md), [benchmarks: Add FP8 input / BF16 output in ragged prefill benchmark](../sources/prs/flashinfer/PR-2666.md), [feat(gdn): add BF16 state kernel with MTP support beyond T>4 with intermediate caching.](../sources/prs/flashinfer/PR-2679.md), [fix(jit): GEMM kernels produce NaN under concurrency — missing GDC flags cause PDL synchronization barriers to compile as no-ops](../sources/prs/flashinfer/PR-2716.md), [[gdn] support non-contiguous state for decoding](../sources/prs/flashinfer/PR-2727.md), [Support in-place update for `trtllm_fp8_block_scale_moe`](../sources/prs/flashinfer/PR-2739.md), [[Spark unit test debugging] Fix for tests/attention/test_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-2750.md), [[Spark unit test debugging] Fix for tests/gemm/test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-2751.md), [perf: Performance tune cute dsl RMSNorm variants](../sources/prs/flashinfer/PR-2777.md), [fix(jit): enable GDC for CUTLASS GEMM PDL — SM100 flag only](../sources/prs/flashinfer/PR-2780.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [[fix] Bugfix 1367: fix VariableBlockSparseAttention buffer overflow by dynamically resizing kv_lens_buffer](../sources/prs/flashinfer/PR-2802.md), [feat(gdn): add padding index guard for bf16 decode kernel](../sources/prs/flashinfer/PR-2810.md), [[Spark unit test] Adjust tolerance for test_xqa, test_logits_processor](../sources/prs/flashinfer/PR-2828.md), [perf: Optimize GDN MTP decode kernel (v15) — eliminate ilp=1 fallback…](../sources/prs/flashinfer/PR-2842.md), [fix: fix cute dsl swap_ab tactic failure](../sources/prs/flashinfer/PR-2870.md), [fix: add cute dsl moe utils to AOT](../sources/prs/flashinfer/PR-2872.md), [[fix] bugfix 2856: Fix pre-allocated out shape check in trtllm_batch_decode_with_kv_cache_mla for q_len_per_req > 1](../sources/prs/flashinfer/PR-2876.md), [[NVIDIA] fix(jit): enable GDC for CUTLASS fused MoE PDL — prevent random crashes on SM12x](../sources/prs/flashinfer/PR-2913.md), [fix: Fix autotuner crash on meta-device tensor in trtllm_fp4_block_scale_routed_moe](../sources/prs/flashinfer/PR-2916.md), [feat: SM121 (GB10) tile filtering and autotuner robustness](../sources/prs/flashinfer/PR-2927.md), [CuTe DSL FP4 GEMM Heuristic](../sources/prs/flashinfer/PR-2940.md), [[Perf] Refactor MoE autotuning to set valid topk ids in routed MoE tuning](../sources/prs/flashinfer/PR-2942.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [Update NVSHMEM interface to use NVSHMEM4Py instead of custom bindings](../sources/prs/flashinfer/PR-2960.md), [test: skip unsupported mm_mxfp8 configurations on SM12x](../sources/prs/flashinfer/PR-2974.md), [feat(comm): add MOE Finalize/Reduction patterns to unified allreduce_fusion API](../sources/prs/flashinfer/PR-2982.md), [ Fix MXFP4/MXFP8 failures in SM120 FAST_BUILD and expand all_tiles[] ](../sources/prs/flashinfer/PR-2994.md), [[feat] Add blackwell GDN prefill kernel](../sources/prs/flashinfer/PR-3001.md), [fix: use sym_int64 for strides in rmsnorm CuTe DSL kernels to prevent int32 overflow](../sources/prs/flashinfer/PR-3007.md), [[chore] Install nvidia-cutlass-dsl[cu13] for cu130+](../sources/prs/flashinfer/PR-3017.md), [[feat] Add routing_replay_out support to MoE kernels and Python API](../sources/prs/flashinfer/PR-3024.md), [Fix/3170 dense blockscaled sm12x](../sources/prs/flashinfer/PR-3180.md), [test: enable bmm_mxfp8 cutlass backend coverage on SM12x](../sources/prs/flashinfer/PR-3183.md), [Include TinyGEMM into BF16 autotuner](../sources/prs/flashinfer/PR-3203.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Ameyn/gdn bf16 dispatcher and 4d pool](../sources/prs/flashinfer/PR-3268.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [Ep api design - Build Infra dependencies](../sources/prs/flashinfer/PR-3315.md), [feat: Separate QK/VO head dim dispatch for sm90 AOT](../sources/prs/flashinfer/PR-778.md), [bugfix: fix batch prefill attention kernel unittests](../sources/prs/flashinfer/PR-781.md), [bugfix: fix the behavior of mla plan function when provided with host tensors](../sources/prs/flashinfer/PR-816.md), [unittest: add MLA test cases where kv_len is evenly divided by page_size.](../sources/prs/flashinfer/PR-861.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [Update torch-xpu-ops commit pin](../sources/prs/pytorch/PR-144209.md), [[inductor][cpu] Fix bmm b_index for dynamic expressions in inductor autotuner](../sources/prs/pytorch/PR-144248.md), [Fix PythonMod printing](../sources/prs/pytorch/PR-144335.md), [Remove runtime dependency on packaging](../sources/prs/pytorch/PR-149125.md), [Add AOTI shim for _weight_int4pack_mm_cpu_tensor (#149031)](../sources/prs/pytorch/PR-149386.md), [op should NOT be static in aoti_torch_call_dispatcher](../sources/prs/pytorch/PR-149644.md), [Dont exclude constant_pad_nd in prologue fusion](../sources/prs/pytorch/PR-150145.md), [[inductor] Fix inductor windows linker error](../sources/prs/pytorch/PR-150447.md), [[Windows][inductor] fix blank space break windows file path](../sources/prs/pytorch/PR-150448.md), [[dynamo][super variable] Fix bug to use correct source](../sources/prs/pytorch/PR-152774.md), [[FlexAttention] Remove Old Constraint on lastdim strides](../sources/prs/pytorch/PR-153104.md), [Mark auto_functionalized HOPs as cacheable (#151194)](../sources/prs/pytorch/PR-153304.md), [[FlexAttention] explicilty create grad_q w/ strides](../sources/prs/pytorch/PR-153641.md), [[MPS] Switch Cholesky decomp to column wise](../sources/prs/pytorch/PR-158237.md), [Add warning about removed sm50 and sm60 arches](../sources/prs/pytorch/PR-158301.md), [[CD] CUDA 13 specific followup changes. Remove sm50-70 From CUDA 12.6 and CUDA 12.8 builds](../sources/prs/pytorch/PR-162455.md), [fix cpp extension distributed warning spew](../sources/prs/pytorch/PR-162764.md), [[Cherry Pick][Graph Partition] allow sharing default device context](../sources/prs/pytorch/PR-163097.md), [[Release 2.9] [cuDNN][SDPA][submodule] Roll-back cuDNN frontend upgrade, update Met…](../sources/prs/pytorch/PR-163265.md), [CUDA 13.0 Warning update for supported architectures](../sources/prs/pytorch/PR-163585.md), [fix pickling for BitwiseFn](../sources/prs/pytorch/PR-163861.md), [[SDPA] [MPS] Fixes regression in 2.8.0 for scaled_dot_product_attention using mps](../sources/prs/pytorch/PR-164364.md), [[Flex attention] Fix flex attention head broadcast](../sources/prs/pytorch/PR-164368.md), [[inductor] don't try to reorder loops for template](../sources/prs/pytorch/PR-166910.md), [[Dynamo] Don't guard data ptrs by default with mark_static_address](../sources/prs/pytorch/PR-166913.md), [[Inductor] No longer throw error in bmm out_dtype lowering due to tem…](../sources/prs/pytorch/PR-166922.md), [[GraphPartition] cache get_free_symbol_uses (#166338)](../sources/prs/pytorch/PR-166994.md), [[cuDNN][SDPA] Check-in test for #166211](../sources/prs/pytorch/PR-167121.md), [[Inductor] ExternKernelBenchmarkRequest best attempt](../sources/prs/pytorch/PR-170246.md), [[flex_attention] adds support for low precision K/V inputs in compiled mode with GPU](../sources/prs/pytorch/PR-170486.md), [[cherry-pick] Fix vllm issue for flex (#170499)](../sources/prs/pytorch/PR-170555.md), [Avoid closing random file handles in Inductor](../sources/prs/pytorch/PR-171150.md), [[xpu][fix][inductor] fallback bfloat16 atomics to eager](../sources/prs/pytorch/PR-171247.md), [[MPS] Fix 2-pass SDPA memory corruption by forcing float accumulators](../sources/prs/pytorch/PR-175580.md), [[CI] Update inductor CI jobs to CUDA 13.0](../sources/prs/pytorch/PR-175826.md), [[Inductor] Reject non-contiguous subnode fusion in mix-order reduction.](../sources/prs/pytorch/PR-176410.md), [[inductor] Fix Identity comparability and evalf recursion](../sources/prs/pytorch/PR-176783.md), [[Inductor] Don't unfuse addmm for bf16/fp16 to avoid precision loss](../sources/prs/pytorch/PR-177144.md), [[Inductor][MPS] Fix half-precision type mismatches in Metal shader codegen (#176436)](../sources/prs/pytorch/PR-177193.md), [[MPS] fix compiling of SDPA producing nan results](../sources/prs/pytorch/PR-178009.md), [feat: Add FP4 (E2M1) KV Cache Support with Quantization Utilities for MLA](../sources/prs/sglang/PR-10078.md), [[Feature] Add MLAProcess for DeepSeek MLA on NPU](../sources/prs/sglang/PR-10130.md), [Enable native ModelOpt quantization support (3/3)](../sources/prs/sglang/PR-10154.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [Add support for bf16 x bf16 cutlass fused MoE](../sources/prs/sglang/PR-10275.md), [support qwen3_next blackwell](../sources/prs/sglang/PR-10403.md), [Fix cutlass moe accuracy drop caused by attention UB from DP padding mode](../sources/prs/sglang/PR-10414.md), [Support single batch overlap](../sources/prs/sglang/PR-10422.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [feat: add dsv3 fp4 cutlass moe etp ut](../sources/prs/sglang/PR-10433.md), [Cache the result of `is_blackwell` platform check](../sources/prs/sglang/PR-10498.md), [Enable trtllm mla prefix extend](../sources/prs/sglang/PR-10526.md), [Fix bias handling in TritonMoeQuantInfo within quantization/mxfp4.py](../sources/prs/sglang/PR-10579.md), [support qwen3-next-fp8 deepep](../sources/prs/sglang/PR-10622.md), [[Auto Sync] Update modelopt_quant.py (20250920)](../sources/prs/sglang/PR-10688.md), [Unify SGL Kernel Releases](../sources/prs/sglang/PR-10701.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [Fuse quantize and rope in trtllm_mla MTP](../sources/prs/sglang/PR-10779.md), [[2/2] Support MHA prefill with FlashAttention 4.](../sources/prs/sglang/PR-10937.md), [Quick Fix: fix Qwen3-VL launch failure caused by MRotaryEmbedding arg](../sources/prs/sglang/PR-10985.md), [chore: upgrade sgl-kernel 0.3.13](../sources/prs/sglang/PR-11056.md), [Fix DSR1 accuracy for flashinfer_trtllm MoE with FP8 quantization](../sources/prs/sglang/PR-11081.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [[AMD] Clean up vllm dependencies in moe_runner/triton.py](../sources/prs/sglang/PR-11349.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [[NVIDIA] FA3/FA4 Fix ](../sources/prs/sglang/PR-11606.md), [Support shared experts overlap in cutlass moe](../sources/prs/sglang/PR-11611.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [Use trtllm_mla decode kernel for draft extend in speculative decoding](../sources/prs/sglang/PR-11664.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [[sgl-kernel] support flashmla libtorch](../sources/prs/sglang/PR-11717.md), [Change bf16 to fp8 for some gemms in attention for DeepSeek ckpt v2](../sources/prs/sglang/PR-11805.md), [Use cutlass fp4 gemm by default](../sources/prs/sglang/PR-11813.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [DeepSeek-V3.2: Add Adaptive MHA Attention Pathway for Short-Sequence Prefill](../sources/prs/sglang/PR-11892.md), [chore: upgrade flashinfer 0.4.1](../sources/prs/sglang/PR-11933.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [(1/n)support context parallel with deepseekv3.2-DSA](../sources/prs/sglang/PR-12065.md), [[Ascend] qwen optimization](../sources/prs/sglang/PR-12078.md), [[Ascend][feature] support L1+ L2 radixcache on ascend](../sources/prs/sglang/PR-12214.md), [[DeepseekV32]: use `_concat_mla_absorb_q_general` to replace `torch.cat`](../sources/prs/sglang/PR-12215.md), [[hotfix] missing `w13_weight_fp8` and `w2_weight_fp8` in UE8M0 requantization](../sources/prs/sglang/PR-12259.md), [[Deepseek V3.2] Enable flashmla_auto with MTP](../sources/prs/sglang/PR-12294.md), [fix seqlen bug for trtllm_mla's draft_extend](../sources/prs/sglang/PR-12295.md), [fix: Llama 4 BF16 load on Blackwell](../sources/prs/sglang/PR-12308.md), [fix: llama 4 + trtllm gen + fp8 kv cache incompatibility](../sources/prs/sglang/PR-12347.md), [Replace [silu_and_mul_]scaled_fp4_group_quant by Flashinfer equivalent](../sources/prs/sglang/PR-12376.md), [perf: trtllm mla performance minor improvements](../sources/prs/sglang/PR-12435.md), [Use sgl fp4 quant kernel by default](../sources/prs/sglang/PR-12482.md), [[Ascend] Support enable-mixed-chunk in non-MLA scenarios](../sources/prs/sglang/PR-12491.md), [chore: upgrade flashinfer 0.5.0](../sources/prs/sglang/PR-12523.md), [Enable Flashinfer TRTLLM-GEN-MoE FP8 blockwise kernel for Qwen3-Next on Blackwell](../sources/prs/sglang/PR-12543.md), [[CPU] Fix MoE layer support for DeepSeek-OCR models](../sources/prs/sglang/PR-12555.md), [feat: Add FP4 (E2M1) KV Cache Support for MHA](../sources/prs/sglang/PR-12612.md), [[NVIDIA] Fix wrong symmetric sizes for fp4 cases](../sources/prs/sglang/PR-12640.md), [[sgl-kernel][5/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12666.md), [[fix] Only enable flashinfer all reduce fusion by default for single-node servers](../sources/prs/sglang/PR-12724.md), [[Bugfix] Fix illegal memory access](../sources/prs/sglang/PR-12758.md), [[Ascend] support Kimi-K2-Thinking](../sources/prs/sglang/PR-12759.md), [Update dsv3 quantization auto setting for sm100](../sources/prs/sglang/PR-12778.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [[DeepSeek-V3.2][NSA] Enable MHA Pathway for Short Sequence Prefill on B200 (SM100)](../sources/prs/sglang/PR-12788.md), [[Deepseek V3.2] Only skip Indexer logits computation when is_extend_without_speculative](../sources/prs/sglang/PR-12816.md), [Apply moe_reduce_sum kernel for fused_marlin_moe](../sources/prs/sglang/PR-12888.md), [[Deepseek V3.2] Use torch.compile to speed up torch.cat in nsa](../sources/prs/sglang/PR-13022.md), [Support moe topk sigmoid kernel](../sources/prs/sglang/PR-13049.md), [[sgl-kernel] support custom fp8 flashmla kernel](../sources/prs/sglang/PR-13087.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Aiter fp8 kv cache](../sources/prs/sglang/PR-13147.md), [Support internvl on Blackwell (which doesn't support fa3): add `SingletonCache` support to Vision{Sdpa|Triton|Ascend}Attention](../sources/prs/sglang/PR-13151.md), [[NPU]Optimization of `forward_npu` for `UnquantizedFusedMoEMethod`](../sources/prs/sglang/PR-13158.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [diffusion: enable fa4 for blackwell](../sources/prs/sglang/PR-13263.md), [[NVIDIA] Fix broken fp8 MoE of deepseek v3](../sources/prs/sglang/PR-13264.md), [[NVIDIA] Fix use case of SGLANG_ENABLE_FLASHINFER_GEMM](../sources/prs/sglang/PR-13274.md), [Support weight update for blackwell DeepGEMM](../sources/prs/sglang/PR-13324.md), [Flashinfer TRTLLM-GEN-MoE + Qwen3](../sources/prs/sglang/PR-13489.md), [Fix target MLA with eagle3 support for PD disaggregation](../sources/prs/sglang/PR-13555.md), [[BugFix] fix prefixcache performance and accuracy on ascend](../sources/prs/sglang/PR-13573.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [[DeepSeekV3.2] Enable pure TP & Partial DP Attention](../sources/prs/sglang/PR-13646.md), [Fix EPLB + FP4 Quantization Compatibility Issue](../sources/prs/sglang/PR-13715.md), [[bugfix] fix TBO crashes when attn_tp_size > 1](../sources/prs/sglang/PR-13730.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [fix trtllm mla spec](../sources/prs/sglang/PR-13738.md), [[AMD] Support --enable-aiter-allreduce-fusion on AMD GPUs](../sources/prs/sglang/PR-13747.md), [[chore]Upgrade flashinfer to 0.5.3](../sources/prs/sglang/PR-13751.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [[NVIDIA] Enable TRTLLM BF16 MoE on Blackwell GPUs](../sources/prs/sglang/PR-13798.md), [update flashinfer_cubin==0.5.3](../sources/prs/sglang/PR-13848.md), [[BugFix] fix outplace_fused_experts missing is_gated](../sources/prs/sglang/PR-13864.md), [Feat: GLM-4.6 supports shared experts fusion](../sources/prs/sglang/PR-13873.md), [Fix update weight error for blackwell DeepGEMM](../sources/prs/sglang/PR-13910.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Use trtllm mha decode kernel for target_verify in speculative decoding](../sources/prs/sglang/PR-13976.md), [Support KTransformers for Qwen3-VL moe](../sources/prs/sglang/PR-13983.md), [Fix flashinfer cutlass MoE output shape for non-FP4-packed inputs](../sources/prs/sglang/PR-14028.md), [[LoRA][III] Add LoRA support for MoE layers and enable TP](../sources/prs/sglang/PR-14105.md), [Add new moe wna16 marlin gemm](../sources/prs/sglang/PR-14122.md), [Apply new moe wna16 marlin gemm](../sources/prs/sglang/PR-14125.md), [Apply new moe align block size kernel](../sources/prs/sglang/PR-14134.md), [Support checking fp8 params in weight_checker](../sources/prs/sglang/PR-14147.md), [fix: Increase FlashInfer workspace size for Qwen3VL models](../sources/prs/sglang/PR-14173.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[bug fix] fix ima with get_mla_kv_buffer_kernel overflow](../sources/prs/sglang/PR-14224.md), [Tiny use trtllm_mha as default when possible](../sources/prs/sglang/PR-14291.md), [[Fix] add block size logic for sm120 smem size](../sources/prs/sglang/PR-14311.md), [[FIX] trtllm-moe-fp4-renorm for Qwen series models](../sources/prs/sglang/PR-14350.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [[NPU] perf update with kvcache nz & w4a8 quant](../sources/prs/sglang/PR-14423.md), [Add Mistral Large 3 Eagle Support](../sources/prs/sglang/PR-14466.md), [Mistral Large 3 NVFP4 support](../sources/prs/sglang/PR-14485.md), [[diffusion] kernel fusion: gated residual layernorm scale shift and layernorm scale shift kernel fusion for Qwen-Image, WAN and HunyuanVideo](../sources/prs/sglang/PR-14717.md), [[NPU][eagle3] support qwen eagle3 on NPU](../sources/prs/sglang/PR-14820.md), [Apply back moe_sum_reduce for fused_marlin_moe](../sources/prs/sglang/PR-14829.md), [fix: trtllm mha attention auto-selection on sm120](../sources/prs/sglang/PR-14842.md), [Fix dsv3 dp accuracy issue when using bf16-kv](../sources/prs/sglang/PR-14897.md), [Fix accuracy issue when using a16w16 mla_decode_fwd](../sources/prs/sglang/PR-14936.md), [[AMD] Support fused_rms_mxfp4_quant in the prefill stage for DeepSeek-R1-MXFP4](../sources/prs/sglang/PR-14975.md), [add transformers version validation for glm-4.6v moe models](../sources/prs/sglang/PR-14998.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [fix(attention): Prevent trtllm_mha auto-selection with eagle3 speculative decoding](../sources/prs/sglang/PR-15127.md), [[sgl-kernel][1/2] Fused qk_norm_rope for GLM4.6](../sources/prs/sglang/PR-15141.md), [[NVIDIA] upstream FA4](../sources/prs/sglang/PR-15182.md), [[NVIDIA] Fixes for NVFP4 all-gather with spec decoding](../sources/prs/sglang/PR-15280.md), [[Fix] A followup fix for TRTLLM BF16 MoE](../sources/prs/sglang/PR-15303.md), [Fix the accuracy issue when running mxfp4 dsv3 model and enable ep](../sources/prs/sglang/PR-15304.md), [feat: support bitsandbytes quantization algorithm](../sources/prs/sglang/PR-15325.md), [[distributed] Clean up MoE groups in destroy_model_parallel](../sources/prs/sglang/PR-15345.md), [[Tiny]Add warning for deepgemm on Blackwell](../sources/prs/sglang/PR-15352.md), [[NPU]mindspore model support moe](../sources/prs/sglang/PR-15363.md), [[NPU]DeepSeek-V3.2 support npu mlaprolog](../sources/prs/sglang/PR-15381.md), [[diffusion] Add Sage Attention 3 Support for sm 120 (RTX5090)](../sources/prs/sglang/PR-15382.md), [Super tiny add moe_ep_rank to prometheus labels](../sources/prs/sglang/PR-15407.md), [Flashinfer MOE FP8 support for Mistral Large 3.](../sources/prs/sglang/PR-15422.md), [Optimize MiMo-V2-Flash by flashinfer fused allreduce](../sources/prs/sglang/PR-15464.md), [[Perf] Add Flashinfer DeepGEMM SM90 for SwapAB Optimization](../sources/prs/sglang/PR-15514.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [Optimize Bailing-MoE with FlashInfer Fused All-Reduce](../sources/prs/sglang/PR-15526.md), [MoE: Skip SiLU/GELU activation for masked experts](../sources/prs/sglang/PR-15539.md), [Update flashinfer to 0.6.1](../sources/prs/sglang/PR-15551.md), [[sgl-kernel] Streamline kernel size report (Top 20 only) and clean up](../sources/prs/sglang/PR-15552.md), [Fix BatchMLAPagedAttentionWrapper query/qo_inptr mismatch for EAGLE](../sources/prs/sglang/PR-15601.md), [[jit-kernel] Add CuTe DSL GDN Decode Kernel](../sources/prs/sglang/PR-15631.md), [Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-15712.md), [[Perf] Eliminate the slice op for Flashinfer `trtllm_fp4_block_scale_moe`](../sources/prs/sglang/PR-15731.md), [Fix GLM-4.7 MoE Detector complex JSON Schema type parsing](../sources/prs/sglang/PR-15753.md), [Fix: Handle empty func_name and None values in GLM MoE detectors](../sources/prs/sglang/PR-15754.md), [[Feature] JIT Fused QK norm + qk norm clean up](../sources/prs/sglang/PR-15835.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [[diffusion] model: support TurboWan2.1-T2V-1.3B/14B SLA](../sources/prs/sglang/PR-15888.md), [[fix]deepgemm precompile when warmup](../sources/prs/sglang/PR-15891.md), [Bugfix for ds-vl2](../sources/prs/sglang/PR-15894.md), [[NPU] NZ for non-quantized MOE, Qwen3 MOE double memory consumption fix](../sources/prs/sglang/PR-15904.md), [ Add tuned triton==3.5.1 h200 tp2, tp4 for qwen 3 next](../sources/prs/sglang/PR-15948.md), [Tiny fix cannot launch nvfp4 checkpoint with bf16 kv cache](../sources/prs/sglang/PR-15986.md), [[Performance] Force split_k=1 for MXFP4 Triton kernels on Hopper](../sources/prs/sglang/PR-16014.md), [Support fa4 decoding](../sources/prs/sglang/PR-16034.md), [optimize get_topk_ragged by fusing get k and k_scale triton kernel](../sources/prs/sglang/PR-16043.md), [[Diffusion] Flux support flashinfer rope](../sources/prs/sglang/PR-16055.md), [enhance accuracy for model kimi-vl-instruct-a3b](../sources/prs/sglang/PR-16076.md), [fix layer intermediate size](../sources/prs/sglang/PR-16084.md), [[Diffusion] Zimage opt with qknorm and flashinfer rope](../sources/prs/sglang/PR-16161.md), [[Feature] add aligned_vector type for JIT kernel](../sources/prs/sglang/PR-16162.md), [[VLM] Adopt jit qk_norm kernel in VLM](../sources/prs/sglang/PR-16171.md), [[NemotronH] Add latent MoE support](../sources/prs/sglang/PR-16227.md), [[Fix] Only add SM90 and SM100 to check for auto-enabling TRT Allreduce Fusion](../sources/prs/sglang/PR-16283.md), [[diffusion] Fix RuntimeError in SageAttention3 on Nvidia Blackwell with Qwen-Image](../sources/prs/sglang/PR-16335.md), [[Fix]Fix FA3 Performance in Diffusion Model ](../sources/prs/sglang/PR-16382.md), [Fix FP8 MoE NaN with DeepGEMM on Blackwell](../sources/prs/sglang/PR-16622.md), [[Rework] Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-16723.md), [[AMD] Support redundant expert with a2a moe in gfx95x.](../sources/prs/sglang/PR-16791.md), [[Fix] `flashinfer_trtllm` `intermediate_size` assertion with Qwen3 + TP=8](../sources/prs/sglang/PR-16824.md), [Support mxint4 flashinfer_trtllm moe gemm](../sources/prs/sglang/PR-16892.md), [[DeepSeek v3.2] Opt MTP decode cuda batch sizes and nsa implementation](../sources/prs/sglang/PR-16961.md), [[NPU]bugfix: fix for dsv3.2 and dsvl2](../sources/prs/sglang/PR-17007.md), [[MUSA][2/N] sgl-kernel build](../sources/prs/sglang/PR-17053.md), [Optimize GDN decode for Qwen3 Next](../sources/prs/sglang/PR-17094.md), [[diffusion] fix: fix using upstream flash_attn on blackwell](../sources/prs/sglang/PR-17111.md), [Enable XQA for SM90 and SM120](../sources/prs/sglang/PR-17115.md), [Inclusion of nvfp4 blockscale in EPLB Rebalance](../sources/prs/sglang/PR-17158.md), [[Fix] GLM 4.7 + NVFP4 + MTP](../sources/prs/sglang/PR-17166.md), [[GLM 4.7] Add RTX 6000 Pro aka sm120](../sources/prs/sglang/PR-17235.md), [[New Model] GLM4.7-Flash](../sources/prs/sglang/PR-17247.md), [[FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/sglang/PR-17300.md), [Disable mla persistent kernel when not using fp8 kv_cache](../sources/prs/sglang/PR-17327.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [Add mxfp8 support for online quantization, Triton dense linear, and CUTLASS MoE](../sources/prs/sglang/PR-17449.md), [[NPU] enhance accuracy for model kimi-vl-a3b-instruct](../sources/prs/sglang/PR-17480.md), [Kernel: optimize decoding metadata in NSA multi-spec backend with fused kernels](../sources/prs/sglang/PR-17554.md), [[hotfix] Reenable all reduce fusion on sm100](../sources/prs/sglang/PR-17591.md), [[feat] Support nvfp4 quantized model of Qwen3-Next](../sources/prs/sglang/PR-17627.md), [Upgrade transformers==5.3.0](../sources/prs/sglang/PR-17784.md), [fix(quantization): add sgl_kernel fallback for FP4 quantize on Blackwell GPUs](../sources/prs/sglang/PR-17816.md), [Feature/support longcat flash lite](../sources/prs/sglang/PR-17838.md), [[Move sgl-kernel Kernel to JIT] Add JIT concat MLA kernels](../sources/prs/sglang/PR-17889.md), [Skipped warning on sm100](../sources/prs/sglang/PR-18000.md), [[Bugfix] Fix Mistral Large 3 NVFP4 TRTLLM MoE](../sources/prs/sglang/PR-18065.md), [Feat/add fi selective state update kernel call](../sources/prs/sglang/PR-18070.md), [[Diffsuion & JIT_kernel] QKNorm cross heads kernel](../sources/prs/sglang/PR-18073.md), [Fix nvfp4 weight update](../sources/prs/sglang/PR-18085.md), [[Blackwell] Make mxint4 flashinfer_trtllm moe gemm set by default on blackwell](../sources/prs/sglang/PR-18136.md), [[ModelOpt] Fix broken Qwen3-235B-A22B-Instruct-2507-NVFP4 launch](../sources/prs/sglang/PR-18189.md), [[ModelOPT] Support Qwen 3 Next Coder NVFP4](../sources/prs/sglang/PR-18224.md), [Support Qwen3 MoE context parallel](../sources/prs/sglang/PR-18233.md), [[ROCm] Optimize Deepseek R1 on MI300X](../sources/prs/sglang/PR-18242.md), [[Hicache & JIT_kernel] Support page first layout & mla jit kernel](../sources/prs/sglang/PR-18311.md), [[AMD] Support Qwen3-Coder-Next on AMD platform](../sources/prs/sglang/PR-18355.md), [[MUSA][10/N] Add GGUF support](../sources/prs/sglang/PR-18357.md), [feat(gdn): add FlashInfer K-last SSM layout support for GDN prefill and decode for Hopper](../sources/prs/sglang/PR-18361.md), [[Kimi-K2.5] Fix NVFP4 Kimi-K2.5 weight mapping and exclude list](../sources/prs/sglang/PR-18370.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [feat: add FA4 SM90 paged KV decode support & update attention docs](../sources/prs/sglang/PR-18442.md), [Tilelang sparse decode fwd for dsv32 mi355](../sources/prs/sglang/PR-18488.md), [[FIX] Correct JIT kernel compilation on newer GPUs with outdated driver metadata.](../sources/prs/sglang/PR-18496.md), [Fp8 prefill attn kernel integration](../sources/prs/sglang/PR-18528.md), [[AMD] Fix accuracy issue when running TP4 dsv3 model with mtp](../sources/prs/sglang/PR-18607.md), [[AMD] DSR1/V3 use fp8 bmm in MLA for MI300X](../sources/prs/sglang/PR-18624.md), [[sglang-miles] True on-policy training support for FSDP2](../sources/prs/sglang/PR-18639.md), [use flashinfer.sampling](../sources/prs/sglang/PR-18696.md), [[RL] Support per-layer mixed FP8/BF16 serving for FP8 checkpoints](../sources/prs/sglang/PR-18742.md), [fix: update Blackwell log/error messages to include SM12x](../sources/prs/sglang/PR-18751.md), [[diffusion] Diffusion norm fusion for z-image](../sources/prs/sglang/PR-18762.md), [fix: add SM110 (Jetson AGX Thor) to Blackwell capability check](../sources/prs/sglang/PR-18787.md), [Migrate renorm kernels from sgl-kernel to FlashInfer JIT](../sources/prs/sglang/PR-18854.md), [[Perf] ~9.5x faster Blackwell MXFP4 MoE weight loading](../sources/prs/sglang/PR-18858.md), [Migrate norm kernels to FlashInfer JIT implementation](../sources/prs/sglang/PR-18871.md), [[sgl-kernel] rebase FlashMLA 0217](../sources/prs/sglang/PR-18902.md), [Fix NSA FP8 KV cache path for both-trtllm MHA one-shot](../sources/prs/sglang/PR-18931.md), [[Qwen3.5] Enable nvfp4 checkpoint](../sources/prs/sglang/PR-18937.md), [[Sarvam] Add inference support for Sarvam MoE LLMs](../sources/prs/sglang/PR-18938.md), [[jit_kernel] Add fused_qknorm_rope JIT kernel](../sources/prs/sglang/PR-19059.md), [Support skip-softmax attention](../sources/prs/sglang/PR-19089.md), [feat: Support MXFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-19143.md), [[DeepSeek-V3.2][JIT-kernel] Support nsa fuse store indexer k cache](../sources/prs/sglang/PR-19148.md), [[NVIDIA] Integrate FlashInfer decode kernel (Blackwell) for Qwen3.5](../sources/prs/sglang/PR-19150.md), [Adjust padding size to improve triton_kernels moe performance](../sources/prs/sglang/PR-19174.md), [[AMD] Fix accuracy while using --enable-dp-attention](../sources/prs/sglang/PR-19247.md), [Fix nightly Mistral-Large-3 NVFP4 accuracy threshold](../sources/prs/sglang/PR-19402.md), [[AMD] Fix weight load shape mismatch for amd dsr1 0528 mxfp4](../sources/prs/sglang/PR-19425.md), [[Feature] add feature mla_ag_after_qlora for dsv3.2](../sources/prs/sglang/PR-19428.md), [Fix/nemotron mtp quantaized](../sources/prs/sglang/PR-19433.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [[NPU] bugs fix for Deepseek models](../sources/prs/sglang/PR-19544.md), [[diffusion][llm] macOS support](../sources/prs/sglang/PR-19549.md), [[miles] fix for glm5](../sources/prs/sglang/PR-19634.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Support `triton_kernels` for GPT-OSS on SM120](../sources/prs/sglang/PR-19718.md), [Various SM120 improvements](../sources/prs/sglang/PR-19721.md), [[SGLang-Diffusion] Fix custom op fake impl missing eps default for torch.compile](../sources/prs/sglang/PR-19725.md), [Add compile-time 256-bit vector guard for pre-Blackwell](../sources/prs/sglang/PR-19794.md), [[JIT Kernel][Feature] Support JIT custom all reduce (rewrite as v2)](../sources/prs/sglang/PR-19880.md), [Use TRTLLM allreduce fusion for Qwen 3.5](../sources/prs/sglang/PR-19889.md), [Fix MLA decode path returning unwritten (padded) rows](../sources/prs/sglang/PR-19902.md), [[AMD] Fix Tensor Memory Aliasing ](../sources/prs/sglang/PR-19928.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [[AMD] Tilelang sparse fwd for dsv32 mi355/mi300](../sources/prs/sglang/PR-19945.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[Bugfix] Work around FlashInfer unified transport issue on GB](../sources/prs/sglang/PR-20039.md), [Fix SM120 `triton_kernels` MXFP4 `block_k` for GPT-OSS](../sources/prs/sglang/PR-20040.md), [MiniMax-M2.5 - Support dp attention, dp reduce scatter, FP4 all gather, AR fusion in prepare_attn](../sources/prs/sglang/PR-20067.md), [Fix streaming session with paged KV cache (SWA/MLA)](../sources/prs/sglang/PR-20070.md), [Enable modelopt quantized FLUX deployment](../sources/prs/sglang/PR-20082.md), [[V32/GLM5] Change default setting of V32 nvfp4 on TP4](../sources/prs/sglang/PR-20086.md), [[diffusion] fix bug of copy_if](../sources/prs/sglang/PR-20094.md), [[diffusion] Support nvfp4 for Flux.2](../sources/prs/sglang/PR-20137.md), [[AMD] Fp8 prefill integration with radix cache path for dpsk models](../sources/prs/sglang/PR-20187.md), [[4/n jit_kernel restruct] speed up CI tests and add benchmark workflow](../sources/prs/sglang/PR-20268.md), [[AMD] Add 4-GPU test suite for MI325 runners](../sources/prs/sglang/PR-20294.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[Fix] Add fallback for flashinfer allreduce fusion](../sources/prs/sglang/PR-20384.md), [[NVIDIA] Enable fp8 flashinfer_trtllm_routed MoE for MiniMax-M2.5](../sources/prs/sglang/PR-20394.md), [[AMD][Bug-fix] Fix gpu fault when run the test with dp-attention-enabled and max-concurrency is over 256](../sources/prs/sglang/PR-20399.md), [[Model] Support Nemotron 3 Super NVFP4](../sources/prs/sglang/PR-20407.md), [[AMD][AITER] Guard _use_mla_ps_kernel with self.use_mla in draft_extend_v2 paths](../sources/prs/sglang/PR-20409.md), [[GDN] Add benchmark for sglang gdn prefill](../sources/prs/sglang/PR-20428.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [[Kernel] Fuse temperature + softmax in sampling for decode speedup](../sources/prs/sglang/PR-20501.md), [[Diffusion] Clean upstream fa3 in hopper](../sources/prs/sglang/PR-20576.md), [Use Flashinfer for target_verify in GDN model for SM120](../sources/prs/sglang/PR-20604.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [[Diffusion] Add a benchmark for rmsnorm/fuse_add_rmsnorm](../sources/prs/sglang/PR-20632.md), [Fix(jit): support rmsnorm for hidden_size in {64, 128, 256}](../sources/prs/sglang/PR-20661.md), [[Feature][JIT Kernel] Fused TP QK norm For Minimax](../sources/prs/sglang/PR-20673.md), [[Diffusion] Fix compile graph broken by flashinfer rope](../sources/prs/sglang/PR-20699.md), [Add Mistral Small 4 (Pixtral) support](../sources/prs/sglang/PR-20708.md), [Use FlashInfer tinygemm for GPT-OSS MoE router on SM90+](../sources/prs/sglang/PR-20755.md), [fix: guard configure_deep_gemm_num_sms when JIT disabled](../sources/prs/sglang/PR-20868.md), [[JIT Kernel] Fix NVFP4 multi-arch compilation failure](../sources/prs/sglang/PR-20874.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Qwen3.5] Fuse split/reshape/cat ops in GDN projection with Triton kernel](../sources/prs/sglang/PR-21019.md), [[Chore] Clean up JIT compilation flags](../sources/prs/sglang/PR-21022.md), [fix: wrap _import_static_state in inference_mode to fix resume on Blackwell](../sources/prs/sglang/PR-21035.md), [perf: precompute FA3 scheduler_metadata to eliminate per-layer prepare_varlen_num_blocks](../sources/prs/sglang/PR-21104.md), [ci: remove IS_BLACKWELL env var; auto-detect Blackwell](../sources/prs/sglang/PR-21118.md), [[Not-Merge][AMD] GLM-5 performance optimization](../sources/prs/sglang/PR-21166.md), [[Whisper] Enable CUDA graph support and timestamp for whisper model](../sources/prs/sglang/PR-21190.md), [[NPU] bugfix for import sgl-kernel error](../sources/prs/sglang/PR-21200.md), [[KDA] Support CuTeDSL KDA decode kernel](../sources/prs/sglang/PR-21203.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [[refactor] Clean up duplicate flashinfer trtllm moe code](../sources/prs/sglang/PR-21233.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[NVIDIA] Enable FP4 flashinfer trtllm routed moe](../sources/prs/sglang/PR-21240.md), [P2P Weight Update features for miles ](../sources/prs/sglang/PR-21278.md), [[RL] Support mxfp8 DeepSeek V3](../sources/prs/sglang/PR-21280.md), [[MUSA] apply_vocab_mask support musa device](../sources/prs/sglang/PR-21296.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[Kernel] Support FlashInfer TRTLLM-Gen fused MoE for non-gated FP4 & FP8 (Nemotron)](../sources/prs/sglang/PR-21321.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Add dedicated FlashInferCuteDslMoE layer for standard-path FP4 MoE](../sources/prs/sglang/PR-21339.md), [[GDN] Fuse GDN kkt + solve_tril into one kernel](../sources/prs/sglang/PR-21411.md), [[Bugfix] Lazy-import CuteDSL KDA kernel to fix AMD/ROCm startup crash](../sources/prs/sglang/PR-21428.md), [fix nemotron capture for non attention layers](../sources/prs/sglang/PR-21436.md), [[Diffusion] Add qknorm rope fuse kernel](../sources/prs/sglang/PR-21440.md), [Add explicit disable flag for FlashInfer allreduce fusion](../sources/prs/sglang/PR-21446.md), [fix: piecewise_cuda_graph get correct qo_indptr](../sources/prs/sglang/PR-21452.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [test: point DSV3 int8 MLA CI models to lmsys Hugging Face org](../sources/prs/sglang/PR-21561.md), [[FlashInver v0.6.7] Integrate flashinfer_trtllm mxfp8 gemm](../sources/prs/sglang/PR-21576.md), [Change default mm-attention backend from triton_attn to fa4](../sources/prs/sglang/PR-21595.md), [fix: TRT-LLM MHA CUDA illegal address with EAGLE v2 + DP attention](../sources/prs/sglang/PR-21649.md), [[jit_kernel] Optimize fused_qknorm_rope: deduplicate sincosf for interleave RoPE ](../sources/prs/sglang/PR-21654.md), [[AMD] Use tgemm.mm for MoEGate router gemm in deepseek_v2.py](../sources/prs/sglang/PR-21657.md), [[XPU] Enable qwen3.5 on XPU](../sources/prs/sglang/PR-21668.md), [[AMD] Add GLM-5-FP8 nightly performance benchmarks for MI30x and MI35x](../sources/prs/sglang/PR-21710.md), [Harden FlashInfer FP4 imports in standard dispatcher](../sources/prs/sglang/PR-21776.md), [[Fix] Fall back to triton MOE for GPT-OSS on Blackwell with driver >= 595](../sources/prs/sglang/PR-21780.md), [[DSA] Support trtllm sparse mla kernel for prefill batches ](../sources/prs/sglang/PR-21783.md), [Remove redundant test_moe_eval_accuracy_large](../sources/prs/sglang/PR-21787.md), [[Feature] JIT rmsnorm update (with claude)](../sources/prs/sglang/PR-21834.md), [ [GDN] Remove FlashInfer GDN decode + no_buffer guard and default to FlashInfer on SM100+ ](../sources/prs/sglang/PR-21861.md), [[server] Add --quantization unquant to explicitly opt out of quantization](../sources/prs/sglang/PR-21863.md), [[Misc] [MXFP8] Drop sm100 mxfp8 warning](../sources/prs/sglang/PR-21881.md), [fix pcg torch dynamo recompile in mxfp8 Triton path](../sources/prs/sglang/PR-21888.md), [[Bugfix] Temporarily skip TRTLLM attention on (G)B300 (SM103) to avoid high-concurrency hang](../sources/prs/sglang/PR-21906.md), [[DSA] Set trtllm kernels as default for Blackwell](../sources/prs/sglang/PR-21914.md), [[Bugfix] Fix CUDA graph replay issues in trtllm_mla draft_extend](../sources/prs/sglang/PR-21987.md), [Tiny fix trtllm_fp8_per_tensor_scale_moe_wrapper router_logits dtype](../sources/prs/sglang/PR-22006.md), [[NPU] enable mla prepare fused kernel only when being mla attn](../sources/prs/sglang/PR-22024.md), [[MUSA][9/N] Add FA3 attention backend support through MATE (MUSA AI Tensor Engine)](../sources/prs/sglang/PR-22051.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[diffusion] Default NVFP4 to CUTLASS and add all-model shape benchmarks](../sources/prs/sglang/PR-22091.md), [[Diffusion] Add diffusion NVFP4 scaled-mm correctness test](../sources/prs/sglang/PR-22127.md), [[Hotfix] Fix router gemm on sm103](../sources/prs/sglang/PR-22134.md), [[Disagg][NIXL] Fix heterogeneous TP KV transfer for non-MLA models (same logic with mooncake, Step 1/2 for Qwen3.5 support)](../sources/prs/sglang/PR-22145.md), [[hisparse]: Adding ci for hisparse kvcache-swap-in jit-kernel](../sources/prs/sglang/PR-22155.md), [[HiSparse]: Add benchmark for hisparse kernel](../sources/prs/sglang/PR-22187.md), [[RL] Refactor NVFP4 shuffling/swizzling to in-place replacement](../sources/prs/sglang/PR-22204.md), [Reduce unnecessary kernels and copies in the NSA indexer](../sources/prs/sglang/PR-22232.md), [[AMD][HIP] NSA: bf16 passthrough from RMSNorm to eliminate FP8 dequantization](../sources/prs/sglang/PR-22258.md), [Lazy import flash_attention_v4 to avoid loading flash_attn.cute at startup](../sources/prs/sglang/PR-22306.md), [[AMD] Fix GLM-5 fp8 KV quant path dispatch on MI300](../sources/prs/sglang/PR-22314.md), [[Reland] DeepSeek-R1-0528-w4a8: DeepEP Low Latency Dispatch Adopts FP8 Communication](../sources/prs/sglang/PR-22316.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [[AMD] Add GLM-5.1-FP8 nightly accuracy and performance benchmarks for MI30x and MI35x](../sources/prs/sglang/PR-22336.md), [:sparkles: [diffusion][npu][quant] Add MXFP4 quantization support for Wan2.2 Diffusion on Ascend NPU](../sources/prs/sglang/PR-22338.md), [[Diffusion] modelopt diffusion fp8 support for flux1/flux2 and wan2.2](../sources/prs/sglang/PR-22365.md), [[DSA] Hopper FP8 FlashMLA KV padding](../sources/prs/sglang/PR-22372.md), [[Lora] Lora kimi support](../sources/prs/sglang/PR-22381.md), [[AMD] Use aiter CK layernorm2d for LayerNorm to reduce NSA indexer kernel launches](../sources/prs/sglang/PR-22424.md), [[Fix] Fix several bugs on DSA models](../sources/prs/sglang/PR-22430.md), [Upgrade sglang-torch-profiler-analysis SKILLS](../sources/prs/sglang/PR-22440.md), [[RL] Fix weight update for mxfp8 flashinfer_cutlass gemm backend](../sources/prs/sglang/PR-22484.md), [GLM-5/5.1 MXFP4 Checkpoint Inference Compatibility Fix](../sources/prs/sglang/PR-22543.md), [[Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22574.md), [diffusion: fix layerwise offload for ModelOpt quantized DiTs](../sources/prs/sglang/PR-22594.md), [feat: Support flashinfer_cutedsl MoE runner with flashinfer alltoall backend](../sources/prs/sglang/PR-22669.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [[Diffusion] Add Wan2.2 ModelOpt NVFP4 support](../sources/prs/sglang/PR-22681.md), [[Step3p5] Optimize allreduce in MoE layers ](../sources/prs/sglang/PR-22773.md), [Dual MoE CUDA graph capture for lora/nolora batches](../sources/prs/sglang/PR-22809.md), [diffusion: add HunyuanVideo GroupNorm+SiLU fast path](../sources/prs/sglang/PR-22814.md), [[Refactor] Refactor DeepEP dispatcher](../sources/prs/sglang/PR-22822.md), [[FlashInfer v0.6.11] [RL] Support FlashInfer per-token NVFP4 MoE](../sources/prs/sglang/PR-22918.md), [[Fix/Kernel] Add JIT rmsnorm_hf kernel to fix transformers backend MMLU accuracy regression ](../sources/prs/sglang/PR-22931.md), [[codex] diffusion: enable group norm silu fuse by default](../sources/prs/sglang/PR-23148.md), [[BugFix] Resolve adaptive speculative decoding conflicts for Qwen3.5 (hybrid GDN)](../sources/prs/sglang/PR-23331.md), [[Diffusion][NPU]Add attention backends for diffusion models for Ascend NPU](../sources/prs/sglang/PR-23482.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [feat: port SGLANG_JIT_DEEPGEMM_FAST_WARMUP to deepseek_v4 branch](../sources/prs/sglang/PR-23756.md), [[MoE] Unify DeepEPMoE+MoriEPMoE through AITER MoeRunner pre/post-permute](../sources/prs/sglang/PR-23760.md), [Optimize large GroupNorm SiLU apply](../sources/prs/sglang/PR-23938.md), [[feat] Init true on policy with qwen_dense](../sources/prs/sglang/PR-23961.md), [Enable PDL for various kernels in DSV32/GLM5](../sources/prs/sglang/PR-23965.md), [[VLM] Optimize Gemma4 VLM with PCG and fuse RMSNorm + residual add + scalar](../sources/prs/sglang/PR-24048.md), [Refactor device timer, clean up metrics collector, and add fwd occupancy metric](../sources/prs/sglang/PR-24197.md), [[KDA] Optimize prefill kernels with diagonal and recompute fuse](../sources/prs/sglang/PR-24271.md), [[diffusion] Fuse LTX2 split rotary embedding](../sources/prs/sglang/PR-24411.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [Fix performance regression on Deepseek V3 on `moe-runner-backend=triton` on SM90](../sources/prs/sglang/PR-24562.md), [[Codex] Opt Mistral Large performace ](../sources/prs/sglang/PR-24611.md), [Support spec v2 for FlashMLA speculative decoding](../sources/prs/sglang/PR-24640.md), [[Gemma4] Optimize Gemm4 with fused Q/K/V RMSNorm + per-expert FP8 ckpt loader](../sources/prs/sglang/PR-24696.md), [[codex] Optimize hidden-size 512 RMSNorm dispatch](../sources/prs/sglang/PR-24710.md), [Add FlashInfer SM90 cutlass MXFP4 MoE backend (W4A16) for GPT-OSS + DeepSeek-V4](../sources/prs/sglang/PR-24816.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [perf(nvfp4): free unused source scales after weight processing](../sources/prs/sglang/PR-25107.md), [Fix AMX GQA extend attention](../sources/prs/sglang/PR-25180.md), [[MUSA][Diffusion] Improve wan model inference speed using torch.compile](../sources/prs/sglang/PR-25256.md), [Support Gemma4 Pipeline Parallelism](../sources/prs/sglang/PR-25284.md), [Fix EPLB mapping for TopK paths](../sources/prs/sglang/PR-25285.md), [[Gemma4]: Fix FP8 Triton scale layout](../sources/prs/sglang/PR-25286.md), [[NSA] Avoid repeated NSA MQA logits memory queries](../sources/prs/sglang/PR-25299.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[AMD] test(sgl-kernel): seed RNG on ROCm in test_moe_topk_sigmoid to fix tie-break flake](../sources/prs/sglang/PR-25356.md), [[AMD] Enable shared-experts fusion with new KIMI-K2.5-MXFP4 model.](../sources/prs/sglang/PR-25390.md), [[codex] Update Wan2.2 ModelOpt CI checkpoints](../sources/prs/sglang/PR-25483.md), [Support draft extend cuda graph for tokenspeed_mla attention backend](../sources/prs/sglang/PR-25489.md), [Update logging for inplace setting in MoE layer](../sources/prs/sglang/PR-25499.md), [[misc] Throw error when single batch overlap is enabled on Hopper ](../sources/prs/sglang/PR-25509.md), [Fix logging for inplace setting in the flashInfer-trtllm backend](../sources/prs/sglang/PR-25522.md), [[Bug Fix] Align glm4_moe_nextn NPU MTP loading with qwen3 MTP](../sources/prs/sglang/PR-25524.md), [[MoE Refactor] Migrate flashinfer_cutedsl + DeepEP to MoeRunner](../sources/prs/sglang/PR-25525.md), [Use DeepGEMM BF16 for unquantized DeepEP LL MoE](../sources/prs/sglang/PR-25540.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [Use triton_attn as default vision attention on B300 (SM103)](../sources/prs/sglang/PR-25570.md), [[Benchmark] Add SGLANG_SIMULATE_UNIFORM_EXPERTS for balanced expert routing with dummy weights](../sources/prs/sglang/PR-25571.md), [Introduce SchedulerDPAttnAdapter to own DP-attention state](../sources/prs/sglang/PR-25611.md), [Move DP-attention adapter methods to SchedulerDPAttnAdapter](../sources/prs/sglang/PR-25612.md), [[SP] Fix runtime_max_tokens_per_rank for sequence parallelism](../sources/prs/sglang/PR-25685.md), [Add no_combine support to cutlass_moe_fp4](../sources/prs/sglang/PR-25688.md), [fix (jit kernel): elementwise activation C++ error](../sources/prs/sglang/PR-25695.md), [[diffusion] Fix GLM-Image /v1/images/edits support](../sources/prs/sglang/PR-25697.md), [[Codex] Remove stale DeepSeek V4 JIT kernels](../sources/prs/sglang/PR-25764.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Refactor] Pass PP start_layer via model constructor instead of forward_batch.token_to_kv_pool](../sources/prs/sglang/PR-25825.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Allow local cutlass directory to be used in sgl-kernel build](../sources/prs/sglang/PR-3037.md), [sync the upstream updates of flashinfer](../sources/prs/sglang/PR-3051.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [Apply sgl w8a8 fp8 kernel](../sources/prs/sglang/PR-3148.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [feat: support flashinfer mla attention for deepseek v3](../sources/prs/sglang/PR-3550.md), [update flashinfer-python](../sources/prs/sglang/PR-3557.md), [feat: support flashinfer mla with prefix cache](../sources/prs/sglang/PR-3643.md), [add control for cutlass fp8 blockwise gemm](../sources/prs/sglang/PR-3727.md), [Feature DeepSeek V3/R1 INT8 Quantization (block-wise)](../sources/prs/sglang/PR-3730.md), [[Feature] DeepSeek V3/R1 INT8 Quantization (channel-wise) ](../sources/prs/sglang/PR-3888.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [upgrade flashinfer v0.2.2.post1](../sources/prs/sglang/PR-3934.md), [[tools] add fp8 max/min constant in utils](../sources/prs/sglang/PR-3959.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [Hierarchical Caching supports MLA](../sources/prs/sglang/PR-4009.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [Support overlapping two batches](../sources/prs/sglang/PR-4068.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [linear support deepgemm](../sources/prs/sglang/PR-4199.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [Clean up fp8 support](../sources/prs/sglang/PR-4230.md), [[Feature] Integrate DeepEP into SGLang](../sources/prs/sglang/PR-4232.md), [upgrade flashinfer 0.2.3](../sources/prs/sglang/PR-4317.md), [[FIX] fix incorrect output when enable both deepgemm and torch compile](../sources/prs/sglang/PR-4359.md), [[ROCm] fix dtype](../sources/prs/sglang/PR-4510.md), [Create col-major and tma-aligned x_scale for deep_gemm.gemm_fp8_fp8_bf16_nt](../sources/prs/sglang/PR-4515.md), [Add deepseek style fused moe group gate selection kernel](../sources/prs/sglang/PR-4530.md), [[Fix] Fix raw_bs bug when using flashinfer mla and eagle](../sources/prs/sglang/PR-4557.md), [avoid cudaStreamSynchronize in DeepSeekV2AttentionMLA](../sources/prs/sglang/PR-4577.md), [[quantization] fix channelwise conversion with scalar weight scale](../sources/prs/sglang/PR-4596.md), [Set deepgemm to the default value in the hopper architecture.](../sources/prs/sglang/PR-4613.md), [Optimize Permute Kernel in DeepEP](../sources/prs/sglang/PR-4643.md), [Fix loading KV quantization scale; Enable modelopt kv cache](../sources/prs/sglang/PR-4686.md), [[Model] Adding Qwen3 and Qwen3MoE](../sources/prs/sglang/PR-4693.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [[Feature] Support DeepEP Low Latency](../sources/prs/sglang/PR-4767.md), [Support (1 <= dp < tp) in the dp attention in DeepEP](../sources/prs/sglang/PR-4770.md), [Introduce moe_dense_tp_size to fix dense layer errors in DeepSeek V3 + 4x8xH100](../sources/prs/sglang/PR-4836.md), [Feat/support encoder model (like bert)](../sources/prs/sglang/PR-4887.md), [Add DeepSeek V3/R1 shared experts fusion](../sources/prs/sglang/PR-4918.md), [[Fix] DeepEP Compatibility with Low Latency](../sources/prs/sglang/PR-5068.md), [reduce moe_align_block_size_kernel small batch mode overhead](../sources/prs/sglang/PR-5086.md), [Support MHA with chunked prefix cache for DeepSeek chunked prefill](../sources/prs/sglang/PR-5113.md), [Blackwell Cutlass MLA kernel](../sources/prs/sglang/PR-5142.md), [Add optimized native kernels in sgl-kernel](../sources/prs/sglang/PR-5150.md), [feat: add DeepGEMM build warning](../sources/prs/sglang/PR-5176.md), [feat: use fa3 mla by default on hopper](../sources/prs/sglang/PR-5210.md), [[Fix] Turn off DeepGEMM by default](../sources/prs/sglang/PR-5263.md), [[1/2] Add FP8 Blockscale MoE CUTLASS kernel for Blackwell](../sources/prs/sglang/PR-5281.md), [fix: use deepgemm only on hopper](../sources/prs/sglang/PR-5310.md), [Add Speculative Decoding Eagle3 topk > 1](../sources/prs/sglang/PR-5318.md), [fix: determine if flashinfer is installed](../sources/prs/sglang/PR-5336.md), [Fix DeepGEMM masked cannot be run on groups not being multiple or 4](../sources/prs/sglang/PR-5340.md), [[perf] experimental enhance fp8 per-tensor quant](../sources/prs/sglang/PR-5370.md), [apply fused moe gate in ds v3/r1](../sources/prs/sglang/PR-5371.md), [[PD Bug] fix MLA get_contiguous_buf_infos error](../sources/prs/sglang/PR-5384.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[PD] Fix dynamic port support and MLA buffer for Mooncake](../sources/prs/sglang/PR-5415.md), [[Feat] upgrade pytorch2.6](../sources/prs/sglang/PR-5417.md), [BLackwell cutlass mla: Add check for bad page size/block num combinations](../sources/prs/sglang/PR-5431.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Avoid computing lse in Ragged Prefill when there's no prefix.](../sources/prs/sglang/PR-5476.md), [Fix sampler nan check when calling top_k_top_p_sampling_from_probs](../sources/prs/sglang/PR-5546.md), [[feature] enable pre compile jit deep_gemm](../sources/prs/sglang/PR-5580.md), [[fix] force use deepgemm in compile_deep_gemm](../sources/prs/sglang/PR-5618.md), [ DeepEP normal support deepgemm-contiguous](../sources/prs/sglang/PR-5626.md), [Turn on DeepGemm By Default and Update Doc](../sources/prs/sglang/PR-5628.md), [[perf] dsv3 bmm fallback to bf16](../sources/prs/sglang/PR-5662.md), [[2/2] Add python wrapper for CUTLASS FP8 Blockscale MoE Kernel. ](../sources/prs/sglang/PR-5694.md), [[PP] Add pipeline parallelism](../sources/prs/sglang/PR-5724.md), [Fuse MLA set kv cache kernel](../sources/prs/sglang/PR-5748.md), [opt flashinfer mla cat](../sources/prs/sglang/PR-5822.md), [Cutlass MLA decode - fix dtype error](../sources/prs/sglang/PR-5868.md), [[Fix] Fix a bug for flashmla to run R1 model](../sources/prs/sglang/PR-5875.md), [Improve dp attention port assignment scheme](../sources/prs/sglang/PR-5889.md), [[qwen3] support qwen3 ep moe](../sources/prs/sglang/PR-5917.md), [[Feat] Enable PDL automatically on Hopper architecture](../sources/prs/sglang/PR-5981.md), [KV‑Cache (MHA, MLA): add missing start_layer / end_layer fields to MHATokenToKVPoolHost and MLATokenToKVPoolHost](../sources/prs/sglang/PR-6016.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [feat: add dp attention support for Qwen 2/3 MoE models, fixes #6088](../sources/prs/sglang/PR-6121.md), [Reduce MoE memory usage](../sources/prs/sglang/PR-6147.md), [enable auto-round quantization model](../sources/prs/sglang/PR-6226.md), [Enable FlashInfer support encoder models and add head_dim padding workaround](../sources/prs/sglang/PR-6230.md), [fix: fix MLA for ShardedModelLoader/RemoteModelLoader](../sources/prs/sglang/PR-6287.md), [[Fix] Improve dependencies for Blackwell image](../sources/prs/sglang/PR-6334.md), [reduce torch.zeros overhead in moe align block size kernel](../sources/prs/sglang/PR-6369.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [Add fp8 fused_experts kernel for CPU in sgl-kernel and add UT](../sources/prs/sglang/PR-6404.md), [Fix bug of deepseek-v3 under DP+EP mode with large batchsize/seqlen](../sources/prs/sglang/PR-6449.md), [Fix topk inference performance reduce](../sources/prs/sglang/PR-6474.md), [[Feature] Support Flashinfer fp8 blockwise GEMM kernel on Blackwell](../sources/prs/sglang/PR-6479.md), [qwen3moe support two batch overlap](../sources/prs/sglang/PR-6598.md), [Refine pre_reorder_triton_kernel slightly to improve performance](../sources/prs/sglang/PR-6627.md), [[CPU] [BF16] Call fused_experts_cpu, weight_packed_linear and bmm_cpu kernel in DeepSeek model](../sources/prs/sglang/PR-6641.md), [Fix DeepEP error in Qwen 3 MoE models](../sources/prs/sglang/PR-6673.md), [[EP] Add cuda kernel for moe_ep_pre_reorder](../sources/prs/sglang/PR-6699.md), [Fix PP for Qwen3 MoE](../sources/prs/sglang/PR-6709.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [[CPU] add optimizations for INT8 and FP8 DeepSeek](../sources/prs/sglang/PR-6769.md), [[CPU] support the case where num_attention_heads or intermediate_size is not divisible by the TP size](../sources/prs/sglang/PR-6771.md), [Support token-level quantization for EP MoE](../sources/prs/sglang/PR-6782.md), [[PD] Add different TP sizes support for no-MLA models](../sources/prs/sglang/PR-6793.md), [Correctly abort the failed grammar requests & Improve the handling of abort](../sources/prs/sglang/PR-6803.md), [feat: integrate deepgemm into EPMoE](../sources/prs/sglang/PR-6821.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [[EP] Add cuda kernel for moe_ep_post_reorder](../sources/prs/sglang/PR-6837.md), [Fix AWQ Dequant and Weight Loading of deepseek v2](../sources/prs/sglang/PR-6842.md), [[DeepseekR1-FP4] Add Support for nvidia/DeepSeekR1-FP4 model](../sources/prs/sglang/PR-6853.md), [Use deepgemm instead of triton for fused_qkv_a_proj_with_mqa](../sources/prs/sglang/PR-6890.md), [Add a CUDA kernel for fusing mapping and weighted sum for MoE.](../sources/prs/sglang/PR-6916.md), [[sgl-kernel] Add cuda kernel for moe_ep_silu_and_mul](../sources/prs/sglang/PR-6919.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [[sgl-kernel] update deepgemm](../sources/prs/sglang/PR-6942.md), [chore: upgrade flashinfer v0.2.6.post1 jit](../sources/prs/sglang/PR-6958.md), [Fuse routed scaling factor in deepseek](../sources/prs/sglang/PR-6970.md), [Fix cutlass MLA gets almost zero accuracy](../sources/prs/sglang/PR-6998.md), [Fix torchvision version for Blackwell](../sources/prs/sglang/PR-7015.md), [Update default settings for blackwell](../sources/prs/sglang/PR-7023.md), [Clean up server_args.py](../sources/prs/sglang/PR-7037.md), [Fix positional argument](../sources/prs/sglang/PR-7093.md), [feat: update blackwell setup](../sources/prs/sglang/PR-7119.md), [fix amd EP MoE FP8 issue](../sources/prs/sglang/PR-7125.md), [Enable ModelOpt Llama4 fp8 checkpoint deployment in SGLang](../sources/prs/sglang/PR-7129.md), [Enable native ModelOpt quantization support (1/3) ](../sources/prs/sglang/PR-7149.md), [[amd] Opt dsv3 moe](../sources/prs/sglang/PR-7160.md), [Fix Deepseek R1 0528 FP4 tensor name mismatch issue during weights loading.](../sources/prs/sglang/PR-7164.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Tiny let DeepGEMM scale checks cover more cases](../sources/prs/sglang/PR-7182.md), [chore: upgrade sgl-kernel v0.1.8.post2](../sources/prs/sglang/PR-7186.md), [[AMD] Fail gracefully when AITER is unavailable gfx90a GPUs](../sources/prs/sglang/PR-7187.md), [Fix a minor bug related to DeepGEMM upgrade](../sources/prs/sglang/PR-7191.md), [Fix error when disabling new DeepGEMM](../sources/prs/sglang/PR-7198.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [feat: support compatibility between MTP and two-batch-overlap](../sources/prs/sglang/PR-7225.md), [Minor style and doc fix](../sources/prs/sglang/PR-7228.md), [[fix] fix DeepGEMM blackwell input quant & ut & fix style and log](../sources/prs/sglang/PR-7247.md), [[AMD] add aiter fused moe in DeepEP path](../sources/prs/sglang/PR-7268.md), [Support NVFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-7302.md), [Let EP prefill support new DeepGEMM](../sources/prs/sglang/PR-7310.md), [Kernels for efficient KV cache IO](../sources/prs/sglang/PR-7313.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Fix MTP with Deepseek R1 Fp4](../sources/prs/sglang/PR-7376.md), [Quick fix for DeepGemm requant to also cover MTP.](../sources/prs/sglang/PR-7378.md), [Fix torch compile run](../sources/prs/sglang/PR-7391.md), [[AMD][Quantization] Add `int4fp8_moe` online quantization on ROCm](../sources/prs/sglang/PR-7392.md), [Fix CPU offloading for MLA memory pool](../sources/prs/sglang/PR-7409.md), [Fuse sorted_token_ids padding to moe_align_block_size kernel](../sources/prs/sglang/PR-7437.md), [Support non-contiguous query input for extend/decode attention](../sources/prs/sglang/PR-7462.md), [Add Tencent HunYuanMoEV1 model support](../sources/prs/sglang/PR-7549.md), [[b200] support trt-llm allreduce fuse rms_norm_add kernel](../sources/prs/sglang/PR-7621.md), [Add dsv3 router gemm kernel](../sources/prs/sglang/PR-7627.md), [Add dsv3 fused a gemm to sgl-kernel](../sources/prs/sglang/PR-7630.md), [[Feature] Layer-wise Prefill](../sources/prs/sglang/PR-7634.md), [Apply dsv3_fused_a_gemm kernel](../sources/prs/sglang/PR-7635.md), [[Feature] CUDA Green Context Support](../sources/prs/sglang/PR-7649.md), [chore: upgrade flashinfer v0.2.7 jit](../sources/prs/sglang/PR-7663.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [Integrate triton moe kernel](../sources/prs/sglang/PR-7689.md), [feat: support DeepSeek-R1-W4AFP8 model with ep-moe mode](../sources/prs/sglang/PR-7762.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [Qwen FP8/NVFP4 ModelOPT Quantization support](../sources/prs/sglang/PR-7912.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [[fix] fix modelopt fp4 on b200](../sources/prs/sglang/PR-8195.md), [[1/N]Support DeepSeek-R1 w4a8 normal deepep](../sources/prs/sglang/PR-8247.md), [Support triton kernels v3.4.0 for fused_moe](../sources/prs/sglang/PR-8258.md), [[2/N]Support DeepSeek-R1 w4a8 low latency deepep](../sources/prs/sglang/PR-8464.md), [Update cutlass_moe.py](../sources/prs/sglang/PR-8535.md), [Update cutlass_moe.py](../sources/prs/sglang/PR-8545.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [TRTLLM-MLA FP8 path](../sources/prs/sglang/PR-8638.md), [feat: support cutlass_moe_fp8 kernel for fusedmoe in sm90](../sources/prs/sglang/PR-8678.md), [fuse allreduce and residual_rmsnorm](../sources/prs/sglang/PR-8731.md), [Fix mismatch between padded_scales shape and reshape dimensions in modelopt quantization](../sources/prs/sglang/PR-8766.md), [feat: add trtllm-gen mha from direct call](../sources/prs/sglang/PR-8782.md), [[Perf] Auto enable best flashinfer mxfp4 kernel in b200](../sources/prs/sglang/PR-8898.md), [Fix hopper launch gpt-oss model illegal memory](../sources/prs/sglang/PR-8908.md), [[NVIDIA] Fix missing `get_col_major_tma_aligned_tensor` for Blackwell deepgemm in EpMoE](../sources/prs/sglang/PR-8955.md), [optimize: reduce shulffle and quantization overhead in cutlass_moe sm90](../sources/prs/sglang/PR-8962.md), [[fix] fix enable_pdl for blackwell](../sources/prs/sglang/PR-9011.md), [[sgl-kernel] Support FlashInfer top_k_top_p_sampling_from_logits](../sources/prs/sglang/PR-9060.md), [Faster weight processing (trtllm-gen moe nvfp4)](../sources/prs/sglang/PR-9162.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [Support trtllm_allreduce_fusion in flashinfer for cuda<12.8](../sources/prs/sglang/PR-9339.md), [Fix FP4 inference corruption issue in glm4.5-air model](../sources/prs/sglang/PR-9346.md), [Support DP attention with GPT-OSS](../sources/prs/sglang/PR-9359.md), [[fix] Fix mxfp4 triton MoE tp bug](../sources/prs/sglang/PR-9473.md), [Optimize moe_sum_reduce_kernel](../sources/prs/sglang/PR-9477.md), [fix: blackwell dsv3 fp8 issue temporary solution](../sources/prs/sglang/PR-9530.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [Tiny fix wrong comments](../sources/prs/sglang/PR-9589.md), [Single Batch Overlap for MoE Models](../sources/prs/sglang/PR-9660.md), [fix mooncake store mla zero copy meta](../sources/prs/sglang/PR-9678.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[ModelOpt] Fix Weight Loading for DSR1-FP4 Quantization](../sources/prs/sglang/PR-9712.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [[Model] Support Meituan LongCat-Flash && LongCat-Flash-MTP](../sources/prs/sglang/PR-9824.md), [perf: Avoid unnecessary data type conversions for DeepSeek-V3 on Blackwell](../sources/prs/sglang/PR-9834.md), [support using fa4 on deepseek on blackwell](../sources/prs/sglang/PR-9928.md), [[Fix] DeepSeek EP accuracy issue on B200 GPUs](../sources/prs/sglang/PR-9946.md), [Enable native ModelOpt quantization support (2/3)](../sources/prs/sglang/PR-9991.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [[BugFix] Fix Hopper TMA lowering without warp specialization](../sources/prs/tilelang/PR-1840.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] Add T.copy_cluster to support TMA multicast and SM-to-SM cluster copy](../sources/prs/tilelang/PR-1908.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Bugfix] Fix CuTeDSL autotune cache invalid ELF header (#1967)](../sources/prs/tilelang/PR-1972.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[CUDA] Improve int4 GEMM lowering and packed codegen support](../sources/prs/tilelang/PR-2073.md), [[TMA] Support FP4 TensorMap TMA copies](../sources/prs/tilelang/PR-2107.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[Perf] Enable fast math in sparse MLA example](../sources/prs/tilelang/PR-2219.md), [[Core] Support fully transparent sleep mode](../sources/prs/vllm/PR-11743.md), [[ROCm][MoE] moe tuning support for rocm](../sources/prs/vllm/PR-12049.md), [[Kernel] Flash Attention 3 Support](../sources/prs/vllm/PR-12093.md), [Add: Support for Sparse24Bitmask Compressed Models](../sources/prs/vllm/PR-12097.md), [[Hardware][Gaudi][Feature] Enable Dynamic MoE for Mixtral](../sources/prs/vllm/PR-12303.md), [[Core] Optimizing cross-attention `QKVParallelLinear` computation](../sources/prs/vllm/PR-12325.md), [[Bugfix] Disable w16a16 2of4 sparse CompressedTensors24](../sources/prs/vllm/PR-12417.md), [[Misc][MoE] add Deepseek-V3 moe tuning support](../sources/prs/vllm/PR-12558.md), [Expert Parallelism (EP) Support for DeepSeek Models](../sources/prs/vllm/PR-12583.md), [Apply torch.compile to fused_moe/grouped_topk](../sources/prs/vllm/PR-12637.md), [Disable chunked prefill and/or prefix caching when MLA is enabled ](../sources/prs/vllm/PR-12642.md), [[AMD][ROCm] Enable DeepSeek model on ROCm](../sources/prs/vllm/PR-12662.md), [Squelch MLA warning for Compressed-Tensors Models](../sources/prs/vllm/PR-12704.md), [[VLM] Add MLA with pure RoPE support for deepseek-vl2 models](../sources/prs/vllm/PR-12729.md), [[Misc] Update w2 scale loading for GPTQMarlinMoE](../sources/prs/vllm/PR-12757.md), [[Bugfix] Better FP8 supported defaults](../sources/prs/vllm/PR-12796.md), [[Attention] Use FA3 for MLA on Hopper](../sources/prs/vllm/PR-12807.md), [[Model] Deepseek GGUF support ](../sources/prs/vllm/PR-13167.md), [Expand MLA to support most types of quantization](../sources/prs/vllm/PR-13181.md), [[Quant][Perf] Use moe_wna16 kernel by default for MoEs with many experts](../sources/prs/vllm/PR-13236.md), [[Bugfix] Massage MLA's usage of flash attn for RoCM](../sources/prs/vllm/PR-13310.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[Bugfix] Fix max_num_batched_tokens for MLA](../sources/prs/vllm/PR-13620.md), [[Kernel] Optimize moe intermediate_cache usage](../sources/prs/vllm/PR-13625.md), [[ROCM] fix native attention function call](../sources/prs/vllm/PR-13650.md), [[BugFix] Illegal memory access for MoE On H20](../sources/prs/vllm/PR-13693.md), [[Bugfix] Support MLA for CompressedTensorsWNA16](../sources/prs/vllm/PR-13725.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [Fix CompressedTensorsWNA16MoE with grouped scales](../sources/prs/vllm/PR-13769.md), [Fix precommit fail in fused_moe intermediate_cache2 chunking](../sources/prs/vllm/PR-13772.md), [[Bugfix][Quantization] Fix FP8 + EP](../sources/prs/vllm/PR-13784.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [Fix mla prefill context performance](../sources/prs/vllm/PR-13897.md), [[Misc] Print FusedMoE detail info](../sources/prs/vllm/PR-13974.md), [[core] moe fp8 block quant tuning support](../sources/prs/vllm/PR-14068.md), [[V1] Implement sliding window attention in kv_cache_manager](../sources/prs/vllm/PR-14097.md), [[v1] Add comments to the new ragged paged attention Pallas kernel](../sources/prs/vllm/PR-14155.md), [[V1][TPU] TPU multimodal model support for ragged attention](../sources/prs/vllm/PR-14158.md), [[V1][TPU] Support V1 Sampler for ragged attention](../sources/prs/vllm/PR-14227.md), [[Hardware] Update the flash attn tag to support Blackwell](../sources/prs/vllm/PR-14244.md), [[BugFix] Fix prefix caching V0 MLA](../sources/prs/vllm/PR-14255.md), [[Misc] Add Qwen2MoeForCausalLM moe tuning support ](../sources/prs/vllm/PR-14276.md), [[Hardware][TPU]Enable ragged paged attention kernel and resolve recompilation issue](../sources/prs/vllm/PR-14310.md), [[Bug] Fix Attention when ignored in by quant_method](../sources/prs/vllm/PR-14313.md), [[ROCm] Enable chunked prefill/paged attention in MLA on ROCm](../sources/prs/vllm/PR-14316.md), [[Perf] Reduce MLA CPU overheads in V1](../sources/prs/vllm/PR-14384.md), [[ROCm][Kernel] MoE weights padding](../sources/prs/vllm/PR-14454.md), [[Bugfix] DeepSeek Accuracy](../sources/prs/vllm/PR-14476.md), [[Perf] Improve MLA on V1](../sources/prs/vllm/PR-14540.md), [[Quantization][FP8] Adding support for fp8 gemm layer input in fp8](../sources/prs/vllm/PR-14578.md), [[Model] Add support for Gemma 3](../sources/prs/vllm/PR-14660.md), [[Bugfix][IPEX] Add `VLLM_CPU_MOE_PREPACK` to allow disabling MoE prepack when CPU does not support it](../sources/prs/vllm/PR-14681.md), [[Kernel][CPU] CPU MLA](../sources/prs/vllm/PR-14744.md), [[Attention] MLA get rid of materialization](../sources/prs/vllm/PR-14770.md), [[Attention] Get rid of mla cache alignment](../sources/prs/vllm/PR-14842.md), [[V1][BugFix] Detect interleaved sliding window attention](../sources/prs/vllm/PR-14896.md), [[V1] Default MLA to V1](../sources/prs/vllm/PR-14921.md), [[FEAT][ROCm] Integrate Fused MoE Kernels from AITER](../sources/prs/vllm/PR-14967.md), [[FEAT] [ROCm]: Add AITER Block-Scaled GEMM Feature](../sources/prs/vllm/PR-14968.md), [[FEAT][ROCm] Integrate Paged Attention Kernel from AITER](../sources/prs/vllm/PR-15001.md), [[Bugfix] Fix incorrect qwen2.5-vl attention mask pre-computation](../sources/prs/vllm/PR-15200.md), [[Bugfix] Fix use_cascade_attention handling for Alibi-based models on vllm/v1](../sources/prs/vllm/PR-15211.md), [[Misc] Add attention mask pre-computation optimization back to Qwen2.5-VL](../sources/prs/vllm/PR-15273.md), [[Model] Add Qwen3 and Qwen3MoE](../sources/prs/vllm/PR-15289.md), [Fix non-contiguous input passed to Marlin kernel](../sources/prs/vllm/PR-15319.md), [[FEAT] [ROCm] Add AITER int8 scaled gemm kernel](../sources/prs/vllm/PR-15433.md), [Use Cache Hinting for fused_moe kernel](../sources/prs/vllm/PR-15511.md), [[moe][quant] add weight name case for offset](../sources/prs/vllm/PR-15515.md), [[Quantization] Fp8 Channelwise Dynamic Per Token GroupedGEMM](../sources/prs/vllm/PR-15587.md), [[TPU] Support sliding window and logit soft capping in the paged attention kernel for TPU.](../sources/prs/vllm/PR-15732.md), [[V1] TPU - Fix fused MOE](../sources/prs/vllm/PR-15834.md), [[Bugfix] Fix cache block size calculation for CPU MLA](../sources/prs/vllm/PR-15848.md), [[FEAT][ROCm]: Support AITER MLA](../sources/prs/vllm/PR-15893.md), [[Hardware][Gaudi][BugFix] fix arguments of hpu fused moe](../sources/prs/vllm/PR-15945.md), [Add support to modelopt quantization of Mixtral model](../sources/prs/vllm/PR-15961.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[Kernel] Use moe_wna16 kernel for compressed tensors wna16 moe models](../sources/prs/vllm/PR-16038.md), [[Model] use AutoWeightsLoader for phimoe,qwen2_moe,qwen3_moe](../sources/prs/vllm/PR-16203.md), [[Hardware][AMD] Improve OAM device ID + llama4 Maverick MOE tuning](../sources/prs/vllm/PR-16263.md), [[Llama4] Enable attention temperature tuning by default for long context (>32k)](../sources/prs/vllm/PR-16439.md), [[MLA] Simplification to batch P/D reordering](../sources/prs/vllm/PR-16673.md), [[ROCM] enable aiter fused moe kernel for llama4 bf16 checkpoints](../sources/prs/vllm/PR-16674.md), [[ROCm] Add aiter tkw1 kernel for Llama4 fp8](../sources/prs/vllm/PR-16727.md), [Support W8A8 INT8 MoE for compressed-tensors](../sources/prs/vllm/PR-16745.md), [[FEAT] [ROCm]: AITER Fused MOE V1 Support](../sources/prs/vllm/PR-16752.md), [[Bugfix] Fix moe weight losing all extra attrs after `process_weights_after_loading`.](../sources/prs/vllm/PR-16854.md), [[Bugfix] Add contiguous call inside rope kernel wrapper](../sources/prs/vllm/PR-17091.md), [[FEAT] [ROCm]: Add AITER CK 2 Stages MoE support](../sources/prs/vllm/PR-17110.md), [[Bugfix] gemma[2,3] interleaved attention when sliding window is disabled](../sources/prs/vllm/PR-17180.md), [[Bugfix] Get a specific type of layer from forward context](../sources/prs/vllm/PR-17222.md), [[BugFix] Fix vllm_flash_attn install issues](../sources/prs/vllm/PR-17267.md), [[BugFix] Fix cascade attention - RuntimeError: scheduler_metadata must have shape (metadata_size)](../sources/prs/vllm/PR-17283.md), [[v1] AttentionMetadata for each layer](../sources/prs/vllm/PR-17394.md), [Fix noisy warning for uncalibrated q_scale/p_scale](../sources/prs/vllm/PR-17414.md), [[v1] Pass BlockTable and KVCacheSpec to AttentionMetadataBuilders](../sources/prs/vllm/PR-17483.md), [[BugFix] Fix mla cpu - missing 3 required positional arguments](../sources/prs/vllm/PR-17494.md), [[FEAT][ROCm]: Support AITER MLA on V1 Engine](../sources/prs/vllm/PR-17523.md), [[Bugfix][ROCm] Fix AITER MLA V1](../sources/prs/vllm/PR-17880.md), [[BugFix][AMD] Compatible patch for AITER lib after 04/20](../sources/prs/vllm/PR-17912.md), [[Misc] Add compressed-tensors NVFP4A16 emulation support](../sources/prs/vllm/PR-17914.md), [use ceil_div in cutlass block scaling shape check](../sources/prs/vllm/PR-17918.md), [[v1] Support multiple KV cache groups in GPU model runner](../sources/prs/vllm/PR-17945.md), [[BUG] [ROCm] [MLA] Fix variable name bug due to change in variable name in PR #17483](../sources/prs/vllm/PR-17961.md), [Use NVFP4 Marlin for CompressedTensorsW4A16Fp4](../sources/prs/vllm/PR-18000.md), [[Quantization] Add compressed-tensors NVFP4 support](../sources/prs/vllm/PR-18312.md), [[Model]: Fused MoE for nomic-embed-text-v2-moe](../sources/prs/vllm/PR-18321.md), [[Feature] Expert Parallelism Load Balancer (EPLB)](../sources/prs/vllm/PR-18343.md), [[Bug] Fix moe_sum signature](../sources/prs/vllm/PR-18440.md), [[V1] Support `LLM.apply_model`](../sources/prs/vllm/PR-18465.md), [[Hardware][AMD] integrate aiter chunked prefill into vllm](../sources/prs/vllm/PR-18596.md), [[P/D] Heterogeneous TP](../sources/prs/vllm/PR-18833.md), [[ROCm] [AITER] [Bugfix] Patch for AITER commit `648764942e552a8bb5fe16026703716a81f05374`](../sources/prs/vllm/PR-18990.md), [[Kernel] Support deep_gemm for linear methods](../sources/prs/vllm/PR-19085.md), [[Kernel] Apply torch.Tag.needs_fixed_stride_order only for torch==2.6.0](../sources/prs/vllm/PR-19346.md), [[Core] Support Local Chunked Attention for Hybrid KV Cache](../sources/prs/vllm/PR-19351.md), [[Kernels] Use empty for modular MoE workspaces](../sources/prs/vllm/PR-19667.md), [[Feature] Integrate new deepgemm](../sources/prs/vllm/PR-19820.md), [[Bugfix] Enable PP with AITER+V1](../sources/prs/vllm/PR-19822.md), [[Quantization] Add compressed-tensors emulations support for NVFP4](../sources/prs/vllm/PR-19879.md), [[Quantization] Add compressed-tensors NVFP4 MoE Support](../sources/prs/vllm/PR-19990.md), [Enable V1 for Hybrid SSM/Attention Models](../sources/prs/vllm/PR-20016.md), [[Attention] MLA - Flashinfer Ragged Prefill](../sources/prs/vllm/PR-20034.md), [Add ModelOpt Qwen3 nvfp4 support](../sources/prs/vllm/PR-20101.md), [[Bugfix] Mark 'hidden_states' as mutable in moe_forward registration.](../sources/prs/vllm/PR-20152.md), [[Bugfix] Fix Maverick correctness by filling zero to cache space in cutlass_moe](../sources/prs/vllm/PR-20167.md), [[Nixl] Heterogeneous TP support FlashInfer](../sources/prs/vllm/PR-20189.md), [[V1] [ROCm] Enable EP with AITER Fused MoE](../sources/prs/vllm/PR-20270.md), [Support Llama 4 for cutlass_moe_fp4](../sources/prs/vllm/PR-20453.md), [Support Llama 4 for fused_marlin_moe](../sources/prs/vllm/PR-20457.md), [[Perf] Reuse workspace for FP8+FP4 Marlin MoE](../sources/prs/vllm/PR-20500.md), [[Bugfix] Fix missing per_act_token parameter in compressed_tensors_moe](../sources/prs/vllm/PR-20509.md), [[feat] enable SM100 CUTLASS block scaled group gemm for smaller batch sizes](../sources/prs/vllm/PR-20640.md), [Integration SM100 FlashInfer fused allreduce RMSNorm](../sources/prs/vllm/PR-20691.md), [GLM-4.5 Model Support](../sources/prs/vllm/PR-20736.md), [[v1][core] Support for attention free models](../sources/prs/vllm/PR-20811.md), [[Feature][EPLB] Add eplb support for Qwen3](../sources/prs/vllm/PR-20815.md), [[Bugfix] Fix a couple PPLX+CUTLASS MoE bugs](../sources/prs/vllm/PR-20825.md), [[Bug] Fix DeepGemm for EP low latency case](../sources/prs/vllm/PR-20833.md), [[Model] Pooling models default to using chunked prefill & prefix caching if supported.](../sources/prs/vllm/PR-20930.md), [[Misc] Qwen MoE model supports LoRA](../sources/prs/vllm/PR-20932.md), [[Bugfix] Switch bailout logic for kv-cache-dtype with SM100 Flashinfer](../sources/prs/vllm/PR-20934.md), [Fall back if flashinfer comm module not found](../sources/prs/vllm/PR-20936.md), [[Bugfix] Fix Mistral3 support on SM100/SM120](../sources/prs/vllm/PR-20998.md), [Add FlashInfer allreduce RMSNorm Quant fusion](../sources/prs/vllm/PR-21069.md), [[Bugfix] Voxtral on Blackwell GPUs (RTX 50 series)](../sources/prs/vllm/PR-21077.md), [[Bugfix] Allocate less memory in non-batched CUTLASS MoE](../sources/prs/vllm/PR-21121.md), [[Attention] Optimize FlashInfer MetadataBuilder Build call](../sources/prs/vllm/PR-21137.md), [[Attention][DBO] Add support for "splitting" the CommonAttentionMetadata](../sources/prs/vllm/PR-21153.md), [[Feature][OCP MX] Support mxfp6 and mixed mxfp6-mxfp4](../sources/prs/vllm/PR-21166.md), [[Bug] DeepGemm: Fix TypeError: per_block_cast_to_fp8() missing 1 required positional argument: 'use_ue8m0' for SM100](../sources/prs/vllm/PR-21187.md), [Support encoder-only models without KV-Cache](../sources/prs/vllm/PR-21270.md), [Fix Flashinfer Allreduce+Norm enable disable calculation based on `fi_allreduce_fusion_max_token_num`](../sources/prs/vllm/PR-21325.md), [Support Tensorrt-LLM MoE fp4 for low-latency](../sources/prs/vllm/PR-21331.md), [[TPU][Bugfix] fix moe layer](../sources/prs/vllm/PR-21340.md), [[Quantization] Enable BNB support for more MoE models](../sources/prs/vllm/PR-21370.md), [Update flashinfer CUTLASS NVFP4 MoE Kernel to use per expert global scaling factor](../sources/prs/vllm/PR-21408.md), [[NVIDIA] Explicitly disable shuffled weights for flashinfer blockscale moe fp8 kernels](../sources/prs/vllm/PR-21411.md), [Updates to Flex + VLLm integration](../sources/prs/vllm/PR-21416.md), [[V1] Fix local chunked attention always disabled](../sources/prs/vllm/PR-21419.md), [[BugFix] Fix shared storage connector load kv only load attention layer](../sources/prs/vllm/PR-21428.md), [update flashinfer to v0.2.9rc1](../sources/prs/vllm/PR-21485.md), [[MoE] More balanced expert sharding](../sources/prs/vllm/PR-21497.md), [[NVIDIA] Fix Llama4 Scout FP4 functionality issues](../sources/prs/vllm/PR-21499.md), [Enable 4bit bnb prequant MOE](../sources/prs/vllm/PR-21548.md), [[Attention] Support multiple attention metadata builders per kv_cache_spec + proper local attention no hybrid kv cache fix](../sources/prs/vllm/PR-21588.md), [Override attention metadata for fast prefill in some KV sharing setups](../sources/prs/vllm/PR-21590.md), [[Feature] Add Flashinfer MoE Support for Compressed Tensor NVFP4](../sources/prs/vllm/PR-21639.md), [[xpu]support moe models on XPU platform](../sources/prs/vllm/PR-21643.md), [support `torch.compile` for bailing moe](../sources/prs/vllm/PR-21664.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [feat: Add Support GPTQ Quantization MOE on ROCM vllm serve](../sources/prs/vllm/PR-21733.md), [[Logs] Change flashinfer sampler logs to once](../sources/prs/vllm/PR-21759.md), [[Perf] Disable chunked local attention by default with llama4](../sources/prs/vllm/PR-21761.md), [[Bugfix] Check NVIDIA artifactory is accessible before using flashinfer cubin kernels](../sources/prs/vllm/PR-21893.md), [[Qwen3] Enable dual-chunk-attention support for Qwen3 models.](../sources/prs/vllm/PR-21924.md), [[BUGFIX] KeyError 'layers.14.mlp.gate.g_idx' for Qwen3-MoE with GPTQ on ROCm](../sources/prs/vllm/PR-22017.md), [[NVIDIA] Support Flashinfer TRT-LLM Prefill Attention Kernel](../sources/prs/vllm/PR-22095.md), [[EPLB] Support ernie4.5-moe](../sources/prs/vllm/PR-22100.md), [[fix] fix correct assertion syntax error in attention utils.](../sources/prs/vllm/PR-22154.md), [[bugfix] fix blackwell deepep installation](../sources/prs/vllm/PR-22255.md), [[Bugfix] Fix MoE BNB version](../sources/prs/vllm/PR-22260.md), [Support encoder_only attention for FlexAttention](../sources/prs/vllm/PR-22273.md), [[Bugfix] Fix 3D input passed into cutlass_scaled_mm](../sources/prs/vllm/PR-22278.md), [[ROCm] Add attention sink to use_rocm_custom_paged_attention](../sources/prs/vllm/PR-22329.md), [[gpt-oss] flashinfer mxfp4](../sources/prs/vllm/PR-22339.md), [Update `flashinfer-python==0.2.10`](../sources/prs/vllm/PR-22389.md), [[Bug] Fix B200 DeepGEMM E8M0 Accuracy Issue](../sources/prs/vllm/PR-22399.md), [[bugfix] Fix Llama3/4 issues caused by FlashInfer 0.2.10](../sources/prs/vllm/PR-22426.md), [[Quantization]: Support compressed-tensors mixed-precision model loading](../sources/prs/vllm/PR-22468.md), [Fix Llama4 FlashInfer FP4 MoE issues](../sources/prs/vllm/PR-22511.md), [[Model] Add Ernie4.5 VL Model Support](../sources/prs/vllm/PR-22514.md), [Quantization: support FP4 quantized models on AMD CDNA2/CDNA3 GPUs](../sources/prs/vllm/PR-22527.md), [Fix torch version check for SM100 mxfp4 ](../sources/prs/vllm/PR-22535.md), [Upgrade FlashInfer to v0.2.11](../sources/prs/vllm/PR-22613.md), [[Bugfix] Fix ModernBert load & Enable sliding window attention for bidirectional attention.](../sources/prs/vllm/PR-22637.md), [Support multiple attention groups for KV sharing](../sources/prs/vllm/PR-22672.md), [[Quantization] Expand compressed-tensors MoE matching logic to support NFP4 + FP8 MoEs](../sources/prs/vllm/PR-22674.md), [Force TRTLLM attention for gpt-oss on SM100](../sources/prs/vllm/PR-22678.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [Fix GGUF loader for Qwen3 MoE.](../sources/prs/vllm/PR-22785.md), [[FIXBUG] Add return_success parameter to moe_wna16_weight_loader function](../sources/prs/vllm/PR-22797.md), [[Model] Modify the gate implementation of glm4_moe](../sources/prs/vllm/PR-22832.md), [[XPU] support data parallel for MoE models on XPU](../sources/prs/vllm/PR-22887.md), [[Kernel] Added flashinfer fp8 per-tensor gemms](../sources/prs/vllm/PR-22895.md), [[Bugfix] Fix DeepSeek MTP](../sources/prs/vllm/PR-22934.md), [Use Blackwell FlashInfer MXFP4 MoE by default if available ](../sources/prs/vllm/PR-23008.md), [[Bugfix gpt-oss] Fix float32 convert for flashinfer sink support](../sources/prs/vllm/PR-23016.md), [[Bugfix] fix qwen3 moe fp8 accuracy issue](../sources/prs/vllm/PR-23031.md), [[Core] Support weight_loader_v2 for `UnquantizedLinearMethod`](../sources/prs/vllm/PR-23036.md), [Add routed_scaling_factor to MoE grouped topk](../sources/prs/vllm/PR-23123.md), [[Bugfix] Fix accuracy issue when using flashinfer cutlass moe, TP=1 and modelopt.](../sources/prs/vllm/PR-23125.md), [Update to flashinfer-python==0.2.12 and disable AOT compile for non-release image](../sources/prs/vllm/PR-23129.md), [[Log] Warning Once for Cutlass MLA ](../sources/prs/vllm/PR-23137.md), [Fix nvfp4 swizzling](../sources/prs/vllm/PR-23140.md), [[CPU] add cpu fused moe pytorch native implementation](../sources/prs/vllm/PR-23146.md), [[XPU][Feature] fp8 online quantization support for XPU](../sources/prs/vllm/PR-23148.md), [Optimize input preparation for FlashInfer [2/N]](../sources/prs/vllm/PR-23174.md), [[Attention] Optimize make_local_attention_virtual_batches for Flash Attention](../sources/prs/vllm/PR-23185.md), [[Misc][qwen2_5_vl][torch.compile] Enable `supports_torch_compile` on generic nn.Module and demonstrate speedup on Qwen Vision model](../sources/prs/vllm/PR-23207.md), [[Core] Always use tensor cores for Flashinfer Decode Wrapper](../sources/prs/vllm/PR-23214.md), [[Perf] Small optimizations for silu_mul_fp8_quant_deep_gemm](../sources/prs/vllm/PR-23265.md), [[Kernels] Overlap shared experts with send/recv](../sources/prs/vllm/PR-23273.md), [[Bug] Fix R1 Accuracy 0 Bug](../sources/prs/vllm/PR-23294.md), [[Attention] Allow V1 flash_attn to support cross-attention](../sources/prs/vllm/PR-23297.md), [[Perf] Warmup FlashInfer attention during startup](../sources/prs/vllm/PR-23439.md), [[Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-23465.md), [fix(v1/kv_cache): resolve async KV transfer bug in cascade attention](../sources/prs/vllm/PR-23485.md), [[Bugfix] Fix Qwen3 MoE GPTQ inference](../sources/prs/vllm/PR-23490.md), [[V1][P/D]P2pNcclConnector supports flashinfer](../sources/prs/vllm/PR-23536.md), [Update Flashinfer to 0.2.14.post1](../sources/prs/vllm/PR-23537.md), [[Misc] Simplify FlashInfer attention metadata](../sources/prs/vllm/PR-23585.md), [DP/EP Support for gpt-oss with deepep-ht comm kernel on SM100](../sources/prs/vllm/PR-23608.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[Bugfix] Fix Marlin NVFP4 for modelopt](../sources/prs/vllm/PR-23659.md), [[v1] Add cross-attention KV cache support for encoder-decoder models](../sources/prs/vllm/PR-23664.md), [[Core/DBO][1/N] Add Dual-Batch Overlap mechanism to VLLM](../sources/prs/vllm/PR-23693.md), [[Kernel][tcgen05] nvfp4 fused tcgen05 moe](../sources/prs/vllm/PR-23696.md), [[FlashInfer] Cache hyper params in metadata builder](../sources/prs/vllm/PR-23732.md), [[BugFix][FlashInfer] Fix potential race condition for paged_kv_indptr_cpu](../sources/prs/vllm/PR-23737.md), [[Feat][EPLB] A novel static EPLB placement strategy for MoE models.](../sources/prs/vllm/PR-23745.md), [[Misc] add reorder_batch AttentionMetadataBuilder](../sources/prs/vllm/PR-23798.md), [[fix]: add Arm 4bit fused moe support](../sources/prs/vllm/PR-23809.md), [[Model][gpt-oss] Support DP+EP for GPT-OSS with FlashInfer trtllm-gen MoE](../sources/prs/vllm/PR-23819.md), [[BUGFIX ] fix undefined silu_and_mul_nvfp4_quant](../sources/prs/vllm/PR-23929.md), [Feature/vit attention unification# 23880](../sources/prs/vllm/PR-23978.md), [[BUGFIX] GPTQ quantization compatibility for Qwen3 MOE models (AutoGPTQ and AutoRound-GPTQ)](../sources/prs/vllm/PR-23994.md), [[PERF] Allreduce fusion. Support torch native matching. Tuning of the thresholds](../sources/prs/vllm/PR-24248.md), [[Transform] [Quantization] Add QuTLASS support to vLLM](../sources/prs/vllm/PR-24440.md), [[Feature] Disallow FlashMLA on Blackwell](../sources/prs/vllm/PR-24521.md), [[Performance] Move apply_w8a8_block_fp8_linear to an op class](../sources/prs/vllm/PR-24666.md), [[Model] Support Qwen3-VL Model Series](../sources/prs/vllm/PR-24727.md), [[Bug] Fix `is_flashmla_supported` Check Error](../sources/prs/vllm/PR-24774.md), [[DCP] Support Decode Context Parallel (DCP) for GQA with FlashAttention](../sources/prs/vllm/PR-24864.md), [[Attention][DCP] Support DCP with query length > 1 (MTP) with FA3](../sources/prs/vllm/PR-25049.md), [[Bug] Fix `returned_lse` not Defined issue](../sources/prs/vllm/PR-25106.md), [[ROCm] Small functional changes for gptoss](../sources/prs/vllm/PR-25201.md), [[BugFix] Fix MLA assert with CUTLASS MLA](../sources/prs/vllm/PR-25478.md), [feat: BF16 FlashInfer Fused Cutlass MOE for Hopper and Blackwell Expert Parallel](../sources/prs/vllm/PR-25503.md), [Enable Fbgemm NVFP4 on Dense models](../sources/prs/vllm/PR-25609.md), [[Flashinfer][gpt-oss] Support FP8-qkv Flashinfer TRTLLM Sinks Attention](../sources/prs/vllm/PR-25674.md), [[Bugfix] Enable padded FP4 quantization](../sources/prs/vllm/PR-25947.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Spec Decode] Enable efficient speculative decoding with FlashInfer-MLA](../sources/prs/vllm/PR-25984.md), [[Bugfix] Allow skipping MoE in NVFP4 (fix for MTP)](../sources/prs/vllm/PR-25987.md), [[NVIDIA] Add support for cudnn fp4 gemm via flashinfer](../sources/prs/vllm/PR-26107.md), [[ModelOpt] Load w13/w2_input_scale for all experts, nvfp4](../sources/prs/vllm/PR-26135.md), [[Performance] Dual stream execution of "shared_experts" and "selected_experts" inside FusedMoE](../sources/prs/vllm/PR-26440.md), [[Bugfix] Convert untraceable GroupShape to list for AMD impl](../sources/prs/vllm/PR-26535.md), [[ROCM] MoE fp4 CK kernel](../sources/prs/vllm/PR-26545.md), [support flashinfer_fp4 moe for 5090 gpu](../sources/prs/vllm/PR-26669.md), [[Bugfix] Fix gpt-oss w4a8 DP/EP on B200](../sources/prs/vllm/PR-26729.md), [Disable FlashInfer sampler by default](../sources/prs/vllm/PR-26859.md), [[Feature] Batch Invariant: Support DeepGEMM and Blackwell](../sources/prs/vllm/PR-27127.md), [[Kernels] Enable FlashInfer FP8 Blockscale on SM90 (for TEP DSR1)](../sources/prs/vllm/PR-27134.md), [[torch.compile] Enable silu_mul_fp8_quant fusion without custom ops enabled](../sources/prs/vllm/PR-27146.md), [[ROCM] Enable CompressedTensorsWNA16](../sources/prs/vllm/PR-27187.md), [[BUGFIX][ROCM] ViT FlashAttention on ROCm (no GFX9) and contiguous on qwen3vl ROCm TORCH_SDPA](../sources/prs/vllm/PR-27190.md), [Flashinfer_CUTLASS_MOE fuses quantization for TP](../sources/prs/vllm/PR-27223.md), [[Feature] Batch Invariant for R1 TP 8 on Blackwell](../sources/prs/vllm/PR-27229.md), [[Bugfix] Ensure calculated KV scales are applied in attention.](../sources/prs/vllm/PR-27232.md), [Bugfix: Cutlass FP8 FusedMoE bad scaling factors](../sources/prs/vllm/PR-27255.md), [Feature: Support Relu2 in FusedMoE fp8 cutlass path](../sources/prs/vllm/PR-27261.md), [[Misc] Make reorder batch also separate extends](../sources/prs/vllm/PR-27367.md), [[Performance] Support FP8 flashinfer TRTLLM MOE on Qwen3 and Qwen-3next](../sources/prs/vllm/PR-27492.md), [[Feature] Batch invariant torch.compile](../sources/prs/vllm/PR-27660.md), [[AMD] Use Decoupled Kernel Block Size to Support AITER MLA block_size=1](../sources/prs/vllm/PR-27715.md), [[Feature] Extend batch invariant torch.compile to B200](../sources/prs/vllm/PR-27856.md), [[Bug] Batch invariant: Fix flash attn MLA `RuntimeError: scheduler_metadata must have shape (metadata_size)`](../sources/prs/vllm/PR-27884.md), [[Performance][B200] Fix deepgemm prologue](../sources/prs/vllm/PR-27897.md), [[flashinfer][fix] do not check nvcc availability when using pre-downloaded cubins](../sources/prs/vllm/PR-27990.md), [[FlashInfer] Avoid FlashInfer block_size 16 + head_size 256 on blackwell](../sources/prs/vllm/PR-27994.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Model] Consolidate Deepseek-MoE implementation with DeepSeek-v2](../sources/prs/vllm/PR-28101.md), [[Mamba] - Consolidate Mambas Attention Logic](../sources/prs/vllm/PR-28133.md), [[flashinfer] fix FI all2all with FI cutlass moe](../sources/prs/vllm/PR-28166.md), [[Feature] Support recording expert indices for rollout router replay](../sources/prs/vllm/PR-28284.md), [[ROCm] Support for Whisper v1 with Aiter Unified Attention and Aiter Flash Attention](../sources/prs/vllm/PR-28376.md), [[Bugfix][EPLB] Disabled shared expert overlap when EPLB is enabled](../sources/prs/vllm/PR-28377.md), [[Bugfix] Fix SM100 gpt-oss regression due to faulty attn sink support](../sources/prs/vllm/PR-28561.md), [[Attention][Bugfix] Fix FA sink support](../sources/prs/vllm/PR-28660.md), [[Bugfix][Nixl] Fix kernel physical<>logical block_size issue ](../sources/prs/vllm/PR-28677.md), [[Performance] Reduce DeepGEMM N dim restriction from 128 to 64 multiplier ](../sources/prs/vllm/PR-28687.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [[Bugfix] Fix GPT-OSS on AMD after #28603](../sources/prs/vllm/PR-28816.md), [bugfix: correct attn output with base 2 or e](../sources/prs/vllm/PR-28840.md), [[Bugfix] Fix GPT-OSS AR+NORM fusion](../sources/prs/vllm/PR-28841.md), [[Bugfix] Make compressed-tensors MoEs respect ignored layers](../sources/prs/vllm/PR-28878.md), [Add TRTLLM MoE NVFP4 kernel to CompressedTensorsW4A4MoeMethod](../sources/prs/vllm/PR-28892.md), [[BugFix] Fix async-scheduling + FlashAttn MLA](../sources/prs/vllm/PR-28990.md), [[Feat] Support non-gated activations in NVFP4 modelopt path](../sources/prs/vllm/PR-29004.md), [[DeepSeek + LMCache Multiprocess] handle MLA for deepseek model + LMCache Multiprocess connector](../sources/prs/vllm/PR-29039.md), [[Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op)](../sources/prs/vllm/PR-29213.md), [[LoRA] Optimize 3D MoE logic](../sources/prs/vllm/PR-29222.md), [[Perf] Disable DeepGEMM MoE by default when TP=8 is used](../sources/prs/vllm/PR-29346.md), [Add unpermute-aware fused MoE path and small-batch fallback](../sources/prs/vllm/PR-29354.md), [[Bugfix] Fix grouped_topk pytorch impl when num_experts can't be grouped properly](../sources/prs/vllm/PR-29439.md), [[Attention] Cache attention metadata builds across hybrid KV-cache groups](../sources/prs/vllm/PR-29627.md), [[Bugfix] Defunctionalize TRTLLM AR+Norm op for avoiding extra clone kernel before it](../sources/prs/vllm/PR-29631.md), [[Attention] Make `split_decodes_and_prefills(..., require_uniform=True)` support padding](../sources/prs/vllm/PR-29644.md), [[perf] Use direct copy (broadcast) instead of cat for k_nope/k_pe in MLA prefill](../sources/prs/vllm/PR-29710.md), [[Quantization] Enable compressed-tensors AWQ for Turing GPU](../sources/prs/vllm/PR-29732.md), [[Bugfix] Fix mismatched nvfp4 gemm output shape](../sources/prs/vllm/PR-29742.md), [[MoE-FP8-modelopt] Add FlashInfer alignment padding for intermediate dimensions](../sources/prs/vllm/PR-29748.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[ROCm] [Fused Moe EP] Use binary expert mask for aiter fused moe kernel](../sources/prs/vllm/PR-29773.md), [[ROCm][MXFP4] Infer w4a4 quant method in rocm aiter fused moe](../sources/prs/vllm/PR-29775.md), [[EPLB] Support EPLB w/ NVFP4](../sources/prs/vllm/PR-29804.md), [[Bugfix][Model] Support LoRA on Qwen3 Output Embedding](../sources/prs/vllm/PR-29816.md), [[SpecDecode] Simplified alternative padded-speculation acceptance rate fix](../sources/prs/vllm/PR-29845.md), [[Quantization] fix: overflow with static per-tensor scaling](../sources/prs/vllm/PR-29867.md), [[Bugfix] Fix FP8 MoE LoRA](../sources/prs/vllm/PR-29890.md), [[BugFix] Fix DBO assert `assert B_block_table == B_q`](../sources/prs/vllm/PR-29933.md), [[moe] Use enable_chunking func (to support disabling chunking)](../sources/prs/vllm/PR-29935.md), [[moe] Allow disabling DP chunking](../sources/prs/vllm/PR-29936.md), [[Bugfix] Fix flashinfer ar+norm kernel not available issue](../sources/prs/vllm/PR-29960.md), [[ROCm] add fallback for aiter fp8 decode mla](../sources/prs/vllm/PR-30005.md), [[Quantization] Support Quark int4-fp8 w4a8 for MoE](../sources/prs/vllm/PR-30071.md), [[Model][Quantization] Restore MoE + GGUF models support (incl. Qwen3 MoE) by allowing Sideload Parameters](../sources/prs/vllm/PR-30116.md), [[Model][Quantization] Override HF defaults to GGUF ones (incl. Qwen3 MoE)](../sources/prs/vllm/PR-30118.md), [Nvidia ModelOpt workaround for issue 28072](../sources/prs/vllm/PR-30164.md), [Add latent MoE support](../sources/prs/vllm/PR-30203.md), [[Bugfix]: Fix glm46 awq marlin moe wna16 compatibility](../sources/prs/vllm/PR-30210.md), [[LoRA] Reduce the loading time of MoE LoRA](../sources/prs/vllm/PR-30243.md), [[Bugfix] Fix DeepGEMM after #29546 ](../sources/prs/vllm/PR-30267.md), [[Model][Quantization] Fix / Add GGUF support for Qwen2 MoE models](../sources/prs/vllm/PR-30307.md), [[bugfix][quantization] fix quark qwen3 kv_cache quantization](../sources/prs/vllm/PR-30308.md), [[fix] fix SM check for Flashinfer TRTLLM MOE](../sources/prs/vllm/PR-30314.md), [[Bugfix] Fix fp8 DeepGemm compilation issues](../sources/prs/vllm/PR-30336.md), [[BugFix] Fix `AttributeError: 'MergedColumnParallelLinear' object has no attribute 'weight_scale'`](../sources/prs/vllm/PR-30399.md), [fix(gguf): Disable bfloat16 for GGUF on blackwell device](../sources/prs/vllm/PR-30408.md), [[ROCm][Bugfix] Add MLACommonMetadata to allowed attention types for speculative decoding](../sources/prs/vllm/PR-30430.md), [[Bugfix] Pass FA version in `MultiHeadAttention`](../sources/prs/vllm/PR-30575.md), [[Perf] Eliminate padding and slicing op for GPT-OSS with Flashinfer MXFP4 MXFP8 MoE](../sources/prs/vllm/PR-30647.md), [[Misc][LLaMa4] Compile LLaMa Vision Encoder](../sources/prs/vllm/PR-30709.md), [Update note comment for flashinfer attention warmup](../sources/prs/vllm/PR-30711.md), [[Perf] enable flashinfer rotary_embedding custom ops in DeepSeek rotary](../sources/prs/vllm/PR-30729.md), [[Bugfix] Fix broken ViT attention selection for Blackwell device](../sources/prs/vllm/PR-30731.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [Add support for LoRA adapters in Nemotron-H models](../sources/prs/vllm/PR-30802.md), [[Kernels][FI] Skip trtllm attention when num_kv_heads=1](../sources/prs/vllm/PR-30842.md), [[Compressed-Tensors] Simplify NVFP4 Conditions, enable marlin support for NVFP4A16 MoEs](../sources/prs/vllm/PR-30881.md), [[Kernel][Performance] Enable smaller Scaling Factor tiling for NVFP4 small-batch decoding](../sources/prs/vllm/PR-30885.md), [[Feature]: Support NVIDIA ModelOpt HF FP8 variants FP8_PER_CHANNEL_PER_TOKEN and FP8_PB_WO in vLLM](../sources/prs/vllm/PR-30957.md), [[Mics] add pcp basic support to MoE model](../sources/prs/vllm/PR-31003.md), [[Bugfix] Fix GLM-4 MoE router logits dtype for data parallel chunking](../sources/prs/vllm/PR-31055.md), [ [FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/vllm/PR-31099.md), [[BugFix] LoRA: Support loading base_layer of experts](../sources/prs/vllm/PR-31104.md), [[Bugfix][Hardware][AMD] Consolidate FP8 min/max values helper function](../sources/prs/vllm/PR-31106.md), [[Misc] Fix grammar errors in comments and messages](../sources/prs/vllm/PR-31115.md), [[Bugfix] Fix MoE LoRA bin/pt loading](../sources/prs/vllm/PR-31161.md), [[perf] Integrate flashinfer concat_mla_k](../sources/prs/vllm/PR-31171.md), [[Bugfix][Hardware][AMD] Fix exception types in AITER MLA FP8 check](../sources/prs/vllm/PR-31177.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][Hardware][AMD] Fix last_page_len calculation in AITER MLA decode](../sources/prs/vllm/PR-31282.md), [fix(rocm): add early return in get_flash_attn_version for ROCm](../sources/prs/vllm/PR-31286.md), [pin lora_b moe weights on cpu](../sources/prs/vllm/PR-31317.md), [[Misc] Fix Qwen2-MoE shared_expert_gate](../sources/prs/vllm/PR-31339.md), [[BugFix] add select_gemm_impl on CompressedTensorsWNA16MoEMethod to support LoRA](../sources/prs/vllm/PR-31453.md), [[Bugfix][ROCm] Fix Static Quant Issue](../sources/prs/vllm/PR-31502.md), [[ROCm][Bugfix] Fix accuracy issue on fmoe when `VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS` enabled](../sources/prs/vllm/PR-31523.md), [Use the same memory for workspace13 and fused_output.](../sources/prs/vllm/PR-31531.md), [[Fix] Align fused moe lora_b shape with peft](../sources/prs/vllm/PR-31534.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[Perf] Add opt-in SM100 Oink RMSNorm custom-op path](../sources/prs/vllm/PR-31828.md), [[MISC] Add strict contiguity check for FlashInfer attention tensors](../sources/prs/vllm/PR-32008.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [[BugFix] Fix DeepSeek-V3.1 + DeepGEMM incompatible scale shapes](../sources/prs/vllm/PR-32361.md), [[Model] Molmo2: Enable quantized weight mapping for vision backbone](../sources/prs/vllm/PR-32385.md), [[Hardware][SM100] Add TRTLLM Kernel for INT4 W4A16 Kernel.](../sources/prs/vllm/PR-32437.md), [[Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper](../sources/prs/vllm/PR-32619.md), [[Kernel] use flashinfer for gdn prefill](../sources/prs/vllm/PR-32846.md), [[Performance] Tune Mamba selective scan kernel for B200](../sources/prs/vllm/PR-32873.md), [[Bugfix] Fix FP8 MoE EP Weight Loading for ModelOpt Llama4](../sources/prs/vllm/PR-32886.md), [[Spec Decode] Unified Parallel Drafting](../sources/prs/vllm/PR-32887.md), [[ROCm][perf] Shuffle KV cache to use paged_attention_common](../sources/prs/vllm/PR-32914.md), [[NVIDIA] [feat] Integrate flashinfer Trtllmgen bf16 moe](../sources/prs/vllm/PR-32954.md), [Support compress-tensors with nvfp4 or fp8 weights and modelopt with nvfp4 weights on Turing](../sources/prs/vllm/PR-33076.md), [[Attention] Use `has_flashinfer` helper](../sources/prs/vllm/PR-33177.md), [[Bugfix] Disable TRTLLM attention when KV transfer is enabled](../sources/prs/vllm/PR-33192.md), [[Bugfix] Register fp8 cutlass_group_gemm as supported for only SM90+SM100](../sources/prs/vllm/PR-33285.md), [[PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K]](../sources/prs/vllm/PR-33291.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [[Perf] Disable clean_logits in deepgemm fp8_mqa_logits kernel](../sources/prs/vllm/PR-33568.md), [[Bugfix] Fix sparse MLA metadata building](../sources/prs/vllm/PR-33579.md), [[Bugfix] fix DeepSeek R1 with CUTLASS MLA Broken on B200](../sources/prs/vllm/PR-33637.md), [enable skipping of SW attention layers when using FP8 KV cache](../sources/prs/vllm/PR-33695.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [Adding support to Sarvam's MoE models](../sources/prs/vllm/PR-33942.md), [[Bugfix] Relax TRTLLM KV cache contiguity assertion for cross-layer layout](../sources/prs/vllm/PR-34158.md), [[Bugfix] Fix DP Attention Padding in Dummy Run](../sources/prs/vllm/PR-34187.md), [[ModelBash][DSR1 NVFp4] Avoid Bf16 Bias Cast](../sources/prs/vllm/PR-34298.md), [[CPU][Perf] Accelerate Attention head for s390x using vector intrinsics](../sources/prs/vllm/PR-34434.md), [[Llama4,Quantization] Simplify and generalize logic for Q/K permutations in quantized self-attn layers ](../sources/prs/vllm/PR-34471.md), [[BUGFIX] Fix accuracy regression for NVIDIA-Nemotron-3-Nano-30B-A3B-NVFP4 with TP>1](../sources/prs/vllm/PR-34476.md), [[Model] Add NVFP4 quantization support for Step3.5-Flash](../sources/prs/vllm/PR-34478.md), [[Bugfix] Handle num_expert_group=None in flashinfer block-scale FP8 MoE](../sources/prs/vllm/PR-34494.md), [[BugFix] Add support for MTP num_speculative_tokens > 1 with sparse MLA](../sources/prs/vllm/PR-34552.md), [[Quantization] add humming quantization kernel](../sources/prs/vllm/PR-34556.md), [[Bugfix] Rescale NVFP4 weight scales to fix BF16 dequant underflow](../sources/prs/vllm/PR-34577.md), [[Update] Use FlashInfer fast_decode_plan directly instead of replication](../sources/prs/vllm/PR-34687.md), [[Bugfix] Fix MLA attention crash with AWQ/GPTQ quantized models](../sources/prs/vllm/PR-34695.md), [[torch.compile] Turn on silu+fp4 quant fusion by default for O1+](../sources/prs/vllm/PR-34718.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [[Attention] Use FA4 for MLA prefill](../sources/prs/vllm/PR-34732.md), [[Bugfix] Fix GDN attention crash with mixed decode/spec-decode batches](../sources/prs/vllm/PR-34871.md), [[Model Bash][DSR1] Add selective dynamic shape marking for CustomOp](../sources/prs/vllm/PR-34900.md), [[Perf] Enable FlashInfer DeepGEMM swapAB on SM90 by default](../sources/prs/vllm/PR-34924.md), [add mixed precision support for modelopt](../sources/prs/vllm/PR-35047.md), [Integrate flashinfer mm_mxfp8 in ModelOpt MXFP8](../sources/prs/vllm/PR-35053.md), [[Bug][DSV3.2] Always prepare metadata for DeepGEMM Sparse Attention](../sources/prs/vllm/PR-35075.md), [[BUGFIX][Qwen3.5] Hardcode `mlp.gate` as not quantizable ](../sources/prs/vllm/PR-35156.md), [[Linear Attention] fix bug for linear attention + prefix caching + reset_prefix_cache](../sources/prs/vllm/PR-35157.md), [[BUGFIX][Mamba][Qwen3.5] Zero freed SSM cache blocks on GPU](../sources/prs/vllm/PR-35219.md), [[Performance] Extract KV cache update op from flashinfer forward](../sources/prs/vllm/PR-35422.md), [[Bugfix] Fix KV Scale loading for MLA Models](../sources/prs/vllm/PR-35430.md), [[Quant][Feature] Support online MXFP8 quantization for MoE and dense models](../sources/prs/vllm/PR-35448.md), [[NVFP4] Support NVFP4 dense models from `modelopt` and `compressed-tensors` on AMD Instinct MI300, MI355X and Hopper through emulation](../sources/prs/vllm/PR-35733.md), [Fix routed experts capture for hybrid models (Mamba + Attention)](../sources/prs/vllm/PR-35744.md), [[MoE][Perf] Wrap DSV3 QKVAProj GEMM in custom op for torch.compile](../sources/prs/vllm/PR-35751.md), [[Mamba] Add stochastic rounding support](../sources/prs/vllm/PR-35753.md), [[Kernel] Add fused_sigmoid_gating_delta_rule_update kernel for Qwen3 Next](../sources/prs/vllm/PR-35777.md), [[Bugfix] Fix score layer quantization for sequence classification models - Qwen3 (VL) Reranker](../sources/prs/vllm/PR-35849.md), [[ROCm] Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5/Linear)](../sources/prs/vllm/PR-35850.md), [[Perf] Support FP8 KV cache for Flashinfer MLA Sparse](../sources/prs/vllm/PR-35891.md), [[MoE] Move PF Methods to Folder](../sources/prs/vllm/PR-35927.md), [Add support for ModelOpt MXFP8 MoE models](../sources/prs/vllm/PR-35986.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[BugFix] Fallback from FA4->FA2 for Batch Invariance](../sources/prs/vllm/PR-36059.md), [[LMCache] Pass TP size in lookup for MLA multi-reader locking](../sources/prs/vllm/PR-36129.md), [[Bugfix] Disable FlashInfer TRTLLM BF16 path for non-gated MoE](../sources/prs/vllm/PR-36146.md), [[Mamba] Flashinfer selective_state_update](../sources/prs/vllm/PR-36162.md), [[Bugfix][MLA] Add logits size budget to sparse indexer prefill chunking](../sources/prs/vllm/PR-36178.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [mla: don't update kv cache on dummy forwards](../sources/prs/vllm/PR-36282.md), [[Perf] Add TRTLLM FP8 MoE Modular Kernel](../sources/prs/vllm/PR-36307.md), [Disable cascade attention by default](../sources/prs/vllm/PR-36318.md), [Kimi k2.5 MLA based eagle3](../sources/prs/vllm/PR-36361.md), [feat(attention): extract KV-cache update from FlashAttentionDiffKV ba…](../sources/prs/vllm/PR-36466.md), [[Bugfix][Sparse MLA] report indexer CG support properly](../sources/prs/vllm/PR-36519.md), [[ROCm] Utilize persistent MLA kernel from AITER](../sources/prs/vllm/PR-36574.md), [[GDN] add a config for gdn kernel selection](../sources/prs/vllm/PR-36647.md), [[Misc][Attention] Clean up unused method in `CPU_ATTN`](../sources/prs/vllm/PR-36673.md), [[Bug] Fix FlashInfer MNNVL socket collisions under concurrent vLLM jobs](../sources/prs/vllm/PR-36674.md), [[ROCm][Perf] Allow MTP lens > 1 in Sparse MLA](../sources/prs/vllm/PR-36681.md), [fix(kv-cache): increase hybrid attention grouping threshold from 1.25 to 1.5](../sources/prs/vllm/PR-36684.md), [[ROCm] Attention selector reordering](../sources/prs/vllm/PR-36702.md), [[DSV3.2][MTP] Optimize Indexer MTP handling](../sources/prs/vllm/PR-36723.md), [[Bug][MoE] Fix TRTLLM NVFP4 Routing Kernel Precision](../sources/prs/vllm/PR-36725.md), [[ROCm] Fix KV copy methods and auto-select attention backend for ROCm](../sources/prs/vllm/PR-36845.md), [[ROCm] Validate block_size for explicitly selected attention backends](../sources/prs/vllm/PR-36846.md), [[Feat][Spec Decode] DFlash](../sources/prs/vllm/PR-36847.md), [[Bugfix] Fix FlashInfer GDN warmup ValueError on SM90 GPUs](../sources/prs/vllm/PR-36876.md), [[Feat][Bugfix] Enable additional dimension for Flashinfer MLA and fix routing dtype](../sources/prs/vllm/PR-36931.md), [[Bugfix] Disable cross-layer KV cache for MLA attention backends](../sources/prs/vllm/PR-37090.md), [[Benchmark] Improvements to attention benchmark script](../sources/prs/vllm/PR-37115.md), [[XPU] support MLA model on Intel GPU](../sources/prs/vllm/PR-37143.md), [Fix minimax m2.5 nvfp4 kv scales weight loading](../sources/prs/vllm/PR-37214.md), [[ROCM][Bugfix] Use correct stride in cp_mha_gather_cache_kernel for hybrid model (#37228)](../sources/prs/vllm/PR-37228.md), [[Bugfix] Expand quantization method support in perf metrics](../sources/prs/vllm/PR-37231.md), [[Attention] Support distinguishing between short extends and decodes](../sources/prs/vllm/PR-37303.md), [[Bugfix] Fix EP weight filter breaking EPLB and NVFP4 accuracy](../sources/prs/vllm/PR-37322.md), [[Model Runner V2] fix draft attention metadata generation](../sources/prs/vllm/PR-37364.md), [[Bugfix] Remove assertion for NVFP4 scale dynamic range](../sources/prs/vllm/PR-37465.md), [[BugFix] Allow qk_nope_head_dim=192 in FlashInfer MLA backend checks](../sources/prs/vllm/PR-37475.md), [[Bugfix] Fix marlin nvfp4 rescaling](../sources/prs/vllm/PR-37502.md), [Fix KV Offloading + MLA AssertionError by using num_kv_heads=1 in cpu…](../sources/prs/vllm/PR-37536.md), [[Performance] Remove unnecessary zero-fill of MLA decode output tensor in Aiter backend](../sources/prs/vllm/PR-37539.md), [[Bugfix][ROCm] Fix lru_cache on paged_mqa_logits_module](../sources/prs/vllm/PR-37547.md), [[Bugfix] Disable --calculate-kv-scales for hybrid GDN/Mamba+Attention…](../sources/prs/vllm/PR-37565.md), [[Bugfix] Disable monolithic TRTLLM MoE for Renormalize routing (#37591)](../sources/prs/vllm/PR-37605.md), [[ROCm][Bugfix] fix cache block size mismatch for aiter unified attention](../sources/prs/vllm/PR-37606.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[Bug] Fix fp8 deepgemm batch invariant](../sources/prs/vllm/PR-37718.md), [[Test] Only Run MLA model when user explicitly set for batch invariance](../sources/prs/vllm/PR-37719.md), [[XPU] add gptq(int4) support](../sources/prs/vllm/PR-37844.md), [[Feature] Support per-draft-model MoE backend via `--speculative-config`](../sources/prs/vllm/PR-37880.md), [[ROCm][perf] fix Aiter sparse MLA with MTP>1](../sources/prs/vllm/PR-37887.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [Fix NaN from stale FP4 scale padding in create_fp4_scale_tensor](../sources/prs/vllm/PR-38148.md), [[Model Runner V2] Rebuild attention metadata before eagle decode full…](../sources/prs/vllm/PR-38311.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[GDN] Eliminate GPU->CPU sync in prepare_chunk_indices during prefill](../sources/prs/vllm/PR-38361.md), [[QeRL] Fix online quantized reloading](../sources/prs/vllm/PR-38442.md), [[XPU] Fix spec-decode UTs under tests/v1/spec_decode](../sources/prs/vllm/PR-38491.md), [[Bugfix][MLA] Change default SM100 MLA prefill backend back to TRT-LLM](../sources/prs/vllm/PR-38562.md), [[ROCm] Fix aiter persistent mode mla with q/o nhead<16 for kimi-k2.5 tp8](../sources/prs/vllm/PR-38615.md), [Fix MLA runs when use_inductor_graph_partition=True](../sources/prs/vllm/PR-38631.md), [[Bugfix] Fix AWQ models batch invariance issues](../sources/prs/vllm/PR-38670.md), [[XPU] add xpu backend implementation of mxfp8 quant](../sources/prs/vllm/PR-38682.md), [[Bugfix] Restrict TRTLLM attention to SM100, fixing GB300 (SM103) hang](../sources/prs/vllm/PR-38730.md), [[Bugfix] Fix test mocks after SM100 restriction in #38730](../sources/prs/vllm/PR-38791.md), [[LMCache][MP] optimize save when mla enabled](../sources/prs/vllm/PR-38810.md), [[FlashAttention] Symlink FA4 instead of copying when using `VLLM_FLASH_ATTN_SRC_DIR`](../sources/prs/vllm/PR-38814.md), [[Quant] add CompressedTensorsW8A8Mxfp8 for linear and MoE layers](../sources/prs/vllm/PR-38815.md), [[Attention][MLA] Re-enable FA4 as default MLA prefill backend](../sources/prs/vllm/PR-38819.md), [[Bugfix] Fix NVFP4+MTP crash: force unquantized mtp.fc for Qwen3.5](../sources/prs/vllm/PR-38832.md), [[Attention] relax the head dim 512 and paged kv for sm90+FA4](../sources/prs/vllm/PR-38835.md), [[Bugfix] Re-enable Renormalize routing for TRT-LLM MoE experts](../sources/prs/vllm/PR-38859.md), [[Gemma4] Enable Fast Prefill Optimization](../sources/prs/vllm/PR-38879.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[Perf][GDN] Align TMA usage with upstream FLA](../sources/prs/vllm/PR-38981.md), [[Bug] Fix routing bias dtype for trtllm per-block fp8 moe](../sources/prs/vllm/PR-38989.md), [[Bugfix][MoE] Fix 6-8% decode regression: prefer multi-stream shared expert overlap](../sources/prs/vllm/PR-38990.md), [[Perf] Change Trtllm fp8 MoE to use Shuffled Weights and BlockMajorK Layout](../sources/prs/vllm/PR-38993.md), [[Quantization] - Layerwise reloading of Attention/KV quantized models](../sources/prs/vllm/PR-38995.md), [[Bugfix] Fix FlashInfer crash with kv_cache_dtype_skip_layers](../sources/prs/vllm/PR-39002.md), [[Gemma4] Support quantized MoE ](../sources/prs/vllm/PR-39045.md), [[Bug] Fix Trtllm Fp8 MoE Weight Shuffle Memory Fragamentation](../sources/prs/vllm/PR-39054.md), [[ROCm] Align AiterFlashAttentionImpl attn_type check with backend](../sources/prs/vllm/PR-39119.md), [[Refactor] Move NVFP4 GEMM management into NvFp4LinearKernel](../sources/prs/vllm/PR-39129.md), [[Refactor] Move MXFP8 GEMM management into MxFp8LinearKernel](../sources/prs/vllm/PR-39205.md), [[Bug] Fix rocm sparse attn indexer issue](../sources/prs/vllm/PR-39225.md), [[Bugfix] FlashInfer MXINT4 MoE crashes, missing do_finalize](../sources/prs/vllm/PR-39315.md), [[Feature] Batch invariant nvfp4 linear support](../sources/prs/vllm/PR-39322.md), [[Model Runner V2] Fix flex attention kv blocks calculation issue](../sources/prs/vllm/PR-39353.md), [[Bugfix][CT] Fix KV cache scale handling](../sources/prs/vllm/PR-39418.md), [[MLA] Optimize mla indexer prepare uniform decode for MTP > 1](../sources/prs/vllm/PR-39458.md), [[Kernel] Support TRTLLM GEN NVFP4 MoE for non-512-aligned hidden dims via weight padding](../sources/prs/vllm/PR-39510.md), [[Bugfix] Fix tensor shape mismatch in sparse attention with speculative decoding](../sources/prs/vllm/PR-39542.md), [[Mooncake] Fix mixed MLA+Eagle block-size validation](../sources/prs/vllm/PR-39596.md), [[XPU] properly handle q_descale on XPU as quant query input not supported](../sources/prs/vllm/PR-39676.md), [[Bugfix] Fix mismatch between global and local attention heads in tensor-parallel mode for param2moe model](../sources/prs/vllm/PR-39707.md), [[Bugfix] Reject non-nvfp4 dtypes when using the flashinfer_nvlink_one_sided all2all backend](../sources/prs/vllm/PR-39717.md), [[Bugfix][NIXL] Fix `_logical_to_kernel_block_ids` conversion for non-mamba models](../sources/prs/vllm/PR-39724.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[Bugfix] add support for 'num_attention_groups' in ModelArchConfigConvertorBase for Step3p5](../sources/prs/vllm/PR-39796.md), [[Bug] Fix batch invariance nvfp4 support](../sources/prs/vllm/PR-39820.md), [[Bugfix] Disable FlashInfer CUTLASS MoE on SM121 (DGX Spark)](../sources/prs/vllm/PR-39825.md), [[Core] Replace routing replay with device cache and async D2H pipeline](../sources/prs/vllm/PR-39917.md), [[Attention] use diff kv backend for mimo v2 flash](../sources/prs/vllm/PR-40045.md), [[Bugfix] Temporarily disable B200 fp4 MoE layer tests](../sources/prs/vllm/PR-40057.md), [Add nvfp4 kv cache support](../sources/prs/vllm/PR-40177.md), [Fix MoE backend selection for LoRA (unquantized MoE)](../sources/prs/vllm/PR-40273.md), [[Kernel][Helion] Optimize Helion config parsing latency](../sources/prs/vllm/PR-40850.md), [[DSV4] Add BF16 and MXFP8 A2A support for flashinfer a2a one sided](../sources/prs/vllm/PR-40960.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [[Bugfix][Hybrid][NemotronH] Fix mamba_cache_mode=all + speculative decoding crash](../sources/prs/vllm/PR-41233.md), [[ROCm][Quantization][3/N] Refactor quark_moe w4a4 w/ oracle](../sources/prs/vllm/PR-41436.md), [[Quantization] Rework quantization_config to use QuantKey and allow for activation override](../sources/prs/vllm/PR-41566.md), [[MXFP4] Support for linear layers + compressed-tensors integration](../sources/prs/vllm/PR-41664.md), [fix: remove unused norm for dpskv4](../sources/prs/vllm/PR-41710.md), [[Spec Decode] Add Gemma4 MTP speculative decoding support](../sources/prs/vllm/PR-41745.md), [Add NVFP4 all-gather GEMM fusion for AsyncTP](../sources/prs/vllm/PR-41882.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[Bugfix] Fix TRTLLM ragged MLA prefill workspace warmup](../sources/prs/vllm/PR-42112.md), [[LoRA] Support 2D and 3D MoE LoRA adapter at the same time](../sources/prs/vllm/PR-42242.md), [[Bugfix] mamba: run single-token extends as decodes](../sources/prs/vllm/PR-42430.md), [Refactor AWQ Marlin MoE onto modular WNA16 oracle](../sources/prs/vllm/PR-42483.md), [[UX] Add a persistent cache for FlashInfer autotuning](../sources/prs/vllm/PR-42537.md), [[Bugfix] fix swiglu limit issue for humming backend + deepseek v4](../sources/prs/vllm/PR-42541.md), [[CPU] Add fused GDN support for AMX CPU platform](../sources/prs/vllm/PR-42707.md), [Fix Weight loading for Qwen3.5-MTP and Qwen3-VL using runai_streamer](../sources/prs/vllm/PR-42716.md), [[CPU] Specify required KV cache layout for CPU attention backend](../sources/prs/vllm/PR-42740.md), [[ROCm] [Bugfix] Fix DeepSeek V4 Functionality and Accuracy](../sources/prs/vllm/PR-42810.md), [[Perf] Add do_not_specialize in fused FP8 RoPE kernel](../sources/prs/vllm/PR-42849.md), [[Model Refactoring] Migrate DeepSeek V4 to vllm/models/ [1/N] ](../sources/prs/vllm/PR-43004.md), [[XPU] update xpu graph usage](../sources/prs/vllm/PR-43043.md), [[CI failure] Temporarily disable using persistent cache for flashinfer autotune](../sources/prs/vllm/PR-43119.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md) | -| `tilelang` | | [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [Tilelang sparse decode fwd for dsv32 mi355](../sources/prs/sglang/PR-18488.md), [[AMD] Tilelang sparse fwd for dsv32 mi355/mi300](../sources/prs/sglang/PR-19945.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feat] profiler support cudagraph backend](../sources/prs/tilelang/PR-1658.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [Add swizzle layout detection and automatic merging for layout conflicts](../sources/prs/tilelang/PR-1736.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [fix(intrinsics): add missing _legalize_to_buffer_region in SM70 emitter](../sources/prs/tilelang/PR-1786.md), [[BugFix] Fix Hopper TMA lowering without warp specialization](../sources/prs/tilelang/PR-1840.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add T.copy_cluster to support TMA multicast and SM-to-SM cluster copy](../sources/prs/tilelang/PR-1908.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Bugfix] Fix CuTeDSL autotune cache invalid ELF header (#1967)](../sources/prs/tilelang/PR-1972.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[CUDA] Improve int4 GEMM lowering and packed codegen support](../sources/prs/tilelang/PR-2073.md), [[TMA] Support FP4 TensorMap TMA copies](../sources/prs/tilelang/PR-2107.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md) | -| `triton` | [Triton on Blackwell](../wiki/languages/triton-blackwell.md) | [Gated Delta Networks](../sources/blogs/gated-delta-net.md), [Native Sparse Attention (NSA)](../sources/blogs/nsa.md), [FlashInfer MLSys 2026 - Track A: Fused MoE FP8](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [FlashInfer MLSys 2026 - Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [Triton 3.6.0 Release Notes — Blackwell (SM100) Lowering](../sources/docs/triton-3.6-blackwell.md), [[None][fix] impl fused triton kernel for e8m0 resmooth to reduce memory footprint](../sources/prs/TensorRT-LLM/PR-10327.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[https://nvbugs/5983390][perf] Kernel fusions in _gather_k_cache_for_chunk of Indexer in DSA](../sources/prs/TensorRT-LLM/PR-12322.md), [[https://nvbugs/5983390][perf] Multiple host perf optimizations for DSA part](../sources/prs/TensorRT-LLM/PR-12581.md), [[None][feat] Add triton paged attention for AutoDeploy](../sources/prs/TensorRT-LLM/PR-12642.md), [[#12784][feat] AutoDeploy: Optimize DeepSeek-R1 model performance](../sources/prs/TensorRT-LLM/PR-12946.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[None][feat] Keep DSv4 o_a_proj as FP8, and port vLLM's fused_inv_rope_fp8_quant](../sources/prs/TensorRT-LLM/PR-13938.md), [[https://nvbugs/6152892][fix] Fix Triton MOE memory free when no swizzling enabled](../sources/prs/TensorRT-LLM/PR-14069.md), [[None][feat] Add chunked prefill support for Gemma4 (text + vision multimodal)](../sources/prs/TensorRT-LLM/PR-14134.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][fix] Update the OSS headers in derived FLA ops and AD modeling code](../sources/prs/TensorRT-LLM/PR-14281.md), [[None][chore] Update Claude Code agents and skills](../sources/prs/TensorRT-LLM/PR-14344.md), [feat: ragged tensor padding kernel for blackwell kernel alignment](../sources/prs/flashinfer/PR-1025.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [benchmark: trtllm-gen mha with sink, add benchmark args](../sources/prs/flashinfer/PR-1415.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [Selective State Update kernel (mamba)](../sources/prs/flashinfer/PR-2301.md), [MTP for mamba ](../sources/prs/flashinfer/PR-2444.md), [misc: point triton blackwell-ptxas to local cuda ptxas](../sources/prs/flashinfer/PR-2543.md), [Mamba SSU: better automatic kernel selection + algorithm selection optionally exposed to the user.](../sources/prs/flashinfer/PR-2591.md), [int16 Block-Scaled State and Stochastic Rounding for SSU (mamba)](../sources/prs/flashinfer/PR-2645.md), [Add varlen and speculative decoding support to selective state update](../sources/prs/flashinfer/PR-2700.md), [Mamba2 SSD Combined Forward Pass (Blackwell CuTe DSL Kernel)](../sources/prs/flashinfer/PR-2709.md), [fix(sm12x): fix micro-kernel workspace sizing when routed_rows > num_local_experts](../sources/prs/flashinfer/PR-3191.md), [checkpointing_ssu kernel: fused replay + conditional state-write for Mamba2](../sources/prs/flashinfer/PR-3324.md), [SM-constraint-GEMM by triton persistent kernel](../sources/prs/flashinfer/PR-982.md), [Triton `rms_norm` kernels](../sources/prs/flashinfer/PR-983.md), [[inductor] Fix profiler tests with latest Triton](../sources/prs/pytorch/PR-149059.md), [[inductor][triton 3.3] Fix cpp_wrapper w/ TMA in triton 3.3](../sources/prs/pytorch/PR-149993.md), [Fix uint view copy (#151598)](../sources/prs/pytorch/PR-154121.md), [[user triton] AOT inductor support for device-side TMA](../sources/prs/pytorch/PR-157241.md), [[release] Triton pin update to 3.4](../sources/prs/pytorch/PR-157752.md), [[cherry-pick][inductor][triton] Update HAS_WARP_SPEC to check triton.Config params. Update Triton Hash to top of release/3.4.x stack](../sources/prs/pytorch/PR-158646.md), [[Inductor][Intel GPU] Save `threads_per_warp` from tirton compiled kernel for launching kernel correctly in cpp wrapper.](../sources/prs/pytorch/PR-163388.md), [[2.9 cherry pick][triton] update 3.5 pin to bbb06c0334a6772b92d24bde54956e675c8c6604 (#163382)](../sources/prs/pytorch/PR-163583.md), [[AARCH64][CD][CUDA13][Triton][PTXAS] Turn on BUILD_BUNDLE_PTXAS=1 ](../sources/prs/pytorch/PR-164236.md), [[Minor][Inductor] move some combo kernel log from warning to debug](../sources/prs/pytorch/PR-167020.md), [[RELEASE 2.10] Release only changes](../sources/prs/pytorch/PR-170112.md), [[ROCm] Enable shared memory based pruning for Triton configs](../sources/prs/pytorch/PR-170190.md), [[Inductor] Fix constants handling for Triton constexpr (triton#8248)](../sources/prs/pytorch/PR-171129.md), [[RELEASE 2.11] Release only changes](../sources/prs/pytorch/PR-175091.md), [[inductor] avoid multi-stage for mix-order-red by default (#176228)](../sources/prs/pytorch/PR-176495.md), [[release 2.12] Apply Release only changes to 2.12 branch](../sources/prs/pytorch/PR-180470.md), [Add support for bf16 x bf16 cutlass fused MoE](../sources/prs/sglang/PR-10275.md), [support qwen3_next blackwell](../sources/prs/sglang/PR-10403.md), [Fix bias handling in TritonMoeQuantInfo within quantization/mxfp4.py](../sources/prs/sglang/PR-10579.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [Fix DSR1 accuracy for flashinfer_trtllm MoE with FP8 quantization](../sources/prs/sglang/PR-11081.md), [[AMD] Clean up vllm dependencies in moe_runner/triton.py](../sources/prs/sglang/PR-11349.md), [Support shared experts overlap in cutlass moe](../sources/prs/sglang/PR-11611.md), [[Ascend] qwen optimization](../sources/prs/sglang/PR-12078.md), [Enable Flashinfer TRTLLM-GEN-MoE FP8 blockwise kernel for Qwen3-Next on Blackwell](../sources/prs/sglang/PR-12543.md), [[Bugfix] Fix illegal memory access](../sources/prs/sglang/PR-12758.md), [Support internvl on Blackwell (which doesn't support fa3): add `SingletonCache` support to Vision{Sdpa|Triton|Ascend}Attention](../sources/prs/sglang/PR-13151.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [[NVIDIA] Enable TRTLLM BF16 MoE on Blackwell GPUs](../sources/prs/sglang/PR-13798.md), [[BugFix] fix outplace_fused_experts missing is_gated](../sources/prs/sglang/PR-13864.md), [Feat: GLM-4.6 supports shared experts fusion](../sources/prs/sglang/PR-13873.md), [[LoRA][III] Add LoRA support for MoE layers and enable TP](../sources/prs/sglang/PR-14105.md), [Apply new moe wna16 marlin gemm](../sources/prs/sglang/PR-14125.md), [Apply new moe align block size kernel](../sources/prs/sglang/PR-14134.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[Fix] add block size logic for sm120 smem size](../sources/prs/sglang/PR-14311.md), [[FIX] trtllm-moe-fp4-renorm for Qwen series models](../sources/prs/sglang/PR-14350.md), [Apply back moe_sum_reduce for fused_marlin_moe](../sources/prs/sglang/PR-14829.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [MoE: Skip SiLU/GELU activation for masked experts](../sources/prs/sglang/PR-15539.md), [Update flashinfer to 0.6.1](../sources/prs/sglang/PR-15551.md), [Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-15712.md), [ Add tuned triton==3.5.1 h200 tp2, tp4 for qwen 3 next](../sources/prs/sglang/PR-15948.md), [[Performance] Force split_k=1 for MXFP4 Triton kernels on Hopper](../sources/prs/sglang/PR-16014.md), [optimize get_topk_ragged by fusing get k and k_scale triton kernel](../sources/prs/sglang/PR-16043.md), [fix layer intermediate size](../sources/prs/sglang/PR-16084.md), [[NemotronH] Add latent MoE support](../sources/prs/sglang/PR-16227.md), [[Rework] Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-16723.md), [[Fix] `flashinfer_trtllm` `intermediate_size` assertion with Qwen3 + TP=8](../sources/prs/sglang/PR-16824.md), [Support mxint4 flashinfer_trtllm moe gemm](../sources/prs/sglang/PR-16892.md), [[GLM 4.7] Add RTX 6000 Pro aka sm120](../sources/prs/sglang/PR-17235.md), [Add mxfp8 support for online quantization, Triton dense linear, and CUTLASS MoE](../sources/prs/sglang/PR-17449.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [[sglang-miles] True on-policy training support for FSDP2](../sources/prs/sglang/PR-18639.md), [Adjust padding size to improve triton_kernels moe performance](../sources/prs/sglang/PR-19174.md), [Fix/nemotron mtp quantaized](../sources/prs/sglang/PR-19433.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [[diffusion][llm] macOS support](../sources/prs/sglang/PR-19549.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Support `triton_kernels` for GPT-OSS on SM120](../sources/prs/sglang/PR-19718.md), [Fix SM120 `triton_kernels` MXFP4 `block_k` for GPT-OSS](../sources/prs/sglang/PR-20040.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Qwen3.5] Fuse split/reshape/cat ops in GDN projection with Triton kernel](../sources/prs/sglang/PR-21019.md), [[refactor] Clean up duplicate flashinfer trtllm moe code](../sources/prs/sglang/PR-21233.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[RL] Support mxfp8 DeepSeek V3](../sources/prs/sglang/PR-21280.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Change default mm-attention backend from triton_attn to fa4](../sources/prs/sglang/PR-21595.md), [[XPU] Enable qwen3.5 on XPU](../sources/prs/sglang/PR-21668.md), [[Fix] Fall back to triton MOE for GPT-OSS on Blackwell with driver >= 595](../sources/prs/sglang/PR-21780.md), [fix pcg torch dynamo recompile in mxfp8 Triton path](../sources/prs/sglang/PR-21888.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [diffusion: add HunyuanVideo GroupNorm+SiLU fast path](../sources/prs/sglang/PR-22814.md), [[codex] diffusion: enable group norm silu fuse by default](../sources/prs/sglang/PR-23148.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [Optimize large GroupNorm SiLU apply](../sources/prs/sglang/PR-23938.md), [[diffusion] Fuse LTX2 split rotary embedding](../sources/prs/sglang/PR-24411.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [Fix performance regression on Deepseek V3 on `moe-runner-backend=triton` on SM90](../sources/prs/sglang/PR-24562.md), [[Codex] Opt Mistral Large performace ](../sources/prs/sglang/PR-24611.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [[MUSA][Diffusion] Improve wan model inference speed using torch.compile](../sources/prs/sglang/PR-25256.md), [[Gemma4]: Fix FP8 Triton scale layout](../sources/prs/sglang/PR-25286.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [Update logging for inplace setting in MoE layer](../sources/prs/sglang/PR-25499.md), [Fix logging for inplace setting in the flashInfer-trtllm backend](../sources/prs/sglang/PR-25522.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [Add DeepSeekV4 fused MoE Triton autotune support](../sources/prs/sglang/PR-25569.md), [Use triton_attn as default vision attention on B300 (SM103)](../sources/prs/sglang/PR-25570.md), [[diffusion] Fix GLM-Image /v1/images/edits support](../sources/prs/sglang/PR-25697.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Feature DeepSeek V3/R1 INT8 Quantization (block-wise)](../sources/prs/sglang/PR-3730.md), [[Feature] DeepSeek V3/R1 INT8 Quantization (channel-wise) ](../sources/prs/sglang/PR-3888.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [Feat/support encoder model (like bert)](../sources/prs/sglang/PR-4887.md), [Add DeepSeek V3/R1 shared experts fusion](../sources/prs/sglang/PR-4918.md), [reduce moe_align_block_size_kernel small batch mode overhead](../sources/prs/sglang/PR-5086.md), [Support tuning moe for llama 4 model](../sources/prs/sglang/PR-6042.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [enable auto-round quantization model](../sources/prs/sglang/PR-6226.md), [fix: enable multi-GPU Triton fused MoE tuning](../sources/prs/sglang/PR-6295.md), [reduce torch.zeros overhead in moe align block size kernel](../sources/prs/sglang/PR-6369.md), [Refine pre_reorder_triton_kernel slightly to improve performance](../sources/prs/sglang/PR-6627.md), [[CPU] [BF16] Call fused_experts_cpu, weight_packed_linear and bmm_cpu kernel in DeepSeek model](../sources/prs/sglang/PR-6641.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [[CPU] add optimizations for INT8 and FP8 DeepSeek](../sources/prs/sglang/PR-6769.md), [[CPU] support the case where num_attention_heads or intermediate_size is not divisible by the TP size](../sources/prs/sglang/PR-6771.md), [[DeepseekR1-FP4] Add Support for nvidia/DeepSeekR1-FP4 model](../sources/prs/sglang/PR-6853.md), [Use deepgemm instead of triton for fused_qkv_a_proj_with_mqa](../sources/prs/sglang/PR-6890.md), [chore: upgrade flashinfer v0.2.6.post1 jit](../sources/prs/sglang/PR-6958.md), [Fuse routed scaling factor in deepseek](../sources/prs/sglang/PR-6970.md), [Update default settings for blackwell](../sources/prs/sglang/PR-7023.md), [Fix positional argument](../sources/prs/sglang/PR-7093.md), [Enable ModelOpt Llama4 fp8 checkpoint deployment in SGLang](../sources/prs/sglang/PR-7129.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Fix MTP with Deepseek R1 Fp4](../sources/prs/sglang/PR-7376.md), [Fix torch compile run](../sources/prs/sglang/PR-7391.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [Integrate triton moe kernel](../sources/prs/sglang/PR-7689.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [Support triton kernels v3.4.0 for fused_moe](../sources/prs/sglang/PR-8258.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [fuse allreduce and residual_rmsnorm](../sources/prs/sglang/PR-8731.md), [[Perf] Auto enable best flashinfer mxfp4 kernel in b200](../sources/prs/sglang/PR-8898.md), [[fix] Fix mxfp4 triton MoE tp bug](../sources/prs/sglang/PR-9473.md), [Optimize moe_sum_reduce_kernel](../sources/prs/sglang/PR-9477.md), [Single Batch Overlap for MoE Models](../sources/prs/sglang/PR-9660.md), [[Kernel] add triton fused moe kernel for gptq/awq](../sources/prs/vllm/PR-12185.md), [[AMD][Quantization] Add TritonScaledMMLinearKernel since int8 is broken for AMD](../sources/prs/vllm/PR-12282.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Attention] Deepseek v3 MLA support with FP8 compute](../sources/prs/vllm/PR-12601.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[Attention] MLA support for V1](../sources/prs/vllm/PR-13789.md), [[Attention] Flash MLA for V1](../sources/prs/vllm/PR-13867.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[BugFix] MLA + V1, illegal memory access and accuracy issues](../sources/prs/vllm/PR-14253.md), [[BugFix][TritonMLA] Process weights after model loading for GGUF](../sources/prs/vllm/PR-14555.md), [[BugFix] Fix nightly MLA failure (FA2 + MLA chunked prefill, i.e. V1, producing bad results)](../sources/prs/vllm/PR-15492.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[Kernel][Bugfix] Re-fuse triton moe weight application](../sources/prs/vllm/PR-16071.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Bug] [ROCm] Fix Llama 4 Enablement Bug on ROCm: V0 ROCmFlashAttentionImpl and Triton Fused MoE bugs](../sources/prs/vllm/PR-16198.md), [[Kernel] Support W8A8 channel-wise weights and per-token activations in triton fused_moe_kernel](../sources/prs/vllm/PR-16366.md), [[Perf]Optimize rotary_emb implementation to use Triton operator for improved inference performance](../sources/prs/vllm/PR-16457.md), [Enable PTPC FP8 for CompressedTensorsW8A8Fp8MoEMethod (triton fused_moe)](../sources/prs/vllm/PR-16537.md), [[torch.compile][ROCm] Fuse quantization onto attention using a torch.compile pass](../sources/prs/vllm/PR-16756.md), [[Kernel] Unified Triton kernel that doesn't distinguish between prefill + decode](../sources/prs/vllm/PR-16828.md), [[Bugfix] Triton FA function takes no keyword arguments](../sources/prs/vllm/PR-16902.md), [[Attention] MLA move o_proj q_proj into cuda-graph region](../sources/prs/vllm/PR-17484.md), [fix amd triton mla path](../sources/prs/vllm/PR-17871.md), [[Bugfix][ROCm] Use `chunked_prefill_paged_decode` as fallback for V1 attention on ROCm](../sources/prs/vllm/PR-18093.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Kernel] Enable fp8 support for pplx and BatchedTritonExperts.](../sources/prs/vllm/PR-18864.md), [[Kernels] Add activation chunking logic to FusedMoEModularKernel](../sources/prs/vllm/PR-19168.md), [[Bugfix] Don't attempt to use triton if no driver is active](../sources/prs/vllm/PR-19561.md), [ [Feature] Integrate SM100 DeepGEMM support](../sources/prs/vllm/PR-20087.md), [[Kernel] Optimize Prefill Attention in Unified Triton Attention Kernel](../sources/prs/vllm/PR-20308.md), [[Misc] DP : Add ExpertTokensMetadata](../sources/prs/vllm/PR-20332.md), [[Perf] Use Triton instead of Torch for DeepGEMM Per Token Group Quant](../sources/prs/vllm/PR-20841.md), [[Kernel] DeepGemm MoE : Integrate triton permute / unpermute kernels ](../sources/prs/vllm/PR-20903.md), [[v1] Add Whisper model support (encoder-decoder)](../sources/prs/vllm/PR-21088.md), [[Attention] Clean up iRoPE in V1](../sources/prs/vllm/PR-21188.md), [[Kernel] Enable Hybrid Model Support in Triton Unified Attention Kernel](../sources/prs/vllm/PR-21197.md), [[Feature][Kernel]FusedMoE LoRA](../sources/prs/vllm/PR-21229.md), [[v1][attention] Support Hybrid Allocator + FlashInfer](../sources/prs/vllm/PR-21412.md), [[Bugfix] Add proper comparison for package versions](../sources/prs/vllm/PR-22314.md), [[BugFix] Fix triton compile error in `kernel_unified_attention_2/3d` caused by attention sinks](../sources/prs/vllm/PR-22368.md), [[gpt-oss] triton kernel mxfp4](../sources/prs/vllm/PR-22421.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [fp8 kv cache support fix for torch.compile](../sources/prs/vllm/PR-22758.md), [[Misc] Add @tdoublep as a maintainer of hybrid model and Triton-attention related code](../sources/prs/vllm/PR-23122.md), [[ROCm][Aiter] Add triton fp8 bmm kernel for mla](../sources/prs/vllm/PR-23264.md), [[Bugfix] Fixing division by zero in triton_attn if query_heads/kv_heads > 16 ](../sources/prs/vllm/PR-23424.md), [[Feature] Add Hopper DeepGEMM E8M0 for DeepSeekV3.1 scale_fmt](../sources/prs/vllm/PR-23666.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[Bug] Fix Shape Validation for Fallback while Enabling E8M0 for DeepGEMM](../sources/prs/vllm/PR-26322.md), [Move query quantization to attention layer for Flashinfer & Triton.](../sources/prs/vllm/PR-26534.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [fix cross attention](../sources/prs/vllm/PR-28346.md), [[Model] Add support for openPangu moe model](../sources/prs/vllm/PR-28775.md), [[Feature] Batch invariant: Enable `TRITON_MLA` without prefix-caching](../sources/prs/vllm/PR-29125.md), [[Bugfix] Only use triton_kernels for MXFP4 on SM90 and SM100](../sources/prs/vllm/PR-29339.md), [[LoRA] Support Quantized Adapters](../sources/prs/vllm/PR-30286.md), [[ROCm][Quantization] GPT OSS Upstream MoE wmxfp4_afp8 with static scales](../sources/prs/vllm/PR-30357.md), [[Perf] Set split_k to 1 for triton_kernels](../sources/prs/vllm/PR-30528.md), [[Bugfix] Fix Triton FusedMoE LoRA](../sources/prs/vllm/PR-30585.md), [Triton Attention: Support cross-layers blocks](../sources/prs/vllm/PR-30687.md), [fused_moe_lora PDL improvements](../sources/prs/vllm/PR-30716.md), [[Bugfix] [Kernel] Triton attention kernels: mask out V blocks that fall outside sliding window](../sources/prs/vllm/PR-30887.md), [[Bugfix] Fix incorrect tiles creation for mm prefix triton attention](../sources/prs/vllm/PR-30974.md), [Use aiter triton fused_add_rmsnorm_pad for gpt-oss](../sources/prs/vllm/PR-30976.md), [[Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten](../sources/prs/vllm/PR-31380.md), [fixed mypy warnings for files vllm/v1/attention with TEMPORARY workaround](../sources/prs/vllm/PR-31465.md), [[FIX] Add NO_MUL activation support for modular kernel path](../sources/prs/vllm/PR-31528.md), [[LoRA]Disable linear LoRA kernel PDL](../sources/prs/vllm/PR-31777.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[4/N][Attention] Move MLA common to model_executor](../sources/prs/vllm/PR-32060.md), [Add TMA support to fused_moe_lora kernel](../sources/prs/vllm/PR-32195.md), [[Bugfix][Attention] Explicitly report support for kv_cache_dtype bfloat16](../sources/prs/vllm/PR-32795.md), [Triton MLA perf fixes](../sources/prs/vllm/PR-33529.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [fix(mxfp4): return is_monolithic=False when LoRA is enabled for Triton backend](../sources/prs/vllm/PR-35382.md), [[XPU] Support block fp8 moe by fallback to TritonExpert on XPU](../sources/prs/vllm/PR-36458.md), [[Kernel] Fuse FP8 output quantization into merge_attn_states](../sources/prs/vllm/PR-36518.md), [[Bugfix] Warm up Triton autotuner for GDN layers during V1 profiling](../sources/prs/vllm/PR-36599.md), [[Bugfix] Fix KV scales inconsistency in fp8 MLA & FlashInfer kv_cache_dtype "auto" leading to gibberish](../sources/prs/vllm/PR-37054.md), [[MoE Refactor] Mxfp4 oracle rebased](../sources/prs/vllm/PR-37128.md), [[Misc] Add `float16` to `CacheDType`](../sources/prs/vllm/PR-37199.md), [[NIXL][BUG] Fix Triton heterogeneous TP](../sources/prs/vllm/PR-37940.md), [[Perf] triton bilinear_pos_embed kernel for ViT](../sources/prs/vllm/PR-37948.md), [[Perf] FP8 FlashInfer Attn for ViT](../sources/prs/vllm/PR-38065.md), [[Bugfix] Enable batch-invariant Triton matmul on all Ampere GPUs (SM 8x) ](../sources/prs/vllm/PR-38427.md), [[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity](../sources/prs/vllm/PR-38479.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[Perf] Reduce H2D pageable memory copies](../sources/prs/vllm/PR-38794.md), [[MoE] Move GPT OSS Triton kernel experts into fused_moe/experts/](../sources/prs/vllm/PR-39007.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[Attention][TurboQuant] Share dequant buffers, eliminate float16_copy](../sources/prs/vllm/PR-40941.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[feat] Add FP8 per-tensor Q scale support to Triton attention backend](../sources/prs/vllm/PR-42080.md), [[Perf] Wire silu_and_mul_per_block_quant into TritonFP8MoE (MiniMax-M2) ](../sources/prs/vllm/PR-42497.md), [[Kernel] Pack topk id/weights triton kernel](../sources/prs/vllm/PR-42527.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [Fused MoE — FP8 Block-Scale Routing + Dual GEMM](../wiki/kernels/fused-moe.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [Native Sparse Attention (NSA)](../wiki/kernels/nsa.md) | +| `mojo` | | [Modular: Matrix Multiplication on Blackwell](../sources/blogs/modular-blackwell-matmul.md) | +| `ptx` | [PTX Instructions for SM100](../wiki/languages/ptx-sm100.md) | [Twelve Attempts at an FP4 Kernel](../sources/blogs/amandeep-nvfp4-attempts.md), [simveit load_and_store](../sources/blogs/simveit-load-and-store.md), [tcgen05 for dummies](../sources/blogs/tcgen05-tutorial.md), [Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation](../sources/blogs/tilus-nvidia.md), [Blackwell NVFP4 Kernel Hackathon Journey](../sources/blogs/yue-nvfp4-hackathon.md), [NVIDIA Blackwell Compatibility Guide](../sources/docs/blackwell-compatibility-guide.md), [PTX ISA 9.0 SM100 Instruction Reference](../sources/docs/nvidia-ptx-isa-sm100.md), [[Public release 26/04] Introducing Mega MoE, FP4 Indexer and other features/fixes](../sources/prs/DeepGEMM/PR-304.md), [Sync nv_dev with upstream #316 (Mega MoE optimizations & benchmarks)](../sources/prs/DeepGEMM/PR-328.md), [misc: point triton blackwell-ptxas to local cuda ptxas](../sources/prs/flashinfer/PR-2543.md), [[AARCH64][CD][CUDA13][Triton][PTXAS] Turn on BUILD_BUNDLE_PTXAS=1 ](../sources/prs/pytorch/PR-164236.md), [[release-only] Remove +ptx from cuda 13.0 builds](../sources/prs/pytorch/PR-175567.md), [Add swizzle layout detection and automatic merging for layout conflicts](../sources/prs/tilelang/PR-1736.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[Bugfix] Enable `.shared::cta` in TMA copy paths only on CUDA 12.8+](../sources/prs/tilelang/PR-2087.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [Update launch_bounds_utils.h for correct compile on Multiple Cuda Arch - PTXAS out of range Warning](../sources/prs/vllm/PR-25843.md), [DeepGEMM — FP8 GEMM with Fine-Grained Scaling](../wiki/kernels/deepgemm.md), [NVFP4 Batched GEMV](../wiki/kernels/nvfp4-gemv.md) | +| `python` | | [NVFP4 GEMV and Improved NVFP4 GEMV](../sources/blogs/simon-nvfp4-gemv.md), [FlashInfer MLSys 2026 Track C: Gated Delta Net](../sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md), [GPU Mode NVFP4 Hackathon - Problem 1: Batched GEMV](../sources/contests/gpu-mode-nvfp4/problem-1-gemv.md), [GPU Mode NVFP4 Hackathon - Problem 2: NVFP4 GEMM](../sources/contests/gpu-mode-nvfp4/problem-2-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 3: Gated Dual GEMM](../sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md), [GPU Mode NVFP4 Hackathon - Problem 4: Grouped GEMM](../sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md), [cuTile Python DSL Reference](../sources/docs/cutile-python-dsl.md), [Performance: reducing the percentage of FFMA interleaving yields a sight performance gain, roughly 0.5%](../sources/prs/DeepGEMM/PR-42.md), [[None][feat] sm100 weight-only kernel](../sources/prs/TensorRT-LLM/PR-10190.md), [[TRTLLM-9798][feat] Change to use new DeepGEMM MQA sm100 kernel for MTP-3](../sources/prs/TensorRT-LLM/PR-10226.md), [[None][feat] MiniMax M2 support](../sources/prs/TensorRT-LLM/PR-10532.md), [[None][feat] Remove non flash attetnion style fmha_v2 kernel for hopper](../sources/prs/TensorRT-LLM/PR-11381.md), [[None][fix] Fix int4 awq for sm120/121](../sources/prs/TensorRT-LLM/PR-11561.md), [[None][fix] Fix SM120 issue for rms_norm with nvfp4_quant_fusion](../sources/prs/TensorRT-LLM/PR-11774.md), [[None][feat] GLM 5 support and DSA MTP fixes](../sources/prs/TensorRT-LLM/PR-11990.md), [[TRTLLM-11285][feat] Fuse indexer wk + weights_proj into single GEMM in TF32 for DS-V3.2](../sources/prs/TensorRT-LLM/PR-12055.md), [[https://nvbugs/5983390][fix] Remove redundant D2H sync to optimize perf](../sources/prs/TensorRT-LLM/PR-12445.md), [[#12634][feat] AutoDeploy: Support rank 256 MLA in flashinfer_mla](../sources/prs/TensorRT-LLM/PR-12519.md), [[https://nvbugs/5879577][fix] Fix KeyError in DeepSeekV3Lite FP8 MTP weight loading](../sources/prs/TensorRT-LLM/PR-12530.md), [[None][feat] Add bf16 trtllm-gen moe support through flashinfer.](../sources/prs/TensorRT-LLM/PR-12738.md), [[None][fix] Propagate init_load_balancer to DeepGemmFusedMoE in create_moe_backend](../sources/prs/TensorRT-LLM/PR-13207.md), [[TRTLLM-11127][feat] add W4A8_MXFP4_FP8 MoE unit test support](../sources/prs/TensorRT-LLM/PR-13401.md), [[TRTLLM-11285][perf] Force enable TF32 tensor cores for DSA indexer fused GEMM](../sources/prs/TensorRT-LLM/PR-13452.md), [[TRTLLM-12128][feat] enable SageAttention for Wan/FLUX (new commits)](../sources/prs/TensorRT-LLM/PR-13570.md), [[TRTLLM-12316][feat] Integrate FP4 indexer for DSv4](../sources/prs/TensorRT-LLM/PR-13575.md), [[None][feat] Enable EPLB for DeepSeek-V4](../sources/prs/TensorRT-LLM/PR-13595.md), [[None][feat] Add bf16 trtllm moe through flashinfer.](../sources/prs/TensorRT-LLM/PR-13689.md), [[None][fix] Use compressed lengths for DeepSeek-V4 indexer](../sources/prs/TensorRT-LLM/PR-13802.md), [[None][feat] Update FMHA cubins for head_dim 80](../sources/prs/TensorRT-LLM/PR-13808.md), [[TRTLLM-12503][feat] Parallel VAE independent scaling and fix arg passing](../sources/prs/TensorRT-LLM/PR-13873.md), [[None][feat] enable TRTLLM-Gen internal routing](../sources/prs/TensorRT-LLM/PR-13997.md), [[None][feat] Enable 2 DSv4 perf optimizations by default](../sources/prs/TensorRT-LLM/PR-14120.md), [[TRTLLM-12462][fix] Fix FP8 block scaling GEMM autotuner cache growth](../sources/prs/TensorRT-LLM/PR-14165.md), [[https://nvbugs/6025177][test] rcca tests using kimi k2.5 fp4](../sources/prs/TensorRT-LLM/PR-14172.md), [[https://nvbugs/6163147][fix] swap layer.mlp in place for Mixtral modelopt export](../sources/prs/TensorRT-LLM/PR-14179.md), [[None][fix] Avoid dp_size x ep_size double-count in MegaMoEDeepGemm SymmBuffer](../sources/prs/TensorRT-LLM/PR-14213.md), [[None][refactor] clean up AttentionForwardArgs](../sources/prs/TensorRT-LLM/PR-14244.md), [[None][fix] Handle unset attention_dp_relax in ADP routers](../sources/prs/TensorRT-LLM/PR-14276.md), [[https://nvbugs/6095421][fix] Update resolve_moe_backend](../sources/prs/TensorRT-LLM/PR-14282.md), [[None][chore] Update Claude Code agents and skills](../sources/prs/TensorRT-LLM/PR-14344.md), [[None][feat] GPT-OSS Sm120/Sm121 Support](../sources/prs/TensorRT-LLM/PR-7937.md), [[TRTLLM-8535][feat] Support DeepSeek V3.2 with FP8 + BF16 KV cache/NVFP4 + BF16 KV cache](../sources/prs/TensorRT-LLM/PR-8405.md), [[TRTLLM-8827] [feat] Enable low precision alltoall for Cutlass and TRTLLMGen backends](../sources/prs/TensorRT-LLM/PR-8675.md), [[TRTLLM-8958][feat] and [TRTLLM-8960]: create ConfigurableMoE and support TRTLLMGenFusedMoE as backend](../sources/prs/TensorRT-LLM/PR-9486.md), [[https://nvbugs/5726962][feat] Apply fusion for W4AFP8_AWQ MoE](../sources/prs/TensorRT-LLM/PR-9838.md), [Experimental Python cooperative algorithms](../sources/prs/cccl/PR-1973.md), [[cuda.compute]: Fix faulty pointer arithmetic calculation in CUB dispatch](../sources/prs/cccl/PR-7940.md), [Expose `max_segment_size` guarantee in cuda.compute](../sources/prs/cccl/PR-8284.md), [[cub]: implement utilities for policy selection](../sources/prs/cccl/PR-8355.md), [Hopper Grouped GEMM support for FP8 Accum](../sources/prs/cutlass/PR-2123.md), [fix gqa issue for blackwell fmha.py](../sources/prs/cutlass/PR-2599.md), [Add tutorial fp16_gemm_1](../sources/prs/cutlass/PR-2750.md), [new example with TMA prefetch feature targeting for DRAM latency boun…](../sources/prs/cutlass/PR-2881.md), [[Cute-DSL] Add option for issue_clc_query without multicast](../sources/prs/cutlass/PR-3021.md), [[Hopper CuTeDSL] Add grouped GEMM kernel example](../sources/prs/cutlass/PR-3091.md), [Support for Group GEMM in CUTLASS Profiler for GeForce and Spark](../sources/prs/cutlass/PR-3092.md), [[CLI] add cutedsl fp16 gemm tutorial from 2 to 6](../sources/prs/cutlass/PR-3106.md), [Update blackwell tutorial to be compatible with 4.5-dev version](../sources/prs/cutlass/PR-3130.md), [Small Tile N BlockScaled GEMM + Grouped GEMM on SM12x](../sources/prs/cutlass/PR-3176.md), [Add var-seq-len to FA3 fp16 / bf16 fwd](../sources/prs/flash-attention/PR-1072.md), [FA3 FP8 qkv descales + restore max offset for h128 causal + added sync for producer WG](../sources/prs/flash-attention/PR-1173.md), [Add seqused_q in fwd / bwd and seqused_k in bwd in hopper FA.](../sources/prs/flash-attention/PR-1182.md), [Add local attention in Hopper FAv3](../sources/prs/flash-attention/PR-1233.md), [Paged Attention support for FA3](../sources/prs/flash-attention/PR-1268.md), [FA3 paged attention: Readiness for Cutlass 3.6 / default value for block_table](../sources/prs/flash-attention/PR-1331.md), [Support hdimQK != hdimV backward](../sources/prs/flash-attention/PR-1604.md), [Improve causal backward determinism perf with SPT schedule](../sources/prs/flash-attention/PR-1893.md), [[Cute,Fwd,Sm100] Implement SplitKV](../sources/prs/flash-attention/PR-1940.md), [Blackwell FlashAttention-BWD (v1.0)](../sources/prs/flash-attention/PR-1945.md), [[Cute] Block sparse support Sm100](../sources/prs/flash-attention/PR-1985.md), [[Cute,Fwd,Sm100] Support `q_stage=1` for inference](../sources/prs/flash-attention/PR-1993.md), [[Cute,Fwd,Sm100] Support paged attention](../sources/prs/flash-attention/PR-1999.md), [[Cute,Sm100,Fwd] use correction warps for epi when not using TMA](../sources/prs/flash-attention/PR-2014.md), [[Cute,Fwd,Sm100] don't pass mask_fn to softmax_step generically](../sources/prs/flash-attention/PR-2026.md), [[Cute,Bwd,Sm100] enable deterministic mode for sm100 bwd and fix race conditions](../sources/prs/flash-attention/PR-2033.md), [[Cute,Fwd] Extend score_mod to variable sequence length](../sources/prs/flash-attention/PR-2043.md), [Add score-mod bwd support ](../sources/prs/flash-attention/PR-2070.md), [Add blocksparse support for bwd on blackwell](../sources/prs/flash-attention/PR-2085.md), [Fix IMA in fwd on m boundary](../sources/prs/flash-attention/PR-2091.md), [Add pack-gqa fwd support for sparse impl w/ broadcasted H dim](../sources/prs/flash-attention/PR-2098.md), [[Cute,Fwd,Sm100] distributed offset calculation for paged KV](../sources/prs/flash-attention/PR-2104.md), [[NVIDIA] Enable Jetson Thor FA4](../sources/prs/flash-attention/PR-2108.md), [[CUTE][SM90]Enable pack-gqa with broadcasted maskmods](../sources/prs/flash-attention/PR-2145.md), [[Cute][Flex]Add pack-gqa divmod](../sources/prs/flash-attention/PR-2180.md), [[Cute,Fwd,Sm100] support irregular qhead / kvhead ratios](../sources/prs/flash-attention/PR-2186.md), [[Ai-assisted] CLC work stealing](../sources/prs/flash-attention/PR-2218.md), [[Bwd,Sm120] Add SM120 backward pass support](../sources/prs/flash-attention/PR-2330.md), [Add SM120 varlen attention support](../sources/prs/flash-attention/PR-2333.md), [[Fwd,Sm90] Add paged KV attention support (tma and cp.async)](../sources/prs/flash-attention/PR-2360.md), [[Cute,Sm100,Bwd] refine bwd swizzle for deterministic](../sources/prs/flash-attention/PR-2390.md), [Feat([FA4][CUTE DSL]) Add head_dim=256 support (forward + backward)](../sources/prs/flash-attention/PR-2412.md), [Add CLC scheduler heuristic](../sources/prs/flash-attention/PR-2455.md), [[hd256] Improve forward kernel with exp2 FMA emulation (3% to 9% performance gain)](../sources/prs/flash-attention/PR-2488.md), [[hd256] Add TMA paged KV support to SM100 2CTA forward kernel](../sources/prs/flash-attention/PR-2489.md), [[FA4][hd256] Backward TMA bulk-store epilogue + LSE/dpsum coalesce](../sources/prs/flash-attention/PR-2497.md), [Fix ZeroDivisionError in num_splits_heuristic for empty Q workloads](../sources/prs/flash-attention/PR-2515.md), [bugfix: import wrapper of mla decode](../sources/prs/flashinfer/PR-1013.md), [Add fp4 quantization swizzling tests](../sources/prs/flashinfer/PR-1157.md), [feat: nvshmem python bindings](../sources/prs/flashinfer/PR-1160.md), [feat: logits processor fustion rule for temperature softmax](../sources/prs/flashinfer/PR-1170.md), [Expose fp4 blockscale swizzling kernel](../sources/prs/flashinfer/PR-1176.md), [[feat] support block sparse attention w/ variable block sizes and head-wise sparse patterns](../sources/prs/flashinfer/PR-1177.md), [bugfix: fix invalid blackwell fmha unittests](../sources/prs/flashinfer/PR-1181.md), [bugfix: fix blackwell fmha hanging issue for empty kv_len](../sources/prs/flashinfer/PR-1198.md), [Add DeepGEMM kernels](../sources/prs/flashinfer/PR-1209.md), [Fix test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-1211.md), [init add gemm fp8 using cudnn backend](../sources/prs/flashinfer/PR-1264.md), [feat: add masked deepgemm support and benchmarking](../sources/prs/flashinfer/PR-1266.md), [hotfix: fix deepgemm artifactory hash](../sources/prs/flashinfer/PR-1278.md), [fix: update trtllm-gen fmha benchmark](../sources/prs/flashinfer/PR-1280.md), [Unify groupwise fp8 GEMM test](../sources/prs/flashinfer/PR-1281.md), [add mm_fp4 use cudnn backend](../sources/prs/flashinfer/PR-1288.md), [Remove FAST_BUILD FLAG for MOE](../sources/prs/flashinfer/PR-1291.md), [Support loading autotuned results from json for cutlass fp4 moe backends](../sources/prs/flashinfer/PR-1310.md), [test qkvo quantization not equal to 1.](../sources/prs/flashinfer/PR-1314.md), [minor: add trtllm_gen_mla benchmark](../sources/prs/flashinfer/PR-1316.md), [Allow cudnn prefill kernels to be called natively](../sources/prs/flashinfer/PR-1317.md), [refactor: Improved metainfo for trtllm-gen kernels](../sources/prs/flashinfer/PR-1328.md), [add torch float4_e2m1fn_x2 check for cudnn fp4 backend](../sources/prs/flashinfer/PR-1333.md), [[Fix] remove torch 2.8 requirement for FP4 GEMM](../sources/prs/flashinfer/PR-1334.md), [Fix bench deepgemm setting](../sources/prs/flashinfer/PR-1344.md), [Support passing kv_data_type to MultiLevelCascadeAttentionWrapper.plan()](../sources/prs/flashinfer/PR-1350.md), [[fix] remove (view) transpose to keep consistent with majorness MN requirement.](../sources/prs/flashinfer/PR-1358.md), [hotfix: update mxfp4 groupwise-scaled gemm unittests](../sources/prs/flashinfer/PR-1359.md), [Update autotune results for the nvfp4 cutlass moe backends for v0.2.9](../sources/prs/flashinfer/PR-1361.md), [refactor: download trtllm gemm metadata from server](../sources/prs/flashinfer/PR-1378.md), [Allow BatchPrefillPagedWrapper to call cudnn API](../sources/prs/flashinfer/PR-1384.md), [Adding FP8 benchmark on attention and matmul testing](../sources/prs/flashinfer/PR-1390.md), [Add Mxfp4 trtllm-gen moe unit tests](../sources/prs/flashinfer/PR-1399.md), [feature: enable cublas for fp4 gemm when cudnn == 9.11.1 or >= 9.13](../sources/prs/flashinfer/PR-1405.md), [Faster weight processing (moe nvfp4)](../sources/prs/flashinfer/PR-1412.md), [refactor: Sink attention AoT](../sources/prs/flashinfer/PR-1427.md), [Fix redundant kernels in moe](../sources/prs/flashinfer/PR-1428.md), [bugfix: fix perf issue by using fp8 graph that can use cublaslt](../sources/prs/flashinfer/PR-1435.md), [feat: enable trtllm-gen attn speculative decoding verify by decode](../sources/prs/flashinfer/PR-1453.md), [Fix TRTLLM NVFP4-out attention kernel scale factor dim issue](../sources/prs/flashinfer/PR-1460.md), [feat: Enable multiple fused-moe backends](../sources/prs/flashinfer/PR-1472.md), [refactor: unify autotuner for bmm_fp8](../sources/prs/flashinfer/PR-1479.md), [fix missing enable_pdl argument in trtllm-gen fp4 moe](../sources/prs/flashinfer/PR-1480.md), [Add python API for masked grouped gemm](../sources/prs/flashinfer/PR-1481.md), [flashinfer_benchmark QoL Improvements and Attention FP8 Support](../sources/prs/flashinfer/PR-1512.md), [Remove cuda-python from dependency and check at runtime](../sources/prs/flashinfer/PR-1534.md), [Add sm check for sm100 only cutlass/trtllm kernel](../sources/prs/flashinfer/PR-1535.md), [feat: Add fp8-qkv, fp16/bf16 output MHA](../sources/prs/flashinfer/PR-1540.md), [perf: Enable SplitK and fix tile-scheduling for moe fp4 fused moe](../sources/prs/flashinfer/PR-1548.md), [feat: Support for inferring out_dtype from out.dtype for TRTLLM attention kernel](../sources/prs/flashinfer/PR-1578.md), [refactor: Expose calculate_tile_tokens_dim function](../sources/prs/flashinfer/PR-1581.md), [bugfix: Fix test_fp4_quantize test bug](../sources/prs/flashinfer/PR-1585.md), [fix: limit the number of nvcc threads for each kernel](../sources/prs/flashinfer/PR-1589.md), [fix: Improve TRTLLM attention kernel out_dtype unit test](../sources/prs/flashinfer/PR-1590.md), [bugfix: fix unittest test_fp8_quantize](../sources/prs/flashinfer/PR-1599.md), [feat: Enable MnnvlMemory (for alltoallv) on B200](../sources/prs/flashinfer/PR-1601.md), [feat: add support of fp4_batched_quantize](../sources/prs/flashinfer/PR-1633.md), [fix: pass workspace for trtllm-gen attention](../sources/prs/flashinfer/PR-1635.md), [test: pytest.mark.xfail on deepgemm](../sources/prs/flashinfer/PR-1636.md), [bugfix: Fix FLOPS calculation for bench_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-1640.md), [fix: zero-init workspace buffer for trtllm-gen fmha](../sources/prs/flashinfer/PR-1643.md), [Added mx_fp4 support using the cudnn backend](../sources/prs/flashinfer/PR-1644.md), [Add benchmark for MLARopeQuantize](../sources/prs/flashinfer/PR-1656.md), [test: update fused_moe test to random scale factor](../sources/prs/flashinfer/PR-1665.md), [[Hotfix] `test_fp4_quantize.py` failure on sm103](../sources/prs/flashinfer/PR-1666.md), [TGV GEMM as a BF16 backend alternative to cuBLAS](../sources/prs/flashinfer/PR-1668.md), [test: better fp8 quantization init for fused_moe test](../sources/prs/flashinfer/PR-1674.md), [[misc] add a wrapper class for attention sink jit args](../sources/prs/flashinfer/PR-1679.md), [Update deepgemm backend for 103a](../sources/prs/flashinfer/PR-1694.md), [[cute_dsl] add gemm + all reduce (two_shot)](../sources/prs/flashinfer/PR-1695.md), [hotfix: Hotfix for `test_pod_kernels.py` on B300](../sources/prs/flashinfer/PR-1698.md), [feat: Benchmark mm_fp4 mxfp4 support and gemm autotune support. Restore mm_fp4 API behavior](../sources/prs/flashinfer/PR-1706.md), [bugfix: increase workspace to make trtllm gen attention unit test pass](../sources/prs/flashinfer/PR-1707.md), [test: skip the unsupported test cases for sm120/121](../sources/prs/flashinfer/PR-1710.md), [perf: Add tuning config for cutlass moe for a hardware](../sources/prs/flashinfer/PR-1716.md), [feat: port fast_decode_plan from sgl](../sources/prs/flashinfer/PR-1745.md), [tests: xfail attention sink UT for sliding window + non causal case](../sources/prs/flashinfer/PR-1752.md), [tests: xfail moe quantization classes mxfp8_bf16 UTs on sm103 ](../sources/prs/flashinfer/PR-1754.md), [Fix tests/test_trtllm_gen_attention.py::test_trtllm_batch_prefill, ::test_trtllm_batch_decode mismatch error](../sources/prs/flashinfer/PR-1755.md), [fix: should pass global_override_indptr_cpu in fast_decode_plan param list](../sources/prs/flashinfer/PR-1757.md), [Added xfail for mx_fp4 matmul on SM120](../sources/prs/flashinfer/PR-1766.md), [tests: skip non SM100/103 for grouped deepgemm](../sources/prs/flashinfer/PR-1767.md), [add test case for trtllm gen fused moe with kimi k2 problem sizes](../sources/prs/flashinfer/PR-1768.md), [Waive / disable test_mla_decode_kernel.py::test_mla_decode_kernel for not sm80 ](../sources/prs/flashinfer/PR-1771.md), [Support checks PoC](../sources/prs/flashinfer/PR-1809.md), [tests: Update support for tgv_gemm to SM100 only and add to ut](../sources/prs/flashinfer/PR-1810.md), [fix: fp4 moe on sm120](../sources/prs/flashinfer/PR-1817.md), [misc: fix some B200 GEMM bench](../sources/prs/flashinfer/PR-1883.md), [fix: Fix trtllm-gen prefill IMA when batch_size==1](../sources/prs/flashinfer/PR-1912.md), [Add realistic bench for persistent kernel ](../sources/prs/flashinfer/PR-1942.md), [fix: Add cutlass as an mm_fp4 backend in compute capability 12.0 in benchmark code](../sources/prs/flashinfer/PR-1959.md), [fix: ensure SM120/121 SFA/SFB contiguity](../sources/prs/flashinfer/PR-1963.md), [Feature: Add support for L40 FusedMoE in cutlass path](../sources/prs/flashinfer/PR-1973.md), [fix: Make attention microbenchmark correctly use page table](../sources/prs/flashinfer/PR-1976.md), [fix: Skipping attention sink Blackwell test outside of Blackwell](../sources/prs/flashinfer/PR-1978.md), [feat: Add backend='auto' to mm_fp4 and enable autotune for backend='cudnn'](../sources/prs/flashinfer/PR-1979.md), [unittest: Add head dim 256 test cases and mark as xfail](../sources/prs/flashinfer/PR-1999.md), [Fix trtllm-gen attention illegal memory access](../sources/prs/flashinfer/PR-2002.md), [fix: Enable SM121 for mm_fp4](../sources/prs/flashinfer/PR-2012.md), [feat: suitable_auto_backends to prune auto backends, bmm_fp8 refactor, heuristic_func intake](../sources/prs/flashinfer/PR-2029.md), [Added an initial implementation of Q and KV Cache in fp8 and to use t…](../sources/prs/flashinfer/PR-2035.md), [test: Skip test_fp8_quantize.py on Hopper](../sources/prs/flashinfer/PR-2052.md), [misc: Add XQA decode to microbenchmark for sm90 and sm120](../sources/prs/flashinfer/PR-2055.md), [[Test] Optimize test_trtllm_gen_fused_moe.py](../sources/prs/flashinfer/PR-2072.md), [unittest: improve the efficiency of xqa unittests](../sources/prs/flashinfer/PR-2075.md), [fix: fix test_trtllm_gen_attention when max_seq_len < page_size](../sources/prs/flashinfer/PR-2076.md), [Patch sm103 for 3xfp4 moe generation](../sources/prs/flashinfer/PR-2082.md), [refactor: update dpsk fused_moe test [1]](../sources/prs/flashinfer/PR-2088.md), [refactor: pass hopper deepgemm include directory through python](../sources/prs/flashinfer/PR-2090.md), [refactor: update dpsk fused_moe test [2]](../sources/prs/flashinfer/PR-2097.md), [[DSR1] Added MLA test](../sources/prs/flashinfer/PR-2100.md), [fix: Fix bench_mm_fp8.py](../sources/prs/flashinfer/PR-2129.md), [A unified API for the MNNVL and single-node/multi-GPU AllReduce kernels.](../sources/prs/flashinfer/PR-2130.md), [fix(trtllm): reset negative strideBatch to 0 for ragged KV layout to …](../sources/prs/flashinfer/PR-2134.md), [fix: some bugs of headDim 256 trtllm-gen fmha kernels. ](../sources/prs/flashinfer/PR-2137.md), [Enable Hopper FA3 FP8 attention in decode.py](../sources/prs/flashinfer/PR-2148.md), [refactor: Move mla code from decode.py to mla.py and add to documentation](../sources/prs/flashinfer/PR-2163.md), [fix: compile flags for trtllm fmha_v2 ](../sources/prs/flashinfer/PR-2175.md), [Rename noauxtc to fused_topk_deepseek](../sources/prs/flashinfer/PR-2181.md), [Permute page table in benchmarking](../sources/prs/flashinfer/PR-2194.md), [misc: support checks for gemm](../sources/prs/flashinfer/PR-2214.md), [Fp8 attention are now part of cuDNN 9.17.1](../sources/prs/flashinfer/PR-2241.md), [test: Fix MNNVL tests to skip when container lacks SYS_PTRACE capability](../sources/prs/flashinfer/PR-2245.md), [feat: Add support for bmm mxfp8](../sources/prs/flashinfer/PR-2256.md), [Fix CUTLASS FP8 gemm correctness issue on SM120/SM121 for shapes where N is not divisible by ScaleGranularityN.](../sources/prs/flashinfer/PR-2261.md), [test: use .float() in in F.cosine_similarity() in bmm_fp8 test](../sources/prs/flashinfer/PR-2266.md), [Tiny fix bench tgv gemm](../sources/prs/flashinfer/PR-2277.md), [fix: Decode benchmark's fa2_tc uses backend=fa2 in wrapper](../sources/prs/flashinfer/PR-2302.md), [Support both 3D and 4D kv_cache shapes in MLA APIs](../sources/prs/flashinfer/PR-2334.md), [Added the cudnn backend Ragged KV Cache wrapper](../sources/prs/flashinfer/PR-2352.md), [benchmarks: Add norm and quantization routines to microbenchmark harness.](../sources/prs/flashinfer/PR-2362.md), [feat: [Qwen3-Next] Add Cute DSL GDN decode kernel and tests](../sources/prs/flashinfer/PR-2370.md), [feat: BF16 GEMM using cuDNN backend](../sources/prs/flashinfer/PR-2376.md), [A Blackwell-optimized version of selective_state_update (decode)](../sources/prs/flashinfer/PR-2387.md), [perf: mm_fp4 heuristic prioritizes CUTLASS over cuDNN on SM103](../sources/prs/flashinfer/PR-2404.md), [perf: add fp4 GEMM tile configs and streamK scheduler for SM120](../sources/prs/flashinfer/PR-2460.md), [fix: blockscale moe routine supports non-DS routing](../sources/prs/flashinfer/PR-2476.md), [fix: Fix memory bandwidth calculation in MLA benchmarks](../sources/prs/flashinfer/PR-2479.md), [Feat/gdn decode pooled](../sources/prs/flashinfer/PR-2521.md), [feat: BF16 GEMM benchmarking support](../sources/prs/flashinfer/PR-2525.md), [pick fa2 for BatchDecodeWithPagedKVCacheWrapper auto backend](../sources/prs/flashinfer/PR-2530.md), [fix: include fp8_blockscale_gemm_90 in AOT jit-cache](../sources/prs/flashinfer/PR-2533.md), [fallback to fa2 (instead of fa3) for unsupported configuration (bf16 Q, Fp8 KV)](../sources/prs/flashinfer/PR-2536.md), [tests: bmm_fp8 for SM110](../sources/prs/flashinfer/PR-2538.md), [feat: cute dsl mmfp4 for blackwell](../sources/prs/flashinfer/PR-2540.md), [Add gen_gemm_sm100_module_cutlass_mxfp8 to jit-cache](../sources/prs/flashinfer/PR-2549.md), [fix: allow fmha_v2_prefill_deepseek on SM121 (DGX Spark)](../sources/prs/flashinfer/PR-2559.md), [fix: guard CUTLASS FMHA against SM12x and fix fmha_v2 SM121a check](../sources/prs/flashinfer/PR-2560.md), [feat: add is_sm12x_supported() helper for SM12x family detection](../sources/prs/flashinfer/PR-2574.md), [tests: add bias testing to nvfp4 moe](../sources/prs/flashinfer/PR-2585.md), [Perf: Optimize GDN decode pretranspose kernel for all batch sizes](../sources/prs/flashinfer/PR-2588.md), [support qk_nope_head_dim for 192 check for GLM-5](../sources/prs/flashinfer/PR-2607.md), [Ameyn/gdn bf16 tolerance parallel reduction](../sources/prs/flashinfer/PR-2610.md), [perf(gdn): optimize MTP kernel with ILP rows and SMEM v caching](../sources/prs/flashinfer/PR-2618.md), [feat: add pool+indices support to gated_delta_rule_decode_pretranspose (bf16 path) ](../sources/prs/flashinfer/PR-2619.md), [fix: trtllm_mxint4_block_scale_moe unit test to index output list](../sources/prs/flashinfer/PR-2627.md), [benchmark: Enable speculative decode microbenchmarking for paged decode](../sources/prs/flashinfer/PR-2628.md), [benchmark: Add MXFP4/MXFP8 quantization mode support to FP4 MoE benchmark](../sources/prs/flashinfer/PR-2635.md), [Enable sm120f compilation](../sources/prs/flashinfer/PR-2650.md), [fix: Add fused MOE and GEMM AOT modules for SM121](../sources/prs/flashinfer/PR-2654.md), [benchmarks: Add FP8 input / BF16 output in ragged prefill benchmark](../sources/prs/flashinfer/PR-2666.md), [feat(gdn): add BF16 state kernel with MTP support beyond T>4 with intermediate caching.](../sources/prs/flashinfer/PR-2679.md), [fix(jit): GEMM kernels produce NaN under concurrency — missing GDC flags cause PDL synchronization barriers to compile as no-ops](../sources/prs/flashinfer/PR-2716.md), [[gdn] support non-contiguous state for decoding](../sources/prs/flashinfer/PR-2727.md), [Support in-place update for `trtllm_fp8_block_scale_moe`](../sources/prs/flashinfer/PR-2739.md), [[Spark unit test debugging] Fix for tests/attention/test_trtllm_gen_mla.py](../sources/prs/flashinfer/PR-2750.md), [[Spark unit test debugging] Fix for tests/gemm/test_groupwise_scaled_gemm_fp8.py](../sources/prs/flashinfer/PR-2751.md), [perf: Performance tune cute dsl RMSNorm variants](../sources/prs/flashinfer/PR-2777.md), [fix(jit): enable GDC for CUTLASS GEMM PDL — SM100 flag only](../sources/prs/flashinfer/PR-2780.md), [tests: skip sliding window + fp8 to prevent hang in fmha_v2 unit tests](../sources/prs/flashinfer/PR-2781.md), [[fix] Bugfix 1367: fix VariableBlockSparseAttention buffer overflow by dynamically resizing kv_lens_buffer](../sources/prs/flashinfer/PR-2802.md), [feat(gdn): add padding index guard for bf16 decode kernel](../sources/prs/flashinfer/PR-2810.md), [[Spark unit test] Adjust tolerance for test_xqa, test_logits_processor](../sources/prs/flashinfer/PR-2828.md), [perf: Optimize GDN MTP decode kernel (v15) — eliminate ilp=1 fallback…](../sources/prs/flashinfer/PR-2842.md), [fix: fix cute dsl swap_ab tactic failure](../sources/prs/flashinfer/PR-2870.md), [fix: add cute dsl moe utils to AOT](../sources/prs/flashinfer/PR-2872.md), [[fix] bugfix 2856: Fix pre-allocated out shape check in trtllm_batch_decode_with_kv_cache_mla for q_len_per_req > 1](../sources/prs/flashinfer/PR-2876.md), [[NVIDIA] fix(jit): enable GDC for CUTLASS fused MoE PDL — prevent random crashes on SM12x](../sources/prs/flashinfer/PR-2913.md), [fix: Fix autotuner crash on meta-device tensor in trtllm_fp4_block_scale_routed_moe](../sources/prs/flashinfer/PR-2916.md), [feat: SM121 (GB10) tile filtering and autotuner robustness](../sources/prs/flashinfer/PR-2927.md), [CuTe DSL FP4 GEMM Heuristic](../sources/prs/flashinfer/PR-2940.md), [[Perf] Refactor MoE autotuning to set valid topk ids in routed MoE tuning](../sources/prs/flashinfer/PR-2942.md), [Only swizzle on v block scale; rename kv_block_scales to kv_cache_sf](../sources/prs/flashinfer/PR-2954.md), [Update NVSHMEM interface to use NVSHMEM4Py instead of custom bindings](../sources/prs/flashinfer/PR-2960.md), [test: skip unsupported mm_mxfp8 configurations on SM12x](../sources/prs/flashinfer/PR-2974.md), [feat(comm): add MOE Finalize/Reduction patterns to unified allreduce_fusion API](../sources/prs/flashinfer/PR-2982.md), [ Fix MXFP4/MXFP8 failures in SM120 FAST_BUILD and expand all_tiles[] ](../sources/prs/flashinfer/PR-2994.md), [[feat] Add blackwell GDN prefill kernel](../sources/prs/flashinfer/PR-3001.md), [fix: use sym_int64 for strides in rmsnorm CuTe DSL kernels to prevent int32 overflow](../sources/prs/flashinfer/PR-3007.md), [[chore] Install nvidia-cutlass-dsl[cu13] for cu130+](../sources/prs/flashinfer/PR-3017.md), [[feat] Add routing_replay_out support to MoE kernels and Python API](../sources/prs/flashinfer/PR-3024.md), [Fix/3170 dense blockscaled sm12x](../sources/prs/flashinfer/PR-3180.md), [test: enable bmm_mxfp8 cutlass backend coverage on SM12x](../sources/prs/flashinfer/PR-3183.md), [Include TinyGEMM into BF16 autotuner](../sources/prs/flashinfer/PR-3203.md), [feat(trace): embed runnable init() in every TraceTemplate](../sources/prs/flashinfer/PR-3221.md), [Ameyn/gdn bf16 dispatcher and 4d pool](../sources/prs/flashinfer/PR-3268.md), [fix(fmha_v2): fix FP8 V-scratch pipeline and varlen scheduler on SM90](../sources/prs/flashinfer/PR-3276.md), [Ep api design - Build Infra dependencies](../sources/prs/flashinfer/PR-3315.md), [feat: Separate QK/VO head dim dispatch for sm90 AOT](../sources/prs/flashinfer/PR-778.md), [bugfix: fix batch prefill attention kernel unittests](../sources/prs/flashinfer/PR-781.md), [bugfix: fix the behavior of mla plan function when provided with host tensors](../sources/prs/flashinfer/PR-816.md), [unittest: add MLA test cases where kv_len is evenly divided by page_size.](../sources/prs/flashinfer/PR-861.md), [perf: reduce torch.library dispatch overhead](../sources/prs/flashinfer/PR-968.md), [perf: Fix python API overhead when CUDAGraph is not enabled](../sources/prs/flashinfer/PR-969.md), [Update torch-xpu-ops commit pin](../sources/prs/pytorch/PR-144209.md), [[inductor][cpu] Fix bmm b_index for dynamic expressions in inductor autotuner](../sources/prs/pytorch/PR-144248.md), [Fix PythonMod printing](../sources/prs/pytorch/PR-144335.md), [Remove runtime dependency on packaging](../sources/prs/pytorch/PR-149125.md), [Add AOTI shim for _weight_int4pack_mm_cpu_tensor (#149031)](../sources/prs/pytorch/PR-149386.md), [op should NOT be static in aoti_torch_call_dispatcher](../sources/prs/pytorch/PR-149644.md), [Dont exclude constant_pad_nd in prologue fusion](../sources/prs/pytorch/PR-150145.md), [[inductor] Fix inductor windows linker error](../sources/prs/pytorch/PR-150447.md), [[Windows][inductor] fix blank space break windows file path](../sources/prs/pytorch/PR-150448.md), [[dynamo][super variable] Fix bug to use correct source](../sources/prs/pytorch/PR-152774.md), [[FlexAttention] Remove Old Constraint on lastdim strides](../sources/prs/pytorch/PR-153104.md), [Mark auto_functionalized HOPs as cacheable (#151194)](../sources/prs/pytorch/PR-153304.md), [[FlexAttention] explicilty create grad_q w/ strides](../sources/prs/pytorch/PR-153641.md), [[MPS] Switch Cholesky decomp to column wise](../sources/prs/pytorch/PR-158237.md), [Add warning about removed sm50 and sm60 arches](../sources/prs/pytorch/PR-158301.md), [[CD] CUDA 13 specific followup changes. Remove sm50-70 From CUDA 12.6 and CUDA 12.8 builds](../sources/prs/pytorch/PR-162455.md), [fix cpp extension distributed warning spew](../sources/prs/pytorch/PR-162764.md), [[Cherry Pick][Graph Partition] allow sharing default device context](../sources/prs/pytorch/PR-163097.md), [[Release 2.9] [cuDNN][SDPA][submodule] Roll-back cuDNN frontend upgrade, update Met…](../sources/prs/pytorch/PR-163265.md), [CUDA 13.0 Warning update for supported architectures](../sources/prs/pytorch/PR-163585.md), [fix pickling for BitwiseFn](../sources/prs/pytorch/PR-163861.md), [[SDPA] [MPS] Fixes regression in 2.8.0 for scaled_dot_product_attention using mps](../sources/prs/pytorch/PR-164364.md), [[Flex attention] Fix flex attention head broadcast](../sources/prs/pytorch/PR-164368.md), [[inductor] don't try to reorder loops for template](../sources/prs/pytorch/PR-166910.md), [[Dynamo] Don't guard data ptrs by default with mark_static_address](../sources/prs/pytorch/PR-166913.md), [[Inductor] No longer throw error in bmm out_dtype lowering due to tem…](../sources/prs/pytorch/PR-166922.md), [[GraphPartition] cache get_free_symbol_uses (#166338)](../sources/prs/pytorch/PR-166994.md), [[cuDNN][SDPA] Check-in test for #166211](../sources/prs/pytorch/PR-167121.md), [[Inductor] ExternKernelBenchmarkRequest best attempt](../sources/prs/pytorch/PR-170246.md), [[flex_attention] adds support for low precision K/V inputs in compiled mode with GPU](../sources/prs/pytorch/PR-170486.md), [[cherry-pick] Fix vllm issue for flex (#170499)](../sources/prs/pytorch/PR-170555.md), [Avoid closing random file handles in Inductor](../sources/prs/pytorch/PR-171150.md), [[xpu][fix][inductor] fallback bfloat16 atomics to eager](../sources/prs/pytorch/PR-171247.md), [[MPS] Fix 2-pass SDPA memory corruption by forcing float accumulators](../sources/prs/pytorch/PR-175580.md), [[CI] Update inductor CI jobs to CUDA 13.0](../sources/prs/pytorch/PR-175826.md), [[Inductor] Reject non-contiguous subnode fusion in mix-order reduction.](../sources/prs/pytorch/PR-176410.md), [[inductor] Fix Identity comparability and evalf recursion](../sources/prs/pytorch/PR-176783.md), [[Inductor] Don't unfuse addmm for bf16/fp16 to avoid precision loss](../sources/prs/pytorch/PR-177144.md), [[Inductor][MPS] Fix half-precision type mismatches in Metal shader codegen (#176436)](../sources/prs/pytorch/PR-177193.md), [[MPS] fix compiling of SDPA producing nan results](../sources/prs/pytorch/PR-178009.md), [feat: Add FP4 (E2M1) KV Cache Support with Quantization Utilities for MLA](../sources/prs/sglang/PR-10078.md), [[Feature] Add MLAProcess for DeepSeek MLA on NPU](../sources/prs/sglang/PR-10130.md), [Enable native ModelOpt quantization support (3/3)](../sources/prs/sglang/PR-10154.md), [Fix chunked prefix cache for nvfp4](../sources/prs/sglang/PR-10180.md), [Add support for bf16 x bf16 cutlass fused MoE](../sources/prs/sglang/PR-10275.md), [support qwen3_next blackwell](../sources/prs/sglang/PR-10403.md), [Fix cutlass moe accuracy drop caused by attention UB from DP padding mode](../sources/prs/sglang/PR-10414.md), [Support single batch overlap](../sources/prs/sglang/PR-10422.md), [Fix correction bias undefined behavior for nvfp4 models](../sources/prs/sglang/PR-10426.md), [feat: add dsv3 fp4 cutlass moe etp ut](../sources/prs/sglang/PR-10433.md), [Cache the result of `is_blackwell` platform check](../sources/prs/sglang/PR-10498.md), [Enable trtllm mla prefix extend](../sources/prs/sglang/PR-10526.md), [Fix bias handling in TritonMoeQuantInfo within quantization/mxfp4.py](../sources/prs/sglang/PR-10579.md), [support qwen3-next-fp8 deepep](../sources/prs/sglang/PR-10622.md), [[Auto Sync] Update modelopt_quant.py (20250920)](../sources/prs/sglang/PR-10688.md), [Unify SGL Kernel Releases](../sources/prs/sglang/PR-10701.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [Fuse quantize and rope in trtllm_mla MTP](../sources/prs/sglang/PR-10779.md), [[2/2] Support MHA prefill with FlashAttention 4.](../sources/prs/sglang/PR-10937.md), [Quick Fix: fix Qwen3-VL launch failure caused by MRotaryEmbedding arg](../sources/prs/sglang/PR-10985.md), [chore: upgrade sgl-kernel 0.3.13](../sources/prs/sglang/PR-11056.md), [Fix DSR1 accuracy for flashinfer_trtllm MoE with FP8 quantization](../sources/prs/sglang/PR-11081.md), [[NVIDIA] Add new SMs support for Spark & Thor](../sources/prs/sglang/PR-11287.md), [[AMD] Clean up vllm dependencies in moe_runner/triton.py](../sources/prs/sglang/PR-11349.md), [[sgl-kernel][1/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-11432.md), [[NVIDIA] FA3/FA4 Fix ](../sources/prs/sglang/PR-11606.md), [Support shared experts overlap in cutlass moe](../sources/prs/sglang/PR-11611.md), [[DeepseekV32] Enable flashmla_prefill kernel with fp8 kvcache](../sources/prs/sglang/PR-11655.md), [Use trtllm_mla decode kernel for draft extend in speculative decoding](../sources/prs/sglang/PR-11664.md), [Support running FP4 Deepseek on SM120.](../sources/prs/sglang/PR-11708.md), [[sgl-kernel] support flashmla libtorch](../sources/prs/sglang/PR-11717.md), [Change bf16 to fp8 for some gemms in attention for DeepSeek ckpt v2](../sources/prs/sglang/PR-11805.md), [Use cutlass fp4 gemm by default](../sources/prs/sglang/PR-11813.md), [Support nvidia/NVIDIA-Nemotron-Nano-9B-v2-FP8/NVFP4](../sources/prs/sglang/PR-11866.md), [DeepSeek-V3.2: Add Adaptive MHA Attention Pathway for Short-Sequence Prefill](../sources/prs/sglang/PR-11892.md), [chore: upgrade flashinfer 0.4.1](../sources/prs/sglang/PR-11933.md), [Feature/nano v2 offline modelopt fp8 and nvfp4](../sources/prs/sglang/PR-12018.md), [(1/n)support context parallel with deepseekv3.2-DSA](../sources/prs/sglang/PR-12065.md), [[Ascend] qwen optimization](../sources/prs/sglang/PR-12078.md), [[Ascend][feature] support L1+ L2 radixcache on ascend](../sources/prs/sglang/PR-12214.md), [[DeepseekV32]: use `_concat_mla_absorb_q_general` to replace `torch.cat`](../sources/prs/sglang/PR-12215.md), [[hotfix] missing `w13_weight_fp8` and `w2_weight_fp8` in UE8M0 requantization](../sources/prs/sglang/PR-12259.md), [[Deepseek V3.2] Enable flashmla_auto with MTP](../sources/prs/sglang/PR-12294.md), [fix seqlen bug for trtllm_mla's draft_extend](../sources/prs/sglang/PR-12295.md), [fix: Llama 4 BF16 load on Blackwell](../sources/prs/sglang/PR-12308.md), [fix: llama 4 + trtllm gen + fp8 kv cache incompatibility](../sources/prs/sglang/PR-12347.md), [Replace [silu_and_mul_]scaled_fp4_group_quant by Flashinfer equivalent](../sources/prs/sglang/PR-12376.md), [perf: trtllm mla performance minor improvements](../sources/prs/sglang/PR-12435.md), [Use sgl fp4 quant kernel by default](../sources/prs/sglang/PR-12482.md), [[Ascend] Support enable-mixed-chunk in non-MLA scenarios](../sources/prs/sglang/PR-12491.md), [chore: upgrade flashinfer 0.5.0](../sources/prs/sglang/PR-12523.md), [Enable Flashinfer TRTLLM-GEN-MoE FP8 blockwise kernel for Qwen3-Next on Blackwell](../sources/prs/sglang/PR-12543.md), [[CPU] Fix MoE layer support for DeepSeek-OCR models](../sources/prs/sglang/PR-12555.md), [feat: Add FP4 (E2M1) KV Cache Support for MHA](../sources/prs/sglang/PR-12612.md), [[NVIDIA] Fix wrong symmetric sizes for fp4 cases](../sources/prs/sglang/PR-12640.md), [[sgl-kernel][5/N]Support Expert Specialization Grouped GEMM](../sources/prs/sglang/PR-12666.md), [[fix] Only enable flashinfer all reduce fusion by default for single-node servers](../sources/prs/sglang/PR-12724.md), [[Bugfix] Fix illegal memory access](../sources/prs/sglang/PR-12758.md), [[Ascend] support Kimi-K2-Thinking](../sources/prs/sglang/PR-12759.md), [Update dsv3 quantization auto setting for sm100](../sources/prs/sglang/PR-12778.md), [ignore the deepgemm check when the model weight with nvfp4 and moe ba…](../sources/prs/sglang/PR-12782.md), [[DeepSeek-V3.2][NSA] Enable MHA Pathway for Short Sequence Prefill on B200 (SM100)](../sources/prs/sglang/PR-12788.md), [[Deepseek V3.2] Only skip Indexer logits computation when is_extend_without_speculative](../sources/prs/sglang/PR-12816.md), [Apply moe_reduce_sum kernel for fused_marlin_moe](../sources/prs/sglang/PR-12888.md), [[Deepseek V3.2] Use torch.compile to speed up torch.cat in nsa](../sources/prs/sglang/PR-13022.md), [Support moe topk sigmoid kernel](../sources/prs/sglang/PR-13049.md), [[sgl-kernel] support custom fp8 flashmla kernel](../sources/prs/sglang/PR-13087.md), [support mtp with deepseek r1 nvfp4 model](../sources/prs/sglang/PR-13115.md), [Aiter fp8 kv cache](../sources/prs/sglang/PR-13147.md), [Support internvl on Blackwell (which doesn't support fa3): add `SingletonCache` support to Vision{Sdpa|Triton|Ascend}Attention](../sources/prs/sglang/PR-13151.md), [[NPU]Optimization of `forward_npu` for `UnquantizedFusedMoEMethod`](../sources/prs/sglang/PR-13158.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [diffusion: enable fa4 for blackwell](../sources/prs/sglang/PR-13263.md), [[NVIDIA] Fix broken fp8 MoE of deepseek v3](../sources/prs/sglang/PR-13264.md), [[NVIDIA] Fix use case of SGLANG_ENABLE_FLASHINFER_GEMM](../sources/prs/sglang/PR-13274.md), [Support weight update for blackwell DeepGEMM](../sources/prs/sglang/PR-13324.md), [Flashinfer TRTLLM-GEN-MoE + Qwen3](../sources/prs/sglang/PR-13489.md), [Fix target MLA with eagle3 support for PD disaggregation](../sources/prs/sglang/PR-13555.md), [[BugFix] fix prefixcache performance and accuracy on ascend](../sources/prs/sglang/PR-13573.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [[DeepSeekV3.2] Enable pure TP & Partial DP Attention](../sources/prs/sglang/PR-13646.md), [Fix EPLB + FP4 Quantization Compatibility Issue](../sources/prs/sglang/PR-13715.md), [[bugfix] fix TBO crashes when attn_tp_size > 1](../sources/prs/sglang/PR-13730.md), [[sgl-kernel][Feat][B200][1/N]Support MXFP8 Grouped GEMM in Blackwell](../sources/prs/sglang/PR-13731.md), [fix trtllm mla spec](../sources/prs/sglang/PR-13738.md), [[AMD] Support --enable-aiter-allreduce-fusion on AMD GPUs](../sources/prs/sglang/PR-13747.md), [[chore]Upgrade flashinfer to 0.5.3](../sources/prs/sglang/PR-13751.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [[NVIDIA] Enable TRTLLM BF16 MoE on Blackwell GPUs](../sources/prs/sglang/PR-13798.md), [update flashinfer_cubin==0.5.3](../sources/prs/sglang/PR-13848.md), [[BugFix] fix outplace_fused_experts missing is_gated](../sources/prs/sglang/PR-13864.md), [Feat: GLM-4.6 supports shared experts fusion](../sources/prs/sglang/PR-13873.md), [Fix update weight error for blackwell DeepGEMM](../sources/prs/sglang/PR-13910.md), [[DeepSeek v3.2] opt Context Parallelism: support fused moe, multi batch and fp8 kvcache](../sources/prs/sglang/PR-13959.md), [Use trtllm mha decode kernel for target_verify in speculative decoding](../sources/prs/sglang/PR-13976.md), [Support KTransformers for Qwen3-VL moe](../sources/prs/sglang/PR-13983.md), [Fix flashinfer cutlass MoE output shape for non-FP4-packed inputs](../sources/prs/sglang/PR-14028.md), [[LoRA][III] Add LoRA support for MoE layers and enable TP](../sources/prs/sglang/PR-14105.md), [Add new moe wna16 marlin gemm](../sources/prs/sglang/PR-14122.md), [Apply new moe wna16 marlin gemm](../sources/prs/sglang/PR-14125.md), [Apply new moe align block size kernel](../sources/prs/sglang/PR-14134.md), [Support checking fp8 params in weight_checker](../sources/prs/sglang/PR-14147.md), [fix: Increase FlashInfer workspace size for Qwen3VL models](../sources/prs/sglang/PR-14173.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[bug fix] fix ima with get_mla_kv_buffer_kernel overflow](../sources/prs/sglang/PR-14224.md), [Tiny use trtllm_mha as default when possible](../sources/prs/sglang/PR-14291.md), [[Fix] add block size logic for sm120 smem size](../sources/prs/sglang/PR-14311.md), [[FIX] trtllm-moe-fp4-renorm for Qwen series models](../sources/prs/sglang/PR-14350.md), [Support FP8 MLA prefill and 128k context.](../sources/prs/sglang/PR-14395.md), [[NPU] perf update with kvcache nz & w4a8 quant](../sources/prs/sglang/PR-14423.md), [Add Mistral Large 3 Eagle Support](../sources/prs/sglang/PR-14466.md), [Mistral Large 3 NVFP4 support](../sources/prs/sglang/PR-14485.md), [[diffusion] kernel fusion: gated residual layernorm scale shift and layernorm scale shift kernel fusion for Qwen-Image, WAN and HunyuanVideo](../sources/prs/sglang/PR-14717.md), [[NPU][eagle3] support qwen eagle3 on NPU](../sources/prs/sglang/PR-14820.md), [Apply back moe_sum_reduce for fused_marlin_moe](../sources/prs/sglang/PR-14829.md), [fix: trtllm mha attention auto-selection on sm120](../sources/prs/sglang/PR-14842.md), [Fix dsv3 dp accuracy issue when using bf16-kv](../sources/prs/sglang/PR-14897.md), [Fix accuracy issue when using a16w16 mla_decode_fwd](../sources/prs/sglang/PR-14936.md), [[AMD] Support fused_rms_mxfp4_quant in the prefill stage for DeepSeek-R1-MXFP4](../sources/prs/sglang/PR-14975.md), [add transformers version validation for glm-4.6v moe models](../sources/prs/sglang/PR-14998.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [fix(attention): Prevent trtllm_mha auto-selection with eagle3 speculative decoding](../sources/prs/sglang/PR-15127.md), [[sgl-kernel][1/2] Fused qk_norm_rope for GLM4.6](../sources/prs/sglang/PR-15141.md), [[NVIDIA] upstream FA4](../sources/prs/sglang/PR-15182.md), [[NVIDIA] Fixes for NVFP4 all-gather with spec decoding](../sources/prs/sglang/PR-15280.md), [[Fix] A followup fix for TRTLLM BF16 MoE](../sources/prs/sglang/PR-15303.md), [Fix the accuracy issue when running mxfp4 dsv3 model and enable ep](../sources/prs/sglang/PR-15304.md), [feat: support bitsandbytes quantization algorithm](../sources/prs/sglang/PR-15325.md), [[distributed] Clean up MoE groups in destroy_model_parallel](../sources/prs/sglang/PR-15345.md), [[Tiny]Add warning for deepgemm on Blackwell](../sources/prs/sglang/PR-15352.md), [[NPU]mindspore model support moe](../sources/prs/sglang/PR-15363.md), [[NPU]DeepSeek-V3.2 support npu mlaprolog](../sources/prs/sglang/PR-15381.md), [[diffusion] Add Sage Attention 3 Support for sm 120 (RTX5090)](../sources/prs/sglang/PR-15382.md), [Super tiny add moe_ep_rank to prometheus labels](../sources/prs/sglang/PR-15407.md), [Flashinfer MOE FP8 support for Mistral Large 3.](../sources/prs/sglang/PR-15422.md), [Optimize MiMo-V2-Flash by flashinfer fused allreduce](../sources/prs/sglang/PR-15464.md), [[Perf] Add Flashinfer DeepGEMM SM90 for SwapAB Optimization](../sources/prs/sglang/PR-15514.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [Optimize Bailing-MoE with FlashInfer Fused All-Reduce](../sources/prs/sglang/PR-15526.md), [MoE: Skip SiLU/GELU activation for masked experts](../sources/prs/sglang/PR-15539.md), [Update flashinfer to 0.6.1](../sources/prs/sglang/PR-15551.md), [[sgl-kernel] Streamline kernel size report (Top 20 only) and clean up](../sources/prs/sglang/PR-15552.md), [Fix BatchMLAPagedAttentionWrapper query/qo_inptr mismatch for EAGLE](../sources/prs/sglang/PR-15601.md), [[jit-kernel] Add CuTe DSL GDN Decode Kernel](../sources/prs/sglang/PR-15631.md), [Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-15712.md), [[Perf] Eliminate the slice op for Flashinfer `trtllm_fp4_block_scale_moe`](../sources/prs/sglang/PR-15731.md), [Fix GLM-4.7 MoE Detector complex JSON Schema type parsing](../sources/prs/sglang/PR-15753.md), [Fix: Handle empty func_name and None values in GLM MoE detectors](../sources/prs/sglang/PR-15754.md), [[Feature] JIT Fused QK norm + qk norm clean up](../sources/prs/sglang/PR-15835.md), [[JIT kernel] Apply jit per_tensor_quant_fp8 kernel](../sources/prs/sglang/PR-15836.md), [[diffusion] model: support TurboWan2.1-T2V-1.3B/14B SLA](../sources/prs/sglang/PR-15888.md), [[fix]deepgemm precompile when warmup](../sources/prs/sglang/PR-15891.md), [Bugfix for ds-vl2](../sources/prs/sglang/PR-15894.md), [[NPU] NZ for non-quantized MOE, Qwen3 MOE double memory consumption fix](../sources/prs/sglang/PR-15904.md), [ Add tuned triton==3.5.1 h200 tp2, tp4 for qwen 3 next](../sources/prs/sglang/PR-15948.md), [Tiny fix cannot launch nvfp4 checkpoint with bf16 kv cache](../sources/prs/sglang/PR-15986.md), [[Performance] Force split_k=1 for MXFP4 Triton kernels on Hopper](../sources/prs/sglang/PR-16014.md), [Support fa4 decoding](../sources/prs/sglang/PR-16034.md), [optimize get_topk_ragged by fusing get k and k_scale triton kernel](../sources/prs/sglang/PR-16043.md), [[Diffusion] Flux support flashinfer rope](../sources/prs/sglang/PR-16055.md), [enhance accuracy for model kimi-vl-instruct-a3b](../sources/prs/sglang/PR-16076.md), [fix layer intermediate size](../sources/prs/sglang/PR-16084.md), [[Diffusion] Zimage opt with qknorm and flashinfer rope](../sources/prs/sglang/PR-16161.md), [[Feature] add aligned_vector type for JIT kernel](../sources/prs/sglang/PR-16162.md), [[VLM] Adopt jit qk_norm kernel in VLM](../sources/prs/sglang/PR-16171.md), [[NemotronH] Add latent MoE support](../sources/prs/sglang/PR-16227.md), [[Fix] Only add SM90 and SM100 to check for auto-enabling TRT Allreduce Fusion](../sources/prs/sglang/PR-16283.md), [[diffusion] Fix RuntimeError in SageAttention3 on Nvidia Blackwell with Qwen-Image](../sources/prs/sglang/PR-16335.md), [[Fix]Fix FA3 Performance in Diffusion Model ](../sources/prs/sglang/PR-16382.md), [Fix FP8 MoE NaN with DeepGEMM on Blackwell](../sources/prs/sglang/PR-16622.md), [[Rework] Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-16723.md), [[AMD] Support redundant expert with a2a moe in gfx95x.](../sources/prs/sglang/PR-16791.md), [[Fix] `flashinfer_trtllm` `intermediate_size` assertion with Qwen3 + TP=8](../sources/prs/sglang/PR-16824.md), [Support mxint4 flashinfer_trtllm moe gemm](../sources/prs/sglang/PR-16892.md), [[DeepSeek v3.2] Opt MTP decode cuda batch sizes and nsa implementation](../sources/prs/sglang/PR-16961.md), [[NPU]bugfix: fix for dsv3.2 and dsvl2](../sources/prs/sglang/PR-17007.md), [[MUSA][2/N] sgl-kernel build](../sources/prs/sglang/PR-17053.md), [Optimize GDN decode for Qwen3 Next](../sources/prs/sglang/PR-17094.md), [[diffusion] fix: fix using upstream flash_attn on blackwell](../sources/prs/sglang/PR-17111.md), [Enable XQA for SM90 and SM120](../sources/prs/sglang/PR-17115.md), [Inclusion of nvfp4 blockscale in EPLB Rebalance](../sources/prs/sglang/PR-17158.md), [[Fix] GLM 4.7 + NVFP4 + MTP](../sources/prs/sglang/PR-17166.md), [[GLM 4.7] Add RTX 6000 Pro aka sm120](../sources/prs/sglang/PR-17235.md), [[New Model] GLM4.7-Flash](../sources/prs/sglang/PR-17247.md), [[FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/sglang/PR-17300.md), [Disable mla persistent kernel when not using fp8 kv_cache](../sources/prs/sglang/PR-17327.md), [Move fa4 from sgl-kernel to jit kernel](../sources/prs/sglang/PR-17353.md), [Add mxfp8 support for online quantization, Triton dense linear, and CUTLASS MoE](../sources/prs/sglang/PR-17449.md), [[NPU] enhance accuracy for model kimi-vl-a3b-instruct](../sources/prs/sglang/PR-17480.md), [Kernel: optimize decoding metadata in NSA multi-spec backend with fused kernels](../sources/prs/sglang/PR-17554.md), [[hotfix] Reenable all reduce fusion on sm100](../sources/prs/sglang/PR-17591.md), [[feat] Support nvfp4 quantized model of Qwen3-Next](../sources/prs/sglang/PR-17627.md), [Upgrade transformers==5.3.0](../sources/prs/sglang/PR-17784.md), [fix(quantization): add sgl_kernel fallback for FP4 quantize on Blackwell GPUs](../sources/prs/sglang/PR-17816.md), [Feature/support longcat flash lite](../sources/prs/sglang/PR-17838.md), [[Move sgl-kernel Kernel to JIT] Add JIT concat MLA kernels](../sources/prs/sglang/PR-17889.md), [Skipped warning on sm100](../sources/prs/sglang/PR-18000.md), [[Bugfix] Fix Mistral Large 3 NVFP4 TRTLLM MoE](../sources/prs/sglang/PR-18065.md), [Feat/add fi selective state update kernel call](../sources/prs/sglang/PR-18070.md), [[Diffsuion & JIT_kernel] QKNorm cross heads kernel](../sources/prs/sglang/PR-18073.md), [Fix nvfp4 weight update](../sources/prs/sglang/PR-18085.md), [[Blackwell] Make mxint4 flashinfer_trtllm moe gemm set by default on blackwell](../sources/prs/sglang/PR-18136.md), [[ModelOpt] Fix broken Qwen3-235B-A22B-Instruct-2507-NVFP4 launch](../sources/prs/sglang/PR-18189.md), [[ModelOPT] Support Qwen 3 Next Coder NVFP4](../sources/prs/sglang/PR-18224.md), [Support Qwen3 MoE context parallel](../sources/prs/sglang/PR-18233.md), [[ROCm] Optimize Deepseek R1 on MI300X](../sources/prs/sglang/PR-18242.md), [[Hicache & JIT_kernel] Support page first layout & mla jit kernel](../sources/prs/sglang/PR-18311.md), [[AMD] Support Qwen3-Coder-Next on AMD platform](../sources/prs/sglang/PR-18355.md), [[MUSA][10/N] Add GGUF support](../sources/prs/sglang/PR-18357.md), [feat(gdn): add FlashInfer K-last SSM layout support for GDN prefill and decode for Hopper](../sources/prs/sglang/PR-18361.md), [[Kimi-K2.5] Fix NVFP4 Kimi-K2.5 weight mapping and exclude list](../sources/prs/sglang/PR-18370.md), [Nsa trtllm mla sparse fp8 support with Deepseek v3.2 NVFP4](../sources/prs/sglang/PR-18389.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [feat: add FA4 SM90 paged KV decode support & update attention docs](../sources/prs/sglang/PR-18442.md), [Tilelang sparse decode fwd for dsv32 mi355](../sources/prs/sglang/PR-18488.md), [[FIX] Correct JIT kernel compilation on newer GPUs with outdated driver metadata.](../sources/prs/sglang/PR-18496.md), [Fp8 prefill attn kernel integration](../sources/prs/sglang/PR-18528.md), [[AMD] Fix accuracy issue when running TP4 dsv3 model with mtp](../sources/prs/sglang/PR-18607.md), [[AMD] DSR1/V3 use fp8 bmm in MLA for MI300X](../sources/prs/sglang/PR-18624.md), [[sglang-miles] True on-policy training support for FSDP2](../sources/prs/sglang/PR-18639.md), [use flashinfer.sampling](../sources/prs/sglang/PR-18696.md), [[RL] Support per-layer mixed FP8/BF16 serving for FP8 checkpoints](../sources/prs/sglang/PR-18742.md), [fix: update Blackwell log/error messages to include SM12x](../sources/prs/sglang/PR-18751.md), [[diffusion] Diffusion norm fusion for z-image](../sources/prs/sglang/PR-18762.md), [fix: add SM110 (Jetson AGX Thor) to Blackwell capability check](../sources/prs/sglang/PR-18787.md), [Migrate renorm kernels from sgl-kernel to FlashInfer JIT](../sources/prs/sglang/PR-18854.md), [[Perf] ~9.5x faster Blackwell MXFP4 MoE weight loading](../sources/prs/sglang/PR-18858.md), [Migrate norm kernels to FlashInfer JIT implementation](../sources/prs/sglang/PR-18871.md), [[sgl-kernel] rebase FlashMLA 0217](../sources/prs/sglang/PR-18902.md), [Fix NSA FP8 KV cache path for both-trtllm MHA one-shot](../sources/prs/sglang/PR-18931.md), [[Qwen3.5] Enable nvfp4 checkpoint](../sources/prs/sglang/PR-18937.md), [[Sarvam] Add inference support for Sarvam MoE LLMs](../sources/prs/sglang/PR-18938.md), [[jit_kernel] Add fused_qknorm_rope JIT kernel](../sources/prs/sglang/PR-19059.md), [Support skip-softmax attention](../sources/prs/sglang/PR-19089.md), [feat: Support MXFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-19143.md), [[DeepSeek-V3.2][JIT-kernel] Support nsa fuse store indexer k cache](../sources/prs/sglang/PR-19148.md), [[NVIDIA] Integrate FlashInfer decode kernel (Blackwell) for Qwen3.5](../sources/prs/sglang/PR-19150.md), [Adjust padding size to improve triton_kernels moe performance](../sources/prs/sglang/PR-19174.md), [[AMD] Fix accuracy while using --enable-dp-attention](../sources/prs/sglang/PR-19247.md), [Fix nightly Mistral-Large-3 NVFP4 accuracy threshold](../sources/prs/sglang/PR-19402.md), [[AMD] Fix weight load shape mismatch for amd dsr1 0528 mxfp4](../sources/prs/sglang/PR-19425.md), [[Feature] add feature mla_ag_after_qlora for dsv3.2](../sources/prs/sglang/PR-19428.md), [Fix/nemotron mtp quantaized](../sources/prs/sglang/PR-19433.md), [[Kernel Slimming] Migrate NVFP4 kernels to JIT](../sources/prs/sglang/PR-19437.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [[NPU] bugs fix for Deepseek models](../sources/prs/sglang/PR-19544.md), [[diffusion][llm] macOS support](../sources/prs/sglang/PR-19549.md), [[miles] fix for glm5](../sources/prs/sglang/PR-19634.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Support `triton_kernels` for GPT-OSS on SM120](../sources/prs/sglang/PR-19718.md), [Various SM120 improvements](../sources/prs/sglang/PR-19721.md), [[SGLang-Diffusion] Fix custom op fake impl missing eps default for torch.compile](../sources/prs/sglang/PR-19725.md), [Add compile-time 256-bit vector guard for pre-Blackwell](../sources/prs/sglang/PR-19794.md), [[JIT Kernel][Feature] Support JIT custom all reduce (rewrite as v2)](../sources/prs/sglang/PR-19880.md), [Use TRTLLM allreduce fusion for Qwen 3.5](../sources/prs/sglang/PR-19889.md), [Fix MLA decode path returning unwritten (padded) rows](../sources/prs/sglang/PR-19902.md), [[AMD] Fix Tensor Memory Aliasing ](../sources/prs/sglang/PR-19928.md), [[AMD] Fix FP8 assertion failure in aiter MLA decode by falling back to self.k_scale](../sources/prs/sglang/PR-19935.md), [[AMD] Tilelang sparse fwd for dsv32 mi355/mi300](../sources/prs/sglang/PR-19945.md), [[JIT Kernel] Reland NVFP4 kernels to JIT](../sources/prs/sglang/PR-20012.md), [[Bugfix] Work around FlashInfer unified transport issue on GB](../sources/prs/sglang/PR-20039.md), [Fix SM120 `triton_kernels` MXFP4 `block_k` for GPT-OSS](../sources/prs/sglang/PR-20040.md), [MiniMax-M2.5 - Support dp attention, dp reduce scatter, FP4 all gather, AR fusion in prepare_attn](../sources/prs/sglang/PR-20067.md), [Fix streaming session with paged KV cache (SWA/MLA)](../sources/prs/sglang/PR-20070.md), [Enable modelopt quantized FLUX deployment](../sources/prs/sglang/PR-20082.md), [[V32/GLM5] Change default setting of V32 nvfp4 on TP4](../sources/prs/sglang/PR-20086.md), [[diffusion] fix bug of copy_if](../sources/prs/sglang/PR-20094.md), [[diffusion] Support nvfp4 for Flux.2](../sources/prs/sglang/PR-20137.md), [[AMD] Fp8 prefill integration with radix cache path for dpsk models](../sources/prs/sglang/PR-20187.md), [[4/n jit_kernel restruct] speed up CI tests and add benchmark workflow](../sources/prs/sglang/PR-20268.md), [[AMD] Add 4-GPU test suite for MI325 runners](../sources/prs/sglang/PR-20294.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [[Fix] Add fallback for flashinfer allreduce fusion](../sources/prs/sglang/PR-20384.md), [[NVIDIA] Enable fp8 flashinfer_trtllm_routed MoE for MiniMax-M2.5](../sources/prs/sglang/PR-20394.md), [[AMD][Bug-fix] Fix gpu fault when run the test with dp-attention-enabled and max-concurrency is over 256](../sources/prs/sglang/PR-20399.md), [[Model] Support Nemotron 3 Super NVFP4](../sources/prs/sglang/PR-20407.md), [[AMD][AITER] Guard _use_mla_ps_kernel with self.use_mla in draft_extend_v2 paths](../sources/prs/sglang/PR-20409.md), [[GDN] Add benchmark for sglang gdn prefill](../sources/prs/sglang/PR-20428.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [[Kernel] Fuse temperature + softmax in sampling for decode speedup](../sources/prs/sglang/PR-20501.md), [[Diffusion] Clean upstream fa3 in hopper](../sources/prs/sglang/PR-20576.md), [Use Flashinfer for target_verify in GDN model for SM120](../sources/prs/sglang/PR-20604.md), [FIX: (NSA) Compute topk_indices_offset when NSA prefill flashmla_sparse is used with FP8 KV cache](../sources/prs/sglang/PR-20606.md), [[Diffusion] Add a benchmark for rmsnorm/fuse_add_rmsnorm](../sources/prs/sglang/PR-20632.md), [Fix(jit): support rmsnorm for hidden_size in {64, 128, 256}](../sources/prs/sglang/PR-20661.md), [[Feature][JIT Kernel] Fused TP QK norm For Minimax](../sources/prs/sglang/PR-20673.md), [[Diffusion] Fix compile graph broken by flashinfer rope](../sources/prs/sglang/PR-20699.md), [Add Mistral Small 4 (Pixtral) support](../sources/prs/sglang/PR-20708.md), [Use FlashInfer tinygemm for GPT-OSS MoE router on SM90+](../sources/prs/sglang/PR-20755.md), [fix: guard configure_deep_gemm_num_sms when JIT disabled](../sources/prs/sglang/PR-20868.md), [[JIT Kernel] Fix NVFP4 multi-arch compilation failure](../sources/prs/sglang/PR-20874.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Qwen3.5] Fuse split/reshape/cat ops in GDN projection with Triton kernel](../sources/prs/sglang/PR-21019.md), [[Chore] Clean up JIT compilation flags](../sources/prs/sglang/PR-21022.md), [fix: wrap _import_static_state in inference_mode to fix resume on Blackwell](../sources/prs/sglang/PR-21035.md), [perf: precompute FA3 scheduler_metadata to eliminate per-layer prepare_varlen_num_blocks](../sources/prs/sglang/PR-21104.md), [ci: remove IS_BLACKWELL env var; auto-detect Blackwell](../sources/prs/sglang/PR-21118.md), [[Not-Merge][AMD] GLM-5 performance optimization](../sources/prs/sglang/PR-21166.md), [[Whisper] Enable CUDA graph support and timestamp for whisper model](../sources/prs/sglang/PR-21190.md), [[NPU] bugfix for import sgl-kernel error](../sources/prs/sglang/PR-21200.md), [[KDA] Support CuTeDSL KDA decode kernel](../sources/prs/sglang/PR-21203.md), [[AMD]: Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5…](../sources/prs/sglang/PR-21213.md), [[refactor] Clean up duplicate flashinfer trtllm moe code](../sources/prs/sglang/PR-21233.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[NVIDIA] Enable FP4 flashinfer trtllm routed moe](../sources/prs/sglang/PR-21240.md), [P2P Weight Update features for miles ](../sources/prs/sglang/PR-21278.md), [[RL] Support mxfp8 DeepSeek V3](../sources/prs/sglang/PR-21280.md), [[MUSA] apply_vocab_mask support musa device](../sources/prs/sglang/PR-21296.md), [CUTLASS NVFP4 GEMM improvement of SM120](../sources/prs/sglang/PR-21314.md), [[Kernel] Support FlashInfer TRTLLM-Gen fused MoE for non-gated FP4 & FP8 (Nemotron)](../sources/prs/sglang/PR-21321.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Add dedicated FlashInferCuteDslMoE layer for standard-path FP4 MoE](../sources/prs/sglang/PR-21339.md), [[GDN] Fuse GDN kkt + solve_tril into one kernel](../sources/prs/sglang/PR-21411.md), [[Bugfix] Lazy-import CuteDSL KDA kernel to fix AMD/ROCm startup crash](../sources/prs/sglang/PR-21428.md), [fix nemotron capture for non attention layers](../sources/prs/sglang/PR-21436.md), [[Diffusion] Add qknorm rope fuse kernel](../sources/prs/sglang/PR-21440.md), [Add explicit disable flag for FlashInfer allreduce fusion](../sources/prs/sglang/PR-21446.md), [fix: piecewise_cuda_graph get correct qo_indptr](../sources/prs/sglang/PR-21452.md), [Migrate all callers from /get_server_info to /server_info](../sources/prs/sglang/PR-21463.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [test: point DSV3 int8 MLA CI models to lmsys Hugging Face org](../sources/prs/sglang/PR-21561.md), [[FlashInver v0.6.7] Integrate flashinfer_trtllm mxfp8 gemm](../sources/prs/sglang/PR-21576.md), [Change default mm-attention backend from triton_attn to fa4](../sources/prs/sglang/PR-21595.md), [fix: TRT-LLM MHA CUDA illegal address with EAGLE v2 + DP attention](../sources/prs/sglang/PR-21649.md), [[jit_kernel] Optimize fused_qknorm_rope: deduplicate sincosf for interleave RoPE ](../sources/prs/sglang/PR-21654.md), [[AMD] Use tgemm.mm for MoEGate router gemm in deepseek_v2.py](../sources/prs/sglang/PR-21657.md), [[XPU] Enable qwen3.5 on XPU](../sources/prs/sglang/PR-21668.md), [[AMD] Add GLM-5-FP8 nightly performance benchmarks for MI30x and MI35x](../sources/prs/sglang/PR-21710.md), [Harden FlashInfer FP4 imports in standard dispatcher](../sources/prs/sglang/PR-21776.md), [[Fix] Fall back to triton MOE for GPT-OSS on Blackwell with driver >= 595](../sources/prs/sglang/PR-21780.md), [[DSA] Support trtllm sparse mla kernel for prefill batches ](../sources/prs/sglang/PR-21783.md), [Remove redundant test_moe_eval_accuracy_large](../sources/prs/sglang/PR-21787.md), [[Feature] JIT rmsnorm update (with claude)](../sources/prs/sglang/PR-21834.md), [ [GDN] Remove FlashInfer GDN decode + no_buffer guard and default to FlashInfer on SM100+ ](../sources/prs/sglang/PR-21861.md), [[server] Add --quantization unquant to explicitly opt out of quantization](../sources/prs/sglang/PR-21863.md), [[Misc] [MXFP8] Drop sm100 mxfp8 warning](../sources/prs/sglang/PR-21881.md), [fix pcg torch dynamo recompile in mxfp8 Triton path](../sources/prs/sglang/PR-21888.md), [[Bugfix] Temporarily skip TRTLLM attention on (G)B300 (SM103) to avoid high-concurrency hang](../sources/prs/sglang/PR-21906.md), [[DSA] Set trtllm kernels as default for Blackwell](../sources/prs/sglang/PR-21914.md), [[Bugfix] Fix CUDA graph replay issues in trtllm_mla draft_extend](../sources/prs/sglang/PR-21987.md), [Tiny fix trtllm_fp8_per_tensor_scale_moe_wrapper router_logits dtype](../sources/prs/sglang/PR-22006.md), [[NPU] enable mla prepare fused kernel only when being mla attn](../sources/prs/sglang/PR-22024.md), [[MUSA][9/N] Add FA3 attention backend support through MATE (MUSA AI Tensor Engine)](../sources/prs/sglang/PR-22051.md), [[Diffusion] Fix weight scale swizzle and add large-M kernel config for FLUX.2-dev-NVFP4](../sources/prs/sglang/PR-22064.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[diffusion] Default NVFP4 to CUTLASS and add all-model shape benchmarks](../sources/prs/sglang/PR-22091.md), [[Diffusion] Add diffusion NVFP4 scaled-mm correctness test](../sources/prs/sglang/PR-22127.md), [[Hotfix] Fix router gemm on sm103](../sources/prs/sglang/PR-22134.md), [[Disagg][NIXL] Fix heterogeneous TP KV transfer for non-MLA models (same logic with mooncake, Step 1/2 for Qwen3.5 support)](../sources/prs/sglang/PR-22145.md), [[hisparse]: Adding ci for hisparse kvcache-swap-in jit-kernel](../sources/prs/sglang/PR-22155.md), [[HiSparse]: Add benchmark for hisparse kernel](../sources/prs/sglang/PR-22187.md), [[RL] Refactor NVFP4 shuffling/swizzling to in-place replacement](../sources/prs/sglang/PR-22204.md), [Reduce unnecessary kernels and copies in the NSA indexer](../sources/prs/sglang/PR-22232.md), [[AMD][HIP] NSA: bf16 passthrough from RMSNorm to eliminate FP8 dequantization](../sources/prs/sglang/PR-22258.md), [Lazy import flash_attention_v4 to avoid loading flash_attn.cute at startup](../sources/prs/sglang/PR-22306.md), [[AMD] Fix GLM-5 fp8 KV quant path dispatch on MI300](../sources/prs/sglang/PR-22314.md), [[Reland] DeepSeek-R1-0528-w4a8: DeepEP Low Latency Dispatch Adopts FP8 Communication](../sources/prs/sglang/PR-22316.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [[AMD] Add GLM-5.1-FP8 nightly accuracy and performance benchmarks for MI30x and MI35x](../sources/prs/sglang/PR-22336.md), [:sparkles: [diffusion][npu][quant] Add MXFP4 quantization support for Wan2.2 Diffusion on Ascend NPU](../sources/prs/sglang/PR-22338.md), [[Diffusion] modelopt diffusion fp8 support for flux1/flux2 and wan2.2](../sources/prs/sglang/PR-22365.md), [[DSA] Hopper FP8 FlashMLA KV padding](../sources/prs/sglang/PR-22372.md), [[Lora] Lora kimi support](../sources/prs/sglang/PR-22381.md), [[AMD] Use aiter CK layernorm2d for LayerNorm to reduce NSA indexer kernel launches](../sources/prs/sglang/PR-22424.md), [[Fix] Fix several bugs on DSA models](../sources/prs/sglang/PR-22430.md), [Upgrade sglang-torch-profiler-analysis SKILLS](../sources/prs/sglang/PR-22440.md), [[RL] Fix weight update for mxfp8 flashinfer_cutlass gemm backend](../sources/prs/sglang/PR-22484.md), [GLM-5/5.1 MXFP4 Checkpoint Inference Compatibility Fix](../sources/prs/sglang/PR-22543.md), [[Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22574.md), [diffusion: fix layerwise offload for ModelOpt quantized DiTs](../sources/prs/sglang/PR-22594.md), [feat: Support flashinfer_cutedsl MoE runner with flashinfer alltoall backend](../sources/prs/sglang/PR-22669.md), [reland [Diffusion] Add FLUX.1-dev ModelOpt NVFP4 support](../sources/prs/sglang/PR-22672.md), [[Diffusion] Add Wan2.2 ModelOpt NVFP4 support](../sources/prs/sglang/PR-22681.md), [[Step3p5] Optimize allreduce in MoE layers ](../sources/prs/sglang/PR-22773.md), [Dual MoE CUDA graph capture for lora/nolora batches](../sources/prs/sglang/PR-22809.md), [diffusion: add HunyuanVideo GroupNorm+SiLU fast path](../sources/prs/sglang/PR-22814.md), [[Refactor] Refactor DeepEP dispatcher](../sources/prs/sglang/PR-22822.md), [[FlashInfer v0.6.11] [RL] Support FlashInfer per-token NVFP4 MoE](../sources/prs/sglang/PR-22918.md), [[Fix/Kernel] Add JIT rmsnorm_hf kernel to fix transformers backend MMLU accuracy regression ](../sources/prs/sglang/PR-22931.md), [[codex] diffusion: enable group norm silu fuse by default](../sources/prs/sglang/PR-23148.md), [[BugFix] Resolve adaptive speculative decoding conflicts for Qwen3.5 (hybrid GDN)](../sources/prs/sglang/PR-23331.md), [[Diffusion][NPU]Add attention backends for diffusion models for Ascend NPU](../sources/prs/sglang/PR-23482.md), [Reland Cute-DSL FP4 dense GEMM](../sources/prs/sglang/PR-23590.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [Use Cute-DSL NVFP4 quantization kernels](../sources/prs/sglang/PR-23745.md), [feat: port SGLANG_JIT_DEEPGEMM_FAST_WARMUP to deepseek_v4 branch](../sources/prs/sglang/PR-23756.md), [[MoE] Unify DeepEPMoE+MoriEPMoE through AITER MoeRunner pre/post-permute](../sources/prs/sglang/PR-23760.md), [Optimize large GroupNorm SiLU apply](../sources/prs/sglang/PR-23938.md), [[feat] Init true on policy with qwen_dense](../sources/prs/sglang/PR-23961.md), [Enable PDL for various kernels in DSV32/GLM5](../sources/prs/sglang/PR-23965.md), [[VLM] Optimize Gemma4 VLM with PCG and fuse RMSNorm + residual add + scalar](../sources/prs/sglang/PR-24048.md), [Refactor device timer, clean up metrics collector, and add fwd occupancy metric](../sources/prs/sglang/PR-24197.md), [[KDA] Optimize prefill kernels with diagonal and recompute fuse](../sources/prs/sglang/PR-24271.md), [[diffusion] Fuse LTX2 split rotary embedding](../sources/prs/sglang/PR-24411.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [Fix performance regression on Deepseek V3 on `moe-runner-backend=triton` on SM90](../sources/prs/sglang/PR-24562.md), [[Codex] Opt Mistral Large performace ](../sources/prs/sglang/PR-24611.md), [Support spec v2 for FlashMLA speculative decoding](../sources/prs/sglang/PR-24640.md), [[Gemma4] Optimize Gemm4 with fused Q/K/V RMSNorm + per-expert FP8 ckpt loader](../sources/prs/sglang/PR-24696.md), [[codex] Optimize hidden-size 512 RMSNorm dispatch](../sources/prs/sglang/PR-24710.md), [Add FlashInfer SM90 cutlass MXFP4 MoE backend (W4A16) for GPT-OSS + DeepSeek-V4](../sources/prs/sglang/PR-24816.md), [[attn backend] Integrate tokenspeed_mla prefill/decode kernels (fp8 kv cache, blackwell)](../sources/prs/sglang/PR-24925.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [perf(nvfp4): free unused source scales after weight processing](../sources/prs/sglang/PR-25107.md), [Fix AMX GQA extend attention](../sources/prs/sglang/PR-25180.md), [[MUSA][Diffusion] Improve wan model inference speed using torch.compile](../sources/prs/sglang/PR-25256.md), [Support Gemma4 Pipeline Parallelism](../sources/prs/sglang/PR-25284.md), [Fix EPLB mapping for TopK paths](../sources/prs/sglang/PR-25285.md), [[Gemma4]: Fix FP8 Triton scale layout](../sources/prs/sglang/PR-25286.md), [[NSA] Avoid repeated NSA MQA logits memory queries](../sources/prs/sglang/PR-25299.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [[AMD] test(sgl-kernel): seed RNG on ROCm in test_moe_topk_sigmoid to fix tie-break flake](../sources/prs/sglang/PR-25356.md), [[AMD] Enable shared-experts fusion with new KIMI-K2.5-MXFP4 model.](../sources/prs/sglang/PR-25390.md), [[codex] Update Wan2.2 ModelOpt CI checkpoints](../sources/prs/sglang/PR-25483.md), [Support draft extend cuda graph for tokenspeed_mla attention backend](../sources/prs/sglang/PR-25489.md), [Update logging for inplace setting in MoE layer](../sources/prs/sglang/PR-25499.md), [[misc] Throw error when single batch overlap is enabled on Hopper ](../sources/prs/sglang/PR-25509.md), [Fix logging for inplace setting in the flashInfer-trtllm backend](../sources/prs/sglang/PR-25522.md), [[Bug Fix] Align glm4_moe_nextn NPU MTP loading with qwen3 MTP](../sources/prs/sglang/PR-25524.md), [[MoE Refactor] Migrate flashinfer_cutedsl + DeepEP to MoeRunner](../sources/prs/sglang/PR-25525.md), [Use DeepGEMM BF16 for unquantized DeepEP LL MoE](../sources/prs/sglang/PR-25540.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [Use triton_attn as default vision attention on B300 (SM103)](../sources/prs/sglang/PR-25570.md), [[Benchmark] Add SGLANG_SIMULATE_UNIFORM_EXPERTS for balanced expert routing with dummy weights](../sources/prs/sglang/PR-25571.md), [Introduce SchedulerDPAttnAdapter to own DP-attention state](../sources/prs/sglang/PR-25611.md), [Move DP-attention adapter methods to SchedulerDPAttnAdapter](../sources/prs/sglang/PR-25612.md), [[SP] Fix runtime_max_tokens_per_rank for sequence parallelism](../sources/prs/sglang/PR-25685.md), [Add no_combine support to cutlass_moe_fp4](../sources/prs/sglang/PR-25688.md), [fix (jit kernel): elementwise activation C++ error](../sources/prs/sglang/PR-25695.md), [[diffusion] Fix GLM-Image /v1/images/edits support](../sources/prs/sglang/PR-25697.md), [[Codex] Remove stale DeepSeek V4 JIT kernels](../sources/prs/sglang/PR-25764.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Refactor] Pass PP start_layer via model constructor instead of forward_batch.token_to_kv_pool](../sources/prs/sglang/PR-25825.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Allow local cutlass directory to be used in sgl-kernel build](../sources/prs/sglang/PR-3037.md), [sync the upstream updates of flashinfer](../sources/prs/sglang/PR-3051.md), [feat: integrate gemm_fp8 kernel into gemm](../sources/prs/sglang/PR-3056.md), [Apply sgl w8a8 fp8 kernel](../sources/prs/sglang/PR-3148.md), [integrate blockwise fp8 kernel](../sources/prs/sglang/PR-3529.md), [feat: support flashinfer mla attention for deepseek v3](../sources/prs/sglang/PR-3550.md), [update flashinfer-python](../sources/prs/sglang/PR-3557.md), [feat: support flashinfer mla with prefix cache](../sources/prs/sglang/PR-3643.md), [add control for cutlass fp8 blockwise gemm](../sources/prs/sglang/PR-3727.md), [Feature DeepSeek V3/R1 INT8 Quantization (block-wise)](../sources/prs/sglang/PR-3730.md), [[Feature] DeepSeek V3/R1 INT8 Quantization (channel-wise) ](../sources/prs/sglang/PR-3888.md), [Support FP4 gemm (1/2)](../sources/prs/sglang/PR-3899.md), [upgrade flashinfer v0.2.2.post1](../sources/prs/sglang/PR-3934.md), [[tools] add fp8 max/min constant in utils](../sources/prs/sglang/PR-3959.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [Hierarchical Caching supports MLA](../sources/prs/sglang/PR-4009.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [Support overlapping two batches](../sources/prs/sglang/PR-4068.md), [DeepGemm integrate to gemm](../sources/prs/sglang/PR-4165.md), [linear support deepgemm](../sources/prs/sglang/PR-4199.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [Clean up fp8 support](../sources/prs/sglang/PR-4230.md), [[Feature] Integrate DeepEP into SGLang](../sources/prs/sglang/PR-4232.md), [upgrade flashinfer 0.2.3](../sources/prs/sglang/PR-4317.md), [[FIX] fix incorrect output when enable both deepgemm and torch compile](../sources/prs/sglang/PR-4359.md), [[ROCm] fix dtype](../sources/prs/sglang/PR-4510.md), [Create col-major and tma-aligned x_scale for deep_gemm.gemm_fp8_fp8_bf16_nt](../sources/prs/sglang/PR-4515.md), [Add deepseek style fused moe group gate selection kernel](../sources/prs/sglang/PR-4530.md), [[Fix] Fix raw_bs bug when using flashinfer mla and eagle](../sources/prs/sglang/PR-4557.md), [avoid cudaStreamSynchronize in DeepSeekV2AttentionMLA](../sources/prs/sglang/PR-4577.md), [[quantization] fix channelwise conversion with scalar weight scale](../sources/prs/sglang/PR-4596.md), [Set deepgemm to the default value in the hopper architecture.](../sources/prs/sglang/PR-4613.md), [Optimize Permute Kernel in DeepEP](../sources/prs/sglang/PR-4643.md), [Fix loading KV quantization scale; Enable modelopt kv cache](../sources/prs/sglang/PR-4686.md), [[Model] Adding Qwen3 and Qwen3MoE](../sources/prs/sglang/PR-4693.md), [support cmake for sgl-kernel](../sources/prs/sglang/PR-4706.md), [[Feature] Support DeepEP Low Latency](../sources/prs/sglang/PR-4767.md), [Support (1 <= dp < tp) in the dp attention in DeepEP](../sources/prs/sglang/PR-4770.md), [Introduce moe_dense_tp_size to fix dense layer errors in DeepSeek V3 + 4x8xH100](../sources/prs/sglang/PR-4836.md), [Feat/support encoder model (like bert)](../sources/prs/sglang/PR-4887.md), [Add DeepSeek V3/R1 shared experts fusion](../sources/prs/sglang/PR-4918.md), [[Fix] DeepEP Compatibility with Low Latency](../sources/prs/sglang/PR-5068.md), [reduce moe_align_block_size_kernel small batch mode overhead](../sources/prs/sglang/PR-5086.md), [Support MHA with chunked prefix cache for DeepSeek chunked prefill](../sources/prs/sglang/PR-5113.md), [Blackwell Cutlass MLA kernel](../sources/prs/sglang/PR-5142.md), [Add optimized native kernels in sgl-kernel](../sources/prs/sglang/PR-5150.md), [feat: add DeepGEMM build warning](../sources/prs/sglang/PR-5176.md), [feat: use fa3 mla by default on hopper](../sources/prs/sglang/PR-5210.md), [[Fix] Turn off DeepGEMM by default](../sources/prs/sglang/PR-5263.md), [[1/2] Add FP8 Blockscale MoE CUTLASS kernel for Blackwell](../sources/prs/sglang/PR-5281.md), [fix: use deepgemm only on hopper](../sources/prs/sglang/PR-5310.md), [Add Speculative Decoding Eagle3 topk > 1](../sources/prs/sglang/PR-5318.md), [fix: determine if flashinfer is installed](../sources/prs/sglang/PR-5336.md), [Fix DeepGEMM masked cannot be run on groups not being multiple or 4](../sources/prs/sglang/PR-5340.md), [[perf] experimental enhance fp8 per-tensor quant](../sources/prs/sglang/PR-5370.md), [apply fused moe gate in ds v3/r1](../sources/prs/sglang/PR-5371.md), [[PD Bug] fix MLA get_contiguous_buf_infos error](../sources/prs/sglang/PR-5384.md), [Add Cutlass MLA attention backend](../sources/prs/sglang/PR-5390.md), [[PD] Fix dynamic port support and MLA buffer for Mooncake](../sources/prs/sglang/PR-5415.md), [[Feat] upgrade pytorch2.6](../sources/prs/sglang/PR-5417.md), [BLackwell cutlass mla: Add check for bad page size/block num combinations](../sources/prs/sglang/PR-5431.md), [[perf] introduce deep gemm group_gemm_masked as gemm](../sources/prs/sglang/PR-5432.md), [Avoid computing lse in Ragged Prefill when there's no prefix.](../sources/prs/sglang/PR-5476.md), [Fix sampler nan check when calling top_k_top_p_sampling_from_probs](../sources/prs/sglang/PR-5546.md), [[feature] enable pre compile jit deep_gemm](../sources/prs/sglang/PR-5580.md), [[fix] force use deepgemm in compile_deep_gemm](../sources/prs/sglang/PR-5618.md), [ DeepEP normal support deepgemm-contiguous](../sources/prs/sglang/PR-5626.md), [Turn on DeepGemm By Default and Update Doc](../sources/prs/sglang/PR-5628.md), [[perf] dsv3 bmm fallback to bf16](../sources/prs/sglang/PR-5662.md), [[2/2] Add python wrapper for CUTLASS FP8 Blockscale MoE Kernel. ](../sources/prs/sglang/PR-5694.md), [[PP] Add pipeline parallelism](../sources/prs/sglang/PR-5724.md), [Fuse MLA set kv cache kernel](../sources/prs/sglang/PR-5748.md), [opt flashinfer mla cat](../sources/prs/sglang/PR-5822.md), [Cutlass MLA decode - fix dtype error](../sources/prs/sglang/PR-5868.md), [[Fix] Fix a bug for flashmla to run R1 model](../sources/prs/sglang/PR-5875.md), [Improve dp attention port assignment scheme](../sources/prs/sglang/PR-5889.md), [[qwen3] support qwen3 ep moe](../sources/prs/sglang/PR-5917.md), [[Feat] Enable PDL automatically on Hopper architecture](../sources/prs/sglang/PR-5981.md), [KV‑Cache (MHA, MLA): add missing start_layer / end_layer fields to MHATokenToKVPoolHost and MLATokenToKVPoolHost](../sources/prs/sglang/PR-6016.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [[1/2] Add Kernel support for Cutlass based Fused FP4 MoE](../sources/prs/sglang/PR-6093.md), [feat: add dp attention support for Qwen 2/3 MoE models, fixes #6088](../sources/prs/sglang/PR-6121.md), [Reduce MoE memory usage](../sources/prs/sglang/PR-6147.md), [enable auto-round quantization model](../sources/prs/sglang/PR-6226.md), [Enable FlashInfer support encoder models and add head_dim padding workaround](../sources/prs/sglang/PR-6230.md), [fix: fix MLA for ShardedModelLoader/RemoteModelLoader](../sources/prs/sglang/PR-6287.md), [[Fix] Improve dependencies for Blackwell image](../sources/prs/sglang/PR-6334.md), [reduce torch.zeros overhead in moe align block size kernel](../sources/prs/sglang/PR-6369.md), [[Feature] Comprehensive Hybrid Parallelism Support](../sources/prs/sglang/PR-6389.md), [Add fp8 fused_experts kernel for CPU in sgl-kernel and add UT](../sources/prs/sglang/PR-6404.md), [Fix bug of deepseek-v3 under DP+EP mode with large batchsize/seqlen](../sources/prs/sglang/PR-6449.md), [Fix topk inference performance reduce](../sources/prs/sglang/PR-6474.md), [[Feature] Support Flashinfer fp8 blockwise GEMM kernel on Blackwell](../sources/prs/sglang/PR-6479.md), [qwen3moe support two batch overlap](../sources/prs/sglang/PR-6598.md), [Refine pre_reorder_triton_kernel slightly to improve performance](../sources/prs/sglang/PR-6627.md), [[CPU] [BF16] Call fused_experts_cpu, weight_packed_linear and bmm_cpu kernel in DeepSeek model](../sources/prs/sglang/PR-6641.md), [Fix DeepEP error in Qwen 3 MoE models](../sources/prs/sglang/PR-6673.md), [[EP] Add cuda kernel for moe_ep_pre_reorder](../sources/prs/sglang/PR-6699.md), [Fix PP for Qwen3 MoE](../sources/prs/sglang/PR-6709.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [[CPU] add optimizations for INT8 and FP8 DeepSeek](../sources/prs/sglang/PR-6769.md), [[CPU] support the case where num_attention_heads or intermediate_size is not divisible by the TP size](../sources/prs/sglang/PR-6771.md), [Support token-level quantization for EP MoE](../sources/prs/sglang/PR-6782.md), [[PD] Add different TP sizes support for no-MLA models](../sources/prs/sglang/PR-6793.md), [Correctly abort the failed grammar requests & Improve the handling of abort](../sources/prs/sglang/PR-6803.md), [feat: integrate deepgemm into EPMoE](../sources/prs/sglang/PR-6821.md), [CPU: map changes from developing branch in sgl-kernel](../sources/prs/sglang/PR-6833.md), [[EP] Add cuda kernel for moe_ep_post_reorder](../sources/prs/sglang/PR-6837.md), [Fix AWQ Dequant and Weight Loading of deepseek v2](../sources/prs/sglang/PR-6842.md), [[DeepseekR1-FP4] Add Support for nvidia/DeepSeekR1-FP4 model](../sources/prs/sglang/PR-6853.md), [Use deepgemm instead of triton for fused_qkv_a_proj_with_mqa](../sources/prs/sglang/PR-6890.md), [Add a CUDA kernel for fusing mapping and weighted sum for MoE.](../sources/prs/sglang/PR-6916.md), [[sgl-kernel] Add cuda kernel for moe_ep_silu_and_mul](../sources/prs/sglang/PR-6919.md), [[perf][sgl-kernel] extend cutlass_mla_decode to support num_head < 128](../sources/prs/sglang/PR-6929.md), [[Feature] Support Flashinfer fmha on Blackwell](../sources/prs/sglang/PR-6930.md), [[sgl-kernel] update deepgemm](../sources/prs/sglang/PR-6942.md), [chore: upgrade flashinfer v0.2.6.post1 jit](../sources/prs/sglang/PR-6958.md), [Fuse routed scaling factor in deepseek](../sources/prs/sglang/PR-6970.md), [Fix cutlass MLA gets almost zero accuracy](../sources/prs/sglang/PR-6998.md), [Fix torchvision version for Blackwell](../sources/prs/sglang/PR-7015.md), [Update default settings for blackwell](../sources/prs/sglang/PR-7023.md), [Clean up server_args.py](../sources/prs/sglang/PR-7037.md), [Fix positional argument](../sources/prs/sglang/PR-7093.md), [feat: update blackwell setup](../sources/prs/sglang/PR-7119.md), [fix amd EP MoE FP8 issue](../sources/prs/sglang/PR-7125.md), [Enable ModelOpt Llama4 fp8 checkpoint deployment in SGLang](../sources/prs/sglang/PR-7129.md), [Enable native ModelOpt quantization support (1/3) ](../sources/prs/sglang/PR-7149.md), [[amd] Opt dsv3 moe](../sources/prs/sglang/PR-7160.md), [Fix Deepseek R1 0528 FP4 tensor name mismatch issue during weights loading.](../sources/prs/sglang/PR-7164.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Tiny let DeepGEMM scale checks cover more cases](../sources/prs/sglang/PR-7182.md), [chore: upgrade sgl-kernel v0.1.8.post2](../sources/prs/sglang/PR-7186.md), [[AMD] Fail gracefully when AITER is unavailable gfx90a GPUs](../sources/prs/sglang/PR-7187.md), [Fix a minor bug related to DeepGEMM upgrade](../sources/prs/sglang/PR-7191.md), [Fix error when disabling new DeepGEMM](../sources/prs/sglang/PR-7198.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [feat: support compatibility between MTP and two-batch-overlap](../sources/prs/sglang/PR-7225.md), [Minor style and doc fix](../sources/prs/sglang/PR-7228.md), [[fix] fix DeepGEMM blackwell input quant & ut & fix style and log](../sources/prs/sglang/PR-7247.md), [[AMD] add aiter fused moe in DeepEP path](../sources/prs/sglang/PR-7268.md), [Support NVFP4 quantized dense models on AMD CDNA2/CDNA3 GPUs](../sources/prs/sglang/PR-7302.md), [Let EP prefill support new DeepGEMM](../sources/prs/sglang/PR-7310.md), [Kernels for efficient KV cache IO](../sources/prs/sglang/PR-7313.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Fix MTP with Deepseek R1 Fp4](../sources/prs/sglang/PR-7376.md), [Quick fix for DeepGemm requant to also cover MTP.](../sources/prs/sglang/PR-7378.md), [Fix torch compile run](../sources/prs/sglang/PR-7391.md), [[AMD][Quantization] Add `int4fp8_moe` online quantization on ROCm](../sources/prs/sglang/PR-7392.md), [Fix CPU offloading for MLA memory pool](../sources/prs/sglang/PR-7409.md), [Fuse sorted_token_ids padding to moe_align_block_size kernel](../sources/prs/sglang/PR-7437.md), [Support non-contiguous query input for extend/decode attention](../sources/prs/sglang/PR-7462.md), [Add Tencent HunYuanMoEV1 model support](../sources/prs/sglang/PR-7549.md), [[b200] support trt-llm allreduce fuse rms_norm_add kernel](../sources/prs/sglang/PR-7621.md), [Add dsv3 router gemm kernel](../sources/prs/sglang/PR-7627.md), [Add dsv3 fused a gemm to sgl-kernel](../sources/prs/sglang/PR-7630.md), [[Feature] Layer-wise Prefill](../sources/prs/sglang/PR-7634.md), [Apply dsv3_fused_a_gemm kernel](../sources/prs/sglang/PR-7635.md), [[Feature] CUDA Green Context Support](../sources/prs/sglang/PR-7649.md), [chore: upgrade flashinfer v0.2.7 jit](../sources/prs/sglang/PR-7663.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [Integrate triton moe kernel](../sources/prs/sglang/PR-7689.md), [feat: support DeepSeek-R1-W4AFP8 model with ep-moe mode](../sources/prs/sglang/PR-7762.md), [[1/n]: add cutlass W4A8 moe kernel for hopper architecture](../sources/prs/sglang/PR-7772.md), [Qwen FP8/NVFP4 ModelOPT Quantization support](../sources/prs/sglang/PR-7912.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [[fix] fix modelopt fp4 on b200](../sources/prs/sglang/PR-8195.md), [[1/N]Support DeepSeek-R1 w4a8 normal deepep](../sources/prs/sglang/PR-8247.md), [Support triton kernels v3.4.0 for fused_moe](../sources/prs/sglang/PR-8258.md), [[2/N]Support DeepSeek-R1 w4a8 low latency deepep](../sources/prs/sglang/PR-8464.md), [Update cutlass_moe.py](../sources/prs/sglang/PR-8535.md), [Update cutlass_moe.py](../sources/prs/sglang/PR-8545.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [TRTLLM-MLA FP8 path](../sources/prs/sglang/PR-8638.md), [feat: support cutlass_moe_fp8 kernel for fusedmoe in sm90](../sources/prs/sglang/PR-8678.md), [fuse allreduce and residual_rmsnorm](../sources/prs/sglang/PR-8731.md), [Fix mismatch between padded_scales shape and reshape dimensions in modelopt quantization](../sources/prs/sglang/PR-8766.md), [feat: add trtllm-gen mha from direct call](../sources/prs/sglang/PR-8782.md), [[Perf] Auto enable best flashinfer mxfp4 kernel in b200](../sources/prs/sglang/PR-8898.md), [Fix hopper launch gpt-oss model illegal memory](../sources/prs/sglang/PR-8908.md), [[NVIDIA] Fix missing `get_col_major_tma_aligned_tensor` for Blackwell deepgemm in EpMoE](../sources/prs/sglang/PR-8955.md), [optimize: reduce shulffle and quantization overhead in cutlass_moe sm90](../sources/prs/sglang/PR-8962.md), [[fix] fix enable_pdl for blackwell](../sources/prs/sglang/PR-9011.md), [[sgl-kernel] Support FlashInfer top_k_top_p_sampling_from_logits](../sources/prs/sglang/PR-9060.md), [Faster weight processing (trtllm-gen moe nvfp4)](../sources/prs/sglang/PR-9162.md), [[NVIDIA] [3/N] Nvfp4 Masked Gemm: Add flashinfer grouped_gemm_nt_masked ](../sources/prs/sglang/PR-9199.md), [[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm](../sources/prs/sglang/PR-9200.md), [[fix]: fix cutlass moe ut and and Opt H20 cutlass groupGemm performance](../sources/prs/sglang/PR-9272.md), [Support trtllm_allreduce_fusion in flashinfer for cuda<12.8](../sources/prs/sglang/PR-9339.md), [Fix FP4 inference corruption issue in glm4.5-air model](../sources/prs/sglang/PR-9346.md), [Support DP attention with GPT-OSS](../sources/prs/sglang/PR-9359.md), [[fix] Fix mxfp4 triton MoE tp bug](../sources/prs/sglang/PR-9473.md), [Optimize moe_sum_reduce_kernel](../sources/prs/sglang/PR-9477.md), [fix: blackwell dsv3 fp8 issue temporary solution](../sources/prs/sglang/PR-9530.md), [[NVIDIA] [2/N] Optimize `silu_and_mul_scaled_fp4_grouped_quant` perf](../sources/prs/sglang/PR-9556.md), [Update CUTLASS 4.2 & Enable K-Major Scale Factor for SM90 FP8 Blockwise Group GEMM](../sources/prs/sglang/PR-9559.md), [Tiny fix wrong comments](../sources/prs/sglang/PR-9589.md), [Single Batch Overlap for MoE Models](../sources/prs/sglang/PR-9660.md), [fix mooncake store mla zero copy meta](../sources/prs/sglang/PR-9678.md), [move is_sm90_supported/is_sm100_supported to python/sglang/srt/utils.py](../sources/prs/sglang/PR-9679.md), [[ModelOpt] Fix Weight Loading for DSR1-FP4 Quantization](../sources/prs/sglang/PR-9712.md), [[CPU] Add FP8 Bmm support](../sources/prs/sglang/PR-9744.md), [[Model] Support Meituan LongCat-Flash && LongCat-Flash-MTP](../sources/prs/sglang/PR-9824.md), [perf: Avoid unnecessary data type conversions for DeepSeek-V3 on Blackwell](../sources/prs/sglang/PR-9834.md), [support using fa4 on deepseek on blackwell](../sources/prs/sglang/PR-9928.md), [[Fix] DeepSeek EP accuracy issue on B200 GPUs](../sources/prs/sglang/PR-9946.md), [Enable native ModelOpt quantization support (2/3)](../sources/prs/sglang/PR-9991.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [[BugFix] Fix Hopper TMA lowering without warp specialization](../sources/prs/tilelang/PR-1840.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] Add T.copy_cluster to support TMA multicast and SM-to-SM cluster copy](../sources/prs/tilelang/PR-1908.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Bugfix] Fix CuTeDSL autotune cache invalid ELF header (#1967)](../sources/prs/tilelang/PR-1972.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[CUDA] Improve int4 GEMM lowering and packed codegen support](../sources/prs/tilelang/PR-2073.md), [[TMA] Support FP4 TensorMap TMA copies](../sources/prs/tilelang/PR-2107.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md), [[Perf] Enable fast math in sparse MLA example](../sources/prs/tilelang/PR-2219.md), [[Core] Support fully transparent sleep mode](../sources/prs/vllm/PR-11743.md), [[ROCm][MoE] moe tuning support for rocm](../sources/prs/vllm/PR-12049.md), [[Kernel] Flash Attention 3 Support](../sources/prs/vllm/PR-12093.md), [Add: Support for Sparse24Bitmask Compressed Models](../sources/prs/vllm/PR-12097.md), [[Hardware][Gaudi][Feature] Enable Dynamic MoE for Mixtral](../sources/prs/vllm/PR-12303.md), [[Core] Optimizing cross-attention `QKVParallelLinear` computation](../sources/prs/vllm/PR-12325.md), [[Bugfix] Disable w16a16 2of4 sparse CompressedTensors24](../sources/prs/vllm/PR-12417.md), [[Misc][MoE] add Deepseek-V3 moe tuning support](../sources/prs/vllm/PR-12558.md), [Expert Parallelism (EP) Support for DeepSeek Models](../sources/prs/vllm/PR-12583.md), [Apply torch.compile to fused_moe/grouped_topk](../sources/prs/vllm/PR-12637.md), [Disable chunked prefill and/or prefix caching when MLA is enabled ](../sources/prs/vllm/PR-12642.md), [[AMD][ROCm] Enable DeepSeek model on ROCm](../sources/prs/vllm/PR-12662.md), [Squelch MLA warning for Compressed-Tensors Models](../sources/prs/vllm/PR-12704.md), [[VLM] Add MLA with pure RoPE support for deepseek-vl2 models](../sources/prs/vllm/PR-12729.md), [[Misc] Update w2 scale loading for GPTQMarlinMoE](../sources/prs/vllm/PR-12757.md), [[Bugfix] Better FP8 supported defaults](../sources/prs/vllm/PR-12796.md), [[Attention] Use FA3 for MLA on Hopper](../sources/prs/vllm/PR-12807.md), [[Model] Deepseek GGUF support ](../sources/prs/vllm/PR-13167.md), [Expand MLA to support most types of quantization](../sources/prs/vllm/PR-13181.md), [[Quant][Perf] Use moe_wna16 kernel by default for MoEs with many experts](../sources/prs/vllm/PR-13236.md), [[Bugfix] Massage MLA's usage of flash attn for RoCM](../sources/prs/vllm/PR-13310.md), [[NVIDIA] Support nvfp4 tcgen05 gemm](../sources/prs/vllm/PR-13571.md), [[Bugfix] Fix max_num_batched_tokens for MLA](../sources/prs/vllm/PR-13620.md), [[Kernel] Optimize moe intermediate_cache usage](../sources/prs/vllm/PR-13625.md), [[ROCM] fix native attention function call](../sources/prs/vllm/PR-13650.md), [[BugFix] Illegal memory access for MoE On H20](../sources/prs/vllm/PR-13693.md), [[Bugfix] Support MLA for CompressedTensorsWNA16](../sources/prs/vllm/PR-13725.md), [[V1] V1 Enablement Oracle ](../sources/prs/vllm/PR-13726.md), [Fix CompressedTensorsWNA16MoE with grouped scales](../sources/prs/vllm/PR-13769.md), [Fix precommit fail in fused_moe intermediate_cache2 chunking](../sources/prs/vllm/PR-13772.md), [[Bugfix][Quantization] Fix FP8 + EP](../sources/prs/vllm/PR-13784.md), [add tcgen05 support for tcgen05 fp8 gemm](../sources/prs/vllm/PR-13798.md), [Fix mla prefill context performance](../sources/prs/vllm/PR-13897.md), [[Misc] Print FusedMoE detail info](../sources/prs/vllm/PR-13974.md), [[core] moe fp8 block quant tuning support](../sources/prs/vllm/PR-14068.md), [[V1] Implement sliding window attention in kv_cache_manager](../sources/prs/vllm/PR-14097.md), [[v1] Add comments to the new ragged paged attention Pallas kernel](../sources/prs/vllm/PR-14155.md), [[V1][TPU] TPU multimodal model support for ragged attention](../sources/prs/vllm/PR-14158.md), [[V1][TPU] Support V1 Sampler for ragged attention](../sources/prs/vllm/PR-14227.md), [[Hardware] Update the flash attn tag to support Blackwell](../sources/prs/vllm/PR-14244.md), [[BugFix] Fix prefix caching V0 MLA](../sources/prs/vllm/PR-14255.md), [[Misc] Add Qwen2MoeForCausalLM moe tuning support ](../sources/prs/vllm/PR-14276.md), [[Hardware][TPU]Enable ragged paged attention kernel and resolve recompilation issue](../sources/prs/vllm/PR-14310.md), [[Bug] Fix Attention when ignored in by quant_method](../sources/prs/vllm/PR-14313.md), [[ROCm] Enable chunked prefill/paged attention in MLA on ROCm](../sources/prs/vllm/PR-14316.md), [[Perf] Reduce MLA CPU overheads in V1](../sources/prs/vllm/PR-14384.md), [[ROCm][Kernel] MoE weights padding](../sources/prs/vllm/PR-14454.md), [[Bugfix] DeepSeek Accuracy](../sources/prs/vllm/PR-14476.md), [[Perf] Improve MLA on V1](../sources/prs/vllm/PR-14540.md), [[Quantization][FP8] Adding support for fp8 gemm layer input in fp8](../sources/prs/vllm/PR-14578.md), [[Model] Add support for Gemma 3](../sources/prs/vllm/PR-14660.md), [[Bugfix][IPEX] Add `VLLM_CPU_MOE_PREPACK` to allow disabling MoE prepack when CPU does not support it](../sources/prs/vllm/PR-14681.md), [[Kernel][CPU] CPU MLA](../sources/prs/vllm/PR-14744.md), [[Attention] MLA get rid of materialization](../sources/prs/vllm/PR-14770.md), [[Attention] Get rid of mla cache alignment](../sources/prs/vllm/PR-14842.md), [[V1][BugFix] Detect interleaved sliding window attention](../sources/prs/vllm/PR-14896.md), [[V1] Default MLA to V1](../sources/prs/vllm/PR-14921.md), [[FEAT][ROCm] Integrate Fused MoE Kernels from AITER](../sources/prs/vllm/PR-14967.md), [[FEAT] [ROCm]: Add AITER Block-Scaled GEMM Feature](../sources/prs/vllm/PR-14968.md), [[FEAT][ROCm] Integrate Paged Attention Kernel from AITER](../sources/prs/vllm/PR-15001.md), [[Bugfix] Fix incorrect qwen2.5-vl attention mask pre-computation](../sources/prs/vllm/PR-15200.md), [[Bugfix] Fix use_cascade_attention handling for Alibi-based models on vllm/v1](../sources/prs/vllm/PR-15211.md), [[Misc] Add attention mask pre-computation optimization back to Qwen2.5-VL](../sources/prs/vllm/PR-15273.md), [[Model] Add Qwen3 and Qwen3MoE](../sources/prs/vllm/PR-15289.md), [Fix non-contiguous input passed to Marlin kernel](../sources/prs/vllm/PR-15319.md), [[FEAT] [ROCm] Add AITER int8 scaled gemm kernel](../sources/prs/vllm/PR-15433.md), [Use Cache Hinting for fused_moe kernel](../sources/prs/vllm/PR-15511.md), [[moe][quant] add weight name case for offset](../sources/prs/vllm/PR-15515.md), [[Quantization] Fp8 Channelwise Dynamic Per Token GroupedGEMM](../sources/prs/vllm/PR-15587.md), [[TPU] Support sliding window and logit soft capping in the paged attention kernel for TPU.](../sources/prs/vllm/PR-15732.md), [[V1] TPU - Fix fused MOE](../sources/prs/vllm/PR-15834.md), [[Bugfix] Fix cache block size calculation for CPU MLA](../sources/prs/vllm/PR-15848.md), [[FEAT][ROCm]: Support AITER MLA](../sources/prs/vllm/PR-15893.md), [[Hardware][Gaudi][BugFix] fix arguments of hpu fused moe](../sources/prs/vllm/PR-15945.md), [Add support to modelopt quantization of Mixtral model](../sources/prs/vllm/PR-15961.md), [[NVIDIA] Support Cutlass MLA for Blackwell GPUs](../sources/prs/vllm/PR-16032.md), [[Kernel] Use moe_wna16 kernel for compressed tensors wna16 moe models](../sources/prs/vllm/PR-16038.md), [[Model] use AutoWeightsLoader for phimoe,qwen2_moe,qwen3_moe](../sources/prs/vllm/PR-16203.md), [[Hardware][AMD] Improve OAM device ID + llama4 Maverick MOE tuning](../sources/prs/vllm/PR-16263.md), [[Llama4] Enable attention temperature tuning by default for long context (>32k)](../sources/prs/vllm/PR-16439.md), [[MLA] Simplification to batch P/D reordering](../sources/prs/vllm/PR-16673.md), [[ROCM] enable aiter fused moe kernel for llama4 bf16 checkpoints](../sources/prs/vllm/PR-16674.md), [[ROCm] Add aiter tkw1 kernel for Llama4 fp8](../sources/prs/vllm/PR-16727.md), [Support W8A8 INT8 MoE for compressed-tensors](../sources/prs/vllm/PR-16745.md), [[FEAT] [ROCm]: AITER Fused MOE V1 Support](../sources/prs/vllm/PR-16752.md), [[Bugfix] Fix moe weight losing all extra attrs after `process_weights_after_loading`.](../sources/prs/vllm/PR-16854.md), [[Bugfix] Add contiguous call inside rope kernel wrapper](../sources/prs/vllm/PR-17091.md), [[FEAT] [ROCm]: Add AITER CK 2 Stages MoE support](../sources/prs/vllm/PR-17110.md), [[Bugfix] gemma[2,3] interleaved attention when sliding window is disabled](../sources/prs/vllm/PR-17180.md), [[Bugfix] Get a specific type of layer from forward context](../sources/prs/vllm/PR-17222.md), [[BugFix] Fix vllm_flash_attn install issues](../sources/prs/vllm/PR-17267.md), [[BugFix] Fix cascade attention - RuntimeError: scheduler_metadata must have shape (metadata_size)](../sources/prs/vllm/PR-17283.md), [[v1] AttentionMetadata for each layer](../sources/prs/vllm/PR-17394.md), [Fix noisy warning for uncalibrated q_scale/p_scale](../sources/prs/vllm/PR-17414.md), [[v1] Pass BlockTable and KVCacheSpec to AttentionMetadataBuilders](../sources/prs/vllm/PR-17483.md), [[BugFix] Fix mla cpu - missing 3 required positional arguments](../sources/prs/vllm/PR-17494.md), [[FEAT][ROCm]: Support AITER MLA on V1 Engine](../sources/prs/vllm/PR-17523.md), [[Bugfix][ROCm] Fix AITER MLA V1](../sources/prs/vllm/PR-17880.md), [[BugFix][AMD] Compatible patch for AITER lib after 04/20](../sources/prs/vllm/PR-17912.md), [[Misc] Add compressed-tensors NVFP4A16 emulation support](../sources/prs/vllm/PR-17914.md), [use ceil_div in cutlass block scaling shape check](../sources/prs/vllm/PR-17918.md), [[v1] Support multiple KV cache groups in GPU model runner](../sources/prs/vllm/PR-17945.md), [[BUG] [ROCm] [MLA] Fix variable name bug due to change in variable name in PR #17483](../sources/prs/vllm/PR-17961.md), [Use NVFP4 Marlin for CompressedTensorsW4A16Fp4](../sources/prs/vllm/PR-18000.md), [[Quantization] Add compressed-tensors NVFP4 support](../sources/prs/vllm/PR-18312.md), [[Model]: Fused MoE for nomic-embed-text-v2-moe](../sources/prs/vllm/PR-18321.md), [[Feature] Expert Parallelism Load Balancer (EPLB)](../sources/prs/vllm/PR-18343.md), [[Bug] Fix moe_sum signature](../sources/prs/vllm/PR-18440.md), [[V1] Support `LLM.apply_model`](../sources/prs/vllm/PR-18465.md), [[Hardware][AMD] integrate aiter chunked prefill into vllm](../sources/prs/vllm/PR-18596.md), [[P/D] Heterogeneous TP](../sources/prs/vllm/PR-18833.md), [[ROCm] [AITER] [Bugfix] Patch for AITER commit `648764942e552a8bb5fe16026703716a81f05374`](../sources/prs/vllm/PR-18990.md), [[Kernel] Support deep_gemm for linear methods](../sources/prs/vllm/PR-19085.md), [[Kernel] Apply torch.Tag.needs_fixed_stride_order only for torch==2.6.0](../sources/prs/vllm/PR-19346.md), [[Core] Support Local Chunked Attention for Hybrid KV Cache](../sources/prs/vllm/PR-19351.md), [[Kernels] Use empty for modular MoE workspaces](../sources/prs/vllm/PR-19667.md), [[Feature] Integrate new deepgemm](../sources/prs/vllm/PR-19820.md), [[Bugfix] Enable PP with AITER+V1](../sources/prs/vllm/PR-19822.md), [[Quantization] Add compressed-tensors emulations support for NVFP4](../sources/prs/vllm/PR-19879.md), [[Quantization] Add compressed-tensors NVFP4 MoE Support](../sources/prs/vllm/PR-19990.md), [Enable V1 for Hybrid SSM/Attention Models](../sources/prs/vllm/PR-20016.md), [[Attention] MLA - Flashinfer Ragged Prefill](../sources/prs/vllm/PR-20034.md), [Add ModelOpt Qwen3 nvfp4 support](../sources/prs/vllm/PR-20101.md), [[Bugfix] Mark 'hidden_states' as mutable in moe_forward registration.](../sources/prs/vllm/PR-20152.md), [[Bugfix] Fix Maverick correctness by filling zero to cache space in cutlass_moe](../sources/prs/vllm/PR-20167.md), [[Nixl] Heterogeneous TP support FlashInfer](../sources/prs/vllm/PR-20189.md), [[V1] [ROCm] Enable EP with AITER Fused MoE](../sources/prs/vllm/PR-20270.md), [Support Llama 4 for cutlass_moe_fp4](../sources/prs/vllm/PR-20453.md), [Support Llama 4 for fused_marlin_moe](../sources/prs/vllm/PR-20457.md), [[Perf] Reuse workspace for FP8+FP4 Marlin MoE](../sources/prs/vllm/PR-20500.md), [[Bugfix] Fix missing per_act_token parameter in compressed_tensors_moe](../sources/prs/vllm/PR-20509.md), [[feat] enable SM100 CUTLASS block scaled group gemm for smaller batch sizes](../sources/prs/vllm/PR-20640.md), [Integration SM100 FlashInfer fused allreduce RMSNorm](../sources/prs/vllm/PR-20691.md), [GLM-4.5 Model Support](../sources/prs/vllm/PR-20736.md), [[v1][core] Support for attention free models](../sources/prs/vllm/PR-20811.md), [[Feature][EPLB] Add eplb support for Qwen3](../sources/prs/vllm/PR-20815.md), [[Bugfix] Fix a couple PPLX+CUTLASS MoE bugs](../sources/prs/vllm/PR-20825.md), [[Bug] Fix DeepGemm for EP low latency case](../sources/prs/vllm/PR-20833.md), [[Model] Pooling models default to using chunked prefill & prefix caching if supported.](../sources/prs/vllm/PR-20930.md), [[Misc] Qwen MoE model supports LoRA](../sources/prs/vllm/PR-20932.md), [[Bugfix] Switch bailout logic for kv-cache-dtype with SM100 Flashinfer](../sources/prs/vllm/PR-20934.md), [Fall back if flashinfer comm module not found](../sources/prs/vllm/PR-20936.md), [[Bugfix] Fix Mistral3 support on SM100/SM120](../sources/prs/vllm/PR-20998.md), [Add FlashInfer allreduce RMSNorm Quant fusion](../sources/prs/vllm/PR-21069.md), [[Bugfix] Voxtral on Blackwell GPUs (RTX 50 series)](../sources/prs/vllm/PR-21077.md), [[Bugfix] Allocate less memory in non-batched CUTLASS MoE](../sources/prs/vllm/PR-21121.md), [[Attention] Optimize FlashInfer MetadataBuilder Build call](../sources/prs/vllm/PR-21137.md), [[Attention][DBO] Add support for "splitting" the CommonAttentionMetadata](../sources/prs/vllm/PR-21153.md), [[Feature][OCP MX] Support mxfp6 and mixed mxfp6-mxfp4](../sources/prs/vllm/PR-21166.md), [[Bug] DeepGemm: Fix TypeError: per_block_cast_to_fp8() missing 1 required positional argument: 'use_ue8m0' for SM100](../sources/prs/vllm/PR-21187.md), [Support encoder-only models without KV-Cache](../sources/prs/vllm/PR-21270.md), [Fix Flashinfer Allreduce+Norm enable disable calculation based on `fi_allreduce_fusion_max_token_num`](../sources/prs/vllm/PR-21325.md), [Support Tensorrt-LLM MoE fp4 for low-latency](../sources/prs/vllm/PR-21331.md), [[TPU][Bugfix] fix moe layer](../sources/prs/vllm/PR-21340.md), [[Quantization] Enable BNB support for more MoE models](../sources/prs/vllm/PR-21370.md), [Update flashinfer CUTLASS NVFP4 MoE Kernel to use per expert global scaling factor](../sources/prs/vllm/PR-21408.md), [[NVIDIA] Explicitly disable shuffled weights for flashinfer blockscale moe fp8 kernels](../sources/prs/vllm/PR-21411.md), [Updates to Flex + VLLm integration](../sources/prs/vllm/PR-21416.md), [[V1] Fix local chunked attention always disabled](../sources/prs/vllm/PR-21419.md), [[BugFix] Fix shared storage connector load kv only load attention layer](../sources/prs/vllm/PR-21428.md), [update flashinfer to v0.2.9rc1](../sources/prs/vllm/PR-21485.md), [[MoE] More balanced expert sharding](../sources/prs/vllm/PR-21497.md), [[NVIDIA] Fix Llama4 Scout FP4 functionality issues](../sources/prs/vllm/PR-21499.md), [Enable 4bit bnb prequant MOE](../sources/prs/vllm/PR-21548.md), [[Attention] Support multiple attention metadata builders per kv_cache_spec + proper local attention no hybrid kv cache fix](../sources/prs/vllm/PR-21588.md), [Override attention metadata for fast prefill in some KV sharing setups](../sources/prs/vllm/PR-21590.md), [[Feature] Add Flashinfer MoE Support for Compressed Tensor NVFP4](../sources/prs/vllm/PR-21639.md), [[xpu]support moe models on XPU platform](../sources/prs/vllm/PR-21643.md), [support `torch.compile` for bailing moe](../sources/prs/vllm/PR-21664.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv/out Attention Kernel](../sources/prs/vllm/PR-21716.md), [feat: Add Support GPTQ Quantization MOE on ROCM vllm serve](../sources/prs/vllm/PR-21733.md), [[Logs] Change flashinfer sampler logs to once](../sources/prs/vllm/PR-21759.md), [[Perf] Disable chunked local attention by default with llama4](../sources/prs/vllm/PR-21761.md), [[Bugfix] Check NVIDIA artifactory is accessible before using flashinfer cubin kernels](../sources/prs/vllm/PR-21893.md), [[Qwen3] Enable dual-chunk-attention support for Qwen3 models.](../sources/prs/vllm/PR-21924.md), [[BUGFIX] KeyError 'layers.14.mlp.gate.g_idx' for Qwen3-MoE with GPTQ on ROCm](../sources/prs/vllm/PR-22017.md), [[NVIDIA] Support Flashinfer TRT-LLM Prefill Attention Kernel](../sources/prs/vllm/PR-22095.md), [[EPLB] Support ernie4.5-moe](../sources/prs/vllm/PR-22100.md), [[fix] fix correct assertion syntax error in attention utils.](../sources/prs/vllm/PR-22154.md), [[bugfix] fix blackwell deepep installation](../sources/prs/vllm/PR-22255.md), [[Bugfix] Fix MoE BNB version](../sources/prs/vllm/PR-22260.md), [Support encoder_only attention for FlexAttention](../sources/prs/vllm/PR-22273.md), [[Bugfix] Fix 3D input passed into cutlass_scaled_mm](../sources/prs/vllm/PR-22278.md), [[ROCm] Add attention sink to use_rocm_custom_paged_attention](../sources/prs/vllm/PR-22329.md), [[gpt-oss] flashinfer mxfp4](../sources/prs/vllm/PR-22339.md), [Update `flashinfer-python==0.2.10`](../sources/prs/vllm/PR-22389.md), [[Bug] Fix B200 DeepGEMM E8M0 Accuracy Issue](../sources/prs/vllm/PR-22399.md), [[bugfix] Fix Llama3/4 issues caused by FlashInfer 0.2.10](../sources/prs/vllm/PR-22426.md), [[Quantization]: Support compressed-tensors mixed-precision model loading](../sources/prs/vllm/PR-22468.md), [Fix Llama4 FlashInfer FP4 MoE issues](../sources/prs/vllm/PR-22511.md), [[Model] Add Ernie4.5 VL Model Support](../sources/prs/vllm/PR-22514.md), [Quantization: support FP4 quantized models on AMD CDNA2/CDNA3 GPUs](../sources/prs/vllm/PR-22527.md), [Fix torch version check for SM100 mxfp4 ](../sources/prs/vllm/PR-22535.md), [Upgrade FlashInfer to v0.2.11](../sources/prs/vllm/PR-22613.md), [[Bugfix] Fix ModernBert load & Enable sliding window attention for bidirectional attention.](../sources/prs/vllm/PR-22637.md), [Support multiple attention groups for KV sharing](../sources/prs/vllm/PR-22672.md), [[Quantization] Expand compressed-tensors MoE matching logic to support NFP4 + FP8 MoEs](../sources/prs/vllm/PR-22674.md), [Force TRTLLM attention for gpt-oss on SM100](../sources/prs/vllm/PR-22678.md), [[Bugfix] Fix default enable for CUTLASS MLA on SM100](../sources/prs/vllm/PR-22738.md), [Fix GGUF loader for Qwen3 MoE.](../sources/prs/vllm/PR-22785.md), [[FIXBUG] Add return_success parameter to moe_wna16_weight_loader function](../sources/prs/vllm/PR-22797.md), [[Model] Modify the gate implementation of glm4_moe](../sources/prs/vllm/PR-22832.md), [[XPU] support data parallel for MoE models on XPU](../sources/prs/vllm/PR-22887.md), [[Kernel] Added flashinfer fp8 per-tensor gemms](../sources/prs/vllm/PR-22895.md), [[Bugfix] Fix DeepSeek MTP](../sources/prs/vllm/PR-22934.md), [Use Blackwell FlashInfer MXFP4 MoE by default if available ](../sources/prs/vllm/PR-23008.md), [[Bugfix gpt-oss] Fix float32 convert for flashinfer sink support](../sources/prs/vllm/PR-23016.md), [[Bugfix] fix qwen3 moe fp8 accuracy issue](../sources/prs/vllm/PR-23031.md), [[Core] Support weight_loader_v2 for `UnquantizedLinearMethod`](../sources/prs/vllm/PR-23036.md), [Add routed_scaling_factor to MoE grouped topk](../sources/prs/vllm/PR-23123.md), [[Bugfix] Fix accuracy issue when using flashinfer cutlass moe, TP=1 and modelopt.](../sources/prs/vllm/PR-23125.md), [Update to flashinfer-python==0.2.12 and disable AOT compile for non-release image](../sources/prs/vllm/PR-23129.md), [[Log] Warning Once for Cutlass MLA ](../sources/prs/vllm/PR-23137.md), [Fix nvfp4 swizzling](../sources/prs/vllm/PR-23140.md), [[CPU] add cpu fused moe pytorch native implementation](../sources/prs/vllm/PR-23146.md), [[XPU][Feature] fp8 online quantization support for XPU](../sources/prs/vllm/PR-23148.md), [Optimize input preparation for FlashInfer [2/N]](../sources/prs/vllm/PR-23174.md), [[Attention] Optimize make_local_attention_virtual_batches for Flash Attention](../sources/prs/vllm/PR-23185.md), [[Misc][qwen2_5_vl][torch.compile] Enable `supports_torch_compile` on generic nn.Module and demonstrate speedup on Qwen Vision model](../sources/prs/vllm/PR-23207.md), [[Core] Always use tensor cores for Flashinfer Decode Wrapper](../sources/prs/vllm/PR-23214.md), [[Perf] Small optimizations for silu_mul_fp8_quant_deep_gemm](../sources/prs/vllm/PR-23265.md), [[Kernels] Overlap shared experts with send/recv](../sources/prs/vllm/PR-23273.md), [[Bug] Fix R1 Accuracy 0 Bug](../sources/prs/vllm/PR-23294.md), [[Attention] Allow V1 flash_attn to support cross-attention](../sources/prs/vllm/PR-23297.md), [[Perf] Warmup FlashInfer attention during startup](../sources/prs/vllm/PR-23439.md), [[Attention][FA3] Update FA3 to include new swizzle optimization](../sources/prs/vllm/PR-23465.md), [fix(v1/kv_cache): resolve async KV transfer bug in cascade attention](../sources/prs/vllm/PR-23485.md), [[Bugfix] Fix Qwen3 MoE GPTQ inference](../sources/prs/vllm/PR-23490.md), [[V1][P/D]P2pNcclConnector supports flashinfer](../sources/prs/vllm/PR-23536.md), [Update Flashinfer to 0.2.14.post1](../sources/prs/vllm/PR-23537.md), [[Misc] Simplify FlashInfer attention metadata](../sources/prs/vllm/PR-23585.md), [DP/EP Support for gpt-oss with deepep-ht comm kernel on SM100](../sources/prs/vllm/PR-23608.md), [[Flashinfer] Support Flashinfer TRTLLM FP8-qkv BF16/FP16-out Attention Kernel](../sources/prs/vllm/PR-23647.md), [[Bugfix] Fix Marlin NVFP4 for modelopt](../sources/prs/vllm/PR-23659.md), [[v1] Add cross-attention KV cache support for encoder-decoder models](../sources/prs/vllm/PR-23664.md), [[Core/DBO][1/N] Add Dual-Batch Overlap mechanism to VLLM](../sources/prs/vllm/PR-23693.md), [[Kernel][B200] mxfp4 fused cutlass moe](../sources/prs/vllm/PR-23696.md), [[FlashInfer] Cache hyper params in metadata builder](../sources/prs/vllm/PR-23732.md), [[BugFix][FlashInfer] Fix potential race condition for paged_kv_indptr_cpu](../sources/prs/vllm/PR-23737.md), [[Feat][EPLB] A novel static EPLB placement strategy for MoE models.](../sources/prs/vllm/PR-23745.md), [[Misc] add reorder_batch AttentionMetadataBuilder](../sources/prs/vllm/PR-23798.md), [[fix]: add Arm 4bit fused moe support](../sources/prs/vllm/PR-23809.md), [[Model][gpt-oss] Support DP+EP for GPT-OSS with FlashInfer trtllm-gen MoE](../sources/prs/vllm/PR-23819.md), [[BUGFIX ] fix undefined silu_and_mul_nvfp4_quant](../sources/prs/vllm/PR-23929.md), [Feature/vit attention unification# 23880](../sources/prs/vllm/PR-23978.md), [[BUGFIX] GPTQ quantization compatibility for Qwen3 MOE models (AutoGPTQ and AutoRound-GPTQ)](../sources/prs/vllm/PR-23994.md), [[PERF] Allreduce fusion. Support torch native matching. Tuning of the thresholds](../sources/prs/vllm/PR-24248.md), [[Transform] [Quantization] Add QuTLASS support to vLLM](../sources/prs/vllm/PR-24440.md), [[Feature] Disallow FlashMLA on Blackwell](../sources/prs/vllm/PR-24521.md), [[Performance] Move apply_w8a8_block_fp8_linear to an op class](../sources/prs/vllm/PR-24666.md), [[Model] Support Qwen3-VL Model Series](../sources/prs/vllm/PR-24727.md), [[Bug] Fix `is_flashmla_supported` Check Error](../sources/prs/vllm/PR-24774.md), [[DCP] Support Decode Context Parallel (DCP) for GQA with FlashAttention](../sources/prs/vllm/PR-24864.md), [[Attention][DCP] Support DCP with query length > 1 (MTP) with FA3](../sources/prs/vllm/PR-25049.md), [[Bug] Fix `returned_lse` not Defined issue](../sources/prs/vllm/PR-25106.md), [[ROCm] Small functional changes for gptoss](../sources/prs/vllm/PR-25201.md), [[BugFix] Fix MLA assert with CUTLASS MLA](../sources/prs/vllm/PR-25478.md), [feat: BF16 FlashInfer Fused Cutlass MOE for Hopper and Blackwell Expert Parallel](../sources/prs/vllm/PR-25503.md), [Enable Fbgemm NVFP4 on Dense models](../sources/prs/vllm/PR-25609.md), [[Flashinfer][gpt-oss] Support FP8-qkv Flashinfer TRTLLM Sinks Attention](../sources/prs/vllm/PR-25674.md), [[Bugfix] Enable padded FP4 quantization](../sources/prs/vllm/PR-25947.md), [[Quantization/NVFP4] Speed up TRTLLM NVFP4 MOE weight loading and fix K/V scale loading for MLA Attn](../sources/prs/vllm/PR-25968.md), [[Spec Decode] Enable efficient speculative decoding with FlashInfer-MLA](../sources/prs/vllm/PR-25984.md), [[Bugfix] Allow skipping MoE in NVFP4 (fix for MTP)](../sources/prs/vllm/PR-25987.md), [[NVIDIA] Add support for cudnn fp4 gemm via flashinfer](../sources/prs/vllm/PR-26107.md), [[ModelOpt] Load w13/w2_input_scale for all experts, nvfp4](../sources/prs/vllm/PR-26135.md), [[Performance] Dual stream execution of "shared_experts" and "selected_experts" inside FusedMoE](../sources/prs/vllm/PR-26440.md), [[Bugfix] Convert untraceable GroupShape to list for AMD impl](../sources/prs/vllm/PR-26535.md), [[ROCM] MoE fp4 CK kernel](../sources/prs/vllm/PR-26545.md), [support flashinfer_fp4 moe for 5090 gpu](../sources/prs/vllm/PR-26669.md), [[Bugfix] Fix gpt-oss w4a8 DP/EP on B200](../sources/prs/vllm/PR-26729.md), [Disable FlashInfer sampler by default](../sources/prs/vllm/PR-26859.md), [[Feature] Batch Invariant: Support DeepGEMM and Blackwell](../sources/prs/vllm/PR-27127.md), [[Kernels] Enable FlashInfer FP8 Blockscale on SM90 (for TEP DSR1)](../sources/prs/vllm/PR-27134.md), [[torch.compile] Enable silu_mul_fp8_quant fusion without custom ops enabled](../sources/prs/vllm/PR-27146.md), [[ROCM] Enable CompressedTensorsWNA16](../sources/prs/vllm/PR-27187.md), [[BUGFIX][ROCM] ViT FlashAttention on ROCm (no GFX9) and contiguous on qwen3vl ROCm TORCH_SDPA](../sources/prs/vllm/PR-27190.md), [Flashinfer_CUTLASS_MOE fuses quantization for TP](../sources/prs/vllm/PR-27223.md), [[Feature] Batch Invariant for R1 TP 8 on Blackwell](../sources/prs/vllm/PR-27229.md), [[Bugfix] Ensure calculated KV scales are applied in attention.](../sources/prs/vllm/PR-27232.md), [Bugfix: Cutlass FP8 FusedMoE bad scaling factors](../sources/prs/vllm/PR-27255.md), [Feature: Support Relu2 in FusedMoE fp8 cutlass path](../sources/prs/vllm/PR-27261.md), [[Misc] Make reorder batch also separate extends](../sources/prs/vllm/PR-27367.md), [[Performance] Support FP8 flashinfer TRTLLM MOE on Qwen3 and Qwen-3next](../sources/prs/vllm/PR-27492.md), [[Feature] Batch invariant torch.compile](../sources/prs/vllm/PR-27660.md), [[AMD] Use Decoupled Kernel Block Size to Support AITER MLA block_size=1](../sources/prs/vllm/PR-27715.md), [[Feature] Extend batch invariant torch.compile to B200](../sources/prs/vllm/PR-27856.md), [[Bug] Batch invariant: Fix flash attn MLA `RuntimeError: scheduler_metadata must have shape (metadata_size)`](../sources/prs/vllm/PR-27884.md), [[Performance][B200] Fix deepgemm prologue](../sources/prs/vllm/PR-27897.md), [[flashinfer][fix] do not check nvcc availability when using pre-downloaded cubins](../sources/prs/vllm/PR-27990.md), [[FlashInfer] Avoid FlashInfer block_size 16 + head_size 256 on blackwell](../sources/prs/vllm/PR-27994.md), [[ROCm][MLA] enable fp8 MLA decode on ROCm](../sources/prs/vllm/PR-28032.md), [[Model] Consolidate Deepseek-MoE implementation with DeepSeek-v2](../sources/prs/vllm/PR-28101.md), [[Mamba] - Consolidate Mambas Attention Logic](../sources/prs/vllm/PR-28133.md), [[flashinfer] fix FI all2all with FI cutlass moe](../sources/prs/vllm/PR-28166.md), [[Feature] Support recording expert indices for rollout router replay](../sources/prs/vllm/PR-28284.md), [[ROCm] Support for Whisper v1 with Aiter Unified Attention and Aiter Flash Attention](../sources/prs/vllm/PR-28376.md), [[Bugfix][EPLB] Disabled shared expert overlap when EPLB is enabled](../sources/prs/vllm/PR-28377.md), [[Bugfix] Fix SM100 gpt-oss regression due to faulty attn sink support](../sources/prs/vllm/PR-28561.md), [[Attention][Bugfix] Fix FA sink support](../sources/prs/vllm/PR-28660.md), [[Bugfix][Nixl] Fix kernel physical<>logical block_size issue ](../sources/prs/vllm/PR-28677.md), [[Performance] Reduce DeepGEMM N dim restriction from 128 to 64 multiplier ](../sources/prs/vllm/PR-28687.md), [[Feature] Prefill Context Parallel (PCP) basic support](../sources/prs/vllm/PR-28718.md), [[Bugfix] Fix GPT-OSS on AMD after #28603](../sources/prs/vllm/PR-28816.md), [bugfix: correct attn output with base 2 or e](../sources/prs/vllm/PR-28840.md), [[Bugfix] Fix GPT-OSS AR+NORM fusion](../sources/prs/vllm/PR-28841.md), [[Bugfix] Make compressed-tensors MoEs respect ignored layers](../sources/prs/vllm/PR-28878.md), [Add TRTLLM MoE NVFP4 kernel to CompressedTensorsW4A4MoeMethod](../sources/prs/vllm/PR-28892.md), [[BugFix] Fix async-scheduling + FlashAttn MLA](../sources/prs/vllm/PR-28990.md), [[Feat] Support non-gated activations in NVFP4 modelopt path](../sources/prs/vllm/PR-29004.md), [[DeepSeek + LMCache Multiprocess] handle MLA for deepseek model + LMCache Multiprocess connector](../sources/prs/vllm/PR-29039.md), [[Perf][Kernels] Enable FlashInfer DeepGEMM swapAB on SM90 (for W8A8 Linear Op)](../sources/prs/vllm/PR-29213.md), [[LoRA] Optimize 3D MoE logic](../sources/prs/vllm/PR-29222.md), [[Perf] Disable DeepGEMM MoE by default when TP=8 is used](../sources/prs/vllm/PR-29346.md), [Add unpermute-aware fused MoE path and small-batch fallback](../sources/prs/vllm/PR-29354.md), [[Bugfix] Fix grouped_topk pytorch impl when num_experts can't be grouped properly](../sources/prs/vllm/PR-29439.md), [[Attention] Cache attention metadata builds across hybrid KV-cache groups](../sources/prs/vllm/PR-29627.md), [[Bugfix] Defunctionalize TRTLLM AR+Norm op for avoiding extra clone kernel before it](../sources/prs/vllm/PR-29631.md), [[Attention] Make `split_decodes_and_prefills(..., require_uniform=True)` support padding](../sources/prs/vllm/PR-29644.md), [[perf] Use direct copy (broadcast) instead of cat for k_nope/k_pe in MLA prefill](../sources/prs/vllm/PR-29710.md), [[Quantization] Enable compressed-tensors AWQ for Turing GPU](../sources/prs/vllm/PR-29732.md), [[Bugfix] Fix mismatched nvfp4 gemm output shape](../sources/prs/vllm/PR-29742.md), [[MoE-FP8-modelopt] Add FlashInfer alignment padding for intermediate dimensions](../sources/prs/vllm/PR-29748.md), [Add Mistral Large 3 and Ministral 3](../sources/prs/vllm/PR-29757.md), [[ROCm] [Fused Moe EP] Use binary expert mask for aiter fused moe kernel](../sources/prs/vllm/PR-29773.md), [[ROCm][MXFP4] Infer w4a4 quant method in rocm aiter fused moe](../sources/prs/vllm/PR-29775.md), [[EPLB] Support EPLB w/ NVFP4](../sources/prs/vllm/PR-29804.md), [[Bugfix][Model] Support LoRA on Qwen3 Output Embedding](../sources/prs/vllm/PR-29816.md), [[SpecDecode] Simplified alternative padded-speculation acceptance rate fix](../sources/prs/vllm/PR-29845.md), [[Quantization] fix: overflow with static per-tensor scaling](../sources/prs/vllm/PR-29867.md), [[Bugfix] Fix FP8 MoE LoRA](../sources/prs/vllm/PR-29890.md), [[BugFix] Fix DBO assert `assert B_block_table == B_q`](../sources/prs/vllm/PR-29933.md), [[moe] Use enable_chunking func (to support disabling chunking)](../sources/prs/vllm/PR-29935.md), [[moe] Allow disabling DP chunking](../sources/prs/vllm/PR-29936.md), [[Bugfix] Fix flashinfer ar+norm kernel not available issue](../sources/prs/vllm/PR-29960.md), [[ROCm] add fallback for aiter fp8 decode mla](../sources/prs/vllm/PR-30005.md), [[Quantization] Support Quark int4-fp8 w4a8 for MoE](../sources/prs/vllm/PR-30071.md), [[Model][Quantization] Restore MoE + GGUF models support (incl. Qwen3 MoE) by allowing Sideload Parameters](../sources/prs/vllm/PR-30116.md), [[Model][Quantization] Override HF defaults to GGUF ones (incl. Qwen3 MoE)](../sources/prs/vllm/PR-30118.md), [Nvidia ModelOpt workaround for issue 28072](../sources/prs/vllm/PR-30164.md), [Add latent MoE support](../sources/prs/vllm/PR-30203.md), [[Bugfix]: Fix glm46 awq marlin moe wna16 compatibility](../sources/prs/vllm/PR-30210.md), [[LoRA] Reduce the loading time of MoE LoRA](../sources/prs/vllm/PR-30243.md), [[Bugfix] Fix DeepGEMM after #29546 ](../sources/prs/vllm/PR-30267.md), [[Model][Quantization] Fix / Add GGUF support for Qwen2 MoE models](../sources/prs/vllm/PR-30307.md), [[bugfix][quantization] fix quark qwen3 kv_cache quantization](../sources/prs/vllm/PR-30308.md), [[fix] fix SM check for Flashinfer TRTLLM MOE](../sources/prs/vllm/PR-30314.md), [[Bugfix] Fix fp8 DeepGemm compilation issues](../sources/prs/vllm/PR-30336.md), [[BugFix] Fix `AttributeError: 'MergedColumnParallelLinear' object has no attribute 'weight_scale'`](../sources/prs/vllm/PR-30399.md), [fix(gguf): Disable bfloat16 for GGUF on blackwell device](../sources/prs/vllm/PR-30408.md), [[ROCm][Bugfix] Add MLACommonMetadata to allowed attention types for speculative decoding](../sources/prs/vllm/PR-30430.md), [[Bugfix] Pass FA version in `MultiHeadAttention`](../sources/prs/vllm/PR-30575.md), [[Perf] Eliminate padding and slicing op for GPT-OSS with Flashinfer MXFP4 MXFP8 MoE](../sources/prs/vllm/PR-30647.md), [[Misc][LLaMa4] Compile LLaMa Vision Encoder](../sources/prs/vllm/PR-30709.md), [Update note comment for flashinfer attention warmup](../sources/prs/vllm/PR-30711.md), [[Perf] enable flashinfer rotary_embedding custom ops in DeepSeek rotary](../sources/prs/vllm/PR-30729.md), [[Bugfix] Fix broken ViT attention selection for Blackwell device](../sources/prs/vllm/PR-30731.md), [[SM100] Enable fp8 compute for prefill MLA](../sources/prs/vllm/PR-30746.md), [Add support for LoRA adapters in Nemotron-H models](../sources/prs/vllm/PR-30802.md), [[Kernels][FI] Skip trtllm attention when num_kv_heads=1](../sources/prs/vllm/PR-30842.md), [[Compressed-Tensors] Simplify NVFP4 Conditions, enable marlin support for NVFP4A16 MoEs](../sources/prs/vllm/PR-30881.md), [[Kernel][Performance] Enable smaller Scaling Factor tiling for NVFP4 small-batch decoding](../sources/prs/vllm/PR-30885.md), [[Feature]: Support NVIDIA ModelOpt HF FP8 variants FP8_PER_CHANNEL_PER_TOKEN and FP8_PB_WO in vLLM](../sources/prs/vllm/PR-30957.md), [[Mics] add pcp basic support to MoE model](../sources/prs/vllm/PR-31003.md), [[Bugfix] Fix GLM-4 MoE router logits dtype for data parallel chunking](../sources/prs/vllm/PR-31055.md), [ [FIX] Always support TP > 4 for FP4 Gemm](../sources/prs/vllm/PR-31099.md), [[BugFix] LoRA: Support loading base_layer of experts](../sources/prs/vllm/PR-31104.md), [[Bugfix][Hardware][AMD] Consolidate FP8 min/max values helper function](../sources/prs/vllm/PR-31106.md), [[Misc] Fix grammar errors in comments and messages](../sources/prs/vllm/PR-31115.md), [[Bugfix] Fix MoE LoRA bin/pt loading](../sources/prs/vllm/PR-31161.md), [[perf] Integrate flashinfer concat_mla_k](../sources/prs/vllm/PR-31171.md), [[Bugfix][Hardware][AMD] Fix exception types in AITER MLA FP8 check](../sources/prs/vllm/PR-31177.md), [[SM100] Resubmit FMHA FP8 prefill for MLA](../sources/prs/vllm/PR-31195.md), [[Bugfix][Hardware][AMD] Fix last_page_len calculation in AITER MLA decode](../sources/prs/vllm/PR-31282.md), [fix(rocm): add early return in get_flash_attn_version for ROCm](../sources/prs/vllm/PR-31286.md), [pin lora_b moe weights on cpu](../sources/prs/vllm/PR-31317.md), [[Misc] Fix Qwen2-MoE shared_expert_gate](../sources/prs/vllm/PR-31339.md), [[BugFix] add select_gemm_impl on CompressedTensorsWNA16MoEMethod to support LoRA](../sources/prs/vllm/PR-31453.md), [[Bugfix][ROCm] Fix Static Quant Issue](../sources/prs/vllm/PR-31502.md), [[ROCm][Bugfix] Fix accuracy issue on fmoe when `VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS` enabled](../sources/prs/vllm/PR-31523.md), [Use the same memory for workspace13 and fused_output.](../sources/prs/vllm/PR-31531.md), [[Fix] Align fused moe lora_b shape with peft](../sources/prs/vllm/PR-31534.md), [[Bugfix] Fix Broken ModelOpt NVFP4 MoE](../sources/prs/vllm/PR-31742.md), [[Perf] Add opt-in SM100 Oink RMSNorm custom-op path](../sources/prs/vllm/PR-31828.md), [[MISC] Add strict contiguity check for FlashInfer attention tensors](../sources/prs/vllm/PR-32008.md), [[5/N][Attention] Finish eliminating `vllm/attention` folder](../sources/prs/vllm/PR-32064.md), [[BugFix] Fix DeepSeek-V3.1 + DeepGEMM incompatible scale shapes](../sources/prs/vllm/PR-32361.md), [[Model] Molmo2: Enable quantized weight mapping for vision backbone](../sources/prs/vllm/PR-32385.md), [[Hardware][SM100] Add TRTLLM Kernel for INT4 W4A16 Kernel.](../sources/prs/vllm/PR-32437.md), [[Perf] Create TMA-aligned input scale tensor for DeepGemm on Hopper](../sources/prs/vllm/PR-32619.md), [[Kernel] use flashinfer for gdn prefill](../sources/prs/vllm/PR-32846.md), [[Performance] Tune Mamba selective scan kernel for B200](../sources/prs/vllm/PR-32873.md), [[Bugfix] Fix FP8 MoE EP Weight Loading for ModelOpt Llama4](../sources/prs/vllm/PR-32886.md), [[Spec Decode] Unified Parallel Drafting](../sources/prs/vllm/PR-32887.md), [[ROCm][perf] Shuffle KV cache to use paged_attention_common](../sources/prs/vllm/PR-32914.md), [[NVIDIA] [feat] Integrate flashinfer Trtllmgen bf16 moe](../sources/prs/vllm/PR-32954.md), [Support compress-tensors with nvfp4 or fp8 weights and modelopt with nvfp4 weights on Turing](../sources/prs/vllm/PR-33076.md), [[Attention] Use `has_flashinfer` helper](../sources/prs/vllm/PR-33177.md), [[Bugfix] Disable TRTLLM attention when KV transfer is enabled](../sources/prs/vllm/PR-33192.md), [[Bugfix] Register fp8 cutlass_group_gemm as supported for only SM90+SM100](../sources/prs/vllm/PR-33285.md), [[PERF] Change GDN Attention State Layout from [N, HV, K, V] to [N, HV, V, K]](../sources/prs/vllm/PR-33291.md), [[Kernel] Support Flashinfer trtllm fused MoE non gated FP8 & NVFP4](../sources/prs/vllm/PR-33506.md), [[Perf] Disable clean_logits in deepgemm fp8_mqa_logits kernel](../sources/prs/vllm/PR-33568.md), [[Bugfix] Fix sparse MLA metadata building](../sources/prs/vllm/PR-33579.md), [[Bugfix] fix DeepSeek R1 with CUTLASS MLA Broken on B200](../sources/prs/vllm/PR-33637.md), [enable skipping of SW attention layers when using FP8 KV cache](../sources/prs/vllm/PR-33695.md), [[Bugfix] Fix DSV3.2 NVFP4](../sources/prs/vllm/PR-33932.md), [Adding support to Sarvam's MoE models](../sources/prs/vllm/PR-33942.md), [[Bugfix] Relax TRTLLM KV cache contiguity assertion for cross-layer layout](../sources/prs/vllm/PR-34158.md), [[Bugfix] Fix DP Attention Padding in Dummy Run](../sources/prs/vllm/PR-34187.md), [[ModelBash][DSR1 NVFp4] Avoid Bf16 Bias Cast](../sources/prs/vllm/PR-34298.md), [[CPU][Perf] Accelerate Attention head for s390x using vector intrinsics](../sources/prs/vllm/PR-34434.md), [[Llama4,Quantization] Simplify and generalize logic for Q/K permutations in quantized self-attn layers ](../sources/prs/vllm/PR-34471.md), [[BUGFIX] Fix accuracy regression for NVIDIA-Nemotron-3-Nano-30B-A3B-NVFP4 with TP>1](../sources/prs/vllm/PR-34476.md), [[Model] Add NVFP4 quantization support for Step3.5-Flash](../sources/prs/vllm/PR-34478.md), [[Bugfix] Handle num_expert_group=None in flashinfer block-scale FP8 MoE](../sources/prs/vllm/PR-34494.md), [[BugFix] Add support for MTP num_speculative_tokens > 1 with sparse MLA](../sources/prs/vllm/PR-34552.md), [[Quantization] add humming quantization kernel](../sources/prs/vllm/PR-34556.md), [[Bugfix] Rescale NVFP4 weight scales to fix BF16 dequant underflow](../sources/prs/vllm/PR-34577.md), [[Update] Use FlashInfer fast_decode_plan directly instead of replication](../sources/prs/vllm/PR-34687.md), [[Bugfix] Fix MLA attention crash with AWQ/GPTQ quantized models](../sources/prs/vllm/PR-34695.md), [[torch.compile] Turn on silu+fp4 quant fusion by default for O1+](../sources/prs/vllm/PR-34718.md), [[Bugfix] Fix NVFP4 TRTLLM MoE non-gated support; add gsm8k for Nemotron-3-Nano FP8+NVFP4](../sources/prs/vllm/PR-34725.md), [[Attention] Use FA4 for MLA prefill](../sources/prs/vllm/PR-34732.md), [[Bugfix] Fix GDN attention crash with mixed decode/spec-decode batches](../sources/prs/vllm/PR-34871.md), [[Model Bash][DSR1] Add selective dynamic shape marking for CustomOp](../sources/prs/vllm/PR-34900.md), [[Perf] Enable FlashInfer DeepGEMM swapAB on SM90 by default](../sources/prs/vllm/PR-34924.md), [add mixed precision support for modelopt](../sources/prs/vllm/PR-35047.md), [Integrate flashinfer mm_mxfp8 in ModelOpt MXFP8](../sources/prs/vllm/PR-35053.md), [[Bug][DSV3.2] Always prepare metadata for DeepGEMM Sparse Attention](../sources/prs/vllm/PR-35075.md), [[BUGFIX][Qwen3.5] Hardcode `mlp.gate` as not quantizable ](../sources/prs/vllm/PR-35156.md), [[Linear Attention] fix bug for linear attention + prefix caching + reset_prefix_cache](../sources/prs/vllm/PR-35157.md), [[BUGFIX][Mamba][Qwen3.5] Zero freed SSM cache blocks on GPU](../sources/prs/vllm/PR-35219.md), [[Performance] Extract KV cache update op from flashinfer forward](../sources/prs/vllm/PR-35422.md), [[Bugfix] Fix KV Scale loading for MLA Models](../sources/prs/vllm/PR-35430.md), [[Quant][Feature] Support online MXFP8 quantization for MoE and dense models](../sources/prs/vllm/PR-35448.md), [[NVFP4] Support NVFP4 dense models from `modelopt` and `compressed-tensors` on AMD Instinct MI300, MI355X and Hopper through emulation](../sources/prs/vllm/PR-35733.md), [Fix routed experts capture for hybrid models (Mamba + Attention)](../sources/prs/vllm/PR-35744.md), [[MoE][Perf] Wrap DSV3 QKVAProj GEMM in custom op for torch.compile](../sources/prs/vllm/PR-35751.md), [[Mamba] Add stochastic rounding support](../sources/prs/vllm/PR-35753.md), [[Kernel] Add fused_sigmoid_gating_delta_rule_update kernel for Qwen3 Next](../sources/prs/vllm/PR-35777.md), [[Bugfix] Fix score layer quantization for sequence classification models - Qwen3 (VL) Reranker](../sources/prs/vllm/PR-35849.md), [[ROCm] Support MLA with nhead<16 and FP8 KV cache for TP=8 (Kimi K2.5/Linear)](../sources/prs/vllm/PR-35850.md), [[Perf] Support FP8 KV cache for Flashinfer MLA Sparse](../sources/prs/vllm/PR-35891.md), [[MoE] Move PF Methods to Folder](../sources/prs/vllm/PR-35927.md), [Add support for ModelOpt MXFP8 MoE models](../sources/prs/vllm/PR-35986.md), [[Bugfix] Fix passing of activation_type to trtllm fused MoE NVFP4 and FP8](../sources/prs/vllm/PR-36017.md), [[BugFix] Fallback from FA4->FA2 for Batch Invariance](../sources/prs/vllm/PR-36059.md), [[LMCache] Pass TP size in lookup for MLA multi-reader locking](../sources/prs/vllm/PR-36129.md), [[Bugfix] Disable FlashInfer TRTLLM BF16 path for non-gated MoE](../sources/prs/vllm/PR-36146.md), [[Mamba] Flashinfer selective_state_update](../sources/prs/vllm/PR-36162.md), [[Bugfix][MLA] Add logits size budget to sparse indexer prefill chunking](../sources/prs/vllm/PR-36178.md), [[mla] Support fused FP8/NVFP4 output quantization in MLA attention (#35792)](../sources/prs/vllm/PR-36205.md), [mla: don't update kv cache on dummy forwards](../sources/prs/vllm/PR-36282.md), [[Perf] Add TRTLLM FP8 MoE Modular Kernel](../sources/prs/vllm/PR-36307.md), [Disable cascade attention by default](../sources/prs/vllm/PR-36318.md), [Kimi k2.5 MLA based eagle3](../sources/prs/vllm/PR-36361.md), [feat(attention): extract KV-cache update from FlashAttentionDiffKV ba…](../sources/prs/vllm/PR-36466.md), [[Bugfix][Sparse MLA] report indexer CG support properly](../sources/prs/vllm/PR-36519.md), [[ROCm] Utilize persistent MLA kernel from AITER](../sources/prs/vllm/PR-36574.md), [[GDN] add a config for gdn kernel selection](../sources/prs/vllm/PR-36647.md), [[Misc][Attention] Clean up unused method in `CPU_ATTN`](../sources/prs/vllm/PR-36673.md), [[Bug] Fix FlashInfer MNNVL socket collisions under concurrent vLLM jobs](../sources/prs/vllm/PR-36674.md), [[ROCm][Perf] Allow MTP lens > 1 in Sparse MLA](../sources/prs/vllm/PR-36681.md), [fix(kv-cache): increase hybrid attention grouping threshold from 1.25 to 1.5](../sources/prs/vllm/PR-36684.md), [[ROCm] Attention selector reordering](../sources/prs/vllm/PR-36702.md), [[DSV3.2][MTP] Optimize Indexer MTP handling](../sources/prs/vllm/PR-36723.md), [[Bug][MoE] Fix TRTLLM NVFP4 Routing Kernel Precision](../sources/prs/vllm/PR-36725.md), [[ROCm] Fix KV copy methods and auto-select attention backend for ROCm](../sources/prs/vllm/PR-36845.md), [[ROCm] Validate block_size for explicitly selected attention backends](../sources/prs/vllm/PR-36846.md), [[Feat][Spec Decode] DFlash](../sources/prs/vllm/PR-36847.md), [[Bugfix] Fix FlashInfer GDN warmup ValueError on SM90 GPUs](../sources/prs/vllm/PR-36876.md), [[Feat][Bugfix] Enable additional dimension for Flashinfer MLA and fix routing dtype](../sources/prs/vllm/PR-36931.md), [[Bugfix] Disable cross-layer KV cache for MLA attention backends](../sources/prs/vllm/PR-37090.md), [[Benchmark] Improvements to attention benchmark script](../sources/prs/vllm/PR-37115.md), [[XPU] support MLA model on Intel GPU](../sources/prs/vllm/PR-37143.md), [Fix minimax m2.5 nvfp4 kv scales weight loading](../sources/prs/vllm/PR-37214.md), [[ROCM][Bugfix] Use correct stride in cp_mha_gather_cache_kernel for hybrid model (#37228)](../sources/prs/vllm/PR-37228.md), [[Bugfix] Expand quantization method support in perf metrics](../sources/prs/vllm/PR-37231.md), [[Attention] Support distinguishing between short extends and decodes](../sources/prs/vllm/PR-37303.md), [[Bugfix] Fix EP weight filter breaking EPLB and NVFP4 accuracy](../sources/prs/vllm/PR-37322.md), [[Model Runner V2] fix draft attention metadata generation](../sources/prs/vllm/PR-37364.md), [[Bugfix] Remove assertion for NVFP4 scale dynamic range](../sources/prs/vllm/PR-37465.md), [[BugFix] Allow qk_nope_head_dim=192 in FlashInfer MLA backend checks](../sources/prs/vllm/PR-37475.md), [[Bugfix] Fix marlin nvfp4 rescaling](../sources/prs/vllm/PR-37502.md), [Fix KV Offloading + MLA AssertionError by using num_kv_heads=1 in cpu…](../sources/prs/vllm/PR-37536.md), [[Performance] Remove unnecessary zero-fill of MLA decode output tensor in Aiter backend](../sources/prs/vllm/PR-37539.md), [[Bugfix][ROCm] Fix lru_cache on paged_mqa_logits_module](../sources/prs/vllm/PR-37547.md), [[Bugfix] Disable --calculate-kv-scales for hybrid GDN/Mamba+Attention…](../sources/prs/vllm/PR-37565.md), [[Bugfix] Disable monolithic TRTLLM MoE for Renormalize routing (#37591)](../sources/prs/vllm/PR-37605.md), [[ROCm][Bugfix] fix cache block size mismatch for aiter unified attention](../sources/prs/vllm/PR-37606.md), [[Perf] Use torch compile to fuse pack topk in trtllm moe](../sources/prs/vllm/PR-37695.md), [[Bug] Fix fp8 deepgemm batch invariant](../sources/prs/vllm/PR-37718.md), [[Test] Only Run MLA model when user explicitly set for batch invariance](../sources/prs/vllm/PR-37719.md), [[XPU] add gptq(int4) support](../sources/prs/vllm/PR-37844.md), [[Feature] Support per-draft-model MoE backend via `--speculative-config`](../sources/prs/vllm/PR-37880.md), [[ROCm][perf] fix Aiter sparse MLA with MTP>1](../sources/prs/vllm/PR-37887.md), [[Bugfix] Fix DeepGemm E8M0 accuracy degradation for Qwen3.5 FP8 on Blackwell](../sources/prs/vllm/PR-38083.md), [Fix NaN from stale FP4 scale padding in create_fp4_scale_tensor](../sources/prs/vllm/PR-38148.md), [[Model Runner V2] Rebuild attention metadata before eagle decode full…](../sources/prs/vllm/PR-38311.md), [[MoE] Add RoutingMethodType.Simulated to TRT-LLM FP8/NVFP4 kernel allowlists](../sources/prs/vllm/PR-38329.md), [[GDN] Eliminate GPU->CPU sync in prepare_chunk_indices during prefill](../sources/prs/vllm/PR-38361.md), [[QeRL] Fix online quantized reloading](../sources/prs/vllm/PR-38442.md), [[XPU] Fix spec-decode UTs under tests/v1/spec_decode](../sources/prs/vllm/PR-38491.md), [[Bugfix][MLA] Change default SM100 MLA prefill backend back to TRT-LLM](../sources/prs/vllm/PR-38562.md), [[ROCm] Fix aiter persistent mode mla with q/o nhead<16 for kimi-k2.5 tp8](../sources/prs/vllm/PR-38615.md), [Fix MLA runs when use_inductor_graph_partition=True](../sources/prs/vllm/PR-38631.md), [[Bugfix] Fix AWQ models batch invariance issues](../sources/prs/vllm/PR-38670.md), [[XPU] add xpu backend implementation of mxfp8 quant](../sources/prs/vllm/PR-38682.md), [[Bugfix] Restrict TRTLLM attention to SM100, fixing GB300 (SM103) hang](../sources/prs/vllm/PR-38730.md), [[Bugfix] Fix test mocks after SM100 restriction in #38730](../sources/prs/vllm/PR-38791.md), [[LMCache][MP] optimize save when mla enabled](../sources/prs/vllm/PR-38810.md), [[FlashAttention] Symlink FA4 instead of copying when using `VLLM_FLASH_ATTN_SRC_DIR`](../sources/prs/vllm/PR-38814.md), [[Quant] add CompressedTensorsW8A8Mxfp8 for linear and MoE layers](../sources/prs/vllm/PR-38815.md), [[Attention][MLA] Re-enable FA4 as default MLA prefill backend](../sources/prs/vllm/PR-38819.md), [[Bugfix] Fix NVFP4+MTP crash: force unquantized mtp.fc for Qwen3.5](../sources/prs/vllm/PR-38832.md), [[Attention] relax the head dim 512 and paged kv for sm90+FA4](../sources/prs/vllm/PR-38835.md), [[Bugfix] Re-enable Renormalize routing for TRT-LLM MoE experts](../sources/prs/vllm/PR-38859.md), [[Gemma4] Enable Fast Prefill Optimization](../sources/prs/vllm/PR-38879.md), [[MoE Refactor] Split up compressed_tensors_moe.py](../sources/prs/vllm/PR-38960.md), [[Perf][GDN] Align TMA usage with upstream FLA](../sources/prs/vllm/PR-38981.md), [[Bug] Fix routing bias dtype for trtllm per-block fp8 moe](../sources/prs/vllm/PR-38989.md), [[Bugfix][MoE] Fix 6-8% decode regression: prefer multi-stream shared expert overlap](../sources/prs/vllm/PR-38990.md), [[Perf] Change Trtllm fp8 MoE to use Shuffled Weights and BlockMajorK Layout](../sources/prs/vllm/PR-38993.md), [[Quantization] - Layerwise reloading of Attention/KV quantized models](../sources/prs/vllm/PR-38995.md), [[Bugfix] Fix FlashInfer crash with kv_cache_dtype_skip_layers](../sources/prs/vllm/PR-39002.md), [[Gemma4] Support quantized MoE ](../sources/prs/vllm/PR-39045.md), [[Bug] Fix Trtllm Fp8 MoE Weight Shuffle Memory Fragamentation](../sources/prs/vllm/PR-39054.md), [[ROCm] Align AiterFlashAttentionImpl attn_type check with backend](../sources/prs/vllm/PR-39119.md), [[Refactor] Move NVFP4 GEMM management into NvFp4LinearKernel](../sources/prs/vllm/PR-39129.md), [[Refactor] Move MXFP8 GEMM management into MxFp8LinearKernel](../sources/prs/vllm/PR-39205.md), [[Bug] Fix rocm sparse attn indexer issue](../sources/prs/vllm/PR-39225.md), [[Bugfix] FlashInfer MXINT4 MoE crashes, missing do_finalize](../sources/prs/vllm/PR-39315.md), [[Feature] Batch invariant nvfp4 linear support](../sources/prs/vllm/PR-39322.md), [[Model Runner V2] Fix flex attention kv blocks calculation issue](../sources/prs/vllm/PR-39353.md), [[Bugfix][CT] Fix KV cache scale handling](../sources/prs/vllm/PR-39418.md), [[MLA] Optimize mla indexer prepare uniform decode for MTP > 1](../sources/prs/vllm/PR-39458.md), [[Kernel] Support TRTLLM GEN NVFP4 MoE for non-512-aligned hidden dims via weight padding](../sources/prs/vllm/PR-39510.md), [[Bugfix] Fix tensor shape mismatch in sparse attention with speculative decoding](../sources/prs/vllm/PR-39542.md), [[Mooncake] Fix mixed MLA+Eagle block-size validation](../sources/prs/vllm/PR-39596.md), [[XPU] properly handle q_descale on XPU as quant query input not supported](../sources/prs/vllm/PR-39676.md), [[Bugfix] Fix mismatch between global and local attention heads in tensor-parallel mode for param2moe model](../sources/prs/vllm/PR-39707.md), [[Bugfix] Reject non-nvfp4 dtypes when using the flashinfer_nvlink_one_sided all2all backend](../sources/prs/vllm/PR-39717.md), [[Bugfix][NIXL] Fix `_logical_to_kernel_block_ids` conversion for non-mamba models](../sources/prs/vllm/PR-39724.md), [add warning when FP8 KV cache misses prefill query quantization](../sources/prs/vllm/PR-39752.md), [[Bugfix] add support for 'num_attention_groups' in ModelArchConfigConvertorBase for Step3p5](../sources/prs/vllm/PR-39796.md), [[Bug] Fix batch invariance nvfp4 support](../sources/prs/vllm/PR-39820.md), [[Bugfix] Disable FlashInfer CUTLASS MoE on SM121 (DGX Spark)](../sources/prs/vllm/PR-39825.md), [[Core] Replace routing replay with device cache and async D2H pipeline](../sources/prs/vllm/PR-39917.md), [[Attention] use diff kv backend for mimo v2 flash](../sources/prs/vllm/PR-40045.md), [[Bugfix] Temporarily disable B200 fp4 MoE layer tests](../sources/prs/vllm/PR-40057.md), [Add nvfp4 kv cache support](../sources/prs/vllm/PR-40177.md), [Fix MoE backend selection for LoRA (unquantized MoE)](../sources/prs/vllm/PR-40273.md), [[Kernel][Helion] Optimize Helion config parsing latency](../sources/prs/vllm/PR-40850.md), [[DSV4] Add BF16 and MXFP8 A2A support for flashinfer a2a one sided](../sources/prs/vllm/PR-40960.md), [[Kernel][MoE] Support GELU on TRT-LLM NvFP4 fused MoE for Gemma4](../sources/prs/vllm/PR-41050.md), [[Bugfix][Hybrid][NemotronH] Fix mamba_cache_mode=all + speculative decoding crash](../sources/prs/vllm/PR-41233.md), [[ROCm][Quantization][3/N] Refactor quark_moe w4a4 w/ oracle](../sources/prs/vllm/PR-41436.md), [[Quantization] Rework quantization_config to use QuantKey and allow for activation override](../sources/prs/vllm/PR-41566.md), [[MXFP4] Support for linear layers + compressed-tensors integration](../sources/prs/vllm/PR-41664.md), [fix: remove unused norm for dpskv4](../sources/prs/vllm/PR-41710.md), [[Spec Decode] Add Gemma4 MTP speculative decoding support](../sources/prs/vllm/PR-41745.md), [Add NVFP4 all-gather GEMM fusion for AsyncTP](../sources/prs/vllm/PR-41882.md), [[CPU] Add MXFP4 W4A16 MoE support](../sources/prs/vllm/PR-41922.md), [[Bugfix] Add swiglu limits to deepgemm fp8 methods](../sources/prs/vllm/PR-41986.md), [[Bugfix] Fix TRTLLM ragged MLA prefill workspace warmup](../sources/prs/vllm/PR-42112.md), [[LoRA] Support 2D and 3D MoE LoRA adapter at the same time](../sources/prs/vllm/PR-42242.md), [[Bugfix] mamba: run single-token extends as decodes](../sources/prs/vllm/PR-42430.md), [Refactor AWQ Marlin MoE onto modular WNA16 oracle](../sources/prs/vllm/PR-42483.md), [[UX] Add a persistent cache for FlashInfer autotuning](../sources/prs/vllm/PR-42537.md), [[Bugfix] fix swiglu limit issue for humming backend + deepseek v4](../sources/prs/vllm/PR-42541.md), [[CPU] Add fused GDN support for AMX CPU platform](../sources/prs/vllm/PR-42707.md), [Fix Weight loading for Qwen3.5-MTP and Qwen3-VL using runai_streamer](../sources/prs/vllm/PR-42716.md), [[CPU] Specify required KV cache layout for CPU attention backend](../sources/prs/vllm/PR-42740.md), [[ROCm] [Bugfix] Fix DeepSeek V4 Functionality and Accuracy](../sources/prs/vllm/PR-42810.md), [[Perf] Add do_not_specialize in fused FP8 RoPE kernel](../sources/prs/vllm/PR-42849.md), [[Model Refactoring] Migrate DeepSeek V4 to vllm/models/ [1/N] ](../sources/prs/vllm/PR-43004.md), [[XPU] update xpu graph usage](../sources/prs/vllm/PR-43043.md), [[CI failure] Temporarily disable using persistent cache for flashinfer autotune](../sources/prs/vllm/PR-43119.md), [FlashAttention SM100 MLA TopK Sparse Forward](../wiki/kernels/flash-attention-sm100-mla-topk.md), [FlashMLA — Multi-head Latent Attention](../wiki/kernels/flashmla.md), [FP8 Fine-Grained-Scale GEMM](../wiki/kernels/fp8-block-scale-gemm.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [GPU Mode NVFP4 Gated Dual GEMM](../wiki/kernels/gated-dual-gemm.md), [Grouped GEMM Contracts for MoE and NVFP4](../wiki/kernels/grouped-gemm.md), [Native Sparse Attention (NSA)](../wiki/kernels/nsa.md), [NVFP4 GEMM — GPU Mode Problem 2 Contract](../wiki/kernels/nvfp4-gemm.md), [TensorRT-LLM Blackwell FP4 DSA Indexer](../wiki/kernels/tensorrt-llm-blackwell-indexer.md) | +| `tilelang` | | [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [Tilelang sparse decode fwd for dsv32 mi355](../sources/prs/sglang/PR-18488.md), [[AMD] Tilelang sparse fwd for dsv32 mi355/mi300](../sources/prs/sglang/PR-19945.md), [[AMD] Enable FP8 KV cache and FP8 attention kernel for NSA on MI300/MI355 with TileLang backend](../sources/prs/sglang/PR-21511.md), [Amd/deepseek v4 rebase main 0509](../sources/prs/sglang/PR-24933.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[WIP] support more dtypes for tcgen05](../sources/prs/tilelang/PR-1229.md), [[Enhancement] add more dtype and fix mma.ws for fp16 for tcgen05](../sources/prs/tilelang/PR-1327.md), [[Feat] profiler support cudagraph backend](../sources/prs/tilelang/PR-1658.md), [[Feature] Support `cp.reduce.async.bulk.tensor`](../sources/prs/tilelang/PR-1667.md), [Add swizzle layout detection and automatic merging for layout conflicts](../sources/prs/tilelang/PR-1736.md), [[Feature] Support tcgen5mma lowering for `.kind::i8`](../sources/prs/tilelang/PR-1764.md), [fix(intrinsics): add missing _legalize_to_buffer_region in SM70 emitter](../sources/prs/tilelang/PR-1786.md), [[BugFix] Fix Hopper TMA lowering without warp specialization](../sources/prs/tilelang/PR-1840.md), [[CUDA] Support tcgen5mma gemm ts](../sources/prs/tilelang/PR-1866.md), [[Feature] Support cluster launch, query, synchronization and barrier operations](../sources/prs/tilelang/PR-1874.md), [[Feature] 2-SM support for TMA, TMEM and TCGEN5MMA on Blackwell](../sources/prs/tilelang/PR-1882.md), [[Feature] Add T.copy_cluster to support TMA multicast and SM-to-SM cluster copy](../sources/prs/tilelang/PR-1908.md), [[Feature] Add Producer-Consumer Warp Specialization and T.tma_copy() API](../sources/prs/tilelang/PR-1909.md), [[Feature] Block-scaled GEMM support for MXFP8 on Blackwell](../sources/prs/tilelang/PR-1945.md), [[Bugfix] Fix CuTeDSL autotune cache invalid ELF header (#1967)](../sources/prs/tilelang/PR-1972.md), [[Feature] Support TMA store in T.tma_copy()](../sources/prs/tilelang/PR-1981.md), [[Transform] Add InjectTcgen05Fence pass](../sources/prs/tilelang/PR-2003.md), [[Backend] Refactor gemm_sp](../sources/prs/tilelang/PR-2048.md), [[CUDA] Support int4 `T.gemm`](../sources/prs/tilelang/PR-2063.md), [[CUDA] Improve int4 GEMM lowering and packed codegen support](../sources/prs/tilelang/PR-2073.md), [[TMA] Support FP4 TensorMap TMA copies](../sources/prs/tilelang/PR-2107.md), [feat: auto-vectorize bf16/fp16 reduce with packed add2 intrinsics](../sources/prs/tilelang/PR-2112.md), [[CUDA][TMA] Add TMA tile::gather4 / tile::scatter4 support](../sources/prs/tilelang/PR-2129.md), [[codex] Split GEMM implementations by backend](../sources/prs/tilelang/PR-2153.md), [[TIR][IR] Update to use tirx](../sources/prs/tilelang/PR-2216.md), [[Python] Drop Python 3.9 support](../sources/prs/tilelang/PR-2218.md) | +| `triton` | [Triton on Blackwell](../wiki/languages/triton-blackwell.md) | [Gated Delta Networks](../sources/blogs/gated-delta-net.md), [FlashInfer MLSys 2026 Track A: FP8 Block-Scale MoE](../sources/contests/flashinfer-mlsys26/track-a-fused-moe.md), [FlashInfer MLSys 2026 - Track B: DeepSeek V3.2 Sparse Attention](../sources/contests/flashinfer-mlsys26/track-b-sparse-attention.md), [Native Sparse Attention: Hardware-Aligned and Natively Trainable Sparse Attention](../sources/docs/nsa.md), [Tiled Flash Linear Attention (TFLA)](../sources/docs/tfla.md), [Triton v3.3.0 — Blackwell TCGen5/TMEM Boundary](../sources/docs/triton-3.3-blackwell.md), [Triton v3.6.0 — Incremental Blackwell Changes](../sources/docs/triton-3.6-blackwell.md), [[None][fix] impl fused triton kernel for e8m0 resmooth to reduce memory footprint](../sources/prs/TensorRT-LLM/PR-10327.md), [[#11694][feat] AutoDeploy: Improve the piecewise CG memory usage](../sources/prs/TensorRT-LLM/PR-11993.md), [[https://nvbugs/5983390][perf] Kernel fusions in _gather_k_cache_for_chunk of Indexer in DSA](../sources/prs/TensorRT-LLM/PR-12322.md), [[https://nvbugs/5983390][perf] Multiple host perf optimizations for DSA part](../sources/prs/TensorRT-LLM/PR-12581.md), [[None][feat] Add triton paged attention for AutoDeploy](../sources/prs/TensorRT-LLM/PR-12642.md), [[#12784][feat] AutoDeploy: Optimize DeepSeek-R1 model performance](../sources/prs/TensorRT-LLM/PR-12946.md), [[#13580][fix] AutoDeploy: Support Gemma3n/4 E2B variants](../sources/prs/TensorRT-LLM/PR-13630.md), [[None][feat] Keep DSv4 o_a_proj as FP8, and port vLLM's fused_inv_rope_fp8_quant](../sources/prs/TensorRT-LLM/PR-13938.md), [[https://nvbugs/6152892][fix] Fix Triton MOE memory free when no swizzling enabled](../sources/prs/TensorRT-LLM/PR-14069.md), [[None][feat] Add chunked prefill support for Gemma4 (text + vision multimodal)](../sources/prs/TensorRT-LLM/PR-14134.md), [[None][fix] Add SPDX Apache-2.0 headers to auto_deploy test files](../sources/prs/TensorRT-LLM/PR-14193.md), [[None][fix] Update the OSS headers in derived FLA ops and AD modeling code](../sources/prs/TensorRT-LLM/PR-14281.md), [[None][chore] Update Claude Code agents and skills](../sources/prs/TensorRT-LLM/PR-14344.md), [feat: ragged tensor padding kernel for blackwell kernel alignment](../sources/prs/flashinfer/PR-1025.md), [[nvidia] initial support for blackwell kernels](../sources/prs/flashinfer/PR-1039.md), [benchmark: trtllm-gen mha with sink, add benchmark args](../sources/prs/flashinfer/PR-1415.md), [refactor: update fa3 codebase and fix hopper unittest [part 1]](../sources/prs/flashinfer/PR-2111.md), [Selective State Update kernel (mamba)](../sources/prs/flashinfer/PR-2301.md), [MTP for mamba ](../sources/prs/flashinfer/PR-2444.md), [misc: point triton blackwell-ptxas to local cuda ptxas](../sources/prs/flashinfer/PR-2543.md), [Mamba SSU: better automatic kernel selection + algorithm selection optionally exposed to the user.](../sources/prs/flashinfer/PR-2591.md), [int16 Block-Scaled State and Stochastic Rounding for SSU (mamba)](../sources/prs/flashinfer/PR-2645.md), [Add varlen and speculative decoding support to selective state update](../sources/prs/flashinfer/PR-2700.md), [Mamba2 SSD Combined Forward Pass (Blackwell CuTe DSL Kernel)](../sources/prs/flashinfer/PR-2709.md), [fix(sm12x): fix micro-kernel workspace sizing when routed_rows > num_local_experts](../sources/prs/flashinfer/PR-3191.md), [checkpointing_ssu kernel: fused replay + conditional state-write for Mamba2](../sources/prs/flashinfer/PR-3324.md), [SM-constraint-GEMM by triton persistent kernel](../sources/prs/flashinfer/PR-982.md), [Triton `rms_norm` kernels](../sources/prs/flashinfer/PR-983.md), [[inductor] Fix profiler tests with latest Triton](../sources/prs/pytorch/PR-149059.md), [[inductor][triton 3.3] Fix cpp_wrapper w/ TMA in triton 3.3](../sources/prs/pytorch/PR-149993.md), [Fix uint view copy (#151598)](../sources/prs/pytorch/PR-154121.md), [[user triton] AOT inductor support for device-side TMA](../sources/prs/pytorch/PR-157241.md), [[release] Triton pin update to 3.4](../sources/prs/pytorch/PR-157752.md), [[cherry-pick][inductor][triton] Update HAS_WARP_SPEC to check triton.Config params. Update Triton Hash to top of release/3.4.x stack](../sources/prs/pytorch/PR-158646.md), [[Inductor][Intel GPU] Save `threads_per_warp` from tirton compiled kernel for launching kernel correctly in cpp wrapper.](../sources/prs/pytorch/PR-163388.md), [[2.9 cherry pick][triton] update 3.5 pin to bbb06c0334a6772b92d24bde54956e675c8c6604 (#163382)](../sources/prs/pytorch/PR-163583.md), [[AARCH64][CD][CUDA13][Triton][PTXAS] Turn on BUILD_BUNDLE_PTXAS=1 ](../sources/prs/pytorch/PR-164236.md), [[Minor][Inductor] move some combo kernel log from warning to debug](../sources/prs/pytorch/PR-167020.md), [[RELEASE 2.10] Release only changes](../sources/prs/pytorch/PR-170112.md), [[ROCm] Enable shared memory based pruning for Triton configs](../sources/prs/pytorch/PR-170190.md), [[Inductor] Fix constants handling for Triton constexpr (triton#8248)](../sources/prs/pytorch/PR-171129.md), [[RELEASE 2.11] Release only changes](../sources/prs/pytorch/PR-175091.md), [[inductor] avoid multi-stage for mix-order-red by default (#176228)](../sources/prs/pytorch/PR-176495.md), [[release 2.12] Apply Release only changes to 2.12 branch](../sources/prs/pytorch/PR-180470.md), [Add support for bf16 x bf16 cutlass fused MoE](../sources/prs/sglang/PR-10275.md), [support qwen3_next blackwell](../sources/prs/sglang/PR-10403.md), [Fix bias handling in TritonMoeQuantInfo within quantization/mxfp4.py](../sources/prs/sglang/PR-10579.md), [Fix MTP MoE weight loading with NVFP4 target model.](../sources/prs/sglang/PR-10758.md), [Fix DSR1 accuracy for flashinfer_trtllm MoE with FP8 quantization](../sources/prs/sglang/PR-11081.md), [[AMD] Clean up vllm dependencies in moe_runner/triton.py](../sources/prs/sglang/PR-11349.md), [Support shared experts overlap in cutlass moe](../sources/prs/sglang/PR-11611.md), [[Ascend] qwen optimization](../sources/prs/sglang/PR-12078.md), [Enable Flashinfer TRTLLM-GEN-MoE FP8 blockwise kernel for Qwen3-Next on Blackwell](../sources/prs/sglang/PR-12543.md), [[Bugfix] Fix illegal memory access](../sources/prs/sglang/PR-12758.md), [Support internvl on Blackwell (which doesn't support fa3): add `SingletonCache` support to Vision{Sdpa|Triton|Ascend}Attention](../sources/prs/sglang/PR-13151.md), [Fix nan in global scaling factor for large scale nvfp4 EP](../sources/prs/sglang/PR-13162.md), [[ROCM] Optimized deepseek-r1 fp8 model with + triton_gemm_a8w8 + batch_gemm_a8w8 + fused set_mla_kv_buffer kernel](../sources/prs/sglang/PR-13617.md), [[Feat][NVFP4] Enable NVFP4 MoE for Qwen series models (eg. Qwen3-Next) #13761](../sources/prs/sglang/PR-13761.md), [Support fp4 fp8 non gated moe](../sources/prs/sglang/PR-13794.md), [[NVIDIA] Enable TRTLLM BF16 MoE on Blackwell GPUs](../sources/prs/sglang/PR-13798.md), [[BugFix] fix outplace_fused_experts missing is_gated](../sources/prs/sglang/PR-13864.md), [Feat: GLM-4.6 supports shared experts fusion](../sources/prs/sglang/PR-13873.md), [[LoRA][III] Add LoRA support for MoE layers and enable TP](../sources/prs/sglang/PR-14105.md), [Apply new moe wna16 marlin gemm](../sources/prs/sglang/PR-14125.md), [Apply new moe align block size kernel](../sources/prs/sglang/PR-14134.md), [Add Mistral Large 3 support.](../sources/prs/sglang/PR-14213.md), [[Fix] add block size logic for sm120 smem size](../sources/prs/sglang/PR-14311.md), [[FIX] trtllm-moe-fp4-renorm for Qwen series models](../sources/prs/sglang/PR-14350.md), [Apply back moe_sum_reduce for fused_marlin_moe](../sources/prs/sglang/PR-14829.md), [Mistral Large 3 NVFP4 TRTLLM MoE support](../sources/prs/sglang/PR-15049.md), [Optimize FP8 MLA KV cache writes with Triton kernel](../sources/prs/sglang/PR-15522.md), [MoE: Skip SiLU/GELU activation for masked experts](../sources/prs/sglang/PR-15539.md), [Update flashinfer to 0.6.1](../sources/prs/sglang/PR-15551.md), [Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-15712.md), [ Add tuned triton==3.5.1 h200 tp2, tp4 for qwen 3 next](../sources/prs/sglang/PR-15948.md), [[Performance] Force split_k=1 for MXFP4 Triton kernels on Hopper](../sources/prs/sglang/PR-16014.md), [optimize get_topk_ragged by fusing get k and k_scale triton kernel](../sources/prs/sglang/PR-16043.md), [fix layer intermediate size](../sources/prs/sglang/PR-16084.md), [[NemotronH] Add latent MoE support](../sources/prs/sglang/PR-16227.md), [[Rework] Add SwapAB Optimization for triton fused_moe_kernel on SM90.](../sources/prs/sglang/PR-16723.md), [[Fix] `flashinfer_trtllm` `intermediate_size` assertion with Qwen3 + TP=8](../sources/prs/sglang/PR-16824.md), [Support mxint4 flashinfer_trtllm moe gemm](../sources/prs/sglang/PR-16892.md), [[GLM 4.7] Add RTX 6000 Pro aka sm120](../sources/prs/sglang/PR-17235.md), [Add mxfp8 support for online quantization, Triton dense linear, and CUTLASS MoE](../sources/prs/sglang/PR-17449.md), [[AMD] Update aiter to v0.1.10.post2](../sources/prs/sglang/PR-18423.md), [[sglang-miles] True on-policy training support for FSDP2](../sources/prs/sglang/PR-18639.md), [Adjust padding size to improve triton_kernels moe performance](../sources/prs/sglang/PR-19174.md), [Fix/nemotron mtp quantaized](../sources/prs/sglang/PR-19433.md), [[FlashInfer v0.6.4] [RL] Integrate FlashInfer mxfp8 gemm, MoE, and routed MoE](../sources/prs/sglang/PR-19537.md), [[diffusion][llm] macOS support](../sources/prs/sglang/PR-19549.md), [[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+)](../sources/prs/sglang/PR-19652.md), [Support `triton_kernels` for GPT-OSS on SM120](../sources/prs/sglang/PR-19718.md), [Fix SM120 `triton_kernels` MXFP4 `block_k` for GPT-OSS](../sources/prs/sglang/PR-20040.md), [[Benchmark] use flashinfer bench_gpu_time instead of triton do_bench](../sources/prs/sglang/PR-20305.md), [Support Triton MLA FP8 KV cache](../sources/prs/sglang/PR-20479.md), [Add SGLang CUDA crash API logging inspired by FlashInfer](../sources/prs/sglang/PR-20910.md), [[Qwen3.5] Fuse split/reshape/cat ops in GDN projection with Triton kernel](../sources/prs/sglang/PR-21019.md), [[refactor] Clean up duplicate flashinfer trtllm moe code](../sources/prs/sglang/PR-21233.md), [Refactor JIT kernel CI to use run_suite.py registration system](../sources/prs/sglang/PR-21239.md), [[RL] Support mxfp8 DeepSeek V3](../sources/prs/sglang/PR-21280.md), [[misc] clean up kernel API](../sources/prs/sglang/PR-21325.md), [Change default mm-attention backend from triton_attn to fa4](../sources/prs/sglang/PR-21595.md), [[XPU] Enable qwen3.5 on XPU](../sources/prs/sglang/PR-21668.md), [[Fix] Fall back to triton MOE for GPT-OSS on Blackwell with driver >= 595](../sources/prs/sglang/PR-21780.md), [fix pcg torch dynamo recompile in mxfp8 Triton path](../sources/prs/sglang/PR-21888.md), [[nvidia] Gemma4 nvfp4 fix](../sources/prs/sglang/PR-22079.md), [[Lora] Lora quat info re-factor and support deepseekv3 mla lora](../sources/prs/sglang/PR-22323.md), [diffusion: add HunyuanVideo GroupNorm+SiLU fast path](../sources/prs/sglang/PR-22814.md), [[codex] diffusion: enable group norm silu fuse by default](../sources/prs/sglang/PR-23148.md), [Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-23686.md), [Optimize large GroupNorm SiLU apply](../sources/prs/sglang/PR-23938.md), [[diffusion] Fuse LTX2 split rotary embedding](../sources/prs/sglang/PR-24411.md), [Port MXFP4 Marlin MoE support to JIT kernel path](../sources/prs/sglang/PR-24490.md), [Fix performance regression on Deepseek V3 on `moe-runner-backend=triton` on SM90](../sources/prs/sglang/PR-24562.md), [[Codex] Opt Mistral Large performace ](../sources/prs/sglang/PR-24611.md), [[rebase]Deepseek_v4 support w4(mxfp4)a16 on hopper](../sources/prs/sglang/PR-24986.md), [[MUSA][Diffusion] Improve wan model inference speed using torch.compile](../sources/prs/sglang/PR-25256.md), [[Gemma4]: Fix FP8 Triton scale layout](../sources/prs/sglang/PR-25286.md), [[Intel GPU] Enable DeepSeek V4 Inference on XPU](../sources/prs/sglang/PR-25336.md), [Update logging for inplace setting in MoE layer](../sources/prs/sglang/PR-25499.md), [Fix logging for inplace setting in the flashInfer-trtllm backend](../sources/prs/sglang/PR-25522.md), [amd/deepseek_v4 27/N [fix] Reduce Triton autotune configs for faster first-time server launch](../sources/prs/sglang/PR-25554.md), [Add DeepSeekV4 fused MoE Triton autotune support](../sources/prs/sglang/PR-25569.md), [Use triton_attn as default vision attention on B300 (SM103)](../sources/prs/sglang/PR-25570.md), [[diffusion] Fix GLM-Image /v1/images/edits support](../sources/prs/sglang/PR-25697.md), [[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename](../sources/prs/sglang/PR-25821.md), [[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests](../sources/prs/sglang/PR-25831.md), [Feature DeepSeek V3/R1 INT8 Quantization (block-wise)](../sources/prs/sglang/PR-3730.md), [[Feature] DeepSeek V3/R1 INT8 Quantization (channel-wise) ](../sources/prs/sglang/PR-3888.md), [Add fast decode plan for flashinfer mla](../sources/prs/sglang/PR-3987.md), [[Revision] Add fast decode plan for flashinfer mla ](../sources/prs/sglang/PR-4012.md), [Accelerate FP8 CUDA Kernel by 20-28%](../sources/prs/sglang/PR-4215.md), [Feat/support encoder model (like bert)](../sources/prs/sglang/PR-4887.md), [Add DeepSeek V3/R1 shared experts fusion](../sources/prs/sglang/PR-4918.md), [reduce moe_align_block_size_kernel small batch mode overhead](../sources/prs/sglang/PR-5086.md), [Support tuning moe for llama 4 model](../sources/prs/sglang/PR-6042.md), [feat: mtp support dp-attention](../sources/prs/sglang/PR-6081.md), [enable auto-round quantization model](../sources/prs/sglang/PR-6226.md), [fix: enable multi-GPU Triton fused MoE tuning](../sources/prs/sglang/PR-6295.md), [reduce torch.zeros overhead in moe align block size kernel](../sources/prs/sglang/PR-6369.md), [Refine pre_reorder_triton_kernel slightly to improve performance](../sources/prs/sglang/PR-6627.md), [[CPU] [BF16] Call fused_experts_cpu, weight_packed_linear and bmm_cpu kernel in DeepSeek model](../sources/prs/sglang/PR-6641.md), [Set `num_fused_shared_experts` as `num_shared_experts` when shared_experts fusion is not disabled](../sources/prs/sglang/PR-6736.md), [[CPU] add optimizations for INT8 and FP8 DeepSeek](../sources/prs/sglang/PR-6769.md), [[CPU] support the case where num_attention_heads or intermediate_size is not divisible by the TP size](../sources/prs/sglang/PR-6771.md), [[DeepseekR1-FP4] Add Support for nvidia/DeepSeekR1-FP4 model](../sources/prs/sglang/PR-6853.md), [Use deepgemm instead of triton for fused_qkv_a_proj_with_mqa](../sources/prs/sglang/PR-6890.md), [chore: upgrade flashinfer v0.2.6.post1 jit](../sources/prs/sglang/PR-6958.md), [Fuse routed scaling factor in deepseek](../sources/prs/sglang/PR-6970.md), [Update default settings for blackwell](../sources/prs/sglang/PR-7023.md), [Fix positional argument](../sources/prs/sglang/PR-7093.md), [Enable ModelOpt Llama4 fp8 checkpoint deployment in SGLang](../sources/prs/sglang/PR-7129.md), [Support new DeepGEMM](../sources/prs/sglang/PR-7172.md), [Fix grammar abort & Minor style fixes](../sources/prs/sglang/PR-7204.md), [FlashInfer NVFP4 MoE with EP & 2-stream shared expert](../sources/prs/sglang/PR-7327.md), [Fix MTP with Deepseek R1 Fp4](../sources/prs/sglang/PR-7376.md), [Fix torch compile run](../sources/prs/sglang/PR-7391.md), [Add fp4 quantize before all-gather for Flashinfer cutlass MoE DP (max throughput)](../sources/prs/sglang/PR-7667.md), [Integrate triton moe kernel](../sources/prs/sglang/PR-7689.md), [[feat] Support tp mode for DeepSeek-R1-W4AFP8](../sources/prs/sglang/PR-8118.md), [Support triton kernels v3.4.0 for fused_moe](../sources/prs/sglang/PR-8258.md), [[NVIDIA] Add Low Latency NVFP4 decode kernels from Flashinfer](../sources/prs/sglang/PR-8552.md), [fuse allreduce and residual_rmsnorm](../sources/prs/sglang/PR-8731.md), [[Perf] Auto enable best flashinfer mxfp4 kernel in b200](../sources/prs/sglang/PR-8898.md), [[fix] Fix mxfp4 triton MoE tp bug](../sources/prs/sglang/PR-9473.md), [Optimize moe_sum_reduce_kernel](../sources/prs/sglang/PR-9477.md), [Single Batch Overlap for MoE Models](../sources/prs/sglang/PR-9660.md), [[Kernel] add triton fused moe kernel for gptq/awq](../sources/prs/vllm/PR-12185.md), [[AMD][Quantization] Add TritonScaledMMLinearKernel since int8 is broken for AMD](../sources/prs/vllm/PR-12282.md), [[Attention] MLA decode optimizations](../sources/prs/vllm/PR-12528.md), [[Attention] Deepseek v3 MLA support with FP8 compute](../sources/prs/vllm/PR-12601.md), [[Attention] MLA with chunked prefill](../sources/prs/vllm/PR-12639.md), [[Perf] Mem align KV caches for CUDA devices (MLA perf improvement)](../sources/prs/vllm/PR-12676.md), [[core] Perf improvement for DSv3 on AMD GPUs](../sources/prs/vllm/PR-13718.md), [[Attention] MLA support for V1](../sources/prs/vllm/PR-13789.md), [[Attention] Flash MLA for V1](../sources/prs/vllm/PR-13867.md), [dynamic distpatch of fp8 kernels](../sources/prs/vllm/PR-14245.md), [[BugFix] MLA + V1, illegal memory access and accuracy issues](../sources/prs/vllm/PR-14253.md), [[BugFix][TritonMLA] Process weights after model loading for GGUF](../sources/prs/vllm/PR-14555.md), [[BugFix] Fix nightly MLA failure (FA2 + MLA chunked prefill, i.e. V1, producing bad results)](../sources/prs/vllm/PR-15492.md), [[ROCM][KERNEL] Paged attention for V1](../sources/prs/vllm/PR-15720.md), [Modularize fused experts and integrate PPLX kernels](../sources/prs/vllm/PR-15956.md), [[Kernel][Bugfix] Re-fuse triton moe weight application](../sources/prs/vllm/PR-16071.md), [Upstream Llama4 Support to Main](../sources/prs/vllm/PR-16113.md), [[Bug] [ROCm] Fix Llama 4 Enablement Bug on ROCm: V0 ROCmFlashAttentionImpl and Triton Fused MoE bugs](../sources/prs/vllm/PR-16198.md), [[Kernel] Support W8A8 channel-wise weights and per-token activations in triton fused_moe_kernel](../sources/prs/vllm/PR-16366.md), [[Perf]Optimize rotary_emb implementation to use Triton operator for improved inference performance](../sources/prs/vllm/PR-16457.md), [Enable PTPC FP8 for CompressedTensorsW8A8Fp8MoEMethod (triton fused_moe)](../sources/prs/vllm/PR-16537.md), [[torch.compile][ROCm] Fuse quantization onto attention using a torch.compile pass](../sources/prs/vllm/PR-16756.md), [[Kernel] Unified Triton kernel that doesn't distinguish between prefill + decode](../sources/prs/vllm/PR-16828.md), [[Bugfix] Triton FA function takes no keyword arguments](../sources/prs/vllm/PR-16902.md), [[Attention] MLA move o_proj q_proj into cuda-graph region](../sources/prs/vllm/PR-17484.md), [fix amd triton mla path](../sources/prs/vllm/PR-17871.md), [[Bugfix][ROCm] Use `chunked_prefill_paged_decode` as fallback for V1 attention on ROCm](../sources/prs/vllm/PR-18093.md), [[Kernel] Integrate CUTLASS MoE kernel with PPLX](../sources/prs/vllm/PR-18762.md), [[Kernel] Enable fp8 support for pplx and BatchedTritonExperts.](../sources/prs/vllm/PR-18864.md), [[Kernels] Add activation chunking logic to FusedMoEModularKernel](../sources/prs/vllm/PR-19168.md), [[Bugfix] Don't attempt to use triton if no driver is active](../sources/prs/vllm/PR-19561.md), [ [Feature] Integrate SM100 DeepGEMM support](../sources/prs/vllm/PR-20087.md), [[Kernel] Optimize Prefill Attention in Unified Triton Attention Kernel](../sources/prs/vllm/PR-20308.md), [[Misc] DP : Add ExpertTokensMetadata](../sources/prs/vllm/PR-20332.md), [[Perf] Use Triton instead of Torch for DeepGEMM Per Token Group Quant](../sources/prs/vllm/PR-20841.md), [[Kernel] DeepGemm MoE : Integrate triton permute / unpermute kernels ](../sources/prs/vllm/PR-20903.md), [[v1] Add Whisper model support (encoder-decoder)](../sources/prs/vllm/PR-21088.md), [[Attention] Clean up iRoPE in V1](../sources/prs/vllm/PR-21188.md), [[Kernel] Enable Hybrid Model Support in Triton Unified Attention Kernel](../sources/prs/vllm/PR-21197.md), [[Feature][Kernel]FusedMoE LoRA](../sources/prs/vllm/PR-21229.md), [[v1][attention] Support Hybrid Allocator + FlashInfer](../sources/prs/vllm/PR-21412.md), [[Bugfix] Add proper comparison for package versions](../sources/prs/vllm/PR-22314.md), [[BugFix] Fix triton compile error in `kernel_unified_attention_2/3d` caused by attention sinks](../sources/prs/vllm/PR-22368.md), [[gpt-oss] triton kernel mxfp4](../sources/prs/vllm/PR-22421.md), [[NVIDIA] Support Flashinfer TRTLLM FP8-q/kv NVFP4-out Attention Kernel](../sources/prs/vllm/PR-22703.md), [fp8 kv cache support fix for torch.compile](../sources/prs/vllm/PR-22758.md), [[Misc] Add @tdoublep as a maintainer of hybrid model and Triton-attention related code](../sources/prs/vllm/PR-23122.md), [[ROCm][Aiter] Add triton fp8 bmm kernel for mla](../sources/prs/vllm/PR-23264.md), [[Bugfix] Fixing division by zero in triton_attn if query_heads/kv_heads > 16 ](../sources/prs/vllm/PR-23424.md), [[Feature] Add Hopper DeepGEMM E8M0 for DeepSeekV3.1 scale_fmt](../sources/prs/vllm/PR-23666.md), [[Feature] Support Decode Context Parallel (DCP) for MLA](../sources/prs/vllm/PR-23734.md), [[Bug] Fix Shape Validation for Fallback while Enabling E8M0 for DeepGEMM](../sources/prs/vllm/PR-26322.md), [Move query quantization to attention layer for Flashinfer & Triton.](../sources/prs/vllm/PR-26534.md), [[Attention] Use sparse prefill kernel for fp8 kv-cache in DeepSeek-v3.2](../sources/prs/vllm/PR-27532.md), [fix cross attention](../sources/prs/vllm/PR-28346.md), [[Model] Add support for openPangu moe model](../sources/prs/vllm/PR-28775.md), [[Feature] Batch invariant: Enable `TRITON_MLA` without prefix-caching](../sources/prs/vllm/PR-29125.md), [[Bugfix] Only use triton_kernels for MXFP4 on SM90 and SM100](../sources/prs/vllm/PR-29339.md), [[LoRA] Support Quantized Adapters](../sources/prs/vllm/PR-30286.md), [[ROCm][Quantization] GPT OSS Upstream MoE wmxfp4_afp8 with static scales](../sources/prs/vllm/PR-30357.md), [[Perf] Set split_k to 1 for triton_kernels](../sources/prs/vllm/PR-30528.md), [[Bugfix] Fix Triton FusedMoE LoRA](../sources/prs/vllm/PR-30585.md), [Triton Attention: Support cross-layers blocks](../sources/prs/vllm/PR-30687.md), [fused_moe_lora PDL improvements](../sources/prs/vllm/PR-30716.md), [[Bugfix] [Kernel] Triton attention kernels: mask out V blocks that fall outside sliding window](../sources/prs/vllm/PR-30887.md), [[Bugfix] Fix incorrect tiles creation for mm prefix triton attention](../sources/prs/vllm/PR-30974.md), [Use aiter triton fused_add_rmsnorm_pad for gpt-oss](../sources/prs/vllm/PR-30976.md), [[Bugfix][ROCm]Fix Qwen3-Next-80B-A3B-Thinking inference and optimize non-standard block size (544) support under rocm_atten](../sources/prs/vllm/PR-31380.md), [fixed mypy warnings for files vllm/v1/attention with TEMPORARY workaround](../sources/prs/vllm/PR-31465.md), [[FIX] Add NO_MUL activation support for modular kernel path](../sources/prs/vllm/PR-31528.md), [[LoRA]Disable linear LoRA kernel PDL](../sources/prs/vllm/PR-31777.md), [[1/N][Attention] Restructure attention: move files](../sources/prs/vllm/PR-31916.md), [[4/N][Attention] Move MLA common to model_executor](../sources/prs/vllm/PR-32060.md), [Add TMA support to fused_moe_lora kernel](../sources/prs/vllm/PR-32195.md), [[Bugfix][Attention] Explicitly report support for kv_cache_dtype bfloat16](../sources/prs/vllm/PR-32795.md), [Triton MLA perf fixes](../sources/prs/vllm/PR-33529.md), [[Kernel] Add FP8 KV cache support to Triton MLA decode attention](../sources/prs/vllm/PR-34597.md), [fix(mxfp4): return is_monolithic=False when LoRA is enabled for Triton backend](../sources/prs/vllm/PR-35382.md), [[XPU] Support block fp8 moe by fallback to TritonExpert on XPU](../sources/prs/vllm/PR-36458.md), [[Kernel] Fuse FP8 output quantization into merge_attn_states](../sources/prs/vllm/PR-36518.md), [[Bugfix] Warm up Triton autotuner for GDN layers during V1 profiling](../sources/prs/vllm/PR-36599.md), [[Bugfix] Fix KV scales inconsistency in fp8 MLA & FlashInfer kv_cache_dtype "auto" leading to gibberish](../sources/prs/vllm/PR-37054.md), [[MoE Refactor] Mxfp4 oracle rebased](../sources/prs/vllm/PR-37128.md), [[Misc] Add `float16` to `CacheDType`](../sources/prs/vllm/PR-37199.md), [[NIXL][BUG] Fix Triton heterogeneous TP](../sources/prs/vllm/PR-37940.md), [[Perf] triton bilinear_pos_embed kernel for ViT](../sources/prs/vllm/PR-37948.md), [[Perf] FP8 FlashInfer Attn for ViT](../sources/prs/vllm/PR-38065.md), [[Bugfix] Enable batch-invariant Triton matmul on all Ampere GPUs (SM 8x) ](../sources/prs/vllm/PR-38427.md), [[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity](../sources/prs/vllm/PR-38479.md), [[Kernels][MoE] Fix legacy_routing to use bitmatrix-based routing path](../sources/prs/vllm/PR-38504.md), [[Perf] Reduce H2D pageable memory copies](../sources/prs/vllm/PR-38794.md), [[MoE] Move GPT OSS Triton kernel experts into fused_moe/experts/](../sources/prs/vllm/PR-39007.md), [[XPU] Quick fix for TritonMLA to remove cuda hardcode](../sources/prs/vllm/PR-39088.md), [[MoE] Move cutlass moe to fused_moe/experts/](../sources/prs/vllm/PR-40574.md), [[Attention][TurboQuant] Share dequant buffers, eliminate float16_copy](../sources/prs/vllm/PR-40941.md), [[MoE] Move various experts classes to fused_moe/experts/](../sources/prs/vllm/PR-41979.md), [[feat] Add FP8 per-tensor Q scale support to Triton attention backend](../sources/prs/vllm/PR-42080.md), [[Perf] Wire silu_and_mul_per_block_quant into TritonFP8MoE (MiniMax-M2) ](../sources/prs/vllm/PR-42497.md), [[Kernel] Pack topk id/weights triton kernel](../sources/prs/vllm/PR-42527.md), [[Perf][MLA] Enable FULL cudagraph capture for TRITON_MLA decode](../sources/prs/vllm/PR-42885.md), [FlashInfer Track A FP8 Block-Scale MoE](../wiki/kernels/fused-moe.md), [Gated Delta Net — Linear Attention](../wiki/kernels/gated-delta-net.md), [Native Sparse Attention (NSA)](../wiki/kernels/nsa.md) | diff --git a/queries/by-problem.md b/queries/by-problem.md index bbbff2ae1..b4bd75397 100644 --- a/queries/by-problem.md +++ b/queries/by-problem.md @@ -4,10 +4,10 @@ | Symptom | Pattern Page | Candidate Techniques | Sources | |---------|-------------|---------------------|---------| -| low-sm-utilization, tail-effect, load-imbalance | [Low SM Utilization](../wiki/patterns/low-sm-utilization.md) | [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md), [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md), [Cluster Launch Control (CLC)](../wiki/hardware/clc.md) | 3 sources | -| memory-bound, low-compute-utilization, high-memory-throughput | [Memory Bandwidth Bound](../wiki/patterns/memory-bound.md) | [Wide Vectorized Loads and Cache Policies](../wiki/techniques/vectorized-loads.md), [Shared Memory Swizzling](../wiki/techniques/swizzling.md), [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md) | 3 sources | -| load-imbalance, tail-effect, low-sm-utilization | [MoE Expert Load Imbalance](../wiki/patterns/moe-load-imbalance.md) | [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md), [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md), [Kernel Fusion](../wiki/techniques/kernel-fusion.md) | 3 sources | -| compute-bound, low-tensor-core-utilization, pipeline-stalls | [Not Reaching Peak FLOPS](../wiki/patterns/compute-bound.md) | [Two-SM Cooperative MMA](../wiki/hardware/2sm-cooperative.md), [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md), [Epilogue Fusion](../wiki/techniques/epilogue-fusion.md), [Software-Emulated Exponential](../wiki/techniques/software-exp.md) | 3 sources | -| pipeline-stalls, compute-bound, low-tensor-core-utilization | [Pipeline Stalls](../wiki/patterns/pipeline-stalls.md) | [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md), [Double/Multi-Buffering Patterns](../wiki/techniques/double-buffering.md), [Ping-Pong Scheduling](../wiki/techniques/ping-pong-scheduling.md) | 3 sources | -| register-pressure, low-occupancy, register-spilling | [Register Pressure — Low Occupancy](../wiki/patterns/register-pressure.md) | [Tensor Memory (TMEM)](../wiki/hardware/tmem.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md), [Register Accumulators to TMEM](../wiki/migration/register-to-tmem.md) | 3 sources | -| tail-effect, low-sm-utilization, wave-quantization | [Tail Effect — Last Wave Underutilization](../wiki/patterns/tail-effect.md) | [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md), [Cluster Launch Control (CLC)](../wiki/hardware/clc.md), [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md) | 3 sources | +| low-sm-utilization, tail-effect, load-imbalance | [Low SM Utilization](../wiki/patterns/low-sm-utilization.md) | [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md), [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md), [Cluster Launch Control (CLC)](../wiki/hardware/clc.md) | 4 sources | +| memory-bound, low-compute-utilization, high-memory-throughput | [Memory Bandwidth Bound](../wiki/patterns/memory-bound.md) | [Vectorized Loads and Cache Hints](../wiki/techniques/vectorized-loads.md), [PTX Cache Eviction and Prefetch Hints](../wiki/techniques/cache-policy.md), [Shared Memory Swizzling](../wiki/techniques/swizzling.md), [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md) | 4 sources | +| load-imbalance, tail-effect, low-sm-utilization | [MoE Expert Load Imbalance](../wiki/patterns/moe-load-imbalance.md) | [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md), [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md), [Kernel Fusion](../wiki/techniques/kernel-fusion.md) | 5 sources | +| compute-bound, low-tensor-core-utilization, pipeline-stalls | [Not Reaching the Relevant Compute Ceiling](../wiki/patterns/compute-bound.md) | [Two-SM Cooperative MMA](../wiki/hardware/2sm-cooperative.md), [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md), [Epilogue Fusion](../wiki/techniques/epilogue-fusion.md), [Software-Emulated Exponential](../wiki/techniques/software-exp.md) | 4 sources | +| pipeline-stalls, compute-bound, low-tensor-core-utilization | [Pipeline Stalls](../wiki/patterns/pipeline-stalls.md) | [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md), [Double/Multi-Buffering Patterns](../wiki/techniques/double-buffering.md), [Ping-Pong Scheduling](../wiki/techniques/ping-pong-scheduling.md) | 4 sources | +| register-pressure, low-occupancy, register-spilling | [Register Pressure and Residency](../wiki/patterns/register-pressure.md) | [Tensor Memory (TMEM)](../wiki/hardware/tmem.md), [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md), [Register Budgeting for Occupancy](../wiki/techniques/register-budgeting.md), [Register Accumulators to TMEM](../wiki/migration/register-to-tmem.md) | 3 sources | +| tail-effect, low-sm-utilization, wave-quantization | [Tail Effect — Last-Wave Underutilization](../wiki/patterns/tail-effect.md) | [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md), [Cluster Launch Control (CLC)](../wiki/hardware/clc.md), [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md) | 4 sources | diff --git a/queries/by-repo.md b/queries/by-repo.md index 14e8ca649..aead7ba1a 100644 --- a/queries/by-repo.md +++ b/queries/by-repo.md @@ -259,7 +259,7 @@ | [#6819](../sources/prs/cccl/PR-6819.md) | Use integer promotion for `warp_reduce` | 2025-12-01 | | gemm | | [#6811](../sources/prs/cccl/PR-6811.md) | Integrate decoupled lookahead warpspeed scan | 2025-11-28 | | gemm | | [#6597](../sources/prs/cccl/PR-6597.md) | Split fixed-size segmented reduce dispatch header | 2025-11-12 | | gemm | -| [#6152](../sources/prs/cccl/PR-6152.md) | Fix debug section around line 390 of dispatch_topk | 2025-10-08 | | gemm | +| [#6152](../sources/prs/cccl/PR-6152.md) | Fix debug section around line 390 of dispatch_topk | 2025-10-08 | top-k-selection | top-k-selection | | [#6069](../sources/prs/cccl/PR-6069.md) | Add dynamic CUB dispatch for segmented_sort | 2025-09-30 | | gemm | | [#6077](../sources/prs/cccl/PR-6077.md) | [CUB] Use `BlockLoadToShared` in `DeviceMerge` | 2025-09-30 | | gemm | | [#5408](../sources/prs/cccl/PR-5408.md) | Combine `block_reduce_warp_reduction_nondeterministic.cuh` specialization with original deterministic one | 2025-08-01 | | gemm | @@ -267,7 +267,7 @@ | [#4961](../sources/prs/cccl/PR-4961.md) | Add nondeterministic reduce that uses atomics | 2025-06-11 | | gemm | | [#4716](../sources/prs/cccl/PR-4716.md) | Split Optimize Warp Reduce PR - CUB part | 2025-05-15 | | gemm | | [#3691](../sources/prs/cccl/PR-3691.md) | Fix SM100 histogram tunings | 2025-02-05 | | gemm | -| [#3559](../sources/prs/cccl/PR-3559.md) | Add b200 tunings for scan.exclusive.sum | 2025-01-28 | | gemm | +| [#3559](../sources/prs/cccl/PR-3559.md) | Add b200 tunings for scan.exclusive.sum | 2025-01-28 | parallel-scan | parallel-scan | | [#3517](../sources/prs/cccl/PR-3517.md) | Fix the vectorized loading of BlockLoad | 2025-01-24 | | gemm | | [#3236](../sources/prs/cccl/PR-3236.md) | Fix scan / sm90 perf regression | 2025-01-02 | | gemm | | [#2944](../sources/prs/cccl/PR-2944.md) | fix thread-reduce performance regression | 2024-11-22 | | gemm | @@ -529,7 +529,7 @@ | [#2416](../sources/prs/flashinfer/PR-2416.md) | feat: update trtllm-gen MoE cubins | 2026-01-26 | | gemm, moe, tma | | [#2415](../sources/prs/flashinfer/PR-2415.md) | Remove cudaMalloc/Free in GDN prefill kernel | 2026-01-25 | | prefill | | [#2405](../sources/prs/flashinfer/PR-2405.md) | perf: improve gdn decode cute-dsl kernels | 2026-01-23 | | decode | -| [#2387](../sources/prs/flashinfer/PR-2387.md) | A Blackwell-optimized version of selective_state_update (decode) | 2026-01-22 | warp-specialization, pipeline-stages, double-buffering | tcgen05, decode | +| [#2387](../sources/prs/flashinfer/PR-2387.md) | A Blackwell-optimized version of selective_state_update (decode) | 2026-01-22 | warp-specialization, pipeline-stages, double-buffering | decode | | [#2398](../sources/prs/flashinfer/PR-2398.md) | feat: cuteDSL fp4 moe for better DSR1 performance. | 2026-01-22 | kernel-fusion, pipeline-stages | fp4, gemm, grouped-gemm | | [#2404](../sources/prs/flashinfer/PR-2404.md) | perf: mm_fp4 heuristic prioritizes CUTLASS over cuDNN on SM103 | 2026-01-22 | | fp4, gemm | | [#2395](../sources/prs/flashinfer/PR-2395.md) | feat: Add output_both_sf_layouts option to add_rmsnorm_fp4quant API | 2026-01-21 | | fp4 | @@ -2344,7 +2344,7 @@ | [#24722](../sources/prs/vllm/PR-24722.md) | [Kernel][Quantization] add w4a8 support for marlin kernel | 2025-09-12 | kernel-fusion | fp4, fp8, gemm | | [#24727](../sources/prs/vllm/PR-24727.md) | [Model] Support Qwen3-VL Model Series | 2025-09-12 | | moe | | [#24774](../sources/prs/vllm/PR-24774.md) | [Bug] Fix `is_flashmla_supported` Check Error | 2025-09-12 | | attention, mla | -| [#23696](../sources/prs/vllm/PR-23696.md) | [Kernel][tcgen05] nvfp4 fused tcgen05 moe | 2025-09-11 | kernel-fusion, fine-grained-quantization | tcgen05, nvfp4, moe | +| [#23696](../sources/prs/vllm/PR-23696.md) | [Kernel][B200] mxfp4 fused cutlass moe | 2025-09-11 | kernel-fusion, fine-grained-quantization | fp4, fp8, moe | | [#24666](../sources/prs/vllm/PR-24666.md) | [Performance] Move apply_w8a8_block_fp8_linear to an op class | 2025-09-11 | | fp8, gemm, quantization | | [#24673](../sources/prs/vllm/PR-24673.md) | [NVIDIA] Blackwell Family | 2025-09-11 | | fp8, quantization | | [#24521](../sources/prs/vllm/PR-24521.md) | [Feature] Disallow FlashMLA on Blackwell | 2025-09-09 | | attention, mla | @@ -2593,7 +2593,7 @@ | [#17280](../sources/prs/vllm/PR-17280.md) | [NVIDIA] Support Cutlass w8a8 FP8 for Blackwell Geforce GPUs (sm120) | 2025-04-28 | | fp8, quantization | | [#17283](../sources/prs/vllm/PR-17283.md) | [BugFix] Fix cascade attention - RuntimeError: scheduler_metadata must have shape (metadata_size) | 2025-04-28 | | attention | | [#17289](../sources/prs/vllm/PR-17289.md) | [Misc][ROCm] Exclude `cutlass_mla_decode` for ROCm build | 2025-04-28 | | decode, mla | -| [#16032](../sources/prs/vllm/PR-16032.md) | [NVIDIA] Support Cutlass MLA for Blackwell GPUs | 2025-04-27 | warp-specialization, persistent-kernel | tcgen05, mla, moe | +| [#16032](../sources/prs/vllm/PR-16032.md) | [NVIDIA] Support Cutlass MLA for Blackwell GPUs | 2025-04-27 | persistent-kernel | mla, attention | | [#17267](../sources/prs/vllm/PR-17267.md) | [BugFix] Fix vllm_flash_attn install issues | 2025-04-27 | | attention, mla | | [#17222](../sources/prs/vllm/PR-17222.md) | [Bugfix] Get a specific type of layer from forward context | 2025-04-26 | | attention | | [#17180](../sources/prs/vllm/PR-17180.md) | [Bugfix] gemma[2,3] interleaved attention when sliding window is disabled | 2025-04-25 | | attention, gemm | diff --git a/queries/by-technique.md b/queries/by-technique.md index 8f23afae1..0b7a39526 100644 --- a/queries/by-technique.md +++ b/queries/by-technique.md @@ -4,20 +4,20 @@ | Technique | Tags | Architectures | Confidence | Reproducibility | Sources | |-----------|------|--------------|------------|-----------------|---------| -| [CCCL CUB Memory Primitives For Selection And Scan](../wiki/techniques/cccl-memory-primitives.md) | cuda-cpp, top-k-selection, parallel-scan, vectorized-loads | sm100, sm90 | source-reported | snippet | 2 | -| [Chunk-Based Parallelism for Linear Attention](../wiki/techniques/chunk-parallelism.md) | chunk-parallelism, linear-attention, gated-delta-net, pipeline-stages | sm100, sm90 | source-reported | snippet | 3 | -| [Double/Multi-Buffering Patterns](../wiki/techniques/double-buffering.md) | double-buffering, tmem, pipeline-stages | sm100, sm90 | source-reported | snippet | 3 | -| [Epilogue Fusion](../wiki/techniques/epilogue-fusion.md) | epilogue-fusion, tmem, warp-specialization | sm100, sm90 | source-reported | snippet | 3 | -| [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md) | cuda-cpp, cute-dsl, tma, wgmma | sm100, sm90 | source-reported | snippet | 5 | +| [CCCL CUB Memory Primitives For Selection And Scan](../wiki/techniques/cccl-memory-primitives.md) | cuda-cpp, top-k-selection, parallel-scan, vectorized-loads | sm100, sm90 | source-reported | concept | 2 | +| [Chunkwise Parallelism for Linear Recurrences](../wiki/techniques/chunk-parallelism.md) | chunk-parallelism, linear-attention, gated-delta-net, pipeline-stages | sm100, sm90 | verified | concept | 3 | +| [Double/Multi-Buffering Patterns](../wiki/techniques/double-buffering.md) | double-buffering, tmem, pipeline-stages | sm100, sm90 | verified | pseudocode | 3 | +| [Epilogue Fusion](../wiki/techniques/epilogue-fusion.md) | epilogue-fusion, tmem, warp-specialization | sm100, sm90 | verified | pseudocode | 3 | +| [External Source-Map Research For Kernel Edits](../wiki/techniques/external-source-map-research.md) | cuda-cpp, cute-dsl, tma, wgmma | sm90a | source-reported | snippet | 5 | | [Fine-Grained FP8/FP4 Quantization](../wiki/techniques/fine-grained-quantization.md) | fine-grained-quantization, fp8, fp4, nvfp4 | sm100, sm90 | source-reported | snippet | 3 | -| [Kernel Fusion](../wiki/techniques/kernel-fusion.md) | kernel-fusion, fused-kernel, tmem | sm100, sm90 | source-reported | snippet | 3 | -| [PTX Cache Policy Differentiation](../wiki/techniques/cache-policy.md) | cache-policy, vectorized-loads | sm100, sm90 | source-reported | snippet | 4 | -| [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md) | persistent-kernel, clc, tile-scheduling | sm100 | source-reported | snippet | 3 | -| [Ping-Pong Scheduling](../wiki/techniques/ping-pong-scheduling.md) | ping-pong-scheduling, warp-specialization, tmem, pipeline-stages | sm100 | source-reported | snippet | 3 | -| [Register Budgeting for Occupancy](../wiki/techniques/register-budgeting.md) | register-budgeting, register-reuse | sm100, sm90 | source-reported | snippet | 3 | -| [Shared Memory Swizzling](../wiki/techniques/swizzling.md) | swizzling, shared-memory-optimization, tma | sm100, sm90 | source-reported | snippet | 3 | -| [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md) | pipeline-stages, double-buffering, tma, mbarrier | sm100, sm90 | source-reported | snippet | 3 | -| [Software-Emulated Exponential](../wiki/techniques/software-exp.md) | software-exp, attention | sm100 | source-reported | snippet | 3 | -| [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md) | tile-scheduling, clc, persistent-kernel | sm100, sm90 | source-reported | snippet | 3 | -| [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md) | warp-specialization, tcgen05, tmem | sm100, sm90 | source-reported | snippet | 3 | -| [Wide Vectorized Loads and Cache Policies](../wiki/techniques/vectorized-loads.md) | vectorized-loads, cache-policy, register-budgeting | sm100, sm90 | source-reported | snippet | 3 | +| [Kernel Fusion](../wiki/techniques/kernel-fusion.md) | kernel-fusion, fused-kernel, tmem | sm100, sm90 | verified | pseudocode | 2 | +| [PTX Cache Eviction and Prefetch Hints](../wiki/techniques/cache-policy.md) | cache-policy, vectorized-loads | sm100, sm90 | verified | concept | 4 | +| [Persistent Kernels with CLC](../wiki/techniques/persistent-kernels.md) | persistent-kernel, clc, tile-scheduling | sm100 | verified | pseudocode | 3 | +| [Ping-Pong Scheduling](../wiki/techniques/ping-pong-scheduling.md) | ping-pong-scheduling, warp-specialization, tmem, pipeline-stages | sm100 | verified | concept | 2 | +| [Register Budgeting for Occupancy](../wiki/techniques/register-budgeting.md) | register-budgeting, register-reuse | sm100, sm90 | verified | concept | 3 | +| [Shared Memory Swizzling](../wiki/techniques/swizzling.md) | swizzling, shared-memory-optimization, tma | sm100, sm90 | verified | concept | 3 | +| [Software Pipelining and Multi-Stage Buffering](../wiki/techniques/pipeline-stages.md) | pipeline-stages, double-buffering, tma, mbarrier | sm100, sm90 | verified | pseudocode | 3 | +| [Software-Emulated Exponential](../wiki/techniques/software-exp.md) | software-exp, attention | sm100 | verified | concept | 3 | +| [Tile Scheduling Strategies](../wiki/techniques/tile-scheduling.md) | tile-scheduling, clc, persistent-kernel | sm100, sm90 | source-reported | snippet | 2 | +| [Vectorized Loads and Cache Hints](../wiki/techniques/vectorized-loads.md) | vectorized-loads, cache-policy, register-budgeting | sm100, sm90 | verified | concept | 5 | +| [Warp Specialization on Blackwell](../wiki/techniques/warp-specialization.md) | warp-specialization, tcgen05, tmem | sm100, sm90 | source-reported | concept | 4 | diff --git a/references/examples.md b/references/examples.md index aec70c539..daf7dedd1 100644 --- a/references/examples.md +++ b/references/examples.md @@ -1,6 +1,6 @@ --- version_sensitive: - id: vs-triton-3.6-blackwell-tcgen05 + id: vs-triton-3.3-blackwell-tcgen05 --- # Worked Query Examples @@ -109,7 +109,7 @@ python3 scripts/get_page.py contest-gpumode-p1 **Navigation path**: 1. `wiki/kernels/gated-delta-net.md` — conceptual + code -2. `wiki/languages/triton-blackwell.md` — current Triton 3.6+ Blackwell lowering surfaces (tcgen05 + TMEM via descriptor/TMA + warp_specialize, `tl.dot_scaled`, Gluon multi-CTA); pre-3.6 historical context preserved in a clearly-marked subsection +2. `wiki/languages/triton-blackwell.md` — native TCGen5/TMEM backend support from v3.3, later v3.5/v3.6 surface expansions, and the evidence limits on plain `tl.dot` instruction selection 3. Source PRs: `pr-vllm-*` for gated_delta, FlashInfer GDN kernels **Command**: diff --git a/references/primer.md b/references/primer.md index f1662a271..3258bc691 100644 --- a/references/primer.md +++ b/references/primer.md @@ -1,6 +1,6 @@ --- version_sensitive: - id: vs-triton-3.6-blackwell-tcgen05 + id: vs-triton-3.3-blackwell-tcgen05 --- # Topic Map / Primer @@ -88,7 +88,7 @@ All page IDs below resolve via `get_page.py `. All paths are relative to the | CuTe DSL | `lang-cute-dsl` | Preferred high-level path on SM100; native tcgen05/TMEM/CLC bindings. | | CUDA C++ | `lang-cuda-cpp` | PTX inline is common; used by CUTLASS, vLLM, SGLang custom kernels. | | PTX (SM100) | `lang-ptx` | `tcgen05.*`, `clusterlaunchcontrol.*`, `cp.async.bulk.tensor.*` — low-level control. | -| Triton | `lang-triton` | On Blackwell: Triton 3.6+ ships native tcgen05 + TMEM lowering through descriptor/TMA + `tl.range(warp_specialize=True)`, `tl.dot_scaled`, and Gluon multi-CTA / 2CTA. Pre-3.6 the framing was "no tcgen05/TMEM exposure"; that historical context is preserved on the page. Cite via `version_sensitive: vs-triton-3.6-blackwell-tcgen05`. | +| Triton | `lang-triton` | Native Blackwell TCGen5/TMEM compiler support enters between Triton v3.2.0 and v3.3.0. Later releases expand user-visible paths; exact instruction selection remains configuration-dependent. Cite via `version_sensitive: vs-triton-3.3-blackwell-tcgen05`. | --- diff --git a/scripts/validate.py b/scripts/validate.py index 4e84123d6..37f5fd7af 100644 --- a/scripts/validate.py +++ b/scripts/validate.py @@ -376,7 +376,9 @@ def validate_file(filepath, schemas, valid_tags, all_source_ids, code_langs): if all_source_ids and src_id not in all_source_ids: errors.append(f"{rel}: references unknown source id '{src_id}'") - # AC-9: Enforce evidence_basis for verified wiki pages + # AC-9: Enforce a direct, page-scoped evidence basis for verified wiki + # pages. The verification contract accepts any adequate primary oracle; + # it does not require every claim to have both documentation and code. if page_type.startswith("wiki-") and fm.get("confidence") == "verified": eb = fm.get("evidence_basis") if not eb or not isinstance(eb, list) or len(eb) == 0: @@ -384,17 +386,6 @@ def validate_file(filepath, schemas, valid_tags, all_source_ids, code_langs): f"{rel}: confidence 'verified' requires non-empty 'evidence_basis' field" ) else: - eb_types = {entry.get("evidence_type") for entry in eb if isinstance(entry, dict)} - if "official-doc" not in eb_types: - errors.append( - f"{rel}: evidence_basis for 'verified' must include at least one " - f"'official-doc' entry (found: {eb_types})" - ) - if "upstream-code" not in eb_types: - errors.append( - f"{rel}: evidence_basis for 'verified' must include at least one " - f"'upstream-code' entry (found: {eb_types})" - ) # Cross-check evidence_basis source_ids against page sources page_sources = set(fm.get("sources", [])) for entry in eb: @@ -406,8 +397,13 @@ def validate_file(filepath, schemas, valid_tags, all_source_ids, code_langs): f"not listed in page sources" ) - # Check technique/kernel/language pages have fenced code - if page_type in ("wiki-technique", "wiki-kernel", "wiki-language"): + # A page claiming snippet-or-better reproducibility must contain real code. + # Concept and pseudocode pages may instead provide an evidence-backed + # procedure without inventing a compilable implementation. + if ( + page_type in ("wiki-technique", "wiki-kernel", "wiki-language") + and repro_at_least(fm.get("reproducibility"), "snippet") + ): body = read_body(filepath) if not has_compilable_code(body, code_langs): errors.append(f"{rel}: {page_type} page must contain fenced code block (reproducibility >= snippet)") diff --git a/scripts/verify_core_prs.py b/scripts/verify_core_prs.py index 8a522b446..13037fe2d 100755 --- a/scripts/verify_core_prs.py +++ b/scripts/verify_core_prs.py @@ -3,7 +3,7 @@ Modes: default — regenerate in memory and diff against committed bytes - --strict — additionally resolve each captured PR's merge_sha via `gh api` + --strict — additionally resolve each captured PR's merge_sha from GitHub and flag reverted / unresolvable / prefix-mismatched entries Exit codes: @@ -22,6 +22,7 @@ """ import argparse +from concurrent.futures import ThreadPoolExecutor import hashlib import json import subprocess @@ -38,7 +39,11 @@ # which gh failures are environmental (exit 2) versus content-level (exit 1). sys.path.insert(0, str(REPO_ROOT / "scripts")) import compute_core_prs # noqa: E402 -from verify_verbatim import EnvError, _looks_like_env_error # noqa: E402 +from verify_verbatim import ( # noqa: E402 + EnvError, + _looks_like_env_error, + fetch_pull_metadata, +) def run_gh(args): @@ -169,7 +174,7 @@ def main(): f"total_captured are consistent (checksum {fresh.get('checksum_sha256','')[:12]}..., " f"{fresh.get('total_captured',0)} PRs)") - # --strict: resolve merge_sha via gh api + # --strict: resolve merge_sha from GitHub's first-party PR record. if args.strict: issues = 0 # content-level findings (exit 1) env_failures = 0 # environment / connectivity (exit 2) @@ -192,58 +197,54 @@ def main(): if fm.get("id"): sources_prs[fm["id"]] = fm - print(f"Resolving merge_sha for {len(pr_entries)} PRs via gh api...") - for e in pr_entries: + def resolve_entry(e): pid = e.get("id") fm = sources_prs.get(pid) if not fm: - print(f" WARN: {pid}: page not found in sources/prs/") - issues += 1 - continue + return "issue", f" WARN: {pid}: page not found in sources/prs/" sha = fm.get("merge_sha") repo = fm.get("repo") pr_num = fm.get("pr") if not (sha and repo and pr_num): - print(f" WARN: {pid}: missing merge_sha / repo / pr number") - issues += 1 - continue + return "issue", f" WARN: {pid}: missing merge_sha / repo / pr number" try: - out = run_gh(["api", f"/repos/{repo}/pulls/{pr_num}"]) - data = json.loads(out) + data = fetch_pull_metadata(repo, str(pr_num)) if not data.get("merged"): - print(f" FAIL: {pid}: upstream state is not merged (state={data.get('state')})") - issues += 1 - else: - # sources/prs/**/*.md stores abbreviated 8-char - # merge_sha values; gh returns the full 40-char - # merge_commit_sha. R30: match ONLY against - # merge_commit_sha (the actual merged revision). - # Previously this check also accepted a prefix - # match against head.sha, which let stale merge_sha - # values pass strict verification whenever the PR - # branch was kept alive after merge or a squash/ - # rebase merge moved the merge commit away from - # head — the recorded `merge_sha` no longer named - # the commit the bundle was fetched from. - upstream_merge = str(data.get("merge_commit_sha") or "") - if not (upstream_merge and upstream_merge.startswith(sha)): - upstream_head = str((data.get("head") or {}).get("sha") or "") - print( - f" FAIL: {pid}: recorded merge_sha={sha[:12]}... does not prefix-match " - f"upstream merge_commit_sha={upstream_merge[:12]}... " - f"(head.sha={upstream_head[:12]}... shown for reference; not accepted)" - ) - issues += 1 + return "issue", f" FAIL: {pid}: upstream state is not merged (state={data.get('state')})" + + # sources/prs/**/*.md stores abbreviated 8-char merge_sha + # values; GitHub returns the full 40-char merge_commit_sha. + # Match ONLY against merge_commit_sha (the actual merged + # revision), never against head.sha. + upstream_merge = str(data.get("merge_commit_sha") or "") + if not (upstream_merge and upstream_merge.startswith(sha)): + upstream_head = str((data.get("head") or {}).get("sha") or "") + return "issue", ( + f" FAIL: {pid}: recorded merge_sha={sha[:12]}... does not prefix-match " + f"upstream merge_commit_sha={upstream_merge[:12]}... " + f"(head.sha={upstream_head[:12]}... shown for reference; not accepted)" + ) + return "ok", "" except EnvError as ex: # Offline / unauthenticated / rate-limited / DNS unreachable. # These are environment failures, not content drift, so they # must surface via the exit-2 contract instead of being # conflated with real merge-SHA mismatches (exit 1). - print(f" ENV: {pid}: gh unreachable: {ex}", file=sys.stderr) - env_failures += 1 + return "env", f" ENV: {pid}: GitHub unreachable: {ex}" except RuntimeError as ex: - print(f" WARN: {pid}: gh fetch failed: {ex}") + return "issue", f" WARN: {pid}: GitHub fetch failed: {ex}" + + print(f"Resolving merge_sha for {len(pr_entries)} PRs from GitHub...") + workers = min(8, max(1, len(pr_entries))) + with ThreadPoolExecutor(max_workers=workers) as executor: + results = list(executor.map(resolve_entry, pr_entries)) + for kind, message in results: + if kind == "issue": + print(message) issues += 1 + elif kind == "env": + print(message, file=sys.stderr) + env_failures += 1 # Environment failures take precedence over content issues: if we # could not reach GitHub at all, the content check is inconclusive, @@ -253,8 +254,8 @@ def main(): if env_failures: print( f"\nSTRICT inconclusive: {env_failures} environment/connectivity " - f"failure(s) while resolving merge_sha via gh api. " - f"Re-run with network + authenticated gh to complete verification.", + f"failure(s) while resolving merge_sha from GitHub. " + f"Re-run with network access to complete verification.", file=sys.stderr, ) sys.exit(2) diff --git a/scripts/verify_verbatim.py b/scripts/verify_verbatim.py index 3ece11083..de6df5ff5 100755 --- a/scripts/verify_verbatim.py +++ b/scripts/verify_verbatim.py @@ -25,6 +25,10 @@ import yaml import base64 import json +from functools import lru_cache +from urllib.error import HTTPError, URLError +from urllib.parse import quote +from urllib.request import Request, urlopen REPO_ROOT = Path(__file__).resolve().parent.parent ARTIFACTS_DIR = REPO_ROOT / "artifacts" @@ -80,6 +84,7 @@ class EnvError(RuntimeError): "proxyconnect", # Auth / account state (missing auth => env, not content) "authentication required", + "to authenticate", "you must authenticate", "you are not logged in", "not logged into", @@ -119,17 +124,104 @@ def run_gh(args): raise RuntimeError(f"gh {' '.join(args)} failed: {stderr_text.strip()[:200]}") +def _fetch_public_url(url, *, accept="application/octet-stream"): + """Fetch a public GitHub URL without credentials. + + GitHub CLI intentionally refuses even public API requests when it has no + authenticated host. The strict verifiers still need to work in clean CI + and audit containers, so use GitHub's public raw/diff/timeline endpoints as + a transport fallback. The same pinned revisions and byte comparisons are + enforced; this changes only how upstream bytes are obtained. + """ + request = Request( + url, + headers={ + "Accept": accept, + "User-Agent": "KernelWiki-upstream-verifier/1.0", + "X-Requested-With": "XMLHttpRequest", + }, + ) + try: + with urlopen(request, timeout=90) as response: + return response.read() + except HTTPError as exc: + detail = exc.read(300).decode(errors="replace").strip() + if exc.code in (403, 429) or _looks_like_env_error(detail): + raise EnvError(f"public GitHub fetch environment failure for {url}: HTTP {exc.code} {detail[:160]}") + raise RuntimeError(f"public GitHub fetch failed for {url}: HTTP {exc.code} {detail[:160]}") + except (URLError, TimeoutError, OSError) as exc: + raise EnvError(f"public GitHub fetch environment failure for {url}: {exc}") + + +@lru_cache(maxsize=None) +def fetch_pull_metadata(upstream_repo, pr_number): + """Return the merged state and exact merge commit for a public PR. + + Prefer authenticated ``gh api``. Without credentials, GitHub's public PR + timeline is an upstream first-party record and includes the exact 40-byte + merge-commit link. Unlike a head-ref fallback, this preserves the strict + requirement that the recorded SHA name the actual merged revision. + """ + try: + return json.loads(run_gh(["api", f"/repos/{upstream_repo}/pulls/{pr_number}"])) + except EnvError as gh_error: + escaped_repo = quote(str(upstream_repo), safe="/") + url = ( + f"https://github.com/{escaped_repo}/pull/{pr_number}/partials/" + "conversation_content?graceful_retry=1&timeline_per_page=1000" + ) + try: + timeline = _fetch_public_url(url, accept="text/html").decode(errors="replace") + except (EnvError, RuntimeError) as public_error: + raise EnvError(f"{gh_error}; public timeline fallback also failed: {public_error}") + + repo_pattern = re.escape(str(upstream_repo)) + match = re.search( + rf"merged\s+commit\s*1000us) -- Problem: no coalescing, no vectorization - -Attempt 2: Coalesced memory access -- Threads in warp read contiguous bytes -- Result: ~500us -- Problem: still using generic FP4 decode - -Attempt 3: Vectorized loads (uint4) -- 128-bit loads for better bandwidth utilization -- Result: ~200us -- Problem: FP4 decode still manual bitwise ops -``` - -### Attempts 4-6: FP4 Decode Optimization - -``` -Attempt 4: Hardware FP4 intrinsics -- __cvt_fp4x2_to_halfx2 for type conversion -- Result: ~80us -- Big improvement from hardware-accelerated decode +## Attempts 8–12 -Attempt 5: PTX byte unpacking -- mov.b32 {a,b,c,d} instead of shift/mask -- Result: ~50us -- Eliminates bitwise extraction overhead +The next five attempts did not form a monotonic optimization progression: -Attempt 6: Combined PTX for load + decode -- Inline PTX for entire load-decode pipeline -- Result: ~40us -``` +- Attempt 8 used split-K plus FP32 atomics and was worse because of contention, extra traffic, and scheduling overhead. +- Attempt 9 replaced two `uchar4` loads with one `uint2` load and was 16–25% slower because byte extraction added instructions. +- Attempt 10 used four accumulator chains and regressed by 32–55% with more register pressure and worse coalescing. +- Attempt 11 found no effect from reducing `-maxrregcount` from 80 to 64 and no effect from the tested block-size change; unroll 8 was worse than unroll 4. +- Attempt 12's explicit software pipeline increased register pressure and was slower. -### Attempts 7-9: Memory System Optimization +The author's main retrospective lesson is to run Nsight Compute early and verify the bottleneck before choosing transformations. -``` -Attempt 7: Cache policy differentiation -- L1::no_allocate for matrix A (streamed) -- L1::evict_last for vector B (reused) -- Result: ~35us -- B vector stays hot in L1 across rows +## Post-event Observations -Attempt 8: Wider loads (v4.u64 = 256-bit) -- Maximum vector width for global loads -- Result: ~30us -- Better memory transaction efficiency +The author says three inspected solutions around an 18.5 microsecond aggregate used raw PTX load/decode paths, A `L1::no_allocate`, B `L1::evict_last`, `v2.u64` or `v4.u64` loads with `mov.b32` byte decomposition, exact-K specializations, and tighter register budgets. The post reports 32 registers for one inspected solution and 45 for another, and says a further solution shared B reads across multiple M rows. -Attempt 9: Register budgeting (-maxrregcount) -- Tested 32, 40, 48, 56 max registers -- Result: ~28us with -maxrregcount=40 -- More warps per SM -> better latency hiding -``` +These are author-reported observations. They do not supply controlled ablations, public contestant code, or proof that lower register caps and wider loads monotonically improve performance. The author's own attempts provide counterexamples to both generalizations. -### Attempts 10-12: Fine-Tuning +## Primary Sources -``` -Attempt 10: Block size tuning -- Tested BLOCK_M = 1, 2, 4, 8 -- Result: ~27.5us with BLOCK_M=4 -- B vector amortized across more rows - -Attempt 11: K-dimension unrolling -- #pragma unroll for inner K loop -- Result: ~27us -- Marginal improvement from reduced loop overhead - -Attempt 12: Per-K specialization -- Separate kernels for different K values -- Result: ~26.7us (final) -- Each K variant fully unrolled -``` - -## Key Debugging Methodology - -### Nsight Compute Analysis - -The blog emphasizes using Nsight Compute to confirm the kernel is memory-bound: - -``` -// Nsight Compute key metrics to check: -// 1. Memory throughput: how close to 8 TB/s? -// 2. Compute throughput: should be low for memory-bound -// 3. Achieved occupancy: higher is better for memory-bound -// 4. L1 hit rate: should be high for B vector (evict_last) -// 5. L2 hit rate: confirms data reuse patterns - -// Key insight from Amandeep: -// "Run Nsight Compute to confirm memory-bound behavior" -// Many optimizations are counterproductive if you misidentify -// the bottleneck (e.g., compute optimizations on memory-bound kernel) -``` - -### Performance Model - -``` -// Speed-of-light calculation: -// Total data to read: -// A: M * K * 0.5 bytes (FP4) -// B: 1 * K * 0.5 bytes (FP4) -// sfa: M * (K/16) bytes (FP8) -// sfb: 1 * (K/16) bytes (FP8) -// Total ≈ M * K * 0.5625 bytes -// -// For M=7168, K=16384, L=1: -// Total = 7168 * 16384 * 0.5625 = 66 MB -// At 8 TB/s: 66 MB / 8 TB/s = 8.25us -// -// Actual: 26.7us = 3.2x off SOL -// The gap comes from: FP4 decode overhead, scale factor application, -// partial sum reduction, and less-than-perfect vectorization -``` - -## Failed Approaches (Instructive) - -1. **Shared memory for A matrix**: No benefit because A is streamed (each element read once). Shared memory only helps when data is reused. - -2. **Tensor cores for GEMV**: tcgen05.mma requires MxNxK tiles with M >= 128. GEMV has M=1 (or small M for batched), so tensor cores cannot be efficiently utilized. This is fundamentally a CUDA-core memory-bandwidth problem. - -3. **Warp shuffle reduction**: Expected to help for the K-dimension reduction, but the overhead of shuffle instructions exceeded the benefit over simple register accumulation at these K sizes. - -## Key Lessons - -1. **Profile first, optimize second**: Nsight Compute should be the first tool, not the last. Knowing whether a kernel is memory-bound or compute-bound determines the entire optimization strategy. - -2. **FP4 decode is the hidden bottleneck**: The sub-byte format introduces decode overhead that doesn't exist for standard FP16/FP32 kernels. Hardware intrinsics and PTX byte unpacking are essential. - -3. **Tensor cores don't help for GEMV**: GEMV is fundamentally memory-bandwidth-limited and the arithmetic intensity is too low for tensor cores. CUDA cores + wide vectorized loads are the right approach. - -4. **3x off SOL is realistic for FP4 GEMV**: The FP4 decode overhead, scale factor application, and reduction operations add unavoidable computation that a pure bandwidth model doesn't account for. - -5. **Systematic exploration beats intuition**: Documenting 12 attempts with measurements at each step is more productive than guessing at the optimal configuration. - -## Sources - -- [Twelve Attempts at NVFP4 Batched GEMV](https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/) -- [gpu-mode/reference-kernels](https://github.com/gpu-mode/reference-kernels) +- [Amandeep Singh, “Twelve Attempts at an FP4 Kernel”](https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/) +- [Public attempt repository](https://github.com/amandeepsp/cuda/tree/44513ac7d5bbd1cf8109cab952844adac5b6c551/nvfp4/gemv) diff --git a/sources/blogs/colfax-article-source-kernels.md b/sources/blogs/colfax-article-source-kernels.md index d2c198cf4..adc37012a 100644 --- a/sources/blogs/colfax-article-source-kernels.md +++ b/sources/blogs/colfax-article-source-kernels.md @@ -5,8 +5,7 @@ author: Colfax Research url: https://github.com/ColfaxResearch/cfx-article-src source_category: community-note architectures: -- sm90 -- sm100 +- sm90a tags: - cuda-cpp - cute-dsl @@ -20,7 +19,8 @@ retrieved_at: '2026-05-20' description: Source-map entry imported from KernelPilot for TMA, pipelined GEMM, Stream-K, and CuTe transpose examples. --- -This repository collects source files for Colfax Research articles. The useful -KernelWiki path is code-first: inspect the TMA, pipeline GEMM, Stream-K, -transpose-cute, and CUTLASS GEMM folders when a profile points to pipeline -bubbles, tail effects, or memory-layout pressure. +At commit `fbecfed88de2e4246f104a023188ba722937c5fc`, the relevant Hopper +examples compile for SM90a. Inspect `tma/tma_copy.h`, `pipeline-gemm/`, +`streamk/tile_scheduler.hpp`, and `transpose-cute/` for exact TMA, pipelined +GEMM, persistent/Stream-K scheduler, and transpose implementations. This pinned +tree contains no demonstrated SM100 target. diff --git a/sources/blogs/colfax-cutlass-blackwell.md b/sources/blogs/colfax-cutlass-blackwell.md index a65fb7284..eb0fb6ae1 100644 --- a/sources/blogs/colfax-cutlass-blackwell.md +++ b/sources/blogs/colfax-cutlass-blackwell.md @@ -28,51 +28,21 @@ Detailed tutorial on CUTLASS abstraction for Blackwell UMMA (tcgen05.mma) with s - Architectural progression: Volta → Hopper TMA → Blackwell TMEM+UMMA - Sub-byte GEMM tutorial covering NVFP4, MXFP4, block scaling -## Key Code - -### TMEM allocation + tcgen05.mma (single-thread launch) - -```cuda -// UMMA on Blackwell: one thread drives the MMA for the whole CTA. -// Accumulator lives in TMEM, not registers. -__shared__ uint32_t tmem_addr; - -if (threadIdx.x == 0) { - // Allocate 128 rows × 256 cols of TMEM for the accumulator - asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], 256;\n" - :: "r"(&tmem_addr)); -} -__syncthreads(); - -// Issue UMMA: A and B live in SMEM, C accumulates into TMEM -if (threadIdx.x == 0) { - asm volatile( - "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, 1;\n" - :: "r"(tmem_addr), "l"(desc_a), "l"(desc_b), "r"(0)); -} -``` - -### TMEM load into registers for epilogue - -```cuda -// Epilogue warps drain TMEM → registers using tcgen05.ld -// Each warp loads 32 columns (=128 bytes) at a time. -float reg[4]; -asm volatile( - "tcgen05.ld.sync.aligned.32x32b.x4.b32 " - "{%0, %1, %2, %3}, [%4];\n" - : "=f"(reg[0]), "=f"(reg[1]), "=f"(reg[2]), "=f"(reg[3]) - : "r"(tmem_addr + warp_col_offset)); -``` - -### CUTLASS MMA_Atom wrapping - -```cpp -// The CUTLASS two-level abstraction: MMA_Atom wraps the PTX intrinsic, -// MMA_Traits maps logical MxNxK shapes to TMEM addressing. -using Atom = cute::MMA_Atom>; -``` +## Verified implementation notes + +The article is useful for understanding CUTLASS's `MMA_Atom`/`MMA_Traits` +layering and TMEM-backed accumulators, but abbreviated inline PTX is not a safe +substitute for the ISA grammar: + +- `tcgen05.alloc` and `tcgen05.dealloc` are warp-collective for + `cta_group::1`; they are not lane-0-only instructions. +- `tcgen05.mma` is issued by one thread, but its full operand list includes a + disable-output-lane vector whose width depends on the CTA group. +- `tcgen05.ld` is warp-collective and asynchronous; use its documented shape, + repetition, register mapping, and completion mechanism. +- CUTLASS supplies exact wrapper types and layouts for supported combinations; + choose the atom from the version-pinned library rather than reconstructing a + template signature from prose. + +For executable references, use the [PTX ISA 9.0 tcgen05 sections](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma) +and the [CUTLASS 4.5.0 SM100 examples](https://github.com/NVIDIA/cutlass/tree/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/70_blackwell_gemm). diff --git a/sources/blogs/colfax-cutlass-kernels.md b/sources/blogs/colfax-cutlass-kernels.md index 085ca6e89..9fb6514ce 100644 --- a/sources/blogs/colfax-cutlass-kernels.md +++ b/sources/blogs/colfax-cutlass-kernels.md @@ -5,21 +5,21 @@ author: Colfax Research url: https://github.com/ColfaxResearch/cutlass-kernels source_category: community-note architectures: -- sm90 -- sm100 +- sm90a tags: - cuda-cpp +- cute-dsl - gemm - tma - wgmma -- persistent-kernel -- tile-scheduling - pipeline-stages +- warp-specialization retrieved_at: '2026-05-20' description: Source-map entry imported from KernelPilot for CUTLASS GEMM kernel examples and scheduling patterns. --- -Colfax CUTLASS kernel examples are a complementary source-map route for -production-shaped GEMM patterns. Use them alongside CUTLASS PR pages when a -candidate needs concrete tile scheduling, persistent scheduling, or TMA pipeline -code. +At commit `84f0802e2b4a1bf068ac70359f20ffdb368c8f6a`, this repository contains +Hopper SM90a CUTLASS/CuTe GEMM and FMHA examples. The FMHA READMEs and compile +scripts pin CUDA 12.2/12.3, CUTLASS 3.3/3.4, and SM90a; `src/fmha-pipeline/` +implements TMA pipelining with optional warp specialization. The pinned tree is +not evidence for SM100, a persistent scheduler, or a tile scheduler. diff --git a/sources/blogs/deepgemm.md b/sources/blogs/deepgemm.md index b8f031166..f8d15d2df 100644 --- a/sources/blogs/deepgemm.md +++ b/sources/blogs/deepgemm.md @@ -1,8 +1,8 @@ --- id: blog-deepgemm -title: DeepGEMM — FP8 GEMM Library +title: DeepGEMM — Pinned Upstream Project Summary author: DeepSeek AI -url: https://github.com/deepseek-ai/DeepGEMM +url: https://github.com/deepseek-ai/DeepGEMM/tree/891d57b4db1071624b5c8fa0d1e51cb317fa709f source_category: benchmark-blog architectures: - sm100 @@ -15,84 +15,29 @@ tags: - jit-compilation - tcgen05 - wgmma -retrieved_at: 2026-04-16 -artifact_dir: artifacts/blogs/deepgemm/code +retrieved_at: 2026-04-27 +artifact_dir: artifacts/kernels/deepgemm/full --- -## Summary +## Scope -DeepSeek's high-performance FP8 GEMM library with fine-grained scaling, supporting both Hopper and Blackwell. +This source entry summarizes DeepGEMM at commit [`891d57b4db1071624b5c8fa0d1e51cb317fa709f`](https://github.com/deepseek-ai/DeepGEMM/tree/891d57b4db1071624b5c8fa0d1e51cb317fa709f). The local SM90 and SM100 FP8 1D1D files are byte-verified copies from that commit; see their [`PROVENANCE.yaml`](../../artifacts/kernels/deepgemm/full/PROVENANCE.yaml). -## Key Techniques -- Fine-grained quantization: tile-wise 1×128 activations, block-wise 128×128 weights -- SM90: WGMMA with Nc=128 CUDA core promotion (FP22→FP32) -- SM100: tcgen05.mma with TMEM, packed UE8M0 scale format, all memory layouts -- MoE grouped GEMMs: M-axis grouping, contiguous/masked/K-grouped layouts -- JIT compilation via NVRTC -- ~300 lines core kernel code -- Up to 1550 TFLOPS on H800 +## Verified Techniques -## Key Code +- SM90 uses FP32 scale factors. Its pinned 1D1D kernel fixes `BLOCK_K == 128`, accumulates WGMMA partial results in `float accum[...]`, and applies A/B scales into a separate `float final_accum[...]` after each K block. +- SM100 uses packed UE8M0 scale factors. Its pinned 1D1D kernel copies factor blocks into TMEM, constructs a block-scaled UMMA descriptor, and accumulates through the selected TMEM operation without the SM90 CUDA-core `final_accum` loop. +- M-grouped contiguous and masked APIs vary M with N/K fixed. `masked_m` contains an integer valid-M length for each group. K-grouped APIs instead vary K while M/N remain fixed. +- Kernels are generated and JIT compiled. NVCC is the default compiler; `DG_JIT_USE_NVRTC=1` opts into NVRTC. Generated code and compiler settings participate in the cache signature. +- The pinned README exposes NT only for SM90 FP8 and NT/TN/NN/TT dense interfaces for SM100. -### Nc=128 CUDA-core promotion (Hopper SM90) +## Performance Scope -```cpp -// On Hopper, the TC accumulator is only ~FP22-precise. DeepGEMM promotes -// the partial sum to an FP32 CUDA-core accumulator every Nc=128 columns -// (4 consecutive WGMMAs of n=32 each) to avoid precision drift. -constexpr int Nc = 128; -constexpr int WGMMA_N = 32; +The pinned README contains a source-reported claim of **up to 1550 TFLOPS on H800**. It does not attach that number to `M=N=K=4096`, report approximately 90% utilization, or retain a complete reproduction environment. No more specific measurement is attributed to this source entry. -float cuda_core_acc[TILE_M][TILE_N] = {0}; +## Primary References -for (int k = 0; k < K; k += Nc) { - __half2 tc_acc[TILE_M][WGMMA_N]; - memset(tc_acc, 0, sizeof(tc_acc)); - for (int sub_k = 0; sub_k < Nc; sub_k += WGMMA_K) { - wgmma_mma_async(tc_acc, A_smem + sub_k, B_smem + sub_k); - } - wgmma_wait(); - for (int m = 0; m < TILE_M; m++) - for (int n = 0; n < TILE_N; n++) - cuda_core_acc[m][n] += (float)tc_acc[m][n] * scale_a[m] * scale_b[n]; -} -``` - -### SM100 path — tcgen05.mma with UE8M0 block scaling - -```cpp -// On Blackwell, tcgen05.mma consumes UE8M0 scale factors directly. -// 4 UE8M0 values pack into a single uint32; TMEM accumulates in full FP32 -// precision so no CUDA-core promotion is needed. -uint32_t packed_scales = pack_ue8m0(sf[0], sf[1], sf[2], sf[3]); -asm volatile( - "tcgen05.mma.cta_group::1.kind::f8f6f4.block_scale " - "[%0], %1, %2, [%3], %4, 1;\n" - :: "r"(tmem_acc), "l"(desc_a), "l"(desc_b), - "r"(sf_tmem_addr), "r"(0)); -``` - -### MoE grouped-GEMM launch - -```cpp -// Grouped-GEMM packs a variable list of per-expert GEMMs into one kernel -// launch via a prefix-sum offset array; layouts are contiguous (M-axis), -// masked (variable-K), or K-grouped depending on router output. -struct GroupedGemmArgs { - int num_groups; - int* m_prefix; // [num_groups+1] - const __nv_fp8_e4m3* A; - const __nv_fp8_e4m3* B; - const float* scales_a; - const float* scales_b; - __half* C; - int N, K; -}; - -__global__ void grouped_gemm_launch(GroupedGemmArgs args) { - int group = blockIdx.y; - int m_start = args.m_prefix[group]; - int m_end = args.m_prefix[group + 1]; - // Dispatch a standard tile-level GEMM for [m_start, m_end) × N × K. -} -``` +- [README at the pinned commit](https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md) +- [GEMM API at the pinned commit](https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp) +- [JIT compiler at the pinned commit](https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/jit/compiler.hpp) +- [DeepSeek-V3 Technical Report v2](https://arxiv.org/abs/2412.19437v2) diff --git a/sources/blogs/flash-attention-4.md b/sources/blogs/flash-attention-4.md index 53ad4c5d0..8817627fe 100644 --- a/sources/blogs/flash-attention-4.md +++ b/sources/blogs/flash-attention-4.md @@ -16,76 +16,53 @@ tags: - ping-pong-scheduling - conditional-rescaling - cute-dsl -retrieved_at: 2026-04-27 +retrieved_at: 2026-08-08 artifact_dir: artifacts/blogs/flash-attention-4/code --- -## Summary +## Evidence Scope -Tri Dao's blog post on FlashAttention-4 design for Blackwell's asymmetric hardware scaling. +Tri Dao's first-party explanation of FlashAttention-4's Blackwell design and source-reported performance. The two code blocks below are KernelWiki illustrations derived from formulas and dimensions in the post; they are explicitly not verbatim FA4 source from the post. ## Key Techniques -- Asymmetric problem: tensor core throughput doubles but SFU count and SMEM bandwidth unchanged -- Ping-pong scheduling: two 128-token query tiles per CTA -- Software 2^x: Cody-Waite range reduction + Horner polynomial (Sollya-optimized coefficients) -- Multiplies exponential throughput without additional SFU hardware -- Conditional softmax rescaling: only when max jump is large -- 2-CTA backward: paired CTAs share TMEM, halves SMEM traffic -- CuTe-DSL implementation: 20-30x faster compilation than C++ templates -## Performance -- 1605 TFLOPS on B200 BF16 (71% utilization) -- 1.1-1.3x over cuDNN 9.13, 2.1-2.7x over Triton +- A CTA alternates two 128-row output tiles so tensor-core MMA and non-matmul softmax/correction work can overlap. +- FA4 evaluates only a selected fraction of exponentials with FMA polynomial code while retaining hardware `ex2` for the rest. +- The software-selected path uses `n=floor(x)`, a fraction in `[0,1)`, and the post's rounded degree-3 coefficients. +- Conditional rescaling compares running maxima, normally with `tau=8.0` base-2 units, retains the old reference maximum on skipped updates, and renormalizes at the end. +- Two-CTA backward shares operand B for five GEMMs, exchanges the required dS half through distributed shared memory for dQ, and reduces dQ global atomic reductions. It does not halve every dQ/dK/dV shared-memory transfer. -## Key Code +## Performance -### Software exp (Cody-Waite + Horner) +The post reports up to 1605 TFLOPS/s on B200 BF16, labeled 71%, plus up to 1.3x over cuDNN 9.13 and up to 2.7x over Triton. These are maxima over the author's evaluated configurations, not one fully specified `seqlen=8192, headdim=128` row. -```cuda -// Software-emulated exp2(x) using Cody-Waite range reduction and a -// Horner-scheme polynomial, Sollya-optimized coefficients. Lets FA-4 -// overlap the exp path with tcgen05.mma because it stays off the SFU. -__device__ __forceinline__ float sw_exp2(float x) { - // Range reduction: x = n + r, with n = round(x), r in [-0.5, 0.5] - int n = __float2int_rn(x); - float r = x - (float)n; - // Horner-scheme polynomial for 2^r, r in [-0.5, 0.5] - float p = 0x1.62e430p-1f; // ~ ln(2) - p = fmaf(p, r, 0x1.ebfc1ep-3f); - p = fmaf(p, r, 0x1.c6af98p-5f); - p = fmaf(p, r, 0x1.3b2c9cp-7f); - p = fmaf(p, r, 0x1.62e43ap-10f); - float y = fmaf(r, p, 1.0f); - // Scale by 2^n via direct FP32 bit manipulation - int bits = __float_as_int(y) + (n << 23); - return __int_as_float(bits); -} -``` +## Illustrative Code -### Ping-pong scheduling +### Software exp (published range reduction and rounded polynomial) - ```cuda -// Ping-pong two 128-token query tiles per CTA. While one tile is in the -// softmax/rescale stage, the other issues tcgen05.mma — the 2x tensor-core -// throughput on B200 gets fed while the SFU-bound softmax stays out of the -// critical path. -for (int tile = 0; tile < Q_tiles; tile += 2) { - issue_mma(query_a, key_block); - wait_mma(); - softmax_and_rescale(query_a); // SFU + MUFU path - issue_mma(query_b, key_block); - wait_mma(); - softmax_and_rescale(query_b); +// KernelWiki scalar illustration derived from the FA4 blog equations. +// This is not verbatim upstream FA4 code and omits selection and clamping. +#include + +__host__ __device__ inline float fa4_blog_exp2_reference(float x) { + const int n = static_cast(floorf(x)); + const float f = x - static_cast(n); // f in [0, 1) + const float p = 1.0f + f * (0.6951f + f * (0.2276f + f * 0.0771f)); + return ldexpf(p, n); } ``` ### 2-CTA cooperative backward ```cuda -// 2-CTA cooperative backward: paired CTAs in a cluster share a single TMEM -// accumulator half, halving SMEM traffic for dK/dV accumulation. -asm volatile( - "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, 1;" - : : "r"(tmem_acc_shared), "l"(desc_a), "l"(desc_b), "r"(0)); +// KernelWiki schematic derived from the FA4 paper/blog dimensions. +// This is not upstream inline PTX or a complete kernel. +struct Fa4TwoCtaBackwardShape { + static constexpr int cta_group = 2; + static constexpr int mma_m = 256; + static constexpr int mma_n = 128; + static constexpr int mma_k = 128; + static constexpr int backward_gemm_count = 5; +}; ``` diff --git a/sources/blogs/flashmla.md b/sources/blogs/flashmla.md index 3b84964a4..f06e86300 100644 --- a/sources/blogs/flashmla.md +++ b/sources/blogs/flashmla.md @@ -2,7 +2,7 @@ id: blog-flashmla title: FlashMLA — Multi-head Latent Attention author: DeepSeek AI -url: https://github.com/deepseek-ai/FlashMLA +url: https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232 source_category: benchmark-blog architectures: - sm100 @@ -20,75 +20,65 @@ retrieved_at: 2026-04-27 artifact_dir: artifacts/blogs/flashmla/code --- -## Summary - -DeepSeek's efficient MLA kernels for V3/V3.2 with massive KV cache compression (70KB/token). - -## Variants -- Dense MLA decoding (SM90): BF16, paged KV (block 64), 3000 GB/s, 660 TFLOPS on H800 -- Sparse MLA decoding (SM90/SM100): FP8 KV, token-level sparsity, 410 TFLOPS H800, 350 TFLOPS B200 -- Dense prefill (SM100): 1460 TFLOPS fwd, 1000 TFLOPS bwd on B200 -- Sparse prefill (SM90/SM100): 640 TFLOPS H800, 1450 TFLOPS B200 - -## Token Format -656 bytes/token: 512B FP8 data + 16B FP32 scales + 128B BF16 RoPE embeddings - -## Key Code - -### MLA decode inner loop - -```cuda -// MLA collapses K and V into a shared latent matrix of head-dim Dc=128. -// On decode (one query vector against N KV tokens) we alternate TMA load, -// wgmma/tcgen05 into the q@K^T accumulator, online softmax, and the second -// accumulator against V. -constexpr int Dc = 128; // latent head dim -constexpr int BLOCK_N = 64; // paged KV block size -float acc[Dc] = {0}; -float max_val = -INFINITY; -float l = 0.f; -for (int n0 = 0; n0 < seqlen; n0 += BLOCK_N) { - tma_load(smem_kv, KV_pages + n0); - cp_async_wait(); - float scores[BLOCK_N]; - wgmma_or_tcgen05_mma(scores, q, smem_kv); // q @ K^T - float new_max = warp_reduce_max(scores, BLOCK_N); - float scale = expf(max_val - new_max); - for (int j = 0; j < Dc; j++) acc[j] *= scale; - l *= scale; - for (int j = 0; j < BLOCK_N; j++) { - float p = expf(scores[j] - new_max); - l += p; - for (int d = 0; d < Dc; d++) acc[d] += p * smem_kv[j * Dc + d]; - } - max_val = new_max; -} -for (int d = 0; d < Dc; d++) O[d] = acc[d] / l; +## Captured Revision + +This source record summarizes DeepSeek FlashMLA commit `71c737929f2567bd0a094ae140f8f60f390b1232` (2026-03-31). It is a repository/benchmark capture; code below is explicitly KernelWiki-derived and is not copied from the upstream implementation. + +## Supported Operators + +| Operator | Architecture | Mode and format | +|---|---|---| +| Dense decode | SM90 | MQA dimensions `576/512`, BF16 KV cache | +| Sparse decode | SM90/SM100 | MQA dimensions, FP8 KV cache dequantized for BF16 MMA | +| Dense prefill | SM100 | MHA dimensions `192/128` or `128/128`, BF16 inputs | +| Sparse prefill | SM90/SM100 | MQA mode, BF16 Q/KV inputs | + +The repository requires CUDA 12.8+, CUDA 12.9+ for SM100, and PyTorch 2.0+. + +## Exact V3 FP8 Sparse-Decode Layout + +When `is_fp8_kvcache=True` for the DeepSeek-V3-family sparse-decode path, each token uses 512 E4M3 NoPE bytes, four FP32 group scales (16 bytes), and 64 BF16 RoPE values (128 bytes), totaling 656 bytes. Dense decode and other sparse-cache layouts are different. + +### V3 FP8 sparse-decode byte check + +```python +# KernelWiki-derived contract check; not upstream FlashMLA code. +NOPE_FP8_VALUES = 512 +GROUPS = 4 +FP32_BYTES = 4 +ROPE_BF16_VALUES = 64 +BF16_BYTES = 2 + +V3_FP8_SPARSE_BYTES = ( + NOPE_FP8_VALUES + GROUPS * FP32_BYTES + ROPE_BF16_VALUES * BF16_BYTES +) +assert V3_FP8_SPARSE_BYTES == 656 ``` -### Sparse-MLA KV-retrieval kernel (V3.2) - -```cuda -// Sparse MLA selects top-k KV positions per query before running the dense -// MLA kernel on just those positions. Retrieval uses FP8 dot products with -// per-token scale factors. -__global__ void sparse_mla_topk( - const __nv_fp8_e4m3* Q, const __nv_fp8_e4m3* K, - const float* Q_scale, const float* K_scale, - int* topk_idx, float* topk_score, - int N, int K_DIM, int TOPK) -{ - int q_tile = blockIdx.x; - float scores[N]; - for (int n = 0; n < N; n++) { - float s = 0.f; - for (int k = 0; k < K_DIM; k++) { - s += decode_fp8(Q[q_tile * K_DIM + k]) * Q_scale[q_tile] - * decode_fp8(K[n * K_DIM + k]) * K_scale[n]; - } - scores[n] = s; - } - warp_topk_select(scores, N, topk_idx + q_tile * TOPK, - topk_score + q_tile * TOPK, TOPK); -} +## Sparse Index Contracts + +Sparse decode consumes `indices[batch,s_q,topk]` whose entries encode a physical page and offset. Invalid entries are `-1`, and no block table is needed after physical-page encoding. Sparse prefill instead consumes unbatched `indices[s_q,h_kv,topk]` with BF16 Q/KV and accepts negative or out-of-range invalid entries. + +### Decode page-index round trip + +```python +# KernelWiki-derived contract check; not upstream FlashMLA code. +def encode_page_index(physical_page: int, offset: int, page_size: int) -> int: + assert physical_page >= 0 and 0 <= offset < page_size + return physical_page * page_size + offset + +def decode_page_index(encoded: int, page_size: int) -> tuple[int, int]: + assert encoded >= 0 and page_size > 0 + return divmod(encoded, page_size) + +assert decode_page_index(encode_page_index(7, 13, 64), 64) == (7, 13) ``` + +## Source-Reported Performance + +- Dense MLA decode, H800 SXM5/CUDA 12.8: up to 3000 GB/s memory-bound and 660 TFLOPS compute-bound. +- Sparse MLA decode: 410 TFLOPS on H800 SXM5/CUDA 12.8 and up to 350 TFLOPS on B200; FP8 describes KV storage and MMA is BF16. +- Dense **MHA** prefill, B200: up to 1460 TFLOPS forward and 1000 TFLOPS backward, reported by NVIDIA. +- Sparse MLA prefill: up to 640 TFLOPS forward on H800 SXM5/CUDA 12.8 and up to 1450 TFLOPS on B200/CUDA 12.9; documented Q/KV inputs are BF16. + +The repository does not supply complete shape/timing/sample/variance records for these maxima. They remain qualified author reports rather than structured benchmark entries. diff --git a/sources/blogs/gated-delta-net.md b/sources/blogs/gated-delta-net.md index f50a83775..1a80539dd 100644 --- a/sources/blogs/gated-delta-net.md +++ b/sources/blogs/gated-delta-net.md @@ -2,101 +2,31 @@ id: blog-gated-delta-net title: Gated Delta Networks author: NVlabs -url: https://github.com/NVlabs/GatedDeltaNet +url: https://github.com/NVlabs/GatedDeltaNet/tree/b53d6d3a161267432a79c1c04af69fa52bddc921 source_category: benchmark-blog -architectures: -- sm90 -- sm100 +architectures: [] tags: - gated-delta-net - linear-attention - attention - triton - chunk-parallelism -retrieved_at: 2026-04-16 -artifact_dir: artifacts/blogs/gated-delta-net/code +retrieved_at: 2026-08-08 --- -## Summary +## Scope -Linear attention mechanism with delta rule for intelligent memory management (ICLR 2025). Used in Qwen3-Next (3:1 hybrid ratio). +This source capture summarizes the official NVlabs repository at commit `b53d6d3a161267432a79c1c04af69fa52bddc921` and the associated ICLR 2025 paper. It does not preserve a hardware performance record. -## Architecture -- Delta rule: targeted state updates (keep/forget) -- Exponential gating: adaptive memory decay -- Causal Conv1D for local context -- Fixed-size 128×128 state matrix (independent of sequence length) -- O(n) complexity vs O(n²) for standard attention +## Mechanism -## Implementations -- NVlabs reference: Triton kernels -- FLA optimized: recommended, significantly faster, varlen support -- Chunk-based parallelism for prefill, streaming for decode +- Gated DeltaNet combines an independent exponential decay gate with the delta rule's targeted memory correction. +- In the repository implementation, the recurrent state is shaped `[batch, heads, head_qk_dim, head_v_dim]`; its dimensions are model parameters rather than a universal `128x128` constant. +- The layer also owns learned Q/K/V, decay, update, convolution, output-gate, normalization, and output-projection parameters. +- The training path uses chunkwise Triton kernels and a WY representation rather than the additive update shown in the former local snippets. -## Adoption -- Qwen3-Next-80B (3:1 GDN:attention ratio, 512 experts) -- Qwen3.5 (262K context, 10x+ throughput over Qwen3-32B at 32K+) +## Implementations and adoption -## Key Code +The authors' FAQ says that FLA kernels are faster, support variable-length training, and are strongly recommended for better performance. The repository's dated updates record integration into Qwen3-Next and Qwen3.5. -### Chunk-parallel prefill reference (PyTorch) - -```python -import torch - -def gated_delta_net_prefill(q, k, v, gate, initial_state, CHUNK_SIZE=64): - """ - Chunk-parallel prefill. Each chunk's state matrix is reused across its - query window, so we pay the O(Dk*Dv) state update once per chunk, not - per token. - q, k: [B, L, Dk] v: [B, L, Dv] gate: [B, L] - """ - B, L, Dk = q.shape - Dv = v.shape[-1] - out = torch.empty(B, L, Dv, device=q.device, dtype=q.dtype) - state = initial_state.clone() # [B, Dk, Dv] - for ci in range(0, L, CHUNK_SIZE): - ce = min(ci + CHUNK_SIZE, L) - k_chunk = k[:, ci:ce] - v_chunk = v[:, ci:ce] - g_chunk = gate[:, ci:ce] - decay = torch.cumprod(g_chunk, dim=1) # adaptive memory decay - for t in range(ce - ci): - state = state * decay[:, t:t+1, None] - state = state + k_chunk[:, t, :, None] * v_chunk[:, t, None, :] - out[:, ci + t] = (q[:, ci + t, :, None] * state).sum(dim=1) - return out, state -``` - -### Triton decode-step kernel (streaming) - -```python -import triton -import triton.language as tl - -@triton.jit -def gdn_decode_step_kernel( - Q, K, V, GATE, STATE, OUT, - stride_qb, stride_kb, stride_vb, - Dk: tl.constexpr, Dv: tl.constexpr): - """ - One-token delta-rule update for decode. STATE is a [Dk, Dv] matrix kept - per sample; we fold in the new (k,v) pair after applying the decay gate. - """ - b = tl.program_id(0) - dk = tl.arange(0, Dk) - dv = tl.arange(0, Dv) - - q = tl.load(Q + b * stride_qb + dk) # [Dk] - k = tl.load(K + b * stride_kb + dk) # [Dk] - v = tl.load(V + b * stride_vb + dv) # [Dv] - g = tl.load(GATE + b) # scalar decay - - state = tl.load(STATE + b * Dk * Dv + dk[:, None] * Dv + dv[None, :]) - state = state * g # apply decay - state = state + k[:, None] * v[None, :] # delta update - tl.store(STATE + b * Dk * Dv + dk[:, None] * Dv + dv[None, :], state) - - out = tl.sum(q[:, None] * state, axis=0) # [Dv] - tl.store(OUT + b * Dv + dv, out) -``` +No local code block is extracted from this summary. Consult the pinned upstream implementation for executable kernels. diff --git a/sources/blogs/modular-blackwell-matmul.md b/sources/blogs/modular-blackwell-matmul.md index 8b600b8df..12bf4cf88 100644 --- a/sources/blogs/modular-blackwell-matmul.md +++ b/sources/blogs/modular-blackwell-matmul.md @@ -2,105 +2,29 @@ id: blog-modular-blackwell title: "Modular: Matrix Multiplication on Blackwell" author: Modular -url: https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-1-introduction +url: https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-3-the-optimizations-behind-85-of-sota-performance source_category: community-note architectures: [sm100, sm100a] -tags: [gemm, tcgen05, tmem, tma, 2sm-cooperative, pipeline-stages, tma-multicast, clc] +tags: [gemm, tcgen05, tmem, tma, 2sm-cooperative, pipeline-stages, tma-multicast, warp-specialization, double-buffering] techniques: [pipeline-stages, tma-multicast, warp-specialization, double-buffering] -hardware_features: [tcgen05, tmem, tma, 2sm-cooperative, clc] +hardware_features: [tcgen05, tmem, tma, 2sm-cooperative] kernel_types: [gemm] -languages: [cuda-cpp] -retrieved_at: 2026-04-16 +languages: [mojo] +retrieved_at: 2026-08-09 --- -# Modular: Matrix Multiplication on Blackwell +# Modular Blackwell matmul series -## Overview +## Evidence scope -Multi-part blog series from Modular on building a high-performance GEMM kernel for Blackwell GPUs. The series provides a clear optimization progression, reaching 85% of SOTA performance with documented techniques at each step. +Part 3 describes a sequence of Blackwell matmul changes rather than isolated universal prescriptions. The implementation uses 2-SM cooperative MMA and TMA multicast, then adds a five-stage circular buffer for A/B shared-memory tiles. Separate warp roles issue TMA and MMA so different stages can progress concurrently. -**Part 1**: [Introduction](https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-1-introduction) -**Part 3**: [The Optimizations Behind 85% of SOTA Performance](https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-3-the-optimizations-behind-85-of-sota-performance) +The article later double-buffers output writeback in shared memory: TMEM partitions are loaded/converted/stored to alternating output buffers while TMA stores progress. It says the reduced output-buffer footprint frees shared memory for deeper input pipelining, reports an additional 64 TFLOP/s for that final change, and labels the resulting endpoint 85% of the article's SOTA reference. -## Key Techniques +Those are author-reported results for the series' code and benchmark context. The article does not establish that five stages are universally optimal, a fixed B200 HBM latency, a portable percentage for each earlier step, or an architecture-wide optimization order. -### TMA Multicasting +## References -TMA can deliver the same data to multiple SMs in a cluster simultaneously: - -``` -// Without multicast: each SM loads its own copy of shared tiles -// With multicast: TMA loads once, broadcasts to N SMs - -// Example: B matrix tile shared across M-dimension SMs -// If cluster has 4 SMs along M dimension: -// - Without multicast: 4 separate global memory reads -// - With multicast: 1 read, hardware broadcasts to 4 SMs -// 4x reduction in global memory bandwidth for B tiles -``` - -TMA multicasting is particularly effective for GEMM where the B matrix tile is shared across the M dimension of the output. - -### 2-SM Cooperative MMA - -Two SMs cooperate on a single m256 x n256 x k16 tile: - -``` -// Single SM: m128 x n256 x k16 = 128 * 256 * 16 * 2 = 1M FLOPs per MMA -// 2-SM: m256 x n256 x k16 = 256 * 256 * 16 * 2 = 2M FLOPs per MMA - -// Benefits: -// 1. Doubled M dimension -> better data reuse for A tile -// 2. Larger output tile -> fewer tiles needed for full GEMM -// 3. Both SMs share B tile (loaded once via TMA multicast) -``` - -### 5-Stage Circular Buffer Pipeline - -Multi-stage software pipeline for overlapping TMA loads with compute: - -``` -// 5 SMEM buffer slots: -// Slot 0: being consumed by tcgen05.mma (current compute) -// Slot 1: data ready, waiting for compute -// Slot 2: TMA load in progress -// Slot 3: TMA load issued, waiting for completion -// Slot 4: free, ready for next TMA load - -// Deeper pipeline (5 vs 2-3) hides more memory latency -// Critical for large K dimensions where many tiles must stream through -``` - -The 5-stage depth is deeper than the typical 2-3 stages used in simpler implementations, providing better latency hiding at the cost of more shared memory for buffers. - -### Optimization Progression - -The Modular blog documents a clear progression: - -| Step | Technique | Approximate % SOTA | -|------|-----------|-------------------| -| 1 | Basic tcgen05.mma | ~20% | -| 2 | Swizzled SMEM layout | ~45% | -| 3 | TMA async pipeline (5-stage) | ~60% | -| 4 | Warp specialization | ~70% | -| 5 | 2-SM cooperative + TMA multicast | ~85% | - -The remaining 15% gap to SOTA (cuBLAS / CUTLASS persistent) comes from: -- Persistent kernel with CLC scheduling -- Fine-tuned tile sizes for specific problem shapes -- Advanced register allocation and instruction scheduling - -## Key Insights - -1. **TMA multicast reduces bandwidth pressure**: For GEMM, the B matrix tile can be multicast to all SMs processing different M rows. This is a free bandwidth reduction that requires only cluster configuration. - -2. **5-stage pipeline is optimal for B200**: The B200's 8 TB/s bandwidth and deep memory hierarchy benefit from deeper pipelines. Shallower pipelines (2-3 stages) leave performance on the table. - -3. **85% without persistence**: Notably, 85% of SOTA is achievable without persistent kernels or CLC. This makes non-persistent kernels viable for many use cases where simplicity is preferred. - -4. **Clear optimization ordering**: The series demonstrates that optimizations should be applied in order of impact: swizzling > pipelining > warp specialization > 2-SM cooperative. Attempting later optimizations without earlier ones yields minimal benefit. - -## Sources - -- [Part 1: Introduction](https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-1-introduction) -- [Part 3: 85% of SOTA](https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-3-the-optimizations-behind-85-of-sota-performance) +- [Part 1: introduction](https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-1-introduction) +- [Part 3: optimizations behind the 85% endpoint](https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-3-the-optimizations-behind-85-of-sota-performance) +- [Part 3 linked kernel 6](https://github.com/modular/modular/blob/main/max/kernels/test/gpu/linalg/matmul_blackwell_iterative/6_2sm_pipelined.mojo) — rolling branch, not an immutable revision diff --git a/sources/blogs/nsa.md b/sources/blogs/nsa.md deleted file mode 100644 index d29c3e236..000000000 --- a/sources/blogs/nsa.md +++ /dev/null @@ -1,26 +0,0 @@ ---- -id: blog-nsa -title: "Native Sparse Attention (NSA)" -author: DeepSeek AI -url: https://arxiv.org/abs/2502.11089 -source_category: benchmark-blog -architectures: [sm90, sm100] -tags: [sparse-attention, attention, triton, chunk-parallelism] -retrieved_at: 2026-04-16 ---- - -## Summary - -DeepSeek's natively trainable sparse attention with three parallel paths. - -## Architecture -1. Token compression via learnable MLP (coarse-grained) -2. Token selection using blockwise importance scores (top-n fine-grained blocks) -3. Sliding window (w=512) for local context - -## Key Techniques -- Hardware-aligned blockwise memory access -- Group-centric loading: shares sparse KV blocks across GQA group heads -- Triton kernel: grid-based loop scheduling -- 9x forward speedup, 6x backward at 64K sequences vs FlashAttention-2 -- Deployed in DeepSeek-V3.2-Exp diff --git a/sources/blogs/nvidia-code-samples.md b/sources/blogs/nvidia-code-samples.md index 2a5106eae..b4585ae96 100644 --- a/sources/blogs/nvidia-code-samples.md +++ b/sources/blogs/nvidia-code-samples.md @@ -4,22 +4,20 @@ title: NVIDIA Developer Code Samples author: NVIDIA Developer Blog url: https://github.com/NVIDIA-developer-blog/code-samples source_category: community-note -architectures: -- sm90 -- sm100 +architectures: [] tags: - cuda-cpp - gemm -- swizzling - shared-memory-optimization -- vectorized-loads -- register-budgeting retrieved_at: '2026-05-20' description: Source-map entry imported from KernelPilot for CUDA sample kernels and memory-system examples. --- -NVIDIA's developer-blog sample-code repository is useful as a source-map route -for small CUDA examples: coalesced global loads, shared-memory staging, -reductions, transposes, and occupancy-sensitive launch choices. In KernelWiki it -serves as an upstream source pointer rather than a synthesized implementation -claim. +At commit `3350d216083a902ccbf5b31665e3b82096a75b55`, this cross-generation +repository contains small CUDA examples including +`series/cuda-cpp/coalescing-global/coalescing.cu`, +`series/cuda-cpp/shared-memory/shared-memory.cu`, +`series/cuda-cpp/transpose/transpose.cu`, and +`posts/tensor-cores/simpleTensorCoreGEMM.cu`. The source card makes no SM90 or +SM100 compatibility claim; inspect the selected example's build requirements +before reuse. diff --git a/sources/blogs/simon-nvfp4-gemv.md b/sources/blogs/simon-nvfp4-gemv.md index 3fafe9928..4352c36ca 100644 --- a/sources/blogs/simon-nvfp4-gemv.md +++ b/sources/blogs/simon-nvfp4-gemv.md @@ -12,132 +12,58 @@ tags: - fp4 - block-scale - cute-dsl -- vectorized-loads -- register-reuse - batched-gemv -retrieved_at: 2026-04-17 -artifact_dir: artifacts/blogs/simon-nvfp4-gemv/code +techniques: +- k-dimension-parallelism +- reduction +hardware_features: +- nvfp4 +- fp4 +- block-scale +kernel_types: +- batched-gemv +- gemv +languages: +- cute-dsl +- python +retrieved_at: 2026-08-08 --- -# NVFP4 GEMV and Improved NVFP4 GEMV (Simon Veitner) - -## Overview - -Simon Veitner's two-part blog series on implementing NVFP4 GEMV kernels using CuTe DSL for Blackwell GPUs. Part 1 presents a reference CuTe implementation with hierarchical tensor layouts for FP4 block-scaled GEMV. Part 2 ("Improved") introduces three optimization strategies that parallelize the K-dimension reduction, achieving up to 6.4x speedup over the reference. - -## Part 1: Reference CuTe DSL Implementation - -### Configuration - -- Tile dimensions: (128, 1, 64) for M, N, K -- Data types: FP4 (E2M1) for weight matrix, FP8 (E4M3) for scale factors, FP16 output -- Scale factor block size: 16 elements per FP8 scale value -- Thread block size: 128 threads per CTA - -### NVFP4 Format Handling - -NVFP4 is composed of two tensors: one in FP4 precision and another in FP8 precision. The scale factor applies to every block of 16 values to minimize quantization error while reducing memory footprint. - -### Memory Access Patterns - -The kernel uses hierarchical CuTe tensor indexing: -- Matrix A: shape (128, 64, 1, 4, 1) representing one M-tile with four K-tiles -- Scale factors: hierarchical layout ((32,4), (16,4)) enabling broadcast optimization -- Vector B: single N-tile with K-dimension iteration - -### Core Computation - -The computation loop applies two-level scaling: -``` -res += tArA[i] * tArSFA[i] * tBrB[i] * tBrSFB[i] -``` -FP4 values are multiplied by their corresponding FP8 scale factors before accumulation. Values convert from FP4/FP8 to FP32 registers for computation, then convert to FP16 for storage. - -## Part 2: Improved NVFP4 GEMV +# NVFP4 GEMV and Improved NVFP4 GEMV -### Three Optimization Strategies +## Evidence Scope -**Strategy 1: Extra Blocks (K-Parallel Grid)** -- Launches grid blocks corresponding to K-tiles, eliminating the K-tile loop -- Uses atomic operations on global memory (F32 accumulation buffer) -- Performance: ~36,864 ops (benchmark 0), ~55,399 ops (benchmark 1) -- Achieves 6.4x improvement on benchmark 0 versus reference +Simon Veitner's two posts present CuTe DSL Python kernels. They do not publish the CUDA C++ listings formerly attributed to them by this card, and the benchmark outputs are times in nanoseconds rather than operation counts. -**Strategy 2: Thread-Level with Atomic Add** -- Distributes work across thread dimensions (threads_per_m=32, threads_per_k=32) -- Uses shared memory atomics for collaborative result calculation -- Avoids separate F32 tensor allocation overhead -- Performance: ~38,911 ops (benchmark 0), ~67,258 ops (benchmark 1) +## Reference Post -**Strategy 3: Thread-Level with Reduction (No Atomics)** -- Allocates 2D shared memory tensor (K-major stride) -- Each thread pair stores intermediate results, then performs synchronous reduction -- Performance: ~38,911 ops (benchmark 0), ~65,599 ops (benchmark 1) +The first post develops a CuTe DSL reference for the official NVFP4 batched GEMV task. It describes a `(128, 1, 64)` M-N-K tile, 128 threads per block, packed E2M1 operands, E4M3 block scales, and FP32 register accumulation before FP16 output. -### Key Technical Changes +The post's benchmark output includes: -- Serial K-dimension loop replaced with parallel K-reduction -- Intermediate products converted to FP16 for storage efficiency -- FP32 maintained for scale factor operations -- Synchronization barriers inserted between computation and reduction phases -- K-major memory layouts optimize the reduction step access patterns +| Row | Mean time (ns) | +|---:|---:| +| 0 | 234495.997 | +| 1 | 119713.035 | +| 2 | 38911.998 | -### Performance Summary +These are author-reported benchmark results from the displayed environment and are not independent reproduction. -Reference baseline: ~234,495 ops. Best improvement (extra blocks) delivers 6.4x speedup on larger K dimensions, though smaller K problems show more modest gains. +## Improved Post -## Key Insights +The second post parallelizes the K reduction in three ways: -- CuTe DSL's hierarchical tensor layouts naturally express NVFP4's two-level scaling structure -- K-dimension parallelism is critical for GEMV performance on Blackwell -- Atomic-free reductions in shared memory match or approach atomic-based approaches -- The choice between strategies depends on K-dimension size and available SM resources +1. Extra K-grid blocks compute partial sums and use an FP32 global atomic before conversion to FP16. +2. Additional threads collaborate on each row and use an atomic reduction path. +3. Additional threads collaborate through shared memory and an atomic-free reduction. -## Key Code +For the extra-block strategy, the displayed means are 36864.001, 55399.918, and 24576.001 ns for rows 0–2. The post reports additional timing blocks for the two thread-collaboration variants and discusses their shape-dependent tradeoffs. The approximately 6.4× statement compares the first reference row, 234495.997 ns, with 36864.001 ns; it is not a leaderboard score or operation-rate unit. -### Reference core computation (Part 1) +## Provenance Limits -```cpp -// NVFP4 GEMV: FP4 values are decoded to FP32 via their per-block FP8 scale, -// then multiplied against a decoded B element + its FP8 scale. Accumulation -// stays in FP32. Simon's reference kernel does this in a CuTe register tile: -for (int i = 0; i < TILES_K; i++) { - float a = decode_nvfp4(tArA[i]) * decode_fp8(tArSFA[i]); - float b = decode_nvfp4(tBrB[i]) * decode_fp8(tBrSFB[i]); - res += a * b; // FP32 accumulation -} -``` +The posts provide CuTe DSL snippets and benchmark text. Locally reconstructed `.cpp` files extracted from an earlier summary are not verbatim author source and must not be labeled contestant submissions. The public leaderboard snapshot fetched on 2026-08-08 places the `Simon` row at current rank 25 with a 25.112153955 microsecond aggregate score; it does not expose that submission's code. -### Strategy 1 — K-parallel grid with atomic accumulation +## Primary Sources -```cpp -// Launch one CTA per (M-tile, K-tile); accumulate partial products into a -// global FP32 buffer via atomicAdd, then cast to FP16 in a second pass. -__global__ void nvfp4_gemv_k_parallel( - const __nv_fp4_e2m1* A, const __nv_fp8_e4m3* SFA, - const __nv_fp4_e2m1* B, const __nv_fp8_e4m3* SFB, - float* accum_f32, int K_TILES) -{ - int m_tile = blockIdx.x; - int k_tile = blockIdx.y; - float partial = nvfp4_dot_product(A, SFA, B, SFB, m_tile, k_tile); - atomicAdd(&accum_f32[m_tile], partial); -} -``` - -### Strategy 3 — Atomic-free shared-memory reduction - -```cpp -// Each thread pair stores an intermediate product; after __syncthreads() -// the CTA reduces along K-major in shared memory without atomics. -__shared__ float smem[THREADS_PER_M][THREADS_PER_K]; -smem[tid_m][tid_k] = thread_partial; -__syncthreads(); - -// Warp-wide parallel reduction along the K axis -for (int s = THREADS_PER_K / 2; s > 0; s >>= 1) { - if (tid_k < s) smem[tid_m][tid_k] += smem[tid_m][tid_k + s]; - __syncthreads(); -} -if (tid_k == 0) C[m_base + tid_m] = __float2half(smem[tid_m][0]); -``` +- [NVFP4 GEMV](https://veitner.bearblog.dev/nvfp4-gemv/) +- [Improved NVFP4 GEMV](https://veitner.bearblog.dev/nvfp4-gemv-improved/) diff --git a/sources/blogs/simveit-effective-transpose.md b/sources/blogs/simveit-effective-transpose.md index e9385840e..c406bd585 100644 --- a/sources/blogs/simveit-effective-transpose.md +++ b/sources/blogs/simveit-effective-transpose.md @@ -5,20 +5,17 @@ author: Simon Veitner url: https://github.com/simveit/effective_transpose source_category: community-note architectures: -- sm90 -- sm100 +- sm90a tags: -- cute-dsl -- gemm +- cuda-cpp - tma - swizzling -- vectorized-loads - shared-memory-optimization retrieved_at: '2026-05-20' description: Source-map entry imported from KernelPilot for CuTe transpose, swizzle, and memory-layout examples. --- -The effective_transpose repository provides compact CuTe-oriented transpose and -layout examples. Use it when a kernel profile indicates poor sector utilization, -shared-memory bank conflicts, or a need to reason about tiled load/store -layouts. +At commit `994b2b5acaa67f80e411df3e8274b6ae13fd1949`, this Hopper repository +compiles for SM90a and contains raw CUDA C++ TMA transpose variants. +`transpose_swizzle_batched.cu` encodes 128-byte tensor-map swizzling. It is not +a CuTe DSL, GEMM, SM100, or explicit vector-load-width source. diff --git a/sources/blogs/simveit-load-and-store.md b/sources/blogs/simveit-load-and-store.md index 7aec49436..7d29f534f 100644 --- a/sources/blogs/simveit-load-and-store.md +++ b/sources/blogs/simveit-load-and-store.md @@ -5,20 +5,17 @@ author: Simon Veitner url: https://github.com/simveit/load_and_store source_category: community-note architectures: -- sm90 -- sm100 +- sm90a tags: -- cute-dsl -- gemm -- tma -- wgmma -- vectorized-loads -- shared-memory-optimization +- cuda-cpp +- ptx +- ldmatrix +- stmatrix retrieved_at: '2026-05-20' description: Source-map entry imported from KernelPilot for CuTe load/store and shared-memory movement examples. --- -The load_and_store repository is a source-map route for CuTe load/store -mechanics. It is most useful when converting a profiler symptom into a concrete -data-movement edit: vector width, layout, shared staging, or TMA-friendly access -structure. +At commit `05d828cf910dd43f0053ddbbe4744218a06e9d7f`, this repository contains +six inline-PTX examples for `ldmatrix` and `stmatrix` x1/x2/x4 forms. Its +Makefile compiles for SM90a. It contains no CuTe, GEMM, TMA, WGMMA, SM100, or +generic vector-width implementation. diff --git a/sources/blogs/tcgen05-tutorial.md b/sources/blogs/tcgen05-tutorial.md index 9070b0bf8..96491bd0c 100644 --- a/sources/blogs/tcgen05-tutorial.md +++ b/sources/blogs/tcgen05-tutorial.md @@ -20,95 +20,38 @@ retrieved_at: 2026-04-16 artifact_dir: artifacts/blogs/tcgen05-tutorial/code --- -## Summary +# tcgen05 for dummies -Step-by-step tutorial building a Blackwell GEMM kernel from scratch in plain CUDA C++ with PTX, achieving 98% of cuBLAS performance. +## Scope and provenance -## Performance Progression -- Basic kernel: 255 TFLOPS (17%) -- 128B swizzling: 695 TFLOPS (46%) -- Pipelining: 940 TFLOPS (62%) -- Warp specialization: ~1200 TFLOPS (80%) -- Persistent kernel: 1476 TFLOPS (98%) vs 1507 cuBLAS +Gau Nernst's tutorial develops a plain CUDA C++/PTX GEMM on a Modal B200. The article is dated 2025-12-21, and the relevant code is in `02e_matmul_sm100` at repository commit `3b90ac9b3f624bdf1f6f78d02dcd533675d36573`. The disclosed benchmark uses M=N=K=4096 and compares against PyTorch 2.9.1 with CUDA 13 cuBLAS. -## Key Findings -- tcgen05.mma operates directly on shared memory — no ldmatrix needed -- TMEM: 128×512 capacity, 32-bit elements, must alloc/dealloc -- mbarrier synchronization with phases and parity bits -- "Tensor Core programming on Blackwell is easier than previous generations" -- 128B swizzling alone gives 2.7× speedup +Use the linked pinned source for complete assembly operands and synchronization. Earlier local excerpts omitted required tcgen05 operands and were not valid standalone code. -## Key Code +## Source-reported progression -### Basic tcgen05.mma kernel (17% of peak) +| Version | Author's description | TFLOP/s | +|---|---|---:| +| cuBLAS | PyTorch 2.9.1 + CUDA 13 | 1506.74 | +| v1a | basic tcgen05 + 2D 16B TMA | 254.62 | +| v1b | 3D 16B TMA | 252.81 | +| v2a | 2D 128B TMA | 681.20 | +| v2b | 3D 128B TMA | 695.43 | +| v3 | pipelining | 939.61 | +| v4 | warp specialization | 1208.83 | +| v5 | 2-SM MMA | 1302.29 | +| v6 | persistent with static scheduling | 1475.93 | -```cuda -// The naive building block: one-thread-launched tcgen05.mma into TMEM. -// ~255 TFLOPS on B200 (17% of peak). -__shared__ uint32_t tmem; -if (threadIdx.x == 0) { - asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], 256;\n" - :: "r"(&tmem)); -} -__syncthreads(); +These values are reports for the author's exact environment; they are not portable performance guarantees. The final v6 kernel uses static scheduling. The article explicitly says threadblock swizzling and Cluster Launch Control were not added. -for (int k = 0; k < K; k += K_TILE) { - cp_async(smem_a, A + k); - cp_async(smem_b, B + k); - cp_async_commit(); - cp_async_wait<0>(); - __syncthreads(); - if (threadIdx.x == 0) { - asm volatile("tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, 1;\n" - :: "r"(tmem), "l"(desc_a), "l"(desc_b), "r"(0)); - } -} -``` +## Supported takeaways -### 128B swizzling (46% of peak) +- The tutorial demonstrates TMEM allocation/lifecycle, tcgen05 MMA, TMA transfers, mbarrier-driven pipelines, 128-byte swizzling as a performance optimization, warp specialization, 2-SM MMA, and persistence. +- Its 128-byte swizzle stage substantially improves this benchmark, but PTX also defines other valid shared-memory descriptor modes. +- The article's completion and pipeline code should be read in full; short fragments can omit the mbarrier, fence, descriptor, and operand-lifetime context required for correctness. -```cuda -// XOR-swizzled SMEM layout eliminates bank conflicts on MMA load; -// 128-byte granularity gives 2.7x speedup on its own. -template -__device__ void swizzle_128b_store(half* smem, const half* gmem, int k_tile) { - int tid = threadIdx.x; - int col = (tid * 8) % N_K; - int row = (tid * 8) / N_K; - int swizzled = col ^ ((row & 0x7) << 4); // 8-lane XOR swizzle - *reinterpret_cast(&smem[row * N_K + swizzled]) = - *reinterpret_cast(&gmem[k_tile + row * N_K + col]); -} -``` +## References -### Pipelining + mbarrier phases (62% of peak) - -```cuda -// Multi-stage TMA load pipeline. mbarrier phase bits toggle every STAGES -// arrivals so try_wait.parity can distinguish consecutive rounds without a -// counter rollover. -constexpr int STAGES = 4; -__shared__ uint64_t mbar_full[STAGES]; -__shared__ uint64_t mbar_empty[STAGES]; - -if (threadIdx.x == 0) { - for (int i = 0; i < STAGES; i++) { - asm volatile("mbarrier.init.shared::cta.b64 [%0], 1;\n" :: "r"(&mbar_full[i])); - asm volatile("mbarrier.init.shared::cta.b64 [%0], 1;\n" :: "r"(&mbar_empty[i])); - } -} -__syncthreads(); - -int phase = 0; -for (int k = 0; k < K_TILES; k++) { - int stage = k % STAGES; - if (k >= STAGES) { - asm volatile("mbarrier.try_wait.parity.shared::cta.b64 _, [%0], %1;\n" - :: "r"(&mbar_empty[stage]), "r"(phase)); - } - tma_load(smem_a[stage], gmem_a, k); - asm volatile("mbarrier.arrive.shared::cta.b64 _, [%0];\n" - :: "r"(&mbar_full[stage])); - if ((k + 1) % STAGES == 0) phase ^= 1; -} -``` +- [Article](https://gau-nernst.github.io/tcgen05/) +- [Pinned source tree](https://github.com/gau-nernst/learn-cuda/tree/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100) +- [PTX ISA 9.0 tcgen05 reference](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma) diff --git a/sources/blogs/yue-nvfp4-hackathon.md b/sources/blogs/yue-nvfp4-hackathon.md index 23b925f76..a03e0372a 100644 --- a/sources/blogs/yue-nvfp4-hackathon.md +++ b/sources/blogs/yue-nvfp4-hackathon.md @@ -16,7 +16,6 @@ tags: techniques: - vectorized-loads - cache-policy -- register-reuse - loop-unrolling hardware_features: - nvfp4 @@ -29,126 +28,43 @@ languages: - cuda-cpp - ptx - cute-dsl -retrieved_at: 2026-04-16 -artifact_dir: artifacts/blogs/yue-nvfp4-hackathon/code +retrieved_at: 2026-08-08 --- -# Blackwell NVFP4 Kernel Hackathon Journey (Yue Zhang) +# Blackwell NVFP4 Kernel Hackathon Journey -## Overview +## Evidence Scope -Yue Zhang's detailed account of optimizing Problem 1 (NVFP4 Batched GEMV) in the GPU Mode hackathon. Documents the full optimization journey from a naive CuTe DSL implementation (~100us) to a highly optimized CUDA/PTX kernel (22.392us) -- a 4.5x improvement through systematic optimization. +This is an evidence-scoped summary of Yue Zhang's own optimization report for Problem 1. Its performance values and explanations are author-reported; the post does not provide raw repeated-trial data or a complete released submission. At retrieval, the post still said its source-code link was coming soon. -## Performance Progression +## Reported Progression -| Stage | Approach | Latency | Improvement | -|-------|----------|---------|-------------| -| 1 | CuTe DSL baseline | ~100us | -- | -| 2 | Naive CUDA (coalesced access) | ~443us | (worse than CuTe initially) | -| 3 | Hardware intrinsics | ~39us | 11.4x from stage 2 | -| 4 | PTX assembly | ~27us | 1.44x from stage 3 | -| 5 | ILP optimization | ~22.9us | 1.18x from stage 4 | -| 6 | Final tuned | 22.392us | 4.5x from stage 1 | +| Stage | Combined change | Author-reported latency | +|---|---|---:| +| Initial CuTe DSL | First working CuTe path | ~100 µs | +| Optimized CuTe DSL | Scale-load/arithmetic changes and thread collaboration | ~33 µs | +| Initial CUDA | Naive hand-written path | ~2000 µs | +| CUDA optimization 1 | Coalescing, shared B, thread collaboration, warp reduction | ~443 µs | +| CUDA optimization 2 | Remove shared B, per-thread tiles, `float4` loads, hardware intrinsics | ~39 µs | +| CUDA optimization 3 | Vectorized PTX FP4 and scale decode | ~27 µs | +| Parameter tuning | Threads per row and rows per block | ~26 µs | +| ILP | Two tiles per loop iteration | ~22.9 µs | +| Aggressive PTX fusion | Decode, scales, multiply, and accumulation in a larger PTX block | ~22.3 µs | +| Submitted leaderboard score | Geometric mean | 22.392 µs | -Key observation: The initial naive CUDA attempt was slower than CuTe DSL, demonstrating that manual optimization requires deep understanding of the hardware to outperform a well-designed DSL. +The 443-to-39 step is not a coalescing-only result, and the 443-to-27 endpoints do not isolate C intrinsics versus PTX. Each spans multiple simultaneous changes. -## Key Optimization Steps +## Reported Technical Details -### Step 1: CuTe DSL Baseline (~100us) +- The CuTe path reduced duplicate scale loads and scale-product arithmetic, then used multiple threads per output with a shared-memory partial-sum reduction. +- Loading the entire B vector into shared memory and double buffering with asynchronous copy did not improve that CuTe attempt. +- The first CUDA improvement combined coalescing, B/SFB shared-memory staging, multiple threads per row, and warp reduction. +- The next CUDA stage removed B shared-memory staging and combined per-thread K tiles, 16-byte `float4` loads, and hardware FP4 conversion intrinsics. +- The PTX stage used `mov.b32` decomposition and packed `cvt.rn.f16x2.e2m1x2` conversion as part of a vectorized decode path. +- Processing two tiles per loop improved the author's implementation; three or four tiles were slightly slower. -```cpp -// CuTe DSL approach: -// - Automatic partition/copy for NVFP4 data -// - Handles packing/unpacking of FP4 values -// - Reasonable but not optimal memory access patterns -// Result: ~100us -- decent starting point -``` +These observations do not establish that shared memory, load width, inline PTX, or ILP has the same effect in another kernel. -CuTe DSL provided a functional baseline without requiring deep hardware knowledge, but left significant performance on the table for this memory-bound kernel. +## Primary Source -### Step 2: Coalesced Memory Access (~443us, then improved) - -Initial hand-written CUDA was actually slower because the memory access pattern was not properly coalesced: - -```cpp -// Bad: each thread reads non-contiguous FP4 elements -// Good: threads in a warp read contiguous 128-byte chunks -// The FP4 packing (2 elements per byte) requires careful indexing -// to maintain coalesced access at the byte level -``` - -After fixing coalescing, performance improved dramatically but still required hardware-specific optimizations. - -### Step 3: Hardware Intrinsics (~39us) - -Replaced generic type conversions with NVIDIA FP4 hardware intrinsics: - -```cpp -// Generic: manual bit manipulation for FP4 -> FP16 conversion -// float val = decode_fp4_manual(packed_byte >> 4); // slow - -// Hardware intrinsic: single instruction for FP4 -> FP16x2 -// __half2 result = __cvt_fp4x2_to_halfx2(packed_fp4); // fast -``` - -The hardware intrinsic path is 11.4x faster than the manual approach, demonstrating the importance of using ISA-specific instructions for sub-byte data types. - -### Step 4: PTX Assembly (~27us) - -Dropped to raw PTX for fine-grained control: - -```asm -// Key PTX optimizations: -// 1. cvt.rn.f16x2.e2m1x2 for FP4 conversion (vs C intrinsic) -cvt.rn.f16x2.e2m1x2 %result, %fp4_packed; - -// 2. Byte unpacking via mov.b32 (vs bitwise shift/mask) -mov.b32 {b0, b1, b2, b3}, %packed_word; -// Splits 32-bit word into 4 bytes without arithmetic - -// 3. Cache-qualified loads -ld.global.L1::no_allocate.v4.u64 {a0,a1,a2,a3}, [addr_a]; // stream A -ld.global.L1::evict_last.v4.u64 {b0,b1,b2,b3}, [addr_b]; // keep B hot -``` - -The PTX byte unpacking (`mov.b32 {a,b,c,d}`) is a critical optimization: it replaces 3-4 shift/mask instructions with a single register move, and the savings compound across the entire K dimension. - -### Step 5: ILP Optimization (~22.9us) - -Increased instruction-level parallelism by unrolling and interleaving independent operations: - -```cpp -// Before: sequential FP4 decode + accumulate -for (int k = 0; k < K; k += 16) { - decode_fp4(a[k:k+16]); - accumulate(partial_sum); -} - -// After: unrolled with interleaved decode + accumulate -// Decode batch[i+1] while accumulating batch[i] -// Multiple independent accumulator registers -``` - -### Final Result: 22.392us - -The final kernel combined all optimizations. Key factors in the 4.5x total improvement: -1. Hardware FP4 conversion intrinsics (biggest single win) -2. PTX byte unpacking (avoids bitwise overhead) -3. Cache policy differentiation (A: no-allocate, B: evict-last) -4. ILP through unrolling and register interleaving -5. Proper memory coalescing for FP4 packed data - -## Key Lessons Shared - -1. **CuTe DSL is a good starting point**: Even for memory-bound kernels, CuTe provides a reasonable baseline. But for the last 4x of performance, manual optimization is required. - -2. **Hardware intrinsics are essential for sub-byte types**: Generic FP4 decoding is an order of magnitude slower than hardware-specific paths. - -3. **PTX gives control that C++ cannot**: Cache policies, byte unpacking, and instruction scheduling are only accessible at the PTX level. - -4. **Memory-bound kernels need different optimization strategies**: Unlike compute-bound GEMM (where tensor core utilization is key), GEMV optimization is about maximizing memory bandwidth utilization. - -## Sources - -- [Yue's Hackathon Journey](https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html) -- [gpu-mode/reference-kernels](https://github.com/gpu-mode/reference-kernels) +- [Yue Zhang, “My Blackwell NVFP4 Kernel Hackathon Journey”](https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html) diff --git a/sources/contests/flashinfer-mlsys26/track-a-fused-moe.md b/sources/contests/flashinfer-mlsys26/track-a-fused-moe.md index 546d8f9d2..20748edaa 100644 --- a/sources/contests/flashinfer-mlsys26/track-a-fused-moe.md +++ b/sources/contests/flashinfer-mlsys26/track-a-fused-moe.md @@ -1,6 +1,6 @@ --- id: contest-flashinfer-track-a -title: 'FlashInfer MLSys 2026 - Track A: Fused MoE FP8' +title: 'FlashInfer MLSys 2026 Track A: FP8 Block-Scale MoE' source_category: contest-report architectures: - sm100 @@ -9,257 +9,109 @@ tags: - moe - fp8 - block-scale -- fused-kernel +- grouped-gemm techniques: - kernel-fusion -- warp-specialization - tile-scheduling -- pipeline-stages - fine-grained-quantization hardware_features: -- tcgen05 -- tmem - fp8 - block-scale -- tma kernel_types: - moe -- fused-kernel -- gemm - grouped-gemm +- fused-kernel languages: - cuda-cpp - cute-dsl - triton url: https://mlsys26.flashinfer.ai/ -submissions: -- rank: 1 - participant: Gemini 2.5 Pro (AI baseline) - score: 0.628x avg speedup vs FlashInfer - technique: iterative refinement with evolve agent, leverages FP8 block-scale MoE - baseline - submission_truth: unavailable - code_unavailable_reason: AI-baseline submission generated by Gemini 2.5 Pro; the - FlashInfer MLSys 2026 contest organizers have not released the generated code - to the public repository -- rank: 2 - participant: GPT-5 (2025-08-07) - score: 0.467x avg speedup, 92.3% resolve rate - technique: code generation with str_replace iteration; high resolve rate but modest - speedup - submission_truth: unavailable - code_unavailable_reason: AI-baseline submission generated by GPT-5 (2025-08-07 snapshot); - organizers have not released generated code publicly -- rank: 3 - participant: Claude Opus 4.1 - score: 0.456x avg speedup, 73.1% resolve rate - technique: iterative kernel refinement; strong on structured kernels - submission_truth: unavailable - code_unavailable_reason: AI-baseline submission generated by Claude Opus 4.1; organizers - have not released generated code publicly -- rank: notable - participant: SGLang baseline - score: 1262 TFLOPS at batch 4096, 206.9us at batch 1 - technique: 5-fused-launch MoE (vs vLLM 7 launches); CUTLASS SM100 warp-specialized - schedule - submission_truth: unavailable - code_unavailable_reason: SGLang baseline fused-MoE kernel for reference comparison; - sglang's public fused-MoE code lives in the main repo and is captured via pr-sglang-21239 - / pr-sglang-21339 rather than as a contest submission bundle +benchmark_url: https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048 +captured_at: 2026-08-08 +starter_kit_sha: 75ccd05cafceb0fd1f86be4cd0f2117249463c66 +flashinfer_sha: 7f614b86470180bab2d22e36fd1775791c6bf3e6 --- -# Track A: Fused MoE (FP8 Block Scale) - -## Problem Description - -Fused Mixture-of-Experts kernel with FP8 block-scale quantization, targeting B200 GPUs. The kernel must fuse routing, dispatch, dual GEMM (gate-up + down projections), SwiGLU activation, and combine into minimal kernel launches. - -**Benchmark identifier**: `fp8_moe_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048` - -**Parameters**: -| Parameter | Value | -|-----------|-------| -| topk | 8 (experts per token) | -| num_groups | 8 | -| topk_group | 4 | -| num_experts | 32 | -| hidden_size | 7168 | -| intermediate_size | 2048 | -| Scaling | FP8 block-scale (block size 128) | - -## Contest Context - -One of three tracks in the FlashInfer AI Kernel Generation Contest at MLSys 2026. B200 GPU evaluation. Human, AI, or hybrid submissions accepted. Teams of up to 5 members. - -**Timeline**: -- Launch: January 22, 2026 -- Dataset released: February 5, 2026 -- Submission deadline: April 24, 2026 -- Writeup due: May 1, 2026 (4 pages max) -- Awards: May 17-22, 2026 (Bellevue, WA) - -**Submission format**: Fork starter kit, implement in `solution/triton/kernel.py` or `solution/cuda/kernel.cu` + `binding.py`. Pack with `python scripts/pack_solution.py`. CUDA bindings via TVM FFI. - -**API**: `flashinfer.fused_moe.trtllm_fp8_block_scale_moe()` - -## Baseline Performance - -| Framework | Batch 4096 TFLOPS | Batch 1 Latency | -|-----------|-------------------|-----------------| -| SGLang | 1262 | 206.9us | -| FlashInfer CuTeDSL | 1225 | 481.9us | -| vLLM | 1117 | 369.5us | - -SGLang leads at large batch (1262 TFLOPS) and small batch (206.9us). FlashInfer CuTeDSL is competitive at large batch but has higher small-batch latency. - -## Key Challenges - -### 1. No Pre-Tuned FP8 MoE Config for B200 - -Existing FP8 MoE kernels are tuned for Hopper (SM90). Blackwell's different tensor core interface (tcgen05 vs wgmma), TMEM, and CLC require fresh tuning of tile sizes, pipeline depths, and warp configurations. - -### 2. FP8 Numerical Overflow with Block Scaling - -Block size 128 means every 128 elements share one scale factor. Careful handling required: - -```python -# Block-scale FP8 quantization -# Each 128-element block has its own E4M3 scale factor -# Overflow risk: if any element in the block is too large, -# the scale factor saturates and precision is lost for all 128 elements -block_size = 128 -for i in range(0, len(tensor), block_size): - block = tensor[i:i+block_size] - scale = compute_scale_e4m3(block.abs().max()) - quantized[i:i+block_size] = quantize_fp8(block / scale) - scales[i // block_size] = scale -``` - -### 3. Performance Varies by Batch Size - -The kernel must handle both: -- **Large batch** (4096+ tokens): Compute-bound, maximize tensor core utilization -- **Small batch** (1-32 tokens): Memory-bound or launch-overhead-bound, minimize latency - -Different strategies needed for each regime. - -### 4. Multiple Kernel Launches - -Existing implementations use multiple launches: -- **vLLM**: 7 kernel launches (routing, sort, scatter, GEMM1, activation, GEMM2, gather) -- **SGLang**: 5 fused launches -- **Optimal**: 1-2 launches (maximum fusion) - -Each launch adds overhead: kernel launch latency (~5-10us on B200), synchronization, memory traffic for intermediate buffers. - -### 5. Variable Expert Load Balancing - -With topk=8 out of 32 experts, token-to-expert assignment is dynamic. Some experts may receive many tokens while others receive few. The kernel must handle this imbalance efficiently without wasting compute on idle experts. +# Track A: FP8 Block-Scale MoE -### 6. TMA 128-Byte Alignment +## Primary Scope -Tensor Memory Accelerator requires 128-byte aligned descriptors. With dynamic expert routing, per-expert weight and activation pointers must be carefully aligned: +The organizer page identifies Fused MoE as Track A of the MLSys 2026 FlashInfer AI Kernel Generation Contest. The contest challenge targets NVIDIA Blackwell B200 GPUs, and Track A links directly to this definition: -```cpp -// Each expert's weight matrix must start at 128-byte boundary -// For FP8 weights: 128 bytes = 128 elements -// Expert weight layout must account for alignment padding -assert(reinterpret_cast(expert_weights[i]) % 128 == 0); -``` +`moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048` -## Architecture: Fused MoE Pipeline +The definition describes an FP8 block-scale MoE operation with routing and two grouped GEMMs included. It is tagged for DeepSeek-V3 and DeepSeek-R1 and records expert parallelism `ep:8`. -``` -Input tokens (hidden_size=7168) - | - v -[Routing] -> expert assignments (topk=8 per token) - | - v -[Dispatch] -> scatter tokens to assigned experts - | - v -[Gate GEMM] A @ W_gate (FP8 block-scale, 7168 -> 2048) -[Up GEMM] A @ W_up (FP8 block-scale, 7168 -> 2048) - | - v -[SwiGLU] SiLU(gate) * up - | - v -[Down GEMM] activated @ W_down (FP8 block-scale, 2048 -> 7168) - | - v -[Combine] -> weighted sum of expert outputs per token - | - v -Output tokens (hidden_size=7168) -``` +## Definition Axes -## Optimization Strategies +| Axis | Value | +| --- | ---: | +| `seq_len` | variable | +| `num_experts` | 256 | +| `num_local_experts` | 32 | +| `hidden_size` | 7168 | +| `intermediate_size` | 2048 | +| `gemm1_out_size` | 4096 | +| `num_hidden_blocks` | 56 | +| `num_intermediate_blocks` | 16 | +| `num_gemm1_out_blocks` | 32 | -### Kernel Fusion +The definition name and reference fix `top_k=8`, `n_group=8`, and `topk_group=4`. Thus `e32` denotes local experts; routing logits still span 256 global experts. -Fuse dispatch + dual GEMM + SwiGLU + down GEMM + combine into minimal launches: +## Signature -``` -// Strategy 1: 2-launch approach -// Launch 1: dispatch + gate_up_gemm + SwiGLU (fused) -// Launch 2: down_gemm + combine (fused) +| Input | Dtype | Shape | +| --- | --- | --- | +| `routing_logits` | FP32 | `[seq_len, num_experts]` | +| `routing_bias` | BF16 | `[num_experts]` | +| `hidden_states` | FP8 E4M3FN | `[seq_len, hidden_size]` | +| `hidden_states_scale` | FP32 | `[num_hidden_blocks, seq_len]` | +| `gemm1_weights` | FP8 E4M3FN | `[num_local_experts, gemm1_out_size, hidden_size]` | +| `gemm1_weights_scale` | FP32 | `[num_local_experts, num_gemm1_out_blocks, num_hidden_blocks]` | +| `gemm2_weights` | FP8 E4M3FN | `[num_local_experts, hidden_size, intermediate_size]` | +| `gemm2_weights_scale` | FP32 | `[num_local_experts, num_hidden_blocks, num_intermediate_blocks]` | +| `local_expert_offset` | INT32 | scalar | +| `routed_scaling_factor` | FP32 | scalar | -// Strategy 2: 1-launch persistent kernel -// Single persistent kernel handles entire MoE pipeline -// Uses CLC for dynamic tile scheduling across expert groups -``` +The output is BF16 `[seq_len, hidden_size]`. -### Warp Specialization for MoE +## Reference Semantics -``` -// Warp roles in fused MoE: -// - Router warps: compute expert assignments (small, fast) -// - TMA warps: async load expert weights for next batch -// - Compute warps: execute tcgen05.mma for gate/up/down GEMMs -// - Epilogue warps: SwiGLU activation + combine -``` +The official reference uses sigmoid routing. It adds `routing_bias` only for expert selection, scores each of eight groups by the sum of its two largest selection scores, retains four groups, and selects eight global experts. Combine weights come from the corresponding unbiased sigmoid values, normalized per token and multiplied by `routed_scaling_factor`. -### Per-Expert Tile Scheduling +Each rank computes only global experts in its 32-expert local interval. GEMM1 produces the concatenated 4096-column W13 result; the reference splits it into two 2048-column halves, applies SwiGLU, performs GEMM2, and accumulates each expert result with its routing weight. -Dynamic tile assignment based on per-expert token counts: +The reference semantics specify an operation, not a GPU launch count or required tcgen05/TMEM decomposition. -``` -// Expert i has M_i tokens -// Tile grid for expert i: ceil(M_i / tile_M) x ceil(N / tile_N) -// Total tiles across all experts: sum(tiles_per_expert) -// CLC distributes total tiles to available SMs -``` +## Official Evaluation Contract -## FlashInfer-Bench Leaderboard (AI Agent Results) +At starter-kit commit `75ccd05cafceb0fd1f86be4cd0f2117249463c66`, `EVALUATION.md` records: -| Model | Avg Speedup | Resolved % | -|-------|-------------|------------| -| Gemini 2.5 Pro | 0.628x | 73.1% | -| GPT-5 (2025-08-07) | 0.467x | 92.3% | -| Claude Opus 4.1 | 0.456x | 73.1% | -| GPT-O3 | 0.450x | 92.3% | +| Field | Value | +| --- | --- | +| GPU | Bare-metal NVIDIA B200 (`sm_100a`) | +| Locked clocks | `nvidia-smi -ac 3996,1965` | +| Container | `flashinfer/flashinfer-ci-cu132:20260401-2c675fb` | +| CUDA | 13.2 | +| Python | 3.12 | +| PyTorch | 2.12.0+cu132 | +| Triton | 3.6.0 | +| MoE correctness | `atol=1`, `rtol=0.3`, required matched ratio `0.9` | -All AI-generated kernels perform below 1.0x vs FlashInfer baselines, demonstrating that MoE kernel optimization remains a human-expertise task. +The baseline solution is `flashinfer_wrapper_9sdjf3`. For the single-definition MoE track, the score is the arithmetic mean of per-workload `baseline_latency / candidate_latency`; any failing workload zeros that kernel's score. -## Agent Baseline +## Performance Boundary -The [mlsys26-agent-baseline](https://github.com/flashinfer-ai/mlsys26-agent-baseline) provides two approaches: -- **Iterative Agent**: propose solution -> refine via `str_replace` edits -- **Evolve Agent**: generate multiple proposals -> elite pool -> evolutionary improvement -- Supports OpenAI and Claude models +No framework TFLOPS/latency/launch-count table is retained from this source. The current definition page exposes per-solution, per-`seq_len` traces, but a reusable performance record would need a named solution and revision, exact workload, environment, timed region, synchronization, warmup, repetitions, statistic, and variance. The former local 1262-TFLOPS record did not supply those fields. -## K-Search Framework +## Contest Dates and Results -Automated kernel generation using co-evolving world model to guide LLM optimization. Achieves 2.10x average improvement over OpenEvolve, up to 14.3x on complex MoE kernels. +The current organizer page records a January 22, 2026 public launch, February 9 baseline release, April 24 kernel submission deadline, May 1 writeup deadline, May 12 winner notification, and May 22 award ceremony. It now lists the actual Track A winners separately for agent-assisted and full-agent approaches; stale pre-contest AI-baseline rankings are not reproduced here. -## Sources +## Primary Sources -- [MLSys 2026 Contest](https://mlsys26.flashinfer.ai/) -- [FlashInfer Starter Kit](https://github.com/flashinfer-ai/flashinfer-bench-starter-kit) -- [FlashInfer Agent Baseline](https://github.com/flashinfer-ai/mlsys26-agent-baseline) -- [FlashInfer-Bench Paper](https://arxiv.org/abs/2601.00227) -- [FlashInfer-Bench Leaderboard](https://bench.flashinfer.ai/) -- [K-Search Paper](https://arxiv.org/abs/2602.19128) -- [mlsys26-contest Dataset (HuggingFace)](https://huggingface.co/datasets/flashinfer-ai/mlsys26-contest) +- [Organizer page](https://mlsys26.flashinfer.ai/) +- [Exact benchmark definition](https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048) +- [Starter kit at `75ccd05`](https://github.com/flashinfer-ai/flashinfer-bench-starter-kit/tree/75ccd05cafceb0fd1f86be4cd0f2117249463c66) +- [Evaluation contract at `75ccd05`](https://github.com/flashinfer-ai/flashinfer-bench-starter-kit/blob/75ccd05cafceb0fd1f86be4cd0f2117249463c66/EVALUATION.md) +- [FlashInfer reference template at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/trace/templates/moe.py) diff --git a/sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md b/sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md index 9585d75fe..36f8b8d20 100644 --- a/sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md +++ b/sources/contests/flashinfer-mlsys26/track-c-gated-delta-net.md @@ -1,6 +1,6 @@ --- id: contest-flashinfer-track-c -title: 'FlashInfer MLSys 2026 - Track C: Gated Delta Net' +title: 'FlashInfer MLSys 2026 Track C: Gated Delta Net' source_category: contest-report architectures: - sm100 @@ -11,284 +11,71 @@ tags: - chunk-parallelism techniques: - chunk-parallelism -- kernel-fusion -- warp-specialization -- pipeline-stages -hardware_features: -- tcgen05 -- tmem -- tma +hardware_features: [] kernel_types: - gated-delta-net - linear-attention - decode - prefill languages: -- cuda-cpp - cute-dsl -- triton -- tilelang +- python url: https://mlsys26.flashinfer.ai/ -submissions: -- rank: 1 - participant: Gemini 2.5 Pro (AI baseline) - score: 0.628x avg speedup - technique: evolve agent generating GatedDeltaNet chunk-parallel prefill + recurrent - decode - submission_truth: unavailable - code_unavailable_reason: AI-baseline submission generated by Gemini 2.5 Pro for - the Gated Delta Net track; organizers have not released generated code publicly -- rank: 2 - participant: GPT-5 - score: 0.467x avg speedup - technique: iterative Triton kernel generation targeting linear attention delta rule - submission_truth: unavailable - code_unavailable_reason: AI-baseline submission generated by GPT-5 for the Gated - Delta Net track; organizers have not released generated code publicly -- rank: 3 - participant: Claude Opus 4.1 - score: 0.456x avg speedup - technique: code generation referencing NVlabs/GatedDeltaNet and FLA kernels - submission_truth: unavailable - code_unavailable_reason: AI-baseline submission generated by Claude Opus 4.1 for - the Gated Delta Net track; organizers have not released generated code publicly -- rank: notable - participant: FLA (Flash Linear Attention) - score: 10x+ throughput vs Qwen3-32B at 32K+ - technique: optimized Triton kernels for gated delta rule; variable-length support; - chunk-based parallel prefill - submission_truth: unavailable - code_unavailable_reason: FLA (Flash Linear Attention) referenced as the Gated Delta - Net notable baseline; its code lives in fla-org/flash-linear-attention and is - summarized by sources/blogs/gated-delta-net.md + artifacts/blogs/gated-delta-net/code/ - rather than as a contest submission bundle +benchmark_decode_url: https://bench.flashinfer.ai/kernels/gdn_decode_qk4_v8_d128_k_last +benchmark_prefill_url: https://bench.flashinfer.ai/kernels/gdn_prefill_qk4_v8_d128_k_last +captured_at: 2026-08-08 +flashinfer_sha: 7f614b86470180bab2d22e36fd1775791c6bf3e6 --- -# Track C: Gated Delta Net (Qwen3-Next) +# Track C: Gated Delta Net -## Problem Description +## Primary scope -Gated Delta Network kernels for both decode and prefill modes, targeting B200 GPUs. GatedDeltaNet is the linear attention mechanism used in Qwen3-Next-80B and Qwen3.5, replacing standard attention in 75% of layers. +The MLSys 2026 FlashInfer organizer identifies Gated Delta Net as Track C, targets NVIDIA Blackwell B200, and links separate decode and prefill definitions. Both definitions were captured from Qwen3-Next linear-attention layers at tensor parallelism four and are tagged `status:verified`. -**Benchmark identifiers**: -- Decode: `qk4_v8_d128_k_last` -- Prefill: `qk4_v8_d128_k_last` +## Fixed geometry -**Parameters**: qk_dim=4, v_dim=8, d=128 (head dimension) +| Axis | Value | +| --- | ---: | +| `num_q_heads` | 4 | +| `num_k_heads` | 4 | +| `num_v_heads` | 8 | +| `head_size` | 128 | -## GatedDeltaNet Mechanism +The heads remain separate. The recurrent state is `[batch_or_sequences,8,128,128]`, not a flattened `512x1024` matrix. -### Delta Rule +## Decode definition -Unlike standard attention (which writes new KV pairs additively), the delta rule performs error-correcting state updates: +The decode definition fixes `seq_len=1` and varies batch size. Q, K, and V are BF16; the state is FP32 in K-last layout `[B,H,V,K]`. The public inputs also include `A_log`, `a`, `dt_bias`, `b`, and an optional scale. Output is BF16 `[B,1,8,128]`, accompanied by the updated FP32 state. -```python -# Standard linear attention: -# S = S + k @ v^T (additive, no forgetting) +At FlashInfer commit `7f614b8`, the reference computes: -# Delta rule: -# S = S + k @ (v - S^T @ k)^T -# = S + k @ v^T - k @ k^T @ S -# This "deletes" the old value at key k before writing the new value v +```text +g = exp(-exp(A_log) * softplus(a + dt_bias)) +beta = sigmoid(b) +decayed = g * state +read = k @ decayed +new_state = decayed + outer(k, beta * (v - read)) +output = scale * (q @ new_state) ``` -The delta rule enables the model to actively overwrite stale information, which standard linear attention cannot do. +## Prefill definition -### Exponential Gating +The prefill definition varies total sequence length and sequence count, accepts `cu_seqlens[num_seqs+1]`, and returns one final state per sequence. At commit `7f614b8`, FlashInfer dispatches SM90 and SM100 implementations. The SM100/SM103 CuTe DSL path requires CUDA 13 or newer and head size 128. -Adaptive memory decay prevents state saturation: +## Results boundary -```python -# Gated delta rule: -# S_t = gate_t * S_{t-1} + k_t @ (v_t - S_{t-1}^T @ k_t)^T -# where gate_t = exp(-softplus(alpha_t)) in [0, 1] +The current organizer page lists Track C winners separately: -# gate close to 1: retain memory (long-term context) -# gate close to 0: forget quickly (short-term patterns) -# Learned per-head, adaptive per-token -``` - -### Dual-Mode Operation - -GatedDeltaNet operates in two modes with different computational characteristics: - -**Prefill (chunk-based parallel)**: -``` -// Sequence divided into chunks of size C -// Within each chunk: parallel matmul-based computation -// Across chunks: sequential state propagation -// Complexity: O(n * C) for chunk-parallel, O(n/C * d^2) for state updates -``` - -**Decode (streaming recurrent)**: -``` -// Single token at a time -// Update recurrent state S: O(d^2) per token -// State size: (num_heads, qk_dim * d, v_dim * d) = (h, 512, 1024) -// O(1) per token during generation -``` - -## Qwen Architecture Context - -### Qwen3-Next-80B -- 80B parameters, 3B active per token -- 48 layers: 12 x (3 x [GatedDeltaNet -> MoE] -> [Full Attention -> MoE]) -- 75% GatedDeltaNet layers, 25% full attention layers -- 512 routed experts, ~19 active per token (1:50 activation ratio) - -### Qwen3.5 -- 60 layers: 15 x (3 x [GatedDeltaNet -> MoE] -> 1 x [Full Attention -> MoE]) -- 262K token context window -- 10x+ throughput over Qwen3-32B at 32K+ context lengths - -## Key Challenges - -### 1. O(n) Linear Complexity - -Unlike O(n^2) attention, GatedDeltaNet has O(n) complexity. This changes the optimization target: -- Standard attention: reduce memory traffic for QK^T and softmax -- GatedDeltaNet: optimize state update operations and chunk boundaries -- Different roofline model and bottleneck analysis - -### 2. Recurrent State Management - -The hidden state S has shape (qk_dim * d) x (v_dim * d) = 512 x 1024 per head: - -``` -// State S is large: 512 * 1024 * sizeof(float) = 2MB per head -// For 64 heads: 128MB of state per layer -// Must be kept in HBM between tokens during decode -// Must be updated atomically during prefill chunk boundaries -``` - -### 3. Gating Mechanism - -The exponential gating adds branching and additional computation: - -``` -// Per-token gating requires: -// 1. Compute alpha from input (learned linear projection) -// 2. Apply softplus: softplus(alpha) = log(1 + exp(alpha)) -// 3. Negate and exponentiate: gate = exp(-softplus(alpha)) -// 4. Element-wise multiply with state -// The exp and log operations are SFU-bound on Blackwell -``` - -### 4. Variable-Length Support - -Production inference requires handling variable-length sequences in a single batch: - -``` -// Batch of requests at different decode positions: -// Request 0: decode token 1024 (state from prefill of 1023 tokens) -// Request 1: decode token 50 (state from prefill of 49 tokens) -// Request 2: prefill 8192 tokens (chunk-parallel mode) -// Must handle mixed prefill/decode in same batch -``` - -### 5. Triton CPU Launch Overhead - -Current implementations (NVlabs/GatedDeltaNet, FLA) use Triton kernels. Triton's CPU-side compilation and launch overhead impacts small-batch decode latency. vLLM enables full CUDA graph mode to mitigate this. - -## Implementation Status (FlashInfer issue #1690) - -| Mode | Hopper (SM90) | Blackwell (SM100) | -|------|---------------|-------------------| -| Prefill | Done | In progress | -| Decode | Done | Done | - -Blackwell prefill kernel is the primary optimization target for this contest track. - -## Reference Implementations - -### NVlabs/GatedDeltaNet (ICLR 2025) -- Reference Triton kernels -- Chunk-based parallel prefill -- Recurrent decode - -### FLA (Flash Linear Attention) -- Optimized Triton kernels (recommended, significantly faster than NVlabs reference) -- Variable-length support -- Better memory efficiency - -### Key Code Pattern: Chunk-Parallel Prefill - -```python -# Triton kernel sketch for GatedDeltaNet prefill -@triton.jit -def gated_delta_net_chunk_prefill( - Q, K, V, Gate, Output, State, - chunk_size: tl.constexpr, - d: tl.constexpr, -): - # Load chunk of Q, K, V, Gate - q = tl.load(Q + offsets) # [chunk_size, qk_dim * d] - k = tl.load(K + offsets) # [chunk_size, qk_dim * d] - v = tl.load(V + offsets) # [chunk_size, v_dim * d] - g = tl.load(Gate + offsets) # [chunk_size] - - # Intra-chunk: parallel computation - # Compute attention-like scores within chunk - scores = tl.dot(q, tl.trans(k)) # [chunk_size, chunk_size] - - # Apply causal mask and gating - # ... - - # Inter-chunk: update state sequentially - state = tl.load(State + state_offsets) - # state = gate * state + k @ (v - state^T @ k)^T - # ... - - tl.store(Output + offsets, output) - tl.store(State + state_offsets, state) -``` - -## Optimization Strategies for Blackwell - -### TMEM for State Management - -``` -// GatedDeltaNet state S (512 x 1024 floats) could reside in TMEM -// TMEM: 128 rows x 512 cols x 32-bit = 256KB per SM -// State chunk (e.g., 128 x 512) fits in TMEM -// Avoid spilling state to shared memory during updates -``` - -### tcgen05.mma for State Update - -``` -// The state update is a matrix operation: -// S = gate * S + k @ delta_v^T -// Where delta_v = v - S^T @ k -// Both terms involve matmuls suitable for tcgen05.mma -``` - -### Chunk Size Tuning - -Larger chunks -> more parallelism within chunks but more state materialization: - -``` -// Chunk size tradeoffs on B200: -// Small chunks (64): good for decode-like workloads, low latency -// Large chunks (256-512): better tensor core utilization for prefill -// TFLA (Tiled Flash Linear Attention) enables arbitrarily large chunks -// via two-level sequence parallelism -``` - -## Contest Submission Format - -Fork the starter kit per track. Implement in: -- `solution/triton/kernel.py` (Triton) -- `solution/cuda/kernel.cu` + `binding.py` (CUDA) +- Agent-assisted: Kachua, UW SyFI, and LLM-CUDA. +- Full-agent: UW SyFI, LLM-CUDA, and HAN Lab Kernel Mafia. -DPS (Destination Passing Style) by default. CUDA binding via TVM FFI. +The former local Gemini/GPT/Claude ranking was a stale agent-baseline snapshot and is not reproduced as a final result. No latency or speedup record is retained here because a revision-pinned result table with workload, environment, timing protocol, repetitions, statistic, and variance was not captured. -## Sources +## Primary sources -- [MLSys 2026 Contest](https://mlsys26.flashinfer.ai/) -- [FlashInfer Starter Kit](https://github.com/flashinfer-ai/flashinfer-bench-starter-kit) -- [NVlabs/GatedDeltaNet](https://github.com/NVlabs/GatedDeltaNet) (ICLR 2025) -- [FLA (Flash Linear Attention)](https://github.com/fla-org/flash-linear-attention) (recommended implementation) -- [FlashInfer issue #1690](https://github.com/flashinfer-ai/flashinfer/issues/1690) (implementation status) -- [Qwen3-Next NVIDIA Blog](https://developer.nvidia.com/blog/new-open-source-qwen3-next-models-preview-hybrid-moe-architecture-delivering-improved-accuracy-and-accelerated-parallel-processing-across-nvidia-platform/) -- [TFLA Paper](https://arxiv.org/abs/2503.14376) +- [Organizer and winners](https://mlsys26.flashinfer.ai/) +- [Decode definition](https://bench.flashinfer.ai/kernels/gdn_decode_qk4_v8_d128_k_last) +- [Prefill definition](https://bench.flashinfer.ai/kernels/gdn_prefill_qk4_v8_d128_k_last) +- [Pinned FlashInfer reference](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/trace/templates/gdn.py) +- [Pinned FlashInfer prefill dispatch](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/gdn_prefill.py) diff --git a/sources/contests/gpu-mode-nvfp4/problem-1-gemv.md b/sources/contests/gpu-mode-nvfp4/problem-1-gemv.md index d144d4390..a483c5c19 100644 --- a/sources/contests/gpu-mode-nvfp4/problem-1-gemv.md +++ b/sources/contests/gpu-mode-nvfp4/problem-1-gemv.md @@ -10,14 +10,6 @@ tags: - gemv - fp4 - block-scale -techniques: -- vectorized-loads -- cache-policy -- register-reuse -- per-k-specialization -- data-reuse -- register-budgeting -- loop-unrolling hardware_features: - nvfp4 - fp4 @@ -26,203 +18,54 @@ kernel_types: - batched-gemv - gemv languages: -- cuda-cpp -- ptx +- python - cute-dsl -url: https://github.com/gpu-mode/reference-kernels -submissions: -- rank: 1 - participant: Simon (veitner) - score: ~22.4us geomean - technique: Full PTX assembly with cache policy differentiation, byte unpacking, - and aggressive register budgeting (maxrregcount=32) - submission_truth: reconstructed-from-blog - code_path: artifacts/contests/gpu-mode-nvfp4/problem-1-gemv/submissions/rank-1-simon-veitner/03-strategy-3-atomic-free-shared-memory-reduction.cpp -- rank: 2 - participant: yue - score: ~23.0us geomean - technique: Shared B vector reads across BLOCK_M rows, PTX load/decode path, ILP - optimization - submission_truth: reconstructed-from-blog - code_path: artifacts/contests/gpu-mode-nvfp4/problem-1-gemv/submissions/rank-2-yue/05-step-5-ilp-optimization-22-9us.cpp -- rank: 3 - participant: Amandeep - score: ~24.0us geomean - technique: PTX assembly with per-K specialization, vectorized 256-bit loads, cache - bypass for streamed matrix A - submission_truth: unavailable - code_unavailable_reason: Amandeep's PTX-level per-K specialization kernel was shared - in the GPU Mode Discord problem-1 thread; author has not republished to a public - platform at collection time -artifact_dir: artifacts/contests/gpu-mode-nvfp4/problem-1-gemv +url: https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv +retrieved_at: 2026-08-08 --- # Problem 1: NVFP4 Batched GEMV -## Problem Description +## Evidence Scope -Batched matrix-vector multiply with NVFP4 (E2M1) block-scaled inputs on B200 GPUs. +This card records the official task at `gpu-mode/reference-kernels` commit `ae67948685dfccf54ae8374dc9402addb7aae4f6`, the official contest rules, and a dated public leaderboard response. It does not attribute implementations to contestants because the public API exposes no source or technique field. -**Inputs**: -- Matrix `a`: shape (M x K x L), NVFP4 format -- Vector `b`: shape (1 x K x L), NVFP4 format -- Scale factors `sfa`: shape (M x K/16 x L), FP8 E4M3 (one scale per 16 FP4 elements) -- Scale factors `sfb`: shape (1 x K/16 x L), FP8 E4M3 +## Task Contract -**Output**: `c`: shape (M x 1 x L), FP16 +The operation is an N=1 block-scaled NVFP4 matrix-vector product on B200 with FP16 output. Although `task.yml` describes a logical five-tensor tuple, the pinned Python callable receives seven physical tensors: -**Nature**: Memory-bound (low arithmetic intensity -- each FP4 element is only used once in the dot product). +| Tensor | Physical shape | +|---|---| +| A payload | `[M, K/2, L]` | +| B payload | `[128, K/2, L]` | +| logical SFA | `[M, K/16, L]` | +| logical SFB | `[128, K/16, L]` | +| reordered SFA | `[32, 4, ceil(M/128), 4, K/64, L]` | +| reordered SFB | `[32, 4, 1, 4, K/64, L]` | +| C | `[M, 1, L]` | -**Benchmark configurations**: -| Config | M | K | L | -|--------|------|-------|---| -| 1 | 7168 | 16384 | 1 | -| 2 | 4096 | 7168 | 8 | -| 3 | 7168 | 2048 | 4 | +B is physically padded to 128 rows to support the `torch._scaled_mm` reference, but only logical result column zero is copied to C. The generator constructs E4M3FN scale tensors even though the task prose says E4M3FNUZ. There are no FP32 global-scale arguments in this task ABI. Correctness uses `rtol=1e-3` and `atol=1e-3`; K must be divisible by 64, and M must satisfy the submitted kernel's M-tile divisibility rule. -**Speed of light**: ~8.6us for the largest configuration (theoretical bound from B200 8 TB/s memory bandwidth). +## Benchmarks and Ranking -## Timeline +The task publishes these theoretical times under a 1.5 GHz B200 model based on the slower of FFMA math and DRAM transfer time: -November 10 -- November 28, 2025. First of four problems in the hackathon series. +| M | K | L | Theoretical time (µs) | +|---:|---:|---:|---:| +| 7168 | 16384 | 1 | 8.622 | +| 4096 | 7168 | 8 | 17.275 | +| 7168 | 2048 | 4 | 4.317 | -Prizes: 1st place DGX Spark + GTC pass, 2nd RTX 5090 + GTC, 3rd RTX 5080. +Submissions are ranked by the geometric mean of the three benchmark results. The pinned task also contains ten correctness cases. -## NVFP4 Data Format +## Timeline and Public Snapshot -- 4-bit floating-point E2M1: 1 sign bit, 2 exponent bits, 1 mantissa bit -- Representable values: 0, 0.5, 1, 1.5, 2, 3, 4, 6 (positive and negative) -- Block scaling: every 16 FP4 elements share one FP8 E4M3 scale factor -- Two-level scaling: per-block E4M3 scale + per-tensor FP32 global scale -- Dequantization formula: `x_hat_i = s_global * s_block * deq_FP4(q_i)` -- Key difference from MXFP4: E4M3 block scale (non-power-of-two), smaller block size (16 vs 32) +The official rules run Kernel 1 from November 10, 2025 at 12:00 a.m. PT through November 28, 2025 at 11:59 p.m. PT and assign it 10% of the four-kernel grand-prize score. -## Top Performer Results +The mutable public endpoint fetched on 2026-08-08 showed `s.am._`, `gau.nernst`, and `shellsmile15795` in its first three rows with aggregate scores of 18.549562452, 18.552844757, and 18.707609314 microseconds. Yue's 22.392217755 score was rank 11 and Simon's 25.112153955 score was rank 25. Current ranks 2 and 3 have post-cutoff timestamps, so this response must not be presented as an official prize-placement snapshot. -Geometric mean across all three benchmark configurations: -- Rank 1: ~22.4us (using full PTX assembly with per-K specialization) -- Rank 2: ~23.0us (shared B vector reads across BLOCK_M rows) -- Rank 3: ~24.0us +## Primary Sources -Speed-of-light gap: top performers achieved roughly 2.6x of SOL (~8.6us), reflecting the overhead of FP4 decoding and scale application. - -## Optimization Techniques from Top Performers - -### PTX-Level Control - -Raw PTX instructions instead of C intrinsics for critical paths: - -```asm -// FP4 to FP16 conversion via PTX -cvt.rn.f16x2.e2m1x2 %result, %fp4_packed; - -// Byte unpacking: avoid bitwise extraction overhead -mov.b32 {tmp0, tmp1, tmp2, tmp3}, %packed_word; -``` - -Key insight: PTX byte unpacking (`mov.b32 {a, b, c, d}`) is significantly faster than manual bitwise extraction (`>> 4 & 0xF`) for splitting packed FP4 values. - -### Cache Policy Differentiation - -Different cache strategies for different access patterns: - -```asm -// Matrix A (streamed once, never reused): bypass L1 to avoid pollution -ld.global.L1::no_allocate.v4.u64 {a0,a1,a2,a3}, [addr_a]; - -// Vector B (reused across M rows): keep hot in L1 -ld.global.L1::evict_last.v4.u64 {b0,b1,b2,b3}, [addr_b]; -``` - -Rank 1 solution used different `ld.global` qualifiers depending on which K-dimension variant was being compiled. - -### Register Budgeting - -Lower register counts force higher occupancy, which is critical for memory-bound kernels: - -``` -// Rank 1: aggressive register limit -nvcc -maxrregcount=32 ... - -// Rank 3: slightly relaxed -nvcc -maxrregcount=45 ... -``` - -Fewer registers per thread -> more warps per SM -> better memory latency hiding. - -### Wider Vectorized Loads - -128-bit and 256-bit vector loads to maximize memory bandwidth utilization: - -```asm -// 128-bit load (2x uint64) -ld.global.v2.u64 {r0, r1}, [addr]; - -// 256-bit load (4x uint64) -ld.global.v4.u64 {r0, r1, r2, r3}, [addr]; -``` - -Only effective when combined with PTX byte unpacking to avoid bitwise overhead in the unpack stage. - -### Per-K Specialization - -Separate kernel compilations per K-dimension, each with full loop unrolling: - -```cpp -// Each K variant compiled separately with optimal config -template -__global__ void nvfp4_gemv_specialized(); - -// K=1024: fewer iterations, aggressive unrolling -// K=3584: moderate unrolling, different block dims -// K=8192: deepest loop, different register budget -``` - -Different K values have different optimal block dimensions, register limits, and unroll factors. Compiling separate kernels avoids runtime branching. - -### Data Reuse (Rank 2 approach) - -Share the B vector reads across all BLOCK_M rows within a thread block: - -``` -// Each thread block handles BLOCK_M rows -// Vector B is loaded once into shared memory -// All threads in the block reuse the same B data -__shared__ half b_shared[K_TILE]; -``` - -Since B is shape (1 x K x L), every row of A multiplies against the same B vector. Sharing B reads across BLOCK_M rows reduces global memory traffic proportionally. - -## Performance Progression (from Yue's blog) - -| Stage | Technique | Latency | -|-------|-----------|---------| -| CuTe DSL baseline | Basic CuTe partition/copy | ~100us | -| Coalesced access | Fix memory access patterns | ~443us -> 39us | -| Hardware intrinsics | Use cvt.rn.f16x2.e2m1x2 | ~39us | -| PTX assembly | Full PTX with byte unpacking | ~27us | -| ILP optimization | Instruction-level parallelism | ~22.9us | -| Final submission | All combined | 22.392us | - -## Key Lessons - -1. **Memory-bound kernels need bandwidth-first thinking**: Arithmetic optimizations have minimal impact; focus on memory access patterns, cache policies, and vectorized loads. -2. **PTX gives real control on Blackwell**: The gap between C intrinsics and hand-written PTX was substantial (443us -> 27us in one participant's journey). -3. **Nsight Compute confirms memory-bound behavior**: "Run Nsight Compute to confirm memory-bound behavior" (Amandeep's key lesson after 12 attempts). -4. **Register budgeting matters**: On memory-bound kernels, lower register count -> higher occupancy -> better memory latency hiding. The difference between 32 and 45 max registers was measurable. - -## B200 Context - -- Architecture: sm_100a, 142 SMs -- Memory bandwidth: 8 TB/s HBM3e -- Native FP4 (E2M1) tensor core instructions -- TMA for async bulk loads -- TMEM: 128 x 512 x 32-bit per SM (not used for GEMV -- memory-bound, not compute-bound) - -## Sources - -- [gpu-mode/reference-kernels](https://github.com/gpu-mode/reference-kernels) (`/problems/nvidia/nvfp4_gemv/`) -- [Yue's Hackathon Journey](https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html) -- [Twelve Attempts (Amandeep)](https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/) -- [Simon's NVFP4 GEMV Blog](https://veitner.bearblog.dev/nvfp4-gemv/) -- [NVFP4 Format Details](https://haroldbenoit.com/notes/ml/engineering/precision/nvfp4-format) +- [Pinned task directory](https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv) +- [Official terms and conditions](https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf) +- [Public leaderboard endpoint](https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemv/NVIDIA?limit=100) diff --git a/sources/contests/gpu-mode-nvfp4/problem-2-gemm.md b/sources/contests/gpu-mode-nvfp4/problem-2-gemm.md index 0469d52b1..f52c9810b 100644 --- a/sources/contests/gpu-mode-nvfp4/problem-2-gemm.md +++ b/sources/contests/gpu-mode-nvfp4/problem-2-gemm.md @@ -10,181 +10,53 @@ tags: - gemm - fp4 - block-scale -- tcgen05 -- tmem -- tma -techniques: -- warp-specialization -- pipeline-stages -- swizzling -- register-reuse hardware_features: - nvfp4 - fp4 - block-scale -- tcgen05 -- tmem -- tma kernel_types: - gemm languages: -- cuda-cpp -- ptx -- cute-dsl -url: https://github.com/gpu-mode/reference-kernels -submissions: -- rank: 1 - participant: Simon (veitner) - score: 10.807us geomean - technique: CUTLASS SM100 warp-specialized NVFP4 GEMM with tcgen05.mma, optimized - TMA pipeline depth and tile scheduling - submission_truth: unavailable - code_unavailable_reason: Simon's NVFP4 GEMM winning submission posted in the GPU - Mode Discord problem-2 thread; author has not republished the GEMM variant on - a public platform -- rank: 2 - participant: yue - score: 10.914us geomean - technique: CUTLASS-based warp specialization with tuned pipeline stages, TMA async - bulk loads, TMEM accumulator management - submission_truth: unavailable - code_unavailable_reason: Yue's NVFP4 GEMM submission posted in the GPU Mode Discord - problem-2 thread; the public hackathon blog covers GEMV (problem 1), not problem-2 - GEMM -- rank: 3 - participant: currybab - score: 10.931us geomean - technique: CUTLASS KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100 schedule with custom - tile size and cluster shape tuning - submission_truth: unavailable - code_unavailable_reason: currybab's submission posted in the GPU Mode Discord problem-2 - thread; no public author republish at collection time +- python +url: https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm +captured_at: 2026-08-08 --- # Problem 2: NVFP4 GEMM -## Problem Description +## Evidence-scoped task record -Standard NVFP4 block-scaled general matrix multiplication on B200 GPUs. Unlike Problem 1 (GEMV), this is compute-bound and targets tensor core utilization. +The official NVIDIA rules identify this as Kernel Challenge 2, running from November 29 through December 19, 2025. It targets NVIDIA B200 and contributes 20% of the four-problem grand-prize score. -**Operation**: C = A * B where A and B are NVFP4 (E2M1) with per-16-element FP8 E4M3 block scaling. +At `gpu-mode/reference-kernels` commit `ae67948685dfccf54ae8374dc9402addb7aae4f6`, the public task implements block-scaled matrix multiplication over each `L` slice with packed E2M1 A and B, per-16 logical scales, reordered scale copies, and preallocated FP16 C. The correctness checker uses `rtol=1e-3` and `atol=1e-3`. -**Nature**: Compute-bound -- high arithmetic intensity enables tensor core saturation. +The task description abbreviates the input as five tensors, but `task.py`, `template.py`, and `reference.py` expose seven: A, B, logical SFA/SFB, reordered SFA/SFB, and C. The prose/template call the scales E4M3FNUZ, while `reference.py` constructs `torch.float8_e4m3fn`; consumers must follow the actual tensors supplied by the harness. -## Timeline +`K` is divisible by 256. `M` and `N` divisibility depends on the submission's MMA tile. The repository publishes ten correctness cases and three ranking cases. -November 29 -- December 19, 2025. Second problem, weighted 20% for grand prize. +## Ranking contract -## Top Performer Results +Ranking uses the geometric mean of three benchmark results. The task labels these B200 values a theoretical speed-of-light analysis at 1.5 GHz, using the maximum of FP4 Tensor Core math time and DRAM-memory time: -Geometric mean across benchmark configurations: -| Rank | Participant | Geometric Mean | -|------|-----------|----------------| -| 1 | Simon | 10.807us | -| 2 | yue | 10.914us | -| 3 | currybab | 10.931us | +| M | N | K | L | Theoretical time (µs) | +| ---: | ---: | ---: | ---: | ---: | +| 128 | 7168 | 16384 | 1 | 8.994 | +| 128 | 4096 | 7168 | 1 | 2.354 | +| 128 | 7168 | 2048 | 1 | 1.333 | -Extremely tight competition -- top 3 within 1.1% of each other. +These rows are not measured contestant results or a cuBLAS comparison. -## Optimization Techniques +## Public leaderboard boundary -### Tensor Core Utilization +The public Popcorn API snapshot fetched August 8, 2026 places `gau.nernst`, `s.am._`, and `billcarson` at current ranks 1-3. It places `Simon`, `yue`, and `currybab` at ranks 8-10; their API scores, multiplied by one million, are 10.806750, 10.914084, and 10.930623. -Unlike Problem 1 (memory-bound GEMV), GEMM fully leverages Blackwell tensor cores: +The current top-three timestamps are December 20-21, after the official December 19 cutoff. The endpoint therefore does not by itself establish prize winners or cutoff rankings. It exposes score metadata and submission filenames, not contestant source code, optimization techniques, a cuBLAS baseline, trials, or variance. -``` -// tcgen05.mma operates directly on shared memory -// No ldmatrix needed -- operands read from SMEM, results written to TMEM -tcgen05.mma.cta_group::1.kind::f16 - [tmem_addr], // accumulator in TMEM - [smem_desc_a], // operand A descriptor (shared memory) - [smem_desc_b]; // operand B descriptor (shared memory) -``` +## Primary references -Key Blackwell advantage: tcgen05.mma reads operands directly from shared memory and writes results to tensor memory (TMEM), eliminating the register-based ldmatrix/stmatrix pipeline required on Hopper. - -### Warp Specialization - -Dedicated warp roles for overlapping data movement and computation: - -- **TMA warps**: Issue async bulk loads from global to shared memory via TMA descriptors -- **Tensor core warps**: Execute tcgen05.mma on data already in shared memory -- **Epilogue warps**: Handle accumulator readback from TMEM and output conversion - -``` -// CUTLASS schedule used by top performers: -// KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100 -``` - -### TMA for Async Bulk Loads - -Tensor Memory Accelerator handles data movement without consuming SM resources: - -- 128-byte alignment requirement for TMA descriptors -- Async pipeline from HBM -> SMEM via TMA, overlapped with tensor core compute -- Shared memory acts as staging buffer for NVFP4 data + scale factors - -### TMEM for MMA Results - -Tensor Memory holds accumulator state: - -- 128 x 512 matrix of 32-bit elements per SM -- MMA results written directly to TMEM (not registers) -- Eliminates register pressure from large accumulator tiles -- Readback to registers only during epilogue - -### NVFP4 Block Scale Handling - -Scale factors must be applied during or after the MMA: - -``` -// Two-level dequantization in epilogue: -// 1. Apply per-block E4M3 scale factors -// 2. Apply per-tensor FP32 global scale -// 3. Convert accumulator to FP16 output -result[i] = fp16(global_scale * block_scale_a[i/16] * block_scale_b[j/16] * acc[i][j]); -``` - -## Key Code Pattern: CUTLASS SM100 NVFP4 GEMM - -Top performers leveraged CUTLASS 4.x infrastructure: - -```cpp -// CUTLASS collective MMA for NVFP4 on SM100 -using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder< - cutlass::arch::Sm100, - cutlass::arch::OpClassTensorOp, - cutlass::float_e2m1_t, // Element A: NVFP4 - LayoutA, - AlignmentA, - cutlass::float_e2m1_t, // Element B: NVFP4 - LayoutB, - AlignmentB, - float, // Accumulator: FP32 - TileShape, - ClusterShape, - cutlass::gemm::collective::StageCountAutoCarveout<>, - cutlass::gemm::KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100 ->::CollectiveOp; -``` - -## Performance Context - -On B200 (142 SMs, peak FP4 tensor TFLOPS): -- Top performers achieved near-cuBLAS performance for NVFP4 GEMM -- The ~10.8us geometric mean represents excellent tensor core utilization -- Key differentiator from Problem 1: this is compute-bound, so tensor core scheduling and pipeline depth matter more than memory access patterns - -## B200 Hardware Used - -- sm_100a, 142 SMs -- TMEM: 256KB per SM (128 rows x 512 cols x 32-bit) -- tcgen05.mma with native NVFP4 support -- TMA with 128-byte alignment -- 8 TB/s HBM3e bandwidth (less relevant for compute-bound GEMM) - -## Sources - -- [gpu-mode/reference-kernels](https://github.com/gpu-mode/reference-kernels) (`/problems/nvidia/nvfp4_gemm/`) -- [NVIDIA Forums Announcement](https://forums.developer.nvidia.com/t/join-us-for-the-blackwell-nvfp4-kernel-hackathon-with-nvidia-and-gpu-mode/350092) -- [TFLOPS Gap Blog](https://huggingface.co/blog/apsys/blackwell-nvfp4-comparison) +- [Official contest rules](https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf) +- [Pinned task definition](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.yml) +- [Pinned task types](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.py) +- [Pinned starter template](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/template.py) +- [Pinned correctness reference](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/reference.py) +- [Public Popcorn leaderboard API](https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemm/NVIDIA?limit=12) diff --git a/sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md b/sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md index 6664aa758..a7009954e 100644 --- a/sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md +++ b/sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md @@ -7,181 +7,70 @@ architectures: - sm100a tags: - nvfp4 -- gemm - fp4 - block-scale -- tcgen05 -- tmem -- tma -techniques: -- warp-specialization -- kernel-fusion -- epilogue-fusion -- pipeline-stages -hardware_features: -- nvfp4 -- fp4 -- block-scale -- tcgen05 -- tmem -- tma +- gemm +- gated-dual-gemm kernel_types: - gated-dual-gemm - gemm -- fused-kernel languages: -- cuda-cpp -- ptx -- cute-dsl -url: https://github.com/gpu-mode/reference-kernels -submissions: -- rank: 1 - participant: Simon (veitner) - score: ~19us geomean - technique: Fused dual GEMM with shared A tile, epilogue SiLU fusion, dual TMEM accumulator - layout, CUTLASS SM100 schedule - submission_truth: unavailable - code_unavailable_reason: Simon's gated-dual-GEMM winning submission posted in the - GPU Mode Discord problem-3 thread; not republished publicly -- rank: 2 - participant: yue - score: ~19.5us geomean - technique: CUTLASS warp-specialized dual GEMM with TMA pipeline overlap for W_gate - and W_up streams - submission_truth: unavailable - code_unavailable_reason: Yue's gated-dual-GEMM submission posted in the GPU Mode - Discord problem-3 thread; blog covers problem-1 progression, not this problem -- rank: 3 - participant: currybab - score: ~20us geomean - technique: Epilogue-fused SiLU + element-wise multiply, shared input tiling across - both GEMMs - submission_truth: unavailable - code_unavailable_reason: currybab's gated-dual-GEMM submission posted in the GPU - Mode Discord problem-3 thread; no public republish at collection time +- python +url: https://github.com/gpu-mode/reference-kernels/tree/c5b2f7c062d5015f29c3a1043cfd04954397944c/problems/nvidia/nvfp4_dual_gemm +problem_number: 3 +description: Exact public task and correctness-reference scope at the challenge-opening + commit; no unpublished leaderboard or submission details are asserted. --- # Problem 3: NVFP4 Gated Dual GEMM -## Problem Description - -Fused gated dual GEMM implementing the standard MLP gate-up pattern found in modern LLMs (e.g., LLaMA, DeepSeek, Qwen): - -``` -gate = A @ W_gate // First GEMM -up = A @ W_up // Second GEMM -out = SiLU(gate) * up // Activation + element-wise multiply -``` - -Both GEMMs use NVFP4 (E2M1) block-scaled inputs on B200 GPUs. The challenge is fusing the two GEMMs with the SiLU activation and element-wise multiply into a single kernel launch. - -**Nature**: Compute-bound (two full GEMMs), with fusion opportunity in the epilogue. - -## Timeline - -December 20, 2025 -- January 16, 2026. Third problem, weighted 30% for grand prize. +## Verified identity -## Optimization Techniques +The official NVIDIA rules name this Kernel Challenge 3 and give its entry window as December 20, 2025 through January 16, 2026. The public GPU Mode task at commit `c5b2f7c062d5015f29c3a1043cfd04954397944c` targets NVIDIA B200. -### Kernel Fusion Strategy +## Exact operation -The naive approach requires 3 kernel launches: -1. GEMM for gate projection -2. GEMM for up projection -3. Element-wise SiLU(gate) * up +For each batch index `l`, the reference computes: -The fused approach combines all three into a single kernel: - -``` -// Fused approach: single kernel, shared input tiles -// 1. Load A tile from SMEM (shared between both GEMMs) -// 2. Load W_gate tile -> compute partial gate accumulator -// 3. Load W_up tile -> compute partial up accumulator -// 4. In epilogue: apply SiLU to gate, multiply with up, write output +```python +gate = scaled_mm(a[:, :, l], b1[:, :, l].T, sfa, sfb1) +up = scaled_mm(a[:, :, l], b2[:, :, l].T, sfa, sfb2) +output[:, :, l] = silu(gate) * up ``` -Key benefit: Input matrix A is loaded once from HBM and reused for both GEMMs, cutting global memory traffic for A in half. +The two products share `a` and its scale tensor `sfa`; `b1` and `b2` have separate scale tensors. The FP32 product results are combined and converted to FP16 by the correctness reference. -### Epilogue Fusion +## Published tensor contract -The SiLU activation and element-wise multiply are fused into the GEMM epilogue: +| Tensor | Dtype | Logical shape | +| --- | --- | --- | +| `a` | NVFP4 E2M1 | `[M,K,L]`, K-major | +| `b1`, `b2` | NVFP4 E2M1 | `[N,K,L]`, K-major | +| `sfa` | FP8 E4M3FNUZ | `[M,K/16,L]`, K-major | +| `sfb1`, `sfb2` | FP8 E4M3FNUZ | `[N,K/16,L]`, K-major | +| `c` | FP16 | `[M,N,L]` | -```cpp -// SiLU(x) = x * sigmoid(x) = x / (1 + exp(-x)) -// Applied to gate GEMM output, then multiplied with up GEMM output +The submission tuple also includes reordered copies of all three scale tensors and a preallocated output. There is an upstream dtype-label inconsistency at this commit: `task.yml` and `template.py` call the scales E4M3FNUZ, while `reference.py` constructs `torch.float8_e4m3fn`. This capture preserves that distinction instead of silently choosing one spelling. -// In CUTLASS epilogue visitor: -struct SiLUGateFusion { - template - __device__ auto operator()(AccumTile const& gate_acc, AccumTile const& up_acc) { - auto gate_f32 = convert(gate_acc); - auto up_f32 = convert(up_acc); - // SiLU + element-wise multiply - return gate_f32 * sigmoid(gate_f32) * up_f32; - } -}; -``` +`K` must be divisible by 256. The task additionally requires `M` and `N` to be divisible by the selected MMA tile dimensions. The correctness checker uses relative and absolute tolerances of `1e-3`. -### Dual Accumulator Management in TMEM +## Published benchmark and scoring contract -Both GEMM accumulators must fit in TMEM simultaneously: +| M | N | K | L | Theoretical speed-of-light time (µs) | +| ---: | ---: | ---: | ---: | ---: | +| 256 | 4096 | 7168 | 1 | 4.708 | +| 512 | 4096 | 7168 | 1 | 8.714 | +| 256 | 3072 | 4096 | 1 | 2.125 | +| 512 | 3072 | 7168 | 1 | 6.535 | -- TMEM capacity: 128 rows x 512 columns x 32-bit per SM -- Gate accumulator: occupies one region of TMEM -- Up accumulator: occupies adjacent region -- Careful tile sizing to fit both without spilling +Ranking uses the geometric mean of benchmark times. The task labels the last column a speed-of-light analysis based on the maximum of FP4 Tensor Core math time and DRAM-memory time for B200 at a 1.5 GHz clock. These are theoretical comparison values, not measured winning latencies. -``` -// TMEM layout for dual GEMM: -// [0, 255] columns: gate accumulator -// [256, 511] columns: up accumulator -// Both share the same 128 rows -``` - -### Warp Specialization for Dual GEMM - -Extended warp specialization with separate pipelines for each GEMM's weight loads: - -- **TMA warp group 1**: Loads A tiles + W_gate tiles -- **TMA warp group 2**: Loads W_up tiles (A tiles shared) -- **Compute warps**: Execute tcgen05.mma for both GEMMs -- **Epilogue warps**: Fused SiLU + multiply + FP16 output - -### Pipeline Scheduling - -Multi-stage software pipeline handles both weight streams: - -``` -// Stage N: TMA loads A[n], W_gate[n], W_up[n] -// Stage N-1: tcgen05.mma on A[n-1] * W_gate[n-1], A[n-1] * W_up[n-1] -// Stage N-2: Epilogue fusion on completed tiles -``` +## Evidence boundary -The shared A tile across both GEMMs means only 3 TMA streams (A, W_gate, W_up) instead of 4 (A_gate, W_gate, A_up, W_up). - -## Relevance to LLM Inference - -This pattern appears in every transformer MLP block using gated activations: -- **LLaMA/LLaMA-2/LLaMA-3**: SwiGLU MLP (gate + up projections) -- **DeepSeek-V3**: Same gated MLP structure in each expert -- **Qwen-3**: SwiGLU in both dense and MoE variants -- **Mistral/Mixtral**: Gated MLP in every layer - -Fusing the dual GEMM reduces kernel launch overhead and halves the A matrix memory traffic, making it essential for inference latency optimization. - -## CUTLASS Schedule - -Top performers used CUTLASS 4.x with the SM100 NVFP4 schedule: - -```cpp -using KernelSchedule = cutlass::gemm::KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100; - -// The dual GEMM is composed as two CUTLASS GEMMs with shared input -// and a fused epilogue visitor -``` +The public task and reference do not publish a final leaderboard, winning source, launch count, TMEM partition, TMA pipeline, CUTLASS schedule, physical input-load count, or compute-/memory-bound verdict for a submission. No such implementation or result claims are retained in this source capture. -## Sources +## Primary sources -- [gpu-mode/reference-kernels](https://github.com/gpu-mode/reference-kernels) (`/problems/nvidia/nvfp4_dual_gemm/`, `/problems/nvidia/modal_nvfp4_dual_gemm/`) -- [GPU MODE Hackathon (Luma)](https://luma.com/9n27uem4) -- [NVIDIA Forums Announcement](https://forums.developer.nvidia.com/t/join-us-for-the-blackwell-nvfp4-kernel-hackathon-with-nvidia-and-gpu-mode/350092) +- [Official challenge rules](https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf) +- [Pinned public task](https://github.com/gpu-mode/reference-kernels/blob/c5b2f7c062d5015f29c3a1043cfd04954397944c/problems/nvidia/nvfp4_dual_gemm/task.yml) +- [Pinned correctness reference](https://github.com/gpu-mode/reference-kernels/blob/c5b2f7c062d5015f29c3a1043cfd04954397944c/problems/nvidia/nvfp4_dual_gemm/reference.py) diff --git a/sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md b/sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md index e14edcb94..cd58c4719 100644 --- a/sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md +++ b/sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md @@ -10,185 +10,69 @@ tags: - grouped-gemm - fp4 - block-scale -- tcgen05 -- tmem -- tma - moe -techniques: -- warp-specialization -- tile-scheduling -- pipeline-stages -- kernel-fusion -hardware_features: -- nvfp4 -- fp4 -- block-scale -- tcgen05 -- tmem -- tma -- clc kernel_types: - grouped-gemm - gemm - moe languages: -- cuda-cpp -- ptx -- cute-dsl -url: https://github.com/gpu-mode/reference-kernels -submissions: -- rank: 1 - participant: (reward hack - invalidated) - score: 11.191us geomean (invalid) - technique: 'Exploited eval harness: batched all 15 benchmark problems into first - call, subsequent calls returned pre-computed results' - submission_truth: unavailable - code_unavailable_reason: Problem-4 rank-1 slot was invalidated after a reward-hacking - incident; no legitimate kernel was archived, so there is no code to collect -- rank: 2 - participant: Simon (veitner) - score: ~13.2us geomean - technique: CLC dynamic tile scheduling, CUTLASS grouped GEMM with ptr-array interface, - cross-group TMA prefetching - submission_truth: unavailable - code_unavailable_reason: Simon's grouped-GEMM submission posted in the GPU Mode - Discord problem-4 thread; not republished publicly -- rank: 3 - participant: currybab - score: ~13.5us geomean - technique: Group packing for small-M experts, warp-specialized pipeline with group-boundary-aware - scheduling - submission_truth: unavailable - code_unavailable_reason: currybab's grouped-GEMM submission posted in the GPU Mode - Discord problem-4 thread; no public republish at collection time +- python +url: https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm +problem_number: 4 +description: Exact public task and correctness-reference scope after the published + K-divisibility correction; no unpublished legitimate leaderboard is asserted. --- # Problem 4: NVFP4 Grouped GEMM -## Problem Description - -Multiple GEMMs with variable M dimensions but shared N and K, directly relevant to Mixture-of-Experts (MoE) inference on B200 GPUs: - -``` -for i in range(num_groups): - C[i] = A[i] @ B[i] - // A[i] shape: (M_i x K), variable M per group (tokens routed to expert i) - // B[i] shape: (K x N), shared N and K across all groups - // All in NVFP4 with block scaling -``` - -**Nature**: Compute-bound with load-balancing challenge. Variable M_i across groups means some experts receive many tokens while others receive few. - -## Timeline - -January 17 -- February 13, 2026. Final problem, weighted 40% (heaviest) for grand prize. - -Grand Prize: Dell Pro Max with GB300 NVLink. Weighted scoring across all 4 problems: 10% / 20% / 30% / 40%. - -## MoE Relevance - -Grouped GEMM is the core compute kernel for MoE inference: -- DeepSeek-V3: 256 experts, tokens routed to 8 experts each -- Qwen3-Next: 512 experts, ~19 active per token -- Each expert's forward pass is a grouped GEMM where M_i = number of tokens routed to expert i - -The variable M dimension creates significant load imbalance challenges. Some experts may receive hundreds of tokens while others receive zero. - -## Optimization Techniques - -### Dynamic Tile Scheduling with CLC - -Cluster Launch Control (CLC) enables hardware-level dynamic work distribution: - -``` -// CLC dynamically assigns tiles to SMs based on availability -// Critical for grouped GEMM where groups have vastly different sizes -// Small groups (M_i < tile_M) waste compute with static scheduling -// CLC balances load across SMs at hardware speed -``` - -Without CLC, static tile assignment leaves SMs idle when their assigned group finishes early. CLC redistributes remaining tiles to available SMs. - -### Group Packing and Scheduling - -Multiple small groups can be packed into shared tile grids: - -``` -// Naive: one kernel launch per group (high launch overhead) -// Better: single kernel, all groups in one grid -// Best: tile scheduler that packs small groups efficiently - -// For groups with M_i < tile_M (e.g., M_i=3, tile_M=128): -// Pack multiple small groups into shared tiles -// or use specialized small-M kernels -``` - -### Warp Specialization for Variable Workloads - -The warp specialization pattern adapts to variable group sizes: - -- **TMA warps**: Prefetch tiles for the next group while current group computes -- **Compute warps**: Execute tcgen05.mma on current tiles -- **Scheduling warps**: Track group boundaries and manage tile assignment +## Verified identity -### CUTLASS Grouped GEMM Schedule +The official NVIDIA rules name this Kernel Challenge 4, give its entry window as January 17 through February 13, 2026, and assign it 40% of the four-problem grand-prize score. The public GPU Mode task at commit `ae67948685dfccf54ae8374dc9402addb7aae4f6` targets NVIDIA B200. -```cpp -// CUTLASS 4.x grouped GEMM for NVFP4 on SM100 -using KernelSchedule = cutlass::gemm::KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100; +## Exact group contract -// Ptr-array interface: each group has its own A, B, C pointers -// M array specifies per-group row count -// N and K shared across all groups -using GemmKernel = cutlass::gemm::kernel::GemmUniversal< - ProblemShape, // GroupedGemmProblemShape - CollectiveMainloop, - CollectiveEpilogue ->; -``` +The operation is a list of independent block-scaled products. Group `i` computes `C_i = A_i @ B_i.T`. Unlike an M-grouped MoE-only interface, the official correctness cases can vary `M_i`, `N_i`, and `K_i` within the same list. -### Pipeline Overlap Across Groups +| Per-group value | Published dtype | Logical shape | +| --- | --- | --- | +| `a_i` | packed NVFP4 E2M1, two values per byte | `[M_i,K_i/2,L_i]` | +| `b_i` | packed NVFP4 E2M1, two values per byte | `[N_i,K_i/2,L_i]` | +| `c_i` | FP16 | `[M_i,N_i,L_i]` | +| `sfa_i` | FP8 E4M3FNUZ in task/template | `[M_i,K_i/16,L_i]` | +| `sfb_i` | FP8 E4M3FNUZ in task/template | `[N_i,K_i/16,L_i]` | +| size | integers | `(M_i,N_i,K_i,L_i)` | -When processing multiple groups sequentially within a CTA: +The actual Python tuple contains four lists: `(abc_tensors, sfasfb_tensors, sfasfb_reordered_tensors, problem_sizes)`. `task.yml` initially describes only three names, while `template.py`, `task.py`, and `reference.py` expose the reordered-scale list as the fourth value. The first two lists contain logical scales; the third contains layout-reordered scale copies intended for the custom kernel. -``` -// While computing group[i] tiles: -// TMA prefetches group[i+1] weight tiles -// Previous group[i-1] epilogue writes complete -// This hides group-transition latency -``` +At this revision, the prose/template label scales `float8_e4m3fnuz`, but the generator constructs `torch.float8_e4m3fn`. This source capture preserves that upstream inconsistency. Each published case uses `L=1`; `K_i` is divisible by 256, and each `M_i`/`N_i` must satisfy the selected MMA tile divisibility. -## The Reward Hack +The correctness reference independently invokes `torch._scaled_mm` for each group with `B_i` transposed, writes FP16 output, and checks with `rtol=1e-3` and `atol=1e-3`. -A notable submission to Problem 4 reported 11.191us (~2us ahead of the next competitor): +## Published benchmark and scoring contract -**Mechanism**: -1. **Correctness phase**: The evaluation harness clones data objects, so the real kernel runs correctly on fresh data -2. **Timing phase**: The harness reuses the same data objects. The exploit detects first call, fires a single fused super-batch covering all 15 benchmark problems (all 120 groups across all configs). Subsequent calls 2-15 detect pre-computed results and return immediately +| Groups | M values | N | K | L | Theoretical speed-of-light time (µs) | +| ---: | --- | ---: | ---: | ---: | ---: | +| 8 | 80, 176, 128, 72, 64, 248, 96, 160 | 4096 | 7168 | 1 | 18.833 | +| 8 | 40, 76, 168, 72, 164, 148, 196, 160 | 7168 | 2048 | 1 | 10.667 | +| 2 | 192, 320 | 3072 | 4096 | 1 | 2.406 | +| 2 | 128, 384 | 4096 | 1536 | 1 | 1.525 | -**Impact**: Led to improvements in the FlashInfer-Bench evaluation methodology for the MLSys 2026 contest. The incident demonstrated that kernel benchmarking harnesses must isolate timing runs from state carried across invocations. +Ranking uses the geometric mean of benchmark results. The task labels the final column a speed-of-light analysis based on the maximum of B200 FP4 Tensor Core math time and DRAM-memory time at a 1.5 GHz clock. These are theoretical comparison values, not contestant measurements. -## Performance Data +## Reward-hack boundary -| Approach | Approximate Time | -|----------|-----------------| -| Reward hack submission | 11.191us (invalid) | -| Legitimate top performers | ~13-14us range | -| CUTLASS baseline | ~15us range | +GPU Mode's official postmortem records a submission that temporarily reported `11.191 µs`, roughly `2 µs` ahead of the next entry, before being scrubbed. During correctness, it ran a real padded 8-group kernel on each of 15 cloned objects. During timing, one call launched a merged 120-group kernel for all 15 objects and calls 2 through 15 returned cached output pointers; the harness divided the combined work by 15. This number is therefore an invalid amortized exploit result, not a legitimate performance record. -Exact legitimate leaderboard data not fully published due to the hack incident. +The postmortem points to `gpu-mode/reference-kernels` PR #104 as the evaluation-harness response. It does not establish a FlashInfer-Bench or MLSys 2026 causal link. -## Key Challenges +## Evidence boundary -1. **Load imbalance**: Expert routing creates highly variable M_i values. Some groups may have M_i=0 (no tokens routed) -2. **Small-group efficiency**: Groups with M_i < tile_M waste compute on padding -3. **Group-transition overhead**: Switching between groups incurs pointer arithmetic and descriptor updates -4. **TMA alignment**: Each group's A matrix must be 128-byte aligned for TMA, requiring careful memory layout -5. **TMEM reuse**: Accumulator tiles in TMEM must be cleared between groups +The task fixes observable tensors, correctness, benchmark workloads, theoretical estimates, timeout, and scoring. It does not require one GPU launch, CUTLASS, CLC, TMA, TMEM, a persistent scheduler, or a particular bottleneck classification. No legitimate final ranks, winner source, or implementation techniques are published in the pinned task, so none are asserted here. -## Sources +## Primary sources -- [gpu-mode/reference-kernels](https://github.com/gpu-mode/reference-kernels) (`/problems/nvidia/nvfp4_group_gemm/`) -- [Reward Hack Writeup](https://www.gpumode.com/news/reward-hacking-nvfp4) -- [GPU MODE Hackathon (Luma)](https://luma.com/9n27uem4) -- [NVIDIA Forums Announcement](https://forums.developer.nvidia.com/t/join-us-for-the-blackwell-nvfp4-kernel-hackathon-with-nvidia-and-gpu-mode/350092) +- [Official challenge rules](https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf) +- [Pinned public task](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml) +- [Pinned starter template](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/template.py) +- [Pinned correctness reference](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/reference.py) +- [Official reward-hack postmortem](https://www.gpumode.com/news/reward-hacking-nvfp4) diff --git a/sources/docs/cutlass-clc-documentation.md b/sources/docs/cutlass-clc-documentation.md index c329e4e3e..9688e2724 100644 --- a/sources/docs/cutlass-clc-documentation.md +++ b/sources/docs/cutlass-clc-documentation.md @@ -1,124 +1,33 @@ --- id: doc-cutlass-clc -title: "CUTLASS Cluster Launch Control (CLC) Documentation" -url: https://docs.nvidia.com/cutlass/latest/media/docs/cpp/blackwell_cluster_launch_control.html +title: "CUTLASS 4.5.0 Cluster Launch Control Documentation" +url: https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md source_category: official-doc architectures: [sm100, sm100a] tags: [clc, cluster, tile-scheduling, persistent-kernel, mbarrier, 2sm-cooperative, pipeline-stages, gemm] -retrieved_at: 2026-04-17 +retrieved_at: 2026-08-09 --- -# CUTLASS Cluster Launch Control (CLC) Documentation +# CUTLASS 4.5.0 Cluster Launch Control -## Overview +## Verified scope -Cluster Launch Control (CLC) is a Blackwell hardware feature enabling dynamic tile scheduling for persistent GEMM kernels. Rather than static tile distribution where each thread block computes a predetermined output tile, CLC launches a grid of thread blocks and dynamically allocates work based on SM resource availability. Introduced in CUTLASS 3.8.0, CLC eliminates workload imbalance when SMs have uneven availability (e.g., partial SM allocation with Green Context or concurrent kernel execution). +This card is pinned to CUTLASS v4.5.0 commit `e406c186f510a15091cce01f782020ceb7ba8eb5`. -## Core Mechanism +CLC launches the full problem grid. Every ClcID is processed either by the block/cluster that launches at that coordinate or by a running worker that successfully cancels that not-yet-started ClcID and receives its coordinate. A worker therefore processes its initial `blockIdx` before requesting later work. -### Static vs Dynamic Scheduling +`clusterlaunchcontrol.try_cancel` writes a 16-byte response asynchronously to shared memory and completes a transaction on an mbarrier. The response is decoded only after completion. A failed response is terminal for requests from that thread; issuing another request from the same thread after observing failure is undefined. -**Static Persistent Kernels (Hopper approach)**: -- Each thread block is pre-assigned a set of output tiles at launch -- Suffers from workload imbalance when SMs are occupied by other work -- Idle SM stalls reduce overall throughput +For thread-block clusters, cancellation and the returned first coordinate are cluster-granular. Each participating CTA adds its local cluster rank to derive its coordinate. -**CLC Dynamic Scheduling (Blackwell)**: -- Launches a grid containing as many thread blocks as there are output tiles -- Thread blocks query CLC to receive their next tile assignment at runtime -- Tiles are allocated only to available workers -- Prevents idle SM stalls from uneven workload distribution +## CUTLASS integration -### ClcID System +CUTLASS 4.5.0 uses `PersistentTileSchedulerSm100` and `PipelineCLCFetchAsync`. Scheduler methods such as `advance_to_next_work()` and `fetch_next_work()` stage and consume CLC requests. Exact pipeline depth and participant counts are kernel configuration, not universal CLC constants. -Grid coordinates are treated as ClcID identifiers. Each ClcID represents one output tile. The system guarantees that all coordinates are processed through one of two paths: -1. Direct worker launch (for the initial wave) -2. Scheduler query response (for subsequent tiles) +Swizzle size and raster order are CUTLASS software coordinate-transform policy applied to initial and returned coordinates. They are not operands or policies programmed into the raw CLC instruction. Stream-K decomposition and multi-problem scheduling are likewise higher-level scheduler decisions, not work synthesized by CLC. -## Pipeline Architecture +## References -### Key Configuration Parameters - -| Parameter | Value | Description | -|---|---|---| -| Transaction size | 16 bytes | Size of CLC response stored in SMEM | -| Pipeline depth | 3 | Number of overlapped CLC operation waves | -| Producer arrival count | 1 | Single scheduler warp thread | -| Consumer arrival count | Total threads of consuming warps | All warps needing ClcIDs | -| Producer block ID | 0 | First CTA in cluster acts as scheduler | - -### Pipeline Depth = 3 - -The CLC pipeline uses depth 3 to overlap CLC operations across multiple waves for latency hiding. This means up to 3 CLC queries can be in-flight simultaneously, with responses arriving asynchronously. - -## Producer-Consumer Architecture - -### Producer: Scheduler Warp -- Warp 1 of the 0th CTA in the cluster acts as the scheduler -- Issues CLC queries via `advance_to_next_work()` -- Produces ClcID responses into shared memory -- The scheduler warp is also its own consumer (to detect grid completion signals) - -### Consumers: All Computation Warps -- MMA warps (tensor core computation) -- Mainloop load warps (TMA data fetching) -- Epilogue load warps -- Epilogue store warps -- All consume ClcID assignments via `get_current_work()` - -### Asynchronous Pipeline Management - -CLC queries are pipelined using `PipelineCLCFetchAsync`, which manages the producer-consumer relationship: -1. Producer issues query (stores response address in SMEM) -2. CLC hardware writes 16-byte response to specified SMEM address -3. Consumer warps wait on barrier for response availability -4. Consumer reads ClcID and begins processing the assigned tile -5. Producer can issue next query before consumers finish current tile - -## Cluster Granularity - -CLC operates on cluster granularity, not individual CTA granularity: -- A 2x2 persistent worker cluster consumes 2x2 = 4 ClcIDs per query -- This aligns with Blackwell's 2SM cooperative execution model -- Cluster shapes can be specified as preferred or fallback configurations - -### Preferred and Fallback Cluster Shapes - -The CLC API supports specifying: -- **Preferred cluster shape**: The optimal configuration (e.g., 2x1 for 2SM cooperative) -- **Fallback cluster shape**: Used when the preferred shape cannot be satisfied due to resource constraints - -## Core CUTLASS Classes - -### PipelineCLCFetchAsync -Manages the asynchronous CLC query pipeline with producer-consumer semantics. Key operations: -- Initialize pipeline with depth, transaction bytes, and arrival counts -- Producer phase: issue CLC queries and signal barriers -- Consumer phase: wait on barriers and read responses - -### PersistentTileSchedulerSm100 -Implements the tile scheduling logic: -- `advance_to_next_work()`: Issues the next CLC query (producer side) -- `get_current_work()`: Retrieves the current tile assignment (consumer side) -- Handles grid completion detection -- Manages stream-K decomposition for load balancing - -## Integration with GEMM Kernels - -CLC is used in CUTLASS Blackwell persistent GEMM kernels: -1. Kernel launches with grid size = number of output tiles -2. Initial tiles are assigned directly by CLC hardware -3. After processing a tile, each cluster queries for the next tile -4. Grid completes when all ClcIDs have been consumed and processed -5. Supports both tile-parallel and stream-K decomposition - -## Comparison with Hopper Scheduling - -| Aspect | Hopper (Static) | Blackwell (CLC) | -|---|---|---| -| Tile assignment | Pre-computed at launch | Dynamic at runtime | -| Load balancing | Fixed, may be uneven | Adaptive to SM availability | -| Overhead | Zero runtime overhead | CLC query latency (hidden by pipeline) | -| Green Context | Poor utilization | Efficient partial SM use | -| Stream-K | Software-managed | Hardware-assisted | -| Cluster support | Limited | Native preferred/fallback shapes | +- [Pinned CLC documentation](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md) +- [Pinned SM100 scheduler](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cutlass/gemm/kernel/sm100_tile_scheduler.hpp) +- [PTX ISA 9.0 CLC instructions](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel) diff --git a/sources/docs/deepseek-v2-mla.md b/sources/docs/deepseek-v2-mla.md new file mode 100644 index 000000000..aa6b3504a --- /dev/null +++ b/sources/docs/deepseek-v2-mla.md @@ -0,0 +1,18 @@ +--- +id: doc-deepseek-v2-mla +title: 'DeepSeek-V2: A Strong, Economical, and Efficient Mixture-of-Experts Language Model' +author: DeepSeek-AI +url: https://arxiv.org/abs/2405.04434v5 +source_category: paper +architectures: [] +tags: +- mla +- attention +retrieved_at: 2026-08-08 +--- + +## MLA Cache Formula + +Section 2.1.1 defines Multi-head Latent Attention and Table 1 compares per-layer, per-token KV-cache elements. Standard MHA caches `2 * n_h * d_h` elements. MLA caches `d_c + d_h^R` elements; for the paper's `d_c=4*d_h` and decoupled-RoPE dimension `d_h^R=d_h/2`, this is approximately `4.5*d_h` elements. + +The comparison is stated in elements, so byte totals additionally depend on storage dtype, layer count, and any quantization metadata. This paper record supports the model-level mechanism; FlashMLA's implementation-specific 656-byte FP8 sparse-decode layout is documented separately by its repository. diff --git a/sources/docs/deepseek-v3-fp8.md b/sources/docs/deepseek-v3-fp8.md new file mode 100644 index 000000000..ed9294323 --- /dev/null +++ b/sources/docs/deepseek-v3-fp8.md @@ -0,0 +1,21 @@ +--- +id: doc-deepseek-v3-fp8 +title: 'DeepSeek-V3 Technical Report: FP8 Training' +author: DeepSeek-AI +url: https://arxiv.org/abs/2412.19437v2 +source_category: paper +architectures: +- sm90 +tags: [fp8, fine-grained-quantization, block-scale, gemm] +retrieved_at: 2026-08-08 +--- + +## Fine-Grained Quantization + +Sections 3.3.1-3.3.2 define the DeepSeek-V3 FP8 mixed-precision framework. Forward activations are scaled per `1x128` tile and weights per `128x128` block so smaller groups can better accommodate outliers. The paper also documents phase-specific exceptions, such as `128x1` activation grouping for backward use. + +## Hopper Accumulation + +Sections 3.3.3 and 3.5.2 describe promotion on Hopper. A 128-element K interval—equivalent to four WGMMAs in the cited configuration—is accumulated and then combined with scaling factors in FP32 CUDA-core registers. The paper characterizes the Tensor Core alignment/addition precision relevant to the limitation as 14 bits and discusses the extra scale handling rather than claiming zero overhead. + +This paper establishes the model/training format and numerical motivation. DeepGEMM's exact scale tensor layouts, supported recipes, and architecture-specific kernel implementations are pinned separately. diff --git a/sources/docs/flash-attention-4.md b/sources/docs/flash-attention-4.md index e29629def..4c6769839 100644 --- a/sources/docs/flash-attention-4.md +++ b/sources/docs/flash-attention-4.md @@ -1,33 +1,31 @@ --- id: doc-flash-attention-4 -title: "FlashAttention-4: Hardware-Friendly Attention on Blackwell" -url: https://arxiv.org/abs/2603.05451 +title: "FlashAttention-4: Algorithm and Kernel Co-design for Blackwell GPUs" +url: https://arxiv.org/abs/2603.05451v1 source_category: paper architectures: [sm100] tags: [attention, flash-attention, tcgen05, tmem, 2sm-cooperative, software-exp, ping-pong-scheduling] -retrieved_at: 2026-04-16 +retrieved_at: 2026-08-08 --- -## Summary +## Evidence Scope -FlashAttention-4 paper — algorithm-kernel co-design for Blackwell's asymmetric hardware scaling (tensor core throughput doubles but SFU count unchanged). +FlashAttention-4 paper v1 (2026-03-05), an author-primary description of the algorithm, CuTe DSL implementation, and B200 evaluation. This entry is a summary, not executable source or an independently reproduced benchmark. -## Key Contributions +## Forward Pass -### Forward Pass -- Ping-pong scheduling with two 128-token query tiles per CTA -- Dedicated softmax warpgroups handle S=QK^T accumulator in TMEM -- Software-emulated exponential via Cody-Waite range reduction + Horner polynomial -- Conditional softmax rescaling (only when max jump is large) +- One CTA pipelines two 128-row output tiles through one MMA warp, two softmax warpgroups, and a correction warpgroup, with score/output accumulators in TMEM. +- Roughly 10-25% of exponential entries are evaluated with a Cody-Waite-style floor reduction and degree-3 FMA polynomial; the remainder use hardware MUFU `ex2`. +- Conditional rescaling permits the retained row maximum to lag, typically by `tau=log2(256)=8.0`, then performs final renormalization. -### Backward Pass -- 2-CTA backward spanning paired CTAs in a cluster, sharing TMEM -- Halves shared memory traffic and global atomic reductions for dQ +## Backward Pass -### Implementation -- Written in CuTe-DSL (Python), 20-30x faster compilation than C++ templates +- Five backward GEMMs use two-CTA MMA with `M=256, N=128, K=128` in the described configuration. +- Pairing roughly halves shared-memory reads for operand B of those GEMMs; it does not halve all backward shared-memory traffic. +- dQ uses a distributed-shared-memory exchange of half-dS tiles and a doubled reduction width that halves the described global atomic reductions. -## Performance -- Up to 1605 TFLOPS on B200 BF16 (71% utilization) -- 1.1-1.3x over cuDNN 9.13 -- 2.1-2.7x over Triton +## Implementation and Performance + +- The implementation is written in CuTe DSL. The paper reports single-kernel compilation of 2.5 seconds versus 55 seconds for forward and 1.4 seconds versus 45 seconds for backward compared with FA3. +- Paper v1 reports up to 1613 TFLOPS/s on B200 BF16, labeled 71% under the authors' peak convention, and up to 1.3x over cuDNN 9.13 and 2.7x over Triton. +- The benchmark suite spans several sequence lengths and head-dimension pairs. The text does not establish one `seqlen=8192, headdim=128` row containing all those maxima. diff --git a/sources/docs/nsa.md b/sources/docs/nsa.md new file mode 100644 index 000000000..0e2e92ce2 --- /dev/null +++ b/sources/docs/nsa.md @@ -0,0 +1,39 @@ +--- +id: blog-nsa +title: "Native Sparse Attention: Hardware-Aligned and Natively Trainable Sparse Attention" +author: DeepSeek AI +url: https://aclanthology.org/2025.acl-long.1126/ +source_category: paper +architectures: [] +tags: [sparse-attention, attention, triton] +retrieved_at: 2026-08-08 +--- + +## Source identity and scope + +This is the ACL 2025 proceedings paper for Native Sparse Attention. Its efficiency experiments use an eight-GPU A100 system. It does not establish SM90/SM100 compatibility or Blackwell performance for the paper's Triton implementation. + +## Architecture + +NSA combines three attention branches with learned input-dependent sigmoid gates: + +1. overlapping KV blocks compressed by learned MLPs with intra-block position encoding; +2. fine-grained blocks selected by aggregating and reusing compression-attention scores; and +3. a direct sliding window over recent tokens. + +The experimental settings are compression block length 32/stride 16, selected block length 64 with 16 blocks, and a 512-token window. + +## Hardware-aligned selected attention + +For selected attention, the paper describes a Triton training/prefill kernel that loads all query heads in a GQA/MQA group together, shares their sparse KV indices, consumes contiguous KV blocks, and maps nearly constant query/output loops to grid parallelism. It does not publish source code or an exact three-dimensional grid declaration. + +## Source-reported performance + +- Figure 5 reports 9.0x forward and 6.0x backward speedup at 64K against the authors' Triton FlashAttention-2 baseline. +- Table 4 gives 11.6x as an **expected** 64K decoding speedup derived from memory-access volume, not a matched timing measurement. + +The record does not provide dtype, software versions, batch details, raw samples, or variance for a fully reproducible benchmark tuple. + +## Deployment boundary + +DeepSeek-V3.2-Exp later released DeepSeek Sparse Attention (DSA), whose learned indexer selects token positions and whose sparse kernels are provided through FlashMLA. That later DSA mechanism is not the paper's gated three-branch NSA architecture. diff --git a/sources/docs/nvidia-blackwell-tuning-guide.md b/sources/docs/nvidia-blackwell-tuning-guide.md index 2c3949a34..69b64aa98 100644 --- a/sources/docs/nvidia-blackwell-tuning-guide.md +++ b/sources/docs/nvidia-blackwell-tuning-guide.md @@ -10,138 +10,30 @@ retrieved_at: 2026-04-16 # NVIDIA Blackwell Tuning Guide -## Overview +## Scope -Official NVIDIA tuning guide for Blackwell (SM100/SM100a) GPU architectures. The primary reference for understanding Blackwell hardware features and their performance implications for kernel developers. +Official NVIDIA tuning guidance for Blackwell. Exact tcgen05 instruction grammar, operand locations, descriptor fields, target constraints, and ordering rules should be checked in the version-pinned PTX ISA rather than inferred from this higher-level tuning page. -## Key Hardware Features +## Evidence-scoped hardware summary -### tcgen05.mma (Tensor Core Generation 05) +- PTX describes tcgen05 as the fifth-generation TensorCore family. Dense `tcgen05.mma` is asynchronous and is issued by one thread. +- D resides in TMEM. A can be described in SMEM or addressed in TMEM; B is described in SMEM. +- The dense kinds in PTX ISA 9.0 are `f16`, `tf32`, `f8f6f4`, `i8`, `mxf8f6f4`, `mxf4`, and `mxf4nvf4`. The three MX forms use the block-scaled grammar. +- M and N are encoded by the instruction descriptor and have kind-, layout-, CTA-group-, and target-specific constraints. m128n256k16 and m256n256k16 are maximum-shape examples for common F16/BF16 configurations, not an exhaustive shape list. +- `cta_group::2` cooperates with a peer CTA and can access peer resources as defined by PTX. It does not imply one universal rule that doubles M for every legal configuration. +- `tcgen05.commit` plus an mbarrier provides completion tracking. `tcgen05.fence` provides ordering around execution-ordering operations; it does not replace the completion wait. +- The shared-memory descriptor supports multiple swizzle modes, including none, 128B, 64B, and 32B. The selected layout must satisfy its documented constraints. -Replaces Hopper's wgmma.mma_async. Fundamental changes: +## Cluster Launch Control -- **Single-thread launch**: One thread issues the MMA instruction (vs warpgroup of 128 threads on Hopper) -- **CTA scope**: Operates at CTA level, not warpgroup level -- **Direct SMEM operand reads**: Operands read directly from shared memory -- no ldmatrix needed -- **TMEM accumulator output**: Results written to Tensor Memory, not registers -- **7 data type variants**: TF32, FP16/BF16, INT8, FP8 (E4M3/E5M2), FP6, FP4/NVFP4 +CLC launches the problem-sized grid. A worker begins with its own `blockIdx`; after that work, it may request cancellation of an unspecified not-yet-started block or cluster and process the returned identifier itself. This work-stealing mechanism can improve utilization in suitable persistent schedules, but it neither deletes application-selected work nor guarantees removal of every last-wave or load-imbalance effect. -Maximum MMA shapes: -| Configuration | Shape | -|---|---| -| 1-SM (1-CTA) | m128 x n256 x k16 (BF16) | -| 2-SM cooperative | m256 x n256 x k16 (BF16) | +## Use of performance claims -7 variants: tf32, f16, i8, f8f6f4, mxf8f6f4.block_scale, mxf4.block_scale, mxf4nvf4.block_scale +Treat quantitative claims as source- and environment-specific. The separate `tcgen05 for dummies` source reports one B200 M=N=K=4096 progression. Its final persistent result uses static scheduling, not CLC. -### Tensor Memory (TMEM) - -Dedicated 256KB per-SM memory for MMA accumulators: - -- Layout: 128 rows x 512 columns x 32-bit elements -- Accessible only by the SM's tensor core unit -- Eliminates register pressure from large accumulator tiles -- 420 clock cycles end-to-end for cache-miss access (58% less than Hopper's 1000 cycles for register path) -- Best for multi-stage tensor pipelines with large working sets -- SMEM better for single-shot small-matrix operations -- Explicit alloc/dealloc lifecycle -- Power-of-2 column allocation (minimum 32) -- Data movement: tcgen05.st (reg->TMEM), tcgen05.ld (TMEM->reg), tcgen05.cp (SMEM->TMEM) - -### Cluster Launch Control (CLC) - -Hardware-level dynamic tile scheduling: - -- Replaces static grid-based tile assignment -- Dynamically distributes tiles to available SMs -- Eliminates tail effects (last-wave underutilization) -- Enables persistent kernels without manual tile queue management -- `clusterlaunchcontrol.try_cancel` API for graceful termination -- Critical for grouped GEMM / MoE where group sizes vary - -### TMA (Tensor Memory Accelerator) - -Async bulk data movement engine (carried from Hopper, enhanced): - -- Moves data from global -> shared memory without SM intervention -- 128-byte alignment requirement for descriptors -- Supports multicasting to multiple SMs in a cluster -- Pipelined with mbarrier for async producer-consumer - -### 2-SM Cooperative MMA - -Two SMs cooperate on a single larger MMA: - -- Doubles effective M dimension (m256 vs m128) -- SMs share the output tile via TMEM -- Requires SMs to be in the same cluster -- Best for large GEMM tiles where single-SM MMA is not wide enough - -### NVFP4 and Sub-Byte Data Types - -Native tensor core support for narrow data types: - -- **FP4 (E2M1)**: 4-bit float, representable values: 0, 0.5, 1, 1.5, 2, 3, 4, 6 -- **FP6**: 6-bit float -- **FP8 (E4M3, E5M2)**: 8-bit float (carried from Hopper) -- **Block scaling**: Built into MMA instruction. Per-block UE8M0 scale factors. -- **NVFP4 block scale**: 16 FP4 elements share one FP8 E4M3 scale factor - -### PDL (Programmatic Dependent Launch) / GDC (Grid Dependency Control) - -- PDL enabled by default on Blackwell -- Overlaps dependent kernel launches -- GDC controls inter-kernel dependencies at grid level -- Reduces kernel launch gaps from ~5us to near-zero for dependent chains - -## Hardware Specifications - -| Feature | Value | -|---|---| -| Architecture | SM100a (B200) | -| SMs | 142 | -| Max warps/SM | 64 | -| 32-bit registers | 64K per SM | -| SMEM per SM | 228 KB | -| TMEM per SM | 256 KB (128 rows x 512 cols) | -| Max thread blocks/SM | 32 | -| Max cluster size | 8 (portable), 16 (opt-in) | -| L2 cache | 126 MB (B200) | -| HBM3e bandwidth | 8 TB/s | -| Peak FP16/BF16 tensor | ~2x Hopper | -| Peak FP4 tensor | ~4x Hopper | - -## Performance Optimization Path - -Demonstrated progression from the tcgen05 tutorial (Gau Nernst): - -``` -Naive (17% cuBLAS) -> 128B Swizzling (46%) -> Pipelining (62%) --> Warp Specialization (80%) -> 2-SM MMA (86%) --> Persistent Kernel + CLC (98% cuBLAS) -``` - -Each step addresses a specific bottleneck: -1. **Swizzling**: Eliminates shared memory bank conflicts -2. **Pipelining**: Overlaps TMA loads with compute -3. **Warp specialization**: Dedicated warps for TMA vs compute -4. **2-SM cooperative**: Larger effective tile for better reuse -5. **Persistent + CLC**: Eliminates tail effects and kernel launch overhead - -## Hopper-to-Blackwell Migration Summary - -| Aspect | Hopper (SM90) | Blackwell (SM100) | -|---|---|---| -| MMA instruction | wgmma.mma_async (warpgroup) | tcgen05.mma (single-thread, CTA) | -| MMA output | Registers | TMEM (256KB/SM) | -| Max BF16 MMA | m64n256k16 | m128n256k16 (1-CTA), m256n256k16 (2-CTA) | -| Matrix loading | ldmatrix to registers | Direct from SMEM | -| Synchronization | Warpgroup (4 warps) | Single thread, fully async | -| New data types | FP8 | FP4, FP6, FP8 with block scaling | -| Scaling | External (CUDA core promotion) | Native UE8M0 block scaling in MMA | -| Register pressure | High (accumulators in regs) | Low (accumulators in TMEM) | - -## Sources +## Primary references - [NVIDIA Blackwell Tuning Guide](https://docs.nvidia.com/cuda/blackwell-tuning-guide/) -- [Blackwell Architecture Whitepaper](https://www.nvidia.com/en-us/data-center/technologies/blackwell-architecture/) +- [PTX ISA 9.0, CUDA 13.0.2 archive](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html) +- [CUDA Programming Guide: Cluster Launch Control](https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html) diff --git a/sources/docs/nvidia-cuda-13-0-2-tma.md b/sources/docs/nvidia-cuda-13-0-2-tma.md new file mode 100644 index 000000000..9dedac309 --- /dev/null +++ b/sources/docs/nvidia-cuda-13-0-2-tma.md @@ -0,0 +1,27 @@ +--- +id: doc-cuda-13-0-2-tma +title: "CUDA 13.0.2 TMA Documentation" +url: https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#asynchronous-data-copies-using-the-tensor-memory-accelerator-tma +source_category: official-doc +architectures: [sm90, sm90a, sm100, sm100a] +tags: [tma, mbarrier, swizzling] +retrieved_at: 2026-08-08 +version: "CUDA 13.0.2" +--- + +# CUDA 13.0.2 TMA documentation + +## Evidence-scoped summary + +- TMA uses tensor maps for non-blocking rank-1 through rank-5 tensor copies on compute capability 9.0 and later. +- Global-to-shared loads complete through mbarrier transaction-byte accounting; shared-to-global stores use bulk async groups. +- Tensor-map swizzling changes shared-memory layout and must be paired with matching consumer indexing and alignment. +- The version-pinned Driver API defines encoder alignment, dimension, stride, datatype, interleave, swizzle, and OOB-fill constraints. +- Blackwell supports documented device-side tensor-map construction and modification with tensor-map proxy ordering. + +The documentation defines mechanisms and constraints, not a universal stage depth, bandwidth multiplier, or best swizzle for every kernel. + +## Primary references + +- [CUDA 13.0.2 Programming Guide: TMA](https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#asynchronous-data-copies-using-the-tensor-memory-accelerator-tma) +- [CUDA Driver API 13.0.97: tensor maps](https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html) diff --git a/sources/docs/nvidia-cuda-register-controls.md b/sources/docs/nvidia-cuda-register-controls.md new file mode 100644 index 000000000..f0449b5e5 --- /dev/null +++ b/sources/docs/nvidia-cuda-register-controls.md @@ -0,0 +1,29 @@ +--- +id: doc-cuda-register-controls +title: "CUDA 13 Register Controls and Occupancy APIs" +url: https://docs.nvidia.com/cuda/archive/13.0.0/cuda-c-programming-guide/index.html +source_category: official-doc +architectures: [sm100, sm100a, sm90, sm90a] +tags: [register-budgeting, occupancy, launch-bounds, maxrregcount, spills] +retrieved_at: 2026-08-09 +--- + +# CUDA 13 Register Controls and Occupancy APIs + +## Evidence Scope + +This card routes register-budget claims to archived NVIDIA documentation. The CUDA C++ Programming Guide 13.0 defines launch-bounds compiler behavior and the occupancy calculator. The CUDA Compiler Driver 13.0.2 defines `--maxrregcount`, `--resource-usage`, and the assembler's spill warning. The CUDA Runtime API 13.0.2 defines the occupancy function contract. + +## Exact Contracts + +- `__launch_bounds__(maxThreadsPerBlock, minBlocksPerMultiprocessor, maxBlocksPerCluster)` supplies launch constraints and compiler guidance. The compiler derives a register threshold `L`; it does not make the second argument an exact achieved block count or directly set registers per thread. +- If initial use exceeds `L`, the compiler reduces it, usually at the expense of local-memory use and/or instruction count. If both maximum threads and minimum blocks are present, the compiler may also increase use up to `L` to reduce instructions. +- `--maxrregcount` sets a maximum for GPU functions. A value below the ABI minimum is raised, some registers are compiler-reserved, and NVIDIA describes the option as a tradeoff between individual-thread performance and available parallelism. +- `--resource-usage` reports registers and memory, including stack-frame bytes and spill loads/stores. `ptxas --warn-on-spills` warns when registers spill to local memory. +- `cudaOccupancyMaxActiveBlocksPerMultiprocessor` returns the maximum active blocks per SM for a compiled function, intended block size, and dynamic shared-memory size. It predicts residency, not application performance. + +## Primary References + +- [CUDA C++ Programming Guide 13.0: Occupancy Calculator and Launch Bounds](https://docs.nvidia.com/cuda/archive/13.0.0/cuda-c-programming-guide/index.html) +- [CUDA Compiler Driver 13.0.2: `--maxrregcount` and `--resource-usage`](https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html) +- [CUDA Runtime API 13.0.2: Occupancy](https://docs.nvidia.com/cuda/archive/13.0.2/cuda-runtime-api/group__CUDART__OCCUPANCY.html) diff --git a/sources/docs/nvidia-cutlass-blackwell.md b/sources/docs/nvidia-cutlass-blackwell.md index 76f37cc29..190b917e6 100644 --- a/sources/docs/nvidia-cutlass-blackwell.md +++ b/sources/docs/nvidia-cutlass-blackwell.md @@ -1,149 +1,36 @@ --- id: doc-cutlass-blackwell -title: "NVIDIA CUTLASS 4.x Blackwell Support" -url: https://docs.nvidia.com/cutlass/latest/CHANGELOG.html +title: "NVIDIA CUTLASS 4.5.0 Blackwell Sources" +url: https://github.com/NVIDIA/cutlass/tree/v4.5.0 source_category: official-doc architectures: [sm100, sm100a] -tags: [tcgen05, tmem, tma, clc, 2sm-cooperative, nvfp4, fp8, fp4, fp6, block-scale, cute-dsl] -retrieved_at: 2026-04-16 +tags: [tcgen05, tmem, tma, clc, nvfp4, block-scale, cute-dsl] +version: "4.5.0" +retrieved_at: 2026-08-09 --- -# NVIDIA CUTLASS 4.x Blackwell Support +# NVIDIA CUTLASS 4.5.0 Blackwell Sources -## Overview +## Evidence scope -CUTLASS 4.x introduces comprehensive SM100 (Blackwell) support, including new MMA atoms for tcgen05, TMEM management, CLC-based tile scheduling, and sub-byte data type support (FP4, FP6, FP8 with block scaling). +This card routes version-sensitive CUTLASS claims to tag `v4.5.0`, commit `e406c186f510a15091cce01f782020ceb7ba8eb5`. CUTLASS provides both C++ template APIs and Python-native DSLs; this card does not rank one as the primary Blackwell interface. Rolling `latest` documentation can describe later APIs and is not evidence for an exact 4.5.0 symbol. -## Key Components +## Verified CuTe DSL loci -### UMMA (Unified Matrix Multiply-Accumulate) +- `python/CuTeDSL/cutlass/cute/nvgpu/tcgen05/mma.py` defines typed tcgen05 operations including `MmaF16BF16Op`, `CtaGroup`, operand sources, and traits. +- `python/CuTeDSL/cutlass/cute/nvgpu/tcgen05/copy.py` defines TMEM load, store, and shared-to-TMEM copy operations. +- `python/CuTeDSL/cutlass/cute/arch/tmem.py` defines allocation, pointer retrieval, permit relinquishment, and deallocation helpers. +- `examples/python/CuTeDSL/cute/blackwell/tutorial/tutorial_gemm/fp16_gemm_0.py` through `fp16_gemm_6.py` are the tagged progressive dense-GEMM tutorials. +- The tutorial constructs TMA atoms with `CopyBulkTensorTileG2SOp` plus `make_tiled_tma_atom_A/B`; it does not define `SM100_TMA_LOAD_2D`. +- The tutorial uses `TmemAllocator`, typed copy atoms, `make_tmem_copy`, and explicit pipeline state. Short snippets that omit those lifetimes are not standalone kernel recipes. -CUTLASS abstraction replacing WGMMA for Blackwell: +## Scope limits -- **Register-free operation**: Operands in SMEM, accumulators in TMEM -- **Single-thread launch**: One thread issues the MMA (vs warpgroup of 128 on Hopper) -- **Built-in block scaling**: Native support for FP4/FP6/FP8 with per-block scale factors -- **Two-level abstraction**: - - `MMA_Atom`: Direct PTX wrapper for tcgen05.mma variants - - `MMA_Traits`: CuTe layout definitions for data arrangement +The tag supplies layout algebra and Blackwell helper functions, but users still choose datatypes, instruction/CTA shapes, operand modes, tile layouts, alignment, swizzles, participant groups, and pipeline policy. The source tree alone does not establish a universal runtime-performance percentage. -### SM100 GEMM Schedules +## Direct links -CUTLASS provides several optimized kernel schedules for SM100: - -```cpp -// Standard 1-SM warp-specialized GEMM -cutlass::gemm::KernelTmaWarpSpecialized1Sm - -// 2-SM cooperative GEMM (doubled M tile) -cutlass::gemm::KernelTmaWarpSpecialized2Sm - -// NVFP4 specialized (block-scale aware) -cutlass::gemm::KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100 - -// Persistent kernel with CLC scheduling -cutlass::gemm::KernelTmaWarpSpecializedPersistent1Sm -``` - -### CuTe SM100 Atoms - -New CuTe atoms for Blackwell hardware: - -```cpp -// tcgen05 MMA atom -using MMA = decltype(make_tiled_mma( - SM100_MMA_SS_128x256x16_BF16_RS{}, // MMA atom: SMEM x SMEM -> TMEM - Layout>{} // Atom layout -)); - -// TMA copy atom -using CopyA = SM100_TMA_LOAD; -using CopyB = SM100_TMA_LOAD; -``` - -### SM100 Attention Kernels - -CUTLASS 4.x adds SM100 attention kernels with Blackwell-specific features: - -- **Fused reduction for MLA**: Weight-absorbed MLA decoding kernel, similar to FlashMLA -- **MLA K-splitting**: Supports splitting K dimension across multiple SMs for large head dimensions -- **16-warp kernels**: Distinct warp specialization roles (TMA, compute, softmax, epilogue) -- **Ping-pong scheduling**: Two query tiles per CTA with dedicated softmax warpgroups handling TMEM - -### Sub-Byte Data Type Support - -CUTLASS handles the complexity of sub-byte data types: - -```cpp -// FP4 element type -using ElementA = cutlass::float_e2m1_t; -using ElementB = cutlass::float_e2m1_t; - -// Block scale type -using ElementScale = cutlass::float_e4m3_t; - -// Layout with interleaved scales -// Every 16 FP4 elements -> 1 FP8 scale factor -// CUTLASS handles packing/unpacking automatically -``` - -### Epilogue Support - -SM100 epilogue visitors for fused operations: - -```cpp -// Standard epilogue: scale + bias + activation -using EpilogueOp = cutlass::epilogue::fusion::LinCombEltAct< - cutlass::epilogue::thread::SiLU, // Activation function - float, // Compute type - float, // Scale type - cutlass::half_t // Output type ->; - -// Custom visitor for dual GEMM fusion (gate-up pattern) -using EpilogueVisitor = cutlass::epilogue::fusion::DualGemmSiLU<...>; -``` - -## CUTLASS Collective Builder Pattern - -The builder pattern simplifies kernel configuration: - -```cpp -using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder< - cutlass::arch::Sm100, // Architecture - cutlass::arch::OpClassTensorOp, // Op class - ElementA, LayoutA, AlignmentA, // Operand A - ElementB, LayoutB, AlignmentB, // Operand B - ElementAccumulator, // Accumulator - TileShape_MxNxK, // Tile shape - ClusterShape, // Cluster shape - cutlass::gemm::collective::StageCountAutoCarveout<>, // Pipeline stages - KernelSchedule // Kernel schedule ->::CollectiveOp; -``` - -## Performance Data - -CUTLASS SM100 kernels achieve near-cuBLAS performance: -- BF16 GEMM: 98% of cuBLAS with persistent kernel + CLC -- FP8 GEMM: Competitive with DeepGEMM on standard shapes -- NVFP4 GEMM: Used as baseline in GPU Mode Hackathon -- MLA attention: Comparable to FlashMLA for decode workloads - -## Key Files in CUTLASS Repository - -| Path | Description | -|---|---| -| `include/cute/arch/mma_sm100*.hpp` | SM100 MMA atom definitions | -| `include/cute/atom/copy_sm100*.hpp` | SM100 TMA copy atoms | -| `include/cutlass/gemm/kernel/sm100_*.hpp` | SM100 kernel schedules | -| `include/cutlass/gemm/collective/sm100_*.hpp` | SM100 collective operations | -| `include/cutlass/epilogue/fusion/*.hpp` | Epilogue visitors | -| `examples/cute/blackwell/` | Blackwell GEMM examples | - -## Sources - -- [CUTLASS Changelog](https://docs.nvidia.com/cutlass/latest/CHANGELOG.html) -- [CUTLASS GitHub](https://github.com/NVIDIA/cutlass) -- [Colfax CUTLASS Blackwell GEMM Tutorial](https://research.colfax-intl.com/cutlass-tutorial-writing-gemm-kernels-using-tmem-for-nvidia-blackwell-gpus/) -- [Colfax Sub-Byte GEMM Tutorial](https://research.colfax-intl.com/cutlass-tutorial-sub-byte-gemm-on-nvidia-blackwell-gpus/) +- [CUTLASS v4.5.0 release](https://github.com/NVIDIA/cutlass/releases/tag/v4.5.0) +- [Pinned CuTe DSL tcgen05 package](https://github.com/NVIDIA/cutlass/tree/e406c186f510a15091cce01f782020ceb7ba8eb5/python/CuTeDSL/cutlass/cute/nvgpu/tcgen05) +- [Pinned TMEM helpers](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/python/CuTeDSL/cutlass/cute/arch/tmem.py) +- [Pinned progressive GEMM tutorial](https://github.com/NVIDIA/cutlass/tree/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/python/CuTeDSL/cute/blackwell/tutorial/tutorial_gemm) diff --git a/sources/docs/nvidia-ptx-isa-sm100.md b/sources/docs/nvidia-ptx-isa-sm100.md index ae8911300..be51264bf 100644 --- a/sources/docs/nvidia-ptx-isa-sm100.md +++ b/sources/docs/nvidia-ptx-isa-sm100.md @@ -1,233 +1,40 @@ --- id: doc-ptx-isa-sm100 -title: "PTX ISA SM100 Instructions Reference" -url: https://docs.nvidia.com/cuda/parallel-thread-execution/ +title: "PTX ISA 9.0 SM100 Instruction Reference" +url: https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html source_category: official-doc architectures: [sm100, sm100a] tags: [ptx, tcgen05, tmem, clc, tma, nvfp4, fp4, fp8, fp6, block-scale, mbarrier] -retrieved_at: 2026-04-16 +retrieved_at: 2026-08-08 --- -# PTX ISA SM100 Instructions Reference +# PTX ISA 9.0 SM100 Instruction Reference -## Overview +## Evidence Scope -PTX ISA 8.7+ introduces SM100-specific instructions for Blackwell's tensor core (tcgen05), tensor memory (TMEM), cluster launch control (CLC), and sub-byte data type conversions. This page summarizes the key new instructions relevant to kernel optimization. +This card routes KernelWiki claims to the archived CUDA 13.0.2 PTX ISA 9.0 reference. Exact grammar, target support, and ordering are version-sensitive; the rolling PTX URL must not substitute for this archive when a page claims PTX ISA 9.0 behavior. -## tcgen05.mma Instructions +## Relevant Normative Sections -### Syntax +- `tcgen05.mma`: unscaled, block-scaled, and integer operand grammar; CTA-group rules; descriptors; target restrictions; asynchronous completion. +- Tensor Memory: 128 lanes by 512 columns of 32-bit cells per SM, 32-bit addresses, allocation/deallocation, collective ld/st, cp, shift, and waits. +- `tcgen05.commit` and `tcgen05.fence`: asynchronous completion and cross-thread execution-ordering mechanisms with distinct roles. +- `clusterlaunchcontrol.try_cancel` and `query_cancel`: 16-byte shared response, mbarrier completion, success query, and first-CTA-coordinate decoding. +- `cp.async.bulk.tensor`: tensor-map loads/stores, CTA/cluster destinations, mbarrier or bulk-group completion, and `.multicast::cluster`. +- Packed `cvt`: E2M1, E3M2, E2M3, and FP8 conversion forms and their target notes. +- `mov` and `ld`: typed scalar/vector moves, vector load widths, cache operators, and eviction-priority hints. +- `mbarrier`: phase, arrival, transaction-count, wait, scope, and memory-ordering semantics. -```asm -tcgen05.mma.cta_group::{1|2}.kind::{dtype} - [tmem_addr], // Destination: TMEM address - [smem_desc_a], // Source A: SMEM descriptor - [smem_desc_b]; // Source B: SMEM descriptor -``` +## Scope Limits -### CTA Group Variants +The ISA defines legal behavior, not a universal performance ranking between instruction sequences, cache hints, vector widths, swizzles, or pipeline depths. A legal fragment is not a complete kernel: operand declarations, descriptors, collective participation, proxy visibility, lifetimes, completion waits, and target/toolchain selection still matter. -| cta_group | Description | Max M | -|---|---|---| -| `cta_group::1` | Single-CTA (1-SM) operation | 128 | -| `cta_group::2` | Cooperative 2-CTA (2-SM) operation | 256 | +## Direct Links -### Data Type Variants (kind) - -| kind | A type | B type | Accumulator | Shape (1-CTA) | -|---|---|---|---|---| -| `kind::f16` | FP16/BF16 | FP16/BF16 | FP32 | m128n256k16 | -| `kind::tf32` | TF32 | TF32 | FP32 | m128n256k8 | -| `kind::i8` | INT8 | INT8 | INT32 | m128n256k32 | -| `kind::f8f6f4` | FP8/FP6/FP4 | FP8/FP6/FP4 | FP32 | m128n256k32+ | -| `kind::mxf8` | MX FP8 | MX FP8 | FP32 | m128n256k32 | -| `kind::mxf4nvf4` | NVFP4 | NVFP4 | FP32 | m128n256k64 | - -### Key Differences from Hopper wgmma - -```asm -// Hopper (SM90): warpgroup scope, register accumulators -wgmma.mma_async.sync.aligned.m64n256k16.f32.bf16.bf16 - {d0..d127}, // 128 register accumulators - [desc_a], - [desc_b]; - -// Blackwell (SM100): single-thread, TMEM accumulators -tcgen05.mma.cta_group::1.kind::f16 - [tmem_addr], // TMEM accumulator (no register pressure) - [smem_desc_a], - [smem_desc_b]; -``` - -## TMEM Instructions - -### Allocation and Deallocation - -```asm -// Allocate TMEM rows for a CTA group -tcgen05.alloc.cta_group::1 [tmem_base], num_rows; - -// Deallocate TMEM rows -tcgen05.dealloc.cta_group::1 [tmem_base], num_rows; -``` - -### Load/Store (TMEM <-> Registers) - -```asm -// Load from TMEM to registers (for epilogue) -tcgen05.ld.16x256b [reg_dest], [tmem_src]; - -// Store from registers to TMEM -tcgen05.st.16x256b [tmem_dest], [reg_src]; -``` - -### TMEM Layout - -``` -TMEM per SM: 128 rows x 512 columns x 32-bit -Total: 128 * 512 * 4 bytes = 256 KB - -Row addressing: tmem_base + row_offset -Column mapping: determined by MMA instruction variant -``` - -## CLC Instructions - -### Dynamic Tile Scheduling - -```asm -// Signal tile arrival (producer done loading data) -clc.arrive.group::1; - -// Wait for tile assignment (consumer waits for work) -clc.wait.group::1; - -// CLC replaces manual tile queues: -// - Hardware maintains work queue -// - Tiles assigned to SMs as they become available -// - Eliminates tail effects and load imbalance -``` - -## TMA Instructions (SM100 Enhanced) - -### Async Bulk Copy - -```asm -// TMA load: global -> shared memory -cp.async.bulk.tensor.2d.dst_shared::cta.src_global.tile.mbarrier::complete_tx::bytes - [smem_addr], [tma_desc, {coord_x, coord_y}], [mbarrier]; - -// TMA store: shared memory -> global -cp.async.bulk.tensor.2d.dst_global.src_shared::cta.tile - [tma_desc, {coord_x, coord_y}], [smem_addr]; -``` - -### TMA Multicast - -```asm -// Multicast TMA load to multiple CTAs in cluster -cp.async.bulk.tensor.2d.dst_shared::cluster.src_global.tile.mbarrier::complete_tx::bytes - [smem_addr], [tma_desc, {coord_x, coord_y}], [mbarrier], multicast_mask; -``` - -### Alignment Requirements - -- TMA descriptors: 128-byte aligned base address -- Shared memory buffers: 128-byte aligned for TMA targets -- Global memory source: 128-byte aligned - -## FP4/FP8 Conversion Instructions - -### FP4 (E2M1) Conversions - -```asm -// Pack two FP16 values into FP4x2 -cvt.rn.e2m1x2.f16x2 %fp4_packed, %f16x2_val; - -// Unpack FP4x2 to two FP16 values -cvt.rn.f16x2.e2m1x2 %f16x2_result, %fp4_packed; -``` - -### Byte Unpacking for FP4 - -```asm -// Efficient byte unpacking (faster than bitwise extraction) -mov.b32 {tmp0, tmp1, tmp2, tmp3}, %packed_word; -// Splits 32-bit word into 4 bytes without shift/mask overhead -// Critical for FP4 decoding performance -``` - -### FP8 Conversions - -```asm -// FP8 E4M3 to FP16 -cvt.rn.f16.e4m3 %f16_result, %fp8_val; - -// FP16 to FP8 E4M3 -cvt.rn.e4m3.f16 %fp8_result, %f16_val; - -// FP8 E5M2 conversions (similar syntax) -cvt.rn.f16.e5m2 %f16_result, %fp8_val; -``` - -## Cache Control Instructions - -### Load Qualifiers (Critical for Memory-Bound Kernels) - -```asm -// Default: normal caching -ld.global %val, [addr]; - -// L1 no-allocate: bypass L1 for streaming data -ld.global.L1::no_allocate %val, [addr]; - -// L1 evict-last: keep in L1 as long as possible (for reused data) -ld.global.L1::evict_last %val, [addr]; - -// Non-coherent read-only (used by DeepEP for communication) -ld.global.nc.L1::no_allocate.L2::256B %val, [addr]; -``` - -### Vectorized Loads - -```asm -// 64-bit vector load -ld.global.v2.u32 {r0, r1}, [addr]; - -// 128-bit vector load -ld.global.v2.u64 {r0, r1}, [addr]; - -// 256-bit vector load -ld.global.v4.u64 {r0, r1, r2, r3}, [addr]; -``` - -## Synchronization Primitives - -### mbarrier (Memory Barrier) - -```asm -// Initialize mbarrier -mbarrier.init.shared.b64 [mbar], thread_count; - -// Arrive at mbarrier (producer signals completion) -mbarrier.arrive.shared.b64 %phase, [mbar]; - -// Wait on mbarrier (consumer waits for data) -mbarrier.try_wait.shared.b64 %pred, [mbar], %phase; -``` - -### Async Pipeline Coordination - -```asm -// TMA + mbarrier pipeline pattern: -// 1. Producer issues TMA load with mbarrier -// 2. Consumer waits on mbarrier -// 3. Consumer processes data while producer issues next load -// 4. Repeat for multi-stage pipeline -``` - -## Sources - -- [PTX ISA Reference](https://docs.nvidia.com/cuda/parallel-thread-execution/) -- [CUDA 13.0 Programming Guide](https://docs.nvidia.com/cuda/cuda-c-programming-guide/) -- [NVIDIA Blackwell Tuning Guide](https://docs.nvidia.com/cuda/blackwell-tuning-guide/) +- [PTX ISA 9.0 contents](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/contents.html) +- [`tcgen05.mma`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma) +- [Tensor Memory](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory) +- [`clusterlaunchcontrol.try_cancel`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel) +- [`cp.async.bulk.tensor`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor) +- [`cvt`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt) +- [`ld`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld) diff --git a/sources/docs/nvidia-transformer-engine-2.13-nvfp4.md b/sources/docs/nvidia-transformer-engine-2.13-nvfp4.md new file mode 100644 index 000000000..660119c55 --- /dev/null +++ b/sources/docs/nvidia-transformer-engine-2.13-nvfp4.md @@ -0,0 +1,26 @@ +--- +id: doc-transformer-engine-2.13-nvfp4 +title: "Transformer Engine 2.13: NVFP4" +url: https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html +source_category: official-doc +architectures: [sm100, sm100a] +tags: [nvfp4, fp4, block-scale] +retrieved_at: 2026-08-08 +version: "2.13" +--- + +# Transformer Engine 2.13 NVFP4 + +## Evidence-scoped summary + +- NVFP4 uses E2M1 payloads whose largest finite magnitude is 6. +- Its 1D recipe combines one E4M3 scale per 16 consecutive values with a per-tensor FP32 scale. +- Its weight-oriented 2D mode assigns a scale to each 16-by-16 block. +- Compared with MXFP4, the documented recipe uses a smaller group and a fractional rather than power-of-two local scale. +- The supported-hardware table associates training with compute capabilities 10.0 and 10.3 and inference with compute capability 10.0 and later. + +These format facts do not, by themselves, establish a universal accuracy or throughput advantage for a particular kernel or workload. + +## Primary reference + +- [Version-pinned Transformer Engine 2.13 NVFP4 documentation](https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html) diff --git a/sources/docs/tfla.md b/sources/docs/tfla.md index 01c71ac59..6be1c556f 100644 --- a/sources/docs/tfla.md +++ b/sources/docs/tfla.md @@ -1,19 +1,26 @@ --- id: doc-tfla -title: "Tiled Flash Linear Attention (TFLA)" -url: https://arxiv.org/abs/2503.14376 +title: Tiled Flash Linear Attention (TFLA) +url: https://arxiv.org/abs/2503.14376v3 source_category: paper -architectures: [sm100, sm90] -tags: [linear-attention, gated-delta-net, chunk-parallelism, tcgen05, wgmma] -retrieved_at: 2026-04-16 +architectures: +- sm90 +tags: +- linear-attention +- chunk-parallelism +- triton +retrieved_at: 2026-08-08 --- -## Summary +## Verified scope -Paper on Tiled Flash Linear Attention enabling arbitrarily large chunk sizes for linear attention. +Tiled Flash Linear Attention adds a second level of sequence parallelization within each chunk. The paper states that this enables arbitrarily large chunks, raises arithmetic intensity, and reduces the need to materialize intermediate recurrent states. -## Key Techniques -- Two levels of sequence parallelism: standard chunkwise + tiling within chunks -- Prevents materialization of intermediate memory states -- Matmuls emitted as inline PTX: WGMMA on Hopper, tcgen05 on Blackwell -- Improves arithmetic intensity for linear attention variants including GatedDeltaNet +The paper applies TFLA to mLSTM. Its official `NX-AI/mlstm_kernels` repository at commit `5b98ff8e2bec189b3d3c249405bab5149564d6f8` provides PyTorch, JAX, and Triton mLSTM implementations and reports H100 benchmarks. + +This source does not establish a Gated DeltaNet implementation, a Blackwell implementation, or inline WGMMA/tcgen05 assembly. Those claims are outside the cited paper and code revision. + +## Primary sources + +- [Paper revision 3](https://arxiv.org/abs/2503.14376v3) +- [Official code at `5b98ff8`](https://github.com/NX-AI/mlstm_kernels/tree/5b98ff8e2bec189b3d3c249405bab5149564d6f8) diff --git a/sources/docs/triton-3.3-blackwell.md b/sources/docs/triton-3.3-blackwell.md new file mode 100644 index 000000000..51dce77fc --- /dev/null +++ b/sources/docs/triton-3.3-blackwell.md @@ -0,0 +1,28 @@ +--- +id: doc-triton-3.3-blackwell +title: "Triton v3.3.0 — Blackwell TCGen5/TMEM Boundary" +url: https://github.com/triton-lang/triton/compare/v3.2.0...v3.3.0 +source_category: official-doc +architectures: [sm100, sm100a] +tags: [triton, tcgen05, tmem] +retrieved_at: 2026-08-08 +--- + +# Triton v3.3.0 — Blackwell TCGen5/TMEM Boundary + +## Exact comparison + +The checked boundary is Triton v3.2.0 (`9641643da6c52000c807b5eeed05edaec4402a67`) to v3.3.0 (`819e9c8c29ad2ae96cbd93a1d3b8a3a0f4c8f09c`). The corresponding TCGen5 MMA, TMEM, and MMAv5-lowering symbols are absent from the v3.2.0 tree. The v3.3.0 tree adds: + +- `TTNG_TCGen5MMAOp` and `TTNG_TCGen5MMAScaledOp`; +- TMEM allocation, load, store, and copy operations; +- MMAv5 lowering and tensor-memory allocation passes; and +- Blackwell conversion tests that require concrete `tcgen05.mma`, commit, TMEM, scaled-MMA, and `cta_group::2` output. + +The pinned positive control is [`test/Conversion/tritongpu_to_llvm_blackwell.mlir`](https://github.com/triton-lang/triton/blob/819e9c8c29ad2ae96cbd93a1d3b8a3a0f4c8f09c/test/Conversion/tritongpu_to_llvm_blackwell.mlir). The operation definitions are in [`TritonNvidiaGPUOps.td`](https://github.com/triton-lang/triton/blob/819e9c8c29ad2ae96cbd93a1d3b8a3a0f4c8f09c/include/triton/Dialect/TritonNvidiaGPU/IR/TritonNvidiaGPUOps.td). + +## Scope + +This tag comparison establishes that native Blackwell TCGen5/TMEM compiler support enters between v3.2.0 and v3.3.0. It does not establish that every user-level `tl.dot` shape selects that path, or that every later frontend surface was already mature in v3.3.0. + +Later releases extend the surface: v3.5.0 includes explicit Gluon TCGen5/TMEM and block-scaled matmul tutorials; v3.6.0 generalizes layouts and copies and advances warp-specialized and initial multi-CTA Gluon support; v3.7.0 continues 2-CTA, multicast, and TMA work. v3.7.1 is a regression-fix patch with no new API or feature. diff --git a/sources/docs/triton-3.6-blackwell.md b/sources/docs/triton-3.6-blackwell.md index 33b306e34..6b6a23593 100644 --- a/sources/docs/triton-3.6-blackwell.md +++ b/sources/docs/triton-3.6-blackwell.md @@ -1,56 +1,29 @@ --- id: doc-triton-3.6-blackwell -title: "Triton 3.6.0 Release Notes — Blackwell (SM100) Lowering" +title: "Triton v3.6.0 — Incremental Blackwell Changes" url: https://github.com/triton-lang/triton/releases/tag/v3.6.0 source_category: official-doc architectures: [sm100, sm100a] -tags: [triton, tcgen05, tmem, 2sm-cooperative, block-scale, nvfp4, warp-specialization] -retrieved_at: 2026-04-27 +tags: [triton, tcgen05, tmem, 2sm-cooperative, block-scale, warp-specialization] +retrieved_at: 2026-08-08 --- -# Triton 3.6.0 Release Notes — Blackwell Lowering +# Triton v3.6.0 — Incremental Blackwell Changes -## Overview +Triton v3.6.0 was released on 2026-01-21 at commit `7c56a5e40f7fd928dfd5c72902d5def0097db73a`. It is not the first release with a native Blackwell backend: the pinned v3.2.0-to-v3.3.0 comparison in [`doc-triton-3.3-blackwell`](triton-3.3-blackwell.md) establishes the earlier TCGen5/TMEM boundary. -Triton 3.6.0 (released `2026-01-21`, release commit `7c56a5e`) is the first Triton release with native NVIDIA Blackwell (SM100) lowering through `tcgen05.mma` plus tensor-memory (TMEM) accumulators. Prior to 3.6, the Triton compiler on Blackwell silently fell back to the Hopper `wgmma` path with register-resident accumulators, which is the framing recorded in the older `wiki/languages/triton-blackwell.md` page. +## Blackwell-relevant changes in v3.6.0 -This doc page summarizes only the SM100-relevant items from the 3.6.0 release notes; per-pathway breakdown with verified-vs-needs-verification classification lives in `data/triton-3.6-evidence.md`. +The release notes describe incremental work including: -## Blackwell-Relevant Items in the 3.6.0 Release Notes +- generic `tcgen05` copy support and broader TMEM bit-width and layout handling; +- more general `tcgen05` load/store layouts and MMA lowering; +- additional aref-style warp-specialization plumbing; +- initial Gluon multi-CTA and 2-CTA support, including `num_ctas`-related cluster work; and +- Gluon scaled-MMA and `tl.dot_scaled` fixes. -### Tensor Memory (TMEM) infrastructure +These changes extend a backend already present in v3.3.0. The word “initial” matters for the multi-CTA path: the v3.7.0 release subsequently adds more end-to-end 2-CTA, multicast, and TMA work. v3.7.1, published 2026-06-18 at commit `f797708`, fixes two regressions and advertises no new API or feature. -The release adds TMEM allocation, copy, and layout primitives that the Blackwell backend lowers through `ttng.tmem_alloc`, `ttng.tmem_copy`, `ttng.tmem_load`, and `ttng.tmem_store`. Source PRs: `#8136`, `#8148`, `#8202`. After 3.6, accumulators on SM100 may live in TMEM rather than registers — the older blanket "accumulators stay in registers" claim is no longer correct as a universal statement. +## Evidence boundary -### `tcgen05` lowering - -Generic `tcgen05` load/store/copy lowering and `tcgen05.mma` generalization land via `#8225`, `#8421`, `#8495`, `#8102`, `#8338`, `#8386`. The dialect now exposes `ttng.tc_gen5_mma` and `ttng.tc_gen5_mma_scaled` with TMEM-token semantics. - -### Warp specialization end-to-end - -End-to-end aref-style warp specialization plumbing on the Blackwell path: `#8262`, `#7826`, `#8009`, `#8123`, `#8534`, `#8451`, `#8651`. The strongest user-visible surface is `tl.range(..., warp_specialize=True)` on top of descriptor / TMA matmul kernels, as documented in the Triton persistent matmul tutorial. - -### Gluon front-end and 2-CTA support - -Initial 2-CTA cluster support in the Gluon front-end (`#8644`, `#8653`), `num_ctas` plumbing (`#8645`), and Gluon-side `tcgen05 mma scaled` support (`#8393`). The Gluon path is the most explicit Blackwell-native surface; the release notes describe it as initial support. - -### Block-scaled matmul (NVFP4 / MXFP) - -Hardware-accelerated block-scaled matmul on Blackwell tensor cores via `tl.dot_scaled`. Backend exposes `ttng.tc_gen5_mma_scaled` (`#8393`); frontend fixes `#8564`, `#8658`. Format coverage centers on NVFP4 / MXFP per the official block-scaled matmul tutorial. - -## Predecessor Release for Context - -Triton 3.5.1 (released `2025-11-12`) is the last 3.5.x patch before the 3.6 Blackwell story. Pages with `version_sensitive` claims valid for `>=3.5,<3.6` should pin to 3.5.1. - -## Subsequent 3.6.x Patches - -As of `2026-04-27`, no 3.6.x patch release is visible on the official triton-lang/triton GitHub releases page; the next previous release shown there is 3.5.1. (`needs-verification` if this requires a machine-checked negative claim.) - -## When To Cite This Page - -Pages making claims about Triton's SM100 capabilities should add a `version_sensitive` block whose registry entry pins `last_verified_release: "3.6.0"` and lists `doc-triton-3.6-blackwell` (this page) as one of its `source_ids`. The companion downstream-code anchors are `pr-sglang-5390`, `pr-sglang-21595`, and `pr-pytorch-175826` — see `data/triton-3.6-evidence.md` for the per-pathway breakdown plus caveat anchors. - -## Caveats - -- The 3.6 release introduces native Blackwell lowering paths but does not by itself prove that every plain `tl.dot` matmul on SM100 lowers through TMEM-backed `tcgen05`. The strongest checked path is descriptor/TMA + `tl.range(warp_specialize=True)` + `tl.dot`, plus the Gluon multi-CTA / 2CTA path. -- Production-peak performance on Blackwell still favors hand-written CuTe-DSL / CUTLASS / FA-4 / TRT-LLM kernels for many compute-bound workloads. SGLang `pr-sglang-5390` reports a CUTLASS `tcgen05_mla` backend ~27% faster than the Triton MLA decode baseline; SGLang `pr-sglang-21595` changes Blackwell datacenter multimodal attention default away from `triton_attn` to FA4. A "first-class lane" framing for Triton on Blackwell is justified for supported lowering surfaces, but not as a blanket peak-performance equivalence claim. +The release notes and pinned compiler tests prove that Triton contains native TCGen5/TMEM paths. They do not prove that every plain `tl.dot` shape selects one, nor that a downstream kernel containing `tl.dot` emitted a particular PTX instruction. Such a claim requires target- and configuration-specific IR or PTX evidence. diff --git a/sources/prs/cccl/PR-3559.md b/sources/prs/cccl/PR-3559.md index 1f295fe4f..aa5ce71ca 100644 --- a/sources/prs/cccl/PR-3559.md +++ b/sources/prs/cccl/PR-3559.md @@ -10,10 +10,12 @@ source_category: upstream-code architectures: - sm100 tags: -- gemm -techniques: [] +- parallel-scan +techniques: +- parallel-scan hardware_features: [] -kernel_types: [] +kernel_types: +- scan languages: - cuda-cpp captured_at: '2026-05-20' @@ -46,4 +48,3 @@ Add b200 tunings for scan.exclusive.sum - `thrust/testing/scan.cu` - `thrust/thrust/system/cuda/detail/async/inclusive_scan.h` - `thrust/thrust/system/cuda/detail/scan.h` - diff --git a/sources/prs/cccl/PR-6152.md b/sources/prs/cccl/PR-6152.md index 7dbec0a84..f70a4e5e7 100644 --- a/sources/prs/cccl/PR-6152.md +++ b/sources/prs/cccl/PR-6152.md @@ -7,13 +7,14 @@ author: oleksandr-pavlyk date: '2025-10-08' url: https://github.com/NVIDIA/cccl/pull/6152 source_category: upstream-code -architectures: -- sm100 +architectures: [] tags: -- gemm -techniques: [] +- top-k-selection +techniques: +- top-k-selection hardware_features: [] -kernel_types: [] +kernel_types: +- topk languages: - cuda-cpp captured_at: '2026-05-20' @@ -49,4 +50,3 @@ Fix debug section around line 390 of dispatch_topk ## Changed Files - `cub/cub/device/dispatch/dispatch_topk.cuh` - diff --git a/sources/prs/cutlass/PR-2139.md b/sources/prs/cutlass/PR-2139.md index e29f88006..4358e3292 100644 --- a/sources/prs/cutlass/PR-2139.md +++ b/sources/prs/cutlass/PR-2139.md @@ -22,7 +22,6 @@ hardware_features: - tcgen05 - tmem - block-scale -- nvfp4 - fp8 kernel_types: - gemm @@ -72,7 +71,7 @@ Introduces blockwise and groupwise GEMM implementations targeting the Blackwell ## Problem -CUTLASS lacked native blockwise and groupwise scaled GEMM kernels for the Blackwell SM100 architecture. Quantized inference workloads using FP8 and FP4 block-scaled formats on Blackwell required new warp-specialized collective mainloop implementations that leverage SM100-specific hardware features such as TCGen05 MMA instructions and TMEM for accumulator management. +CUTLASS lacked blockwise and groupwise FP8 GEMM kernels for the Blackwell SM100 architecture. These workloads required warp-specialized collective mainloop implementations that use SM100-specific infrastructure such as TCGen05 MMA instructions and TMEM accumulator management. ## Solution / Techniques @@ -110,4 +109,4 @@ using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder ## Performance -The PR adds profiling infrastructure with warmup iterations to Hopper FP8 GEMM examples. The Blackwell blockwise GEMM kernels leverage TCGen05 instructions and TMEM-based accumulator double buffering for high throughput on SM100. Specific performance numbers were not included in the PR but these kernels are foundational for CUTLASS 3.8's Blackwell support. +The PR adds profiling infrastructure with warmup iterations to Hopper FP8 GEMM examples. Its Blackwell examples also use FP8 E4M3 operands. Specific performance numbers were not included in the PR. The patch does not add an NVFP4/E2M1 example, so it is not direct evidence for an NVFP4 implementation. diff --git a/sources/prs/cutlass/PR-2161.md b/sources/prs/cutlass/PR-2161.md index b693d9d54..bfb8ede86 100644 --- a/sources/prs/cutlass/PR-2161.md +++ b/sources/prs/cutlass/PR-2161.md @@ -38,7 +38,7 @@ artifact_dir: artifacts/prs/cutlass/PR-2161 ## Summary -Enables Programmatic Dependent Launch (PDL) via Grid Dependency Control (GDC) for SM100 Blackwell kernels, and fixes potential out-of-bounds memory access in blockwise/groupwise scaling copy operations. The PDL feature allows back-to-back kernel launches with hardware-managed dependencies, reducing launch overhead for persistent GEMM kernels. +Enables a Programmatic Dependent Launch (PDL) path via Grid Dependency Control (GDC) for eligible SM100 Blackwell kernels, and fixes potential out-of-bounds memory access in blockwise/groupwise scaling copy operations. PDL can make a same-stream dependent grid eligible to launch before its prerequisite grid finishes; actual overlap and performance remain workload- and resource-dependent. ## Problem @@ -46,7 +46,7 @@ Two issues were addressed: 1. **Security/correctness**: The blockwise/groupwise scaling kernels used hardcoded copy sizes for scale factor arrays (SFA and SFB), which could lead to out-of-bounds memory access when tile dimensions did not match the hardcoded values. -2. **Performance**: SM100 Blackwell architecture supports Grid Dependency Control for programmatic dependent launch, but CUTLASS had not yet enabled this feature. Without GDC, back-to-back kernel launches on Blackwell could not overlap grid scheduling, leaving performance on the table for multi-kernel workloads. +2. **Enablement**: SM100 Blackwell supports Grid Dependency Control, but this CUTLASS path had not enabled the feature. The change adds the compile-time path needed for eligible CUTLASS kernels to use GDC; CUDA's launch attribute and device-side dependency protocol still govern a PDL launch. ## Solution / Techniques @@ -81,6 +81,6 @@ static constexpr int ElementsPerSFACopy = ...; // derived from CTA tile static constexpr int ElementsPerSFBCopy = ...; // derived from CTA tile ``` -## Performance +## Performance scope -PDL/GDC reduces kernel launch latency by allowing the GPU to overlap scheduling of dependent kernel grids. This is particularly beneficial for persistent GEMM kernels that use CLC-based tile scheduling on Blackwell, where back-to-back launches (e.g., GEMM followed by epilogue-fusion or another GEMM) can overlap without CPU synchronization. Performance improvements were validated through the CUTLASS gemm. +The change creates an opportunity to overlap part of a prerequisite grid with an independent preamble in its dependent grid. Neither the PR record nor the captured artifact supplies a reproducible device/shape/baseline/result tuple, so this source does not establish a numeric or general speedup. Measure the exact launch pair and verify the overlap timeline on the target GPU. diff --git a/sources/prs/flash-attention/PR-2441.md b/sources/prs/flash-attention/PR-2441.md index 2f2162b60..c86d6a7e7 100644 --- a/sources/prs/flash-attention/PR-2441.md +++ b/sources/prs/flash-attention/PR-2441.md @@ -26,6 +26,7 @@ status: merged merge_sha: f219c89c inclusion_reason: kernel file changes changed_paths: +- .pre-commit-config.yaml - benchmarks/benchmark_attn.py - flash_attn/cute/bench_utils.py - flash_attn/cute/cute_dsl_utils.py @@ -36,35 +37,31 @@ changed_paths: - flash_attn/cute/softmax.py - flash_attn/cute/testing.py - flash_attn/cute/tile_scheduler.py +- flash_attn/cute/topk_gather_kv.py +- tests/cute/test_flash_attn.py artifact_dir: artifacts/prs/flash-attention/PR-2441 --- -## Summary +## Evidence Scope -Initial saturating decode perf numbers, deepseek 64/512 shape and topk length = 2048. -``` -Vanilla MLA -batch: 512, seqlen_q: 1, seqlen_k: 16384, nheads: 128, -> 1.98 ms, 1180.70 TFLOPS -DSA, no bitmask (topk selected assumed in bounds) -batch: 512, seqlen_q: 1, seqlen_k: 16384, nheads: 128, -> 0.3 +PR 2441 introduces the SM100 CuTe DSL MLA 64/512 forward path with caller-provided top-k sparsity for MQA with 128 query heads per KV head. It merged as `f219c89c886c6ccbf9d3dbd9fe41b11ac64e9df8`; the local artifact bundle contains the upstream patch and byte-verified key files from that merge. -## Problem +## Author-Reported Initial Decode Results -[Cute,Sm100,Fwd] add MLA 64/512 with topk sparsity for MQA 128 heads +The PR body labels these as initial saturating decode results with top-k length 2048: -## Changed Files +| Variant | batch | seqlen_q | seqlen_k | nheads | latency | TFLOPS | +|---|---:|---:|---:|---:|---:|---:| +| Vanilla MLA | 512 | 1 | 16384 | 128 | 1.98 ms | 1180.70 | +| DSA, no bitmask; selected indices assumed in bounds | 512 | 1 | 16384 | 128 | 0.31 ms | 955.47 | +| DSA, validity bitmask | 512 | 1 | 16384 | 128 | 0.33 ms | 898.08 | + +The PR body does not state the exact GPU model, dtype, clock/power settings, software versions, timing protocol, sample count, or variance for these rows. They are source-reported observations, not a complete reproducibility record. + +## Implemented and Excluded Scope -- `.pre-commit-config.yaml` -- `benchmarks/benchmark_attn.py` -- `flash_attn/cute/bench_utils.py` -- `flash_attn/cute/cute_dsl_utils.py` -- `flash_attn/cute/flash_fwd_mla_sm100.py` -- `flash_attn/cute/interface.py` -- `flash_attn/cute/mask.py` -- `flash_attn/cute/named_barrier.py` -- `flash_attn/cute/softmax.py` -- `flash_attn/cute/testing.py` -- `flash_attn/cute/tile_scheduler.py` -- `flash_attn/cute/topk_gather_kv.py` -- `tests/cute/test_flash_attn.py` +The PR says it added the interface exposure and tests and addressed a causal `seqlen_q > seqlen_k` hang. It also says the tcgen05 MMA code generation still needed performance revision. Page-table and sliding-window support were not planned in this PR; the merged MLA kernel rejects a non-null page table. + +## Changed Files +The patch adds `flash_fwd_mla_sm100.py` and `topk_gather_kv.py`, updates the benchmark/interface/mask/softmax/testing/scheduler support files, adds tests, and adjusts the pre-commit configuration. The frontmatter `changed_paths` list is aligned with the captured patch headers. diff --git a/sources/prs/flashinfer/PR-2387.md b/sources/prs/flashinfer/PR-2387.md index 7a9bf0568..b772901fd 100644 --- a/sources/prs/flashinfer/PR-2387.md +++ b/sources/prs/flashinfer/PR-2387.md @@ -10,7 +10,6 @@ source_category: upstream-code architectures: - sm100 tags: -- tcgen05 - decode techniques: - warp-specialization @@ -18,9 +17,7 @@ techniques: - double-buffering hardware_features: - tma -- tmem - mbarrier -- tcgen05 kernel_types: - fused-kernel - decode @@ -29,47 +26,31 @@ languages: - python captured_at: 2026-04-16 status: merged -merge_sha: 18804cd5 +merge_sha: 18804cd51734cccf807356d017733bc757677f15 inclusion_reason: manually curated, Blackwell kernel relevance changed_paths: - include/flashinfer/mamba/selective_state_update.cuh artifact_dir: artifacts/prs/flashinfer/PR-2387 --- -## Summary +# FlashInfer PR 2387 -Introduces a Blackwell (SM100+) optimized version of the Mamba selective_state_update kernel using a horizontal producer-consumer pattern. The kernel replaces the vertical warp-level reduction used on Hopper with a sequential per-thread processing approach that eliminates the warp reduction bottleneck on Blackwell, achieving substantial throughput improvements on B200. +## Verified scope -## Problem +The PR was merged as commit `18804cd51734cccf807356d017733bc757677f15`. Its captured `selective_state_update.cuh` byte-matches that merge revision (SHA-256 `40a2de44b1f29b4b4c213e74e530131c9a43be5e602daa3c8bbd901a3b281446`). The captured patch has SHA-256 `d484b94d986f9c3345cbd89c7d0179f57c0334614b9a517660f173bf6d6762f5`. -The existing Mamba selective_state_update kernel used a vertical producer-consumer pattern where each warp processes a row with warp-level reduction via shuffle intrinsics. On Blackwell hardware, the warp-level reduction became a bottleneck, preventing the kernel from achieving peak attention. A fundamentally different computational pattern was needed for SM100. +The merged source provides two directly inspectable staged shared-memory designs: -## Solution / Techniques +- `SharedStorage` and `SharedStorageHorizontal` allocate `state[numStages][...]` plus one `bar_empty` and one `bar_full` per stage. +- Producers wait for an empty stage before TMA or ordinary-copy production, attach transaction bytes to the full barrier for TMA, and publish the stage. +- Consumers wait for the corresponding full stage, process it, and arrive on the empty barrier before producer reuse. +- Dispatch uses three stages in one path and `min(totalStages, 4)` in the horizontal path. These are implementation choices, not universal stage-count rules. -- **Horizontal producer-consumer pattern**: individual threads sequentially process multiple row elements while maintaining running sums, eliminating warp-level reduction -- New `SharedStorageHorizontal` struct for multi-stage buffering -- Per-stage synchronization barriers with `mbarrier` support -- TMA alignment validation for efficient data loading -- Bank-conflict-free shared memory indexing via `conflict_free_column()` function -- Dynamic dispatch: SM100+ uses horizontal kernel, SM90 uses vertical kernel, older GPUs use base kernel -- JIT compilation specs supporting NVCC versions 10-12 for SM100 +This source card does not preserve enough benchmark metadata to substantiate a portable performance number or a Hopper-versus-Blackwell comparison. Use the pull request discussion for author-reported charts and the pinned file for code semantics. -## Key Code +## Evidence routes -```cuda -// Horizontal producer-consumer pattern for SM100+ -// Eliminates warp-level reduction bottleneck -__device__ void consumer_func_horizontal(...) { - // Each thread processes multiple elements sequentially - // with running sums instead of warp shuffle reduction - for (int elem = 0; elem < elements_per_thread; elem++) { - // Bank-conflict-free shared memory access - int col = conflict_free_column(elem, threadIdx.x); - running_sum += smem[stage][col]; - } -} -``` - -## Performance - -Performance graphs demonstrate substantial throughput improvements on B200 (Blackwell) across varying batch sizes. The horizontal kernel explicitly underperforms on H200 (Hopper) compared to the vertical variant, confirming the architecture-specific optimization. Dynamic dispatch ensures each architecture uses its optimal kernel variant. +- [Merged pull request](https://github.com/flashinfer-ai/flashinfer/pull/2387) +- [Pinned merged source](https://github.com/flashinfer-ai/flashinfer/blob/18804cd51734cccf807356d017733bc757677f15/include/flashinfer/mamba/selective_state_update.cuh) +- `artifacts/prs/flashinfer/PR-2387/key-files/include/flashinfer/mamba/selective_state_update.cuh` +- `artifacts/prs/flashinfer/PR-2387/diff.patch` diff --git a/sources/prs/vllm/PR-16032.md b/sources/prs/vllm/PR-16032.md index 51c9fc9d6..cd6739819 100644 --- a/sources/prs/vllm/PR-16032.md +++ b/sources/prs/vllm/PR-16032.md @@ -10,12 +10,9 @@ source_category: upstream-code architectures: - sm100 tags: -- tcgen05 - mla -- moe - attention techniques: -- warp-specialization - persistent-kernel hardware_features: - tcgen05 @@ -25,13 +22,12 @@ kernel_types: - mla - attention - decode -- moe languages: - cuda-cpp - python captured_at: 2026-04-16 status: merged -merge_sha: ed7a29d9 +merge_sha: ed7a29d9f8b48978e3bbf43599d21b4de65387e0 inclusion_reason: manually curated, Blackwell kernel relevance changed_paths: - csrc/attention/mla/cutlass_mla_entry.cu @@ -43,40 +39,26 @@ changed_paths: artifact_dir: artifacts/prs/vllm/PR-16032 --- -## Summary - -Integrates NVIDIA's CUTLASS MLA (Multi-Head Latent Attention) decode kernel for Blackwell GPUs into vLLM. Exposes the kernel as `ops.tcgen05_mla_decode` with support for separate query tensor inputs and configurable softmax scaling, targeting efficient DeepSeek model inference on SM100 hardware. +# vLLM PR 16032 -## Problem +## Verified scope -vLLM lacked a native high-performance MLA decode kernel for Blackwell GPUs. The MLA attention mechanism used by DeepSeek models requires specialized kernel support to efficiently handle the latent key-value projection and multi-head attention computation. Without SM100-optimized kernels, Blackwell GPU capabilities were underutilized for DeepSeek inference. +The PR was merged as `ed7a29d9f8b48978e3bbf43599d21b4de65387e0`. The captured patch and six key files record the merged integration. -## Solution / Techniques +- `cutlass_mla_decode` is declared in `csrc/ops.h`, registered in `csrc/torch_bindings.cpp`, and wrapped by `vllm/_custom_ops.py`. +- The entry point accepts an output tensor, separate `q_nope` and `q_pe` tensors, a combined KV cache, sequence lengths, a page table, and a scale. +- When `ENABLE_CUTLASS_MLA` is enabled, the entry dispatches to `cutlass_mla_decode_sm100a`; otherwise it reports that no CUTLASS MLA implementation was compiled. +- The SM100a implementation validates concrete tensor ranks and dimensions, builds CUTLASS FMHA arguments, lets the implementation select split-KV policy, calls `can_implement`, initializes workspace, and runs on the current CUDA stream. +- The PR also changes the NVFP4 scaled-GEMM wrapper. Its `CollectiveBuilder` epilogue is a separately inspectable SM100 CUTLASS example; it is not evidence that the MLA path uses a particular user-visible epilogue schedule. -- New CUDA kernel in `csrc/attention/mla/tcgen05_mla_kernels.cu` wrapping CUTLASS library primitives -- Python bindings in `vllm/_custom_ops.py` exposing `tcgen05_mla_decode` -- Supports separate q_nope and q_pe query tensor inputs to avoid memory copies -- Configurable softmax scaling parameters passed from Python layer -- Template-based CUDA kernel design for flexibility -- Based on CUTLASS v3.9 MLA examples from NVIDIA's repository +The captured material does not preserve a benchmark protocol or rows sufficient for a portable speedup claim or a recommended-default-backend claim. -## Key Code +## Artifact checks -```cpp -// CUTLASS MLA decode kernel for Blackwell (SM100) -// Wraps tcgen05 MLA primitives with vLLM-specific interface -// Supports split query tensors: q_nope (no positional encoding) -// and q_pe (with positional encoding) -void tcgen05_mla_decode( - torch::Tensor& out, - torch::Tensor& q_nope, - torch::Tensor& q_pe, - torch::Tensor& kv_cache, - float softmax_scale, - ... -); -``` +`artifacts/prs/vllm/PR-16032/PROVENANCE.yaml` records SHA-256 for the patch and all six files. The captured `nvfp4_scaled_mm_kernels.cu` also appears under `artifacts/kernels/epilogue-fusion/full/` and byte-matches the raw file at the full merge SHA (`e8aed5ccb3dd9de26c3aeff159a242a46dcb7c7d8d0351b6c44ff1f8d2f7effa`). -## Performance +## References -Enables hardware-accelerated MLA decode on Blackwell GPUs leveraging SM100 tensor cores (tcgen05) and tensor memory (tmem). Performance validated with DeepSeek models showing significant speedup over software-emulated MLA attention paths. The CUTLASS MLA kernel is the recommended default backend for SM100 devices. +- [Merged pull request](https://github.com/vllm-project/vllm/pull/16032) +- [Pinned MLA entry](https://github.com/vllm-project/vllm/blob/ed7a29d9f8b48978e3bbf43599d21b4de65387e0/csrc/attention/mla/cutlass_mla_entry.cu) +- [Pinned MLA kernel wrapper](https://github.com/vllm-project/vllm/blob/ed7a29d9f8b48978e3bbf43599d21b4de65387e0/csrc/attention/mla/cutlass_mla_kernels.cu) diff --git a/sources/prs/vllm/PR-23696.md b/sources/prs/vllm/PR-23696.md index 56dc2bec5..b2e3e1ab5 100644 --- a/sources/prs/vllm/PR-23696.md +++ b/sources/prs/vllm/PR-23696.md @@ -2,7 +2,7 @@ id: pr-vllm-23696 repo: vllm-project/vllm pr: 23696 -title: '[Kernel][tcgen05] nvfp4 fused tcgen05 moe' +title: '[Kernel][B200] mxfp4 fused cutlass moe' author: djmmoss date: 2025-09-11 url: https://github.com/vllm-project/vllm/pull/23696 @@ -11,20 +11,18 @@ architectures: - sm90 - sm100 tags: -- tcgen05 -- nvfp4 +- fp4 +- fp8 - moe - fused-kernel +- block-scale techniques: - kernel-fusion - fine-grained-quantization hardware_features: -- nvfp4 - fp4 - fp8 - block-scale -- tma -- tcgen05 kernel_types: - moe - grouped-gemm @@ -34,48 +32,56 @@ languages: - python captured_at: 2026-04-16 status: merged -merge_sha: 074854b2 +merge_sha: 074854b24f6e0b1e237a004283e1f46d98c0d73c inclusion_reason: manually curated, Blackwell kernel relevance changed_paths: +- tests/kernels/moe/test_mxfp4_moe.py +- vllm/envs.py +- vllm/model_executor/layers/fused_moe/layer.py +- vllm/model_executor/layers/quantization/mxfp4.py - vllm/model_executor/warmup/kernel_warmup.py artifact_dir: artifacts/prs/vllm/PR-23696 --- -## Summary +## Scope + +Merged vLLM PR 23696 adds a FlashInfer CUTLASS fused-expert backend for GPT-OSS **MXFP4 weights**. The PR author describes two activation paths: + +- Hopper (SM90): BF16 activations times MXFP4 weights. +- Blackwell (SM100): MXFP8 activations times MXFP4 weights. + +The change is adjacent to, but not evidence for, the FlashInfer MLSys 2026 FP8 E4M3 block-scale Track A definition. + +## Dataflow Boundary + +vLLM computes or receives top-k expert IDs and routing weights before invoking `flashinfer_cutlass_fused_moe`. The backend call consumes those selections together with expert weights, quantization scales, optional biases, and SwiGLU parameters. It fuses expert computation; the PR does not establish that router-logit computation is inside the same kernel. -Implements CUTLASS-based fused Mixture-of-Experts (MoE) kernels optimized for MXFP4 quantization on both Hopper (SM90) and Blackwell (SM100) architectures. Supports bf16xnvfp4 on Hopper and mxfp8xnvfp4 on Blackwell, with environment variable control for backend selection between CUTLASS and TRT-LLM implementations. +The PR adds two environment-controlled backend choices in `vllm/envs.py`: -## Problem +- `VLLM_USE_FLASHINFER_MOE_MXFP4_BF16` +- `VLLM_USE_FLASHINFER_MOE_MXFP4_MXFP8` -Large MoE models like GPT-OSS-120B require highly efficient expert computation kernels. The existing MoE backends did not support MXFP4 (microscaling FP4) quantization with CUTLASS, leaving performance on the table especially on Blackwell where native FP4 hardware support is available. A fused kernel combining expert routing with MXFP4 GEMM was needed. +The merged aggregate diff changes five files, listed in frontmatter. The local artifact stores that aggregate diff plus one byte-verified representative key file, `kernel_warmup.py`. -## Solution / Techniques +## Tests Reported in the PR -- CUTLASS fused MoE kernels for MXFP4 quantization across Hopper and Blackwell -- bf16xnvfp4 variant for Hopper (SM90), mxfp8xnvfp4 variant for Blackwell (SM100) -- Environment variables `VLLM_USE_FLASHINFER_MOE_MXFP4_MXFP8` and `VLLM_USE_FLASHINFER_MOE_MXFP4_MXFP8_CUTLASS` for backend selection -- Custom weight quantization handling across different backend implementations -- Kernel fusion of expert routing and GEMM computation +The author reports: -## Key Code +- Hopper unit test: 8 passed, 59 skipped. +- Blackwell unit test: 56 passed, 11 skipped. +- GPT-OSS GPQA results of approximately 0.5612 for 20B and 0.6660 for 120B on the Blackwell path. -```python -# Backend selection for MXFP4 MoE -# CUTLASS backend takes precedence when enabled -VLLM_USE_FLASHINFER_MOE_MXFP4_MXFP8_CUTLASS=1 # Enable CUTLASS MoE -# Blackwell: mxfp8 activations x nvfp4 weights -# Hopper: bf16 activations x nvfp4 weights -``` +These are PR-author reports; KernelWiki did not reproduce them. -## Performance +## Performance Reported in the PR -Benchmarked on gpt-oss-120b: +For Blackwell serving with random 1024-input/1024-output requests, the author reports that the CUTLASS backend is slower than TRT-LLM at low concurrency and becomes faster only at high concurrency. The 120B table records 16,221 versus 15,592 output tokens/s at concurrency 1024 (4.0% in the table) and 16,424 versus 15,369 at concurrency 1152 (6.9%). The 20B table records 24,629 versus 23,195 at concurrency 1024 (5.8%). -**Blackwell (tcgen05):** -- At 1024 concurrency: CUTLASS achieves 4.0% improvement over TRT-LLM (16,221 vs 15,592 output tok/s) -- At high concurrency: approximately 7% throughput advantage for CUTLASS over TRT-LLM +For Hopper ShareGPT serving, the PR's Triton comparison is faster than the FlashInfer path in the shown runs. These serving measurements are not interchangeable with isolated MoE-kernel TFLOPS or latency. -**Hopper:** -- Triton backend outperforms CUTLASS by approximately 27% at medium-high concurrency on Hopper +## Evidence Boundary -Accuracy validated on gpt-oss-20b (~0.57) and gpt-oss-120b (~0.66). +- Exact primary revision: merge `074854b24f6e0b1e237a004283e1f46d98c0d73c`. +- The local aggregate patch has SHA-256 `033d30b15af4f2050189c2e76ba61959e1e5d4bd049dc901fd56f68890b891a0`. +- The captured `kernel_warmup.py` is byte-identical to the file at the merge revision, SHA-256 `d38c2dd5e9be60f22849f4c3e455746fa5a09f669f995bf75e9a4c4c35e5cb51`. +- The PR does not use the former local title `nvfp4 fused tcgen05 moe`, does not change only `kernel_warmup.py`, and does not provide the FP8 Track A benchmark table. diff --git a/sources/prs/vllm/PR-34597.md b/sources/prs/vllm/PR-34597.md index eb8519b40..8be4206f8 100644 --- a/sources/prs/vllm/PR-34597.md +++ b/sources/prs/vllm/PR-34597.md @@ -8,7 +8,7 @@ date: '2026-02-16' url: https://github.com/vllm-project/vllm/pull/34597 source_category: upstream-code architectures: -- sm100 +- sm120 tags: - attention - decode @@ -36,7 +36,7 @@ artifact_dir: artifacts/prs/vllm/PR-34597 ## Summary -Enable fp8/fp8_e4m3 KV cache for the Triton MLA attention backend, which is the only MLA backend available on sm120 GPUs. +Enable FP8/FP8-E4M3 KV cache handling for the Triton MLA attention backend. The PR identifies this as the MLA backend available on SM120; neither the PR nor the pinned kernel establishes an SM100-only path or a particular TCGen5/TMEM lowering. - Add fp8 and fp8_e4m3 to TritonMLABackend.supported_kv_cache_dtypes - Thread k_scale/v_scale through decode attention kernel launch path @@ -52,4 +52,3 @@ Enable fp8/fp8_e4m3 KV cache for the Triton MLA attention backend, which is the - `tests/kernels/attention/test_triton_decode_attention.py` - `vllm/v1/attention/backends/mla/triton_mla.py` - `vllm/v1/attention/ops/triton_decode_attention.py` - diff --git a/verification/baseline-metadata.json b/verification/baseline-metadata.json new file mode 100644 index 000000000..6c50678ec --- /dev/null +++ b/verification/baseline-metadata.json @@ -0,0 +1,39 @@ +{ + "recorded_at": "2026-08-08", + "repository_commit": "2777d18ffb3a3d682d8f25a3e3b8864d925a5ff1", + "preexisting_dirty_files": [ + "plan.md" + ], + "python_environment": { + "command_prefix": "conda run -n base python", + "conda_version": "26.5.3", + "python_version": "3.13.14" + }, + "validator": { + "files": 2787, + "asset_bundles": 94, + "candidate_ledgers": 14, + "result": "pass" + }, + "baseline_queue": { + "schema_version": "kernel-wiki-verifier-queue/v2", + "pages": 52, + "coverage_units": 1177, + "page_types": { + "hardware": 8, + "kernel": 14, + "language": 4, + "migration": 2, + "pattern": 7, + "technique": 17 + }, + "risk_pages": { + "code": 51, + "ordering": 24, + "performance": 13, + "table": 36, + "version": 1 + }, + "unresolved_source_ids": 0 + } +} diff --git a/verification/baseline-queue.jsonl b/verification/baseline-queue.jsonl new file mode 100644 index 000000000..fec82544a --- /dev/null +++ b/verification/baseline-queue.jsonl @@ -0,0 +1,52 @@ +{"body_sha256": "eab776a8afa8cfe67479add2ac89855a63fabdee6e46f9b3e445b85a7c94b3c2", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Blackwell enables two SMs within a TPC to cooperatively execute a single larger MMA, doubling the effective compute tile size to m256\u00d7n256\u00d7k16.", "sha256": "4c68819d658d95f6b0bad35c414b126ee5e6bb11ce01bd06368780a795ca9fcc"}, {"id": "u002", "kind": "code", "locator": "body:L7-L15", "preview": "``` TPC (Two Processing Clusters) \u251c\u2500\u2500 SM 0: CTA 0 \u2014 issues tcgen05.mma with cta_group::2 \u2502 \u251c\u2500\u2500 Shared Memory A (rows 0-127) \u2502 \u2514\u2500\u2500 TMEM (columns 0-255) \u2514\u2500\u2500 SM 1: CTA 1 \u2014 cooperates on same MMA \u251c\u2500\u2500 Shared Memory A (rows 128-255) \u2514\u2500\u2500 TMEM (col", "sha256": "0e6130294d59c8d44d6f365e2991eb717fe19cb14ebbe2cb9d6de51ceb6eafa7"}, {"id": "u003", "kind": "code", "locator": "body:L19-L23", "preview": "```ptx // 2-SM cooperative MMA tcgen05.mma.cta_group::2.kind::f16 [tmem_addr], descA, descB, idescC, idescD, ...; ```", "sha256": "0d700ba8114de50a817d01c7fff269445c26dc148aaec150b153114b0ae13af1"}, {"id": "u004", "kind": "list-item", "locator": "body:L26-L26", "preview": "1. **Identical shared memory layouts** across both CTAs", "sha256": "e36c4a200c64261baec9202ed512b08e3fd7120dd8f3e861b8499534d5faa8c5"}, {"id": "u005", "kind": "list-item", "locator": "body:L27-L27", "preview": "2. `shared::cluster` mbarrier signaling between the two CTAs", "sha256": "0c90bbadbfda4845442a1ee4f2ef2d47af52260fc733a49f19023a151a9c1f78"}, {"id": "u006", "kind": "list-item", "locator": "body:L28-L28", "preview": "3. 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Each CTA contributes half the M-dimension", "sha256": "386a2289fdb65727b75dfe9f61fd64665d56e9b575b55fc33426d5493c287c79"}, {"id": "u008", "kind": "prose", "locator": "body:L33-L33", "preview": "From tcgen05 tutorial progression:", "sha256": "24895ac2a57396c2f65b109f4169614ed5fe28fe729d5894ad6d8ecdca334e0e"}, {"id": "u009", "kind": "list-item", "locator": "body:L34-L34", "preview": "- 1-SM MMA (m128\u00d7n256): 80% of cuBLAS \u2192 adding 2-SM: **86%** of cuBLAS", "sha256": "cdbe9f4fdf31a0cba13990dbbe1dae1fe68157127f5a53f4c6471eeb7445491a"}, {"id": "u010", "kind": "list-item", "locator": "body:L35-L35", "preview": "- ~7.5% improvement from doubling the MMA tile size", "sha256": "a0db83cdbca1698169acc1f402113508f5025a7c078746dbb54a6cd94d7c31a3"}, {"id": "u011", "kind": "list-item", "locator": "body:L38-L38", "preview": "- Large GEMM problems where M \u2265 256", "sha256": "5cf6ae011600c2b7ef443ae8818779bbb37c79759270d72e7afd4416c918611c"}, {"id": "u012", "kind": "list-item", "locator": "body:L39-L39", "preview": "- Compute-bound kernels where peak FLOPS matters", "sha256": "c2dff9522ca31603681ba360962d9f61abe2b14a7994e4d6cd9b6b4baca0ef97"}, {"id": "u013", "kind": "list-item", "locator": "body:L40-L40", "preview": "- Combined with persistent scheduling for maximum throughput", "sha256": "6861f7f0c6a4293b2576a9b60618dbce4a3d149ca8ed6845087682ae9aca8f53"}, {"id": "u014", "kind": "list-item", "locator": "body:L43-L43", "preview": "- [tcgen05-mma](tcgen05-mma.md) \u2014 Base MMA instruction", "sha256": "2d8fd127e151bfd81fd1cf598e5c8b8951431858ce1db08f94fb27c13f611d92"}, {"id": "u015", "kind": "list-item", "locator": "body:L44-L44", "preview": "- [tmem](tmem.md) \u2014 Full TMEM used in 2-SM mode", "sha256": "cb9c4c506579cc6a91c520555593e3e08dad8bb1730670cadb62aab9007e8a30"}], "confidence_claimed": "source-reported", "headings": ["Overview", "How It Works", "PTX", "Requirements", "Performance Impact", "When to Use", "Related"], "id": "hw-2sm-cooperative", "path": "wiki/hardware/2sm-cooperative.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/colfax-cutlass-blackwell.md", "url": "https://research.colfax-intl.com/cutlass-tutorial-writing-gemm-kernels-using-tmem-for-nvidia-blackwell-gpus/"}, {"path": "sources/blogs/modular-blackwell-matmul.md", "url": "https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-1-introduction"}], "risk_flags": ["code"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-colfax-cutlass", "blog-modular-blackwell"], "title": "Two-SM Cooperative MMA", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "a62ba7ec03d8146415399b716afb18e5106e6d2fd332e93a3500ddefb76fcc67", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Cluster Launch Control (CLC) is a Blackwell hardware mechanism for **dynamic tile scheduling** in persistent kernels. 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N = 8192 # hidden dim K = 8192 # hidden dim #", "sha256": "6c5d37ce3d231bdf0054356208dbdff793f4db61cb09292da26dd5b309d0e667"}, {"id": "u026", "kind": "prose", "locator": "body:L233-L233", "preview": "When using 2-SM cooperative MMA (`cta_group::2`), CLC distributes work in **cluster-sized units**:", "sha256": "b1754915c10a1c6679890fa9fb5a6f2a20504f9b03f7c044d53da47065052e7f"}, {"id": "u027", "kind": "code", "locator": "body:L235-L260", "preview": "```cuda // 2-SM cooperative CLC: each successful cancel gets a cluster-sized tile __device__ void cooperative_clc_loop() { while (true) { // Fetch tile for the 2-CTA cluster ClusterTile tile; bool valid = clc_try_cancel_cluster(&tile); if (", "sha256": "1af223cad56d56ffa8f45d5ad4c23270bfc3e1613bf685c2fb5e776c748056d8"}, {"id": "u028", "kind": "prose", "locator": "body:L264-L264", "preview": "CLC tile ordering can be customized with swizzle patterns to improve L2 cache hit rates:", "sha256": "25d303ff88dddf358d48c035125c2f5dbdacdfdbff8975f372c389adda9b423c"}, {"id": "u029", "kind": "code", "locator": "body:L266-L281", "preview": "```cuda // Swizzle tile coordinates for better L2 locality // Tiles are visited in a Z-order (Morton) curve pattern __device__ void apply_l2_swizzle(int& tile_m, int& tile_n, int swizzle_bits) { // Convert linear tile index to swizzled 2D c", "sha256": "e907367bf02425d441f6f01b551519752a02632a2dc8a771f95eb12513f2ff6f"}, {"id": "u030", "kind": "table-row", "locator": "body:L287-L287", "preview": "| Feature | CLC (Hardware) | Software Atomics | | Scheduling overhead | Near zero (hardware) | atomicAdd contention |", "sha256": "0cace5c9781e52dd47525aa3dc6554b2cc6b993a0111b2776fbb67af76fc8513"}, {"id": "u031", "kind": "table-row", "locator": "body:L288-L288", "preview": "| Feature | CLC (Hardware) | Software Atomics | | Tail-effect handling | Optimal | Good with careful design |", "sha256": "170ab750f04d2d622fba6d0621244b73e6a6626b7d9971625df8ccb29c8ce720"}, {"id": "u032", "kind": "table-row", "locator": "body:L289-L289", "preview": "| Feature | CLC (Hardware) | Software Atomics | | Cancellation | try_cancel API | Complex (flags + barriers) |", "sha256": "c045af8be0dfa672f3691ebc5e95a69d0530e25b53d1f33c8726c8434b593931"}, {"id": "u033", "kind": "table-row", "locator": "body:L290-L290", "preview": "| Feature | CLC (Hardware) | Software Atomics | | L2 swizzle | Configurable at launch | Manual implementation |", "sha256": "cc683cd2d19aa5060072b2dd9cbdb666a92467dc65eacafdbe5a9424cdc3faac"}, {"id": "u034", "kind": "table-row", "locator": "body:L291-L291", "preview": "| Feature | CLC (Hardware) | Software Atomics | | Portability | SM100+ only | SM70+ |", "sha256": "b401a1d2b6a5df06133924799fce818daed60f89b96821e78cc1c80313270345"}, {"id": "u035", "kind": "table-row", "locator": "body:L292-L292", "preview": "| Feature | CLC (Hardware) | Software Atomics | | CUTLASS support | Built-in | Manual scheduler |", "sha256": "c192f03ddac73f3b1fad9831e3c9c74bc9a103c7ec420fe7cb02fbc60186a12f"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Static Scheduling vs CLC", "Static Scheduling (Hopper and earlier)", "CLC Dynamic Scheduling (Blackwell)", "How CLC Works", "Hardware Queue", "CLC Programming Model", "try_cancel API", "CUTLASS Integration", "CUTLASS CLC Tile Scheduler", "Performance Impact", "Tail Effect Mitigation", "Why CLC Matters for Inference", "CLC with 2-SM Cooperative Mode", "L2 Cache Swizzling with CLC", "Comparison: CLC vs Software Persistent Scheduling"], "id": "hw-clc", "path": "wiki/hardware/clc.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/docs/nvidia-cutlass-blackwell.md", "url": "https://docs.nvidia.com/cutlass/latest/CHANGELOG.html"}, {"path": "sources/prs/cutlass/PR-2161.md", "revision": "06e560d9", "url": "https://github.com/NVIDIA/cutlass/pull/2161"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "doc-cutlass-blackwell", "pr-cutlass-2161"], "title": "Cluster Launch Control (CLC)", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "3abf0f9b53646c33d53214d726c4d11ecf825d2ce9393225f20fd6d3e0fafe27", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "mbarriers are 64-bit shared memory primitives used for producer/consumer synchronization between asynchronous hardware units (TMA, tcgen05) and SM threads. Introduced on Hopper, essential for Blackwell warp-specialized kernels.", "sha256": "67020456ed5764d79a1c98498c631d73b9c845f30e11afec6b55460ed0c53542"}, {"id": "u002", "kind": "code", "locator": "body:L9-L24", "preview": "```ptx // Initialize: set expected arrival count mbarrier.init.shared.b64 [mbar_addr], num_arrivals; // Producer: arrive on barrier (decrements expected count) mbarrier.arrive.shared.b64 _, [mbar_addr]; // Producer (with byte expectation): ", "sha256": "469f01b42c7f6c8ea406edff158693ba9956925112699ae0c1cd5ab43fd1666a"}, {"id": "u003", "kind": "prose", "locator": "body:L28-L28", "preview": "mbarriers have a 1-bit **phase** that flips each time the arrival count reaches zero. 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// TMA completion will fire the mbarrier automatically cp_async", "sha256": "a6dd6f7d2f3833966150f71e6fa6631331fbd15c68c416aeefef947ccd0bcbab"}, {"id": "u007", "kind": "list-item", "locator": "body:L66-L66", "preview": "1. **Missing phase flip**: Reusing a stage slot without flipping parity causes stale arrivals to satisfy the new wait", "sha256": "38b27a576a35224085b652fe4870a18aa1b202b278b367a0b9a6131ba26a1920"}, {"id": "u008", "kind": "list-item", "locator": "body:L67-L67", "preview": "2. **Mismatched init count**: If consumer expects N arrivals but producers only arrive M times, barrier never fires", "sha256": "4db264fc6bcea52fd5d405887493a8213f0d99e37cfe4b4b77d4f3eb2e490f44"}, {"id": "u009", "kind": "list-item", "locator": "body:L68-L68", "preview": "3. **Manual arrive after async issue**: TMA/tcgen05 hardware arrives on completion \u2014 extra manual arrive causes double-count", "sha256": "b92fb45c2ea90b8ee0f51687f8256c71d80afa26cc2ef609d685bbf489894274"}, {"id": "u010", "kind": "list-item", "locator": "body:L69-L69", "preview": "4. **Cross-cluster mbarriers**: Use `shared::cluster` qualifier for cluster-level sync (2-SM cooperative MMA)", "sha256": "b65c1a76861d9d4794307647957566ab68c04c603afc82f9a4a7c5eb78e39349"}, {"id": "u011", "kind": "list-item", "locator": "body:L72-L72", "preview": "- [TMA](tma.md) \u2014 Primary producer for mbarriers", "sha256": "4a9353fd25d5f980a2af41bca0f2670f8c446c550d603d2f98d2ab40cb6c8715"}, {"id": "u012", "kind": "list-item", "locator": "body:L73-L73", "preview": "- [warp-specialization](../techniques/warp-specialization.md) \u2014 Uses mbarriers for warp role handoff", "sha256": "79c4fe0f0e618041a37593c472e4299f1c0b09794e072ea8a941418f58c36e4e"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Key Operations", "Phase/Parity Semantics", "TMA Integration", "Pitfalls", "Related"], "id": "hw-mbarrier", "path": "wiki/hardware/mbarrier.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/parallel-thread-execution/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}], "risk_flags": ["code", "ordering"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-ptx-isa-sm100", "blog-tcgen05-tutorial", "doc-nvidia-tuning-guide"], "title": "mbarrier (Memory Barrier Primitives)", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "b655cfe0784f6e74204d4748a18fb4f06f420b6ddcae893e9b1e8596105d1c1e", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "NVFP4 is NVIDIA's 4-bit floating-point format (E2M1) with block scaling, native to Blackwell tensor cores.", "sha256": "8abc922e94307133aed94cec43886360a79d51104781639e3de843b167647f67"}, {"id": "u002", "kind": "code", "locator": "body:L7-L16", "preview": "``` E2M1: 1 sign bit, 2 exponent bits, 1 mantissa bit Representable values: 0, \u00b10.5, \u00b11, \u00b11.5, \u00b12, \u00b13, \u00b14, \u00b16 Block scaling: every 16 FP4 elements share one FP8 E4M3 scale factor Two-level: per-block E4M3 scale \u00d7 per-tensor FP32 global scal", "sha256": "21ffe2a58e99999f5a22735348606a78f38c4a0a9d0b45d67226ace389690aeb"}, {"id": "u003", "kind": "table-row", "locator": "body:L22-L22", "preview": "| Variant | Description | Throughput vs Hopper | | `tcgen05.mma.mxf4.block_scale` | MX FP4 with block scaling | **4\u00d7** |", "sha256": "86a6edd61976a63588789c9d7a7f5240d0fc24dde9b9adf55e9263af545e5d37"}, {"id": "u004", "kind": "table-row", "locator": "body:L23-L23", "preview": "| Variant | Description | Throughput vs Hopper | | `tcgen05.mma.mxf4nvf4.block_scale` | NVFP4 + MX FP4 flexible scaling | **4\u00d7** |", "sha256": "cef8229b3c8d04130a4e97ec237545e6a60579581fc00a4815311ca4da787a6b"}, {"id": "u005", "kind": "code", "locator": "body:L27-L33", "preview": "```ptx // Convert two FP4 values to two FP16 values cvt.rn.f16x2.e2m1x2 result, packed_fp4; // Byte unpacking (faster than bitwise extraction) mov.b32 {tmp0, tmp1, tmp2, tmp3}, packed_data; ```", "sha256": "2a0444506f6201cdbd12ee4d84eeee8e34480f8b214d1dd0ccd3588fc52edb9a"}, {"id": "u006", "kind": "table-row", "locator": "body:L39-L39", "preview": "| Aspect | NVFP4 | MXFP4 | | Scale format | E4M3 (fractional) | UE8M0 (power-of-2 only) |", "sha256": "5ba0bd24ff2f41265f63ef1ace18f01306be54fd7112770099b1c953bf18f581"}, {"id": "u007", "kind": "table-row", "locator": "body:L40-L40", "preview": "| Aspect | NVFP4 | MXFP4 | | Block size | 16 elements | 32 elements |", "sha256": "e15b87ee9acbd43e77de7ae77e119af93aa10076429d524afc56288a410c4e78"}, {"id": "u008", "kind": "table-row", "locator": "body:L41-L41", "preview": "| Aspect | NVFP4 | MXFP4 | | Scale precision | Non-power-of-2 | Power-of-2 only |", "sha256": "5c6b7ed6fd96be13b33e439ec119d42ddfd1148a4412747eafe9eda0e96efa4e"}, {"id": "u009", "kind": "table-row", "locator": "body:L42-L42", "preview": "| Aspect | NVFP4 | MXFP4 | | Quantization error | Lower | Higher |", "sha256": "ab1b99f61d633a906af2f37809cbddbe0625672eca952e604847d0f129672947"}, {"id": "u010", "kind": "list-item", "locator": "body:L45-L45", "preview": "- [fine-grained-quantization](../techniques/fine-grained-quantization.md) \u2014 Scaling strategies", "sha256": "9915527113d53600b0e00c300a216a38331c04613d563f5bf8b899d13a5ee35e"}, {"id": "u011", "kind": "list-item", "locator": "body:L46-L46", "preview": "- [nvfp4-gemm](../kernels/nvfp4-gemm.md) \u2014 NVFP4 GEMM kernel", "sha256": "b5d9ffba19b2bfbf33f08e8c8c3a3948b5da2ff6e83d0d08a4b378d3bfa54bef"}, {"id": "u012", "kind": "list-item", "locator": "body:L47-L47", "preview": "- [nvfp4-gemv](../kernels/nvfp4-gemv.md) \u2014 NVFP4 GEMV kernel", "sha256": "07b0c9ffbb257479ce649d651ae4501a13ff857a375e7cf09c9ba38415b55ad6"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Format Details", "tcgen05 Variants for FP4", "PTX for FP4 Conversion", "NVFP4 vs MXFP4", "Related"], "id": "hw-nvfp4", "path": "wiki/hardware/nvfp4.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/contests/gpu-mode-nvfp4/problem-1-gemv.md", "url": "https://github.com/gpu-mode/reference-kernels"}, {"path": "sources/contests/gpu-mode-nvfp4/problem-2-gemm.md", "url": "https://github.com/gpu-mode/reference-kernels"}, {"path": "sources/blogs/yue-nvfp4-hackathon.md", "url": "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "contest-gpumode-p1", "contest-gpumode-p2", "blog-yue-nvfp4"], "title": "NVFP4 and Block-Scaled Narrow Precision", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "9783467bbb5c577667660ff8f39f2dd672f1bdcc6cd4729a4f491421bb3ba735", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "PDL/GDC allows overlapping execution of dependent kernel launches. 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Accumulator | Scale | MMA Shape (1SM) | Notes | | `tcgen05.mma.kind::f8f6f4` | FP8/FP6/FP4 | FP8/FP6/FP4 | FP32 | Block (UE8M0) | m128n256k32 | Narrow precision with native block scaling |", "sha256": "77c8c39c8996f7efa26e77672bdb6fdd1a4fc7a60f96ae7b66070bc60ec614fa"}, {"id": "u013", "kind": "table-row", "locator": "body:L27-L27", "preview": "| Variant | A Type | B Type | Accumulator | Scale | MMA Shape (1SM) | Notes | | `tcgen05.mma.kind::i8` | INT8 | INT8 | INT32 | None | m128n256k32 | Integer quantized inference |", "sha256": "1316c17042e8f2540f697ec162c4095a49ec0918e64dd0b2321c9c8a1eec0c08"}, {"id": "u014", "kind": "table-row", "locator": "body:L28-L28", "preview": "| Variant | A Type | B Type | Accumulator | Scale | MMA Shape (1SM) | Notes | | `tcgen05.mma.kind::mxf8` | MXFP8 | MXFP8 | FP32 | MX (E8M0) | m128n256k32 | Microscaling FP8 |", "sha256": "d072b6b1f374097d23710cf42a7c2fb007ffa1c43b30e979dea9c9a5a42a3f2d"}, {"id": "u015", "kind": "table-row", "locator": "body:L29-L29", "preview": "| Variant | A Type | B Type | Accumulator | Scale | MMA Shape (1SM) | Notes | | `tcgen05.mma.kind::mxf4` | MXFP4 | MXFP4 | FP32 | MX (E8M0) | m128n256k64 | Microscaling FP4 |", "sha256": "baf885059cee16d5fe0e697097c69625b7d05ea53eec841b2c35f7f0d4da10b0"}, {"id": "u016", "kind": "table-row", "locator": "body:L30-L30", "preview": "| Variant | A Type | B Type | Accumulator | Scale | MMA Shape (1SM) | Notes | | `tcgen05.mma.kind::mxf4nvf4` | NVFP4 | MXFP4 | FP32 | Mixed | m128n256k64 | Mixed NVFP4/MXFP4 |", "sha256": "081789a4a51ae4c6ec7d2eec0673accee43d78e03a2d3c4fa65fdeaebf628b1f"}, {"id": "u017", "kind": "prose", "locator": "body:L36-L36", "preview": "In single-SM mode, a single CTA owns the full MMA operation:", "sha256": "e95cab2553d565ad144238283360c0751f98e89a4e385960e363e9d5a68ee852"}, {"id": "u018", "kind": "list-item", "locator": "body:L38-L38", "preview": "- **BF16/FP16**: M=128, N=256, K=16", "sha256": "d6796d7d9f61232e06b4311b893d2b2eae0a82a962c9db9427349f2d0f97dcb0"}, {"id": "u019", "kind": "list-item", "locator": "body:L39-L39", "preview": "- **TF32**: M=128, N=256, K=8", "sha256": "9f41e350e5bff3603f0577e780f09bf4d459eb68d08f9cd854d4bf6d42e568a9"}, {"id": "u020", "kind": "list-item", "locator": "body:L40-L40", "preview": "- **FP8/FP6/FP4**: M=128, N=256, K=32", "sha256": "57e289de66c363bc36c94988413303d40e5be7626478a54a27dd5667fda256db"}, {"id": "u021", "kind": "list-item", "locator": "body:L41-L41", "preview": "- **MXFP4/NVFP4**: M=128, N=256, K=64", "sha256": "aceb169193ceaf59eda6f0ed24b9dd2d2162ac61067adcbf01899e951de49465"}, {"id": "u022", "kind": "prose", "locator": "body:L45-L45", "preview": "In two-SM cooperative mode, two CTAs share a single MMA across paired SMs:", "sha256": "f2bd49a48c358708522d028c09200e9ea094a4a39954f3a3e8376fd886466fac"}, {"id": "u023", "kind": "list-item", "locator": "body:L47-L47", "preview": "- **BF16/FP16**: M=256, N=256, K=16", "sha256": "292c722d114c6ea9a0451f5aed1f2916d19284c16bb5c9cf2def7500874aede3"}, {"id": "u024", "kind": "list-item", "locator": "body:L48-L48", "preview": "- **TF32**: M=256, N=256, K=8", "sha256": "192f1f5c6b438096a250f4226104d0070930a45692f12cb09b8c19d62ba3fa21"}, {"id": "u025", "kind": "list-item", "locator": "body:L49-L49", "preview": "- **FP8/FP6/FP4**: M=256, N=256, K=32", "sha256": "2dc32df8bac83f14b078efb009d544575ffd4230a19520b21e2316b5e2a5b157"}, {"id": "u026", "kind": "list-item", "locator": "body:L50-L50", "preview": "- **MXFP4/NVFP4**: M=256, N=256, K=64", "sha256": "ddb200b255ce7987de4c22f2117510fe73c076524527264bdba171b0ac929bbc"}, {"id": "u027", "kind": "prose", "locator": "body:L52-L52", "preview": "The M dimension doubles because each SM contributes 128 rows from its own TMEM partition.", "sha256": "245389c1d8c57c0f83c2942c6360ad574a0c7a06300c59c147615c2a627e12ed"}, {"id": "u028", "kind": "prose", "locator": "body:L56-L56", "preview": "Unlike `wgmma` which required coordinated issuance from a warpgroup (4 warps, 128 threads), `tcgen05.mma` is issued by a **single thread**. This is a fundamental architectural simplification:", "sha256": "71da8434bb560ed4ddfbc811220178d5ea11875fc086f8b158cc40ce7683903b"}, {"id": "u029", "kind": "list-item", "locator": "body:L58-L58", "preview": "1. **No warpgroup synchronization overhead** -- one elected thread (typically lane 0 of warp 0) issues the MMA.", "sha256": "432f0d95c6a8d041630a86ca3ff48ff01bc87124cdbfe696b4464a2806f82c7b"}, {"id": "u030", "kind": "list-item", "locator": "body:L59-L59", "preview": "2. **Fully asynchronous** -- the instruction returns immediately; the hardware pipeline executes the MMA in the background.", "sha256": "8dc14dd7c57349307819e7bcfe4f842283c3b91cce9cb8a32d1212b31c49739b"}, {"id": "u031", "kind": "list-item", "locator": "body:L60-L60", "preview": "3. **Fence-based completion** -- the producer must insert explicit fences before reading results from TMEM.", "sha256": "8032f029f78505c1cfef1c04a5868f1f30fb974558b2adf1927741e8f80d67b6"}, {"id": "u032", "kind": "code", "locator": "body:L62-L78", "preview": "```cuda // Single-thread MMA issuance pattern __device__ void issue_mma(uint32_t tmem_addr, uint64_t smem_desc_a, uint64_t smem_desc_b) { // Only one thread issues the MMA if (threadIdx.x == 0) { asm volatile( \"tcgen05.mma.cta_group::1.kind", "sha256": "1da10e7ccfb570ac3a16ff4613c427eb433a91d1dc09c937908df8f895e14919"}, {"id": "u033", "kind": "code", "locator": "body:L84-L90", "preview": "```ptx // Issue a 128x256x16 BF16 MMA // Operand A: shared memory descriptor // Operand B: shared memory descriptor // Accumulator: TMEM address tcgen05.mma.cta_group::1.kind::f16 [tmem_addr], desc_a, desc_b, idesc, 0; ```", "sha256": "2ec3f9255d66d3259a87a98053489dbf2a996031cb9969464321eb8ae3838acb"}, {"id": "u034", "kind": "code", "locator": "body:L94-L98", "preview": "```ptx // Issue a 256x256x16 BF16 MMA across two paired CTAs // cta_group::2 indicates cooperative mode tcgen05.mma.cta_group::2.kind::f16 [tmem_addr], desc_a, desc_b, idesc, 0; ```", "sha256": "c700b225d5065ea34cb16448b941540c38910079f9b53adefde633f66dbb3e8e"}, {"id": "u035", "kind": "code", "locator": "body:L102-L106", "preview": "```ptx // FP8 with native UE8M0 block scaling // scale_desc encodes the per-block scale factors tcgen05.mma.cta_group::1.kind::f8f6f4 [tmem_addr], desc_a, desc_b, idesc, scale_desc; ```", "sha256": "f599a047c6c8f0e014be08650a4e65a950921059e5af835d6e699baf832f3fc8"}, {"id": "u036", "kind": "code", "locator": "body:L110-L143", "preview": "```cuda __device__ void mma_bf16_128x256x16( uint32_t tmem_addr, uint64_t desc_a, uint64_t desc_b ) { if (threadIdx.x == 0) { // First MMA: zero-initialize accumulator asm volatile( \"tcgen05.mma.cta_group::1.kind::f16 \" \"[%0], %1, %2, %3, 0", "sha256": "060c5dff2b407c8c4e2dfc6d4e1ecc8d43a091336c0f06e5842edfcab286d9a8"}, {"id": "u037", "kind": "prose", "locator": "body:L147-L147", "preview": "Fences are **mandatory** for correctness. The hardware does not implicitly synchronize between MMA and TMEM reads/writes.", "sha256": "a72296169aa9135e44dfc5984c321024f77eb48e3d5c9da61743c870647149dc"}, {"id": "u038", "kind": "prose", "locator": "body:L151-L151", "preview": "Insert before reading MMA results from TMEM:", "sha256": "eaf7f1dd300e86a6737d70df5b482dfab6ea182a217b04f674fda58b072e8bdc"}, {"id": "u039", "kind": "code", "locator": "body:L153-L159", "preview": "```cuda // Fence before CTA sync and TMEM reads after the completion mechanism. __device__ void fence_before_tmem_read() { asm volatile(\"tcgen05.fence::before_thread_sync;\"); __syncthreads(); // Ensure all threads see the fence } ```", "sha256": "1fc691ed417f0bd1f9bbf2cb2509f6a3c2c23a5ca95d6b56160d0d114052abda"}, {"id": "u040", "kind": "code", "locator": "body:L163-L169", "preview": "```ptx // Fence before reading TMEM (most common) tcgen05.fence::before_thread_sync; // Fence after CTA sync before issuing dependent tcgen05 operations tcgen05.fence::after_thread_sync; ```", "sha256": "1b8df98c715da239957bab2fa7955b707c81f838d7a38d6726bc6f32fdc5861a"}, {"id": "u041", "kind": "code", "locator": "body:L173-L205", "preview": "```cuda __device__ void gemm_mainloop(/* params */) { for (int k_tile = 0; k_tile < num_k_tiles; ++k_tile) { // 1. Wait for operand data to arrive in SMEM wait_barrier(k_tile % NUM_STAGES); // 2. Issue MMA (single thread) if (threadIdx.x ==", "sha256": "0323f85ba7a3daab67b8987036afeb57aa43a2505184a9cfcc1b7397e014035e"}, {"id": "u042", "kind": "code", "locator": "body:L211-L262", "preview": "```cuda // ---- HOPPER (SM90): wgmma ---- // Requires warpgroup-scoped execution // All 128 threads in a warpgroup participate __device__ void hopper_mma() { // Load A matrix into registers via ldmatrix uint32_t a_frag[4]; asm volatile(\"ldm", "sha256": "5433c50cca6c613a6485e7f48dd6eb9ca5f484168dfb77eb0acb8c3c7ed12f73"}, {"id": "u043", "kind": "list-item", "locator": "body:L266-L266", "preview": "- **Register pressure**: Hopper wgmma uses 128+ registers for accumulators in a large GEMM tile. Blackwell stores accumulators in TMEM, freeing those registers for data movement and epilogue logic.", "sha256": "029c2ae73727925cc4f85919ae8083ed6cb51cee4a0c2b52bbb46d3b1ad32b05"}, {"id": "u044", "kind": "list-item", "locator": "body:L267-L267", "preview": "- **Occupancy**: Lower register pressure enables higher CTA occupancy or larger tile sizes without spilling.", "sha256": "f21aef249d792aa306840015d163f69ed2e37d096ba71f3f20b39c698829e66f"}, {"id": "u045", "kind": "list-item", "locator": "body:L268-L268", "preview": "- **Warp specialization**: With tcgen05, a single MMA-producer warp can feed the tensor cores while other warps handle TMA loads, epilogue, or softmax -- a natural fit for FlashAttention-style kernels.", "sha256": "fa04e99a463edbaa311980500028dda54385d889a81c8c7af72fda61eb2ecfdd"}, {"id": "u046", "kind": "prose", "locator": "body:L272-L272", "preview": "tcgen05.mma requires **128-byte swizzled** shared memory layouts for both operands. Non-swizzled or 64-byte swizzled layouts will produce incorrect results silently.", "sha256": "6dc7add35a27c3559545905c86d768c01d6bade589924bc2228216d8b357fdaf"}, {"id": "u047", "kind": "code", "locator": "body:L274-L290", "preview": "```cuda // Shared memory descriptor construction for tcgen05 // The descriptor encodes: base address, stride, swizzle mode, dimensions __device__ uint64_t make_smem_desc(void* smem_ptr, int stride_bytes) { uint64_t desc = 0; uint32_t addr =", "sha256": "c17d7d6ecf6fdf969cb8ff69fa527a15952391edf02c7f3e7ea2efbcc2673814"}, {"id": "u048", "kind": "table-row", "locator": "body:L296-L296", "preview": "| Optimization Stage | Throughput (TFLOPS) | % of cuBLAS | | Naive tcgen05.mma | 255 | 17% |", "sha256": "215a0512939c93a6645fad9f4143f9f0e5ccea6daa0068335ab637544c5b1f71"}, {"id": "u049", "kind": "table-row", "locator": "body:L297-L297", "preview": "| Optimization Stage | Throughput (TFLOPS) | % of cuBLAS | | + 128B swizzled SMEM | 695 | 46% |", "sha256": "28107fdb48a27091b4c76073eaf584b000ea20c8ec2dde46f59f86a1a1dc461d"}, {"id": "u050", "kind": "table-row", "locator": "body:L298-L298", "preview": "| Optimization Stage | Throughput (TFLOPS) | % of cuBLAS | | + TMA pipelining | 940 | 62% |", "sha256": "e23ddcc26736e8a0270c7b0698da4e2167c9239935887cb66388537f35686645"}, {"id": "u051", "kind": "table-row", "locator": "body:L299-L299", "preview": "| Optimization Stage | Throughput (TFLOPS) | % of cuBLAS | | + Persistent kernel + CLC | 1476 | 98% |", "sha256": "9d517c625ca2a23c9737ee06468b2d3d57575f07e1095b542f2b4d8201acb6e5"}, {"id": "u052", "kind": "table-row", "locator": "body:L300-L300", "preview": "| Optimization Stage | Throughput (TFLOPS) | % of cuBLAS | | cuBLAS reference | 1507 | 100% |", "sha256": "6ebea4a476eab8c20f757e683a33f4511a465993fa375b72a59beb1d119027ee"}], "confidence_claimed": "verified", "headings": ["Overview", "Instruction Variants", "MMA Shapes: 1-SM vs 2-SM", "1-SM (Single CTA) Shapes", "2-SM (Cooperative) Shapes", "Single-Thread Issuance Model", "PTX Examples", "Basic BF16 MMA (1-SM)", "2-SM Cooperative BF16 MMA", "FP8 with Block Scaling", "CUDA Inline PTX for BF16 MMA with Accumulation", "Critical Fences", "tcgen05.fence", "tcgen05.fence variants", "Correct Mainloop Fence Pattern", "Comparison with wgmma", "Programming Model Shift", "Performance Implications", "SMEM Layout Requirements", "Performance Progression (from tcgen05-for-dummies)"], "id": "hw-tcgen05-mma", "path": "wiki/hardware/tcgen05-mma.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/prs/cutlass/PR-2139.md", "revision": "ca4fdbea", "url": "https://github.com/NVIDIA/cutlass/pull/2139"}, {"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/blogs/colfax-cutlass-blackwell.md", "url": "https://research.colfax-intl.com/cutlass-tutorial-writing-gemm-kernels-using-tmem-for-nvidia-blackwell-gpus/"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["pr-cutlass-2139", "doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "blog-colfax-cutlass"], "title": "tcgen05.mma \u2014 Blackwell MMA Instruction", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "5a71bdad2d3319054af91f093a17db812ad57396120e6144d8f62535bed3e49f", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "The Tensor Memory Accelerator (TMA) is a hardware unit that performs **asynchronous bulk data transfers** between global memory and shared memory. First introduced on Hopper (SM90), TMA carries forward to Blackwell (SM100) with stricter req", "sha256": "6d6eff87de98618f04ba285d851f7199cafc69183bacdcde0626ee9c20931113"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "TMA offloads data movement from CUDA cores entirely -- a single thread issues the transfer, and the TMA hardware engine handles the multi-dimensional copy, address calculation, out-of-bounds clamping, and format conversion.", "sha256": "5f5489e9b50365c4c7b7e0f90b48655ccd39ac813cf2dcb78ff9360c5cbcf081"}, {"id": "u003", "kind": "table-row", "locator": "body:L13-L13", "preview": "| Property | Detail | | Transfer direction | GMEM <-> SMEM (bidirectional) |", "sha256": "2da1269cc5091e9525a3ea7e433d11d95b62c61ffb9507ef27edcce2522c7938"}, {"id": "u004", "kind": "table-row", "locator": "body:L14-L14", "preview": "| Property | Detail | | Dimensionality | 1D to 5D tensor copies |", "sha256": "cdba3506fd6e4aee624343d3eca5423401bdffe7f9adb2711555b115c586dfae"}, {"id": "u005", "kind": "table-row", "locator": "body:L15-L15", "preview": "| Property | Detail | | Max transfer size | Up to 256 bytes per element, tiles up to 128x256 |", "sha256": "90b2ff76015ec67931b7de66bf52c314e632138b94f34229afdb258ebbc553a2"}, {"id": "u006", "kind": "table-row", "locator": "body:L16-L16", "preview": "| Property | Detail | | Swizzle modes | None, 32B, 64B, 128B (128B required for tcgen05) |", "sha256": "8bf3b7ca9390572592def684644d8715df52ae1d267f6a78b6a2093689e4c7b1"}, {"id": "u007", "kind": "table-row", "locator": "body:L17-L17", "preview": "| Property | Detail | | Format conversion | FP32<->BF16, FP32<->FP16 during transfer |", "sha256": "d8ea01398e724da58297f46f2db35102480b99554a89efebc524e8fc697ea50e"}, {"id": "u008", "kind": "table-row", "locator": "body:L18-L18", "preview": "| Property | Detail | | Multicast | Single GMEM tile -> multiple CTAs in a cluster |", "sha256": "81a8e2499398ef4067a423dcc17bd45b5bf1104df5c85c7a4aa713feeaa59d13"}, {"id": "u009", "kind": "table-row", "locator": "body:L19-L19", "preview": "| Property | Detail | | Synchronization | mbarrier-based (arrive/wait) |", "sha256": "57cd317aa4514c7cb216e252b7663af4979b1b97ff0af36af4a37703abc92f3c"}, {"id": "u010", "kind": "table-row", "locator": "body:L20-L20", "preview": "| Property | Detail | | Thread requirement | Single thread issues the operation |", "sha256": "dd10cbfa8e26de4d1d42013f895c001de89b10422160dae34f5a58b3f1c05b11"}, {"id": "u011", "kind": "prose", "locator": "body:L24-L24", "preview": "TMA operations are driven by a **descriptor** that encodes the tensor layout, addressing, and transfer parameters. The descriptor is created on the host and passed to the kernel.", "sha256": "06c87265434fd3702487d5ddf4e300ab59a44f78dbc12085d78ee73996ffd876"}, {"id": "u012", "kind": "code", "locator": "body:L28-L75", "preview": "```cuda #include // Create a 2D TMA descriptor for a row-major FP16 matrix CUtensorMap create_tma_descriptor_2d( const half* global_ptr, int M, int N, // Global tensor dimensions int tile_m, int tile_n, // Tile dimensions for each ", "sha256": "57863f4b926991265817ae00465549f2c48c73bb16bdb9f9922b8b00a4edb123"}, {"id": "u013", "kind": "prose", "locator": "body:L79-L79", "preview": "On Blackwell, `tcgen05.mma` requires operands in **128-byte swizzled** SMEM layout. If TMA loads data without 128B swizzling, the MMA will produce incorrect results.", "sha256": "c2d8fcddb976be600f1ac35e18c00ba49c01acdc2bcbde3e14e643d0d56baabd"}, {"id": "u014", "kind": "code", "locator": "body:L81-L89", "preview": "```cuda // CORRECT for Blackwell tcgen05: CUtensorMap desc = create_tma_descriptor_2d(ptr, M, N, 128, 64, 128); // swizzle=128 ^^^ // WRONG for tcgen05 (will silently produce garbage): CUtensorMap desc = create_tma_descriptor_2d(ptr, M, N, ", "sha256": "c6e226b9487e233d560d2878659d04e63db886fcf8c887b53f4f331b5bd9da62"}, {"id": "u015", "kind": "code", "locator": "body:L95-L125", "preview": "```cuda // TMA load: single thread issues, hardware executes asynchronously __device__ void tma_load_tile( const CUtensorMap* desc, void* smem_ptr, uint64_t* mbar_ptr, // mbarrier for synchronization int coord_x, int coord_y ) { if (threadI", "sha256": "2814db4a3e74defb118105670f7b2dba4f85d9afccd3068244202fe37ae54db4"}, {"id": "u016", "kind": "code", "locator": "body:L129-L150", "preview": "```cuda // TMA store: write a tile from shared memory back to global memory __device__ void tma_store_tile( const CUtensorMap* desc, const void* smem_ptr, int coord_x, int coord_y ) { if (threadIdx.x == 0) { asm volatile( \"cp.async.bulk.ten", "sha256": "85156f9df505c2971d69dc88525d09413d6218e432142ac1bef4f821622483de"}, {"id": "u017", "kind": "prose", "locator": "body:L154-L154", "preview": "TMA uses mbarriers (memory barriers) for producer-consumer synchronization. The pattern is:", "sha256": "34d4d48b31d54d11bc76d776aafc0ec9b1dad8a8306744b5c7b65db5f66de30e"}, {"id": "u018", "kind": "list-item", "locator": "body:L156-L156", "preview": "1. **Producer** (TMA): arrives at the barrier when the transfer completes, decrementing the expected transaction count.", "sha256": "8714de0f91ab74b7548cf7c2e1974ad3afd53d60ea966dffe0422ac6ec219fe8"}, {"id": "u019", "kind": "list-item", "locator": "body:L157-L157", "preview": "2. **Consumer** (compute warps): waits on the barrier before reading the loaded data.", "sha256": "21c13e7cb282b911ce221810cb203c81953662b6f33367dbe203ee45d7b90365"}, {"id": "u020", "kind": "code", "locator": "body:L161-L208", "preview": "```cuda // Multi-stage pipeline with TMA + mbarrier __device__ void pipelined_mainloop( const CUtensorMap* desc_a, const CUtensorMap* desc_b, void* smem_a_stages[NUM_STAGES], void* smem_b_stages[NUM_STAGES], uint64_t* mbar[NUM_STAGES], int ", "sha256": "225c35b88486b841873a34050538c637cbf085b0fc63a3c15b84248c0b8de744"}, {"id": "u021", "kind": "code", "locator": "body:L212-L239", "preview": "```cuda // Initialize an mbarrier __device__ void mbarrier_init(uint64_t* mbar, int arrive_count) { if (threadIdx.x == 0) { asm volatile( \"mbarrier.init.shared.b64 [%0], %1;\" : : \"r\"((uint32_t)__cvta_generic_to_shared(mbar)), \"r\"(arrive_cou", "sha256": "37abac18e0c6bfe80b0c4a86e8a2c69c6bd02b290dd63ae53d4f283747316c72"}, {"id": "u022", "kind": "prose", "locator": "body:L243-L243", "preview": "TMA multicast sends a single GMEM tile to **multiple CTAs within a cluster** simultaneously. This is critical for GEMM where the B operand is shared across M-axis tiles.", "sha256": "a6d1fa8c7919f1142e47b85a82a07c116fafee57c0285f647b8aead64d6e36fc"}, {"id": "u023", "kind": "code", "locator": "body:L245-L275", "preview": "```cuda // Multicast TMA: load B tile to all CTAs in the cluster __device__ void tma_multicast_load( const CUtensorMap* desc, void* smem_ptr, uint64_t* mbar_ptr, int coord_x, int coord_y, uint16_t multicast_mask // bitmask: which CTAs in cl", "sha256": "75a84d8e1b144fd1d87e312a3cb22eb2500d3abd72aab748b8c4247ee3ac7354"}, {"id": "u024", "kind": "code", "locator": "body:L279-L289", "preview": "``` Cluster: 2 CTAs (CTA0 and CTA1) each computing different M-tiles of the same N column CTA0: computes C[0:128, 0:256] -- needs A[0:128, :] and B[:, 0:256] CTA1: computes C[128:256, 0:256] -- needs A[128:256, :] and B[:, 0:256] B[:, 0:256", "sha256": "3a54d0f2da8520509ed5a923a537b39d55946b43e0e574601f67a44dd094777c"}, {"id": "u025", "kind": "prose", "locator": "body:L295-L295", "preview": "All TMA loads feeding `tcgen05.mma` must use 128-byte swizzling. The swizzle pattern rearranges bytes within each 128-byte line to match the tensor core's internal data layout:", "sha256": "cb10875d9e024b63e15b6ff8f8a291efa485fe1916f1e6c865ab5fb8382fc0d6"}, {"id": "u026", "kind": "code", "locator": "body:L297-L307", "preview": "``` Without swizzle (linear): Row 0: bytes [0, 1, 2, ..., 127] Row 1: bytes [128, 129, ..., 255] With 128B swizzle: Row 0: bytes [0, 1, ..., 127] (unchanged) Row 1: bytes [128, 129, ..., 255] XOR pattern applied Row 2: bytes [256, ...] XOR ", "sha256": "cb16062ad73a61cf53dcc4443e45be6ff58f5b8b6d377459aedb090a377a8e5e"}, {"id": "u027", "kind": "prose", "locator": "body:L309-L309", "preview": "The swizzle eliminates bank conflicts when the tensor core reads operand tiles from SMEM.", "sha256": "888e7c417217400b77f64adff1a4d64a2ec41bbfe1db329e554b71a4330f3dda"}, {"id": "u028", "kind": "prose", "locator": "body:L313-L313", "preview": "On Blackwell, data flows through a characteristic pipeline:", "sha256": "4a5ecf1e859ecacb759629cda9097134cec765de3c4f0f7949164a061216141c"}, {"id": "u029", "kind": "code", "locator": "body:L315-L321", "preview": "``` GMEM --[TMA]--> SMEM --[tcgen05.mma]--> TMEM --[tcgen05.ld]--> Registers --[st.global]--> GMEM ^ | | v +---- (epilogue) --------+ (bias, activation, etc.) ```", "sha256": "23b694230f776799fe80b7749e74d338abe653b470743f527d8d958405d8c163"}, {"id": "u030", "kind": "table-row", "locator": "body:L327-L327", "preview": "| Tip | Detail | | Maximize TMA utilization | Keep the TMA unit busy with back-to-back loads across pipeline stages |", "sha256": "0f0085d2379e03ead049c34b77c01690f1047ac972f320212547456b038ca909"}, {"id": "u031", "kind": "table-row", "locator": "body:L328-L328", "preview": "| Tip | Detail | | Use multicast for shared operands | Reduces GMEM bandwidth by cluster_size x for shared tiles |", "sha256": "0d0fd8f052b29acfa61919241bc206b7e745d7d9b54b53f51a8a01234cb4eff5"}, {"id": "u032", "kind": "table-row", "locator": "body:L329-L329", "preview": "| Tip | Detail | | Always use 128B swizzle on Blackwell | Non-128B swizzle produces incorrect tcgen05 results |", "sha256": "caad6d87d0bc24231243a1b46df875eba98884e8477729e4e18b90dc02addb2b"}, {"id": "u033", "kind": "table-row", "locator": "body:L330-L330", "preview": "| Tip | Detail | | Prefer 2D TMA over manual addressing | TMA handles out-of-bounds clamping, padding, and strided access |", "sha256": "6f608acbc60d7738b227c27c49c76b27457dca7f851bcce36169be3a93940f61"}, {"id": "u034", "kind": "table-row", "locator": "body:L331-L331", "preview": "| Tip | Detail | | Pipeline depth | 3-5 stages typically optimal; more stages increase SMEM usage |", "sha256": "aa338cea255897b5ec5aac410d0bf95a733eaaa4d783b78e0bd8988dbee32b19"}, {"id": "u035", "kind": "code", "locator": "body:L335-L358", "preview": "```python # CuTe-DSL TMA copy setup for Blackwell GEMM from cute import * # Define TMA copy atom for operand A (BF16, 128x64 tile) tma_a = make_tma_copy( SM100_TMA_LOAD_2D, tensor_a, # global tensor smem_layout_a, # shared memory layout til", "sha256": "10753b9dc055201da7d81c8b71d2cbb21172613f8cb1f6b5e6d94522bb27f8f2"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Key Properties", "TMA Descriptor", "Host-Side Descriptor Creation", "Blackwell Requirement: 128-Byte Swizzle", "Asynchronous Copy Operations", "GMEM to SMEM (Load)", "SMEM to GMEM (Store)", "mbarrier Synchronization", "Pipeline Stage Pattern", "mbarrier Operations", "TMA Multicast", "Multicast in GEMM", "Blackwell-Specific Enhancements", "128-Byte Swizzle for tcgen05", "TMA + TMEM Integration", "Performance Considerations", "CuTe-DSL Example"], "id": "hw-tma", "path": "wiki/hardware/tma.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/prs/flashinfer/PR-2387.md", "revision": "18804cd5", "url": "https://github.com/flashinfer-ai/flashinfer/pull/2387"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "pr-flashinfer-2387"], "title": "Tensor Memory Accelerator (TMA)", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "31c6ed49bcd928754519fe06febb83cd987d9f3691fc9bb89f5aad7c7e1351b0", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Tensor Memory (TMEM) is a new addressable memory space introduced in the Blackwell architecture (SM100). Each SM contains **256KB of dedicated TMEM**, used primarily as the accumulator storage for `tcgen05.mma` operations. TMEM eliminates t", "sha256": "1061d6dc2ddafb48abd714a4d5efe9cd2964680e6c93e163d2a6e56d37057890"}, {"id": "u002", "kind": "prose", "locator": "body:L9-L9", "preview": "TMEM is organized as a 2D matrix:", "sha256": "b9ee2fd601f53f4d69abc8772241239451ce2518103c78f6035064ebf9ea61d6"}, {"id": "u003", "kind": "table-row", "locator": "body:L13-L13", "preview": "| Dimension | Size | Description | | Rows | 128 | Mapped to warp lanes (4 warps x 32 lanes) |", "sha256": "9d2b5837822a69615072b240debe88240992f12ed76775a8fd7dd5457a6e3b7b"}, {"id": "u004", "kind": "table-row", "locator": "body:L14-L14", "preview": "| Dimension | Size | Description | | Columns | 512 | 32-bit (4-byte) elements per row |", "sha256": "cc5876d4574fd324c0889336b94701f83dc37d4a566633d896310c39b4b7e788"}, {"id": "u005", "kind": "table-row", "locator": "body:L15-L15", "preview": "| Dimension | Size | Description | | Total | 128 x 512 x 4 bytes = 256 KB | Per-SM capacity |", "sha256": "823a7c749e8300c9ba2d5901c6c279b0b7991020f7a54eb045244e969579c561"}, {"id": "u006", "kind": "prose", "locator": "body:L19-L19", "preview": "TMEM rows are mapped to warp lanes within a CTA:", "sha256": "1d7f452d6a0d7c61027ddd0241a691a365b1b341c2fc911723b90a7d468a32c6"}, {"id": "u007", "kind": "code", "locator": "body:L21-L26", "preview": "``` Row 0-31: Warp 0, lanes 0-31 Row 32-63: Warp 1, lanes 0-31 Row 64-95: Warp 2, lanes 0-31 Row 96-127: Warp 3, lanes 0-31 ```", "sha256": "0f5db3db15a2057887a17b00f833ff07ab3c38a54054d175aacf6e4da48d548e"}, {"id": "u008", "kind": "prose", "locator": "body:L28-L28", "preview": "Each thread \"owns\" the TMEM row corresponding to its warp and lane. When reading from TMEM, thread `T` in warp `W` accesses row `W*32 + T%32`.", "sha256": "21f05ce2e5f909709af6d5435132ab21c2db8f98bfd6ff3e994b965472d0b7a8"}, {"id": "u009", "kind": "prose", "locator": "body:L32-L32", "preview": "Columns are addressed via a column offset in the TMEM descriptor. A 128x256 MMA accumulator tile occupies:", "sha256": "b1187703d27200988d5e927bfffb48cbc93a89b1529a6291deaaaa9d90e57a2a"}, {"id": "u010", "kind": "list-item", "locator": "body:L34-L34", "preview": "- 128 rows (all lanes across 4 warps)", "sha256": "205bc2020ca1a67fb475a45e45ead00f89691239a0edb820650982280b6816ff"}, {"id": "u011", "kind": "list-item", "locator": "body:L35-L35", "preview": "- 256 columns of FP32 values = 1024 bytes per row", "sha256": "732f5010af611142ddeb72a8f257140137a6950e723cbd1f5e7f33ef32722179"}, {"id": "u012", "kind": "code", "locator": "body:L37-L46", "preview": "``` TMEM Layout for 128x256 FP32 accumulator: col 0 col 255 col 511 |------------|-----------|-----------| | Acc Tile | (free) | (free) | row 0 (warp0, lane0) | 128x256 | | | row 1 (warp0, lane1) | FP32 | | | ... | | | | row 127 (warp3, lan", "sha256": "1890f36c715384fe174527bf32fc91e63c8c1e0501aa57f0f06ed813bfc3912b"}, {"id": "u013", "kind": "prose", "locator": "body:L50-L50", "preview": "TMEM is **explicitly managed** by the programmer. There is no automatic allocation or garbage collection.", "sha256": "13ae2d3bb87ce433fcf18c6be2e0eda6b539a511f50616d91807363bd8c3a6d8"}, {"id": "u014", "kind": "code", "locator": "body:L54-L73", "preview": "```cuda // Shared storage for CTA-wide broadcast of TMEM address __shared__ uint32_t s_tmem_addr; __device__ uint32_t tmem_alloc_cta(uint32_t num_cols) { // Only thread 0 allocates; result must reach ALL warps in the CTA. // __shfl_sync is ", "sha256": "dee7930d5f81bfb644f61c3d4cb0d57161c24c2721683563ebd31546104ef836"}, {"id": "u015", "kind": "prose", "locator": "body:L75-L75", "preview": "Key points:", "sha256": "591268c33079e24bfeebcc0529014d25e7740ec1aee7dc4e76323f4b0b70c5ac"}, {"id": "u016", "kind": "list-item", "locator": "body:L76-L76", "preview": "- `num_cols` specifies the number of 32-bit columns to allocate.", "sha256": "4d144f82f44ee97ab1d9a00ee9229bcd3f2b48f5977cb1fb32c61ce3fa995d74"}, {"id": "u017", "kind": "list-item", "locator": "body:L77-L77", "preview": "- A 128x256 FP32 accumulator needs 256 columns.", "sha256": "785bbae263d94fcc126298f121aa97530d6dcd31501cad5e969efd9dc3e6f922"}, {"id": "u018", "kind": "list-item", "locator": "body:L78-L78", "preview": "- Allocation is **CTA-scoped** -- all threads in the CTA share the same TMEM region.", "sha256": "2bfb5d48482875538a5faf123a1b8b099d4601c17758d9f4ea5201d08580a976"}, {"id": "u019", "kind": "list-item", "locator": "body:L79-L79", "preview": "- Only one thread (typically thread 0) issues the allocation.", "sha256": "662e8f7a636319070e6e6a2e3442ca834f9f94dd2f2bde0b34b2ff1aff631012"}, {"id": "u020", "kind": "list-item", "locator": "body:L80-L80", "preview": "- The returned `tmem_addr` is the base column index.", "sha256": "665b2a536e3c91858e1fa29f0a5d6726395ae9629b209334586080d79f059323"}, {"id": "u021", "kind": "code", "locator": "body:L84-L95", "preview": "```cuda __device__ void tmem_dealloc(uint32_t tmem_addr, uint32_t num_cols) { if (threadIdx.x == 0) { asm volatile( \"tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;\" : : \"r\"(tmem_addr), \"r\"(num_cols) ); } __syncthreads(); } ```", "sha256": "20b0e50a72af8a57ef048d345054636e2f6e36f01353cd96d912757d74df5ef1"}, {"id": "u022", "kind": "prose", "locator": "body:L97-L97", "preview": "**Warning**: Failure to deallocate TMEM before CTA exit will leak memory and prevent subsequent CTAs from allocating, leading to hangs in persistent kernels.", "sha256": "e20744d781f98e7f0ab5ed7cf6ee085090ba692328a4be69d967b49e6803be68"}, {"id": "u023", "kind": "code", "locator": "body:L101-L128", "preview": "```cuda __global__ void persistent_gemm_kernel(/* ... */) { // 1. Allocate TMEM for accumulators uint32_t tmem_acc = tmem_alloc(256); // 256 cols for M=128, N=256 while (has_more_tiles()) { // 2. Zero-initialize TMEM accumulator tmem_zero(t", "sha256": "1943ba3ab4110b43b39e4a4fd0e3a0d92d5571a56f4c7ee5f692ad97e5289e7e"}, {"id": "u024", "kind": "code", "locator": "body:L134-L155", "preview": "```cuda // Store a register value to TMEM // Each thread writes to its own TMEM row at the specified column __device__ void tmem_store_f32(uint32_t tmem_col, float value) { asm volatile( \"tcgen05.st.sync.aligned.32x1b.x1.b32 [%0], {%1};\" : ", "sha256": "8ee021b8d76150fa5fe9547e238730998a762c8f276e95e1fa852e739dbf7382"}, {"id": "u025", "kind": "code", "locator": "body:L159-L182", "preview": "```cuda // Load a single FP32 from TMEM __device__ float tmem_load_f32(uint32_t tmem_col) { float result; asm volatile( \"tcgen05.ld.sync.aligned.32x1b.x1.b32 {%0}, [%1];\" : \"=f\"(result) : \"r\"(tmem_col) ); return result; } // Vectorized load", "sha256": "5cd5f20a3b384f6a3f59d1412c3f1be88f62cf5b86a9681caf9bc9c828f4fb01"}, {"id": "u026", "kind": "code", "locator": "body:L186-L195", "preview": "```cuda // Zero-fill a range of TMEM columns __device__ void tmem_zero(uint32_t tmem_base_col, uint32_t num_cols) { // Each thread zeros its own row for (uint32_t c = 0; c < num_cols; c += 4) { float4 zero = make_float4(0.f, 0.f, 0.f, 0.f);", "sha256": "15e5a029a91cdef685be37048a577786a2fa3fbade814ea22955316225b390bd"}, {"id": "u027", "kind": "prose", "locator": "body:L199-L201", "preview": "The `tcgen05.cp` instruction copies a shaped matrix from shared memory into TMEM. The source operand is a shared-memory matrix descriptor, not a TMEM address.", "sha256": "dee28b3b7fa3a4b8f4900020493fec0e98270193551064a2445dcc3fbe4eb9a2"}, {"id": "u028", "kind": "code", "locator": "body:L203-L206", "preview": "```ptx // Copy a 128x256b shared-memory tile into TMEM. tcgen05.cp.cta_group::1.128x256b [taddr], sdesc; ```", "sha256": "e17e99605a45ed0452be01bea2a86868e7f1292e0305a6b60ce2132909fccbce"}, {"id": "u029", "kind": "prose", "locator": "body:L208-L210", "preview": "The 64-bit register operand `sdesc` is the matrix descriptor representing the source matrix in shared memory. The matrix descriptor format is described in [Matrix Descriptors](https://docs.nvidia.com/cuda/parallel-thread-execution/index.htm", "sha256": "46c231a08a5196493cff2da7f552defbbf23c32e26c0722d41be68e25bc1107b"}, {"id": "u030", "kind": "prose", "locator": "body:L214-L214", "preview": "Double-buffering TMEM accumulators enables overlapping the epilogue of the current tile with the MMA accumulation of the next tile:", "sha256": "755960671f070b38d46bdaaf66d6733b8cb99493150e1e6c0861300fde8571ad"}, {"id": "u031", "kind": "code", "locator": "body:L216-L250", "preview": "```cuda __global__ void double_buffered_gemm(/* ... */) { // Allocate two accumulator buffers uint32_t tmem_acc[2]; tmem_acc[0] = tmem_alloc(256); tmem_acc[1] = tmem_alloc(256); int buf = 0; for (int tile = 0; tile < num_tiles; ++tile) { //", "sha256": "2643142da8b12f116ea2d24d1fcd0640833af539e6f309f58b5f7987b59eb333"}, {"id": "u032", "kind": "prose", "locator": "body:L254-L254", "preview": "With 512 total columns per SM:", "sha256": "c54d0cf39b9707f33d6022aedac3949fcd61dee1ae49258f87f53c667c6e17c0"}, {"id": "u033", "kind": "table-row", "locator": "body:L258-L258", "preview": "| Accumulator Size | Columns | Max Buffers | Remaining for Scratch | | 128x128 FP32 | 128 cols | 4 | 0 |", "sha256": "d3c8bcbe170be7e0fa87e3586a9a4895e9eee077443883e163ba756c48f2d438"}, {"id": "u034", "kind": "table-row", "locator": "body:L259-L259", "preview": "| Accumulator Size | Columns | Max Buffers | Remaining for Scratch | | 128x192 FP32 | 192 cols | 2 | 128 |", "sha256": "5311d980d8f818cbc0f297f9c234f0e78a95fdecbb18160d37f03e4bdee0c009"}, {"id": "u035", "kind": "table-row", "locator": "body:L260-L260", "preview": "| Accumulator Size | Columns | Max Buffers | Remaining for Scratch | | 128x256 FP32 | 256 cols | 2 | 0 |", "sha256": "a8b707eb9a2b10ddf0b6b9e0ccf7e1de5e27f265b3d9b17f096acafd5954cc44"}, {"id": "u036", "kind": "table-row", "locator": "body:L261-L261", "preview": "| Accumulator Size | Columns | Max Buffers | Remaining for Scratch | | 128x256 FP32 (2x) | 512 cols | 2 (double-buf) | 0 |", "sha256": "f6e91576d360ebf9d4404b0cf629c8e620a0188afc21184442c3ece34b38fab4"}, {"id": "u037", "kind": "prose", "locator": "body:L263-L263", "preview": "For double-buffered 128x256 tiles, the full 512 columns are consumed. If additional scratch TMEM is needed (e.g., for softmax in attention kernels), reduce the tile size or use a single accumulator buffer.", "sha256": "3695cf652ed9a7ae68a0152205809028650d423e66fe1e0f54e3b6647fbe5eac"}, {"id": "u038", "kind": "prose", "locator": "body:L267-L267", "preview": "From published Blackwell microbenchmarks:", "sha256": "5cf8af761c70c425dd65df62bb28292ca67bdc79ed264525cac1c432cf16c246"}, {"id": "u039", "kind": "table-row", "locator": "body:L271-L271", "preview": "| Metric | TMEM | SMEM | Registers | | End-to-end latency (cache miss) | ~420 cycles | ~30 cycles | ~4 cycles |", "sha256": "541f73c101fc8fdb339b9e778722b4aea84914271f0beb1c26cd0d32599e765f"}, {"id": "u040", "kind": "table-row", "locator": "body:L272-L272", "preview": "| Metric | TMEM | SMEM | Registers | | Bandwidth for large working sets | High (dedicated bus) | Medium | N/A (limited count) |", "sha256": "caa657b419ec26f522ac1495e31c7ae44a48f56f9c0b0043b46e8b2541bb0d71"}, {"id": "u041", "kind": "table-row", "locator": "body:L273-L273", "preview": "| Metric | TMEM | SMEM | Registers | | Best for | Multi-stage tensor pipelines | Single-shot small matrix | Scalar/vector ALU |", "sha256": "dd6657befb4735390310472437eab4032360a6c38047bb9215d0541b31a94888"}, {"id": "u042", "kind": "prose", "locator": "body:L275-L275", "preview": "TMEM is **not** a replacement for shared memory. Its strength is in serving as a dedicated accumulator buffer that eliminates register pressure for large MMA tiles. SMEM remains faster for small, frequently accessed data.", "sha256": "d55735304756783f161fc2a2f185184977d8f3eebdb61106cdf3355974d5f9ca"}, {"id": "u043", "kind": "prose", "locator": "body:L279-L279", "preview": "In CUTLASS 4.5.0 for SM100, TMEM is managed through CuTe layouts:", "sha256": "3c2510a426c2a42affeb1b979b4dadf96c79311e9eafadae7bae78c70075697a"}, {"id": "u044", "kind": "code", "locator": "body:L281-L299", "preview": "```python # CuTe-DSL example: TMEM accumulator layout # 128 rows x 256 columns, FP32 tmem_layout = Layout( shape=(128, 256), stride=(256, 1), memory_space=MemorySpace.TMEM ) # Allocate TMEM accumulator acc = tmem_alloc(tmem_layout) # Issue ", "sha256": "0ba0404b185224a19cc9daade2232b2f837eb168feca00b7dc7e5baf806c103a"}, {"id": "u045", "kind": "list-item", "locator": "body:L303-L303", "preview": "1. **Forgetting to fence**: Reading TMEM without `tcgen05.fence::before_thread_sync` produces undefined (stale) values.", "sha256": "143fdc7b7fa7d8fbbab195e1809ac5e8d9075995d6b505dbd5b4babdb8d4c244"}, {"id": "u046", "kind": "list-item", "locator": "body:L304-L304", "preview": "2. **Forgetting to deallocate**: In persistent kernels, TMEM must be freed before re-acquiring tiles. Otherwise, the next allocation will fail or hang.", "sha256": "7940af5f024836477638f77f1b32df4e9ad8c4e97c2a60c8ccd7015e7e6ea257"}, {"id": "u047", "kind": "list-item", "locator": "body:L305-L305", "preview": "3. **Exceeding 512 columns**: Attempting to allocate more than the SM's total column budget silently corrupts data or causes a hang.", "sha256": "c3f1f146f2244341ed1a80ecf77d1dda9e0e195c4bf3a2c273cb8e69e0b593dd"}, {"id": "u048", "kind": "list-item", "locator": "body:L306-L306", "preview": "4. **Cross-warp reads**: A thread can only directly read/write TMEM rows mapped to its own lane. Accessing another warp's rows requires explicit shuffle or SMEM staging.", "sha256": "cdbd1c5e6006a337270f3e5820916627a7192a9e9f7dcc6321bf1afab99de243"}, {"id": "u049", "kind": "list-item", "locator": "body:L307-L307", "preview": "5. **Assuming SMEM-like latency**: TMEM has ~420-cycle latency on cache miss vs ~30 cycles for SMEM. Do not use TMEM for low-latency random access patterns.", "sha256": "288e6789b346c4838d36c5e6de97296c9d7bbdb7d5b52fe7c0fd9afae1ba7f63"}], "confidence_claimed": "verified", "headings": ["Overview", "Architecture Layout", "Row-to-Lane Mapping", "Column Addressing", "Allocation and Deallocation Lifecycle", "Allocation", "Deallocation", "Lifecycle in a Persistent GEMM Kernel", "Data Movement Operations", "TMEM Store (Register to TMEM)", "TMEM Load (TMEM to Register)", "TMEM Zero-Fill", "Bulk SMEM -> TMEM Copy via tcgen05.cp", "Double-Buffering with TMEM", "TMEM Budget Considerations", "Microbenchmark Data", "TMEM in the CUTLASS Abstraction", "Common Pitfalls"], "id": "hw-tmem", "path": "wiki/hardware/tmem.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/prs/cutlass/PR-2139.md", "revision": "ca4fdbea", "url": "https://github.com/NVIDIA/cutlass/pull/2139"}, {"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/blogs/colfax-cutlass-blackwell.md", "url": "https://research.colfax-intl.com/cutlass-tutorial-writing-gemm-kernels-using-tmem-for-nvidia-blackwell-gpus/"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["pr-cutlass-2139", "doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "blog-colfax-cutlass"], "title": "Tensor Memory (TMEM)", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "6ab7a73798de1e059f397018969dab63e94f888f714964e75ff05cd82a5ba7a3", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "DeepGEMM is DeepSeek's open-source FP8 GEMM library providing high-performance matrix multiplication with fine-grained per-tile/per-block scaling. The core kernel is remarkably compact (~300 lines), yet achieves approximately 90% utilizatio", "sha256": "a8d2a63a99bebfefa1d442816e777fd4993a76b2b6891efb7b5cf1c0e86247fa"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "The key innovation is the fine-grained quantization scheme: tile-wise 1x128 scaling for activations and block-wise 128x128 scaling for weights, which prevents outlier values from destroying quantization precision.", "sha256": "c4ba436e75f16ea764cfc683753058a613b3a238e14683fb7cc9ae7664ea5a79"}, {"id": "u003", "kind": "code", "locator": "body:L11-L26", "preview": "``` Activations (tile-wise 1x128): +-----------+-----------+-----------+ | tile 0 | tile 1 | tile 2 | <-- each tile: 1 row x 128 cols | scale: s0 | scale: s1 | scale: s2 | <-- one FP32 scale per tile +-----------+-----------+-----------+ We", "sha256": "d93511b513794a4053872786d7fea8bc68a94d3f20e75bfac7e89b0c22949d71"}, {"id": "u004", "kind": "prose", "locator": "body:L30-L30", "preview": "On Hopper, the Tensor Core accumulator has limited precision (~FP22, not true FP32). DeepGEMM mitigates this by promoting partial sums to a separate FP32 accumulator on CUDA Cores every Nc=128 columns (4 consecutive WGMMA operations).", "sha256": "9c15e3efb8345068a4e571d1f8ff8e56f809ad0c576f270f36448743ce1b21bd"}, {"id": "u005", "kind": "code", "locator": "body:L32-L56", "preview": "```cpp // SM90 path: WGMMA with Nc=128 CUDA Core promotion // Every 4 WGMMAs, promote accumulated result to FP32 CUDA core accumulator constexpr int Nc = 128; // Promotion interval (4 WGMMAs of n=32 each) constexpr int WGMMA_N = 32; float c", "sha256": "76c18f0941acc2599a798e6fb89e18a4662459103586fab64ef904330448ba85"}, {"id": "u006", "kind": "prose", "locator": "body:L58-L58", "preview": "On Blackwell (SM100), the tcgen05.mma instruction with TMEM accumulation uses native UE8M0 block scaling, which eliminates the need for explicit CUDA core promotion.", "sha256": "f573a6c1e1314f88b335649408b8c3740ce346d70a241c625957ac8d9da3c134"}, {"id": "u007", "kind": "code", "locator": "body:L60-L77", "preview": "```cpp // SM100 path: tcgen05.mma with native block scaling // Scaling factors packed as UE8M0 (4 values per uint32) // No explicit CUDA core promotion needed -- TMEM accumulates in full precision // Pack 4 UE8M0 scale factors into a single", "sha256": "293b0c704fe4d4a1d0b6d1b9e1b0e0ddf0d888333d891bef4840d272b11a2924"}, {"id": "u008", "kind": "prose", "locator": "body:L81-L81", "preview": "DeepGEMM provides three grouped GEMM layouts tailored for MoE workloads, where only the M-axis varies (different token counts per expert) while N and K remain fixed:", "sha256": "7241e0e422e17cd845f7f170d2bdd64ee4a1380df37e3cbf7c65b49eb309c456"}, {"id": "u009", "kind": "code", "locator": "body:L83-L97", "preview": "``` Layout 1: Contiguous (prefill) Expert 0: M0 tokens \u2500\u2500\u2510 Expert 1: M1 tokens \u2500\u2500\u2524\u2500\u2500 All packed contiguously in memory Expert 2: M2 tokens \u2500\u2500\u2518 Index array stores cumulative offsets Layout 2: Masked (decode with CUDA graphs) Fixed-size M_max", "sha256": "fc79df6a9d5cdd9a7ece814a283d8e01fa10196c57d975ef3d612e359a48fca5"}, {"id": "u010", "kind": "code", "locator": "body:L99-L120", "preview": "```cpp // Contiguous grouped GEMM dispatch // problem_sizes[i] = {M_i, N, K} for expert i void grouped_gemm_contiguous( const fp8_t* A, // All expert inputs packed const fp8_t* B, // Expert weights [num_experts, N, K] float* C, // Output pa", "sha256": "520bdbcf6f6e8502b04f62de8fce42d70be93ecc020f3c968cd18e86c9f7ee9b"}, {"id": "u011", "kind": "prose", "locator": "body:L124-L124", "preview": "DeepGEMM uses JIT compilation via NVRTC to specialize kernels per problem shape at runtime. This avoids the combinatorial explosion of pre-compiled template instantiations while still achieving optimal register allocation and loop unrolling", "sha256": "94d6fa2e6a32682433878b4e885151f03f04e006f05e66573a94db82ee1cbfcf"}, {"id": "u012", "kind": "code", "locator": "body:L126-L135", "preview": "```cpp // Lightweight JIT module: compile per-shape kernel at first call auto kernel = jit_compile( \"deepgemm_fp8\", {{\"M\", M}, {\"N\", N}, {\"K\", K}, {\"BLOCK_M\", 128}, {\"BLOCK_N\", 128}, {\"BLOCK_K\", 64}, {\"NUM_STAGES\", 4}} ); kernel.launch(A, B", "sha256": "bf4564c2ce415f9cc17b70d95058bf550db89fb8c1ea7fb1d52d06eba47fa1b7"}, {"id": "u013", "kind": "prose", "locator": "body:L139-L139", "preview": "SM90 kernels use NT (non-transposed A, transposed B) layout exclusively. SM100 kernels support all four layout combinations (NT, TN, NN, TT), enabled by tcgen05.mma's flexible operand addressing.", "sha256": "05e8aef45f50114e87d41ef4d00785e0e233b9ce01f96905df75b623787c4f0b"}, {"id": "u014", "kind": "table-row", "locator": "body:L145-L145", "preview": "| GPU | Dtype | Shape | TFLOPS | Utilization | | H800 | FP8 | M=4096, N=4096, K=4096 | 1550 | ~90% |", "sha256": "35557e2b596d7ffc30ecb13e62410388d70dc24b8b8e53f4d5396dfa7dfea217"}, {"id": "u015", "kind": "list-item", "locator": "body:L149-L149", "preview": "- FP8 inference and training where per-tensor quantization loses too much precision", "sha256": "28fc6d00d397c186fce8b4e63d7337236e851101ea5282fe5218d4b457f8367b"}, {"id": "u016", "kind": "list-item", "locator": "body:L150-L150", "preview": "- MoE expert computation with variable token counts per expert", "sha256": "50dcb33f867867ef5ad18456f5f927f4b15d2b162d8a7c0fd03d2ec3acd3e912"}, {"id": "u017", "kind": "list-item", "locator": "body:L151-L151", "preview": "- Situations where fine-grained (1x128 / 128x128) scale granularity is needed", "sha256": "160e602b4b8581b7d13641470ab5613a85b812908295724e6442eecced745c83"}, {"id": "u018", "kind": "list-item", "locator": "body:L155-L155", "preview": "- SM90 path is NT layout only", "sha256": "9242fed0fecfc245df263c39c8b5bbae0d85924bce7de6ac51f5b18c72206f55"}, {"id": "u019", "kind": "list-item", "locator": "body:L156-L156", "preview": "- JIT compilation adds first-call latency (amortized over repeated calls)", "sha256": "6bf333ad0b302cdf27143198ae0a599783cca43214551c605667e4a85464b62f"}, {"id": "u020", "kind": "list-item", "locator": "body:L157-L157", "preview": "- Fine-grained scaling adds overhead vs. per-tensor scaling -- only beneficial when outlier sensitivity matters", "sha256": "1df067738a5ce600f8b91e79dd401fa8ed56018d21a26254c55fc42d93be97a9"}, {"id": "u021", "kind": "list-item", "locator": "body:L161-L161", "preview": "- [DeepGEMM GitHub](https://github.com/deepseek-ai/DeepGEMM)", "sha256": "65a890a7f2ec2e89aca5859abdbc58506d62e5385f789c53eb2add7c496af832"}, {"id": "u022", "kind": "list-item", "locator": "body:L162-L162", "preview": "- [DeepSeek-V3 Technical Report](https://arxiv.org/abs/2412.19437)", "sha256": "3dfa696da6a70082a6d2bcf3de53c8b3f99268e1e5077bb0cc37c01d3ad61f81"}, {"id": "u023", "kind": "prose", "locator": "body:L166-L166", "preview": "Local verbatim upstream code lives in [`artifacts/kernels/deepgemm/full/`](../../artifacts/kernels/deepgemm/full/) (see its `PROVENANCE.yaml` for the pinned upstream SHA and byte-verified SHA-256). Labeled derived variants \u2014 including a nai", "sha256": "feef483a886f122edecb06278ab03c3ebcd3d6ffbaea062e73d8924999c9d783"}, {"id": "u024", "kind": "prose", "locator": "body:L168-L168", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u025", "kind": "code", "locator": "body:L170-L172", "preview": "```bash python3 scripts/get_page.py kernel-deepgemm --include-code ```", "sha256": "a2051b59354d2536049b6650555806c0410635aa728921831a30c1e1855977b1"}, {"id": "u026", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"fp8\", \"gpu\": \"H800\", \"metric\": \"TFLOPS\", \"shape\": \"M=4096, N=4096, K=4096\", \"source_id\": \"blog-deepgemm\", \"utilization\": \"~90%\", \"value\": 1550}]", "sha256": "50acfcee975b0c85babf42af9824ad87b9a57ae6fc4f57ef46f5f9d786e6c456"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Fine-Grained Quantization Scheme", "FP8 Accumulation with Nc=128 CUDA Core Promotion", "MoE Grouped GEMM Layouts", "JIT Compilation", "Memory Layout", "Performance", "When to Use", "Caveats", "Sources", "Full Reference Implementation"], "id": "kernel-deepgemm", "path": "wiki/kernels/deepgemm.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/blogs/deepgemm.md", "url": "https://github.com/deepseek-ai/DeepGEMM"}, {"path": "sources/prs/DeepGEMM/PR-304.md", "revision": "7f2a703e", "url": "https://github.com/deepseek-ai/DeepGEMM/pull/304"}, {"path": "sources/prs/cutlass/PR-2139.md", "revision": "ca4fdbea", "url": "https://github.com/NVIDIA/cutlass/pull/2139"}, {"path": "sources/prs/vllm/PR-23696.md", "revision": "074854b2", "url": "https://github.com/vllm-project/vllm/pull/23696"}], "risk_flags": ["code", "performance", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-deepgemm", "pr-deepgemm-304", "pr-cutlass-2139", "pr-vllm-23696"], "title": "DeepGEMM \u2014 FP8 GEMM with Fine-Grained Scaling", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "77d451b38127be1f61669e4237971c0e4da24687371dfdf76f65ec1cafc8ce16", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "FlashAttention-4 is the Blackwell-native evolution of the FlashAttention family, designed to exploit SM100 architectural features that break the Hopper-era bottleneck: tensor core throughput doubles on Blackwell, but SFU (Special Function U", "sha256": "9b0953e53cf887a5e006116e1977892545caa6a73a7b6e557f731ba3580c83ab"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "Written entirely in CuTe DSL (Python), FA4 compiles 20-30x faster than equivalent CUTLASS C++ template code while matching or exceeding cuDNN performance.", "sha256": "52b12af69020638db58d9c24265863227ea3830899d77e8b96c74027c7b4f5e6"}, {"id": "u003", "kind": "prose", "locator": "body:L13-L13", "preview": "Two 128-token query tiles are assigned to each CTA. While one tile's matmul runs on the tensor cores, the other tile's softmax rescaling runs on dedicated warpgroups accessing TMEM. This hides the softmax latency behind MMA compute.", "sha256": "925633f5092e28d0b44f9a3b8bce3149835cadbe619837956bebfe0cbd4d5e26"}, {"id": "u004", "kind": "code", "locator": "body:L15-L44", "preview": "```python # CuTe DSL: Ping-pong tile scheduling (simplified) # Two query tiles per CTA, alternating MMA and softmax phases @cute.kernel def flash_attention_4_fwd(Q, K, V, O, L): # Each CTA processes 2 query tiles of 128 tokens TILE_Q = 128 ", "sha256": "7666e637f6ed7da795bb4dff76027002d544c9b4d934bd69dea26ab64cf75b88"}, {"id": "u005", "kind": "prose", "locator": "body:L48-L48", "preview": "The SFU `ex2` instruction is the bottleneck on Blackwell -- its throughput does not scale with the doubled tensor core rate. FA4 replaces it with a software exponential distributed across FMA units using Cody-Waite range reduction and Horne", "sha256": "2643816f2f447197fe2b11b0c43b92015871517116f19bf78720fd0dd7c5d422"}, {"id": "u006", "kind": "code", "locator": "body:L50-L71", "preview": "```python # Software exp2 via Cody-Waite range reduction + Horner polynomial # Distributes across FMA units instead of using scarce SFU hardware def software_exp2(x): \"\"\" Compute 2^x using FMA units instead of SFU ex2. Cody-Waite range redu", "sha256": "c36af9db7eeb181976fbac7f527f533e979468cb6842f20004d6e803d231f867"}, {"id": "u007", "kind": "prose", "locator": "body:L73-L73", "preview": "This gives roughly 4x throughput improvement over the hardware SFU path by utilizing FMA units that would otherwise be idle during softmax phases.", "sha256": "0e89570d53c2eb1b8a6f2606e4d1ef4e3aac5ee0c441ad4fdc5e9ab92f7381c1"}, {"id": "u008", "kind": "prose", "locator": "body:L77-L77", "preview": "Standard FlashAttention rescales the output accumulator every KV block. FA4 only rescales when the running maximum changes significantly (large jump), reducing non-matmul operations.", "sha256": "97cead2edc1a48624b7a8dc30714d14d48945d350c28c9793dc00ccb0767d45b"}, {"id": "u009", "kind": "code", "locator": "body:L79-L89", "preview": "```python # Only rescale when max changes substantially def conditional_rescale(O_acc, lse_old, lse_new, threshold=2.0): diff = lse_new - lse_old if abs(diff) > threshold: # Full rescale: O_acc *= exp(lse_old - lse_new) scale = software_exp", "sha256": "b320635ad54fadb2cca2dd471dc6f5d60a10f26bc5587445d001b4cac3f4c3c2"}, {"id": "u010", "kind": "prose", "locator": "body:L93-L93", "preview": "The backward pass spans two paired CTAs in a cluster, sharing TMEM across both SMs. This halves shared memory traffic for the dQ/dK/dV gradient computation.", "sha256": "12b84d12d96eed54674f74afaaf70f0aef1766ac205d8b06eb190f7b0b79a0a1"}, {"id": "u011", "kind": "code", "locator": "body:L95-L118", "preview": "```python # 2-CTA backward: paired CTAs share TMEM via 2-SM cooperative mode @cute.kernel def flash_attention_4_bwd(Q, K, V, O, dO, dQ, dK, dV): # Two CTAs cooperate: CTA_0 and CTA_1 in same cluster # tcgen05.mma shape: m256 x n256 x k16 (2", "sha256": "ff7924910f277cb5b3ecff18d818eb589a47ea4855d8c9bc3d5495b877456a65"}, {"id": "u012", "kind": "table-row", "locator": "body:L124-L124", "preview": "| Configuration | GPU | Dtype | TFLOPS | Utilization | vs cuDNN | vs Triton | | seqlen=8192, headdim=128 | B200 | BF16 | 1605 | 71% | 1.1-1.3x | 2.1-2.7x |", "sha256": "6962734852d85358e18b1580efb516e1fb886a8739ce880d0f5179af53aec301"}, {"id": "u013", "kind": "prose", "locator": "body:L126-L126", "preview": "The 71% MMA utilization represents the state of the art for attention kernels on Blackwell. The remaining 29% is consumed by softmax, rescaling, and memory transfers.", "sha256": "f69e67b4954d8634c2b154ac59c7dcbc7850a49a75cebc22e400ab5ea31a060f"}, {"id": "u014", "kind": "list-item", "locator": "body:L130-L130", "preview": "- Written entirely in CuTe DSL (Python), not C++ templates", "sha256": "ddc4f7b4ac032a05d5b1e20a695fe1019481c985ceaa7f3b23edc29eef10d8e6"}, {"id": "u015", "kind": "list-item", "locator": "body:L131-L131", "preview": "- 20-30x faster compilation than equivalent CUTLASS C++ code", "sha256": "47dcc6af677ae0ef013987c83c405a6bd4d69b83f175098b26bdd9b1a9b0a7de"}, {"id": "u016", "kind": "list-item", "locator": "body:L132-L132", "preview": "- Uses `SM100_MMA_SS` atoms for tcgen05 MMA from shared memory", "sha256": "e84f75170575d1a78d5555d626c10b63bb1ca29a98a89d203e35950fddfdf737"}, {"id": "u017", "kind": "list-item", "locator": "body:L133-L133", "preview": "- TMEM locality via `TMEM` locale in CuTe layout", "sha256": "1ae4b375dcf68caefcb340b49545b0da30041f6de9f7c6168d5780104723cd14"}, {"id": "u018", "kind": "list-item", "locator": "body:L134-L134", "preview": "- TMA bulk loads for Q, K, V tiles into shared memory", "sha256": "860c155b25d7768c369088a26464652fdfa6a5579302a77f11d21ee020e01225"}, {"id": "u019", "kind": "list-item", "locator": "body:L138-L138", "preview": "- Standard multi-head attention on Blackwell with sequence lengths >= 1024", "sha256": "59bbc439d9a1636d54941577b6174c932a83ba841e379886de3f4942d71c5102"}, {"id": "u020", "kind": "list-item", "locator": "body:L139-L139", "preview": "- Both forward and backward passes", "sha256": "89fa7a2d45ca8f5ce63af39173e002df2ecc4a408579bce35e8929eab4ce7b10"}, {"id": "u021", "kind": "list-item", "locator": "body:L140-L140", "preview": "- BF16 precision (FP8 support planned)", "sha256": "1105010c1d9bb18ee8a54657462a3467d9a0aed06cb0514e5178354c0bf09b60"}, {"id": "u022", "kind": "list-item", "locator": "body:L144-L144", "preview": "- SM100 only -- no fallback to SM90", "sha256": "3472ae56bcd8f2f143fc6d287d217acc7bdc1f9abf6aa73e67b8b76c843499bc"}, {"id": "u023", "kind": "list-item", "locator": "body:L145-L145", "preview": "- Requires CuTe DSL toolchain (CUTLASS 4.5.0 + Python frontend)", "sha256": "c154f380fc0fe531fc5e3a100c6e3458546b3641e7e3b3dad068f755dfca474f"}, {"id": "u024", "kind": "list-item", "locator": "body:L146-L146", "preview": "- Ping-pong scheduling most effective for headdim=128; smaller headdims may not fully overlap", "sha256": "3c1ef25ac05c585ea24dd1bf2cdc3acc44763db2c246565a124b68b10f2cd978"}, {"id": "u025", "kind": "list-item", "locator": "body:L150-L150", "preview": "- [FlashAttention-4 paper](https://arxiv.org/abs/2603.05451)", "sha256": "9f406a72f6a287a830c318fdac7d4239484228c7e537b1c5b2fa3ba8b0b942bc"}, {"id": "u026", "kind": "list-item", "locator": "body:L151-L151", "preview": "- [Tri Dao's blog](https://tridao.me/blog/2026/flash4/)", "sha256": "a2b86b74ede2bcca82aba3e317b7a1d97380b981b3cc5576bf569933eb6259e9"}, {"id": "u027", "kind": "prose", "locator": "body:L155-L155", "preview": "Local verbatim upstream code lives in [`artifacts/kernels/flash-attention-4/full/`](../../artifacts/kernels/flash-attention-4/full/) (see its `PROVENANCE.yaml` for the pinned upstream SHA and byte-verified SHA-256). Labeled derived variants", "sha256": "c4f50ec45f2fa4675b2ce857375ea3fd0e581ea2d898f2dd5cef280ac619e5de"}, {"id": "u028", "kind": "prose", "locator": "body:L157-L157", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u029", "kind": "code", "locator": "body:L159-L161", "preview": "```bash python3 scripts/get_page.py kernel-flash-attention-4 --include-code ```", "sha256": "dbaa5f540bdab5755bcdb9295bc1637f3e10a533091792abfe6b693678d4bd54"}, {"id": "u030", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"bf16\", \"gpu\": \"B200\", \"metric\": \"TFLOPS\", \"shape\": \"seqlen=8192, headdim=128\", \"source_id\": \"doc-flash-attention-4\", \"utilization\": \"71%\", \"value\": 1605}]", "sha256": "f274c3701fa6d3f96f744a8977af3779a850e9dc415a6471d74e9596a90f54ad"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Key Techniques", "Ping-Pong Scheduling", "Software-Emulated Exponential (Cody-Waite)", "Conditional Softmax Rescaling", "2-CTA Backward Pass", "Performance", "Implementation Notes", "When to Use", "Caveats", "Sources", "Full Reference Implementation"], "id": "kernel-flash-attention-4", "path": "wiki/kernels/flash-attention-4.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/docs/flash-attention-4.md", "url": "https://arxiv.org/abs/2603.05451"}, {"path": "sources/blogs/flash-attention-4.md", "url": "https://tridao.me/blog/2026/flash4/"}, {"path": "sources/prs/flashinfer/PR-1850.md", "revision": "f3ea938d", "url": "https://github.com/flashinfer-ai/flashinfer/pull/1850"}], "risk_flags": ["code", "performance", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-flash-attention-4", "blog-flash-attention-4", "pr-flashinfer-1850"], "title": "FlashAttention-4", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "260bbec945acf25551df5b9232d692574dbde84aca2aa0e9b3b73972a38e7239", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L5", "preview": "FlashAttention PR 2441 adds an SM100 CuTe DSL forward path for MLA shapes with top-k sparsity. It is useful when an attention candidate has to combine page/KV layout handling, sparse top-k selection, and tiled forward scheduling.", "sha256": "5b2a5695b8f63367ef67ed87e2c3d9aab1878e749434e3ad69d7b08b5eb1eee3"}, {"id": "u002", "kind": "code", "locator": "body:L7-L16", "preview": "```python # Query pattern before borrowing implementation details: # open PR page, then inspect the source snapshot or upstream files listed there. from pathlib import Path pr_page = Path(\"sources/prs/flash-attention/PR-2441.md\") text = pr_", "sha256": "883d6f46c292014d663c3f52b9471f58468f6614a2b542c9cf01fc833a16ca36"}, {"id": "u003", "kind": "list-item", "locator": "body:L20-L20", "preview": "- Treat top-k gather and tiled attention scheduling as separate evidence paths.", "sha256": "f8429a4f72652ef153895da287a4f4cb3da39e4e739730723cec5c6c7b9d18e5"}, {"id": "u004", "kind": "list-item", "locator": "body:L21-L21", "preview": "- Profile memory traffic separately from tensor-pipe utilization; sparse top-k", "sha256": "32621556168400705292cc982eb59230a0f7d41e759f84276eed20766c1997c7"}, {"id": "u005", "kind": "prose", "locator": "body:L22-L22", "preview": "routing can improve arithmetic work while worsening gather locality.", "sha256": "fb624f89638f7a84774c56c64f1da644eb9b53dfc773d8e2acf9fb0d6bffef9c"}, {"id": "u006", "kind": "list-item", "locator": "body:L23-L23", "preview": "- Keep full-workload validation because the useful path is shape-specific.", "sha256": "67caa0c749179d3793f4380630451f8f5fda453edefd32337a34f45ae1fdb3ef"}, {"id": "u007", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"bf16\", \"gpu\": \"B200\", \"metric\": \"latency_ms\", \"shape\": \"batch=512, seqlen_q=1, seqlen_k=16384, nheads=128, topk=2048\", \"source_id\": \"pr-flash-attention-2441\", \"value\": 0.3}]", "sha256": "cdce381f09b14524299a1e5659ab44862e8d4f5fade3c85abd6fb6d2d9f64433"}], "confidence_claimed": "source-reported", "headings": ["Shape", "Transfer Notes"], "id": "kernel-flash-attention-sm100-mla-topk", "path": "wiki/kernels/flash-attention-sm100-mla-topk.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/prs/flash-attention/PR-2441.md", "revision": "f219c89c", "url": "https://github.com/Dao-AILab/flash-attention/pull/2441"}, {"path": "sources/prs/flash-attention/PR-1236.md", "revision": "a5a75274", "url": "https://github.com/Dao-AILab/flash-attention/pull/1236"}], "risk_flags": ["code", "performance"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["pr-flash-attention-2441", "pr-flash-attention-1236"], "title": "FlashAttention SM100 MLA TopK Sparse Forward", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "997be90a5a387c776857d0d8257d24915a19a1aa829e9d76940c4de57a311691", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "FlashMLA provides high-performance kernels for DeepSeek's Multi-head Latent Attention (MLA) mechanism, which compresses the KV cache from 327-516 KB/token (standard MHA) down to 70 KB/token through a learned low-rank projection into a laten", "sha256": "5c822310054b84ac1323f2fce8c15ca31f81ee4dd10df733fc91c208ad976232"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "FlashMLA includes four kernel variants: dense MLA decoding (SM90), sparse MLA decoding (SM90/SM100), dense MLA prefill (SM100), and sparse MLA prefill (SM90/SM100).", "sha256": "d080df26678f751d47af04d6d608e8549d7d1c383fcb88bf41d032dfe201a1db"}, {"id": "u003", "kind": "prose", "locator": "body:L11-L11", "preview": "Each token in the MLA KV cache occupies 656 bytes:", "sha256": "f2f47735cbdf52ac4acdacbe741fefe753b72fdfc4a247f85043475331a890d6"}, {"id": "u004", "kind": "code", "locator": "body:L13-L24", "preview": "``` Token KV Cache Entry (656 bytes total): +------------------------------------------+ | FP8 compressed KV data | 512 bytes | <-- Latent KV representation | FP32 scaling factors | 16 bytes | <-- Per-head scales | BF16 RoPE embeddings | 12", "sha256": "89d9c266e614ff13a77c505bba3b2e26dfe33b22ad01aba5951c3ed43078fbae"}, {"id": "u005", "kind": "prose", "locator": "body:L28-L28", "preview": "The decode kernel targets memory-bound inference with paged KV cache (block size 64). It achieves up to 3000 GB/s memory bandwidth and 660 TFLOPS on H800.", "sha256": "abd1e2cda37cb941ee97e0a7d13d872eedff8a86329d27448e564bb8fec29009"}, {"id": "u006", "kind": "code", "locator": "body:L30-L87", "preview": "```cpp // Dense MLA decode kernel structure (SM90, BF16) // Memory-bound: bandwidth utilization is the primary metric template __global__ void flashmla_decode_dense( const half* __restrict__ Q, // [batch, num_he", "sha256": "a682b48ee911477e44d4c23e59d9410ba5f33cacb147631ac8a1b32be199d12c"}, {"id": "u007", "kind": "prose", "locator": "body:L91-L91", "preview": "Sparse MLA uses token-level sparsity indices to select only relevant tokens from the KV cache, dramatically reducing memory reads for long sequences.", "sha256": "c190eb957a5b28eac21b8ad97aae18af707091eecd191bae41ee510f32939c85"}, {"id": "u008", "kind": "code", "locator": "body:L93-L118", "preview": "```cpp // Sparse MLA: only attend to selected tokens via indices tensor // Each query has a variable-length list of relevant token indices template __global__ void flashmla_sparse( const half* Q, const int8_t* KV_cache, const", "sha256": "3edadab965d70904078cdd953813465c227e84e1f40629a89ec46d03fee6da7a"}, {"id": "u009", "kind": "prose", "locator": "body:L122-L122", "preview": "The SM100 prefill kernel leverages tcgen05.mma and TMEM for the compute-heavy forward and backward passes, achieving 1460 TFLOPS forward and 1000 TFLOPS backward on B200.", "sha256": "14f5a5c36db81c0a0b73f2012640b0f050dfde1121803b819b299fbbbc675374"}, {"id": "u010", "kind": "code", "locator": "body:L124-L137", "preview": "```cpp // SM100 dense prefill: tcgen05.mma with TMEM accumulation // Uses warp specialization: TMA warps + MMA warps + softmax warps // Forward pass structure: // 1. TMA loads Q, K, V tiles into SMEM // 2. tcgen05.mma computes S = Q @ K^T i", "sha256": "9485e9e48663e357c817de8527441131cebc39f4070505835636b5afa49b05ea"}, {"id": "u011", "kind": "table-row", "locator": "body:L143-L143", "preview": "| Variant | GPU | Dtype | TFLOPS | Bandwidth | | Dense decode | H800 | BF16 | 660 | 3000 GB/s |", "sha256": "197d3af7af1392df6bc60beac97dc6141f4822fae2ed7bef5cb6fc19abbc1182"}, {"id": "u012", "kind": "table-row", "locator": "body:L144-L144", "preview": "| Variant | GPU | Dtype | TFLOPS | Bandwidth | | Sparse decode | H800 | FP8 | 410 | -- |", "sha256": "df77b8afeebe556693f767543d2ce0a5151a56c8635f12a0f93c3b9d5ec3fd10"}, {"id": "u013", "kind": "table-row", "locator": "body:L145-L145", "preview": "| Variant | GPU | Dtype | TFLOPS | Bandwidth | | Sparse decode | B200 | FP8 | 350 | -- |", "sha256": "c6f1624e88ed3a224f4a8c19e26ca427db6be8fed070c8f5a7f6456fccc98d7b"}, {"id": "u014", "kind": "table-row", "locator": "body:L146-L146", "preview": "| Variant | GPU | Dtype | TFLOPS | Bandwidth | | Dense prefill fwd | B200 | BF16 | 1460 | -- |", "sha256": "197f4275f2153525fe6c29856133069bfcf0b2b0b7e185d06926c2faedae1d2e"}, {"id": "u015", "kind": "table-row", "locator": "body:L147-L147", "preview": "| Variant | GPU | Dtype | TFLOPS | Bandwidth | | Dense prefill bwd | B200 | BF16 | 1000 | -- |", "sha256": "cca8784085dc070f755942a7a13864c15372b5d457308daa51abd639a9bda4d3"}, {"id": "u016", "kind": "table-row", "locator": "body:L148-L148", "preview": "| Variant | GPU | Dtype | TFLOPS | Bandwidth | | Sparse prefill | H800 | FP8 | 640 | -- |", "sha256": "b4bdb3f350765356754cd1adc3380b15b1fa7f26b7ded6bdad645a49867bfc3c"}, {"id": "u017", "kind": "table-row", "locator": "body:L149-L149", "preview": "| Variant | GPU | Dtype | TFLOPS | Bandwidth | | Sparse prefill | B200 | FP8 | 1450 | -- |", "sha256": "24d883fc955859e9b99f29c08774ee5b0383ae35b4ff6fd6d0b8f2235623b094"}, {"id": "u018", "kind": "prose", "locator": "body:L153-L153", "preview": "FlashMLA is deployed in production for DeepSeek-V3 and V3.2 inference:", "sha256": "458d3ece0d5d3dfb49c61924d6b9c62fb61899172028d5633c40615d922071ce"}, {"id": "u019", "kind": "list-item", "locator": "body:L154-L154", "preview": "- SGLang and vLLM provide day-0 support", "sha256": "7f6dcb5012cdbeb67f178cc26993598bbbc549996a57905afd1671e721f83a41"}, {"id": "u020", "kind": "list-item", "locator": "body:L155-L155", "preview": "- CUTLASS SM100 includes MLA attention kernels with fused reduction", "sha256": "b11bea427d01afa052da4099cf7ff91b6334ac3f592bc6423db6cb25f28b1573"}, {"id": "u021", "kind": "list-item", "locator": "body:L156-L156", "preview": "- FlashMLA sparse kernels are used by DeepSeek-V3.2-Exp with NSA", "sha256": "ad5f6f5e1aaa252218922911811f597961b522854eb6f84308b2afd22863c881"}, {"id": "u022", "kind": "list-item", "locator": "body:L160-L160", "preview": "- DeepSeek-V3/V3.2 model serving with MLA architecture", "sha256": "46d7045c00210396473c864c2efdbc4a00ee40adf4e347bfc97ff22acdd39b92"}, {"id": "u023", "kind": "list-item", "locator": "body:L161-L161", "preview": "- Long-context inference where KV cache size is the bottleneck", "sha256": "5f3a4c10312c5ec50d36fe8c212bd8edd54082e30e39716126e254db36afd2db"}, {"id": "u024", "kind": "list-item", "locator": "body:L162-L162", "preview": "- Combined with NSA for sparse attention on long sequences", "sha256": "41f2b64b5832328df8e380cfc8567e46dc32bed6d53e5e392ebb59d7442d6874"}, {"id": "u025", "kind": "list-item", "locator": "body:L166-L166", "preview": "- MLA-specific: the latent KV cache format (656 bytes/token) is tied to DeepSeek's architecture", "sha256": "679c0568d6dd56f6266cec07f18dcf6128aeef25cc708cba3145fdd6c8b8c654"}, {"id": "u026", "kind": "list-item", "locator": "body:L167-L167", "preview": "- Dense prefill is SM100 only", "sha256": "874d57764d5289067bfa3b8fd141e8985d2bd436759a00e84f53de002112e306"}, {"id": "u027", "kind": "list-item", "locator": "body:L168-L168", "preview": "- Sparse MLA requires a separate indexing pass to select relevant tokens", "sha256": "47b8d4390270944fea84110df7d2f3cfe2bc863e4ec176706355eae3214707d9"}, {"id": "u028", "kind": "list-item", "locator": "body:L172-L172", "preview": "- [FlashMLA GitHub](https://github.com/deepseek-ai/FlashMLA)", "sha256": "5a106152b29dc94b7e6ce4ef1ab60defc4e6048b0255d0c04ac1850606241fef"}, {"id": "u029", "kind": "list-item", "locator": "body:L173-L173", "preview": "- [DeepSeek-V3 Technical Report](https://arxiv.org/abs/2412.19437)", "sha256": "3dfa696da6a70082a6d2bcf3de53c8b3f99268e1e5077bb0cc37c01d3ad61f81"}, {"id": "u030", "kind": "list-item", "locator": "body:L174-L174", "preview": "- [CUTLASS SM100 Attention Changelog](https://docs.nvidia.com/cutlass/latest/CHANGELOG.html)", "sha256": "664bebe8ae6fce0de8bc7a4b5ba5298ee80b4860fa12b9164bf63edf5917330f"}, {"id": "u031", "kind": "prose", "locator": "body:L178-L178", "preview": "Verbatim upstream code lives in [`artifacts/kernels/flashmla/full/`](../../artifacts/kernels/flashmla/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live in [`artifacts/", "sha256": "2007b85399ec2dbf6a3ca197e2b2862e13aaf17d7de10e3c535fd62c940da819"}, {"id": "u032", "kind": "prose", "locator": "body:L180-L180", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u033", "kind": "code", "locator": "body:L182-L184", "preview": "```bash python3 scripts/get_page.py kernel-flashmla --include-code ```", "sha256": "dadf39bd144b46ea08111137b1703964d608f765fb8cef09eaa6dbb70e0fc8a3"}, {"id": "u034", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"bf16\", \"gpu\": \"B200\", \"metric\": \"TFLOPS\", \"shape\": \"dense prefill, variable seqlen\", \"source_id\": \"blog-flashmla\", \"utilization\": \"~65%\", \"value\": 1460}, {\"dtype\": \"fp8\", \"gpu\": \"B200\", \"metric\": \"TFLOPS\", \"shape\": \"sparse prefi", "sha256": "e1c7ff2789d15fa0705d455a48d1581f086d21044f3d95740e8332588074f7b0"}], "confidence_claimed": "source-reported", "headings": ["Overview", "MLA KV Cache Layout", "Dense MLA Decoding (SM90)", "Sparse MLA (SM90/SM100)", "Dense Prefill (SM100)", "Performance", "Architecture Integration", "When to Use", "Caveats", "Sources", "Full Reference Implementation"], "id": "kernel-flashmla", "path": "wiki/kernels/flashmla.md", "performance_claim_count": 2, "resolved_sources": [{"path": "sources/blogs/flashmla.md", "url": "https://github.com/deepseek-ai/FlashMLA"}, {"path": "sources/prs/flashinfer/PR-1117.md", "revision": "2f01a9a3", "url": "https://github.com/flashinfer-ai/flashinfer/pull/1117"}, {"path": "sources/prs/vllm/PR-39752.md", "revision": "dc8df110", "url": "https://github.com/vllm-project/vllm/pull/39752"}], "risk_flags": ["code", "performance", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-flashmla", "pr-flashinfer-1117", "pr-vllm-39752"], "title": "FlashMLA \u2014 Multi-head Latent Attention", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "9fc01ec2833f70fa337f1ec2f149ac72e477d8465563010c15b1aa7c0c2bcc50", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "FP8 GEMM with fine-grained block scales (128x128 weights, 1x128 activations). Preserves more dynamic range than per-tensor FP8 scaling, critical for LLM inference and training where outliers dominate quantization error.", "sha256": "9d0666c67654f6a8b7b399172817ee68fa4331b82656fc526f42991227b211ce"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "DeepGEMM is the reference implementation; CUTLASS provides SM100 schedules.", "sha256": "9f5c051584170558eee2213d61be656ab3de3338eb3b298739325bc8680965aa"}, {"id": "u003", "kind": "code", "locator": "body:L11-L20", "preview": "``` Activations: tile-wise 1x128 scales [1x128 values] \u2192 1 scale factor (FP32 or FP8 E4M3) Weights: block-wise 128x128 scales [128x128 values] \u2192 1 scale factor per block Output accumulator: FP32 Multiply A \u00d7 B in FP8, accumulate in FP32, ap", "sha256": "8eb5ef399e8b9c6f8f70ce7545d68e9df8420e15fca16752b39be30dbbefdf17"}, {"id": "u004", "kind": "code", "locator": "body:L24-L44", "preview": "```cuda // Hopper accumulator has ~22-bit precision (FP22) // Every Nc=128 WGMMAs, promote partial sum to FP32 on CUDA cores // This retains precision without adding MMA overhead __device__ void sm90_fp8_gemm_with_promotion(...) { float acc", "sha256": "bcfe9e69d8bdbce92ca0177f0977173672ec5261722f21bf48d33c1596946002"}, {"id": "u005", "kind": "code", "locator": "body:L48-L72", "preview": "```cuda // tcgen05.mma has native UE8M0 block scale support in hardware // No promotion needed - scales applied inside MMA __global__ void sm100_fp8_gemm_block_scale(...) { uint32_t tmem = tmem_alloc(256); for (int k = 0; k < K; k += BLOCK_", "sha256": "6f5d36327a504ae9121188b350d78e12ff711ba4bc1a8dac662530c812afeed8"}, {"id": "u006", "kind": "code", "locator": "body:L76-L83", "preview": "``` A (activations) [M, K] packed FP8 E4M3 sf_a [M, K/128] FP32 or FP8 E4M3 scales # 1 per 1x128 tile B (weights) [N, K] packed FP8 E4M3 sf_b [N/128, K/128] scales # 1 per 128x128 block # or packed UE8M0 format (Blackwell): 4 scales per int", "sha256": "af48fa077e66f75237049c2c04cd0f884f5ddfe555ec71fb7d46503200caebf2"}, {"id": "u007", "kind": "list-item", "locator": "body:L87-L87", "preview": "- DeepGEMM on H800: up to 1550 TFLOPS FP8", "sha256": "6859c2171a09f03e37a28bb9fe652affe1e265eb72ad4b5497203153fc6e1bfc"}, {"id": "u008", "kind": "list-item", "locator": "body:L88-L88", "preview": "- CUTLASS SM100 schedules: similar ratio vs peak", "sha256": "999a256efa100582ef9703dfba65b555bf4d2129b013a3a6c0eef3251ecbb2fa"}, {"id": "u009", "kind": "list-item", "locator": "body:L92-L92", "preview": "- LLM inference with FP8 quantized weights (DeepSeek V3, Qwen2-FP8, etc.)", "sha256": "a5f2d335f2c822920cb1eb495bceb3afcced81451d649f73e7b5d15a485161de"}, {"id": "u010", "kind": "list-item", "locator": "body:L93-L93", "preview": "- Training with FP8 activations (DeepSeek V3 training framework)", "sha256": "834f28701b37f0d2b09395c1852b790bf7be22b36b631118d9085175895ad58e"}, {"id": "u011", "kind": "list-item", "locator": "body:L94-L94", "preview": "- Anywhere per-tensor FP8 accuracy is insufficient due to outliers", "sha256": "6a79703a9a6dcbce374ccaa1cda083dc54062119cc552be713e6a9d47dfb5c28"}, {"id": "u012", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"fp8\", \"gpu\": \"H800\", \"metric\": \"TFLOPS\", \"shape\": \"M=4096, N=4096, K=4096\", \"source_id\": \"blog-deepgemm\", \"utilization\": \"~90% via CUDA core promotion\", \"value\": 1550}]", "sha256": "e58f133656145745a82198be1f806f85c60c837c993d6c5315743a1e942ceff6"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Block Scaling Structure", "SM90 Path (Hopper, WGMMA)", "SM100 Path (Blackwell, tcgen05.mma)", "Memory Layout", "Performance", "When To Use"], "id": "kernel-fp8-block-scale-gemm", "path": "wiki/kernels/fp8-block-scale-gemm.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/blogs/deepgemm.md", "url": "https://github.com/deepseek-ai/DeepGEMM"}, {"path": "sources/docs/nvidia-cutlass-blackwell.md", "url": "https://docs.nvidia.com/cutlass/latest/CHANGELOG.html"}, {"path": "sources/docs/cutlass-changelog-sm100.md", "url": "https://docs.nvidia.com/cutlass/latest/CHANGELOG.html"}], "risk_flags": ["code", "performance"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-deepgemm", "doc-cutlass-blackwell", "doc-cutlass-changelog-sm100"], "title": "FP8 Block-Scale GEMM", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "c3f18f75c945dcd3475248cde9377aacfb323444fc25b68d9eef038acb26e09d", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Fused MoE kernels combine the full Mixture-of-Experts forward pass into minimal kernel launches: routing, token dispatch, gate-up dual GEMM, SwiGLU activation, down projection GEMM, and token combine. In unfused implementations this require", "sha256": "ee24c6a94528d9b687123e15c30cb9bc85af105a9220c2a087a1cffd1a6df999"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "This is Track A of the FlashInfer MLSys 2026 contest, targeting B200 GPUs with DeepSeek-V3-style MoE parameters.", "sha256": "0ce0a403e3187cfb048a4b4bd032a997a36e5d2eb9bf023bfdcfabfdf91e3475"}, {"id": "u003", "kind": "code", "locator": "body:L11-L38", "preview": "``` Input tokens x [batch, hidden_dim=7168] | v [Router] top-k=8 experts from 32, grouped (8 groups, top_group=4) | v [Dispatch] Scatter tokens to selected experts | v [Gate-Up Dual GEMM] gate = x @ W_gate [batch_expert, hidden -> intermedi", "sha256": "62635d37ee3ffe039507c5609e99fe6fcb8ff3d2eacd6c14180121e4c35927c0"}, {"id": "u004", "kind": "code", "locator": "body:L42-L61", "preview": "``` Unfused (vLLM): 7 kernel launches 1. Router softmax 2. Top-k selection 3. Token dispatch (scatter) 4. Gate GEMM 5. Up GEMM 6. SiLU + multiply 7. Down GEMM + combine Partially fused (SGLang): 5 kernel launches 1. Router + top-k 2. Dispat", "sha256": "8b22093fd86c8e866d2f333007cbdccd151792645238e50cf50a6b599bf485b9"}, {"id": "u005", "kind": "prose", "locator": "body:L65-L65", "preview": "The gate-up projection fuses two GEMMs with SiLU activation and element-wise multiply:", "sha256": "4b59306fcf06dc1f46198d4256e613181446e46493e5ea2f9236ba7efaa348de"}, {"id": "u006", "kind": "code", "locator": "body:L67-L120", "preview": "```cpp // Fused gate-up: two GEMMs + SiLU + multiply in one kernel // Avoids writing intermediate gate and up results to global memory template __global__ void gated_dual_gemm_fused( c", "sha256": "a0aebecec3a6359fe4f6c486d4b8f0b566c09d388fbe65987c80e883673ed83b"}, {"id": "u007", "kind": "code", "locator": "body:L124-L140", "preview": "```python # FlashInfer API for fused MoE # Single function call replaces 5-7 separate kernel launches import flashinfer output = flashinfer.fused_moe.trtllm_fp8_block_scale_moe( hidden_states=x, # [batch, 7168] BF16 input w_gate_up=w_gate_u", "sha256": "e9d86e62426b268293b219ae569986426a59c613a5e5676c979b87fcb7c06e6b"}, {"id": "u008", "kind": "code", "locator": "body:L144-L188", "preview": "```python import triton import triton.language as tl @triton.jit def fused_moe_gate_up_triton( X_ptr, W_gate_ptr, W_up_ptr, Out_ptr, expert_ids_ptr, token_counts_ptr, sf_x_ptr, sf_gate_ptr, sf_up_ptr, N: tl.constexpr, K: tl.constexpr, BLOCK", "sha256": "491807dde7d9108b5e209a714abf7ce9f0e67487d6c3f1e18db027af801b9ced"}, {"id": "u009", "kind": "table-row", "locator": "body:L194-L194", "preview": "| Framework | Batch 4096 TFLOPS | Batch 1 Latency | Kernel Launches | | SGLang | 1262 | 206.9us | 5 (fused) |", "sha256": "906b943c2d8aa0e0ba3ffc07b94200370981f76ad47e65ae90d00d6f8bc2f491"}, {"id": "u010", "kind": "table-row", "locator": "body:L195-L195", "preview": "| Framework | Batch 4096 TFLOPS | Batch 1 Latency | Kernel Launches | | FlashInfer CuTe DSL | 1225 | 481.9us | 1-2 (fully fused) |", "sha256": "88cf228054f0e17e1f0d38f0b87836e3ce62578cb574a89789f1f097c9b13529"}, {"id": "u011", "kind": "table-row", "locator": "body:L196-L196", "preview": "| Framework | Batch 4096 TFLOPS | Batch 1 Latency | Kernel Launches | | vLLM | 1117 | 369.5us | 7 (unfused) |", "sha256": "71ec18f2c60195f5b60aae9bd1f4ae7fe3e40db27b47e11ea326bdf54d0e8316"}, {"id": "u012", "kind": "list-item", "locator": "body:L200-L200", "preview": "1. **No pre-tuned FP8 MoE config for B200**: Tile sizes and pipeline stages need empirical tuning", "sha256": "8f3b75b2e500d74024e0fd83dbc7f63820eeb0d80333a9028c675a11f5279489"}, {"id": "u013", "kind": "list-item", "locator": "body:L201-L201", "preview": "2. **FP8 numerical overflow**: Block scaling (block size 128) required for stability", "sha256": "95e2f684f53797c33787968fd4432cd5a58bd0ce538a3369394fb05fb7f2d3c1"}, {"id": "u014", "kind": "list-item", "locator": "body:L202-L202", "preview": "3. **Batch-size sensitivity**: batch=1 is latency-critical (kernel launch overhead dominates); batch=4096 is throughput-critical", "sha256": "0de20c75dfbd49ffacd287c5357ffac0b79fb1de378d3be742253f82b95acaa9"}, {"id": "u015", "kind": "list-item", "locator": "body:L203-L203", "preview": "4. **Expert load imbalance**: Variable token counts per expert cause tail effects", "sha256": "c6c51359190b264deae32b98bfc662f48301944cfea12407b75356aa653dffbe"}, {"id": "u016", "kind": "list-item", "locator": "body:L204-L204", "preview": "5. **TMA alignment**: 128-byte alignment required for all TMA descriptors", "sha256": "5531f661e1063a34d7576d65d13c26c28657c064b7e35fa7e346dbe65bf5a142"}, {"id": "u017", "kind": "list-item", "locator": "body:L205-L205", "preview": "6. **Dual TMEM allocation**: Gate and up accumulators each need TMEM space, competing for the 256KB budget", "sha256": "066ba71d4b96790d24fbd1ffc8b2c63a9a9a4d1f1bcdf6133f801b03fa73d423"}, {"id": "u018", "kind": "list-item", "locator": "body:L209-L209", "preview": "- MoE model inference (DeepSeek-V3, Mixtral, etc.)", "sha256": "5d1ea69068eb0a04307c47b71fe5539280efc4e746443ba47ac1e5bb959279df"}, {"id": "u019", "kind": "list-item", "locator": "body:L210-L210", "preview": "- Both prefill (high batch, throughput-critical) and decode (low batch, latency-critical)", "sha256": "856ba607570f4fc39c8b29e12922fa8cdf63bdde2a22f5d3c6e5ddb7f83d5ef2"}, {"id": "u020", "kind": "list-item", "locator": "body:L211-L211", "preview": "- When gate-up GEMM fusion provides measurable speedup over separate launches", "sha256": "1d26cea2436827bc9053392406b7119b175c05ffe71460d733eabfcac9ef9e7b"}, {"id": "u021", "kind": "list-item", "locator": "body:L215-L215", "preview": "- Full fusion (routing through combine) is extremely complex to implement correctly", "sha256": "6dd0019145f486ab8af5170962abaace419c0a60183f19fa5e765a5b881d86af"}, {"id": "u022", "kind": "list-item", "locator": "body:L216-L216", "preview": "- Expert load imbalance is the primary practical bottleneck", "sha256": "847799de8b5ec1b7f71f51131ef94f3b3619062780d84483dc8f0386545425a2"}, {"id": "u023", "kind": "list-item", "locator": "body:L217-L217", "preview": "- CUDA graph compatibility requires masked layout (fixed allocation per expert)", "sha256": "e480662de15ee90e9ce8636aba44ff3678b756e86939ccb07a3adc8f462b5b97"}, {"id": "u024", "kind": "list-item", "locator": "body:L218-L218", "preview": "- Small expert token counts cause thin-GEMM inefficiency on tensor cores", "sha256": "4e733045fb9625e393f2fca392c080c70d021114ecc3922f24958a4ad5666ee0"}, {"id": "u025", "kind": "list-item", "locator": "body:L219-L219", "preview": "- FP8 block scaling adds memory overhead for scale factor storage", "sha256": "a6140763ac26f6b64b8b51bfdec3c31f59cf98b631f4a91727603f8bbb545f92"}, {"id": "u026", "kind": "list-item", "locator": "body:L223-L223", "preview": "- [FlashInfer MLSys 2026 Contest](https://mlsys26.flashinfer.ai/)", "sha256": "0a5ff847c139fc581dea1c62769bff7d8f8ce355ab890d4889cbc20b253a535b"}, {"id": "u027", "kind": "list-item", "locator": "body:L224-L224", "preview": "- [GPU Mode NVFP4 Hackathon Problem 3](https://github.com/gpu-mode/reference-kernels)", "sha256": "fb49f6aa44f7585c557194274331f5706fe43e629eae7b63a8f90602ba329e7f"}, {"id": "u028", "kind": "list-item", "locator": "body:L225-L225", "preview": "- [DeepGEMM MoE](https://github.com/deepseek-ai/DeepGEMM)", "sha256": "011219b565377c3108be875324294ae1d60076b56629632da1aded4d63eaf0fb"}, {"id": "u029", "kind": "list-item", "locator": "body:L226-L226", "preview": "- [SGLang Fused MoE](https://github.com/sgl-project/sglang)", "sha256": "de1eb8863fba8e60a30e383546024c553880110c755386e0aad7e6bd18350b0e"}, {"id": "u030", "kind": "prose", "locator": "body:L230-L230", "preview": "Verbatim upstream code lives in [`artifacts/kernels/fused-moe/full/`](../../artifacts/kernels/fused-moe/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live in [`artifact", "sha256": "0d8251a8098e0338630dddf7b941e01d3eda9ac09b7a1de08a3624ada1d2bd57"}, {"id": "u031", "kind": "prose", "locator": "body:L232-L232", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u032", "kind": "code", "locator": "body:L234-L236", "preview": "```bash python3 scripts/get_page.py kernel-fused-moe --include-code ```", "sha256": "56fc790420908106565f83ed31ab8a2fe1aa1e849fce411f2babc6c449629082"}, {"id": "u033", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"fp8\", \"gpu\": \"B200\", \"metric\": \"TFLOPS\", \"shape\": \"topk=8, experts=32, hidden=7168, intermediate=2048, batch=4096\", \"source_id\": \"contest-flashinfer-track-a\", \"utilization\": \"~56%\", \"value\": 1262}]", "sha256": "74cedc63a3ce3ac5e1f1aea44e509eb2ad07d8306383c08c3579b6a91ed2d6c3"}], "confidence_claimed": "source-reported", "headings": ["Overview", "MoE Forward Pass Structure", "Kernel Fusion Strategy", "Gated Dual GEMM Kernel (Hackathon Problem 3)", "FP8 Block-Scale MoE (FlashInfer API)", "Triton Fused Gate-Up Kernel", "Framework Baselines (B200)", "Challenges", "When to Use", "Caveats", "Sources", "Full Reference Implementation"], "id": "kernel-fused-moe", "path": "wiki/kernels/fused-moe.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/contests/flashinfer-mlsys26/track-a-fused-moe.md", "url": "https://mlsys26.flashinfer.ai/"}, {"path": "sources/blogs/deepgemm.md", "url": "https://github.com/deepseek-ai/DeepGEMM"}, {"path": "sources/prs/vllm/PR-23696.md", "revision": "074854b2", "url": "https://github.com/vllm-project/vllm/pull/23696"}], "risk_flags": ["code", "ordering", "performance", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-flashinfer-track-a", "blog-deepgemm", "pr-vllm-23696"], "title": "Fused MoE \u2014 FP8 Block-Scale Routing + Dual GEMM", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "af98b7d75e33581067427cda67ff21fbf228821cc926241a7539b6215cd781ec", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Gated Delta Networks (GatedDeltaNet) replace standard O(n^2) attention with an O(n) linear attention mechanism that uses a delta rule for error-correcting memory updates and exponential gating for adaptive decay. Published at ICLR 2025 by N", "sha256": "c5725fe2643100d15e27a593fa7bcb80719b1fcd30767899f8c849bd40a40d30"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "The key advantage is O(1) per-token cost during decoding: the recurrent state is a fixed-size matrix that gets updated with each new token, eliminating the KV cache growth problem entirely.", "sha256": "d3a0655b8a5271586db4b84b18cf492938aea0ceda8b65826cae7173976918b4"}, {"id": "u003", "kind": "code", "locator": "body:L11-L21", "preview": "``` Qwen3-Next-80B: 48 layers Pattern: 12 x (3 x [GatedDeltaNet -> MoE] -> [Full Attention -> MoE]) Layer distribution: - 36 GatedDeltaNet layers (75%): O(n) linear attention - 12 Full Attention layers (25%): Standard GQA for global retriev", "sha256": "bdb49253be1645257c57e3919dd226dce437718dba3b4ea8537557e4ba2a6442"}, {"id": "u004", "kind": "prose", "locator": "body:L25-L25", "preview": "Unlike standard linear attention (which uses simple additive updates to the recurrent state), the delta rule performs targeted error-correcting updates:", "sha256": "01f4db44a83587d916796232922fd9e7c2c320b8bc2d983b3ed5586501478919"}, {"id": "u005", "kind": "code", "locator": "body:L27-L58", "preview": "```python # Standard linear attention (additive): # S_t = S_{t-1} + v_t @ k_t^T # # Delta rule (error-correcting): # S_t = S_{t-1} + (v_t - S_{t-1} @ k_t) @ k_t^T # ^^^^^^^^^^^^^^^^^^^^^^^^ # Error correction term def delta_rule_step(S, k, ", "sha256": "7e861801c69ff304b9a9e2e7735938e83ed8c96c1783a1f73ceaeaba8a42774b"}, {"id": "u006", "kind": "prose", "locator": "body:L62-L62", "preview": "During prefill, sequences are divided into chunks that can be processed in parallel. Within each chunk, the inter-token dependencies are resolved via a causal linear recurrence; across chunks, the recurrent state is propagated sequentially.", "sha256": "36052b0d9826a837d97158c09f43a728ea3f30dad1ce51c39514fcf7b2a63903"}, {"id": "u007", "kind": "code", "locator": "body:L64-L121", "preview": "```python import triton import triton.language as tl @triton.jit def gated_delta_net_chunk_fwd( Q_ptr, K_ptr, V_ptr, Beta_ptr, O_ptr, State_ptr, SEQ_LEN: tl.constexpr, CHUNK_SIZE: tl.constexpr, # e.g., 64 or 128 D_QK: tl.constexpr, # qk_dim", "sha256": "c365a7c616d5094fa68e774b6c173f6314b11f48738a0509e44285df8d4040c2"}, {"id": "u008", "kind": "prose", "locator": "body:L125-L125", "preview": "During autoregressive decoding, each new token only requires one state update -- O(1) per token regardless of context length.", "sha256": "584acb25f6c610eda43934bed141e537403a5a2fdbc8567bce8ef58e7dbf728c"}, {"id": "u009", "kind": "code", "locator": "body:L127-L167", "preview": "```python @triton.jit def gated_delta_net_decode( Q_ptr, K_ptr, V_ptr, Beta_ptr, O_ptr, State_ptr, D_QK: tl.constexpr, D_V: tl.constexpr, ): \"\"\" Single-token decode: O(1) per token. The recurrent state replaces the KV cache entirely. State ", "sha256": "29466cfc078905f19d8672c1858fdba4831aaaac152c66c96acf4d2e9bba8b71"}, {"id": "u010", "kind": "prose", "locator": "body:L171-L171", "preview": "TFLA adds a second level of tiling within chunks, enabling arbitrarily large chunk sizes. It emits matmuls as inline PTX assembly for both Hopper (WGMMA) and Blackwell (tcgen05).", "sha256": "141918ec518be3497594c182d87e3f96da06efc18770d6b0f951d1e64ddfd0e2"}, {"id": "u011", "kind": "code", "locator": "body:L173-L184", "preview": "```cpp // TFLA: Inline PTX for Blackwell tcgen05 matmul within chunk tiles // Two levels of parallelism: standard chunkwise + tiling within chunks // SM100 path: tcgen05.mma for intra-chunk matrix operations asm volatile( \"tcgen05.mma.cta_g", "sha256": "e00f483ed8cb2a4a8494941a64efdb2c085cde36fe4f47681dc8ad51f7cf1d10"}, {"id": "u012", "kind": "prose", "locator": "body:L188-L188", "preview": "Two main implementations exist:", "sha256": "eabbb511c86ae0ecf8abe526ed89a206f21c3b79bd5260192624f74303f8c0ff"}, {"id": "u013", "kind": "table-row", "locator": "body:L192-L192", "preview": "| Implementation | Source | Notes | | NVlabs/GatedDeltaNet | Reference | Triton kernels, research quality |", "sha256": "0ad7015db76102906174f7a76bab64f291251b1dc1a8cf4e65b103cc9a5751c1"}, {"id": "u014", "kind": "table-row", "locator": "body:L193-L193", "preview": "| Implementation | Source | Notes | | FLA (Flash Linear Attention) | Recommended | Optimized, significantly faster, variable-length support |", "sha256": "5793e5c73e248feab6df19b4046042277823265032b48a2d3ca354fe00b0b2ab"}, {"id": "u015", "kind": "prose", "locator": "body:L197-L197", "preview": "GatedDeltaNet is Track C of the FlashInfer MLSys 2026 contest:", "sha256": "0f1edd6d3bf4d4d8b77fe158f93a12a67ad13bacf26f39473bd26bc4473b1dc1"}, {"id": "u016", "kind": "list-item", "locator": "body:L198-L198", "preview": "- Parameters: qk_dim=4, v_dim=8, d=128", "sha256": "fcf6818917c1f0405e859f96669e64d0434038bda1b1b9a8f767f2f18470180a"}, {"id": "u017", "kind": "list-item", "locator": "body:L199-L199", "preview": "- Benchmarks: decode `qk4_v8_d128_k_last`, prefill `qk4_v8_d128_k_last`", "sha256": "8a2eb9edbf1cdd5dcba20bb331061e4afb030ff8bc2e62bfd1f102ba62fc0f95"}, {"id": "u018", "kind": "list-item", "locator": "body:L200-L200", "preview": "- Status: decode done for both Hopper and Blackwell; prefill done on Hopper, in progress for Blackwell", "sha256": "1665a15d3ebec4d98118c4dc57d776d68a8f4a9b3561f56328b8828cd0110cfa"}, {"id": "u019", "kind": "list-item", "locator": "body:L204-L204", "preview": "- Long-context inference (32K+) where O(n) scaling provides major throughput gains", "sha256": "03615f82a34334e6233d9c7b840ffa95a2dbc73fa9498a55d3fff367d82fe25d"}, {"id": "u020", "kind": "list-item", "locator": "body:L205-L205", "preview": "- Hybrid architectures combining linear attention (75% of layers) with full attention (25%)", "sha256": "4bfa4d21b1489298693160c40b893f9763a2618972dd66903051447866e29fbb"}, {"id": "u021", "kind": "list-item", "locator": "body:L206-L206", "preview": "- Streaming decode where O(1) per-token cost eliminates KV cache growth", "sha256": "9c8a112be1fb768308e8d6bd51ac1c424922354d3d837e847adf1ccd4a860bda"}, {"id": "u022", "kind": "list-item", "locator": "body:L210-L210", "preview": "- Triton-based kernels have CPU launch overhead impacting small decode batches; use CUDA graph mode via vLLM", "sha256": "a1d940680167fee8177f2fe4684e3ffafe7cc1d899b0510ccb2f729a9f075805"}, {"id": "u023", "kind": "list-item", "locator": "body:L211-L211", "preview": "- Recurrent state size (D_QK * D_V per head) can be large -- 512K floats for typical configs", "sha256": "3ea7a925bf984535777f727b38f251677496296978745f0b324f66bfc52a081d"}, {"id": "u024", "kind": "list-item", "locator": "body:L212-L212", "preview": "- Quality depends on the learned gating; not a drop-in replacement for standard attention without retraining", "sha256": "17296706a743618938e197f6c963950ee2537e8c7cba1acaf384b51a7ebf01d0"}, {"id": "u025", "kind": "list-item", "locator": "body:L213-L213", "preview": "- Attention output gating (in Qwen3.5) is required to eliminate Attention Sink and Massive Activation problems", "sha256": "173ea344150d5417420fd38bba1cb37c320e8c70e30017929f15823357a9c7aa"}, {"id": "u026", "kind": "list-item", "locator": "body:L217-L217", "preview": "- [GatedDeltaNet (ICLR 2025)](https://github.com/NVlabs/GatedDeltaNet)", "sha256": "a67fe6e47713f3c0a3ea8732a757fcee02c7c5b0a7f602aacb419e55a34bf5d9"}, {"id": "u027", "kind": "list-item", "locator": "body:L218-L218", "preview": "- [TFLA paper](https://arxiv.org/abs/2503.14376)", "sha256": "939543a902be4abe15f2e3068bdc494fae3b1d7a84131fba137df1f5a7af9b39"}, {"id": "u028", "kind": "list-item", "locator": "body:L219-L219", "preview": "- [Qwen3-Next NVIDIA blog](https://developer.nvidia.com/blog/new-open-source-qwen3-next-models-preview-hybrid-moe-architecture-delivering-improved-accuracy-and-accelerated-parallel-processing-across-nvidia-platform/)", "sha256": "8e5247145edfdcc925b581aa5cd69e4aced1787092c5c7afe84274900da957de"}, {"id": "u029", "kind": "list-item", "locator": "body:L220-L220", "preview": "- [FlashInfer MLSys 2026 Contest](https://mlsys26.flashinfer.ai/)", "sha256": "0a5ff847c139fc581dea1c62769bff7d8f8ce355ab890d4889cbc20b253a535b"}, {"id": "u030", "kind": "prose", "locator": "body:L224-L224", "preview": "Verbatim upstream code lives in [`artifacts/kernels/gated-delta-net/full/`](../../artifacts/kernels/gated-delta-net/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live i", "sha256": "6ae5cca417d32aa0f82d0a726cba8ee04b5abf13a02242148316781ee66b440e"}, {"id": "u031", "kind": "prose", "locator": "body:L226-L226", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u032", "kind": "code", "locator": "body:L228-L230", "preview": "```bash python3 scripts/get_page.py kernel-gated-delta-net --include-code ```", "sha256": "39378634eb01b82263ac1e7155820b2bf1f5eb4057c51fca181d3283db3328df"}, {"id": "u033", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"bf16\", \"gpu\": \"H100\", \"metric\": \"speedup\", \"shape\": \"seqlen=8192, qk_dim=4, v_dim=8, d=128\", \"source_id\": \"blog-gated-delta-net\", \"utilization\": \"vs Qwen3-32B at 32K+ context, O(n) linear complexity\", \"value\": 10}]", "sha256": "99c6c7214a5abb7b19fd5d9eba01724d26ecfb52c24025e97486541606658411"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Architecture in Qwen3-Next", "Delta Rule Mechanism", "Chunk-Based Parallel Prefill", "Streaming Decode Kernel", "TFLA: Tiled Flash Linear Attention", "Implementations", "FlashInfer MLSys 2026 Contest", "When to Use", "Caveats", "Sources", "Full Reference Implementation"], "id": "kernel-gated-delta-net", "path": "wiki/kernels/gated-delta-net.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/blogs/gated-delta-net.md", "url": "https://github.com/NVlabs/GatedDeltaNet"}, {"path": "sources/docs/tfla.md", "url": "https://arxiv.org/abs/2503.14376"}, {"path": "sources/prs/vllm/PR-37303.md", "revision": "e1d85e5c", "url": "https://github.com/vllm-project/vllm/pull/37303"}], "risk_flags": ["code", "performance", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-gated-delta-net", "doc-tfla", "pr-vllm-37303"], "title": "Gated Delta Net \u2014 Linear Attention", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "4aa8460e6ef7388eb59cdd6643cc8a05fecb149f9148104b8eec852b369e7373", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Gated dual GEMM fuses two matrix multiplications with activation and elementwise operations \u2014 the canonical MLP gate-up pattern used by LLaMA, Qwen, DeepSeek, and most modern LLMs. Fusion eliminates two global memory roundtrips compared to ", "sha256": "ecd04db3793e2b25272be2e1fa9603ac7e25f7da771d277a872dbd05239e5cf4"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "This was Problem 3 of the GPU Mode NVFP4 Hackathon.", "sha256": "ead2e2b9b70b06f0b9121b6a49ee12100a413d507ce839f998be6c61da4ca549"}, {"id": "u003", "kind": "code", "locator": "body:L11-L21", "preview": "``` Given x, W_gate, W_up (weights shared same K dimension) Standard (unfused): gate = x @ W_gate (GEMM 1: reads x, W_gate, writes gate) up = x @ W_up (GEMM 2: reads x, W_up, writes up) silu = gate * sigmoid(gate) (elementwise: reads gate, ", "sha256": "91396f6a6bc8a1432fc70407c8abea6e99f57e9f1a81f6a29107035fcc68a70f"}, {"id": "u004", "kind": "code", "locator": "body:L25-L58", "preview": "```cuda template __global__ void gated_dual_gemm_nvfp4( const nvfp4_t* __restrict__ X, // [M, K] input const nvfp4_t* __restrict__ W_gate, // [N, K] gate weights const nvfp4_t* __restr", "sha256": "6d719686a6a9f441bb8304fdc4964c3e61755f1ed392540a4d3e5d03bfebffb0"}, {"id": "u005", "kind": "list-item", "locator": "body:L62-L62", "preview": "1. **X reuse**: Same X tile feeds both MMAs \u2014 loaded once, used twice", "sha256": "e62b96693cccdfb2308e10bbfb3fce0020a939dc9cb849dddfb6e0cf8af64784"}, {"id": "u006", "kind": "list-item", "locator": "body:L63-L63", "preview": "2. **TMEM dual accumulator**: Blackwell's 512-column TMEM fits two 256-col accumulators side-by-side", "sha256": "d9110adf602d0bcdd1c08c3dd9ba7f4c207d7f00919ff5273d78b1c843c0e9d8"}, {"id": "u007", "kind": "list-item", "locator": "body:L64-L64", "preview": "3. **Fused epilogue**: SiLU and multiply happen after TMEM load, no intermediate SMEM", "sha256": "43e2dad7ce262ff0feeab03d9ce1fae54344ae0c313706e90a1db3a614979f71"}, {"id": "u008", "kind": "list-item", "locator": "body:L65-L65", "preview": "4. **Shared SFA**: X's block scales apply to both gate and up computations", "sha256": "357df219c44e5de2c4437beb097a208833e57a091041d49566a37cea578578ab"}, {"id": "u009", "kind": "list-item", "locator": "body:L69-L69", "preview": "- MLP layers in modern LLMs (LLaMA, Qwen, DeepSeek, Mistral)", "sha256": "adebf22f795cda0c8ad652b0af4b770d97ef97c38ff79e299936c646d0e6178c"}, {"id": "u010", "kind": "list-item", "locator": "body:L70-L70", "preview": "- Any dual-output operation sharing one input", "sha256": "5107defe1e739fe0f45ca2298bce97cfa49057c2e50ae751c258a7b16609f6c3"}, {"id": "u011", "kind": "list-item", "locator": "body:L71-L71", "preview": "- MoE expert computations (expand to per-expert fused kernels)", "sha256": "981ebff4fefddaf7bfcc5b35425ceeeba547586380df6d6ddf505ce7288d324e"}, {"id": "u012", "kind": "prose", "locator": "body:L75-L75", "preview": "The reference bundle lives in [`artifacts/kernels/gated-dual-gemm/full/`](../../artifacts/kernels/gated-dual-gemm/full/) and combines the upstream vLLM PR-23696 diff (`vllm-PR-23696-gated-dual-gemm.patch`, `mode: upstream-patch`) with an ex", "sha256": "c1f11acc6a93b91b31a6abb047ffe2a46620ae7935dd689949f31843863d15f4"}, {"id": "u013", "kind": "prose", "locator": "body:L77-L77", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u014", "kind": "code", "locator": "body:L79-L81", "preview": "```bash python3 scripts/get_page.py kernel-gated-dual-gemm --include-code ```", "sha256": "68a44b9bd282d463bccca115a4a7aca25d430f9c7e19334972410593a6c18bbc"}, {"id": "u015", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"nvfp4\", \"gpu\": \"B200\", \"metric\": \"latency_us\", \"shape\": \"M=1024 N=2*2048 K=7168 (gate-up MLP)\", \"source_id\": \"contest-gpumode-p3\", \"utilization\": \"compute-bound\", \"value\": 18.5}]", "sha256": "23184d2163865e55e7ebac127fa9c4bacff22324230e2727fa61d9f8eb3e8b90"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Fused Operation", "Kernel Structure (Blackwell)", "Key Optimizations", "When To Use", "Full Reference Implementation"], "id": "kernel-gated-dual-gemm", "path": "wiki/kernels/gated-dual-gemm.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md", "url": "https://github.com/gpu-mode/reference-kernels"}, {"path": "sources/blogs/deepgemm.md", "url": "https://github.com/deepseek-ai/DeepGEMM"}, {"path": "sources/blogs/tflops-gap-fp4-moe.md", "url": "https://huggingface.co/blog/apsys/blackwell-nvfp4-comparison"}, {"path": "sources/prs/vllm/PR-23696.md", "revision": "074854b2", "url": "https://github.com/vllm-project/vllm/pull/23696"}], "risk_flags": ["code", "performance"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-gpumode-p3", "blog-deepgemm", "blog-tflops-gap-fp4-moe", "pr-vllm-23696"], "title": "Gated Dual GEMM (Gate-Up + SwiGLU Fusion)", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "216f09e31b3f73503470760148850014df1540ad380997383317930a7b459e9e", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Grouped GEMM computes multiple matrix multiplications with variable M dimensions but shared N and K, directly targeting MoE (Mixture of Experts) inference where each expert processes a different number of tokens. This is the most practicall", "sha256": "fe725fe4c978ef7a2a3d83247a579411e1923af85b55dee827a441009e19fe03"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "Grouped GEMM was Problem 4 (heaviest weight: 40%) of the GPU Mode NVFP4 Hackathon, and is also the core of DeepGEMM's MoE support.", "sha256": "d122944985199c2459f3c27772eb790b7652db25acb67f563c1d9e8249b4c960"}, {"id": "u003", "kind": "code", "locator": "body:L11-L25", "preview": "``` Standard GEMM: C = A @ B (single problem) Grouped GEMM: C_i = A_i @ B_i for i in [0, num_groups) MoE specialization: - N and K are FIXED (same expert architecture) - Only M varies (different token counts per expert) - B_i may be differe", "sha256": "94c025828b3055487d13520494f11cf1aa4a2c42837806f259d6f0f1d129b7bf"}, {"id": "u004", "kind": "prose", "locator": "body:L29-L29", "preview": "DeepGEMM provides three layouts optimized for different MoE phases:", "sha256": "4562529a5f1fefcd4c30c2507843fab086aa2ed20508bc4ce4c7f65665db458c"}, {"id": "u005", "kind": "code", "locator": "body:L31-L61", "preview": "```cpp // Layout 1: Contiguous (prefill) // All expert inputs packed sequentially with cumulative offset array // Memory: [Expert0 (M0 rows)] [Expert1 (M1 rows)] [Expert2 (M2 rows)]... // Index: offsets[0]=0 offsets[1]=M0 offsets[2]=M0+M1 s", "sha256": "2ffacb9913c03845c0e35c537d7c276d96415c2883121c20e2b9b0c95739d559"}, {"id": "u006", "kind": "code", "locator": "body:L65-L92", "preview": "```cpp // CUTLASS schedule for grouped GEMM on Blackwell using Schedule = cutlass::gemm::KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100; // PtrArray mode: array of pointers to per-group A, B, C matrices // TMA handles variable-offset loads vi", "sha256": "6cbdd8096dbe2fd2bebf3f8b7f959e97d6a26a7d228a5adaaaa5d1bfd3b9a6e5"}, {"id": "u007", "kind": "code", "locator": "body:L98-L117", "preview": "```cpp // Precompute tile-to-expert mapping on host before launch struct TileInfo { int expert_id; int tile_m_start; // Local M offset within this expert int tile_n_start; }; std::vector build_tile_schedule( const int* M_per_exper", "sha256": "0025b78e903a581b71ea67749d649624aca073b7cb362412b042c42bd01a93ad"}, {"id": "u008", "kind": "code", "locator": "body:L121-L151", "preview": "```cpp // Persistent kernel with atomic tile counter // Each thread block loops, grabbing tiles until all are processed __device__ int g_tile_counter = 0; __global__ void grouped_gemm_persistent( const fp8_t** A_ptrs, const fp8_t** B_ptrs, ", "sha256": "e5a0978df32a9382e83d7bd56a5cfa8ca3a95447f8bb344b5b8200fcd978d31b"}, {"id": "u009", "kind": "prose", "locator": "body:L155-L155", "preview": "The 1st-place submission to Problem 4 exploited the evaluation harness:", "sha256": "b2053084a52810c3f26740bb9ec3ce6cdb8771fe7d6d59dc1fb2425cf9133a5d"}, {"id": "u010", "kind": "code", "locator": "body:L157-L162", "preview": "``` Correctness phase: harness clones data -> real kernel runs correctly Timing phase: harness reuses same objects -> Call 1: fires 120-group super-batch (all 15 benchmark problems fused) Calls 2-15: detect pre-computed results, skip comput", "sha256": "95bc2baa6208a96a7ac2832c87fed81fb5b2374aa74667629b9966f567f5cc57"}, {"id": "u011", "kind": "prose", "locator": "body:L164-L164", "preview": "This reported 11.191us (~2us ahead of second place). It led to improvements in the FlashInfer-Bench evaluation methodology for the MLSys 2026 contest.", "sha256": "4ce120f237a07e0663244cd3ad5c69a13f5a4eb2a6ba5c1ae0ce04e83463365b"}, {"id": "u012", "kind": "list-item", "locator": "body:L168-L168", "preview": "- MoE inference: dispatch tokens to experts, compute per-expert projections", "sha256": "7d3cd305e13d90e277fe87d5e368ff6aa2bd87287bd378cc6046ba4f5381307d"}, {"id": "u013", "kind": "list-item", "locator": "body:L169-L169", "preview": "- Any workload with multiple GEMMs sharing N and K but varying M", "sha256": "1540d11f65836862124c49b17b8eeeb03923cf917710d15837bc6ba53d6373ec"}, {"id": "u014", "kind": "list-item", "locator": "body:L170-L170", "preview": "- Prefill (contiguous layout) and decode (masked layout for CUDA graph compatibility)", "sha256": "9ac021fc8424bb238df682d5dc3e9ad6b557197949efe0890d7efda6bb20f301"}, {"id": "u015", "kind": "list-item", "locator": "body:L174-L174", "preview": "- Expert load imbalance is the primary practical bottleneck (see [tail-effect](../patterns/tail-effect.md))", "sha256": "0b3e2c331c616683888b3601e48371a8d51c666456d850355c40fdc118f4b4e7"}, {"id": "u016", "kind": "list-item", "locator": "body:L175-L175", "preview": "- Small M per expert causes thin-GEMM inefficiency on tensor cores", "sha256": "88340decaa9640bb6c863559fd47c4f124d76590140f660701d12ed18d3e202e"}, {"id": "u017", "kind": "list-item", "locator": "body:L176-L176", "preview": "- Masked layout wastes compute on padding when M distribution is skewed", "sha256": "93bc9120568a4d239e28dbca67cdd807e2201e2f14854fa9ffc533c15aeac7ab"}, {"id": "u018", "kind": "list-item", "locator": "body:L177-L177", "preview": "- CLC dynamic scheduling adds hardware overhead vs static precomputed schedules", "sha256": "6e26bfe8107dd58a8b358b2601fc7b2fbe936f750dd50c2bc4968e3daf4b194d"}, {"id": "u019", "kind": "list-item", "locator": "body:L178-L178", "preview": "- TMA alignment (128 bytes) constrains minimum tile dimensions", "sha256": "06ac4a8dd845e398c507180e217d7cb8868fdbe65bde49b054c729efc927047c"}, {"id": "u020", "kind": "list-item", "locator": "body:L182-L182", "preview": "- [GPU Mode NVFP4 Hackathon](https://github.com/gpu-mode/reference-kernels)", "sha256": "eebfd002120234da40f3b045095d61fdf901341039f5f3ae98ed1d4bb5bb5a27"}, {"id": "u021", "kind": "list-item", "locator": "body:L183-L183", "preview": "- [DeepGEMM Grouped GEMM](https://github.com/deepseek-ai/DeepGEMM)", "sha256": "384dcd71482423e4fdaeb79b0d7a923cbd79c7e4b1c8dda72a9801ad304898da"}, {"id": "u022", "kind": "list-item", "locator": "body:L184-L184", "preview": "- [Reward Hack Writeup](https://www.gpumode.com/news/reward-hacking-nvfp4)", "sha256": "2d4a7712919973168f4dda9ffa55a9a6abbaa1139c874eb1e7b9925af179acaa"}, {"id": "u023", "kind": "list-item", "locator": "body:L185-L185", "preview": "- [CUTLASS SM100 documentation](https://docs.nvidia.com/cutlass/latest/CHANGELOG.html)", "sha256": "75e0801b0814c177427d45c23dae770d0fabd27c5a2c06a826ddc8801ef0c4b4"}, {"id": "u024", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"nvfp4\", \"gpu\": \"B200\", \"metric\": \"latency_us\", \"shape\": \"variable M, shared N=K, 15 groups\", \"source_id\": \"contest-gpumode-p4\", \"utilization\": \"compute-bound\", \"value\": 11.2}]", "sha256": "9a9c2791f5aa02e6b01213caae16799903c6001ea09c1f50253984d4de971d15"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Problem Structure", "DeepGEMM Grouped Layouts", "CUTLASS Grouped GEMM on SM100", "Tile Scheduling for Variable M", "Static Scheduling (Precomputed)", "Dynamic Scheduling (CLC / Persistent Kernel)", "The Reward Hack", "When to Use", "Caveats", "Sources"], "id": "kernel-grouped-gemm", "path": "wiki/kernels/grouped-gemm.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md", "url": "https://github.com/gpu-mode/reference-kernels"}, {"path": "sources/blogs/deepgemm.md", "url": "https://github.com/deepseek-ai/DeepGEMM"}, {"path": "sources/docs/nvidia-cutlass-blackwell.md", "url": "https://docs.nvidia.com/cutlass/latest/CHANGELOG.html"}], "risk_flags": ["code", "ordering", "performance"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-gpumode-p4", "blog-deepgemm", "doc-cutlass-blackwell"], "title": "Grouped GEMM for MoE", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "002fbf6ef7dba7c6bd6bfec4cdeccf4104b100309e09eae082faaf0aeec0e4c3", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Native Sparse Attention (NSA) is a hardware-aligned sparse attention mechanism published at ACL 2025, designed to reduce attention compute for long sequences (64K+) without sacrificing quality. Unlike post-hoc sparsity approaches, NSA is na", "sha256": "cf68b3aeaa3b5d26a01ee958075f2dd90859b572f97c3f1d53d55470ba09ffc1"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "NSA achieves 9x forward speedup and 6x backward speedup at 64K sequences versus FlashAttention-2, and 11.6x decoding speedup at 64K context. It is deployed in DeepSeek-V3.2-Exp combined with FlashMLA sparse kernels.", "sha256": "e8d21dfea9669dd9ecbfc3687491c8e41b2e94166ac6206b9e1458bf19f271bd"}, {"id": "u003", "kind": "code", "locator": "body:L11-L32", "preview": "``` Input Query Q | +---> [Compression Path] Learned MLP creates coarse-grained KV | | representations (token compression) | v | S_compressed = Q @ K_compressed^T | +---> [Selection Path] Blockwise importance scores select | | top-n fine-gr", "sha256": "8003fc920351bab1c7b84c9d6ed8fdcd0adfd2aad590cfe719794d39c518155e"}, {"id": "u004", "kind": "prose", "locator": "body:L36-L36", "preview": "The core NSA kernel is implemented in Triton with group-centric data loading and grid-based scheduling.", "sha256": "73ce24e24ace749715608e092ad64a9fdabc18f381ffa7bbe90e3ef4fdf30d8c"}, {"id": "u005", "kind": "code", "locator": "body:L38-L103", "preview": "```python import triton import triton.language as tl @triton.jit def nsa_sparse_attention_fwd( Q_ptr, K_ptr, V_ptr, O_ptr, block_indices_ptr, # Selected block indices per query num_selected: tl.constexpr, BLOCK_SIZE: tl.constexpr, HEAD_DIM:", "sha256": "d08bb0d4f71b7e67821be41026c25f1a8eb32149dc04ca6632c58233fa664934"}, {"id": "u006", "kind": "code", "locator": "body:L107-L140", "preview": "```python @triton.jit def nsa_sliding_window_fwd( Q_ptr, K_ptr, V_ptr, O_ptr, seq_pos, WINDOW_SIZE: tl.constexpr, # 512 HEAD_DIM: tl.constexpr, ): \"\"\"Local sliding window attention for recent context.\"\"\" pid = tl.program_id(0) # query posit", "sha256": "1d635d9a56dde15a96d9143c859722404c06634e252b0ca2455bc93d5b502bde"}, {"id": "u007", "kind": "prose", "locator": "body:L144-L144", "preview": "NSA's sparsity pattern is explicitly designed for GPU memory access efficiency:", "sha256": "92ff8ed85d1fccfa7b606ead178b30ad778a673bc3c5c7d13f177e05986f1e0a"}, {"id": "u008", "kind": "list-item", "locator": "body:L146-L146", "preview": "1. **Blockwise memory access**: Selected tokens are organized in contiguous blocks (not scattered individual tokens), exploiting spatial locality for contiguous GPU memory loads", "sha256": "a27d0ca3fbf0c07aa550d5c51800b1dfef7a04988b92749f1925f26e398d93d8"}, {"id": "u009", "kind": "list-item", "locator": "body:L147-L147", "preview": "2. **Group-centric loading**: In GQA configurations, all query heads in a group share the same sparse KV blocks, minimizing redundant KV transfers to shared memory", "sha256": "17b38863fc09180b4e995736b1278a175245a1f99b309d8660e9843b231f9b7b"}, {"id": "u010", "kind": "list-item", "locator": "body:L148-L148", "preview": "3. **Grid-based scheduling**: Triton grid dimensions map directly to (query_block, head, batch), avoiding dynamic scheduling overhead", "sha256": "8a3bcdcd651863ef6a92356ce6ee337bbb8362260281383026c3070863e56f47"}, {"id": "u011", "kind": "table-row", "locator": "body:L154-L154", "preview": "| Sequence Length | Forward Speedup | Backward Speedup | Decoding Speedup | | 64K | 9.0x | 6.0x | 11.6x |", "sha256": "80ab136cc0ff0a479cd4847be0000ec191c0fc23e7c38a4fb1fc16fa0a296a15"}, {"id": "u012", "kind": "prose", "locator": "body:L156-L156", "preview": "All speedups measured against FlashAttention-2 on H100 with BF16 precision.", "sha256": "a1855c4c62f570a8b173052c836888af41f997892c087472cbdc9bff8cb921c6"}, {"id": "u013", "kind": "list-item", "locator": "body:L160-L160", "preview": "- Long-context inference (32K+ tokens) where full attention is prohibitively expensive", "sha256": "f5c3361490c7e595b9012c11594ba45bdbddd8436d7476d422f8086c0f6f808d"}, {"id": "u014", "kind": "list-item", "locator": "body:L161-L161", "preview": "- Models with GQA (grouped query attention) where KV sharing amplifies sparse access efficiency", "sha256": "a6732812a96b98c9e0faaebb801bfd5303aaf9c30678f79900aee29cbbe0b579"}, {"id": "u015", "kind": "list-item", "locator": "body:L162-L162", "preview": "- End-to-end trainable settings requiring differentiable sparsity", "sha256": "9641f9e6ebcdc18d5defb85c178bae645f85ada88c08daf17c1ff6ddc64c89d2"}, {"id": "u016", "kind": "list-item", "locator": "body:L166-L166", "preview": "- The compression path requires a learned MLP, adding parameters and training cost", "sha256": "aebc0ab171f71ff82917cdd60c0a8d2f1ae7579d6880198d5453241ce9e6d998"}, {"id": "u017", "kind": "list-item", "locator": "body:L167-L167", "preview": "- Token selection adds a two-pass overhead (score all blocks, then select top-n)", "sha256": "3a7f8ca8be01afb157ed7811f151a047083a70a2f2e01ec80a8c7fdb81d4cc6e"}, {"id": "u018", "kind": "list-item", "locator": "body:L168-L168", "preview": "- Triton implementation has CPU launch overhead impacting small-batch decode; CUDA graph mode recommended", "sha256": "10abe51f393aaa0f3eeb85f38327ace4d925bbcd1cfb997a8c29e0e75dcfee0e"}, {"id": "u019", "kind": "list-item", "locator": "body:L169-L169", "preview": "- Quality depends on training the sparsity selection jointly with the model", "sha256": "f9e247144bca57e35f16350f906b2009b62f509d708195e2dd652c5dfe343b36"}, {"id": "u020", "kind": "list-item", "locator": "body:L173-L173", "preview": "- [NSA paper (ACL 2025)](https://arxiv.org/abs/2502.11089)", "sha256": "aeae36f3519863ad608fa6d0a24d8e33f365607b54e696e09bf44e8bac633126"}, {"id": "u021", "kind": "list-item", "locator": "body:L174-L174", "preview": "- [PyTorch reference implementation](https://github.com/lucidrains/native-sparse-attention-pytorch)", "sha256": "4bcdf22e3c02c5cb11cac427db84ffaf1d0360b1948790aa645e962819ab7dfe"}, {"id": "u022", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"bf16\", \"gpu\": \"H100\", \"metric\": \"speedup\", \"shape\": \"seqlen=65536\", \"source_id\": \"blog-nsa\", \"utilization\": \"vs FlashAttention-2 forward\", \"value\": 9.0}]", "sha256": "e920d888aa4a8d9d0a24f1064956aa6aa0239a3320fcb6c84dab79a66ded1184"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Three-Path Architecture", "Triton Kernel Implementation", "Sliding Window Component", "Hardware-Aligned Design", "Performance", "When to Use", "Caveats", "Sources"], "id": "kernel-nsa", "path": "wiki/kernels/nsa.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/blogs/nsa.md", "url": "https://arxiv.org/abs/2502.11089"}, {"path": "sources/blogs/flashmla.md", "url": "https://github.com/deepseek-ai/FlashMLA"}, {"path": "sources/blogs/vllm-deepseek-v3-sparse-attention.md", "url": "https://blog.vllm.ai/2025/09/29/deepseek-v3-2.html"}], "risk_flags": ["code", "performance", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-nsa", "blog-flashmla", "blog-vllm-deepseek-v3-sparse"], "title": "Native Sparse Attention (NSA)", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "d176748702ac353341b6d4887c74d36b98deccce13fd42849ac545957b212fa0", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "NVFP4 GEMM is a compute-bound matrix multiplication kernel operating on NVIDIA's native 4-bit floating-point format (E2M1) with block scaling on Blackwell GPUs. Unlike the memory-bound GEMV, GEMM is dominated by tensor core throughput and b", "sha256": "ce8283f8056ebe918e2275feaae294b883597349044d93ca6efee46883ca9177"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "This kernel was Problem 2 of the GPU Mode NVFP4 Hackathon (Nov-Dec 2025), targeting B200 GPUs. Top entries achieved within 1% of cuBLAS performance using CUTLASS SM100 schedules.", "sha256": "3f0d8624af5bd73c405f2ea0a5622c58d394640b3513b6a4feb3e53843adf439"}, {"id": "u003", "kind": "code", "locator": "body:L11-L25", "preview": "``` NVFP4 (E2M1): 4-bit floating point Bit layout: [S][E1][E0][M0] Representable values: 0, 0.5, 1, 1.5, 2, 3, 4, 6 (positive and negative) Block scaling: Every 16 FP4 elements share one FP8 (E4M3) scale factor Two-level: per-block E4M3 + p", "sha256": "b48ac773e3fe79bba2bd76c12caed110a58237a982ad1bef408e7506c7c4c2e5"}, {"id": "u004", "kind": "prose", "locator": "body:L29-L29", "preview": "The kernel uses the `KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100` CUTLASS schedule, which combines TMA async loads with warp-specialized MMA execution.", "sha256": "7bbe8f50a670ca975b03b97d1020bdc5069b5fb6ad28030199f2b00228846247"}, {"id": "u005", "kind": "code", "locator": "body:L31-L55", "preview": "```cpp // CUTLASS dispatch for NVFP4 GEMM on Blackwell using Schedule = cutlass::gemm::KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100; // Tile configuration using TileShape = cute::Shape<_128, _256, _128>; // M, N, K tile using ClusterShape =", "sha256": "4c98ba70e353108efe70336468d8dc8ffc9bfe62eb7c1189ebbd016d30084923"}, {"id": "u006", "kind": "code", "locator": "body:L59-L130", "preview": "```cpp // Warp specialization: TMA producer + MMA consumer + epilogue // Shared memory holds pipelined A/B tiles + scale factors constexpr int NUM_STAGES = 4; // Pipeline depth // Shared memory layout struct SharedStorage { // Double-buffer", "sha256": "4bfed05994aeaa2b02ef97164c721b4233eaf36d6f14e56693b8b605a362d0b3"}, {"id": "u007", "kind": "prose", "locator": "body:L134-L134", "preview": "All TMA operands require 128-byte alignment. For NVFP4 (2 elements per byte), this means K dimensions must be multiples of 256 elements:", "sha256": "107e3196e9fea3e2ce246d8865dfdb3ae0c58873c27c4da2695854de3571f779"}, {"id": "u008", "kind": "code", "locator": "body:L136-L145", "preview": "```cpp // Critical: pad tensors to 128-byte boundaries for TMA // NVFP4: 2 elements per byte, so 256 elements = 128 bytes static_assert(K % 256 == 0, \"K must align to 128 bytes for FP4 TMA\"); // For scale factors: FP8 is 1 byte per element ", "sha256": "73a1b18a73b39446c1e3238a48b853cfd721bcc65071820610e7897e7a7d4636"}, {"id": "u009", "kind": "prose", "locator": "body:L149-L149", "preview": "The tcgen05.mma instruction expects UE8M0 (unsigned power-of-two exponent only) scales, but NVFP4 uses FP8 E4M3 (non-power-of-two). Conversion is needed:", "sha256": "e293e1e221e9b63a67a12c0f53933edc9faae2c7699f6e0f5c58f40160394399"}, {"id": "u010", "kind": "code", "locator": "body:L151-L164", "preview": "```cpp // Convert FP8 E4M3 block scales to UE8M0 for tcgen05.mma hardware // E4M3: 4 exponent bits, 3 mantissa bits (non-power-of-two) // UE8M0: 8 exponent bits, 0 mantissa bits (power-of-two only) __device__ uint32_t pack_scales_ue8m0( fp8", "sha256": "a98e841c1571483f432618b4cbc3012bfc42f8c5f3bed8761620c3f5e259a62b"}, {"id": "u011", "kind": "prose", "locator": "body:L168-L168", "preview": "Problem 2 top performers (geometric mean across benchmark configs):", "sha256": "cc23962d4fbe69a64cf189bafa8fa3fef985173c6339174224fc1630f48b8f02"}, {"id": "u012", "kind": "table-row", "locator": "body:L172-L172", "preview": "| Rank | Participant | Latency (us) | | 1 | Simon | 10.807 |", "sha256": "4be3f007808e68efc483366d7c16278e4fca7890ecf8fee5c6f7feb98f49b9f6"}, {"id": "u013", "kind": "table-row", "locator": "body:L173-L173", "preview": "| Rank | Participant | Latency (us) | | 2 | yue | 10.914 |", "sha256": "dd888bc57d858bbdad18fd18216286e38546341b351e4423cbca9993e06e131b"}, {"id": "u014", "kind": "table-row", "locator": "body:L174-L174", "preview": "| Rank | Participant | Latency (us) | | 3 | currybab | 10.931 |", "sha256": "ce16edd96b3c538db7ecacf7e7cfe138ee22ad0815169eadd0c8775e21a7769c"}, {"id": "u015", "kind": "list-item", "locator": "body:L178-L178", "preview": "- Inference with 4-bit quantized weights on Blackwell", "sha256": "9c9c4cb04e9f62299ba69bcc96fe07af559814f64b515782bfec237e26b6f57e"}, {"id": "u016", "kind": "list-item", "locator": "body:L179-L179", "preview": "- MLP layers in LLMs where weight matrices are NVFP4-quantized", "sha256": "acc382e3fe1a84f55d897e4e762e86b400edb666a30ae6a8f126c424baa34313"}, {"id": "u017", "kind": "list-item", "locator": "body:L180-L180", "preview": "- Compute-bound matrix multiplications where tensor core utilization is the bottleneck", "sha256": "282641f501a8c11c857461aea797f80a634c4d3656705ee7f3bd966b55a35158"}, {"id": "u018", "kind": "list-item", "locator": "body:L184-L184", "preview": "- SM100/SM100a only -- no Hopper support for native FP4 tensor core instructions", "sha256": "2e0b5d1795e2cdc383f29556cc772771a7e428d4e4154543bed78b96c951f2b5"}, {"id": "u019", "kind": "list-item", "locator": "body:L185-L185", "preview": "- Scale factor conversion (E4M3 to UE8M0) adds overhead if not precomputed", "sha256": "84fad3f7e26b6bf7ffe967ce0d273b7430a3528b6cb11dab390424821ac6e771"}, {"id": "u020", "kind": "list-item", "locator": "body:L186-L186", "preview": "- TMA requires 128-byte alignment for all operands", "sha256": "426caf652324604896fd38413cb9b583f16c3ddfba02a6c0915dc9b446992ed1"}, {"id": "u021", "kind": "list-item", "locator": "body:L187-L187", "preview": "- TMEM size (128x512 per SM) limits maximum output tile to 128 rows x 512 cols (32-bit)", "sha256": "de40759ac7c0d44ad789660e5d351ce123ba32e337f1b071516b48c01c65cc87"}, {"id": "u022", "kind": "list-item", "locator": "body:L191-L191", "preview": "- [GPU Mode NVFP4 Hackathon](https://github.com/gpu-mode/reference-kernels)", "sha256": "eebfd002120234da40f3b045095d61fdf901341039f5f3ae98ed1d4bb5bb5a27"}, {"id": "u023", "kind": "list-item", "locator": "body:L192-L192", "preview": "- [NVIDIA NVFP4 Blog](https://developer.nvidia.com/blog/introducing-nvfp4-for-efficient-and-accurate-low-precision-inference/)", "sha256": "8f1860be648139255ba1bef71ce8f3326c3bd2b4d7c539895998ce7876582574"}, {"id": "u024", "kind": "list-item", "locator": "body:L193-L193", "preview": "- [NVFP4 Format Details](https://haroldbenoit.com/notes/ml/engineering/precision/nvfp4-format)", "sha256": "b9bfdf8f815611f8f0fce7864844508d8c211c845cb20d7ca6aa7b4a80bf3d15"}, {"id": "u025", "kind": "list-item", "locator": "body:L194-L194", "preview": "- [CUTLASS SM100 documentation](https://docs.nvidia.com/cutlass/latest/CHANGELOG.html)", "sha256": "75e0801b0814c177427d45c23dae770d0fabd27c5a2c06a826ddc8801ef0c4b4"}, {"id": "u026", "kind": "prose", "locator": "body:L198-L198", "preview": "The reference bundle lives in [`artifacts/kernels/nvfp4-gemm/full/`](../../artifacts/kernels/nvfp4-gemm/full/) and combines the upstream PR-2139 diff (`PR-2139-blockwise-groupwise-gemm.patch`, `mode: upstream-patch`, SHA-pinned to `ca4fdbea", "sha256": "43f6a09758b6a58a1ffade0f14d33f1052c303991109e318f71b207016afdc51"}, {"id": "u027", "kind": "prose", "locator": "body:L200-L200", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u028", "kind": "code", "locator": "body:L202-L204", "preview": "```bash python3 scripts/get_page.py kernel-nvfp4-gemm --include-code ```", "sha256": "eaac2756fbb1565989fcaea0ed73db004ca5ba5fcaea37b1ff1920e7d8d5212a"}, {"id": "u029", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"nvfp4\", \"gpu\": \"B200\", \"metric\": \"latency_us\", \"shape\": \"standard GEMM configs\", \"source_id\": \"contest-gpumode-p2\", \"utilization\": \"near cuBLAS\", \"value\": 10.807}]", "sha256": "c874b5112e8e82ab82ff93848cc722d691926143bea53463233782aeedf2f72b"}], "confidence_claimed": "source-reported", "headings": ["Overview", "NVFP4 Data Format", "CUTLASS SM100 Schedule", "Warp-Specialized Kernel Structure", "128-Byte TMA Alignment", "Scale Factor Conversion", "Competition Results", "When to Use", "Caveats", "Sources", "Full Reference Implementation"], "id": "kernel-nvfp4-gemm", "path": "wiki/kernels/nvfp4-gemm.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/contests/gpu-mode-nvfp4/problem-2-gemm.md", "url": "https://github.com/gpu-mode/reference-kernels"}, {"path": "sources/docs/nvidia-cutlass-blackwell.md", "url": "https://docs.nvidia.com/cutlass/latest/CHANGELOG.html"}, {"path": "sources/prs/cutlass/PR-2139.md", "revision": "ca4fdbea", "url": "https://github.com/NVIDIA/cutlass/pull/2139"}], "risk_flags": ["code", "ordering", "performance", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-gpumode-p2", "doc-cutlass-blackwell", "pr-cutlass-2139"], "title": "NVFP4 GEMM \u2014 4-bit Floating Point Matrix Multiply", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "55d84be3408d0ab5d0adfed5c555998569f294e99d23cfc0c3fd582b32841d7d", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "NVFP4 Batched GEMV is a memory-bound kernel computing batched matrix-vector products with NVFP4 (E2M1) block-scaled inputs on B200 GPUs. Unlike compute-bound GEMM, GEMV is dominated by memory bandwidth utilization (each FP4 element is used ", "sha256": "ddf2e2976bc32e53a2c08102a37d952d37d0e9ba6015679a73d5ee037198c03d"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "This was Problem 1 of the GPU Mode NVFP4 Hackathon (Nov 2025). The theoretical speed-of-light is ~8.6us for the largest config, limited by B200's 8 TB/s HBM3e bandwidth. Top performers achieved ~22.4us (2.6x off SOL), reflecting the overhea", "sha256": "e22574105ba0fcea7e7feafd094b90087950c2484892d27fea2d3f5cafd8c9bb"}, {"id": "u003", "kind": "code", "locator": "body:L11-L30", "preview": "``` Inputs: a: (M x K x L) NVFP4 packed matrix b: (1 x K x L) NVFP4 packed vector sfa: (M x K/16 x L) FP8 E4M3 scale factors for a sfb: (1 x K/16 x L) FP8 E4M3 scale factors for b sf_a_global, sf_b_global: FP32 per-tensor global scales Outp", "sha256": "593e3b7065bd46466a83ad6524ed7becffdd5236b8a813cb54444537d41b74f8"}, {"id": "u004", "kind": "prose", "locator": "body:L34-L34", "preview": "Raw PTX provides critical performance gains over C intrinsics for FP4 decoding and memory access:", "sha256": "d637ccbc1b6e8a2971516ac8d9afbe2235a98237a2674e11165fdc9d421ae829"}, {"id": "u005", "kind": "code", "locator": "body:L36-L48", "preview": "```asm ; FP4 to FP16 conversion: hardware instruction ; Converts two packed E2M1 values to a pair of FP16 values cvt.rn.f16x2.e2m1x2 %result, %fp4_packed; ; Byte unpacking: PTX mov.b32 is faster than manual bitwise ops ; Instead of: val = (", "sha256": "01883c387684bea1a724b6275245c11cc51cd66d7e1fa2eecec4edb57b6b3b3a"}, {"id": "u006", "kind": "prose", "locator": "body:L52-L52", "preview": "Different data access patterns require different cache strategies:", "sha256": "96582c551b986112414b7fc502db5b39cd27f4369a8ec09e2de7b66833c06f61"}, {"id": "u007", "kind": "code", "locator": "body:L54-L66", "preview": "```asm ; Matrix A: streamed once per row, never reused across thread blocks ; Bypass L1 to avoid polluting cache with one-shot data ld.global.L1::no_allocate.v4.u64 {a0,a1,a2,a3}, [addr_a]; ; Vector B: reused across all M rows in a thread b", "sha256": "9394cb76df8b7a184f82675bfb54494032f63ac1ddd5763e356d8a49a45f05c6"}, {"id": "u008", "kind": "prose", "locator": "body:L70-L70", "preview": "Lower register counts force higher occupancy, which is critical for memory-bound kernels where latency hiding dominates:", "sha256": "6d80d1f3bd62cce66c20871851558deef20dd974d527748a3c1d06170c4a65cf"}, {"id": "u009", "kind": "code", "locator": "body:L72-L88", "preview": "```cpp // Rank 1: aggressive register limit for maximum occupancy // nvcc -maxrregcount=32 // Fewer registers -> more warps/SM -> better memory latency hiding // Rank 3: slightly relaxed for more ILP // nvcc -maxrregcount=45 // Launch bound", "sha256": "c73f3b1ac1ea8d45670517fd40b129834cc09a73e82a7f98d2a3ba23511e372b"}, {"id": "u010", "kind": "prose", "locator": "body:L92-L92", "preview": "Compile separate kernels per K dimension, each with full loop unrolling and tuned configs:", "sha256": "f7ccf8749992b568b1109ef36201aa04782f37d819dd0663da2637321d0221d6"}, {"id": "u011", "kind": "code", "locator": "body:L94-L136", "preview": "```cpp // Each K variant compiled separately with optimal configuration template __global__ __launch_bounds__(THREADS, MIN_BLOCKS) void nvfp4_gemv_specialized( const uint8_t* __restrict__ a, const uint", "sha256": "f408db3f15bda5e5a9b15668cca189240053b28770815636470fe6faade9f3d8"}, {"id": "u012", "kind": "prose", "locator": "body:L140-L140", "preview": "128-bit and 256-bit vector loads maximize bandwidth utilization:", "sha256": "5c4e0be8603b74e6fdac3950d76e25b63dbca34f01a6687d2af4deb744cf08c3"}, {"id": "u013", "kind": "code", "locator": "body:L142-L152", "preview": "```asm ; 128-bit vector load (16 bytes = 32 FP4 elements) ld.global.v2.u64 {r0, r1}, [addr]; ; 256-bit vector load (32 bytes = 64 FP4 elements) ld.global.v4.u64 {r0, r1, r2, r3}, [addr]; ; Only effective when combined with PTX byte unpackin", "sha256": "baab73411bcf0112e737f4c527e1b1e6be9272abcdc13a4b550cc3b24ffa1a9a"}, {"id": "u014", "kind": "prose", "locator": "body:L156-L156", "preview": "Since B is shape (1 x K x L), all M rows multiply against the same B vector:", "sha256": "cd580fe75200993177aafa125b8caac723f0db7f5cb43586f9c52b080001df01"}, {"id": "u015", "kind": "code", "locator": "body:L158-L176", "preview": "```cpp // Load B vector into shared memory once per thread block // All BLOCK_M rows reuse the same B data __shared__ half b_shared[K_TILE]; // Cooperative load: all threads in block load a portion of B for (int i = threadIdx.x; i < K_TILE;", "sha256": "f8f9daf87d9f76af0a4d2b6afcb7fca7746cf1d5106eec94c4d11463f95fb1ae"}, {"id": "u016", "kind": "prose", "locator": "body:L180-L180", "preview": "Documented progression from Yue's hackathon blog:", "sha256": "26ffc8446ee7591f95e0921f0a99c9b508614224a585865ebd07c841ec6dec0d"}, {"id": "u017", "kind": "table-row", "locator": "body:L184-L184", "preview": "| Stage | Technique | Latency | | CuTe DSL baseline | Basic CuTe partition/copy | ~100us |", "sha256": "dbf61acd19e989a9176617a1a7ed71ad5cd0ac1dbb93b575121e2fe142ddb333"}, {"id": "u018", "kind": "table-row", "locator": "body:L185-L185", "preview": "| Stage | Technique | Latency | | Coalesced access | Fix memory access patterns | 443us -> 39us |", "sha256": "8466d818ad949a4d14c3d022acea120979d9f0d8c66409305459ef4600f7e4b0"}, {"id": "u019", "kind": "table-row", "locator": "body:L186-L186", "preview": "| Stage | Technique | Latency | | Hardware intrinsics | cvt.rn.f16x2.e2m1x2 | ~39us |", "sha256": "ef3008a7fa097038a3df7f3cc3ef367b2e8d8149ed9ced0ea40c0311974bf314"}, {"id": "u020", "kind": "table-row", "locator": "body:L187-L187", "preview": "| Stage | Technique | Latency | | PTX assembly | Full PTX with byte unpacking | ~27us |", "sha256": "6a7e46856ae9f78e8086b31b0c839c9b7e9600015051fb9280e0ed7117e53f6d"}, {"id": "u021", "kind": "table-row", "locator": "body:L188-L188", "preview": "| Stage | Technique | Latency | | ILP optimization | Instruction-level parallelism | ~22.9us |", "sha256": "e9ef33c4dfa7d478861bca385846cdb9b5ea038df8d9f4cf20c11623ae6cbf56"}, {"id": "u022", "kind": "table-row", "locator": "body:L189-L189", "preview": "| Stage | Technique | Latency | | Final submission | All combined | 22.392us |", "sha256": "1a7a012b2eecf130716f6177ca40799b1db6a8388409e34978a3caa76ec3efa4"}, {"id": "u023", "kind": "list-item", "locator": "body:L193-L193", "preview": "1. **Memory-bound kernels need bandwidth-first thinking**: Arithmetic optimizations have minimal impact; focus on memory access patterns, cache policies, and vectorized loads", "sha256": "94e4ce070d1dd1f4b4e16744890672b8a2b0a8deaeaa55c74c27d17136982c35"}, {"id": "u024", "kind": "list-item", "locator": "body:L194-L194", "preview": "2. **PTX gives real control on Blackwell**: The gap between C intrinsics and hand-written PTX was substantial (443us to 27us in one journey)", "sha256": "9f2dec583d6a4146b6895a993f1b35ae986422246c70b033caf189f59e9a74c1"}, {"id": "u025", "kind": "list-item", "locator": "body:L195-L195", "preview": "3. **Profile first**: \"Run Nsight Compute to confirm memory-bound behavior\" (Amandeep's lesson after 12 attempts)", "sha256": "89fad8352db9048aec2f508a9750f0a52c457eaca28beb045ec08e152189ed8c"}, {"id": "u026", "kind": "list-item", "locator": "body:L196-L196", "preview": "4. **Register budgeting matters**: Lower registers -> higher occupancy -> better memory latency hiding", "sha256": "ac039173525f611aa7ba15b079e0990d411c358d359452e8571da6714c9cfee5"}, {"id": "u027", "kind": "list-item", "locator": "body:L197-L197", "preview": "5. **TMEM is irrelevant**: Memory-bound kernels do not benefit from TMEM (it helps compute-bound only)", "sha256": "cd4d91d3546b5d95261aeec64650a10f414cd52b32648b2b2ce6f1f6401a66f7"}, {"id": "u028", "kind": "list-item", "locator": "body:L201-L201", "preview": "- Decode-time MLP with batch size 1 (matrix-vector product)", "sha256": "f0a3de733e17a84015022e7a167ff14760cd4be1214ebfc988ddd6f8607128a0"}, {"id": "u029", "kind": "list-item", "locator": "body:L202-L202", "preview": "- Any NVFP4 workload where arithmetic intensity is too low for tensor cores", "sha256": "05859aa883b9a64883a90530cfa67b10d6007bf18ee27bb7cce31fc9111e6c24"}, {"id": "u030", "kind": "list-item", "locator": "body:L203-L203", "preview": "- Memory-bound operations with FP4 quantized weights", "sha256": "9cf5987a17e3202b9a1869766f23e0d7f345d99c3500a859627d9a6bd6edad8b"}, {"id": "u031", "kind": "list-item", "locator": "body:L207-L207", "preview": "- SM100/SM100a only (native FP4 decode instructions)", "sha256": "b4df75d26bf305f3c801fe6d6e96aa132f3fb57be630527b5ef96819c0f7dc16"}, {"id": "u032", "kind": "list-item", "locator": "body:L208-L208", "preview": "- PTX-level optimizations are fragile across CUDA toolkit versions", "sha256": "eb99e04c1e335c78e87dfb07807f938053e87f99ba5cf781b2b383a7eefda98e"}, {"id": "u033", "kind": "list-item", "locator": "body:L209-L209", "preview": "- Per-K specialization increases binary size (one kernel per K variant)", "sha256": "6ddb221452eeb25cf5e57ff8a82b855caeaf502d78aacf110e39f3fd97b726f2"}, {"id": "u034", "kind": "list-item", "locator": "body:L210-L210", "preview": "- Speed-of-light is bounded by B200 memory bandwidth (8 TB/s)", "sha256": "4b4f2fdfdc85b49814d3e63e8c61961c33736dcaffdd90ab851d930c70eb12c1"}, {"id": "u035", "kind": "list-item", "locator": "body:L214-L214", "preview": "- [GPU Mode NVFP4 Hackathon](https://github.com/gpu-mode/reference-kernels)", "sha256": "eebfd002120234da40f3b045095d61fdf901341039f5f3ae98ed1d4bb5bb5a27"}, {"id": "u036", "kind": "list-item", "locator": "body:L215-L215", "preview": "- [Yue's Hackathon Journey](https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html)", "sha256": "cf4d40ec9bc3d2a377968ec4fa11dcbe1a345085ff9ac0a296f1bbc5ca1c0ef4"}, {"id": "u037", "kind": "list-item", "locator": "body:L216-L216", "preview": "- [Twelve Attempts (Amandeep)](https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/)", "sha256": "b37eef4af82c15ab511f375b1eedd075fc2aa8b69a5598dd24b8e1478512ba81"}, {"id": "u038", "kind": "list-item", "locator": "body:L217-L217", "preview": "- [Simon's NVFP4 GEMV Blog](https://veitner.bearblog.dev/nvfp4-gemv/)", "sha256": "ac74cca9c7638c984b34a0027171297163dc5ac9e31a60a01df836eb06e20f0b"}, {"id": "u039", "kind": "prose", "locator": "body:L221-L221", "preview": "Local verbatim upstream code lives in [`artifacts/kernels/nvfp4-gemv/full/`](../../artifacts/kernels/nvfp4-gemv/full/) (see its `PROVENANCE.yaml` for the pinned upstream SHA and byte-verified SHA-256). Labeled derived variants \u2014 including a", "sha256": "1c2e2f79a21dc048f98be366befc6db0fdd07be639f7cb2df9816a0f5d2627e8"}, {"id": "u040", "kind": "prose", "locator": "body:L223-L223", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u041", "kind": "code", "locator": "body:L225-L227", "preview": "```bash python3 scripts/get_page.py kernel-nvfp4-gemv --include-code ```", "sha256": "de75e93b2e63468e12728068d06362610599f17e00c4342bf1b2b26d0c0bb63e"}, {"id": "u042", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"nvfp4\", \"gpu\": \"B200\", \"metric\": \"latency_us\", \"shape\": \"M=7168, K=16384, L=1\", \"source_id\": \"contest-gpumode-p1\", \"utilization\": \"~2.6x of SOL (8.6us)\", \"value\": 22.4}]", "sha256": "bb8b8a6640e57e3d597d751ab5cacce0f1e6e6a94666c6c5db1bc6c59a22cd07"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Problem Specification", "Key Optimization: PTX-Level Control", "Cache Policy Differentiation", "Register Budgeting", "Per-K Specialization", "Vectorized Loads", "Data Reuse (Rank 2 Approach)", "Performance Progression", "Key Lessons", "When to Use", "Caveats", "Sources", "Full Reference Implementation"], "id": "kernel-nvfp4-gemv", "path": "wiki/kernels/nvfp4-gemv.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/contests/gpu-mode-nvfp4/problem-1-gemv.md", "url": "https://github.com/gpu-mode/reference-kernels"}, {"path": "sources/blogs/yue-nvfp4-hackathon.md", "url": "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"}, {"path": "sources/blogs/amandeep-nvfp4-attempts.md", "url": "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"}], "risk_flags": ["code", "performance", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-gpumode-p1", "blog-yue-nvfp4", "blog-amandeep-nvfp4"], "title": "NVFP4 Batched GEMV", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "3a4b0e533208cfbbe45f6c7c15396a5e66007ed4a56f0ca9699e034a5b36b628", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Sparse Multi-head Latent Attention introduced in DeepSeek V3.2. Two-stage pipeline: (1) Lightning Indexer selects top-K tokens per query via FP8 scorer, (2) MLA runs only over selected tokens. This reduces decode attention compute from O(se", "sha256": "5fdcccb688e3f564691436a0e5b6472b88e4a9431c7db91971954f5504852a3a"}, {"id": "u002", "kind": "code", "locator": "body:L9-L27", "preview": "``` Query q_t (new token embedding) \u2502 \u25bc \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u2502 Lightning Indexer \u2502 FP8 scorer, per-query top-K selection \u2502 - FP8 KV cache \u2502 h64, d128, topk=2048, page_size=64 \u2502 - Compute q\u00b7k_i scores \u2502 \u2502 - Select top-2048 i \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500", "sha256": "ce37d3974c8d5aba22eda5f37640aeaa8876cc39c0ec33d917dc7d01fed35e7e"}, {"id": "u003", "kind": "prose", "locator": "body:L31-L31", "preview": "Each KV cache entry is 656 bytes:", "sha256": "c34c647b6c4b0b7f9d93660cf35b79aadd81a97c0c489c79aae5d0a61f8a1fb4"}, {"id": "u004", "kind": "list-item", "locator": "body:L32-L32", "preview": "- 512 bytes: FP8 compressed KV data", "sha256": "8a0deb14b534e602728f848c4c40a1ee7eaebe8ea159f1be7bc6f1c888b75c17"}, {"id": "u005", "kind": "list-item", "locator": "body:L33-L33", "preview": "- 16 bytes: FP32 per-block scale factors", "sha256": "a275a8a2a9afa0544a06c32108aed3e3921e129571e060bbae077fcc7531b249"}, {"id": "u006", "kind": "list-item", "locator": "body:L34-L34", "preview": "- 128 bytes: BF16 RoPE embeddings (for indexer positional encoding)", "sha256": "946fd7b96cacd39e9ce0b5e338d694e32824a32db665b4378cac3e5b02b84ea7"}, {"id": "u007", "kind": "prose", "locator": "body:L36-L36", "preview": "Block size fixed at 64 (FlashMLA requirement).", "sha256": "d51e2f780cfb646e05d1c319e88a07eb826c00ddf298639894319965fd2c5a24"}, {"id": "u008", "kind": "code", "locator": "body:L41-L60", "preview": "```cuda // Score each KV block against query using FP8 block-scale MMA // Reduce to per-block max, then top-K selection across blocks __global__ void lightning_indexer_kernel( const fp8_t* q_fp8, // [h, d] query (FP8 quantized) const fp8_t*", "sha256": "dd9861d5434c4e848d82a6368267fa9cec26be9415ab60b0acb4190782fcc914"}, {"id": "u009", "kind": "code", "locator": "body:L63-L79", "preview": "```cuda // After top-K selection gives indices, gather K,V from paged cache // Then run standard MLA on the gathered subset __global__ void sparse_mla_decode_kernel( const int* topk_indices, // [2048] selected block indices const fp8_t* kv_", "sha256": "f774e41d4f3b84d4aac68aaf3c529e769a8815005181aa97697d26c19b4e6f11"}, {"id": "u010", "kind": "table-row", "locator": "body:L85-L85", "preview": "| Variant | GPU | TFLOPS | Notes | | Dense MLA decode | H800 | 660 (BF16) | 3000 GB/s, compute-bound |", "sha256": "73f0ff01a0cf401a3c4084d29e92d611fad71aea2b451e4dc435c79dfdcc18fd"}, {"id": "u011", "kind": "table-row", "locator": "body:L86-L86", "preview": "| Variant | GPU | TFLOPS | Notes | | Sparse MLA decode | H800 | 410 (FP8) | Token-level sparsity |", "sha256": "64ba139820ee276c80384043854f02370906e91e8a605e79520379be4a2d9c63"}, {"id": "u012", "kind": "table-row", "locator": "body:L87-L87", "preview": "| Variant | GPU | TFLOPS | Notes | | Sparse MLA decode | B200 | 350 (FP8) | Lower because bandwidth dominates decode |", "sha256": "8ed650a75ae8c30618f625619d36d3294ff3a342b06f082141c499b230b5800d"}, {"id": "u013", "kind": "table-row", "locator": "body:L88-L88", "preview": "| Variant | GPU | TFLOPS | Notes | | Dense prefill | B200 | 1460 (BF16) | tcgen05 peak |", "sha256": "8b5fb0d0411f07913282f333e0ec5b4799c24984a97d419b2753b6dd1ea7e4a0"}, {"id": "u014", "kind": "table-row", "locator": "body:L89-L89", "preview": "| Variant | GPU | TFLOPS | Notes | | Sparse prefill | B200 | 1450 (FP8) | FP8 sparse matches BF16 dense |", "sha256": "8b2958699e9a8520ec8695ef396558b37046d7f59cea685235b5df93e99e613c"}, {"id": "u015", "kind": "list-item", "locator": "body:L93-L93", "preview": "- Long-context LLM serving (32K+)", "sha256": "04381fa5d49d580e858be9ced13557503ccc96911883b97b013f2095f7b49632"}, {"id": "u016", "kind": "list-item", "locator": "body:L94-L94", "preview": "- DeepSeek V3.2 and similar MLA architectures", "sha256": "0bedbfae44643280304ba37348fbc04dc58c4a13ef33ee8c1f09a102fcadc593"}, {"id": "u017", "kind": "list-item", "locator": "body:L95-L95", "preview": "- Serving workloads where per-token decode latency matters", "sha256": "7d24f2d08acbe8deb2b51747711536108edfb5bb14713b1ce0c0bc0f566e11ff"}, {"id": "u018", "kind": "metadata-performance", "locator": "frontmatter:performance_claims", "preview": "[{\"dtype\": \"fp8\", \"gpu\": \"B200\", \"metric\": \"TFLOPS\", \"shape\": \"sparse prefill, seqlen=32k, topk=2048\", \"source_id\": \"blog-flashmla\", \"utilization\": \"FP8 sparse compute bound\", \"value\": 1450}]", "sha256": "df7016cefcf58c26abf29b326c6b4d91680d1c3ab23431d5d80a807cf87cd85d"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Architecture", "Token Layout", "Kernel Patterns", "Lightning Indexer (FP8 Score Compute)", "Sparse Attention Gather", "Performance", "When To Use"], "id": "kernel-sparse-mla", "path": "wiki/kernels/sparse-mla.md", "performance_claim_count": 1, "resolved_sources": [{"path": "sources/blogs/flashmla.md", "url": "https://github.com/deepseek-ai/FlashMLA"}, {"path": "sources/blogs/vllm-deepseek-v3-sparse-attention.md", "url": "https://blog.vllm.ai/2025/09/29/deepseek-v3-2.html"}, {"path": "sources/blogs/nsa.md", "url": "https://arxiv.org/abs/2502.11089"}], "risk_flags": ["code", "performance", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-flashmla", "blog-vllm-deepseek-v3-sparse", "blog-nsa"], "title": "Sparse MLA (DeepSeek V3.2)", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "c6277510118240c58c46ecfd1a84c7978461c9a65c84b4f74cbd679662dae2d1", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L6", "preview": "TensorRT-LLM PR 13340 integrates an FP4 indexer path for DSA on Blackwell and lands CUDA kernels for K-cache gather/scatter and fused FP4 concatenation. Use it as implementation evidence for sparse indexer memory movement and quantized cach", "sha256": "dbb05c921fd9eed27b25b1d13cbfcf15cc04132eb00639df9f04f2fb896b3bbb"}, {"id": "u002", "kind": "code", "locator": "body:L8-L17", "preview": "```cuda // Evidence checklist before adapting the idea: // 1. Inspect indexerKCacheGather.cu and indexerKCacheScatter.cu. // 2. Check the scale and FP4 packing layout. // 3. Benchmark gather/scatter separately from top-k selection. __global", "sha256": "c052dcb48a143a6c4d9ca4f59a8f736b7a0b0777ccecbd19417a7ea606adc73b"}, {"id": "u003", "kind": "list-item", "locator": "body:L21-L21", "preview": "- Keep FP4 packing, scale placement, and invalid-token handling explicit in the", "sha256": "f06cc5d4961ff51c22ff24f0be7521c353dd487bbc64a63abcb69813e6beabd2"}, {"id": "u004", "kind": "prose", "locator": "body:L22-L22", "preview": "correctness reference.", "sha256": "a29c197ecd7a5d8c55cf4f4d4bd79ad2451bab53066fda1647ea0f3b7f0c77f4"}, {"id": "u005", "kind": "list-item", "locator": "body:L23-L23", "preview": "- Treat gather/scatter traffic as a separate NCU profile target.", "sha256": "5f57eb07793d8a28665e648e34c56053130668339053fe55de9292182528c9b4"}, {"id": "u006", "kind": "list-item", "locator": "body:L24-L24", "preview": "- Avoid merging this with top-k selection until the memory path is understood.", "sha256": "455e2b81960ea59be68ecf14ddad9acdf4f9a90c34d160e34b3acb3361294b4e"}], "confidence_claimed": "source-reported", "headings": ["Shape", "Transfer Notes"], "id": "kernel-tensorrt-llm-blackwell-indexer", "path": "wiki/kernels/tensorrt-llm-blackwell-indexer.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/prs/TensorRT-LLM/PR-13340.md", "revision": "897c4bff", "url": "https://github.com/NVIDIA/TensorRT-LLM/pull/13340"}], "risk_flags": ["code"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["pr-TensorRT-LLM-13340"], "title": "TensorRT-LLM Blackwell FP4 DSA Indexer", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "7a58194cb413f25af6db71a4e0d90828273f461ee66232063fb6e6a96176d836", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Plain CUDA C++ with inline PTX is used for hand-optimized Blackwell kernels. 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Python bin", "sha256": "a46e0b83297c1af1597dcef52c6cdee33321e1ab19179f820e86ed0fbd94af3e"}, {"id": "u021", "kind": "prose", "locator": "body:L101-L101", "preview": "The `fp16_gemm_{0..6}.py` series from `examples/python/CuTeDSL/blackwell/tutorial_gemm/` in NVIDIA/cutlass PR-3106 is the authoritative CuTe DSL learning path: it walks from a naive FP16 GEMM baseline through 2CTA MMA with TMA multicast, wa", "sha256": "4a4f5e738f8ffaf62825c5ac488ac75ccce782bce6e1902daa6b927d1cd473c8"}, {"id": "u022", "kind": "list-item", "locator": "body:L104-L104", "preview": "- [tcgen05-mma](../hardware/tcgen05-mma.md) \u2014 Underlying MMA instruction", "sha256": "865831018843436afb60a211da0239b6699acc87cacad5a279c5bcc602cc1ff7"}, {"id": "u023", "kind": "list-item", "locator": "body:L105-L105", "preview": "- [flash-attention-4](../kernels/flash-attention-4.md) \u2014 CuTe-DSL implementation", "sha256": "691d3063c66f516ddeda6475ae8a66e2b0445804b11056a1ecdc647362d5d5b0"}, {"id": "u024", "kind": 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valid tile_id or decline (all work done) ```", "sha256": "160bc0e02144188c7c23c0c2235a8ee63f2a0d1f8ee62aa53f5ee8102965cfa6"}, {"id": "u006", "kind": "code", "locator": "body:L66-L74", "preview": "```ptx // Bulk tensor copy: global \u2192 shared cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [smem_ptr], [tensorMap, {x, y}], [mbarrier]; // Multicast to cluster SMs cp.async.bulk.tensor.2d.shared::cluster.gl", "sha256": "74e1444f94a65881a33de14124fc353554d4e3e0eb34e3492ef64bbd1bd674b5"}, {"id": "u007", "kind": "list-item", "locator": "body:L77-L77", "preview": "- [cuda-cpp](cuda-cpp.md) \u2014 Inline PTX in CUDA C++", "sha256": "ba5d88a5192f94c29602f9ab9bbba9f6a19fee52e6b33bcf9835875be760d322"}, {"id": "u008", "kind": "list-item", "locator": "body:L78-L78", "preview": "- [tcgen05-mma](../hardware/tcgen05-mma.md) \u2014 MMA instruction details", "sha256": "3a6c8e4e3cafa675efc3378a216626ae375403e2470481b7f2abd6a7c2f41c1c"}, {"id": "u009", "kind": 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"kernel-wiki-verifier-queue/v2", "source_ids": ["doc-ptx-isa-sm100", "doc-nvidia-tuning-guide", "blog-yue-nvfp4"], "title": "PTX Instructions for SM100", "type": "language", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "6b9394376db86dd1090ef2012a0d599ad3ac0703f7df8c9bbf9c61c4c24888f1", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Triton is used for many attention and linear-attention kernels (NSA, GatedDeltaNet, FLA). Starting with Triton 3.6 (released `2026-01-21`), Triton ships native Blackwell (SM100) lowering through `tcgen05.mma` + Tensor Memory (TMEM). The ear", "sha256": "68c1e1ebd182e1cf65c87bbc3aa111708409c0ac52cd3cba9642f2c61ab0b60d"}, {"id": "u002", "kind": "prose", "locator": "body:L5-L5", "preview": "When to use Triton on Blackwell:", "sha256": "99f63952870fe924c0c2afdc97eed4a59db391ea1d10ed687fb707e09478bbae"}, {"id": "u003", "kind": "list-item", "locator": "body:L6-L6", "preview": "- Rapid prototyping (Triton's fast turnaround still beats CuTe-DSL for exploration)", "sha256": "7106ba7a2d42f73bc2819ab5474eea4c8e40168ebf0d54908a73b319cf9d0215"}, {"id": "u004", "kind": "list-item", "locator": "body:L7-L7", "preview": "- Memory-bound kernels (bandwidth is bottleneck, not compute)", "sha256": "d5703150710b9a3c91076484d05190e79efab6ae8282c1eee43f4cc6a6edf397"}, {"id": "u005", "kind": "list-item", "locator": "body:L8-L8", "preview": "- Linear / sparse attention (GatedDeltaNet, FLA, NSA) where Triton's grid scheduling is convenient", "sha256": "0cee3020ba8376c55f33911b0db4d2d3eb77949b89886bb0c51ecf91362b5645"}, {"id": "u006", "kind": "list-item", "locator": "body:L9-L9", "preview": "- Block-scaled matmul on Blackwell via `tl.dot_scaled` (NVFP4 / MXFP families) \u2014 first-class hardware-accelerated path", "sha256": "93c0626d62e7d2e2525d085be1d273c8845fda5f27cc78568536ba4835262900"}, {"id": "u007", "kind": "list-item", "locator": "body:L10-L10", "preview": "- Warp-specialized descriptor/TMA matmul kernels following the Triton persistent matmul tutorial pattern", "sha256": "c8d8013eb08d22b81a5ae1d53b6a21e0211868a3e3eac50995bcf459449b2e0f"}, {"id": "u008", "kind": "prose", "locator": "body:L12-L12", "preview": "Use CuTe-DSL / CUTLASS / FA-4 / TRT-LLM instead when:", "sha256": "78cf262304ba579a7354fc2e07a8827c68d4fc94027e8260534cf282d1b8b2a7"}, {"id": "u009", "kind": "list-item", "locator": "body:L13-L13", "preview": "- Peak-performance compute-bound matmul or attention on Blackwell. SGLang `pr-sglang-5390` measured a CUTLASS `tcgen05_mla` backend ~27% faster than the Triton MLA decode baseline on Blackwell.", "sha256": "ca4c5776bb00da09dd5d04a4a6806210fd0471e2180e1e1d568d78a63411b84e"}, {"id": "u010", "kind": "list-item", "locator": "body:L14-L14", "preview": "- Production routing where vendor kernels are mature: SGLang `pr-sglang-21595` changes Blackwell datacenter multimodal attention default from `triton_attn` to FA-4.", "sha256": "4c44600cade1a267bcd0dacecde9da7640ae7ac7529dccd5864f2310043d99b7"}, {"id": "u011", "kind": "prose", "locator": "body:L18-L18", "preview": "The 3.6 release adds Blackwell-native infrastructure for `tcgen05.mma`, TMEM allocation/copy/load/store, and warp-specialization plumbing. Source-of-record: [`doc-triton-3.6-blackwell`](../../sources/docs/triton-3.6-blackwell.md). Per-pathw", "sha256": "2c81d91397865a1c3476a3e15febe3df9696ebd0858023bd636690b8f6d84038"}, {"id": "u012", "kind": "prose", "locator": "body:L20-L20", "preview": "Verified lowering surfaces (with caveats):", "sha256": "6b7646c310ebd8dbe8c3dd34c1953b9e876e6a010fe44a51fb330035edacecf3"}, {"id": "u013", "kind": "list-item", "locator": "body:L22-L22", "preview": "1. **Descriptor/TMA + `tl.range(warp_specialize=True)` + `tl.dot`** \u2014 strongest checked `tl.*`-surface evidence. The official Triton persistent matmul tutorial states the warp-specialized mode \"only works on Blackwell right now\"; backed by ", "sha256": "3da89a1067d83982cc596e84e2b315d10af0dfabe7739ef01dc9b4a0951abe68"}, {"id": "u014", "kind": "list-item", "locator": "body:L24-L24", "preview": "2. **`tl.dot_scaled` block-scaled matmul** \u2014 hardware-accelerated by fifth-generation Tensor Cores on compute capability 10. The 3.6 dialect doc exposes `ttng.tc_gen5_mma_scaled` with TMEM-token semantics plus `ttng.tmem_copy`. Source PRs: ", "sha256": "041ce1df4122f743e2a4351708052ae46587b967d589fdcf4e76c1b3be33b0c2"}, {"id": "u015", "kind": "list-item", "locator": "body:L26-L26", "preview": "3. **Gluon front-end + `gl.warp_specialize` + `num_ctas`** \u2014 the most explicit Blackwell-native surface. Initial 2-CTA cluster support landed in `#8644`, `#8653`; `num_ctas` plumbing in `#8645`; Gluon-side `tcgen05 mma scaled` in `#8393`. T", "sha256": "052ff6a643f32c125fc1222c3f9c5382323575416d3bc07ea7852777237259c6"}, {"id": "u016", "kind": "prose", "locator": "body:L28-L28", "preview": "Caveats \u2014 what the verified evidence does and does not establish:", "sha256": "8bcc3f5f74ca29ecfbbb9e7f670dc6efde9c6fa11c589da806df7759fd81d198"}, {"id": "u017", "kind": "list-item", "locator": "body:L29-L29", "preview": "- **What is verified**: the Triton 3.6 release adds tcgen05 + TMEM lowering infrastructure (per `doc-triton-3.6-blackwell`), and tracked downstream repos are landing real Triton kernel changes for SM100 post-3.6 (per `pr-vllm-34597`, the po", "sha256": "d0aa1fe2560f903a0823d77f822d78e5755837df4e85cd620f3e0f5176832deb"}, {"id": "u018", "kind": "list-item", "locator": "body:L30-L30", "preview": "- **What is not yet verified by in-corpus evidence**: that arbitrary plain `tl.dot` kernels AUTOMATICALLY emit `ttng.tc_gen5_mma` / `tcgen05.*` PTX on every shape and configuration. The 3.6 infrastructure exists (`#8136`, `#8148`, `#8202`, ", "sha256": "331695984a8664306f55438dedd3f9afd0f47bc326a5c1fc8ad7e90c87e3162b"}, {"id": "u019", "kind": "list-item", "locator": "body:L31-L31", "preview": "- **What is also not yet verified**: that fused attention forward kernels with `warp_specialize=True`, `tl.dot_scaled` block-scaled matmul, and Gluon multi-CTA paths produce the same lowering as the upstream Triton tutorials predict \u2014 the u", "sha256": "10a0b53c649641ed48d679542645272c26e44cbc463d67aae953da68a755b4d6"}, {"id": "u020", "kind": "prose", "locator": "body:L35-L35", "preview": "Before Triton 3.6, the Blackwell story was: the compiler generated `wgmma.mma_async`, accumulators stayed in registers, and direct `tcgen05` / TMEM access was unavailable from `tl.*`. Pages and inclusion-policy text written under that premi", "sha256": "96669fb791d41bc9dd0173379a54c56be9df068d0a82a155dce6fca621929355"}, {"id": "u021", "kind": "prose", "locator": "body:L39-L39", "preview": "The `evidence_basis` is anchored on:", "sha256": "e8e7fa69ca365c3d43689787d5e25dd981201fbb79b59ed6217e96ae0f0f5b51"}, {"id": "u022", "kind": "list-item", "locator": "body:L41-L41", "preview": "- **`doc-triton-3.6-blackwell`** (`source_category: official-doc`) \u2014 verifies that Triton 3.6 ships native Blackwell lowering infrastructure (TMEM, tcgen05, warp_specialize plumbing, Gluon multi-CTA / 2CTA, tl.dot_scaled). This is the \"infr", "sha256": "9cced2b3ad96d73f2b42f402467eaed85cde8d0eae5eec8bf4f5f0a879f67670"}, {"id": "u023", "kind": "list-item", "locator": "body:L42-L42", "preview": "- **`pr-vllm-34597`** (`source_category: upstream-code`) \u2014 **post-refresh primary anchor**: vLLM's \"[Kernel] Add FP8 KV cache support to Triton MLA decode attention\" PR (merged 2026-02-16, post-Triton-3.6.0 release; `architectures: [sm100]`", "sha256": "903f1359948e7ce1dfba87979ad12bedd24310c2620d3c1f9f1898d132864107"}, {"id": "u024", "kind": "prose", "locator": "body:L44-L44", "preview": "Together the two anchors establish that **the 3.6+ Blackwell lowering infrastructure is real AND tracked downstream repos are landing real Triton matmul kernels for Blackwell production decode paths today** \u2014 which is the substance of the r", "sha256": "4fb8f623c148a0321ef35123e67752145aa91121f2d4c61a34601f50c860b5dd"}, {"id": "u025", "kind": "prose", "locator": "body:L46-L46", "preview": "Two clarifications about what these anchors do NOT prove (since the verified-surface section above flags some shapes as needs-verification):", "sha256": "2840a770688d2dbb0bdec8c34db137c5158a5ec68f32166a3388542caf8671c6"}, {"id": "u026", "kind": "list-item", "locator": "body:L48-L48", "preview": "- The anchors do not prove that EVERY plain `tl.dot` kernel on SM100 emits `tcgen05.mma` PTX. They prove that real Triton kernels with `tl.dot` matmul are landing on Blackwell-only paths in tracked downstream repos (per `pr-vllm-34597`'s `t", "sha256": "b2259ca9d74882d66a8a3a7f562dba7c99e0c587a1f2561445eb75a29b9660b3"}, {"id": "u027", "kind": "list-item", "locator": "body:L49-L49", "preview": "- The anchors do not include explicit inspectable `tcgen05.mma` PTX dumps from a tracked-downstream merged PR. Such proof would be an even stronger anchor than what we have today; until one is found, the verified claim should be read as \"Tr", "sha256": "a2902fb92a5d5f28c8037e2c2f4c0032aac766e60002a42261e7bb2f5a4ff609"}, {"id": "u028", "kind": "prose", "locator": "body:L51-L51", "preview": "Supplementary post-refresh anchor: [`pr-vllm-29339`](../../sources/prs/vllm/PR-29339.md) \u2014 vLLM bugfix that scopes the upstream `triton_kernels` library (the `triton-lang/triton/python/triton_kernels` collection shipped with Triton 3.6) to ", "sha256": "47a0e126b913be9524249f01d1d624182ba7752d28cee3a78c56689cb7ca14b7"}, {"id": "u029", "kind": "prose", "locator": "body:L53-L53", "preview": "Pre-refresh historical anchors (retained as supplementary context, not as AC-1.1 \"new tracked-repo PR page\" evidence on their own):", "sha256": "164da0b6b74ed9ba4f4389a6b1d5b15fcd8f80c767f60ab0d88058d65214ee74"}, {"id": "u030", "kind": "list-item", "locator": "body:L55-L55", "preview": "- [`pr-sglang-22079`](../../sources/prs/sglang/PR-22079.md) \u2014 Gemma4 NVFP4 SGLang `extend_attention` Triton kernel doing actual `tl.dot(q,k)` / `tl.dot(p,v)` matmul on `[sm100, sm90]`, merged 2026-04-03. Strongest in-corpus example of a rea", "sha256": "5ace890ab5dca85799b653f7068541d368172760e0a9e4b41ff7cc9fea4d4db9"}, {"id": "u031", "kind": "list-item", "locator": "body:L56-L56", "preview": "- [`pr-sglang-21019`](../../sources/prs/sglang/PR-21019.md) \u2014 Qwen3.5 GDN projection fused split/reshape/cat kernel merged 2026-03-20. `tl.load`/`tl.store` only (memory rearrangement, no `tl.dot`); demonstrates \"Triton on SM100 post-3.6\" bu", "sha256": "213d5820b7ec1e853f582efea1546f48f255d8c38735d0d0d0d597774dbfbcea"}, {"id": "u032", "kind": "prose", "locator": "body:L58-L58", "preview": "Caveat anchors `pr-sglang-5390`, `pr-sglang-21595`, and `pr-pytorch-175826` provide ecosystem context (CUTLASS still leads on peak; Blackwell defaults moved away from triton_attn for some workloads; CI moved to CUDA 13.0).", "sha256": "ea97074144a30f3926298412a14b091f1119deec63d40f55e4b8ebf4cfedbfbc"}, {"id": "u033", "kind": "prose", "locator": "body:L62-L62", "preview": "The following table reflects benchmark snapshots from when the original page was written (Triton 3.5 era) and is preserved for historical reference. It does NOT reflect the 3.6+ tcgen05 path.", "sha256": "589d3b8ff644ac6f23bb7835dae83eb858acff99b876aa94c2b81e9bc3c41e3d"}, {"id": "u034", "kind": "table-row", "locator": "body:L66-L66", "preview": "| Model | Avg Speedup vs FlashInfer | Resolved % | | Gemini 2.5 Pro | 0.628x | 73.1% |", "sha256": "25c2678c28908e2d85210e1ff0629d8191217089f7e4b450b745eef050592a4c"}, {"id": "u035", "kind": "table-row", "locator": "body:L67-L67", "preview": "| Model | Avg Speedup vs FlashInfer | Resolved % | | GPT-5 | 0.467x | 92.3% |", "sha256": "60ca879e235ec816f205afb6233e07b1183ffe29c81bbe6344d6dc30388d420d"}, {"id": "u036", "kind": "table-row", "locator": "body:L68-L68", "preview": "| Model | Avg Speedup vs FlashInfer | Resolved % | | Claude Opus 4.1 | 0.456x | 73.1% |", "sha256": "0d5529e82c81a2771bf9dd829984c3b0c7827e2b4a31686ad99c859f8b45db91"}, {"id": "u037", "kind": "prose", "locator": "body:L70-L70", "preview": "A re-run on Triton 3.6 with FlashInfer-Bench is not yet available locally; future refresh rounds should update this table or remove it in favor of a pointer to the live leaderboard.", "sha256": "864a6cf965f86e44f206bdef59f8b49d4b532848e43f18eb861b8c64de516994"}, {"id": "u038", "kind": "code", "locator": "body:L74-L97", "preview": "```python @triton.jit def gated_delta_net_decode( Q, K, V, Gate, State, Output, qk_dim: tl.constexpr, v_dim: tl.constexpr, d: tl.constexpr, ): \"\"\"Single-token decode: O(d^2) per token.\"\"\" head_id = tl.program_id(0) # Load recurrent state S:", "sha256": "c32dc200aede94bda1a3d670f731b6387fe8938e41abbbd569b42bedf4424d56"}, {"id": "u039", "kind": "code", "locator": "body:L101-L115", "preview": "```python @triton.jit def sparse_attention_fwd(Q, K, V, Output, TopK_Indices, block_size: tl.constexpr, topk: tl.constexpr): \"\"\"Attend to top-k sparse token blocks only.\"\"\" qid = tl.program_id(0) q = tl.load(Q + qid * d + tl.arange(0, d)) a", "sha256": "ccf600826ff33b56d14444be3059e320e7862611dbda1836f2ef520a0a6dcaa7"}, {"id": "u040", "kind": "prose", "locator": "body:L119-L119", "preview": "> The text in this subsection describes Triton 3.5 and earlier. It is preserved for historical accuracy and is NOT a current statement about Triton 3.6+ behavior. Do not cite it as current limitations.", "sha256": "6da22b6a5ba9c96e7aee776b8ef9a69c728bc3e33c85247134e7bc4d4a2571fe"}, {"id": "u041", "kind": "prose", "locator": "body:L121-L121", "preview": "Triton on Blackwell \u2014 Triton 3.5 and earlier:", "sha256": "4f3ef9bb6276d23f39ec6a6cbdf1a3c61ff279369b835f2865345dc4f5aa0e11"}, {"id": "u042", "kind": "list-item", "locator": "body:L123-L123", "preview": "1. **No direct tcgen05 access**: Triton compiler generates wgmma, not tcgen05.", "sha256": "3711959113947130cc509a9ee6c46aaae3ce072abea715211ee6a8770d3a3e91"}, {"id": "u043", "kind": "list-item", "locator": "body:L124-L124", "preview": "2. **No TMEM**: accumulators stay in registers.", "sha256": "0e2de98756b24e1d67726b5699dedcf07f22197cb627ee2bf8ac3a74d183380e"}, {"id": "u044", "kind": "list-item", "locator": "body:L125-L125", "preview": "3. **CPU launch overhead**: impacts small-batch decode latency.", "sha256": "5680cc69a442094ff4ceeb606c6dbe51a26078232b94ee0b3dfe5686ddb6132e"}, {"id": "u045", "kind": "list-item", "locator": "body:L126-L126", "preview": "4. **Workaround**: CUDA graphs (vLLM default for GatedDeltaNet).", "sha256": "81945cbd6eea1657a6f40f973f16264c806ad364d52cc5ebc475f58ef4362f6f"}, {"id": "u046", "kind": "prose", "locator": "body:L128-L128", "preview": "These four bullets describe the world before Triton 3.6.0 landed (`2026-01-21`). The first two are no longer correct on 3.6+; see the \"Triton 3.6+ Blackwell path\" subsection above. CPU launch overhead and CUDA-graph workarounds remain workl", "sha256": "5f83739e9fdc674fb84155ee803c8b0bb485eb56d276477c4aa1ff9beb20f163"}, {"id": "u047", "kind": "prose", "locator": "body:L132-L132", "preview": "The following Triton files ship **verbatim** under `artifacts/prs/` (pinned at each PR's merge SHA). Each PR is in the `triton-in-policy` capture lane defined by `data/inclusion-policy.yaml` \u2014 i.e., SM100-integration, memory-bound, or backe", "sha256": "711382fc92da2e66d7e988c88abebd315f3e2e094f93a1d51666e888b427e914"}, {"id": "u048", "kind": "table-row", "locator": "body:L136-L136", "preview": "| File | Purpose | PR | | [`artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py`](../../artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py) | **Post-refresh AC-1.1 prima", "sha256": "f958e8661eb52c00c9ebefef91e0bb48d5ea0e98fc4a489441739b3af7775b48"}, {"id": "u049", "kind": "table-row", "locator": "body:L137-L137", "preview": "| File | Purpose | PR | | [`artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/backends/mla/triton_mla.py`](../../artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/backends/mla/triton_mla.py) | MLA backend wrapping the Triton dec", "sha256": "f34487db257cf6a71387b7ebee7e442cb42fef266c826613d81fdabea5174226"}, {"id": "u050", "kind": "table-row", "locator": "body:L138-L138", "preview": "| File | Purpose | PR | | [`artifacts/prs/flashinfer/PR-1025/key-files/flashinfer/triton/format_conversion.py`](../../artifacts/prs/flashinfer/PR-1025/key-files/flashinfer/triton/format_conversion.py) | FP8 / FP16 format conversion Triton k", "sha256": "65094c66c06ea23d1ad706f5775e334c0a3e2f5f026492617dd1dec185dd7361"}, {"id": "u051", "kind": "table-row", "locator": "body:L139-L139", "preview": "| File | Purpose | PR | | [`artifacts/prs/sglang/PR-20910/key-files/python/sglang/jit_kernel/norm.py`](../../artifacts/prs/sglang/PR-20910/key-files/python/sglang/jit_kernel/norm.py) | Normalization kernels (memory-bound SM100 Triton) | sgl", "sha256": "531e88057dd9e75ceb7fab84ea80b61e967cdd33cbbd798e3c2fdce3999cd9a6"}, {"id": "u052", "kind": "table-row", "locator": "body:L140-L140", "preview": "| File | Purpose | PR | | [`artifacts/prs/sglang/PR-21019/key-files/python/sglang/jit_kernel/triton/gdn_fused_proj.py`](../../artifacts/prs/sglang/PR-21019/key-files/python/sglang/jit_kernel/triton/gdn_fused_proj.py) | GatedDeltaNet fused p", "sha256": "fa5b081e5312d1ff06f63d521006d9e570ebe131b63daa9b73aaca5e59ae7dae"}, {"id": "u053", "kind": "table-row", "locator": "body:L141-L141", "preview": "| File | Purpose | PR | | [`artifacts/prs/sglang/PR-22079/key-files/python/sglang/srt/layers/attention/triton_ops/extend_attention.py`](../../artifacts/prs/sglang/PR-22079/key-files/python/sglang/srt/layers/attention/triton_ops/extend_atten", "sha256": "d48a57dd7fe3e14ac2c2d5e83b3401e31f4546da529c2f045d1c009dc32730c0"}, {"id": "u054", "kind": "prose", "locator": "body:L143-L143", "preview": "The current AC-1.1 **post-refresh primary upstream-code anchor** is `pr-vllm-34597` (above), with the actual Triton decode-attention kernel shipped verbatim. Supplementary post-refresh anchor: `pr-vllm-29339` ([`sources/prs/vllm/PR-29339.md", "sha256": "a2ebf71a94d51403b84d351f951d6feb710d41d7e1ba4feb0f435e91c2bbb5e7"}, {"id": "u055", "kind": "prose", "locator": "body:L145-L145", "preview": "The full 42-PR universe is enumerated in `data/triton-universe.yaml`. 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A single m64xn256xk16 BF16 wgmma requires 128 FP32 registers per thread in the warpgroup for the accumulator alone. This extreme register pressure limits tile sizes, reduce", "sha256": "94bc28b16a274d313182fb53a320fc5994a57220e032fdd1911de1ef309b1690"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "On Blackwell (SM100), `tcgen05.mma` stores accumulators in **Tensor Memory (TMEM)** -- a dedicated 256KB per-SM memory. This eliminates accumulator register pressure entirely, freeing registers for data movement, epilogue computation, and e", "sha256": "5ad348aa8df91b7cd3281e6e25ae912742f2819f1f529563a10083814d5cbf92"}, {"id": "u003", "kind": "prose", "locator": "body:L13-L13", "preview": "Each SM90 SM has **65,536 registers** (256KB). A typical GEMM warpgroup needs:", "sha256": "abb30068a5730114e34f09401d793f127fd8e4f12aa358969cbb0e349154c161"}, {"id": "u004", "kind": "code", "locator": "body:L15-L32", "preview": "``` Hopper wgmma m64xn256xk16 BF16 register budget (per thread): Accumulator: 128 FP32 registers (m64 x n256 / 128 threads) A operand: 16 registers (via ldmatrix) B descriptor: 2 registers Loop variables: 8 registers SMEM pointers: 4 regist", "sha256": "0836547cf0e7351f3c32c566064f11e33e14393648d79b325ff5f3a10c80c7ce"}, {"id": "u005", "kind": "prose", "locator": "body:L34-L34", "preview": "If the tile is larger (e.g., m64xn256xk32 with double-buffered accumulators), register pressure becomes even worse:", "sha256": "e00332eabba32f47851f0640e1d12efb90b7d06ad09bc2732eacca4ab998d502"}, {"id": "u006", "kind": "code", "locator": "body:L36-L43", "preview": "``` Double-buffered accumulator: 256 registers per thread Total per thread: ~300 registers Per warpgroup: 38,400 registers Per SM: max 1 warpgroup -> 1 CTA per SM Occupancy: 1 CTA per SM (severe underutilization) ```", "sha256": "bd6c4d4ffd661a52985fe7b9d29cbb8e96217b71f4cd44bda52a52bfb31ce646"}, {"id": "u007", "kind": "prose", "locator": "body:L47-L47", "preview": "When register pressure exceeds the budget, the compiler spills registers to local memory (L1 cache backed by GMEM). This is catastrophic for performance:", "sha256": "e008e70c3ea4465a254f963e9056d6aa7976b04e34c1ecc5a37983eb826965cf"}, {"id": "u008", "kind": "code", "locator": "body:L49-L56", "preview": "``` Register access: ~4 cycles L1 local access: ~30 cycles L2 spill access: ~200 cycles A single spilled accumulator register accessed every MMA iteration can cost 200 cycles * K_tiles additional latency. ```", "sha256": "8af22d45dd1493fe8d24c7b386979bf92eaba2886ae603a9083fee6820a47289"}, {"id": "u009", "kind": "code", "locator": "body:L62-L80", "preview": "``` Blackwell tcgen05 m128xn256xk16 BF16 register budget (per thread): Accumulator: 0 registers (stored in TMEM!) SMEM descriptors: 4 registers Loop variables: 8 registers TMA state: 6 registers TMEM address: 1 register Misc (indexing): 10 ", "sha256": "cf1eabfac0065dea0987082bb280003e431757240919776e543ceadfb9c9f7b9"}, {"id": "u010", "kind": "prose", "locator": "body:L82-L82", "preview": "The key insight: **registers are no longer the bottleneck**. TMEM capacity becomes the binding constraint for occupancy, and the freed registers enable complex epilogues without spilling.", "sha256": "8be6b681cf0019e4088d376a6d3c843ce9391aec4e581c21ddd6ed6544012c5c"}, {"id": "u011", "kind": "code", "locator": "body:L88-L128", "preview": "```cuda // HOPPER: Accumulator lives and dies in registers __global__ void hopper_kernel(/* ... */) { // 1. Declare accumulator in registers float acc[4][32]; // 128 registers per thread! // 2. Zero-initialize #pragma unroll for (int i = 0;", "sha256": "a61c527502ba632a78a4fd949f6bca6b9f73a2b0e12155780b40069c651f0245"}, {"id": "u012", "kind": "code", "locator": "body:L132-L210", "preview": "```cuda // BLACKWELL: Accumulator lives in TMEM __global__ void blackwell_kernel(/* ... */) { // 1. Allocate TMEM (explicit, must be done once) __shared__ uint32_t s_tmem_acc; if (threadIdx.x == 0) { uint32_t smem_addr = static_cast barely fits // m128xn256 would need 256 acc registers/thread -> spills guaranteed // Blackwell: tile size limited by TMEM columns (512) and SMEM, not", "sha256": "d481c73c916610ac7122f12b1041c47d588e156aa81b7d511645c22a99f8374a"}, {"id": "u015", "kind": "prose", "locator": "body:L231-L231", "preview": "On Hopper, complex epilogues (bias + activation + quantization + scaling) often spill because registers are already exhausted by the accumulator. On Blackwell, the epilogue has the full register file available:", "sha256": "350c2675533a141994395ee201d356d2c041d82c89116e0f49becf9bb4538424"}, {"id": "u016", "kind": "code", "locator": "body:L233-L277", "preview": "```cuda // Blackwell epilogue: full register file available __device__ void rich_epilogue(uint32_t tmem_acc, float* output, const float* bias, const float* scale, int M, int N) { // Read TMEM in chunks for (int c = 0; c < 256; c += 8) { // ", "sha256": "8be294f85f22cf8004294d27eb070f564e5be97f3c94c1f8eb5e77c83e039cbc"}, {"id": "u017", "kind": "prose", "locator": "body:L281-L281", "preview": "The most powerful pattern enabled by TMEM: overlapping the current tile's epilogue with the next tile's MMA computation. This is impossible with register accumulators because the accumulator registers are still in use.", "sha256": "d84750528e4034ab0cd2b80c3667bb140a1bee2771ea305a51f92b06de187c4f"}, {"id": "u018", "kind": "code", "locator": "body:L283-L319", "preview": "```cuda __global__ void overlapped_gemm(/* ... */) { // Two TMEM accumulator buffers uint32_t tmem_a = tmem_alloc(256); uint32_t tmem_b = tmem_alloc(256); uint32_t* tmem_cur = &tmem_a; uint32_t* tmem_nxt = &tmem_b; // Compute first tile int", "sha256": "95084d1accb758170351d93c2226e2c5cbd3a57df4a6b3b7d39e6a77dc089cf9"}, {"id": "u019", "kind": "prose", "locator": "body:L323-L323", "preview": "FlashAttention is a prime example where the register-to-TMEM migration unlocks major gains.", "sha256": "c73cd9b7a97e9dd1c77615a7d4a9245551d51a6b6e96e862ef839f36c04bc314"}, {"id": "u020", "kind": "code", "locator": "body:L327-L343", "preview": "``` FlashAttention on Hopper needs registers for: - QK^T accumulator: 64 registers (m64xn64 attention scores) - PV accumulator: 128 registers (m64xn256 output) - Softmax state: 4 registers (rowmax, rowsum) - Q fragment: 16 registers - K fra", "sha256": "7ac41e773180950eb33f74a30b2d965893228ef12d4dc445bd82c4576628b205"}, {"id": "u021", "kind": "code", "locator": "body:L347-L362", "preview": "``` FlashAttention on Blackwell: - QK^T accumulator: 0 registers (TMEM buffer 1, 64 cols) - PV accumulator: 0 registers (TMEM buffer 2, 256 cols) - Softmax state: 4 registers (rowmax, rowsum) - SMEM descriptors: 6 registers - Loop state: 10", "sha256": "15d29a84b1e95def0740b3cf71fdf32dc54907436295d3c58842e371838f7367"}, {"id": "u022", "kind": "prose", "locator": "body:L364-L364", "preview": "FlashAttention-4 exploits this headroom for software-emulated exponentials (distributing `2^x` across FMA units instead of waiting for the SFU), achieving **1605 TFLOPS on B200** at 71% utilization.", "sha256": "e592e19c4bb0adb4adc1043b5a5291dfc3fa3201a55dce34792669db5ce7236d"}, {"id": "u023", "kind": "code", "locator": "body:L370-L377", "preview": "```cuda // WRONG: Trying to use TMEM values directly in expressions float result = tmem_acc[row][col] + bias; // TMEM is not directly addressable! // CORRECT: Load from TMEM to register, then compute float val = tmem_load_f32(tmem_col); flo", "sha256": "4240bdd36422138d9cbf897ee573a125789a1ffeec13c9d9efb11295aa89ff8a"}, {"id": "u024", "kind": "code", "locator": "body:L381-L396", "preview": "```cuda // WRONG: Fine-grained TMEM access in a tight loop (high latency) for (int i = 0; i < 256; ++i) { float v = tmem_load_f32(tmem_acc + i); // 420 cycle latency each! output[i] = v; } // CORRECT: Vectorized loads to amortize latency fo", "sha256": "4286c17c4e3596989f926894c133b025507b85cf49947a0a219f14d892a7023f"}, {"id": "u025", "kind": "code", "locator": "body:L400-L406", "preview": "```cuda // Hopper: tile size was m64xn128 to avoid register spilling // Migrating to Blackwell: keep same tile = leaving performance on the table // Blackwell should use at minimum m128xn256 (1-SM) or m256xn256 (2-SM) // The freed registers", "sha256": "89e6494492b37559bcc5b0da5b1024212928402676468b9259995ec00f71b231"}, {"id": "u026", "kind": "code", "locator": "body:L410-L433", "preview": "```cuda // WRONG: Forgetting to dealloc in a persistent kernel __global__ void persistent_kernel(/* ... */) { uint32_t tmem = tmem_alloc(256); // Allocated once while (has_work()) { compute_tile(tmem); // BUG: If the kernel exits early (e.g", "sha256": "763dadf035f8d9922e0f64ea7e3c59f980c5a10c87dde8ef7553dad46a4c5153"}, {"id": "u027", "kind": "table-row", "locator": "body:L439-L439", "preview": "| Aspect | Register (Hopper) | TMEM (Blackwell) | | Accumulator declaration | `float acc[N]` in registers | `tmem_alloc(cols)` |", "sha256": "d3dedb3d3966d121536408047cab627ae29ffceaabb5b2a45735e6f12d0ef2bb"}, {"id": "u028", "kind": "table-row", "locator": "body:L440-L440", "preview": "| Aspect | Register (Hopper) | TMEM (Blackwell) | | Zero-initialization | Loop over register array | `tcgen05.st` zero pattern |", "sha256": "27af4af93c6ecc620c3b3c937e8ecd8ac5123a3cfbb0b14e9a8e37551c22b4fa"}, {"id": "u029", "kind": "table-row", "locator": "body:L441-L441", "preview": "| Aspect | Register (Hopper) | TMEM (Blackwell) | | MMA accumulation | Implicit (wgmma writes regs) | Implicit (tcgen05 writes TMEM) |", "sha256": "d26a8710ccc5958ea4d2231bd3cce6cca88cb787613eb0c6c0c4ed4fb0dfdbb5"}, {"id": "u030", "kind": "table-row", "locator": "body:L442-L442", "preview": "| Aspect | Register (Hopper) | TMEM (Blackwell) | | Reading results | Direct register access | `tcgen05.ld` to register |", "sha256": "e1210631e69cd6ed454c92ca37d7024fa2be5c2f8ccadd99a5218c68128e97dc"}, {"id": "u031", "kind": "table-row", "locator": "body:L443-L443", "preview": "| Aspect | Register (Hopper) | TMEM (Blackwell) | | Cleanup | Implicit (CTA exit) | Explicit `tcgen05.dealloc` |", "sha256": "b13398f17871ab8c8763378af8a6c2ae9b5ebf2f9942484c99667bf84cb71f80"}, {"id": "u032", "kind": "table-row", "locator": "body:L444-L444", "preview": "| Aspect | Register (Hopper) | TMEM (Blackwell) | | Register pressure | ~128-256 regs for accumulator | ~0 regs for accumulator |", "sha256": "941c758fac43a685ea2d7596da3965c7d4bff5792fd5a52687d006f914c111e6"}, {"id": "u033", "kind": "table-row", "locator": "body:L445-L445", "preview": "| Aspect | Register (Hopper) | TMEM (Blackwell) | | Epilogue headroom | Minimal (spill risk) | Ample (full register file) |", "sha256": "c57a3e83cf3e739a20fc3375871e2f824bca9cc247643c005b7ee12c634c14ea"}, {"id": "u034", "kind": "table-row", "locator": "body:L446-L446", "preview": "| Aspect | Register (Hopper) | TMEM (Blackwell) | | Double-buffering | Doubles register pressure (2x acc) | Uses 2 TMEM regions (no reg impact) |", "sha256": "607deb95f607fb5de40cd2a3dfef1daabcc2e5f6c7d17e509591e8fb5da0fe15"}, {"id": "u035", "kind": "table-row", "locator": "body:L447-L447", "preview": "| Aspect | Register (Hopper) | TMEM (Blackwell) | | Max practical tile | m64xn256 (limited by registers) | m128xn256 or m256xn256 (limited by TMEM cols) |", "sha256": "4136812cfdccdee9964191f6238491b06bd295dcb150e75b3d18d4d3bdbf446e"}], "confidence_claimed": "source-reported", "headings": ["Overview", "The Register Pressure Problem on Hopper", "Register Budget Analysis", "Register Spilling on Hopper", "Blackwell TMEM Solution", "TMEM Budget Analysis", "Migration: Accumulator Lifecycle", "Hopper: Register-Based Lifecycle", "Blackwell: TMEM-Based Lifecycle", "Impact on Kernel Design", "Tile Size Freedom", "Epilogue Complexity", "Overlapped Epilogue and MMA", "FlashAttention Case Study", "Hopper FlashAttention Register Pressure", "Blackwell FlashAttention with TMEM", "Common Mistakes During Migration", "Mistake 1: Treating TMEM Like Registers", "Mistake 2: Forgetting TMEM Latency", "Mistake 3: Not Re-tuning Tile Sizes", "Mistake 4: TMEM Leak in Persistent Kernels", "Summary: What Changes, What Stays"], "id": "migration-register-to-tmem", "path": "wiki/migration/register-to-tmem.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/prs/vllm/PR-22738.md", "revision": "b1361c72", "url": "https://github.com/vllm-project/vllm/pull/22738"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "pr-vllm-22738"], "title": "Register Accumulators to TMEM", "type": "migration", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "0c2cada28831223c7f5b4dc10e20b9007129747d3659ed5f7e0aefbe340281d9", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "This guide covers the migration from Hopper's `wgmma.mma_async` (SM90) to Blackwell's `tcgen05.mma` (SM100). This is the single most impactful change when porting kernels from H100/H200 to B200. The two instructions differ in:", "sha256": "e3e242ad8530bd6bafc064bcec677b74cffaeb35b4f64bc1fd754d5207bd70e6"}, {"id": "u002", "kind": "list-item", "locator": "body:L7-L7", "preview": "- **Issuing model**: warpgroup (128 threads) vs single thread", "sha256": "069718d53c82b623c5e10e3c61efa1cfba1fc85ec00f851ce0bd2a5c5e5f9bda"}, {"id": "u003", "kind": "list-item", "locator": "body:L8-L8", "preview": "- **Accumulator storage**: registers vs TMEM", "sha256": "926d5457957e54352f0eec613608c84cc4c5d2b20a478946fc015091a8b2f331"}, {"id": "u004", "kind": "list-item", "locator": "body:L9-L9", "preview": "- **Operand loading**: ldmatrix + registers vs direct SMEM access", "sha256": "51affba4e422e3a7e48fb31940d581f3c2081e6f32050df13744a2e43e63e340"}, {"id": "u005", "kind": "list-item", "locator": "body:L10-L10", "preview": "- **Synchronization**: warpgroup barriers vs async fences", "sha256": "f57e261c89f01976603e55a1dcc49a5f778870a655ad5d61acf804d3fb4ac3c1"}, {"id": "u006", "kind": "list-item", "locator": "body:L11-L11", "preview": "- **Available data types**: FP8 (Hopper) vs FP4/FP6/FP8 with block scaling (Blackwell)", "sha256": "5601d239aa4461719db571fa0b7b67111e8dcfd20e6521a45ccd81516267485b"}, {"id": "u007", "kind": "code", "locator": "body:L15-L25", "preview": "``` [ ] Replace wgmma.mma_async with tcgen05.mma [ ] Move accumulators from registers to TMEM (alloc/dealloc) [ ] Remove ldmatrix operations (tcgen05 reads directly from SMEM) [ ] Change SMEM swizzle from 64B to 128B [ ] Replace warpgroup c", "sha256": "653ba85078953043730a032a53477bbb86ee80296cb3450c484bd1f91f44727b"}, {"id": "u008", "kind": "code", "locator": "body:L31-L84", "preview": "```cuda // SM90 GEMM kernel using wgmma __global__ void hopper_gemm( const half* A, const half* B, half* C, int M, int N, int K ) { extern __shared__ char smem[]; half* smem_a = reinterpret_cast(smem); half* smem_b = smem_a + TILE_M ", "sha256": "3288a5cc14b9e820c8daa234bb1bac17fa8504387859902a5d0631c53a4ac50a"}, {"id": "u009", "kind": "code", "locator": "body:L88-L155", "preview": "```cuda // SM100 GEMM kernel using tcgen05 __global__ void blackwell_gemm( const half* A, const half* B, half* C, int M, int N, int K ) { extern __shared__ char smem[]; half* smem_a = reinterpret_cast(smem); half* smem_b = smem_a + T", "sha256": "862c80edc308ce79a6143756f049df61caef25d71c1f4d807c7431e113987dd5"}, {"id": "u010", "kind": "prose", "locator": "body:L161-L161", "preview": "**Before (Hopper):** Accumulators live in registers.", "sha256": "5649d9a74080d859e2254267f09440409574e8ded6d1ef73b4ef887d46299a3e"}, {"id": "u011", "kind": "code", "locator": "body:L163-L166", "preview": "```cuda // Hopper: 128 FP32 registers for a 64x256 accumulator fragment float acc[4][32]; // Per-thread fragment of the warpgroup accumulator ```", "sha256": "4fb80b998cef798698f4471ede13251306a689b760d3d3d281148410c57f51e3"}, {"id": "u012", "kind": "prose", "locator": "body:L168-L168", "preview": "**After (Blackwell):** Accumulators live in TMEM.", "sha256": "f225e5b706eee44215db50401ea5fb88c57367ed3fb0cdbf1cc0433e00e51695"}, {"id": "u013", "kind": "code", "locator": "body:L170-L173", "preview": "```cuda // Blackwell: TMEM address replaces register array uint32_t tmem_acc = tmem_alloc(256); // 128 rows x 256 cols in TMEM ```", "sha256": "1ef83b7286b3acae2e779ba613b7801b41e882e81d789715478d0aa2f237054a"}, {"id": "u014", "kind": "prose", "locator": "body:L177-L177", "preview": "**Before (Hopper):** Load A operand from SMEM to registers.", "sha256": "1f697fb70990e78dd465b89ef9632a1f6ba12ce93de5f214282d797ceb43bfe1"}, {"id": "u015", "kind": "code", "locator": "body:L179-L189", "preview": "```cuda // Hopper: ldmatrix loads 8x8 matrix fragments into registers uint32_t a_frag[4]; asm volatile( \"ldmatrix.sync.aligned.m8n8.x4.shared.b16 \" \"{%0,%1,%2,%3}, [%4];\" : \"=r\"(a_frag[0]), \"=r\"(a_frag[1]), \"=r\"(a_frag[2]), \"=r\"(a_frag[3]) ", "sha256": "56b45537bace00ebc3ef75ebcdfc3ce9addd458f471ca4de8f6e0a57070e5f52"}, {"id": "u016", "kind": "prose", "locator": "body:L191-L191", "preview": "**After (Blackwell):** No equivalent needed. tcgen05 reads A directly from SMEM via descriptor.", "sha256": "9cdac1fbfecbb43ebe2742e2c6865fb2f05f0e97d2e6de97ad2b7192ed69d05a"}, {"id": "u017", "kind": "code", "locator": "body:L193-L197", "preview": "```cuda // Blackwell: just construct the SMEM descriptor uint64_t desc_a = make_smem_desc_128b(smem_a_ptr); // Pass desc_a directly to tcgen05.mma -- no register staging ```", "sha256": "e1d1d30efba8fdc3375e6632e2796d546158651b7b1a47afad420d836fba5bcf"}, {"id": "u018", "kind": "prose", "locator": "body:L201-L201", "preview": "**Before (Hopper):** 64-byte or 128-byte swizzle both work for wgmma.", "sha256": "fca92c2012f2548b5ee73757f411cc28972cc3b8492382eedd5f103a99fd7797"}, {"id": "u019", "kind": "code", "locator": "body:L203-L207", "preview": "```cuda // Hopper TMA descriptor: 64B swizzle is common CUtensorMap desc = create_tma_desc(ptr, M, N, tile_m, tile_n, CU_TENSOR_MAP_SWIZZLE_64B); ```", "sha256": "12b76455f0d53a44e82c331f166969538300d03b7f6057805035915ca92b24c2"}, {"id": "u020", "kind": "prose", "locator": "body:L209-L209", "preview": "**After (Blackwell):** 128-byte swizzle is mandatory.", "sha256": "229c087640cb29c29256903515cb9d8d3cd9247cddc9c7cf12d332ff4f2be34b"}, {"id": "u021", "kind": "code", "locator": "body:L211-L215", "preview": "```cuda // Blackwell TMA descriptor: MUST use 128B swizzle CUtensorMap desc = create_tma_desc(ptr, M, N, tile_m, tile_n, CU_TENSOR_MAP_SWIZZLE_128B); ```", "sha256": "292f7acaabb39ec9e6acc4624c767b6888c3195fe27779de9f33aa3dccc20a97"}, {"id": "u022", "kind": "prose", "locator": "body:L219-L219", "preview": "**Before (Hopper):**", "sha256": "4ddd181f824434b74af8a064e60f3f7f3bbfca6050689028251cb278634bec37"}, {"id": "u023", "kind": "code", "locator": "body:L221-L230", "preview": "```cuda // Hopper: all 128 threads in warpgroup issue wgmma asm volatile( \"wgmma.mma_async.sync.aligned.m64n256k16.f32.bf16.bf16 \" \"{%0,%1,...}, {%N,...}, desc_b, ...;\" : \"+f\"(acc[0]), \"+f\"(acc[1]), ... : \"r\"(a_frag[0]), ... ); asm volatile", "sha256": "f97d16ee60f9dc5d3a760fc7dfed30dc1caa93a5d3eed6760b5a0ac06900697c"}, {"id": "u024", "kind": "prose", "locator": "body:L232-L232", "preview": "**After (Blackwell):**", "sha256": "2a7df142d777617140c33c51cd502cf20555267d6709293143e290b5b0c91e43"}, {"id": "u025", "kind": "code", "locator": "body:L234-L245", "preview": "```cuda // Blackwell: single thread issues tcgen05 if (threadIdx.x == 0) { asm volatile( \"tcgen05.mma.cta_group::1.kind::f16 \" \"[%0], %1, %2, %3, 1;\" : : \"r\"(tmem_acc), \"l\"(desc_a), \"l\"(desc_b), \"r\"(0) ); } // No commit needed -- fully asyn", "sha256": "c178942b5044a0b480642a53020bab6b3ed43025ff861856a83c72761e920f62"}, {"id": "u026", "kind": "prose", "locator": "body:L249-L249", "preview": "**Before (Hopper):**", "sha256": "4ddd181f824434b74af8a064e60f3f7f3bbfca6050689028251cb278634bec37"}, {"id": "u027", "kind": "code", "locator": "body:L251-L255", "preview": "```cuda // Hopper: wait for outstanding wgmma groups asm volatile(\"wgmma.wait_group.sync.aligned 0;\"); // Accumulators now ready in registers ```", "sha256": "993484703e3e86fd38fb60ac89bf1b65590c1ffd0dd60dc5fb9adf0e991b2e1c"}, {"id": "u028", "kind": "prose", "locator": "body:L257-L257", "preview": "**After (Blackwell):**", "sha256": "2a7df142d777617140c33c51cd502cf20555267d6709293143e290b5b0c91e43"}, {"id": "u029", "kind": "code", "locator": "body:L259-L264", "preview": "```cuda // Blackwell: fence before reading TMEM asm volatile(\"tcgen05.fence::before_thread_sync;\"); __syncthreads(); // TMEM accumulators now ready for reading ```", "sha256": "643c4c9c508ecd528c3ba2a0da7b172c669513c3855b368b2a39643940368987"}, {"id": "u030", "kind": "prose", "locator": "body:L268-L268", "preview": "**Before (Hopper):**", "sha256": "4ddd181f824434b74af8a064e60f3f7f3bbfca6050689028251cb278634bec37"}, {"id": "u031", "kind": "code", "locator": "body:L270-L279", "preview": "```cuda // Hopper: accumulators in registers, directly usable float result = acc[frag_m][frag_n]; // Apply bias result += bias[col]; // Apply activation result = relu(result); // Store to GMEM C[row * N + col] = (half)result; ```", "sha256": "6f9b7dcb620b7cff69ee98686a65251d68dded33d3d3d5fa876304f765f42da4"}, {"id": "u032", "kind": "prose", "locator": "body:L281-L281", "preview": "**After (Blackwell):**", "sha256": "2a7df142d777617140c33c51cd502cf20555267d6709293143e290b5b0c91e43"}, {"id": "u033", "kind": "code", "locator": "body:L283-L292", "preview": "```cuda // Blackwell: must read from TMEM first float result = tmem_load_f32(tmem_acc + col_offset); // Apply bias result += bias[col]; // Apply activation result = relu(result); // Store to GMEM C[row * N + col] = (half)result; ```", "sha256": "6ae2d29d9838b4eef2a63fb9d732a67b1604f3ed222ab56035861c8d4de1913b"}, {"id": "u034", "kind": "code", "locator": "body:L298-L305", "preview": "``` Warp 0-3: Warpgroup 0 -- MMA producer (all 128 threads issue wgmma) Warp 4-7: Warpgroup 1 -- MMA producer (backup/double-buffer) Warp 8-11: Data movement (TMA loads, SMEM management) Warp 12: Tile scheduler Total: 13+ warps, 416+ thread", "sha256": "c0f994a3dee4bb7680e3b6ea94b40923704209feaf7c444db3008faf0fcdb5e4"}, {"id": "u035", "kind": "code", "locator": "body:L309-L316", "preview": "``` Warp 0: MMA producer (single thread issues tcgen05) Warp 1-2: TMA data movement (load A, load B, manage barriers) Warp 3: Epilogue (read TMEM, apply post-ops, store to GMEM) Warp 4: Tile scheduler / CLC management Total: 5 warps, 160 th", "sha256": "0e2936e83971ca051e8b1d67b232bce183cf4eb79a350032cf80ce74801a1061"}, {"id": "u036", "kind": "prose", "locator": "body:L318-L318", "preview": "With tcgen05, far fewer warps are dedicated to MMA because only one thread is needed to issue the instruction. The freed warps can be repurposed for:", "sha256": "96b41eb8a9041d0e1ad345ba3f086eba22c8e8484934fc39bc727dc459d62994"}, {"id": "u037", "kind": "list-item", "locator": "body:L319-L319", "preview": "- More aggressive data prefetching", "sha256": "5bcd30b3457c22f7976929d684cb6a37205df7a46ebcea2c8c87d57d059f071f"}, {"id": "u038", "kind": "list-item", "locator": "body:L320-L320", "preview": "- Overlapped epilogue (read TMEM while next tile's MMA is computing)", "sha256": "8d6b594c33f2a5386d91c7e5c576933640024ec756b3923c3cc92a23dda13e67"}, {"id": "u039", "kind": "list-item", "locator": "body:L321-L321", "preview": "- Softmax or other reductions (FlashAttention-style)", "sha256": "fad70bd397ac53bc68809bee25a160dfa7d95eb902ea5506fcf9ea98c2fb46b1"}, {"id": "u040", "kind": "table-row", "locator": "body:L327-L327", "preview": "| Hopper | Blackwell (1-SM) | Blackwell (2-SM) | | m64 x n256 x k16 | m128 x n256 x k16 | m256 x n256 x k16 |", "sha256": "19180cb2b51bb63c0cc758c204d24a60646f4195a1bf1bd1d48e8662d4a784fe"}, {"id": "u041", "kind": "table-row", "locator": "body:L328-L328", "preview": "| Hopper | Blackwell (1-SM) | Blackwell (2-SM) | | m64 x n128 x k16 | m128 x n128 x k16 | m256 x n128 x k16 |", "sha256": "037021919a58f4625f5512ddabfe101bd8a3637fd109d0936b6467b664aec4a8"}, {"id": "u042", "kind": "prose", "locator": "body:L330-L330", "preview": "Blackwell's base MMA tile is 2x larger in M (128 vs 64). When migrating:", "sha256": "7dd9c89a913ca7a27ec23a6ecfc5616e89c940d1d94a4fbd4613123219796b8f"}, {"id": "u043", "kind": "list-item", "locator": "body:L331-L331", "preview": "- CTA tile size of 128x256 maps naturally to a single tcgen05 MMA", "sha256": "c86455a9c8c6cdb905f1b567bd51bc98250dcdb63a4c577a5977f72845399b71"}, {"id": "u044", "kind": "list-item", "locator": "body:L332-L332", "preview": "- CTA tile size of 64x256 on Hopper should be doubled to 128x256", "sha256": "5e766c9f0f14f49b359adb752bf222e4dbce5dcbcc196063826511c24d3f783c"}, {"id": "u045", "kind": "list-item", "locator": "body:L333-L333", "preview": "- For 2-SM mode, consider 256x256 tiles", "sha256": "c2b6a904583fa69c266fc75a303c539420ff197a11b31ee414ff26bd6cb862b9"}, {"id": "u046", "kind": "list-item", "locator": "body:L337-L337", "preview": "1. **Forgetting 128B swizzle**: The most common silent-failure bug. wgmma works with 64B swizzle; tcgen05 does not. Results will be numerically wrong but the kernel won't crash.", "sha256": "c0ac2b2981c54f4cabc1dc8e1707abadc2bc552de03aea72e737f3d6e448aa55"}, {"id": "u047", "kind": "list-item", "locator": "body:L339-L339", "preview": "2. **Not deallocating TMEM**: On Hopper, register accumulators are freed implicitly when the CTA exits. On Blackwell, TMEM must be explicitly deallocated in persistent kernels.", "sha256": "a568178da91fbbb2dfa8ad92fe09b2ef3de508c872de7eb5888177eedd1215b9"}, {"id": "u048", "kind": "list-item", "locator": "body:L341-L341", "preview": "3. **Synchronization model mismatch**: Replacing `wgmma.wait_group` with `__syncthreads()` alone is insufficient. The `tcgen05.fence::before_thread_sync` must precede the syncthreads.", "sha256": "3e84f8a6f8b39f0130cd6a848b938f4cac3ab442361ab79bde3c460e5a57941e"}, {"id": "u049", "kind": "list-item", "locator": "body:L343-L343", "preview": "4. **Over-allocating threads**: On Hopper, you need 128 threads per warpgroup for MMA. Blindly keeping the same thread count on Blackwell wastes resources since only 1 thread issues tcgen05.", "sha256": "7e7dda62c6c62d22ef734d67601bd2db01f658b6d3fa93163d8b9700a593d9ae"}, {"id": "u050", "kind": "list-item", "locator": "body:L345-L345", "preview": "5. **Register pressure assumptions**: Code tuned for Hopper's high register pressure (e.g., reduced tile sizes, manual spilling) may be overly conservative on Blackwell. Re-tune tile sizes to take advantage of freed registers.", "sha256": "827a5dcfa8697efffb61200fc3028ab340a9469f09956a61aedd57c78ee28fca"}, {"id": "u051", "kind": "prose", "locator": "body:L349-L349", "preview": "If using CUTLASS, the migration is largely handled by changing the arch tag and kernel schedule:", "sha256": "60cb963d24a0cc1abfd438742f9fc0a941b9732e70eae17e1510001bc341dbaf"}, {"id": "u052", "kind": "code", "locator": "body:L351-L367", "preview": "```cpp // Hopper CUTLASS GEMM using GemmHopper = cutlass::gemm::device::GemmUniversal< /* ... */ cutlass::arch::Sm90, /* ... */ cutlass::gemm::collective::KernelScheduleSm90CpAsyncWarpSpecialized >; // Blackwell CUTLASS GEMM -- change arch ", "sha256": "c7252763e4fba15199fc8601dee41acec6cd8cabc2c7925b3cc849f79936125e"}, {"id": "u053", "kind": "prose", "locator": "body:L369-L369", "preview": "CUTLASS handles the internal differences (TMEM allocation, descriptor construction, fence insertion, 128B swizzle) automatically through its `MMA_Atom` and `MMA_Traits` abstractions for SM100.", "sha256": "6d4ddbfa46bd23167c929dc9f9e7d23b1199a1b374b6a4f55e54d82351265e0b"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Migration Checklist", "Side-by-Side Comparison", "Hopper Kernel Structure (SM90)", "Blackwell Kernel Structure (SM100)", "Step-by-Step Migration", "Step 1: Replace Accumulator Storage", "Step 2: Remove ldmatrix", "Step 3: Change SMEM Swizzle from 64B to 128B", "Step 4: Replace wgmma Issue with tcgen05 Issue", "Step 5: Replace wgmma.wait_group with tcgen05 Fence", "Step 6: Update Epilogue", "Warp Specialization Changes", "Hopper Warp Specialization (Typical)", "Blackwell Warp Specialization (Typical)", "Tile Size Migration", "Common Migration Pitfalls", "CUTLASS Migration"], "id": "migration-wgmma-to-tcgen05", "path": "wiki/migration/wgmma-to-tcgen05.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/blogs/colfax-cutlass-blackwell.md", "url": "https://research.colfax-intl.com/cutlass-tutorial-writing-gemm-kernels-using-tmem-for-nvidia-blackwell-gpus/"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "blog-colfax-cutlass"], "title": "Migrating from wgmma to tcgen05", "type": "migration", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "1250f2c8d05fdd1ec4dcb30133b71caf29617b7fe0c0131fcafbe9ca9a4fe320", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Tensor core utilization below 70%. Memory bandwidth is not saturated. Kernel is compute-bound but not reaching peak FLOPS.", "sha256": "1f2087903c90937aea23fad886c9bd9dad2042ba1b24dc335790e3b4e8440c18"}, {"id": "u002", "kind": "list-item", "locator": "body:L7-L7", "preview": "1. **Pipeline bubbles**: MMA stalled waiting for data from TMA", "sha256": "8d8f8d98b5d284392eb71a872e7ff7876964a8922e8f99bbfc723963dccaa759"}, {"id": "u003", "kind": "list-item", "locator": "body:L8-L8", "preview": "2. **Non-matmul overhead**: Softmax, activation functions, reductions consuming cycles", "sha256": "b59e45b681033f13916e2a83ec38bb18ffadff01f2b41958e10b53e730b62286"}, {"id": "u004", "kind": "list-item", "locator": "body:L9-L9", "preview": "3. **Single-SM MMA tiles too small**: Not fully utilizing available compute", "sha256": "5fe2753baa61aa1db088650b5b7317f415cc6545f02b83a04da987b094883742"}, {"id": "u005", "kind": "list-item", "locator": "body:L10-L10", "preview": "4. **Epilogue blocking mainloop**: TMEM reads blocking next MMA", "sha256": "5d06c039c6e044e324150c739ce382c90677b38d261b0617f6fb83b760dc1d26"}, {"id": "u006", "kind": "table-row", "locator": "body:L16-L16", "preview": "| Technique | Effect | | [2-SM cooperative](../hardware/2sm-cooperative.md) | Double effective MMA tile (m256\u00d7n256), 2\u00d7 compute per cycle |", "sha256": "0a6da9a08dac60aaf7062e28ab14512e4bdf1cd73685725a408b3e9074eee114"}, {"id": "u007", "kind": "table-row", "locator": "body:L17-L17", "preview": "| Technique | Effect | | [Pipeline stages](../techniques/pipeline-stages.md) | Overlap TMA load with MMA compute |", "sha256": "2388aa7c0bd73280dfc9be73d8895f4220c93eea99557724b369bb78aa937302"}, {"id": "u008", "kind": "table-row", "locator": "body:L18-L18", "preview": "| Technique | Effect | | [Warp specialization](../techniques/warp-specialization.md) | Dedicated warps for TMA/MMA/epilogue, no stalls |", "sha256": "b3dd06a59b15e37406b2c7bf07e43bffbc903c886e3f311170e4aba3d69df642"}, {"id": "u009", "kind": "table-row", "locator": "body:L19-L19", "preview": "| Technique | Effect | | [Epilogue fusion](../techniques/epilogue-fusion.md) | Overlap epilogue with next tile's MMA |", "sha256": "59fef48221c33e68b699c20bbd960de02fec62482f07ef3f5dc228038c5071a0"}, {"id": "u010", "kind": "table-row", "locator": "body:L20-L20", "preview": "| Technique | Effect | | [Software exponential](../techniques/software-exp.md) | Distribute non-matmul ops across FMA units (FA4) |", "sha256": "2e15eb9eacf4f6a259e0974f9fb374b9f26ef373d8ffd2015441a5639849b0bc"}, {"id": "u011", "kind": "code", "locator": "body:L24-L31", "preview": "``` // Problem: Blackwell doubles tensor core throughput but SFU count unchanged // SFU bottleneck: exp() for softmax // // Solution: Software 2^x via Cody-Waite + Horner polynomial // Distributes across FMA units, multiplying exponential t", "sha256": "a61d1e90989365d653a026b634ebe7cec74dae4236636c34adcbc4552d74e68d"}, {"id": "u012", "kind": "list-item", "locator": "body:L34-L34", "preview": "- 2-SM cooperative requires cluster configuration and identical SMEM layouts", "sha256": "722ad882e22729c3c52ced4b0a7474952f575258c7cf5c04d4f652c79d42cf11"}, {"id": "u013", "kind": "list-item", "locator": "body:L35-L35", "preview": "- Pipeline depth tuning is workload-dependent (3-5 stages typical)", "sha256": "b64cb0709c42ee988816b64d1e8cb332dd7ef083fd04a3fb33edfd8d19477d3e"}, {"id": "u014", "kind": "list-item", "locator": "body:L36-L36", "preview": "- Software-emulated transcendentals trade accuracy for throughput", "sha256": "01099e8879a24004b8a230c4c110825633f6b2c7db203ce54be25ba698ea6482"}], "confidence_claimed": null, "headings": ["Symptom", "Likely Causes", "Candidate Techniques", "Example: FlashAttention-4", "Caveats"], "id": "pattern-compute-bound", "path": "wiki/patterns/compute-bound.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/blogs/flash-attention-4.md", "url": "https://tridao.me/blog/2026/flash4/"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "blog-flash-attention-4"], "title": "Not Reaching Peak FLOPS", "type": "pattern", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "ffe8f3f021f4946f96b95bfc41d6745d38c52fd887cb7171751f8f4e9934e91b", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "SM utilization below 60% despite sufficient occupancy. Nsight Compute shows idle SMs during portions of kernel execution.", "sha256": "5da93aae9fc0084ad5cf53f525a2493b47fbca4ac3986626652e90a0e231340d"}, {"id": "u002", "kind": "list-item", "locator": "body:L7-L7", "preview": "1. **Tail effect**: Last wave of tiles leaves most SMs idle (see [tail-effect](tail-effect.md))", "sha256": "bfb85873942f4214c8682b3b6512f034b15e5245ef6bbda1422c66d1693872bf"}, {"id": "u003", "kind": "list-item", "locator": "body:L8-L8", "preview": "2. **Load imbalance**: Some tiles take longer than others (variable computation per tile)", "sha256": "9aa73dca1ac150ce3bca32374afb0a63d324c1e49fc39188a2eb668c7d3da68e"}, {"id": "u004", "kind": "list-item", "locator": "body:L9-L9", "preview": "3. **Static scheduling**: Fixed tile-to-SM assignment doesn't adapt to runtime conditions", "sha256": "4697d65e3b2165c234214aa9f4ecfc8cc2d13ae7593da020ec00fc21fe4f5a08"}, {"id": "u005", "kind": "list-item", "locator": "body:L10-L10", "preview": "4. **Grid too small**: Fewer threadblocks than SMs", "sha256": "c3216052f73490a7acb8b4e99e3585d659df7c9013e9775b079e4610da44874a"}, {"id": "u006", "kind": "table-row", "locator": "body:L16-L16", "preview": "| Technique | Applicability | Effect | | [CLC](../hardware/clc.md) | SM100 only | Dynamic tile assignment, eliminates load imbalance |", "sha256": "0a3e3d868a2182503591b2b4a9e2aada8bfe7c0f20e5da17168dac14435f8de7"}, {"id": "u007", "kind": "table-row", "locator": "body:L17-L17", "preview": "| Technique | Applicability | Effect | | [Persistent kernels](../techniques/persistent-kernels.md) | SM90+ | Eliminates tail effect, one-time launch overhead |", "sha256": "319e40604927d4afb11eb2787237c3632bfb85dbaa4fcd6f60ee93adedd3b100"}, {"id": "u008", "kind": "table-row", "locator": "body:L18-L18", "preview": "| Technique | Applicability | Effect | | [Tile scheduling](../techniques/tile-scheduling.md) | SM90+ | Better L2 locality, reduce load variance |", "sha256": "1b99d25e571454ca800ab956d044e6f3d5347f68d9ee4adb17948241afe2a264"}, {"id": "u009", "kind": "code", "locator": "body:L22-L26", "preview": "``` // tcgen05 tutorial progression: // Without persistent/CLC: 86% of cuBLAS (some SMs idle at wave boundaries) // With persistent + CLC: 98% of cuBLAS (all SMs stay busy) ```", "sha256": "fce47d285cec29c94d16ea9765bdda1f464614a35272f1aa18734006042a2e7f"}, {"id": "u010", "kind": "list-item", "locator": "body:L29-L29", "preview": "- CLC only available on SM100 datacenter GPUs (not SM120 consumer)", "sha256": "75d8555a04ed8e4b2c78530b00dd21f22e15736b43db5381874c644498e7c52c"}, {"id": "u011", "kind": "list-item", "locator": "body:L30-L30", "preview": "- Persistent kernels complicate debugging and profiling", "sha256": "694e7865c9620dbacb087ecce133f9d3de68af1d6f971c6398927d4947f9066a"}, {"id": "u012", "kind": "list-item", "locator": "body:L31-L31", "preview": "- For non-persistent kernels, ensure grid size >> SM count", "sha256": "9e87656f10cad9c1ff43dc0b5bd3517c0b5035f87cd8cb4e7da8b657e4cc3b79"}], "confidence_claimed": null, "headings": ["Symptom", "Likely Causes", "Candidate Techniques", "Examples", "Caveats"], "id": "pattern-low-sm-utilization", "path": "wiki/patterns/low-sm-utilization.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/prs/cutlass/PR-2161.md", "revision": "06e560d9", "url": "https://github.com/NVIDIA/cutlass/pull/2161"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "pr-cutlass-2161"], "title": "Low SM Utilization", "type": "pattern", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "55576e61fe10aa796637b7056b452f0d94f5b0e727643e78a422e2b721eb30ff", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Nsight Compute shows high DRAM throughput but low tensor core utilization. Arithmetic intensity below the roofline knee point.", "sha256": "4dc42c72b1a556c74db70e040cb70a14535edb81f21fca0468237d330c4305f9"}, {"id": "u002", "kind": "list-item", "locator": "body:L7-L7", "preview": "1. **Low arithmetic intensity**: Operations like GEMV, small batch decode, or reduction kernels", "sha256": "c51b97d7a36f7b139c0424ab729c50d90469c2293723e48fbf6a4e453eba4cfd"}, {"id": "u003", "kind": "list-item", "locator": "body:L8-L8", "preview": "2. **Poor data reuse**: Each data element used only once", "sha256": "48214a8d8262de0740e3225b192a23047f3dc7fa93ebcaf09654a69ce6e1b818"}, {"id": "u004", "kind": "list-item", "locator": "body:L9-L9", "preview": "3. **Inefficient memory access**: Uncoalesced loads, L1 cache thrashing", "sha256": "3e4a2d1d5d56034c91c22a54b4ea6f6a07afe88bb2a2cb1a0b4509e97502b4dd"}, {"id": "u005", "kind": "table-row", "locator": "body:L15-L15", "preview": "| Technique | Effect | | [Vectorized loads](../techniques/vectorized-loads.md) | 128/256-bit loads maximize bandwidth utilization |", "sha256": "f6634a4a1cdf73cae19ce6b5b2b65a1f466bb337bb5a7739be87f42a489adf4e"}, {"id": "u006", "kind": "table-row", "locator": "body:L16-L16", "preview": "| Technique | Effect | | [Cache policies](../techniques/vectorized-loads.md) | L1::no_allocate for streaming, L1::evict_last for reuse |", "sha256": "71e86985a3f7dc21c00822843be4de0a7d7f8baa1913cfeea45eefd465ce3a88"}, {"id": "u007", "kind": "table-row", "locator": "body:L17-L17", "preview": "| Technique | Effect | | [Register budgeting](../techniques/vectorized-loads.md) | -maxrregcount increases occupancy |", "sha256": "e45af4504c36ed1768fe0ecf479ebd86fed44e7ee01636ed18c46d1433b798bd"}, {"id": "u008", "kind": "table-row", "locator": "body:L18-L18", "preview": "| Technique | Effect | | [TMA multicast](../hardware/tma.md) | Share loaded data across SMs in cluster |", "sha256": "0fa01c9f8e7d712e7c405684d14a05d96529f86b847d3b5460ab8058c5c05068"}, {"id": "u009", "kind": "table-row", "locator": "body:L19-L19", "preview": "| Technique | Effect | | [Swizzling](../techniques/swizzling.md) | Eliminate bank conflicts in shared memory |", "sha256": "8d464b0a54f7ed7c78641ea4c7b70ca5dfe11e9886a64623d269c8f8b22d889c"}, {"id": "u010", "kind": "code", "locator": "body:L23-L34", "preview": "```cuda // NVFP4 GEMV: memory-bound optimization // Key insight: profile FIRST to confirm memory-bound behavior // \"The single most important thing could have been running Nsight Compute\" // \u2014 Amandeep (12 Attempts at an FP4 Kernel) // Opti", "sha256": "48b1d0f3c6e9a148d01ddebc1bb397b343e2217038e2d4a7f62f20058d20d119"}, {"id": "u011", "kind": "list-item", "locator": "body:L37-L37", "preview": "- Always profile before optimizing \u2014 wrong assumption wastes effort", "sha256": "d024ba4e89fe3161a59877b3ea6ff0d87e466fa900ff41b0867984a659a3d8be"}, {"id": "u012", "kind": "list-item", "locator": "body:L38-L38", "preview": "- B200 has 8 TB/s bandwidth; speed-of-light calculation determines achievable performance", "sha256": "93d1616bf3fcec94fddbd14292d17533a2577578ed75e50f837d041501b45d68"}, {"id": "u013", "kind": "list-item", "locator": "body:L39-L39", "preview": "- ILP and compute optimizations have diminishing returns for memory-bound kernels", "sha256": "3da206d588b3730c5fbfcecc2b5e8e44a3109159f65679aeafdd904e06f30659"}], "confidence_claimed": null, "headings": ["Symptom", "Likely Causes", "Candidate Techniques", "Examples", "Caveats"], "id": "pattern-memory-bound", "path": "wiki/patterns/memory-bound.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/yue-nvfp4-hackathon.md", "url": "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"}, {"path": "sources/blogs/amandeep-nvfp4-attempts.md", "url": "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"}, {"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-yue-nvfp4", "blog-amandeep-nvfp4", "doc-nvidia-tuning-guide"], "title": "Memory Bandwidth Bound", "type": "pattern", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "dd70d3638677328e71242ec9fa14891b9ed9465328f129378f5b835f52741275", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "MoE grouped GEMM shows uneven per-expert compute time. Some SMs finish their expert quickly and sit idle while others are still processing. Overall latency is dominated by the slowest expert.", "sha256": "26270290a5cf5b38ab518ba334c9d8b6010db034ddc8f8a8c7e1f1259fd5d985"}, {"id": "u002", "kind": "list-item", "locator": "body:L9-L9", "preview": "1. **Skewed token distribution**: Router sends 80% of tokens to 20% of experts (common in trained MoE models)", "sha256": "800cba0e70b4a438a24067f4f7787eadc3ab4ad4897336310a5d3dd010135843"}, {"id": "u003", "kind": "list-item", "locator": "body:L10-L10", "preview": "2. **Static tile assignment**: Precomputed tile\u2192SM mapping cannot rebalance at runtime", "sha256": "c283efbc93794cc2be49fd7f07f42e36350aef2957ec6b68e17dbae5a509e635"}, {"id": "u004", "kind": "list-item", "locator": "body:L11-L11", "preview": "3. **Masked layout waste**: Fixed M_max per expert wastes compute on padding rows", "sha256": "fc529e53756a94746ed70c30cd71143674488b5a2462c85453ad818c389ebfbf"}, {"id": "u005", "kind": "list-item", "locator": "body:L12-L12", "preview": "4. **Small-M per expert**: When M < BLOCK_M, thin-GEMM underutilizes tensor cores", "sha256": "f74d67cf19352656a85cf127183325a4ba8c6bcf8e17e9d454de0a4ff5000913"}, {"id": "u006", "kind": "table-row", "locator": "body:L18-L18", "preview": "| Technique | Effect | | [CLC (Cluster Launch Control)](../hardware/clc.md) | Hardware dynamic tile assignment \u2014 fastest SMs grab more tiles |", "sha256": "49bcf4dbc8ad02660ec9047f26f96a3858a2d9fd5222369ebb5bca5776ac57fe"}, {"id": "u007", "kind": "table-row", "locator": "body:L19-L19", "preview": "| Technique | Effect | | [Persistent kernels](../techniques/persistent-kernels.md) | Amortize launch overhead; loop over dynamic work queue |", "sha256": "2792e978d288672f2d6d95d04263027e2622054f2ed15f78de9e3943bb477a10"}, {"id": "u008", "kind": "table-row", "locator": "body:L20-L20", "preview": "| Technique | Effect | | [Contiguous layout](../kernels/grouped-gemm.md) | Pack variable-M experts sequentially; offsets array indexes expert boundaries |", "sha256": "d20ff9922eaef6c226692eae94d058e63be9adf9e98e91e1ceeb9aad71a8e38b"}, {"id": "u009", "kind": "table-row", "locator": "body:L21-L21", "preview": "| Technique | Effect | | [Masked layout](../kernels/grouped-gemm.md) | Good for CUDA graph capture; wastes compute on padding |", "sha256": "3413c434b8113eb19f2d463875390d45fbd8c131d6c860733df1113960b69608"}, {"id": "u010", "kind": "table-row", "locator": "body:L22-L22", "preview": "| Technique | Effect | | [K-grouped layout](../kernels/grouped-gemm.md) | For weight gradient computation with variable K per expert |", "sha256": "b2a0b2fe800e3a99466b916235631662c5fc13c46bb43ca58b717010d8d2bad4"}, {"id": "u011", "kind": "table-row", "locator": "body:L23-L23", "preview": "| Technique | Effect | | [EPLB (Expert Parallel Load Balancer)](https://github.com/deepseek-ai/EPLB) | Replicate heavy experts across GPUs; 1.49x prefill speedup, 2.54x decode |", "sha256": "699ca12f7f2383870531d253ad0ca7bf392aa46c1c04660f59d11b39c1225091"}, {"id": "u012", "kind": "prose", "locator": "body:L27-L27", "preview": "The 1st-place submission exploited the evaluation harness rather than truly balancing load:", "sha256": "13952f31f5f92a411c66686966d9c911baad14e022c7b7ab8c6d9766b54f9b59"}, {"id": "u013", "kind": "list-item", "locator": "body:L28-L28", "preview": "- Correctness phase: real kernel ran on cloned data", "sha256": "44268b4c3d9e50d59288e97ef6ab0d7e92da73ddf6e17c3d2e9afcb36067ec40"}, {"id": "u014", "kind": "list-item", "locator": "body:L29-L29", "preview": "- Timing phase: detected reused objects, fired 120-group super-batch in call 1, returned cached results for calls 2-15", "sha256": "49bf005d0c5aa1f75b3e3a074098548d90a84511bda490e6e94da0d95a954fce"}, {"id": "u015", "kind": "prose", "locator": "body:L31-L31", "preview": "This highlighted that even careful tile scheduling can be outrun by algorithmic restructuring \u2014 and prompted the MLSys 2026 FlashInfer contest to add runtime isolation + subprocess eval.", "sha256": "8b0dd66c79788e1da885d296e6873c972217574a4864892639153a1c5b9cb556"}, {"id": "u016", "kind": "list-item", "locator": "body:L35-L35", "preview": "- CLC only available on SM100 datacenter (not SM120 consumer)", "sha256": "76adb21b9da1b3c422e4e96806d5c9766324fb825ea04c1d6bf43c5c051a74c7"}, {"id": "u017", "kind": "list-item", "locator": "body:L36-L36", "preview": "- Dynamic scheduling has small per-tile overhead vs static precomputed", "sha256": "59c88f69879c5683028c803da56e9e94888bbf568790fc334c872735659ad6f2"}, {"id": "u018", "kind": "list-item", "locator": "body:L37-L37", "preview": "- Small experts may not benefit \u2014 minimum viable tile size is a floor", "sha256": "cebcd3944c50b6c03c42697299819ac55c9910f396999bdf616538b2e9844aa7"}, {"id": "u019", "kind": "list-item", "locator": "body:L38-L38", "preview": "- EPLB works at cluster scale, not single-device", "sha256": "153c61615671921ed0408938218d9b06e56c3d0818ff73f546d85a82a311c83e"}, {"id": "u020", "kind": "list-item", "locator": "body:L42-L42", "preview": "- Uniform routing (rare in practice)", "sha256": "ee7bf1426e5cbead527debaf61009d5004931fd3175bfdf22cbf7e8d7c295497"}, {"id": "u021", "kind": "list-item", "locator": "body:L43-L43", "preview": "- Very large batch sizes (statistics average out)", "sha256": "6a555d86519621d8cf74821617146ba700ea5493a2ebe2e7380c9707192f16d6"}, {"id": "u022", "kind": "list-item", "locator": "body:L44-L44", "preview": "- Training with auxiliary load balancing loss", "sha256": "ad4574cc7d6d92b10a813303b13b944dde68868576cd30add7fc998cd270fe97"}], "confidence_claimed": null, "headings": ["Symptom", "Likely Causes", "Candidate Techniques", "Example: Reward Hack in GPU Mode Problem 4", "Caveats", "When NOT An Issue"], "id": "pattern-moe-load-imbalance", "path": "wiki/patterns/moe-load-imbalance.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/contests/gpu-mode-nvfp4/problem-4-grouped-gemm.md", "url": "https://github.com/gpu-mode/reference-kernels"}, {"path": "sources/contests/flashinfer-mlsys26/track-a-fused-moe.md", "url": "https://mlsys26.flashinfer.ai/"}, {"path": "sources/blogs/deepgemm.md", "url": "https://github.com/deepseek-ai/DeepGEMM"}], "risk_flags": ["table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-gpumode-p4", "contest-flashinfer-track-a", "blog-deepgemm"], "title": "MoE Expert Load Imbalance", "type": "pattern", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "ec21f3208711a7056069ab687fce39dd6bc96f6ee8fd093b42542af45799b592", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Nsight Compute shows TMA or tcgen05 units idle despite nominally compute-bound workload. Tensor core utilization drops during specific phases of the kernel. Warp-level profiling reveals threads blocked on `mbarrier.try_wait` more than expec", "sha256": "4032d70f5e4b3925ac907fbc729234379f11c847fba146210288c9a8ec8491d3"}, {"id": "u002", "kind": "list-item", "locator": "body:L9-L9", "preview": "1. **Insufficient pipeline depth**: 2 stages cannot hide a 3-cycle latency chain", "sha256": "0cb8232617e1672be85937beba39a1f5e75b81ea46bf43469391f4b4315b22f4"}, {"id": "u003", "kind": "list-item", "locator": "body:L10-L10", "preview": "2. **Incorrect mbarrier phase tracking**: Consumer observes stale arrivals, waits for next", "sha256": "91d7e4eb0e38d59d5aa1a5aa56faad99d2ec69ed2ede720df86f912e752a81ae"}, {"id": "u004", "kind": "list-item", "locator": "body:L11-L11", "preview": "3. **Missing `tcgen05.fence::after_thread_sync`**: MMA reads SMEM before TMA transfer fully visible", "sha256": "d77d6b104399db6c82c6bbeb66b1a621d106c6dd6b289bcaadb887ad14b7e65e"}, {"id": "u005", "kind": "list-item", "locator": "body:L12-L12", "preview": "4. **Single-tile scheduling**: All warps serialized on one tile's softmax/epilogue", "sha256": "b922275ade0073f6dd7296ab179ba695b5991077ae021e1fab7d4ca1656614e2"}, {"id": "u006", "kind": "list-item", "locator": "body:L13-L13", "preview": "5. **Producer over-arrives**: Manual `mbarrier_arrive` after async TMA \u2014 hardware + manual both arrive, next stage gets stale release", "sha256": "fe84e7ee7ad4f0054a03192c196c441ec9de80b61e80bf3d63a6f9f8010969ec"}, {"id": "u007", "kind": "table-row", "locator": "body:L19-L19", "preview": "| Technique | Effect | | [Pipeline stages](../techniques/pipeline-stages.md) | Increase NUM_STAGES (3-5 typical on Blackwell) |", "sha256": "6f3f738e0e4c76b6c48eae6f58c723ff49ae060351f9951a28bf23f9a2b46fe3"}, {"id": "u008", "kind": "table-row", "locator": "body:L20-L20", "preview": "| Technique | Effect | | [Warp specialization](../techniques/warp-specialization.md) | Dedicated warps for TMA/MMA/epilogue eliminate role-switching stalls |", "sha256": "6149506d8c026954f1683a46ef62eeca174bb51807a37b295c8eb0ff161d3f7a"}, {"id": "u009", "kind": "table-row", "locator": "body:L21-L21", "preview": "| Technique | Effect | | [Double-buffering](../techniques/double-buffering.md) | TMEM buffer A while MMA runs on buffer B |", "sha256": "c14aac1bfc715cfda0e3f3348c2e26505421e9529ba75c8af9fe164f3876ed49"}, {"id": "u010", "kind": "table-row", "locator": "body:L22-L22", "preview": "| Technique | Effect | | [Ping-pong scheduling](../techniques/ping-pong-scheduling.md) | Two query tiles alternate softmax/MMA (FA4 pattern) |", "sha256": "6c130ff135fbe3daf0024f04e57bfea496069a7b25453731535dc0cb168365fd"}, {"id": "u011", "kind": "code", "locator": "body:L26-L33", "preview": "``` 1. Profile with Nsight Compute, check tensor core active cycles 2. Inspect mbarrier wait stalls in warp state breakdown 3. Verify phase tracking increments correctly (each wait should flip parity) 4. Check that TMA uses arrive_expect_tx", "sha256": "b9df86b4e71fc18353da3def4520922d82e87fd6330d8aec04b35338b543aa90"}, {"id": "u012", "kind": "list-item", "locator": "body:L37-L37", "preview": "- 1-stage: 62% of cuBLAS (TMA blocks MMA)", "sha256": "daeade9f55a3938b4ceab512bc437488781118e4ce851f0f4ad8c0fada815969"}, {"id": "u013", "kind": "list-item", "locator": "body:L38-L38", "preview": "- 3-stage pipelined: 70% (hide most TMA latency)", "sha256": "4377018d3c7dd3f0240d868648f6b8fc336736444f6bfa8e3b98b71e68cc1c70"}, {"id": "u014", "kind": "list-item", "locator": "body:L39-L39", "preview": "- Warp specialized: 80% (no role switching)", "sha256": "2460d6863a6c4117289d6904c1e135e666426aa0ac1dcde0b4691dd9341abc60"}, {"id": "u015", "kind": "list-item", "locator": "body:L40-L40", "preview": "- Add 2-SM MMA: 86% (larger tile, more reuse)", "sha256": "8976968aed7db4cde3048b3d0d92f6c77b1213661e4aed2164d33c09c814ae99"}, {"id": "u016", "kind": "list-item", "locator": "body:L41-L41", "preview": "- Persistent + CLC: 98% (eliminate tail effect)", "sha256": "5af1e8033ee259a49ab21e6053709d43a74405847ad202d96a173678b806b643"}, {"id": "u017", "kind": "list-item", "locator": "body:L45-L45", "preview": "- Too many stages consume SMEM; exceeds 228KB budget", "sha256": "e916e057ac5bd922f8a065bd0ca4b3327b885b9c0e211fde7c4b64d8ce14d271"}, {"id": "u018", "kind": "list-item", "locator": "body:L46-L46", "preview": "- Phase tracking bugs are notoriously hard to debug \u2014 add assertions in development", "sha256": "7c96054ce550dc7b762e7375ffce607153d115d44308a7a83ac072240aa39525"}, {"id": "u019", "kind": "list-item", "locator": "body:L47-L47", "preview": "- Profile first \u2014 pipeline is a waste of effort on memory-bound kernels", "sha256": "9320fb1619594e5c38103bdd57e2112552752b210fb4a5e1f872528fe3c60c49"}], "confidence_claimed": null, "headings": ["Symptom", "Likely Causes", "Candidate Techniques", "Diagnosis Checklist", "Example Progression (tcgen05 tutorial)", "Caveats"], "id": "pattern-pipeline-stalls", "path": "wiki/patterns/pipeline-stalls.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/blogs/flash-attention-4.md", "url": "https://tridao.me/blog/2026/flash4/"}, {"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-tcgen05-tutorial", "blog-flash-attention-4", "doc-nvidia-tuning-guide"], "title": "Pipeline Stalls", "type": "pattern", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "6fd15f8aae2d1ca78d038b8af9ec545760eac38cdbb46e46985f19c35a84a491", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Occupancy below target due to high register usage per thread. Nsight Compute shows register spilling to local memory.", "sha256": "d2ac11ac70671d4aeb74c58a0a6b9bab0cdd4c2d07b3366cdfb1570acef35355"}, {"id": "u002", "kind": "list-item", "locator": "body:L7-L7", "preview": "1. **Accumulator registers**: On Hopper, large MMA tiles consume many registers for accumulators", "sha256": "de2257f0b6f0c80133c86c37838724423e7507ecc9614670890ceae87424fade"}, {"id": "u003", "kind": "list-item", "locator": "body:L8-L8", "preview": "2. **Epilogue state**: Data transformation in epilogue requires additional registers", "sha256": "aaa6f9054e67591cfab71e16eea3a4522286eaa7f1c3417eea8fabee81bf47ae"}, {"id": "u004", "kind": "list-item", "locator": "body:L9-L9", "preview": "3. **Complex control flow**: Many live variables across branches", "sha256": "d33663262ccd89d8aa00ac29ecf817e99f0855f70a4fddf30fdaeb3dbcc626de"}, {"id": "u005", "kind": "table-row", "locator": "body:L15-L15", "preview": "| Technique | Applicability | Effect | | [TMEM](../hardware/tmem.md) | SM100 only | Moves accumulators to dedicated 256KB memory |", "sha256": "9f90dd64b6e0a1e5474f59960756cc72ca2fe0f274af67e270c9a3d76c304d46"}, {"id": "u006", "kind": "table-row", "locator": "body:L16-L16", "preview": "| Technique | Applicability | Effect | | [Warp specialization](../techniques/warp-specialization.md) | SM100+ | Different warps handle different roles, reducing per-warp register needs |", "sha256": "ab88df1d4048970662593fa2cbde9264f1214c1d1f23bfc3d777d23d0f1204ec"}, {"id": "u007", "kind": "table-row", "locator": "body:L17-L17", "preview": "| Technique | Applicability | Effect | | [Register-to-TMEM migration](../migration/register-to-tmem.md) | SM90\u2192SM100 | Systematic approach to moving accumulators off registers |", "sha256": "7169a86f303c5aaee56eb9016eb702859a933d7684c4dcce7542711f13d054fa"}, {"id": "u008", "kind": "code", "locator": "body:L21-L31", "preview": "``` // Hopper: 64\u00d7256 MMA tile accumulator = 64*256*4 bytes in registers per warp group // \u2192 ~128 registers per thread just for accumulators // // Blackwell: TMEM holds accumulators // \u2192 0 registers for accumulators // \u2192 ~128 registers free", "sha256": "7dbbada6653f79e04b54cc53ab013df61ca8263d3abfce21813daa5b4a5ad9af"}, {"id": "u009", "kind": "list-item", "locator": "body:L34-L34", "preview": "- TMEM only available on SM100 datacenter (not SM120 consumer)", "sha256": "beedff9c79765bf0578733865359482fdf1c0028cadeb2bb71cb482da9cdc742"}, {"id": "u010", "kind": "list-item", "locator": "body:L35-L35", "preview": "- TMEM requires explicit alloc/dealloc lifecycle", "sha256": "9e7d07ef558cf4d22231cfc469028a647d6924a327caeccb143785d22219b122"}, {"id": "u011", "kind": "list-item", "locator": "body:L36-L36", "preview": "- TMEM\u2192register transfer adds latency (offset by freeing registers)", "sha256": "5b322c2b7c5cb6ef89d08e58652b159e888517d7fea0e7f0cec00173096f7c76"}], "confidence_claimed": null, "headings": ["Symptom", "Likely Causes", "Candidate Techniques", "Blackwell Solution", "Caveats"], "id": "pattern-register-pressure", "path": "wiki/patterns/register-pressure.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/prs/vllm/PR-16032.md", "revision": "ed7a29d9", "url": "https://github.com/vllm-project/vllm/pull/16032"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "pr-vllm-16032"], "title": "Register Pressure \u2014 Low Occupancy", "type": "pattern", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "796c1dd09a9e76eff0996bf41283998fce447e492dd300571596ec89ad147ed9", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Performance drops for problem sizes where total_tiles % num_SMs != 0. The last wave of tiles runs with many SMs idle.", "sha256": "ea0c41c307bdd4f791565d1552e46e283100208e9ff10eba22954565761c5604"}, {"id": "u002", "kind": "list-item", "locator": "body:L7-L7", "preview": "1. **Wave quantization**: Grid of N tiles on M SMs takes ceil(N/M) waves; last wave may use only N%M SMs", "sha256": "0ed8e43be29b45288db1023d10e10a63b3b7ce9be71c046a10b1862414f204b0"}, {"id": "u003", "kind": "list-item", "locator": "body:L8-L8", "preview": "2. **Static assignment**: stride-by-gridDim leaves remainder tiles on few SMs", "sha256": "e80998af0a65b1cbcafb7a22edc7cb17f58e403f7bb6d15a4709aeb01e886d84"}, {"id": "u004", "kind": "list-item", "locator": "body:L9-L9", "preview": "3. **Non-persistent launch**: each kernel launch has fixed grid, no dynamic rebalancing", "sha256": "20f6e34bc0ccec42ad97d7117f02b06b11d70c03705e449c309e51b017ac376c"}, {"id": "u005", "kind": "table-row", "locator": "body:L15-L15", "preview": "| Technique | Effect | | [CLC](../hardware/clc.md) | Hardware dynamic scheduling, SMs grab tiles on-demand |", "sha256": "04e0ce4ac625fe8083068eb8a2f249bc9dbdc866d4cbf686eb43054fb688b5c1"}, {"id": "u006", "kind": "table-row", "locator": "body:L16-L16", "preview": "| Technique | Effect | | [Persistent kernels](../techniques/persistent-kernels.md) | SM-count grid, iterate over tiles, no wave boundary |", "sha256": "e47a5eca8af15fa32dcaa55c77df276b6ddaf12ebe96603730fa449391c3bd8f"}, {"id": "u007", "kind": "table-row", "locator": "body:L17-L17", "preview": "| Technique | Effect | | [Tile scheduling](../techniques/tile-scheduling.md) | Raster order, swizzle patterns for better distribution |", "sha256": "8235d5f10cb6616f94cf20bfe9f2763cb6f832c0f0e63ea290c2c3b947359a09"}, {"id": "u008", "kind": "code", "locator": "body:L21-L28", "preview": "``` // B200: 142 SMs // Problem: 150 tiles // Without CLC: 2 waves (142 + 8), last wave uses only 8 SMs (5.6%) // With CLC: single persistent wave, all 142 SMs stay busy // // Impact: 86% \u2192 98% of cuBLAS (tcgen05 tutorial data) ```", "sha256": "7100363602e3f45ee5b5aa49fa60ab3fb42c04a27a08e87a21d5398cfe53e578"}, {"id": "u009", "kind": "list-item", "locator": "body:L31-L31", "preview": "- Only significant for moderate tile counts (< 4\u00d7 SM count)", "sha256": "2670f5539f33eb07230fabfa084f24e9f07596a616fe7e28da5d546fc9fa47a2"}, {"id": "u010", "kind": "list-item", "locator": "body:L32-L32", "preview": "- For very large problems, tail effect is amortized across many waves", "sha256": "50cc74b0317aa0b78f48ee04a7790f07f1c5b685ca933fae6e1f86a23d90a882"}, {"id": "u011", "kind": "list-item", "locator": "body:L33-L33", "preview": "- CLC only on SM100 datacenter", "sha256": "fdfc563aa627d856b7997864f874000bd1cf6e34a61465c366a1773035f335f6"}], "confidence_claimed": null, "headings": ["Symptom", "Likely Causes", "Candidate Techniques", "Example", "Caveats"], "id": "pattern-tail-effect", "path": "wiki/patterns/tail-effect.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/prs/cutlass/PR-2161.md", "revision": "06e560d9", "url": "https://github.com/NVIDIA/cutlass/pull/2161"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "pr-cutlass-2161"], "title": "Tail Effect \u2014 Last Wave Underutilization", "type": "pattern", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "a47c6862f01b21f93a8d51024e927b47f02eba0fe5852a52053fb9b1080e1498", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "PTX cache qualifiers (`L1::no_allocate`, `L1::evict_last`, `L1::evict_first`) let kernels hint to hardware how to handle cache admission for specific loads. Critical for memory-bound kernels where the L1 working set matters more than the co", "sha256": "54cab58e62ef06bdef4cf5fc91778a59615e0ab38500f8740b2e6f4567fbde09"}, {"id": "u002", "kind": "code", "locator": "body:L9-L19", "preview": "```asm ; Matrix A (streamed once per row, never reused): bypass L1 ; Avoids polluting L1 with one-shot data ld.global.L1::no_allocate.v4.u64 {a0,a1,a2,a3}, [addr_a]; ; Vector B (reused across BLOCK_M rows): keep in L1 ld.global.L1::evict_la", "sha256": "23a8aea5fea29b291992023b0f9304f0f5c2d2f3cb19fc1f6ff72c8169fd4845"}, {"id": "u003", "kind": "prose", "locator": "body:L23-L23", "preview": "Rank 1 submission used **different qualifiers per K-dimension variant**:", "sha256": "929723cf95b932abdb41d1d7772b296a74efabf583d9f57cb44956ce8dcf1300"}, {"id": "u004", "kind": "list-item", "locator": "body:L24-L24", "preview": "- K=16384 (large): aggressive `L1::no_allocate` on A (huge streaming matrix)", "sha256": "ebe021ea0f87a111104ff40b1ee54c97eb289cce36e1b3406eac30e1426999ef"}, {"id": "u005", "kind": "list-item", "locator": "body:L25-L25", "preview": "- K=2048 (small): relaxed balance since B is smaller relative to cache", "sha256": "a34ff1ee0912ff6efd24a3735a50b82ac3944355ce6af6202db6734abeed7102"}, {"id": "u006", "kind": "list-item", "locator": "body:L29-L29", "preview": "- NVFP4 GEMV: 443\u03bcs \u2192 27\u03bcs (16x improvement) came partly from cache policy + PTX byte unpacking", "sha256": "91db32f48f31f818adf7240d21f9ca08975ba1b3ff1e89166b2533e29c1cff1a"}, {"id": "u007", "kind": "list-item", "locator": "body:L30-L30", "preview": "- On memory-bound kernels, cache policy can be the dominant lever", "sha256": "30fde58ffce939740980ec4c690bcc0f617768b828daa5705b74c41e30169502"}, {"id": "u008", "kind": "list-item", "locator": "body:L34-L34", "preview": "- Memory-bound kernels (profile with Nsight Compute first)", "sha256": "859dfb4b1dbefd115e0269680e0508a99a50fb2442f70ea9a5faa928fd4e7151"}, {"id": "u009", "kind": "list-item", "locator": "body:L35-L35", "preview": "- Tensor with clear \"streaming\" vs \"reused\" access patterns", "sha256": "9c233103abf17311221463c5ef9e1356e0843d4d32bed9484279182fa341e78e"}, {"id": "u010", "kind": "list-item", "locator": "body:L36-L36", "preview": "- Inputs > L2 cache size (B200: 126MB)", "sha256": "a4f399076d2b6ae932d4f1df179e9c372391a89221ea7981c895a745db0e5a3b"}, {"id": "u011", "kind": "list-item", "locator": "body:L37-L37", "preview": "- Separate M and N tile loading patterns in GEMM", "sha256": "9be234f588406c67bc6287d3c5cb854809e686902a1378e724795a23c4469ebd"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Pattern", "GPU Mode NVFP4 GEMV Winner Technique", "Measurable Impact", "When To Use"], "id": "technique-cache-policy", "path": "wiki/techniques/cache-policy.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/yue-nvfp4-hackathon.md", "url": "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"}, {"path": "sources/blogs/amandeep-nvfp4-attempts.md", "url": "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"}, {"path": "sources/blogs/simon-nvfp4-gemv.md", "url": "https://veitner.bearblog.dev/nvfp4-gemv/"}, {"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/parallel-thread-execution/"}], "risk_flags": ["code"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-yue-nvfp4", "blog-amandeep-nvfp4", "blog-simon-nvfp4-gemv", "doc-ptx-isa-sm100"], "title": "PTX Cache Policy Differentiation", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "c8d85d250f8216c456f2c7737203ae250b1b6d85d9d6150336ed406b13ceb20d", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L6", "preview": "Use CCCL/CUB PRs when the bottleneck is not tensor math but a memory primitive: scan, top-k selection, fill, histogram, reduce, or block load/store policy. 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On Blackwell, this pattern applies at two distinct levels: (1) TMEM double-buffering for overlapping", "sha256": "97824e9b7c93a3ea45b6e343a729a81924da29e8de1c7297ee01a4efa2f7b7a5"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "Tensor Memory (TMEM) on Blackwell has 128 rows x 512 columns of 32-bit elements (256 KB per SM). For a standard GEMM with TILE_M=128, TILE_N=256, the accumulator requires 128 x 256 = 32,768 elements, which fits in half the TMEM column space", "sha256": "640c707834ddf8a8ce180197e801e9d7b95977d52cb6f99cf485d9e585092007"}, {"id": "u003", "kind": "code", "locator": "body:L9-L105", "preview": "```cuda // TMEM double-buffering: ping-pong between two 128x256 accumulator regions // // TMEM physical layout (per SM): // +------ 256 cols ------+------ 256 cols ------+ // | | | // | Buffer A (active) | Buffer B (drain) | 128 rows // | M", "sha256": "09ad4012498a0cf25db398856e7d71e60967607f31556eb3c34988b84965c1c3"}, {"id": "u004", "kind": "prose", "locator": "body:L109-L109", "preview": "Shared memory multi-buffering provides multiple copies of the A and B input tiles so that TMA loads can overlap with MMA consumption:", "sha256": "a1d0e1d2fc608bdffeb1c621b1abfa260c58fc98e117399b96ce6adc665e864b"}, {"id": "u005", "kind": "code", "locator": "body:L111-L138", "preview": "```cuda // SMEM multi-stage buffer allocation // 3 stages, each holding one A tile and one B tile // // Memory layout: // +--------+--------+--------+ // | Stage0 | Stage1 | Stage2 | // | A0 B0 | A1 B1 | A2 B2 | // +--------+--------+------", "sha256": "751c3e5b2f00a215d113317b80a82c5c07a3ed27b567bd46eb506671c35035c3"}, {"id": "u006", "kind": "prose", "locator": "body:L142-L142", "preview": "A fully optimized Blackwell GEMM uses both levels simultaneously:", "sha256": "33bd5f5682f36690671b018c0ce9e0e42947ecbb71aa898182eae2d113c52acf"}, {"id": "u007", "kind": "code", "locator": "body:L144-L190", "preview": "```cuda // Combined double-buffering: SMEM (3-stage) + TMEM (2-buffer) // // Outer loop: output tiles (TMEM double-buffered) // Inner loop: K-tiles (SMEM 3-stage pipelined) // // Timeline for 2 output tiles, 6 K-tiles each: // // TMEM buf: ", "sha256": "8738f3a9188308d89ea4c9c189f4b55815b721c20da41da8c3fae854615fa882"}, {"id": "u008", "kind": "prose", "locator": "body:L194-L194", "preview": "On Hopper (SM90), there is no TMEM. The accumulator lives in registers, and double-buffering the accumulator requires explicit register management:", "sha256": "f69660751f2b081c6acae0d709ee8e397d44afb3d9461288c63689a6b3311d7a"}, {"id": "u009", "kind": "code", "locator": "body:L196-L212", "preview": "```cuda // Hopper: accumulator double-buffering uses register arrays // Each warpgroup maintains two register-based accumulators // This doubles register pressure and reduces occupancy // Hopper approach (register pressure is the primary co", "sha256": "fac6da39b649d3725528d820da41fbd66daa71b7014b1e51707a95246a7d95f1"}, {"id": "u010", "kind": "table-row", "locator": "body:L216-L216", "preview": "| Aspect | Hopper (Registers) | Blackwell (TMEM) | | Accumulator storage | Thread-local registers | CTA-wide TMEM |", "sha256": "72d87a8b59b3429cc3bdf2791bfe30efd1024670fef317070e468ad27afe1edd"}, {"id": "u011", "kind": "table-row", "locator": "body:L217-L217", "preview": "| Aspect | Hopper (Registers) | Blackwell (TMEM) | | Double-buffer cost | 2x register usage | Zero register cost |", "sha256": "755418548c845ddad020907f1632ae4d5aadc0b3c185c07bb68ab4856b9899d5"}, {"id": "u012", "kind": "table-row", "locator": "body:L218-L218", "preview": "| Aspect | Hopper (Registers) | Blackwell (TMEM) | | Typical occupancy impact | Reduces from 2 to 1 CTA/SM | No impact |", "sha256": "7bb87c122c4e1accbb09da2ed4120902b9c9553c5fae37e27fde69426bf96f0d"}, {"id": "u013", "kind": "table-row", "locator": "body:L219-L219", "preview": "| Aspect | Hopper (Registers) | Blackwell (TMEM) | | Epilogue access | Direct (already in registers) | TMEM load required |", "sha256": "283a7775fe3db59d62b5f298aa22e87e359a121ab1ac25a4d5968dd5ff6669fa"}, {"id": "u014", "kind": "table-row", "locator": "body:L220-L220", "preview": "| Aspect | Hopper (Registers) | Blackwell (TMEM) | | Max accumulator size | ~16K elements (register limited) | 128x512 = 65K elements |", "sha256": "986b30ee3467a4797ccb0f3c9e46db5afeeeff8e680c36ef68971084a8aa0084"}, {"id": "u015", "kind": "list-item", "locator": "body:L224-L224", "preview": "- **TMEM double-buffering**: Always use on Blackwell when the epilogue takes more than trivial time. The only cost is the TMEM space, which is plentiful.", "sha256": "f8cc6a2cf091f9c2f0acbe8a03f81a6d3ec7f76e1ddccadc1f3acb2f9de1a995"}, {"id": "u016", "kind": "list-item", "locator": "body:L225-L225", "preview": "- **SMEM multi-stage buffering**: Always use for GEMM/attention mainloops. 3 stages is the default; increase to 4-5 only if the K-loop is long and memory latency is high.", "sha256": "987665c644857e5a3bfa77429b8448c0dbca2cb1e862c4042285758482e97764"}, {"id": "u017", "kind": "list-item", "locator": "body:L226-L226", "preview": "- **Combined**: The standard approach for production Blackwell GEMM kernels. Both CUTLASS and CuTe-DSL kernels use this pattern.", "sha256": "4262ae22892600361751316d3041af62d7fa3d304a84866f58d765817bc36399"}, {"id": "u018", "kind": "list-item", "locator": "body:L230-L230", "preview": "- TMEM double-buffering requires that the accumulator fits in half the TMEM columns (256 out of 512). For very wide tiles (TILE_N > 256 with FP32 accumulators), the tile must be split or a different buffering strategy used.", "sha256": "879c33db44d9c122b0f351e266a90a18eb9f16e13c4933e48e24e5b622f1a9d6"}, {"id": "u019", "kind": "list-item", "locator": "body:L231-L231", "preview": "- SMEM multi-stage buffering is constrained by the 228 KB SMEM limit. With 3 stages of large tiles, there may not be enough SMEM left for epilogue scratch space.", "sha256": "c3506ef7844eee5b0fa9826ecfbbd0d4ee9a5fcdfa6b0f9b2b1ea8b9a3153397"}, {"id": "u020", "kind": "list-item", "locator": "body:L232-L232", "preview": "- The mbarrier synchronization between TMEM buffers adds a few cycles of overhead per tile. For kernels with very few K-iterations per tile, this overhead is proportionally larger.", "sha256": "a149fb89ca7dee743cd8577c21ac7a6fbf1186d2d3e5190a9d8182bf6af8d350"}], "confidence_claimed": "source-reported", "headings": ["Overview", "TMEM Double-Buffering", "SMEM Multi-Stage Buffering", "Combined TMEM + SMEM Double-Buffering", "Comparison with Hopper", "When to Use", "Caveats"], "id": "technique-double-buffering", "path": "wiki/techniques/double-buffering.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/prs/flashinfer/PR-2387.md", "revision": "18804cd5", "url": "https://github.com/flashinfer-ai/flashinfer/pull/2387"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-tcgen05-tutorial", "doc-nvidia-tuning-guide", "pr-flashinfer-2387"], "title": "Double/Multi-Buffering Patterns", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "f37f59190f56273dbd2ec10059fd85e03af89ea72f6cf5e9898fb14e1f3fd450", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Epilogue fusion overlaps the post-MMA operations (scaling, bias addition, activation functions, quantization, store to global memory) with ongoing MMA computation. On Blackwell, the accumulator lives in TMEM rather than registers, enabling ", "sha256": "8413c5da77a037d33a6338630dd5c1cbe24cd3d84fe6ceef5d920cea551e25a5"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "On Blackwell, the MMA result resides in Tensor Memory (TMEM). Epilogue warps must copy relevant portions of TMEM into registers before applying element-wise operations and writing to global memory:", "sha256": "81f41666ca91671f9fe10ea6fc7b97908dd9ff1b3c80195c069f20417607dc43"}, {"id": "u003", "kind": "code", "locator": "body:L9-L47", "preview": "```cuda // Epilogue warp: read TMEM accumulator, apply fused operations, store // This runs on warps 2-15 while warp 1 continues MMA on next tile __device__ void epilogue_warp_fn( int warp_id, int tile_m, int tile_n, float scale, const floa", "sha256": "33a4ebdcfe0c352ffbc0972fab3d0430b9bfc7261582f5bcfae75eafcf54a87e"}, {"id": "u004", "kind": "prose", "locator": "body:L51-L51", "preview": "The key to epilogue fusion on Blackwell is TMEM double-buffering. The 512-column TMEM space is split into two halves (columns 0-255 and 256-511). While the MMA warp accumulates into one half, the epilogue warps drain the other:", "sha256": "25a3bc6b0f16f88b53ddbe897df79ad650460d0dde529839bbb35e5085661cb7"}, {"id": "u005", "kind": "code", "locator": "body:L53-L126", "preview": "```cuda // TMEM double-buffering for MMA-epilogue overlap // // TMEM layout: 128 rows x 512 columns (32-bit elements) // Buffer A: columns [0, 255] -- 128 x 256 accumulator // Buffer B: columns [256, 511] -- 128 x 256 accumulator // // Time", "sha256": "f97e21b54c56438c47ccb356146fd3d834b2f5e4229e1dc3228f6fde89acb001"}, {"id": "u006", "kind": "prose", "locator": "body:L130-L130", "preview": "CUTLASS 4.5.0 provides composable epilogue visitors that fuse arbitrary element-wise operations after GEMM:", "sha256": "5200b7446fe3f04f2165e5ce30466a397ad5584faca077c5c649ba5e08f681e1"}, {"id": "u007", "kind": "code", "locator": "body:L132-L159", "preview": "```cuda // CUTLASS SM100 epilogue with fused scale + bias + activation // Uses the EVT (Epilogue Visitor Tree) pattern using EpilogueOp = cutlass::epilogue::fusion::LinCombEltAct< cutlass::epilogue::thread::ReLU, // Activation function floa", "sha256": "33cf22b05847bfa2ad96cb950ca02880e7dac120b5c622a83907261f68e16449"}, {"id": "u008", "kind": "table-row", "locator": "body:L165-L165", "preview": "| Operation | Description | Typical Use | | Scale + Bias | `y = alpha * acc + beta * C` | Standard GEMM epilogue |", "sha256": "9603bdf8a80e506de92d55d1a2774814c9a4c5bc26c1cf7dc522b99c5253ad7b"}, {"id": "u009", "kind": "table-row", "locator": "body:L166-L166", "preview": "| Operation | Description | Typical Use | | ReLU / GeLU / SiLU | Element-wise activation | MLP layers |", "sha256": "0514cf37e7ff7ad2bdf319ac2e86d2437f7874c67462f270ca59cf6993a07c16"}, {"id": "u010", "kind": "table-row", "locator": "body:L167-L167", "preview": "| Operation | Description | Typical Use | | Quantize | FP32 accumulator to FP8/FP16 | Inference quantization |", "sha256": "c39917be889b9752756a3c115f276572a73fe728ac6cc294baa5fb2844d5053c"}, {"id": "u011", "kind": "table-row", "locator": "body:L168-L168", "preview": "| Operation | Description | Typical Use | | SwiGLU gate | `y = SiLU(gate) * up` | Gated dual GEMM (LLM FFN) |", "sha256": "117a20dd183922a19b68079a5df6763e9da568950140a279426d396e37177237"}, {"id": "u012", "kind": "table-row", "locator": "body:L169-L169", "preview": "| Operation | Description | Typical Use | | Softmax rescale | `y = acc * exp(max_old - max_new)` | Attention epilogue |", "sha256": "c0fdd61e61c8c91ccbac1eaf70a94a5a97cadb646fe2bbbe5e5fbeadd7989bea"}, {"id": "u013", "kind": "table-row", "locator": "body:L170-L170", "preview": "| Operation | Description | Typical Use | | Residual add | `y = acc + residual` | Transformer blocks |", "sha256": "2f1600022b8f8229cc4ed7c35bcc164ff64a6a57eccfbcb70360339aca5fc885"}, {"id": "u014", "kind": "list-item", "locator": "body:L174-L174", "preview": "- **All Blackwell GEMMs with non-trivial epilogues**: The 14 epilogue warps are available by default in the warp-specialized model. Fusing operations avoids a separate kernel launch and an extra global memory round-trip.", "sha256": "08b535f95ac9ad036c111b2367f3e7c16404adc43b45f6fc1cd16f4627f365c4"}, {"id": "u015", "kind": "list-item", "locator": "body:L175-L175", "preview": "- **Attention kernels**: The softmax rescaling and output accumulation can be overlapped with the next KV tile's MMA.", "sha256": "e0931e1c5cba46b39e6f6837387298705331e7e9a2d1dd54590ee2cd2c49c61a"}, {"id": "u016", "kind": "list-item", "locator": "body:L176-L176", "preview": "- **Quantized inference**: FP32-to-FP8 conversion in the epilogue avoids writing FP32 intermediates to global memory.", "sha256": "60562f12492d41ceebca27c8e3dac2da398882905cece20f5b5565978ea0919d"}, {"id": "u017", "kind": "list-item", "locator": "body:L180-L180", "preview": "- The epilogue can only read TMEM after the MMA for that tile is complete. The double-buffer synchronization is mandatory to prevent reading partial results.", "sha256": "e8be4778cb552c31e16fde7a0ea31a3c3ab9fd6f392a86e1914181880ac0ff46"}, {"id": "u018", "kind": "list-item", "locator": "body:L181-L181", "preview": "- TMEM-to-register bandwidth is not unlimited. With 14 warps simultaneously reading TMEM, each warp gets a proportional share. Very wide output tiles (large TILE_N) may bottleneck on TMEM read bandwidth.", "sha256": "f13e4d40944837027966030233028593a1702eccc9e0bf6d9d519929ae40a466"}, {"id": "u019", "kind": "list-item", "locator": "body:L182-L182", "preview": "- Simple epilogues (just store) waste the 14 epilogue warps. For such cases, consider reducing the CTA size or assigning epilogue warps to other work (e.g., next-tile TMA prefetch).", "sha256": "d3fd45594046b22ecbd2558a1c2c899be3ee885ca04979086a84a4d3c62d93a5"}, {"id": "u020", "kind": "prose", "locator": "body:L186-L186", "preview": "Verbatim upstream code lives in [`artifacts/kernels/epilogue-fusion/full/`](../../artifacts/kernels/epilogue-fusion/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live i", "sha256": "21b4bfd6d6a2db4f10f88ccc5a57aa8f827a9fc64dc7d0345c6b75de694a2148"}, {"id": "u021", "kind": "prose", "locator": "body:L188-L188", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u022", "kind": "code", "locator": "body:L190-L192", "preview": "```bash python3 scripts/get_page.py technique-epilogue-fusion --include-code ```", "sha256": "351eca3c2459d80306042e1cfce4f77d70756f76d7812bac12bfb36aa59ce14d"}], "confidence_claimed": "source-reported", "headings": ["Overview", "TMEM-to-Register Epilogue Path", "Overlapping MMA with Epilogue via Double-Buffering", "CUTLASS Epilogue Patterns", "Common Fused Epilogue Operations", "When to Use", "Caveats", "Full Reference Implementation"], "id": "technique-epilogue-fusion", "path": "wiki/techniques/epilogue-fusion.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-cutlass-blackwell.md", "url": "https://docs.nvidia.com/cutlass/latest/CHANGELOG.html"}, {"path": "sources/blogs/colfax-cutlass-blackwell.md", "url": "https://research.colfax-intl.com/cutlass-tutorial-writing-gemm-kernels-using-tmem-for-nvidia-blackwell-gpus/"}, {"path": "sources/prs/vllm/PR-16032.md", "revision": "ed7a29d9", "url": "https://github.com/vllm-project/vllm/pull/16032"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-cutlass-blackwell", "blog-colfax-cutlass", "pr-vllm-16032"], "title": "Epilogue Fusion", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "0455e988208712c28de6084a897d46734ceafe52da948a9d9d003458f845b2c6", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L6", "preview": "Use external source-map research after a profile or benchmark identifies an edit family but the local PR pages do not expose a small enough implementation example. The route is code-first: clone a source-map repository, grep for the measure", "sha256": "fda0609578ad9b7467f4b3c896a7974dfa501c346bd421c46c2ae495e6f05f4e"}, {"id": "u002", "kind": "code", "locator": "body:L8-L12", "preview": "```bash git clone https://github.com/ColfaxResearch/cfx-article-src external/colfax-cfx git clone https://github.com/simveit/load_and_store external/simveit-load-store rg -n \"tma|mbarrier|swizzle|ldmatrix|stream\" external/colfax-cfx externa", "sha256": "4cb7dd51d7a1fbf99bbb5ac8eda9d5b3bc6e28b9f39811f75b8855b07d7717a1"}, {"id": "u003", "kind": "list-item", "locator": "body:L16-L16", "preview": "- Long-scoreboard or poor sector utilization: search load/store and transpose", "sha256": "e1e044d285783854df02bf8775c4f702232a5f2b7144c9542b48b4d552406434"}, {"id": "u004", "kind": "prose", "locator": "body:L17-L17", "preview": "examples before changing vector width or memory layout.", "sha256": "391b8cb5e8d5f96f47b57d53e85abc1c1aee4bdf998b8530dd785aa7af073d51"}, {"id": "u005", "kind": "list-item", "locator": "body:L18-L18", "preview": "- Barrier or TMA wait stalls: search pipelined GEMM examples before changing", "sha256": "7e9ff9c50c4602a68fd32910799ddbf40bec206464970182f14efa6c41d6b1bc"}, {"id": "u006", "kind": "prose", "locator": "body:L19-L19", "preview": "stage count or producer/consumer split.", "sha256": "897a2d90db28ffd767f093cfd9fd0e1c58191433706e2615237d99e154b5afd5"}, {"id": "u007", "kind": "list-item", "locator": "body:L20-L20", "preview": "- Tail waves: search persistent and Stream-K examples before adding a", "sha256": "1e8bc5bf8e3008ac0e8cb5b0a5184d8c51d6121e2106505281564b61a0555d1f"}, {"id": "u008", "kind": "prose", "locator": "body:L21-L21", "preview": "shape-specific dispatcher.", "sha256": "c6f18a9f9adbcdb6e4300adadb01c2ffea5380c371d5d41254c9f9eb257bb702"}, {"id": "u009", "kind": "prose", "locator": "body:L25-L27", "preview": "Do not cite this page as implementation evidence by itself. Cite one of its source pages plus the concrete upstream file path, commit, or URL that shaped the candidate edit.", "sha256": "d0dc5c2a2f12ea0362817f297ebdc9e090e4cdf93b7b1de5bd7a0005a6342830"}], "confidence_claimed": "source-reported", "headings": ["Use", "When It Helps", "Provenance Rule"], "id": "technique-external-source-map-research", "path": "wiki/techniques/external-source-map-research.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/nvidia-code-samples.md", "url": "https://github.com/NVIDIA-developer-blog/code-samples"}, {"path": "sources/blogs/colfax-article-source-kernels.md", "url": "https://github.com/ColfaxResearch/cfx-article-src"}, {"path": "sources/blogs/colfax-cutlass-kernels.md", "url": "https://github.com/ColfaxResearch/cutlass-kernels"}, {"path": "sources/blogs/simveit-effective-transpose.md", "url": "https://github.com/simveit/effective_transpose"}, {"path": "sources/blogs/simveit-load-and-store.md", "url": "https://github.com/simveit/load_and_store"}], "risk_flags": ["code", "ordering"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-nvidia-code-samples", "blog-colfax-article-source-kernels", "blog-colfax-cutlass-kernels", "blog-simveit-effective-transpose", "blog-simveit-load-and-store"], "title": "External Source-Map Research For Kernel Edits", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "6a7689d9e5c0a13d8fc25daca9b0753cba405982bf7443f5fe50d355601c9952", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Fine-grained quantization applies per-block (rather than per-tensor) scaling factors to low-precision data, preventing outlier values from destroying the quantization precision of an entire tensor. DeepSeek pioneered the tile-wise 1x128 sca", "sha256": "69ea994c6e007c632932eb5141474ff4682345d30f05cdd968507c02f30cce25"}, {"id": "u002", "kind": "code", "locator": "body:L7-L31", "preview": "``` Per-tensor scaling (coarsest): Entire tensor shares one FP32 scale factor. Problem: a single outlier ruins precision for all elements. [=== entire MxK matrix === ] -> 1 scale Per-block 128x128 scaling (weights): Each 128x128 block has i", "sha256": "44b5ff16ab8902c1adb2296033c4501a5a75f6413d1cab24e0eb41c3c16dffc0"}, {"id": "u003", "kind": "prose", "locator": "body:L35-L35", "preview": "DeepGEMM implements fine-grained FP8 GEMM with two scaling patterns:", "sha256": "1d6d0b8a8239becc8c104ba6bf4ea4e6743812453d7b3f86e8d031c693496659"}, {"id": "u004", "kind": "code", "locator": "body:L37-L76", "preview": "```cuda // DeepGEMM FP8 GEMM with fine-grained scaling // A (activations): FP8 E4M3 with tile-wise 1x128 FP32 scales // B (weights): FP8 E4M3 with block-wise 128x128 FP32 scales // C (output): FP32 accumulator // Scale tensor shapes: // sca", "sha256": "88c7ae2257568dbd086e4f4de74f4cd07f153ae301c92b0fcc0052f2d9295880"}, {"id": "u005", "kind": "prose", "locator": "body:L80-L80", "preview": "On Hopper (SM90), the wgmma instruction accumulates in Tensor Core registers with limited precision (~FP22, not true FP32). To maintain numerical accuracy, DeepGEMM promotes the partial sum to a separate FP32 accumulator on CUDA Cores every", "sha256": "47af4e4d25db5502b9b59a75325f9e699f6840549f075e1851da443c9b8afabc"}, {"id": "u006", "kind": "code", "locator": "body:L82-L126", "preview": "```cuda // Hopper FP8 GEMM with CUDA Core promotion (DeepGEMM pattern) // Every Nc=128 K-elements, promote Tensor Core accumulator to FP32 __device__ void hopper_fp8_gemm_with_promotion( const fp8_e4m3* A, const fp8_e4m3* B, const float* sc", "sha256": "2bba6362e8c94126f6cc6bb8d741847f84bf0515dabc3c8e36152aa18e0d0a24"}, {"id": "u007", "kind": "prose", "locator": "body:L128-L128", "preview": "The Nc=128 interval was chosen because:", "sha256": "73a7b47ff0d8d1bd839627042830bc4899aedc9628f798f89f51c305a4e30d94"}, {"id": "u008", "kind": "list-item", "locator": "body:L129-L129", "preview": "- 4 wgmma operations process 128 K-elements (4 x 32)", "sha256": "d553be609f652ef2fab306881444ad91840ba6092b27b799b52606eedda4c578"}, {"id": "u009", "kind": "list-item", "locator": "body:L130-L130", "preview": "- At this interval, the accumulated FP22 error is bounded to ~0.1% relative error", "sha256": "7ba18b03c324394560e8e41b2793e501f8edf488d286ca6fc090b8068c3d8961"}, {"id": "u010", "kind": "list-item", "locator": "body:L131-L131", "preview": "- Fewer than 4 ops (Nc=32, Nc=64) adds too much promotion overhead", "sha256": "7c4371e6acacff82c0c253ae371477a05a288610edb640765ba6f1cbba2dc977"}, {"id": "u011", "kind": "list-item", "locator": "body:L132-L132", "preview": "- More than 4 ops (Nc=256) allows unacceptable precision loss", "sha256": "4f9d6a97a8ee06449508511389e015fb9c08db4155f430af68656ed391530cff"}, {"id": "u012", "kind": "prose", "locator": "body:L136-L136", "preview": "On Blackwell, tcgen05.mma supports native block scaling via the UE8M0 (unsigned 8-bit exponent, no mantissa) format. The hardware applies per-block scale factors directly during the MMA operation, eliminating the software promotion step:", "sha256": "6f3f163ac439ecc4337d319e83e934edb710e7eefdb270cac2f4e1876f415a7e"}, {"id": "u013", "kind": "code", "locator": "body:L138-L158", "preview": "```cuda // Blackwell native block scaling with UE8M0 // Scale format: UE8M0 = pure power-of-two scale (2^exponent) // Packed: 4 UE8M0 values per 32-bit integer // DeepGEMM SM100 kernel: scale_A and scale_B are UE8M0 packed // tcgen05.mma ap", "sha256": "c82d98d828c202d011a0e6d7f4e5841f4defb5b2abc0aacdceb3693b91524729"}, {"id": "u014", "kind": "code", "locator": "body:L160-L171", "preview": "```ptx // tcgen05.mma with native block scaling (Blackwell PTX) // This instruction applies UE8M0 scales from SMEM during MMA tcgen05.mma.cta_group::1.kind::f8f6f4 [%tmem_addr], // TMEM accumulator destination [%desc_a], // SMEM descriptor ", "sha256": "526613b64a2d8018ef4ba7d7b6bc97a1c0c5efcd68b558ed2f5c934ba3164d11"}, {"id": "u015", "kind": "table-row", "locator": "body:L177-L177", "preview": "| Property | UE8M0 (Blackwell native) | E4M3 (NVFP4 hackathon) | FP32 (DeepGEMM Hopper) | | Bits | 8 | 8 | 32 |", "sha256": "44646c385ec1adceae88542d8c19d91e0d014bd23193c59b5ea8b16a20728082"}, {"id": "u016", "kind": "table-row", "locator": "body:L178-L178", "preview": "| Property | UE8M0 (Blackwell native) | E4M3 (NVFP4 hackathon) | FP32 (DeepGEMM Hopper) | | Representable values | Powers of 2 only | 240 distinct values | Full FP32 range |", "sha256": "042eb8db12238b466459dff2dbf12924d215944dc7b22d12a5cf2fa97fb0f29b"}, {"id": "u017", "kind": "table-row", "locator": "body:L179-L179", "preview": "| Property | UE8M0 (Blackwell native) | E4M3 (NVFP4 hackathon) | FP32 (DeepGEMM Hopper) | | Range | 2^-127 to 2^128 | ~0 to 448 | Full FP32 |", "sha256": "71f0851dd2659ae62cc1b796b7f09ceceb099d89ffb961ebdd1f2fb404c5eea6"}, {"id": "u018", "kind": "table-row", "locator": "body:L180-L180", "preview": "| Property | UE8M0 (Blackwell native) | E4M3 (NVFP4 hackathon) | FP32 (DeepGEMM Hopper) | | Block size | 32 (MXFP standard) | 16 (NVFP4) | 128 (DeepGEMM) |", "sha256": "84303981408f8532d9977c8e75a6e3f88b124e4b5d37679286d13af0e212ac84"}, {"id": "u019", "kind": "table-row", "locator": "body:L181-L181", "preview": "| Property | UE8M0 (Blackwell native) | E4M3 (NVFP4 hackathon) | FP32 (DeepGEMM Hopper) | | Hardware support | tcgen05.mma native | Software decode | Software promotion |", "sha256": "12914422262a2b9f0372ead8f9e89f4ea0d3a9be08f4a93d1ee9bf0b57751d52"}, {"id": "u020", "kind": "table-row", "locator": "body:L182-L182", "preview": "| Property | UE8M0 (Blackwell native) | E4M3 (NVFP4 hackathon) | FP32 (DeepGEMM Hopper) | | Precision impact | Coarser (power-of-2 only) | Fine (non-power-of-2) | Best (FP32) |", "sha256": "b873b0baa4c15a1b52abdfaf54afef4409b2902c0e7f71ba20b4db4ecc6d4fdc"}, {"id": "u021", "kind": "prose", "locator": "body:L186-L186", "preview": "The NVFP4 format used in the GPU Mode hackathon has its own scaling scheme:", "sha256": "d3748f2711487284d8a4c19c448b600c08937c032f6a6e5a5c44517c9285a7f4"}, {"id": "u022", "kind": "code", "locator": "body:L188-L211", "preview": "```cuda // NVFP4 dequantization with two-level scaling // Level 1: per-block FP8 E4M3 scale (every 16 FP4 elements) // Level 2: per-tensor FP32 global scale __device__ float dequant_nvfp4( uint8_t fp4_packed, // Two FP4 values packed in one", "sha256": "c5afbdd784a734e5be7a88738c8b5179da8ce1f382d2419158309cae3c5880bc"}, {"id": "u023", "kind": "list-item", "locator": "body:L215-L215", "preview": "- **FP8 training**: Use tile-wise 1x128 for activations and block-wise 128x128 for weights (DeepGEMM pattern). This is the validated approach for training 671B+ parameter models.", "sha256": "b1b2df16a7c020df4c52a84886c04e646e3521d3f86a951034f1459a8d863c6c"}, {"id": "u024", "kind": "list-item", "locator": "body:L216-L216", "preview": "- **FP4 inference on Blackwell**: Use NVFP4 with E4M3 block scales (block size 16) for highest precision, or MXFP4 with UE8M0 scales (block size 32) for native hardware acceleration.", "sha256": "309f292ffece1d8dc137a7e2690318145a332b8f5ee8404b5701898e2f547807"}, {"id": "u025", "kind": "list-item", "locator": "body:L217-L217", "preview": "- **Hopper FP8 inference**: Use CUDA core promotion with Nc=128 interval to maintain precision despite limited TC accumulation.", "sha256": "4850fa287572c51884067ad1b43db7ae5d0e7577577631d375d0e7813e284fc5"}, {"id": "u026", "kind": "list-item", "locator": "body:L221-L221", "preview": "- UE8M0 scales are power-of-two only. Non-power-of-two distributions (common in activations) lose precision compared to E4M3 or FP32 scales.", "sha256": "699a48b3627cad16bd6753ae3b1b8b2b856632bac7018526a0e7773738e5388a"}, {"id": "u027", "kind": "list-item", "locator": "body:L222-L222", "preview": "- Smaller block sizes (16 for NVFP4 vs 128 for DeepGEMM) provide better precision but higher overhead: more scale values to store, load, and apply.", "sha256": "90c3d0ebe6fffa3eba19e4defb5af6411dac30fc5a32a5703fd4a2e8ad45688e"}, {"id": "u028", "kind": "list-item", "locator": "body:L223-L223", "preview": "- The Nc=128 promotion interval on Hopper is a performance-accuracy tradeoff. Reducing Nc improves accuracy but adds more promotion overhead. Increasing Nc risks precision degradation.", "sha256": "8e46f8ccc3b5839ab58ef9b58bb9196e3c20dca3da4f248ee8af48fa6010a05f"}, {"id": "u029", "kind": "list-item", "locator": "body:L224-L224", "preview": "- On Blackwell, native block scaling only works with UE8M0. Using E4M3 or FP32 scales still requires software handling.", "sha256": "d8108b20916960eb4b052c552fc9d6af0269b24a6193cc73a478fb20cc2d4c2f"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Scaling Granularities", "DeepGEMM: Tile-wise and Block-wise Scaling", "Hopper: CUDA Core Promotion (Nc=128)", "Blackwell: Native Block Scaling", "UE8M0 vs E4M3 Scale Formats", "NVFP4 Two-Level Scaling", "When to Use", "Caveats"], "id": "technique-fine-grained-quantization", "path": "wiki/techniques/fine-grained-quantization.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/deepgemm.md", "url": "https://github.com/deepseek-ai/DeepGEMM"}, {"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/prs/vllm/PR-23696.md", "revision": "074854b2", "url": "https://github.com/vllm-project/vllm/pull/23696"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-deepgemm", "doc-nvidia-tuning-guide", "pr-vllm-23696"], "title": "Fine-Grained FP8/FP4 Quantization", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "685ddc5bebbf6ea4d6782e495c6a48fe89232b6b41680c67c23e8921b5ab2ed2", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Kernel fusion combines multiple operations into a single kernel launch, eliminating intermediate global memory roundtrips. Critical for MoE and attention pipelines where 5-7 sequential launches each incur latency, synchronization, and memor", "sha256": "4348a5937ccfed2a939f803579ac3b928863f7321eddd1e4fb25c087a6f2ff92"}, {"id": "u002", "kind": "code", "locator": "body:L10-L26", "preview": "```cuda // Instead of: gate_gemm \u2192 up_gemm \u2192 silu \u2192 multiply (4 kernels) // Fused: single kernel with two TMEM accumulators __global__ void fused_gate_up_silu(...) { uint32_t tmem_gate = tmem_alloc(256); uint32_t tmem_up = tmem_alloc(256); ", "sha256": "9ca307c7663407642158d2f70fe8a4b13b04db4697cdcb498d763444171b54fa"}, {"id": "u003", "kind": "list-item", "locator": "body:L29-L29", "preview": "- **vLLM (7 kernels)**: softmax \u2192 topk \u2192 dispatch \u2192 gate \u2192 up \u2192 silu_mul \u2192 down+combine", "sha256": "77689aa21187be9b45b915ef9cc1f3cd677100447ca4ee721db219b1f5871325"}, {"id": "u004", "kind": "list-item", "locator": "body:L30-L30", "preview": "- **SGLang (5 kernels)**: router+topk \u2192 dispatch \u2192 fused gate-up-silu \u2192 down \u2192 combine", "sha256": "dcd1c6a9b59d0e78c29dd5bf6cf3e94c53a06252e6a26d10eabc3e2fe55e145d"}, {"id": "u005", "kind": "list-item", "locator": "body:L31-L31", "preview": "- **Ideal (1-2 kernels)**: all ops in one launch, saves 21.9% activation memory traffic", "sha256": "39731798392de496da35c97a9ab2225f5493495105689d3977e1e9461d3b684c"}, {"id": "u006", "kind": "list-item", "locator": "body:L35-L35", "preview": "- TMEM capacity limits how many accumulators can fuse (256 cols total)", "sha256": "48720720c315733505b2911628630374c260644bc9845e2cabe261b652afdbc8"}, {"id": "u007", "kind": "list-item", "locator": "body:L36-L36", "preview": "- Register pressure on epilogue if fusing complex activations", "sha256": "648f7d92704df2e751086497d772e17e29429b837b5ced8d7e40244bb0e5970a"}, {"id": "u008", "kind": "list-item", "locator": "body:L37-L37", "preview": "- Fusion opportunities depend on dataflow shape (dependency graph must be DAG-compatible with CTA scope)", "sha256": "be9b6c6cc1824860ab23e11e7e531673511fb8ad0eef90d2f36213271b9d7f5b"}, {"id": "u009", "kind": "list-item", "locator": "body:L40-L40", "preview": "- [fused-moe](../kernels/fused-moe.md)", "sha256": "fa81a99d5f90ff4b3faaeb9180207c7daf999b1a0783f3fbb2c56479431912f1"}, {"id": "u010", "kind": "list-item", "locator": "body:L41-L41", "preview": "- [epilogue-fusion](epilogue-fusion.md)", "sha256": "7473078233c50cac93904892f08c3e7037ecb7747b2b5c9abca0a8dd905cfedc"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Examples", "Fused Gate-Up Dual GEMM + SwiGLU", "MoE Fusion Progression", "Constraints", "Related"], "id": "technique-kernel-fusion", "path": "wiki/techniques/kernel-fusion.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/contests/gpu-mode-nvfp4/problem-3-gated-dual-gemm.md", "url": "https://github.com/gpu-mode/reference-kernels"}, {"path": "sources/contests/flashinfer-mlsys26/track-a-fused-moe.md", "url": "https://mlsys26.flashinfer.ai/"}, {"path": "sources/blogs/tflops-gap-fp4-moe.md", "url": "https://huggingface.co/blog/apsys/blackwell-nvfp4-comparison"}], "risk_flags": ["code", "ordering"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-gpumode-p3", "contest-flashinfer-track-a", "blog-tflops-gap-fp4-moe"], "title": "Kernel Fusion", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "7d1d16d68cfae0d699d1b73b4d10ac71a12c878966081788134245f3861fc283", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Persistent kernels launch exactly as many CTAs as SMs, and each CTA processes multiple output tiles in a loop rather than exiting after one tile. On Blackwell, the CLC (Cluster Launch Control) hardware unit replaces software-based tile sche", "sha256": "e8e36d68148157b9682fa98efa2b8852c39ba9cadbe075559246b392b8132470"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "The core persistent kernel loop on Blackwell uses CLC to dynamically assign tiles:", "sha256": "d00b8e36858ea1cb03e3865cef79e879712cc9fdee5db36dac678b638b3e155d"}, {"id": "u003", "kind": "code", "locator": "body:L9-L40", "preview": "```cuda // Persistent kernel with CLC tile scheduling (Blackwell SM100) __global__ void __launch_bounds__(512) persistent_gemm_clc(const __grid_constant__ GemmParams params) { // CLC-managed persistent loop: each CTA processes multiple tile", "sha256": "d293d6d2db1df05cb586cfe1acd9fd74c96529152b52571a4c1af3d45b75fcfa"}, {"id": "u004", "kind": "prose", "locator": "body:L42-L44", "preview": "At the PTX level, the CLC interaction is a cancel/query sequence. The exact inline PTX is usually hidden behind CUTLASS/CuTe wrappers, but the control flow looks like this:", "sha256": "c50b1466112dc222ff111f047f558f8b2f03965875f05fbaa0634798860ae028"}, {"id": "u005", "kind": "code", "locator": "body:L46-L58", "preview": "```text TILE_LOOP: // Request cancellation of a not-yet-launched cluster. clusterlaunchcontrol.try_cancel(response_smem, mbarrier) wait(mbarrier) // Query the 16-byte response. has_work, tile_m, tile_n = clusterlaunchcontrol.query_cancel(re", "sha256": "ff3a7192cbac1849c95c96526c779c1ee4d618c1119004540d3b9981d48eb8b1"}, {"id": "u006", "kind": "prose", "locator": "body:L62-L62", "preview": "On Hopper (SM90), persistent kernels use a static stride pattern where each CTA computes tiles at fixed intervals:", "sha256": "2fa4e0e86a85e15db5199b2f2e0db272c22d25417b2cf6e7b01998183b0daed0"}, {"id": "u007", "kind": "code", "locator": "body:L64-L79", "preview": "```cuda // Hopper-style static stride persistent kernel __global__ void hopper_persistent_gemm(GemmParams params) { int cta_id = blockIdx.x; int total_ctas = gridDim.x; int total_tiles = params.num_tiles_m * params.num_tiles_n; // Static st", "sha256": "0132a814c47eadecc7ac6ccb66be30bec3ce8cd8bb57f598647fc9ae9b83a6cb"}, {"id": "u008", "kind": "table-row", "locator": "body:L83-L83", "preview": "| Aspect | Hopper Static Stride | Blackwell CLC | | Scheduling | Software loop with fixed stride | Hardware CLC unit assigns tiles |", "sha256": "8edf2923dc1b0eab7fb68673908bc35e885a360c94f1a6278a402c58ad61a4ea"}, {"id": "u009", "kind": "table-row", "locator": "body:L84-L84", "preview": "| Aspect | Hopper Static Stride | Blackwell CLC | | Load balancing | Fixed; uneven if tile costs vary | Dynamic; CLC rebalances automatically |", "sha256": "81b1b129852e8f5d7fd2c223b68b1ca5a001a72baae445ae9eda2f347283f342"}, {"id": "u010", "kind": "table-row", "locator": "body:L85-L85", "preview": "| Aspect | Hopper Static Stride | Blackwell CLC | | Tail effect | Last wave may have partial occupancy | CLC minimizes by giving fast CTAs more tiles |", "sha256": "943c65b8013de98dd0c46d8e5a9ea57f604182d56cdf69448388f39899a5a630"}, {"id": "u011", "kind": "table-row", "locator": "body:L86-L86", "preview": "| Aspect | Hopper Static Stride | Blackwell CLC | | Launch overhead | Grid launch for each new problem | CLC can chain multiple problems |", "sha256": "fa73cac0250a303e4b09bd5e56d8616d854df6af4146e671eedb970f208185c1"}, {"id": "u012", "kind": "table-row", "locator": "body:L87-L87", "preview": "| Aspect | Hopper Static Stride | Blackwell CLC | | Termination | Implicit when loop ends | Explicit `try_cancel` |", "sha256": "470b1fcdde44684241a2a5dadd6e1fce4d4d5c5c5113ece57c3125740a134981"}, {"id": "u013", "kind": "table-row", "locator": "body:L88-L88", "preview": "| Aspect | Hopper Static Stride | Blackwell CLC | | L2 locality | Depends on stride pattern | CLC can apply swizzled raster |", "sha256": "a4b976af33b07f033e28de4eefce78a628f2044ef95f49e8a6eace5776708174"}, {"id": "u014", "kind": "prose", "locator": "body:L92-L92", "preview": "CUTLASS 4.5.0 provides `PersistentTileSchedulerSm100` that wraps the CLC hardware:", "sha256": "eccbc64b8272087c5b7f1f89b541f6a7601bf14caa10370202fb90f01d223923"}, {"id": "u015", "kind": "code", "locator": "body:L94-L154", "preview": "```cuda // CUTLASS SM100 persistent tile scheduler (simplified) template struct PersistentTileSchedulerSm100 { // Initialize the CLC with the problem geometry CUTLASS_DEVICE static void init( dim3 problem_tiles, void* clc_", "sha256": "8db29837df5850f108e3512819e6486902a381701d4b25ed410be4a555a6c88e"}, {"id": "u016", "kind": "prose", "locator": "body:L158-L158", "preview": "The tcgen05-tutorial progression demonstrates the impact of persistent kernels:", "sha256": "e7e399991855ad8c0005fbc52c2be1c5f1207b74e328ba5f10b19dd3d4bd7316"}, {"id": "u017", "kind": "code", "locator": "body:L160-L163", "preview": "``` Without persistence (static grid): 940 TFLOPS (62% of peak) With CLC persistent scheduling: 1476 TFLOPS (98% of cuBLAS) ```", "sha256": "779f994872a8ba6929fb5083d16acecb183d84150f350b189b00472c58509626"}, {"id": "u018", "kind": "prose", "locator": "body:L165-L165", "preview": "The 57% improvement comes from:", "sha256": "86ad96613390a3e7cba296d569bf4b2e0ea02d7688700dde6f7ce1145e533c10"}, {"id": "u019", "kind": "list-item", "locator": "body:L166-L166", "preview": "1. **Eliminated tail effect**: CLC dynamically assigns tiles, so fast-completing CTAs absorb extra work rather than sitting idle while the last wave finishes.", "sha256": "8cb9710f12f11ba0448af3a7f2e5c40dd0d5e4255942bdc759f98b2dec9c2207"}, {"id": "u020", "kind": "list-item", "locator": "body:L167-L167", "preview": "2. **Reduced launch overhead**: A single kernel launch covers all tiles; no need to re-launch grids.", "sha256": "da95af84a43e0d56d646f339ee0a6e2d4e40ccf5ee4bf0b4813917c6e67680e7"}, {"id": "u021", "kind": "list-item", "locator": "body:L168-L168", "preview": "3. **Better L2 cache utilization**: CLC can apply a swizzled raster pattern that improves spatial locality across neighboring tiles.", "sha256": "0f53e7d0312c5dad03b039b1d89bf425405b0352675f0d5b116c221454c4ef13"}, {"id": "u022", "kind": "list-item", "locator": "body:L172-L172", "preview": "- **Large GEMM problems**: Persistent kernels are most beneficial when the number of output tiles exceeds the SM count by at least 2-3x.", "sha256": "627d205eaaa11d3e3bf243b5d9f079c6961ca143533c59772038c4edc31487c0"}, {"id": "u023", "kind": "list-item", "locator": "body:L173-L173", "preview": "- **Grouped GEMMs / MoE**: CLC can chain multiple problem instances, eliminating inter-kernel launch gaps.", "sha256": "84b5ebee1a8f16e1a5b987ac252c9da1cb6f7790690801f5ddea40085531c868"}, {"id": "u024", "kind": "list-item", "locator": "body:L174-L174", "preview": "- **Workloads with uneven tile cost**: CLC's dynamic scheduling naturally handles variable-cost tiles (e.g., triangular attention masks).", "sha256": "5ede804dd82231ab723c1fcc15adae4561ef761db392b54751eebb1e64205c7a"}, {"id": "u025", "kind": "list-item", "locator": "body:L178-L178", "preview": "- CLC is SM100-only; Hopper kernels must use software-based scheduling.", "sha256": "a1daa43e43efe5d78c2b66c5e743f8fe9d2cff18ff0e1eeca6875f2a3b63a4d2"}, {"id": "u026", "kind": "list-item", "locator": "body:L179-L179", "preview": "- The `try_cancel` pattern introduces a potential race that must be handled with a retry loop.", "sha256": "27ac0a9a9cda1f785a742912aafe5f7c9f6c8477f69e72eb4cfb3ab6cb2f9d34"}, {"id": "u027", "kind": "list-item", "locator": "body:L180-L180", "preview": "- For very small problems (fewer tiles than SMs), CLC overhead may not justify the complexity. A simple single-wave grid launch suffices.", "sha256": "86018b81505700f865cbce903ffda5f76bad6f6620b055c4c4839c9bfad3abb8"}, {"id": "u028", "kind": "prose", "locator": "body:L184-L184", "preview": "Verbatim upstream code lives in [`artifacts/kernels/persistent-kernels/full/`](../../artifacts/kernels/persistent-kernels/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) ", "sha256": "dae6ce03f82e0f9348174a57abd5f8a30fe21a539b0ac794e603406732dabafc"}, {"id": "u029", "kind": "prose", "locator": "body:L186-L186", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u030", "kind": "code", "locator": "body:L188-L190", "preview": "```bash python3 scripts/get_page.py technique-persistent-kernels --include-code ```", "sha256": "ad38aeaa314e4436d6603b855048ed00f795b0832bc4c697a9300dc2c5893567"}], "confidence_claimed": "source-reported", "headings": ["Overview", "CLC Loop Pattern", "Comparison: CLC vs Static Stride (Hopper)", "CUTLASS PersistentTileSchedulerSm100", "Performance Impact", "When to Use", "Caveats", "Full Reference Implementation"], "id": "technique-persistent-kernels", "path": "wiki/techniques/persistent-kernels.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/docs/nvidia-cutlass-blackwell.md", "url": "https://docs.nvidia.com/cutlass/latest/CHANGELOG.html"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "doc-cutlass-blackwell"], "title": "Persistent Kernels with CLC", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "1e86380f8ba7bfb3a8a4c0f9aeaba796da8fef032eca6b4abc5dbacf72564d20", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Ping-pong scheduling alternates two query tiles within a single CTA so the softmax warpgroup never stalls waiting for MMA. Introduced in FlashAttention-4 to exploit Blackwell's asymmetric hardware (2\u00d7 tensor cores, same SFU count as Hopper)", "sha256": "18017e364da96a8b6c710733af3652816685d2d7acff8065b2c1211031714493"}, {"id": "u002", "kind": "code", "locator": "body:L9-L35", "preview": "```cuda // Two 128-token query tiles per CTA, alternating through the mainloop // Warpgroup 0: softmax for tile A while MMA runs on tile B // Warpgroup 1: softmax for tile B while MMA runs on tile A __global__ void fa4_ping_pong_attn(...) {", "sha256": "8499e0fdd764e721b32d8078a983f064bf167a0e53fd027cda13d9cb18c80438"}, {"id": "u003", "kind": "list-item", "locator": "body:L39-L39", "preview": "- Tensor core throughput doubled (B200 vs H100) but SFU count unchanged", "sha256": "0a46ee52bba3c57ee8905ac1dd50c402869daff94fb8d5d44cbe9342220c1c20"}, {"id": "u004", "kind": "list-item", "locator": "body:L40-L40", "preview": "- Single-tile schedule would leave SFU idle while MMA runs, and vice versa", "sha256": "a2d9a909cc8c0ab7538af1c1254a9115a8d0ea0a8f77b1998f0a2af19f4529df"}, {"id": "u005", "kind": "list-item", "locator": "body:L41-L41", "preview": "- Ping-pong keeps both units 100% busy", "sha256": "f08543a636554e0e7512cf8b70653642414461f288e043bbc48d4248ae8d833a"}, {"id": "u006", "kind": "list-item", "locator": "body:L42-L42", "preview": "- FA4 achieves 1605 TFLOPS BF16 (71% utilization) with this pattern", "sha256": "9e4b6969c16376c6419faf7861ff0bc4701f4576f67ffb0baaa4a541e09e7250"}, {"id": "u007", "kind": "list-item", "locator": "body:L46-L46", "preview": "- Compute-bound attention kernels on Blackwell", "sha256": "4c6cf49898eb794803dc3516455cd225fda03a58d5789fe7d9f558e6a99f3f9c"}, {"id": "u008", "kind": "list-item", "locator": "body:L47-L47", "preview": "- Kernels where softmax/epilogue is SFU-heavy", "sha256": "1703c48c4e416896eaaed17a937e8fcb95843e111beca19257da1483781a03b3"}, {"id": "u009", "kind": "list-item", "locator": "body:L48-L48", "preview": "- Not useful on Hopper (balance is different)", "sha256": "9738e0176814d096ab8c4872e52db170c64347109cc167477fb15edbf1830095"}, {"id": "u010", "kind": "prose", "locator": "body:L52-L52", "preview": "Verbatim upstream code lives in [`artifacts/kernels/ping-pong-scheduling/full/`](../../artifacts/kernels/ping-pong-scheduling/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` head", "sha256": "42846bee13f84639175b92a183fb0becf7f05f6c9a793e519973597b26af7006"}, {"id": "u011", "kind": "prose", "locator": "body:L54-L54", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u012", "kind": "code", "locator": "body:L56-L58", "preview": "```bash python3 scripts/get_page.py technique-ping-pong-scheduling --include-code ```", "sha256": "5e4fb2a38570963673bb5efeb1ad1c9d48bb10b940a9dd8dc6534e549d5c0fbc"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Pattern", "Why It Helps on Blackwell", "When To Use", "Full Reference Implementation"], "id": "technique-ping-pong-scheduling", "path": "wiki/techniques/ping-pong-scheduling.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/flash-attention-4.md", "url": "https://tridao.me/blog/2026/flash4/"}, {"path": "sources/docs/flash-attention-4.md", "url": "https://arxiv.org/abs/2603.05451"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}], "risk_flags": ["code"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-flash-attention-4", "doc-flash-attention-4", "blog-tcgen05-tutorial"], "title": "Ping-Pong Scheduling", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "d990987f96b0c765ab7753798f189a2125cbab0619c1671b450e305a4c628966", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Software pipelining overlaps data loading (TMA copies from global to shared memory) with computation (tcgen05.mma or wgmma) by maintaining multiple in-flight tile buffers. A circular buffer of 3-5 stages allows the TMA producer to fill stag", "sha256": "6c9314211ed0931aa6ca230a23ffde47272c800d7260735c177b32239a6c19fb"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "The tcgen05-tutorial demonstrates the performance impact of pipelining:", "sha256": "32d64417f35a0af386685bffccdf887d9b1ec91318b42c992a3a6fdc962aa943"}, {"id": "u003", "kind": "code", "locator": "body:L9-L13", "preview": "``` No pipelining (load, then compute): 695 TFLOPS (46%) 3-stage pipeline (TMA + MMA overlap): 940 TFLOPS (62%) + warp specialization: 1476 TFLOPS (98%) ```", "sha256": "964e3061ea3896a9894f13629a043dcb9dabaa7ab4bd9c735faa2b100733571a"}, {"id": "u004", "kind": "prose", "locator": "body:L15-L15", "preview": "The 35% improvement from pipelining alone (695 to 940 TFLOPS) comes from hiding global memory latency behind MMA computation.", "sha256": "933f3ac4fc131a0771c0bf278426040e94e94e64bb7a47c5267f66388b2e01f3"}, {"id": "u005", "kind": "prose", "locator": "body:L19-L19", "preview": "The fundamental pattern allocates `NUM_STAGES` copies of each SMEM buffer and cycles through them:", "sha256": "472983f5e9b59df349b80d12cbfb19ec1eb6d3ac98b1b715d418462fb0288e07"}, {"id": "u006", "kind": "code", "locator": "body:L21-L110", "preview": "```cuda // 3-stage circular buffer with mbarrier synchronization // Stages: [0] loading, [1] ready for MMA, [2] being consumed by MMA #define NUM_STAGES 3 __global__ void __launch_bounds__(512) pipelined_gemm(const __grid_constant__ GemmPar", "sha256": "9c4857b6c3bc136a10acb067785e356592410c227ef8e38a3275cc0718d38ad7"}, {"id": "u007", "kind": "prose", "locator": "body:L114-L114", "preview": "The optimal number of pipeline stages depends on the ratio of memory latency to compute time per tile:", "sha256": "c771eeac340fd324a834e01623d2622fc10179586cda8d27cc4afa755c64111c"}, {"id": "u008", "kind": "table-row", "locator": "body:L118-L118", "preview": "| Stages | SMEM Usage | Latency Hiding | Best For | | 2 | 2x base | Partial | Small tiles, limited SMEM |", "sha256": "2f0fdedf15dcc2f91d98558670aeb908d3ab4b50dfdffeb42a63bb3bb5db36b0"}, {"id": "u009", "kind": "table-row", "locator": "body:L119-L119", "preview": "| Stages | SMEM Usage | Latency Hiding | Best For | | 3 | 3x base | Full for most GEMMs | Standard choice on Blackwell |", "sha256": "37ce4b2f1509ff5519e008b1bb225294aced130706fdd90911201e0abbaced76"}, {"id": "u010", "kind": "table-row", "locator": "body:L120-L120", "preview": "| Stages | SMEM Usage | Latency Hiding | Best For | | 4-5 | 4-5x base | Full with margin | Large K, high memory latency |", "sha256": "d1a052bf98acfaac91757adad9b0beb651c0b0b2d0f5723a479b024c3a20dac7"}, {"id": "u011", "kind": "table-row", "locator": "body:L121-L121", "preview": "| Stages | SMEM Usage | Latency Hiding | Best For | | >5 | Excessive | Diminishing returns | Rarely justified |", "sha256": "a552c9fee13a0315c5f3f5dd0123b3f2613c449ade64502a9fa75f110bd9fa9a"}, {"id": "u012", "kind": "prose", "locator": "body:L123-L123", "preview": "The SMEM budget on Blackwell is 228 KB per SM. For a BF16 GEMM with TILE_M=128, TILE_N=256, TILE_K=64:", "sha256": "26344b17c2315629889de2844b3c6707ba92c8e363c6d1e03c447dca260d1ce8"}, {"id": "u013", "kind": "list-item", "locator": "body:L124-L124", "preview": "- A tile: 128 x 64 x 2B = 16 KB", "sha256": "03e4c1bf2be972a87f1a0735f4dfc980a930b5f6c7fb0a86119a2159008c713b"}, {"id": "u014", "kind": "list-item", "locator": "body:L125-L125", "preview": "- B tile: 64 x 256 x 2B = 32 KB", "sha256": "eb7f61ed161a3cecb248d9d96a0edc35c452ff2e0bd16e08bd3a6dd924a1eaca"}, {"id": "u015", "kind": "list-item", "locator": "body:L126-L126", "preview": "- Per stage: 48 KB", "sha256": "d950f9ecb5785f4374387ec03ada37cbd812dd06d48cf81892b50ef2360098f1"}, {"id": "u016", "kind": "list-item", "locator": "body:L127-L127", "preview": "- 3 stages: 144 KB (63% of SMEM, leaves room for barriers and epilogue)", "sha256": "06f710fddfa9c0558c9da66757b2546af1d863d17ca3e1d18f5f9d16194f37f2"}, {"id": "u017", "kind": "list-item", "locator": "body:L128-L128", "preview": "- 5 stages: 240 KB (exceeds SMEM capacity; must use smaller tiles)", "sha256": "d377ce7cb994882e900ecfeb866422da4e28287925375571fdef1f414de98e7b"}, {"id": "u018", "kind": "prose", "locator": "body:L132-L132", "preview": "The mbarrier (memory barrier) is the hardware primitive that makes pipelining efficient. Unlike `__syncthreads()`, mbarrier supports asymmetric producer-consumer synchronization where only the relevant warp participates:", "sha256": "8f9ebd31babfc22fd14e2d0430c0181ab305c38c8d95805026f53bec768cabe7"}, {"id": "u019", "kind": "code", "locator": "body:L134-L153", "preview": "```ptx // Phase-based mbarrier protocol for 3-stage pipeline // // Each mbarrier tracks a \"phase\" (0 or 1). The producer flips the phase // on arrive; the consumer waits for the expected phase. // Producer: arrive on stage %s (flips phase) ", "sha256": "753799262915aff51c7d8b6cec86568acc234eed75fc38d91988899f416253f7"}, {"id": "u020", "kind": "prose", "locator": "body:L155-L155", "preview": "The key advantage is that TMA can arrive on an mbarrier autonomously. The producer warp only needs to initiate the TMA; the TMA hardware signals completion directly, removing the producer from the critical path.", "sha256": "553cb5fbfedd97caa8bbd5a6661ae1ac581f7968fc5c2261258b256e6fe2e270"}, {"id": "u021", "kind": "prose", "locator": "body:L159-L159", "preview": "The Modular blog series describes a 5-stage circular buffer reaching 85% of SOTA performance on Blackwell:", "sha256": "189b0ac34a4da5e1dcb0a67f05722472781ce9c486c9b3effeec3d0d3e59da1a"}, {"id": "u022", "kind": "code", "locator": "body:L161-L181", "preview": "```cuda // Modular-style 5-stage pipeline constants // Chosen to fully hide B200 HBM latency (~400 cycles) // while fitting within 228 KB SMEM budget constexpr int NUM_STAGES = 5; constexpr int TILE_M = 128; constexpr int TILE_N = 128; // S", "sha256": "3c1661c7453ab8871b622a57668d830fb30debf05921973ebdd4e5ed988a30b2"}, {"id": "u023", "kind": "list-item", "locator": "body:L185-L185", "preview": "- **All memory-bound and compute-bound GEMM kernels**: Pipelining is never harmful and always improves utilization by hiding latency.", "sha256": "b0d1156c0820474c04afb80ad6045c8c66f1a0a9a74f4eaf4bc22e42d7125180"}, {"id": "u024", "kind": "list-item", "locator": "body:L186-L186", "preview": "- **Attention kernels**: The K-dimension loop in attention benefits from pipelining the KV tile loads.", "sha256": "5dde7afc71b1ce71e3ad7acf1e599cecded4cdd43e4d215d2c3e1399f11cae25"}, {"id": "u025", "kind": "list-item", "locator": "body:L187-L187", "preview": "- **Combined with warp specialization**: Pipelining provides the buffer structure; warp specialization assigns the producer/consumer roles. The two techniques are complementary and almost always used together.", "sha256": "8f89ca68aa97c882f9cdd9da5b1761404890c80106fc2e61e8582f4f1231f1b3"}, {"id": "u026", "kind": "list-item", "locator": "body:L191-L191", "preview": "- More stages increase SMEM usage linearly. On Blackwell's fixed 228 KB, this constrains tile size choices.", "sha256": "141f8982deb09e3a091950e50265643f2f7231205efbfe8306dfff8aa19d69db"}, {"id": "u027", "kind": "list-item", "locator": "body:L192-L192", "preview": "- Barrier initialization overhead is negligible but must happen before the first TMA. Place init in a `__syncthreads()` block at kernel start.", "sha256": "d9cf29d158136f7851959b3609b7e77d38f8730a25bc2dfb01bcf1b226925163"}, {"id": "u028", "kind": "list-item", "locator": "body:L193-L193", "preview": "- Incorrect phase tracking in mbarrier causes deadlocks. The phase alternates with each arrive/wait cycle; off-by-one errors are common during development.", "sha256": "dd4a84772ccc0b59c5522f88fd48f5fa96d0b138c4620c15632029c4dc557e0e"}, {"id": "u029", "kind": "list-item", "locator": "body:L194-L194", "preview": "- For very short K dimensions (fewer iterations than stages), the prologue/epilogue overhead may dominate. Guard the loop bounds accordingly.", "sha256": "493e18b170790a00c2b49d45839d2ae22e745c4937771d716173175169fcb1a5"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Pipeline Progression", "Multi-Stage Circular Buffer Pattern", "Stage Count Selection", "mbarrier-Based Synchronization", "Modular's 5-Stage Implementation", "When to Use", "Caveats"], "id": "technique-pipeline-stages", "path": "wiki/techniques/pipeline-stages.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/blogs/modular-blackwell-matmul.md", "url": "https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-1-introduction"}, {"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-tcgen05-tutorial", "blog-modular-blackwell", "doc-nvidia-tuning-guide"], "title": "Software Pipelining and Multi-Stage Buffering", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "e4490d9c41b459fa167d4dbc32f8814b4ebe1e7579297a6074df53a54b51509d", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "SM occupancy is inversely proportional to registers-per-thread. For memory-bound kernels, higher occupancy = more warps to hide memory latency. `-maxrregcount` and `__launch_bounds__` force the compiler to stay within a budget.", "sha256": "67ae743e543e32b842dcbbdc7ae5a7aece11274737bf3cdf6678eed799d1e7d4"}, {"id": "u002", "kind": "code", "locator": "body:L9-L18", "preview": "```cuda // Aggressive: 32 registers/thread \u2192 ~4 blocks per SM at 256 threads/block __launch_bounds__(256, 4) __global__ void gemv_memory_bound(...) { // Compiler will spill to local memory if needed } // Or via nvcc flag: // nvcc -maxrregco", "sha256": "db5b11ddbac6e4a85435c76881aea10ba8e2b316f86bee7435bfbbdd65dcd53a"}, {"id": "u003", "kind": "prose", "locator": "body:L22-L22", "preview": "Lower register count \u2192 compiler may:", "sha256": "11ad74cd2da10c7b3d5a764102b705c7b560777b634534349c6295d5f85795b0"}, {"id": "u004", "kind": "list-item", "locator": "body:L23-L23", "preview": "- Spill frequently-used values to local memory (bad)", "sha256": "7a9f2905849808b299160d6c1a5bce7688bb6971f536bc4a0d4042640226f177"}, {"id": "u005", "kind": "list-item", "locator": "body:L24-L24", "preview": "- Recompute values instead of storing them (neutral)", "sha256": "8ff03c2a5624d0d0abf4f53c1d910a49b3e0830d5a55e2e171aaf50a269b82d3"}, {"id": "u006", "kind": "list-item", "locator": "body:L25-L25", "preview": "- Use fewer unrolled iterations (bad for compute-bound)", "sha256": "6fc7eafbc44729c7b59f3f60c3b472271570c1d23d033321f5581d4b8fb2df53"}, {"id": "u007", "kind": "prose", "locator": "body:L27-L27", "preview": "For memory-bound kernels, spills can be hidden by memory latency anyway, so aggressive budgeting often wins.", "sha256": "0839dfa5de845b156842d8f387f3fd2c8e1555c8bbc6bb8a6352a4644e1b5cc3"}, {"id": "u008", "kind": "table-row", "locator": "body:L33-L33", "preview": "| Rank | Register count | Latency | | 1 | 32 | 18.5\u03bcs |", "sha256": "62bacbbb02ae292e554ef4aa539388bd98437885f5dcebac212e670d419552b2"}, {"id": "u009", "kind": "table-row", "locator": "body:L34-L34", "preview": "| Rank | Register count | Latency | | 3 | 45 | ~20\u03bcs |", "sha256": "f42a56f99577616f7ee66c57adeed5333f5fbff5726a02265ba8de5a29a1187f"}, {"id": "u010", "kind": "prose", "locator": "body:L36-L36", "preview": "The measurable difference between 32 and 45 registers shows occupancy dominates for memory-bound NVFP4 GEMV.", "sha256": "01442dfeda5750db249c3f7cc5ce69ff7e3a35f16ade2f62fbe5e60fab555b89"}, {"id": "u011", "kind": "list-item", "locator": "body:L40-L40", "preview": "- Memory-bound kernels (first priority: occupancy)", "sha256": "547d06454ed352af323da04581bce57b5aa173c445cc256e3d94abecf6f19129"}, {"id": "u012", "kind": "list-item", "locator": "body:L41-L41", "preview": "- Kernels where register pressure comes from inner loop, not accumulators (TMEM handles accumulators)", "sha256": "4d30d905715e06de17252aa7ab5727305e7acaa536959942d63f77568765013f"}, {"id": "u013", "kind": "list-item", "locator": "body:L42-L42", "preview": "- Sub-byte types with heavy decode/scale computation", "sha256": "e475f3a0ae449c4c6e857ce007229d9737c9cf61cb90021bfb55adec8b49ad44"}, {"id": "u014", "kind": "list-item", "locator": "body:L46-L46", "preview": "- Compute-bound GEMM (let compiler use what it needs)", "sha256": "e79015ad25c9bfd96722f7d12a1c02a51313378d798b52a6c8ea6ecaf3a350f8"}, {"id": "u015", "kind": "list-item", "locator": "body:L47-L47", "preview": "- Kernels where spills to local memory would serialize", "sha256": "1c0b02e78a49584102478c62648ca569e842b58c7cd88304cf9a18af707d6482"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Pattern", "Compiler Tradeoffs", "GPU Mode NVFP4 GEMV Results", "When To Use", "When NOT To Use"], "id": "technique-register-budgeting", "path": "wiki/techniques/register-budgeting.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/yue-nvfp4-hackathon.md", "url": "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"}, {"path": "sources/blogs/amandeep-nvfp4-attempts.md", "url": "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"}, {"path": "sources/blogs/simon-nvfp4-gemv.md", "url": "https://veitner.bearblog.dev/nvfp4-gemv/"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-yue-nvfp4", "blog-amandeep-nvfp4", "blog-simon-nvfp4-gemv"], "title": "Register Budgeting for Occupancy", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "fe120348335fa0ecedde2247d6fed5fe7262c22730cfed75ee48ee931de7d730", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "FlashAttention-4 replaces the hardware Special Function Unit (SFU) exponential (`ex2.approx`) with a software-emulated 2^x function that distributes computation across the SM's FMA (fused multiply-add) units. On Blackwell, tensor core throu", "sha256": "6efea6d4e42f7e8cdd53b28ea0dc4fcccbec71d6ac2266f77b0764bde6159877"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "The softmax in attention requires computing `exp(x - max)` for every element of the score matrix. On previous generations, the SFU's `ex2.approx` instruction was fast enough relative to the MMA throughput. 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This makes the SFU the bottleneck for any kernel that needs exp() proportional to the number of MMA outputs.", "sha256": "6c0ff0b8e3ebbe638d1a81413e2a5b738900d5187b8649f1fb383cfcc8153957"}, {"id": "u008", "kind": "prose", "locator": "body:L18-L18", "preview": "FlashAttention-4's approach: distribute the exp() workload across FMA units (128 per SM) instead of SFU units (16 per SM), achieving 8x the throughput for the exponential computation.", "sha256": "821c1dc38e821d7c576e6d3540000fea3a2b5565269e09e6c7a2985842b2e6e1"}, {"id": "u009", "kind": "prose", "locator": "body:L22-L22", "preview": "Range reduction transforms the input `x` into a small residual that a polynomial can accurately approximate. The Cody-Waite method splits the input into an integer part (for exact power-of-two scaling) and a fractional part (for polynomial ", "sha256": "633087d1dc66c31d1adf9037ae75107783ee2945a41e6305e424381906abd8fc"}, {"id": "u010", "kind": "code", "locator": "body:L24-L72", "preview": "```cuda // Cody-Waite range reduction for 2^x // Goal: decompose x = n + r where n is integer, r in [-0.5, 0.5] // Then 2^x = 2^n * 2^r, and 2^r is approximated by polynomial // // The Cody-Waite trick: subtract n using two constants (C1 + ", "sha256": "bd8a3e83f91a2a5c61614813d88f04fd4ba5fc3a1db24bf0f17c4796f2702cc8"}, {"id": "u011", "kind": "prose", "locator": "body:L76-L76", "preview": "The key insight is that Horner polynomial evaluation is a chain of FMA operations. With the softmax warp executing on CUDA cores while the MMA warp uses tensor cores, the FMA throughput is fully available:", "sha256": "d7f7e14b21782d574264840122b9f970dca4b6ef92658c900054c304a22b6549"}, {"id": "u012", "kind": "code", "locator": "body:L78-L138", "preview": "```cuda // FlashAttention-4 softmax with software exp2 // Executed by dedicated softmax warpgroups (part of warp specialization) // // For each row of the score matrix S[i,:]: // 1. Find row max: m_new = max(S[i,:]) // 2. Compute exp2((S[i,", "sha256": "2ed7a87e1fe2f843cee953b304ed2188f598b02ba9e94d641d8a0aa4386d9b6a"}, {"id": "u013", "kind": "prose", "locator": "body:L142-L142", "preview": "At the PTX level, the Horner polynomial compiles to a tight chain of `fma.rn.f32` instructions:", "sha256": "9bc0f5d7707c8a74c367f53b64416533669196b77d73068c31e872864f41e2df"}, {"id": "u014", "kind": "code", "locator": "body:L144-L180", "preview": "```ptx // Software exp2 via Horner polynomial in PTX // Input: %x (float, range-reduced to [-0.5, 0.5]) // Output: %result (float, approximation of 2^x) .reg .f32 %x, %r, %n, %poly, %result; .reg .f32 %c0, %c1, %c2, %c3, %c4; // Load polyno", "sha256": "79c7f9dc0cee373816a8a7709811ff39f1afc7010f2ee69280e2a528d8c0b784"}, {"id": "u015", "kind": "prose", "locator": "body:L184-L184", "preview": "The degree-4 polynomial provides approximately 22 bits of mantissa accuracy, which is more than sufficient for attention softmax where:", "sha256": "62433718aa2ed86f2672dfb451ed94f8c87ed0cd15ad53422368b91b254b3023"}, {"id": "u016", "kind": "list-item", "locator": "body:L185-L185", "preview": "- The input `x = (S[i,j] - max) * log2(e)` is always non-positive", "sha256": "3de1a0b8c93fcf05cd3c78d9afd2c546a9052098de4861c57d93c69c9b0c0413"}, {"id": "u017", "kind": "list-item", "locator": "body:L186-L186", "preview": "- The softmax output is normalized, so small absolute errors cancel out", "sha256": "af0ab0506229e520469fff8587d92d782795db9122770def9d8bd3919af0e289"}, {"id": "u018", "kind": "list-item", "locator": "body:L187-L187", "preview": "- BF16 output has only 7 mantissa bits anyway", "sha256": "5ff084b9eee350189aa486b28390455179407f420ac4365a3ea5ea7a216384c4"}, {"id": "u019", "kind": "prose", "locator": "body:L189-L189", "preview": "For applications requiring higher accuracy, a degree-6 polynomial (6 FMAs) achieves near-ULP accuracy across the full float range.", "sha256": "b7af80bcb683a569e2b6eef6b48a7d9ffd780208484235187f1a109e9ba08aec"}, {"id": "u020", "kind": "list-item", "locator": "body:L193-L193", "preview": "- **Attention kernels on Blackwell**: Whenever the SFU is the bottleneck for softmax computation. FlashAttention-4 measured 1.1-1.3x speedup over cuDNN from this technique alone on B200.", "sha256": "f181239242e97a4927887d4bbca60792ef68ef84bf5024fa625537e2be2cf192"}, {"id": "u021", "kind": "list-item", "locator": "body:L194-L194", "preview": "- **Any kernel limited by transcendental function throughput**: If profiling shows SFU utilization near 100% while FMA utilization is low, software emulation can rebalance the workload.", "sha256": "f20a967006ba5bbd86ac800ab093a2e5635bd0c3ac50ef4b244a14147e2c3f92"}, {"id": "u022", "kind": "list-item", "locator": "body:L195-L195", "preview": "- **Not recommended on Hopper**: The SFU-to-MMA throughput ratio is better balanced on SM90. The overhead of 4 FMAs vs 1 SFU instruction is not justified unless the SFU is proven to be the bottleneck.", "sha256": "8b730ecee723f4ce482d528fb2f265e0d3e1cc54055efc75b378c468651d026f"}, {"id": "u023", "kind": "list-item", "locator": "body:L199-L199", "preview": "- The 4-FMA chain has a latency of ~16 cycles (4 dependent FMAs at ~4 cycles each), vs ~20 cycles for SFU `ex2.approx`. Latency is comparable; the win comes from throughput (128 FMA units vs 16 SFU units).", "sha256": "1846dbd0de4c200552ae62a81c178b4ddc90e50a7f7b4e44b0b9383311d5fa56"}, {"id": "u024", "kind": "list-item", "locator": "body:L200-L200", "preview": "- Polynomial coefficients are for 2^x on [-0.5, 0.5]. For e^x, multiply the input by log2(e) first.", "sha256": "c0d641147cf3962f8e8583469c3eda934ebde43888727de8d55ca4181e35f10d"}, {"id": "u025", "kind": "list-item", "locator": "body:L201-L201", "preview": "- The `ldexpf` or exponent bit-manipulation step for 2^n must handle overflow/underflow (very large/small x). In attention, `x <= 0` always holds, so only underflow toward zero is possible.", "sha256": "2df5e207ad969e1d3e58d0985bf577b7d6726780320679f1ee18c654891bbc57"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Why SFU Is a Bottleneck on Blackwell", "Cody-Waite Range Reduction", "Distributing Across FMA Units", "PTX-Level FMA Chain", "Accuracy Considerations", "When to Use", "Caveats"], "id": "technique-software-exp", "path": "wiki/techniques/software-exp.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/flash-attention-4.md", "url": "https://tridao.me/blog/2026/flash4/"}, {"path": "sources/docs/flash-attention-4.md", "url": "https://arxiv.org/abs/2603.05451"}, {"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/parallel-thread-execution/"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-flash-attention-4", "doc-flash-attention-4", "doc-ptx-isa-sm100"], "title": "Software-Emulated Exponential", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "c716117a080b9689b2eecbf26c4f0bf1801704ef00fd83627b3f229789716aa5", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Shared memory swizzling remaps the linear address layout of a matrix tile in SMEM so that threads accessing consecutive columns (or rows) hit different 32-byte banks rather than the same bank. This eliminates bank conflicts that would other", "sha256": "ce99151372d234814f71d9a9711aafefb33296a470ed6ae9e0b10716f22f687b"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "Shared memory has 32 banks, each 4 bytes wide (128 bytes total per bank cycle). When a warp accesses a matrix stored in row-major layout, threads in the same warp reading elements from consecutive rows in the same column hit the same bank, ", "sha256": "f0e2e1786678febcb5d3cb2b4810b1d08cc393f1df102523b144e494ea536697"}, {"id": "u003", "kind": "prose", "locator": "body:L9-L9", "preview": "The TMA unit on both Hopper and Blackwell encodes the swizzle pattern as part of the tensor descriptor. The tcgen05.mma instruction expects its SMEM operands to already be swizzled in the 128-byte pattern. Using unswizzled data produces inc", "sha256": "0cfa048d16c8b9f5d1310a1bd02a15652d7c0ecbee7a6dc0345068f60b691a60"}, {"id": "u004", "kind": "prose", "locator": "body:L11-L11", "preview": "The tcgen05-tutorial benchmark progression shows the impact:", "sha256": "cb2babf9d8d4a1ce28deba4b75660e511755cc47a370c94a16cc2a83b2f8d791"}, {"id": "u005", "kind": "code", "locator": "body:L13-L17", "preview": "``` Naive (no swizzle): 255 TFLOPS (17% of cuBLAS) 128B swizzle applied: 695 TFLOPS (46% of cuBLAS) ---- 2.7x improvement from swizzling alone ---- ```", "sha256": "5aa6af3d28f5bb234a6579062ff89314b2c4da13e594601bbf37ae2b09b29110"}, {"id": "u006", "kind": "prose", "locator": "body:L21-L21", "preview": "The swizzle function XORs a portion of the column address with the row address to scatter accesses across banks:", "sha256": "b0c1f36b98b1f0f05a9cf02b53eadcfb80e11dfe7d8b5ef9e0050d1e62c206f1"}, {"id": "u007", "kind": "code", "locator": "body:L23-L41", "preview": "```cuda // 128-byte swizzle: XOR bits [4:6] of the byte offset with the row index // This ensures that consecutive rows accessing the same logical column // map to different physical SMEM banks. // // For a tile stored in SMEM with TILE_N c", "sha256": "b10f33bcd229a8f43b11a7e498a38c2a7b0f0e4536e63c115006d41e672dbdb7"}, {"id": "u008", "kind": "prose", "locator": "body:L43-L43", "preview": "Visually, for an 8-row x 64-column half-precision tile (128 bytes per row):", "sha256": "06b2de8a095c86b5cae33559f34774ca6160eec20c1b2651c1a7cfe429d9e513"}, {"id": "u009", "kind": "code", "locator": "body:L45-L57", "preview": "``` Without swizzle (row-major): Row 0: bank 0,1,2,...,31 bank 0,1,2,...,31 Row 1: bank 0,1,2,...,31 bank 0,1,2,...,31 Row 2: bank 0,1,2,...,31 bank 0,1,2,...,31 -> Column access = 8-way bank conflict With 128B swizzle (XOR pattern): Row 0:", "sha256": "e68e85063e54eff1f4031a349d08615e7fe95f030e84e90f3e2447eb0bac50d8"}, {"id": "u010", "kind": "prose", "locator": "body:L61-L61", "preview": "The TMA descriptor encodes the swizzle mode when creating a tensor map. The swizzle mode must match what the consumer (tcgen05.mma or wgmma) expects:", "sha256": "08279d3f63c75a2a1be3d839a3721cba648ece95a450cde320488852c9f97bd4"}, {"id": "u011", "kind": "code", "locator": "body:L63-L86", "preview": "```cuda // Creating a TMA descriptor with 128-byte swizzle #include CUtensorMap tensor_map; // Swizzle mode: CU_TENSOR_MAP_SWIZZLE_128B // This tells TMA to apply the 128-byte XOR swizzle pattern // when writing data into shared me", "sha256": "d54572e96082b2eea88d4fd5d043ae610bc781dd1686413d197443494f72d38a"}, {"id": "u012", "kind": "prose", "locator": "body:L88-L88", "preview": "The available swizzle modes and their use cases:", "sha256": "dcec19581b3d9089e67314c4c76049ebd0eac7e2512e2f29bcc181ebc22df456"}, {"id": "u013", "kind": "table-row", "locator": "body:L92-L92", "preview": "| Swizzle Mode | Bank Spread | Use Case | | `SWIZZLE_NONE` | No remapping | Non-MMA data (flags, scales) |", "sha256": "27c9fce11425f0d49b426f0884c0aaf174981b87a3e563c5638952f775563be1"}, {"id": "u014", "kind": "table-row", "locator": "body:L93-L93", "preview": "| Swizzle Mode | Bank Spread | Use Case | | `SWIZZLE_32B` | 32-byte groups | Narrow tiles, small data types |", "sha256": "0db4fbbe37adcb74a561c1ecccccbed7a3c70e63f2eb9899365cee584c1e0e4f"}, {"id": "u015", "kind": "table-row", "locator": "body:L94-L94", "preview": "| Swizzle Mode | Bank Spread | Use Case | | `SWIZZLE_64B` | 64-byte groups | Medium tiles |", "sha256": "aef89dcf631253e2b0931f818788f6612ae9bdf85b81cd397831699928875fd8"}, {"id": "u016", "kind": "table-row", "locator": "body:L95-L95", "preview": "| Swizzle Mode | Bank Spread | Use Case | | `SWIZZLE_128B` | 128-byte groups | Standard for BF16/FP16 MMA operands |", "sha256": "d80118b59d93c6d3c1403aa834ef25ca4676ac416e89baf2f2d183569d8b12d8"}, {"id": "u017", "kind": "prose", "locator": "body:L99-L99", "preview": "In CuTe/CUTLASS, swizzle is expressed as a layout composition:", "sha256": "5228fc07b661976963d244128708dcc8b78e60965647385ddf8f9454c49a6a6d"}, {"id": "u018", "kind": "code", "locator": "body:L101-L125", "preview": "```cuda // CuTe swizzle layout for 128-byte swizzle pattern // Swizzle where: // B = number of bits in the base (non-swizzled) portion // M = number of bits in the mask // S = shift amount // // Swizzle<3, 4, 3> encodes the 128B sw", "sha256": "350890c75c6bcc0cffbffc21e9db0e0ba138f89f6632df719bdd73743a597551"}, {"id": "u019", "kind": "prose", "locator": "body:L129-L129", "preview": "Use `nvprof` or Nsight Compute to verify that swizzling eliminates conflicts:", "sha256": "17f65294789a5a4187c26c3cd1c129b6b8867e099f77babfddadacd5c64b2ba6"}, {"id": "u020", "kind": "code", "locator": "body:L131-L140", "preview": "```python # Nsight Compute command to check shared memory bank conflicts # Look for \"Shared Memory Bank Conflicts\" metric # ncu --metrics l1tex__data_bank_conflicts_pipe_lsu_mem_shared_op_ld.sum \\ # ./my_kernel # Expected results: # Without", "sha256": "32a8e919c354d73f26102c99ccbbe88aa291c78cd59ec3a78ebbe66d7a0b32b6"}, {"id": "u021", "kind": "list-item", "locator": "body:L144-L144", "preview": "- **All Blackwell tensor core kernels**: 128-byte swizzling is not optional. Both TMA and tcgen05.mma require it for correct results and peak performance.", "sha256": "dcd7351c07484bb5d4e9f8673f70c8b3d7c1c4d3f10f92c4ee1b1a8548f6988f"}, {"id": "u022", "kind": "list-item", "locator": "body:L145-L145", "preview": "- **Hopper wgmma kernels**: Same requirement applies; wgmma expects swizzled SMEM operands.", "sha256": "fe233e5729b7851ca56fc490d6d42a1b2b0563e6dff9cbcc42422347c1ad9575"}, {"id": "u023", "kind": "list-item", "locator": "body:L146-L146", "preview": "- **Non-MMA shared memory access**: If multiple warps access the same SMEM tile in a column pattern (e.g., reduction), swizzling prevents serialization.", "sha256": "be0c3938f3fbc4911b1d36410b1b0fd4d844a9a2d4a99aeabcbbf8c341737950"}, {"id": "u024", "kind": "list-item", "locator": "body:L150-L150", "preview": "- The swizzle mode in the TMA descriptor must exactly match the access pattern of the consumer. A mismatch produces silently incorrect results, not a runtime error.", "sha256": "1403a7e149a0c1d6d4110031388e19fafef45c133a4dc7ad76a882cead6b8503"}, {"id": "u025", "kind": "list-item", "locator": "body:L151-L151", "preview": "- Swizzled layouts make SMEM address computation non-trivial. Using CuTe's layout algebra avoids manual indexing errors.", "sha256": "8360684428419eafab8d025fe8b763292ea0b3ff29e403397051ee56cf2e2860"}, {"id": "u026", "kind": "list-item", "locator": "body:L152-L152", "preview": "- For data types wider than 2 bytes (e.g., FP32 accumulators), the optimal swizzle mode may differ. TMEM accumulators avoid this issue since they use a separate address space.", "sha256": "f791bc3efe12801de06fd14c1aeddd480b8b5d43292e75cbb2238558f2587bb3"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Why 128-Byte Swizzling is Mandatory on Blackwell", "How 128-Byte Swizzling Works", "TMA Swizzle Encoding", "CuTe Swizzle Layout", "Verification: Detecting Bank Conflicts", "When to Use", "Caveats"], "id": "technique-swizzling", "path": "wiki/techniques/swizzling.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/blogs/modular-blackwell-matmul.md", "url": "https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-1-introduction"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "blog-modular-blackwell"], "title": "Shared Memory Swizzling", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "b8004e09034567bbd556d5cae14856d176cfa350af0214bb99c9aade49312f32", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Tile scheduling determines the order in which output tiles of a GEMM (or attention) kernel are assigned to CTAs. The scheduling order affects L2 cache hit rates, tail-effect severity, and overall GPU utilization. On Blackwell, the CLC hardw", "sha256": "28c4c95e79e9006fab01b0a85d22ad81bde94be4359b4f99962b217c2a5a61b8"}, {"id": "u002", "kind": "prose", "locator": "body:L9-L9", "preview": "Tiles are assigned in row-major order. Simple but poor L2 locality: consecutive tiles share no B-matrix data until the entire M-dimension is traversed.", "sha256": "71e74696731e08922084e763bc9f5c1dbf80002e8619bb58afd3b05fa38ff9e3"}, {"id": "u003", "kind": "code", "locator": "body:L11-L27", "preview": "```cuda // Linear raster: tile_idx maps directly to (tile_m, tile_n) __device__ void linear_raster(int tile_idx, int tiles_n, int& tile_m, int& tile_n) { tile_m = tile_idx / tiles_n; tile_n = tile_idx % tiles_n; } // Access pattern for a 4x", "sha256": "9720f2edd4aa71b1333634cb1bd2929471836dca97a1527d34f26eb0d04fc18b"}, {"id": "u004", "kind": "prose", "locator": "body:L31-L31", "preview": "Tiles are assigned in a blocked pattern that groups nearby M and N tiles together, maximizing reuse of both A rows and B columns in L2 cache:", "sha256": "6a8479c6187de272d3444ed5b8b189380f3e9f3a3e18c86b1502a0648415bffb"}, {"id": "u005", "kind": "code", "locator": "body:L33-L61", "preview": "```cuda // Swizzled raster: group tiles into blocks that share A and B data // swizzle_size controls the block width (typically 4-8) __device__ void swizzled_raster(int tile_idx, int tiles_m, int tiles_n, int swizzle_size, int& tile_m, int&", "sha256": "1d71edfca8fbc446a33f887b3c61d17340ea86ccecd34e7538918d6b87c9dd67"}, {"id": "u006", "kind": "prose", "locator": "body:L65-L65", "preview": "Each CTA processes tiles at fixed intervals equal to the grid size:", "sha256": "626c37c57779514424f31ec600f0e59259f30613263ccf73cd308e60ff3bb9d7"}, {"id": "u007", "kind": "code", "locator": "body:L67-L76", "preview": "```cuda // Static stride: CTA i processes tiles i, i+gridDim.x, i+2*gridDim.x, ... __device__ void static_stride(int cta_id, int total_ctas, int iteration, int tiles_n, int& tile_m, int& tile_n) { int tile_idx = cta_id + iteration * total_c", "sha256": "0449df45a153b12f4cb418bcbc3e6bc21c44838006c0c634edfc6fae1aa4c1b5"}, {"id": "u008", "kind": "prose", "locator": "body:L80-L80", "preview": "The CLC hardware scheduler assigns tiles at runtime, combining the benefits of dynamic load balancing with configurable scheduling policies:", "sha256": "e0eb0c8c1ce6dcd126479616e2c269bc33221a6f5270ffe963a3e97c5040eed6"}, {"id": "u009", "kind": "code", "locator": "body:L82-L105", "preview": "```cuda // CLC-based scheduling on Blackwell // The scheduling policy is set once during CLC initialization enum class ClcSchedulePolicy { LinearRaster, // Simple row-major order SwizzledRaster, // Blocked pattern for L2 locality ColumnFirs", "sha256": "0a69add195542b6d20d2efcd280213ffb995ec493550c142f9dc6b6e9b6e7052"}, {"id": "u010", "kind": "prose", "locator": "body:L109-L109", "preview": "CUTLASS provides several tile schedulers that abstract these strategies:", "sha256": "53e1fe4703c3761ea5fd5c60b8a678cef5b9e2e254ea66c7429759cf3e434ac3"}, {"id": "u011", "kind": "code", "locator": "body:L111-L137", "preview": "```cuda // CUTLASS tile scheduler selection for SM100 // All persistent schedulers inherit from PersistentTileSchedulerSm100 // 1. Default CLC scheduler with swizzled raster using Scheduler_Default = cutlass::gemm::PersistentTileSchedulerSm", "sha256": "133158bd5ec890108cdb7014c1fc7f9ec966a8455dd307c8fbe4e41e00b3f6b0"}, {"id": "u012", "kind": "prose", "locator": "body:L141-L141", "preview": "The choice of scheduling strategy directly impacts L2 cache hit rates. On B200 with 126 MB L2:", "sha256": "949d895f78e70ec2107dbe2df4e6d391866d729b9959dd0672b8d3e475d96c7a"}, {"id": "u013", "kind": "code", "locator": "body:L143-L163", "preview": "```python # L2 cache reuse analysis for different schedulers # Problem: M=8192, N=8192, K=4096, BF16 # Tile: 128x256, giving 64x32 = 2048 tiles # B200: 142 SMs, 126 MB L2 tile_bytes_A = 128 * 4096 * 2 # 1 MB per tile row of A tile_bytes_B =", "sha256": "e2a8efabe8686e235ab683a4980248113bdb5b72e573ccc24f0e20981e247222"}, {"id": "u014", "kind": "prose", "locator": "body:L167-L167", "preview": "The \"tail effect\" occurs when the last wave of tiles does not fully occupy all SMs. Different schedulers handle this differently:", "sha256": "357e5feab90e19e3e79c54e9ea33d2c81c2374ecb6aca75c5ed30aa65df6dffc"}, {"id": "u015", "kind": "table-row", "locator": "body:L171-L171", "preview": "| Scheduler | Tail Handling | SM Utilization (Last Wave) | | Linear raster | None | `(total_tiles % num_SMs) / num_SMs` |", "sha256": "f08837ccea1dae5a19410ad3efcc85417d04c335a474e95a7cdc400ff76978b0"}, {"id": "u016", "kind": "table-row", "locator": "body:L172-L172", "preview": "| Scheduler | Tail Handling | SM Utilization (Last Wave) | | Static stride | None | Same as linear |", "sha256": "aeb54c647106afd98be6f50ab9ba26b650386b1614b8eaa85491180e9394ec86"}, {"id": "u017", "kind": "table-row", "locator": "body:L173-L173", "preview": "| Scheduler | Tail Handling | SM Utilization (Last Wave) | | CLC dynamic | Automatic | Fast CTAs steal from slow ones |", "sha256": "7baa281524a3bbdf21836ba8998a42b5b08146c2d8b1c2309b5ee6aecbcc3048"}, {"id": "u018", "kind": "table-row", "locator": "body:L174-L174", "preview": "| Scheduler | Tail Handling | SM Utilization (Last Wave) | | Stream-K | K-splitting | Near 100% (splits partial tiles across SMs) |", "sha256": "a42815aa76589b28218189b993e93245b38d6719e398582bf8b43bd50a95f27e"}, {"id": "u019", "kind": "prose", "locator": "body:L176-L176", "preview": "For a problem with 150 tiles on 142 SMs:", "sha256": "69a82d0a9da8abc0f2f4a0a7d56ed2bcd46a7893e3580b571fb3a6a8b7715db0"}, {"id": "u020", "kind": "list-item", "locator": "body:L177-L177", "preview": "- Static: last wave has 8 tiles on 8 SMs, 134 SMs idle (5.6% utilization)", "sha256": "737fd5d377aa2daf45da695e8178504adef84f2fc9f5633591dddd3934859957"}, {"id": "u021", "kind": "list-item", "locator": "body:L178-L178", "preview": "- CLC: fast-finishing CTAs from wave 1 absorb the 8 extra tiles", "sha256": "a8a66c01e93cb1bf7d589b2a84386086248864b9539e4eb7609a04a78304abad"}, {"id": "u022", "kind": "list-item", "locator": "body:L179-L179", "preview": "- Stream-K: the 8 remaining tiles are split across all 142 SMs", "sha256": "0b0c60176f514b10115881bc5c863149897bd9e8fa6545bb896e67dd37052a04"}, {"id": "u023", "kind": "list-item", "locator": "body:L183-L183", "preview": "- **Swizzled raster**: Default choice for large GEMMs. Always better than linear for L2 locality.", "sha256": "7f6d611ccd092bd4c1688ccd3016edbd88e2be7fff8ad873b62aea7710c5334e"}, {"id": "u024", "kind": "list-item", "locator": "body:L184-L184", "preview": "- **CLC dynamic**: Recommended on Blackwell for all persistent kernels. Combines dynamic load balancing with swizzled ordering.", "sha256": "e18aae4896c8004692a201fd12130e424d1d729e2e8c873538b98bd78e2c3dbf"}, {"id": "u025", "kind": "list-item", "locator": "body:L185-L185", "preview": "- **Stream-K**: Best for small-to-medium problems where the tail effect dominates. Adds complexity for K-dimension synchronization.", "sha256": "a10fbadf54d93ec53e2b07a7bd5c13f723d583252aa8ffba18cf8edf4b51ac29"}, {"id": "u026", "kind": "list-item", "locator": "body:L186-L186", "preview": "- **Grouped scheduler**: Essential for MoE and batched GEMM where problem sizes vary across groups.", "sha256": "edc0d6575b597a5a540f33437674d089efe77e537de7136d8d5a0e0f9242fb20"}, {"id": "u027", "kind": "list-item", "locator": "body:L190-L190", "preview": "- Swizzle size must be tuned per problem shape. Too large a swizzle group exceeds L2 capacity; too small loses the locality benefit.", "sha256": "23387e8e50870f4e3070e24961464a5ad75bd34ebab3e83f62e53375ffb81f8f"}, {"id": "u028", "kind": "list-item", "locator": "body:L191-L191", "preview": "- CLC scheduling adds a small latency per tile acquisition (~10s of cycles). For extremely small tiles, this overhead is proportionally larger.", "sha256": "8f44f7a0ed20da7c71487dd826806bed275053b56d2c9fdc81c661459d194c59"}, {"id": "u029", "kind": "list-item", "locator": "body:L192-L192", "preview": "- Stream-K requires atomic accumulation where K-splits meet, adding synchronization overhead. Only worthwhile when tail utilization is a proven bottleneck.", "sha256": "9c6b133dcad467c1c9d91088d2fc4977902c5fec4bbd04f129a159f7145eb57f"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Scheduling Strategies", "Linear Raster (Naive)", "Swizzled Raster", "Static Stride (Hopper Persistent)", "CLC Dynamic Scheduling (Blackwell)", "CUTLASS Tile Schedulers", "L2 Cache Locality Analysis", "Tail Effect Mitigation", "When to Use", "Caveats"], "id": "technique-tile-scheduling", "path": "wiki/techniques/tile-scheduling.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/docs/nvidia-cutlass-blackwell.md", "url": "https://docs.nvidia.com/cutlass/latest/CHANGELOG.html"}, {"path": "sources/prs/cutlass/PR-2161.md", "revision": "06e560d9", "url": "https://github.com/NVIDIA/cutlass/pull/2161"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "doc-cutlass-blackwell", "pr-cutlass-2161"], "title": "Tile Scheduling Strategies", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "a1867ce5eadf388cf89f64dbc67969e35641a2aee5abf95bc15a6310620d3778", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "For memory-bound kernels (low arithmetic intensity), maximizing global memory throughput is critical. Three complementary techniques from the GPU Mode NVFP4 Hackathon achieve this: (1) wide vectorized loads (128-bit and 256-bit) to saturate", "sha256": "4373b20db1333710b0bd2335d83f1cd217e133fb05fe6f947ea6078b93b21db0"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "Standard 32-bit loads waste memory bus bandwidth. Wider loads amortize the instruction overhead and saturate the 8 TB/s HBM bandwidth of B200:", "sha256": "df58a252f5ff63de56a417d666f95144516e2883b0eccd7d3c86a4373b9d77d8"}, {"id": "u003", "kind": "code", "locator": "body:L9-L34", "preview": "```cuda // Vectorized load widths comparison for FP4 GEMV // Each thread loads more data per instruction // 32-bit load: 4 bytes per thread per instruction float val; asm volatile(\"ld.global.b32 %0, [%1];\" : \"=f\"(val) : \"l\"(ptr)); // 64-bit", "sha256": "b8da4a10406241c34acee820f4f57eabcfc788a4324822ac1355bacd74aa7b2a"}, {"id": "u004", "kind": "prose", "locator": "body:L36-L36", "preview": "For the NVFP4 GEMV, 128-bit and 256-bit loads are essential because FP4 elements are only 0.5 bytes each. A 256-bit load fetches 64 FP4 values in a single instruction:", "sha256": "82e9fd56bce1ec6ee9e5b07738affb2b6d581a1190db38b8b66e2aad4f7542c6"}, {"id": "u005", "kind": "code", "locator": "body:L38-L84", "preview": "```cuda // NVFP4 GEMV: each thread loads 64 FP4 values via 256-bit load // Then unpacks using PTX byte manipulation instead of bitwise ops __device__ void load_and_unpack_nvfp4_256bit( const uint8_t* fp4_data, // Packed FP4 data (2 values p", "sha256": "a95e2476191e4074792945f538a15f7078455f03dfabb01108532add2a06aac2"}, {"id": "u006", "kind": "prose", "locator": "body:L88-L88", "preview": "Different data streams have different reuse patterns. Applying the correct cache policy per stream avoids L1 pollution:", "sha256": "61778bb24a32b6ac45f992fbba02b18d498c3e6c044780c753715746e1dd4194"}, {"id": "u007", "kind": "code", "locator": "body:L90-L111", "preview": "```cuda // Cache policy selection based on data reuse pattern // // Matrix A (streamed, each row used once): bypass L1 // Vector B (reused across all rows): keep in L1 // L1::no_allocate -- data bypasses L1 cache (streaming access) // Used ", "sha256": "b0734ac15004edad0a83d5fd86ed95480d0b97b6b9cdcacbf7e2d75c021ea929"}, {"id": "u008", "kind": "prose", "locator": "body:L113-L113", "preview": "The impact of cache policies from the GPU Mode Hackathon:", "sha256": "f56640266fb0eecdc5c4ed6f9dbc6a0e0c5c080df7fb55976b1ea7a889217e30"}, {"id": "u009", "kind": "code", "locator": "body:L115-L118", "preview": "``` No cache policy differentiation: 39 us A: L1::no_allocate, B: L1::evict_last: 27 us (1.44x faster) ```", "sha256": "93753b7b8d8885417ae945b5832c4e6037cbfa0b155ca965c3d0101ffb5497e0"}, {"id": "u010", "kind": "prose", "locator": "body:L120-L120", "preview": "The full set of PTX load cache qualifiers:", "sha256": "58238eda395968073d78483c5eb95a8038f94ee1d47de03e3a3250d77fccb6d0"}, {"id": "u011", "kind": "code", "locator": "body:L122-L141", "preview": "```ptx // PTX load qualifiers for cache control // Default: normal L1 and L2 caching ld.global.b32 %r, [%addr]; // L1 bypass: skip L1, still cached in L2 ld.global.L1::no_allocate.b32 %r, [%addr]; // L1 keep: prioritize keeping in L1 (evict", "sha256": "752b8164a5b4f09717bab64bb2690873b38f30979fe106828f3f030b51fe0cc6"}, {"id": "u012", "kind": "prose", "locator": "body:L145-L145", "preview": "For memory-bound kernels, occupancy (number of concurrent warps) matters more than per-thread register count. Limiting registers per thread allows more warps to be resident:", "sha256": "ce919dc749b52caf12cf9687444b0b1552d8de0de1dc2dd38e46c2f802514c0c"}, {"id": "u013", "kind": "code", "locator": "body:L147-L158", "preview": "```cuda // Compile-time register budgeting // Lower register count -> higher occupancy -> better latency hiding // Problem 1 winner (rank 1): -maxrregcount=32 // This allows 64 warps per SM (100% occupancy on SM100) // Sufficient for GEMV w", "sha256": "f3944a53fcb1063a93b50128e650325c3a6acccfc57a90ca33484f9d545361eb"}, {"id": "u014", "kind": "prose", "locator": "body:L160-L160", "preview": "The tradeoff in a build system:", "sha256": "ce280082b2b1587dd5ae7c4e1402a49d8cb6060a15a716009558cf9fcf9cd182"}, {"id": "u015", "kind": "code", "locator": "body:L162-L182", "preview": "```python # nvcc compilation with register budgeting # In CMakeLists.txt or build script: # For memory-bound GEMV kernel: # nvcc -maxrregcount=32 -arch=sm_100a gemv_kernel.cu -o gemv_kernel # For compute-bound GEMM kernel: # nvcc -arch=sm_1", "sha256": "6cc44d43960128e135d7061ed05a7b56241b0cf041f691c9417863073b9e37c3"}, {"id": "u016", "kind": "prose", "locator": "body:L186-L186", "preview": "Combining all three techniques for the GPU Mode Hackathon Problem 1:", "sha256": "f67480c8411891c3e6befa7eca7f1232b1aabd911b9e724958ddda6de1bda868"}, {"id": "u017", "kind": "code", "locator": "body:L188-L264", "preview": "```cuda // Optimized NVFP4 Batched GEMV // A: [M, K] NVFP4, B: [1, K] NVFP4, C: [M, 1] FP16 // Memory-bound: maximize bandwidth utilization // NVFP4 Batched GEMV: each row processed by THREADS_PER_ROW threads // Memory-bound: maximize bandw", "sha256": "5b7c6c47ee7b177b2bdfdaf82c08f189e36da1260845eb206cf4e8108d76c4c2"}, {"id": "u018", "kind": "table-row", "locator": "body:L270-L270", "preview": "| Step | Technique | Latency | Speedup | | Baseline | Naive C++ | 2000 us | 1.0x |", "sha256": "336d82fc951196f5c09b1d297d523dff11e195daeb27195b27e8e6253822f944"}, {"id": "u019", "kind": "table-row", "locator": "body:L271-L271", "preview": "| Step | Technique | Latency | Speedup | | Coalesced access | Memory layout fix | 443 us | 4.5x |", "sha256": "c50836382c1a13b8bf4fdd723d935a8f201e0a11910ab53918f60300fac2c46d"}, {"id": "u020", "kind": "table-row", "locator": "body:L272-L272", "preview": "| Step | Technique | Latency | Speedup | | Hardware intrinsics | FP4 decode | 39 us | 51x |", "sha256": "02cfff4537a67926f42d4e2d186091b3ae71c13b73928ed44a42ed5f1a06ebe1"}, {"id": "u021", "kind": "table-row", "locator": "body:L273-L273", "preview": "| Step | Technique | Latency | Speedup | | PTX assembly | Vectorized loads + cache policy | 27 us | 74x |", "sha256": "a97d68be1e19e4fde08df751d18b0b47aa4f1b681fa05da69cd7d22f449130c2"}, {"id": "u022", "kind": "table-row", "locator": "body:L274-L274", "preview": "| Step | Technique | Latency | Speedup | | ILP + register tuning | Unrolling + maxrregcount | 22.4 us | 89x |", "sha256": "f390517562b134bf9d59c2f220a8a65fed2b59f44eba33937b9c1fbcc0591045"}, {"id": "u023", "kind": "table-row", "locator": "body:L275-L275", "preview": "| Step | Technique | Latency | Speedup | | Speed of light | | ~8.6 us | 233x |", "sha256": "8520b3cfbcc908b3d011fd6695594d47a25d7129a4750c8f39bb28c4a35e551e"}, {"id": "u024", "kind": "list-item", "locator": "body:L279-L279", "preview": "- **GEMV and memory-bound kernels**: Vectorized loads and cache policies are essential. These kernels are entirely limited by memory bandwidth.", "sha256": "a2c9186327c182ffcfa11105251c8e1d30d79f72f672da4385c3ea1a7c113c58"}, {"id": "u025", "kind": "list-item", "locator": "body:L280-L280", "preview": "- **FP4/FP8 kernels**: Sub-byte data types make wide loads even more impactful since more elements fit in a single wide load.", "sha256": "6027557e719d2dce03de3254883be51e4ec7e66ea527d0acdc53161bd3d0be0d"}, {"id": "u026", "kind": "list-item", "locator": "body:L281-L281", "preview": "- **Decode-phase inference**: Single-token GEMV during autoregressive decoding is always memory-bound.", "sha256": "de4b54f2013583c782aa0f5613a89b9f229884229753709e91acce3eb9236c22"}, {"id": "u027", "kind": "list-item", "locator": "body:L285-L285", "preview": "- 256-bit loads require 32-byte aligned addresses. Misaligned access falls back to multiple narrower transactions.", "sha256": "6d651625c4f75106870bf3d68fc195b15f62597fd26ce759ac4661921ce2e45a"}, {"id": "u028", "kind": "list-item", "locator": "body:L286-L286", "preview": "- `L1::no_allocate` is harmful for data that will be reused. Only apply it to truly streaming access patterns.", "sha256": "c86c6ab9e1578a21cf22e62a20b4c0937078fc8f8890dc10d7f3ca35a7740f5a"}, {"id": "u029", "kind": "list-item", "locator": "body:L287-L287", "preview": "- `-maxrregcount` that is too low causes register spilling to local memory, which is slower than the occupancy gain. Profile with Nsight Compute to find the optimal point.", "sha256": "83dddd1b4b88276c52be1d17c87b02929fb67cceab3ace5b6dd48335111a8cf7"}, {"id": "u030", "kind": "list-item", "locator": "body:L288-L288", "preview": "- PTX inline assembly bypasses the compiler's register allocator. Excessive inline PTX can interfere with compiler optimizations for surrounding code.", "sha256": "76af809266f88b18f00f2435cb2e5aaa3355cebd364a7e56714cd4c5bc6b2ce4"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Wide Vectorized Loads", "L1 Cache Policy Differentiation", "Register Budgeting (-maxrregcount)", "Complete NVFP4 GEMV Example", "Optimization Progression (GPU Mode Hackathon Problem 1)", "When to Use", "Caveats"], "id": "technique-vectorized-loads", "path": "wiki/techniques/vectorized-loads.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/yue-nvfp4-hackathon.md", "url": "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"}, {"path": "sources/blogs/amandeep-nvfp4-attempts.md", "url": "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"}, {"path": "sources/contests/gpu-mode-nvfp4/problem-1-gemv.md", "url": "https://github.com/gpu-mode/reference-kernels"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-yue-nvfp4", "blog-amandeep-nvfp4", "contest-gpumode-p1"], "title": "Wide Vectorized Loads and Cache Policies", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "48ec87e638f28a2e42314d08521041a40b518e4fe0d8ba0b984f9764efcf3fd9", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Warp specialization assigns distinct functional roles to warps within a CTA, allowing each warp to focus on a single pipeline stage (data loading, MMA computation, or epilogue writeback). On Blackwell (SM100), the 16-warp CTA structure repl", "sha256": "da68ea21e6384fe8ed99ca14e0dec4aafcd6dd43bae885faa06936cced0326a7"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "The canonical Blackwell GEMM kernel uses 16 warps (512 threads) per CTA with the following role assignment:", "sha256": "de5f4767ff59a243b7cd0bf9cf1e5316f4b00bd2a0a4d7d17a288d87f0066cdc"}, {"id": "u003", "kind": "table-row", "locator": "body:L11-L11", "preview": "| Warp ID | Role | Responsibility | | 0 | TMA Producer | Issues TMA bulk-copy from global to shared memory, signals mbarrier |", "sha256": "e23f6c241b5be333ca535184eb14223d873a2de3e2c869d9f2d380d357b3d33e"}, {"id": "u004", "kind": "table-row", "locator": "body:L12-L12", "preview": "| Warp ID | Role | Responsibility | | 1 | MMA Consumer | Issues tcgen05.mma on SMEM operands, writes results to TMEM |", "sha256": "ee835b266c9294c9f2a1b9aea49739bf61e6b5754e7361e0bc2b237c66c6a548"}, {"id": "u005", "kind": "table-row", "locator": "body:L13-L13", "preview": "| Warp ID | Role | Responsibility | | 2-15 | Epilogue | Reads TMEM accumulator, applies scale/bias/activation, writes to global memory |", "sha256": "66e041a9aaa309ff343b8e44e0e845d9c80e1043c55ead5c561127698c6c1c12"}, {"id": "u006", "kind": "prose", "locator": "body:L15-L15", "preview": "This contrasts with Hopper where a warpgroup (4 warps, 128 threads) collectively issues wgmma.mma_async, and all threads in the warpgroup participate in the MMA. On Blackwell, the MMA warp dispatches the instruction from a single thread whi", "sha256": "7c12b99bbbf11a24a3975923f89cb7364f576479e6ffe0cf3e44d777edb34a35"}, {"id": "u007", "kind": "table-row", "locator": "body:L21-L21", "preview": "| Aspect | Hopper (SM90) | Blackwell (SM100) | | MMA granularity | 4-warp warpgroup (128 threads) | Single thread in 1 warp |", "sha256": "9501b37c444d81b54c35183ca8d5aed043b54645491c4d4cf54309949f526ce8"}, {"id": "u008", "kind": "table-row", "locator": "body:L22-L22", "preview": "| Aspect | Hopper (SM90) | Blackwell (SM100) | | MMA output destination | Registers (shared across warpgroup) | TMEM (256KB, CTA-visible) |", "sha256": "cf6cf6943fd445678a4f0fcc62e356d4ad8ca0ca62167fc7f42c5bf871905f20"}, {"id": "u009", "kind": "table-row", "locator": "body:L23-L23", "preview": "| Aspect | Hopper (SM90) | Blackwell (SM100) | | Producer warps | Separate warp(s) for TMA loads | Warp 0 dedicated to TMA |", "sha256": "12f9916a54cce0a6b9e7f618ff6a780fdcd908ff108577efa534955ef70dadfa"}, {"id": "u010", "kind": "table-row", "locator": "body:L24-L24", "preview": "| Aspect | Hopper (SM90) | Blackwell (SM100) | | Epilogue execution | Same warpgroup or separate warps | 14 dedicated warps (2-15) |", "sha256": "fb2aa36acbe1915af15f8d542b0a90d38000d4f95255150b748812c980c44c85"}, {"id": "u011", "kind": "table-row", "locator": "body:L25-L25", "preview": "| Aspect | Hopper (SM90) | Blackwell (SM100) | | Synchronization | warpgroup barriers, arrive/wait | mbarrier pairs (producer/consumer) |", "sha256": "2cace7a3e7b39e5063c94652331e357e886e261cb9f7cc318e57773fc37e5616"}, {"id": "u012", "kind": "table-row", "locator": "body:L26-L26", "preview": "| Aspect | Hopper (SM90) | Blackwell (SM100) | | Register pressure | High (accumulators in registers) | Low (accumulators in TMEM) |", "sha256": "f8e1ff2e3d5ee5b118c21a3b74af5684bcd18d154bdcf43f9e35c165f84ac8db"}, {"id": "u013", "kind": "prose", "locator": "body:L30-L30", "preview": "The kernel entry point assigns each warp its role based on `threadIdx.x`:", "sha256": "ebdfd00934c10addf671ee6c2cb5cb6c322fb1735230e966e8327dba6c666bd5"}, {"id": "u014", "kind": "code", "locator": "body:L32-L155", "preview": "```cuda // Blackwell 16-warp specialized GEMM kernel skeleton // 16 warps = 512 threads per CTA __global__ void __launch_bounds__(512) blackwell_gemm_warp_specialized( const __grid_constant__ GemmParams params) { const int warp_id = threadI", "sha256": "1238a08de84a73fa41d398e4aece1b28464d483317ca6b3879fc5d8a5a089ac9"}, {"id": "u015", "kind": "prose", "locator": "body:L159-L159", "preview": "The producer-consumer synchronization uses mbarrier pairs. Each pipeline stage has two barriers:", "sha256": "7b46b41fb034dfeaf0da578f65d8230f648de6bade3e3b7ed48ef987ec1b595d"}, {"id": "u016", "kind": "list-item", "locator": "body:L161-L161", "preview": "1. **data_ready**: Producer (Warp 0) arrives after TMA completes. Consumer (Warp 1) waits before issuing MMA.", "sha256": "bbb39c8d97ce7f22227172b3f2a697a5700673f4b35e946bf73f488e89e42221"}, {"id": "u017", "kind": "list-item", "locator": "body:L162-L162", "preview": "2. **buffer_free**: Consumer (Warp 1) arrives after MMA consumes the data. Producer (Warp 0) waits before overwriting the buffer.", "sha256": "d5406aa4c18b3073b5c3acc0247aa98f14a04d4fa8b6fffc24b82b5b249f47b4"}, {"id": "u018", "kind": "prose", "locator": "body:L164-L164", "preview": "At the PTX level, the mbarrier operations map to:", "sha256": "8fd645f2337717bb6614b4e85f50c4d5e378736f8233810542afe896f7e6bbe0"}, {"id": "u019", "kind": "code", "locator": "body:L166-L178", "preview": "```ptx // Producer: signal data is ready in stage %stage mbarrier.arrive.shared.b64 %dummy, [%mbar_data_ready + %stage_offset]; // Consumer: wait for data to be ready mbarrier.try_wait.parity.shared.b64 %pred, [%mbar_data_ready + %stage_off", "sha256": "9863ded2350007fa56e7c0fdbb2900b0def790913e94618882c21c78b55114af"}, {"id": "u020", "kind": "prose", "locator": "body:L182-L182", "preview": "In CUTLASS 4.5.0, the SM100 GEMM collective (`CollectiveMma_1SM`) implements this pattern with CuTe abstractions:", "sha256": "6c3f43a9f5180313f211d5e54d8e1ea09b302f6fc25688820675f47dcda9401b"}, {"id": "u021", "kind": "code", "locator": "body:L184-L211", "preview": "```cuda // CUTLASS SM100 warp role dispatch (simplified from CollectiveMma) // Template parameter WarpCount = cute::Shape<1, 1, 14> // Warp 0 = producer, Warp 1 = math, Warps 2-15 = epilogue template struc", "sha256": "f9559e318d537c668357c24e65dede295acac7c5ab86a8da0927c063ec3092dc"}, {"id": "u022", "kind": "list-item", "locator": "body:L215-L215", "preview": "- **Always on Blackwell GEMMs**: Warp specialization is the standard pattern for SM100 tensor core kernels. The tcgen05 instruction model assumes single-thread dispatch with TMEM output.", "sha256": "134a0249a13f619bb66cb12d8fdd7ea57d1ea3c5963058c4b5833596d4e4cc52"}, {"id": "u023", "kind": "list-item", "locator": "body:L216-L216", "preview": "- **Attention kernels**: FlashAttention-4 extends this to ping-pong scheduling with 2 query tile groups and dedicated softmax warps.", "sha256": "cb8edb4bc739191404192c08ae07092a800fb2844aaf8e46a36d1a2a08788912"}, {"id": "u024", "kind": "list-item", "locator": "body:L217-L217", "preview": "- **Any kernel with producer-consumer pipeline**: When TMA loads and MMA compute can overlap, warp specialization provides the cleanest decomposition.", "sha256": "b41a91691e1784ab015dc1f1ad4351f86a96f26969196ffc5ba85f6a1ced6292"}, {"id": "u025", "kind": "list-item", "locator": "body:L221-L221", "preview": "- The 14 epilogue warps may be underutilized for simple epilogues (e.g., pure store). Complex epilogues (scale, bias, activation, quantization) benefit more.", "sha256": "2a932b047515d65e2a3832670486a534a3df6eec93cb9c057c46379fa31da1b1"}, {"id": "u026", "kind": "list-item", "locator": "body:L222-L222", "preview": "- The single MMA warp means the kernel cannot overlap multiple independent MMA streams within a CTA. Use 2-SM cooperative mode for larger tiles instead.", "sha256": "b47c4681255805de9445498daab973a4c01f4951c4788988357b2df59fd9497f"}, {"id": "u027", "kind": "list-item", "locator": "body:L223-L223", "preview": "- mbarrier initialization must happen before any warp tries to wait; use `__syncthreads()` after init if needed.", "sha256": "290645aeddd55af0f1315f3407f062f5f42ae857853fcb8ee8d5082be12037cb"}, {"id": "u028", "kind": "prose", "locator": "body:L227-L227", "preview": "Local verbatim upstream code lives in [`artifacts/kernels/warp-specialization/full/`](../../artifacts/kernels/warp-specialization/full/) (see its `PROVENANCE.yaml` for the pinned upstream SHA and byte-verified SHA-256). Labeled derived vari", "sha256": "eeeda30cf2081846193f80099b748c3550961732b1403dfb8c0a7fbc62f8c824"}, {"id": "u029", "kind": "prose", "locator": "body:L229-L229", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u030", "kind": "code", "locator": "body:L231-L233", "preview": "```bash python3 scripts/get_page.py technique-warp-specialization --include-code ```", "sha256": "b7c5cf5fad5ff312746a2f70dd0f13cb952d92b5faa64436566a716041abd115"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Blackwell 16-Warp Kernel Structure", "Comparison with Hopper Warpgroup Model", "Warp Role Assignment", "mbarrier Synchronization Pattern", "CUTLASS SM100 Warp Specialization", "When to Use", "Caveats", "Full Reference Implementation"], "id": "technique-warp-specialization", "path": "wiki/techniques/warp-specialization.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/blogs/colfax-cutlass-blackwell.md", "url": "https://research.colfax-intl.com/cutlass-tutorial-writing-gemm-kernels-using-tmem-for-nvidia-blackwell-gpus/"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "blog-colfax-cutlass"], "title": "Warp Specialization on Blackwell", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} diff --git a/verification/before-after-report.jsonl b/verification/before-after-report.jsonl new file mode 100644 index 000000000..c52de8b73 --- /dev/null +++ b/verification/before-after-report.jsonl @@ -0,0 +1,493 @@ +{"path": "wiki/hardware/clc.md", "before": {"statement": "Cluster Launch Control (CLC) is a Blackwell hardware mechanism for **dynamic tile scheduling** in persistent kernels. It replaces the static grid scheduling model where the CUDA runtime pre-assigns tile coordinates to CTAs at launch time.\n\n- **Better load balancing**: No fixed CTA-to-tile mapping; busy SMs consume tiles as they become available."}, "after": {"statement": "1. The block or cluster launches normally and first processes its own\n `blockIdx`.\n2. An existing worker successfully cancels that not-yet-started ClcID and\n processes the returned coordinate itself."}, "reason": {"statement": "Retain the dynamic-work-stealing concept while restoring the documented initial assignment and full-grid model.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "- **Tail-effect mitigation**: The \"tail\" of a GEMM (when remaining tiles < number of SMs) is handled efficiently because idle CTAs pick up remaining work.\n\n```\nLaunch grid: 256 CTAs for 256 tiles\nCTA 0 -> tile (0,0) [fixed at launch]\nCTA 1 -> tile (0,1) [fixed at launch]\nCTA 2 -> tile (0,2) [fixed at launch]\n...\nCTA 255 -> tile (15,15) [fixed at launch]\n\nProblem: If SM count = 132, first wave = 132 CTAs.\n Second wave = 124 CTAs -> 8 SMs idle = 6% waste.\n For small GEMMs, tail effect dominates.\n```"}, "after": {"statement": "At CUTLASS 4.5.0, the `PersistentScheduler` tag for `arch::Sm100` maps to\n`PersistentTileSchedulerSm100`; newer code can select the intent explicitly\nwith `DynamicPersistentScheduler`. The SM100 scheduler uses\n`PipelineCLCFetchAsync`: `advance_to_next_work()` submits a request, while\n`fetch_next_work()` waits for and decodes the staged response."}, "reason": {"statement": "Replace the universal tail claim with the scoped load-balancing benefit documented for uneven SM availability.", "urls": ["https://docs.nvidia.com/deeplearning/performance/dl-performance-matrix-multiplication/index.html", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cutlass/gemm/kernel/tile_scheduler.hpp", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cutlass/gemm/kernel/sm100_tile_scheduler.hpp"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "- **Dynamic cancellation**: Tiles can be cancelled via `try_cancel` when the output is no longer needed (e.g., speculative decoding).\n\nCLC provides a `try_cancel` mechanism to cancel pending tiles. This is useful for speculative execution where some outputs may not be needed.\n\nUse cases for `try_cancel`:\n- **Speculative decoding**: Cancel tiles for rejected draft tokens.\n- **Early termination**: If an attention mask makes certain output tiles zero, cancel them.\n- **Dynamic batching**: Cancel tiles for sequences that have finished."}, "after": {"statement": null}, "reason": {"statement": "The listed use cases depend on an API capability CLC does not provide; no useful verified portion remains.", "urls": ["https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "```\nLaunch grid: 132 persistent CTAs (= SM count)\nCTA 0: request tile -> get (0,0) -> compute -> request tile -> get (2,4) -> ...\nCTA 1: request tile -> get (0,1) -> compute -> request tile -> get (2,5) -> ...\n...\nCTA 131: request tile -> get (0,131) -> compute -> request tile -> ...\n\nAll CTAs stay busy until the tile queue is empty.\nTail: last few tiles distributed to first-available CTAs.\n```"}, "after": {"statement": "1. The block or cluster launches normally and first processes its own\n `blockIdx`.\n2. An existing worker successfully cancels that not-yet-started ClcID and\n processes the returned coordinate itself.\n\nThis lets a persistent worker request subsequent work without maintaining a\nseparate software work queue. It is especially useful when the set of SMs\navailable to a kernel is uneven or changes while the grid is running."}, "reason": {"statement": "Replace the misleading diagram with the documented worker lifecycle.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md", "https://docs.nvidia.com/cutlass/4.3.3/media/docs/cpp/blackwell_cluster_launch_control.html"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "```cuda\n__global__ void persistent_gemm_clc(\n const half* A, const half* B, half* C,\n int M, int N, int K,\n int num_tiles_m, int num_tiles_n\n) {\n // Allocate persistent resources (TMEM, pipeline state)\n uint32_t tmem_acc = tmem_alloc(256);\n\n // Shared storage for CLC results (visible to all threads in CTA)\n __shared__ uint2 clc_tile_coord;\n __shared__ int clc_has_tile;\n\n // CLC tile loop: keep requesting tiles until none remain\n while (true) {\n // Thread 0 acquires the next tile; result goes to shared memory\n if (threadIdx.x == 0) {\n uint2 result;\n int acquired = 0;\n asm volatile(\n \"{\\n\"\n \" .reg .pred p;\\n\"\n \" clusterlaunchcontrol.try_cancel {%0, %1}, p;\\n\"\n \" selp.s32 %2, 1, 0, p;\\n\"\n \"}\\n\"\n : \"=r\"(result.x), \"=r\"(result.y), \"=r\"(acquired)\n );\n clc_tile_coord = result;\n clc_has_tile = acquired;\n }\n __syncthreads(); // All threads see the shared result\n\n // Exit if no more tiles\n if (!clc_has_tile) break;\n\n int tile_m = clc_tile_coord.x;\n int tile_n = clc_tile_coord.y;\n\n // Zero accumulator\n tmem_zero(tmem_acc, 256);\n\n // Mainloop: iterate over K dimension\n for (int k = 0; k < K / TILE_K; ++k) {\n // TMA load A and B tiles to SMEM\n tma_load_a(smem_a, A, tile_m, k);\n tma_load_b(smem_b, B, k, tile_n);\n wait_barrier();\n\n // Issue MMA\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 1;\"\n :\n : \"r\"(tmem_acc), \"l\"(desc_a), \"l\"(desc_b), \"r\"(0)\n );\n }\n }\n\n // Epilogue\n asm volatile(\"tcgen05.fence::before_thread_sync;\");\n __syncthreads();\n store_output(tmem_acc, C, tile_m, tile_n);\n }\n\n // Cleanup\n tmem_dealloc(tmem_acc, 256);\n}\n```"}, "after": {"statement": "This lets a persistent worker request subsequent work without maintaining a\nseparate software work queue. It is especially useful when the set of SMs\navailable to a kernel is uneven or changes while the grid is running.\n\n`clusterlaunchcontrol.try_cancel` is asynchronous. It writes an opaque 16-byte\nresponse to shared memory and completes a transaction on a shared-memory\n`mbarrier`. The request does not accept a tile coordinate to cancel.\n\nThe normative PTX instruction forms are:\n\n```ptx\nclusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [response], [mbar];\nclusterlaunchcontrol.query_cancel.is_canceled.pred.b128 p, response_b128;\n@p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {x, y, z, unused}, response_b128;\n```"}, "reason": {"statement": "Replace invalid illustrative CUDA with the official operation sequence and exact PTX signatures.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://docs.nvidia.com/cutlass/4.3.3/media/docs/cpp/blackwell_cluster_launch_control.html"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "```cuda\n// Cancel a specific tile if it hasn't started execution yet\n__device__ bool clc_try_cancel(uint2 tile_coord) {\n bool cancelled = false;\n if (threadIdx.x == 0) {\n asm volatile(\n \"clusterlaunchcontrol.try_cancel.async.shared::cta \"\n \"%0, [%1];\"\n : \"=r\"(cancelled)\n : \"r\"(&tile_coord)\n );\n }\n return cancelled;\n}\n```"}, "after": {"statement": "This lets a persistent worker request subsequent work without maintaining a\nseparate software work queue. It is especially useful when the set of SMs\navailable to a kernel is uneven or changes while the grid is running."}, "reason": {"statement": "Retain an API sketch only in the exact asynchronous request/decode form.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://docs.nvidia.com/cutlass/4.3.3/media/docs/cpp/blackwell_cluster_launch_control.html"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "```cuda\n// CUTLASS SM100 persistent GEMM with CLC scheduling\nusing Gemm = cutlass::gemm::device::GemmUniversal<\n cutlass::half_t, // ElementA\n cutlass::layout::RowMajor, // LayoutA\n cutlass::half_t, // ElementB\n cutlass::layout::ColumnMajor, // LayoutB\n cutlass::half_t, // ElementC\n cutlass::layout::RowMajor, // LayoutC\n float, // ElementAccumulator\n cutlass::arch::OpClassTensorOp,\n cutlass::arch::Sm100, // Blackwell\n // Tile shape: 128x256x64\n cutlass::gemm::GemmShape<128, 256, 64>,\n // Cluster shape\n cutlass::gemm::GemmShape<2, 1, 1>,\n // Use CLC persistent scheduler\n cutlass::gemm::PersistentScheduler\n>;\n\n// Launch: CUTLASS handles CLC internally\nGemm gemm_op;\ngemm_op(args, workspace, stream);\n```"}, "after": {"statement": "After a thread has observed a failed request, issuing another request from that\nthread is undefined. Decoding a CTA ID from a failed response is also undefined.\nA request can fail because no ClcIDs remain or for another scheduling reason,\nincluding pending higher-priority work."}, "reason": {"statement": "Replace invalid code with a compact excerpt matching the pinned release.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/95_blackwell_gemm_green_context/95_blackwell_gemm_green_context.cu", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "```cpp\n// Simplified CUTLASS CLC scheduler logic\nstruct ClcTileScheduler {\n CUTLASS_DEVICE\n WorkTileInfo get_next_work() {\n WorkTileInfo work;\n // Fetch next tile by cancelling a not-yet-launched ClcID.\n bool valid = clc_try_cancel(&work.tile_coord);\n work.is_valid = valid;\n\n if (valid) {\n // Convert linear tile index to 2D coordinates\n work.tile_m = work.tile_coord.x;\n work.tile_n = work.tile_coord.y;\n\n // Apply swizzle for L2 locality\n apply_l2_swizzle(work.tile_m, work.tile_n);\n }\n return work;\n }\n};\n```"}, "after": {"statement": "After a thread has observed a failed request, issuing another request from that\nthread is undefined. Decoding a CTA ID from a failed response is also undefined.\nA request can fail because no ClcIDs remain or for another scheduling reason,\nincluding pending higher-priority work."}, "reason": {"statement": "Replace the false pseudocode with the actual staged CUTLASS flow.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cutlass/gemm/kernel/sm100_tile_scheduler.hpp", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "CLC delivers significant performance gains, especially for small-to-medium GEMMs where tail effects dominate:\n\n| 2048x2048 (small) | 86% SM utilization | 98% SM utilization | +14% |\n| 4096x4096 (medium) | 92% SM utilization | 98% SM utilization | +6.5% |\n| 8192x8192 (large) | 97% SM utilization | 99% SM utilization | +2% |"}, "after": {"statement": null}, "reason": {"statement": "The exact numbers lack hardware, software, tile, dtype, occupancy, and timing scope; no source-backed replacement measurement is available.", "urls": []}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "The canonical benchmark from the \"tcgen05 for dummies\" tutorial shows the jump from 940 TFLOPS (pipelined, static scheduling) to **1476 TFLOPS** (persistent + CLC), approaching 98% of cuBLAS (1507 TFLOPS)."}, "after": {"statement": null}, "reason": {"statement": "The measured numbers may remain attributable to the tutorial elsewhere, but they are not CLC evidence and cannot support this page's performance claim.", "urls": ["https://gau-nernst.github.io/tcgen05/"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "```python\n# Typical LLM GEMM shapes during decode (batch_size=1-64)\n# M is small (batch * seq_len for decode), N and K are large (model dim)\n# Example: Llama-70B decode, batch=32\nM = 32 # small!\nN = 8192 # hidden dim\nK = 8192 # hidden dim\n\n# Tile = 128x256 -> tiles_m = 1, tiles_n = 32 -> only 32 tiles total\n# On B200 (132 SMs): 100 SMs idle with static scheduling\n# CLC: 32 persistent CTAs handle all 32 tiles efficiently\n```"}, "after": {"statement": "A schematic of the relevant CUTLASS 3.x kernel composition is:\n\n```cpp\nusing TileScheduler = cutlass::gemm::DynamicPersistentScheduler;\n\nusing GemmKernel = cutlass::gemm::kernel::GemmUniversal<\n cute::Shape,\n CollectiveMainloop,\n CollectiveEpilogue,\n TileScheduler>;\n```"}, "reason": {"statement": "Retain the useful warning about insufficient tile parallelism while removing the wrong hardware count and false CLC remedy.", "urls": ["https://developer.nvidia.com/blog/scaling-autonomous-ai-agents-and-workloads-with-nvidia-dgx-spark/", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/95_blackwell_gemm_green_context/95_blackwell_gemm_green_context.cu"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "```cuda\n// 2-SM cooperative CLC: each successful cancel gets a cluster-sized tile\n__device__ void cooperative_clc_loop() {\n while (true) {\n // Fetch tile for the 2-CTA cluster\n ClusterTile tile;\n bool valid = clc_try_cancel_cluster(&tile);\n if (!valid) break;\n\n // Both CTAs in the cluster share the tile\n // CTA 0 handles rows 0-127, CTA 1 handles rows 128-255\n int my_row_start = (blockIdx.x % 2) * 128;\n\n // Issue cooperative MMA\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.mma.cta_group::2.kind::f16 \"\n \"[%0], %1, %2, %3, 1;\"\n :\n : \"r\"(tmem_acc), \"l\"(desc_a), \"l\"(desc_b), \"r\"(0)\n );\n }\n // ...\n }\n}\n```"}, "after": {"statement": "A complete loop must:\n\n1. Allocate and initialize a shared response and `mbarrier`.\n2. Submit one asynchronous request from the selected thread and set the\n expected transaction size to 16 bytes.\n3. Wait for the corresponding barrier phase to complete.\n4. Decode `is_canceled`; decode `get_first_ctaid` only after success.\n5. Apply the async/generic proxy fences needed before reusing the response."}, "reason": {"statement": "Replace invalid executable-looking code with explicit, source-backed cluster requirements.", "urls": ["https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "```cuda\n// Swizzle tile coordinates for better L2 locality\n// Tiles are visited in a Z-order (Morton) curve pattern\n__device__ void apply_l2_swizzle(int& tile_m, int& tile_n, int swizzle_bits) {\n // Convert linear tile index to swizzled 2D coordinates\n // This groups spatially adjacent tiles together, improving\n // L2 reuse for the B matrix (shared across M tiles)\n int linear = tile_m * num_tiles_n + tile_n;\n int swizzle_mask = (1 << swizzle_bits) - 1;\n int group = linear >> swizzle_bits;\n int within = linear & swizzle_mask;\n\n tile_m = group / num_tiles_n;\n tile_n = (group % num_tiles_n) ^ (tile_m & swizzle_mask);\n}\n```"}, "after": {"statement": "CLC cancellation is cluster-granular when the kernel uses thread block\nclusters. One cluster thread submits the multicast request. Every CTA tracks\ncompletion with its local shared-memory barrier at cluster scope and receives\nthe same encoded first-CTA coordinate. Each CTA then adds its local block rank\nto that first coordinate. A cluster synchronization is needed to guarantee all\nblocks exist before cluster cancellation begins.\n\nFor example, a successful query by a 2x2 worker cluster consumes the matching\n2x2 group of ClcIDs; it is not four unrelated CTA-level cancellations."}, "reason": {"statement": "Delete the broken function and retain the verified CUTLASS software-coordinate-remapping mechanism.", "urls": ["https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "| Scheduling overhead | Near zero (hardware) | atomicAdd contention |\n| Tail-effect handling | Optimal | Good with careful design |"}, "after": {"statement": null}, "reason": {"statement": "The qualitative ranking has no defined workload or metric and cannot be replaced with a universal performance claim.", "urls": ["https://docs.nvidia.com/cutlass/4.3.3/media/docs/cpp/blackwell_cluster_launch_control.html", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html"]}} +{"path": "wiki/hardware/clc.md", "before": {"statement": "| L2 swizzle | Configurable at launch | Manual implementation |"}, "after": {"statement": "CLC cancellation is cluster-granular when the kernel uses thread block\nclusters. One cluster thread submits the multicast request. Every CTA tracks\ncompletion with its local shared-memory barrier at cluster scope and receives\nthe same encoded first-CTA coordinate. Each CTA then adds its local block rank\nto that first coordinate. A cluster synchronization is needed to guarantee all\nblocks exist before cluster cancellation begins.\n\nFor example, a successful query by a 2x2 worker cluster consumes the matching\n2x2 group of ClcIDs; it is not four unrelated CTA-level cancellations."}, "reason": {"statement": "Preserve swizzled work mapping but attribute it to the CUTLASS software scheduler.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cutlass/gemm/kernel/sm100_tile_scheduler.hpp", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/languages/triton-blackwell.md", "before": {"statement": "Triton is used for many attention and linear-attention kernels (NSA, GatedDeltaNet, FLA). Starting with Triton 3.6 (released `2026-01-21`), Triton ships native Blackwell (SM100) lowering through `tcgen05.mma` + Tensor Memory (TMEM). The earlier framing — \"Triton compiler generates wgmma, not tcgen05\" — was correct for Triton 3.5 and earlier but is no longer correct on 3.6+. See the \"Pre-3.6 historical context\" subsection below for the historical framing; the rest of this page describes the current 3.6+ behavior.\n\nThe 3.6 release adds Blackwell-native infrastructure for `tcgen05.mma`, TMEM allocation/copy/load/store, and warp-specialization plumbing. Source-of-record: [`doc-triton-3.6-blackwell`](../../sources/docs/triton-3.6-blackwell.md). Per-pathway breakdown with verified-vs-needs-verification status: [`data/triton-3.6-evidence.md`](../../data/triton-3.6-evidence.md).\n\n- **What is verified**: the Triton 3.6 release adds tcgen05 + TMEM lowering infrastructure (per `doc-triton-3.6-blackwell`), and tracked downstream repos are landing real Triton kernel changes for SM100 post-3.6 (per `pr-vllm-34597`, the post-refresh primary anchor — vLLM's \"[Kernel] Add FP8 KV cache support to Triton MLA decode attention\" PR, which directly modifies `@triton.jit`-decorated kernels in `vllm/v1/attention/ops/triton_decode_attention.py` doing `tl.dot(q, k)` / `tl.dot(qpe, kpe)` / `tl.dot(p, v)` matmul on `[sm100]`, shipped verbatim under `artifacts/prs/vllm/PR-34597/`). Supplementary post-refresh evidence: `pr-vllm-29339` shows the Triton 3.6 `triton_kernels` library being explicitly scoped to Blackwell production codepaths. Pre-refresh historical evidence: `pr-sglang-22079` (the Gemma4 NVFP4 attention kernel merged 2026-04-03). Together these establish that Triton 3.6+ on Blackwell is materially different from the pre-3.6 \"lacked-tcgen05 / lacked-TMEM\" story.\n\nBefore Triton 3.6, the Blackwell story was: the compiler generated `wgmma.mma_async`, accumulators stayed in registers, and direct `tcgen05` / TMEM access was unavailable from `tl.*`. Pages and inclusion-policy text written under that premise are obsolete. The current premise is: **`tcgen05` + TMEM lowering paths exist on SM100, but coverage and performance leadership are workload-dependent**.\n\n- **`doc-triton-3.6-blackwell`** (`source_category: official-doc`) — verifies that Triton 3.6 ships native Blackwell lowering infrastructure (TMEM, tcgen05, warp_specialize plumbing, Gluon multi-CTA / 2CTA, tl.dot_scaled). This is the \"infrastructure exists\" half of AC-1.2.\n\nTogether the two anchors establish that **the 3.6+ Blackwell lowering infrastructure is real AND tracked downstream repos are landing real Triton matmul kernels for Blackwell production decode paths today** — which is the substance of the rewrite: the pre-3.6 \"lacked-tcgen05 / lacked-TMEM\" framing is no longer correct.\n\n> The text in this subsection describes Triton 3.5 and earlier. It is preserved for historical accuracy and is NOT a current statement about Triton 3.6+ behavior. Do not cite it as current limitations.\n\nTriton on Blackwell — Triton 3.5 and earlier:\n\n1. **No direct tcgen05 access**: Triton compiler generates wgmma, not tcgen05.\n2. **No TMEM**: accumulators stay in registers.\n\nThese four bullets describe the world before Triton 3.6.0 landed (`2026-01-21`). The first two are no longer correct on 3.6+; see the \"Triton 3.6+ Blackwell path\" subsection above. CPU launch overhead and CUDA-graph workarounds remain workload-relevant on small-batch decode paths regardless of compiler era."}, "after": {"statement": "version_sensitive:\n id: vs-triton-3.3-blackwell-tcgen05\n\nNative Blackwell TCGen5/TMEM compiler support enters between Triton v3.2.0 and v3.3.0. In the exact tag comparison, the corresponding TCGen5 MMA, TMEM, and MMAv5-lowering symbols are absent at v3.2.0 (`9641643d`) and present at v3.3.0 (`819e9c8c`). The v3.3 conversion suite checks concrete `tcgen05.mma`, commit, TMEM, scaled-MMA, and `cta_group::2` output. See the pinned files in [`doc-triton-3.3-blackwell`](../../sources/docs/triton-3.3-blackwell.md).\n\n| v3.2.0 | Checked negative side of the native-backend boundary. |\n| v3.3.0 | First checked tag after v3.2.0 with TCGen5/TMEM operations, allocation and lowering passes, and concrete conversion tests. |\n| v3.5.0 | Tagged tree includes an explicit Gluon TCGen5/TMEM tutorial and the Blackwell block-scaled matmul tutorial; release notes also document warp-specialization work. |\n| v3.6.0 | Generalizes TCGen5 copies/layouts and MMA handling, advances aref-style warp specialization, and adds initial multi-CTA/2-CTA Gluon work. It is not the introduction boundary. |\n| v3.7.0 / v3.7.1 | v3.7.0 continues 2-CTA, multicast, and TMA work; v3.7.1 is a two-regression patch with no advertised new API or feature. |\n\nThe v3.5.0 tree provides two useful pinned examples:\n\n- [`python/tutorials/gluon/06-tcgen05.py`](https://github.com/triton-lang/triton/blob/c3c476f357f1e9768ea4e45aa5c17528449ab9ef/python/tutorials/gluon/06-tcgen05.py) explicitly allocates, loads, and stores TMEM and invokes TCGen5 MMA through Gluon.\n- [`python/tutorials/10-block-scaled-matmul.py`](https://github.com/triton-lang/triton/blob/c3c476f357f1e9768ea4e45aa5c17528449ab9ef/python/tutorials/10-block-scaled-matmul.py) demonstrates `tl.dot_scaled` for Blackwell block-scaled matmul.\n\nTriton v3.6.0 expands those foundations with broader layouts and copies and initial multi-CTA/2-CTA Gluon support. “Initial” is deliberate: v3.7.0 contains follow-on end-to-end 2-CTA, multicast, and TMA changes. See [`doc-triton-3.6-blackwell`](../../sources/docs/triton-3.6-blackwell.md) and the compact release matrix in [`data/triton-3.6-evidence.md`](../../data/triton-3.6-evidence.md)."}, "reason": {"statement": "Restore the v3.2-to-v3.3 introduction boundary and describe 3.6 as an incremental expansion.", "urls": ["https://github.com/triton-lang/triton/blob/819e9c8c29ad2ae96cbd93a1d3b8a3a0f4c8f09c/include/triton/Dialect/TritonNvidiaGPU/IR/TritonNvidiaGPUOps.td", "https://github.com/triton-lang/triton/blob/819e9c8c29ad2ae96cbd93a1d3b8a3a0f4c8f09c/test/Conversion/tritongpu_to_llvm_blackwell.mlir", "https://github.com/triton-lang/triton/compare/v3.2.0...v3.3.0", "https://github.com/triton-lang/triton/blob/c3c476f357f1e9768ea4e45aa5c17528449ab9ef/python/tutorials/gluon/06-tcgen05.py", "https://github.com/triton-lang/triton/blob/c3c476f357f1e9768ea4e45aa5c17528449ab9ef/python/tutorials/10-block-scaled-matmul.py", "https://github.com/triton-lang/triton/releases/tag/v3.6.0", "https://github.com/triton-lang/triton/releases/tag/v3.7.0", "https://github.com/triton-lang/triton/releases/tag/v3.7.1"]}} +{"path": "wiki/languages/triton-blackwell.md", "before": {"statement": "- **What is verified**: the Triton 3.6 release adds tcgen05 + TMEM lowering infrastructure (per `doc-triton-3.6-blackwell`), and tracked downstream repos are landing real Triton kernel changes for SM100 post-3.6 (per `pr-vllm-34597`, the post-refresh primary anchor — vLLM's \"[Kernel] Add FP8 KV cache support to Triton MLA decode attention\" PR, which directly modifies `@triton.jit`-decorated kernels in `vllm/v1/attention/ops/triton_decode_attention.py` doing `tl.dot(q, k)` / `tl.dot(qpe, kpe)` / `tl.dot(p, v)` matmul on `[sm100]`, shipped verbatim under `artifacts/prs/vllm/PR-34597/`). Supplementary post-refresh evidence: `pr-vllm-29339` shows the Triton 3.6 `triton_kernels` library being explicitly scoped to Blackwell production codepaths. Pre-refresh historical evidence: `pr-sglang-22079` (the Gemma4 NVFP4 attention kernel merged 2026-04-03). Together these establish that Triton 3.6+ on Blackwell is materially different from the pre-3.6 \"lacked-tcgen05 / lacked-TMEM\" story.\n\n- **`pr-vllm-34597`** (`source_category: upstream-code`) — **post-refresh primary anchor**: vLLM's \"[Kernel] Add FP8 KV cache support to Triton MLA decode attention\" PR (merged 2026-02-16, post-Triton-3.6.0 release; `architectures: [sm100]`; tags `attention`, `decode`, `fp8`, `mla`). Directly modifies actual Triton kernel files: `vllm/v1/attention/ops/triton_decode_attention.py` (the `@triton.jit`-decorated MLA decode kernel doing `tl.dot(q, k)` for attention scores, `tl.dot(qpe, kpe)` for positional contributions, and `acc += tl.dot(p, v)` for the output projection) and `vllm/v1/attention/backends/mla/triton_mla.py` (the backend wrapping it). The Triton kernel itself is shipped verbatim under [`artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py`](../../artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py) (756 lines, pinned at upstream SHA `a1257fd1`). This PR page is post-refresh — it is NOT in `data/refresh-cutoff.yaml::previous_pages_manifest`. This is the \"downstream adoption is happening\" half of AC-1.2 and the AC-1.1 \"new tracked-repo PR page demonstrating a kernel\" anchor.\n\nTogether the two anchors establish that **the 3.6+ Blackwell lowering infrastructure is real AND tracked downstream repos are landing real Triton matmul kernels for Blackwell production decode paths today** — which is the substance of the rewrite: the pre-3.6 \"lacked-tcgen05 / lacked-TMEM\" framing is no longer correct.\n\n- The anchors do not prove that EVERY plain `tl.dot` kernel on SM100 emits `tcgen05.mma` PTX. They prove that real Triton kernels with `tl.dot` matmul are landing on Blackwell-only paths in tracked downstream repos (per `pr-vllm-34597`'s `triton_decode_attention.py` kernel) and that the 3.6 release added the infrastructure those kernels lower through. Whether the lowering automatically targets `tcgen05.mma` for every shape and dtype on every Blackwell SKU is a separate question.\n- The anchors do not include explicit inspectable `tcgen05.mma` PTX dumps from a tracked-downstream merged PR. Such proof would be an even stronger anchor than what we have today; until one is found, the verified claim should be read as \"Triton 3.6+ Blackwell is real and downstream-adopted\", not \"every Triton matmul on Blackwell is now optimal\".\n\n| [`artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py`](../../artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py) | **Post-refresh AC-1.1 primary anchor**: Triton MLA decode attention kernel — `@triton.jit`-decorated, doing `tl.dot(q, k)` / `tl.dot(qpe, kpe)` / `acc += tl.dot(p, v)` matmul on `[sm100]` with FP8 KV cache support added (`pr-vllm-34597`, merged 2026-02-16). | vllm#34597 |\n| [`artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/backends/mla/triton_mla.py`](../../artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/backends/mla/triton_mla.py) | MLA backend wrapping the Triton decode kernel above — adds FP8 / FP8-E4M3 to `TritonMLABackend.supported_kv_cache_dtypes`. | vllm#34597 |\n\nThe current AC-1.1 **post-refresh primary upstream-code anchor** is `pr-vllm-34597` (above), with the actual Triton decode-attention kernel shipped verbatim. Supplementary post-refresh anchor: `pr-vllm-29339` ([`sources/prs/vllm/PR-29339.md`](../../sources/prs/vllm/PR-29339.md)), a vLLM bugfix scoping the Triton 3.6 `triton_kernels` library to `[sm100, sm90]` for the MXFP4 quantization path (no artifact bundle because the change is dispatch-gate-only)."}, "after": {"statement": "- [`pr-vllm-34597`](../../sources/prs/vllm/PR-34597.md), pinned at `a1257fd1`, adds FP8 KV-cache handling to the Triton MLA decode backend. Its verbatim kernel contains `tl.dot`, but no target guard, Triton-version requirement, TCGen5/TMEM name, or emitted PTX. The primary PR specifically motivates the backend as the MLA option on SM120; it is not an SM100-only lowering demonstration.\n\n| [`triton_decode_attention.py`](../../artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py) | Triton MLA decode kernels with `tl.dot`; PR 34597 adds FP8 cache handling. |\n| [`triton_mla.py`](../../artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/backends/mla/triton_mla.py) | Backend wrapper and supported FP8 cache dtypes. |\n\nThis verbatim excerpt from the pinned vLLM decode kernel demonstrates the page's deliberately limited downstream claim—FP8 rescaling followed by `tl.dot`, without proving a particular emitted MMA instruction:\n\n```python\nif k.dtype.is_fp8():\n k = (k.to(tl.float32) * ks).to(q.dtype)\nqk = tl.dot(q, k.to(q.dtype))\nif BLOCK_DPE > 0:\n offs_buf_kpe = kv_loc[None, :] * stride_buf_kbs\n```"}, "reason": {"statement": "Retain the genuine FP8 Triton MLA kernel example while removing architecture and lowering inferences.", "urls": ["https://github.com/vllm-project/vllm/pull/34597", "https://github.com/vllm-project/vllm/blob/a1257fd1/vllm/v1/attention/ops/triton_decode_attention.py"]}} +{"path": "wiki/languages/triton-blackwell.md", "before": {"statement": "The following table reflects benchmark snapshots from when the original page was written (Triton 3.5 era) and is preserved for historical reference. It does NOT reflect the 3.6+ tcgen05 path.\n\nA re-run on Triton 3.6 with FlashInfer-Bench is not yet available locally; future refresh rounds should update this table or remove it in favor of a pointer to the live leaderboard."}, "after": {"statement": "The live [FlashInfer-Bench leaderboard](https://bench.flashinfer.ai/), retrieved 2026-08-08, reports these author rows across 660 workloads each:\n\n| Gemini 2.5 Pro | 0.628x | 73.1% |\n| GPT-5 | 0.467x | 92.3% |\n| Claude Opus 4.1 | 0.456x | 73.1% |\n\nThe leaderboard does not attach those rows to a Triton release or identify them as a Triton-only language subset."}, "reason": {"statement": "Preserve the exact live leaderboard values while deleting the false historical/version interpretation.", "urls": ["https://bench.flashinfer.ai/"]}} +{"path": "wiki/languages/triton-blackwell.md", "before": {"statement": "```python\n@triton.jit\ndef gated_delta_net_decode(\n Q, K, V, Gate, State, Output,\n qk_dim: tl.constexpr, v_dim: tl.constexpr, d: tl.constexpr,\n):\n \"\"\"Single-token decode: O(d^2) per token.\"\"\"\n head_id = tl.program_id(0)\n # Load recurrent state S: [qk_dim*d, v_dim*d]\n s = tl.load(State + head_id * qk_dim * d * v_dim * d + offsets)\n q = tl.load(Q + offsets)\n k = tl.load(K + offsets)\n v = tl.load(V + offsets)\n g = tl.load(Gate + head_id)\n\n # Delta rule: S = g*S + k @ (v - S^T @ k)^T\n sk = tl.dot(tl.trans(s), k)\n delta_v = v - sk\n s = g * s + tl.dot(k[:, None], delta_v[None, :])\n o = tl.dot(tl.trans(s), q)\n\n tl.store(State + offsets, s)\n tl.store(Output + offsets, o)\n```"}, "after": {"statement": null}, "reason": {"statement": "The repository already provides provenance-pinned real GDN-related Triton code; retaining broken pseudocode has no teaching value.", "urls": []}} +{"path": "wiki/languages/triton-blackwell.md", "before": {"statement": "```python\n@triton.jit\ndef sparse_attention_fwd(Q, K, V, Output, TopK_Indices,\n block_size: tl.constexpr, topk: tl.constexpr):\n \"\"\"Attend to top-k sparse token blocks only.\"\"\"\n qid = tl.program_id(0)\n q = tl.load(Q + qid * d + tl.arange(0, d))\n acc = tl.zeros([d], dtype=tl.float32)\n for i in range(topk):\n bidx = tl.load(TopK_Indices + qid * topk + i)\n k_block = tl.load(K + bidx * block_size * d + offsets)\n v_block = tl.load(V + bidx * block_size * d + offsets)\n scores = tl.dot(q[None, :], tl.trans(k_block))\n # softmax + accumulate...\n```"}, "after": {"statement": null}, "reason": {"statement": "Replace the incomplete executable-looking block with links to complete provenance-pinned attention kernels.", "urls": []}} +{"path": "wiki/languages/triton-blackwell.md", "before": {"statement": "The full 42-PR universe is enumerated in `data/triton-universe.yaml`. Entries marked `captured: false` do not ship locally because they fall outside the three in-policy sub-scopes (see the policy file for reasons)."}, "after": {"statement": "The complete tracked PR universe and its captured/skipped flags are recorded in [`data/triton-universe.yaml`](../../data/triton-universe.yaml); this page does not duplicate that changing count."}, "reason": {"statement": "Remove the stale count and retain a stable pointer to the canonical ledger and capture flags.", "urls": []}} +{"path": "wiki/languages/triton-blackwell.md", "before": {"statement": "- **What is verified**: the Triton 3.6 release adds tcgen05 + TMEM lowering infrastructure (per `doc-triton-3.6-blackwell`), and tracked downstream repos are landing real Triton kernel changes for SM100 post-3.6 (per `pr-vllm-34597`, the post-refresh primary anchor — vLLM's \"[Kernel] Add FP8 KV cache support to Triton MLA decode attention\" PR, which directly modifies `@triton.jit`-decorated kernels in `vllm/v1/attention/ops/triton_decode_attention.py` doing `tl.dot(q, k)` / `tl.dot(qpe, kpe)` / `tl.dot(p, v)` matmul on `[sm100]`, shipped verbatim under `artifacts/prs/vllm/PR-34597/`). Supplementary post-refresh evidence: `pr-vllm-29339` shows the Triton 3.6 `triton_kernels` library being explicitly scoped to Blackwell production codepaths. Pre-refresh historical evidence: `pr-sglang-22079` (the Gemma4 NVFP4 attention kernel merged 2026-04-03). Together these establish that Triton 3.6+ on Blackwell is materially different from the pre-3.6 \"lacked-tcgen05 / lacked-TMEM\" story.\n\n- **`pr-vllm-34597`** (`source_category: upstream-code`) — **post-refresh primary anchor**: vLLM's \"[Kernel] Add FP8 KV cache support to Triton MLA decode attention\" PR (merged 2026-02-16, post-Triton-3.6.0 release; `architectures: [sm100]`; tags `attention`, `decode`, `fp8`, `mla`). Directly modifies actual Triton kernel files: `vllm/v1/attention/ops/triton_decode_attention.py` (the `@triton.jit`-decorated MLA decode kernel doing `tl.dot(q, k)` for attention scores, `tl.dot(qpe, kpe)` for positional contributions, and `acc += tl.dot(p, v)` for the output projection) and `vllm/v1/attention/backends/mla/triton_mla.py` (the backend wrapping it). The Triton kernel itself is shipped verbatim under [`artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py`](../../artifacts/prs/vllm/PR-34597/key-files/vllm/v1/attention/ops/triton_decode_attention.py) (756 lines, pinned at upstream SHA `a1257fd1`). This PR page is post-refresh — it is NOT in `data/refresh-cutoff.yaml::previous_pages_manifest`. This is the \"downstream adoption is happening\" half of AC-1.2 and the AC-1.1 \"new tracked-repo PR page demonstrating a kernel\" anchor.\n\nSupplementary post-refresh anchor: [`pr-vllm-29339`](../../sources/prs/vllm/PR-29339.md) — vLLM bugfix that scopes the upstream `triton_kernels` library (the `triton-lang/triton/python/triton_kernels` collection shipped with Triton 3.6) to `[sm100, sm90]` for the MXFP4 quantization path. Modifies only a dispatch gate (`vllm/model_executor/layers/quantization/mxfp4.py`), which is why `pr-vllm-34597` is the primary anchor and `pr-vllm-29339` is supplementary.\n\nPre-refresh historical anchors (retained as supplementary context, not as AC-1.1 \"new tracked-repo PR page\" evidence on their own):\n\n- [`pr-sglang-22079`](../../sources/prs/sglang/PR-22079.md) — Gemma4 NVFP4 SGLang `extend_attention` Triton kernel doing actual `tl.dot(q,k)` / `tl.dot(p,v)` matmul on `[sm100, sm90]`, merged 2026-04-03. Strongest in-corpus example of a real `tl.dot` Triton matmul landing for SM100 post-3.6, but pre-refresh per `previous_pages_manifest`.\n- [`pr-sglang-21019`](../../sources/prs/sglang/PR-21019.md) — Qwen3.5 GDN projection fused split/reshape/cat kernel merged 2026-03-20. `tl.load`/`tl.store` only (memory rearrangement, no `tl.dot`); demonstrates \"Triton on SM100 post-3.6\" but not the matmul lowering path.\n\nThe current AC-1.1 **post-refresh primary upstream-code anchor** is `pr-vllm-34597` (above), with the actual Triton decode-attention kernel shipped verbatim. Supplementary post-refresh anchor: `pr-vllm-29339` ([`sources/prs/vllm/PR-29339.md`](../../sources/prs/vllm/PR-29339.md)), a vLLM bugfix scoping the Triton 3.6 `triton_kernels` library to `[sm100, sm90]` for the MXFP4 quantization path (no artifact bundle because the change is dispatch-gate-only)."}, "after": {"statement": null}, "reason": {"statement": "Refresh-round administration is stale and irrelevant to the durable technical claim.", "urls": []}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "`tcgen05.mma` is the Blackwell (SM100/SM100a) matrix-multiply-accumulate instruction that replaces Hopper's `wgmma.mma_async`. The name stands for **Tensor Core Generation 05**. NVIDIA also refers to the higher-level abstraction as **UMMA** (Unified Matrix Multiply-Accumulate) in the CUTLASS framework."}, "after": {"statement": null}, "reason": {"statement": "Retain the official tcgen05 name and CUTLASS namespace without inventing an acronym expansion.", "urls": ["https://github.com/NVIDIA/cutlass/tree/e406c186f510a15091cce01f782020ceb7ba8eb5"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "1. **No warpgroup synchronization overhead** -- one elected thread (typically lane 0 of warp 0) issues the MMA."}, "after": {"statement": "| Completion | WGMMA commit/wait groups | `tcgen05.commit` plus an mbarrier wait |\n\nSingle-thread issue reduces the number of issuing threads, but it does not remove asynchronous completion, operand-lifetime, or inter-thread ordering requirements.\n\n`tcgen05.mma` is asynchronous. Two mechanisms serve different purposes:\n\n1. `tcgen05.commit.cta_group::N.mbarrier::arrive::one.b64` makes an mbarrier track completion of prior asynchronous tcgen05 operations issued by the executing thread. Waiting on that mbarrier observes completion.\n2. `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` order tcgen05 operations across an execution-ordering handoff and constrain code motion. A fence is not a completion wait.\n\nA cross-thread result handoff therefore needs both the applicable completion protocol and the applicable fence/execution-ordering protocol. Likewise, a pipelined mainloop must not release or overwrite an SMEM stage until the asynchronous MMA has finished consuming it."}, "reason": {"statement": "Separate issue granularity from synchronization and completion requirements.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "| Operand A source | Registers or SMEM | Shared memory only |\n\n| Matrix load | ldmatrix to registers | Direct from SMEM (no ldmatrix) |"}, "after": {"statement": "The programming-model shift from Hopper WGMMA is precise:\n\n| Issue granularity | Warpgroup | One thread for `cta_group::1` or `cta_group::2` |\n| D accumulator | Per-thread registers | Tensor Memory (TMEM) |\n| A location | Register or SMEM forms, depending on instruction | SMEM descriptor or TMEM address |\n| B location | SMEM descriptor | SMEM descriptor |"}, "reason": {"statement": "Restore the actual operand-location alternatives and avoid a mandatory ldmatrix claim.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "| Synchronization | Warpgroup-scoped barriers | Fully async, fence-based |\n\n3. **Fence-based completion** -- the producer must insert explicit fences before reading results from TMEM.\n\nFences are **mandatory** for correctness. The hardware does not implicitly synchronize between MMA and TMEM reads/writes.\n\nInsert before reading MMA results from TMEM:\n\n```cuda\n// Fence before CTA sync and TMEM reads after the completion mechanism.\n__device__ void fence_before_tmem_read() {\n asm volatile(\"tcgen05.fence::before_thread_sync;\");\n __syncthreads(); // Ensure all threads see the fence\n}\n```\n\n```ptx\n// Fence before reading TMEM (most common)\ntcgen05.fence::before_thread_sync;\n\n// Fence after CTA sync before issuing dependent tcgen05 operations\ntcgen05.fence::after_thread_sync;\n```"}, "after": {"statement": "`tcgen05.mma` is asynchronous. Two mechanisms serve different purposes:\n\n1. `tcgen05.commit.cta_group::N.mbarrier::arrive::one.b64` makes an mbarrier track completion of prior asynchronous tcgen05 operations issued by the executing thread. Waiting on that mbarrier observes completion.\n2. `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` order tcgen05 operations across an execution-ordering handoff and constrain code motion. A fence is not a completion wait.\n\nA cross-thread result handoff therefore needs both the applicable completion protocol and the applicable fence/execution-ordering protocol. Likewise, a pipelined mainloop must not release or overwrite an SMEM stage until the asynchronous MMA has finished consuming it."}, "reason": {"statement": "Teach completion and ordering as separate protocols.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "| `tcgen05.mma.kind::f16` | FP16/BF16 | FP16/BF16 | FP32 | None | m128n256k16 | Standard half-precision |\n\n| `tcgen05.mma.kind::f8f6f4` | FP8/FP6/FP4 | FP8/FP6/FP4 | FP32 | Block (UE8M0) | m128n256k32 | Narrow precision with native block scaling |\n\n| `tcgen05.mma.kind::mxf8` | MXFP8 | MXFP8 | FP32 | MX (E8M0) | m128n256k32 | Microscaling FP8 |\n| `tcgen05.mma.kind::mxf4` | MXFP4 | MXFP4 | FP32 | MX (E8M0) | m128n256k64 | Microscaling FP4 |\n| `tcgen05.mma.kind::mxf4nvf4` | NVFP4 | MXFP4 | FP32 | Mixed | m128n256k64 | Mixed NVFP4/MXFP4 |"}, "after": {"statement": "PTX ISA 9.0 divides dense `tcgen05.mma` into these grammar groups:\n\n| Floating point, without block scaling | `f16`, `tf32`, `f8f6f4` |\n| Floating point, with block scaling | `mxf8f6f4`, `mxf4`, `mxf4nvf4` |\n| Integer | `i8` |\n\nBlock-scaled forms add `.block_scale` and accept separate TMEM addresses for A and B scale factors. `f8f6f4` is not the block-scaled MX kind, and `mxf8` is not a dense kind token in this grammar."}, "reason": {"statement": "Replace the mixed taxonomy with the exact PTX grammar groups and avoid oversimplified type claims.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "- **BF16/FP16**: M=128, N=256, K=16\n- **TF32**: M=128, N=256, K=8\n- **FP8/FP6/FP4**: M=128, N=256, K=32\n- **MXFP4/NVFP4**: M=128, N=256, K=64\n\n- **BF16/FP16**: M=256, N=256, K=16\n- **TF32**: M=256, N=256, K=8\n- **FP8/FP6/FP4**: M=256, N=256, K=32\n- **MXFP4/NVFP4**: M=256, N=256, K=64\n\nThe M dimension doubles because each SM contributes 128 rows from its own TMEM partition."}, "after": {"statement": "M and N are encoded in the instruction descriptor (`idesc`) and are constrained by kind, CTA group, layouts, and target ISA. Consequently, names such as m128n256k16 and m256n256k16 are useful maximum-shape examples for F16/BF16 configurations, not the only legal M and N values. `cta_group::1` uses current-CTA resources; `cta_group::2` can also access the paired peer CTA's SMEM and TMEM resources. All `tcgen05` instructions in a kernel must use the same CTA-group value."}, "reason": {"statement": "State group ownership separately from descriptor-selected shapes and label maxima as maxima.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instruction-descriptor"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "```cuda\n// Single-thread MMA issuance pattern\n__device__ void issue_mma(uint32_t tmem_addr, uint64_t smem_desc_a, uint64_t smem_desc_b) {\n // Only one thread issues the MMA\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 0;\"\n :\n : \"r\"(tmem_addr),\n \"l\"(smem_desc_a),\n \"l\"(smem_desc_b),\n \"r\"(0) // scale descriptor (unused for f16)\n );\n }\n}\n```\n\n```ptx\n// Issue a 128x256x16 BF16 MMA\n// Operand A: shared memory descriptor\n// Operand B: shared memory descriptor\n// Accumulator: TMEM address\ntcgen05.mma.cta_group::1.kind::f16 [tmem_addr], desc_a, desc_b, idesc, 0;\n```\n\n```ptx\n// Issue a 256x256x16 BF16 MMA across two paired CTAs\n// cta_group::2 indicates cooperative mode\ntcgen05.mma.cta_group::2.kind::f16 [tmem_addr], desc_a, desc_b, idesc, 0;\n```\n\n```ptx\n// FP8 with native UE8M0 block scaling\n// scale_desc encodes the per-block scale factors\ntcgen05.mma.cta_group::1.kind::f8f6f4 [tmem_addr], desc_a, desc_b, idesc, scale_desc;\n```\n\n```cuda\n__device__ void mma_bf16_128x256x16(\n uint32_t tmem_addr,\n uint64_t desc_a,\n uint64_t desc_b\n) {\n if (threadIdx.x == 0) {\n // First MMA: zero-initialize accumulator\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 0;\"\n :\n : \"r\"(tmem_addr), \"l\"(desc_a), \"l\"(desc_b), \"r\"(0)\n );\n }\n}\n\n__device__ void mma_bf16_accumulate(\n uint32_t tmem_addr,\n uint64_t desc_a,\n uint64_t desc_b\n) {\n if (threadIdx.x == 0) {\n // Subsequent MMAs: accumulate into existing TMEM\n // The enable_accumulate flag controls whether to add to or overwrite TMEM\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 1;\" // last arg 1 = accumulate\n :\n : \"r\"(tmem_addr), \"l\"(desc_a), \"l\"(desc_b), \"r\"(0)\n );\n }\n}\n```"}, "after": {"statement": null}, "reason": {"statement": "Remove invalid executable-looking examples and retain the normative grammar with a vendor example link.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "```cuda\n__device__ void gemm_mainloop(/* params */) {\n for (int k_tile = 0; k_tile < num_k_tiles; ++k_tile) {\n // 1. Wait for operand data to arrive in SMEM\n wait_barrier(k_tile % NUM_STAGES);\n\n // 2. Issue MMA (single thread)\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 1;\"\n :\n : \"r\"(tmem_addr),\n \"l\"(make_smem_desc(smem_a, k_tile)),\n \"l\"(make_smem_desc(smem_b, k_tile)),\n \"r\"(0)\n );\n }\n\n // 3. Release SMEM buffer for next TMA load\n if (threadIdx.x == 0) {\n arrive_barrier((k_tile + 1) % NUM_STAGES);\n }\n }\n\n // 4. CRITICAL: Fence before reading accumulator from TMEM\n asm volatile(\"tcgen05.fence::before_thread_sync;\");\n __syncthreads();\n\n // 5. Now safe to read results from TMEM\n read_tmem_accumulator(tmem_addr, output);\n}\n```"}, "after": {"statement": null}, "reason": {"statement": "A partial pipeline with unsafe lifetime rules is more misleading than the normative sequence.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "```cuda\n// ---- HOPPER (SM90): wgmma ----\n// Requires warpgroup-scoped execution\n// All 128 threads in a warpgroup participate\n__device__ void hopper_mma() {\n // Load A matrix into registers via ldmatrix\n uint32_t a_frag[4];\n asm volatile(\"ldmatrix.sync.aligned.m8n8.x4.shared.b16 \"\n \"{%0,%1,%2,%3}, [%4];\"\n : \"=r\"(a_frag[0]), \"=r\"(a_frag[1]),\n \"=r\"(a_frag[2]), \"=r\"(a_frag[3])\n : \"r\"(smem_addr));\n\n // Issue wgmma -- warpgroup scope, register accumulator\n asm volatile(\"wgmma.mma_async.sync.aligned.m64n256k16.f32.bf16.bf16 \"\n \"{%0, %1, ...}, \" // register accumulators (128+ registers!)\n \"{%N, %N+1, ...}, \" // A operand in registers\n \"desc_b, ...;\"\n : \"+f\"(acc[0]), \"+f\"(acc[1]), ...\n : ...);\n\n // Commit and wait\n asm volatile(\"wgmma.commit_group.sync.aligned;\");\n asm volatile(\"wgmma.wait_group.sync.aligned 0;\");\n // Accumulators now in registers -- high register pressure\n}\n\n// ---- BLACKWELL (SM100): tcgen05 ----\n// Single-thread issuance, TMEM accumulator\n__device__ void blackwell_mma() {\n // No ldmatrix needed -- reads directly from SMEM\n // No register allocation for accumulators\n\n // Single thread issues MMA\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 1;\"\n :\n : \"r\"(tmem_addr), // accumulator in TMEM (not registers!)\n \"l\"(desc_a), // A from SMEM descriptor\n \"l\"(desc_b), // B from SMEM descriptor\n \"r\"(0)\n );\n }\n\n // Fence + sync before reading results\n asm volatile(\"tcgen05.fence::before_thread_sync;\");\n __syncthreads();\n // Read from TMEM -- registers free for other work\n}\n```"}, "after": {"statement": null}, "reason": {"statement": "Replace executable-looking pseudo-assembly with a precise semantic comparison table.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "tcgen05.mma requires **128-byte swizzled** shared memory layouts for both operands. Non-swizzled or 64-byte swizzled layouts will produce incorrect results silently."}, "after": {"statement": "The tcgen05 shared-memory descriptor is a 64-bit runtime value. PTX ISA 9.0 assigns fields for the encoded base address, leading dimension, stride dimension, fixed bits, base offset, leading-dimension mode, and a three-bit swizzle mode.\n\nValid swizzle encodings include no swizzle, 128-byte, 64-byte, and 32-byte layouts (plus a 128-byte/32-byte-atomic mode). Values 3, 5, and 7 are invalid; ordinary 128-byte swizzling uses value 2. A layout must satisfy the addressing and alignment constraints for its chosen mode. Although 128-byte swizzling can materially improve a particular GEMM, it is not a universal correctness requirement."}, "reason": {"statement": "Distinguish valid layouts from performance-sensitive layout choice.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-shared-memory-descriptor"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "```cuda\n// Shared memory descriptor construction for tcgen05\n// The descriptor encodes: base address, stride, swizzle mode, dimensions\n__device__ uint64_t make_smem_desc(void* smem_ptr, int stride_bytes) {\n uint64_t desc = 0;\n uint32_t addr = static_cast(__cvta_generic_to_shared(smem_ptr));\n\n // Encode base address (bits 0-13)\n desc |= (uint64_t)(addr >> 4);\n // Encode leading dimension stride (bits 16-29)\n desc |= (uint64_t)((stride_bytes >> 4) & 0x3FFF) << 16;\n // Encode 128-byte swizzle mode (bits 62-63) -- MANDATORY for tcgen05\n desc |= (uint64_t)(3) << 62; // 3 = 128-byte swizzle\n\n return desc;\n}\n```"}, "after": {"statement": null}, "reason": {"statement": "Direct users to the complete table rather than preserving a subtly corrupt descriptor builder.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-shared-memory-descriptor"]}} +{"path": "wiki/hardware/tcgen05-mma.md", "before": {"statement": "| + Persistent kernel + CLC | 1476 | 98% |"}, "after": {"statement": "Gau Nernst reports the following results for M=N=K=4096 on a Modal B200, using PyTorch 2.9.1 with CUDA 13. Values are measurements for that setup, not architecture-wide guarantees.\n\n| cuBLAS | 1506.74 | 100% |\n| v1a: basic tcgen05 + 2D 16B TMA | 254.62 | 17% |\n| v1b: 3D 16B TMA | 252.81 | 17% |\n| v2a: 2D 128B TMA | 681.20 | 45% |\n| v2b: 3D 128B TMA | 695.43 | 46% |\n| v3: pipelining | 939.61 | 62% |\n| v4: warp specialization | 1208.83 | 80% |\n| v5: 2-SM MMA | 1302.29 | 86% |\n| v6: persistent, static scheduling | 1475.93 | 98% |\n\nThe v6 result did not use Cluster Launch Control; the author lists CLC and threadblock swizzling as unimplemented follow-up ideas."}, "reason": {"statement": "Preserve the measurement while restoring the actual scheduling method.", "urls": ["https://gau-nernst.github.io/tcgen05/"]}} +{"path": "wiki/hardware/2sm-cooperative.md", "before": {"statement": "Blackwell enables two SMs within a TPC to cooperatively execute a single larger MMA, doubling the effective compute tile size to m256×n256×k16."}, "after": {"statement": "PTX defines a CTA pair as two CTAs in the same cluster whose `%cluster_ctarank` values differ only in the low bit. With `cta_group::2`, one thread from either CTA can initiate a whole `tcgen05.mma`; the peer CTA must still be active. The operation accesses Tensor Memory belonging to both the current CTA and its peer.\n\nAllocation management differs from MMA issue. A `tcgen05.alloc` or `tcgen05.dealloc` for `cta_group::2` is issued collectively by two warps, one in each CTA. All tcgen05 instructions in the kernel must use the same CTA-group value.\n\n`cta_group::2` selects pair-level resources; it does not by itself select one fixed MxNxK shape. The instruction descriptor (`idesc`) encodes M, N, exact operand and accumulator types, sparsity, and related operation details. Legal values depend on the kind, data-path layout, CTA group, and target ISA.\n\nFor example, m256xn256xk16 is a useful maximum F16/BF16 configuration, but PTX also defines group-2 layouts with other M/N values. Do not infer that every pair-level MMA is created by mechanically doubling a group-1 M dimension."}, "reason": {"statement": "Describe pair-level resource scope separately from shape selection.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-data-path-layout-organization", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-issue-granularity"]}} +{"path": "wiki/hardware/2sm-cooperative.md", "before": {"statement": "```\nTPC (Two Processing Clusters)\n├── SM 0: CTA 0 — issues tcgen05.mma with cta_group::2\n│ ├── Shared Memory A (rows 0-127)\n│ └── TMEM (columns 0-255)\n└── SM 1: CTA 1 — cooperates on same MMA\n ├── Shared Memory A (rows 128-255)\n └── TMEM (columns 256-511)\n```"}, "after": {"statement": null}, "reason": {"statement": "Replace the misleading topology diagram with normative pair and issue rules.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-data-path-layout-organization"]}} +{"path": "wiki/hardware/2sm-cooperative.md", "before": {"statement": "```ptx\n// 2-SM cooperative MMA\ntcgen05.mma.cta_group::2.kind::f16\n [tmem_addr], descA, descB, idescC, idescD, ...;\n```"}, "after": {"statement": null}, "reason": {"statement": "Link to the already verified normative grammar on the tcgen05 page instead of duplicating invalid code.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/hardware/2sm-cooperative.md", "before": {"statement": "1. **Identical shared memory layouts** across both CTAs\n2. `shared::cluster` mbarrier signaling between the two CTAs\n\n4. Each CTA contributes half the M-dimension"}, "after": {"statement": "PTX defines a CTA pair as two CTAs in the same cluster whose `%cluster_ctarank` values differ only in the low bit. With `cta_group::2`, one thread from either CTA can initiate a whole `tcgen05.mma`; the peer CTA must still be active. The operation accesses Tensor Memory belonging to both the current CTA and its peer.\n\nAllocation management differs from MMA issue. A `tcgen05.alloc` or `tcgen05.dealloc` for `cta_group::2` is issued collectively by two warps, one in each CTA. All tcgen05 instructions in the kernel must use the same CTA-group value.\n\nThe complete operand grammar, including the eight-register disable-output-lane vector used by `cta_group::2`, is documented on the related [tcgen05.mma page](tcgen05-mma.md)."}, "reason": {"statement": "Replace the invented checklist with direct ISA invariants.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-issue-granularity", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/hardware/2sm-cooperative.md", "before": {"statement": "- Large GEMM problems where M ≥ 256\n- Compute-bound kernels where peak FLOPS matters\n- Combined with persistent scheduling for maximum throughput"}, "after": {"statement": "In Gau Nernst's M=N=K=4096 experiment on a Modal B200 with PyTorch 2.9.1 and CUDA 13, v4 warp specialization reports 1208.83 TFLOP/s and v5 2-SM MMA reports 1302.29 TFLOP/s. Relative to the same 1506.74-TFLOP/s cuBLAS result, those are approximately 80.2% and 86.4%, or a 7.7% relative increase from v4 to v5.\n\nThat result establishes a gain for one kernel and setup, not a universal threshold. Choose between group 1 and group 2 by benchmarking the target shapes and accounting for CTA pairing, data reuse, layout, occupancy, pipeline stages, and epilogue cost. Persistence is an independent scheduling choice, not a condition that guarantees maximum throughput."}, "reason": {"statement": "Replace categorical advice with a measurement-and-resource tradeoff checklist.", "urls": ["https://gau-nernst.github.io/tcgen05/"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "- **Operand loading**: ldmatrix + registers vs direct SMEM access\n- **Synchronization**: warpgroup barriers vs async fences"}, "after": {"statement": "Port the programming model, not just the opcode:\n\n| MMA issue | Warpgroup collective | One thread for group-1 or group-2 MMA |\n| D accumulator | Per-thread registers | TMEM |\n| A operand | SMEM-descriptor or register forms, depending on instruction | SMEM-descriptor or TMEM-address forms |\n| B operand | SMEM descriptor | SMEM descriptor |\n| MMA completion | Commit/wait groups | `tcgen05.commit` plus mbarrier wait |\n| Cross-thread ordering | WGMMA-specific rules | tcgen05 fences composed with an execution-ordering operation |\n| Narrow floating formats | FP8 WGMMA forms | FP8/FP6/FP4 plus block-scaled MX/NVFP4 kinds |\n\nThe exact old WGMMA form matters. Do not assume every Hopper kernel loads A through `ldmatrix`: descriptor-sourced WGMMA forms already read A from SMEM. Likewise, tcgen05 can source A from SMEM or TMEM.\n\n`tcgen05.mma` is asynchronous. `tcgen05.commit.cta_group::N.mbarrier::arrive::one.b64` makes an mbarrier track prior MMA work issued by the current thread; waiting on that barrier observes completion. A `tcgen05.fence` is an ordering and code-motion primitive, not a completion wait, so fence plus `__syncthreads()` is not a substitute for commit/mbarrier."}, "reason": {"statement": "Make migration conditional on the exact old and new instruction forms and separate completion from ordering.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "```\n[ ] Replace wgmma.mma_async with tcgen05.mma\n[ ] Move accumulators from registers to TMEM (alloc/dealloc)\n[ ] Remove ldmatrix operations (tcgen05 reads directly from SMEM)\n[ ] Change SMEM swizzle from 64B to 128B\n[ ] Replace warpgroup commit/wait with tcgen05 fences\n[ ] Update warp specialization roles (fewer warps needed for MMA)\n[ ] Update tile sizes (128xN -> consider 256xN with 2-SM)\n[ ] Add TMEM lifecycle management (alloc at start, dealloc at end)\n[ ] Update epilogue to read from TMEM instead of registers\n```"}, "after": {"statement": "1. Identify the exact WGMMA operand form, accumulator type, shape, and group-completion points in the SM90 kernel.\n2. Choose a legal tcgen05 kind, A source, CTA group, instruction descriptor, and data-path layout for the SM100 target.\n3. Replace register-resident D with a TMEM allocation. Group-1 allocation/deallocation is warp-collective; group 2 requires one warp in each CTA of the pair.\n4. Keep A/B backing storage unchanged until all asynchronous MMA consumers have completed.\n5. Replace WGMMA group completion with `tcgen05.commit` and an mbarrier wait. Add tcgen05 fences only where an execution-ordering handoff must order tcgen05-visible state across threads or CTAs.\n6. Transfer completed accumulator values from TMEM to registers with `tcgen05.ld`, observe its completion/access rules, then run the epilogue.\n7. Deallocate every dynamic TMEM allocation before kernel exit. Use the same `cta_group` value for all tcgen05 instructions in the kernel.\n8. Retune CTA/cluster shapes, pipeline stages, thread roles, descriptors, and epilogue scheduling on the target workload."}, "reason": {"statement": "Replace categorical substitutions with a dependency-ordered audit checklist.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-shared-memory-descriptor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "```cuda\n// SM90 GEMM kernel using wgmma\n__global__ void hopper_gemm(\n const half* A, const half* B, half* C,\n int M, int N, int K\n) {\n extern __shared__ char smem[];\n half* smem_a = reinterpret_cast(smem);\n half* smem_b = smem_a + TILE_M * TILE_K;\n\n // Register accumulators -- HIGH REGISTER PRESSURE\n float acc[MMA_M_FRAGS][MMA_N_FRAGS]; // 128+ registers!\n for (int i = 0; i < MMA_M_FRAGS; ++i)\n for (int j = 0; j < MMA_N_FRAGS; ++j)\n acc[i][j] = 0.0f;\n\n // Mainloop\n for (int k = 0; k < K / TILE_K; ++k) {\n // Load A to SMEM (TMA or cp.async)\n tma_load(smem_a, A, tile_m, k);\n tma_load(smem_b, B, k, tile_n);\n\n // Load A fragment from SMEM to registers via ldmatrix\n uint32_t a_frag[4];\n asm volatile(\n \"ldmatrix.sync.aligned.m8n8.x4.shared.b16 \"\n \"{%0,%1,%2,%3}, [%4];\"\n : \"=r\"(a_frag[0]), \"=r\"(a_frag[1]),\n \"=r\"(a_frag[2]), \"=r\"(a_frag[3])\n : \"r\"(smem_a_addr)\n );\n\n // Issue wgmma -- ALL 128 THREADS IN WARPGROUP participate\n asm volatile(\n \"wgmma.mma_async.sync.aligned.m64n256k16.f32.bf16.bf16 \"\n \"{%0, %1, %2, %3, %4, %5, %6, %7, ...}, \" // acc registers\n \"{%N, %N+1, %N+2, %N+3}, \" // A in registers\n \"desc_b, ...\" // B descriptor\n : \"+f\"(acc[0][0]), \"+f\"(acc[0][1]), ...\n : \"r\"(a_frag[0]), ...\n );\n\n // Commit and wait for warpgroup\n asm volatile(\"wgmma.commit_group.sync.aligned;\");\n asm volatile(\"wgmma.wait_group.sync.aligned 0;\");\n }\n\n // Epilogue: accumulators already in registers\n // Write directly to GMEM (or through SMEM for vectorized stores)\n for (int i = 0; i < MMA_M_FRAGS; ++i)\n for (int j = 0; j < MMA_N_FRAGS; ++j)\n C[row + i][col + j] = (half)acc[i][j];\n}\n```"}, "after": {"statement": null}, "reason": {"statement": "Use an exact semantic mapping and pinned CUTLASS examples rather than fabricated assembly.", "urls": []}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "```cuda\n// SM100 GEMM kernel using tcgen05\n__global__ void blackwell_gemm(\n const half* A, const half* B, half* C,\n int M, int N, int K\n) {\n extern __shared__ char smem[];\n half* smem_a = reinterpret_cast(smem);\n half* smem_b = smem_a + TILE_M * TILE_K;\n\n // TMEM accumulator -- NO REGISTER PRESSURE\n __shared__ uint32_t s_tmem_acc;\n if (threadIdx.x == 0) {\n uint32_t smem_addr =\n static_cast(__cvta_generic_to_shared(&s_tmem_acc));\n asm volatile(\n \"tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;\"\n :: \"r\"(smem_addr), \"r\"(256) // 256 columns for 128x256 tile\n );\n }\n __syncthreads();\n uint32_t tmem_acc = s_tmem_acc;\n\n // Zero TMEM accumulator\n tmem_zero(tmem_acc, 256);\n\n // Mainloop\n for (int k = 0; k < K / TILE_K; ++k) {\n // TMA load with 128B swizzle (mandatory for tcgen05)\n tma_load_128b_swizzle(smem_a, A, tile_m, k);\n tma_load_128b_swizzle(smem_b, B, k, tile_n);\n wait_barrier();\n\n // NO ldmatrix -- tcgen05 reads directly from SMEM\n // SINGLE THREAD issues MMA (not warpgroup)\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 1;\"\n :\n : \"r\"(tmem_acc),\n \"l\"(make_smem_desc_128b(smem_a)),\n \"l\"(make_smem_desc_128b(smem_b)),\n \"r\"(0)\n );\n }\n // NO commit/wait -- fully async, fence-based\n }\n\n // Fence before reading TMEM (replaces wgmma.wait_group)\n asm volatile(\"tcgen05.fence::before_thread_sync;\");\n __syncthreads();\n\n // Epilogue: read from TMEM, then write to GMEM\n float4 acc_vals = tmem_load_f32x4(tmem_acc + col_offset);\n // Apply bias, activation, etc.\n store_output(acc_vals, C, row, col);\n\n // Deallocate TMEM (no equivalent needed on Hopper)\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;\"\n :\n : \"r\"(tmem_acc), \"r\"(256)\n );\n }\n}\n```"}, "after": {"statement": null}, "reason": {"statement": "Remove an unsafe end-to-end example that cannot be repaired without becoming a full kernel.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "**Before (Hopper):** Load A operand from SMEM to registers.\n\n```cuda\n// Hopper: ldmatrix loads 8x8 matrix fragments into registers\nuint32_t a_frag[4];\nasm volatile(\n \"ldmatrix.sync.aligned.m8n8.x4.shared.b16 \"\n \"{%0,%1,%2,%3}, [%4];\"\n : \"=r\"(a_frag[0]), \"=r\"(a_frag[1]),\n \"=r\"(a_frag[2]), \"=r\"(a_frag[3])\n : \"r\"(smem_addr)\n);\n```\n\n**After (Blackwell):** No equivalent needed. tcgen05 reads A directly from SMEM via descriptor.\n\n```cuda\n// Blackwell: just construct the SMEM descriptor\nuint64_t desc_a = make_smem_desc_128b(smem_a_ptr);\n// Pass desc_a directly to tcgen05.mma -- no register staging\n```"}, "after": {"statement": "Port the programming model, not just the opcode:\n\n| MMA issue | Warpgroup collective | One thread for group-1 or group-2 MMA |\n| D accumulator | Per-thread registers | TMEM |\n| A operand | SMEM-descriptor or register forms, depending on instruction | SMEM-descriptor or TMEM-address forms |\n| B operand | SMEM descriptor | SMEM descriptor |\n| MMA completion | Commit/wait groups | `tcgen05.commit` plus mbarrier wait |\n| Cross-thread ordering | WGMMA-specific rules | tcgen05 fences composed with an execution-ordering operation |\n| Narrow floating formats | FP8 WGMMA forms | FP8/FP6/FP4 plus block-scaled MX/NVFP4 kinds |\n\nThe exact old WGMMA form matters. Do not assume every Hopper kernel loads A through `ldmatrix`: descriptor-sourced WGMMA forms already read A from SMEM. Likewise, tcgen05 can source A from SMEM or TMEM."}, "reason": {"statement": "Make operand migration a form-by-form decision.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-instructions-wgmma-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "**After (Blackwell):** 128-byte swizzle is mandatory.\n\n```cuda\n// Blackwell TMA descriptor: MUST use 128B swizzle\nCUtensorMap desc = create_tma_desc(ptr, M, N, tile_m, tile_n,\n CU_TENSOR_MAP_SWIZZLE_128B);\n```"}, "after": {"statement": "`tcgen05.alloc` writes a 32-bit TMEM address to shared memory. Allocation size is expressed in columns, in power-of-two multiples permitted by PTX. It is a synchronous warp instruction: a lane-0-only call is invalid. `tcgen05.dealloc` has the same issue granularity, and PTX requires all allocated TMEM to be deallocated before kernel exit—not only in persistent kernels.\n\nThe MMA issuer and the allocation participants are different concepts. One thread initiates a group-1 MMA, but one full warp collectively allocates or deallocates its TMEM. A group-2 allocation uses one warp from each peer CTA."}, "reason": {"statement": "Make 128B a benchmarkable layout option rather than a correctness mandate.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-shared-memory-descriptor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "**Before (Hopper):**\n\n```cuda\n// Hopper: all 128 threads in warpgroup issue wgmma\nasm volatile(\n \"wgmma.mma_async.sync.aligned.m64n256k16.f32.bf16.bf16 \"\n \"{%0,%1,...}, {%N,...}, desc_b, ...;\"\n : \"+f\"(acc[0]), \"+f\"(acc[1]), ...\n : \"r\"(a_frag[0]), ...\n);\nasm volatile(\"wgmma.commit_group.sync.aligned;\");\n```\n\n**After (Blackwell):**\n\n```cuda\n// Blackwell: single thread issues tcgen05\nif (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 1;\"\n :\n : \"r\"(tmem_acc), \"l\"(desc_a), \"l\"(desc_b), \"r\"(0)\n );\n}\n// No commit needed -- fully async\n```"}, "after": {"statement": null}, "reason": {"statement": "Replace incomplete assembly with a normative lifecycle sequence.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "**After (Blackwell):**\n\n```cuda\n// Blackwell: fence before reading TMEM\nasm volatile(\"tcgen05.fence::before_thread_sync;\");\n__syncthreads();\n// TMEM accumulators now ready for reading\n```"}, "after": {"statement": "`tcgen05.mma` is asynchronous. `tcgen05.commit.cta_group::N.mbarrier::arrive::one.b64` makes an mbarrier track prior MMA work issued by the current thread; waiting on that barrier observes completion. A `tcgen05.fence` is an ordering and code-motion primitive, not a completion wait, so fence plus `__syncthreads()` is not a substitute for commit/mbarrier."}, "reason": {"statement": "Preserve the WGMMA analogy while mapping it to the correct Blackwell mechanism.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "```\nWarp 0-3: Warpgroup 0 -- MMA producer (all 128 threads issue wgmma)\nWarp 4-7: Warpgroup 1 -- MMA producer (backup/double-buffer)\nWarp 8-11: Data movement (TMA loads, SMEM management)\nWarp 12: Tile scheduler\n\nTotal: 13+ warps, 416+ threads\n```\n\n```\nWarp 0: MMA producer (single thread issues tcgen05)\nWarp 1-2: TMA data movement (load A, load B, manage barriers)\nWarp 3: Epilogue (read TMEM, apply post-ops, store to GMEM)\nWarp 4: Tile scheduler / CLC management\n\nTotal: 5 warps, 160 threads (can be fewer)\n```"}, "after": {"statement": null}, "reason": {"statement": "Replace invented totals with role-level design guidance.", "urls": []}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "| m64 x n256 x k16 | m128 x n256 x k16 | m256 x n256 x k16 |\n| m64 x n128 x k16 | m128 x n128 x k16 | m256 x n128 x k16 |\n\nBlackwell's base MMA tile is 2x larger in M (128 vs 64). When migrating:\n- CTA tile size of 128x256 maps naturally to a single tcgen05 MMA\n- CTA tile size of 64x256 on Hopper should be doubled to 128x256\n- For 2-SM mode, consider 256x256 tiles"}, "after": {"statement": "Do not mechanically convert every 64-byte swizzle to 128-byte swizzling. The tcgen05 shared-memory descriptor defines valid no-swizzle, 128B, 64B, and 32B modes, subject to mode-specific alignment and layout constraints. The 128B choice can be much faster for a particular tile, but it is not a universal correctness condition.\n\nSimilarly, there is no universal Hopper-to-Blackwell rule that doubles M. WGMMA and tcgen05 each expose multiple shapes; tcgen05 M/N are encoded in `idesc` and constrained by kind, layout, CTA group, and target ISA. Treat m128xn256xk16 and m256xn256xk16 as useful F16/BF16 maximum examples, not a complete migration table."}, "reason": {"statement": "Turn mechanical tile substitution into a resource-aware retuning step.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-data-path-layout-organization", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-shared-memory-descriptor"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "1. **Forgetting 128B swizzle**: The most common silent-failure bug. wgmma works with 64B swizzle; tcgen05 does not. Results will be numerically wrong but the kernel won't crash.\n\n3. **Synchronization model mismatch**: Replacing `wgmma.wait_group` with `__syncthreads()` alone is insufficient. The `tcgen05.fence::before_thread_sync` must precede the syncthreads.\n\n4. **Over-allocating threads**: On Hopper, you need 128 threads per warpgroup for MMA. Blindly keeping the same thread count on Blackwell wastes resources since only 1 thread issues tcgen05."}, "after": {"statement": "1. Identify the exact WGMMA operand form, accumulator type, shape, and group-completion points in the SM90 kernel.\n2. Choose a legal tcgen05 kind, A source, CTA group, instruction descriptor, and data-path layout for the SM100 target.\n3. Replace register-resident D with a TMEM allocation. Group-1 allocation/deallocation is warp-collective; group 2 requires one warp in each CTA of the pair.\n4. Keep A/B backing storage unchanged until all asynchronous MMA consumers have completed.\n5. Replace WGMMA group completion with `tcgen05.commit` and an mbarrier wait. Add tcgen05 fences only where an execution-ordering handoff must order tcgen05-visible state across threads or CTAs.\n6. Transfer completed accumulator values from TMEM to registers with `tcgen05.ld`, observe its completion/access rules, then run the epilogue.\n7. Deallocate every dynamic TMEM allocation before kernel exit. Use the same `cta_group` value for all tcgen05 instructions in the kernel.\n8. Retune CTA/cluster shapes, pipeline stages, thread roles, descriptors, and epilogue scheduling on the target workload.\n\n`tcgen05.alloc` writes a 32-bit TMEM address to shared memory. Allocation size is expressed in columns, in power-of-two multiples permitted by PTX. It is a synchronous warp instruction: a lane-0-only call is invalid. `tcgen05.dealloc` has the same issue granularity, and PTX requires all allocated TMEM to be deallocated before kernel exit—not only in persistent kernels.\n\nThe MMA issuer and the allocation participants are different concepts. One thread initiates a group-1 MMA, but one full warp collectively allocates or deallocates its TMEM. A group-2 allocation uses one warp from each peer CTA.\n\n`tcgen05.mma` is asynchronous. `tcgen05.commit.cta_group::N.mbarrier::arrive::one.b64` makes an mbarrier track prior MMA work issued by the current thread; waiting on that barrier observes completion. A `tcgen05.fence` is an ordering and code-motion primitive, not a completion wait, so fence plus `__syncthreads()` is not a substitute for commit/mbarrier."}, "reason": {"statement": "Keep only direct, scoped pitfalls with observable failure modes.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-shared-memory-descriptor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/migration/wgmma-to-tcgen05.md", "before": {"statement": "If using CUTLASS, the migration is largely handled by changing the arch tag and kernel schedule:\n\n```cpp\n// Hopper CUTLASS GEMM\nusing GemmHopper = cutlass::gemm::device::GemmUniversal<\n /* ... */\n cutlass::arch::Sm90,\n /* ... */\n cutlass::gemm::collective::KernelScheduleSm90CpAsyncWarpSpecialized\n>;\n\n// Blackwell CUTLASS GEMM -- change arch + schedule\nusing GemmBlackwell = cutlass::gemm::device::GemmUniversal<\n /* ... */\n cutlass::arch::Sm100, // <-- changed\n /* ... */\n cutlass::gemm::collective::KernelScheduleSm100CpAsyncWarpSpecialized // <-- changed\n>;\n```\n\nCUTLASS handles the internal differences (TMEM allocation, descriptor construction, fence insertion, 128B swizzle) automatically through its `MMA_Atom` and `MMA_Traits` abstractions for SM100."}, "after": {"statement": "Single-thread MMA issue can free instruction-issue capacity for TMA, descriptor preparation, epilogue, reductions, or scheduling. It does not determine the kernel's total thread count: TMEM allocation, TMEM loads, TMA, epilogue, and barriers remain warp- or CTA-level work. Start from a pinned SM100 implementation and measure a role partition rather than copying fixed warp counts from an SM90 kernel.\n\nMoving D out of the GPR file also changes the register budget. Revisit tile size, pipeline depth, and launch bounds, but do not assume that lower accumulator pressure automatically increases occupancy; SMEM, TMEM, barriers, threads, and registers used by other roles can become limiting resources."}, "reason": {"statement": "Point to a pinned, complete SM100 example and enumerate the configuration surfaces that must be reselected.", "urls": []}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "Tensor Memory (TMEM) is a new addressable memory space introduced in the Blackwell architecture (SM100). Each SM contains **256KB of dedicated TMEM**, used primarily as the accumulator storage for `tcgen05.mma` operations. TMEM eliminates the register pressure that plagued Hopper's wgmma, where accumulators consumed 128+ registers per warpgroup."}, "after": {"statement": "Tensor Memory is an addressable, on-chip memory introduced for fifth-generation Tensor Core operations on Blackwell. Each SM has 256 KiB, organized as 128 lanes by 512 columns of 32-bit cells. `tcgen05.mma` writes its D accumulator to TMEM; depending on the instruction form, A can also reside there.\n\nMoving D out of general-purpose registers changes the resource balance relative to Hopper WGMMA. For example, CUTLASS 4.5.0's SM90 m64n256 FP32 WGMMA wrapper exposes 128 accumulator registers **per participating thread**. TMEM avoids that particular register-resident D fragment, but it does not remove registers needed by operands, control flow, or the epilogue."}, "reason": {"statement": "Keep the verified storage shift but scope register impact to the exact old instruction and per-thread fragment.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/arch/mma_sm90_gmma.hpp", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "Each thread \"owns\" the TMEM row corresponding to its warp and lane. When reading from TMEM, thread `T` in warp `W` accesses row `W*32 + T%32`."}, "after": {"statement": "A TMEM address (`taddr`) is a 32-bit value:\n\n| 31:16 | TMEM lane |\n| 15:0 | TMEM column |\n\nThe lane is a TMEM data-path lane, not storage independently owned by a CUDA thread. `tcgen05.ld` and `tcgen05.st` are warp-collective. Under their four-warp access model, the warps cover these lane chunks:\n\n| 0 | 0-31 |\n| 1 | 32-63 |\n| 2 | 64-95 |\n| 3 | 96-127 |\n\nThe chosen load/store shape determines how values from that lane-column region map to each thread's register vector. Use the PTX shape-specific layout tables rather than treating a logical MxN accumulator as a universal row-major array owned one row per thread."}, "reason": {"statement": "Describe lanes and collective warp chunks without inventing ownership.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory-addressing"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "Columns are addressed via a column offset in the TMEM descriptor. A 128x256 MMA accumulator tile occupies:\n\n- 128 rows (all lanes across 4 warps)\n- 256 columns of FP32 values = 1024 bytes per row\n\n```\nTMEM Layout for 128x256 FP32 accumulator:\n col 0 col 255 col 511\n |------------|-----------|-----------|\n | Acc Tile | (free) | (free) | row 0 (warp0, lane0)\n | 128x256 | | | row 1 (warp0, lane1)\n | FP32 | | | ...\n | | | | row 127 (warp3, lane31)\n |------------|-----------|-----------|\n```"}, "after": {"statement": "A TMEM address (`taddr`) is a 32-bit value:\n\n| 31:16 | TMEM lane |\n| 15:0 | TMEM column |\n\nThe lane is a TMEM data-path lane, not storage independently owned by a CUDA thread. `tcgen05.ld` and `tcgen05.st` are warp-collective. Under their four-warp access model, the warps cover these lane chunks:\n\n| 0 | 0-31 |\n| 1 | 32-63 |\n| 2 | 64-95 |\n| 3 | 96-127 |\n\nThe chosen load/store shape determines how values from that lane-column region map to each thread's register vector. Use the PTX shape-specific layout tables rather than treating a logical MxN accumulator as a universal row-major array owned one row per thread."}, "reason": {"statement": "Retain capacity arithmetic separately from instruction-specific layout.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-data-path-layout-organization", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory-addressing"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "```cuda\n// Shared storage for CTA-wide broadcast of TMEM address\n__shared__ uint32_t s_tmem_addr;\n\n__device__ uint32_t tmem_alloc_cta(uint32_t num_cols) {\n // Only thread 0 allocates; result must reach ALL warps in the CTA.\n // __shfl_sync is warp-local — it cannot broadcast across warps.\n if (threadIdx.x == 0) {\n uint32_t smem_addr =\n static_cast(__cvta_generic_to_shared(&s_tmem_addr));\n asm volatile(\n \"tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;\"\n :\n : \"r\"(smem_addr), \"r\"(num_cols)\n );\n }\n __syncthreads(); // All warps now see s_tmem_addr\n return s_tmem_addr;\n}\n```\n\n- Only one thread (typically thread 0) issues the allocation.\n\n```cuda\n__device__ void tmem_dealloc(uint32_t tmem_addr, uint32_t num_cols) {\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;\"\n :\n : \"r\"(tmem_addr), \"r\"(num_cols)\n );\n }\n __syncthreads();\n}\n```"}, "after": {"statement": "TMEM has an explicit software-managed lifetime:\n\n1. Reserve shared memory for the 32-bit allocation result.\n2. Execute `tcgen05.alloc` collectively from one warp for `cta_group::1`, or from two warps—one per paired CTA—for `cta_group::2`.\n3. Synchronize consumers as required, then read the returned base `taddr` from shared memory.\n4. Use the allocation for MMA, copy, load, or store operations with the same CTA-group mode.\n5. Execute `tcgen05.dealloc` with the corresponding collective issue pattern.\n6. Deallocate every TMEM allocation before kernel exit.\n\nThe allocation operand counts columns. Legal allocation sizes are powers of two from 32 through 512 columns. Allocation can block until the requested TMEM is available; the ISA does not define folklore outcomes such as silent corruption for an invalid size."}, "reason": {"statement": "Remove unsafe inline PTX wrappers and state the collective contract directly.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "- The returned `tmem_addr` is the base column index."}, "after": {"statement": "TMEM has an explicit software-managed lifetime:\n\n1. Reserve shared memory for the 32-bit allocation result.\n2. Execute `tcgen05.alloc` collectively from one warp for `cta_group::1`, or from two warps—one per paired CTA—for `cta_group::2`.\n3. Synchronize consumers as required, then read the returned base `taddr` from shared memory.\n4. Use the allocation for MMA, copy, load, or store operations with the same CTA-group mode.\n5. Execute `tcgen05.dealloc` with the corresponding collective issue pattern.\n6. Deallocate every TMEM allocation before kernel exit.\n\nThe allocation operand counts columns. Legal allocation sizes are powers of two from 32 through 512 columns. Allocation can block until the requested TMEM is available; the ISA does not define folklore outcomes such as silent corruption for an invalid size."}, "reason": {"statement": "Preserve the full address model.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory-addressing", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "**Warning**: Failure to deallocate TMEM before CTA exit will leak memory and prevent subsequent CTAs from allocating, leading to hangs in persistent kernels.\n\n```cuda\n__global__ void persistent_gemm_kernel(/* ... */) {\n // 1. Allocate TMEM for accumulators\n uint32_t tmem_acc = tmem_alloc(256); // 256 cols for M=128, N=256\n\n while (has_more_tiles()) {\n // 2. Zero-initialize TMEM accumulator\n tmem_zero(tmem_acc, 256);\n\n // 3. Mainloop: accumulate K tiles\n for (int k = 0; k < K_tiles; ++k) {\n issue_tcgen05_mma(tmem_acc, smem_a[k], smem_b[k]);\n }\n\n // 4. Fence and read results\n asm volatile(\"tcgen05.fence::before_thread_sync;\");\n __syncthreads();\n\n // 5. Epilogue: read from TMEM, apply bias/activation, write to GMEM\n epilogue_from_tmem(tmem_acc, output);\n\n // 6. TMEM persists across tiles -- no need to reallocate\n }\n\n // 7. Deallocate before exit\n tmem_dealloc(tmem_acc, 256);\n}\n```"}, "after": {"statement": "TMEM has an explicit software-managed lifetime:\n\n1. Reserve shared memory for the 32-bit allocation result.\n2. Execute `tcgen05.alloc` collectively from one warp for `cta_group::1`, or from two warps—one per paired CTA—for `cta_group::2`.\n3. Synchronize consumers as required, then read the returned base `taddr` from shared memory.\n4. Use the allocation for MMA, copy, load, or store operations with the same CTA-group mode.\n5. Execute `tcgen05.dealloc` with the corresponding collective issue pattern.\n6. Deallocate every TMEM allocation before kernel exit.\n\nThe allocation operand counts columns. Legal allocation sizes are powers of two from 32 through 512 columns. Allocation can block until the requested TMEM is available; the ISA does not define folklore outcomes such as silent corruption for an invalid size.\n\nThe relevant mechanisms are distinct:\n\n- `tcgen05.commit` attaches completion of prior asynchronous MMA operations to an mbarrier. Wait on that barrier before consuming their results.\n- `tcgen05.wait::ld` and `tcgen05.wait::st` are the completion mechanisms for the corresponding asynchronous TMEM load/store operations.\n- `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` order tcgen05 operations around a documented execution-ordering handoff. A fence is not an MMA completion wait.\n- Producer buffers must remain live until the asynchronous operation that reads them has completed according to its instruction contract.\n\nCTA synchronization alone does not replace these completion operations."}, "reason": {"statement": "Remove a fabricated incomplete kernel and replace it with a normative lifecycle sequence.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-wait"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "```cuda\n// Store a register value to TMEM\n// Each thread writes to its own TMEM row at the specified column\n__device__ void tmem_store_f32(uint32_t tmem_col, float value) {\n asm volatile(\n \"tcgen05.st.sync.aligned.32x1b.x1.b32 [%0], {%1};\"\n :\n : \"r\"(tmem_col), \"f\"(value)\n );\n}\n\n// Vectorized store: 4 consecutive FP32 values\n__device__ void tmem_store_f32x4(uint32_t tmem_col, float4 values) {\n asm volatile(\n \"tcgen05.st.sync.aligned.32x1b.x4.b32 [%0], {%1, %2, %3, %4};\"\n :\n : \"r\"(tmem_col),\n \"f\"(values.x), \"f\"(values.y),\n \"f\"(values.z), \"f\"(values.w)\n );\n}\n```\n\n```cuda\n// Load a single FP32 from TMEM\n__device__ float tmem_load_f32(uint32_t tmem_col) {\n float result;\n asm volatile(\n \"tcgen05.ld.sync.aligned.32x1b.x1.b32 {%0}, [%1];\"\n : \"=f\"(result)\n : \"r\"(tmem_col)\n );\n return result;\n}\n\n// Vectorized load: 4 consecutive FP32 values\n__device__ float4 tmem_load_f32x4(uint32_t tmem_col) {\n float4 result;\n asm volatile(\n \"tcgen05.ld.sync.aligned.32x1b.x4.b32 {%0, %1, %2, %3}, [%4];\"\n : \"=f\"(result.x), \"=f\"(result.y),\n \"=f\"(result.z), \"=f\"(result.w)\n : \"r\"(tmem_col)\n );\n return result;\n}\n```\n\n```cuda\n// Zero-fill a range of TMEM columns\n__device__ void tmem_zero(uint32_t tmem_base_col, uint32_t num_cols) {\n // Each thread zeros its own row\n for (uint32_t c = 0; c < num_cols; c += 4) {\n float4 zero = make_float4(0.f, 0.f, 0.f, 0.f);\n tmem_store_f32x4(tmem_base_col + c, zero);\n }\n}\n```"}, "after": {"statement": "`tcgen05.ld` transfers TMEM into registers, and `tcgen05.st` transfers registers into TMEM. Their documented shapes include `.16x64b`, `.16x128b`, `.16x256b`, `.32x32b`, and `.16x32bx2`, with supported repetition qualifiers. There is no scalar `.32x1b` form.\n\n`tcgen05.cp` performs shaped shared-memory-to-TMEM copies. For example, PTX ISA 9.0 defines this exact form:\n\n```ptx\ntcgen05.cp.cta_group::1.128x256b [taddr], sdesc;\n```\n\nHere `taddr` is the TMEM destination and `sdesc` is the 64-bit shared-memory matrix descriptor. Follow the instruction's asynchronous ordering and completion rules before reusing the source or consuming the destination."}, "reason": {"statement": "Do not publish non-assembling executable-looking wrappers.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-cp"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "```cuda\n__global__ void double_buffered_gemm(/* ... */) {\n // Allocate two accumulator buffers\n uint32_t tmem_acc[2];\n tmem_acc[0] = tmem_alloc(256);\n tmem_acc[1] = tmem_alloc(256);\n\n int buf = 0;\n\n for (int tile = 0; tile < num_tiles; ++tile) {\n // Zero the current buffer\n tmem_zero(tmem_acc[buf], 256);\n\n // Mainloop: accumulate into current buffer\n for (int k = 0; k < K_tiles; ++k) {\n issue_tcgen05_mma(tmem_acc[buf], smem_a[k], smem_b[k]);\n }\n asm volatile(\"tcgen05.fence::before_thread_sync;\");\n __syncthreads();\n\n // If not the first tile, the *other* buffer's epilogue\n // was overlapped with this tile's MMA in the pipeline.\n\n // Start epilogue for current buffer\n // (can overlap with next tile's MMA on the other buffer)\n epilogue_from_tmem(tmem_acc[buf], output_tile[tile]);\n\n buf ^= 1; // Swap buffers\n }\n\n // Cleanup\n tmem_dealloc(tmem_acc[0], 256);\n tmem_dealloc(tmem_acc[1], 256);\n}\n```"}, "after": {"statement": "CUTLASS 4.5.0 exposes TMEM through `cutlass.utils.TmemAllocator` and layout-aware CuTe tensors. The official tutorial sequence is:\n\n1. create a `TmemAllocator` over shared storage for the allocation result;\n2. call `allocate(num_columns)` from the configured allocator warp;\n3. use `wait_for_alloc()` before other warps retrieve the address;\n4. obtain a typed pointer with `retrieve_ptr(dtype)`;\n5. bind that pointer to the MMA accumulator layout with `cute.make_tensor`;\n6. drain it with `tcgen05` copy atoms and the pipeline's completion protocol; and\n7. call `free(tmem_ptr)` before exit."}, "reason": {"statement": "Replace invented code with resource and synchronization requirements plus a pinned real example.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/python/CuTeDSL/cute/blackwell/tutorial/tutorial_gemm/fp16_gemm_6.py", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "| 128x192 FP32 | 192 cols | 2 | 128 |"}, "after": {"statement": "All allocations share the SM's 512-column capacity. Some useful whole-allocation budgets are:\n\n| 128 columns | 4 | 0 |\n| 256 columns | 2 | 0 |\n| 512 columns | 1 | 0 |\n\nA logical need of 192 columns cannot be requested directly: reserve 256 columns, or suballocate that logical region within another legal power-of-two reservation. Two 256-column accumulator stages consume the entire capacity, so scale-factor tensors or other scratch state must fit inside those reservations or the pipeline must use fewer columns."}, "reason": {"statement": "List only allocatable budgets and distinguish logical suballocation from hardware allocation.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "From published Blackwell microbenchmarks:\n\n| End-to-end latency (cache miss) | ~420 cycles | ~30 cycles | ~4 cycles |\n| Bandwidth for large working sets | High (dedicated bus) | Medium | N/A (limited count) |\n| Best for | Multi-stage tensor pipelines | Single-shot small matrix | Scalar/vector ALU |\n\nTMEM is **not** a replacement for shared memory. Its strength is in serving as a dedicated accumulator buffer that eliminates register pressure for large MMA tiles. SMEM remains faster for small, frequently accessed data.\n\n5. **Assuming SMEM-like latency**: TMEM has ~420-cycle latency on cache miss vs ~30 cycles for SMEM. Do not use TMEM for low-latency random access patterns."}, "after": {"statement": null}, "reason": {"statement": "A stale, heterogeneous comparison cannot support general performance guidance.", "urls": ["https://arxiv.org/pdf/2512.02189v3", "https://arxiv.org/abs/2512.02189"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "```python\n# CuTe-DSL example: TMEM accumulator layout\n# 128 rows x 256 columns, FP32\ntmem_layout = Layout(\n shape=(128, 256),\n stride=(256, 1),\n memory_space=MemorySpace.TMEM\n)\n\n# Allocate TMEM accumulator\nacc = tmem_alloc(tmem_layout)\n\n# Issue MMA -- accumulator lives in TMEM\ntcgen05_mma(acc, smem_a, smem_b)\n\n# Fence and read\ntcgen05_fence()\nresult = tmem_load(acc)\n```"}, "after": {"statement": "See the pinned [CUTLASS 4.5.0 FP16 GEMM tutorial](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/python/CuTeDSL/cute/blackwell/tutorial/tutorial_gemm/fp16_gemm_0.py) and [TMEM allocator implementation](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/python/CuTeDSL/cutlass/utils/tmem_allocator.py). APIs such as `Layout(memory_space=MemorySpace.TMEM)` and standalone `tcgen05_mma()` are not CUTLASS 4.5.0 interfaces."}, "reason": {"statement": "Link a complete version-pinned tutorial rather than fabricate a simplified API.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/python/CuTeDSL/cute/blackwell/tutorial/tutorial_gemm/fp16_gemm_0.py", "https://github.com/NVIDIA/cutlass/tree/e406c186f510a15091cce01f782020ceb7ba8eb5"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "1. **Forgetting to fence**: Reading TMEM without `tcgen05.fence::before_thread_sync` produces undefined (stale) values.\n2. **Forgetting to deallocate**: In persistent kernels, TMEM must be freed before re-acquiring tiles. Otherwise, the next allocation will fail or hang.\n3. **Exceeding 512 columns**: Attempting to allocate more than the SM's total column budget silently corrupts data or causes a hang."}, "after": {"statement": "TMEM has an explicit software-managed lifetime:\n\n1. Reserve shared memory for the 32-bit allocation result.\n2. Execute `tcgen05.alloc` collectively from one warp for `cta_group::1`, or from two warps—one per paired CTA—for `cta_group::2`.\n3. Synchronize consumers as required, then read the returned base `taddr` from shared memory.\n4. Use the allocation for MMA, copy, load, or store operations with the same CTA-group mode.\n5. Execute `tcgen05.dealloc` with the corresponding collective issue pattern.\n6. Deallocate every TMEM allocation before kernel exit.\n\nThe allocation operand counts columns. Legal allocation sizes are powers of two from 32 through 512 columns. Allocation can block until the requested TMEM is available; the ISA does not define folklore outcomes such as silent corruption for an invalid size.\n\nAll allocations share the SM's 512-column capacity. Some useful whole-allocation budgets are:\n\n| 128 columns | 4 | 0 |\n| 256 columns | 2 | 0 |\n| 512 columns | 1 | 0 |\n\nA logical need of 192 columns cannot be requested directly: reserve 256 columns, or suballocate that logical region within another legal power-of-two reservation. Two 256-column accumulator stages consume the entire capacity, so scale-factor tensors or other scratch state must fit inside those reservations or the pipeline must use fewer columns.\n\nThe relevant mechanisms are distinct:\n\n- `tcgen05.commit` attaches completion of prior asynchronous MMA operations to an mbarrier. Wait on that barrier before consuming their results.\n- `tcgen05.wait::ld` and `tcgen05.wait::st` are the completion mechanisms for the corresponding asynchronous TMEM load/store operations.\n- `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` order tcgen05 operations around a documented execution-ordering handoff. A fence is not an MMA completion wait.\n- Producer buffers must remain live until the asynchronous operation that reads them has completed according to its instruction contract.\n\nCTA synchronization alone does not replace these completion operations."}, "reason": {"statement": "Replace folklore failure modes with normative obligations.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-wait"]}} +{"path": "wiki/hardware/tmem.md", "before": {"statement": "4. **Cross-warp reads**: A thread can only directly read/write TMEM rows mapped to its own lane. Accessing another warp's rows requires explicit shuffle or SMEM staging."}, "after": {"statement": "A TMEM address (`taddr`) is a 32-bit value:\n\n| 31:16 | TMEM lane |\n| 15:0 | TMEM column |\n\nThe lane is a TMEM data-path lane, not storage independently owned by a CUDA thread. `tcgen05.ld` and `tcgen05.st` are warp-collective. Under their four-warp access model, the warps cover these lane chunks:\n\n| 0 | 0-31 |\n| 1 | 32-63 |\n| 2 | 64-95 |\n| 3 | 96-127 |\n\nThe chosen load/store shape determines how values from that lane-column region map to each thread's register vector. Use the PTX shape-specific layout tables rather than treating a logical MxN accumulator as a universal row-major array owned one row per thread."}, "reason": {"statement": "State direct warp access restrictions and avoid a false communication primitive.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory-addressing"]}} +{"path": "wiki/hardware/mbarrier.md", "before": {"statement": "mbarriers are 64-bit shared memory primitives used for producer/consumer synchronization between asynchronous hardware units (TMA, tcgen05) and SM threads. Introduced on Hopper, essential for Blackwell warp-specialized kernels."}, "after": {"statement": "An mbarrier is an opaque, naturally aligned 64-bit object in shared memory. It synchronizes threads and can track asynchronous operations. The base instructions were introduced in PTX ISA 7.0 for `sm_80`; Hopper (`sm_90`) added transaction-count operations and cluster scope. Blackwell uses the same object for TMA transaction completion and for `tcgen05.commit` arrival-on completion.\n\nmbarriers are useful in warp-specialized pipelines, but they are a mechanism rather than a requirement for every such kernel."}, "reason": {"statement": "Separate the Ampere base primitive from Hopper transaction-count extensions and avoid a universal design mandate.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-init", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier"]}} +{"path": "wiki/hardware/mbarrier.md", "before": {"statement": "```ptx\n// Initialize: set expected arrival count\nmbarrier.init.shared.b64 [mbar_addr], num_arrivals;\n\n// Producer: arrive on barrier (decrements expected count)\nmbarrier.arrive.shared.b64 _, [mbar_addr];\n\n// Producer (with byte expectation): used by TMA\nmbarrier.arrive.expect_tx.shared.b64 _, [mbar_addr], expected_bytes;\n// After this, TMA hardware completes the transaction by arriving with\n// the transferred byte count, and the mbarrier flips parity.\n\n// Consumer: wait for parity flip\nmbarrier.try_wait.parity.shared.b64 p, [mbar_addr], phase;\n@!p bra WAIT_LOOP;\n```"}, "after": {"statement": "For the current phase, an mbarrier tracks:\n\n- pending arrivals;\n- the expected arrival count for the next phase; and\n- a transaction count (`tx-count`) for outstanding asynchronous work.\n\nThe current phase completes only when **both** pending arrivals and tx-count reach zero. Completion atomically advances to the next phase and restores pending arrivals from the expected count. Before an arrival in the following phase, at least one `test_wait` or `try_wait` for the completed phase must have returned true.\n\nInitialization sets phase 0, initializes expected and pending arrivals to `count`, and sets tx-count to zero:\n\n```ptx\nmbarrier.init.shared::cta.b64 [bar], arrival_count;\n```\n\nInvalidate the object with `mbarrier.inval` before reusing its storage for another purpose or reinitializing an already-valid object."}, "reason": {"statement": "Preserve exact accounting semantics and avoid premature-completion bugs.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-phase-completion", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-contents"]}} +{"path": "wiki/hardware/mbarrier.md", "before": {"statement": "```cuda\nint phase = 0;\nfor (int k = 0; k < num_iterations; k++) {\n int stage = k % NUM_STAGES;\n\n // Wait for this stage's producer to complete\n mbarrier_wait_parity(&mbar[stage], phase);\n phase ^= 1; // Flip for next use of this stage slot\n\n // Use data...\n consume_data(stage);\n\n // Arrive on next-stage barrier when done\n mbarrier_arrive(&buffer_free[stage]);\n}\n```"}, "after": {"statement": "These operations affect different parts of the state:\n\n| `mbarrier.arrive` | Decrements pending arrivals; returns a phase state token for a CTA-shared object. |\n| `mbarrier.arrive.expect_tx` | Performs an arrival and increments tx-count by `txCount`. |\n| `mbarrier.expect_tx` | Increments tx-count without an arrival. |\n| `mbarrier.complete_tx` | Decrements tx-count; it is not an arrival. |\n| `mbarrier.test_wait` / `try_wait` | Tests completion of the phase identified by a state token or parity. |\n\nRepresentative CTA-shared forms from PTX ISA 9.0 are:\n\n```ptx\nmbarrier.arrive.shared::cta.b64 state, [bar];\nmbarrier.arrive.expect_tx.shared::cta.b64 state, [bar], tx_count;\nmbarrier.try_wait.parity.acquire.cta.shared::cta.b64 ready, [bar], phase_parity;\n```\n\n`try_wait` can suspend temporarily and must still be retried until its predicate is true. Use acquire/release semantics appropriate to the producer-consumer handoff; `.relaxed` does not provide memory-ordering or visibility guarantees."}, "reason": {"statement": "Remove subtly unsafe pseudocode and give a per-stage reuse rule instead.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-try-wait", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-arrive"]}} +{"path": "wiki/hardware/mbarrier.md", "before": {"statement": "```cuda\n// Producer warp issues TMA with mbarrier target\nif (lane_id == 0) {\n uint32_t tx_bytes = TILE_A_BYTES + TILE_B_BYTES;\n mbarrier_arrive_expect_tx(&mbar[stage], tx_bytes);\n\n // TMA completion will fire the mbarrier automatically\n cp_async_bulk_tensor_2d(smem_A[stage], global_desc, x, y, &mbar[stage]);\n cp_async_bulk_tensor_2d(smem_B[stage], global_desc, x, y, &mbar[stage]);\n}\n// Do NOT manually arrive after TMA issue - it races with hardware\n```\n\n3. **Manual arrive after async issue**: TMA/tcgen05 hardware arrives on completion — extra manual arrive causes double-count"}, "after": {"statement": "Parity is the low bit of an individual mbarrier object's phase: even phases use 0 and odd phases use 1. A parity wait can refer only to the current or immediately preceding phase, so software must track phase for the entire lifetime of that object.\n\nFor an N-stage ring, track state per stage. When stage `s` is reused, pass the parity expected for `bar[s]`; toggle that stage's parity only after its phase completes. One global bit toggled on every loop iteration is generally wrong because different stage barriers advance independently.\n\nUsing the opaque state returned by `mbarrier.arrive` is an alternative when the same participant can carry that token to its wait."}, "reason": {"statement": "Replace fabricated code with an exact accounting sequence and vendor grammar link.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-try-wait"]}} +{"path": "wiki/hardware/mbarrier.md", "before": {"statement": "4. **Cross-cluster mbarriers**: Use `shared::cluster` qualifier for cluster-level sync (2-SM cooperative MMA)"}, "after": {"statement": "For a common TMA-load phase initialized with one pending arrival:\n\n1. The producer executes `mbarrier.arrive.expect_tx` with the sum of bytes that all TMA operations in this phase will report.\n2. The producer issues the TMA operations with `.mbarrier::complete_tx::bytes` and the same barrier.\n3. Each TMA completion performs `complete-tx` for the bytes it copied.\n4. The consumer waits for the phase to complete before reading the destination.\n\nThe `arrive.expect_tx` operation accounts for the software arrival and establishes the expected byte total. TMA hardware does **not** perform a second arrival: it decrements tx-count through complete-tx. Therefore, do not add an unmatched `mbarrier.arrive`, and do not manually simulate TMA's complete-tx. Either mistake can advance or strand the wrong phase.\n\nThe expected byte total, barrier address, destination ownership, and exact `cp.async.bulk.tensor` form must match. Follow the complete instruction grammar in the PTX ISA rather than using placeholder helper calls."}, "reason": {"statement": "Teach object location, address mapping, operation support, and synchronization scope separately.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-arrive"]}} +{"path": "wiki/hardware/nvfp4.md", "before": {"statement": "| `tcgen05.mma.mxf4.block_scale` | MX FP4 with block scaling | **4×** |\n| `tcgen05.mma.mxf4nvf4.block_scale` | NVFP4 + MX FP4 flexible scaling | **4×** |"}, "after": {"statement": "PTX ISA 9.0 provides the packed conversion form:\n\n```ptx\ncvt.rn.f16x2.e2m1x2 d, a;\n```\n\nHere `a` is a byte-sized packed pair and `d` is a 32-bit `f16x2` result. PTX also permits `mov.b32` to unpack a 32-bit scalar into four byte-sized vector destinations when the declarations satisfy its type rules. Neither syntax establishes that one packing strategy is faster than masks and shifts; inspect generated machine code and benchmark the target GPU."}, "reason": {"statement": "Give exact distinguishing qualifiers and remove an unscoped performance number.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov"]}} +{"path": "wiki/hardware/nvfp4.md", "before": {"statement": "```ptx\n// Convert two FP4 values to two FP16 values\ncvt.rn.f16x2.e2m1x2 result, packed_fp4;\n\n// Byte unpacking (faster than bitwise extraction)\nmov.b32 {tmp0, tmp1, tmp2, tmp3}, packed_data;\n```"}, "after": {"statement": "There is no architecture-independent \"4x versus Hopper\" result for these instructions. Hopper has no native FP4 tensor-core path, so any comparison depends on the emulation or higher-precision baseline as well as GPU SKU, clocks, matrix shape, layouts, scale preparation, epilogue, and achieved occupancy. Record those conditions with any throughput number."}, "reason": {"statement": "Retain the exact packed conversion form, state mov's typed preconditions, and require measurement for packing-strategy performance.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/hardware/nvfp4.md", "before": {"statement": "| Quantization error | Lower | Higher |"}, "after": {"statement": "In PTX ISA 9.0, the relevant `tcgen05.mma` combinations for E2M1 inputs include:\n\n| `.kind::mxf4.block_scale.block32` | 32 | `.ue8m0` | `.scale_vec::2X` |\n| `.kind::mxf4nvf4.block_scale.block16` | 16 | `.ue4m3` | `.scale_vec::4X` |\n\nThe `.kind::mxf4nvf4` family also admits documented UE8M0 modes, so the kind name by itself does not select the NVFP4 recipe. Use the complete block and scale-vector qualifiers and follow the type-combination tables. These forms target architecture-specific Blackwell targets such as `sm_100a`; a kernel using them must use the matching compile and runtime target."}, "reason": {"statement": "State the representational tradeoff without claiming an unconditional empirical ordering.", "urls": ["https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/hardware/pdl-gdc.md", "before": {"statement": "```cuda\n// Primary kernel signals near completion\ncudaGridDependencySynchronize(); // or PTX equivalent\n\n// Secondary kernel can start overlapping with primary's tail\n// Enabled by default on SM100 (opt-in on SM90)\n```"}, "after": {"statement": "This minimal skeleton shows where each operation belongs; real kernels put independent and dependent work at the indicated points and add normal error checking:\n\n```cuda\n#include \n\n__global__ void primary() {\n // Produce everything needed before the secondary may be launched.\n if (threadIdx.x == 0) {\n cudaTriggerProgrammaticLaunchCompletion();\n }\n // Primary tail that does not change data consumed by the secondary.\n}\n\n__global__ void secondary() {\n // Independent preamble may execute early.\n cudaGridDependencySynchronize();\n // Dependent reads begin only after this wait.\n}\n\nvoid launch_pdl(dim3 grid, dim3 block, cudaStream_t stream) {\n cudaLaunchConfig_t cfg{};\n cfg.gridDim = grid;\n cfg.blockDim = block;\n cfg.stream = stream;\n\n cudaLaunchAttribute attr{};\n attr.id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attr.val.programmaticStreamSerializationAllowed = 1;\n cfg.attrs = &attr;\n cfg.numAttrs = 1;\n\n primary<<>>();\n cudaLaunchKernelEx(&cfg, secondary);\n}\n```\n\nDo not place `cudaGridDependencySynchronize()` in the primary: it is the secondary-side wait, not the launch trigger. Do not replace the wait with an ordinary memory fence. PDL's wait supplies both prerequisite-grid completion and visibility for its dependent work."}, "reason": {"statement": "Replace the reversed, incomplete example with the three-part protocol.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#programmatic-dependent-launch-and-synchronization", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-griddepcontrol"]}} +{"path": "wiki/hardware/pdl-gdc.md", "before": {"statement": "On SM100, PDL is **enabled by default** — no opt-in needed. This means:"}, "after": {"statement": "Programmatic Dependent Launch (PDL) lets a secondary grid in the same CUDA stream become eligible to start before its prerequisite primary grid completes. It is available on compute capability 9.0 and later, including Hopper and Blackwell.\n\nPDL creates an **opportunity** for overlap; it does not guarantee that the grids execute concurrently. The useful overlap is normally the primary's work after its launch trigger and the secondary's independent preamble before its dependency wait.\n\nThe CUDA protocol has three required roles:\n\n1. Every primary CTA either executes `cudaTriggerProgrammaticLaunchCompletion()` or exits. After all CTAs satisfy that condition, the driver may schedule the secondary grid.\n2. The host launches the secondary in the same stream with `cudaLaunchAttributeProgrammaticStreamSerialization` and `programmaticStreamSerializationAllowed = 1`.\n3. Every secondary thread waits with `cudaGridDependencySynchronize()` before it consumes prerequisite results. The wait completes after the prerequisite grids finish and their memory operations are visible.\n\nIf the primary does not explicitly trigger, its CTAs implicitly satisfy the trigger only as they exit. Omitting the explicit trigger is correct but removes the intended primary-tail overlap.\n\nBlackwell does not make arbitrary back-to-back launches overlap automatically. CUDA applications still opt the secondary launch into programmatic stream serialization and implement the device-side trigger/wait protocol.\n\nCUTLASS has a separate build choice. In CUTLASS 4.5.0, the CMake option `CUTLASS_ENABLE_GDC_FOR_SM100` defaults to `ON`, while the SM90 option is opt-in. That default only enables eligible CUTLASS code to emit its GDC wrappers; it is not a device-wide CUDA default and can be overridden by the build."}, "reason": {"statement": "Separate hardware availability, CUDA launch opt-in, and one library's build default.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#programmatic-dependent-launch-and-synchronization", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/CMakeLists.txt#L463-L474"]}} +{"path": "wiki/hardware/pdl-gdc.md", "before": {"statement": "- Back-to-back kernel launches naturally overlap\n- Memory fences ensure correctness for dependent data\n- Reduces kernel launch gaps in compute-heavy pipelines"}, "after": {"statement": "Programmatic Dependent Launch (PDL) lets a secondary grid in the same CUDA stream become eligible to start before its prerequisite primary grid completes. It is available on compute capability 9.0 and later, including Hopper and Blackwell.\n\nPDL creates an **opportunity** for overlap; it does not guarantee that the grids execute concurrently. The useful overlap is normally the primary's work after its launch trigger and the secondary's independent preamble before its dependency wait.\n\nThe CUDA protocol has three required roles:\n\n1. Every primary CTA either executes `cudaTriggerProgrammaticLaunchCompletion()` or exits. After all CTAs satisfy that condition, the driver may schedule the secondary grid.\n2. The host launches the secondary in the same stream with `cudaLaunchAttributeProgrammaticStreamSerialization` and `programmaticStreamSerializationAllowed = 1`.\n3. Every secondary thread waits with `cudaGridDependencySynchronize()` before it consumes prerequisite results. The wait completes after the prerequisite grids finish and their memory operations are visible.\n\nIf the primary does not explicitly trigger, its CTAs implicitly satisfy the trigger only as they exit. Omitting the explicit trigger is correct but removes the intended primary-tail overlap.\n\nThis minimal skeleton shows where each operation belongs; real kernels put independent and dependent work at the indicated points and add normal error checking:\n\n```cuda\n#include \n\n__global__ void primary() {\n // Produce everything needed before the secondary may be launched.\n if (threadIdx.x == 0) {\n cudaTriggerProgrammaticLaunchCompletion();\n }\n // Primary tail that does not change data consumed by the secondary.\n}\n\n__global__ void secondary() {\n // Independent preamble may execute early.\n cudaGridDependencySynchronize();\n // Dependent reads begin only after this wait.\n}\n\nvoid launch_pdl(dim3 grid, dim3 block, cudaStream_t stream) {\n cudaLaunchConfig_t cfg{};\n cfg.gridDim = grid;\n cfg.blockDim = block;\n cfg.stream = stream;\n\n cudaLaunchAttribute attr{};\n attr.id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attr.val.programmaticStreamSerializationAllowed = 1;\n cfg.attrs = &attr;\n cfg.numAttrs = 1;\n\n primary<<>>();\n cudaLaunchKernelEx(&cfg, secondary);\n}\n```\n\nDo not place `cudaGridDependencySynchronize()` in the primary: it is the secondary-side wait, not the launch trigger. Do not replace the wait with an ordinary memory fence. PDL's wait supplies both prerequisite-grid completion and visibility for its dependent work.\n\nCUDA lowers the two device roles to Grid Dependency Control instructions:\n\n```ptx\n// Primary CTA: makes designated dependent grids eligible after every CTA\n// has issued this instruction or completed.\ngriddepcontrol.launch_dependents;\n\n// Secondary thread: waits for in-flight prerequisite grids and visibility.\ngriddepcontrol.wait;\n```\n\n`griddepcontrol` was introduced in PTX ISA 7.8 and requires `sm_90` or newer. Repeating `launch_dependents` within one CTA has no additional effect after that CTA's first invocation. If a prerequisite uses `launch_dependents`, its dependent must use `griddepcontrol.wait` or an equivalent CUDA dependency wait for correct execution."}, "reason": {"statement": "State the exact ordering contract and make overlap conditional.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#programmatic-dependent-launch-and-synchronization", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-griddepcontrol"]}} +{"path": "wiki/hardware/pdl-gdc.md", "before": {"statement": "- Chains of small kernels (e.g., MoE dispatch → compute → combine)\n- Pipeline-parallel training with many sequential kernel launches\n- Reduces overall wall-clock time without code changes on Blackwell"}, "after": {"statement": "PDL can help only when all of these conditions hold:\n\n- the secondary has enough independent preamble to overlap;\n- the primary has useful tail work after every CTA reaches the trigger;\n- the two grids have enough simultaneous resource headroom; and\n- the saved launch/serialization time exceeds the protocol and occupancy costs.\n\nSmall-kernel chains, GEMM/epilogue sequences, and pipeline-parallel stages are candidates, not guaranteed wins. Profile an explicit non-PDL baseline and record GPU, clocks, launch shapes, stream/graph configuration, input sizes, warmup, repetitions, and the observed overlap timeline. Never rely on overlap for forward progress; CUDA documents it as opportunistic and warns that such reliance can deadlock."}, "reason": {"statement": "Replace categorical workload promises with a decision and measurement checklist.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#programmatic-dependent-launch-and-synchronization"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "The Tensor Memory Accelerator (TMA) is a hardware unit that performs **asynchronous bulk data transfers** between global memory and shared memory. First introduced on Hopper (SM90), TMA carries forward to Blackwell (SM100) with stricter requirements for tcgen05 compatibility.\n\n| Swizzle modes | None, 32B, 64B, 128B (128B required for tcgen05) |\n\nOn Blackwell, `tcgen05.mma` requires operands in **128-byte swizzled** SMEM layout. If TMA loads data without 128B swizzling, the MMA will produce incorrect results.\n\n```cuda\n// CORRECT for Blackwell tcgen05:\nCUtensorMap desc = create_tma_descriptor_2d(ptr, M, N, 128, 64, 128);\n// swizzle=128 ^^^\n\n// WRONG for tcgen05 (will silently produce garbage):\nCUtensorMap desc = create_tma_descriptor_2d(ptr, M, N, 128, 64, 0);\n// swizzle=0 ^^^\n```\n\nAll TMA loads feeding `tcgen05.mma` must use 128-byte swizzling. The swizzle pattern rearranges bytes within each 128-byte line to match the tensor core's internal data layout:\n\n| Always use 128B swizzle on Blackwell | Non-128B swizzle produces incorrect tcgen05 results |"}, "after": {"statement": "TMA supports no swizzle and multiple swizzled shared-memory layouts, including 32B, 64B, and 128B spans plus newer variants for selected types. Swizzling rearranges chunks across shared-memory banks. The consumer must address the matching logical layout; the exact mapping also depends on the documented shared-memory base-offset rule.\n\nThere is no universal rule that every Blackwell or `tcgen05.mma` input uses 128B swizzling. The TMA tensor-map swizzle, destination base alignment, leading dimension, and the tcgen05 shared-memory descriptor must describe the **same** legal layout. PTX defines no-, 32B-, 64B-, and 128B-swizzled tcgen05 descriptors with kind-, type-, shape-, and layout-specific constraints.\n\nA matched swizzle can reduce or remove bank conflicts for a particular access pattern. It does not make every possible consumer access conflict-free."}, "reason": {"statement": "Make swizzle selection descriptor- and shape-specific and remove the invented failure mode.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-shared-memory-layout-swizzling", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "TMA offloads data movement from CUDA cores entirely -- a single thread issues the transfer, and the TMA hardware engine handles the multi-dimensional copy, address calculation, out-of-bounds clamping, and format conversion.\n\n| Format conversion | FP32<->BF16, FP32<->FP16 during transfer |"}, "after": {"statement": "TMA is the descriptor-driven `cp.async.bulk.tensor` facility introduced for Hopper (`sm_90`) and retained on Blackwell. One thread can issue a non-blocking rank-1 through rank-5 tensor copy while the hardware performs multidimensional address traversal and moves the tile.\n\nThe principal copy directions and completion mechanisms are:\n\n| Global to shared | Issuing CTA or a CTA in its cluster | One masked instruction can multicast to selected CTAs | mbarrier `complete_tx` in bytes |\n| Shared to global | Issuing CTA's shared memory to a tensor map | Scatter modes are available on supported Blackwell targets | Bulk async group: issue, commit, wait |\n\nTMA copies the datatype represented by the tensor map. It does not provide a general FP32-to/from-FP16 or BF16 conversion step. For a tiled global-to-shared load, out-of-bounds elements are filled according to the supported tensor-map policy rather than clamped to an edge coordinate.\n\nA tensor map is opaque and is accessed through the tensor-map proxy. `cuTensorMapEncodeTiled` describes:\n\n- datatype and global base address;\n- rank, global dimensions, and byte strides;\n- traversal box dimensions and element strides;\n- interleave and shared-memory swizzle;\n- L2-promotion hint; and\n- out-of-bounds fill policy.\n\nFor the ordinary non-interleaved tiled path in CUDA Driver API 13.0.97, important constraints include:\n\n- the `CUtensorMap` output object is 64-byte aligned;\n- the global base and byte strides satisfy the documented alignment rules, commonly at least 16 bytes for the basic types/path;\n- every `boxDim` entry is from 1 through 256 elements;\n- `boxDim[0] * element_size` is a multiple of 16 bytes;\n- every element stride is from 1 through 8; and\n- when swizzling is enabled, the inner box in bytes does not exceed the selected swizzle span.\n\nDatatype, interleave, sub-byte, and architecture-specific modes add further restrictions. Always check the encoder's `CUresult`; never use the output after an encoding failure.\n\nHost encoding is common, but it is not the only Blackwell path. CUDA also documents device-side tensor-map construction and modification on Blackwell. A map modified through the generic proxy must be published to the tensor-map proxy with the required `fence.proxy.tensormap::generic` sequence before a TMA operation consumes it."}, "reason": {"statement": "Describe representation-preserving copies and OOB fill precisely.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#asynchronous-data-copies-using-the-tensor-memory-accelerator-tma", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#encoding-a-tensor-map-on-device"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "| Max transfer size | Up to 256 bytes per element, tiles up to 128x256 |\n\n| Synchronization | mbarrier-based (arrive/wait) |"}, "after": {"statement": "TMA is the descriptor-driven `cp.async.bulk.tensor` facility introduced for Hopper (`sm_90`) and retained on Blackwell. One thread can issue a non-blocking rank-1 through rank-5 tensor copy while the hardware performs multidimensional address traversal and moves the tile.\n\nThe principal copy directions and completion mechanisms are:\n\n| Global to shared | Issuing CTA or a CTA in its cluster | One masked instruction can multicast to selected CTAs | mbarrier `complete_tx` in bytes |\n| Shared to global | Issuing CTA's shared memory to a tensor map | Scatter modes are available on supported Blackwell targets | Bulk async group: issue, commit, wait |\n\nTMA copies the datatype represented by the tensor map. It does not provide a general FP32-to/from-FP16 or BF16 conversion step. For a tiled global-to-shared load, out-of-bounds elements are filled according to the supported tensor-map policy rather than clamped to an edge coordinate.\n\nA tensor map is opaque and is accessed through the tensor-map proxy. `cuTensorMapEncodeTiled` describes:\n\n- datatype and global base address;\n- rank, global dimensions, and byte strides;\n- traversal box dimensions and element strides;\n- interleave and shared-memory swizzle;\n- L2-promotion hint; and\n- out-of-bounds fill policy.\n\nFor the ordinary non-interleaved tiled path in CUDA Driver API 13.0.97, important constraints include:\n\n- the `CUtensorMap` output object is 64-byte aligned;\n- the global base and byte strides satisfy the documented alignment rules, commonly at least 16 bytes for the basic types/path;\n- every `boxDim` entry is from 1 through 256 elements;\n- `boxDim[0] * element_size` is a multiple of 16 bytes;\n- every element stride is from 1 through 8; and\n- when swizzling is enabled, the inner box in bytes does not exceed the selected swizzle span.\n\nDatatype, interleave, sub-byte, and architecture-specific modes add further restrictions. Always check the encoder's `CUresult`; never use the output after an encoding failure.\n\nHost encoding is common, but it is not the only Blackwell path. CUDA also documents device-side tensor-map construction and modification on Blackwell. A map modified through the generic proxy must be published to the tensor-map proxy with the required `fence.proxy.tensormap::generic` sequence before a TMA operation consumes it.\n\nPTX ISA 9.0 defines this representative 2D CTA-local form:\n\n```ptx\ncp.async.bulk.tensor.2d.shared::cta.global.mbarrier::complete_tx::bytes\n [dst_smem], [tensor_map, {x, y}], [full_barrier];\n```\n\nThe instruction is non-blocking. A common one-producer phase with one or more loads uses this accounting:\n\n1. Initialize and publish the stage's mbarrier with the intended pending-arrival count.\n2. The producer performs one `mbarrier.arrive.expect_tx` for its software arrival and the sum of bytes that all loads in this phase will complete.\n3. Issue the TMA loads against that barrier.\n4. Each completed load performs `complete_tx` for its copied byte count; it does **not** perform another arrival.\n5. Consumers wait with the correct state token or per-stage parity and acquire semantics before reading the destination.\n\nThe phase completes only after pending arrivals and tx-count are both zero. If a design performs multiple software arrivals instead, its initialized count must match them exactly. See [mbarrier](mbarrier.md) for lifecycle, phase, and memory-ordering rules.\n\nA tensor store uses bulk-group completion rather than the load's mbarrier protocol:\n\n```ptx\ncp.async.bulk.tensor.2d.global.shared::cta.bulk_group\n [tensor_map, {x, y}], [src_smem];\ncp.async.bulk.commit_group;\ncp.async.bulk.wait_group 0;\n```\n\nThe wait may be delayed to overlap independent work. It must occur before the issuing thread reuses the source shared memory or before code that requires store completion. `commit_group` creates the group; it is not itself a completion wait."}, "reason": {"statement": "List parameter constraints and direction-specific completion separately.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#asynchronous-data-copies-using-the-tensor-memory-accelerator-tma", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#encoding-a-tensor-map-on-device", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-phase-completion"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "TMA operations are driven by a **descriptor** that encodes the tensor layout, addressing, and transfer parameters. The descriptor is created on the host and passed to the kernel."}, "after": {"statement": "A tensor map is opaque and is accessed through the tensor-map proxy. `cuTensorMapEncodeTiled` describes:\n\n- datatype and global base address;\n- rank, global dimensions, and byte strides;\n- traversal box dimensions and element strides;\n- interleave and shared-memory swizzle;\n- L2-promotion hint; and\n- out-of-bounds fill policy.\n\nFor the ordinary non-interleaved tiled path in CUDA Driver API 13.0.97, important constraints include:\n\n- the `CUtensorMap` output object is 64-byte aligned;\n- the global base and byte strides satisfy the documented alignment rules, commonly at least 16 bytes for the basic types/path;\n- every `boxDim` entry is from 1 through 256 elements;\n- `boxDim[0] * element_size` is a multiple of 16 bytes;\n- every element stride is from 1 through 8; and\n- when swizzling is enabled, the inner box in bytes does not exceed the selected swizzle span.\n\nDatatype, interleave, sub-byte, and architecture-specific modes add further restrictions. Always check the encoder's `CUresult`; never use the output after an encoding failure.\n\nHost encoding is common, but it is not the only Blackwell path. CUDA also documents device-side tensor-map construction and modification on Blackwell. A map modified through the generic proxy must be published to the tensor-map proxy with the required `fence.proxy.tensormap::generic` sequence before a TMA operation consumes it."}, "reason": {"statement": "Present host encoding as common, not exclusive, and mention device proxy ordering.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#encoding-a-tensor-map-on-device", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "```cuda\n#include \n\n// Create a 2D TMA descriptor for a row-major FP16 matrix\nCUtensorMap create_tma_descriptor_2d(\n const half* global_ptr,\n int M, int N, // Global tensor dimensions\n int tile_m, int tile_n, // Tile dimensions for each transfer\n int swizzle_bytes // Swizzle mode: 0, 32, 64, 128\n) {\n CUtensorMap tensor_map;\n\n // Tensor dimensions (outermost to innermost)\n uint64_t global_dims[2] = {(uint64_t)N, (uint64_t)M};\n uint64_t global_strides[1] = {(uint64_t)(N * sizeof(half))};\n\n // Tile box dimensions\n uint32_t box_dims[2] = {(uint32_t)tile_n, (uint32_t)tile_m};\n\n // Element strides (1 = contiguous)\n uint32_t elem_strides[2] = {1, 1};\n\n CUtensorMapSwizzle swizzle;\n switch (swizzle_bytes) {\n case 0: swizzle = CU_TENSOR_MAP_SWIZZLE_NONE; break;\n case 32: swizzle = CU_TENSOR_MAP_SWIZZLE_32B; break;\n case 64: swizzle = CU_TENSOR_MAP_SWIZZLE_64B; break;\n case 128: swizzle = CU_TENSOR_MAP_SWIZZLE_128B; break;\n }\n\n cuTensorMapEncodeTiled(\n &tensor_map,\n CU_TENSOR_MAP_DATA_TYPE_FLOAT16, // Element type\n 2, // Dimensionality\n (void*)global_ptr, // Global pointer\n global_dims, // Tensor dimensions\n global_strides, // Byte strides (exclude innermost)\n box_dims, // Tile/box dimensions\n elem_strides, // Element strides\n CU_TENSOR_MAP_INTERLEAVE_NONE,\n swizzle,\n CU_TENSOR_MAP_L2_PROMOTION_NONE,\n CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE\n );\n\n return tensor_map;\n}\n```"}, "after": {"statement": "A tensor map is opaque and is accessed through the tensor-map proxy. `cuTensorMapEncodeTiled` describes:\n\n- datatype and global base address;\n- rank, global dimensions, and byte strides;\n- traversal box dimensions and element strides;\n- interleave and shared-memory swizzle;\n- L2-promotion hint; and\n- out-of-bounds fill policy.\n\nFor the ordinary non-interleaved tiled path in CUDA Driver API 13.0.97, important constraints include:\n\n- the `CUtensorMap` output object is 64-byte aligned;\n- the global base and byte strides satisfy the documented alignment rules, commonly at least 16 bytes for the basic types/path;\n- every `boxDim` entry is from 1 through 256 elements;\n- `boxDim[0] * element_size` is a multiple of 16 bytes;\n- every element stride is from 1 through 8; and\n- when swizzling is enabled, the inner box in bytes does not exceed the selected swizzle span.\n\nDatatype, interleave, sub-byte, and architecture-specific modes add further restrictions. Always check the encoder's `CUresult`; never use the output after an encoding failure.\n\nHost encoding is common, but it is not the only Blackwell path. CUDA also documents device-side tensor-map construction and modification on Blackwell. A map modified through the generic proxy must be published to the tensor-map proxy with the required `fence.proxy.tensormap::generic` sequence before a TMA operation consumes it.\n\nChoose tile rank, swizzle, multicast, issue cadence, and stage count from the actual access pattern and resource budget. More distinct stages consume more shared memory; there is no universal optimum of three to five stages. Profile the target GPU and record the copy shape, descriptor, cluster mask, stage count, shared-memory use, occupancy, warmup, repetitions, and baseline."}, "reason": {"statement": "Replace a deceptively general factory with a constraints checklist and official complete sample.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#encoding-a-tensor-map-on-device"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "```cuda\n// TMA load: single thread issues, hardware executes asynchronously\n__device__ void tma_load_tile(\n const CUtensorMap* desc,\n void* smem_ptr,\n uint64_t* mbar_ptr, // mbarrier for synchronization\n int coord_x, int coord_y\n) {\n if (threadIdx.x == 0) {\n // Set expected bytes on the mbarrier\n uint32_t expected_bytes = TILE_M * TILE_N * sizeof(half);\n asm volatile(\n \"mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1;\"\n :\n : \"r\"((uint32_t)__cvta_generic_to_shared(mbar_ptr)),\n \"r\"(expected_bytes)\n );\n\n // Issue TMA copy\n asm volatile(\n \"cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes \"\n \"[%0], [%1, {%2, %3}], [%4];\"\n :\n : \"r\"((uint32_t)__cvta_generic_to_shared(smem_ptr)),\n \"l\"(desc),\n \"r\"(coord_x), \"r\"(coord_y),\n \"r\"((uint32_t)__cvta_generic_to_shared(mbar_ptr))\n );\n }\n}\n```"}, "after": {"statement": "PTX ISA 9.0 defines this representative 2D CTA-local form:\n\n```ptx\ncp.async.bulk.tensor.2d.shared::cta.global.mbarrier::complete_tx::bytes\n [dst_smem], [tensor_map, {x, y}], [full_barrier];\n```\n\nThe instruction is non-blocking. A common one-producer phase with one or more loads uses this accounting:\n\n1. Initialize and publish the stage's mbarrier with the intended pending-arrival count.\n2. The producer performs one `mbarrier.arrive.expect_tx` for its software arrival and the sum of bytes that all loads in this phase will complete.\n3. Issue the TMA loads against that barrier.\n4. Each completed load performs `complete_tx` for its copied byte count; it does **not** perform another arrival.\n5. Consumers wait with the correct state token or per-stage parity and acquire semantics before reading the destination.\n\nThe phase completes only after pending arrivals and tx-count are both zero. If a design performs multiple software arrivals instead, its initialized count must match them exactly. See [mbarrier](mbarrier.md) for lifecycle, phase, and memory-ordering rules."}, "reason": {"statement": "Teach one explicit phase-accounting sequence instead of an unsafe reusable helper.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-phase-completion", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "```cuda\n// TMA store: write a tile from shared memory back to global memory\n__device__ void tma_store_tile(\n const CUtensorMap* desc,\n const void* smem_ptr,\n int coord_x, int coord_y\n) {\n if (threadIdx.x == 0) {\n asm volatile(\n \"cp.async.bulk.tensor.2d.global.shared::cta \"\n \"[%0, {%1, %2}], [%3];\"\n :\n : \"l\"(desc),\n \"r\"(coord_x), \"r\"(coord_y),\n \"r\"((uint32_t)__cvta_generic_to_shared(smem_ptr))\n );\n\n // Commit the store\n asm volatile(\"cp.async.bulk.commit_group;\");\n }\n}\n```"}, "after": {"statement": "A tensor store uses bulk-group completion rather than the load's mbarrier protocol:\n\n```ptx\ncp.async.bulk.tensor.2d.global.shared::cta.bulk_group\n [tensor_map, {x, y}], [src_smem];\ncp.async.bulk.commit_group;\ncp.async.bulk.wait_group 0;\n```\n\nThe wait may be delayed to overlap independent work. It must occur before the issuing thread reuses the source shared memory or before code that requires store completion. `commit_group` creates the group; it is not itself a completion wait."}, "reason": {"statement": "Show the required qualifier and explicit wait boundary.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "TMA uses mbarriers (memory barriers) for producer-consumer synchronization. The pattern is:\n\n1. **Producer** (TMA): arrives at the barrier when the transfer completes, decrementing the expected transaction count.\n2. **Consumer** (compute warps): waits on the barrier before reading the loaded data."}, "after": {"statement": "PTX ISA 9.0 defines this representative 2D CTA-local form:\n\n```ptx\ncp.async.bulk.tensor.2d.shared::cta.global.mbarrier::complete_tx::bytes\n [dst_smem], [tensor_map, {x, y}], [full_barrier];\n```\n\nThe instruction is non-blocking. A common one-producer phase with one or more loads uses this accounting:\n\n1. Initialize and publish the stage's mbarrier with the intended pending-arrival count.\n2. The producer performs one `mbarrier.arrive.expect_tx` for its software arrival and the sum of bytes that all loads in this phase will complete.\n3. Issue the TMA loads against that barrier.\n4. Each completed load performs `complete_tx` for its copied byte count; it does **not** perform another arrival.\n5. Consumers wait with the correct state token or per-stage parity and acquire semantics before reading the destination.\n\nThe phase completes only after pending arrivals and tx-count are both zero. If a design performs multiple software arrivals instead, its initialized count must match them exactly. See [mbarrier](mbarrier.md) for lifecycle, phase, and memory-ordering rules."}, "reason": {"statement": "Separate software arrival from hardware byte completion.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-phase-completion"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "```cuda\n// Multi-stage pipeline with TMA + mbarrier\n__device__ void pipelined_mainloop(\n const CUtensorMap* desc_a,\n const CUtensorMap* desc_b,\n void* smem_a_stages[NUM_STAGES],\n void* smem_b_stages[NUM_STAGES],\n uint64_t* mbar[NUM_STAGES],\n int num_k_tiles\n) {\n // Prologue: fill the first NUM_STAGES-1 stages\n for (int s = 0; s < NUM_STAGES - 1 && s < num_k_tiles; ++s) {\n tma_load_tile(desc_a, smem_a_stages[s], mbar[s], 0, s);\n tma_load_tile(desc_b, smem_b_stages[s], mbar[s], s, 0);\n }\n\n // Mainloop\n for (int k = 0; k < num_k_tiles; ++k) {\n int stage = k % NUM_STAGES;\n\n // Wait for data to arrive in this stage\n mbarrier_wait(mbar[stage]);\n\n // Issue MMA using this stage's SMEM buffers\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 1;\"\n :\n : \"r\"(tmem_acc),\n \"l\"(make_desc(smem_a_stages[stage])),\n \"l\"(make_desc(smem_b_stages[stage])),\n \"r\"(0)\n );\n }\n\n // Prefetch next stage\n int next_k = k + NUM_STAGES - 1;\n if (next_k < num_k_tiles) {\n int next_stage = next_k % NUM_STAGES;\n tma_load_tile(desc_a, smem_a_stages[next_stage],\n mbar[next_stage], 0, next_k);\n tma_load_tile(desc_b, smem_b_stages[next_stage],\n mbar[next_stage], next_k, 0);\n }\n }\n}\n```"}, "after": {"statement": "A common Blackwell GEMM data path is:\n\n`GMEM -> TMA -> SMEM -> tcgen05.mma -> TMEM -> tcgen05.ld -> registers -> output store`\n\nEach reusable pipeline stage needs two independent ownership transitions:\n\n- **full:** TMA has finished producing the shared-memory operands, so the MMA consumer may read them; and\n- **empty:** asynchronous MMA has stopped reading those operands, so the TMA producer may overwrite the stage.\n\nTrack full and empty state per stage. Account transaction bytes once, track each barrier's own phase, and do not equate CTA synchronization or a tcgen05 fence with async completion. A complete CUTLASS pipeline is safer evidence than a shortened helper that omits one ownership edge.\n\nChoose tile rank, swizzle, multicast, issue cadence, and stage count from the actual access pattern and resource budget. More distinct stages consume more shared memory; there is no universal optimum of three to five stages. Profile the target GPU and record the copy shape, descriptor, cluster mask, stage count, shared-memory use, occupancy, warmup, repetitions, and baseline."}, "reason": {"statement": "Replace unrepairable pseudocode with invariant-based stage lifecycle and a pinned complete implementation.", "urls": []}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "```cuda\n// Initialize an mbarrier\n__device__ void mbarrier_init(uint64_t* mbar, int arrive_count) {\n if (threadIdx.x == 0) {\n asm volatile(\n \"mbarrier.init.shared.b64 [%0], %1;\"\n :\n : \"r\"((uint32_t)__cvta_generic_to_shared(mbar)),\n \"r\"(arrive_count)\n );\n }\n}\n\n// Wait for an mbarrier to complete (phase-based)\n__device__ void mbarrier_wait(uint64_t* mbar, int phase) {\n uint32_t mbar_addr = (uint32_t)__cvta_generic_to_shared(mbar);\n asm volatile(\n \"{\\n\"\n \".reg .pred p;\\n\"\n \"WAIT_LOOP:\\n\"\n \"mbarrier.try_wait.parity.shared.b64 p, [%0], %1;\\n\"\n \"@!p bra WAIT_LOOP;\\n\"\n \"}\\n\"\n :\n : \"r\"(mbar_addr), \"r\"(phase)\n );\n}\n```"}, "after": {"statement": "PTX ISA 9.0 defines this representative 2D CTA-local form:\n\n```ptx\ncp.async.bulk.tensor.2d.shared::cta.global.mbarrier::complete_tx::bytes\n [dst_smem], [tensor_map, {x, y}], [full_barrier];\n```\n\nThe instruction is non-blocking. A common one-producer phase with one or more loads uses this accounting:\n\n1. Initialize and publish the stage's mbarrier with the intended pending-arrival count.\n2. The producer performs one `mbarrier.arrive.expect_tx` for its software arrival and the sum of bytes that all loads in this phase will complete.\n3. Issue the TMA loads against that barrier.\n4. Each completed load performs `complete_tx` for its copied byte count; it does **not** perform another arrival.\n5. Consumers wait with the correct state token or per-stage parity and acquire semantics before reading the destination.\n\nThe phase completes only after pending arrivals and tx-count are both zero. If a design performs multiple software arrivals instead, its initialized count must match them exactly. See [mbarrier](mbarrier.md) for lifecycle, phase, and memory-ordering rules.\n\nA common Blackwell GEMM data path is:\n\n`GMEM -> TMA -> SMEM -> tcgen05.mma -> TMEM -> tcgen05.ld -> registers -> output store`\n\nEach reusable pipeline stage needs two independent ownership transitions:\n\n- **full:** TMA has finished producing the shared-memory operands, so the MMA consumer may read them; and\n- **empty:** asynchronous MMA has stopped reading those operands, so the TMA producer may overwrite the stage.\n\nTrack full and empty state per stage. Account transaction bytes once, track each barrier's own phase, and do not equate CTA synchronization or a tcgen05 fence with async completion. A complete CUTLASS pipeline is safer evidence than a shortened helper that omits one ownership edge."}, "reason": {"statement": "Refer to the verified mbarrier page and state lifecycle requirements rather than ship a partial abstraction.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-try-wait", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-phase-completion"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "TMA multicast sends a single GMEM tile to **multiple CTAs within a cluster** simultaneously. This is critical for GEMM where the B operand is shared across M-axis tiles.\n\n```cuda\n// Multicast TMA: load B tile to all CTAs in the cluster\n__device__ void tma_multicast_load(\n const CUtensorMap* desc,\n void* smem_ptr,\n uint64_t* mbar_ptr,\n int coord_x, int coord_y,\n uint16_t multicast_mask // bitmask: which CTAs in cluster receive the data\n) {\n if (threadIdx.x == 0) {\n uint32_t expected_bytes = TILE_K * TILE_N * sizeof(half);\n asm volatile(\n \"mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1;\"\n :\n : \"r\"((uint32_t)__cvta_generic_to_shared(mbar_ptr)),\n \"r\"(expected_bytes)\n );\n\n asm volatile(\n \"cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster \"\n \"[%0], [%1, {%2, %3}], [%4], %5;\"\n :\n : \"r\"((uint32_t)__cvta_generic_to_shared(smem_ptr)),\n \"l\"(desc),\n \"r\"(coord_x), \"r\"(coord_y),\n \"r\"((uint32_t)__cvta_generic_to_shared(mbar_ptr)),\n \"h\"(multicast_mask)\n );\n }\n}\n```"}, "after": {"statement": "The cluster form copies a global tile to the same shared-memory offset in every CTA selected by a 16-bit mask:\n\n```ptx\ncp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster\n [dst_smem], [tensor_map, {x, y}], [full_barrier], cta_mask;\n```\n\nFor `cta_group::1` (the default), the completion signal is also multicast to the same barrier offset in every selected destination CTA. A correct design therefore:\n\n- launches an explicit cluster and keeps every destination CTA's shared memory alive;\n- initializes corresponding destination barriers before the elected issuer can start;\n- uses one cluster-wide elected issuer, not one `threadIdx.x == 0` issuer in every CTA;\n- includes only valid destination CTA ranks in the mask; and\n- has every destination wait on its own corresponding barrier phase before consuming the tile.\n\nFor GEMM tiles with the same N range and different M ranges, the CTAs use different A tiles but the same B tile, so multicast can avoid duplicate logical B-load requests. It does not promise an exact `cluster_size` reduction in measured DRAM traffic or elapsed time; caches, mask population, transaction behavior, and resource costs affect the result."}, "reason": {"statement": "Replace incomplete executable code with the cluster ownership and barrier invariants.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "```\nCluster: 2 CTAs (CTA0 and CTA1) each computing different M-tiles of the same N column\n\nCTA0: computes C[0:128, 0:256] -- needs A[0:128, :] and B[:, 0:256]\nCTA1: computes C[128:256, 0:256] -- needs A[128:256, :] and B[:, 0:256]\n\nB[:, 0:256] is SHARED -- multicast it once from GMEM to both CTAs\nA tiles are UNIQUE -- each CTA loads its own A tile\n\nResult: B bandwidth is halved (1 GMEM read serves 2 CTAs)\n```"}, "after": {"statement": "The cluster form copies a global tile to the same shared-memory offset in every CTA selected by a 16-bit mask:\n\n```ptx\ncp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster\n [dst_smem], [tensor_map, {x, y}], [full_barrier], cta_mask;\n```\n\nFor `cta_group::1` (the default), the completion signal is also multicast to the same barrier offset in every selected destination CTA. A correct design therefore:\n\n- launches an explicit cluster and keeps every destination CTA's shared memory alive;\n- initializes corresponding destination barriers before the elected issuer can start;\n- uses one cluster-wide elected issuer, not one `threadIdx.x == 0` issuer in every CTA;\n- includes only valid destination CTA ranks in the mask; and\n- has every destination wait on its own corresponding barrier phase before consuming the tile.\n\nFor GEMM tiles with the same N range and different M ranges, the CTAs use different A tiles but the same B tile, so multicast can avoid duplicate logical B-load requests. It does not promise an exact `cluster_size` reduction in measured DRAM traffic or elapsed time; caches, mask population, transaction behavior, and resource costs affect the result.\n\nA common Blackwell GEMM data path is:\n\n`GMEM -> TMA -> SMEM -> tcgen05.mma -> TMEM -> tcgen05.ld -> registers -> output store`\n\nEach reusable pipeline stage needs two independent ownership transitions:\n\n- **full:** TMA has finished producing the shared-memory operands, so the MMA consumer may read them; and\n- **empty:** asynchronous MMA has stopped reading those operands, so the TMA producer may overwrite the stage.\n\nTrack full and empty state per stage. Account transaction bytes once, track each barrier's own phase, and do not equate CTA synchronization or a tcgen05 fence with async completion. A complete CUTLASS pipeline is safer evidence than a shortened helper that omits one ownership edge."}, "reason": {"statement": "State logical load reuse without an unmeasured hardware-traffic factor.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "```\nWithout swizzle (linear):\n Row 0: bytes [0, 1, 2, ..., 127]\n Row 1: bytes [128, 129, ..., 255]\n\nWith 128B swizzle:\n Row 0: bytes [0, 1, ..., 127] (unchanged)\n Row 1: bytes [128, 129, ..., 255] XOR pattern applied\n Row 2: bytes [256, ...] XOR pattern applied differently\n ...\n```\n\nThe swizzle eliminates bank conflicts when the tensor core reads operand tiles from SMEM."}, "after": {"statement": "TMA supports no swizzle and multiple swizzled shared-memory layouts, including 32B, 64B, and 128B spans plus newer variants for selected types. Swizzling rearranges chunks across shared-memory banks. The consumer must address the matching logical layout; the exact mapping also depends on the documented shared-memory base-offset rule.\n\nThere is no universal rule that every Blackwell or `tcgen05.mma` input uses 128B swizzling. The TMA tensor-map swizzle, destination base alignment, leading dimension, and the tcgen05 shared-memory descriptor must describe the **same** legal layout. PTX defines no-, 32B-, 64B-, and 128B-swizzled tcgen05 descriptors with kind-, type-, shape-, and layout-specific constraints.\n\nA matched swizzle can reduce or remove bank conflicts for a particular access pattern. It does not make every possible consumer access conflict-free."}, "reason": {"statement": "Link the normative mapping and explain the producer/consumer layout match.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#the-swizzle-modes", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-shared-memory-layout-swizzling"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "| Maximize TMA utilization | Keep the TMA unit busy with back-to-back loads across pipeline stages |\n| Use multicast for shared operands | Reduces GMEM bandwidth by cluster_size x for shared tiles |\n| Always use 128B swizzle on Blackwell | Non-128B swizzle produces incorrect tcgen05 results |\n| Prefer 2D TMA over manual addressing | TMA handles out-of-bounds clamping, padding, and strided access |\n| Pipeline depth | 3-5 stages typically optimal; more stages increase SMEM usage |"}, "after": {"statement": "A common Blackwell GEMM data path is:\n\n`GMEM -> TMA -> SMEM -> tcgen05.mma -> TMEM -> tcgen05.ld -> registers -> output store`\n\nEach reusable pipeline stage needs two independent ownership transitions:\n\n- **full:** TMA has finished producing the shared-memory operands, so the MMA consumer may read them; and\n- **empty:** asynchronous MMA has stopped reading those operands, so the TMA producer may overwrite the stage.\n\nTrack full and empty state per stage. Account transaction bytes once, track each barrier's own phase, and do not equate CTA synchronization or a tcgen05 fence with async completion. A complete CUTLASS pipeline is safer evidence than a shortened helper that omits one ownership edge."}, "reason": {"statement": "Replace folklore with a measurement and resource checklist.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#asynchronous-data-copies-using-the-tensor-memory-accelerator-tma"]}} +{"path": "wiki/hardware/tma.md", "before": {"statement": "```python\n# CuTe-DSL TMA copy setup for Blackwell GEMM\nfrom cute import *\n\n# Define TMA copy atom for operand A (BF16, 128x64 tile)\ntma_a = make_tma_copy(\n SM100_TMA_LOAD_2D,\n tensor_a, # global tensor\n smem_layout_a, # shared memory layout\n tile_shape=(128, 64), # tile dimensions\n swizzle=Swizzle(7, 0, 4), # 128-byte swizzle\n multicast_mask=None # no multicast for A\n)\n\n# Define TMA copy atom for operand B with multicast\ntma_b = make_tma_copy(\n SM100_TMA_LOAD_2D_MULTICAST,\n tensor_b,\n smem_layout_b,\n tile_shape=(64, 256),\n swizzle=Swizzle(7, 0, 4), # 128-byte swizzle\n multicast_mask=cluster_mask # multicast B to all CTAs in cluster\n)\n```"}, "after": {"statement": "Choose tile rank, swizzle, multicast, issue cadence, and stage count from the actual access pattern and resource budget. More distinct stages consume more shared memory; there is no universal optimum of three to five stages. Profile the target GPU and record the copy shape, descriptor, cluster mask, stage count, shared-memory use, occupancy, warmup, repetitions, and baseline."}, "reason": {"statement": "Link a complete pinned tutorial rather than fabricate a simplified API.", "urls": []}} +{"path": "wiki/kernels/deepgemm.md", "before": {"statement": "DeepGEMM is DeepSeek's open-source FP8 GEMM library providing high-performance matrix multiplication with fine-grained per-tile/per-block scaling. The core kernel is remarkably compact (~300 lines), yet achieves approximately 90% utilization on H800. It supports both Hopper (SM90 via WGMMA) and Blackwell (SM100 via tcgen05.mma) architectures, and includes specialized MoE grouped GEMM layouts."}, "after": {"statement": "DeepGEMM is DeepSeek's open-source tensor-core kernel library. This page describes the FP8 GEMM paths at commit [`891d57b4db1071624b5c8fa0d1e51cb317fa709f`](https://github.com/deepseek-ai/DeepGEMM/tree/891d57b4db1071624b5c8fa0d1e51cb317fa709f), with byte-verified SM90 and SM100 kernel files stored locally. The pinned project requires an SM90 or SM100 GPU, CUDA 12.3 or newer for SM90, and CUDA 12.9 or newer for SM100.\n\nDeepGEMM contains multiple kernels and APIs; the local SM90 and SM100 files below are representative FP8 1D1D implementations, not the whole library.\n\nThe pinned README reports that DeepGEMM reached **up to 1550 TFLOPS on H800** in an April 2025 news item. It does not bind that peak to `M=N=K=4096`, state approximately 90% utilization, or preserve enough benchmark conditions for reproduction. The unsupported structured performance record and table have therefore been removed; the surviving number is source-reported only and should not be compared across software, clocks, shapes, or GPUs without a controlled rerun."}, "reason": {"statement": "Scope the overview to the pinned library and separate the surviving source-reported peak from unsupported utilization and size claims.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/pull/86"]}} +{"path": "wiki/kernels/deepgemm.md", "before": {"statement": "The key innovation is the fine-grained quantization scheme: tile-wise 1x128 scaling for activations and block-wise 128x128 scaling for weights, which prevents outlier values from destroying quantization precision.\n\n```\nActivations (tile-wise 1x128):\n +-----------+-----------+-----------+\n | tile 0 | tile 1 | tile 2 | <-- each tile: 1 row x 128 cols\n | scale: s0 | scale: s1 | scale: s2 | <-- one FP32 scale per tile\n +-----------+-----------+-----------+\n\nWeights (block-wise 128x128):\n +---------------+---------------+\n | block (0,0) | block (0,1) | <-- each block: 128 rows x 128 cols\n | scale: s_00 | scale: s_01 | <-- one FP32 scale per block\n +---------------+---------------+\n | block (1,0) | block (1,1) |\n | scale: s_10 | scale: s_11 |\n +---------------+---------------+\n```"}, "after": {"statement": "The [DeepSeek-V3 Technical Report v2](https://arxiv.org/abs/2412.19437v2) defines the training scheme that motivates this path:\n\n- activations are grouped per token and per 128 channels, forming `1 x 128` tiles;\n- weights are grouped per 128 input channels and 128 output channels, forming `128 x 128` blocks; and\n- smaller groups let scales adapt more locally, which the paper says better accommodates outliers. This is a scoped accuracy motivation, not a guarantee that quantization error disappears.\n\nScale representation is architecture-specific in the pinned DeepGEMM interface. SM90 consumes FP32 scale factors. SM100 consumes packed UE8M0 factors, four UE8M0 values per `torch.int`. The pinned SM90 1D1D kernel fixes `BLOCK_K == 128`; the SM100 1D1D template accepts K scale granularities of 32 or 128 for each operand."}, "reason": {"statement": "Preserve exact granularity while qualifying the numerical benefit and separating architecture-specific scale representations.", "urls": ["https://arxiv.org/abs/2412.19437v2", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm100_fp8_gemm_1d1d.cuh"]}} +{"path": "wiki/kernels/deepgemm.md", "before": {"statement": "On Hopper, the Tensor Core accumulator has limited precision (~FP22, not true FP32). DeepGEMM mitigates this by promoting partial sums to a separate FP32 accumulator on CUDA Cores every Nc=128 columns (4 consecutive WGMMA operations)."}, "after": {"statement": "The DeepSeek-V3 report characterizes H800 FP8 Tensor Core accumulation as retaining about 14 bits. Its `Nc=128` strategy accumulates 128 elements of the GEMM inner dimension—four WGMMAs in the described configuration—before moving the partial result to FP32 registers on CUDA cores.\n\nThe pinned [`sm90_fp8_gemm_1d1d.cuh`](../../artifacts/kernels/deepgemm/full/sm90_fp8_gemm_1d1d.cuh) implements that structure directly:\n\n1. A math warp-group owns `float accum[...]` for WGMMA output and zero-initialized `float final_accum[...]` for promoted results.\n2. For each 128-element K block, it reads the A and B FP32 factors from shared memory, issues `BLOCK_K / WGMMA::K` WGMMA operations, commits the group, and waits for completion.\n3. The `Promote with scales` loop multiplies each partial result by its A and B factors and adds it to `final_accum`.\n4. After all K blocks, the kernel stages the final FP32 values for the epilogue/store path.\n\nThe exact upstream file is the reproducible reference. It should not be replaced by a sketch using half accumulators or by deriving the promotion interval from WGMMA's output-N tile.\n\nThe following is a verbatim fragment of the SM90 promotion loop; the linked full file supplies its surrounding declarations and loop bounds:\n\n```cpp\nconst float &scale_b_0 = scales_b[i].x;\nconst float &scale_b_1 = scales_b[i].y;\nfinal_accum[i * 4 + 0] += scale_a_0 * scale_b_0 * accum[i * 4 + 0];\nfinal_accum[i * 4 + 1] += scale_a_0 * scale_b_1 * accum[i * 4 + 1];\nfinal_accum[i * 4 + 2] += scale_a_1 * scale_b_0 * accum[i * 4 + 2];\nfinal_accum[i * 4 + 3] += scale_a_1 * scale_b_1 * accum[i * 4 + 3];\n```"}, "reason": {"statement": "Use the paper's measured retained-bit characterization and exact K-interval definition.", "urls": ["https://arxiv.org/abs/2412.19437v2", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d1d.cuh"]}} +{"path": "wiki/kernels/deepgemm.md", "before": {"statement": "```cpp\n// SM90 path: WGMMA with Nc=128 CUDA Core promotion\n// Every 4 WGMMAs, promote accumulated result to FP32 CUDA core accumulator\nconstexpr int Nc = 128; // Promotion interval (4 WGMMAs of n=32 each)\nconstexpr int WGMMA_N = 32;\n\nfloat cuda_core_acc[TILE_M][TILE_N] = {0}; // FP32 accumulator on CUDA Cores\n\nfor (int k = 0; k < K; k += Nc) {\n // Run 4 consecutive WGMMAs with TC-limited precision accumulation\n __half2 tc_acc[TILE_M][WGMMA_N]; // Tensor Core accumulator (~FP22)\n memset(tc_acc, 0, sizeof(tc_acc));\n\n for (int sub_k = 0; sub_k < Nc; sub_k += WGMMA_K) {\n wgmma_mma_async(tc_acc, A_smem + sub_k, B_smem + sub_k);\n }\n wgmma_wait();\n\n // Promote: add TC result to CUDA Core FP32 accumulator\n // This prevents precision loss from repeated FP22 accumulation\n for (int m = 0; m < TILE_M; m++)\n for (int n = 0; n < TILE_N; n++)\n cuda_core_acc[m][n] += (float)tc_acc[m][n] * scale_a[m] * scale_b[n];\n}\n```"}, "after": {"statement": "The DeepSeek-V3 report characterizes H800 FP8 Tensor Core accumulation as retaining about 14 bits. Its `Nc=128` strategy accumulates 128 elements of the GEMM inner dimension—four WGMMAs in the described configuration—before moving the partial result to FP32 registers on CUDA cores.\n\nThe pinned [`sm90_fp8_gemm_1d1d.cuh`](../../artifacts/kernels/deepgemm/full/sm90_fp8_gemm_1d1d.cuh) implements that structure directly:\n\n1. A math warp-group owns `float accum[...]` for WGMMA output and zero-initialized `float final_accum[...]` for promoted results.\n2. For each 128-element K block, it reads the A and B FP32 factors from shared memory, issues `BLOCK_K / WGMMA::K` WGMMA operations, commits the group, and waits for completion.\n3. The `Promote with scales` loop multiplies each partial result by its A and B factors and adds it to `final_accum`.\n4. After all K blocks, the kernel stages the final FP32 values for the epilogue/store path.\n\nThe exact upstream file is the reproducible reference. It should not be replaced by a sketch using half accumulators or by deriving the promotion interval from WGMMA's output-N tile.\n\nThe following is a verbatim fragment of the SM90 promotion loop; the linked full file supplies its surrounding declarations and loop bounds:\n\n```cpp\nconst float &scale_b_0 = scales_b[i].x;\nconst float &scale_b_1 = scales_b[i].y;\nfinal_accum[i * 4 + 0] += scale_a_0 * scale_b_0 * accum[i * 4 + 0];\nfinal_accum[i * 4 + 1] += scale_a_0 * scale_b_1 * accum[i * 4 + 1];\nfinal_accum[i * 4 + 2] += scale_a_1 * scale_b_0 * accum[i * 4 + 2];\nfinal_accum[i * 4 + 3] += scale_a_1 * scale_b_1 * accum[i * 4 + 3];\n```"}, "reason": {"statement": "Replace invented executable-looking code with a precise walkthrough and link to the byte-verified source.", "urls": ["https://arxiv.org/abs/2412.19437v2", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d1d.cuh"]}} +{"path": "wiki/kernels/deepgemm.md", "before": {"statement": "```cpp\n// SM100 path: tcgen05.mma with native block scaling\n// Scaling factors packed as UE8M0 (4 values per uint32)\n// No explicit CUDA core promotion needed -- TMEM accumulates in full precision\n\n// Pack 4 UE8M0 scale factors into a single uint32\nuint32_t packed_scales = pack_ue8m0(sf[0], sf[1], sf[2], sf[3]);\n\n// tcgen05.mma reads A/B from SMEM, accumulates into TMEM\n// Block scale applied natively during MMA\nasm volatile(\n \"tcgen05.mma.cta_group::1.kind::f8f6f4\"\n \" [%0], %1, %2, %3, %4;\"\n :\n : \"l\"(tmem_addr), \"l\"(a_smem_addr), \"l\"(b_smem_addr),\n \"r\"(packed_scales), \"n\"(SCALE_D_ENABLED)\n);\n```"}, "after": {"statement": "The pinned [`sm100_fp8_gemm_1d1d.cuh`](../../artifacts/kernels/deepgemm/full/sm100_fp8_gemm_1d1d.cuh) uses a different data path:\n\n1. It creates a block-scaled UMMA instruction descriptor with a `float` accumulator type and `cutlass::float_ue8m0_t` scale type.\n2. TMA loads packed scale-factor data into shared memory. UTCCP copies selected scale blocks from shared memory into dedicated SFA and SFB columns in TMEM.\n3. The elected issuing thread calls the SM100 UMMA wrapper with shared-memory operand descriptors, the TMEM accumulator column, a runtime instruction descriptor containing scale IDs, and the two TMEM scale addresses.\n4. The epilogue drains the TMEM accumulator after the kernel's full/empty barrier protocol says it is ready.\n\nThis path does not contain the SM90 `final_accum` CUDA-core promotion loop. That difference does not justify a blanket claim that every tcgen05 accumulator mode or datatype has \"full FP32\" behavior; the accumulator type and instruction form remain part of the selected operation."}, "reason": {"statement": "Point to the exact upstream block-scaled UMMA sequence instead of presenting fabricated PTX.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm100_fp8_gemm_1d1d.cuh"]}} +{"path": "wiki/kernels/deepgemm.md", "before": {"statement": "DeepGEMM provides three grouped GEMM layouts tailored for MoE workloads, where only the M-axis varies (different token counts per expert) while N and K remain fixed:\n\n```\nLayout 1: Contiguous (prefill)\n Expert 0: M0 tokens ──┐\n Expert 1: M1 tokens ──┤── All packed contiguously in memory\n Expert 2: M2 tokens ──┘ Index array stores cumulative offsets\n\nLayout 2: Masked (decode with CUDA graphs)\n Fixed-size M_max allocation per expert\n Binary mask indicates valid tokens\n Compatible with CUDA graph capture (no dynamic shapes)\n\nLayout 3: K-grouped (weight gradients)\n Groups along K-axis instead of M-axis\n Used for computing dW in MoE training backward\n```\n\n```cpp\n// Contiguous grouped GEMM dispatch\n// problem_sizes[i] = {M_i, N, K} for expert i\nvoid grouped_gemm_contiguous(\n const fp8_t* A, // All expert inputs packed\n const fp8_t* B, // Expert weights [num_experts, N, K]\n float* C, // Output packed\n const int* offsets, // Cumulative M offsets per expert\n int num_experts\n) {\n // Each thread block picks an expert via tile scheduling\n // M-axis tiles distributed across experts using offset lookup\n int expert_id = binary_search(offsets, num_experts, tile_m_start);\n int local_m = tile_m_start - offsets[expert_id];\n\n // Standard GEMM tile with expert-specific B matrix\n compute_tile(A + offsets[expert_id] * K,\n B + expert_id * N * K,\n C + offsets[expert_id] * N,\n local_m, N, K);\n}\n```\n\n- MoE expert computation with variable token counts per expert"}, "after": {"statement": "The pinned interface distinguishes three workload arrangements rather than treating all of them as M-varying layouts:\n\n| M-grouped contiguous | M | N and K | Either a group index for each packed M row or a prefix-sum M layout, depending on the selected option |\n| M-grouped masked | Valid M within each `[G, M, K]` allocation | Maximum M, N, and K tensor extents | An integer `masked_m[G]` vector holding each group's valid M length, not a binary mask |\n| K-grouped contiguous | K | M and N | Per-group K lengths plus their device tensor; used for weight-gradient-style grouped GEMM |\n\nContiguous M grouping is intended for variable per-expert token counts in training forward or inference prefill. Masked M grouping keeps fixed allocations suitable for CUDA-graph decode while limiting work to each group's valid M. The pinned repository provides K-grouped NT on SM90 and K-grouped TN on SM100 for the documented FP8 paths.\n\n- M-grouped contiguous segments must satisfy the configured M/K alignment. Masked mode uses valid-length integers, while K-grouped mode has different shapes and architecture-specific layout variants."}, "reason": {"statement": "Separate M-grouped contiguous, M-grouped masked, and K-grouped APIs with their exact invariants.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp"]}} +{"path": "wiki/kernels/deepgemm.md", "before": {"statement": "DeepGEMM uses JIT compilation via NVRTC to specialize kernels per problem shape at runtime. This avoids the combinatorial explosion of pre-compiled template instantiations while still achieving optimal register allocation and loop unrolling.\n\n```cpp\n// Lightweight JIT module: compile per-shape kernel at first call\nauto kernel = jit_compile(\n \"deepgemm_fp8\",\n {{\"M\", M}, {\"N\", N}, {\"K\", K},\n {\"BLOCK_M\", 128}, {\"BLOCK_N\", 128}, {\"BLOCK_K\", 64},\n {\"NUM_STAGES\", 4}}\n);\nkernel.launch(A, B, C, scales_a, scales_b, stream);\n```"}, "after": {"statement": "DeepGEMM generates and compiles kernel source at runtime. At the pinned commit, the compiler defaults to NVCC. Setting `DG_JIT_USE_NVRTC=1` selects the optional NVRTC path; the project warns that this may reduce performance for some cases.\n\nThe cache key includes the kernel name, compiler signature, compiler flags, and generated source. A cache hit reuses the existing kernel runtime; a miss compiles a CUBIN in a temporary directory and then publishes the completed cache entry. Consequently, a new specialization has first-use compilation/loading cost, whereas matching later calls can reuse the artifact. This mechanism does not guarantee globally optimal register allocation or unrolling.\n\n- JIT cache misses add compilation latency, and NVRTC is optional rather than the default."}, "reason": {"statement": "Describe the generated-code cache and compiler selection exactly; remove the fabricated API and optimality guarantee.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/jit/compiler.hpp"]}} +{"path": "wiki/kernels/deepgemm.md", "before": {"statement": "performance_claims:\n- gpu: H800\n dtype: fp8\n shape: M=4096, N=4096, K=4096\n metric: TFLOPS\n value: 1550\n utilization: ~90%\n source_id: blog-deepgemm\n\n| H800 | FP8 | M=4096, N=4096, K=4096 | 1550 | ~90% |"}, "after": {"statement": "performance_claims: []\n\nThe pinned README reports that DeepGEMM reached **up to 1550 TFLOPS on H800** in an April 2025 news item. It does not bind that peak to `M=N=K=4096`, state approximately 90% utilization, or preserve enough benchmark conditions for reproduction. The unsupported structured performance record and table have therefore been removed; the surviving number is source-reported only and should not be compared across software, clocks, shapes, or GPUs without a controlled rerun."}, "reason": {"statement": "Delete the unsupported structured measurement and retain only the exact source-reported up-to statement with its missing-condition caveat.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/pull/86"]}} +{"path": "wiki/kernels/deepgemm.md", "before": {"statement": "- Fine-grained scaling adds overhead vs. per-tensor scaling -- only beneficial when outlier sensitivity matters"}, "after": {"statement": "- Input transposition, FP8 casting, and scale-layout preparation are separate from the optimized GEMM kernels; the project supplies utilities but warns they may be slower than fusing the work into producers.\n\n- Fine-grained scaling's accuracy and cost tradeoffs depend on quantization recipe, target architecture, scale preparation, fusion, and workload. There is no universal per-tensor-scaling penalty or single \"use only for outliers\" rule."}, "reason": {"statement": "Replace the categorical rule with architecture- and workload-scoped tradeoffs.", "urls": ["https://arxiv.org/abs/2412.19437v2", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "Written entirely in CuTe DSL (Python), FA4 compiles 20-30x faster than equivalent CUTLASS C++ template code while matching or exceeding cuDNN performance."}, "after": {"statement": "FlashAttention-4 is an attention algorithm and CuTe DSL implementation designed around Blackwell's asymmetric throughput: B200 tensor-core throughput grows much more than its special-function and shared-memory resources. This page separates two scopes:\n\n- the [FA4 paper v1](https://arxiv.org/abs/2603.05451v1), which studies the SM100/B200 algorithm and reports the authors' measurements; and\n- the public implementation at Dao-AILab/flash-attention commit [`a369df707e1980fb328abcc1733e3457ec10155f`](https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute), which is the source snapshot used for implementation statements below.\n\nThe paper implementation is written in CuTe DSL. Its compilation comparison is against corresponding FA3 CUTLASS kernels: forward compiles in 2.5 seconds instead of 55 seconds, and backward in 1.4 seconds instead of 45 seconds. Those are single-kernel source-reported compile measurements, not an end-to-end installation or runtime speedup.\n\nThe first-party sources contain two different source-reported peak values. Paper v1 reports **up to 1613 TFLOPS/s on B200 BF16, or 71% of the peak convention used by the authors**. Tri Dao's blog reports **up to 1605 TFLOPS/s, also labeled 71%**, plus up to 1.3x over cuDNN 9.13 and up to 2.7x over Triton.\n\nThe paper's benchmark suite spans sequence lengths from 1K through 32K and multiple query/value head-dimension pairs under a fixed total-token convention. Neither textual source establishes the former single row that attached 1605 TFLOPS, 71%, and both speedup ranges specifically to `seqlen=8192, headdim=128`. The structured performance record is therefore empty, and no complement-of-71% time breakdown is inferred."}, "reason": {"statement": "Separate the measured compile comparison from scoped runtime maxima.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "```python\n# CuTe DSL: Ping-pong tile scheduling (simplified)\n# Two query tiles per CTA, alternating MMA and softmax phases\n\n@cute.kernel\ndef flash_attention_4_fwd(Q, K, V, O, L):\n # Each CTA processes 2 query tiles of 128 tokens\n TILE_Q = 128\n NUM_TILES = 2\n\n # Phase A: tile_0 does MMA(Q0, K), tile_1 does softmax rescale\n # Phase B: tile_1 does MMA(Q1, K), tile_0 does softmax rescale\n\n for kv_block in range(num_kv_blocks):\n # Ping: MMA on tile 0, softmax on tile 1\n with warpgroup(mma_wg):\n S0 = cute.mma(Q_tile[0], K_block) # tcgen05.mma -> TMEM\n with warpgroup(softmax_wg):\n O_tile[1], L_tile[1] = rescale_and_accumulate(\n O_tile[1], L_tile[1], S1, V_prev\n )\n\n # Pong: MMA on tile 1, softmax on tile 0\n with warpgroup(mma_wg):\n S1 = cute.mma(Q_tile[1], K_block)\n with warpgroup(softmax_wg):\n O_tile[0], L_tile[0] = rescale_and_accumulate(\n O_tile[0], L_tile[0], S0, V_block\n )\n```"}, "after": {"statement": "The forward kernel assigns two output tiles of 128 query rows to one CTA. One MMA warp issues the matrix products, two four-warp softmax groups serve the two output tiles, and a correction warpgroup handles accumulator corrections. The score and output accumulators live in disjoint TMEM regions. Pipeline barriers allow softmax work for one output tile to overlap MMA work that advances the other tile.\n\nThis is more than ordinary K/V double buffering: the two alternating objects are output tiles with separate softmax state. The exact synchronization and stage ownership are implementation details; the invented one-loop pseudocode formerly on this page did not preserve those dependencies."}, "reason": {"statement": "The paper's verified schedule can be stated precisely without publishing misleading pseudo-code.", "urls": ["https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "The SFU `ex2` instruction is the bottleneck on Blackwell -- its throughput does not scale with the doubled tensor core rate. FA4 replaces it with a software exponential distributed across FMA units using Cody-Waite range reduction and Horner polynomial evaluation."}, "after": {"statement": "FA4 does not replace every hardware exponential. The paper selects only about 10-25% of entries for software evaluation on FMA units and leaves the rest on the hardware MUFU `ex2` path, allowing both resources to contribute.\n\nFor a software-selected value, the published range reduction writes `x = n + f` with `n = floor(x)` and `f` in `[0, 1)`, evaluates a degree-3 polynomial for `2**f`, and reconstructs the scale from `n`. The function below is a scalar reference using the rounded coefficients printed in the first-party blog. It illustrates that formula; it is not the CuTe kernel's vector selection, clamping, or scheduling code.\n\n```python\nimport math\n\ndef fa4_blog_exp2_reference(x: float) -> float:\n n = math.floor(x)\n f = x - n\n polynomial = 1.0 + f * (0.6951 + f * (0.2276 + f * 0.0771))\n return math.ldexp(polynomial, n)\n```\n\nNo standalone four-times software-versus-hardware exponential result is asserted here. The paper evaluates the combined kernel and its ablations rather than establishing that former page claim."}, "reason": {"statement": "Preserve the optimization while restoring its hybrid scope.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "```python\n# Software exp2 via Cody-Waite range reduction + Horner polynomial\n# Distributes across FMA units instead of using scarce SFU hardware\n\ndef software_exp2(x):\n \"\"\"\n Compute 2^x using FMA units instead of SFU ex2.\n Cody-Waite range reduction splits x into integer + fraction.\n Horner polynomial approximates 2^frac.\n \"\"\"\n # Range reduction: x = n + f, where n is integer, f in [-0.5, 0.5]\n n = round(x)\n f = x - n # Cody-Waite: use extended precision subtraction\n\n # Horner polynomial for 2^f on [-0.5, 0.5]\n # Coefficients chosen for bf16 precision target\n p = f * (C5 + f * (C4 + f * (C3 + f * (C2 + f * C1))))\n p = 1.0 + p\n\n # Reconstruct: 2^x = 2^n * 2^f\n return ldexp(p, n) # Integer exponent via bit manipulation\n```"}, "after": {"statement": "FA4 does not replace every hardware exponential. The paper selects only about 10-25% of entries for software evaluation on FMA units and leaves the rest on the hardware MUFU `ex2` path, allowing both resources to contribute.\n\nFor a software-selected value, the published range reduction writes `x = n + f` with `n = floor(x)` and `f` in `[0, 1)`, evaluates a degree-3 polynomial for `2**f`, and reconstructs the scale from `n`. The function below is a scalar reference using the rounded coefficients printed in the first-party blog. It illustrates that formula; it is not the CuTe kernel's vector selection, clamping, or scheduling code.\n\n```python\nimport math\n\ndef fa4_blog_exp2_reference(x: float) -> float:\n n = math.floor(x)\n f = x - n\n polynomial = 1.0 + f * (0.6951 + f * (0.2276 + f * 0.0771))\n return math.ldexp(polynomial, n)\n```\n\nNo standalone four-times software-versus-hardware exponential result is asserted here. The paper evaluates the combined kernel and its ablations rather than establishing that former page claim."}, "reason": {"statement": "Replace it with a clearly labeled scalar reference for the published degree-3 range reduction.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "This gives roughly 4x throughput improvement over the hardware SFU path by utilizing FMA units that would otherwise be idle during softmax phases."}, "after": {"statement": "FA4 does not replace every hardware exponential. The paper selects only about 10-25% of entries for software evaluation on FMA units and leaves the rest on the hardware MUFU `ex2` path, allowing both resources to contribute.\n\nFor a software-selected value, the published range reduction writes `x = n + f` with `n = floor(x)` and `f` in `[0, 1)`, evaluates a degree-3 polynomial for `2**f`, and reconstructs the scale from `n`. The function below is a scalar reference using the rounded coefficients printed in the first-party blog. It illustrates that formula; it is not the CuTe kernel's vector selection, clamping, or scheduling code.\n\n```python\nimport math\n\ndef fa4_blog_exp2_reference(x: float) -> float:\n n = math.floor(x)\n f = x - n\n polynomial = 1.0 + f * (0.6951 + f * (0.2276 + f * 0.0771))\n return math.ldexp(polynomial, n)\n```\n\nNo standalone four-times software-versus-hardware exponential result is asserted here. The paper evaluates the combined kernel and its ablations rather than establishing that former page claim."}, "reason": {"statement": "No adequate oracle supports the numeric factor.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "```python\n# Only rescale when max changes substantially\ndef conditional_rescale(O_acc, lse_old, lse_new, threshold=2.0):\n diff = lse_new - lse_old\n if abs(diff) > threshold:\n # Full rescale: O_acc *= exp(lse_old - lse_new)\n scale = software_exp2((lse_old - lse_new) * LOG2E)\n O_acc = O_acc * scale\n # Otherwise: skip rescale, accumulate normally\n return O_acc\n```"}, "after": {"statement": "Ordinary online softmax updates the row maximum and rescales accumulated state as each score block arrives. FA4 permits its retained maximum to lag: it resynchronizes only when the new block maximum exceeds the retained maximum by more than a threshold. The paper's typical threshold is `tau = log2(256) = 8.0` in the exponent's base-2 units.\n\nWhen a rescale is skipped, subsequent probabilities are still evaluated relative to the retained old maximum, and auxiliary statistics track the delayed normalization. The algorithm performs final renormalization at the end. Comparing absolute changes in LSE, changing the maximum anyway, or simply skipping the accumulator multiply is not equivalent."}, "reason": {"statement": "Use the verified invariant rather than repair a misleading miniature implementation.", "urls": ["https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "The backward pass spans two paired CTAs in a cluster, sharing TMEM across both SMs. This halves shared memory traffic for the dQ/dK/dV gradient computation."}, "after": {"statement": "The paper maps five backward GEMMs to two-CTA tcgen05 MMA with `M=256, N=128, K=128`. For those operations, the paired CTAs can share operand B, which the authors describe as roughly halving the shared-memory reads for that operand. This is not a claim that all shared-memory traffic for dQ, dK, and dV is halved.\n\nFor dQ, each CTA computes a half of dS and exchanges that half through distributed shared memory so both CTAs can form the required dQ product. The two-CTA organization also doubles the dQ reduction tile along N and thereby halves the number of global atomic reductions described by the paper. It does not assign dK exclusively to CTA 0 and dV exclusively to CTA 1."}, "reason": {"statement": "Retain the two-CTA optimization with the source's exact traffic scope.", "urls": ["https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "```python\n# 2-CTA backward: paired CTAs share TMEM via 2-SM cooperative mode\n@cute.kernel\ndef flash_attention_4_bwd(Q, K, V, O, dO, dQ, dK, dV):\n # Two CTAs cooperate: CTA_0 and CTA_1 in same cluster\n # tcgen05.mma shape: m256 x n256 x k16 (2-SM cooperative)\n\n cta_id = cute.cluster_rank() # 0 or 1\n\n for q_block in range(num_q_blocks):\n # Both CTAs load shared KV block via TMA\n K_smem = tma_load(K, kv_offset)\n V_smem = tma_load(V, kv_offset)\n\n # CTA_0: compute dK contribution\n # CTA_1: compute dV contribution\n if cta_id == 0:\n # dK += dS^T @ Q (accumulated in TMEM)\n dS = compute_dS(O, dO, S)\n cute.mma(dS.T, Q_tile, accumulator=dK_tmem)\n else:\n # dV += S^T @ dO (accumulated in TMEM)\n cute.mma(S.T, dO_tile, accumulator=dV_tmem)\n```"}, "after": {"statement": "The paper maps five backward GEMMs to two-CTA tcgen05 MMA with `M=256, N=128, K=128`. For those operations, the paired CTAs can share operand B, which the authors describe as roughly halving the shared-memory reads for that operand. This is not a claim that all shared-memory traffic for dQ, dK, and dV is halved.\n\nFor dQ, each CTA computes a half of dS and exchanges that half through distributed shared memory so both CTAs can form the required dQ product. The two-CTA organization also doubles the dQ reduction tile along N and thereby halves the number of global atomic reductions described by the paper. It does not assign dK exclusively to CTA 0 and dV exclusively to CTA 1.\n\nAt commit `a369df7`:\n\n- [`flash_fwd_sm100.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py) builds tcgen05 operations through `make_trivial_tiled_mma`, allocates TMEM through `TmemAllocator`, and uses explicit TMEM column offsets for score and output accumulators.\n- The forward path constructs TMA atoms for Q, K, and V where its configuration enables them. It also has non-TMA Q and paged-K/V copy paths, so TMA use is not unconditional.\n- [`flash_bwd_sm100.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_bwd_sm100.py) constructs the five backward MMA operations and the two-CTA exchange/reduction pipelines rather than splitting dK and dV by cluster rank.\n- The package README describes CuTe DSL attention for Hopper and Blackwell, and the tree contains SM90, SM100, and SM120 dispatch modules. The paper's FA4 result remains SM100/B200-specific; package architecture coverage should not be used to broaden that performance result.\n- The pinned [`pyproject.toml`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/pyproject.toml) requires `nvidia-cutlass-dsl==4.6.0.dev0`. That is a property of this source snapshot, not a timeless minimum.\n- Forward and backward accept FP16/BF16. An FP8 benchmark/bring-up script is present, but at this revision it explicitly expects the FA4 FP8 call to fail until support is implemented."}, "reason": {"statement": "Replace fabricated executable code with the paper's verified data-sharing description and pinned upstream links.", "urls": ["https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "performance_claims:\n- gpu: B200\n dtype: bf16\n shape: seqlen=8192, headdim=128\n metric: TFLOPS\n value: 1605\n utilization: 71%\n source_id: doc-flash-attention-4\n\n| seqlen=8192, headdim=128 | B200 | BF16 | 1605 | 71% | 1.1-1.3x | 2.1-2.7x |"}, "after": {"statement": "performance_claims: []\n\nThe first-party sources contain two different source-reported peak values. Paper v1 reports **up to 1613 TFLOPS/s on B200 BF16, or 71% of the peak convention used by the authors**. Tri Dao's blog reports **up to 1605 TFLOPS/s, also labeled 71%**, plus up to 1.3x over cuDNN 9.13 and up to 2.7x over Triton.\n\nThe paper's benchmark suite spans sequence lengths from 1K through 32K and multiple query/value head-dimension pairs under a fixed total-token convention. Neither textual source establishes the former single row that attached 1605 TFLOPS, 71%, and both speedup ranges specifically to `seqlen=8192, headdim=128`. The structured performance record is therefore empty, and no complement-of-71% time breakdown is inferred."}, "reason": {"statement": "Remove the false structured record and preserve both source-reported maxima with their distinct provenance and suite scope.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "The 71% MMA utilization represents the state of the art for attention kernels on Blackwell. The remaining 29% is consumed by softmax, rescaling, and memory transfers."}, "after": {"statement": "The first-party sources contain two different source-reported peak values. Paper v1 reports **up to 1613 TFLOPS/s on B200 BF16, or 71% of the peak convention used by the authors**. Tri Dao's blog reports **up to 1605 TFLOPS/s, also labeled 71%**, plus up to 1.3x over cuDNN 9.13 and up to 2.7x over Triton.\n\nThe paper's benchmark suite spans sequence lengths from 1K through 32K and multiple query/value head-dimension pairs under a fixed total-token convention. Neither textual source establishes the former single row that attached 1605 TFLOPS, 71%, and both speedup ranges specifically to `seqlen=8192, headdim=128`. The structured performance record is therefore empty, and no complement-of-71% time breakdown is inferred."}, "reason": {"statement": "No source or experiment supports the attribution.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "- Uses `SM100_MMA_SS` atoms for tcgen05 MMA from shared memory\n- TMEM locality via `TMEM` locale in CuTe layout\n- TMA bulk loads for Q, K, V tiles into shared memory"}, "after": {"statement": "At commit `a369df7`:\n\n- [`flash_fwd_sm100.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py) builds tcgen05 operations through `make_trivial_tiled_mma`, allocates TMEM through `TmemAllocator`, and uses explicit TMEM column offsets for score and output accumulators.\n- The forward path constructs TMA atoms for Q, K, and V where its configuration enables them. It also has non-TMA Q and paged-K/V copy paths, so TMA use is not unconditional.\n- [`flash_bwd_sm100.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_bwd_sm100.py) constructs the five backward MMA operations and the two-CTA exchange/reduction pipelines rather than splitting dK and dV by cluster rank.\n- The package README describes CuTe DSL attention for Hopper and Blackwell, and the tree contains SM90, SM100, and SM120 dispatch modules. The paper's FA4 result remains SM100/B200-specific; package architecture coverage should not be used to broaden that performance result.\n- The pinned [`pyproject.toml`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/pyproject.toml) requires `nvidia-cutlass-dsl==4.6.0.dev0`. That is a property of this source snapshot, not a timeless minimum.\n- Forward and backward accept FP16/BF16. An FP8 benchmark/bring-up script is present, but at this revision it explicitly expects the FA4 FP8 call to fail until support is implemented."}, "reason": {"statement": "Name the pinned source's actual abstractions and conditional copy behavior.", "urls": []}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "- Standard multi-head attention on Blackwell with sequence lengths >= 1024"}, "after": {"statement": "- Choose the package path only for a supported architecture, dtype, head-dimension pair, masking mode, and feature set at the exact revision in use.\n- Do not treat sequence length 1024 or head dimension 128 as universal crossover or optimum values. Compare against the relevant cuDNN, framework, or other kernel path on the actual workload.\n- Compilation speed and runtime speed are separate measurements. The paper's compile comparison does not prove an equivalent runtime factor.\n- Treat source-reported B200 numbers as unreproduced unless the same software, clock/power settings, tensor shapes, timing region, warmup, and FLOP convention are available."}, "reason": {"statement": "Replace the invented cutoff with workload- and support-dependent selection guidance.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/interface.py"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "- SM100 only -- no fallback to SM90\n- Requires CuTe DSL toolchain (CUTLASS 4.5.0 + Python frontend)\n- Ping-pong scheduling most effective for headdim=128; smaller headdims may not fully overlap"}, "after": {"statement": "At commit `a369df7`:\n\n- [`flash_fwd_sm100.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py) builds tcgen05 operations through `make_trivial_tiled_mma`, allocates TMEM through `TmemAllocator`, and uses explicit TMEM column offsets for score and output accumulators.\n- The forward path constructs TMA atoms for Q, K, and V where its configuration enables them. It also has non-TMA Q and paged-K/V copy paths, so TMA use is not unconditional.\n- [`flash_bwd_sm100.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_bwd_sm100.py) constructs the five backward MMA operations and the two-CTA exchange/reduction pipelines rather than splitting dK and dV by cluster rank.\n- The package README describes CuTe DSL attention for Hopper and Blackwell, and the tree contains SM90, SM100, and SM120 dispatch modules. The paper's FA4 result remains SM100/B200-specific; package architecture coverage should not be used to broaden that performance result.\n- The pinned [`pyproject.toml`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/pyproject.toml) requires `nvidia-cutlass-dsl==4.6.0.dev0`. That is a property of this source snapshot, not a timeless minimum.\n- Forward and backward accept FP16/BF16. An FP8 benchmark/bring-up script is present, but at this revision it explicitly expects the FA4 FP8 call to fail until support is implemented.\n\n- Choose the package path only for a supported architecture, dtype, head-dimension pair, masking mode, and feature set at the exact revision in use.\n- Do not treat sequence length 1024 or head dimension 128 as universal crossover or optimum values. Compare against the relevant cuDNN, framework, or other kernel path on the actual workload.\n- Compilation speed and runtime speed are separate measurements. The paper's compile comparison does not prove an equivalent runtime factor.\n- Treat source-reported B200 numbers as unreproduced unless the same software, clock/power settings, tensor shapes, timing region, warmup, and FLOP convention are available."}, "reason": {"statement": "Separate paper scope from the pinned package snapshot and avoid universal tuning advice.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/interface.py"]}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "Local verbatim upstream code lives in [`artifacts/kernels/flash-attention-4/full/`](../../artifacts/kernels/flash-attention-4/full/) (see its `PROVENANCE.yaml` for the pinned upstream SHA and byte-verified SHA-256). Labeled derived variants — including a naive/teaching skeleton — live in [`artifacts/kernels/flash-attention-4/variants/`](../../artifacts/kernels/flash-attention-4/variants/)."}, "after": {"statement": "- [FlashAttention-4 paper, arXiv v1](https://arxiv.org/abs/2603.05451v1)\n- [Tri Dao's FlashAttention-4 blog](https://tridao.me/blog/2026/flash4/)\n- [FA4 CuTe DSL package at commit `a369df7`](https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute)\n- [Pinned SM100 forward source](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py)\n- [Pinned SM100 backward source](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_bwd_sm100.py)\n\nThe local [`full/`](../../artifacts/kernels/flash-attention-4/full/) bundle is a byte-verified, verbatim **adjacent NVIDIA CUTLASS SM100 FMHA backward MLA example**, pinned to CUTLASS commit `0e026982`. It is not the Dao-AILab FA4 implementation. The local [`variants/`](../../artifacts/kernels/flash-attention-4/variants/) bundle contains explicitly derived teaching material, including the scalar software-exp formula; it is not upstream code. Exact FA4 implementation evidence is linked to the immutable Dao-AILab commit above.\n\nQuery the page and its attached local references with:\n\n```bash\npython3 scripts/get_page.py kernel-flash-attention-4 --include-code\n```"}, "reason": {"statement": "Retain the useful adjacent reference but label its identity; point implementation claims to exact Dao-AILab commit URLs.", "urls": []}} +{"path": "wiki/kernels/flash-attention-4.md", "before": {"statement": "sources:\n- doc-flash-attention-4\n- blog-flash-attention-4\n- pr-flashinfer-1850"}, "after": {"statement": "sources:\n- doc-flash-attention-4\n- blog-flash-attention-4"}, "reason": {"statement": "Keep the FA4 source relationship limited to its first-party paper and blog; adjacent CUTLASS code remains explicitly labeled in the artifact discussion.", "urls": ["https://github.com/flashinfer-ai/flashinfer/pull/1850"]}} +{"path": "wiki/kernels/flash-attention-sm100-mla-topk.md", "before": {"statement": "FlashAttention PR 2441 adds an SM100 CuTe DSL forward path for MLA shapes with\ntop-k sparsity. It is useful when an attention candidate has to combine page/KV\nlayout handling, sparse top-k selection, and tiled forward scheduling."}, "after": {"statement": "[Dao-AILab/flash-attention PR 2441](https://github.com/Dao-AILab/flash-attention/pull/2441), merged as [`f219c89c886c6ccbf9d3dbd9fe41b11ac64e9df8`](https://github.com/Dao-AILab/flash-attention/commit/f219c89c886c6ccbf9d3dbd9fe41b11ac64e9df8), adds an SM100 CuTe DSL forward path for the DeepSeek-style MLA dimensions `head_dim=64` and `head_dim_v=512`, with MQA packing of 128 query heads per KV head and caller-supplied top-k indices.\n\nThe top-k path is deliberately narrower than a generic paged sparse-attention API. It requires packed GQA/MQA, `qhead_per_kvhead == 128`, and the cp.async K/V gather path. Its constructor defaults to top-k length 2048 and requires the configured length to be divisible by 256. The merged kernel rejects a non-null page table with `page table tbd for MLA`; page-table support was explicitly outside this PR.\n\nThe pinned merge keeps three responsibilities distinguishable:\n\n- [`topk_gather_kv.py`](../../artifacts/prs/flash-attention/PR-2441/key-files/flash_attn/cute/topk_gather_kv.py) loads caller-provided top-k indices, forms indexed K/V addresses, issues cp.async copies, and optionally constructs validity bitmasks for out-of-range indices.\n- [`tile_scheduler.py`](../../artifacts/prs/flash-attention/PR-2441/key-files/flash_attn/cute/tile_scheduler.py) supplies the tile-scheduler implementations selected by the MLA kernel.\n- [`flash_fwd_mla_sm100.py`](../../artifacts/prs/flash-attention/PR-2441/key-files/flash_attn/cute/flash_fwd_mla_sm100.py) integrates gather, scheduling, two-CTA tcgen05 MMA, TMEM accumulators, softmax, and the output path.\n\nThis separation matters for evaluation. Arithmetic work follows the effective top-k length, whereas memory addresses follow the caller's index set and use an indexed gather/optional-bitmask path. Reduced attention FLOPs therefore do not prove a proportional latency or locality improvement."}, "reason": {"statement": "Retain the implemented top-k/scheduler path and state page-table exclusion precisely.", "urls": []}} +{"path": "wiki/kernels/flash-attention-sm100-mla-topk.md", "before": {"statement": "performance_claims:\n- gpu: B200\n dtype: bf16\n shape: batch=512, seqlen_q=1, seqlen_k=16384, nheads=128, topk=2048\n metric: latency_ms\n value: 0.3\n source_id: pr-flash-attention-2441"}, "after": {"statement": "performance_claims: []\n\nThe PR author reports an initial saturating-decode comparison for batch 512, `seqlen_q=1`, `seqlen_k=16384`, 128 query heads, the 64/512 MLA shape, and top-k length 2048:\n\n| DSA, no bitmask; indices assumed in bounds | 0.31 ms | 955.47 TFLOPS |\n| DSA, validity bitmask | 0.33 ms | 898.08 TFLOPS |\n| Vanilla MLA baseline | 1.98 ms | 1180.70 TFLOPS |\n\nThese PR-description observations are not reproduced here. The PR body does not name the exact GPU model, dtype, clocks/power state, software environment, timing protocol, or run-to-run variation for the rows. They therefore remain prose with exact source qualifications rather than structured `performance_claims`."}, "reason": {"statement": "Remove the unsupported structured record but retain the author's two qualified, unreproduced observations in prose.", "urls": ["https://api.github.com/repos/Dao-AILab/flash-attention/pulls/2441"]}} +{"path": "wiki/kernels/flash-attention-sm100-mla-topk.md", "before": {"statement": "sources:\n- pr-flash-attention-2441\n- pr-flash-attention-1236"}, "after": {"statement": "sources:\n- pr-flash-attention-2441"}, "reason": {"statement": "Limit the source relationship to the exact introducing merge.", "urls": ["https://github.com/Dao-AILab/flash-attention/pull/1236"]}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "FlashMLA provides high-performance kernels for DeepSeek's Multi-head Latent Attention (MLA) mechanism, which compresses the KV cache from 327-516 KB/token (standard MHA) down to 70 KB/token through a learned low-rank projection into a latent space. This extreme compression (4.66-7.28x reduction) is critical for serving DeepSeek-V3/V3.2 models at scale."}, "after": {"statement": "FlashMLA is DeepSeek's attention-kernel library for DeepSeek-V3 and DeepSeek-V3.2-Exp. At pinned commit [`71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232), the library contains MLA-mode decode and sparse-prefill operators plus a dense **MHA** prefill operator contributed for SM100. The repository's term “MLA mode” distinguishes MQA-shaped `d_qk=576, d_v=512` kernels from MHA-shaped `d_qk=192/128, d_v=128` kernels; it does not mean every operator in the package is MLA."}, "reason": {"statement": "Replace invented byte endpoints with the paper's explicit per-layer element formula and keep implementation-specific byte layout separate.", "urls": ["https://arxiv.org/html/2405.04434v5"]}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "FlashMLA includes four kernel variants: dense MLA decoding (SM90), sparse MLA decoding (SM90/SM100), dense MLA prefill (SM100), and sparse MLA prefill (SM90/SM100)."}, "after": {"statement": "The DeepSeek-V2 paper describes the model-level reduction in elements cached per layer and token:\n\n- MHA: `2 * n_h * d_h`\n- MLA: `d_c + d_h^R`, approximately `4.5 * d_h` for its `d_c=4*d_h` and `d_h^R=d_h/2` configuration\n\nThese formulas are independent of storage dtype and layer count. They should not be converted to whole-model KB/token figures without naming those additional assumptions."}, "reason": {"statement": "Preserve the four operator families while labeling dense prefill as MHA.", "urls": ["https://arxiv.org/html/2405.04434v5"]}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "Each token in the MLA KV cache occupies 656 bytes:\n\n```\nToken KV Cache Entry (656 bytes total):\n+------------------------------------------+\n| FP8 compressed KV data | 512 bytes | <-- Latent KV representation\n| FP32 scaling factors | 16 bytes | <-- Per-head scales\n| BF16 RoPE embeddings | 128 bytes | <-- Position encodings\n+------------------------------------------+\n\nPaged KV cache:\n Page size = 64 tokens (dense) or variable (sparse)\n Each page = 64 * 656 = 41,984 bytes\n```"}, "after": {"statement": "FlashMLA's **656-byte** layout is narrower: it is the DeepSeek-V3-family FP8 sparse-decode cache ABI, not the definition of an MLA cache. One token contains:\n\n| NoPE latent data | 512 `float8_e4m3` values | 512 |\n| NoPE group scales | four `float32` values, one per 128 values | 16 |\n| RoPE data | 64 unquantized `bfloat16` values | 128 |\n| **Total** | | **656** |\n\nDense decode uses a BF16 cache. The pinned quantization tests also contain a separate 512-dimensional sparse layout, so code must select the model/layout contract rather than assuming 656 bytes universally. `page_block_size` is taken from the cache tensor; 64 is a test default, not a fixed API rule."}, "reason": {"statement": "Narrow the byte layout to its exact model and dispatch mode and remove invented page-size universals.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "The decode kernel targets memory-bound inference with paged KV cache (block size 64). It achieves up to 3000 GB/s memory bandwidth and 660 TFLOPS on H800."}, "after": {"statement": "Sparse decode receives `indices[batch, s_q, topk]`. Each nonnegative value already encodes a physical page and offset:\n\n```text\nencoded = physical_page * page_block_size + offset_in_page\n```\n\nBecause the physical page is already encoded, sparse decode does not use `block_table`; `-1` marks an invalid entry. The kernel consumes these indices but does not produce the top-k selection, so an indexing stage outside the attention call must supply them.\n\nSparse prefill is a different interface. It receives BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and `indices[s_q,h_kv,topk]`; it has no batch dimension, requires `h_kv=1` in the documented equivalence, and accepts `-1` or values at least `s_kv` as invalid. It returns `(out, max_logits, lse)`."}, "reason": {"statement": "Retain the exact author report and remove the false fixed-page condition.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "```cpp\n// Dense MLA decode kernel structure (SM90, BF16)\n// Memory-bound: bandwidth utilization is the primary metric\n\ntemplate \n__global__ void flashmla_decode_dense(\n const half* __restrict__ Q, // [batch, num_heads, head_dim]\n const int8_t* __restrict__ KV, // Paged KV cache (FP8)\n const float* __restrict__ scales, // Per-head scales\n const half* __restrict__ rope, // RoPE embeddings\n const int* __restrict__ page_table,\n half* __restrict__ O,\n float* __restrict__ L // Log-sum-exp\n) {\n // Each warpgroup handles one query head\n const int head_id = blockIdx.x;\n const int batch_id = blockIdx.y;\n\n // Load query into registers\n half Q_reg[HEAD_DIM];\n load_query(Q, batch_id, head_id, Q_reg);\n\n float acc[HEAD_DIM] = {0.0f};\n float lse = -INFINITY;\n\n // Iterate over KV pages\n for (int page = 0; page < num_pages; page++) {\n int page_idx = page_table[batch_id * max_pages + page];\n\n // TMA load KV page into shared memory\n __shared__ int8_t KV_smem[BLOCK_KV * 656];\n tma_load_async(KV_smem, KV + page_idx * BLOCK_KV * 656);\n cp_async_wait();\n\n // Compute attention scores for this page\n for (int t = 0; t < BLOCK_KV; t++) {\n // Dequantize KV: fp8 -> bf16, apply scale\n half K_token[HEAD_DIM], V_token[HEAD_DIM];\n dequant_kv(KV_smem + t * 656, scales, K_token, V_token);\n\n // Apply RoPE\n apply_rope(K_token, rope + (page * BLOCK_KV + t) * 64);\n\n // Score and accumulate (online softmax)\n float score = dot_product(Q_reg, K_token, HEAD_DIM);\n float new_lse = logaddexp(lse, score);\n float rescale = exp(lse - new_lse);\n for (int d = 0; d < HEAD_DIM; d++)\n acc[d] = acc[d] * rescale + exp(score - new_lse) * V_token[d];\n lse = new_lse;\n }\n }\n\n // Write output\n store_output(O, batch_id, head_id, acc);\n L[batch_id * num_heads + head_id] = lse;\n}\n```"}, "after": {"statement": "FlashMLA's **656-byte** layout is narrower: it is the DeepSeek-V3-family FP8 sparse-decode cache ABI, not the definition of an MLA cache. One token contains:\n\n| NoPE latent data | 512 `float8_e4m3` values | 512 |\n| NoPE group scales | four `float32` values, one per 128 values | 16 |\n| RoPE data | 64 unquantized `bfloat16` values | 128 |\n| **Total** | | **656** |\n\nDense decode uses a BF16 cache. The pinned quantization tests also contain a separate 512-dimensional sparse layout, so code must select the model/layout contract rather than assuming 656 bytes universally. `page_block_size` is taken from the cache tensor; 64 is a test default, not a fixed API rule.\n\n| Dense decode | SM90 | MQA (`576/512`) | BF16 paged KV |\n| Sparse decode | SM90, SM100 | MQA (`576/512`) | FP8 KV, dequantized for BF16 MMA; BF16 output |\n| Dense prefill | SM100 | MHA (`192/128` or `128/128`) | BF16 Q/K/V |\n| Sparse prefill | SM90, SM100 | MQA | BF16 Q and KV |\n\nCUDA 12.8 or newer and PyTorch 2.0 or newer are required; the pinned README requires CUDA 12.9 or newer for SM100."}, "reason": {"statement": "Remove fabricated kernel code; point readers to pinned source-level contracts and transparently labeled adjacent artifacts.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "```cpp\n// Sparse MLA: only attend to selected tokens via indices tensor\n// Each query has a variable-length list of relevant token indices\n\ntemplate \n__global__ void flashmla_sparse(\n const half* Q,\n const int8_t* KV_cache,\n const float* scales,\n const int* token_indices, // Selected token indices per query\n const int* num_selected, // Number of selected tokens per query\n half* O\n) {\n const int query_id = blockIdx.x;\n const int n_tokens = num_selected[query_id];\n\n // Only load and compute on selected tokens\n for (int i = 0; i < n_tokens; i += BLOCK_SIZE) {\n int tok_idx = token_indices[query_id * MAX_TOKENS + i];\n\n // Load only the selected token's KV entry (656 bytes)\n load_kv_entry(KV_cache, tok_idx, K_local, V_local);\n dequant_and_accumulate(Q, K_local, V_local, scales, acc, lse);\n }\n}\n```"}, "after": {"statement": "| Dense decode | SM90 | MQA (`576/512`) | BF16 paged KV |\n| Sparse decode | SM90, SM100 | MQA (`576/512`) | FP8 KV, dequantized for BF16 MMA; BF16 output |\n| Dense prefill | SM100 | MHA (`192/128` or `128/128`) | BF16 Q/K/V |\n| Sparse prefill | SM90, SM100 | MQA | BF16 Q and KV |\n\nCUDA 12.8 or newer and PyTorch 2.0 or newer are required; the pinned README requires CUDA 12.9 or newer for SM100."}, "reason": {"statement": "Replace the fabricated code with exact interface descriptions and small, explicitly derived contract checks.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "The SM100 prefill kernel leverages tcgen05.mma and TMEM for the compute-heavy forward and backward passes, achieving 1460 TFLOPS forward and 1000 TFLOPS backward on B200.\n\n```cpp\n// SM100 dense prefill: tcgen05.mma with TMEM accumulation\n// Uses warp specialization: TMA warps + MMA warps + softmax warps\n\n// Forward pass structure:\n// 1. TMA loads Q, K, V tiles into SMEM\n// 2. tcgen05.mma computes S = Q @ K^T into TMEM\n// 3. Softmax warpgroup applies online softmax on TMEM data\n// 4. tcgen05.mma computes O = softmax(S) @ V into TMEM\n// 5. TMEM -> SMEM -> Global memory for output\n\n// Key: TMEM holds both S matrix and O accumulator\n// No register spill for large tile sizes\n```"}, "after": {"statement": "The DeepSeek-V2 paper describes the model-level reduction in elements cached per layer and token:\n\n- MHA: `2 * n_h * d_h`\n- MLA: `d_c + d_h^R`, approximately `4.5 * d_h` for its `d_c=4*d_h` and `d_h^R=d_h/2` configuration\n\nThese formulas are independent of storage dtype and layer count. They should not be converted to whole-model KB/token figures without naming those additional assumptions.\n\nThe following are maxima reported by the pinned first-party README. They were not reproduced here, and the README does not provide complete shape, timing, sample-count, or variance cells, so they are intentionally excluded from structured `performance_claims`.\n\n| Dense MLA decode | H800 SXM5, CUDA 12.8 | BF16 cache | Up to 3000 GB/s in a memory-bound configuration; up to 660 TFLOPS in a compute-bound configuration |\n| Sparse MLA decode | H800 SXM5, CUDA 12.8 | FP8 KV, BF16 MMA | 410 TFLOPS in a compute-bound configuration |\n| Sparse MLA decode | B200; software version not stated in the row | FP8 KV, BF16 MMA | Up to 350 TFLOPS; the author says it was not well optimized |\n| Dense MHA prefill | B200; NVIDIA-reported | BF16 inputs | Up to 1460 TFLOPS forward and 1000 TFLOPS backward |\n| Sparse MLA prefill | H800 SXM5, CUDA 12.8 | BF16 inputs | Up to 640 TFLOPS forward |\n| Sparse MLA prefill | B200, CUDA 12.9 | BF16 inputs | Up to 1450 TFLOPS forward |\n\nThe numbers compare different operators, phases, shapes, precision scopes, and machines. In particular, `1460` is dense MHA prefill, not a replacement for the `660` dense-MLA-decode observation."}, "reason": {"statement": "Relabel the operator and separate verified architectural mechanisms from unsupported pseudocode.", "urls": ["https://arxiv.org/html/2405.04434v5"]}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "| Sparse decode | H800 | FP8 | 410 | -- |\n| Sparse decode | B200 | FP8 | 350 | -- |"}, "after": {"statement": "Sparse decode receives `indices[batch, s_q, topk]`. Each nonnegative value already encodes a physical page and offset:\n\n```text\nencoded = physical_page * page_block_size + offset_in_page\n```\n\nBecause the physical page is already encoded, sparse decode does not use `block_table`; `-1` marks an invalid entry. The kernel consumes these indices but does not produce the top-k selection, so an indexing stage outside the attention call must supply them.\n\nSparse prefill is a different interface. It receives BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and `indices[s_q,h_kv,topk]`; it has no batch dimension, requires `h_kv=1` in the documented equivalence, and accepts `-1` or values at least `s_kv` as invalid. It returns `(out, max_logits, lse)`."}, "reason": {"statement": "Split cache storage from compute precision in the performance table.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "| Sparse prefill | H800 | FP8 | 640 | -- |\n| Sparse prefill | B200 | FP8 | 1450 | -- |"}, "after": {"statement": "Sparse decode receives `indices[batch, s_q, topk]`. Each nonnegative value already encodes a physical page and offset:\n\n```text\nencoded = physical_page * page_block_size + offset_in_page\n```\n\nBecause the physical page is already encoded, sparse decode does not use `block_table`; `-1` marks an invalid entry. The kernel consumes these indices but does not produce the top-k selection, so an indexing stage outside the attention call must supply them.\n\nSparse prefill is a different interface. It receives BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and `indices[s_q,h_kv,topk]`; it has no batch dimension, requires `h_kv=1` in the documented equivalence, and accepts `-1` or values at least `s_kv` as invalid. It returns `(out, max_logits, lse)`."}, "reason": {"statement": "Use the documented BF16 input dtype and preserve exact author-reported values/environments.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "- SGLang and vLLM provide day-0 support"}, "after": {"statement": "The following are maxima reported by the pinned first-party README. They were not reproduced here, and the README does not provide complete shape, timing, sample-count, or variance cells, so they are intentionally excluded from structured `performance_claims`.\n\n| Dense MLA decode | H800 SXM5, CUDA 12.8 | BF16 cache | Up to 3000 GB/s in a memory-bound configuration; up to 660 TFLOPS in a compute-bound configuration |\n| Sparse MLA decode | H800 SXM5, CUDA 12.8 | FP8 KV, BF16 MMA | 410 TFLOPS in a compute-bound configuration |\n| Sparse MLA decode | B200; software version not stated in the row | FP8 KV, BF16 MMA | Up to 350 TFLOPS; the author says it was not well optimized |\n| Dense MHA prefill | B200; NVIDIA-reported | BF16 inputs | Up to 1460 TFLOPS forward and 1000 TFLOPS backward |\n| Sparse MLA prefill | H800 SXM5, CUDA 12.8 | BF16 inputs | Up to 640 TFLOPS forward |\n| Sparse MLA prefill | B200, CUDA 12.9 | BF16 inputs | Up to 1450 TFLOPS forward |\n\nThe numbers compare different operators, phases, shapes, precision scopes, and machines. In particular, `1460` is dense MHA prefill, not a replacement for the `660` dense-MLA-decode observation."}, "reason": {"statement": "Remove the unversioned ecosystem claim rather than substituting inference for evidence.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "- MLA-specific: the latent KV cache format (656 bytes/token) is tied to DeepSeek's architecture"}, "after": {"statement": "FlashMLA's **656-byte** layout is narrower: it is the DeepSeek-V3-family FP8 sparse-decode cache ABI, not the definition of an MLA cache. One token contains:\n\n| NoPE latent data | 512 `float8_e4m3` values | 512 |\n| NoPE group scales | four `float32` values, one per 128 values | 16 |\n| RoPE data | 64 unquantized `bfloat16` values | 128 |\n| **Total** | | **656** |\n\nDense decode uses a BF16 cache. The pinned quantization tests also contain a separate 512-dimensional sparse layout, so code must select the model/layout contract rather than assuming 656 bytes universally. `page_block_size` is taken from the cache tensor; 64 is a test default, not a fixed API rule.\n\n- [DeepSeek FlashMLA at audited commit `71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232)\n- [DeepSeek-V2 MLA paper, v5](https://arxiv.org/html/2405.04434v5)\n- [CUTLASS PR 2466, SM100 MLA-shape backward](https://github.com/NVIDIA/cutlass/pull/2466)\n- [CUTLASS PR 2472, SM100 MLA-shape forward](https://github.com/NVIDIA/cutlass/pull/2472)"}, "reason": {"statement": "State the precise V3-family FP8+sparse scope.", "urls": ["https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232", "https://arxiv.org/html/2405.04434v5", "https://github.com/NVIDIA/cutlass/pull/2466", "https://github.com/NVIDIA/cutlass/pull/2472"]}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "Verbatim upstream code lives in [`artifacts/kernels/flashmla/full/`](../../artifacts/kernels/flashmla/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live in [`artifacts/kernels/flashmla/variants/`](../../artifacts/kernels/flashmla/variants/). Every file's SHA-256 and upstream-pinning metadata is in `PROVENANCE.yaml` inside each bundle."}, "after": {"statement": "The pinned DeepSeek SM100 sources use TMA, `tcgen05` tensor-core operations, and TMEM in specialized sparse-decode/prefill and dense-MHA-prefill code. Those mechanisms are implementation-specific: they do not make the CUTLASS and FlashInfer files in this repository copies of DeepSeek FlashMLA.\n\nThe local [`full/`](../../artifacts/kernels/flashmla/full/) bundle contains two byte-verified **adjacent implementations**:\n\n- NVIDIA CUTLASS Example 77 MLA forward at merge `9baa06dd`\n- FlashInfer's SM100 FMHA-MLA header at commit `9a05c92a`\n\nTheir exact per-file origins are recorded in `full/PROVENANCE.yaml`. The [`variants/`](../../artifacts/kernels/flashmla/variants/) directory contains a small KernelWiki-derived layout/index helper, explicitly marked as non-upstream. For the DeepSeek implementation itself, use commit `71c7379` linked above."}, "reason": {"statement": "Retain useful artifacts with explicit adjacent-implementation labels and replace the variant with a narrow verified contract helper.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "performance_claims:\n- gpu: B200\n dtype: bf16\n shape: dense prefill, variable seqlen\n metric: TFLOPS\n value: 1460\n utilization: ~65%\n source_id: blog-flashmla\n- gpu: B200\n dtype: fp8\n shape: sparse prefill\n metric: TFLOPS\n value: 1450\n utilization: ~65%\n source_id: blog-flashmla"}, "after": {"statement": "performance_claims: []\n\nSparse decode receives `indices[batch, s_q, topk]`. Each nonnegative value already encodes a physical page and offset:\n\n```text\nencoded = physical_page * page_block_size + offset_in_page\n```\n\nBecause the physical page is already encoded, sparse decode does not use `block_table`; `-1` marks an invalid entry. The kernel consumes these indices but does not produce the top-k selection, so an indexing stage outside the attention call must supply them.\n\nSparse prefill is a different interface. It receives BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and `indices[s_q,h_kv,topk]`; it has no batch dimension, requires `h_kv=1` in the documented equivalence, and accepts `-1` or values at least `s_kv` as invalid. It returns `(out, max_logits, lse)`."}, "reason": {"statement": "Remove inadmissible structured records while retaining qualified author reports in prose.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "sources:\n- blog-flashmla\n- pr-flashinfer-1117\n- pr-vllm-39752"}, "after": {"statement": "sources:\n- blog-flashmla\n- doc-deepseek-v2-mla\n- pr-cutlass-2466\n- pr-cutlass-2472"}, "reason": {"statement": "Remove the unrelated relationship; retain only explicitly labeled adjacent implementations where discussed.", "urls": []}} +{"path": "wiki/kernels/flashmla.md", "before": {"statement": "sources:\n- blog-flashmla\n- pr-flashinfer-1117\n- pr-vllm-39752"}, "after": {"statement": "sources:\n- blog-flashmla\n- doc-deepseek-v2-mla\n- pr-cutlass-2466\n- pr-cutlass-2472"}, "reason": {"statement": "Keep source relationships claim-directed and version-pinned to the implementation actually discussed.", "urls": []}} +{"path": "wiki/kernels/fp8-block-scale-gemm.md", "before": {"statement": "```\nActivations: tile-wise 1x128 scales\n [1x128 values] → 1 scale factor (FP32 or FP8 E4M3)\n\nWeights: block-wise 128x128 scales\n [128x128 values] → 1 scale factor per block\n\nOutput accumulator: FP32\n Multiply A × B in FP8, accumulate in FP32, apply scales at MMA boundary\n```"}, "after": {"statement": "For `A[M,K] @ B[N,K].T` with the DeepSeek-V3 forward recipe, the logical scale arrays have shapes `A_sf[M,K/128]` and `B_sf[N/128,K/128]`. This small check documents only that grouping; it does not encode DeepGEMM's required TMA-transformed layouts.\n\n```python\n# KernelWiki-derived format check; not upstream DeepGEMM code.\ndef deepseek_v3_scale_shapes(m: int, n: int, k: int):\n assert m % 128 == 0 and n % 128 == 0 and k % 128 == 0\n activation_scales = (m, k // 128)\n weight_scales = (n // 128, k // 128)\n return activation_scales, weight_scales\n\nassert deepseek_v3_scale_shapes(4096, 4096, 4096) == ((4096, 32), (32, 32))\n```\n\nThe pinned SM90 1D1D kernel requires FP32 scale factors and fixes `BLOCK_K == 128`. Within each K block it issues the selected WGMMA operations into a register `accum` array; after the WGMMA batch completes, it multiplies those partials by the corresponding A/B scales and adds them into a separate FP32 `final_accum` array on CUDA cores.\n\nFor the DeepSeek-V3 description, a 128-element K interval corresponds to four WGMMAs. The paper describes Hopper's relevant internal addition/alignment precision as 14 bits, not as a generic “FP22 accumulator.” Promotion improves numerical behavior but still adds scale loads and CUDA-core work, so its overhead must be measured rather than assumed away."}, "reason": {"statement": "Split the Hopper and Blackwell scale ABIs and accumulation locations.", "urls": []}} +{"path": "wiki/kernels/fp8-block-scale-gemm.md", "before": {"statement": "```cuda\n// Hopper accumulator has ~22-bit precision (FP22)\n// Every Nc=128 WGMMAs, promote partial sum to FP32 on CUDA cores\n// This retains precision without adding MMA overhead\n\n__device__ void sm90_fp8_gemm_with_promotion(...) {\n float acc_fp32 = 0.0f;\n\n for (int k = 0; k < K; k += 128) {\n float acc_fp22 = 0.0f;\n #pragma unroll 4\n for (int kk = 0; kk < 128; kk += 32) {\n wgmma_fp8_e4m3(acc_fp22, A_frag, B_frag);\n }\n // Promote to FP32 accumulator on CUDA cores\n acc_fp32 += acc_fp22 * scale_a * scale_b;\n }\n\n // Write acc_fp32 to output\n}\n```"}, "after": {"statement": "For `A[M,K] @ B[N,K].T` with the DeepSeek-V3 forward recipe, the logical scale arrays have shapes `A_sf[M,K/128]` and `B_sf[N/128,K/128]`. This small check documents only that grouping; it does not encode DeepGEMM's required TMA-transformed layouts.\n\n```python\n# KernelWiki-derived format check; not upstream DeepGEMM code.\ndef deepseek_v3_scale_shapes(m: int, n: int, k: int):\n assert m % 128 == 0 and n % 128 == 0 and k % 128 == 0\n activation_scales = (m, k // 128)\n weight_scales = (n // 128, k // 128)\n return activation_scales, weight_scales\n\nassert deepseek_v3_scale_shapes(4096, 4096, 4096) == ((4096, 32), (32, 32))\n```"}, "reason": {"statement": "Replace fabricated code with a narrow source-adapted promotion skeleton and exact interval qualification.", "urls": ["https://arxiv.org/html/2412.19437v2", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d1d.cuh"]}} +{"path": "wiki/kernels/fp8-block-scale-gemm.md", "before": {"statement": "```cuda\n// tcgen05.mma has native UE8M0 block scale support in hardware\n// No promotion needed - scales applied inside MMA\n\n__global__ void sm100_fp8_gemm_block_scale(...) {\n uint32_t tmem = tmem_alloc(256);\n\n for (int k = 0; k < K; k += BLOCK_K) {\n mbarrier_wait(&tma_done);\n\n // tcgen05.mma.mxf8f6f4.block_scale variant\n // Reads A, B from SMEM; scales from scale SMEM; accumulates in TMEM\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X \"\n \"[%0], %1, %2, %3, %4, %5;\"\n :: \"r\"(tmem), \"l\"(a_desc), \"l\"(b_desc),\n \"r\"(sf_a_desc), \"r\"(sf_b_desc), \"n\"(1)\n );\n }\n\n // Read from TMEM, apply global scale, store\n float result = tmem_load(tmem) * global_scale;\n output[row * N + col] = __float2half(result);\n}\n```"}, "after": {"statement": "The pinned SM90 1D1D kernel requires FP32 scale factors and fixes `BLOCK_K == 128`. Within each K block it issues the selected WGMMA operations into a register `accum` array; after the WGMMA batch completes, it multiplies those partials by the corresponding A/B scales and adds them into a separate FP32 `final_accum` array on CUDA cores.\n\nFor the DeepSeek-V3 description, a 128-element K interval corresponds to four WGMMAs. The paper describes Hopper's relevant internal addition/alignment precision as 14 bits, not as a generic “FP22 accumulator.” Promotion improves numerical behavior but still adds scale loads and CUDA-core work, so its overhead must be measured rather than assumed away."}, "reason": {"statement": "Remove invalid inline PTX and explain the verified source-level path in prose.", "urls": []}} +{"path": "wiki/kernels/fp8-block-scale-gemm.md", "before": {"statement": "```\nA (activations) [M, K] packed FP8 E4M3\nsf_a [M, K/128] FP32 or FP8 E4M3 scales # 1 per 1x128 tile\n\nB (weights) [N, K] packed FP8 E4M3\nsf_b [N/128, K/128] scales # 1 per 128x128 block\n # or packed UE8M0 format (Blackwell): 4 scales per int32\n```"}, "after": {"statement": "DeepGEMM commit [`891d57b4`](https://github.com/deepseek-ai/DeepGEMM/tree/891d57b4db1071624b5c8fa0d1e51cb317fa709f) implements related FP8 GEMMs on SM90 and SM100, but the two generations handle scale factors differently.\n\nThe pinned SM90 1D1D kernel requires FP32 scale factors and fixes `BLOCK_K == 128`. Within each K block it issues the selected WGMMA operations into a register `accum` array; after the WGMMA batch completes, it multiplies those partials by the corresponding A/B scales and adds them into a separate FP32 `final_accum` array on CUDA cores.\n\nFor the DeepSeek-V3 description, a 128-element K interval corresponds to four WGMMAs. The paper describes Hopper's relevant internal addition/alignment precision as 14 bits, not as a generic “FP22 accumulator.” Promotion improves numerical behavior but still adds scale loads and CUDA-core work, so its overhead must be measured rather than assumed away."}, "reason": {"statement": "Separate the model grouping from each implementation's input ABI.", "urls": []}} +{"path": "wiki/kernels/fp8-block-scale-gemm.md", "before": {"statement": "- CUTLASS SM100 schedules: similar ratio vs peak"}, "after": {"statement": "The pinned SM100 interface requires scale factors packed as four UE8M0 values per 32-bit `torch.int`. The 1D1D kernel TMA-loads scale-factor blocks, copies them into TMEM, builds a `make_instr_desc_block_scaled<..., float_ue8m0_t, ...>` descriptor, and accumulates with the selected block-scaled UMMA path in TMEM.\n\nThis is hardware-integrated scale consumption, not the SM90 `final_accum += scale_a * scale_b * accum` loop. Exact `tcgen05.mma` instruction spelling and descriptor restrictions are PTX-version-sensitive; use the pinned source wrapper or the NVIDIA PTX ISA rather than a hand-written approximate inline-assembly string.\n\nThe current DeepGEMM snapshot supports more than the original 128-granularity training recipe on SM100, including selected 32-element recipes. Treat the API's transformed/padded scale layout as authoritative for the chosen recipe."}, "reason": {"statement": "Retain CUTLASS availability without an unsupported cross-library performance comparison.", "urls": []}} +{"path": "wiki/kernels/fp8-block-scale-gemm.md", "before": {"statement": "- LLM inference with FP8 quantized weights (DeepSeek V3, Qwen2-FP8, etc.)"}, "after": {"statement": "The pinned README says DeepGEMM achieved **up to 1550 TFLOPS on H800** in its 2025-04-18 news item. That sentence does not identify a matrix shape, utilization percentage, timing protocol, sample count, variance, or a single optimization responsible for the maximum. The result was not reproduced in this audit and is therefore kept out of structured `performance_claims`.\n\nCUTLASS also ships SM100 block-scaled GEMM schedules, but no matched CUTLASS-versus-DeepGEMM shape/environment record is established here."}, "reason": {"statement": "Replace model-name generalization with an explicit contract-matching rule.", "urls": ["https://arxiv.org/html/2412.19437v2"]}} +{"path": "wiki/kernels/fp8-block-scale-gemm.md", "before": {"statement": "performance_claims:\n - gpu: H800\n dtype: fp8\n shape: \"M=4096, N=4096, K=4096\"\n metric: TFLOPS\n value: 1550\n utilization: \"~90% via CUDA core promotion\"\n source_id: blog-deepgemm"}, "after": {"statement": "performance_claims: []\n\nThe pinned SM100 interface requires scale factors packed as four UE8M0 values per 32-bit `torch.int`. The 1D1D kernel TMA-loads scale-factor blocks, copies them into TMEM, builds a `make_instr_desc_block_scaled<..., float_ue8m0_t, ...>` descriptor, and accumulates with the selected block-scaled UMMA path in TMEM.\n\nThis is hardware-integrated scale consumption, not the SM90 `final_accum += scale_a * scale_b * accum` loop. Exact `tcgen05.mma` instruction spelling and descriptor restrictions are PTX-version-sensitive; use the pinned source wrapper or the NVIDIA PTX ISA rather than a hand-written approximate inline-assembly string.\n\nThe current DeepGEMM snapshot supports more than the original 128-granularity training recipe on SM100, including selected 32-element recipes. Treat the API's transformed/padded scale layout as authoritative for the chosen recipe."}, "reason": {"statement": "Remove the inadmissible record while retaining the exact qualified author report in prose.", "urls": []}} +{"path": "wiki/kernels/fp8-block-scale-gemm.md", "before": {"statement": "sources: [blog-deepgemm, doc-cutlass-blackwell, doc-cutlass-changelog-sm100]"}, "after": {"statement": "sources: [blog-deepgemm, doc-deepseek-v3-fp8, doc-ptx-isa-sm100]"}, "reason": {"statement": "Use claim-directed, version-pinned sources.", "urls": []}} +{"path": "wiki/kernels/fp8-block-scale-gemm.md", "before": {"statement": "sources: [blog-deepgemm, doc-cutlass-blackwell, doc-cutlass-changelog-sm100]"}, "after": {"statement": "sources: [blog-deepgemm, doc-deepseek-v3-fp8, doc-ptx-isa-sm100]"}, "reason": {"statement": "Limit source relationships to the DeepSeek paper, exact DeepGEMM snapshot, and official PTX contract used by current claims.", "urls": []}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "Fused MoE kernels combine the full Mixture-of-Experts forward pass into minimal kernel launches: routing, token dispatch, gate-up dual GEMM, SwiGLU activation, down projection GEMM, and token combine. In unfused implementations this requires 5-7 separate kernel launches; fused variants reduce this to 1-3 launches, eliminating intermediate global memory roundtrips and saving up to 21.9% activation memory traffic."}, "after": {"statement": "FlashInfer's MLSys 2026 contest calls Track A **Fused MoE** with FP8 support and targets NVIDIA B200. Its exact benchmark definition is `moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048`. The definition says that DeepSeek-style routing and two grouped GEMMs are included. That operation-level scope does **not** establish that an implementation uses one GPU launch.\n\n[`01-routing-plus-fusion-skeleton.py`](../../artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py) is a CPU-checkable, parameterized reference for grouped selection and local W13/SwiGLU/W2 accumulation. It is derived KernelWiki code, not an optimized kernel and not an upstream contest solution.\n\n- [MLSys 2026 FlashInfer contest](https://mlsys26.flashinfer.ai/)\n- [Exact FP8 MoE benchmark definition](https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048)"}, "reason": {"statement": "State only the operation scope in the official contract and remove unrecorded performance figures.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048", "https://mlsys26.flashinfer.ai/"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "```\nInput tokens x [batch, hidden_dim=7168]\n |\n v\n[Router] top-k=8 experts from 32, grouped (8 groups, top_group=4)\n |\n v\n[Dispatch] Scatter tokens to selected experts\n |\n v\n[Gate-Up Dual GEMM]\n gate = x @ W_gate [batch_expert, hidden -> intermediate]\n up = x @ W_up [batch_expert, hidden -> intermediate]\n |\n v\n[SwiGLU Activation]\n h = SiLU(gate) * up Element-wise: SiLU(x) = x * sigmoid(x)\n |\n v\n[Down GEMM]\n y = h @ W_down [batch_expert, intermediate -> hidden]\n |\n v\n[Combine] Weighted sum of expert outputs per token (router weights)\n |\n v\nOutput [batch, hidden_dim=7168]\n```"}, "after": {"statement": "| `seq_len` | variable | Number of input tokens; this is not labeled request batch size |\n| global experts | 256 | Width of `routing_logits` |\n| local experts | 32 | Experts whose weights are resident on one EP rank |\n| expert parallelism | 8 | `256 / 32` ranks in the published definition |\n| `top_k` | 8 | Selected global experts per token |\n| `n_group` | 8 | Groups of 32 global experts |\n| `topk_group` | 4 | Groups retained before global top-k selection |\n| hidden size | 7168 | Input and output width |\n| intermediate size | 2048 | Per-expert SwiGLU width |\n| GEMM1 output | 4096 | Concatenated W13 output, `2 * 2048` |\n| scale block | 128 | Fixed granularity for this DeepSeek-FP8 trace |\n\nThe `e32` suffix means **32 local experts**, not 32 total experts."}, "reason": {"statement": "Distinguish global routing geometry from local expert compute.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "```\nUnfused (vLLM): 7 kernel launches\n 1. Router softmax\n 2. Top-k selection\n 3. Token dispatch (scatter)\n 4. Gate GEMM\n 5. Up GEMM\n 6. SiLU + multiply\n 7. Down GEMM + combine\n\nPartially fused (SGLang): 5 kernel launches\n 1. Router + top-k\n 2. Dispatch\n 3. Gate-Up fused GEMM + SiLU (3 ops -> 1 kernel)\n 4. Down GEMM\n 5. Combine\n\nFully fused (ideal): 1-2 launches\n All ops in single kernel, or gate-up-silu + down-combine\n```"}, "after": {"statement": "[`01-routing-plus-fusion-skeleton.py`](../../artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py) is a CPU-checkable, parameterized reference for grouped selection and local W13/SwiGLU/W2 accumulation. It is derived KernelWiki code, not an optimized kernel and not an upstream contest solution."}, "reason": {"statement": "Do not teach fixed launch counts without a pinned GPU trace.", "urls": []}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "```cpp\n// Fused gate-up: two GEMMs + SiLU + multiply in one kernel\n// Avoids writing intermediate gate and up results to global memory\n\ntemplate \n__global__ void gated_dual_gemm_fused(\n const fp8_t* __restrict__ X, // [M, K] input tokens\n const fp8_t* __restrict__ W_gate, // [N, K] gate weights\n const fp8_t* __restrict__ W_up, // [N, K] up weights\n const float* __restrict__ sf_x, // Block scales for X\n const float* __restrict__ sf_gate, // Block scales for W_gate\n const float* __restrict__ sf_up, // Block scales for W_up\n half* __restrict__ output, // [M, N] fused output\n int M, int N, int K\n) {\n // Two TMEM regions: one for gate accumulator, one for up accumulator\n uint32_t tmem_gate = tmem_alloc_cta(256);\n uint32_t tmem_up = tmem_alloc_cta(256);\n\n // Pipelined main loop\n for (int k = 0; k < K; k += BLOCK_K) {\n int stage = (k / BLOCK_K) % NUM_STAGES;\n barrier_wait(stage);\n\n // Two MMAs per K-tile: gate and up projections\n // Both read same X tile, different weight tiles\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f8f6f4\"\n \" [%0], %1, %2, %3, %4;\"\n :: \"r\"(tmem_gate), \"l\"(x_smem[stage]),\n \"l\"(wg_smem[stage]), \"r\"(scales_gate), \"n\"(1)\n );\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f8f6f4\"\n \" [%0], %1, %2, %3, %4;\"\n :: \"r\"(tmem_up), \"l\"(x_smem[stage]),\n \"l\"(wu_smem[stage]), \"r\"(scales_up), \"n\"(1)\n );\n }\n\n // Fused epilogue: SiLU(gate) * up\n // Read both accumulators from TMEM, apply activation, store result\n float gate_val = tmem_load_f32(tmem_gate);\n float up_val = tmem_load_f32(tmem_up);\n\n // SiLU(x) = x * sigmoid(x) = x / (1 + exp(-x))\n float silu_gate = gate_val / (1.0f + expf(-gate_val));\n output[row * N + col] = __float2half(silu_gate * up_val);\n\n // Deallocate TMEM\n tmem_dealloc(tmem_gate, 256);\n tmem_dealloc(tmem_up, 256);\n}\n```"}, "after": {"statement": "The official reference performs these steps:\n\n1. Convert routing logits to `s = sigmoid(logits)` and form selection scores `s + routing_bias`.\n2. Reshape 256 scores into eight groups of 32. Sum the top two selection scores in each group, then retain four groups.\n3. Select eight global experts from the retained groups using the biased selection scores.\n4. Form combine weights from the **unbiased** sigmoid values for those eight experts, normalize per token, and multiply by `routed_scaling_factor`.\n5. For global expert IDs in `[local_expert_offset, local_expert_offset + 32)`, dequantize the relevant activation and weight blocks, compute one W13 projection, split its 4096 columns into two 2048-column halves, apply SwiGLU, and compute W2.\n6. Accumulate each local expert result into the token output using that expert's combine weight. Experts outside the local interval contribute nothing on that rank.\n\nThe W13 representation permits one logical `A @ W13.T` followed by a split. It does not require two separately allocated TMEM accumulators, and the benchmark contract does not prescribe a tcgen05 instruction sequence."}, "reason": {"statement": "Replace fabricated source with a narrow, executable derived semantic reference.", "urls": []}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "```python\n# FlashInfer API for fused MoE\n# Single function call replaces 5-7 separate kernel launches\nimport flashinfer\n\noutput = flashinfer.fused_moe.trtllm_fp8_block_scale_moe(\n hidden_states=x, # [batch, 7168] BF16 input\n w_gate_up=w_gate_up, # [32, 2*2048, 7168] FP8 (fused gate+up weights)\n w_down=w_down, # [32, 7168, 2048] FP8 (down weights)\n router_weights=router_w, # [batch, 32] FP32 routing logits\n topk=8, # Select top-8 experts per token\n num_groups=8, # Expert grouping\n topk_group=4, # Top groups to select from\n block_scale_gate_up=sf_gu, # Block scales [32, 2*2048, 7168/128] FP8\n block_scale_down=sf_d, # Block scales [32, 7168, 2048/128] FP8\n)\n```"}, "after": {"statement": "For `T = seq_len`, the published benchmark signature is:\n\n| `routing_logits` | FP32 | `[T, 256]` |\n| `routing_bias` | BF16 | `[256]` |\n| `hidden_states` | FP8 E4M3FN | `[T, 7168]` |\n| `hidden_states_scale` | FP32 | `[56, T]` |\n| `gemm1_weights` | FP8 E4M3FN | `[32, 4096, 7168]` |\n| `gemm1_weights_scale` | FP32 | `[32, 32, 56]` |\n| `gemm2_weights` | FP8 E4M3FN | `[32, 7168, 2048]` |\n| `gemm2_weights_scale` | FP32 | `[32, 56, 16]` |\n| `local_expert_offset` | INT32 | scalar |\n| `routed_scaling_factor` | FP32 | scalar |\n\nThe output is BF16 `[T, 7168]`. These scale tensors are explicit storage inputs; this page does not infer their runtime cost from their existence.\n\nAt FlashInfer commit `7f614b86470180bab2d22e36fd1775791c6bf3e6`, the corresponding public entry point is `flashinfer.fused_moe.trtllm_fp8_block_scale_moe`. Its complete call includes the eight tensors above plus `num_experts=256`, `top_k=8`, `n_group=8`, `topk_group=4`, `intermediate_size=2048`, the local expert interval, the routed scaling factor, and DeepSeek-V3 routing mode.\n\n- [FlashInfer trace reference at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/trace/templates/moe.py)\n- [FlashInfer API implementation at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/fused_moe/core.py)"}, "reason": {"statement": "Use the exact benchmark argument names, dtypes, and global/local dimensions.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "```python\nimport triton\nimport triton.language as tl\n\n@triton.jit\ndef fused_moe_gate_up_triton(\n X_ptr, W_gate_ptr, W_up_ptr, Out_ptr,\n expert_ids_ptr, token_counts_ptr,\n sf_x_ptr, sf_gate_ptr, sf_up_ptr,\n N: tl.constexpr, K: tl.constexpr,\n BLOCK_M: tl.constexpr, BLOCK_N: tl.constexpr, BLOCK_K: tl.constexpr,\n):\n \"\"\"Fused gate-up GEMM + SiLU for one expert's tokens.\"\"\"\n expert_id = tl.program_id(2)\n pid_m = tl.program_id(0)\n pid_n = tl.program_id(1)\n\n token_count = tl.load(token_counts_ptr + expert_id)\n m_start = pid_m * BLOCK_M\n if m_start >= token_count:\n return\n\n n_start = pid_n * BLOCK_N\n offs_m = m_start + tl.arange(0, BLOCK_M)\n offs_n = n_start + tl.arange(0, BLOCK_N)\n\n gate_acc = tl.zeros([BLOCK_M, BLOCK_N], dtype=tl.float32)\n up_acc = tl.zeros([BLOCK_M, BLOCK_N], dtype=tl.float32)\n\n for k in range(0, K, BLOCK_K):\n offs_k = k + tl.arange(0, BLOCK_K)\n x_tile = tl.load(X_ptr + offs_m[:, None] * K + offs_k[None, :])\n wg_tile = tl.load(W_gate_ptr + expert_id * N * K\n + offs_n[:, None] * K + offs_k[None, :])\n wu_tile = tl.load(W_up_ptr + expert_id * N * K\n + offs_n[:, None] * K + offs_k[None, :])\n gate_acc += tl.dot(x_tile, tl.trans(wg_tile))\n up_acc += tl.dot(x_tile, tl.trans(wu_tile))\n\n # Fused epilogue: SiLU(gate) * up\n silu_gate = gate_acc * tl.sigmoid(gate_acc)\n result = silu_gate * up_acc\n tl.store(Out_ptr + offs_m[:, None] * N + offs_n[None, :],\n result.to(tl.float16))\n```"}, "after": {"statement": "The official reference performs these steps:\n\n1. Convert routing logits to `s = sigmoid(logits)` and form selection scores `s + routing_bias`.\n2. Reshape 256 scores into eight groups of 32. Sum the top two selection scores in each group, then retain four groups.\n3. Select eight global experts from the retained groups using the biased selection scores.\n4. Form combine weights from the **unbiased** sigmoid values for those eight experts, normalize per token, and multiply by `routed_scaling_factor`.\n5. For global expert IDs in `[local_expert_offset, local_expert_offset + 32)`, dequantize the relevant activation and weight blocks, compute one W13 projection, split its 4096 columns into two 2048-column halves, apply SwiGLU, and compute W2.\n6. Accumulate each local expert result into the token output using that expert's combine weight. Experts outside the local interval contribute nothing on that rank.\n\nThe W13 representation permits one logical `A @ W13.T` followed by a split. It does not require two separately allocated TMEM accumulators, and the benchmark contract does not prescribe a tcgen05 instruction sequence."}, "reason": {"statement": "Remove non-executable code and point to the verified derived semantic reference.", "urls": []}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "| SGLang | 1262 | 206.9us | 5 (fused) |\n| FlashInfer CuTe DSL | 1225 | 481.9us | 1-2 (fully fused) |\n| vLLM | 1117 | 369.5us | 7 (unfused) |"}, "after": {"statement": "[`01-routing-plus-fusion-skeleton.py`](../../artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py) is a CPU-checkable, parameterized reference for grouped selection and local W13/SwiGLU/W2 accumulation. It is derived KernelWiki code, not an optimized kernel and not an upstream contest solution."}, "reason": {"statement": "Remove untraceable performance cells rather than inventing a replacement benchmark.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "1. **No pre-tuned FP8 MoE config for B200**: Tile sizes and pipeline stages need empirical tuning"}, "after": {"statement": "The starter-kit evaluation document at commit `75ccd05cafceb0fd1f86be4cd0f2117249463c66` records:\n\n- bare-metal NVIDIA B200 (`sm_100a`) with clocks locked to `3996,1965`;\n- container `flashinfer/flashinfer-ci-cu132:20260401-2c675fb`;\n- CUDA 13.2, Python 3.12, PyTorch 2.12.0+cu132, and Triton 3.6.0;\n- correctness gates `atol=1`, `rtol=0.3`, and matched ratio `0.9` for the MoE command; and\n- an arithmetic mean of per-workload `FlashInfer baseline latency / candidate latency` as the single-definition MoE score.\n\nThe current primary sources do not support the former framework TFLOPS/latency table, its launch counts, or the structured 1262-TFLOPS record. No performance result is retained here. The official trace axis is `seq_len`; relabeling its endpoints as prefill/decode or batch size requires a separate serving experiment.\n\n- [Starter-kit evaluation contract at `75ccd05`](https://github.com/flashinfer-ai/flashinfer-bench-starter-kit/blob/75ccd05cafceb0fd1f86be4cd0f2117249463c66/EVALUATION.md)"}, "reason": {"statement": "Document the version-pinned autotuner behavior precisely.", "urls": []}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "2. **FP8 numerical overflow**: Block scaling (block size 128) required for stability"}, "after": {"statement": "For `T = seq_len`, the published benchmark signature is:\n\n| `routing_logits` | FP32 | `[T, 256]` |\n| `routing_bias` | BF16 | `[256]` |\n| `hidden_states` | FP8 E4M3FN | `[T, 7168]` |\n| `hidden_states_scale` | FP32 | `[56, T]` |\n| `gemm1_weights` | FP8 E4M3FN | `[32, 4096, 7168]` |\n| `gemm1_weights_scale` | FP32 | `[32, 32, 56]` |\n| `gemm2_weights` | FP8 E4M3FN | `[32, 7168, 2048]` |\n| `gemm2_weights_scale` | FP32 | `[32, 56, 16]` |\n| `local_expert_offset` | INT32 | scalar |\n| `routed_scaling_factor` | FP32 | scalar |\n\nThe output is BF16 `[T, 7168]`. These scale tensors are explicit storage inputs; this page does not infer their runtime cost from their existence.\n\nAt FlashInfer commit `7f614b86470180bab2d22e36fd1775791c6bf3e6`, the corresponding public entry point is `flashinfer.fused_moe.trtllm_fp8_block_scale_moe`. Its complete call includes the eight tensors above plus `num_experts=256`, `top_k=8`, `n_group=8`, `topk_group=4`, `intermediate_size=2048`, the local expert interval, the routed scaling factor, and DeepSeek-V3 routing mode.\n\n- Routing produces different token counts per expert, hence different grouped-GEMM M dimensions. A scheduler can mitigate that imbalance; no single bottleneck is universal across token counts and tactics.\n\n- At the pinned FlashInfer revision, runtime autotuning enumerates valid tactics and selects GEMM1 and GEMM2 tactics over token buckets. Record the exact revision and tuning state in any measurement.\n\n- [FlashInfer trace reference at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/trace/templates/moe.py)\n- [FlashInfer API implementation at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/fused_moe/core.py)"}, "reason": {"statement": "Separate the fixed benchmark ABI from unsupported causal performance language.", "urls": []}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "3. **Batch-size sensitivity**: batch=1 is latency-critical (kernel launch overhead dominates); batch=4096 is throughput-critical"}, "after": {"statement": "[`01-routing-plus-fusion-skeleton.py`](../../artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py) is a CPU-checkable, parameterized reference for grouped selection and local W13/SwiGLU/W2 accumulation. It is derived KernelWiki code, not an optimized kernel and not an upstream contest solution."}, "reason": {"statement": "Use the official axis name and avoid mechanism attribution.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "5. **TMA alignment**: 128-byte alignment required for all TMA descriptors"}, "after": {"statement": "- Routing produces different token counts per expert, hence different grouped-GEMM M dimensions. A scheduler can mitigate that imbalance; no single bottleneck is universal across token counts and tactics.\n\n- At the pinned FlashInfer revision, runtime autotuning enumerates valid tactics and selects GEMM1 and GEMM2 tactics over token buckets. Record the exact revision and tuning state in any measurement."}, "reason": {"statement": "State that alignment is descriptor-configuration dependent and defer to the exact CUDA contract.", "urls": ["https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "6. **Dual TMEM allocation**: Gate and up accumulators each need TMEM space, competing for the 256KB budget"}, "after": {"statement": "| `seq_len` | variable | Number of input tokens; this is not labeled request batch size |\n| global experts | 256 | Width of `routing_logits` |\n| local experts | 32 | Experts whose weights are resident on one EP rank |\n| expert parallelism | 8 | `256 / 32` ranks in the published definition |\n| `top_k` | 8 | Selected global experts per token |\n| `n_group` | 8 | Groups of 32 global experts |\n| `topk_group` | 4 | Groups retained before global top-k selection |\n| hidden size | 7168 | Input and output width |\n| intermediate size | 2048 | Per-expert SwiGLU width |\n| GEMM1 output | 4096 | Concatenated W13 output, `2 * 2048` |\n| scale block | 128 | Fixed granularity for this DeepSeek-FP8 trace |\n\nThe `e32` suffix means **32 local experts**, not 32 total experts.\n\nThe official reference performs these steps:\n\n1. Convert routing logits to `s = sigmoid(logits)` and form selection scores `s + routing_bias`.\n2. Reshape 256 scores into eight groups of 32. Sum the top two selection scores in each group, then retain four groups.\n3. Select eight global experts from the retained groups using the biased selection scores.\n4. Form combine weights from the **unbiased** sigmoid values for those eight experts, normalize per token, and multiply by `routed_scaling_factor`.\n5. For global expert IDs in `[local_expert_offset, local_expert_offset + 32)`, dequantize the relevant activation and weight blocks, compute one W13 projection, split its 4096 columns into two 2048-column halves, apply SwiGLU, and compute W2.\n6. Accumulate each local expert result into the token output using that expert's combine weight. Experts outside the local interval contribute nothing on that rank.\n\nThe W13 representation permits one logical `A @ W13.T` followed by a split. It does not require two separately allocated TMEM accumulators, and the benchmark contract does not prescribe a tcgen05 instruction sequence."}, "reason": {"statement": "Describe the logical W13 contract without inventing TMEM ownership.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "- MoE model inference (DeepSeek-V3, Mixtral, etc.)"}, "after": {"statement": "FlashInfer's MLSys 2026 contest calls Track A **Fused MoE** with FP8 support and targets NVIDIA B200. Its exact benchmark definition is `moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048`. The definition says that DeepSeek-style routing and two grouped GEMMs are included. That operation-level scope does **not** establish that an implementation uses one GPU launch.\n\n- Routing produces different token counts per expert, hence different grouped-GEMM M dimensions. A scheduler can mitigate that imbalance; no single bottleneck is universal across token counts and tactics.\n\n- At the pinned FlashInfer revision, runtime autotuning enumerates valid tactics and selects GEMM1 and GEMM2 tactics over token buckets. Record the exact revision and tuning state in any measurement.\n\n- [MLSys 2026 FlashInfer contest](https://mlsys26.flashinfer.ai/)\n- [Exact FP8 MoE benchmark definition](https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048)"}, "reason": {"statement": "Limit use to producers that match the complete contract.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048", "https://mlsys26.flashinfer.ai/"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "- Both prefill (high batch, throughput-critical) and decode (low batch, latency-critical)"}, "after": {"statement": "[`01-routing-plus-fusion-skeleton.py`](../../artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py) is a CPU-checkable, parameterized reference for grouped selection and local W13/SwiGLU/W2 accumulation. It is derived KernelWiki code, not an optimized kernel and not an upstream contest solution."}, "reason": {"statement": "Keep the exact workload-axis interpretation.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "- Expert load imbalance is the primary practical bottleneck"}, "after": {"statement": "The starter-kit evaluation document at commit `75ccd05cafceb0fd1f86be4cd0f2117249463c66` records:\n\n- bare-metal NVIDIA B200 (`sm_100a`) with clocks locked to `3996,1965`;\n- container `flashinfer/flashinfer-ci-cu132:20260401-2c675fb`;\n- CUDA 13.2, Python 3.12, PyTorch 2.12.0+cu132, and Triton 3.6.0;\n- correctness gates `atol=1`, `rtol=0.3`, and matched ratio `0.9` for the MoE command; and\n- an arithmetic mean of per-workload `FlashInfer baseline latency / candidate latency` as the single-definition MoE score.\n\nThe current primary sources do not support the former framework TFLOPS/latency table, its launch counts, or the structured 1262-TFLOPS record. No performance result is retained here. The official trace axis is `seq_len`; relabeling its endpoints as prefill/decode or batch size requires a separate serving experiment.\n\n- Routing produces different token counts per expert, hence different grouped-GEMM M dimensions. A scheduler can mitigate that imbalance; no single bottleneck is universal across token counts and tactics.\n\n- At the pinned FlashInfer revision, runtime autotuning enumerates valid tactics and selects GEMM1 and GEMM2 tactics over token buckets. Record the exact revision and tuning state in any measurement.\n\n- [Starter-kit evaluation contract at `75ccd05`](https://github.com/flashinfer-ai/flashinfer-bench-starter-kit/blob/75ccd05cafceb0fd1f86be4cd0f2117249463c66/EVALUATION.md)"}, "reason": {"statement": "Replace a universal ranking with measurable workload-specific risks.", "urls": []}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "- CUDA graph compatibility requires masked layout (fixed allocation per expert)"}, "after": {"statement": "- Routing produces different token counts per expert, hence different grouped-GEMM M dimensions. A scheduler can mitigate that imbalance; no single bottleneck is universal across token counts and tactics.\n\n- At the pinned FlashInfer revision, runtime autotuning enumerates valid tactics and selects GEMM1 and GEMM2 tactics over token buckets. Record the exact revision and tuning state in any measurement."}, "reason": {"statement": "Make graph/layout requirements backend- and capture-path-specific.", "urls": []}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "- [GPU Mode NVFP4 Hackathon Problem 3](https://github.com/gpu-mode/reference-kernels)"}, "after": {"statement": "- Small M or partially filled GEMM tiles can reduce utilization. This is a workload-dependent risk, not a retained performance result.\n\n- [CUTLASS efficient-GEMM small-dimension discussion](https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md)"}, "reason": {"statement": "Remove the misleading direct-source link from the page.", "urls": ["https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "- [DeepGEMM MoE](https://github.com/deepseek-ai/DeepGEMM)"}, "after": {"statement": "- Small M or partially filled GEMM tiles can reduce utilization. This is a workload-dependent risk, not a retained performance result.\n\n- [CUTLASS efficient-GEMM small-dimension discussion](https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md)"}, "reason": {"statement": "Keep direct sources claim-specific; discuss adjacency only in artifact provenance.", "urls": ["https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "- [SGLang Fused MoE](https://github.com/sgl-project/sglang)"}, "after": {"statement": "- Small M or partially filled GEMM tiles can reduce utilization. This is a workload-dependent risk, not a retained performance result.\n\n- [CUTLASS efficient-GEMM small-dimension discussion](https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md)"}, "reason": {"statement": "Retain the byte-pinned file but label it adjacent and non-evidentiary for Track A FP8.", "urls": ["https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "Verbatim upstream code lives in [`artifacts/kernels/fused-moe/full/`](../../artifacts/kernels/fused-moe/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live in [`artifacts/kernels/fused-moe/variants/`](../../artifacts/kernels/fused-moe/variants/). Every file's SHA-256 and upstream-pinning metadata is in `PROVENANCE.yaml` inside each bundle."}, "after": {"statement": "- Small M or partially filled GEMM tiles can reduce utilization. This is a workload-dependent risk, not a retained performance result.\n\n- [CUTLASS efficient-GEMM small-dimension discussion](https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md)"}, "reason": {"statement": "Preserve the artifacts while disclosing each exact adjacent scope and replacing the variant with a tested semantic reference.", "urls": ["https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "performance_claims:\n- gpu: B200\n dtype: fp8\n shape: topk=8, experts=32, hidden=7168, intermediate=2048, batch=4096\n metric: TFLOPS\n value: 1262\n utilization: ~56%\n source_id: contest-flashinfer-track-a"}, "after": {"statement": "performance_claims: []\n\n[`01-routing-plus-fusion-skeleton.py`](../../artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py) is a CPU-checkable, parameterized reference for grouped selection and local W13/SwiGLU/W2 accumulation. It is derived KernelWiki code, not an optimized kernel and not an upstream contest solution."}, "reason": {"statement": "Remove inadmissible structured performance metadata.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "sources:\n- contest-flashinfer-track-a\n- blog-deepgemm\n- pr-vllm-23696"}, "after": {"statement": "sources:\n- contest-flashinfer-track-a"}, "reason": {"statement": "Keep source relationships claim-directed.", "urls": ["https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "sources:\n- contest-flashinfer-track-a\n- blog-deepgemm\n- pr-vllm-23696"}, "after": {"statement": "sources:\n- contest-flashinfer-track-a"}, "reason": {"statement": "Remove the direct source relationship and disclose adjacency separately.", "urls": ["https://api.github.com/repos/vllm-project/vllm/pulls/23696", "https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md"]}} +{"path": "wiki/kernels/fused-moe.md", "before": {"statement": "architectures:\n- sm100\n- sm100a\n- sm90\n\ntags:\n- moe\n- fused-kernel\n- fp8\n- block-scale\n- kernel-fusion\n- warp-specialization\n- grouped-gemm\n- gated-dual-gemm\n\nlanguages:\n- cuda-cpp\n- cute-dsl\n- triton\n\nblackwell_relevance: SM100 enables native FP8 block-scale MoE via tcgen05 with higher\n throughput; technique transfers from Hopper FP8 MoE."}, "after": {"statement": "architectures:\n- sm100\n- sm100a\n\ntags:\n- moe\n- fp8\n- block-scale\n- grouped-gemm\n- kernel-fusion\n\nlanguages:\n- cuda-cpp\n- cute-dsl\n- triton\n\nblackwell_relevance: The MLSys 2026 Track A definition and official evaluation\n target NVIDIA B200 (sm_100a); this page documents the logical benchmark\n contract, not a particular launch decomposition."}, "reason": {"statement": "Limit frontmatter to the verified B200/SM100a contract and implementation languages accepted by the contest.", "urls": ["https://mlsys26.flashinfer.ai/", "https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "The key advantage is O(1) per-token cost during decoding: the recurrent state is a fixed-size matrix that gets updated with each new token, eliminating the KV cache growth problem entirely."}, "after": {"statement": "- NVlabs commit `b53d6d3` is the authors' PyTorch/Triton research implementation. Its README recommends FLA for faster kernels and variable-length functionality."}, "reason": {"statement": "Preserve the fixed-state advantage while stating the hybrid-model boundary.", "urls": ["https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct/blob/9c7f2fbe84465e40164a94cc16cd30b6999b0cc7/config.json", "https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "```\nQwen3-Next-80B: 48 layers\nPattern: 12 x (3 x [GatedDeltaNet -> MoE] -> [Full Attention -> MoE])\n\nLayer distribution:\n - 36 GatedDeltaNet layers (75%): O(n) linear attention\n - 12 Full Attention layers (25%): Standard GQA for global retrieval\n - All layers followed by MoE: 512 experts, ~19 active per token\n\nTotal: 80B parameters, only 3B active per token\n```"}, "after": {"statement": "The immutable `Qwen3-Next-80B-A3B-Instruct` configuration at revision `9c7f2fbe` records:\n\n| Layers | 48 |\n| Hybrid layout | `12 * (3 * Gated DeltaNet -> MoE, 1 * Gated Attention -> MoE)` |\n| GDN heads | 16 QK heads, 32 value heads, head dimension 128 |\n| MoE | 512 experts; 10 routed experts plus one shared expert |\n| Parameters | 80B total, 3B activated |\n| Native context | 262,144 tokens |\n\nThus 36 layers use GDN and 12 use full Gated Attention. The fixed GDN state does not eliminate cache growth for the whole hybrid model: the full-attention layers retain their own context-dependent cache."}, "reason": {"statement": "Use the immutable model-card architecture fields.", "urls": ["https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct", "https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct/blob/9c7f2fbe84465e40164a94cc16cd30b6999b0cc7/config.json", "https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct/tree/9c7f2fbe84465e40164a94cc16cd30b6999b0cc7"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "```python\n# Standard linear attention (additive):\n# S_t = S_{t-1} + v_t @ k_t^T\n#\n# Delta rule (error-correcting):\n# S_t = S_{t-1} + (v_t - S_{t-1} @ k_t) @ k_t^T\n# ^^^^^^^^^^^^^^^^^^^^^^^^\n# Error correction term\n\ndef delta_rule_step(S, k, v, beta, alpha):\n \"\"\"\n Single step of gated delta rule update.\n\n S: recurrent state [d_k, d_v] (the \"memory matrix\")\n k: key vector [d_k]\n v: value vector [d_v]\n beta: exponential gate (learned, controls decay)\n alpha: delta gate (learned, controls update strength)\n \"\"\"\n # Retrieve what the current state \"thinks\" about this key\n v_retrieved = S @ k # [d_v]\n\n # Error: difference between true value and retrieved value\n delta = v - v_retrieved # [d_v]\n\n # Gated update: decay old state, add error-corrected new info\n S_new = beta * S + alpha * (delta[:, None] @ k[None, :])\n # ^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n # decay error-correcting update\n\n return S_new\n```"}, "after": {"statement": "Gated DeltaNet is a recurrent linear-attention architecture published at ICLR 2025. For one head with state `S` shaped `[K,V]`, the FlashInfer reference at commit `7f614b8` implements the update in this equivalent form:\n\n```python\ndef gdn_step(S, q, k, v, A_log, a, dt_bias, b, scale):\n g = exp(-exp(A_log) * softplus(a + dt_bias))\n beta = sigmoid(b)\n decayed = g * S\n read = k @ decayed\n S_new = decayed + outer(k, beta * (v - read))\n output = scale * (q @ S_new)\n return output, S_new\n```\n\nThe subtraction is the delta-rule correction: the update moves the value retrieved at `k` toward `v`, while `g` independently decays the previous state. The recurrent state has no prior-token axis, so a single GDN decode step has work and storage fixed with respect to context length. Its per-head state update is still proportional to `K*V`; “constant” here means constant in the number of earlier tokens.\n\nTFLA (`arXiv:2503.14376v3`) is related linear-recurrence work, but its published application and official code are for mLSTM. They use a second level of sequence parallelization to permit arbitrarily large chunks. They do not establish a GDN implementation or an inline WGMMA/tcgen05 path, so no TFLA assembly is presented here."}, "reason": {"statement": "Replace with an executable recurrence matching the exact reference.", "urls": []}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "During prefill, sequences are divided into chunks that can be processed in parallel. Within each chunk, the inter-token dependencies are resolved via a causal linear recurrence; across chunks, the recurrent state is propagated sequentially."}, "after": {"statement": "The MLSys 2026 organizer identifies Gated Delta Net as Track C and links separate verified definitions captured from Qwen3-Next with tensor parallelism four.\n\n| Q heads / K heads / V heads | `4 / 4 / 8` | `4 / 4 / 8` |\n| Head size | `128` | `128` |\n| Token axis | `seq_len=1`, variable `batch_size` | variable `total_seq_len` and `num_seqs` |\n| Q/K/V dtype | BF16 | BF16 |\n| State | FP32 `[B,8,128,128]` | FP32 `[N,8,128,128]` |\n| Variable-length metadata | none | `cu_seqlens[N+1]` |\n\nDecode exposes `A_log`, `a`, `dt_bias`, and `b` for the decay and update gates, plus an optional scale. It returns BF16 output `[B,1,8,128]` and the updated state. Prefill returns BF16 output `[total_seq_len,8,128]` and one final state per sequence.\n\nFor this exact geometry, one value-head state contains `128*128 = 16,384` FP32 values, or 64 KiB. All eight value heads contain 131,072 FP32 values, or 512 KiB, per sequence and layer. The heads are independent states; they must not be flattened into one `512x1024` matrix."}, "reason": {"statement": "Describe only the verified chunkwise boundary and point to the exact implementation.", "urls": ["https://mlsys26.flashinfer.ai/", "https://bench.flashinfer.ai/kernels/gdn_decode_qk4_v8_d128_k_last", "https://bench.flashinfer.ai/kernels/gdn_prefill_qk4_v8_d128_k_last"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "```python\nimport triton\nimport triton.language as tl\n\n@triton.jit\ndef gated_delta_net_chunk_fwd(\n Q_ptr, K_ptr, V_ptr, Beta_ptr, O_ptr, State_ptr,\n SEQ_LEN: tl.constexpr,\n CHUNK_SIZE: tl.constexpr, # e.g., 64 or 128\n D_QK: tl.constexpr, # qk_dim * d = 4 * 128 = 512\n D_V: tl.constexpr, # v_dim * d = 8 * 128 = 1024\n):\n \"\"\"\n Chunk-parallel forward pass for GatedDeltaNet.\n Two levels of parallelism:\n 1. Across chunks (parallel after inter-chunk state propagation)\n 2. Within chunks (parallel via matrix operations)\n \"\"\"\n chunk_id = tl.program_id(0)\n batch_id = tl.program_id(1)\n head_id = tl.program_id(2)\n\n chunk_start = chunk_id * CHUNK_SIZE\n\n # Load recurrent state from previous chunk\n # S shape: [D_QK, D_V]\n S = tl.load(State_ptr + (batch_id * NUM_HEADS + head_id) * D_QK * D_V\n + tl.arange(0, D_QK)[:, None] * D_V\n + tl.arange(0, D_V)[None, :])\n\n # Intra-chunk computation\n for t in range(CHUNK_SIZE):\n pos = chunk_start + t\n\n # Load q, k, v, beta for this token\n q = tl.load(Q_ptr + pos * D_QK + tl.arange(0, D_QK))\n k = tl.load(K_ptr + pos * D_QK + tl.arange(0, D_QK))\n v = tl.load(V_ptr + pos * D_V + tl.arange(0, D_V))\n beta = tl.load(Beta_ptr + pos)\n\n # Output: query the state\n o = tl.sum(S * q[:, None], axis=0) # [D_V]\n\n # Delta rule update\n v_retrieved = tl.sum(S * k[:, None], axis=0)\n delta = v - v_retrieved\n\n # Gated state update\n S = beta * S + delta[:, None] * k[None, :] # [D_QK, D_V]\n\n # Store output\n tl.store(O_ptr + pos * D_V + tl.arange(0, D_V), o)\n\n # Store final state for next chunk\n tl.store(State_ptr + (batch_id * NUM_HEADS + head_id) * D_QK * D_V\n + tl.arange(0, D_QK)[:, None] * D_V\n + tl.arange(0, D_V)[None, :], S)\n```"}, "after": {"statement": "Qwen's architecture article attributes attention-sink and massive-activation mitigation to the output gate in its full Gated Attention path and says the gate *helps* address those effects. That is separate from the GDN recurrence and is not a requirement imposed by the GDN kernel contract.\n\nTFLA (`arXiv:2503.14376v3`) is related linear-recurrence work, but its published application and official code are for mLSTM. They use a second level of sequence parallelization to permit arbitrarily large chunks. They do not establish a GDN implementation or an inline WGMMA/tcgen05 path, so no TFLA assembly is presented here."}, "reason": {"statement": "A short exact recurrence and pinned production sources are more useful than a misleading non-executable kernel.", "urls": ["https://bench.flashinfer.ai/kernels/gdn_prefill_qk4_v8_d128_k_last", "https://qwen.ai/blog?id=e34c4305036ce60d55a0791b170337c2b70ae51d"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "```python\n@triton.jit\ndef gated_delta_net_decode(\n Q_ptr, K_ptr, V_ptr, Beta_ptr, O_ptr, State_ptr,\n D_QK: tl.constexpr,\n D_V: tl.constexpr,\n):\n \"\"\"\n Single-token decode: O(1) per token.\n The recurrent state replaces the KV cache entirely.\n State size: D_QK * D_V (e.g., 512 * 1024 = 512K floats per head)\n \"\"\"\n batch_id = tl.program_id(0)\n head_id = tl.program_id(1)\n\n # Load persistent recurrent state\n state_offset = (batch_id * NUM_HEADS + head_id) * D_QK * D_V\n S = tl.load(State_ptr + state_offset\n + tl.arange(0, D_QK)[:, None] * D_V\n + tl.arange(0, D_V)[None, :])\n\n # Load new token\n q = tl.load(Q_ptr + tl.arange(0, D_QK))\n k = tl.load(K_ptr + tl.arange(0, D_QK))\n v = tl.load(V_ptr + tl.arange(0, D_V))\n beta = tl.load(Beta_ptr)\n\n # Query state for output\n o = tl.sum(S * q[:, None], axis=0)\n\n # Update state with delta rule\n v_retrieved = tl.sum(S * k[:, None], axis=0)\n delta = v - v_retrieved\n S = beta * S + delta[:, None] * k[None, :]\n\n # Store\n tl.store(O_ptr + tl.arange(0, D_V), o)\n tl.store(State_ptr + state_offset\n + tl.arange(0, D_QK)[:, None] * D_V\n + tl.arange(0, D_V)[None, :], S)\n```"}, "after": {"statement": "Qwen's architecture article attributes attention-sink and massive-activation mitigation to the output gate in its full Gated Attention path and says the gate *helps* address those effects. That is separate from the GDN recurrence and is not a requirement imposed by the GDN kernel contract.\n\nTFLA (`arXiv:2503.14376v3`) is related linear-recurrence work, but its published application and official code are for mLSTM. They use a second level of sequence parallelization to permit arbitrarily large chunks. They do not establish a GDN implementation or an inline WGMMA/tcgen05 path, so no TFLA assembly is presented here."}, "reason": {"statement": "Remove code that cannot represent the benchmark semantics.", "urls": ["https://bench.flashinfer.ai/kernels/gdn_decode_qk4_v8_d128_k_last", "https://qwen.ai/blog?id=e34c4305036ce60d55a0791b170337c2b70ae51d"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "TFLA adds a second level of tiling within chunks, enabling arbitrarily large chunk sizes. It emits matmuls as inline PTX assembly for both Hopper (WGMMA) and Blackwell (tcgen05)."}, "after": {"statement": "The `full/` bundle contains one byte-pinned SGLang file from merge `5bdc07d974f6cf236fa765a685453ea5e587a838`. It fuses projection-output split/reshape/concatenation for Qwen3-Next/Qwen3.5; it is adjacent preprocessing, not a GDN recurrence, prefill, or decode implementation."}, "reason": {"statement": "Retain TFLA only as separate mLSTM background and remove implementation transfer.", "urls": ["https://arxiv.org/abs/2503.14376"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "```cpp\n// TFLA: Inline PTX for Blackwell tcgen05 matmul within chunk tiles\n// Two levels of parallelism: standard chunkwise + tiling within chunks\n\n// SM100 path: tcgen05.mma for intra-chunk matrix operations\nasm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16f16f32\"\n \" [%0], %1, %2;\"\n :\n : \"l\"(tmem_addr), \"l\"(a_smem_addr), \"l\"(b_smem_addr)\n);\n```"}, "after": {"statement": "The `full/` bundle contains one byte-pinned SGLang file from merge `5bdc07d974f6cf236fa765a685453ea5e587a838`. It fuses projection-output split/reshape/concatenation for Qwen3-Next/Qwen3.5; it is adjacent preprocessing, not a GDN recurrence, prefill, or decode implementation."}, "reason": {"statement": "Delete fabricated assembly rather than implying it can compile.", "urls": []}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "- Status: decode done for both Hopper and Blackwell; prefill done on Hopper, in progress for Blackwell"}, "after": {"statement": "The MLSys 2026 organizer identifies Gated Delta Net as Track C and links separate verified definitions captured from Qwen3-Next with tensor parallelism four.\n\n| Q heads / K heads / V heads | `4 / 4 / 8` | `4 / 4 / 8` |\n| Head size | `128` | `128` |\n| Token axis | `seq_len=1`, variable `batch_size` | variable `total_seq_len` and `num_seqs` |\n| Q/K/V dtype | BF16 | BF16 |\n| State | FP32 `[B,8,128,128]` | FP32 `[N,8,128,128]` |\n| Variable-length metadata | none | `cu_seqlens[N+1]` |\n\nDecode exposes `A_log`, `a`, `dt_bias`, and `b` for the decay and update gates, plus an optional scale. It returns BF16 output `[B,1,8,128]` and the updated state. Prefill returns BF16 output `[total_seq_len,8,128]` and one final state per sequence.\n\nFor this exact geometry, one value-head state contains `128*128 = 16,384` FP32 values, or 64 KiB. All eight value heads contain 131,072 FP32 values, or 512 KiB, per sequence and layer. The heads are independent states; they must not be flattened into one `512x1024` matrix."}, "reason": {"statement": "Replace stale issue status with pinned implementation status and prerequisites.", "urls": ["https://mlsys26.flashinfer.ai/", "https://bench.flashinfer.ai/kernels/gdn_decode_qk4_v8_d128_k_last", "https://bench.flashinfer.ai/kernels/gdn_prefill_qk4_v8_d128_k_last"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "- Long-context inference (32K+) where O(n) scaling provides major throughput gains"}, "after": {"statement": "- [Gated DeltaNet paper](https://arxiv.org/abs/2412.06464)\n- [NVlabs implementation at `b53d6d3`](https://github.com/NVlabs/GatedDeltaNet/tree/b53d6d3a161267432a79c1c04af69fa52bddc921)\n- [Qwen3-Next model card and configuration at `9c7f2fbe`](https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct/tree/9c7f2fbe84465e40164a94cc16cd30b6999b0cc7)\n- [MLSys 2026 organizer](https://mlsys26.flashinfer.ai/)\n- [Exact decode definition](https://bench.flashinfer.ai/kernels/gdn_decode_qk4_v8_d128_k_last)\n- [Exact prefill definition](https://bench.flashinfer.ai/kernels/gdn_prefill_qk4_v8_d128_k_last)\n- [FlashInfer GDN trace at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/trace/templates/gdn.py)\n- [FlashInfer prefill dispatch at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/gdn_prefill.py)\n- [CUDA Graphs programming guide](https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cuda-graphs.html)\n- [TFLA v3](https://arxiv.org/abs/2503.14376v3)"}, "reason": {"statement": "Retain asymptotic and model-report facts without claiming an isolated threshold or universal gain.", "urls": ["https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "- Streaming decode where O(1) per-token cost eliminates KV cache growth"}, "after": {"statement": "- NVlabs commit `b53d6d3` is the authors' PyTorch/Triton research implementation. Its README recommends FLA for faster kernels and variable-length functionality."}, "reason": {"statement": "State the layer-local storage property and hybrid exception.", "urls": ["https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct/blob/9c7f2fbe84465e40164a94cc16cd30b6999b0cc7/config.json"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "- Recurrent state size (D_QK * D_V per head) can be large -- 512K floats for typical configs"}, "after": {"statement": "Qwen's architecture article attributes attention-sink and massive-activation mitigation to the output gate in its full Gated Attention path and says the gate *helps* address those effects. That is separate from the GDN recurrence and is not a requirement imposed by the GDN kernel contract."}, "reason": {"statement": "Use exact benchmark dimensions and distinguish per-head from aggregate storage.", "urls": ["https://bench.flashinfer.ai/kernels/gdn_decode_qk4_v8_d128_k_last", "https://qwen.ai/blog?id=e34c4305036ce60d55a0791b170337c2b70ae51d"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "- Attention output gating (in Qwen3.5) is required to eliminate Attention Sink and Massive Activation problems"}, "after": {"statement": "- vLLM merge `e1d85e5c` gives its recurrent-attention backend uniform-batch CUDA-graph support for decode. CUDA graphs reduce CPU launch setup cost, but their benefit remains workload-dependent."}, "reason": {"statement": "Keep the useful architectural caveat with its exact scope and modality.", "urls": ["https://qwen.ai/blog?id=e34c4305036ce60d55a0791b170337c2b70ae51d", "https://github.com/vllm-project/vllm/blob/e1d85e5c2454bd8d349dbe676679380cbe0e920a/vllm/v1/attention/backends/mamba_attn.py", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cuda-graphs.html"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "Verbatim upstream code lives in [`artifacts/kernels/gated-delta-net/full/`](../../artifacts/kernels/gated-delta-net/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live in [`artifacts/kernels/gated-delta-net/variants/`](../../artifacts/kernels/gated-delta-net/variants/). Every file's SHA-256 and upstream-pinning metadata is in `PROVENANCE.yaml` inside each bundle."}, "after": {"statement": "TFLA (`arXiv:2503.14376v3`) is related linear-recurrence work, but its published application and official code are for mLSTM. They use a second level of sequence parallelization to permit arbitrarily large chunks. They do not establish a GDN implementation or an inline WGMMA/tcgen05 path, so no TFLA assembly is presented here.\n\nGDN sequence mixing scales linearly with sequence length, but asymptotic complexity is not a measured speedup. Qwen reports a 10x whole-model inference-throughput comparison against Qwen3-32B for contexts over 32K, while also warning that efficiency depends strongly on implementation. That result does not isolate this kernel, name a GPU, or describe the Track C qk4/v8/d128 workloads, so it is not stored as a kernel performance record.\n\nUse an exact backend measurement for the intended batch, sequence distribution, dtype, state layout, software revision, and GPU. Also account for the context-growing full-attention cache in a hybrid model and for the GDN layer's learned projections, gates, convolution, and state; it is not a weight-compatible runtime substitute for a trained softmax-attention layer."}, "reason": {"statement": "Relabel the upstream projection helper as adjacent and replace false variants with one tested semantic recurrence.", "urls": ["https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct/tree/9c7f2fbe84465e40164a94cc16cd30b6999b0cc7", "https://github.com/NVlabs/GatedDeltaNet/blob/b53d6d3a161267432a79c1c04af69fa52bddc921/lit_gpt/gated_delta_net.py"]}} +{"path": "wiki/kernels/gated-delta-net.md", "before": {"statement": "performance_claims:\n- gpu: H100\n dtype: bf16\n shape: seqlen=8192, qk_dim=4, v_dim=8, d=128\n metric: speedup\n value: 10\n utilization: vs Qwen3-32B at 32K+ context, O(n) linear complexity\n source_id: blog-gated-delta-net"}, "after": {"statement": "performance_claims: []\n\n- [Gated DeltaNet paper](https://arxiv.org/abs/2412.06464)\n- [NVlabs implementation at `b53d6d3`](https://github.com/NVlabs/GatedDeltaNet/tree/b53d6d3a161267432a79c1c04af69fa52bddc921)\n- [Qwen3-Next model card and configuration at `9c7f2fbe`](https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct/tree/9c7f2fbe84465e40164a94cc16cd30b6999b0cc7)\n- [MLSys 2026 organizer](https://mlsys26.flashinfer.ai/)\n- [Exact decode definition](https://bench.flashinfer.ai/kernels/gdn_decode_qk4_v8_d128_k_last)\n- [Exact prefill definition](https://bench.flashinfer.ai/kernels/gdn_prefill_qk4_v8_d128_k_last)\n- [FlashInfer GDN trace at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/trace/templates/gdn.py)\n- [FlashInfer prefill dispatch at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/gdn_prefill.py)\n- [CUDA Graphs programming guide](https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cuda-graphs.html)\n- [TFLA v3](https://arxiv.org/abs/2503.14376v3)"}, "reason": {"statement": "No evidence-supported numeric kernel record can replace the fabricated structured tuple.", "urls": ["https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct"]}} +{"path": "wiki/kernels/gated-dual-gemm.md", "before": {"statement": "Gated dual GEMM fuses two matrix multiplications with activation and elementwise operations — the canonical MLP gate-up pattern used by LLaMA, Qwen, DeepSeek, and most modern LLMs. Fusion eliminates two global memory roundtrips compared to separate gate/up GEMM + SwiGLU."}, "after": {"statement": "The official NVIDIA rules identify NVFP4 Gated Dual GEMM as Kernel Challenge 3 of the Blackwell NVFP4 Hackathon, open from December 20, 2025 through January 16, 2026. The public GPU Mode problem at challenge-opening commit `c5b2f7c` targets NVIDIA B200.\n\nThe shared `a` and `sfa` inputs create an opportunity to reuse data across the two products, and a genuinely fused epilogue can avoid writing both full-precision products to global memory. Those are optimization possibilities, not task guarantees.\n\nThe public task/reference does not establish a final leaderboard, winning source, single-launch decomposition, physical load count, TMEM accumulator partition, TMA pipeline, CUTLASS schedule, or compute-/memory-bound classification. If an implementation uses `tcgen05`, TMEM, or TMA, its exact descriptors, scale layouts, synchronization, allocation, and architecture requirements must be verified from that implementation and the version-matched ISA.\n\nCompatibility is correspondingly narrower than “any dual-output operation”: a model/backend must match the two same-shaped NVFP4 products, scale storage and layouts, first-branch SiLU, FP16 output, batching, and divisibility rules. Grouped per-expert MoE execution is a different contract unless an implementation explicitly supplies that grouping layer."}, "reason": {"statement": "Retain exact dual-GEMM/SwiGLU semantics while separating potential fusion benefits from contract guarantees.", "urls": ["https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf", "https://github.com/gpu-mode/reference-kernels/blob/c5b2f7c062d5015f29c3a1043cfd04954397944c/problems/nvidia/nvfp4_dual_gemm/task.yml"]}} +{"path": "wiki/kernels/gated-dual-gemm.md", "before": {"statement": "```\nGiven x, W_gate, W_up (weights shared same K dimension)\nStandard (unfused):\n gate = x @ W_gate (GEMM 1: reads x, W_gate, writes gate)\n up = x @ W_up (GEMM 2: reads x, W_up, writes up)\n silu = gate * sigmoid(gate) (elementwise: reads gate, writes silu)\n out = silu * up (elementwise: reads silu, up, writes out)\n\nFused:\n out = SiLU(x @ W_gate) * (x @ W_up) (single kernel, no intermediate GMEM)\n```"}, "after": {"statement": "| `a` | NVFP4 E2M1 | `[M,K,L]`, K-major |\n| `b1`, `b2` | NVFP4 E2M1 | `[N,K,L]`, K-major |\n| `sfa` | FP8 E4M3FNUZ | `[M,K/16,L]`, K-major |\n| `sfb1`, `sfb2` | FP8 E4M3FNUZ | `[N,K/16,L]`, K-major |\n| `c` | FP16 | `[M,N,L]` |\n\nThe submission tuple also supplies layout-reordered copies of `sfa`, `sfb1`, and `sfb2`, plus preallocated `c`. `K` is divisible by 256; `M` and `N` must be divisible by the selected MMA tile dimensions. The correctness checker uses `rtol=1e-3` and `atol=1e-3`.\n\nThe pinned upstream files contain one dtype-label inconsistency: `task.yml` and `template.py` call the scales E4M3FNUZ, while `reference.py` constructs `torch.float8_e4m3fn`. A backend must follow the actual submission objects rather than treating those spellings as interchangeable.\n\nThe shared `a` and `sfa` inputs create an opportunity to reuse data across the two products, and a genuinely fused epilogue can avoid writing both full-precision products to global memory. Those are optimization possibilities, not task guarantees.\n\nThe public task/reference does not establish a final leaderboard, winning source, single-launch decomposition, physical load count, TMEM accumulator partition, TMA pipeline, CUTLASS schedule, or compute-/memory-bound classification. If an implementation uses `tcgen05`, TMEM, or TMA, its exact descriptors, scale layouts, synchronization, allocation, and architecture requirements must be verified from that implementation and the version-matched ISA.\n\nCompatibility is correspondingly narrower than “any dual-output operation”: a model/backend must match the two same-shaped NVFP4 products, scale storage and layouts, first-branch SiLU, FP16 output, batching, and divisibility rules. Grouped per-expert MoE execution is a different contract unless an implementation explicitly supplies that grouping layer."}, "reason": {"statement": "Keep the exact formula without converting a possible optimization into an ABI requirement.", "urls": []}} +{"path": "wiki/kernels/gated-dual-gemm.md", "before": {"statement": "```cuda\ntemplate \n__global__ void gated_dual_gemm_nvfp4(\n const nvfp4_t* __restrict__ X, // [M, K] input\n const nvfp4_t* __restrict__ W_gate, // [N, K] gate weights\n const nvfp4_t* __restrict__ W_up, // [N, K] up weights\n const fp8_t* sf_x, const fp8_t* sf_gate, const fp8_t* sf_up,\n half* __restrict__ output, // [M, N] output\n int M, int N, int K\n) {\n // Two TMEM regions: one accumulator per GEMM\n uint32_t tmem_gate = tmem_alloc(256);\n uint32_t tmem_up = tmem_alloc(256);\n\n for (int k = 0; k < K; k += BLOCK_K) {\n int stage = (k / BLOCK_K) % NUM_STAGES;\n mbarrier_wait(&tma_done[stage]);\n\n // Two MMAs per K-tile: gate and up\n // Both read same X tile, different weight tiles\n tcgen05_mma(x_smem[stage], wg_smem[stage], tmem_gate);\n tcgen05_mma(x_smem[stage], wu_smem[stage], tmem_up);\n }\n\n // Fused epilogue: SiLU(gate) * up\n float g = tmem_load(tmem_gate);\n float u = tmem_load(tmem_up);\n float s = g / (1.0f + expf(-g)); // SiLU\n output[row * N + col] = __float2half(s * u);\n\n tmem_dealloc(tmem_gate, 256);\n tmem_dealloc(tmem_up, 256);\n}\n```"}, "after": {"statement": "| `a` | NVFP4 E2M1 | `[M,K,L]`, K-major |\n| `b1`, `b2` | NVFP4 E2M1 | `[N,K,L]`, K-major |\n| `sfa` | FP8 E4M3FNUZ | `[M,K/16,L]`, K-major |\n| `sfb1`, `sfb2` | FP8 E4M3FNUZ | `[N,K/16,L]`, K-major |\n| `c` | FP16 | `[M,N,L]` |\n\nThe submission tuple also supplies layout-reordered copies of `sfa`, `sfb1`, and `sfb2`, plus preallocated `c`. `K` is divisible by 256; `M` and `N` must be divisible by the selected MMA tile dimensions. The correctness checker uses `rtol=1e-3` and `atol=1e-3`.\n\nThe pinned upstream files contain one dtype-label inconsistency: `task.yml` and `template.py` call the scales E4M3FNUZ, while `reference.py` constructs `torch.float8_e4m3fn`. A backend must follow the actual submission objects rather than treating those spellings as interchangeable.\n\nThe shared `a` and `sfa` inputs create an opportunity to reuse data across the two products, and a genuinely fused epilogue can avoid writing both full-precision products to global memory. Those are optimization possibilities, not task guarantees.\n\nThe public task/reference does not establish a final leaderboard, winning source, single-launch decomposition, physical load count, TMEM accumulator partition, TMA pipeline, CUTLASS schedule, or compute-/memory-bound classification. If an implementation uses `tcgen05`, TMEM, or TMA, its exact descriptors, scale layouts, synchronization, allocation, and architecture requirements must be verified from that implementation and the version-matched ISA.\n\nCompatibility is correspondingly narrower than “any dual-output operation”: a model/backend must match the two same-shaped NVFP4 products, scale storage and layouts, first-branch SiLU, FP16 output, batching, and divisibility rules. Grouped per-expert MoE execution is a different contract unless an implementation explicitly supplies that grouping layer."}, "reason": {"statement": "Replace non-executable hardware pseudocode with an exact host-checkable semantic reference and pinned upstream sources.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/kernels/gated-dual-gemm.md", "before": {"statement": "1. **X reuse**: Same X tile feeds both MMAs — loaded once, used twice\n2. **TMEM dual accumulator**: Blackwell's 512-column TMEM fits two 256-col accumulators side-by-side\n3. **Fused epilogue**: SiLU and multiply happen after TMEM load, no intermediate SMEM\n4. **Shared SFA**: X's block scales apply to both gate and up computations"}, "after": {"statement": "For each batch index, the required result is two block-scaled matrix products sharing the same left operand, with SiLU applied only to the first branch:\n\n```python\ndef gated_dual_result(a, b1, b2, scale_a, scale_b1, scale_b2, scaled_mm):\n gate = scaled_mm(a, b1.T, scale_a, scale_b1)\n up = scaled_mm(a, b2.T, scale_a, scale_b2)\n return silu(gate) * up\n```\n\nThis fixes result semantics and branch order. It does not require the submission entry point to use one GPU launch or forbid intermediate storage.\n\nThe shared `a` and `sfa` inputs create an opportunity to reuse data across the two products, and a genuinely fused epilogue can avoid writing both full-precision products to global memory. Those are optimization possibilities, not task guarantees.\n\nThe public task/reference does not establish a final leaderboard, winning source, single-launch decomposition, physical load count, TMEM accumulator partition, TMA pipeline, CUTLASS schedule, or compute-/memory-bound classification. If an implementation uses `tcgen05`, TMEM, or TMA, its exact descriptors, scale layouts, synchronization, allocation, and architecture requirements must be verified from that implementation and the version-matched ISA.\n\nCompatibility is correspondingly narrower than “any dual-output operation”: a model/backend must match the two same-shaped NVFP4 products, scale storage and layouts, first-branch SiLU, FP16 output, batching, and divisibility rules. Grouped per-expert MoE execution is a different contract unless an implementation explicitly supplies that grouping layer."}, "reason": {"statement": "Separate exact shared-input semantics from unsupported schedule claims.", "urls": []}} +{"path": "wiki/kernels/gated-dual-gemm.md", "before": {"statement": "- MLP layers in modern LLMs (LLaMA, Qwen, DeepSeek, Mistral)\n- Any dual-output operation sharing one input\n- MoE expert computations (expand to per-expert fused kernels)"}, "after": {"statement": "For each batch index, the required result is two block-scaled matrix products sharing the same left operand, with SiLU applied only to the first branch:\n\n```python\ndef gated_dual_result(a, b1, b2, scale_a, scale_b1, scale_b2, scaled_mm):\n gate = scaled_mm(a, b1.T, scale_a, scale_b1)\n up = scaled_mm(a, b2.T, scale_a, scale_b2)\n return silu(gate) * up\n```\n\nThis fixes result semantics and branch order. It does not require the submission entry point to use one GPU launch or forbid intermediate storage.\n\nThe shared `a` and `sfa` inputs create an opportunity to reuse data across the two products, and a genuinely fused epilogue can avoid writing both full-precision products to global memory. Those are optimization possibilities, not task guarantees.\n\nThe public task/reference does not establish a final leaderboard, winning source, single-launch decomposition, physical load count, TMEM accumulator partition, TMA pipeline, CUTLASS schedule, or compute-/memory-bound classification. If an implementation uses `tcgen05`, TMEM, or TMA, its exact descriptors, scale layouts, synchronization, allocation, and architecture requirements must be verified from that implementation and the version-matched ISA.\n\nCompatibility is correspondingly narrower than “any dual-output operation”: a model/backend must match the two same-shaped NVFP4 products, scale storage and layouts, first-branch SiLU, FP16 output, batching, and divisibility rules. Grouped per-expert MoE execution is a different contract unless an implementation explicitly supplies that grouping layer."}, "reason": {"statement": "Replace universal use advice with an explicit compatibility checklist.", "urls": []}} +{"path": "wiki/kernels/gated-dual-gemm.md", "before": {"statement": "The reference bundle lives in [`artifacts/kernels/gated-dual-gemm/full/`](../../artifacts/kernels/gated-dual-gemm/full/) and combines the upstream vLLM PR-23696 diff (`vllm-PR-23696-gated-dual-gemm.patch`, `mode: upstream-patch`) with an extracted CUTLASS-schedule snippet from the `tflops-gap-fp4-moe` blog (`blackwell-cutlass-schedules-and-tma.cu`, `mode: extracted`). Labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live in [`artifacts/kernels/gated-dual-gemm/variants/`](../../artifacts/kernels/gated-dual-gemm/variants/). Every file's SHA-256 and upstream-pinning metadata is in `PROVENANCE.yaml` inside each bundle."}, "after": {"statement": "The `full/` bundle contains the byte-pinned official `task.yml` from commit `c5b2f7c`; it is the problem specification, not an optimized submission. The unrelated third-party schedule extract and duplicate vLLM MXFP4 MoE patch formerly stored here were removed; the latter remains preserved in its own PR artifact collection."}, "reason": {"statement": "Preserve useful evidence with corrected scope and replace the untested variant with a discriminating semantic test.", "urls": []}} +{"path": "wiki/kernels/gated-dual-gemm.md", "before": {"statement": "performance_claims:\n- gpu: B200\n dtype: nvfp4\n shape: M=1024 N=2*2048 K=7168 (gate-up MLP)\n metric: latency_us\n value: 18.5\n utilization: compute-bound\n source_id: contest-gpumode-p3"}, "after": {"statement": "performance_claims: []\n\n| 256 | 4096 | 7168 | 1 | 4.708 |\n| 512 | 4096 | 7168 | 1 | 8.714 |\n| 256 | 3072 | 4096 | 1 | 2.125 |\n| 512 | 3072 | 7168 | 1 | 6.535 |\n\nRanking uses the geometric mean of the four benchmark times. The task explicitly labels the final column a speed-of-light analysis based on the maximum of B200 FP4 Tensor Core math time and DRAM-memory time at a 1.5 GHz clock. These values are theoretical comparison bounds, not measured contestant results. The former `M=1024, N=4096, K=7168, 18.5 µs` record is not one of the published workloads and has been removed."}, "reason": {"statement": "Remove the fabricated measurement and retain only the clearly labeled theoretical task table.", "urls": []}} +{"path": "wiki/kernels/gated-dual-gemm.md", "before": {"statement": "```cuda\ntemplate \n__global__ void gated_dual_gemm_nvfp4(\n const nvfp4_t* __restrict__ X, // [M, K] input\n const nvfp4_t* __restrict__ W_gate, // [N, K] gate weights\n const nvfp4_t* __restrict__ W_up, // [N, K] up weights\n const fp8_t* sf_x, const fp8_t* sf_gate, const fp8_t* sf_up,\n half* __restrict__ output, // [M, N] output\n int M, int N, int K\n) {\n // Two TMEM regions: one accumulator per GEMM\n uint32_t tmem_gate = tmem_alloc(256);\n uint32_t tmem_up = tmem_alloc(256);\n\n for (int k = 0; k < K; k += BLOCK_K) {\n int stage = (k / BLOCK_K) % NUM_STAGES;\n mbarrier_wait(&tma_done[stage]);\n\n // Two MMAs per K-tile: gate and up\n // Both read same X tile, different weight tiles\n tcgen05_mma(x_smem[stage], wg_smem[stage], tmem_gate);\n tcgen05_mma(x_smem[stage], wu_smem[stage], tmem_up);\n }\n\n // Fused epilogue: SiLU(gate) * up\n float g = tmem_load(tmem_gate);\n float u = tmem_load(tmem_up);\n float s = g / (1.0f + expf(-g)); // SiLU\n output[row * N + col] = __float2half(s * u);\n\n tmem_dealloc(tmem_gate, 256);\n tmem_dealloc(tmem_up, 256);\n}\n```\n\n2. **TMEM dual accumulator**: Blackwell's 512-column TMEM fits two 256-col accumulators side-by-side"}, "after": {"statement": "The official NVIDIA rules identify NVFP4 Gated Dual GEMM as Kernel Challenge 3 of the Blackwell NVFP4 Hackathon, open from December 20, 2025 through January 16, 2026. The public GPU Mode problem at challenge-opening commit `c5b2f7c` targets NVIDIA B200.\n\nThe shared `a` and `sfa` inputs create an opportunity to reuse data across the two products, and a genuinely fused epilogue can avoid writing both full-precision products to global memory. Those are optimization possibilities, not task guarantees.\n\nThe public task/reference does not establish a final leaderboard, winning source, single-launch decomposition, physical load count, TMEM accumulator partition, TMA pipeline, CUTLASS schedule, or compute-/memory-bound classification. If an implementation uses `tcgen05`, TMEM, or TMA, its exact descriptors, scale layouts, synchronization, allocation, and architecture requirements must be verified from that implementation and the version-matched ISA.\n\nCompatibility is correspondingly narrower than “any dual-output operation”: a model/backend must match the two same-shaped NVFP4 products, scale storage and layouts, first-branch SiLU, FP16 output, batching, and divisibility rules. Grouped per-expert MoE execution is a different contract unless an implementation explicitly supplies that grouping layer."}, "reason": {"statement": "Scope hardware metadata to B200/SM100a and avoid unmeasured Hopper claims.", "urls": ["https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://github.com/gpu-mode/reference-kernels/blob/c5b2f7c062d5015f29c3a1043cfd04954397944c/problems/nvidia/nvfp4_dual_gemm/task.yml"]}} +{"path": "wiki/kernels/gated-dual-gemm.md", "before": {"statement": "sources:\n- contest-gpumode-p3\n- blog-deepgemm\n- blog-tflops-gap-fp4-moe\n- pr-vllm-23696"}, "after": {"statement": "sources:\n- contest-gpumode-p3"}, "reason": {"statement": "Keep the direct source graph claim-scoped and disclose any preserved adjacent artifact separately.", "urls": []}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "Grouped GEMM computes multiple matrix multiplications with variable M dimensions but shared N and K, directly targeting MoE (Mixture of Experts) inference where each expert processes a different number of tokens. This is the most practically important kernel pattern for MoE serving: during inference, the router sends different token counts to each expert, and grouped GEMM batches all expert computations into a single kernel launch."}, "after": {"statement": "The official NVIDIA rules identify NVFP4 Grouped GEMM as Kernel Challenge 4 of the Blackwell NVFP4 Hackathon, open from January 17 through February 13, 2026. It carries 40% of the four-problem grand-prize score. The corrected public task at commit `ae67948` targets NVIDIA B200.\n\n“Grouped GEMM” does not imply one universal shape contract. Two relevant interfaces differ materially:\n\n- The GPU Mode challenge accepts a list of independent problems; `M_i`, `N_i`, and `K_i` can all differ by group.\n- DeepGEMM's M-grouped MoE APIs vary M while holding N and K fixed. It separately provides a K-grouped interface for MoE weight backward.\n\nNeither interface definition proves that a conforming implementation uses exactly one GPU launch.\n\nThe following shapes describe the pinned FP8/FP4 grouped APIs; scale tensors and layout conversions are additional required inputs.\n\n| M-grouped contiguous | A `[M,K]`, B `[G,N,K]`, D `[M,N]` | `grouped_layout` is either one expert ID per packed row (with `-1` padding) or one prefix-sum end per group | Training forward or inference prefill; N/K fixed and expert segments M-block aligned |\n| M-grouped masked | A `[G,Mmax,K]`, B `[G,N,K]`, D `[G,Mmax,N]` | `masked_m` is one int32 valid-row count per group | CUDA-graph decode; fixed allocation while computing valid portions |\n| K-grouped contiguous | packed A `[sum(K_i),M]`, B `[sum(K_i),N]`, D `[G,M,N]` | host and device K-size lists; optional C has `[G,M,N]` | MoE weight backward; M/N fixed |\n\nThese are concrete library contracts, not generic C++ structs. Compatibility also depends on the documented architecture, dtype/scale format, operand-major mode, alignment, output dtype, and recipe constraints."}, "reason": {"statement": "Distinguish general independent-shape grouping from DeepGEMM's narrower M-grouped MoE API and avoid launch/perceived-importance claims.", "urls": ["https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/tests/generators.py"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "```\nStandard GEMM: C = A @ B (single problem)\nGrouped GEMM: C_i = A_i @ B_i for i in [0, num_groups)\n\nMoE specialization:\n - N and K are FIXED (same expert architecture)\n - Only M varies (different token counts per expert)\n - B_i may be different weight matrices (per-expert weights)\n\nExample (DeepSeek-V3, 256 experts, top-8 routing):\n Group 0: M=47 tokens -> Expert 0 weights [N, K]\n Group 1: M=23 tokens -> Expert 1 weights [N, K]\n ...\n Group 255: M=31 tokens -> Expert 255 weights [N, K]\n```"}, "after": {"statement": "For each group `i`, the correctness reference computes `C_i = A_i @ B_i.T` with block scales and FP16 output.\n\n| `a_i` | packed NVFP4 E2M1, two values per byte | `[M_i,K_i/2,L_i]` |\n| `b_i` | packed NVFP4 E2M1, two values per byte | `[N_i,K_i/2,L_i]` |\n| `c_i` | FP16 | `[M_i,N_i,L_i]` |\n| `sfa_i` | FP8 E4M3FNUZ in task/template | `[M_i,K_i/16,L_i]` |\n| `sfb_i` | FP8 E4M3FNUZ in task/template | `[N_i,K_i/16,L_i]` |\n| problem size | integers | `(M_i,N_i,K_i,L_i)` |\n\nThe submission object actually contains four lists: logical A/B/C tensors, logical scales, reordered scale copies, and problem sizes. The `task.yml` prose lists only three tuple members, but `task.py`, `template.py`, and `reference.py` expose the reordered scales as the fourth. Each published case has `L=1`; `K_i` is divisible by 256, and `M_i`/`N_i` must satisfy the selected MMA tile divisibility.\n\nThe pinned upstream files also disagree on the scale dtype suffix: task/template text says E4M3FNUZ, while `reference.py` constructs `torch.float8_e4m3fn`. A submission must follow the actual tensors it receives rather than silently treating those names as interchangeable. The correctness checker uses `rtol=1e-3` and `atol=1e-3`.\n\nThe following shapes describe the pinned FP8/FP4 grouped APIs; scale tensors and layout conversions are additional required inputs.\n\n| M-grouped contiguous | A `[M,K]`, B `[G,N,K]`, D `[M,N]` | `grouped_layout` is either one expert ID per packed row (with `-1` padding) or one prefix-sum end per group | Training forward or inference prefill; N/K fixed and expert segments M-block aligned |\n| M-grouped masked | A `[G,Mmax,K]`, B `[G,N,K]`, D `[G,Mmax,N]` | `masked_m` is one int32 valid-row count per group | CUDA-graph decode; fixed allocation while computing valid portions |\n| K-grouped contiguous | packed A `[sum(K_i),M]`, B `[sum(K_i),N]`, D `[G,M,N]` | host and device K-size lists; optional C has `[G,M,N]` | MoE weight backward; M/N fixed |\n\nThese are concrete library contracts, not generic C++ structs. Compatibility also depends on the documented architecture, dtype/scale format, operand-major mode, alignment, output dtype, and recipe constraints."}, "reason": {"statement": "Replace the fabricated example with the exact tensor/list contract and separately describe DeepGEMM M-grouping.", "urls": ["https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/template.py", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/reference.py", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/tests/generators.py"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "```cpp\n// Layout 1: Contiguous (prefill)\n// All expert inputs packed sequentially with cumulative offset array\n// Memory: [Expert0 (M0 rows)] [Expert1 (M1 rows)] [Expert2 (M2 rows)]...\n// Index: offsets[0]=0 offsets[1]=M0 offsets[2]=M0+M1\nstruct ContiguousLayout {\n const fp8_t* A; // Packed input [sum(M_i), K]\n const fp8_t* B; // Expert weights [num_experts, N, K]\n float* C; // Packed output [sum(M_i), N]\n const int* offsets; // Cumulative M offsets [num_experts + 1]\n};\n\n// Layout 2: Masked (decode with CUDA graphs)\n// Fixed allocation per expert, binary mask for valid tokens\n// Compatible with CUDA graph capture (static shapes)\nstruct MaskedLayout {\n const fp8_t* A; // [num_experts, M_max, K]\n const fp8_t* B; // [num_experts, N, K]\n float* C; // [num_experts, M_max, N]\n const bool* mask; // [num_experts, M_max] validity flags\n};\n\n// Layout 3: K-grouped (weight gradients in training backward)\n// Groups along K-axis instead of M-axis\nstruct KGroupedLayout {\n const fp8_t* A; // [M, sum(K_i)]\n const fp8_t* B; // Per-group B matrices with different K\n float* C; // [M, N]\n const int* k_offsets; // Cumulative K offsets\n};\n```"}, "after": {"statement": "The following shapes describe the pinned FP8/FP4 grouped APIs; scale tensors and layout conversions are additional required inputs.\n\n| M-grouped contiguous | A `[M,K]`, B `[G,N,K]`, D `[M,N]` | `grouped_layout` is either one expert ID per packed row (with `-1` padding) or one prefix-sum end per group | Training forward or inference prefill; N/K fixed and expert segments M-block aligned |\n| M-grouped masked | A `[G,Mmax,K]`, B `[G,N,K]`, D `[G,Mmax,N]` | `masked_m` is one int32 valid-row count per group | CUDA-graph decode; fixed allocation while computing valid portions |\n| K-grouped contiguous | packed A `[sum(K_i),M]`, B `[sum(K_i),N]`, D `[G,M,N]` | host and device K-size lists; optional C has `[G,M,N]` | MoE weight backward; M/N fixed |\n\nThese are concrete library contracts, not generic C++ structs. Compatibility also depends on the documented architecture, dtype/scale format, operand-major mode, alignment, output dtype, and recipe constraints."}, "reason": {"statement": "Use a table matching the actual pinned APIs instead of invented structs.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/tests/generators.py"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "```cpp\n// CUTLASS schedule for grouped GEMM on Blackwell\nusing Schedule = cutlass::gemm::KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100;\n\n// PtrArray mode: array of pointers to per-group A, B, C matrices\n// TMA handles variable-offset loads via per-group descriptors\n// CLC distributes tiles across groups dynamically\n\nusing GemmKernel = cutlass::gemm::kernel::GemmGrouped<\n cutlass::gemm::GemmShape<128, 256, 128>, // Tile shape\n cutlass::arch::Sm100,\n cutlass::float_e2m1_t, // NVFP4 operand type\n cutlass::float_e2m1_t,\n float,\n cutlass::layout::RowMajor,\n cutlass::layout::ColumnMajor\n>;\n\n// Launch: single kernel handles all groups\nGemmKernel::Arguments args{\n num_groups,\n problem_sizes, // [num_groups] array of {M_i, N, K}\n ptr_A, ptr_B, ptr_C,\n scale_factors_A, scale_factors_B\n};\nGemmKernel kernel;\nkernel.run(args, stream);\n```"}, "after": {"statement": "The public challenge constrains outputs, tolerances, workloads, and scoring. It does not require CUTLASS, CLC, TMA, TMEM, a persistent kernel, a static schedule, or one launch. The former CUTLASS and CUDA sketches were removed because they were not executable instances of the named APIs.\n\nCUTLASS documents that small M or N can leave threads outside the useful problem bounds, and that a small M/N grid with large K can launch too few threadblocks to use every multiprocessor. This is a possible shape effect, not proof that every grouped workload has the same bottleneck. GPU Mode's postmortem, for example, measured substantial fixed setup cost in its studied implementation.\n\nCLC itself uses an asynchronous cancellation request, shared response, mbarrier completion, and response decoding after a worker's initial block. That is different from a global `atomicAdd` tile queue. Whether CLC improves end-to-end time relative to a static or software-persistent scheduler requires a workload- and implementation-specific measurement.\n\nTMA does not have one universal 128-byte alignment rule from which minimum tile sizes follow. CUDA 13.2.1's tiled tensor-map API generally documents 16-byte global-address and stride alignment, a 64-byte descriptor, and feature-specific 32-byte constraints. An implementation must check the exact descriptor mode and version it uses."}, "reason": {"statement": "Remove noncompiling pseudocode rather than substitute another untested optimized kernel.", "urls": ["https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/gemm/kernel/gemm_grouped.h", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/media/docs/cpp/efficient_gemm.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "```cpp\n// Precompute tile-to-expert mapping on host before launch\nstruct TileInfo {\n int expert_id;\n int tile_m_start; // Local M offset within this expert\n int tile_n_start;\n};\n\nstd::vector build_tile_schedule(\n const int* M_per_expert, int num_experts, int N\n) {\n std::vector schedule;\n for (int e = 0; e < num_experts; e++) {\n for (int m = 0; m < M_per_expert[e]; m += BLOCK_M)\n for (int n = 0; n < N; n += BLOCK_N)\n schedule.push_back({e, m, n});\n }\n return schedule; // Copy to device; blockIdx.x indexes into this\n}\n```"}, "after": {"statement": "The official NVIDIA rules identify NVFP4 Grouped GEMM as Kernel Challenge 4 of the Blackwell NVFP4 Hackathon, open from January 17 through February 13, 2026. It carries 40% of the four-problem grand-prize score. The corrected public task at commit `ae67948` targets NVIDIA B200.\n\n“Grouped GEMM” does not imply one universal shape contract. Two relevant interfaces differ materially:\n\n- The GPU Mode challenge accepts a list of independent problems; `M_i`, `N_i`, and `K_i` can all differ by group.\n- DeepGEMM's M-grouped MoE APIs vary M while holding N and K fixed. It separately provides a K-grouped interface for MoE weight backward.\n\nNeither interface definition proves that a conforming implementation uses exactly one GPU launch.\n\nThe public challenge constrains outputs, tolerances, workloads, and scoring. It does not require CUTLASS, CLC, TMA, TMEM, a persistent kernel, a static schedule, or one launch. The former CUTLASS and CUDA sketches were removed because they were not executable instances of the named APIs.\n\nCUTLASS documents that small M or N can leave threads outside the useful problem bounds, and that a small M/N grid with large K can launch too few threadblocks to use every multiprocessor. This is a possible shape effect, not proof that every grouped workload has the same bottleneck. GPU Mode's postmortem, for example, measured substantial fixed setup cost in its studied implementation.\n\nCLC itself uses an asynchronous cancellation request, shared response, mbarrier completion, and response decoding after a worker's initial block. That is different from a global `atomicAdd` tile queue. Whether CLC improves end-to-end time relative to a static or software-persistent scheduler requires a workload- and implementation-specific measurement.\n\nTMA does not have one universal 128-byte alignment rule from which minimum tile sizes follow. CUDA 13.2.1's tiled tensor-map API generally documents 16-byte global-address and stride alignment, a 64-byte descriptor, and feature-specific 32-byte constraints. An implementation must check the exact descriptor mode and version it uses."}, "reason": {"statement": "Remove the incomplete derived implementation and retain only source-backed contract boundaries.", "urls": ["https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/gemm/kernel/gemm_grouped.h", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/media/docs/cpp/efficient_gemm.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "```cpp\n// Persistent kernel with atomic tile counter\n// Each thread block loops, grabbing tiles until all are processed\n__device__ int g_tile_counter = 0;\n\n__global__ void grouped_gemm_persistent(\n const fp8_t** A_ptrs, const fp8_t** B_ptrs, float** C_ptrs,\n const int* M_per_expert, int N, int K,\n const TileInfo* tile_map, int total_tiles\n) {\n while (true) {\n int tile_id = atomicAdd(&g_tile_counter, 1);\n if (tile_id >= total_tiles) return;\n\n TileInfo info = tile_map[tile_id];\n int M_e = M_per_expert[info.expert_id];\n\n // Effective BLOCK_M may be smaller for the last tile of an expert\n int eff_m = min(BLOCK_M, M_e - info.tile_m_start);\n\n // TMA load + tcgen05.mma for this tile\n tma_load(A_ptrs[info.expert_id] + info.tile_m_start * K, ...);\n tma_load(B_ptrs[info.expert_id] + info.tile_n_start, ...);\n tcgen05_mma(...);\n\n // Store result\n store_tile(C_ptrs[info.expert_id] + info.tile_m_start * N\n + info.tile_n_start, eff_m, BLOCK_N);\n }\n}\n```"}, "after": {"statement": "The public challenge constrains outputs, tolerances, workloads, and scoring. It does not require CUTLASS, CLC, TMA, TMEM, a persistent kernel, a static schedule, or one launch. The former CUTLASS and CUDA sketches were removed because they were not executable instances of the named APIs.\n\nCUTLASS documents that small M or N can leave threads outside the useful problem bounds, and that a small M/N grid with large K can launch too few threadblocks to use every multiprocessor. This is a possible shape effect, not proof that every grouped workload has the same bottleneck. GPU Mode's postmortem, for example, measured substantial fixed setup cost in its studied implementation.\n\nCLC itself uses an asynchronous cancellation request, shared response, mbarrier completion, and response decoding after a worker's initial block. That is different from a global `atomicAdd` tile queue. Whether CLC improves end-to-end time relative to a static or software-persistent scheduler requires a workload- and implementation-specific measurement.\n\nTMA does not have one universal 128-byte alignment rule from which minimum tile sizes follow. CUDA 13.2.1's tiled tensor-map API generally documents 16-byte global-address and stride alignment, a 64-byte descriptor, and feature-specific 32-byte constraints. An implementation must check the exact descriptor mode and version it uses."}, "reason": {"statement": "Remove the mislabeled non-kernel rather than imply an untested launch is authoritative.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/gemm/kernel/gemm_grouped.h", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/media/docs/cpp/efficient_gemm.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "This reported 11.191us (~2us ahead of second place). It led to improvements in the FlashInfer-Bench evaluation methodology for the MLSys 2026 contest."}, "after": {"statement": "GPU Mode's official postmortem records a submission that temporarily reached the number-one leaderboard position with a reported `11.191 µs`, roughly `2 µs` ahead of the next entry, and was scrubbed minutes after the competition.\n\nDuring correctness, it ran a real padded 8-group kernel on each of 15 cloned data objects. During timing, the first call launched one merged 120-group kernel covering all 15 objects; calls 2 through 15 returned cached output pointers. The harness then divided the combined timing by 15. The reported number is evidence about the exploit, not a valid per-call performance record.\n\nThe official post points to `gpu-mode/reference-kernels` PR #104 as the harness response. It does not attribute a FlashInfer-Bench or MLSys 2026 methodology change to this incident."}, "reason": {"statement": "Preserve the verified reported number while replacing the unsupported consequence with the documented PR #104 response.", "urls": ["https://www.gpumode.com/news/reward-hacking-nvfp4"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "- Any workload with multiple GEMMs sharing N and K but varying M"}, "after": {"statement": "The official NVIDIA rules identify NVFP4 Grouped GEMM as Kernel Challenge 4 of the Blackwell NVFP4 Hackathon, open from January 17 through February 13, 2026. It carries 40% of the four-problem grand-prize score. The corrected public task at commit `ae67948` targets NVIDIA B200.\n\n“Grouped GEMM” does not imply one universal shape contract. Two relevant interfaces differ materially:\n\n- The GPU Mode challenge accepts a list of independent problems; `M_i`, `N_i`, and `K_i` can all differ by group.\n- DeepGEMM's M-grouped MoE APIs vary M while holding N and K fixed. It separately provides a K-grouped interface for MoE weight backward.\n\nNeither interface definition proves that a conforming implementation uses exactly one GPU launch.\n\nThe following shapes describe the pinned FP8/FP4 grouped APIs; scale tensors and layout conversions are additional required inputs.\n\n| M-grouped contiguous | A `[M,K]`, B `[G,N,K]`, D `[M,N]` | `grouped_layout` is either one expert ID per packed row (with `-1` padding) or one prefix-sum end per group | Training forward or inference prefill; N/K fixed and expert segments M-block aligned |\n| M-grouped masked | A `[G,Mmax,K]`, B `[G,N,K]`, D `[G,Mmax,N]` | `masked_m` is one int32 valid-row count per group | CUDA-graph decode; fixed allocation while computing valid portions |\n| K-grouped contiguous | packed A `[sum(K_i),M]`, B `[sum(K_i),N]`, D `[G,M,N]` | host and device K-size lists; optional C has `[G,M,N]` | MoE weight backward; M/N fixed |\n\nThese are concrete library contracts, not generic C++ structs. Compatibility also depends on the documented architecture, dtype/scale format, operand-major mode, alignment, output dtype, and recipe constraints."}, "reason": {"statement": "Replace universal advice with contract-specific selection criteria.", "urls": ["https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/tests/generators.py"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "- Expert load imbalance is the primary practical bottleneck (see [tail-effect](../patterns/tail-effect.md))"}, "after": {"statement": "| 8 | 80, 176, 128, 72, 64, 248, 96, 160 | 4096 | 7168 | 1 | 18.833 |\n| 8 | 40, 76, 168, 72, 164, 148, 196, 160 | 7168 | 2048 | 1 | 10.667 |\n| 2 | 192, 320 | 3072 | 4096 | 1 | 2.406 |\n| 2 | 128, 384 | 4096 | 1536 | 1 | 1.525 |\n\nRanking uses the geometric mean. The task labels these microsecond values a speed-of-light analysis derived from the maximum of B200 FP4 Tensor Core math time and DRAM-memory time at a 1.5 GHz clock. They are theoretical comparison values, not measured contestant results.\n\nThe public challenge constrains outputs, tolerances, workloads, and scoring. It does not require CUTLASS, CLC, TMA, TMEM, a persistent kernel, a static schedule, or one launch. The former CUTLASS and CUDA sketches were removed because they were not executable instances of the named APIs.\n\nCUTLASS documents that small M or N can leave threads outside the useful problem bounds, and that a small M/N grid with large K can launch too few threadblocks to use every multiprocessor. This is a possible shape effect, not proof that every grouped workload has the same bottleneck. GPU Mode's postmortem, for example, measured substantial fixed setup cost in its studied implementation.\n\nCLC itself uses an asynchronous cancellation request, shared response, mbarrier completion, and response decoding after a worker's initial block. That is different from a global `atomicAdd` tile queue. Whether CLC improves end-to-end time relative to a static or software-persistent scheduler requires a workload- and implementation-specific measurement.\n\nTMA does not have one universal 128-byte alignment rule from which minimum tile sizes follow. CUDA 13.2.1's tiled tensor-map API generally documents 16-byte global-address and stride alignment, a 64-byte descriptor, and feature-specific 32-byte constraints. An implementation must check the exact descriptor mode and version it uses."}, "reason": {"statement": "State measured contest-specific setup/underfill observations and avoid a universal bottleneck hierarchy.", "urls": ["https://www.gpumode.com/news/reward-hacking-nvfp4", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/gemm/kernel/gemm_grouped.h", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/media/docs/cpp/efficient_gemm.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "- Masked layout wastes compute on padding when M distribution is skewed"}, "after": {"statement": "The following shapes describe the pinned FP8/FP4 grouped APIs; scale tensors and layout conversions are additional required inputs.\n\n| M-grouped contiguous | A `[M,K]`, B `[G,N,K]`, D `[M,N]` | `grouped_layout` is either one expert ID per packed row (with `-1` padding) or one prefix-sum end per group | Training forward or inference prefill; N/K fixed and expert segments M-block aligned |\n| M-grouped masked | A `[G,Mmax,K]`, B `[G,N,K]`, D `[G,Mmax,N]` | `masked_m` is one int32 valid-row count per group | CUDA-graph decode; fixed allocation while computing valid portions |\n| K-grouped contiguous | packed A `[sum(K_i),M]`, B `[sum(K_i),N]`, D `[G,M,N]` | host and device K-size lists; optional C has `[G,M,N]` | MoE weight backward; M/N fixed |\n\nThese are concrete library contracts, not generic C++ structs. Compatibility also depends on the documented architecture, dtype/scale format, operand-major mode, alignment, output dtype, and recipe constraints."}, "reason": {"statement": "Separate fixed allocation from valid computation and describe masked_m accurately.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/tests/generators.py"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "- TMA alignment (128 bytes) constrains minimum tile dimensions"}, "after": {"statement": "The public challenge constrains outputs, tolerances, workloads, and scoring. It does not require CUTLASS, CLC, TMA, TMEM, a persistent kernel, a static schedule, or one launch. The former CUTLASS and CUDA sketches were removed because they were not executable instances of the named APIs.\n\nCUTLASS documents that small M or N can leave threads outside the useful problem bounds, and that a small M/N grid with large K can launch too few threadblocks to use every multiprocessor. This is a possible shape effect, not proof that every grouped workload has the same bottleneck. GPU Mode's postmortem, for example, measured substantial fixed setup cost in its studied implementation.\n\nCLC itself uses an asynchronous cancellation request, shared response, mbarrier completion, and response decoding after a worker's initial block. That is different from a global `atomicAdd` tile queue. Whether CLC improves end-to-end time relative to a static or software-persistent scheduler requires a workload- and implementation-specific measurement.\n\nTMA does not have one universal 128-byte alignment rule from which minimum tile sizes follow. CUDA 13.2.1's tiled tensor-map API generally documents 16-byte global-address and stride alignment, a 64-byte descriptor, and feature-specific 32-byte constraints. An implementation must check the exact descriptor mode and version it uses."}, "reason": {"statement": "Replace the blanket rule with versioned API constraints and direct readers to their exact descriptor/feature.", "urls": ["https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/gemm/kernel/gemm_grouped.h", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/media/docs/cpp/efficient_gemm.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "performance_claims:\n - gpu: B200\n dtype: nvfp4\n shape: \"variable M, shared N=K, 15 groups\"\n metric: latency_us\n value: 11.2\n utilization: \"compute-bound\"\n source_id: contest-gpumode-p4"}, "after": {"statement": "performance_claims: []\n\n| 8 | 80, 176, 128, 72, 64, 248, 96, 160 | 4096 | 7168 | 1 | 18.833 |\n| 8 | 40, 76, 168, 72, 164, 148, 196, 160 | 7168 | 2048 | 1 | 10.667 |\n| 2 | 192, 320 | 3072 | 4096 | 1 | 2.406 |\n| 2 | 128, 384 | 4096 | 1536 | 1 | 1.525 |\n\nRanking uses the geometric mean. The task labels these microsecond values a speed-of-light analysis derived from the maximum of B200 FP4 Tensor Core math time and DRAM-memory time at a 1.5 GHz clock. They are theoretical comparison values, not measured contestant results.\n\nGPU Mode's official postmortem records a submission that temporarily reached the number-one leaderboard position with a reported `11.191 µs`, roughly `2 µs` ahead of the next entry, and was scrubbed minutes after the competition.\n\nDuring correctness, it ran a real padded 8-group kernel on each of 15 cloned data objects. During timing, the first call launched one merged 120-group kernel covering all 15 objects; calls 2 through 15 returned cached output pointers. The harness then divided the combined timing by 15. The reported number is evidence about the exploit, not a valid per-call performance record.\n\nThe official post points to `gpu-mode/reference-kernels` PR #104 as the harness response. It does not attribute a FlashInfer-Bench or MLSys 2026 methodology change to this incident."}, "reason": {"statement": "Remove invalid structured performance metadata and retain only labeled theoretical task estimates in prose.", "urls": ["https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://www.gpumode.com/news/reward-hacking-nvfp4"]}} +{"path": "wiki/kernels/grouped-gemm.md", "before": {"statement": "sources: [contest-gpumode-p4, blog-deepgemm, doc-cutlass-blackwell]"}, "after": {"statement": "sources:\n- contest-gpumode-p4\n- blog-deepgemm\n- blog-gpu-mode-reward-hack"}, "reason": {"statement": "Remove doc-cutlass-blackwell from direct frontmatter evidence and add blog-gpu-mode-reward-hack; retain precise CUTLASS links only where used.", "urls": ["https://www.gpumode.com/news/reward-hacking-nvfp4", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_group_gemm/task.yml", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/gemm/kernel/gemm_grouped.h", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/media/docs/cpp/efficient_gemm.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "NSA achieves 9x forward speedup and 6x backward speedup at 64K sequences versus FlashAttention-2, and 11.6x decoding speedup at 64K context. It is deployed in DeepSeek-V3.2-Exp combined with FlashMLA sparse kernels."}, "after": {"statement": "DeepSeek-V3.2-Exp later introduced **DeepSeek Sparse Attention (DSA)**. Its pinned first-party inference code uses a learned indexer to select up to 2,048 token positions and masks attention to those positions. Its README points to DeepGEMM for indexer-logit kernels and FlashMLA for sparse-attention kernels. FlashMLA likewise says its sparse kernels power DSA.\n\nThat deployed DSA path is related sparse-attention work, but it is not evidence that the ACL paper's gated compression/selection/window NSA architecture was deployed in V3.2-Exp."}, "reason": {"statement": "Separate the ACL NSA paper from the later DSA deployment and retain FlashMLA only as evidence for that distinction.", "urls": []}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "```\nInput Query Q\n |\n +---> [Compression Path] Learned MLP creates coarse-grained KV\n | | representations (token compression)\n | v\n | S_compressed = Q @ K_compressed^T\n |\n +---> [Selection Path] Blockwise importance scores select\n | | top-n fine-grained token blocks\n | v\n | S_selected = Q @ K_selected^T (sparse)\n |\n +---> [Sliding Window] Local context window (w=512)\n |\n v\n S_local = Q @ K_local^T (banded)\n\nOutput = Combine(softmax(S_compressed) @ V_compressed,\n softmax(S_selected) @ V_selected,\n softmax(S_local) @ V_local)\n```"}, "after": {"statement": "For token representation \\(h_t\\), NSA computes three attention outputs and combines them with learned, input-dependent gates:\n\n\\[\no_t = g_t^{cmp} o_t^{cmp} + g_t^{slc} o_t^{slc} + g_t^{win} o_t^{win},\n\\qquad\ng_t^c = \\operatorname{sigmoid}(\\operatorname{MLP}_c(h_t)).\n\\]\n\n| Compression | Learned MLPs with intra-block position encoding compress overlapping KV blocks into coarse-grained representations. |\n| Selection | Compression-attention scores are reused and aggregated into fine-grained block-importance scores; top-n blocks are selected and attended at full token resolution. |\n| Sliding window | Recent tokens are attended directly to preserve local context. |\n\nThe main experimental configuration uses compression block length 32 and stride 16, selected block length 64 with 16 selected blocks, and a 512-token sliding window. These are experiment settings, not universal NSA constants.\n\nThis CPU function checks only the learned gated-sum semantics above. It is KernelWiki-derived, uses ordinary numbers, and makes no claim about the paper's GPU layout or performance.\n\n```python\ndef gated_branch_sum(branch_outputs, gates):\n \"\"\"Combine equal-width branch vectors with one [0, 1] gate per branch.\"\"\"\n if len(branch_outputs) != len(gates) or not branch_outputs:\n raise ValueError(\"one gate is required for each non-empty branch set\")\n width = len(branch_outputs[0])\n if any(len(branch) != width for branch in branch_outputs):\n raise ValueError(\"branch widths must match\")\n if any(not 0.0 <= gate <= 1.0 for gate in gates):\n raise ValueError(\"sigmoid gates must lie in [0, 1]\")\n return [\n sum(gate * branch[i] for branch, gate in zip(branch_outputs, gates))\n for i in range(width)\n ]\n\n\nassert gated_branch_sum([[1.0, 2.0], [10.0, 20.0], [-2.0, 4.0]],\n [0.5, 0.25, 1.0]) == [1.0, 10.0]\n```\n\nRemoving the gates is a useful negative control: the raw branch sum for the same vectors is `[9.0, 26.0]`, not `[1.0, 10.0]`.\n\nThe paper does not publish the former page's kernel listing, specify a grid exactly as `(query_block, head, batch)`, or claim that such a grid eliminates dynamic scheduling overhead. The removed listings were non-executable and mathematically incorrect: the selected-attention sketch omitted within-block softmax normalization, and the sliding-window sketch stepped by a block size while loading only one token."}, "reason": {"statement": "Replace the ambiguous diagram with the paper's gated branch equation and exact branch roles.", "urls": ["https://aclanthology.org/2025.acl-long.1126.pdf"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "```python\nimport triton\nimport triton.language as tl\n\n@triton.jit\ndef nsa_sparse_attention_fwd(\n Q_ptr, K_ptr, V_ptr, O_ptr,\n block_indices_ptr, # Selected block indices per query\n num_selected: tl.constexpr,\n BLOCK_SIZE: tl.constexpr,\n HEAD_DIM: tl.constexpr,\n NUM_HEADS: tl.constexpr,\n GROUP_SIZE: tl.constexpr, # GQA group size\n):\n \"\"\"\n Sparse attention forward: only compute attention over selected KV blocks.\n Group-centric loading: shares sparse KV blocks across all query heads\n in a GQA group, minimizing redundant KV transfers.\n \"\"\"\n pid = tl.program_id(0)\n head_id = tl.program_id(1)\n batch_id = tl.program_id(2)\n\n # GQA: determine which KV head group this query head belongs to\n kv_head_id = head_id // GROUP_SIZE\n\n # Load query tile\n q_offset = batch_id * NUM_HEADS * HEAD_DIM + head_id * HEAD_DIM\n q = tl.load(Q_ptr + q_offset + tl.arange(0, HEAD_DIM))\n\n # Accumulator for online softmax\n acc = tl.zeros([HEAD_DIM], dtype=tl.float32)\n lse = float(\"-inf\")\n\n # Iterate over selected blocks (sparse)\n for block_idx in range(num_selected):\n # Load block index for this query\n sel_offset = (batch_id * NUM_HEADS + kv_head_id) * num_selected + block_idx\n kv_block_start = tl.load(block_indices_ptr + sel_offset) * BLOCK_SIZE\n\n # Group-centric: load KV block once, shared across GROUP_SIZE query heads\n k_offsets = kv_block_start + tl.arange(0, BLOCK_SIZE)\n k_block = tl.load(K_ptr + (batch_id * kv_head_id * SEQ_LEN + k_offsets[:, None]) * HEAD_DIM\n + tl.arange(0, HEAD_DIM)[None, :])\n v_block = tl.load(V_ptr + (batch_id * kv_head_id * SEQ_LEN + k_offsets[:, None]) * HEAD_DIM\n + tl.arange(0, HEAD_DIM)[None, :])\n\n # Compute attention scores for this block\n scores = tl.sum(q[None, :] * k_block, axis=1) # [BLOCK_SIZE]\n\n # Online softmax update\n block_max = tl.max(scores)\n new_lse = tl.where(lse > block_max,\n lse + tl.log(1.0 + tl.exp(block_max - lse)),\n block_max + tl.log(1.0 + tl.exp(lse - block_max)))\n\n # Rescale accumulator and add new contribution\n old_scale = tl.exp(lse - new_lse)\n new_scale = tl.exp(scores - new_lse)\n acc = acc * old_scale + tl.sum(new_scale[:, None] * v_block, axis=0)\n lse = new_lse\n\n # Store output\n o_offset = batch_id * NUM_HEADS * HEAD_DIM + head_id * HEAD_DIM\n tl.store(O_ptr + o_offset + tl.arange(0, HEAD_DIM), acc)\n```"}, "after": {"statement": "This CPU function checks only the learned gated-sum semantics above. It is KernelWiki-derived, uses ordinary numbers, and makes no claim about the paper's GPU layout or performance.\n\n```python\ndef gated_branch_sum(branch_outputs, gates):\n \"\"\"Combine equal-width branch vectors with one [0, 1] gate per branch.\"\"\"\n if len(branch_outputs) != len(gates) or not branch_outputs:\n raise ValueError(\"one gate is required for each non-empty branch set\")\n width = len(branch_outputs[0])\n if any(len(branch) != width for branch in branch_outputs):\n raise ValueError(\"branch widths must match\")\n if any(not 0.0 <= gate <= 1.0 for gate in gates):\n raise ValueError(\"sigmoid gates must lie in [0, 1]\")\n return [\n sum(gate * branch[i] for branch, gate in zip(branch_outputs, gates))\n for i in range(width)\n ]\n\n\nassert gated_branch_sum([[1.0, 2.0], [10.0, 20.0], [-2.0, 4.0]],\n [0.5, 0.25, 1.0]) == [1.0, 10.0]\n```\n\nRemoving the gates is a useful negative control: the raw branch sum for the same vectors is `[9.0, 26.0]`, not `[1.0, 10.0]`.\n\nThe authors say compression and sliding-window attention can use existing FlashAttention-2-style kernels, while selected attention needs a specialized Triton kernel for training and prefill. Its source-described structure is:\n\n1. Load all query heads in one GQA/MQA group into SRAM so they share selected sparse KV indices.\n2. Load selected KV data as contiguous blocks rather than scattered individual tokens.\n3. Put the nearly constant query and output loops in Triton grid parallelism; keep the selected-block loop inside a program because its count is approximately constant.\n\nThe paper does not publish the former page's kernel listing, specify a grid exactly as `(query_block, head, batch)`, or claim that such a grid eliminates dynamic scheduling overhead. The removed listings were non-executable and mathematically incorrect: the selected-attention sketch omitted within-block softmax normalization, and the sliding-window sketch stepped by a block size while loading only one token."}, "reason": {"statement": "Remove a mathematically incorrect and non-executable kernel sketch rather than imply it is paper code.", "urls": ["https://aclanthology.org/2025.acl-long.1126.pdf"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "```python\n@triton.jit\ndef nsa_sliding_window_fwd(\n Q_ptr, K_ptr, V_ptr, O_ptr,\n seq_pos,\n WINDOW_SIZE: tl.constexpr, # 512\n HEAD_DIM: tl.constexpr,\n):\n \"\"\"Local sliding window attention for recent context.\"\"\"\n pid = tl.program_id(0) # query position\n\n # Window bounds\n window_start = tl.maximum(0, seq_pos - WINDOW_SIZE)\n window_end = seq_pos\n\n # Standard dense attention within window\n # This is O(w*d) per query, where w=512\n q = tl.load(Q_ptr + pid * HEAD_DIM + tl.arange(0, HEAD_DIM))\n acc = tl.zeros([HEAD_DIM], dtype=tl.float32)\n lse = float(\"-inf\")\n\n for pos in range(window_start, window_end, BLOCK_SIZE):\n k = tl.load(K_ptr + pos * HEAD_DIM + tl.arange(0, HEAD_DIM))\n v = tl.load(V_ptr + pos * HEAD_DIM + tl.arange(0, HEAD_DIM))\n score = tl.sum(q * k)\n # Online softmax accumulation\n new_lse = tl.where(lse > score,\n lse + tl.log(1 + tl.exp(score - lse)),\n score + tl.log(1 + tl.exp(lse - score)))\n acc = acc * tl.exp(lse - new_lse) + v * tl.exp(score - new_lse)\n lse = new_lse\n\n tl.store(O_ptr + pid * HEAD_DIM + tl.arange(0, HEAD_DIM), acc)\n```"}, "after": {"statement": "For token representation \\(h_t\\), NSA computes three attention outputs and combines them with learned, input-dependent gates:\n\n\\[\no_t = g_t^{cmp} o_t^{cmp} + g_t^{slc} o_t^{slc} + g_t^{win} o_t^{win},\n\\qquad\ng_t^c = \\operatorname{sigmoid}(\\operatorname{MLP}_c(h_t)).\n\\]\n\n| Compression | Learned MLPs with intra-block position encoding compress overlapping KV blocks into coarse-grained representations. |\n| Selection | Compression-attention scores are reused and aggregated into fine-grained block-importance scores; top-n blocks are selected and attended at full token resolution. |\n| Sliding window | Recent tokens are attended directly to preserve local context. |\n\nThe main experimental configuration uses compression block length 32 and stride 16, selected block length 64 with 16 selected blocks, and a 512-token sliding window. These are experiment settings, not universal NSA constants.\n\nThis CPU function checks only the learned gated-sum semantics above. It is KernelWiki-derived, uses ordinary numbers, and makes no claim about the paper's GPU layout or performance.\n\n```python\ndef gated_branch_sum(branch_outputs, gates):\n \"\"\"Combine equal-width branch vectors with one [0, 1] gate per branch.\"\"\"\n if len(branch_outputs) != len(gates) or not branch_outputs:\n raise ValueError(\"one gate is required for each non-empty branch set\")\n width = len(branch_outputs[0])\n if any(len(branch) != width for branch in branch_outputs):\n raise ValueError(\"branch widths must match\")\n if any(not 0.0 <= gate <= 1.0 for gate in gates):\n raise ValueError(\"sigmoid gates must lie in [0, 1]\")\n return [\n sum(gate * branch[i] for branch, gate in zip(branch_outputs, gates))\n for i in range(width)\n ]\n\n\nassert gated_branch_sum([[1.0, 2.0], [10.0, 20.0], [-2.0, 4.0]],\n [0.5, 0.25, 1.0]) == [1.0, 10.0]\n```\n\nRemoving the gates is a useful negative control: the raw branch sum for the same vectors is `[9.0, 26.0]`, not `[1.0, 10.0]`.\n\nThe paper does not publish the former page's kernel listing, specify a grid exactly as `(query_block, head, batch)`, or claim that such a grid eliminates dynamic scheduling overhead. The removed listings were non-executable and mathematically incorrect: the selected-attention sketch omitted within-block softmax normalization, and the sliding-window sketch stepped by a block size while loading only one token."}, "reason": {"statement": "Remove the incomplete sketch and describe the branch from the paper instead.", "urls": ["https://aclanthology.org/2025.acl-long.1126.pdf"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "3. **Grid-based scheduling**: Triton grid dimensions map directly to (query_block, head, batch), avoiding dynamic scheduling overhead"}, "after": {"statement": "The authors say compression and sliding-window attention can use existing FlashAttention-2-style kernels, while selected attention needs a specialized Triton kernel for training and prefill. Its source-described structure is:\n\n1. Load all query heads in one GQA/MQA group into SRAM so they share selected sparse KV indices.\n2. Load selected KV data as contiguous blocks rather than scattered individual tokens.\n3. Put the nearly constant query and output loops in Triton grid parallelism; keep the selected-block loop inside a program because its count is approximately constant.\n\nThe paper does not publish the former page's kernel listing, specify a grid exactly as `(query_block, head, batch)`, or claim that such a grid eliminates dynamic scheduling overhead. The removed listings were non-executable and mathematically incorrect: the selected-attention sketch omitted within-block softmax normalization, and the sliding-window sketch stepped by a block size while loading only one token."}, "reason": {"statement": "Retain the exact outer-loop/grid observation without inventing grid axes or an overhead result.", "urls": ["https://aclanthology.org/2025.acl-long.1126.pdf"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "performance_claims:\n - gpu: H100\n dtype: bf16\n shape: \"seqlen=65536\"\n metric: speedup\n value: 9.0\n utilization: \"vs FlashAttention-2 forward\"\n source_id: blog-nsa\n\nAll speedups measured against FlashAttention-2 on H100 with BF16 precision."}, "after": {"statement": "performance_claims: []\n\n| Training/prefill forward | 9.0x versus the authors' Triton FlashAttention-2 baseline; Figure 5 timing result |\n| Training/prefill backward | 6.0x versus the same baseline; Figure 5 timing result |\n| Decoding | 11.6x **expected** speedup from Table 4's memory-access volumes: 65,536 full-attention tokens versus 5,632 NSA-equivalent tokens |\n\nThe setup states eight A100 GPUs, GQA group count 4, 16 query heads per group, key dimension 192, and value dimension 128. The paper does not provide the benchmark dtype, software versions, batch details, raw samples, or variance. Consequently these values are retained only as explicitly labeled author reports, and `performance_claims` remains empty rather than encoding a falsely reproducible tuple."}, "reason": {"statement": "Remove invalid structured performance metadata and retain source-reported values in prose with exact scope and missing reproducibility fields.", "urls": ["https://aclanthology.org/2025.acl-long.1126.pdf"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "- Long-context inference (32K+ tokens) where full attention is prohibitively expensive"}, "after": {"statement": "- NSA requires a model trained for its compression, selection, window, and gate mechanism; do not treat it as a drop-in sparse mask for an arbitrary checkpoint.\n- GQA/MQA lets query heads in a group share selected blocks, matching the paper's group-centric kernel design.\n- The paper evaluates long contexts through 64K but defines no universal 32K threshold. Compare quality, sequence distribution, memory use, and measured latency or throughput on the target workload.\n- CUDA Graphs can reduce repeated-launch CPU overhead, but they are not an NSA-specific default. Profile first: NVIDIA's guidance says the largest gains occur for CPU-bound workflows and that GPU-bound workloads may see little benefit or regress.\n- The compression MLP adds learned parameters and computation. The paper does not isolate a standalone cost for that component.\n- The paper notes that a Triton implementation can retain abstraction overhead relative to native CUDA; it does not publish an NSA-specific CPU-launch profile."}, "reason": {"statement": "Replace the universal cutoff with a workload- and quality-dependent selection boundary.", "urls": ["https://aclanthology.org/2025.acl-long.1126.pdf", "https://docs.nvidia.com/dl-cuda-graph/troubleshooting/performance-issues.html"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "- Token selection adds a two-pass overhead (score all blocks, then select top-n)"}, "after": {"statement": "For token representation \\(h_t\\), NSA computes three attention outputs and combines them with learned, input-dependent gates:\n\n\\[\no_t = g_t^{cmp} o_t^{cmp} + g_t^{slc} o_t^{slc} + g_t^{win} o_t^{win},\n\\qquad\ng_t^c = \\operatorname{sigmoid}(\\operatorname{MLP}_c(h_t)).\n\\]\n\n| Compression | Learned MLPs with intra-block position encoding compress overlapping KV blocks into coarse-grained representations. |\n| Selection | Compression-attention scores are reused and aggregated into fine-grained block-importance scores; top-n blocks are selected and attended at full token resolution. |\n| Sliding window | Recent tokens are attended directly to preserve local context. |\n\nThe main experimental configuration uses compression block length 32 and stride 16, selected block length 64 with 16 selected blocks, and a 512-token sliding window. These are experiment settings, not universal NSA constants."}, "reason": {"statement": "Describe score reuse and top-n selection without inventing an extra pass.", "urls": ["https://aclanthology.org/2025.acl-long.1126.pdf"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "- Triton implementation has CPU launch overhead impacting small-batch decode; CUDA graph mode recommended"}, "after": {"statement": "- NSA requires a model trained for its compression, selection, window, and gate mechanism; do not treat it as a drop-in sparse mask for an arbitrary checkpoint.\n- GQA/MQA lets query heads in a group share selected blocks, matching the paper's group-centric kernel design.\n- The paper evaluates long contexts through 64K but defines no universal 32K threshold. Compare quality, sequence distribution, memory use, and measured latency or throughput on the target workload.\n- CUDA Graphs can reduce repeated-launch CPU overhead, but they are not an NSA-specific default. Profile first: NVIDIA's guidance says the largest gains occur for CPU-bound workflows and that GPU-bound workloads may see little benefit or regress.\n- The compression MLP adds learned parameters and computation. The paper does not isolate a standalone cost for that component.\n- The paper notes that a Triton implementation can retain abstraction overhead relative to native CUDA; it does not publish an NSA-specific CPU-launch profile."}, "reason": {"statement": "Replace the categorical prescription with a profile-first CUDA Graph boundary.", "urls": ["https://aclanthology.org/2025.acl-long.1126.pdf", "https://docs.nvidia.com/dl-cuda-graph/troubleshooting/performance-issues.html"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "The core NSA kernel is implemented in Triton with group-centric data loading and grid-based scheduling.\n\nNSA's sparsity pattern is explicitly designed for GPU memory access efficiency:"}, "after": {"statement": "Native Sparse Attention is the three-branch, natively trainable sparse-attention design published in the ACL 2025 proceedings. The paper targets long-context training and inference and reports quality comparable to or better than full attention on its evaluated tasks. Those are paper-scoped results, not a guarantee for an arbitrary model or post-training conversion.\n\nThe paper's efficiency experiments use an eight-GPU A100 system. The paper does not establish Hopper or Blackwell compatibility for its Triton implementation.\n\nDeepSeek-V3.2-Exp later introduced **DeepSeek Sparse Attention (DSA)**. Its pinned first-party inference code uses a learned indexer to select up to 2,048 token positions and masks attention to those positions. Its README points to DeepGEMM for indexer-logit kernels and FlashMLA for sparse-attention kernels. FlashMLA likewise says its sparse kernels power DSA.\n\nThat deployed DSA path is related sparse-attention work, but it is not evidence that the ACL paper's gated compression/selection/window NSA architecture was deployed in V3.2-Exp."}, "reason": {"statement": "Scope architecture metadata to the paper's A100 evidence and make Blackwell an unmeasured portability question.", "urls": ["https://aclanthology.org/2025.acl-long.1126.pdf", "https://github.com/deepseek-ai/FlashMLA/blob/71c737929f2567bd0a094ae140f8f60f390b1232/README.md", "https://aclanthology.org/2025.acl-long.1126/"]}} +{"path": "wiki/kernels/nsa.md", "before": {"statement": "sources: [blog-nsa, blog-flashmla, blog-vllm-deepseek-v3-sparse]"}, "after": {"statement": "sources: [blog-nsa, blog-flashmla]"}, "reason": {"statement": "Remove the vLLM community source from direct frontmatter evidence and retain FlashMLA only for the explicit non-equivalence boundary.", "urls": ["https://github.com/deepseek-ai/DeepSeek-V3.2-Exp/tree/87e509a2e5a100d221c97df52c6e8be7835f0057", "https://github.com/deepseek-ai/FlashMLA/blob/71c737929f2567bd0a094ae140f8f60f390b1232/README.md"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "NVFP4 GEMM is a compute-bound matrix multiplication kernel operating on NVIDIA's native 4-bit floating-point format (E2M1) with block scaling on Blackwell GPUs. Unlike the memory-bound GEMV, GEMM is dominated by tensor core throughput and benefits from Blackwell's native FP4 MMA instructions via tcgen05.mma, TMA bulk loads, TMEM accumulation, and warp specialization."}, "after": {"statement": "The official NVIDIA rules identify NVFP4 GEMM as Kernel Challenge 2 of the Blackwell NVFP4 Hackathon. The contest ran from November 29 through December 19, 2025; Problem 2 targeted NVIDIA B200 and contributed 20% of the four-problem grand-prize score.\n\nThe pinned public task defines observable inputs, correctness, test shapes, benchmark shapes, and ranking. It does not publish a canonical optimized kernel, require CUTLASS, or establish which implementation mechanisms any entrant used. “NVFP4 GEMM” also does not determine a bottleneck by itself: shape, layout, staging, launch geometry, and epilogue can change whether math, memory traffic, occupancy, or launch overhead controls runtime.\n\nUse this task contract only when the packed E2M1 payloads, logical and reordered scales, transpose convention, FP16 output, tolerances, and B200 target match the workload. “Four-bit weights” alone is insufficient: INT4, MXFP4, other scale granularities, and other layouts are not interchangeable with this ABI.\n\nThe documented native tensor-core path is Blackwell-specific; Hopper has no native FP4 tensor-core instruction. This does not exclude software conversion or emulation. Choose TMA, TMEM allocation, CUTLASS schedules, warp specialization, tile sizes, and stage counts only after validating their exact API constraints and profiling the actual shapes."}, "reason": {"statement": "Scope bottlenecks and implementation mechanisms to the exact shape and implementation.", "urls": ["https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.yml", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/template.py", "https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://developer.nvidia.com/blog/introducing-nvfp4-for-efficient-and-accurate-low-precision-inference/", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "This kernel was Problem 2 of the GPU Mode NVFP4 Hackathon (Nov-Dec 2025), targeting B200 GPUs. Top entries achieved within 1% of cuBLAS performance using CUTLASS SM100 schedules."}, "after": {"statement": "The task ranks the geometric mean across three benchmark cases. It labels the following values a speed-of-light analysis based on the maximum of B200 FP4 Tensor Core math time and DRAM-memory time at a 1.5 GHz clock:\n\n| 128 | 7168 | 16384 | 1 | 8.994 |\n| 128 | 4096 | 7168 | 1 | 2.354 |\n| 128 | 7168 | 2048 | 1 | 1.333 |\n\nThese are theoretical comparison rows, not measured contestant latencies and not cuBLAS results.\n\nThe public Popcorn endpoint currently gives the following dated snapshot. To make its small floating-point `submission_score` values readable beside the task's microsecond presentation, the table shows `submission_score × 10^6`; it does not relabel the rows as prize placements.\n\n| 1 | `gau.nernst` | 9.981889 | 2025-12-21 00:43:03 |\n| 2 | `s.am._` | 10.060110 | 2025-12-20 17:45:21 |\n| 3 | `billcarson` | 10.137411 | 2025-12-21 03:05:32 |\n| 8 | `Simon` | 10.806750 | 2025-12-16 20:18:42 |\n| 9 | `yue` | 10.914084 | 2025-12-11 04:36:45 |\n| 10 | `currybab` | 10.930623 | 2025-12-19 08:10:18 |\n\nSnapshot fetched August 8, 2026. Because the current first three submissions postdate the official December 19 cutoff, this endpoint alone cannot establish winners or final prize rankings. It also publishes no contestant source, CUTLASS attribution, cuBLAS comparison, raw trials, or variance."}, "reason": {"statement": "Remove an untraceable performance and implementation attribution; retain only dated public fields and theoretical task rows.", "urls": ["https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemm/NVIDIA?limit=12", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.yml", "https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "The kernel uses the `KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100` CUTLASS schedule, which combines TMA async loads with warp-specialized MMA execution."}, "after": {"statement": "The native Blackwell instruction path supports block-of-16 NVFP4 through `tcgen05.mma...kind::mxf4nvf4.block_scale.block16`. It uses UE4M3 scale elements, which CUTLASS names `float_ue4m3_t`; UE8M0 is the MXFP4 scale type. Converting NVFP4 scales to UE8M0 would discard fractional scale values and is not a required NVFP4 preprocessing step.\n\nCUTLASS defines `KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100`, but its direct official example is a grouped pointer-array kernel. The symbol's existence is not evidence that the contest entrants used it. CUTLASS's current official NVFP4 examples use `nv_float4_t`, collective mainloop and epilogue builders, `kernel::GemmUniversal`, and `device::GemmUniversalAdapter`; an old scalar-template `device::GemmUniversal` sketch is not interchangeable with that API.\n\nTMA likewise has no universal 128-byte alignment rule for every operand. CUDA 13.2.1 generally requires a 16-byte-aligned global base and 16-byte-multiple strides for a tiled tensor map, with additional datatype-, interleave-, swizzle-, and mode-specific restrictions. Problem 2's `K % 256 == 0` rule belongs to the task ABI; it does not follow as a universal TMA theorem.\n\nTMEM's 128-lane by 512-column organization is a storage and addressing model, not a universal 128-by-512 logical output-tile limit. Official CUTLASS NVFP4 configurations include a cooperative two-SM MMA tile with logical shape 256 by 256 by 256."}, "reason": {"statement": "Retain the schedule only as an adjacent official CUTLASS example and explicitly deny contestant attribution.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/float_subbyte.h#L494-L512", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "```cpp\n// CUTLASS dispatch for NVFP4 GEMM on Blackwell\nusing Schedule = cutlass::gemm::KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100;\n\n// Tile configuration\nusing TileShape = cute::Shape<_128, _256, _128>; // M, N, K tile\nusing ClusterShape = cute::Shape<_1, _1, _1>; // 1-SM mode\n\n// Element types\nusing ElementA = cutlass::float_e2m1_t; // NVFP4\nusing ElementB = cutlass::float_e2m1_t; // NVFP4\nusing ElementC = float; // FP32 accumulator\nusing ElementScale = cutlass::float_e4m3_t; // FP8 E4M3 block scales\n\n// Kernel definition\nusing Kernel = cutlass::gemm::device::GemmUniversal<\n ElementA, cutlass::layout::RowMajor,\n ElementB, cutlass::layout::ColumnMajor,\n ElementC, cutlass::layout::RowMajor,\n float, // accumulator type\n cutlass::arch::OpClassTensorOp,\n cutlass::arch::Sm100,\n TileShape, ClusterShape, Schedule\n>;\n```"}, "after": {"statement": "The native Blackwell instruction path supports block-of-16 NVFP4 through `tcgen05.mma...kind::mxf4nvf4.block_scale.block16`. It uses UE4M3 scale elements, which CUTLASS names `float_ue4m3_t`; UE8M0 is the MXFP4 scale type. Converting NVFP4 scales to UE8M0 would discard fractional scale values and is not a required NVFP4 preprocessing step.\n\nCUTLASS defines `KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100`, but its direct official example is a grouped pointer-array kernel. The symbol's existence is not evidence that the contest entrants used it. CUTLASS's current official NVFP4 examples use `nv_float4_t`, collective mainloop and epilogue builders, `kernel::GemmUniversal`, and `device::GemmUniversalAdapter`; an old scalar-template `device::GemmUniversal` sketch is not interchangeable with that API.\n\nTMA likewise has no universal 128-byte alignment rule for every operand. CUDA 13.2.1 generally requires a 16-byte-aligned global base and 16-byte-multiple strides for a tiled tensor map, with additional datatype-, interleave-, swizzle-, and mode-specific restrictions. Problem 2's `K % 256 == 0` rule belongs to the task ABI; it does not follow as a universal TMA theorem.\n\nTMEM's 128-lane by 512-column organization is a storage and addressing model, not a universal 128-by-512 logical output-tile limit. Official CUTLASS NVFP4 configurations include a cooperative two-SM MMA tile with logical shape 256 by 256 by 256.\n\n- [Official contest rules](https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf)\n- [Pinned task definition](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.yml)\n- [Pinned task types](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.py)\n- [Pinned starter template](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/template.py)\n- [Pinned correctness reference](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/reference.py)\n- [Public Popcorn leaderboard API](https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemm/NVIDIA?limit=12)\n- [Transformer Engine 2.13 NVFP4 recipe](https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html)\n- [cuBLAS block-scaling formats](https://docs.nvidia.com/cuda/cublas/index.html#element-1d-block-scaling-for-fp8-and-fp4-data-types)\n- [PTX ISA 9.0 block-scaled `tcgen05.mma`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma)\n- [Pinned CUTLASS NVFP4 example](https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu)\n- [Pinned CUTLASS grouped NVFP4 example](https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu)\n- [CUDA 13.2.1 tensor-map constraints](https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html)\n\nQuery via:"}, "reason": {"statement": "Remove non-compiling pseudo-CUTLASS and link to the immutable official example instead.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/float_subbyte.h#L494-L512", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "```cpp\n// Warp specialization: TMA producer + MMA consumer + epilogue\n// Shared memory holds pipelined A/B tiles + scale factors\n\nconstexpr int NUM_STAGES = 4; // Pipeline depth\n\n// Shared memory layout\nstruct SharedStorage {\n // Double-buffered across NUM_STAGES\n nvfp4_t A_smem[NUM_STAGES][BLOCK_M * BLOCK_K / 2]; // Packed FP4: 2 per byte\n nvfp4_t B_smem[NUM_STAGES][BLOCK_N * BLOCK_K / 2];\n fp8_t sfa_smem[NUM_STAGES][BLOCK_M * (BLOCK_K / 16)]; // 1 scale per 16 elements\n fp8_t sfb_smem[NUM_STAGES][BLOCK_N * (BLOCK_K / 16)];\n uint64_t mbarrier[NUM_STAGES];\n};\n\n__global__ void nvfp4_gemm_kernel(\n const nvfp4_t* A, const nvfp4_t* B,\n const fp8_t* sfa, const fp8_t* sfb,\n float sf_a_global, float sf_b_global,\n float* C, int M, int N, int K\n) {\n extern __shared__ SharedStorage smem[];\n int warp_id = threadIdx.x / 32;\n int lane_id = threadIdx.x % 32;\n\n if (warp_id == 0 && lane_id == 0) {\n // TMA producer warp: async bulk loads\n for (int k = 0; k < K; k += BLOCK_K) {\n int stage = (k / BLOCK_K) % NUM_STAGES;\n\n // TMA descriptor-based bulk load (128-byte aligned)\n asm volatile(\n \"cp.async.bulk.tensor.2d.shared::cluster.global.tile\"\n \".mbarrier::complete_tx::bytes\"\n \" [%0], [%1, {%2, %3}], [%4];\"\n :: \"r\"((uint32_t)&smem->A_smem[stage]),\n \"l\"(tma_desc_A),\n \"r\"(tile_m), \"r\"(k),\n \"r\"((uint32_t)&smem->mbarrier[stage])\n );\n // Similarly for B, sfa, sfb\n }\n } else if (warp_id == 1 && lane_id == 0) {\n // MMA consumer warp: tcgen05.mma\n uint32_t tmem_addr = tmem_alloc_cta(256); // 256 TMEM columns\n\n for (int k = 0; k < K; k += BLOCK_K) {\n int stage = (k / BLOCK_K) % NUM_STAGES;\n // Wait for TMA to complete this stage\n mbarrier_wait(&smem->mbarrier[stage]);\n\n // tcgen05.mma with native block scaling\n // Reads A/B from SMEM, accumulates into TMEM\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f8f6f4\"\n \" [%0], %1, %2, %3, %4;\"\n :: \"r\"(tmem_addr),\n \"l\"((uint64_t)&smem->A_smem[stage]),\n \"l\"((uint64_t)&smem->B_smem[stage]),\n \"r\"(packed_scales),\n \"n\"(1) // scale_D enabled\n );\n }\n\n // Signal epilogue warps\n } else {\n // Epilogue warps: read from TMEM, apply global scales, store to C\n // tmem -> registers -> global\n }\n}\n```"}, "after": {"statement": "The native Blackwell instruction path supports block-of-16 NVFP4 through `tcgen05.mma...kind::mxf4nvf4.block_scale.block16`. It uses UE4M3 scale elements, which CUTLASS names `float_ue4m3_t`; UE8M0 is the MXFP4 scale type. Converting NVFP4 scales to UE8M0 would discard fractional scale values and is not a required NVFP4 preprocessing step.\n\nCUTLASS defines `KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100`, but its direct official example is a grouped pointer-array kernel. The symbol's existence is not evidence that the contest entrants used it. CUTLASS's current official NVFP4 examples use `nv_float4_t`, collective mainloop and epilogue builders, `kernel::GemmUniversal`, and `device::GemmUniversalAdapter`; an old scalar-template `device::GemmUniversal` sketch is not interchangeable with that API.\n\nTMA likewise has no universal 128-byte alignment rule for every operand. CUDA 13.2.1 generally requires a 16-byte-aligned global base and 16-byte-multiple strides for a tiled tensor map, with additional datatype-, interleave-, swizzle-, and mode-specific restrictions. Problem 2's `K % 256 == 0` rule belongs to the task ABI; it does not follow as a universal TMA theorem.\n\nTMEM's 128-lane by 512-column organization is a storage and addressing model, not a universal 128-by-512 logical output-tile limit. Official CUTLASS NVFP4 configurations include a cooperative two-SM MMA tile with logical shape 256 by 256 by 256."}, "reason": {"statement": "Remove misleading non-executable CUDA rather than imply it is a reference implementation.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cute/arch/mma_sm100_umma.hpp#L1647-L1659", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/float_subbyte.h#L494-L512", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "All TMA operands require 128-byte alignment. For NVFP4 (2 elements per byte), this means K dimensions must be multiples of 256 elements:\n\n- TMA requires 128-byte alignment for all operands"}, "after": {"statement": "| `a` | packed E2M1, two values per byte | `[M,K/2,L]` |\n| `b` | packed E2M1, two values per byte | `[N,K/2,L]` |\n| `sfa` | logical E4M3 scales | `[M,K/16,L]` |\n| `sfb` | logical E4M3 scales | `[N,K/16,L]` |\n| `sfa_reordered` | MMA-oriented scale copy | `[32,4,ceil(M/128),4,K/64,L]` |\n| `sfb_reordered` | MMA-oriented scale copy | `[32,4,ceil(N/128),4,K/64,L]` |\n| `c` | preallocated FP16 output | `[M,N,L]` |\n\nFor each `L` slice, the correctness reference computes the block-scaled equivalent of `A @ B.T` and stores FP16 output. It uses `rtol=1e-3` and `atol=1e-3`.\n\nThe upstream files contain two interface inconsistencies that implementations must not conceal:\n\n- `task.yml` describes a five-member `(a,b,sfa,sfb,c)` tuple, while `task.py`, `template.py`, and `reference.py` expose the seven tensors above.\n- Task and template prose label scale tensors E4M3FNUZ, while `reference.py` constructs `torch.float8_e4m3fn` values. A submission must follow the tensors supplied by the actual harness rather than treating those suffixes as interchangeable.\n\nThe published task requires `K` divisible by 256. Divisibility of `M` and `N` depends on the submission's selected MMA tile. The following CPU-only helper reproduces the published storage shapes; it does not decode FP4, apply scales, or model a GPU kernel:\n\nThe native Blackwell instruction path supports block-of-16 NVFP4 through `tcgen05.mma...kind::mxf4nvf4.block_scale.block16`. It uses UE4M3 scale elements, which CUTLASS names `float_ue4m3_t`; UE8M0 is the MXFP4 scale type. Converting NVFP4 scales to UE8M0 would discard fractional scale values and is not a required NVFP4 preprocessing step.\n\nCUTLASS defines `KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100`, but its direct official example is a grouped pointer-array kernel. The symbol's existence is not evidence that the contest entrants used it. CUTLASS's current official NVFP4 examples use `nv_float4_t`, collective mainloop and epilogue builders, `kernel::GemmUniversal`, and `device::GemmUniversalAdapter`; an old scalar-template `device::GemmUniversal` sketch is not interchangeable with that API.\n\nTMA likewise has no universal 128-byte alignment rule for every operand. CUDA 13.2.1 generally requires a 16-byte-aligned global base and 16-byte-multiple strides for a tiled tensor map, with additional datatype-, interleave-, swizzle-, and mode-specific restrictions. Problem 2's `K % 256 == 0` rule belongs to the task ABI; it does not follow as a universal TMA theorem.\n\nTMEM's 128-lane by 512-column organization is a storage and addressing model, not a universal 128-by-512 logical output-tile limit. Official CUTLASS NVFP4 configurations include a cooperative two-SM MMA tile with logical shape 256 by 256 by 256."}, "reason": {"statement": "Separate the task's K divisibility rule from actual tensor-map constraints.", "urls": ["https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/float_subbyte.h#L494-L512", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "```cpp\n// Critical: pad tensors to 128-byte boundaries for TMA\n// NVFP4: 2 elements per byte, so 256 elements = 128 bytes\nstatic_assert(K % 256 == 0, \"K must align to 128 bytes for FP4 TMA\");\n\n// For scale factors: FP8 is 1 byte per element\n// 128 bytes = 128 scale values\n// Since 1 scale per 16 FP4 elements: 128 scales cover 2048 FP4 elements\nstatic_assert((K / 16) % 128 == 0, \"Scale array must align to 128 bytes\");\n```"}, "after": {"statement": "| `a` | packed E2M1, two values per byte | `[M,K/2,L]` |\n| `b` | packed E2M1, two values per byte | `[N,K/2,L]` |\n| `sfa` | logical E4M3 scales | `[M,K/16,L]` |\n| `sfb` | logical E4M3 scales | `[N,K/16,L]` |\n| `sfa_reordered` | MMA-oriented scale copy | `[32,4,ceil(M/128),4,K/64,L]` |\n| `sfb_reordered` | MMA-oriented scale copy | `[32,4,ceil(N/128),4,K/64,L]` |\n| `c` | preallocated FP16 output | `[M,N,L]` |\n\nFor each `L` slice, the correctness reference computes the block-scaled equivalent of `A @ B.T` and stores FP16 output. It uses `rtol=1e-3` and `atol=1e-3`.\n\nThe upstream files contain two interface inconsistencies that implementations must not conceal:\n\n- `task.yml` describes a five-member `(a,b,sfa,sfb,c)` tuple, while `task.py`, `template.py`, and `reference.py` expose the seven tensors above.\n- Task and template prose label scale tensors E4M3FNUZ, while `reference.py` constructs `torch.float8_e4m3fn` values. A submission must follow the tensors supplied by the actual harness rather than treating those suffixes as interchangeable.\n\nThe published task requires `K` divisible by 256. Divisibility of `M` and `N` depends on the submission's selected MMA tile. The following CPU-only helper reproduces the published storage shapes; it does not decode FP4, apply scales, or model a GPU kernel:\n\n```python\ndef task_storage_shapes(m, n, k, l=1):\n if min(m, n, k, l) <= 0:\n raise ValueError(\"dimensions must be positive\")\n if k % 256:\n raise ValueError(\"K must be divisible by 256\")\n\n return {\n \"a_packed\": (m, k // 2, l),\n \"b_packed\": (n, k // 2, l),\n \"sfa_logical\": (m, k // 16, l),\n \"sfb_logical\": (n, k // 16, l),\n \"sfa_reordered\": (32, 4, (m + 127) // 128, 4, (k + 63) // 64, l),\n \"sfb_reordered\": (32, 4, (n + 127) // 128, 4, (k + 63) // 64, l),\n \"c\": (m, n, l),\n }\n\n\nfor valid_k in (256, 512, 1536, 2048, 2304, 7168, 16384):\n task_storage_shapes(128, 256, valid_k)\n\nassert (256 // 16) % 128 != 0 # the former scale-array assertion was invalid\n```\n\nNine of the ten official correctness shapes fail the former `(K/16) % 128 == 0` assertion, including the smallest valid case with `K=256`."}, "reason": {"statement": "Replace the false assertion with a host-checkable representation of the published tensor shapes.", "urls": []}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "The tcgen05.mma instruction expects UE8M0 (unsigned power-of-two exponent only) scales, but NVFP4 uses FP8 E4M3 (non-power-of-two). Conversion is needed:\n\n```cpp\n// Convert FP8 E4M3 block scales to UE8M0 for tcgen05.mma hardware\n// E4M3: 4 exponent bits, 3 mantissa bits (non-power-of-two)\n// UE8M0: 8 exponent bits, 0 mantissa bits (power-of-two only)\n__device__ uint32_t pack_scales_ue8m0(\n fp8_e4m3_t s0, fp8_e4m3_t s1, fp8_e4m3_t s2, fp8_e4m3_t s3\n) {\n uint8_t u0 = fp8_e4m3_to_ue8m0(s0); // Round to nearest power-of-two\n uint8_t u1 = fp8_e4m3_to_ue8m0(s1);\n uint8_t u2 = fp8_e4m3_to_ue8m0(s2);\n uint8_t u3 = fp8_e4m3_to_ue8m0(s3);\n return (u3 << 24) | (u2 << 16) | (u1 << 8) | u0;\n}\n```\n\n- Scale factor conversion (E4M3 to UE8M0) adds overhead if not precomputed"}, "after": {"statement": "The generic one-dimensional NVFP4 recipe reconstructs each value from a signed E2M1 payload, one E4M3 local scale per 16 consecutive payloads, and a per-tensor FP32 global scale. E2M1 represents zero and signed magnitudes 0.5, 1, 1.5, 2, 3, 4, and 6, with two payloads packed per byte. MXFP4 is different: its local groups contain 32 payloads and use power-of-two UE8M0 scales.\n\nThe contest ABI is narrower and does not expose the generic recipe's FP32 global scales. Its actual generated input has seven tensors:\n\nThe native Blackwell instruction path supports block-of-16 NVFP4 through `tcgen05.mma...kind::mxf4nvf4.block_scale.block16`. It uses UE4M3 scale elements, which CUTLASS names `float_ue4m3_t`; UE8M0 is the MXFP4 scale type. Converting NVFP4 scales to UE8M0 would discard fractional scale values and is not a required NVFP4 preprocessing step.\n\nCUTLASS defines `KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100`, but its direct official example is a grouped pointer-array kernel. The symbol's existence is not evidence that the contest entrants used it. CUTLASS's current official NVFP4 examples use `nv_float4_t`, collective mainloop and epilogue builders, `kernel::GemmUniversal`, and `device::GemmUniversalAdapter`; an old scalar-template `device::GemmUniversal` sketch is not interchangeable with that API.\n\nTMA likewise has no universal 128-byte alignment rule for every operand. CUDA 13.2.1 generally requires a 16-byte-aligned global base and 16-byte-multiple strides for a tiled tensor map, with additional datatype-, interleave-, swizzle-, and mode-specific restrictions. Problem 2's `K % 256 == 0` rule belongs to the task ABI; it does not follow as a universal TMA theorem.\n\nTMEM's 128-lane by 512-column organization is a storage and addressing model, not a universal 128-by-512 logical output-tile limit. Official CUTLASS NVFP4 configurations include a cooperative two-SM MMA tile with logical shape 256 by 256 by 256."}, "reason": {"statement": "Remove a format-confusing conversion and document the exact UE4M3 scale path.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/float_subbyte.h#L494-L512", "https://docs.nvidia.com/cuda/cublas/index.html#element-1d-block-scaling-for-fp8-and-fp4-data-types", "https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/template.py", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "Problem 2 top performers (geometric mean across benchmark configs):\n\n| 1 | Simon | 10.807 |\n| 2 | yue | 10.914 |\n| 3 | currybab | 10.931 |"}, "after": {"statement": "The public Popcorn endpoint currently gives the following dated snapshot. To make its small floating-point `submission_score` values readable beside the task's microsecond presentation, the table shows `submission_score × 10^6`; it does not relabel the rows as prize placements.\n\n| 1 | `gau.nernst` | 9.981889 | 2025-12-21 00:43:03 |\n| 2 | `s.am._` | 10.060110 | 2025-12-20 17:45:21 |\n| 3 | `billcarson` | 10.137411 | 2025-12-21 03:05:32 |\n| 8 | `Simon` | 10.806750 | 2025-12-16 20:18:42 |\n| 9 | `yue` | 10.914084 | 2025-12-11 04:36:45 |\n| 10 | `currybab` | 10.930623 | 2025-12-19 08:10:18 |\n\nSnapshot fetched August 8, 2026. Because the current first three submissions postdate the official December 19 cutoff, this endpoint alone cannot establish winners or final prize rankings. It also publishes no contestant source, CUTLASS attribution, cuBLAS comparison, raw trials, or variance."}, "reason": {"statement": "Publish only a dated current snapshot and explicitly separate it from official prize placements.", "urls": ["https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemm/NVIDIA?limit=12", "https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "- Inference with 4-bit quantized weights on Blackwell"}, "after": {"statement": "Use this task contract only when the packed E2M1 payloads, logical and reordered scales, transpose convention, FP16 output, tolerances, and B200 target match the workload. “Four-bit weights” alone is insufficient: INT4, MXFP4, other scale granularities, and other layouts are not interchangeable with this ABI.\n\nThe documented native tensor-core path is Blackwell-specific; Hopper has no native FP4 tensor-core instruction. This does not exclude software conversion or emulation. Choose TMA, TMEM allocation, CUTLASS schedules, warp specialization, tile sizes, and stage counts only after validating their exact API constraints and profiling the actual shapes."}, "reason": {"statement": "Scope use to operands prepared for the exact NVFP4 ABI.", "urls": ["https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/template.py", "https://developer.nvidia.com/blog/introducing-nvfp4-for-efficient-and-accurate-low-precision-inference/", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "- TMEM size (128x512 per SM) limits maximum output tile to 128 rows x 512 cols (32-bit)"}, "after": {"statement": "The native Blackwell instruction path supports block-of-16 NVFP4 through `tcgen05.mma...kind::mxf4nvf4.block_scale.block16`. It uses UE4M3 scale elements, which CUTLASS names `float_ue4m3_t`; UE8M0 is the MXFP4 scale type. Converting NVFP4 scales to UE8M0 would discard fractional scale values and is not a required NVFP4 preprocessing step.\n\nCUTLASS defines `KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100`, but its direct official example is a grouped pointer-array kernel. The symbol's existence is not evidence that the contest entrants used it. CUTLASS's current official NVFP4 examples use `nv_float4_t`, collective mainloop and epilogue builders, `kernel::GemmUniversal`, and `device::GemmUniversalAdapter`; an old scalar-template `device::GemmUniversal` sketch is not interchangeable with that API.\n\nTMA likewise has no universal 128-byte alignment rule for every operand. CUDA 13.2.1 generally requires a 16-byte-aligned global base and 16-byte-multiple strides for a tiled tensor map, with additional datatype-, interleave-, swizzle-, and mode-specific restrictions. Problem 2's `K % 256 == 0` rule belongs to the task ABI; it does not follow as a universal TMA theorem.\n\nTMEM's 128-lane by 512-column organization is a storage and addressing model, not a universal 128-by-512 logical output-tile limit. Official CUTLASS NVFP4 configurations include a cooperative two-SM MMA tile with logical shape 256 by 256 by 256.\n\nUse this task contract only when the packed E2M1 payloads, logical and reordered scales, transpose convention, FP16 output, tolerances, and B200 target match the workload. “Four-bit weights” alone is insufficient: INT4, MXFP4, other scale granularities, and other layouts are not interchangeable with this ABI.\n\nThe documented native tensor-core path is Blackwell-specific; Hopper has no native FP4 tensor-core instruction. This does not exclude software conversion or emulation. Choose TMA, TMEM allocation, CUTLASS schedules, warp specialization, tile sizes, and stage counts only after validating their exact API constraints and profiling the actual shapes."}, "reason": {"statement": "Describe TMEM storage separately from implementation tile shapes.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu#L147-L159", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/float_subbyte.h#L494-L512", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/template.py", "https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://developer.nvidia.com/blog/introducing-nvfp4-for-efficient-and-accurate-low-precision-inference/"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "The reference bundle lives in [`artifacts/kernels/nvfp4-gemm/full/`](../../artifacts/kernels/nvfp4-gemm/full/) and combines the upstream PR-2139 diff (`PR-2139-blockwise-groupwise-gemm.patch`, `mode: upstream-patch`, SHA-pinned to `ca4fdbea` on NVIDIA/cutlass) with an extracted CUTLASS-schedule / TMA snippet from the `tflops-gap-fp4-moe` blog (`blackwell-cutlass-schedules-and-tma.cu`, `mode: extracted`). Labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live in [`artifacts/kernels/nvfp4-gemm/variants/`](../../artifacts/kernels/nvfp4-gemm/variants/). Every file's SHA-256 and upstream-pinning metadata is in `PROVENANCE.yaml` inside each bundle."}, "after": {"statement": "- [Official contest rules](https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf)\n- [Pinned task definition](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.yml)\n- [Pinned task types](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.py)\n- [Pinned starter template](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/template.py)\n- [Pinned correctness reference](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/reference.py)\n- [Public Popcorn leaderboard API](https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemm/NVIDIA?limit=12)\n- [Transformer Engine 2.13 NVFP4 recipe](https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html)\n- [cuBLAS block-scaling formats](https://docs.nvidia.com/cuda/cublas/index.html#element-1d-block-scaling-for-fp8-and-fp4-data-types)\n- [PTX ISA 9.0 block-scaled `tcgen05.mma`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma)\n- [Pinned CUTLASS NVFP4 example](https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu)\n- [Pinned CUTLASS grouped NVFP4 example](https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu)\n- [CUDA 13.2.1 tensor-map constraints](https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html)\n\nQuery via:"}, "reason": {"statement": "Detach the artifact_dir and remove the Full Reference Implementation section while preserving audit evidence and files.", "urls": []}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "performance_claims:\n- gpu: B200\n dtype: nvfp4\n shape: standard GEMM configs\n metric: latency_us\n value: 10.807\n utilization: near cuBLAS\n source_id: contest-gpumode-p2"}, "after": {"statement": "performance_claims: []\n\nThe task ranks the geometric mean across three benchmark cases. It labels the following values a speed-of-light analysis based on the maximum of B200 FP4 Tensor Core math time and DRAM-memory time at a 1.5 GHz clock:\n\n| 128 | 7168 | 16384 | 1 | 8.994 |\n| 128 | 4096 | 7168 | 1 | 2.354 |\n| 128 | 7168 | 2048 | 1 | 1.333 |\n\nThese are theoretical comparison rows, not measured contestant latencies and not cuBLAS results.\n\nThe public Popcorn endpoint currently gives the following dated snapshot. To make its small floating-point `submission_score` values readable beside the task's microsecond presentation, the table shows `submission_score × 10^6`; it does not relabel the rows as prize placements.\n\n| 1 | `gau.nernst` | 9.981889 | 2025-12-21 00:43:03 |\n| 2 | `s.am._` | 10.060110 | 2025-12-20 17:45:21 |\n| 3 | `billcarson` | 10.137411 | 2025-12-21 03:05:32 |\n| 8 | `Simon` | 10.806750 | 2025-12-16 20:18:42 |\n| 9 | `yue` | 10.914084 | 2025-12-11 04:36:45 |\n| 10 | `currybab` | 10.930623 | 2025-12-19 08:10:18 |\n\nSnapshot fetched August 8, 2026. Because the current first three submissions postdate the official December 19 cutoff, this endpoint alone cannot establish winners or final prize rankings. It also publishes no contestant source, CUTLASS attribution, cuBLAS comparison, raw trials, or variance."}, "reason": {"statement": "Remove malformed performance metadata and retain exact theoretical rows plus a dated leaderboard snapshot in prose.", "urls": ["https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemm/NVIDIA?limit=12", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.yml", "https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf"]}} +{"path": "wiki/kernels/nvfp4-gemm.md", "before": {"statement": "sources:\n- contest-gpumode-p2\n- doc-cutlass-blackwell\n- pr-cutlass-2139\n\nartifact_dir: artifacts/kernels/nvfp4-gemm"}, "after": {"statement": "sources:\n- contest-gpumode-p2\n- doc-transformer-engine-2.13-nvfp4\n- doc-ptx-isa-sm100\n- doc-cuda-13-0-2-tma"}, "reason": {"statement": "Use claim-directed task, format, PTX, and TMA source cards and detach the invalid bundle.", "urls": ["https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.yml", "https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/template.py", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/include/cutlass/float_subbyte.h#L494-L512", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu", "https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu", "https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/hardware/nvfp4.md", "before": {"statement": "sources: [doc-nvidia-tuning-guide, contest-gpumode-p1, contest-gpumode-p2, blog-yue-nvfp4]"}, "after": {"statement": "sources: [doc-transformer-engine-2.13-nvfp4, doc-ptx-isa-sm100]\n\nevidence_basis:\n - source_id: doc-transformer-engine-2.13-nvfp4\n evidence_type: official-doc\n - source_id: doc-ptx-isa-sm100\n evidence_type: official-doc"}, "reason": {"statement": "Remove the misleading evidence relationship while retaining the verified source-scoped hardware prose unchanged.", "urls": ["https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#alternate-floating-point-data-formats", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "NVFP4 Batched GEMV is a memory-bound kernel computing batched matrix-vector products with NVFP4 (E2M1) block-scaled inputs on B200 GPUs. Unlike compute-bound GEMM, GEMV is dominated by memory bandwidth utilization (each FP4 element is used only once in the dot product), making PTX-level memory access control, cache policy differentiation, and register budgeting the critical optimization levers."}, "after": {"statement": "GPU Mode's Problem 1 asks for a block-scaled NVFP4 batched matrix-vector product on NVIDIA B200. The official task models its three benchmark cases against the slower of FFMA math and DRAM transfer time and reports DRAM-limited theoretical times. That task-specific model does not make every GEMV implementation or shape bandwidth-bound.\n\nPTX ISA 9.0 defines the packed conversion and typed register decomposition used in Yue's author-reported decode path:\n\n```asm\ncvt.rn.f16x2.e2m1x2 %result, %packed_fp4_pair;\nmov.b32 {%b0, %b1, %b2, %b3}, %packed_word;\n```\n\nIt also defines vector loads such as `ld.global.v2.u64` and `ld.global.v4.u64`, which move 16 and 32 bytes and can carry 32 and 64 packed FP4 values. The ISA specifies behavior, not that one width or decomposition is universally faster."}, "reason": {"statement": "Scope bottleneck and optimization statements to the official task model and measured implementations.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "performance_claims:\n- gpu: B200\n dtype: nvfp4\n shape: M=7168, K=16384, L=1\n metric: latency_us\n value: 22.4\n utilization: ~2.6x of SOL (8.6us)\n source_id: contest-gpumode-p1\n\nThis was Problem 1 of the GPU Mode NVFP4 Hackathon (Nov 2025). The theoretical speed-of-light is ~8.6us for the largest config, limited by B200's 8 TB/s HBM3e bandwidth. Top performers achieved ~22.4us (2.6x off SOL), reflecting the overhead of FP4 decoding and scale factor application."}, "after": {"statement": "performance_claims: []\n\nGPU Mode's Problem 1 asks for a block-scaled NVFP4 batched matrix-vector product on NVIDIA B200. The official task models its three benchmark cases against the slower of FFMA math and DRAM transfer time and reports DRAM-limited theoretical times. That task-specific model does not make every GEMV implementation or shape bandwidth-bound.\n\nThe public leaderboard is mutable and reports aggregate scores rather than per-shape latencies. In the snapshot fetched on 2026-08-08, the first three rows were `s.am._` at 18.549562452 µs, `gau.nernst` at 18.552844757 µs, and `shellsmile15795` at 18.707609314 µs. Yue's 22.392217755 µs submission was rank 11. The official cutoff was November 28, 2025 at 11:59 p.m. PT; current ranks 2 and 3 have November 30 timestamps, so this endpoint is not an official prize-placement snapshot."}, "reason": {"statement": "Remove malformed per-shape metadata and publish a dated aggregate snapshot with cutoff caveat.", "urls": ["https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemv/NVIDIA?limit=100", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv/task.yml", "https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "```\nInputs:\n a: (M x K x L) NVFP4 packed matrix\n b: (1 x K x L) NVFP4 packed vector\n sfa: (M x K/16 x L) FP8 E4M3 scale factors for a\n sfb: (1 x K/16 x L) FP8 E4M3 scale factors for b\n sf_a_global, sf_b_global: FP32 per-tensor global scales\n\nOutput:\n c: (M x 1 x L) FP16\n\nComputation per element:\n c[m][l] = sum_k( sf_a_global * sfa[m][k/16][l] * deq(a[m][k][l])\n * sf_b_global * sfb[0][k/16][l] * deq(b[0][k][l]) )\n\nBenchmark configs:\n Config 1: M=7168, K=16384, L=1\n Config 2: M=4096, K=7168, L=8\n Config 3: M=7168, K=2048, L=4\n```"}, "after": {"statement": "The logical operation has one B row, reused by all M output rows. The reference harness pads B and its scales to 128 rows so it can call `torch._scaled_mm`, then retains only result column zero. Consequently, A values are row-specific while the logical B vector is reused across M; it is incorrect to say every FP4 input value is consumed only once.\n\nAt pinned commit `ae679486`, `custom_kernel` receives seven tensors, not five tensors plus global FP32 scale arguments:\n\n| `a` | `[M, K/2, L]` | Packed E2M1 A; two logical values per byte |\n| `b` | `[128, K/2, L]` | Packed E2M1 B, physically padded; logical row 0 is used |\n| `sfa` | `[M, K/16, L]` | Logical/reference A block scales |\n| `sfb` | `[128, K/16, L]` | Logical/reference B block scales, padded to 128 rows |\n| `sfa_reordered` | `[32, 4, ceil(M/128), 4, K/64, L]` | Swizzled A scales for custom kernels |\n| `sfb_reordered` | `[32, 4, 1, 4, K/64, L]` | Swizzled padded-B scales for custom kernels |\n| `c` | `[M, 1, L]` | FP16 output buffer |\n\n`K` must be divisible by 64, and M must be divisible by the implementation's selected M tile. The task prose labels scales `e4m3fnuz`, but the pinned generator constructs `torch.float8_e4m3fn`; implementations should follow the actual harness revision they are tested against. This contest ABI exposes no per-tensor FP32 global scales."}, "reason": {"statement": "Publish both the logical operation and actual seven-tensor callable without inventing inputs.", "urls": []}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "Raw PTX provides critical performance gains over C intrinsics for FP4 decoding and memory access:\n\n```asm\n; FP4 to FP16 conversion: hardware instruction\n; Converts two packed E2M1 values to a pair of FP16 values\ncvt.rn.f16x2.e2m1x2 %result, %fp4_packed;\n\n; Byte unpacking: PTX mov.b32 is faster than manual bitwise ops\n; Instead of: val = (packed >> (i*4)) & 0xF (multiple shifts + masks)\n; Use: direct byte decomposition\nmov.b32 {tmp0, tmp1, tmp2, tmp3}, %packed_word;\n\n; This eliminates the shift-mask chain entirely\n; Key insight: PTX byte unpacking leverages hardware byte decomposition\n```"}, "after": {"statement": "The official table assumes a 1.5 GHz B200 clock and ranks submissions by the geometric mean across all three rows:\n\n| 7168 | 16384 | 1 | 8.622 |\n| 4096 | 7168 | 8 | 17.275 |\n| 7168 | 2048 | 4 | 4.317 |\n\nNVIDIA's Blackwell technical brief specifies 8 TB/s of HBM3e bandwidth for one GB200 GPU. The task's theoretical numbers are model values, not measured kernel timings.\n\nThe public leaderboard is mutable and reports aggregate scores rather than per-shape latencies. In the snapshot fetched on 2026-08-08, the first three rows were `s.am._` at 18.549562452 µs, `gau.nernst` at 18.552844757 µs, and `shellsmile15795` at 18.707609314 µs. Yue's 22.392217755 µs submission was rank 11. The official cutoff was November 28, 2025 at 11:59 p.m. PT; current ranks 2 and 3 have November 30 timestamps, so this endpoint is not an official prize-placement snapshot."}, "reason": {"statement": "Retain exact instruction semantics and author-reported bundled progression without causal isolation.", "urls": ["https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv/task.yml", "https://resources.nvidia.com/en-us-blackwell-architecture/blackwell-architecture-technical-brief", "https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemv/NVIDIA?limit=100", "https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "Lower register counts force higher occupancy, which is critical for memory-bound kernels where latency hiding dominates:\n\n```cpp\n// Rank 1: aggressive register limit for maximum occupancy\n// nvcc -maxrregcount=32\n// Fewer registers -> more warps/SM -> better memory latency hiding\n\n// Rank 3: slightly relaxed for more ILP\n// nvcc -maxrregcount=45\n\n// Launch bounds to complement register budgeting\n__launch_bounds__(256, 4) // 256 threads/block, 4+ blocks per SM\n__global__ void nvfp4_gemv_kernel(...) {\n // ...\n}\n\n// The measurable difference between 32 and 45 registers shows\n// that occupancy is the dominant factor for memory-bound kernels\n```"}, "after": {"statement": "PTX ISA 9.0 defines the packed conversion and typed register decomposition used in Yue's author-reported decode path:\n\n```asm\ncvt.rn.f16x2.e2m1x2 %result, %packed_fp4_pair;\nmov.b32 {%b0, %b1, %b2, %b3}, %packed_word;\n```\n\nIt also defines vector loads such as `ld.global.v2.u64` and `ld.global.v4.u64`, which move 16 and 32 bytes and can carry 32 and 64 packed FP4 values. The ISA specifies behavior, not that one width or decomposition is universally faster."}, "reason": {"statement": "Make register caps a measure-and-verify tuning parameter.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "```cpp\n// Each K variant compiled separately with optimal configuration\ntemplate \n__global__ __launch_bounds__(THREADS, MIN_BLOCKS)\nvoid nvfp4_gemv_specialized(\n const uint8_t* __restrict__ a,\n const uint8_t* __restrict__ b,\n const uint8_t* __restrict__ sfa,\n const uint8_t* __restrict__ sfb,\n half* __restrict__ c,\n float sf_a_global, float sf_b_global,\n int M\n) {\n float acc = 0.0f;\n\n // Full unroll: compiler knows K_SIZE at compile time\n #pragma unroll\n for (int k = 0; k < K_SIZE / ELEMENTS_PER_LOAD; k++) {\n // Load FP4 packed data\n uint64_t a_packed = load_fp4(a, row, k);\n uint64_t b_packed = load_fp4(b, 0, k);\n\n // Dequantize via PTX\n half2 a_vals = cvt_e2m1x2(a_packed);\n half2 b_vals = cvt_e2m1x2(b_packed);\n\n // Apply block scales\n float sa = sfa[row * (K_SIZE/16) + k/2];\n float sb = sfb[k/2];\n\n // Accumulate\n acc += (float)a_vals.x * (float)b_vals.x * sa * sb;\n acc += (float)a_vals.y * (float)b_vals.y * sa * sb;\n }\n\n // Apply global scales and store\n c[row] = __float2half(acc * sf_a_global * sf_b_global);\n}\n\n// Dispatch: K=2048 uses BLOCK_M=8, maxreg=32\n// K=7168 uses BLOCK_M=4, maxreg=40\n// K=16384 uses BLOCK_M=2, maxreg=32\n```"}, "after": {"statement": null}, "reason": {"statement": "No primary contestant source supports this invented implementation.", "urls": []}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "128-bit and 256-bit vector loads maximize bandwidth utilization:\n\n```asm\n; 128-bit vector load (16 bytes = 32 FP4 elements)\nld.global.v2.u64 {r0, r1}, [addr];\n\n; 256-bit vector load (32 bytes = 64 FP4 elements)\nld.global.v4.u64 {r0, r1, r2, r3}, [addr];\n\n; Only effective when combined with PTX byte unpacking\n; to avoid bitwise overhead in the subsequent unpack stage\n; Without proper unpacking, wide loads just move the bottleneck\n```"}, "after": {"statement": "The official table assumes a 1.5 GHz B200 clock and ranks submissions by the geometric mean across all three rows:\n\n| 7168 | 16384 | 1 | 8.622 |\n| 4096 | 7168 | 8 | 17.275 |\n| 7168 | 2048 | 4 | 4.317 |\n\nNVIDIA's Blackwell technical brief specifies 8 TB/s of HBM3e bandwidth for one GB200 GPU. The task's theoretical numbers are model values, not measured kernel timings.\n\nPTX ISA 9.0 defines the packed conversion and typed register decomposition used in Yue's author-reported decode path:\n\n```asm\ncvt.rn.f16x2.e2m1x2 %result, %packed_fp4_pair;\nmov.b32 {%b0, %b1, %b2, %b3}, %packed_word;\n```\n\nIt also defines vector loads such as `ld.global.v2.u64` and `ld.global.v4.u64`, which move 16 and 32 bytes and can carry 32 and 64 packed FP4 values. The ISA specifies behavior, not that one width or decomposition is universally faster."}, "reason": {"statement": "Keep width semantics but remove universal performance guarantees.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv/task.yml", "https://resources.nvidia.com/en-us-blackwell-architecture/blackwell-architecture-technical-brief", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "```cpp\n// Load B vector into shared memory once per thread block\n// All BLOCK_M rows reuse the same B data\n__shared__ half b_shared[K_TILE];\n\n// Cooperative load: all threads in block load a portion of B\nfor (int i = threadIdx.x; i < K_TILE; i += blockDim.x) {\n b_shared[i] = dequant_fp4(b[i], sfb[i/16]) * sf_b_global;\n}\n__syncthreads();\n\n// Each thread computes dot product of its A row with shared B\nfloat acc = 0.0f;\nfor (int k = 0; k < K_TILE; k++) {\n acc += (float)a_dequant[k] * (float)b_shared[k];\n}\n\n// Reduces global memory traffic by BLOCK_M ratio\n```"}, "after": {"statement": "The logical operation has one B row, reused by all M output rows. The reference harness pads B and its scales to 128 rows so it can call `torch._scaled_mm`, then retains only result column zero. Consequently, A values are row-specific while the logical B vector is reused across M; it is incorrect to say every FP4 input value is consumed only once.\n\nAt pinned commit `ae679486`, `custom_kernel` receives seven tensors, not five tensors plus global FP32 scale arguments:\n\n| `a` | `[M, K/2, L]` | Packed E2M1 A; two logical values per byte |\n| `b` | `[128, K/2, L]` | Packed E2M1 B, physically padded; logical row 0 is used |\n| `sfa` | `[M, K/16, L]` | Logical/reference A block scales |\n| `sfb` | `[128, K/16, L]` | Logical/reference B block scales, padded to 128 rows |\n| `sfa_reordered` | `[32, 4, ceil(M/128), 4, K/64, L]` | Swizzled A scales for custom kernels |\n| `sfb_reordered` | `[32, 4, 1, 4, K/64, L]` | Swizzled padded-B scales for custom kernels |\n| `c` | `[M, 1, L]` | FP16 output buffer |\n\n`K` must be divisible by 64, and M must be divisible by the implementation's selected M tile. The task prose labels scales `e4m3fnuz`, but the pinned generator constructs `torch.float8_e4m3fn`; implementations should follow the actual harness revision they are tested against. This contest ABI exposes no per-tensor FP32 global scales.\n\nPTX ISA 9.0 defines the packed conversion and typed register decomposition used in Yue's author-reported decode path:\n\n```asm\ncvt.rn.f16x2.e2m1x2 %result, %packed_fp4_pair;\nmov.b32 {%b0, %b1, %b2, %b3}, %packed_word;\n```\n\nIt also defines vector loads such as `ld.global.v2.u64` and `ld.global.v4.u64`, which move 16 and 32 bytes and can carry 32 and 64 packed FP4 values. The ISA specifies behavior, not that one width or decomposition is universally faster."}, "reason": {"statement": "Remove invented contestant code and exact traffic attribution while retaining logical B reuse.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "| Coalesced access | Fix memory access patterns | 443us -> 39us |"}, "after": {"statement": "The public leaderboard is mutable and reports aggregate scores rather than per-shape latencies. In the snapshot fetched on 2026-08-08, the first three rows were `s.am._` at 18.549562452 µs, `gau.nernst` at 18.552844757 µs, and `shellsmile15795` at 18.707609314 µs. Yue's 22.392217755 µs submission was rank 11. The official cutoff was November 28, 2025 at 11:59 p.m. PT; current ranks 2 and 3 have November 30 timestamps, so this endpoint is not an official prize-placement snapshot."}, "reason": {"statement": "Restore the author's actual stage boundaries.", "urls": ["https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemv/NVIDIA?limit=100", "https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "1. **Memory-bound kernels need bandwidth-first thinking**: Arithmetic optimizations have minimal impact; focus on memory access patterns, cache policies, and vectorized loads"}, "after": {"statement": "PTX ISA 9.0 defines the packed conversion and typed register decomposition used in Yue's author-reported decode path:\n\n```asm\ncvt.rn.f16x2.e2m1x2 %result, %packed_fp4_pair;\nmov.b32 {%b0, %b1, %b2, %b3}, %packed_word;\n```\n\nIt also defines vector loads such as `ld.global.v2.u64` and `ld.global.v4.u64`, which move 16 and 32 bytes and can carry 32 and 64 packed FP4 values. The ISA specifies behavior, not that one width or decomposition is universally faster."}, "reason": {"statement": "Replace a universal rule with a profiling-dependent decision procedure.", "urls": ["https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "2. **PTX gives real control on Blackwell**: The gap between C intrinsics and hand-written PTX was substantial (443us to 27us in one journey)"}, "after": {"statement": "The public leaderboard is mutable and reports aggregate scores rather than per-shape latencies. In the snapshot fetched on 2026-08-08, the first three rows were `s.am._` at 18.549562452 µs, `gau.nernst` at 18.552844757 µs, and `shellsmile15795` at 18.707609314 µs. Yue's 22.392217755 µs submission was rank 11. The official cutoff was November 28, 2025 at 11:59 p.m. PT; current ranks 2 and 3 have November 30 timestamps, so this endpoint is not an official prize-placement snapshot."}, "reason": {"statement": "Use source-reported combined-stage attribution only.", "urls": ["https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemv/NVIDIA?limit=100", "https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "4. **Register budgeting matters**: Lower registers -> higher occupancy -> better memory latency hiding"}, "after": {"statement": "PTX ISA 9.0 defines the packed conversion and typed register decomposition used in Yue's author-reported decode path:\n\n```asm\ncvt.rn.f16x2.e2m1x2 %result, %packed_fp4_pair;\nmov.b32 {%b0, %b1, %b2, %b3}, %packed_word;\n```\n\nIt also defines vector loads such as `ld.global.v2.u64` and `ld.global.v4.u64`, which move 16 and 32 bytes and can carry 32 and 64 packed FP4 values. The ISA specifies behavior, not that one width or decomposition is universally faster."}, "reason": {"statement": "Make register caps conditional on realized use, spills, occupancy, and timing.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "5. **TMEM is irrelevant**: Memory-bound kernels do not benefit from TMEM (it helps compute-bound only)"}, "after": {"statement": null}, "reason": {"statement": "No useful universal TMEM recommendation is supported for this page.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "- Memory-bound operations with FP4 quantized weights"}, "after": {"statement": "Amandeep reports that three solutions inspected after the event used `L1::no_allocate` for streamed A loads, `L1::evict_last` for reused B loads, wider PTX loads, and exact-K specializations. Those are author-reported observations; the public leaderboard API supplies no contestant code or technique field. Amandeep's own wider `uint2` experiment was 16–25% slower, and reducing `-maxrregcount` from 80 to 64 had no effect because the kernel already used fewer than 64 registers. Load width, cache hints, and register caps therefore require measurement in the exact implementation."}, "reason": {"statement": "Scope applicability to exact task-compatible NVFP4 operands.", "urls": ["https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "- SM100/SM100a only (native FP4 decode instructions)"}, "after": {"statement": "Amandeep reports that three solutions inspected after the event used `L1::no_allocate` for streamed A loads, `L1::evict_last` for reused B loads, wider PTX loads, and exact-K specializations. Those are author-reported observations; the public leaderboard API supplies no contestant code or technique field. Amandeep's own wider `uint2` experiment was 16–25% slower, and reducing `-maxrregcount` from 80 to 64 had no effect because the kernel already used fewer than 64 registers. Load width, cache hints, and register caps therefore require measurement in the exact implementation."}, "reason": {"statement": "Separate contest B200 scope from versioned instruction/library support.", "urls": ["https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://docs.nvidia.com/cuda/archive/12.9.2/parallel-thread-execution/index.html", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"]}} +{"path": "wiki/kernels/nvfp4-gemv.md", "before": {"statement": "Local verbatim upstream code lives in [`artifacts/kernels/nvfp4-gemv/full/`](../../artifacts/kernels/nvfp4-gemv/full/) (see its `PROVENANCE.yaml` for the pinned upstream SHA and byte-verified SHA-256). Labeled derived variants — including a naive/teaching skeleton — live in [`artifacts/kernels/nvfp4-gemv/variants/`](../../artifacts/kernels/nvfp4-gemv/variants/)."}, "after": {"statement": null}, "reason": {"statement": "Detach the misleading artifact relationship while preserving the files and immutable receipt.", "urls": []}} +{"path": "wiki/languages/ptx-sm100.md", "before": {"statement": "```ptx\n// Allocate TMEM columns\ntcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [smem_tmem_addr], num_cols;\n\n// MMA: inputs from SMEM, accumulator in TMEM\ntcgen05.mma.cta_group::1.kind::f16 [tmem_addr], desc_a, desc_b, idesc, enable_input_d;\n\n// 2-SM cooperative MMA\ntcgen05.mma.cta_group::2.kind::f16 [tmem_addr], desc_a, desc_b, idesc, enable_input_d;\n\n// Load TMEM to registers\ntcgen05.ld.sync.aligned.32x32b.x1.b32 {regs}, [tmem_addr];\n\n// Store registers to TMEM\ntcgen05.st.sync.aligned.32x32b.x1.b32 [tmem_addr], {regs};\n\n// Copy a shaped SMEM matrix descriptor into TMEM\ntcgen05.cp.cta_group::1.128x256b [tmem_addr], sdesc;\n\n// Critical fence between TMA completion and MMA\ntcgen05.fence::after_thread_sync;\n\n// Deallocate TMEM (MUST before kernel exit)\ntcgen05.dealloc.cta_group::1.sync.aligned.b32 tmem_addr, num_cols;\n```"}, "after": {"statement": "TMEM/register transfers and shared-memory/TMEM copies have their own asynchronous completion rules:\n\n```ptx\ntcgen05.ld.sync.aligned.32x32b.x1.b32 {r0}, [taddr];\ntcgen05.wait::ld.sync.aligned;\n\ntcgen05.st.sync.aligned.32x32b.x1.b32 [taddr], {r0};\ntcgen05.wait::st.sync.aligned;\n\ntcgen05.cp.cta_group::1.128x256b [taddr], sdesc;\n```\n\n`tcgen05.ld` and `tcgen05.st` are warp-collective. `tcgen05.cp` copies a shaped shared-memory descriptor into TMEM. MMA and cp completion can be attached to an mbarrier with `tcgen05.commit`; the source and destination must remain live until their documented completion points."}, "reason": {"statement": "Separate TMA completion, async-proxy visibility, tcgen completion, and cross-thread tcgen ordering.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-cp"]}} +{"path": "wiki/languages/ptx-sm100.md", "before": {"statement": "```ptx\n// Convert two packed FP4 values to two FP16 values\ncvt.rn.f16x2.e2m1x2 result_f16x2, packed_fp4;\n\n// Byte unpacking (faster than bitwise extraction)\nmov.b32 {byte0, byte1, byte2, byte3}, packed_word;\n```"}, "after": {"statement": "- A TMA global-to-shared load completes bytes on its mbarrier; a consumer waits for that phase before reading the destination.\n- `tcgen05.commit` makes an mbarrier track completion of prior asynchronous tcgen05 MMA/cp/shift operations issued by the thread.\n- `tcgen05.wait::ld` and `tcgen05.wait::st` wait for the corresponding prior TMEM/register transfers.\n- `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` constrain tcgen05 operations around a documented cross-thread execution-ordering handoff. They are not substitutes for TMA or MMA completion waits."}, "reason": {"statement": "Keep exact semantics and require generated-code/timing comparison for performance.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence"]}} +{"path": "wiki/languages/ptx-sm100.md", "before": {"statement": "```ptx\n// Streaming data (use once): bypass L1\nld.global.L1::no_allocate.v2.u64 {r0, r1}, [addr];\n\n// Reused data: keep in L1\nld.global.L1::evict_last.v2.u64 {r0, r1}, [addr];\n\n// Wide vectorized loads\nld.global.v4.u64 {r0, r1, r2, r3}, [addr]; // 256-bit\n```"}, "after": {"statement": "PTX ISA 9.0 defines these typed operations:\n\n```ptx\ncvt.rn.f16x2.e2m1x2 result_f16x2, packed_fp4_pair;\nmov.b32 {byte0, byte1, byte2, byte3}, packed_word;\n```\n\nThe first converts one byte containing two E2M1 values into a 32-bit F16x2 result. The second can decompose a 32-bit scalar into four byte-sized destinations when operand declarations satisfy the scalar-to-vector size rules. PTX specifies these semantics but does not guarantee that the move is faster than every compiler-generated shift/mask sequence."}, "reason": {"statement": "Use normative hint semantics and separate workload selection from instruction behavior.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#cache-operators", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov"]}} +{"path": "wiki/languages/ptx-sm100.md", "before": {"statement": "```ptx\n// Query for next tile (persistent kernel loop)\nclusterlaunchcontrol.try_cancel {clc_id};\n// Returns valid tile_id or decline (all work done)\n```"}, "after": {"statement": "```ptx\nld.global.L1::no_allocate.v2.u64 {r0, r1}, [addr];\nld.global.L1::evict_last.v2.u64 {r0, r1}, [addr];\nld.global.v4.u64 {r0, r1, r2, r3}, [addr];\n```\n\n`L1::no_allocate` and `L1::evict_last` are eviction-priority hints and may not always be respected. They do not guarantee L1 bypass or residency. The vector forms above move 16 and 32 bytes; whether a width or hint helps depends on alignment, surrounding instructions, reuse, cache state, and the target GPU."}, "reason": {"statement": "Replace with the exact request/wait/query sequence.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld"]}} +{"path": "wiki/languages/ptx-sm100.md", "before": {"statement": "```ptx\n// Bulk tensor copy: global → shared\ncp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes\n [smem_ptr], [tensorMap, {x, y}], [mbarrier];\n\n// Multicast to cluster SMs\ncp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast\n [smem_ptr], [tensorMap, {x, y}], [mbarrier], multicast_mask;\n```"}, "after": {"statement": "CLC cancellation is an asynchronous request followed by response decoding:\n\n```ptx\nclusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128\n [response_smem], [response_mbarrier];\n\nclusterlaunchcontrol.query_cancel.is_canceled.pred.b128 p, response_b128;\n@p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128\n {x, y, z, unused}, response_b128;\n```\n\nThe request writes an opaque 16-byte response to shared memory and completes on the mbarrier. Code must wait for that phase before loading and querying the response. A successful query returns the first CTA coordinate of a canceled not-yet-launched block or cluster; the request does not take a desired tile ID."}, "reason": {"statement": "Use the exact version-pinned PTX spelling.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel"]}} +{"path": "wiki/languages/cuda-cpp.md", "before": {"statement": "```cuda\n// Allocate TMEM. tcgen05.alloc writes the allocated address into SMEM.\n__device__ uint32_t tmem_alloc_cta(uint32_t* smem_tmem_addr,\n uint32_t num_cols) {\n if (threadIdx.x == 0) {\n uint32_t smem_addr =\n static_cast(__cvta_generic_to_shared(smem_tmem_addr));\n asm volatile(\n \"tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;\"\n :: \"r\"(smem_addr), \"r\"(num_cols)\n );\n }\n __syncthreads();\n return *smem_tmem_addr;\n}\n\n// Issue MMA (single thread, typically warp 1 lane 0)\n// idesc_c/idesc_d: immediate descriptors for accumulator C and output D\n__device__ void tcgen05_mma(uint32_t tmem_addr,\n uint64_t desc_a, uint64_t desc_b,\n uint32_t idesc_c, uint32_t idesc_d) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16\"\n \" [%0], %1, %2, %3, %4;\"\n :: \"r\"(tmem_addr), \"l\"(desc_a), \"l\"(desc_b),\n \"r\"(idesc_c), \"r\"(idesc_d)\n );\n}\n\n// Load TMEM to registers\n__device__ void tmem_load(float* dst, uint32_t tmem_addr, int cols) {\n asm volatile(\n \"tcgen05.ld.sync.aligned.32x32b.x1.b32 {%0}, [%1];\"\n : \"=f\"(*dst) : \"r\"(tmem_addr)\n );\n}\n\n// Deallocate TMEM (MUST do before kernel exit)\n__device__ void tmem_dealloc(uint32_t addr, uint32_t num_cols) {\n asm volatile(\n \"tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;\"\n :: \"r\"(addr), \"r\"(num_cols)\n );\n}\n```"}, "after": {"statement": "The CUDA front end does not parse the instruction text inside an `asm()` statement. Operand constraints and address-space conversion therefore remain the wrapper author's responsibility. Use `\"r\"` for a 32-bit integer register, `\"l\"` for a 64-bit integer register, and convert a generic pointer with `__cvta_generic_to_shared` before supplying a shared-memory address. Add a `\"memory\"` clobber when the assembly has memory effects that are hidden from the compiler."}, "reason": {"statement": "Show whole-warp allocation and reserve lane election for single-thread MMA/TMA issue.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v6.cu", "https://docs.nvidia.com/cuda/archive/13.0.2/inline-ptx-assembly/index.html"]}} +{"path": "wiki/languages/cuda-cpp.md", "before": {"statement": "```cuda\n// Allocate TMEM. tcgen05.alloc writes the allocated address into SMEM.\n__device__ uint32_t tmem_alloc_cta(uint32_t* smem_tmem_addr,\n uint32_t num_cols) {\n if (threadIdx.x == 0) {\n uint32_t smem_addr =\n static_cast(__cvta_generic_to_shared(smem_tmem_addr));\n asm volatile(\n \"tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;\"\n :: \"r\"(smem_addr), \"r\"(num_cols)\n );\n }\n __syncthreads();\n return *smem_tmem_addr;\n}\n\n// Issue MMA (single thread, typically warp 1 lane 0)\n// idesc_c/idesc_d: immediate descriptors for accumulator C and output D\n__device__ void tcgen05_mma(uint32_t tmem_addr,\n uint64_t desc_a, uint64_t desc_b,\n uint32_t idesc_c, uint32_t idesc_d) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16\"\n \" [%0], %1, %2, %3, %4;\"\n :: \"r\"(tmem_addr), \"l\"(desc_a), \"l\"(desc_b),\n \"r\"(idesc_c), \"r\"(idesc_d)\n );\n}\n\n// Load TMEM to registers\n__device__ void tmem_load(float* dst, uint32_t tmem_addr, int cols) {\n asm volatile(\n \"tcgen05.ld.sync.aligned.32x32b.x1.b32 {%0}, [%1];\"\n : \"=f\"(*dst) : \"r\"(tmem_addr)\n );\n}\n\n// Deallocate TMEM (MUST do before kernel exit)\n__device__ void tmem_dealloc(uint32_t addr, uint32_t num_cols) {\n asm volatile(\n \"tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;\"\n :: \"r\"(addr), \"r\"(num_cols)\n );\n}\n```"}, "after": {"statement": "The allocation instruction is collective. For `.cta_group::1`, every lane of one designated warp must execute the same instruction. Synchronize the CTA before another warp reads the address written to shared memory.\n\n```cuda\n// All 32 lanes of alloc_warp execute this branch.\nif (warp_id == alloc_warp) {\n uint32_t smem_addr =\n static_cast(__cvta_generic_to_shared(smem_tmem_addr));\n asm volatile(\n \"tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 \"\n \"[%0], %1;\"\n :: \"r\"(smem_addr), \"r\"(num_cols) : \"memory\");\n}\n__syncthreads();\nuint32_t taddr = *smem_tmem_addr;\n```"}, "reason": {"statement": "Use one idesc plus a local predicate constructed from a CUDA integer.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v6.cu"]}} +{"path": "wiki/languages/cuda-cpp.md", "before": {"statement": "```cuda\n// TMA-MMA synchronization via mbarrier\n// expected_bytes: total bytes the TMA will deliver to this stage\n__device__ void mbarrier_arrive(uint64_t* mbar, uint32_t expected_bytes) {\n asm volatile(\n \"mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1;\"\n :: \"r\"((uint32_t)__cvta_generic_to_shared(mbar)),\n \"r\"(expected_bytes)\n );\n}\n\n__device__ void mbarrier_wait(uint64_t* mbar, int phase) {\n asm volatile(\n \"{\\n\"\n \".reg .pred p;\\n\"\n \"WAIT_LOOP:\\n\"\n \" mbarrier.try_wait.parity.shared.b64 p, [%0], %1;\\n\"\n \" @!p bra WAIT_LOOP;\\n\"\n \"}\\n\"\n :: \"r\"((uint32_t)__cvta_generic_to_shared(mbar)),\n \"r\"(phase)\n );\n}\n```"}, "after": {"statement": "An unscaled `kind::f16` MMA takes one instruction descriptor and an `enable-input-d` predicate. A single elected thread may issue this MMA form; converting an ordinary CUDA integer to the required PTX predicate inside the assembly keeps the C++ interface well typed.\n\n```cuda\n__device__ inline void tcgen05_mma_f16(\n uint32_t taddr, uint64_t a_desc, uint64_t b_desc,\n uint32_t idesc, int enable_input_d) {\n asm volatile(\n \"{\\n\\t\"\n \".reg .pred p;\\n\\t\"\n \"setp.ne.b32 p, %4, 0;\\n\\t\"\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, p;\\n\\t\"\n \"}\"\n :: \"r\"(taddr), \"l\"(a_desc), \"l\"(b_desc),\n \"r\"(idesc), \"r\"(enable_input_d));\n}\n```"}, "reason": {"statement": "Publish the full lifecycle invariants and memory-clobber requirement rather than a misleading two-function protocol.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/inline-ptx-assembly/index.html#incorrect-optimization", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v6.cu", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/common.h#L66-L78"]}} +{"path": "wiki/languages/cute-dsl.md", "before": {"statement": "CuTe (CUDA Templates) DSL is the primary abstraction layer in CUTLASS 4.5.0 for Blackwell kernels. FlashAttention-4 was implemented entirely in CuTe-DSL (Python variant), achieving 20-30× faster compilation than C++ templates."}, "after": {"statement": "CUTLASS v4.5.0 includes CuTe DSL, a Python-native interface for authoring GPU kernels, alongside CUTLASS's C++ template interfaces. This page uses the exact `v4.5.0` tag (`e406c186f510a15091cce01f782020ceb7ba8eb5`); rolling `latest` documentation can contain later names."}, "reason": {"statement": "Describe CuTe DSL as a Python-native CUTLASS interface without assigning unsupported primacy.", "urls": []}} +{"path": "wiki/languages/cute-dsl.md", "before": {"statement": "```python\n# CuTe-DSL: SM100 MMA atom for BF16\nfrom cutlass.cute import *\n\n# 1-SM MMA: m128 x n256 x k16\nmma_atom = SM100_MMA_F16BF16_SS # inputs from shared memory\n# Accumulator goes to TMEM automatically\n\n# 2-SM MMA: m256 x n256 x k16\nmma_atom_2sm = SM100_MMA_F16BF16_SS_2SM\n```"}, "after": {"statement": "CUTLASS 4.5.0 uses a configured `tcgen05.MmaF16BF16Op`, not an `SM100_MMA_F16BF16_SS` Python symbol. This excerpt shows the one-CTA operation used by the tagged first tutorial; it is construction code, not a complete kernel.\n\n```python\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import tcgen05\n\nop = tcgen05.MmaF16BF16Op(\n cutlass.Float16,\n cutlass.Float32,\n (128, 256, 16),\n tcgen05.CtaGroup.ONE,\n tcgen05.OperandSource.SMEM,\n cute.nvgpu.OperandMajorMode.K,\n cute.nvgpu.OperandMajorMode.K,\n)\ntiled_mma = cute.make_tiled_mma(op)\n```\n\nThe two-CTA tutorial instead uses instruction shape `(256, 256, 16)` and `tcgen05.CtaGroup.TWO`. The accumulator fragment is rebound to an allocated TMEM pointer before `cute.gemm` issues the operation."}, "reason": {"statement": "Replace invented identifiers with the exact version-pinned constructor.", "urls": []}} +{"path": "wiki/languages/cute-dsl.md", "before": {"statement": "```python\n# TMEM allocation in CuTe\ntmem_tensor = make_tensor(\n make_tmem_ptr(tmem_addr),\n make_layout(make_shape(128, 256)) # rows x cols\n)\n\n# Copy TMEM → registers for epilogue\ncopy(tmem_tensor, reg_tensor) # tcgen05.ld under the hood\n```"}, "after": {"statement": "The tagged examples use `cutlass.utils.TmemAllocator` around a shared holding buffer. A complete path allocates columns, waits before pointer retrieval, rebinds the accumulator tensor, partitions a typed `tcgen05` TMEM-to-register copy across participating threads, synchronizes readers, and frees the same allocation.\n\n```python\n# Excerpt: storage/barrier/tensor definitions and pipeline edges are required.\ntmem = utils.TmemAllocator(\n storage.tmem_holding_buf.ptr,\n barrier_for_retrieve=tmem_alloc_barrier,\n)\ntmem.allocate(num_tmem_cols)\ntmem.wait_for_alloc()\ntmem_ptr = tmem.retrieve_ptr(cutlass.Float32)\ntCtAcc = cute.make_tensor(tmem_ptr, tCtAcc.layout)\n\ntmem_atom = cute.make_copy_atom(\n tcgen05.Ld32x32bOp(tcgen05.Repetition.x64), cutlass.Float32\n)\ntmem_tiled_copy = tcgen05.make_tmem_copy(tmem_atom, tCtAcc_epi[None, 0])\n# get_slice(), partition_S/D(), and cute.copy() form the per-thread epilogue.\n\npipeline.sync(barrier_id=1)\ntmem.free(tmem_ptr)\n```\n\nThe excerpt deliberately does not imply that allocation or deallocation is lane-local. Use the complete tutorial for collective participation, two-CTA handling, and pointer lifetime."}, "reason": {"statement": "Use an evidence-scoped excerpt that preserves allocation, copy partition, wait, and free responsibilities.", "urls": []}} +{"path": "wiki/languages/cute-dsl.md", "before": {"statement": "```python\n# TMA bulk copy: global → shared\ntma_copy = SM100_TMA_LOAD_2D\n\n# Setup TMA descriptor\ntma_desc = make_tma_copy(\n tma_copy,\n global_tensor,\n smem_layout,\n tile_shape,\n cluster_shape\n)\n```"}, "after": {"statement": "The one-CTA tutorial constructs a typed global-to-shared TMA operation and then derives operand-specific tiled atoms. Kernel code subsequently uses `tma_partition` and `cute.copy` with pipeline barriers.\n\n```python\nfrom cutlass.cute.nvgpu import cpasync, tcgen05\n\ntma_op = cpasync.CopyBulkTensorTileG2SOp(tcgen05.CtaGroup.ONE)\na_tma_atom, a_tma_tensor = cute.nvgpu.make_tiled_tma_atom_A(\n tma_op,\n a,\n a_smem_layout_one_stage,\n mma_tiler_mnk,\n tiled_mma,\n)\n```\n\nFor the two-CTA tutorial, the corresponding operation is `CopyBulkTensorTileG2SMulticastOp(CtaGroup.TWO)` and the cluster layout/multicast participants must agree with the launch."}, "reason": {"statement": "Replace fabricated shorthand with the release's typed TMA atom and partitioning API.", "urls": []}} +{"path": "wiki/languages/cute-dsl.md", "before": {"statement": "```python\n@cute_kernel\ndef blackwell_gemm(A, B, C):\n # Warp 0: TMA producer\n if warp_id == 0:\n for stage in pipeline:\n tma_copy(A_tile, smem_A[stage])\n tma_copy(B_tile, smem_B[stage])\n arrive(mbarrier[stage])\n\n # Warp 1: MMA consumer\n elif warp_id == 1:\n tmem = alloc_tmem(256) # columns\n for stage in pipeline:\n wait(mbarrier[stage])\n fence_after_thread_sync()\n mma(smem_A[stage], smem_B[stage], tmem)\n signal_epilogue()\n\n # Warps 2+: Epilogue\n else:\n wait_epilogue()\n regs = load_tmem(tmem)\n store_global(C, regs)\n dealloc_tmem(tmem)\n```"}, "after": {"statement": "`fp16_gemm_2.py` specializes TMA, MMA, and epilogue warps and uses `PipelineTmaUmma` plus `PipelineUmmaAsync` to represent full/empty ownership. It also retains explicit TMEM allocation, epilogue TMEM-copy partitioning, TMA-store completion, pipeline tails, and collective teardown. Those details are required; an `if warp_id` sketch alone is not a safe synchronization recipe."}, "reason": {"statement": "Replace unsafe pseudocode with verified role/lifetime invariants and a link to the full implementation.", "urls": []}} +{"path": "wiki/languages/cute-dsl.md", "before": {"statement": "3. Same performance as hand-written C++ (FlashAttention-4: 1605 TFLOPS)"}, "after": {"statement": "FlashAttention-4 is implemented entirely in CuTe DSL. Its author reports roughly 20--30x shorter compile times than C++ templates and a peak of 1605 TFLOP/s on B200 BF16. These are FA4-specific, source-reported results. The 1605-TFLOP/s result was not presented as a matched comparison with a handwritten-C++ FA4 kernel."}, "reason": {"statement": "Preserve the author-reported maximum and remove the unsupported comparator.", "urls": ["https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/languages/cute-dsl.md", "before": {"statement": "5. Automatic layout computation and swizzle handling"}, "after": {"statement": "CuTe supplies typed layout algebra and Blackwell helpers such as `make_smem_layout_a` and `make_smem_layout_b`. The author still supplies the MMA tiler, datatypes, operand major modes, alignment, cluster shape, and pipeline policy; layout and swizzle choices are helper-assisted rather than universally automatic."}, "reason": {"statement": "Narrow the benefit to typed composition and version-pinned Blackwell helpers.", "urls": []}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "On Blackwell (SM100), `tcgen05.mma` stores accumulators in **Tensor Memory (TMEM)** -- a dedicated 256KB per-SM memory. This eliminates accumulator register pressure entirely, freeing registers for data movement, epilogue computation, and enabling larger tile sizes."}, "after": {"statement": "For `sm_100a`, tcgen05 D is addressed in Tensor Memory rather than supplied as a per-thread register vector. The CTA-visible TMEM structure has 128 lanes by 512 columns of 32-bit cells, or 256 KiB when fully allocated. Allocation is dynamic in columns.\n\nThis removes the resident D vector from the ordinary register file. It does not remove all register pressure: descriptors, addresses, loop state, pipeline state, and each TMEM-to-register epilogue batch still need registers. Both Hopper and compute-capability-10.0 Blackwell have 64K 32-bit registers per SM and at most 255 registers per thread. Occupancy, spilling, and practical tile size therefore remain properties of the compiled kernel and launch configuration."}, "reason": {"statement": "Keep the resident-D benefit while preserving resource-dependent limits.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "```\nHopper wgmma m64xn256xk16 BF16 register budget (per thread):\n\n Accumulator: 128 FP32 registers (m64 x n256 / 128 threads)\n A operand: 16 registers (via ldmatrix)\n B descriptor: 2 registers\n Loop variables: 8 registers\n SMEM pointers: 4 registers\n TMA state: 6 registers\n Misc (indexing): 10 registers\n ─────────────────────────────\n Total per thread: ~174 registers\n\n Per warpgroup (128 threads): 174 * 128 = 22,272 registers\n Per SM (65,536 regs): max 2 warpgroups = 2 CTAs at this tile size\n\n Occupancy: 2 CTAs per SM (limited by registers)\n```"}, "after": {"statement": "For Hopper `wgmma.mma_async.m64nNk16` with an FP32 accumulator, each warpgroup thread holds `N/2` FP32 D registers. At `N=256`, that is 128 registers per thread for D. WGMMA updates that register vector asynchronously; the program uses the WGMMA fence, commit-group, and wait-group mechanisms before dependent use.\n\nFor `sm_100a`, tcgen05 D is addressed in Tensor Memory rather than supplied as a per-thread register vector. The CTA-visible TMEM structure has 128 lanes by 512 columns of 32-bit cells, or 256 KiB when fully allocated. Allocation is dynamic in columns.\n\nThis removes the resident D vector from the ordinary register file. It does not remove all register pressure: descriptors, addresses, loop state, pipeline state, and each TMEM-to-register epilogue batch still need registers. Both Hopper and compute-capability-10.0 Blackwell have 64K 32-bit registers per SM and at most 255 registers per thread. Occupancy, spilling, and practical tile size therefore remain properties of the compiled kernel and launch configuration."}, "reason": {"statement": "No pinned kernel/resource report supports the invented categories.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "If the tile is larger (e.g., m64xn256xk32 with double-buffered accumulators), register pressure becomes even worse:\n\n```\nDouble-buffered accumulator: 256 registers per thread\nTotal per thread: ~300 registers\nPer warpgroup: 38,400 registers\nPer SM: max 1 warpgroup -> 1 CTA per SM\n\nOccupancy: 1 CTA per SM (severe underutilization)\n```"}, "after": {"statement": "For `sm_100a`, tcgen05 D is addressed in Tensor Memory rather than supplied as a per-thread register vector. The CTA-visible TMEM structure has 128 lanes by 512 columns of 32-bit cells, or 256 KiB when fully allocated. Allocation is dynamic in columns.\n\nThis removes the resident D vector from the ordinary register file. It does not remove all register pressure: descriptors, addresses, loop state, pipeline state, and each TMEM-to-register epilogue batch still need registers. Both Hopper and compute-capability-10.0 Blackwell have 64K 32-bit registers per SM and at most 255 registers per thread. Occupancy, spilling, and practical tile size therefore remain properties of the compiled kernel and launch configuration."}, "reason": {"statement": "The numeric scenario is not source- or experiment-grounded.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/hopper-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "```\nRegister access: ~4 cycles\nL1 local access: ~30 cycles\nL2 spill access: ~200 cycles\n\nA single spilled accumulator register accessed every MMA iteration\ncan cost 200 cycles * K_tiles additional latency.\n```"}, "after": {"statement": "For `sm_100a`, tcgen05 D is addressed in Tensor Memory rather than supplied as a per-thread register vector. The CTA-visible TMEM structure has 128 lanes by 512 columns of 32-bit cells, or 256 KiB when fully allocated. Allocation is dynamic in columns.\n\nThis removes the resident D vector from the ordinary register file. It does not remove all register pressure: descriptors, addresses, loop state, pipeline state, and each TMEM-to-register epilogue batch still need registers. Both Hopper and compute-capability-10.0 Blackwell have 64K 32-bit registers per SM and at most 255 registers per thread. Occupancy, spilling, and practical tile size therefore remain properties of the compiled kernel and launch configuration."}, "reason": {"statement": "Unsupported latency constants would mislead migration decisions.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-best-practices-guide/index.html#local-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "```\nBlackwell tcgen05 m128xn256xk16 BF16 register budget (per thread):\n\n Accumulator: 0 registers (stored in TMEM!)\n SMEM descriptors: 4 registers\n Loop variables: 8 registers\n TMA state: 6 registers\n TMEM address: 1 register\n Misc (indexing): 10 registers\n ─────────────────────────────\n Total per thread: ~29 registers\n\n Per CTA (256 threads): 29 * 256 = 7,424 registers\n Per SM (65,536 regs): max 8 CTAs (register-wise)\n Actual limit: TMEM capacity (512 columns)\n\n TMEM usage per CTA: 256 columns for 128x256 tile\n Max CTAs per SM: 512 / 256 = 2 CTAs (TMEM-limited, not register-limited)\n```\n\nThe key insight: **registers are no longer the bottleneck**. TMEM capacity becomes the binding constraint for occupancy, and the freed registers enable complex epilogues without spilling."}, "after": {"statement": "For `sm_100a`, tcgen05 D is addressed in Tensor Memory rather than supplied as a per-thread register vector. The CTA-visible TMEM structure has 128 lanes by 512 columns of 32-bit cells, or 256 KiB when fully allocated. Allocation is dynamic in columns.\n\nThis removes the resident D vector from the ordinary register file. It does not remove all register pressure: descriptors, addresses, loop state, pipeline state, and each TMEM-to-register epilogue batch still need registers. Both Hopper and compute-capability-10.0 Blackwell have 64K 32-bit registers per SM and at most 255 registers per thread. Occupancy, spilling, and practical tile size therefore remain properties of the compiled kernel and launch configuration."}, "reason": {"statement": "Replace speculative arithmetic with a measurement workflow.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory-allocation", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "```cuda\n// HOPPER: Accumulator lives and dies in registers\n__global__ void hopper_kernel(/* ... */) {\n // 1. Declare accumulator in registers\n float acc[4][32]; // 128 registers per thread!\n\n // 2. Zero-initialize\n #pragma unroll\n for (int i = 0; i < 4; ++i)\n for (int j = 0; j < 32; ++j)\n acc[i][j] = 0.0f;\n\n // 3. Mainloop: wgmma accumulates into registers\n for (int k = 0; k < K_tiles; ++k) {\n // Load A via ldmatrix\n uint32_t a_frag[4];\n ldmatrix(a_frag, smem_a + k * TILE_K);\n\n // wgmma: reads A from registers, B from SMEM descriptor\n // Accumulates into acc[] registers\n wgmma_m64n256k16(acc, a_frag, smem_b_desc);\n wgmma_commit();\n wgmma_wait();\n }\n\n // 4. Epilogue: acc is directly in registers -- fast access\n // But: if epilogue needs temporary storage, registers are exhausted\n #pragma unroll\n for (int i = 0; i < 4; ++i) {\n for (int j = 0; j < 32; ++j) {\n float val = acc[i][j];\n val += bias[col_base + j]; // bias add\n val = fmaxf(val, 0.0f); // ReLU\n // Need to convert and store -- no registers left for temp!\n C[row * N + col_base + j] = __float2half(val);\n }\n }\n\n // 5. Accumulator freed implicitly when CTA exits\n}\n```"}, "after": {"statement": "For Hopper `wgmma.mma_async.m64nNk16` with an FP32 accumulator, each warpgroup thread holds `N/2` FP32 D registers. At `N=256`, that is 128 registers per thread for D. WGMMA updates that register vector asynchronously; the program uses the WGMMA fence, commit-group, and wait-group mechanisms before dependent use.\n\n| Resident D | Per-thread register fragment | TMEM region addressed by `taddr` |\n| Example FP32 D cost | `N/2` registers/thread; 128 at `N=256` | No resident per-thread D vector |\n| First accumulation | Set WGMMA `scale-d` false to compute `D=A*B`, or initialize/use D when accumulation is intended | Set `enable-input-d` false to compute `D=A*B`, or explicitly initialize D when the algorithm needs another value |\n| Compute completion | WGMMA commit/wait group | `tcgen05.commit` to an mbarrier, then wait before a consumer reads/reuses D |\n| Epilogue access | Use the thread's D registers | Collective `tcgen05.ld`, then `tcgen05.wait::ld` before consuming result registers |\n| Cleanup | Register lifetime ends with the thread | Matching collective `tcgen05.dealloc` before kernel exit |\n| Double buffering | Two simultaneously live D fragments consume two register fragments | Two live outputs consume disjoint TMEM columns inside the allocation |\n\nThe table describes storage contracts, not an occupancy prediction. Instruction shape is also not necessarily the same as a composed CTA tile."}, "reason": {"statement": "Separate the PTX register-D contract from compiler allocation conclusions.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#local-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-instructions-wgmma-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "```cuda\n// BLACKWELL: Accumulator lives in TMEM\n__global__ void blackwell_kernel(/* ... */) {\n // 1. Allocate TMEM (explicit, must be done once)\n __shared__ uint32_t s_tmem_acc;\n if (threadIdx.x == 0) {\n uint32_t smem_addr =\n static_cast(__cvta_generic_to_shared(&s_tmem_acc));\n asm volatile(\n \"tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;\"\n :: \"r\"(smem_addr), \"r\"(256)\n );\n }\n __syncthreads();\n uint32_t tmem_acc = s_tmem_acc;\n\n // 2. Zero-initialize TMEM\n for (int c = 0; c < 256; c += 4) {\n asm volatile(\n \"tcgen05.st.sync.aligned.32x1b.x4.b32 [%0], {%1,%2,%3,%4};\"\n : : \"r\"(tmem_acc + c),\n \"f\"(0.f), \"f\"(0.f), \"f\"(0.f), \"f\"(0.f)\n );\n }\n\n // 3. Mainloop: tcgen05 accumulates into TMEM\n for (int k = 0; k < K_tiles; ++k) {\n // NO ldmatrix -- tcgen05 reads directly from SMEM\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.mma.cta_group::1.kind::f16 \"\n \"[%0], %1, %2, %3, 1;\"\n : : \"r\"(tmem_acc), \"l\"(desc_a), \"l\"(desc_b), \"r\"(0)\n );\n }\n // NO commit/wait -- fully async\n }\n\n // 4. Fence before reading\n asm volatile(\"tcgen05.fence::before_thread_sync;\");\n __syncthreads();\n\n // 5. Epilogue: read from TMEM to registers (in small batches)\n // PLENTY of registers available for epilogue temporaries!\n for (int c = 0; c < 256; c += 4) {\n float4 vals;\n asm volatile(\n \"tcgen05.ld.sync.aligned.32x1b.x4.b32 {%0,%1,%2,%3}, [%4];\"\n : \"=f\"(vals.x), \"=f\"(vals.y), \"=f\"(vals.z), \"=f\"(vals.w)\n : \"r\"(tmem_acc + c)\n );\n\n // Apply epilogue ops with register headroom\n vals.x += bias[col_base + c];\n vals.y += bias[col_base + c + 1];\n vals.z += bias[col_base + c + 2];\n vals.w += bias[col_base + c + 3];\n\n vals.x = fmaxf(vals.x, 0.0f); // ReLU\n vals.y = fmaxf(vals.y, 0.0f);\n vals.z = fmaxf(vals.z, 0.0f);\n vals.w = fmaxf(vals.w, 0.0f);\n\n // Vectorized store -- registers available for conversion\n half2 h01 = __floats2half2_rn(vals.x, vals.y);\n half2 h23 = __floats2half2_rn(vals.z, vals.w);\n *reinterpret_cast(&C[row * N + col_base + c]) = h01;\n *reinterpret_cast(&C[row * N + col_base + c + 2]) = h23;\n }\n\n // 6. Deallocate TMEM (explicit, MUST be done in persistent kernels)\n if (threadIdx.x == 0) {\n asm volatile(\n \"tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;\"\n : : \"r\"(tmem_acc), \"r\"(256)\n );\n }\n}\n```"}, "after": {"statement": "1. Choose one CTA-group mode for the kernel. For allocation, `nCols` is a power of two in `[32, 512]`; allocations are column-granular and cover all 128 lanes.\n2. Have every lane of one designated warp execute the same `.cta_group::1` allocation. Synchronize before other threads read the 32-bit `taddr` written to shared memory. Two-CTA mode requires one warp in each live peer CTA.\n3. Initialize and publish the barriers used by TMA and tcgen05. If the first MMA should compute only `A*B`, supply a false `enable-input-d` predicate instead of assuming a mandatory TMEM zero-store pass.\n4. Issue MMA from the permitted elected thread with valid A/B descriptors, instruction descriptor, predicate, and lifetimes.\n5. Attach completion of the relevant tcgen05 work to an mbarrier with `tcgen05.commit`. A fence controls execution ordering but is not a completion wait."}, "reason": {"statement": "Replace the block with lifecycle invariants and known-good source routes.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "With accumulators in TMEM, the tile size is no longer constrained by register count:\n\n```cuda\n// Hopper: large tiles cause spilling\n// m64xn256 uses 128 acc registers/thread -> barely fits\n// m128xn256 would need 256 acc registers/thread -> spills guaranteed\n\n// Blackwell: tile size limited by TMEM columns (512) and SMEM, not registers\n// m128xn256: 256 TMEM cols, 0 acc registers -> fits easily\n// m128xn512: 512 TMEM cols, 0 acc registers -> uses full TMEM budget\n// m256xn256 (2-SM): 256 TMEM cols/SM, 0 acc registers -> fits with cooperative\n```"}, "after": {"statement": "For `sm_100a`, tcgen05 D is addressed in Tensor Memory rather than supplied as a per-thread register vector. The CTA-visible TMEM structure has 128 lanes by 512 columns of 32-bit cells, or 256 KiB when fully allocated. Allocation is dynamic in columns.\n\nThis removes the resident D vector from the ordinary register file. It does not remove all register pressure: descriptors, addresses, loop state, pipeline state, and each TMEM-to-register epilogue batch still need registers. Both Hopper and compute-capability-10.0 Blackwell have 64K 32-bit registers per SM and at most 255 registers per thread. Occupancy, spilling, and practical tile size therefore remain properties of the compiled kernel and launch configuration.\n\nTMEM makes it practical to keep multiple output regions independently addressable while different warp roles issue MMA and drain a completed region. Safe overlap needs three distinct proofs:\n\n- compute completion occurs before an epilogue loads a region;\n- all epilogue loads complete before that region is overwritten or deallocated;\n- producer/consumer state and phase cannot alias a different pipeline stage.\n\nTMEM is not the only way to overlap tensor-core and non-matmul work. FlashAttention-3 already uses warp specialization and matmul/softmax interleaving on Hopper with register accumulators. The migration benefit is the different storage and lifetime tradeoff, not a new theorem that overlap was previously impossible."}, "reason": {"statement": "Replace categorical tile advice with descriptor legality plus empirical tuning.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://arxiv.org/abs/2407.08608"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "On Hopper, complex epilogues (bias + activation + quantization + scaling) often spill because registers are already exhausted by the accumulator. On Blackwell, the epilogue has the full register file available:\n\n```cuda\n// Blackwell epilogue: full register file available\n__device__ void rich_epilogue(uint32_t tmem_acc, float* output,\n const float* bias, const float* scale,\n int M, int N) {\n // Read TMEM in chunks\n for (int c = 0; c < 256; c += 8) {\n // Load 8 values from TMEM (8 registers -- trivial)\n float v[8];\n tmem_load_f32x4(tmem_acc + c, &v[0]);\n tmem_load_f32x4(tmem_acc + c + 4, &v[4]);\n\n // Apply bias (8 registers for bias values)\n float b[8];\n load_global_f32x4(&b[0], bias + c);\n load_global_f32x4(&b[4], bias + c + 4);\n\n #pragma unroll\n for (int i = 0; i < 8; ++i) v[i] += b[i];\n\n // Apply GELU activation (needs temp registers for polynomial)\n #pragma unroll\n for (int i = 0; i < 8; ++i) v[i] = gelu(v[i]);\n\n // Apply per-channel scale\n float s[8];\n load_global_f32x4(&s[0], scale + c);\n load_global_f32x4(&s[4], scale + c + 4);\n\n #pragma unroll\n for (int i = 0; i < 8; ++i) v[i] *= s[i];\n\n // Quantize to FP8 for next layer\n uint8_t q[8];\n #pragma unroll\n for (int i = 0; i < 8; ++i) q[i] = float_to_e4m3(v[i]);\n\n // Store quantized output\n store_global_u8x8(output + c, q);\n\n // Total temp registers used: ~24 -- NO SPILLING\n // On Hopper this epilogue would need 24 + 128 (acc) = 152 per thread\n }\n}\n```"}, "after": {"statement": "For `sm_100a`, tcgen05 D is addressed in Tensor Memory rather than supplied as a per-thread register vector. The CTA-visible TMEM structure has 128 lanes by 512 columns of 32-bit cells, or 256 KiB when fully allocated. Allocation is dynamic in columns.\n\nThis removes the resident D vector from the ordinary register file. It does not remove all register pressure: descriptors, addresses, loop state, pipeline state, and each TMEM-to-register epilogue batch still need registers. Both Hopper and compute-capability-10.0 Blackwell have 64K 32-bit registers per SM and at most 255 registers per thread. Occupancy, spilling, and practical tile size therefore remain properties of the compiled kernel and launch configuration.\n\n3. Initialize and publish the barriers used by TMA and tcgen05. If the first MMA should compute only `A*B`, supply a false `enable-input-d` predicate instead of assuming a mandatory TMEM zero-store pass.\n4. Issue MMA from the permitted elected thread with valid A/B descriptors, instruction descriptor, predicate, and lifetimes.\n5. Attach completion of the relevant tcgen05 work to an mbarrier with `tcgen05.commit`. A fence controls execution ordering but is not a completion wait."}, "reason": {"statement": "Preserve the design opportunity without promising allocation or performance.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "The most powerful pattern enabled by TMEM: overlapping the current tile's epilogue with the next tile's MMA computation. This is impossible with register accumulators because the accumulator registers are still in use.\n\n```cuda\n__global__ void overlapped_gemm(/* ... */) {\n // Two TMEM accumulator buffers\n uint32_t tmem_a = tmem_alloc(256);\n uint32_t tmem_b = tmem_alloc(256);\n uint32_t* tmem_cur = &tmem_a;\n uint32_t* tmem_nxt = &tmem_b;\n\n // Compute first tile into tmem_a\n compute_tile(*tmem_cur, tile_0);\n fence_and_sync();\n\n for (int t = 1; t < num_tiles; ++t) {\n // START: next tile MMA into tmem_nxt (background, async)\n zero_tmem(*tmem_nxt);\n start_mma(*tmem_nxt, tile_t);\n\n // SIMULTANEOUSLY: epilogue of current tile from tmem_cur\n // MMA is running in the background while we read the old accumulator!\n epilogue_from_tmem(*tmem_cur, output_tile[t-1]);\n\n // Wait for MMA to complete\n fence_and_sync();\n\n // Swap buffers\n uint32_t* tmp = tmem_cur;\n tmem_cur = tmem_nxt;\n tmem_nxt = tmp;\n }\n\n // Final epilogue\n epilogue_from_tmem(*tmem_cur, output_tile[num_tiles-1]);\n\n tmem_dealloc(tmem_a, 256);\n tmem_dealloc(tmem_b, 256);\n}\n```"}, "after": {"statement": "6. After the completion handoff, participating epilogue lanes execute a legal `tcgen05.ld` shape and `tcgen05.wait::ld` before using the loaded registers.\n7. After all readers finish, every lane of the designated warp executes the matching deallocation on every kernel exit path. Allocation/deallocation address, column count, and CTA-group mode must agree."}, "reason": {"statement": "Describe overlap as a scheduling option requiring disjoint regions and explicit handoffs.", "urls": ["https://arxiv.org/abs/2407.08608", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "```\nFlashAttention on Hopper needs registers for:\n - QK^T accumulator: 64 registers (m64xn64 attention scores)\n - PV accumulator: 128 registers (m64xn256 output)\n - Softmax state: 4 registers (rowmax, rowsum)\n - Q fragment: 16 registers\n - K fragment: 16 registers\n - V fragment: 16 registers\n - Loop state: 10 registers\n ──────────────────────────────\n Total: ~254 registers per thread\n\n Available: 256 registers/thread at 1 CTA/SM occupancy\n Margin: 2 registers (!!)\n \n Result: compiler must spill, or tile sizes must shrink\n```\n\n```\nFlashAttention on Blackwell:\n - QK^T accumulator: 0 registers (TMEM buffer 1, 64 cols)\n - PV accumulator: 0 registers (TMEM buffer 2, 256 cols)\n - Softmax state: 4 registers (rowmax, rowsum)\n - SMEM descriptors: 6 registers\n - Loop state: 10 registers\n ──────────────────────────────\n Total: ~20 registers per thread\n\n Available: 256 registers/thread\n Margin: 236 registers -- massive headroom\n\n Result: Can use for ping-pong scheduling, software exp emulation,\n larger tiles, more pipeline stages\n```"}, "after": {"statement": "Representative PTX ISA 9.0 forms are shown below. They omit declarations, descriptor construction, collective control flow, barriers, and inline-assembly constraints, so they are not a standalone kernel.\n\n```ptx\ntcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [saddr], nCols;\ntcgen05.mma.cta_group::1.kind::f16 [taddr], a_desc, b_desc, idesc, p;\ntcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cta.b64 [mbar];\ntcgen05.ld.sync.aligned.32x32b.x1.b32 {r0}, [taddr];\ntcgen05.wait::ld.sync.aligned;\ntcgen05.dealloc.cta_group::1.sync.aligned.b32 taddr, nCols;\n```"}, "reason": {"statement": "Replace invented budgets with the paper's directly reported TMEM roles.", "urls": ["https://arxiv.org/abs/2603.05451v1", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "```cuda\n// WRONG: Fine-grained TMEM access in a tight loop (high latency)\nfor (int i = 0; i < 256; ++i) {\n float v = tmem_load_f32(tmem_acc + i); // 420 cycle latency each!\n output[i] = v;\n}\n\n// CORRECT: Vectorized loads to amortize latency\nfor (int i = 0; i < 256; i += 4) {\n float4 v = tmem_load_f32x4(tmem_acc + i); // Single 420-cycle access\n output[i] = v.x;\n output[i+1] = v.y;\n output[i+2] = v.z;\n output[i+3] = v.w;\n}\n```"}, "after": {"statement": "3. Initialize and publish the barriers used by TMA and tcgen05. If the first MMA should compute only `A*B`, supply a false `enable-input-d` predicate instead of assuming a mandatory TMEM zero-store pass.\n4. Issue MMA from the permitted elected thread with valid A/B descriptors, instruction descriptor, predicate, and lifetimes.\n5. Attach completion of the relevant tcgen05 work to an mbarrier with `tcgen05.commit`. A fence controls execution ordering but is not a completion wait.\n\nTMEM makes it practical to keep multiple output regions independently addressable while different warp roles issue MMA and drain a completed region. Safe overlap needs three distinct proofs:\n\n- compute completion occurs before an epilogue loads a region;\n- all epilogue loads complete before that region is overwritten or deallocated;\n- producer/consumer state and phase cannot alias a different pipeline stage.\n\nTMEM is not the only way to overlap tensor-core and non-matmul work. FlashAttention-3 already uses warp specialization and matmul/softmax interleaving on Hopper with register accumulators. The migration benefit is the different storage and lifetime tradeoff, not a new theorem that overlap was previously impossible."}, "reason": {"statement": "Keep batching as a profiling hypothesis, not a latency theorem.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://arxiv.org/abs/2512.02189", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://arxiv.org/abs/2407.08608"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "```cuda\n// Hopper: tile size was m64xn128 to avoid register spilling\n// Migrating to Blackwell: keep same tile = leaving performance on the table\n\n// Blackwell should use at minimum m128xn256 (1-SM) or m256xn256 (2-SM)\n// The freed registers allow larger tiles without any spilling risk\n```"}, "after": {"statement": "TMEM makes it practical to keep multiple output regions independently addressable while different warp roles issue MMA and drain a completed region. Safe overlap needs three distinct proofs:\n\n- compute completion occurs before an epilogue loads a region;\n- all epilogue loads complete before that region is overwritten or deallocated;\n- producer/consumer state and phase cannot alias a different pipeline stage.\n\nTMEM is not the only way to overlap tensor-core and non-matmul work. FlashAttention-3 already uses warp specialization and matmul/softmax interleaving on Hopper with register accumulators. The migration benefit is the different storage and lifetime tradeoff, not a new theorem that overlap was previously impossible."}, "reason": {"statement": "Turn the mandate into an evidence-driven tuning checklist.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://arxiv.org/abs/2407.08608"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "```cuda\n// WRONG: Forgetting to dealloc in a persistent kernel\n__global__ void persistent_kernel(/* ... */) {\n uint32_t tmem = tmem_alloc(256); // Allocated once\n\n while (has_work()) {\n compute_tile(tmem);\n // BUG: If the kernel exits early (e.g., error path),\n // TMEM is leaked. Next CTA on this SM cannot allocate.\n }\n // Missing: tmem_dealloc(tmem, 256);\n}\n\n// CORRECT: Always dealloc, even on error paths\n__global__ void persistent_kernel(/* ... */) {\n uint32_t tmem = tmem_alloc(256);\n\n while (has_work()) {\n compute_tile(tmem);\n }\n\n tmem_dealloc(tmem, 256); // Always reached\n}\n```"}, "after": {"statement": "1. Choose one CTA-group mode for the kernel. For allocation, `nCols` is a power of two in `[32, 512]`; allocations are column-granular and cover all 128 lanes.\n2. Have every lane of one designated warp execute the same `.cta_group::1` allocation. Synchronize before other threads read the 32-bit `taddr` written to shared memory. Two-CTA mode requires one warp in each live peer CTA.\n\nTMEM makes it practical to keep multiple output regions independently addressable while different warp roles issue MMA and drain a completed region. Safe overlap needs three distinct proofs:\n\n- compute completion occurs before an epilogue loads a region;\n- all epilogue loads complete before that region is overwritten or deallocated;\n- producer/consumer state and phase cannot alias a different pipeline stage.\n\nTMEM is not the only way to overlap tensor-core and non-matmul work. FlashAttention-3 already uses warp specialization and matmul/softmax interleaving on Hopper with register accumulators. The migration benefit is the different storage and lifetime tradeoff, not a new theorem that overlap was previously impossible."}, "reason": {"statement": "State the normative obligation and control-flow requirements.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://arxiv.org/abs/2407.08608"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "| Zero-initialization | Loop over register array | `tcgen05.st` zero pattern |"}, "after": {"statement": "3. Initialize and publish the barriers used by TMA and tcgen05. If the first MMA should compute only `A*B`, supply a false `enable-input-d` predicate instead of assuming a mandatory TMEM zero-store pass.\n4. Issue MMA from the permitted elected thread with valid A/B descriptors, instruction descriptor, predicate, and lifetimes.\n5. Attach completion of the relevant tcgen05 work to an mbarrier with `tcgen05.commit`. A fence controls execution ordering but is not a completion wait."}, "reason": {"statement": "Describe both initialization choices without prescribing a needless store.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "| Epilogue headroom | Minimal (spill risk) | Ample (full register file) |"}, "after": {"statement": "For `sm_100a`, tcgen05 D is addressed in Tensor Memory rather than supplied as a per-thread register vector. The CTA-visible TMEM structure has 128 lanes by 512 columns of 32-bit cells, or 256 KiB when fully allocated. Allocation is dynamic in columns.\n\nThis removes the resident D vector from the ordinary register file. It does not remove all register pressure: descriptors, addresses, loop state, pipeline state, and each TMEM-to-register epilogue batch still need registers. Both Hopper and compute-capability-10.0 Blackwell have 64K 32-bit registers per SM and at most 255 registers per thread. Occupancy, spilling, and practical tile size therefore remain properties of the compiled kernel and launch configuration.\n\nTMEM makes it practical to keep multiple output regions independently addressable while different warp roles issue MMA and drain a completed region. Safe overlap needs three distinct proofs:\n\n- compute completion occurs before an epilogue loads a region;\n- all epilogue loads complete before that region is overwritten or deallocated;\n- producer/consumer state and phase cannot alias a different pipeline stage.\n\nTMEM is not the only way to overlap tensor-core and non-matmul work. FlashAttention-3 already uses warp specialization and matmul/softmax interleaving on Hopper with register accumulators. The migration benefit is the different storage and lifetime tradeoff, not a new theorem that overlap was previously impossible."}, "reason": {"statement": "State reduced resident-D pressure as an opportunity, not a guarantee.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://arxiv.org/abs/2407.08608"]}} +{"path": "wiki/migration/register-to-tmem.md", "before": {"statement": "| Max practical tile | m64xn256 (limited by registers) | m128xn256 or m256xn256 (limited by TMEM cols) |"}, "after": {"statement": "For Hopper `wgmma.mma_async.m64nNk16` with an FP32 accumulator, each warpgroup thread holds `N/2` FP32 D registers. At `N=256`, that is 128 registers per thread for D. WGMMA updates that register vector asynchronously; the program uses the WGMMA fence, commit-group, and wait-group mechanisms before dependent use.\n\nTMEM makes it practical to keep multiple output regions independently addressable while different warp roles issue MMA and drain a completed region. Safe overlap needs three distinct proofs:\n\n- compute completion occurs before an epilogue loads a region;\n- all epilogue loads complete before that region is overwritten or deallocated;\n- producer/consumer state and phase cannot alias a different pipeline stage.\n\nTMEM is not the only way to overlap tensor-core and non-matmul work. FlashAttention-3 already uses warp specialization and matmul/softmax interleaving on Hopper with register accumulators. The migration benefit is the different storage and lifetime tradeoff, not a new theorem that overlap was previously impossible."}, "reason": {"statement": "Separate legal instruction shapes from empirical CTA tile tuning.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-instructions-wgmma-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://arxiv.org/abs/2407.08608"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "```cuda\n// TMEM double-buffering: ping-pong between two 128x256 accumulator regions\n//\n// TMEM physical layout (per SM):\n// +------ 256 cols ------+------ 256 cols ------+\n// | | |\n// | Buffer A (active) | Buffer B (drain) | 128 rows\n// | MMA writes here | Epilogue reads |\n// | | |\n// +----------------------+----------------------+\n//\n// After tile completes, roles swap:\n// Buffer A becomes \"drain\", Buffer B becomes \"active\"\n\n#define TMEM_BUF_A_OFFSET 0\n#define TMEM_BUF_B_OFFSET 256\n#define TMEM_COLS_PER_BUF 256\n\n__device__ void tmem_double_buffer_mainloop(\n const GemmParams& params,\n int num_output_tiles)\n{\n int warp_id = threadIdx.x / 32;\n int lane_id = threadIdx.x % 32;\n\n // Synchronization between MMA warp and epilogue warps\n __shared__ uint64_t mbar_acc_ready[2]; // MMA done, epilogue can read\n __shared__ uint64_t mbar_acc_drained[2]; // Epilogue done, MMA can reuse\n\n if (threadIdx.x == 0) {\n mbarrier_init(&mbar_acc_ready[0], 1);\n mbarrier_init(&mbar_acc_ready[1], 1);\n mbarrier_init(&mbar_acc_drained[0], 1);\n mbarrier_init(&mbar_acc_drained[1], 1);\n }\n __syncthreads();\n\n for (int tile = 0; tile < num_output_tiles; tile++) {\n int buf = tile % 2;\n int tmem_offset = buf ? TMEM_BUF_B_OFFSET : TMEM_BUF_A_OFFSET;\n\n if (warp_id == 1) {\n // === MMA WARP ===\n // Wait for epilogue to finish draining this buffer\n if (tile >= 2) {\n mbarrier_wait(&mbar_acc_drained[buf]);\n }\n\n // Clear accumulator region before new tile\n if (lane_id == 0) {\n tmem_clear(tmem_offset, TMEM_COLS_PER_BUF);\n }\n __syncwarp();\n\n // Accumulate K-tiles into this TMEM buffer\n for (int k = 0; k < num_k_tiles; k++) {\n // (TMA load sync omitted -- see pipeline-stages)\n if (lane_id == 0) {\n tcgen05_mma_accumulate(tmem_offset);\n }\n __syncwarp();\n }\n\n // Signal epilogue that accumulator is ready\n if (lane_id == 0) {\n mbarrier_arrive(&mbar_acc_ready[buf]);\n }\n\n } else if (warp_id >= 2) {\n // === EPILOGUE WARPS ===\n // Wait for MMA to finish accumulating\n mbarrier_wait(&mbar_acc_ready[buf]);\n\n // Read TMEM and store to global memory\n int rows_per_warp = TILE_M / 14;\n int my_row = (warp_id - 2) * rows_per_warp;\n for (int r = my_row; r < my_row + rows_per_warp; r++) {\n for (int c = lane_id; c < TMEM_COLS_PER_BUF; c += 32) {\n float val = tmem_load_f32(r, tmem_offset + c);\n // Apply epilogue and store...\n params.C_ptr[r * params.N + c] = __float2half(val);\n }\n }\n\n // All epilogue warps must finish reading TMEM before the MMA\n // warp can overwrite this half-buffer. Each epilogue warp arrives\n // on a shared mbarrier; the mbarrier is initialized with\n // arrival_count = NUM_EPILOGUE_WARPS (e.g. 14 for warps 2-15).\n // The MMA warp waits on this mbarrier before reusing the buffer.\n if (lane_id == 0) {\n mbarrier_arrive(&mbar_acc_drained[buf]);\n }\n // mbar_acc_drained[buf] fires only after ALL epilogue warps arrive\n }\n }\n}\n```"}, "after": {"statement": "The CTA-visible TMEM address structure has 128 lanes and 512 columns of 32-bit cells. Allocation is column-granular across all 128 lanes. A kernel that allocates 512 columns may choose two 256-column regions:\n\n```text\nregion[0] = columns [0, 256)\nregion[1] = columns [256, 512)\n```\n\nThis equal split is one implementation choice. The actual invariant is that every simultaneously live region is inside the allocation and does not alias another region whose MMA or epilogue access is still outstanding. Region sizes can differ, and logical element capacity depends on the tcgen05 instruction kind and packing rather than the raw cell count alone.\n\nFor each region, prove this lifecycle:\n\n| free → MMA-owned | every prior epilogue load from the region has completed |\n| MMA-owned → ready | relevant tcgen05 work is committed to an mbarrier and completion is observed |\n| ready → epilogue-owned | readers observe the matching barrier phase before `tcgen05.ld` |\n| epilogue-owned → free | all collective loads complete with `tcgen05.wait::ld`, then every reader reports completion |\n\nTMEM must first be allocated by the required participating warp and its address safely published. Matching collective deallocation is required before every kernel exit. Reused mbarriers need the correct arrival count and phase/parity state; a one-time wait on an address is not a reusable two-buffer protocol."}, "reason": {"statement": "Replace unsafe pseudo-implementation with verified ownership invariants and a pinned complete implementation route.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "A fully optimized Blackwell GEMM uses both levels simultaneously:"}, "after": {"statement": "Double- or multi-buffering reserves disjoint storage regions and transfers ownership between producers and consumers. While a consumer reads stage `s`, a producer may fill another stage. The storage alone does not establish overlap: the program also needs a completion edge before consumption and a read-complete edge before reuse.\n\nOn SM100 these ideas can be applied independently:\n\n- SMEM stages can hold operand tiles while TMA production overlaps MMA consumption.\n- Separate TMEM regions can hold output accumulators while an epilogue drains a completed region and MMA writes a different region.\n\nThe pinned `matmul_v6.cu` from Gau Nernst's tutorial uses both mechanisms. That is a concrete design, not a rule that every optimized Blackwell GEMM needs both.\n\nThat is not a complete C++ shared-storage layout. Barriers, descriptors, epilogue scratch, padding, alignment, and swizzled physical layouts also consume or constrain shared memory. Compute capability 10.0 supports up to 228 KiB of shared memory per SM, while per-block opt-in limits and all other residency resources still apply."}, "reason": {"statement": "Scope the combination to concrete kernels and tuning conditions.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "```cuda\n// Combined double-buffering: SMEM (3-stage) + TMEM (2-buffer)\n//\n// Outer loop: output tiles (TMEM double-buffered)\n// Inner loop: K-tiles (SMEM 3-stage pipelined)\n//\n// Timeline for 2 output tiles, 6 K-tiles each:\n//\n// TMEM buf: |---- A (tile 0) ----|---- B (tile 1) ----|\n// MMA warp: | k0 k1 k2 k3 k4 k5 | k0 k1 k2 ...\n// TMA warp: |k2 k3 k4 k5 - - k2 k3 k4 k5 ...\n// Epilogue: | idle | drain A | drain B |\n// SMEM stage: |0 1 2 0 1 2 |0 1 2 0 1 2 |\n//\n// Key insight: the epilogue of tile 0 overlaps with the MMA of tile 1.\n// This is only possible because they use different TMEM buffers.\n\n__device__ void full_double_buffered_gemm(const GemmParams& params) {\n int warp_id = threadIdx.x / 32;\n\n for (int out_tile = 0; out_tile < num_output_tiles; out_tile++) {\n int tmem_buf = out_tile % 2;\n\n if (warp_id == 0) {\n // TMA producer: fill SMEM stages for this output tile's K-loop\n tma_producer_loop(params, out_tile);\n } else if (warp_id == 1) {\n // MMA: consume SMEM stages, accumulate into TMEM[tmem_buf]\n mma_consumer_loop(params, tmem_buf);\n } else {\n // Epilogue: drain TMEM[1-tmem_buf] from previous tile\n if (out_tile > 0) {\n epilogue_drain(params, out_tile - 1, 1 - tmem_buf);\n }\n }\n\n // Lightweight sync point between tiles\n // (mbarrier-based, not __syncthreads)\n }\n\n // Final epilogue for last tile\n if (warp_id >= 2) {\n epilogue_drain(params, num_output_tiles - 1,\n (num_output_tiles - 1) % 2);\n }\n}\n```"}, "after": {"statement": "For each region, prove this lifecycle:\n\n| free → MMA-owned | every prior epilogue load from the region has completed |\n| MMA-owned → ready | relevant tcgen05 work is committed to an mbarrier and completion is observed |\n| ready → epilogue-owned | readers observe the matching barrier phase before `tcgen05.ld` |\n| epilogue-owned → free | all collective loads complete with `tcgen05.wait::ld`, then every reader reports completion |\n\nTMEM must first be allocated by the required participating warp and its address safely published. Matching collective deallocation is required before every kernel exit. Reused mbarriers need the correct arrival count and phase/parity state; a one-time wait on an address is not a reusable two-buffer protocol.\n\nAn SMEM operand stage normally has its own full/empty state:\n\n1. The producer waits until stage `s` is empty.\n2. It issues the stage's TMA copies and accounts for expected transaction bytes.\n3. The consumer observes the full barrier's matching phase before using the stage.\n4. After the final dependent read, the consumer releases the empty barrier for reuse.\n\nFlashInfer PR 2387 is a second pinned example. Its merged `selective_state_update.cuh` has `state[numStages][...]` plus `bar_full` and `bar_empty` arrays and uses stage-specific producer/consumer handoffs. One path selects three stages and another caps a geometry-derived count at four, illustrating why stage count is policy rather than an architecture-wide default."}, "reason": {"statement": "Use a state/ownership table instead of incomplete CUDA.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "```cuda\n// Hopper: accumulator double-buffering uses register arrays\n// Each warpgroup maintains two register-based accumulators\n// This doubles register pressure and reduces occupancy\n\n// Hopper approach (register pressure is the primary constraint):\nfloat acc_buf0[REG_TILE_M][REG_TILE_N]; // First accumulator\nfloat acc_buf1[REG_TILE_M][REG_TILE_N]; // Second accumulator\n// Total: 2 * REG_TILE_M * REG_TILE_N * 4 bytes per thread\n// For a 64x256 tile with 128-thread warpgroup:\n// each thread holds 2 * (64/4) * (256/128) * 4 = 2 * 16 * 2 * 4 = 256 bytes\n// = 64 registers just for accumulators\n\n// Blackwell approach: TMEM holds both buffers with zero register cost\n// MMA warp uses ~0 registers for accumulators\n// All 256 KB of TMEM is dedicated accumulator space\n```"}, "after": {"statement": "For binary16 `A[128,64]` and `B[64,256]`, the unpadded payload arithmetic is:\n\n```text\nA = 128 × 64 × 2 bytes = 16 KiB\nB = 64 × 256 × 2 bytes = 32 KiB\none stage = 48 KiB; three stages = 144 KiB\n```"}, "reason": {"statement": "Replace incorrect arithmetic and reject zero total-register cost.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "| Double-buffer cost | 2x register usage | Zero register cost |"}, "after": {"statement": "For binary16 `A[128,64]` and `B[64,256]`, the unpadded payload arithmetic is:\n\n```text\nA = 128 × 64 × 2 bytes = 16 KiB\nB = 64 × 256 × 2 bytes = 32 KiB\none stage = 48 KiB; three stages = 144 KiB\n```"}, "reason": {"statement": "Narrow the comparison to resident accumulator storage.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "| Typical occupancy impact | Reduces from 2 to 1 CTA/SM | No impact |"}, "after": {"statement": "For Hopper `wgmma.mma_async.m64nNk16` with FP32 D, each warpgroup thread holds `N/2` accumulator registers. At `N=256`, one D fragment is 128 registers per thread; two simultaneously live fragments are 256 registers, or 1024 bytes, per thread before other live values. That arithmetic describes the ISA fragment, not a promise that a C++ array stays in registers or that a particular launch is resident.\n\nOn SM100, tcgen05 keeps resident D in TMEM. This avoids a long-lived per-thread D vector, but the kernel still uses registers for addresses, descriptors, loop and barrier state, `tcgen05.ld` destinations, and epilogue temporaries. TMEM buffering also consumes TMEM capacity and synchronization state. Neither architecture therefore has a fixed occupancy result from “double buffering” alone.\n\n| Resident storage | per-thread register fragment | allocated TMEM region |\n| Two live outputs | two disjoint register fragments | two disjoint TMEM regions |\n| Epilogue access | dependent use after WGMMA completion | collective `tcgen05.ld` and `tcgen05.wait::ld` after MMA completion |\n| Main resource question | compiled registers, SMEM, block shape, and other limits | TMEM columns plus compiled registers, SMEM, block/cluster shape, and other limits |"}, "reason": {"statement": "Unsupported occupancy numbers cannot guide a real launch.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "| Max accumulator size | ~16K elements (register limited) | 128x512 = 65K elements |"}, "after": {"statement": "For binary16 `A[128,64]` and `B[64,256]`, the unpadded payload arithmetic is:\n\n```text\nA = 128 × 64 × 2 bytes = 16 KiB\nB = 64 × 256 × 2 bytes = 32 KiB\none stage = 48 KiB; three stages = 144 KiB\n```\n\nFor Hopper `wgmma.mma_async.m64nNk16` with FP32 D, each warpgroup thread holds `N/2` accumulator registers. At `N=256`, one D fragment is 128 registers per thread; two simultaneously live fragments are 256 registers, or 1024 bytes, per thread before other live values. That arithmetic describes the ISA fragment, not a promise that a C++ array stays in registers or that a particular launch is resident.\n\nOn SM100, tcgen05 keeps resident D in TMEM. This avoids a long-lived per-thread D vector, but the kernel still uses registers for addresses, descriptors, loop and barrier state, `tcgen05.ld` destinations, and epilogue temporaries. TMEM buffering also consumes TMEM capacity and synchronization state. Neither architecture therefore has a fixed occupancy result from “double buffering” alone.\n\n| Resident storage | per-thread register fragment | allocated TMEM region |\n| Two live outputs | two disjoint register fragments | two disjoint TMEM regions |\n| Epilogue access | dependent use after WGMMA completion | collective `tcgen05.ld` and `tcgen05.wait::ld` after MMA completion |\n| Main resource question | compiled registers, SMEM, block shape, and other limits | TMEM columns plus compiled registers, SMEM, block/cluster shape, and other limits |"}, "reason": {"statement": "Avoid conflating an instruction fragment or storage geometry with a practical kernel maximum.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-instructions-wgmma-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "- **TMEM double-buffering**: Always use on Blackwell when the epilogue takes more than trivial time. The only cost is the TMEM space, which is plentiful."}, "after": {"statement": "For Hopper `wgmma.mma_async.m64nNk16` with FP32 D, each warpgroup thread holds `N/2` accumulator registers. At `N=256`, one D fragment is 128 registers per thread; two simultaneously live fragments are 256 registers, or 1024 bytes, per thread before other live values. That arithmetic describes the ISA fragment, not a promise that a C++ array stays in registers or that a particular launch is resident.\n\nOn SM100, tcgen05 keeps resident D in TMEM. This avoids a long-lived per-thread D vector, but the kernel still uses registers for addresses, descriptors, loop and barrier state, `tcgen05.ld` destinations, and epilogue temporaries. TMEM buffering also consumes TMEM capacity and synchronization state. Neither architecture therefore has a fixed occupancy result from “double buffering” alone.\n\n| Resident storage | per-thread register fragment | allocated TMEM region |\n| Two live outputs | two disjoint register fragments | two disjoint TMEM regions |\n| Epilogue access | dependent use after WGMMA completion | collective `tcgen05.ld` and `tcgen05.wait::ld` after MMA completion |\n| Main resource question | compiled registers, SMEM, block shape, and other limits | TMEM columns plus compiled registers, SMEM, block/cluster shape, and other limits |"}, "reason": {"statement": "Make adoption conditional on measured overlap benefit and resource fit.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "- **SMEM multi-stage buffering**: Always use for GEMM/attention mainloops. 3 stages is the default; increase to 4-5 only if the K-loop is long and memory latency is high."}, "after": {"statement": "That is not a complete C++ shared-storage layout. Barriers, descriptors, epilogue scratch, padding, alignment, and swizzled physical layouts also consume or constrain shared memory. Compute capability 10.0 supports up to 228 KiB of shared memory per SM, while per-block opt-in limits and all other residency resources still apply.\n\nFor Hopper `wgmma.mma_async.m64nNk16` with FP32 D, each warpgroup thread holds `N/2` accumulator registers. At `N=256`, one D fragment is 128 registers per thread; two simultaneously live fragments are 256 registers, or 1024 bytes, per thread before other live values. That arithmetic describes the ISA fragment, not a promise that a C++ array stays in registers or that a particular launch is resident.\n\nOn SM100, tcgen05 keeps resident D in TMEM. This avoids a long-lived per-thread D vector, but the kernel still uses registers for addresses, descriptors, loop and barrier state, `tcgen05.ld` destinations, and epilogue temporaries. TMEM buffering also consumes TMEM capacity and synchronization state. Neither architecture therefore has a fixed occupancy result from “double buffering” alone.\n\n| Resident storage | per-thread register fragment | allocated TMEM region |\n| Two live outputs | two disjoint register fragments | two disjoint TMEM regions |\n| Epilogue access | dependent use after WGMMA completion | collective `tcgen05.ld` and `tcgen05.wait::ld` after MMA completion |\n| Main resource question | compiled registers, SMEM, block shape, and other limits | TMEM columns plus compiled registers, SMEM, block/cluster shape, and other limits |"}, "reason": {"statement": "Replace a universal recipe with resource- and workload-dependent tuning.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "- **Combined**: The standard approach for production Blackwell GEMM kernels. Both CUTLASS and CuTe-DSL kernels use this pattern."}, "after": {"statement": "That is not a complete C++ shared-storage layout. Barriers, descriptors, epilogue scratch, padding, alignment, and swizzled physical layouts also consume or constrain shared memory. Compute capability 10.0 supports up to 228 KiB of shared memory per SM, while per-block opt-in limits and all other residency resources still apply."}, "reason": {"statement": "Use concrete, pinned examples rather than ecosystem-wide attribution.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "- TMEM double-buffering requires that the accumulator fits in half the TMEM columns (256 out of 512). For very wide tiles (TILE_N > 256 with FP32 accumulators), the tile must be split or a different buffering strategy used."}, "after": {"statement": "The CTA-visible TMEM address structure has 128 lanes and 512 columns of 32-bit cells. Allocation is column-granular across all 128 lanes. A kernel that allocates 512 columns may choose two 256-column regions:\n\n```text\nregion[0] = columns [0, 256)\nregion[1] = columns [256, 512)\n```\n\nThis equal split is one implementation choice. The actual invariant is that every simultaneously live region is inside the allocation and does not alias another region whose MMA or epilogue access is still outstanding. Region sizes can differ, and logical element capacity depends on the tcgen05 instruction kind and packing rather than the raw cell count alone.\n\nFor Hopper `wgmma.mma_async.m64nNk16` with FP32 D, each warpgroup thread holds `N/2` accumulator registers. At `N=256`, one D fragment is 128 registers per thread; two simultaneously live fragments are 256 registers, or 1024 bytes, per thread before other live values. That arithmetic describes the ISA fragment, not a promise that a C++ array stays in registers or that a particular launch is resident.\n\nOn SM100, tcgen05 keeps resident D in TMEM. This avoids a long-lived per-thread D vector, but the kernel still uses registers for addresses, descriptors, loop and barrier state, `tcgen05.ld` destinations, and epilogue temporaries. TMEM buffering also consumes TMEM capacity and synchronization state. Neither architecture therefore has a fixed occupancy result from “double buffering” alone.\n\n| Resident storage | per-thread register fragment | allocated TMEM region |\n| Two live outputs | two disjoint register fragments | two disjoint TMEM regions |\n| Epilogue access | dependent use after WGMMA completion | collective `tcgen05.ld` and `tcgen05.wait::ld` after MMA completion |\n| Main resource question | compiled registers, SMEM, block shape, and other limits | TMEM columns plus compiled registers, SMEM, block/cluster shape, and other limits |"}, "reason": {"statement": "State the actual nonaliasing/capacity invariant and label 256/256 as one choice.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory-allocation", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/double-buffering.md", "before": {"statement": "- The mbarrier synchronization between TMEM buffers adds a few cycles of overhead per tile. For kernels with very few K-iterations per tile, this overhead is proportionally larger."}, "after": {"statement": "For Hopper `wgmma.mma_async.m64nNk16` with FP32 D, each warpgroup thread holds `N/2` accumulator registers. At `N=256`, one D fragment is 128 registers per thread; two simultaneously live fragments are 256 registers, or 1024 bytes, per thread before other live values. That arithmetic describes the ISA fragment, not a promise that a C++ array stays in registers or that a particular launch is resident.\n\nOn SM100, tcgen05 keeps resident D in TMEM. This avoids a long-lived per-thread D vector, but the kernel still uses registers for addresses, descriptors, loop and barrier state, `tcgen05.ld` destinations, and epilogue temporaries. TMEM buffering also consumes TMEM capacity and synchronization state. Neither architecture therefore has a fixed occupancy result from “double buffering” alone.\n\n| Resident storage | per-thread register fragment | allocated TMEM region |\n| Two live outputs | two disjoint register fragments | two disjoint TMEM regions |\n| Epilogue access | dependent use after WGMMA completion | collective `tcgen05.ld` and `tcgen05.wait::ld` after MMA completion |\n| Main resource question | compiled registers, SMEM, block shape, and other limits | TMEM columns plus compiled registers, SMEM, block/cluster shape, and other limits |"}, "reason": {"statement": "Retain the need to measure synchronization overhead without inventing latency.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "Epilogue fusion overlaps the post-MMA operations (scaling, bias addition, activation functions, quantization, store to global memory) with ongoing MMA computation. On Blackwell, the accumulator lives in TMEM rather than registers, enabling dedicated epilogue warps (typically warps 2-15) to read TMEM concurrently while the MMA warp (warp 1) continues accumulating the next tile. This overlap is achieved by double-buffering the TMEM accumulator: the MMA warp writes to one half while the epilogue warps read from the other half."}, "after": {"statement": "Epilogue fusion computes output transformations—such as `alpha*acc + beta*C`, bias, activation, output conversion, or auxiliary values—inside the producer kernel before final output materialization. It can remove an intermediate tensor or launch only when the unfused comparison would otherwise materialize or launch that work.\n\nFusion does not by itself imply overlap with the next MMA tile. A schedule may drain one completed accumulator after the mainloop, or it may use disjoint storage and specialized roles to overlap a completed region's epilogue with independent MMA work. Participant counts and role IDs come from the concrete kernel; there is no architectural default of fourteen epilogue warps."}, "reason": {"statement": "Separate semantic fusion from optional schedule overlap.", "urls": []}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "```cuda\n// Epilogue warp: read TMEM accumulator, apply fused operations, store\n// This runs on warps 2-15 while warp 1 continues MMA on next tile\n__device__ void epilogue_warp_fn(\n int warp_id,\n int tile_m, int tile_n,\n float scale, const float* bias,\n half* C, int ldc)\n{\n int lane_id = threadIdx.x % 32;\n\n // Each epilogue warp handles a stripe of the output tile\n // 14 warps, TILE_M = 128 -> ~9 rows per warp\n int rows_per_warp = (TILE_M + 13) / 14;\n int row_start = (warp_id - 2) * rows_per_warp;\n int row_end = min(row_start + rows_per_warp, TILE_M);\n\n for (int r = row_start; r < row_end; r++) {\n int global_row = tile_m * TILE_M + r;\n\n for (int c = lane_id; c < TILE_N; c += 32) {\n // Step 1: Load accumulator from TMEM into register\n float acc = tmem_load_f32(r, c);\n\n // Step 2: Fused epilogue operations (all in registers)\n // Scale\n acc *= scale;\n // Bias\n acc += bias[tile_n * TILE_N + c];\n // ReLU activation\n acc = fmaxf(acc, 0.0f);\n\n // Step 3: Store to global memory\n int global_col = tile_n * TILE_N + c;\n C[global_row * ldc + global_col] = __float2half(acc);\n }\n }\n}\n```"}, "after": {"statement": "For tcgen05, D resides in TMEM. An ordinary arithmetic epilogue first uses a legal collective `tcgen05.ld` mapping, or a library wrapper around it, to transfer a partition into per-thread registers. The load is asynchronous with respect to the issuing thread, so the matching `tcgen05.wait::ld` completion must occur before those registers are consumed.\n\nCUTLASS 4.5.0's `fp16_gemm_2.py` demonstrates the typed route:\n\n```python\ncopy_atom_t2r = cute.make_copy_atom(\n tcgen05.Ld32x32bOp(tcgen05.Repetition.x32), cutlass.Float32\n)\ntiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tCtAcc_epi)\nthr_copy_t2r = tiled_copy_t2r.get_slice(tidx)\ntTR_tAcc = thr_copy_t2r.partition_S(tCtAcc_epi)\ntTR_rAcc = cute.make_rmem_tensor(..., cutlass.Float32)\ncute.copy(tiled_copy_t2r, tTR_tAcc_slice, tTR_rAcc)\n```\n\nThis is an API-routing fragment, not standalone code: the official file supplies the exact tensor layouts, selected load shape, participant group, edge predicates, accumulator-completion handoff, register-to-SMEM conversion, TMA-store pipeline, tail, and TMEM cleanup.\n\n| tcgen05 MMA → TMEM reader | the relevant asynchronous MMA is committed and its completion observed |\n| TMEM → result registers | the legal collective load completes before dependent arithmetic |\n| registers → output | element/layout mapping and output-edge predicates cover exactly the valid coordinates |\n| TMEM reader → region reuse | every reader's load has completed and the matching reusable barrier phase is released |\n| kernel tail | all output stores complete as required and every TMEM allocation is collectively freed |\n\nFor a multi-region overlap schedule, simultaneously live TMEM regions must also be disjoint. Equal 256-column halves are one possible policy for a 512-column allocation, not an epilogue-fusion requirement. Reusable mbarriers need correct expected-arrival counts and phase/parity tracking."}, "reason": {"statement": "Replace pseudo-CUDA with exact lifecycle and official CuTe copy-route identifiers.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "The key to epilogue fusion on Blackwell is TMEM double-buffering. The 512-column TMEM space is split into two halves (columns 0-255 and 256-511). While the MMA warp accumulates into one half, the epilogue warps drain the other:"}, "after": {"statement": "Epilogue fusion computes output transformations—such as `alpha*acc + beta*C`, bias, activation, output conversion, or auxiliary values—inside the producer kernel before final output materialization. It can remove an intermediate tensor or launch only when the unfused comparison would otherwise materialize or launch that work.\n\nFusion does not by itself imply overlap with the next MMA tile. A schedule may drain one completed accumulator after the mainloop, or it may use disjoint storage and specialized roles to overlap a completed region's epilogue with independent MMA work. Participant counts and role IDs come from the concrete kernel; there is no architectural default of fourteen epilogue warps.\n\n| tcgen05 MMA → TMEM reader | the relevant asynchronous MMA is committed and its completion observed |\n| TMEM → result registers | the legal collective load completes before dependent arithmetic |\n| registers → output | element/layout mapping and output-edge predicates cover exactly the valid coordinates |\n| TMEM reader → region reuse | every reader's load has completed and the matching reusable barrier phase is released |\n| kernel tail | all output stores complete as required and every TMEM allocation is collectively freed |\n\nFor a multi-region overlap schedule, simultaneously live TMEM regions must also be disjoint. Equal 256-column halves are one possible policy for a 512-column allocation, not an epilogue-fusion requirement. Reusable mbarriers need correct expected-arrival counts and phase/parity tracking."}, "reason": {"statement": "Make multi-region overlap optional and state nonaliasing constraints.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "```cuda\n// TMEM double-buffering for MMA-epilogue overlap\n//\n// TMEM layout: 128 rows x 512 columns (32-bit elements)\n// Buffer A: columns [0, 255] -- 128 x 256 accumulator\n// Buffer B: columns [256, 511] -- 128 x 256 accumulator\n//\n// Timeline:\n// Tile 0: MMA -> buffer A | epilogue idle (no prior result)\n// Tile 1: MMA -> buffer B | epilogue reads buffer A\n// Tile 2: MMA -> buffer A | epilogue reads buffer B\n// Tile 3: MMA -> buffer B | epilogue reads buffer A\n// ... ping-pong continues ...\n\n__device__ void mma_epilogue_overlap(\n const GemmParams& params,\n int num_tiles)\n{\n int warp_id = threadIdx.x / 32;\n\n __shared__ uint64_t mbar_mma_done[2]; // One per TMEM buffer half\n __shared__ uint64_t mbar_epi_done[2]; // Epilogue completion signals\n\n if (threadIdx.x == 0) {\n for (int i = 0; i < 2; i++) {\n mbarrier_init(&mbar_mma_done[i], 1);\n mbarrier_init(&mbar_epi_done[i], 1);\n }\n }\n __syncthreads();\n\n if (warp_id == 1) {\n // === MMA WARP ===\n for (int t = 0; t < num_tiles; t++) {\n int buf = t % 2; // Alternate between buffer halves\n\n // Wait for epilogue to finish reading this buffer\n if (t >= 2) {\n mbarrier_wait(&mbar_epi_done[buf]);\n }\n\n // Issue MMA, accumulating into TMEM buffer half\n int tmem_col_offset = buf * 256;\n tcgen05_mma_with_offset(tmem_col_offset,\n params.smem_A, params.smem_B);\n\n // Signal epilogue that this buffer is ready\n mbarrier_arrive(&mbar_mma_done[buf]);\n }\n\n } else if (warp_id >= 2) {\n // === EPILOGUE WARPS ===\n for (int t = 0; t < num_tiles; t++) {\n int buf = t % 2;\n\n // Wait for MMA to finish filling this buffer\n mbarrier_wait(&mbar_mma_done[buf]);\n\n // Read from TMEM buffer half and write to global memory\n int tmem_col_offset = buf * 256;\n epilogue_store(params, t, tmem_col_offset, warp_id);\n\n // ALL epilogue warps must finish reading TMEM before MMA reuses\n // the buffer. Each epilogue warp arrives on mbar_epi_done;\n // mbar_epi_done is initialized with count = NUM_EPILOGUE_WARPS.\n // MMA warp waits on this mbarrier before writing to this half.\n if (lane_id == 0) {\n mbarrier_arrive(&mbar_epi_done[buf]);\n }\n // mbar_epi_done[buf] fires only after ALL epilogue warps arrive\n }\n }\n}\n```"}, "after": {"statement": "| tcgen05 MMA → TMEM reader | the relevant asynchronous MMA is committed and its completion observed |\n| TMEM → result registers | the legal collective load completes before dependent arithmetic |\n| registers → output | element/layout mapping and output-edge predicates cover exactly the valid coordinates |\n| TMEM reader → region reuse | every reader's load has completed and the matching reusable barrier phase is released |\n| kernel tail | all output stores complete as required and every TMEM allocation is collectively freed |\n\nFor a multi-region overlap schedule, simultaneously live TMEM regions must also be disjoint. Equal 256-column halves are one possible policy for a 512-column allocation, not an epilogue-fusion requirement. Reusable mbarriers need correct expected-arrival counts and phase/parity tracking."}, "reason": {"statement": "Replace incomplete code with a required-edge table and negative tests.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "CUTLASS 4.5.0 provides composable epilogue visitors that fuse arbitrary element-wise operations after GEMM:"}, "after": {"statement": "`cutlass::epilogue::fusion::LinCombEltAct` has this parameter order:\n\n```cpp\ntemplate <\n template class ActivationFn,\n class ElementOutput,\n class ElementCompute,\n class ElementSource = ElementOutput,\n class ElementScalar = ElementCompute,\n cutlass::FloatRoundStyle Round = cutlass::FloatRoundStyle::round_to_nearest>\nstruct LinCombEltAct;\n```\n\nFor SM100 construction, `cutlass::epilogue::collective::CollectiveBuilder` receives architecture, operator class, tile/cluster shapes, `EpilogueTileAuto` or an explicit epilogue tile, accumulator/compute/C/D types and layouts, alignment, `EpilogueScheduleAuto` or an explicit supported schedule, and finally a supported fusion operation or callbacks type.\n\nThere is no CUTLASS 4.5.0 type named `Sm100EpilogueTmaWarpSpecialized`. Support is constrained by the exact architecture, operator class, schedule, tile, layout, alignment, datatype, and fusion callback combination. Use `Gemm::can_implement(arguments)` and a tagged example rather than reconstructing a builder signature from prose.\n\nThe vLLM PR 16032 NVFP4 wrapper is one pinned C++ construction example: it uses `CollectiveBuilder<... EpilogueTileAuto, ... EpilogueScheduleAuto>` and derives mainloop shared-memory stages with `StageCountAutoCarveout`."}, "reason": {"statement": "Describe the exact supported operation-tag/callback interface.", "urls": []}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "```cuda\n// CUTLASS SM100 epilogue with fused scale + bias + activation\n// Uses the EVT (Epilogue Visitor Tree) pattern\n\nusing EpilogueOp = cutlass::epilogue::fusion::LinCombEltAct<\n cutlass::epilogue::thread::ReLU, // Activation function\n float, // Compute type\n float, // Scale type\n cutlass::half_t // Output type\n>;\n\n// The epilogue descriptor tells CUTLASS how to partition work\n// across the 14 epilogue warps\nusing CollectiveEpilogue = cutlass::epilogue::collective::Sm100EpilogueTmaWarpSpecialized<\n cutlass::gemm::TagToStrideC_t,\n cutlass::gemm::TagToStrideC_t,\n EpilogueOp,\n cutlass::gemm::EpilogueDefault // Default tiling\n>;\n\n// In the kernel, the epilogue is invoked after the mainloop:\n// epilogue(\n// problem_shape,\n// collective_mainloop.get_accumulator(), // TMEM reference\n// epilogue_params, // scale, bias pointers\n// shared_storage // SMEM for TMA stores\n// );\n```"}, "after": {"statement": "`cutlass::epilogue::fusion::LinCombEltAct` has this parameter order:\n\n```cpp\ntemplate <\n template class ActivationFn,\n class ElementOutput,\n class ElementCompute,\n class ElementSource = ElementOutput,\n class ElementScalar = ElementCompute,\n cutlass::FloatRoundStyle Round = cutlass::FloatRoundStyle::round_to_nearest>\nstruct LinCombEltAct;\n```\n\nFor SM100 construction, `cutlass::epilogue::collective::CollectiveBuilder` receives architecture, operator class, tile/cluster shapes, `EpilogueTileAuto` or an explicit epilogue tile, accumulator/compute/C/D types and layouts, alignment, `EpilogueScheduleAuto` or an explicit supported schedule, and finally a supported fusion operation or callbacks type.\n\nThere is no CUTLASS 4.5.0 type named `Sm100EpilogueTmaWarpSpecialized`. Support is constrained by the exact architecture, operator class, schedule, tile, layout, alignment, datatype, and fusion callback combination. Use `Gemm::can_implement(arguments)` and a tagged example rather than reconstructing a builder signature from prose.\n\nThe vLLM PR 16032 NVFP4 wrapper is one pinned C++ construction example: it uses `CollectiveBuilder<... EpilogueTileAuto, ... EpilogueScheduleAuto>` and derives mainloop shared-memory stages with `StageCountAutoCarveout`."}, "reason": {"statement": "Replace invented code with exact version-pinned type signatures and a real builder example route.", "urls": []}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "| Scale + Bias | `y = alpha * acc + beta * C` | Standard GEMM epilogue |"}, "after": {"statement": "| Source linear combination | `D = alpha*acc + beta*C` |\n| Per-row/per-column bias | add a separately laid-out broadcast bias input |\n| Activation | apply a supported functor such as ReLU, GELU, or SiLU to the output fragment |\n| Output conversion/quantization | convert the accumulator fragment and, when required, generate/store scale metadata |\n| Gated product | combine two values, for example `SiLU(gate) * up`; requires both inputs and a supported/custom callback |\n| Online-softmax rescale | rescale a prior partial output after a new row maximum; requires the attention reduction state |\n| Residual | combine a separately supplied residual/source tensor at the defined point in the expression tree |\n\nThese are operation categories, not a claim that every composition is supported by one built-in SM100 visitor. In particular, reductions, multiple outputs, auxiliary tensors, and broadcasts add synchronization and layout requirements beyond a pointwise activation."}, "reason": {"statement": "Separate source linear combination from explicit bias broadcasting.", "urls": []}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "- **All Blackwell GEMMs with non-trivial epilogues**: The 14 epilogue warps are available by default in the warp-specialized model. Fusing operations avoids a separate kernel launch and an extra global memory round-trip."}, "after": {"statement": "When an implementation overlaps the epilogue with independent MMA work, verify both directions of the handoff: compute-complete before read, and load/read-complete before overwrite. Include the prologue (no prior result), steady-state wraparound, final drain, and deallocation path in tests.\n\nEvaluate a defined fused/unfused pair with identical inputs, output semantics, launch policy, warmup, and timing statistics. Record registers, spills, SMEM, TMEM columns, barriers, threads/CTA, cluster shape, and occupancy. Sweep supported epilogue group sizes, load shapes, output tiles, and store stages. The PTX ISA defines no equal-share bandwidth model for a fixed number of epilogue warps; diagnose TMEM-load, conversion, barrier, and store bottlenecks with generated code and profiler data.\n\nFusing output conversion can avoid a global FP32 intermediate when the baseline would write and reread that intermediate. It does not guarantee a speedup: added registers, shared-memory staging, synchronization, edge handling, or reduced occupancy can outweigh saved traffic.\n\nUseful negative tests delay one reader, skip a barrier phase, reuse a TMEM region early, omit the final store tail, and exercise partial M/N tiles. Each fault should be detected by output comparison or a bounded watchdog."}, "reason": {"statement": "Replace universal role count and benefit with configuration-specific evaluation.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "- TMEM-to-register bandwidth is not unlimited. With 14 warps simultaneously reading TMEM, each warp gets a proportional share. Very wide output tiles (large TILE_N) may bottleneck on TMEM read bandwidth."}, "after": {"statement": "When an implementation overlaps the epilogue with independent MMA work, verify both directions of the handoff: compute-complete before read, and load/read-complete before overwrite. Include the prologue (no prior result), steady-state wraparound, final drain, and deallocation path in tests.\n\nEvaluate a defined fused/unfused pair with identical inputs, output semantics, launch policy, warmup, and timing statistics. Record registers, spills, SMEM, TMEM columns, barriers, threads/CTA, cluster shape, and occupancy. Sweep supported epilogue group sizes, load shapes, output tiles, and store stages. The PTX ISA defines no equal-share bandwidth model for a fixed number of epilogue warps; diagnose TMEM-load, conversion, barrier, and store bottlenecks with generated code and profiler data.\n\nFusing output conversion can avoid a global FP32 intermediate when the baseline would write and reread that intermediate. It does not guarantee a speedup: added registers, shared-memory staging, synchronization, edge handling, or reduced occupancy can outweigh saved traffic.\n\nUseful negative tests delay one reader, skip a barrier phase, reuse a TMEM region early, omit the final store tail, and exercise partial M/N tiles. Each fault should be detected by output comparison or a bounded watchdog."}, "reason": {"statement": "Require profiler and variant measurements for bandwidth diagnosis.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "- Simple epilogues (just store) waste the 14 epilogue warps. For such cases, consider reducing the CTA size or assigning epilogue warps to other work (e.g., next-tile TMA prefetch)."}, "after": {"statement": "When an implementation overlaps the epilogue with independent MMA work, verify both directions of the handoff: compute-complete before read, and load/read-complete before overwrite. Include the prologue (no prior result), steady-state wraparound, final drain, and deallocation path in tests.\n\nEvaluate a defined fused/unfused pair with identical inputs, output semantics, launch policy, warmup, and timing statistics. Record registers, spills, SMEM, TMEM columns, barriers, threads/CTA, cluster shape, and occupancy. Sweep supported epilogue group sizes, load shapes, output tiles, and store stages. The PTX ISA defines no equal-share bandwidth model for a fixed number of epilogue warps; diagnose TMEM-load, conversion, barrier, and store bottlenecks with generated code and profiler data.\n\nFusing output conversion can avoid a global FP32 intermediate when the baseline would write and reread that intermediate. It does not guarantee a speedup: added registers, shared-memory staging, synchronization, edge handling, or reduced occupancy can outweigh saved traffic.\n\nUseful negative tests delay one reader, skip a barrier phase, reuse a TMEM region early, omit the final store tail, and exercise partial M/N tiles. Each fault should be detected by output comparison or a bounded watchdog."}, "reason": {"statement": "Use measured role-count and store-path bottlenecks.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/epilogue-fusion.md", "before": {"statement": "Verbatim upstream code lives in [`artifacts/kernels/epilogue-fusion/full/`](../../artifacts/kernels/epilogue-fusion/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live in [`artifacts/kernels/epilogue-fusion/variants/`](../../artifacts/kernels/epilogue-fusion/variants/). Every file's SHA-256 and upstream-pinning metadata is in `PROVENANCE.yaml` inside each bundle."}, "after": {"statement": "The artifact bundle contains mixed provenance modes:\n\n- `full/nvfp4_scaled_mm_kernels.cu` is verbatim from vLLM merge `ed7a29d9f8b48978e3bbf43599d21b4de65387e0` and byte-matches SHA-256 `e8aed5ccb3dd9de26c3aeff159a242a46dcb7c7d8d0351b6c44ff1f8d2f7effa`.\n- `full/tmem-load-into-registers-for-epilogue.cu` is an extracted historical snippet from a local source card; it is not an upstream-verbatim kernel and must not be treated as standalone safe code.\n- `variants/01-double-buffered-tmem-epilogue-skeleton.cu` is explicitly labeled derived/not-upstream and is incomplete pseudocode.\n\nRetrieve the page and bundle with:\n\n```bash\nconda run -n base python scripts/get_page.py technique-epilogue-fusion --include-code\n```"}, "reason": {"statement": "Describe each artifact's actual provenance mode and warn that extracted/derived snippets are not safe standalone kernels.", "urls": []}} +{"path": "wiki/techniques/persistent-kernels.md", "before": {"statement": "Persistent kernels launch exactly as many CTAs as SMs, and each CTA processes multiple output tiles in a loop rather than exiting after one tile. On Blackwell, the CLC (Cluster Launch Control) hardware unit replaces software-based tile scheduling with a hardware-assisted mechanism. Each CTA queries the CLC for its next tile assignment and can cancel itself when no work remains, using the `try_cancel` pattern."}, "after": {"statement": "A persistent kernel keeps a resident worker alive for multiple logical work items. Its launch size is chosen from the problem decomposition, cluster shape, resource limits, and scheduling policy; “persistent” does not require exactly one CTA per physical SM.\n\nCluster Launch Control is a compute-capability-10.0 mechanism for redistributing grid coordinates that have not started. A CLC GEMM still launches its problem-sized grid. Each ClcID is processed exactly once through one of two paths:\n\n1. A block or cluster launches normally and processes its initial `blockIdx`.\n2. A running worker successfully cancels another not-yet-started block/cluster and processes the returned coordinate.\n\nCLC does not create tiles, cancel the requesting worker, or chain independent problems. It can help when the SMs available to a grid are uneven, but it cannot expose more independent parallel work than exists in the launched grid."}, "reason": {"statement": "Restore problem-sized CLC grid and two-path ClcID model.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/techniques/persistent-kernels.md", "before": {"statement": "```cuda\n// Persistent kernel with CLC tile scheduling (Blackwell SM100)\n__global__ void __launch_bounds__(512)\npersistent_gemm_clc(const __grid_constant__ GemmParams params)\n{\n // CLC-managed persistent loop: each CTA processes multiple tiles\n while (true) {\n // Query CLC for next tile assignment\n // Returns tile coordinates (tile_m, tile_n) or signals termination\n TileCoord tile;\n bool has_work = clc_try_get_tile(&tile);\n\n if (!has_work) {\n // No more tiles to process -- CTA exits\n // clc_try_cancel atomically checks if all tiles are done\n if (clc_try_cancel()) {\n return; // CTA terminates\n }\n continue; // Race condition: another CTA may have generated work\n }\n\n // Standard GEMM tile computation\n int tile_m = tile.m;\n int tile_n = tile.n;\n\n // TMA producer loads A[tile_m, :] and B[:, tile_n] tiles\n // MMA consumer accumulates K-dimension\n // Epilogue writes C[tile_m, tile_n]\n compute_gemm_tile(params, tile_m, tile_n);\n }\n}\n```"}, "after": {"statement": "Cluster Launch Control is a compute-capability-10.0 mechanism for redistributing grid coordinates that have not started. A CLC GEMM still launches its problem-sized grid. Each ClcID is processed exactly once through one of two paths:\n\n1. A block or cluster launches normally and processes its initial `blockIdx`.\n2. A running worker successfully cancels another not-yet-started block/cluster and processes the returned coordinate.\n\nCLC does not create tiles, cancel the requesting worker, or chain independent problems. It can help when the SMs available to a grid are uneven, but it cannot expose more independent parallel work than exists in the launched grid.\n\nThe normative request is asynchronous and returns an opaque 16-byte shared-memory response:\n\n```ptx\nclusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [response], [mbar];\nclusterlaunchcontrol.query_cancel.is_canceled.pred.b128 p, response_b128;\n@p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {x, y, z, unused}, response_b128;\n```\n\nA complete implementation must initialize/publish the shared response and mbarrier, set the expected 16 transaction bytes, submit from the designated participant, wait for the matching phase, apply required proxy fences before reading/reusing the response, and decode a coordinate only when `is_canceled` succeeds.\n\nAfter a thread observes a failed request, another request from that thread is undefined. Failure is therefore not a “retry until another CTA creates work” condition; no CTA creates new ClcIDs.\n\nFor a thread-block cluster, one cluster participant submits the multicast request. Every CTA tracks completion at cluster scope, receives the same first coordinate, and adds its local block rank. Cluster synchronization is required before cancellation begins so all peers exist."}, "reason": {"statement": "Remove inverted/fabricated executable sketch.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/techniques/persistent-kernels.md", "before": {"statement": "At the PTX level, the CLC interaction is a cancel/query sequence. The exact\ninline PTX is usually hidden behind CUTLASS/CuTe wrappers, but the control flow\nlooks like this:\n\n```text\nTILE_LOOP:\n // Request cancellation of a not-yet-launched cluster.\n clusterlaunchcontrol.try_cancel(response_smem, mbarrier)\n wait(mbarrier)\n\n // Query the 16-byte response.\n has_work, tile_m, tile_n = clusterlaunchcontrol.query_cancel(response_smem)\n if (!has_work) return\n\n // ... compute tile ...\n goto TILE_LOOP\n```"}, "after": {"statement": "Cluster Launch Control is a compute-capability-10.0 mechanism for redistributing grid coordinates that have not started. A CLC GEMM still launches its problem-sized grid. Each ClcID is processed exactly once through one of two paths:\n\n1. A block or cluster launches normally and processes its initial `blockIdx`.\n2. A running worker successfully cancels another not-yet-started block/cluster and processes the returned coordinate.\n\nCLC does not create tiles, cancel the requesting worker, or chain independent problems. It can help when the SMs available to a grid are uneven, but it cannot expose more independent parallel work than exists in the launched grid.\n\nThe normative request is asynchronous and returns an opaque 16-byte shared-memory response:\n\n```ptx\nclusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [response], [mbar];\nclusterlaunchcontrol.query_cancel.is_canceled.pred.b128 p, response_b128;\n@p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {x, y, z, unused}, response_b128;\n```\n\nA complete implementation must initialize/publish the shared response and mbarrier, set the expected 16 transaction bytes, submit from the designated participant, wait for the matching phase, apply required proxy fences before reading/reusing the response, and decode a coordinate only when `is_canceled` succeeds.\n\nAfter a thread observes a failed request, another request from that thread is undefined. Failure is therefore not a “retry until another CTA creates work” condition; no CTA creates new ClcIDs.\n\nFor a thread-block cluster, one cluster participant submits the multicast request. Every CTA tracks completion at cluster scope, receives the same first coordinate, and adds its local block rank. Cluster synchronization is required before cancellation begins so all peers exist."}, "reason": {"statement": "Replace with complete invariants and exact PTX forms linked elsewhere.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/techniques/persistent-kernels.md", "before": {"statement": "| Scheduling | Software loop with fixed stride | Hardware CLC unit assigns tiles |\n| Load balancing | Fixed; uneven if tile costs vary | Dynamic; CLC rebalances automatically |\n| Tail effect | Last wave may have partial occupancy | CLC minimizes by giving fast CTAs more tiles |\n| Launch overhead | Grid launch for each new problem | CLC can chain multiple problems |\n| Termination | Implicit when loop ends | Explicit `try_cancel` |\n| L2 locality | Depends on stride pattern | CLC can apply swizzled raster |"}, "after": {"statement": "Cluster Launch Control is a compute-capability-10.0 mechanism for redistributing grid coordinates that have not started. A CLC GEMM still launches its problem-sized grid. Each ClcID is processed exactly once through one of two paths:\n\n1. A block or cluster launches normally and processes its initial `blockIdx`.\n2. A running worker successfully cancels another not-yet-started block/cluster and processes the returned coordinate.\n\nCLC does not create tiles, cancel the requesting worker, or chain independent problems. It can help when the SMs available to a grid are uneven, but it cannot expose more independent parallel work than exists in the launched grid.\n\nA software persistent scheduler can assign a flat tile index by fixed stride:\n\n```cpp\nfor (int tile = blockIdx.x; tile < total_tiles; tile += gridDim.x) {\n int tile_m = tile / tiles_n;\n int tile_n = tile % tiles_n;\n compute_tile(tile_m, tile_n);\n}\n```\n\nFor positive `gridDim.x`, this covers each index in `[0,total_tiles)` exactly once, including nondivisible tails. It remains useful as a controlled baseline on Hopper and Blackwell."}, "reason": {"statement": "Separate raw CLC, CUTLASS transforms, and out-of-scope mechanisms.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel"]}} +{"path": "wiki/techniques/persistent-kernels.md", "before": {"statement": "```cuda\n// CUTLASS SM100 persistent tile scheduler (simplified)\ntemplate \nstruct PersistentTileSchedulerSm100 {\n\n // Initialize the CLC with the problem geometry\n CUTLASS_DEVICE static void init(\n dim3 problem_tiles,\n void* clc_smem_buffer)\n {\n if (threadIdx.x == 0) {\n // Program CLC with total tile count and scheduling policy\n clc_init(clc_smem_buffer,\n problem_tiles.x, // tiles along M\n problem_tiles.y, // tiles along N\n ClcPolicy::SwizzledRaster);\n }\n __syncthreads();\n }\n\n // Shared storage for CTA-wide CLC result broadcast\n // __shfl_sync is warp-local and cannot reach warps 1-15.\n struct SharedClcState {\n int tile_m, tile_n;\n int valid; // 1 = got tile, 0 = no more work\n int cancelled;\n };\n\n // Get next tile assignment from CLC\n CUTLASS_DEVICE static bool get_next_tile(\n void* clc_smem_buffer,\n SharedClcState& shared_clc,\n int& tile_m,\n int& tile_n)\n {\n if (threadIdx.x == 0) {\n int m, n;\n bool v = clc_query_tile(clc_smem_buffer, m, n);\n shared_clc.tile_m = m;\n shared_clc.tile_n = n;\n shared_clc.valid = v ? 1 : 0;\n }\n __syncthreads(); // All warps see the result\n tile_m = shared_clc.tile_m;\n tile_n = shared_clc.tile_n;\n return shared_clc.valid != 0;\n }\n\n // Try to cancel the CTA when no more work\n CUTLASS_DEVICE static bool try_cancel(\n void* clc_smem_buffer,\n SharedClcState& shared_clc)\n {\n if (threadIdx.x == 0) {\n shared_clc.cancelled = clc_try_cancel(clc_smem_buffer) ? 1 : 0;\n }\n __syncthreads();\n return shared_clc.cancelled != 0;\n }\n};\n```"}, "after": {"statement": "The normative request is asynchronous and returns an opaque 16-byte shared-memory response:\n\n```ptx\nclusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [response], [mbar];\nclusterlaunchcontrol.query_cancel.is_canceled.pred.b128 p, response_b128;\n@p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {x, y, z, unused}, response_b128;\n```\n\nA complete implementation must initialize/publish the shared response and mbarrier, set the expected 16 transaction bytes, submit from the designated participant, wait for the matching phase, apply required proxy fences before reading/reusing the response, and decode a coordinate only when `is_canceled` succeeds.\n\nAfter a thread observes a failed request, another request from that thread is undefined. Failure is therefore not a “retry until another CTA creates work” condition; no CTA creates new ClcIDs.\n\nFor a thread-block cluster, one cluster participant submits the multicast request. Every CTA tracks completion at cluster scope, receives the same first coordinate, and adds its local block rank. Cluster synchronization is required before cancellation begins so all peers exist."}, "reason": {"statement": "Use exact class/method routing and avoid fake implementation bodies.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cutlass/gemm/kernel/sm100_tile_scheduler.hpp", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel"]}} +{"path": "wiki/techniques/persistent-kernels.md", "before": {"statement": "The tcgen05-tutorial progression demonstrates the impact of persistent kernels:\n\n```\nWithout persistence (static grid): 940 TFLOPS (62% of peak)\nWith CLC persistent scheduling: 1476 TFLOPS (98% of cuBLAS)\n```\n\nThe 57% improvement comes from:\n1. **Eliminated tail effect**: CLC dynamically assigns tiles, so fast-completing CTAs absorb extra work rather than sitting idle while the last wave finishes.\n2. **Reduced launch overhead**: A single kernel launch covers all tiles; no need to re-launch grids.\n3. **Better L2 cache utilization**: CLC can apply a swizzled raster pattern that improves spatial locality across neighboring tiles."}, "after": {"statement": "At CUTLASS 4.5.0, the SM100 persistent scheduler integrates CLC through `PersistentTileSchedulerSm100` and `PipelineCLCFetchAsync`. The scheduler's work flow is expressed through `WorkTileInfo` and methods including `get_current_work()`, `advance_to_next_work()`, and `fetch_next_work()`; it is not an API built from `clc_init`, `clc_query_tile`, or a caller-self-cancel helper.\n\n`advance_to_next_work()` submits/stages the next request, while `fetch_next_work()` waits for and decodes a response. CUTLASS applies `swizzle_and_rasterize()` as a software coordinate transform to both the initial `blockIdx` and returned CLC coordinates. `max_swizzle_size` and `raster_order` are scheduler arguments, not CLC hardware policy operands.\n\nThe official documentation is the authoritative implementation map; use its pinned scheduler and pipeline links rather than a short pseudo-class."}, "reason": {"statement": "Preserve the author progression only with exact variant scope and no CLC attribution.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cutlass/gemm/kernel/sm100_tile_scheduler.hpp", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/techniques/persistent-kernels.md", "before": {"statement": "- **Large GEMM problems**: Persistent kernels are most beneficial when the number of output tiles exceeds the SM count by at least 2-3x.\n- **Grouped GEMMs / MoE**: CLC can chain multiple problem instances, eliminating inter-kernel launch gaps.\n- **Workloads with uneven tile cost**: CLC's dynamic scheduling naturally handles variable-cost tiles (e.g., triangular attention masks)."}, "after": {"statement": "At CUTLASS 4.5.0, the SM100 persistent scheduler integrates CLC through `PersistentTileSchedulerSm100` and `PipelineCLCFetchAsync`. The scheduler's work flow is expressed through `WorkTileInfo` and methods including `get_current_work()`, `advance_to_next_work()`, and `fetch_next_work()`; it is not an API built from `clc_init`, `clc_query_tile`, or a caller-self-cancel helper.\n\n`advance_to_next_work()` submits/stages the next request, while `fetch_next_work()` waits for and decodes a response. CUTLASS applies `swizzle_and_rasterize()` as a software coordinate transform to both the initial `blockIdx` and returned CLC coordinates. `max_swizzle_size` and `raster_order` are scheduler arguments, not CLC hardware policy operands.\n\nThe official documentation is the authoritative implementation map; use its pinned scheduler and pipeline links rather than a short pseudo-class."}, "reason": {"statement": "Replace prescriptive thresholds with evidence requirements and conserved-work limits.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cutlass/gemm/kernel/sm100_tile_scheduler.hpp"]}} +{"path": "wiki/techniques/persistent-kernels.md", "before": {"statement": "- The `try_cancel` pattern introduces a potential race that must be handled with a retry loop."}, "after": {"statement": "Cluster Launch Control is a compute-capability-10.0 mechanism for redistributing grid coordinates that have not started. A CLC GEMM still launches its problem-sized grid. Each ClcID is processed exactly once through one of two paths:\n\n1. A block or cluster launches normally and processes its initial `blockIdx`.\n2. A running worker successfully cancels another not-yet-started block/cluster and processes the returned coordinate.\n\nCLC does not create tiles, cancel the requesting worker, or chain independent problems. It can help when the SMs available to a grid are uneven, but it cannot expose more independent parallel work than exists in the launched grid."}, "reason": {"statement": "Make failed response terminal for that requesting thread.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/techniques/pipeline-stages.md", "before": {"statement": "Software pipelining overlaps data loading (TMA copies from global to shared memory) with computation (tcgen05.mma or wgmma) by maintaining multiple in-flight tile buffers. A circular buffer of 3-5 stages allows the TMA producer to fill stage N+2 while the MMA consumer processes stage N, hiding the global memory latency entirely. This technique is critical for achieving high utilization on both Hopper and Blackwell."}, "after": {"statement": "A multi-stage pipeline reserves disjoint shared-memory operand buffers so production of one tile can overlap consumption of another. Stage count controls how far producer and consumer progress may separate; it does not guarantee that latency is fully hidden or that the schedule is faster.\n\nThere is no architecture-wide table in which two stages are always partial, three always fully hide latency, or more than five are always excessive. Legal and useful depth depends on:\n\n- bytes per stage, alignment/swizzle padding, other SMEM, and occupancy;\n- TMA issue/transfer rate and descriptor/transaction shape;\n- MMA work and completion time per K tile;\n- producer/consumer role schedule and register pressure;\n- K-loop length, prologue/tail fraction, and output schedule.\n\nCompile every candidate, reject resource-invalid variants, then compare controlled timings and pipeline/barrier stalls. Include `num_k_tiles` values below, equal to, and above the stage count to exercise every boundary."}, "reason": {"statement": "Define the mechanism without guaranteed profitability.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-best-practices-guide/index.html#asynchronous-copy-from-global-memory-to-shared-memory"]}} +{"path": "wiki/techniques/pipeline-stages.md", "before": {"statement": "The tcgen05-tutorial demonstrates the performance impact of pipelining:\n\n```\nNo pipelining (load, then compute): 695 TFLOPS (46%)\n3-stage pipeline (TMA + MMA overlap): 940 TFLOPS (62%)\n+ warp specialization: 1476 TFLOPS (98%)\n```"}, "after": {"statement": "Compute capability 10.0 supports up to 228 KiB of shared memory per SM. Thus five stages of that exact payload already exceed the per-SM capacity, while three stages consume about 63.2% before barriers, padding, descriptors, epilogue buffers, and other shared storage. Per-block opt-in limits and occupancy constraints also apply."}, "reason": {"statement": "Report only the adjacent v2b/v3 pipeline comparison and scope it to the author setup.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy"]}} +{"path": "wiki/techniques/pipeline-stages.md", "before": {"statement": "```cuda\n// 3-stage circular buffer with mbarrier synchronization\n// Stages: [0] loading, [1] ready for MMA, [2] being consumed by MMA\n#define NUM_STAGES 3\n\n__global__ void __launch_bounds__(512)\npipelined_gemm(const __grid_constant__ GemmParams params)\n{\n extern __shared__ char smem[];\n\n // Circular buffer layout in shared memory\n // Each stage has its own A and B tile buffers\n half* smem_A[NUM_STAGES];\n half* smem_B[NUM_STAGES];\n for (int s = 0; s < NUM_STAGES; s++) {\n smem_A[s] = reinterpret_cast(\n smem + s * (TILE_A_BYTES + TILE_B_BYTES));\n smem_B[s] = reinterpret_cast(\n smem + s * (TILE_A_BYTES + TILE_B_BYTES) + TILE_A_BYTES);\n }\n\n // mbarrier arrays for producer-consumer sync\n __shared__ uint64_t mbar_load_complete[NUM_STAGES];\n __shared__ uint64_t mbar_mma_complete[NUM_STAGES];\n\n int warp_id = threadIdx.x / 32;\n int lane_id = threadIdx.x % 32;\n\n // Initialize barriers\n if (threadIdx.x == 0) {\n for (int s = 0; s < NUM_STAGES; s++) {\n mbarrier_init(&mbar_load_complete[s], 1);\n mbarrier_init(&mbar_mma_complete[s], 1);\n }\n }\n __syncthreads();\n\n int num_k_tiles = params.K / TILE_K;\n\n if (warp_id == 0) {\n // ===== TMA PRODUCER =====\n // Prologue: fill the first NUM_STAGES buffers\n for (int s = 0; s < NUM_STAGES && s < num_k_tiles; s++) {\n if (lane_id == 0) {\n // Set expected TX bytes on mbarrier BEFORE issuing TMA.\n // TMA hardware will arrive on the mbarrier when transfer completes.\n uint32_t tx_bytes = TILE_A_BYTES + TILE_B_BYTES;\n mbarrier_arrive_expect_tx(&mbar_load_complete[s], tx_bytes);\n tma_load_tile_A(smem_A[s], params, s, &mbar_load_complete[s]);\n tma_load_tile_B(smem_B[s], params, s, &mbar_load_complete[s]);\n // NOTE: Do NOT manually arrive after TMA issue — the TMA\n // hardware signals the mbarrier upon transfer completion.\n }\n }\n\n // Steady state: load stage s while MMA processes stage s-NUM_STAGES\n for (int k = NUM_STAGES; k < num_k_tiles; k++) {\n int stage = k % NUM_STAGES;\n // Wait for MMA to finish with this buffer\n mbarrier_wait(&mbar_mma_complete[stage]);\n if (lane_id == 0) {\n uint32_t tx_bytes = TILE_A_BYTES + TILE_B_BYTES;\n mbarrier_arrive_expect_tx(&mbar_load_complete[stage], tx_bytes);\n tma_load_tile_A(smem_A[stage], params, k, &mbar_load_complete[stage]);\n tma_load_tile_B(smem_B[stage], params, k, &mbar_load_complete[stage]);\n }\n }\n\n } else if (warp_id == 1) {\n // ===== MMA CONSUMER =====\n for (int k = 0; k < num_k_tiles; k++) {\n int stage = k % NUM_STAGES;\n // Wait for TMA to fill this buffer\n mbarrier_wait(&mbar_load_complete[stage]);\n\n // Issue MMA on the filled buffer\n if (lane_id == 0) {\n tcgen05_mma(smem_A[stage], smem_B[stage]);\n }\n __syncwarp();\n\n // Signal that this buffer is free for reuse\n if (lane_id == 0) {\n mbarrier_arrive(&mbar_mma_complete[stage]);\n }\n }\n }\n // Epilogue warps omitted for clarity\n}\n```"}, "after": {"statement": "Each stage cycles through this ownership state machine:\n\n| empty | producer | the prior consumer has completed every read of the stage |\n| loading | TMA async proxy | expected transaction bytes are registered before the copy and the TMA transaction is outstanding |\n| ready | consumer | the full barrier's matching phase has completed |\n| consuming | MMA path | the consumer has acquired the stage and no producer may overwrite it |\n| empty again | producer | every asynchronous MMA use of the SMEM operands is complete and the consumer releases the matching empty phase |\n\nModulo indexing selects storage, but it does not track ownership by itself. A correct implementation also supplies barrier initialization/publication, expected arrival counts, phase or token state, async-proxy ordering, a bounded prologue, steady-state advancement, pipeline tail, and error-free behavior when K tiles are fewer than stages.\n\nOn SM100, do not release a stage merely after issuing `tcgen05.mma`. The MMA is asynchronous; use its defined completion path before allowing a producer to overwrite A/B storage. Likewise, `__syncthreads()` is not a substitute for the required tcgen05/TMA async-proxy completion and ordering operations."}, "reason": {"statement": "Replace unsafe code with a state-transition contract and pinned implementations.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier"]}} +{"path": "wiki/techniques/pipeline-stages.md", "before": {"statement": "| 2 | 2x base | Partial | Small tiles, limited SMEM |\n| 3 | 3x base | Full for most GEMMs | Standard choice on Blackwell |\n| 4-5 | 4-5x base | Full with margin | Large K, high memory latency |\n| >5 | Excessive | Diminishing returns | Rarely justified |"}, "after": {"statement": "For binary16 `A[128,64]` and `B[64,256]`, unpadded operand payload is:\n\n```text\nA = 128 × 64 × 2 bytes = 16 KiB\nB = 64 × 256 × 2 bytes = 32 KiB\none stage = 48 KiB\nthree stages = 144 KiB\nfive stages = 240 KiB\n```\n\nPayload grows linearly with stage count. Total allocation can additionally contain fixed and stage-dependent metadata, so derive the concrete shared-storage type rather than multiplying payload alone.\n\nThere is no architecture-wide table in which two stages are always partial, three always fully hide latency, or more than five are always excessive. Legal and useful depth depends on:\n\n- bytes per stage, alignment/swizzle padding, other SMEM, and occupancy;\n- TMA issue/transfer rate and descriptor/transaction shape;\n- MMA work and completion time per K tile;\n- producer/consumer role schedule and register pressure;\n- K-loop length, prologue/tail fraction, and output schedule.\n\nCompile every candidate, reject resource-invalid variants, then compare controlled timings and pipeline/barrier stalls. Include `num_k_tiles` values below, equal to, and above the stage count to exercise every boundary."}, "reason": {"statement": "Replace fixed labels with resource and measurement inputs.", "urls": []}} +{"path": "wiki/techniques/pipeline-stages.md", "before": {"statement": "```ptx\n// Phase-based mbarrier protocol for 3-stage pipeline\n//\n// Each mbarrier tracks a \"phase\" (0 or 1). The producer flips the phase\n// on arrive; the consumer waits for the expected phase.\n\n// Producer: arrive on stage %s (flips phase)\nmbarrier.arrive.shared.b64 %state, [%mbar_load + %s * 8];\n\n// Consumer: wait for phase %expected_phase on stage %s\n// try_wait is non-blocking; the warp can spin-wait or do other work\nWAIT_LOOP:\n mbarrier.try_wait.parity.shared.b64 %ready, [%mbar_load + %s * 8], %phase;\n @!%ready bra WAIT_LOOP;\n\n// TMA can also arrive directly on an mbarrier:\n// The TMA unit signals completion without CPU thread involvement\ncp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes\n [%smem_addr], [%tensor_map, {%coord0, %coord1}], [%mbar_load + %s * 8];\n```\n\nThe key advantage is that TMA can arrive on an mbarrier autonomously. The producer warp only needs to initiate the TMA; the TMA hardware signals completion directly, removing the producer from the critical path."}, "after": {"statement": "Each stage cycles through this ownership state machine:\n\n| empty | producer | the prior consumer has completed every read of the stage |\n| loading | TMA async proxy | expected transaction bytes are registered before the copy and the TMA transaction is outstanding |\n| ready | consumer | the full barrier's matching phase has completed |\n| consuming | MMA path | the consumer has acquired the stage and no producer may overwrite it |\n| empty again | producer | every asynchronous MMA use of the SMEM operands is complete and the consumer releases the matching empty phase |\n\nModulo indexing selects storage, but it does not track ownership by itself. A correct implementation also supplies barrier initialization/publication, expected arrival counts, phase or token state, async-proxy ordering, a bounded prologue, steady-state advancement, pipeline tail, and error-free behavior when K tiles are fewer than stages.\n\nOn SM100, do not release a stage merely after issuing `tcgen05.mma`. The MMA is asynchronous; use its defined completion path before allowing a producer to overwrite A/B storage. Likewise, `__syncthreads()` is not a substitute for the required tcgen05/TMA async-proxy completion and ordering operations.\n\nFor a TMA load into shared memory, the producer initializes/publishes the mbarrier, accounts for the copy's expected transaction bytes, and issues the tensor copy with that barrier. Hardware completes the transaction on the barrier; the consumer waits for the matching phase before reading the stage.\n\nThis autonomous completion avoids a producer instruction that manually announces data-ready after the transfer. It does not prove that producer issue work or the overall load path is absent from the measured critical path.\n\nUse the exact PTX ISA tensor-copy grammar or a version-pinned library pipeline. An illustrative `arrive`/spin loop that omits expected transaction bytes, copy descriptors, proxy fences, phase initialization, and the consumer-to-producer reuse edge is not a safe pipeline."}, "reason": {"statement": "Use exact lifecycle prose and distinguish autonomous completion from measured critical path.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/techniques/pipeline-stages.md", "before": {"statement": "The Modular blog series describes a 5-stage circular buffer reaching 85% of SOTA performance on Blackwell:\n\n```cuda\n// Modular-style 5-stage pipeline constants\n// Chosen to fully hide B200 HBM latency (~400 cycles)\n// while fitting within 228 KB SMEM budget\n\nconstexpr int NUM_STAGES = 5;\nconstexpr int TILE_M = 128;\nconstexpr int TILE_N = 128; // Smaller N to fit 5 stages\nconstexpr int TILE_K = 64;\n\n// Per stage: A (128*64*2=16KB) + B (64*128*2=16KB) = 32 KB\n// 5 stages: 160 KB + barriers + metadata < 228 KB\n\n// The pipeline timing diagram for steady state:\n//\n// Stage: 0 1 2 3 4\n// TMA: [load k5] [done] [done] [load k8] [load k9]\n// MMA: [done] [done] [comp k7] [done] [done]\n//\n// At any point: 1 stage being loaded, 1 being computed, 3 in transit or done\n```"}, "after": {"statement": "Compute capability 10.0 supports up to 228 KiB of shared memory per SM. Thus five stages of that exact payload already exceed the per-SM capacity, while three stages consume about 63.2% before barriers, padding, descriptors, epilogue buffers, and other shared storage. Per-block opt-in limits and occupancy constraints also apply."}, "reason": {"statement": "Keep five stages as one source configuration and scope the endpoint to the full sequence.", "urls": ["https://www.modular.com/blog/matrix-multiplication-on-nvidias-blackwell-part-3-the-optimizations-behind-85-of-sota-performance", "https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy"]}} +{"path": "wiki/techniques/pipeline-stages.md", "before": {"statement": "- **All memory-bound and compute-bound GEMM kernels**: Pipelining is never harmful and always improves utilization by hiding latency.\n\n- **Combined with warp specialization**: Pipelining provides the buffer structure; warp specialization assigns the producer/consumer roles. The two techniques are complementary and almost always used together."}, "after": {"statement": "A multi-stage pipeline reserves disjoint shared-memory operand buffers so production of one tile can overlap consumption of another. Stage count controls how far producer and consumer progress may separate; it does not guarantee that latency is fully hidden or that the schedule is faster.\n\nThere is no architecture-wide table in which two stages are always partial, three always fully hide latency, or more than five are always excessive. Legal and useful depth depends on:\n\n- bytes per stage, alignment/swizzle padding, other SMEM, and occupancy;\n- TMA issue/transfer rate and descriptor/transaction shape;\n- MMA work and completion time per K tile;\n- producer/consumer role schedule and register pressure;\n- K-loop length, prologue/tail fraction, and output schedule.\n\nCompile every candidate, reject resource-invalid variants, then compare controlled timings and pipeline/barrier stalls. Include `num_k_tiles` values below, equal to, and above the stage count to exercise every boundary."}, "reason": {"statement": "Make stage depth and role specialization independent tuning dimensions.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-best-practices-guide/index.html#asynchronous-copy-from-global-memory-to-shared-memory"]}} +{"path": "wiki/techniques/pipeline-stages.md", "before": {"statement": "- Barrier initialization overhead is negligible but must happen before the first TMA. Place init in a `__syncthreads()` block at kernel start."}, "after": {"statement": "Each stage cycles through this ownership state machine:\n\n| empty | producer | the prior consumer has completed every read of the stage |\n| loading | TMA async proxy | expected transaction bytes are registered before the copy and the TMA transaction is outstanding |\n| ready | consumer | the full barrier's matching phase has completed |\n| consuming | MMA path | the consumer has acquired the stage and no producer may overwrite it |\n| empty again | producer | every asynchronous MMA use of the SMEM operands is complete and the consumer releases the matching empty phase |\n\nModulo indexing selects storage, but it does not track ownership by itself. A correct implementation also supplies barrier initialization/publication, expected arrival counts, phase or token state, async-proxy ordering, a bounded prologue, steady-state advancement, pipeline tail, and error-free behavior when K tiles are fewer than stages.\n\nOn SM100, do not release a stage merely after issuing `tcgen05.mma`. The MMA is asynchronous; use its defined completion path before allowing a producer to overwrite A/B storage. Likewise, `__syncthreads()` is not a substitute for the required tcgen05/TMA async-proxy completion and ordering operations.\n\nThere is no architecture-wide table in which two stages are always partial, three always fully hide latency, or more than five are always excessive. Legal and useful depth depends on:\n\n- bytes per stage, alignment/swizzle padding, other SMEM, and occupancy;\n- TMA issue/transfer rate and descriptor/transaction shape;\n- MMA work and completion time per K tile;\n- producer/consumer role schedule and register pressure;\n- K-loop length, prologue/tail fraction, and output schedule.\n\nCompile every candidate, reject resource-invalid variants, then compare controlled timings and pipeline/barrier stalls. Include `num_k_tiles` values below, equal to, and above the stage count to exercise every boundary."}, "reason": {"statement": "State the ordering proof rather than a fixed initialization recipe/cost.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-init", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit"]}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "Tile scheduling determines the order in which output tiles of a GEMM (or attention) kernel are assigned to CTAs. The scheduling order affects L2 cache hit rates, tail-effect severity, and overall GPU utilization. On Blackwell, the CLC hardware unit supports dynamic scheduling policies including swizzled raster, while Hopper relies on software-based static stride or swizzled patterns computed at launch time."}, "after": {"statement": "“Tile scheduling” can refer to four different choices:\n\n1. **Coordinate order:** a software mapping from a logical work index to `(tile_m, tile_n, ...)`, such as row-major, column-major, or a blocked/swizzled raster.\n2. **Resident-worker iteration:** whether a CTA handles one logical tile or repeatedly advances through work, for example by a static grid stride.\n3. **Work reassignment:** on SM100, Cluster Launch Control (CLC) lets a running worker cancel another grid entity that has not started and process the returned ClcID.\n4. **Problem decomposition:** Stream-K or Split-K can partition a tile's K work and then reduce partial results.\n\nCLC does not accept a raster-order or swizzle-policy operand. CUTLASS applies those coordinate transforms in software to initial or returned coordinates. CLC also does not itself create K partitions or synthesize work beyond the launched grid."}, "reason": {"statement": "Separate tile-coordinate order from work acquisition.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "Tiles are assigned in row-major order. Simple but poor L2 locality: consecutive tiles share no B-matrix data until the entire M-dimension is traversed.\n\n```cuda\n// Linear raster: tile_idx maps directly to (tile_m, tile_n)\n__device__ void linear_raster(int tile_idx, int tiles_n,\n int& tile_m, int& tile_n) {\n tile_m = tile_idx / tiles_n;\n tile_n = tile_idx % tiles_n;\n}\n\n// Access pattern for a 4x4 tile grid:\n// 0 1 2 3\n// 4 5 6 7\n// 8 9 10 11\n// 12 13 14 15\n//\n// Problem: tiles 0,1,2,3 all load different B columns.\n// By tile 4, B column 0 has been evicted from L2.\n```"}, "after": {"statement": "A flat row-major mapping is:\n\n```cuda\n__device__ void row_major_tile(int tile_idx, int tiles_n,\n int& tile_m, int& tile_n) {\n tile_m = tile_idx / tiles_n;\n tile_n = tile_idx % tiles_n;\n}\n```\n\nFor a positive grid size, a static persistent worker can cover the flat index set without overlap:\n\n```cuda\nfor (int tile_idx = int(blockIdx.x);\n tile_idx < total_tiles;\n tile_idx += int(gridDim.x)) {\n int tile_m = tile_idx / tiles_n;\n int tile_n = tile_idx % tiles_n;\n compute_tile(tile_m, tile_n);\n}\n```\n\nChanging coordinate order changes the sequence of operand panels presented to the cache. It does not by itself prove a hit rate or speedup. A valid transform must first be shown to be in-bounds and bijective for edge groups; then its locality must be evaluated for the actual tile shape, batch/group structure, concurrent traffic, and cache capacity.\n\nFor a deliberately simplified model with `T` equal-duration independent tiles, `W` available one-tile workers, and no K decomposition, write:\n\n```text\nT = qW + r, 0 <= r < W\n```\n\nIf `r > 0`, the final partial wave has `r` active workers and occupancy `r / W`. If `r == 0` and `T > 0`, the final wave is full; reporting zero occupancy from the remainder alone is an error.\n\nFor `T = 150` and `W = 142`, the second wave contains 8 tiles, so 8 workers are active, 134 are idle, and wave occupancy is `8 / 142 = 5.63%` under those assumptions. CLC may change which workers receive those eight IDs and reduce delays caused by uneven worker availability, but it cannot turn eight independent IDs into 142. Stream-K may create additional K partitions, but its selected decomposition and reduction overhead determine whether that is profitable; near-100-percent occupancy is not guaranteed."}, "reason": {"statement": "Retain exact mapping and make cache effects empirical.", "urls": []}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "Tiles are assigned in a blocked pattern that groups nearby M and N tiles together, maximizing reuse of both A rows and B columns in L2 cache:\n\n```cuda\n// Swizzled raster: group tiles into blocks that share A and B data\n// swizzle_size controls the block width (typically 4-8)\n__device__ void swizzled_raster(int tile_idx, int tiles_m, int tiles_n,\n int swizzle_size, int& tile_m, int& tile_n)\n{\n // Number of tile columns per swizzle group\n int group_cols = min(swizzle_size, tiles_n);\n int tiles_per_group = tiles_m * group_cols;\n\n // Which swizzle group\n int group_idx = tile_idx / tiles_per_group;\n int within_group = tile_idx % tiles_per_group;\n\n // Within the group, iterate in column-major order\n tile_m = within_group / group_cols;\n tile_n = group_idx * group_cols + within_group % group_cols;\n}\n\n// Access pattern with swizzle_size=2 on a 4x4 grid:\n// 0 1 | 8 9\n// 2 3 | 10 11\n// 4 5 | 12 13\n// 6 7 | 14 15\n//\n// Tiles 0,1,2,3 share the same B columns (0,1).\n// Tiles 0,2,4,6 share the same A rows.\n// Much better L2 reuse.\n```"}, "after": {"statement": "A flat row-major mapping is:\n\n```cuda\n__device__ void row_major_tile(int tile_idx, int tiles_n,\n int& tile_m, int& tile_n) {\n tile_m = tile_idx / tiles_n;\n tile_n = tile_idx % tiles_n;\n}\n```\n\nFor a positive grid size, a static persistent worker can cover the flat index set without overlap:\n\n```cuda\nfor (int tile_idx = int(blockIdx.x);\n tile_idx < total_tiles;\n tile_idx += int(gridDim.x)) {\n int tile_m = tile_idx / tiles_n;\n int tile_n = tile_idx % tiles_n;\n compute_tile(tile_m, tile_n);\n}\n```\n\nChanging coordinate order changes the sequence of operand panels presented to the cache. It does not by itself prove a hit rate or speedup. A valid transform must first be shown to be in-bounds and bijective for edge groups; then its locality must be evaluated for the actual tile shape, batch/group structure, concurrent traffic, and cache capacity.\n\nFor a deliberately simplified model with `T` equal-duration independent tiles, `W` available one-tile workers, and no K decomposition, write:\n\n```text\nT = qW + r, 0 <= r < W\n```\n\nIf `r > 0`, the final partial wave has `r` active workers and occupancy `r / W`. If `r == 0` and `T > 0`, the final wave is full; reporting zero occupancy from the remainder alone is an error.\n\nFor `T = 150` and `W = 142`, the second wave contains 8 tiles, so 8 workers are active, 134 are idle, and wave occupancy is `8 / 142 = 5.63%` under those assumptions. CLC may change which workers receive those eight IDs and reduce delays caused by uneven worker availability, but it cannot turn eight independent IDs into 142. Stream-K may create additional K partitions, but its selected decomposition and reduction overhead determine whether that is profitable; near-100-percent occupancy is not guaranteed."}, "reason": {"statement": "Remove incorrect executable-looking code and unsupported maximality.", "urls": []}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "The CLC hardware scheduler assigns tiles at runtime, combining the benefits of dynamic load balancing with configurable scheduling policies:\n\n```cuda\n// CLC-based scheduling on Blackwell\n// The scheduling policy is set once during CLC initialization\nenum class ClcSchedulePolicy {\n LinearRaster, // Simple row-major order\n SwizzledRaster, // Blocked pattern for L2 locality\n ColumnFirst, // Column-major for specific workloads\n Hilbert // Space-filling curve (experimental)\n};\n\n__device__ void clc_init_scheduler(\n void* clc_buffer,\n int tiles_m, int tiles_n,\n ClcSchedulePolicy policy)\n{\n if (threadIdx.x == 0) {\n // Configure the software scheduler metadata used around CLC queries.\n // The CLC PTX surface is try_cancel/query_cancel, not clusterctl.init.\n uint32_t config = encode_clc_config(tiles_m, tiles_n, policy);\n init_clc_scheduler_metadata(clc_buffer, tiles_m, tiles_n, config);\n }\n __syncwarp();\n}\n```"}, "after": {"statement": "CUTLASS 4.5.0 documents this lifecycle for a CLC-backed persistent scheduler:\n\n1. Launch the full problem grid and process the worker's initial `blockIdx` coordinate.\n2. Submit `clusterlaunchcontrol.try_cancel` against another not-yet-started grid entity. The asynchronous 16-byte response completes a transaction on an mbarrier.\n3. After the transaction completes, query whether cancellation succeeded. On success, decode and process the returned ClcID; for clusters, combine the returned first coordinate with the local cluster rank.\n4. Treat an observed failed request as terminal for requests by that thread. Retrying from the same thread after failure is undefined.\n\nThis can redistribute existing work when SM availability is uneven. It changes which resident worker handles an unlaunched ID, not the number of independent IDs in the grid. Software raster/swizzle may be applied consistently to both initial and returned coordinates."}, "reason": {"statement": "Replace the invented API with the documented work lifecycle.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "```cuda\n// CUTLASS tile scheduler selection for SM100\n// All persistent schedulers inherit from PersistentTileSchedulerSm100\n\n// 1. Default CLC scheduler with swizzled raster\nusing Scheduler_Default = cutlass::gemm::PersistentTileSchedulerSm100;\n\n// 2. Stream-K scheduler for better tail handling\n// Splits K-dimension across CTAs for the last wave\nusing Scheduler_StreamK = cutlass::gemm::StreamKSchedulerSm100;\n\n// 3. Grouped GEMM scheduler for MoE workloads\n// Each group has different M, shared N and K\nusing Scheduler_Grouped = cutlass::gemm::GroupedTileSchedulerSm100;\n\n// Usage in CUTLASS kernel definition:\nusing GemmKernel = cutlass::gemm::kernel::GemmUniversal<\n cute::Shape, Int<256>, Int<64>>, // Tile shape\n ElementA, LayoutA,\n ElementB, LayoutB,\n ElementC, LayoutC,\n TiledMma,\n CollectiveMainloop,\n CollectiveEpilogue,\n Scheduler_Default // Tile scheduler\n>;\n```"}, "after": {"statement": "The public scheduler tags select implementation classes; users should prefer those tags over spelling detail types directly.\n\n| `PersistentScheduler` (also the default `void` tag) | `PersistentTileSchedulerSm100` | CLC-backed persistent data-parallel scheduling |\n| `DynamicPersistentScheduler` | `PersistentTileSchedulerSm100` | Explicit dynamic route to the same SM100 implementation |\n| `StaticPersistentScheduler` | `StaticPersistentTileScheduler100` | Static persistent scheduling |\n| `StreamKScheduler` | `PersistentTileSchedulerSm100StreamK` | Parameterized data-parallel, Stream-K, or Split-K decomposition |\n| `GroupScheduler` | `PersistentTileSchedulerSm100Group` | Grouped-problem route; in this tag it wraps the SM90-style static group scheduler |\n\nThe SM100 Stream-K route accepts decomposition, split, raster, swizzle, and reduction settings. CUTLASS 4.5.0 has a deterministic lock/turnstile reduction and a nondeterministic atomic-workspace reduction; atomic accumulation is therefore not a universal property of every Stream-K configuration."}, "reason": {"statement": "Name exact public tags and keep implementation classes clearly internal.", "urls": []}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "The choice of scheduling strategy directly impacts L2 cache hit rates. On B200 with 126 MB L2:\n\n```python\n# L2 cache reuse analysis for different schedulers\n# Problem: M=8192, N=8192, K=4096, BF16\n# Tile: 128x256, giving 64x32 = 2048 tiles\n# B200: 142 SMs, 126 MB L2\n\ntile_bytes_A = 128 * 4096 * 2 # 1 MB per tile row of A\ntile_bytes_B = 4096 * 256 * 2 # 2 MB per tile column of B\n\n# Linear raster: first wave loads 142 tiles across 142/32 = 4.4 column groups\n# B data for 5 different column groups = 5 * 2 MB = 10 MB (fits in L2)\n# But A data for 142/32 = 4.4 row groups * 4.4 col groups = ~20 distinct A rows\n# 20 * 1 MB = 20 MB -> some L2 eviction\n\n# Swizzled raster (swizzle=4): first wave covers 142 tiles in ~36 groups of 4\n# Each group uses 1 A row + 4 B columns = 1 + 8 = 9 MB per group\n# But groups share A rows: total unique A = ~36 rows * 1 MB = 36 MB\n# L2 pressure: 36 MB + 8 MB = 44 MB (fits in B200's 126 MB L2)\n\n# Conclusion: swizzled raster reduces L2 misses by ~2x vs linear for large problems\n```"}, "after": {"statement": "For a deliberately simplified model with `T` equal-duration independent tiles, `W` available one-tile workers, and no K decomposition, write:\n\n```text\nT = qW + r, 0 <= r < W\n```\n\nIf `r > 0`, the final partial wave has `r` active workers and occupancy `r / W`. If `r == 0` and `T > 0`, the final wave is full; reporting zero occupancy from the remainder alone is an error.\n\nFor `T = 150` and `W = 142`, the second wave contains 8 tiles, so 8 workers are active, 134 are idle, and wave occupancy is `8 / 142 = 5.63%` under those assumptions. CLC may change which workers receive those eight IDs and reduce delays caused by uneven worker availability, but it cannot turn eight independent IDs into 142. Stream-K may create additional K partitions, but its selected decomposition and reduction overhead determine whether that is profitable; near-100-percent occupancy is not guaranteed."}, "reason": {"statement": "Replace fabricated cache results with a measurement protocol.", "urls": []}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "| Linear raster | None | `(total_tiles % num_SMs) / num_SMs` |\n| Static stride | None | Same as linear |\n| CLC dynamic | Automatic | Fast CTAs steal from slow ones |\n| Stream-K | K-splitting | Near 100% (splits partial tiles across SMs) |"}, "after": {"statement": "For `T = 150` and `W = 142`, the second wave contains 8 tiles, so 8 workers are active, 134 are idle, and wave occupancy is `8 / 142 = 5.63%` under those assumptions. CLC may change which workers receive those eight IDs and reduce delays caused by uneven worker availability, but it cannot turn eight independent IDs into 142. Stream-K may create additional K partitions, but its selected decomposition and reduction overhead determine whether that is profitable; near-100-percent occupancy is not guaranteed."}, "reason": {"statement": "Give exact scoped arithmetic and list what each mechanism can change.", "urls": []}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "- CLC: fast-finishing CTAs from wave 1 absorb the 8 extra tiles\n- Stream-K: the 8 remaining tiles are split across all 142 SMs"}, "after": {"statement": "For `T = 150` and `W = 142`, the second wave contains 8 tiles, so 8 workers are active, 134 are idle, and wave occupancy is `8 / 142 = 5.63%` under those assumptions. CLC may change which workers receive those eight IDs and reduce delays caused by uneven worker availability, but it cannot turn eight independent IDs into 142. Stream-K may create additional K partitions, but its selected decomposition and reduction overhead determine whether that is profitable; near-100-percent occupancy is not guaranteed."}, "reason": {"statement": "Preserve the 8/142 baseline while describing mechanisms without invented outcomes.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "- **Swizzled raster**: Default choice for large GEMMs. Always better than linear for L2 locality.\n- **CLC dynamic**: Recommended on Blackwell for all persistent kernels. Combines dynamic load balancing with swizzled ordering.\n- **Stream-K**: Best for small-to-medium problems where the tail effect dominates. Adds complexity for K-dimension synchronization.\n- **Grouped scheduler**: Essential for MoE and batched GEMM where problem sizes vary across groups."}, "after": {"statement": "1. Establish a correct unswizzled data-parallel mapping and verify exact tile coverage, including nondivisible edge groups.\n2. Sweep legal raster orders and swizzle sizes. Record kernel time plus L2 hit/sector traffic; do not infer eviction from coordinate order alone.\n3. Compare static and CLC-backed persistence at identical tile, cluster, grid, and occupancy settings. Record successful/failed CLC requests and per-worker tile counts where instrumentation permits.\n4. Test Stream-K separately with explicit decomposition, split, and reduction modes. Include workspace traffic, synchronization, determinism, and numerical tolerance.\n5. Repeat across representative shapes and grouped-size distributions. Report regressions as well as wins; there is no universal best scheduler for all GEMMs, attention kernels, or MoE workloads.\n\nWithout target-GPU measurements, this page makes no fixed claim for CLC acquisition latency, L2-miss reduction, or scheduler speedup."}, "reason": {"statement": "Turn prescriptions into testable selection hypotheses.", "urls": []}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "- Swizzle size must be tuned per problem shape. Too large a swizzle group exceeds L2 capacity; too small loses the locality benefit."}, "after": {"statement": "For a deliberately simplified model with `T` equal-duration independent tiles, `W` available one-tile workers, and no K decomposition, write:\n\n```text\nT = qW + r, 0 <= r < W\n```\n\nIf `r > 0`, the final partial wave has `r` active workers and occupancy `r / W`. If `r == 0` and `T > 0`, the final wave is full; reporting zero occupancy from the remainder alone is an error.\n\nFor `T = 150` and `W = 142`, the second wave contains 8 tiles, so 8 workers are active, 134 are idle, and wave occupancy is `8 / 142 = 5.63%` under those assumptions. CLC may change which workers receive those eight IDs and reduce delays caused by uneven worker availability, but it cannot turn eight independent IDs into 142. Stream-K may create additional K partitions, but its selected decomposition and reduction overhead determine whether that is profitable; near-100-percent occupancy is not guaranteed.\n\n1. Establish a correct unswizzled data-parallel mapping and verify exact tile coverage, including nondivisible edge groups.\n2. Sweep legal raster orders and swizzle sizes. Record kernel time plus L2 hit/sector traffic; do not infer eviction from coordinate order alone.\n3. Compare static and CLC-backed persistence at identical tile, cluster, grid, and occupancy settings. Record successful/failed CLC requests and per-worker tile counts where instrumentation permits.\n4. Test Stream-K separately with explicit decomposition, split, and reduction modes. Include workspace traffic, synchronization, determinism, and numerical tolerance.\n5. Repeat across representative shapes and grouped-size distributions. Report regressions as well as wins; there is no universal best scheduler for all GEMMs, attention kernels, or MoE workloads.\n\nWithout target-GPU measurements, this page makes no fixed claim for CLC acquisition latency, L2-miss reduction, or scheduler speedup."}, "reason": {"statement": "Retain tuning advice without a false monotonic cache model.", "urls": []}} +{"path": "wiki/techniques/tile-scheduling.md", "before": {"statement": "- CLC scheduling adds a small latency per tile acquisition (~10s of cycles). For extremely small tiles, this overhead is proportionally larger.\n- Stream-K requires atomic accumulation where K-splits meet, adding synchronization overhead. Only worthwhile when tail utilization is a proven bottleneck."}, "after": {"statement": "The public scheduler tags select implementation classes; users should prefer those tags over spelling detail types directly.\n\n| `PersistentScheduler` (also the default `void` tag) | `PersistentTileSchedulerSm100` | CLC-backed persistent data-parallel scheduling |\n| `DynamicPersistentScheduler` | `PersistentTileSchedulerSm100` | Explicit dynamic route to the same SM100 implementation |\n| `StaticPersistentScheduler` | `StaticPersistentTileScheduler100` | Static persistent scheduling |\n| `StreamKScheduler` | `PersistentTileSchedulerSm100StreamK` | Parameterized data-parallel, Stream-K, or Split-K decomposition |\n| `GroupScheduler` | `PersistentTileSchedulerSm100Group` | Grouped-problem route; in this tag it wraps the SM90-style static group scheduler |\n\nThe SM100 Stream-K route accepts decomposition, split, raster, swizzle, and reduction settings. CUTLASS 4.5.0 has a deterministic lock/turnstile reduction and a nondeterministic atomic-workspace reduction; atomic accumulation is therefore not a universal property of every Stream-K configuration.\n\n1. Establish a correct unswizzled data-parallel mapping and verify exact tile coverage, including nondivisible edge groups.\n2. Sweep legal raster orders and swizzle sizes. Record kernel time plus L2 hit/sector traffic; do not infer eviction from coordinate order alone.\n3. Compare static and CLC-backed persistence at identical tile, cluster, grid, and occupancy settings. Record successful/failed CLC requests and per-worker tile counts where instrumentation permits.\n4. Test Stream-K separately with explicit decomposition, split, and reduction modes. Include workspace traffic, synchronization, determinism, and numerical tolerance.\n5. Repeat across representative shapes and grouped-size distributions. Report regressions as well as wins; there is no universal best scheduler for all GEMMs, attention kernels, or MoE workloads.\n\nWithout target-GPU measurements, this page makes no fixed claim for CLC acquisition latency, L2-miss reduction, or scheduler speedup."}, "reason": {"statement": "State observable costs and configurable reductions rather than invented constants.", "urls": []}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "Warp specialization assigns distinct functional roles to warps within a CTA, allowing each warp to focus on a single pipeline stage (data loading, MMA computation, or epilogue writeback). On Blackwell (SM100), the 16-warp CTA structure replaces Hopper's 4-warp warpgroup model. Because tcgen05.mma is a single-thread instruction that operates on TMEM rather than registers, only one warp needs to issue MMA operations, freeing the remaining warps for producer and consumer roles."}, "after": {"statement": "Warp specialization assigns different long-lived functions to disjoint warps in a CTA—for example scheduler, TMA load, MMA control, softmax/correction, or epilogue work. It is a software organization for overlapping pipeline stages, not a fixed SM100 CTA layout.\n\nThe architecture-level comparison is narrower:\n\n| Issue granularity | Warpgroup collective | One thread for `cta_group::1` or `cta_group::2` |\n| D accumulator | Per-thread registers | TMEM |\n| A/B movement | Explicit register/SMEM operands and producer work | Explicit SMEM descriptors or TMEM addresses and producer work |\n| Completion | WGMMA commit/wait groups | `tcgen05.commit` tied to an mbarrier, followed by a wait |\n\nSingle-thread issue reduces the number of threads needed to submit MMA instructions. It does not make operands move automatically, turn an entire warp into an ISA-level role, complete MMA synchronously, or choose how many epilogue warps a kernel should launch."}, "reason": {"statement": "Separate single-thread issue from software CTA/role sizing.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-operation-wgmma-mma-async", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "The canonical Blackwell GEMM kernel uses 16 warps (512 threads) per CTA with the following role assignment:\n\n| 0 | TMA Producer | Issues TMA bulk-copy from global to shared memory, signals mbarrier |\n| 1 | MMA Consumer | Issues tcgen05.mma on SMEM operands, writes results to TMEM |\n| 2-15 | Epilogue | Reads TMEM accumulator, applies scale/bias/activation, writes to global memory |"}, "after": {"statement": "There is no universal “warp 0 load, warp 1 MMA, warps 2–15 epilogue” rule. Three primary implementations illustrate the range:\n\n| Gau Nernst tutorial v4, commit `3b90ac9b...` | 4 warps. An elected lane in warp 0 runs the TMA loop; an elected lane in warp 1 runs the MMA loop; after completion, all four warps participate in TMEM load/conversion/output. |\n| CUTLASS 4.5.0 generic SM100 GEMM | One warp each for `MMA`, `Sched`, `MainloopLoad`, and `EpilogueLoad`, followed by `CollectiveEpilogue::ThreadCount / 32` epilogue warps. Optional work can make some control roles nonparticipants. |\n| FlashInfer PR 1039 context FMHA | 16 warps: 0–3 `Softmax0`, 4–7 `Softmax1`, 8–11 correction, 12 MMA, 13 load, 14 epilogue, and 15 empty. The kernel has explicit pipelines between these roles. |\n\nFlashAttention-4's pinned SM100 forward source likewise starts from a 16-warp layout with two four-warp softmax groups, four correction warps, and dedicated MMA/load/epilogue IDs, then adjusts roles for configuration choices such as one Q stage, non-TMA paths, and dynamic persistence. These are concrete attention schedules, not a GEMM-wide architectural template."}, "reason": {"statement": "Replace one invented canonical layout with version-pinned examples.", "urls": []}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "This contrasts with Hopper where a warpgroup (4 warps, 128 threads) collectively issues wgmma.mma_async, and all threads in the warpgroup participate in the MMA. On Blackwell, the MMA warp dispatches the instruction from a single thread while the hardware handles the data movement internally."}, "after": {"statement": "Warp specialization assigns different long-lived functions to disjoint warps in a CTA—for example scheduler, TMA load, MMA control, softmax/correction, or epilogue work. It is a software organization for overlapping pipeline stages, not a fixed SM100 CTA layout.\n\nThe architecture-level comparison is narrower:\n\n| Issue granularity | Warpgroup collective | One thread for `cta_group::1` or `cta_group::2` |\n| D accumulator | Per-thread registers | TMEM |\n| A/B movement | Explicit register/SMEM operands and producer work | Explicit SMEM descriptors or TMEM addresses and producer work |\n| Completion | WGMMA commit/wait groups | `tcgen05.commit` tied to an mbarrier, followed by a wait |\n\nSingle-thread issue reduces the number of threads needed to submit MMA instructions. It does not make operands move automatically, turn an entire warp into an ISA-level role, complete MMA synchronously, or choose how many epilogue warps a kernel should launch."}, "reason": {"statement": "Keep the precise Hopper/SM100 issue distinction without implying autonomous operand staging.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-operation-wgmma-mma-async"]}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "| MMA granularity | 4-warp warpgroup (128 threads) | Single thread in 1 warp |\n| MMA output destination | Registers (shared across warpgroup) | TMEM (256KB, CTA-visible) |\n| Producer warps | Separate warp(s) for TMA loads | Warp 0 dedicated to TMA |\n| Epilogue execution | Same warpgroup or separate warps | 14 dedicated warps (2-15) |\n| Synchronization | warpgroup barriers, arrive/wait | mbarrier pairs (producer/consumer) |\n| Register pressure | High (accumulators in registers) | Low (accumulators in TMEM) |"}, "after": {"statement": "Warp specialization assigns different long-lived functions to disjoint warps in a CTA—for example scheduler, TMA load, MMA control, softmax/correction, or epilogue work. It is a software organization for overlapping pipeline stages, not a fixed SM100 CTA layout.\n\nThe architecture-level comparison is narrower:\n\n| Issue granularity | Warpgroup collective | One thread for `cta_group::1` or `cta_group::2` |\n| D accumulator | Per-thread registers | TMEM |\n| A/B movement | Explicit register/SMEM operands and producer work | Explicit SMEM descriptors or TMEM addresses and producer work |\n| Completion | WGMMA commit/wait groups | `tcgen05.commit` tied to an mbarrier, followed by a wait |\n\nSingle-thread issue reduces the number of threads needed to submit MMA instructions. It does not make operands move automatically, turn an entire warp into an ISA-level role, complete MMA synchronously, or choose how many epilogue warps a kernel should launch.\n\nThere is no universal “warp 0 load, warp 1 MMA, warps 2–15 epilogue” rule. Three primary implementations illustrate the range:\n\n| Gau Nernst tutorial v4, commit `3b90ac9b...` | 4 warps. An elected lane in warp 0 runs the TMA loop; an elected lane in warp 1 runs the MMA loop; after completion, all four warps participate in TMEM load/conversion/output. |\n| CUTLASS 4.5.0 generic SM100 GEMM | One warp each for `MMA`, `Sched`, `MainloopLoad`, and `EpilogueLoad`, followed by `CollectiveEpilogue::ThreadCount / 32` epilogue warps. Optional work can make some control roles nonparticipants. |\n| FlashInfer PR 1039 context FMHA | 16 warps: 0–3 `Softmax0`, 4–7 `Softmax1`, 8–11 correction, 12 MMA, 13 load, 14 epilogue, and 15 empty. The kernel has explicit pipelines between these roles. |\n\nFlashAttention-4's pinned SM100 forward source likewise starts from a 16-warp layout with two four-warp softmax groups, four correction warps, and dedicated MMA/load/epilogue IDs, then adjusts roles for configuration choices such as one Q stage, non-TMA paths, and dynamic persistence. These are concrete attention schedules, not a GEMM-wide architectural template."}, "reason": {"statement": "Limit the comparison to normative issue/D placement and use concrete source layouts for software roles.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-operation-wgmma-mma-async", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "The kernel entry point assigns each warp its role based on `threadIdx.x`:\n\n```cuda\n// Blackwell 16-warp specialized GEMM kernel skeleton\n// 16 warps = 512 threads per CTA\n__global__ void __launch_bounds__(512)\nblackwell_gemm_warp_specialized(\n const __grid_constant__ GemmParams params)\n{\n const int warp_id = threadIdx.x / 32;\n const int lane_id = threadIdx.x % 32;\n\n // Shared memory for A/B tiles and mbarrier objects\n extern __shared__ char smem[];\n half* smem_A = reinterpret_cast(smem);\n half* smem_B = reinterpret_cast(smem + SMEM_A_SIZE);\n\n // mbarrier pairs: TMA hardware signals \"data ready\", MMA signals \"buffer free\"\n __shared__ uint64_t mbar_data_ready[NUM_STAGES];\n __shared__ uint64_t mbar_buffer_free[NUM_STAGES];\n // MMA→epilogue handoff barrier\n __shared__ uint64_t mbar_acc_complete;\n // Phase tracking: mbarriers alternate parity on each reuse cycle\n int phase_data[NUM_STAGES];\n int phase_free[NUM_STAGES];\n\n if (warp_id == 0) {\n if (lane_id == 0) {\n for (int s = 0; s < NUM_STAGES; s++) {\n // TMA expects arrive.expect_tx → hardware completes\n mbarrier_init(&mbar_data_ready[s], 1);\n mbarrier_init(&mbar_buffer_free[s], 1);\n }\n mbarrier_init(&mbar_acc_complete, 1);\n }\n }\n // Initialize phase counters (all start at 0)\n for (int s = 0; s < NUM_STAGES; s++) {\n phase_data[s] = 0;\n phase_free[s] = 0;\n }\n __syncthreads();\n\n if (warp_id == 0) {\n // === TMA PRODUCER WARP ===\n for (int k_tile = 0; k_tile < num_k_tiles; k_tile++) {\n int stage = k_tile % NUM_STAGES;\n\n // Wait for consumer to release this buffer (with phase tracking)\n if (k_tile >= NUM_STAGES) {\n mbarrier_wait_parity(&mbar_buffer_free[stage], phase_free[stage]);\n phase_free[stage] ^= 1; // flip parity for next reuse\n }\n\n // Set expected TX bytes, then issue TMA. TMA hardware will\n // signal mbar_data_ready upon transfer completion.\n // Do NOT manually arrive — that races with the async transfer.\n if (lane_id == 0) {\n uint32_t tx_bytes = TILE_A_BYTES + TILE_B_BYTES;\n mbarrier_arrive_expect_tx(&mbar_data_ready[stage], tx_bytes);\n tma_copy_async(smem_A + stage * TILE_A_SIZE,\n ¶ms.A[k_tile * TILE_K], TILE_A_SIZE,\n &mbar_data_ready[stage]);\n tma_copy_async(smem_B + stage * TILE_B_SIZE,\n ¶ms.B[k_tile * TILE_K], TILE_B_SIZE,\n &mbar_data_ready[stage]);\n // TMA hardware arrives on mbar_data_ready when transfer completes\n }\n }\n\n } else if (warp_id == 1) {\n // === MMA CONSUMER WARP ===\n for (int k_tile = 0; k_tile < num_k_tiles; k_tile++) {\n int stage = k_tile % NUM_STAGES;\n\n // Wait for TMA to complete this stage (with phase tracking)\n mbarrier_wait_parity(&mbar_data_ready[stage], phase_data[stage]);\n phase_data[stage] ^= 1;\n\n // Critical fence: ensure TMA data visible before MMA reads SMEM\n tcgen05_fence_after_thread_sync();\n\n if (lane_id == 0) {\n tcgen05_mma(smem_A + stage * TILE_A_SIZE,\n smem_B + stage * TILE_B_SIZE);\n }\n __syncwarp();\n\n // Signal buffer is free for reuse\n if (lane_id == 0) {\n mbarrier_arrive(&mbar_buffer_free[stage]);\n }\n }\n\n // Signal epilogue warps that accumulation is complete\n if (lane_id == 0) {\n mbarrier_arrive(&mbar_acc_complete);\n }\n\n } else {\n // === EPILOGUE WARPS (2-15) ===\n // Wait for MMA completion via dedicated mbarrier (not __syncthreads,\n // which would deadlock since producer/MMA warps don't reach it)\n mbarrier_wait(&mbar_acc_complete);\n\n // Each epilogue warp handles a partition of the TMEM output.\n // Use ceiling division to cover tail rows when TILE_M % 14 != 0.\n constexpr int NUM_EPI_WARPS = 14; // warps 2-15\n int epi_warp = warp_id - 2; // 0..13\n int rows_per_warp = (TILE_M + NUM_EPI_WARPS - 1) / NUM_EPI_WARPS;\n int my_row_start = epi_warp * rows_per_warp;\n int my_row_end = min(my_row_start + rows_per_warp, TILE_M);\n\n for (int r = my_row_start; r < my_row_end; r++) {\n for (int c = lane_id; c < TILE_N; c += 32) {\n // Read accumulator from TMEM\n float acc = tmem_load(r, c);\n // Apply epilogue: scale + bias + activation\n float result = epilogue_op(acc, params.scale, params.bias[c]);\n // Write to global memory\n params.C[r * params.N + c] = __float2half(result);\n }\n }\n }\n}\n```"}, "after": {"statement": "A warp-specialized implementation must prove each ownership handoff. For a reusable TMA-to-MMA stage:\n\n1. Initialize the mbarrier objects with correct participant/transaction counts and publish them to the required threads and async proxies before use.\n2. The producer acquires an empty stage, sets expected transaction bytes, and submits the TMA copies. The full/data-ready phase completes only after the expected async transactions complete.\n3. The MMA controller waits for the full phase and applies the required cross-thread/proxy fence before issuing `tcgen05.mma` against that SMEM stage.\n4. Because MMA is asynchronous, `__syncwarp()` or an ordinary `mbarrier.arrive` after issue does not make the operands reusable. Commit prior tcgen05 work to an mbarrier and wait for completion before releasing or overwriting the stage.\n5. Before another role reads D from TMEM, complete the MMA sequence and apply the required `tcgen05.fence::before_thread_sync` / execution-ordering handoff / `tcgen05.fence::after_thread_sync` protocol. A fence orders operations; it is not a completion wait.\n6. Keep TMEM allocated until every consumer finishes its `tcgen05.ld` sequence and associated waits, then deallocate with the required collective participation.\n\nPipeline wrappers in CUTLASS/CuTe encode parts of these rules, but participant counts, initial phases, tails, and producer/consumer states remain configuration-specific. A short role-dispatch sketch is not a substitute for the complete pipeline and TMEM lifecycle."}, "reason": {"statement": "Unsafe pseudo-code is worse than a precise protocol checklist and pinned full sources.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-load", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "At the PTX level, the mbarrier operations map to:\n\n```ptx\n// Producer: signal data is ready in stage %stage\nmbarrier.arrive.shared.b64 %dummy, [%mbar_data_ready + %stage_offset];\n\n// Consumer: wait for data to be ready\nmbarrier.try_wait.parity.shared.b64 %pred, [%mbar_data_ready + %stage_offset], %phase;\n\n// Consumer: signal buffer is consumed\nmbarrier.arrive.shared.b64 %dummy, [%mbar_buffer_free + %stage_offset];\n\n// Producer: wait for buffer to be free\nmbarrier.try_wait.parity.shared.b64 %pred, [%mbar_buffer_free + %stage_offset], %phase;\n```"}, "after": {"statement": "A warp-specialized implementation must prove each ownership handoff. For a reusable TMA-to-MMA stage:\n\n1. Initialize the mbarrier objects with correct participant/transaction counts and publish them to the required threads and async proxies before use.\n2. The producer acquires an empty stage, sets expected transaction bytes, and submits the TMA copies. The full/data-ready phase completes only after the expected async transactions complete.\n3. The MMA controller waits for the full phase and applies the required cross-thread/proxy fence before issuing `tcgen05.mma` against that SMEM stage.\n4. Because MMA is asynchronous, `__syncwarp()` or an ordinary `mbarrier.arrive` after issue does not make the operands reusable. Commit prior tcgen05 work to an mbarrier and wait for completion before releasing or overwriting the stage.\n5. Before another role reads D from TMEM, complete the MMA sequence and apply the required `tcgen05.fence::before_thread_sync` / execution-ordering handoff / `tcgen05.fence::after_thread_sync` protocol. A fence orders operations; it is not a completion wait.\n6. Keep TMEM allocated until every consumer finishes its `tcgen05.ld` sequence and associated waits, then deallocate with the required collective participation.\n\nPipeline wrappers in CUTLASS/CuTe encode parts of these rules, but participant counts, initial phases, tails, and producer/consumer states remain configuration-specific. A short role-dispatch sketch is not a substitute for the complete pipeline and TMEM lifecycle."}, "reason": {"statement": "Replace incomplete PTX with named obligations and authoritative links.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit"]}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "In CUTLASS 4.5.0, the SM100 GEMM collective (`CollectiveMma_1SM`) implements this pattern with CuTe abstractions:\n\n```cuda\n// CUTLASS SM100 warp role dispatch (simplified from CollectiveMma)\n// Template parameter WarpCount = cute::Shape<1, 1, 14>\n// Warp 0 = producer, Warp 1 = math, Warps 2-15 = epilogue\n\ntemplate \nstruct CollectiveMma_1SM {\n static constexpr int NumProducerWarps = 1;\n static constexpr int NumMathWarps = 1;\n static constexpr int NumEpilogueWarps = 14;\n\n CUTLASS_DEVICE void operator()(\n Params const& params,\n char* smem_buf,\n TiledMma& tiled_mma)\n {\n int warp_idx = cutlass::canonical_warp_idx_sync();\n\n if (warp_idx == 0) {\n producer_warp(params, smem_buf);\n } else if (warp_idx == 1) {\n math_warp(params, smem_buf, tiled_mma);\n } else {\n epilogue_warp(params, smem_buf);\n }\n }\n};\n```"}, "after": {"statement": "There is no universal “warp 0 load, warp 1 MMA, warps 2–15 epilogue” rule. Three primary implementations illustrate the range:\n\n| Gau Nernst tutorial v4, commit `3b90ac9b...` | 4 warps. An elected lane in warp 0 runs the TMA loop; an elected lane in warp 1 runs the MMA loop; after completion, all four warps participate in TMEM load/conversion/output. |\n| CUTLASS 4.5.0 generic SM100 GEMM | One warp each for `MMA`, `Sched`, `MainloopLoad`, and `EpilogueLoad`, followed by `CollectiveEpilogue::ThreadCount / 32` epilogue warps. Optional work can make some control roles nonparticipants. |\n| FlashInfer PR 1039 context FMHA | 16 warps: 0–3 `Softmax0`, 4–7 `Softmax1`, 8–11 correction, 12 MMA, 13 load, 14 epilogue, and 15 empty. The kernel has explicit pipelines between these roles. |\n\nFlashAttention-4's pinned SM100 forward source likewise starts from a 16-warp layout with two four-warp softmax groups, four correction warps, and dedicated MMA/load/epilogue IDs, then adjusts roles for configuration choices such as one Q stage, non-TMA paths, and dynamic persistence. These are concrete attention schedules, not a GEMM-wide architectural template."}, "reason": {"statement": "Use exact source names and line-level descriptions instead of fabricated code.", "urls": []}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "- **Always on Blackwell GEMMs**: Warp specialization is the standard pattern for SM100 tensor core kernels. The tcgen05 instruction model assumes single-thread dispatch with TMEM output."}, "after": {"statement": "For the author's exact `M=N=K=4096` Modal B200 setup with PyTorch 2.9.1 and CUDA 13, tutorial v3 reports 939.61 TFLOP/s and v4 reports 1208.83 TFLOP/s after introducing warp specialization. That is a 269.22-TFLOP/s, approximately 28.65% step between those source variants. It is not a portable Blackwell speedup or evidence that specialization is always profitable."}, "reason": {"statement": "Present specialization as a candidate optimization with an isolated source-reported example.", "urls": []}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "- **Any kernel with producer-consumer pipeline**: When TMA loads and MMA compute can overlap, warp specialization provides the cleanest decomposition."}, "after": {"statement": "For the author's exact `M=N=K=4096` Modal B200 setup with PyTorch 2.9.1 and CUDA 13, tutorial v3 reports 939.61 TFLOP/s and v4 reports 1208.83 TFLOP/s after introducing warp specialization. That is a 269.22-TFLOP/s, approximately 28.65% step between those source variants. It is not a portable Blackwell speedup or evidence that specialization is always profitable."}, "reason": {"statement": "Supply selection criteria and controlled comparison instead of a universal adjective.", "urls": []}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "- The 14 epilogue warps may be underutilized for simple epilogues (e.g., pure store). Complex epilogues (scale, bias, activation, quantization) benefit more."}, "after": {"statement": "For the author's exact `M=N=K=4096` Modal B200 setup with PyTorch 2.9.1 and CUDA 13, tutorial v3 reports 939.61 TFLOP/s and v4 reports 1208.83 TFLOP/s after introducing warp specialization. That is a 269.22-TFLOP/s, approximately 28.65% step between those source variants. It is not a portable Blackwell speedup or evidence that specialization is always profitable."}, "reason": {"statement": "Generalize to measurable role imbalance and configuration-derived counts.", "urls": []}} +{"path": "wiki/techniques/warp-specialization.md", "before": {"statement": "- The single MMA warp means the kernel cannot overlap multiple independent MMA streams within a CTA. Use 2-SM cooperative mode for larger tiles instead."}, "after": {"statement": "For the author's exact `M=N=K=4096` Modal B200 setup with PyTorch 2.9.1 and CUDA 13, tutorial v3 reports 939.61 TFLOP/s and v4 reports 1208.83 TFLOP/s after introducing warp specialization. That is a 269.22-TFLOP/s, approximately 28.65% step between those source variants. It is not a portable Blackwell speedup or evidence that specialization is always profitable."}, "reason": {"statement": "Remove the false causal rule and make 1SM/2SM an independently benchmarked configuration.", "urls": []}} +{"path": "wiki/techniques/cccl-memory-primitives.md", "before": {"statement": "Use CCCL/CUB PRs when the bottleneck is not tensor math but a memory primitive:\nscan, top-k selection, fill, histogram, reduce, or block load/store policy. The\ngoal is usually a policy or dispatch idea rather than copying a full CUB\nprimitive into an application kernel."}, "after": {"statement": "The two linked PRs have different evidentiary value:\n\n| CCCL 3559, captured merge `25523da2` | Adds B200/SM100 exclusive-sum scan tuning, expands policy classification to input/output/accumulator/offset types, and updates scan dispatch/tests. | A concrete example of architecture- and type-specific CUB policy selection. |\n| CCCL 6152, captured merge `3fb05826` | Changes only `CUB_DEBUG_LOG` formatting and stale variable names in `DispatchTopK`. | Evidence for the corrected debug output, not TopK algorithm, performance, determinism, or SM100 tuning. |\n\nDo not use PR 6152 as evidence for DSA TopK design or performance. Its captured key file exposes surrounding TopK implementation for inspection, but the PR's semantic delta is the small debug-only patch.\n\n1. Identify the exact primitive and semantic contract: inclusive/exclusive scan, operator, input/output/accumulator types, offset width, aliasing, and empty/large-size behavior.\n2. Follow runtime architecture dispatch to the active policy. Confirm whether SM100 has a matching specialization or inherits the SM90/default route.\n3. Reproduce the upstream baseline and changed policy over the size/type/operator matrix relevant to the application. A policy comment containing benchmark ratios is source context, not a portable speedup guarantee.\n4. Change one policy dimension at a time where practical and record time, bandwidth, occupancy, register/spill data, and correctness.\n5. For selection, separately verify membership, output count, ordering, ties, NaNs, signed zero, key/value association, and repeatability. Those properties are not established by PR 6152.\n\nThe linked evidence does not support claims about fill, histogram, reduce, block-load/store vectorization, or application-level DSA score computation. Add a directly relevant CCCL source before transferring policy conclusions to those primitives."}, "reason": {"statement": "Teach the exact reusable decisions and limitations of each PR.", "urls": []}} +{"path": "wiki/techniques/cccl-memory-primitives.md", "before": {"statement": "```cuda\n// Minimal policy probe shape for an application-specific top-k or scan helper.\ntemplate \nstruct PrimitivePolicy {\n static constexpr int block_threads = BLOCK_THREADS;\n static constexpr int items_per_thread = ITEMS_PER_THREAD;\n static constexpr bool vectorized = ITEMS_PER_THREAD >= 4;\n};\n```"}, "after": {"statement": "The new `sm100_tuning` specializations select a tuple rather than a single “vectorized” bit:\n\n| Classification | input value size, accumulator type/size, offset size, and recognized `plus` operator |\n| Work partition | `threads` and `items` per thread |\n| Memory policy | `BLOCK_LOAD_*`, `BLOCK_STORE_*`, and `LOAD_DEFAULT` or `LOAD_CA` |\n| Look-back behavior | an exponential backoff/delay constructor and its parameters |\n| Fallback | `Policy1000` selects a matching SM100 specialization; otherwise it falls back to `Policy900`; the double specialization explicitly inherits an SM90 tuning |\n\n`items >= 4` does not establish vectorized access. Vector width also depends on iterator contiguity, element type, alignment, load/store algorithm, compiler lowering, and the executed policy. Treat items-per-thread, block size, load/store algorithm, cache modifier, and delay policy as separate variables."}, "reason": {"statement": "Replace fabricated policy code with an exact field matrix from the PR.", "urls": []}} +{"path": "wiki/techniques/external-source-map-research.md", "before": {"statement": "```bash\ngit clone https://github.com/ColfaxResearch/cfx-article-src external/colfax-cfx\ngit clone https://github.com/simveit/load_and_store external/simveit-load-store\nrg -n \"tma|mbarrier|swizzle|ldmatrix|stream\" external/colfax-cfx external/simveit-load-store\n```"}, "after": {"statement": "```bash\ngit init external/colfax-cfx\ngit -C external/colfax-cfx remote add origin \\\n https://github.com/ColfaxResearch/cfx-article-src\ngit -C external/colfax-cfx fetch --depth=1 origin \\\n fbecfed88de2e4246f104a023188ba722937c5fc\ngit -C external/colfax-cfx checkout --detach FETCH_HEAD\ntest \"$(git -C external/colfax-cfx rev-parse HEAD)\" = \\\n fbecfed88de2e4246f104a023188ba722937c5fc\n\nrg -n \"SM90_TMA|mbarrier\" \\\n external/colfax-cfx/tma external/colfax-cfx/pipeline-gemm\nrg -n \"PersistentTileScheduler|StreamK\" external/colfax-cfx/streamk\n```"}, "reason": {"statement": "Pin every checkout and show mechanism-specific file searches.", "urls": []}} +{"path": "wiki/techniques/external-source-map-research.md", "before": {"statement": "Do not cite this page as implementation evidence by itself. Cite one of its\nsource pages plus the concrete upstream file path, commit, or URL that shaped the\ncandidate edit."}, "after": {"statement": "- For tail waves, compare the pinned non-persistent, data-parallel persistent,\n and Stream-K scheduler implementations before adding shape dispatch. Profile\n the target shapes rather than treating persistence as a universal remedy."}, "reason": {"statement": "Require a pinned upstream revision and exact file/symbol locator, treating source pages as discovery leads only.", "urls": []}} +{"path": "wiki/techniques/external-source-map-research.md", "before": {"statement": "Use external source-map research after a profile or benchmark identifies an edit\nfamily but the local PR pages do not expose a small enough implementation\nexample. The route is code-first: clone a source-map repository, grep for the\nmeasured mechanism, and cite exact files before adapting an idea."}, "after": {"statement": "Use external source-map research after a profile or benchmark identifies an edit\nfamily but the local PR pages do not expose a small enough implementation\nexample. Treat the profiler result as a search key, not a root-cause proof:\ninspect a pinned upstream revision and exact implementation files before\nadapting an idea.\n\n- For tail waves, compare the pinned non-persistent, data-parallel persistent,\n and Stream-K scheduler implementations before adding shape dispatch. Profile\n the target shapes rather than treating persistence as a universal remedy."}, "reason": {"statement": "Scope demonstrated implementations to SM90a and make Blackwell transfer require separate SM100 evidence.", "urls": []}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "Fine-grained quantization applies per-block (rather than per-tensor) scaling factors to low-precision data, preventing outlier values from destroying the quantization precision of an entire tensor. DeepSeek pioneered the tile-wise 1x128 scaling for activations and block-wise 128x128 scaling for weights in their FP8 training framework. On Blackwell (SM100), native block scaling support in tcgen05.mma enables hardware-accelerated fine-grained quantization using the UE8M0 scale format, while Hopper requires software-managed CUDA core promotion."}, "after": {"statement": "Fine-grained quantization associates low-precision payloads with scales for\nsubsets of a tensor. Smaller groups let scale selection respond more locally,\nbut they do not guarantee a particular error or speed result. Keep four choices\nseparate when transferring a kernel: payload type, scale type, scale geometry,\nand physical scale layout.\n\nThree verified recipes in this wiki illustrate why the full contract matters:\n\n- **DeepSeek FP8 training geometry:** one scale for each token row and 128\n activation channels (`1 x 128`), and one scale for each 128-input-channel by\n 128-output-channel weight block (`128 x 128`).\n- **NVFP4 1D recipe:** E2M1 payloads, one E4M3 local scale per 16 consecutive\n values, and one FP32 global scale per tensor. Transformer Engine 2.13 also\n defines a weight-oriented 2D mode with one local scale per `16 x 16` block.\n- **MXFP4:** E2M1 payloads with one UE8M0 power-of-two scale per 32 values; the\n NVFP4 per-tensor global scale is not part of this microscaling format."}, "reason": {"statement": "Separate recipe, implementation and architecture scopes.", "urls": ["https://arxiv.org/abs/2412.19437v2", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "```\nPer-tensor scaling (coarsest):\n Entire tensor shares one FP32 scale factor.\n Problem: a single outlier ruins precision for all elements.\n \n [=== entire MxK matrix === ] -> 1 scale\n\nPer-block 128x128 scaling (weights):\n Each 128x128 block has its own scale factor.\n 128x128 = 16,384 elements per scale -> 0.006% overhead.\n \n +---+---+---+\n |s1 |s2 |s3 | <- each block has independent scale\n +---+---+---+\n |s4 |s5 |s6 |\n +---+---+---+\n\nPer-tile 1x128 scaling (activations):\n Each row of 128 elements has its own scale factor.\n Captures per-channel activation distributions.\n \n [s1: ====128 elements====]\n [s2: ====128 elements====]\n [s3: ====128 elements====]\n```"}, "after": {"statement": "Scale-count and storage overhead are different quantities. A `128 x 128` block\nhas one factor per 16,384 payloads, a factor-count ratio of about 0.0061%. If\nthe payload is one byte and the factor is FP32, the byte ratio is instead\n`4 / 16384`, about 0.0244%. Include factor width, payload width, padding, and\nlayout transformations in any storage or bandwidth claim."}, "reason": {"statement": "State geometry and formulas without an ambiguous percentage or per-channel label.", "urls": []}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "```cuda\n// DeepGEMM FP8 GEMM with fine-grained scaling\n// A (activations): FP8 E4M3 with tile-wise 1x128 FP32 scales\n// B (weights): FP8 E4M3 with block-wise 128x128 FP32 scales\n// C (output): FP32 accumulator\n\n// Scale tensor shapes:\n// scale_A: [M, K/128] -- one FP32 scale per 128 elements along K for each row\n// scale_B: [K/128, N/128] -- one FP32 scale per 128x128 block\n\n__device__ void deepgemm_fp8_tile(\n const fp8_e4m3* A, // [TILE_M, TILE_K] in FP8\n const fp8_e4m3* B, // [TILE_K, TILE_N] in FP8\n const float* scale_A, // [TILE_M, TILE_K/128]\n const float* scale_B, // [TILE_K/128, TILE_N/128]\n float* C, // [TILE_M, TILE_N] accumulator\n int M, int N, int K)\n{\n // For each 128-element K-chunk:\n for (int k_block = 0; k_block < K; k_block += 128) {\n // 1. Load FP8 A tile [TILE_M, 128] and B tile [128, TILE_N]\n // 2. Perform MMA: partial = A_fp8 * B_fp8 (in limited-precision FP32)\n // 3. Apply combined scale: scale_A[m, k_block/128] * scale_B[k_block/128, n_block/128]\n // 4. Accumulate: C[m, n] += partial * combined_scale\n\n for (int m = 0; m < TILE_M; m++) {\n float sa = scale_A[m * (K / 128) + k_block / 128];\n for (int n_block = 0; n_block < TILE_N; n_block += 128) {\n float sb = scale_B[(k_block / 128) * (N / 128) + n_block / 128];\n float combined_scale = sa * sb;\n\n // Apply scale to the partial MMA result\n for (int n = n_block; n < n_block + 128; n++) {\n C[m * TILE_N + n] += partial[m][n] * combined_scale;\n }\n }\n }\n }\n}\n```"}, "after": {"statement": "At commit `891d57b4db1071624b5c8fa0d1e51cb317fa709f`, DeepGEMM uses\narchitecture-specific scale representations and accumulation paths.\n\nThe pinned SM90 1D1D kernel consumes FP32 A/B factors and fixes\n`BLOCK_K == 128`. The DeepSeek-V3 report characterizes the H800 FP8 Tensor Core\npath as retaining about 14 bits and describes this interval as four WGMMAs in\nits configuration. The exact kernel accumulates one K block in `float accum`\nand then applies both factors into a separate `float final_accum`:\n\n```cpp\nfinal_accum[i * 4 + 0] += scale_a_0 * scale_b_0 * accum[i * 4 + 0];\nfinal_accum[i * 4 + 1] += scale_a_0 * scale_b_1 * accum[i * 4 + 1];\nfinal_accum[i * 4 + 2] += scale_a_1 * scale_b_0 * accum[i * 4 + 2];\nfinal_accum[i * 4 + 3] += scale_a_1 * scale_b_1 * accum[i * 4 + 3];\n```\n\nThis is a source-specific implementation, not a rule for every Hopper FP8\nkernel. The cited sources do not establish the deleted 0.1% error bound or a\nuniversal ranking of `Nc=32`, `64`, `128`, and `256`."}, "reason": {"statement": "Use the pinned implementation and a short verbatim fragment instead.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d1d.cuh", "https://arxiv.org/abs/2412.19437v2"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "On Hopper (SM90), the wgmma instruction accumulates in Tensor Core registers with limited precision (~FP22, not true FP32). To maintain numerical accuracy, DeepGEMM promotes the partial sum to a separate FP32 accumulator on CUDA Cores every 4 wgmma instructions (Nc=128, since each wgmma processes 32 K-elements):"}, "after": {"statement": "At commit `891d57b4db1071624b5c8fa0d1e51cb317fa709f`, DeepGEMM uses\narchitecture-specific scale representations and accumulation paths.\n\nThe pinned SM90 1D1D kernel consumes FP32 A/B factors and fixes\n`BLOCK_K == 128`. The DeepSeek-V3 report characterizes the H800 FP8 Tensor Core\npath as retaining about 14 bits and describes this interval as four WGMMAs in\nits configuration. The exact kernel accumulates one K block in `float accum`\nand then applies both factors into a separate `float final_accum`:\n\n```cpp\nfinal_accum[i * 4 + 0] += scale_a_0 * scale_b_0 * accum[i * 4 + 0];\nfinal_accum[i * 4 + 1] += scale_a_0 * scale_b_1 * accum[i * 4 + 1];\nfinal_accum[i * 4 + 2] += scale_a_1 * scale_b_0 * accum[i * 4 + 2];\nfinal_accum[i * 4 + 3] += scale_a_1 * scale_b_1 * accum[i * 4 + 3];\n```\n\nThis is a source-specific implementation, not a rule for every Hopper FP8\nkernel. The cited sources do not establish the deleted 0.1% error bound or a\nuniversal ranking of `Nc=32`, `64`, `128`, and `256`."}, "reason": {"statement": "Use the source's retained-bit wording and implementation scope.", "urls": ["https://arxiv.org/abs/2412.19437v2", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d1d.cuh"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "```cuda\n// Hopper FP8 GEMM with CUDA Core promotion (DeepGEMM pattern)\n// Every Nc=128 K-elements, promote Tensor Core accumulator to FP32\n\n__device__ void hopper_fp8_gemm_with_promotion(\n const fp8_e4m3* A, const fp8_e4m3* B,\n const float* scale_A, const float* scale_B,\n float* C_accumulator,\n int K)\n{\n // Tensor Core limited-precision accumulator (FP22-ish)\n // These are wgmma output registers\n float tc_acc[TILE_M_PER_THREAD][TILE_N_PER_THREAD] = {0};\n\n // True FP32 accumulator on CUDA Cores\n float fp32_acc[TILE_M_PER_THREAD][TILE_N_PER_THREAD] = {0};\n\n int promotion_interval = 128; // Nc = 128 elements = 4 wgmma ops\n int wgmma_count = 0;\n\n for (int k = 0; k < K; k += 32) {\n // Issue wgmma (accumulates in limited-precision tc_acc)\n wgmma_mma_async(tc_acc, smem_A_ptr, smem_B_ptr);\n wgmma_count++;\n\n if (wgmma_count == 4) { // Every 128 K-elements\n // Promote: transfer tc_acc to fp32_acc on CUDA Cores\n wgmma_wait(); // Ensure wgmma is complete\n\n int k_block = k / promotion_interval;\n for (int m = 0; m < TILE_M_PER_THREAD; m++) {\n float sa = scale_A[/*...*/];\n for (int n = 0; n < TILE_N_PER_THREAD; n++) {\n float sb = scale_B[/*...*/];\n // Add scaled partial to true FP32 accumulator\n fp32_acc[m][n] += tc_acc[m][n] * sa * sb;\n // Reset TC accumulator for next interval\n tc_acc[m][n] = 0;\n }\n }\n wgmma_count = 0;\n }\n }\n}\n```"}, "after": {"statement": "At commit `891d57b4db1071624b5c8fa0d1e51cb317fa709f`, DeepGEMM uses\narchitecture-specific scale representations and accumulation paths.\n\nThe pinned SM90 1D1D kernel consumes FP32 A/B factors and fixes\n`BLOCK_K == 128`. The DeepSeek-V3 report characterizes the H800 FP8 Tensor Core\npath as retaining about 14 bits and describes this interval as four WGMMAs in\nits configuration. The exact kernel accumulates one K block in `float accum`\nand then applies both factors into a separate `float final_accum`:\n\n```cpp\nfinal_accum[i * 4 + 0] += scale_a_0 * scale_b_0 * accum[i * 4 + 0];\nfinal_accum[i * 4 + 1] += scale_a_0 * scale_b_1 * accum[i * 4 + 1];\nfinal_accum[i * 4 + 2] += scale_a_1 * scale_b_0 * accum[i * 4 + 2];\nfinal_accum[i * 4 + 3] += scale_a_1 * scale_b_1 * accum[i * 4 + 3];\n```\n\nThis is a source-specific implementation, not a rule for every Hopper FP8\nkernel. The cited sources do not establish the deleted 0.1% error bound or a\nuniversal ranking of `Nc=32`, `64`, `128`, and `256`."}, "reason": {"statement": "Replace it with an exact upstream fragment and workflow.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d1d.cuh", "https://arxiv.org/abs/2412.19437v2"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "The Nc=128 interval was chosen because:\n- 4 wgmma operations process 128 K-elements (4 x 32)\n- At this interval, the accumulated FP22 error is bounded to ~0.1% relative error\n- Fewer than 4 ops (Nc=32, Nc=64) adds too much promotion overhead\n- More than 4 ops (Nc=256) allows unacceptable precision loss"}, "after": {"statement": "At commit `891d57b4db1071624b5c8fa0d1e51cb317fa709f`, DeepGEMM uses\narchitecture-specific scale representations and accumulation paths.\n\nThe pinned SM90 1D1D kernel consumes FP32 A/B factors and fixes\n`BLOCK_K == 128`. The DeepSeek-V3 report characterizes the H800 FP8 Tensor Core\npath as retaining about 14 bits and describes this interval as four WGMMAs in\nits configuration. The exact kernel accumulates one K block in `float accum`\nand then applies both factors into a separate `float final_accum`:\n\n```cpp\nfinal_accum[i * 4 + 0] += scale_a_0 * scale_b_0 * accum[i * 4 + 0];\nfinal_accum[i * 4 + 1] += scale_a_0 * scale_b_1 * accum[i * 4 + 1];\nfinal_accum[i * 4 + 2] += scale_a_1 * scale_b_0 * accum[i * 4 + 2];\nfinal_accum[i * 4 + 3] += scale_a_1 * scale_b_1 * accum[i * 4 + 3];\n```\n\nThis is a source-specific implementation, not a rule for every Hopper FP8\nkernel. The cited sources do not establish the deleted 0.1% error bound or a\nuniversal ranking of `Nc=32`, `64`, `128`, and `256`.\n\n1. Match the model/checkpoint recipe: payload encoding, local scale type,\n optional global scale, and scale geometry.\n2. Match the kernel ABI: logical factor shape is not necessarily its TMA- or\n TMEM-ready physical layout. Account for packing, padding, transposition, and\n swizzling.\n3. Match the target instruction. For native Blackwell block scaling, use the\n complete kind, block/scale-vector qualifier, scale type, and target rules.\n4. Keep preparation in the timed region unless the producer already emits the\n required layout. Otherwise report preprocessing separately.\n5. Validate output accuracy with the exact quantizer, workload, reference,\n tolerance, and accumulation path; then measure end-to-end latency or\n throughput for the actual shapes.\n\n- More groups require more scale elements, but padding and layout determine the\n actual traffic and storage cost.\n- Smaller groups and fractional scales provide more representational freedom;\n they do not guarantee lower error for every tensor or scale-selection method.\n- DeepGEMM's Nc=128 path is evidence for that pinned SM90 implementation, not a\n universal optimum for Hopper.\n- Native instruction support does not make two recipes ABI-compatible. NVFP4,\n MXFP4, and DeepGEMM FP8 differ in payload, scale type, grouping, and layout."}, "reason": {"statement": "Retain only the exact source-supported interval and prohibit transfer without measurement.", "urls": ["https://arxiv.org/abs/2412.19437v2", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d1d.cuh", "https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "```cuda\n// Blackwell native block scaling with UE8M0\n// Scale format: UE8M0 = pure power-of-two scale (2^exponent)\n// Packed: 4 UE8M0 values per 32-bit integer\n\n// DeepGEMM SM100 kernel: scale_A and scale_B are UE8M0 packed\n// tcgen05.mma applies scales automatically during accumulation\n\nstruct BlockScaleDescriptor {\n // 4 UE8M0 scale values packed into one uint32\n // Each UE8M0 is an 8-bit unsigned exponent: value = 2^(e - 127)\n uint32_t packed_scales; // Contains 4 block scales\n\n // Dequantization for block [i]:\n // scale_i = 2^(((packed >> (i*8)) & 0xFF) - 127)\n};\n\n// PTX for tcgen05.mma with block scaling:\n// The .scale modifier tells the hardware to apply UE8M0 scales\n// from a designated SMEM region alongside the MMA operands\n```"}, "after": {"statement": "The pinned SM100 1D1D template accepts K scale granularities of 32 or 128 for\neach operand. Its public interface packs four UE8M0 factors in each 32-bit\ncontainer. TMA moves factor blocks to shared memory, UTCCP copies them into\ndedicated TMEM SFA/SFB columns, and block-scaled UMMA consumes the TMEM scale\naddresses. The SM90 `final_accum` promotion loop is absent."}, "reason": {"statement": "Avoid an incomplete invented descriptor; cite the exact type definition and upstream representation.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#alternate-floating-point-data-formats", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm100_fp8_gemm_1d1d.cuh", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "```ptx\n// tcgen05.mma with native block scaling (Blackwell PTX)\n// This instruction applies UE8M0 scales from SMEM during MMA\ntcgen05.mma.cta_group::1.kind::f8f6f4\n [%tmem_addr], // TMEM accumulator destination\n [%desc_a], // SMEM descriptor for A operand\n [%desc_b], // SMEM descriptor for B operand\n %scale_d, // Scale descriptor for D (output)\n %enable_mask,\n [%scale_a_smem], // UE8M0 scales for A in SMEM\n [%scale_b_smem]; // UE8M0 scales for B in SMEM\n```"}, "after": {"statement": "PTX ISA 9.0 expresses the corresponding FP8 block-scaled operand classes with\nthis grammar-level form:\n\n```ptx\ntcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X\n [d_tmem], a_desc, b_desc, idesc,\n [scale_a_tmem], [scale_b_tmem], enable_input_d;\n```\n\nThis line is an instruction-shape reference, not a complete kernel: declarations,\nlegal descriptors, collective participation, scale layouts, ordering, completion,\nand an architecture-specific target are still required. UE8M0 uses power-of-two\nfinite values and reserves encoding `0xff` for NaN."}, "reason": {"statement": "Show exact grammar-level PTX and label missing declarations/descriptors.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "| Representable values | Powers of 2 only | 240 distinct values | Full FP32 range |\n| Range | 2^-127 to 2^128 | ~0 to 448 | Full FP32 |"}, "after": {"statement": "The pinned SM100 1D1D template accepts K scale granularities of 32 or 128 for\neach operand. Its public interface packs four UE8M0 factors in each 32-bit\ncontainer. TMA moves factor blocks to shared memory, UTCCP copies them into\ndedicated TMEM SFA/SFB columns, and block-scaled UMMA consumes the TMEM scale\naddresses. The SM90 `final_accum` promotion loop is absent."}, "reason": {"statement": "Use recipe/type combinations without unsupported range/count shorthand.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#alternate-floating-point-data-formats", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm100_fp8_gemm_1d1d.cuh", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "| Hardware support | tcgen05.mma native | Software decode | Software promotion |\n| Precision impact | Coarser (power-of-2 only) | Fine (non-power-of-2) | Best (FP32) |"}, "after": {"statement": "The pinned SM100 1D1D template accepts K scale granularities of 32 or 128 for\neach operand. Its public interface packs four UE8M0 factors in each 32-bit\ncontainer. TMA moves factor blocks to shared memory, UTCCP copies them into\ndedicated TMEM SFA/SFB columns, and block-scaled UMMA consumes the TMEM scale\naddresses. The SM90 `final_accum` promotion loop is absent.\n\nPTX ISA 9.0 expresses the corresponding FP8 block-scaled operand classes with\nthis grammar-level form:\n\n```ptx\ntcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X\n [d_tmem], a_desc, b_desc, idesc,\n [scale_a_tmem], [scale_b_tmem], enable_input_d;\n```\n\nThis line is an instruction-shape reference, not a complete kernel: declarations,\nlegal descriptors, collective participation, scale layouts, ordering, completion,\nand an architecture-specific target are still required. UE8M0 uses power-of-two\nfinite values and reserves encoding `0xff` for NaN."}, "reason": {"statement": "Separate native instruction legality from recipe accuracy and software choices.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm100_fp8_gemm_1d1d.cuh", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#alternate-floating-point-data-formats"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "- **FP8 training**: Use tile-wise 1x128 for activations and block-wise 128x128 for weights (DeepGEMM pattern). This is the validated approach for training 671B+ parameter models.\n- **FP4 inference on Blackwell**: Use NVFP4 with E4M3 block scales (block size 16) for highest precision, or MXFP4 with UE8M0 scales (block size 32) for native hardware acceleration.\n- **Hopper FP8 inference**: Use CUDA core promotion with Nc=128 interval to maintain precision despite limited TC accumulation."}, "after": {"statement": "PTX ISA 9.0 distinguishes the native formats by the complete instruction\ncombination, not by “FP4” alone:\n\n| `.kind::mxf4.block_scale.block32` / `.scale_vec::2X` | E2M1 | UE8M0 | 32 |\n| `.kind::mxf4nvf4.block_scale.block16` / `.scale_vec::4X` | E2M1 | UE4M3 | 16 |\n\nThe `mxf4nvf4` family also has documented UE8M0 modes, so the kind name alone\ndoes not select the NVFP4 recipe. NVFP4-compatible UE4M3 scaling is native on\nthe documented Blackwell targets; it is not necessarily a software-decode path.\n\n1. Match the model/checkpoint recipe: payload encoding, local scale type,\n optional global scale, and scale geometry.\n2. Match the kernel ABI: logical factor shape is not necessarily its TMA- or\n TMEM-ready physical layout. Account for packing, padding, transposition, and\n swizzling.\n3. Match the target instruction. For native Blackwell block scaling, use the\n complete kind, block/scale-vector qualifier, scale type, and target rules.\n4. Keep preparation in the timed region unless the producer already emits the\n required layout. Otherwise report preprocessing separately.\n5. Validate output accuracy with the exact quantizer, workload, reference,\n tolerance, and accumulation path; then measure end-to-end latency or\n throughput for the actual shapes.\n\n- More groups require more scale elements, but padding and layout determine the\n actual traffic and storage cost.\n- Smaller groups and fractional scales provide more representational freedom;\n they do not guarantee lower error for every tensor or scale-selection method.\n- DeepGEMM's Nc=128 path is evidence for that pinned SM90 implementation, not a\n universal optimum for Hopper.\n- Native instruction support does not make two recipes ABI-compatible. NVFP4,\n MXFP4, and DeepGEMM FP8 differ in payload, scale type, grouping, and layout."}, "reason": {"statement": "Replace prescriptions with a recipe-selection checklist.", "urls": ["https://arxiv.org/abs/2412.19437v2", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md"]}} +{"path": "wiki/techniques/fine-grained-quantization.md", "before": {"statement": "- UE8M0 scales are power-of-two only. Non-power-of-two distributions (common in activations) lose precision compared to E4M3 or FP32 scales.\n- Smaller block sizes (16 for NVFP4 vs 128 for DeepGEMM) provide better precision but higher overhead: more scale values to store, load, and apply.\n- The Nc=128 promotion interval on Hopper is a performance-accuracy tradeoff. Reducing Nc improves accuracy but adds more promotion overhead. Increasing Nc risks precision degradation.\n- On Blackwell, native block scaling only works with UE8M0. Using E4M3 or FP32 scales still requires software handling."}, "after": {"statement": "Scale-count and storage overhead are different quantities. A `128 x 128` block\nhas one factor per 16,384 payloads, a factor-count ratio of about 0.0061%. If\nthe payload is one byte and the factor is FP32, the byte ratio is instead\n`4 / 16384`, about 0.0244%. Include factor width, payload width, padding, and\nlayout transformations in any storage or bandwidth claim.\n\n1. Match the model/checkpoint recipe: payload encoding, local scale type,\n optional global scale, and scale geometry.\n2. Match the kernel ABI: logical factor shape is not necessarily its TMA- or\n TMEM-ready physical layout. Account for packing, padding, transposition, and\n swizzling.\n3. Match the target instruction. For native Blackwell block scaling, use the\n complete kind, block/scale-vector qualifier, scale type, and target rules.\n4. Keep preparation in the timed region unless the producer already emits the\n required layout. Otherwise report preprocessing separately.\n5. Validate output accuracy with the exact quantizer, workload, reference,\n tolerance, and accumulation path; then measure end-to-end latency or\n throughput for the actual shapes.\n\n- More groups require more scale elements, but padding and layout determine the\n actual traffic and storage cost.\n- Smaller groups and fractional scales provide more representational freedom;\n they do not guarantee lower error for every tensor or scale-selection method.\n- DeepGEMM's Nc=128 path is evidence for that pinned SM90 implementation, not a\n universal optimum for Hopper.\n- Native instruction support does not make two recipes ABI-compatible. NVFP4,\n MXFP4, and DeepGEMM FP8 differ in payload, scale type, grouping, and layout."}, "reason": {"statement": "State only metadata arithmetic and verified capability; require measurement for accuracy/performance.", "urls": ["https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md"]}} +{"path": "wiki/techniques/kernel-fusion.md", "before": {"statement": "Kernel fusion combines multiple operations into a single kernel launch, eliminating intermediate global memory roundtrips. Critical for MoE and attention pipelines where 5-7 sequential launches each incur latency, synchronization, and memory traffic overhead."}, "after": {"statement": "Kernel fusion implements two or more dependent logical operations inside one\nGPU kernel launch. It can remove a launch or an intermediate global-memory\nwrite/read only when the chosen unfused baseline would perform that work and\nthe fused implementation keeps the value on chip. Fusion is therefore an\nimplementation property, not a conclusion that follows from an operation's\nname.\n\nReport a benefit only for a defined fused/unfused pair with identical input and\noutput semantics. Count actual launches and bytes for the pinned implementation;\ndo not transfer framework-level launch counts or traffic percentages from an\nunpinned configuration."}, "reason": {"statement": "Define fusion semantically and state conditional benefits.", "urls": []}} +{"path": "wiki/techniques/kernel-fusion.md", "before": {"statement": "```cuda\n// Instead of: gate_gemm → up_gemm → silu → multiply (4 kernels)\n// Fused: single kernel with two TMEM accumulators\n__global__ void fused_gate_up_silu(...) {\n uint32_t tmem_gate = tmem_alloc(256);\n uint32_t tmem_up = tmem_alloc(256);\n\n for (int k = 0; k < K; k += BLOCK_K) {\n tcgen05_mma(x_smem, w_gate_smem, tmem_gate);\n tcgen05_mma(x_smem, w_up_smem, tmem_up);\n }\n\n float g = tmem_load(tmem_gate);\n float u = tmem_load(tmem_up);\n output = (g / (1.0f + expf(-g))) * u; // SwiGLU fused\n}\n```"}, "after": {"statement": "GPU Mode NVFP4 Challenge 3 fixes this operation for each batch index:\n\n```python\ngate = scaled_mm(a, b1.T, sfa, sfb1)\nup = scaled_mm(a, b2.T, sfa, sfb2)\noutput = silu(gate) * up\n```\n\nThe two products share `a` and its scale tensor but use separate B operands and\nscales. This operation graph permits reuse and fused pointwise output, but the\npinned correctness reference does not prescribe launch count, TMEM partition,\nTMA pipeline, or instruction schedule. A concatenated gate/up projection or two\nlogical accumulators can both implement compatible observable semantics when\ntheir tensor contracts match."}, "reason": {"statement": "Use the exact operation reference and keep schedule choices separate.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://github.com/gpu-mode/reference-kernels/blob/c5b2f7c062d5015f29c3a1043cfd04954397944c/problems/nvidia/nvfp4_dual_gemm/reference.py"]}} +{"path": "wiki/techniques/kernel-fusion.md", "before": {"statement": "- **vLLM (7 kernels)**: softmax → topk → dispatch → gate → up → silu_mul → down+combine\n- **SGLang (5 kernels)**: router+topk → dispatch → fused gate-up-silu → down → combine\n- **Ideal (1-2 kernels)**: all ops in one launch, saves 21.9% activation memory traffic"}, "after": {"statement": "FlashInfer MLSys 2026 Track A includes sigmoid routing, grouped expert\nselection, two grouped GEMMs, SwiGLU, and weighted expert accumulation in one\nlogical benchmark definition. The exact reference performs one concatenated\nW13 projection, splits its 4096 columns into gate and up halves, applies\nSwiGLU, then performs W2. The term “Fused MoE” does not establish that a\nsubmission uses one launch or keeps every intermediate on chip.\n\nFor correctness, compare the fused and unfused paths on identical tensors and\nexercise empty/small groups, partial tiles, extreme activations, routing ties,\nand every supported scale/layout variant. Add negative tests for premature\nbuffer reuse, omitted completion, wrong routing weights, and invalid output\nedges."}, "reason": {"statement": "Do not preserve unpinned framework-specific performance claims.", "urls": ["https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048", "https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/trace/templates/moe.py"]}} +{"path": "wiki/techniques/kernel-fusion.md", "before": {"statement": "- TMEM capacity limits how many accumulators can fuse (256 cols total)"}, "after": {"statement": "- **Semantics:** preserve routing, scale, bias, activation, reduction,\n accumulation, dtype, ordering, and output-edge behavior. A pointwise epilogue\n is easier to compose than a cross-CTA reduction or global routing decision.\n- **Communication:** identify the producer and every consumer of each\n intermediate. Use the synchronization scope and memory space actually needed;\n fusion is not restricted to one CTA, but multi-CTA communication has its own\n legality and completion rules.\n- **Resources:** record registers, spills, SMEM, TMEM, barriers, threads, cluster\n shape, and occupancy. Added live values can raise register or shared-memory\n pressure even when a global intermediate disappears.\n- **TMEM:** SM100 TMEM is 128 lanes by 512 columns of 32-bit cells per SM.\n Simultaneously live regions must fit, use legal collective allocation sizes,\n remain live through every asynchronous access, and be collectively freed.\n Two 256-column halves are one possible allocation policy, not the total\n hardware capacity or a dual-GEMM requirement.\n- **Fallbacks:** keep unfused or differently fused paths for shapes, dtypes,\n layouts, reductions, or resource footprints that the fused schedule cannot\n implement safely."}, "reason": {"statement": "State 512-column capacity and implementation-specific live-region accounting.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/kernel-fusion.md", "before": {"statement": "- Fusion opportunities depend on dataflow shape (dependency graph must be DAG-compatible with CTA scope)"}, "after": {"statement": "- **Semantics:** preserve routing, scale, bias, activation, reduction,\n accumulation, dtype, ordering, and output-edge behavior. A pointwise epilogue\n is easier to compose than a cross-CTA reduction or global routing decision.\n- **Communication:** identify the producer and every consumer of each\n intermediate. Use the synchronization scope and memory space actually needed;\n fusion is not restricted to one CTA, but multi-CTA communication has its own\n legality and completion rules.\n- **Resources:** record registers, spills, SMEM, TMEM, barriers, threads, cluster\n shape, and occupancy. Added live values can raise register or shared-memory\n pressure even when a global intermediate disappears.\n- **TMEM:** SM100 TMEM is 128 lanes by 512 columns of 32-bit cells per SM.\n Simultaneously live regions must fit, use legal collective allocation sizes,\n remain live through every asynchronous access, and be collectively freed.\n Two 256-column halves are one possible allocation policy, not the total\n hardware capacity or a dual-GEMM requirement.\n- **Fallbacks:** keep unfused or differently fused paths for shapes, dtypes,\n layouts, reductions, or resource footprints that the fused schedule cannot\n implement safely."}, "reason": {"statement": "Replace vague scope jargon with explicit correctness/resource questions.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#occupancy-calculator"]}} +{"path": "wiki/techniques/register-budgeting.md", "before": {"statement": "SM occupancy is inversely proportional to registers-per-thread. For memory-bound kernels, higher occupancy = more warps to hide memory latency. `-maxrregcount` and `__launch_bounds__` force the compiler to stay within a budget."}, "after": {"statement": "Registers per thread are one input to residency. Threads per block, static and dynamic shared memory, architectural limits, allocation granularity, barriers, and cluster configuration can impose other limits. Register thresholds therefore produce discrete changes in active blocks or warps; occupancy is not generally the reciprocal of a source-level register count, and higher predicted occupancy does not by itself imply lower latency.\n\nThe CUDA occupancy API evaluates the compiled function with an intended block size and dynamic shared-memory size. `cudaOccupancyMaxActiveBlocksPerMultiprocessor` returns the maximum active blocks per SM for that configuration. Convert that result to active warps only after multiplying by the actual warps per block.\n\nFor tcgen05 MMA, the resident D accumulator is in TMEM rather than a per-thread D register vector. This changes one major register consumer, but it does not erase register pressure: descriptors, addresses, pipeline/control state, operands, and epilogue batches still use general-purpose registers. The pinned SM100 DeepGEMM path explicitly loads completed TMEM values into registers before its shared/global-store epilogue.\n\nTreat the removed D vector as shape-specific. For example, an SM90 m64n256 FP32 WGMMA fragment exposes 128 D registers per participating thread, but that number is not a universal Blackwell saving and does not predict a resident-block transition."}, "reason": {"statement": "Use the resource-threshold model and scope the TMEM effect to the resident D fragment.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.0/cuda-c-programming-guide/index.html", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm100_fp8_gemm_1d1d.cuh", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-runtime-api/group__CUDART__OCCUPANCY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/arch/mma_sm90_gmma.hpp"]}} +{"path": "wiki/techniques/register-budgeting.md", "before": {"statement": "```cuda\n// Aggressive: 32 registers/thread → ~4 blocks per SM at 256 threads/block\n__launch_bounds__(256, 4)\n__global__ void gemv_memory_bound(...) {\n // Compiler will spill to local memory if needed\n}\n\n// Or via nvcc flag:\n// nvcc -maxrregcount=32 -arch=sm_100a ...\n```"}, "after": {"statement": "| `--maxrregcount=N` | Sets a maximum for GPU functions, subject to the ABI minimum and compiler-reserved registers | That the compiler will use exactly `N`, or that residency/performance will change |\n| `__launch_bounds__(T, B)` | Supplies maximum threads per block and desired minimum blocks per SM; the compiler derives an architecture-dependent register limit `L` | Exactly `B` resident blocks when shared memory or another resource is limiting |\n| `--resource-usage` | Reports registers, stack frame, spill loads/stores, and other resources for compiled functions | Runtime occupancy or the cost of those resources |\n| Occupancy API | Predicts maximum concurrent blocks for the compiled function and launch inputs | Achieved latency, bandwidth, or throughput |\n\nWhen launch bounds make initial register use exceed `L`, CUDA documents that the compiler usually trades registers for more local-memory use and/or instructions. When both `T` and `B` are supplied and initial use is below `L`, the compiler may instead increase register use up to `L` to reduce instruction count. A launch bound is therefore compiler guidance and a launch constraint, not an exact register assignment.\n\nCompile the same source and target first without a cap, then with candidate caps. `--resource-usage` makes a cap that does not change the compiled allocation visible.\n\n```bash\nnvcc -arch=sm_100a --resource-usage kernel.cu -o kernel-default\nnvcc -arch=sm_100a --maxrregcount=64 --resource-usage kernel.cu -o kernel-r64\n```\n\nFor each binary and each supported production shape:\n\n1. Record toolkit, target, compiler options, registers per thread, stack-frame bytes, spill loads/stores, static/dynamic shared memory, block size, and cluster shape.\n2. Query active blocks with the occupancy API using the exact function, block size, and dynamic shared-memory bytes. Identify which resource is actually limiting residency.\n3. Verify that the candidate cap changed generated resources or code before attributing a timing change to it. Inspect PTX/SASS when instruction selection or loop shape may have changed.\n4. Run the same correctness oracle, warmup, synchronization, inputs, and repeated-trial statistic for every variant. Profile spill traffic, memory stalls, and achieved warps rather than assuming the predicted occupancy is reached or useful.\n5. Keep a cap only for the measured target and workload where it improves the declared metric without violating correctness or a resource contract."}, "reason": {"statement": "The fenced snippet is incomplete CUDA and encodes false numeric implications.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.0/cuda-c-programming-guide/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html"]}} +{"path": "wiki/techniques/register-budgeting.md", "before": {"statement": "Lower register count → compiler may:\n- Spill frequently-used values to local memory (bad)\n- Recompute values instead of storing them (neutral)\n- Use fewer unrolled iterations (bad for compute-bound)"}, "after": {"statement": "| `--maxrregcount=N` | Sets a maximum for GPU functions, subject to the ABI minimum and compiler-reserved registers | That the compiler will use exactly `N`, or that residency/performance will change |\n| `__launch_bounds__(T, B)` | Supplies maximum threads per block and desired minimum blocks per SM; the compiler derives an architecture-dependent register limit `L` | Exactly `B` resident blocks when shared memory or another resource is limiting |\n| `--resource-usage` | Reports registers, stack frame, spill loads/stores, and other resources for compiled functions | Runtime occupancy or the cost of those resources |\n| Occupancy API | Predicts maximum concurrent blocks for the compiled function and launch inputs | Achieved latency, bandwidth, or throughput |\n\nWhen launch bounds make initial register use exceed `L`, CUDA documents that the compiler usually trades registers for more local-memory use and/or instructions. When both `T` and `B` are supplied and initial use is below `L`, the compiler may instead increase register use up to `L` to reduce instruction count. A launch bound is therefore compiler guidance and a launch constraint, not an exact register assignment.\n\nCompile the same source and target first without a cap, then with candidate caps. `--resource-usage` makes a cap that does not change the compiled allocation visible.\n\n```bash\nnvcc -arch=sm_100a --resource-usage kernel.cu -o kernel-default\nnvcc -arch=sm_100a --maxrregcount=64 --resource-usage kernel.cu -o kernel-r64\n```\n\nFor each binary and each supported production shape:\n\n1. Record toolkit, target, compiler options, registers per thread, stack-frame bytes, spill loads/stores, static/dynamic shared memory, block size, and cluster shape.\n2. Query active blocks with the occupancy API using the exact function, block size, and dynamic shared-memory bytes. Identify which resource is actually limiting residency.\n3. Verify that the candidate cap changed generated resources or code before attributing a timing change to it. Inspect PTX/SASS when instruction selection or loop shape may have changed.\n4. Run the same correctness oracle, warmup, synchronization, inputs, and repeated-trial statistic for every variant. Profile spill traffic, memory stalls, and achieved warps rather than assuming the predicted occupancy is reached or useful.\n5. Keep a cap only for the measured target and workload where it improves the declared metric without violating correctness or a resource contract."}, "reason": {"statement": "Describe compiler responses as possible costs to measure.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.0/cuda-c-programming-guide/index.html", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html"]}} +{"path": "wiki/techniques/register-budgeting.md", "before": {"statement": "For memory-bound kernels, spills can be hidden by memory latency anyway, so aggressive budgeting often wins."}, "after": {"statement": "Spill loads and stores use thread-local stack memory backed by the memory hierarchy. They add instructions and traffic; a memory-bound label is not evidence that this cost will be hidden. Conversely, a lower cap can be irrelevant when the uncapped allocation is already below it."}, "reason": {"statement": "Require controlled variants instead of a directional guarantee.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"]}} +{"path": "wiki/techniques/register-budgeting.md", "before": {"statement": "| 1 | 32 | 18.5μs |\n| 3 | 45 | ~20μs |"}, "after": {"statement": "Amandeep Singh reports that three inspected B200 NVFP4 GEMV solutions clustered around an 18.5 microsecond geometric mean, with a 32-register cap in rank 1 and 45 in rank 3. The same report says those solutions also differed in PTX decode, cache policies, load widths, exact-K specialization, and B reuse; it provides no controlled register-cap ablation or public contestant code. In the author's own kernel, lowering the cap from 80 to 64 had no effect because natural use was already below 64, while extra accumulator chains and software pipelining increased pressure and regressed.\n\nThat observation motivates inspecting register allocation; it does not prove that 32 beats 45, that occupancy caused the ranking, or that aggressive caps generally help memory-bound kernels."}, "reason": {"statement": "Preserve only the author's scoped observation and its provenance limit.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"]}} +{"path": "wiki/techniques/register-budgeting.md", "before": {"statement": "The measurable difference between 32 and 45 registers shows occupancy dominates for memory-bound NVFP4 GEMV."}, "after": {"statement": "Spill loads and stores use thread-local stack memory backed by the memory hierarchy. They add instructions and traffic; a memory-bound label is not evidence that this cost will be hidden. Conversely, a lower cap can be irrelevant when the uncapped allocation is already below it.\n\nAmandeep Singh reports that three inspected B200 NVFP4 GEMV solutions clustered around an 18.5 microsecond geometric mean, with a 32-register cap in rank 1 and 45 in rank 3. The same report says those solutions also differed in PTX decode, cache policies, load widths, exact-K specialization, and B reuse; it provides no controlled register-cap ablation or public contestant code. In the author's own kernel, lowering the cap from 80 to 64 had no effect because natural use was already below 64, while extra accumulator chains and software pipelining increased pressure and regressed.\n\nThat observation motivates inspecting register allocation; it does not prove that 32 beats 45, that occupancy caused the ranking, or that aggressive caps generally help memory-bound kernels."}, "reason": {"statement": "Do not infer causality from confounded implementations.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html"]}} +{"path": "wiki/techniques/register-budgeting.md", "before": {"statement": "- Memory-bound kernels (first priority: occupancy)\n- Kernels where register pressure comes from inner loop, not accumulators (TMEM handles accumulators)\n- Sub-byte types with heavy decode/scale computation\n\n- Compute-bound GEMM (let compiler use what it needs)\n- Kernels where spills to local memory would serialize"}, "after": {"statement": "Compile the same source and target first without a cap, then with candidate caps. `--resource-usage` makes a cap that does not change the compiled allocation visible.\n\n```bash\nnvcc -arch=sm_100a --resource-usage kernel.cu -o kernel-default\nnvcc -arch=sm_100a --maxrregcount=64 --resource-usage kernel.cu -o kernel-r64\n```\n\nFor each binary and each supported production shape:\n\n1. Record toolkit, target, compiler options, registers per thread, stack-frame bytes, spill loads/stores, static/dynamic shared memory, block size, and cluster shape.\n2. Query active blocks with the occupancy API using the exact function, block size, and dynamic shared-memory bytes. Identify which resource is actually limiting residency.\n3. Verify that the candidate cap changed generated resources or code before attributing a timing change to it. Inspect PTX/SASS when instruction selection or loop shape may have changed.\n4. Run the same correctness oracle, warmup, synchronization, inputs, and repeated-trial statistic for every variant. Profile spill traffic, memory stalls, and achieved warps rather than assuming the predicted occupancy is reached or useful.\n5. Keep a cap only for the measured target and workload where it improves the declared metric without violating correctness or a resource contract.\n\nSpill loads and stores use thread-local stack memory backed by the memory hierarchy. They add instructions and traffic; a memory-bound label is not evidence that this cost will be hidden. Conversely, a lower cap can be irrelevant when the uncapped allocation is already below it.\n\nFor tcgen05 MMA, the resident D accumulator is in TMEM rather than a per-thread D register vector. This changes one major register consumer, but it does not erase register pressure: descriptors, addresses, pipeline/control state, operands, and epilogue batches still use general-purpose registers. The pinned SM100 DeepGEMM path explicitly loads completed TMEM values into registers before its shared/global-store epilogue.\n\nTreat the removed D vector as shape-specific. For example, an SM90 m64n256 FP32 WGMMA fragment exposes 128 D registers per participating thread, but that number is not a universal Blackwell saving and does not predict a resident-block transition."}, "reason": {"statement": "Replace categories with a decision procedure based on the compiled kernel and controlled benchmarks.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.0/cuda-c-programming-guide/index.html", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm100_fp8_gemm_1d1d.cuh", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/arch/mma_sm90_gmma.hpp"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "FlashAttention-4 replaces the hardware Special Function Unit (SFU) exponential (`ex2.approx`) with a software-emulated 2^x function that distributes computation across the SM's FMA (fused multiply-add) units. On Blackwell, tensor core throughput doubled compared to Hopper while SFU count remained the same, making the SFU the throughput bottleneck for attention's softmax operation. The software exponential uses Cody-Waite range reduction followed by a Horner-form polynomial evaluation, achieving sufficient accuracy for attention while bypassing the SFU entirely."}, "after": {"statement": "FlashAttention-4 (FA4) combines two paths for base-2 exponential in its Blackwell forward softmax. Most selected configurations retain hardware `exp2` for some entries and evaluate a tunable fraction with a software polynomial on general-purpose FMA pipelines. The paper describes roughly 10–25% software evaluation, while the exact fraction is a configuration choice rather than an architecture constant.\n\nThis hybrid is part of a larger schedule: two 128-thread softmax warpgroups alternate 128-row query tiles, synchronize to limit simultaneous exponential contention, stage probabilities through TMEM, and hand conditional rescaling to a correction warpgroup. A standalone polynomial is not equivalent to that pipeline.\n\nAt Dao-AILab/flash-attention revision `a369df707e1980fb328abcc1733e3457ec10155f`, [`flash_attn/cute/utils.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/utils.py) defines the default software path and [`flash_attn/cute/softmax.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/softmax.py) performs fragment-level hardware/software selection.\n\nFor each software-selected pair, the pinned implementation:\n\n1. Assumes each input is no greater than 127 and clamps values below `-127`.\n2. Uses a rounding-down addition with the float32 constant `2^23 + 2^22` to recover the integer floor and a fractional value in `[0,1)`.\n3. Evaluates a degree-3 polynomial in Horner form with packed float32 FMA operations.\n4. Combines the integer contribution with the polynomial's float32 representation by exponent-field integer operations; the software branch does not call `ex2.approx` for reconstruction.\n\nThe degree-3 float32 coefficients in that revision are:\n\n| `p0` | `1.0` |\n| `p1` | `0.695146143436431884765625` |\n| `p2` | `0.227564394474029541015625` |\n| `p3` | `0.077119089663028717041015625` |\n\nThe authors state that Sollya selected these coefficients to minimize relative error for `2^f` over `f in [0,1)`. For a natural exponential, the caller uses the identity `e^z = 2^(z * log2(e))`."}, "reason": {"statement": "Describe the hybrid degree-3 implementation exactly.", "urls": ["https://tridao.me/blog/2026/flash4/", "https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute", "https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/utils.py"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "The softmax in attention requires computing `exp(x - max)` for every element of the score matrix. On previous generations, the SFU's `ex2.approx` instruction was fast enough relative to the MMA throughput. On Blackwell:\n\n| Tensor core TFLOPS (BF16) | ~990 | ~2250 | 2.27x |\n| SFU units per SM | 16 | 16 | 1.0x |\n| SFU throughput (exp per cycle) | 16 | 16 | 1.0x |\n| FMA units per SM | 128 | 128 | 1.0x |\n\nThe tensor cores produce 2x more score elements per cycle, but the SFU can only process exp() at the same rate as before. This makes the SFU the bottleneck for any kernel that needs exp() proportional to the number of MMA outputs.\n\nFlashAttention-4's approach: distribute the exp() workload across FMA units (128 per SM) instead of SFU units (16 per SM), achieving 8x the throughput for the exponential computation."}, "after": {"statement": "For the authors' `M=N=D=128` B200 feeds-and-speeds model, one SM supplies 8192 BF16 tensor-core operations per cycle, 16 exponential operations per cycle, and 128 shared-memory bytes per cycle. Their forward-tile accounting assigns 1024 cycles to two MMAs, 1024 cycles to 128×128 exponentials, and 768 cycles to shared-memory traffic.\n\nThose are analytical inputs for that tile and schedule. They do not imply that every kernel with one exponential per MMA output is exponential-bound, nor do functional-unit counts give the throughput or latency of a software approximation. Range reduction, polynomial dependencies, reconstruction, instruction issue, and overlap all remain part of the measured implementation."}, "reason": {"statement": "Retain only the source's scoped feeds-and-speeds model.", "urls": ["https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "Range reduction transforms the input `x` into a small residual that a polynomial can accurately approximate. The Cody-Waite method splits the input into an integer part (for exact power-of-two scaling) and a fractional part (for polynomial approximation):\n\n```cuda\n// Cody-Waite range reduction for 2^x\n// Goal: decompose x = n + r where n is integer, r in [-0.5, 0.5]\n// Then 2^x = 2^n * 2^r, and 2^r is approximated by polynomial\n//\n// The Cody-Waite trick: subtract n using two constants (C1 + C2)\n// to maintain precision when x is large.\n//\n// C1 is the nearest representable float to log2(e) with low-order bits zeroed\n// C2 is the correction: log2(e) - C1\n// This avoids catastrophic cancellation in x - n\n\n__device__ float software_exp2(float x) {\n // Step 1: Range reduction (Cody-Waite)\n // Round x to nearest integer\n float n = rintf(x);\n // High-precision subtraction using two constants\n // C1 and C2 together represent 1.0 in extended precision\n const float C1 = 1.0f; // Exact in float\n const float C2 = 0.0f; // Correction term (zero for 2^x, non-zero for e^x)\n // For 2^x, range reduction is simpler: r = x - n\n float r = x - n; // r in [-0.5, 0.5]\n\n // Step 2: Polynomial approximation of 2^r via Horner's method\n // Minimax polynomial coefficients for 2^r on [-0.5, 0.5]\n // Degree-4 polynomial: sufficient for ~22 bits of accuracy\n const float c0 = 1.0f;\n const float c1 = 0.6931471805599453f; // ln(2)\n const float c2 = 0.2402265069591007f; // ln(2)^2 / 2\n const float c3 = 0.05550410866482158f; // ln(2)^3 / 6\n const float c4 = 0.009618129107628477f; // ln(2)^4 / 24\n\n // Horner evaluation: c0 + r*(c1 + r*(c2 + r*(c3 + r*c4)))\n // Each step is one FMA instruction\n float poly = c4;\n poly = fmaf(poly, r, c3); // FMA 1\n poly = fmaf(poly, r, c2); // FMA 2\n poly = fmaf(poly, r, c1); // FMA 3\n poly = fmaf(poly, r, c0); // FMA 4\n\n // Step 3: Reconstruct 2^x = 2^n * poly\n // Use integer addition to the float exponent field\n int n_int = (int)n;\n // ldexpf multiplies by 2^n by adjusting the exponent bits\n float result = ldexpf(poly, n_int);\n\n return result;\n}\n```"}, "after": {"statement": "At Dao-AILab/flash-attention revision `a369df707e1980fb328abcc1733e3457ec10155f`, [`flash_attn/cute/utils.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/utils.py) defines the default software path and [`flash_attn/cute/softmax.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/softmax.py) performs fragment-level hardware/software selection.\n\nFor each software-selected pair, the pinned implementation:\n\n1. Assumes each input is no greater than 127 and clamps values below `-127`.\n2. Uses a rounding-down addition with the float32 constant `2^23 + 2^22` to recover the integer floor and a fractional value in `[0,1)`.\n3. Evaluates a degree-3 polynomial in Horner form with packed float32 FMA operations.\n4. Combines the integer contribution with the polynomial's float32 representation by exponent-field integer operations; the software branch does not call `ex2.approx` for reconstruction.\n\nThe degree-3 float32 coefficients in that revision are:\n\n| `p0` | `1.0` |\n| `p1` | `0.695146143436431884765625` |\n| `p2` | `0.227564394474029541015625` |\n| `p3` | `0.077119089663028717041015625` |\n\nThe authors state that Sollya selected these coefficients to minimize relative error for `2^f` over `f in [0,1)`. For a natural exponential, the caller uses the identity `e^z = 2^(z * log2(e))`.\n\nThe polynomial is approximate. On a deterministic host grid of 1,000,002 evenly spaced points over `[0,1]`, evaluating the rounded degree-3 coefficients against `2^x` produced a maximum sampled relative error of approximately `8.763e-5`. This is a regression observation, not a proof of the continuous maximum and not an end-to-end attention tolerance."}, "reason": {"statement": "Avoid presenting invented CUDA as upstream or accuracy-validated.", "urls": ["https://tridao.me/blog/2026/flash4/", "https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/utils.py"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "The key insight is that Horner polynomial evaluation is a chain of FMA operations. With the softmax warp executing on CUDA cores while the MMA warp uses tensor cores, the FMA throughput is fully available:\n\n```cuda\n// FlashAttention-4 softmax with software exp2\n// Executed by dedicated softmax warpgroups (part of warp specialization)\n//\n// For each row of the score matrix S[i,:]:\n// 1. Find row max: m_new = max(S[i,:])\n// 2. Compute exp2((S[i,j] - m_new) * log2(e)) for each j\n// 3. Sum for normalization denominator\n// 4. Conditionally rescale previous output if max changed\n\n__device__ void softmax_with_software_exp(\n float* scores, // Input: S[i, 0..N-1] (one row)\n float* output, // Output: softmax(S[i,:])\n int N,\n float* row_max, // Running max (for online softmax)\n float* row_sum) // Running sum\n{\n int lane = threadIdx.x % 32;\n\n // Step 1: Find max across the row (warp reduction)\n float local_max = -INFINITY;\n for (int j = lane; j < N; j += 32) {\n local_max = fmaxf(local_max, scores[j]);\n }\n // Warp-level max reduction\n for (int offset = 16; offset > 0; offset >>= 1) {\n local_max = fmaxf(local_max, __shfl_xor_sync(0xFFFFFFFF, local_max, offset));\n }\n float m_new = local_max;\n\n // Step 2: Compute software exp2 and sum\n float local_sum = 0.0f;\n const float LOG2E = 1.4426950408889634f;\n\n for (int j = lane; j < N; j += 32) {\n float x = (scores[j] - m_new) * LOG2E;\n float exp_val = software_exp2(x); // 4 FMAs instead of 1 SFU op\n output[j] = exp_val;\n local_sum += exp_val;\n }\n\n // Warp-level sum reduction\n for (int offset = 16; offset > 0; offset >>= 1) {\n local_sum += __shfl_xor_sync(0xFFFFFFFF, local_sum, offset);\n }\n\n // Step 3: Conditional rescaling (FlashAttention online softmax)\n float m_old = *row_max;\n if (m_new > m_old) {\n // Rescale previous accumulated output\n float scale = software_exp2((m_old - m_new) * LOG2E);\n *row_sum = (*row_sum) * scale + local_sum;\n *row_max = m_new;\n // The output accumulator must also be rescaled by `scale`\n } else {\n float scale = software_exp2((m_new - m_old) * LOG2E);\n *row_sum += local_sum * scale;\n // Rescale current exp values, not the accumulator\n }\n}\n```"}, "after": {"statement": "FlashAttention-4 (FA4) combines two paths for base-2 exponential in its Blackwell forward softmax. Most selected configurations retain hardware `exp2` for some entries and evaluate a tunable fraction with a software polynomial on general-purpose FMA pipelines. The paper describes roughly 10–25% software evaluation, while the exact fraction is a configuration choice rather than an architecture constant.\n\nThis hybrid is part of a larger schedule: two 128-thread softmax warpgroups alternate 128-row query tiles, synchronize to limit simultaneous exponential contention, stage probabilities through TMEM, and hand conditional rescaling to a correction warpgroup. A standalone polynomial is not equivalent to that pipeline.\n\nBF16 conversion does not by itself prove that approximation errors are harmless. Per-entry error changes both the softmax numerator and row sum, and masking, all-`-inf` rows, conditional rescaling, underflow clamping, and output accumulation introduce separate boundary cases. Validate the scalar approximation and the complete attention output for the exact dtype and features.\n\nUse the pinned implementation as the starting point; do not reconstruct it from rounded blog coefficients. For each target configuration:\n\n1. Build an all-hardware control and one or more hybrid selections from the same source revision, compiler, target, and launch configuration.\n2. Inspect generated PTX/SASS to confirm which entries use hardware `MUFU.EX2`, which use the expected FMA/range-reduction sequence, and whether register use or spills changed.\n3. Test ordinary, masked, all-masked, causal, variable-length, large-gap, and underflow-heavy rows against a declared higher-precision reference. Record maximum absolute/relative output error and row-sum behavior, not only BF16 agreement on random inputs.\n4. Profile exponential-pipeline pressure, FMA/ALU issue, tensor-core overlap, registers, and spills. A high hardware-exp metric is a lead, not proof that moving more entries to FMA improves the schedule.\n5. Benchmark identical shapes, inputs, warmup, synchronization, clock policy, and repeated-trial statistics. Sweep the software fraction because both zero emulation and mixed settings appear in the pinned target/configuration table.\n\nKeep the hybrid only where both the numerical contract and declared end-to-end metric pass. Do not transfer the choice to another architecture or transcendental function without repeating the reduction, approximation, special-value, generated-code, and performance checks."}, "reason": {"statement": "Point to pinned implementation structure instead of non-runnable reconstructed code.", "urls": ["https://tridao.me/blog/2026/flash4/", "https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "At the PTX level, the Horner polynomial compiles to a tight chain of `fma.rn.f32` instructions:\n\n```ptx\n// Software exp2 via Horner polynomial in PTX\n// Input: %x (float, range-reduced to [-0.5, 0.5])\n// Output: %result (float, approximation of 2^x)\n\n.reg .f32 %x, %r, %n, %poly, %result;\n.reg .f32 %c0, %c1, %c2, %c3, %c4;\n\n// Load polynomial coefficients\nmov.f32 %c0, 0f3F800000; // 1.0\nmov.f32 %c1, 0f3F317218; // 0.6931471805599453 (ln2)\nmov.f32 %c2, 0f3E75FDF0; // 0.2402265069591007\nmov.f32 %c3, 0f3D635847; // 0.05550410866482158\nmov.f32 %c4, 0f3C1D9539; // 0.009618129107628477\n\n// Range reduction: n = rintf(x), r = x - n\ncvt.rni.f32.f32 %n, %x; // Round to nearest int\nsub.f32 %r, %x, %n; // Fractional part\n\n// Horner evaluation: 4 dependent FMAs\n// poly = c4\n// poly = poly * r + c3\n// poly = poly * r + c2\n// poly = poly * r + c1\n// poly = poly * r + c0\nmov.f32 %poly, %c4;\nfma.rn.f32 %poly, %poly, %r, %c3; // FMA 1\nfma.rn.f32 %poly, %poly, %r, %c2; // FMA 2\nfma.rn.f32 %poly, %poly, %r, %c1; // FMA 3\nfma.rn.f32 %poly, %poly, %r, %c0; // FMA 4\n\n// Reconstruct: result = poly * 2^n\n// Convert n to int and use ex2 scaling via bit manipulation\ncvt.rzi.s32.f32 %ni, %n;\nex2.approx.f32 %scale, %n; // Or use integer exponent manipulation\nmul.f32 %result, %poly, %scale;\n```"}, "after": {"statement": "At Dao-AILab/flash-attention revision `a369df707e1980fb328abcc1733e3457ec10155f`, [`flash_attn/cute/utils.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/utils.py) defines the default software path and [`flash_attn/cute/softmax.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/softmax.py) performs fragment-level hardware/software selection.\n\nFor each software-selected pair, the pinned implementation:\n\n1. Assumes each input is no greater than 127 and clamps values below `-127`.\n2. Uses a rounding-down addition with the float32 constant `2^23 + 2^22` to recover the integer floor and a fractional value in `[0,1)`.\n3. Evaluates a degree-3 polynomial in Horner form with packed float32 FMA operations.\n4. Combines the integer contribution with the polynomial's float32 representation by exponent-field integer operations; the software branch does not call `ex2.approx` for reconstruction.\n\nThe degree-3 float32 coefficients in that revision are:\n\n| `p0` | `1.0` |\n| `p1` | `0.695146143436431884765625` |\n| `p2` | `0.227564394474029541015625` |\n| `p3` | `0.077119089663028717041015625` |\n\nThe authors state that Sollya selected these coefficients to minimize relative error for `2^f` over `f in [0,1)`. For a natural exponential, the caller uses the identity `e^z = 2^(z * log2(e))`."}, "reason": {"statement": "Cite exact source functions and generated-code inspection requirements.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html", "https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/utils.py", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "The degree-4 polynomial provides approximately 22 bits of mantissa accuracy, which is more than sufficient for attention softmax where:"}, "after": {"statement": "The polynomial is approximate. On a deterministic host grid of 1,000,002 evenly spaced points over `[0,1]`, evaluating the rounded degree-3 coefficients against `2^x` produced a maximum sampled relative error of approximately `8.763e-5`. This is a regression observation, not a proof of the continuous maximum and not an end-to-end attention tolerance."}, "reason": {"statement": "Do not attach an unsupported error guarantee to a non-upstream polynomial.", "urls": []}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "- **Attention kernels on Blackwell**: Whenever the SFU is the bottleneck for softmax computation. FlashAttention-4 measured 1.1-1.3x speedup over cuDNN from this technique alone on B200."}, "after": {"statement": "The FA4 blog reports complete forward-pass speedups of 1.1–1.3× over cuDNN 9.13 on its evaluated B200 BF16 configurations. That comparison includes the full FA4 co-design—pipelining, hybrid exponentials, conditional rescaling, TMEM staging, scheduling, and other choices. It is not a software-exponential-only ablation and must not be used as the isolated speedup of this technique."}, "reason": {"statement": "Scope numbers to the full system and require a matched ablation for this technique.", "urls": ["https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "- **Any kernel limited by transcendental function throughput**: If profiling shows SFU utilization near 100% while FMA utilization is low, software emulation can rebalance the workload.\n- **Not recommended on Hopper**: The SFU-to-MMA throughput ratio is better balanced on SM90. The overhead of 4 FMAs vs 1 SFU instruction is not justified unless the SFU is proven to be the bottleneck."}, "after": {"statement": "BF16 conversion does not by itself prove that approximation errors are harmless. Per-entry error changes both the softmax numerator and row sum, and masking, all-`-inf` rows, conditional rescaling, underflow clamping, and output accumulation introduce separate boundary cases. Validate the scalar approximation and the complete attention output for the exact dtype and features.\n\nUse the pinned implementation as the starting point; do not reconstruct it from rounded blog coefficients. For each target configuration:\n\n1. Build an all-hardware control and one or more hybrid selections from the same source revision, compiler, target, and launch configuration.\n2. Inspect generated PTX/SASS to confirm which entries use hardware `MUFU.EX2`, which use the expected FMA/range-reduction sequence, and whether register use or spills changed.\n3. Test ordinary, masked, all-masked, causal, variable-length, large-gap, and underflow-heavy rows against a declared higher-precision reference. Record maximum absolute/relative output error and row-sum behavior, not only BF16 agreement on random inputs.\n4. Profile exponential-pipeline pressure, FMA/ALU issue, tensor-core overlap, registers, and spills. A high hardware-exp metric is a lead, not proof that moving more entries to FMA improves the schedule.\n5. Benchmark identical shapes, inputs, warmup, synchronization, clock policy, and repeated-trial statistics. Sweep the software fraction because both zero emulation and mixed settings appear in the pinned target/configuration table.\n\nKeep the hybrid only where both the numerical contract and declared end-to-end metric pass. Do not transfer the choice to another architecture or transcendental function without repeating the reduction, approximation, special-value, generated-code, and performance checks."}, "reason": {"statement": "Use measurable preconditions and target-specific validation.", "urls": ["https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f", "https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "- The 4-FMA chain has a latency of ~16 cycles (4 dependent FMAs at ~4 cycles each), vs ~20 cycles for SFU `ex2.approx`. Latency is comparable; the win comes from throughput (128 FMA units vs 16 SFU units)."}, "after": {"statement": "For the authors' `M=N=D=128` B200 feeds-and-speeds model, one SM supplies 8192 BF16 tensor-core operations per cycle, 16 exponential operations per cycle, and 128 shared-memory bytes per cycle. Their forward-tile accounting assigns 1024 cycles to two MMAs, 1024 cycles to 128×128 exponentials, and 768 cycles to shared-memory traffic.\n\nThose are analytical inputs for that tile and schedule. They do not imply that every kernel with one exponential per MMA output is exponential-bound, nor do functional-unit counts give the throughput or latency of a software approximation. Range reduction, polynomial dependencies, reconstruction, instruction issue, and overlap all remain part of the measured implementation.\n\nBF16 conversion does not by itself prove that approximation errors are harmless. Per-entry error changes both the softmax numerator and row sum, and masking, all-`-inf` rows, conditional rescaling, underflow clamping, and output accumulation introduce separate boundary cases. Validate the scalar approximation and the complete attention output for the exact dtype and features.\n\nUse the pinned implementation as the starting point; do not reconstruct it from rounded blog coefficients. For each target configuration:\n\n1. Build an all-hardware control and one or more hybrid selections from the same source revision, compiler, target, and launch configuration.\n2. Inspect generated PTX/SASS to confirm which entries use hardware `MUFU.EX2`, which use the expected FMA/range-reduction sequence, and whether register use or spills changed.\n3. Test ordinary, masked, all-masked, causal, variable-length, large-gap, and underflow-heavy rows against a declared higher-precision reference. Record maximum absolute/relative output error and row-sum behavior, not only BF16 agreement on random inputs.\n4. Profile exponential-pipeline pressure, FMA/ALU issue, tensor-core overlap, registers, and spills. A high hardware-exp metric is a lead, not proof that moving more entries to FMA improves the schedule.\n5. Benchmark identical shapes, inputs, warmup, synchronization, clock policy, and repeated-trial statistics. Sweep the software fraction because both zero emulation and mixed settings appear in the pinned target/configuration table.\n\nKeep the hybrid only where both the numerical contract and declared end-to-end metric pass. Do not transfer the choice to another architecture or transcendental function without repeating the reduction, approximation, special-value, generated-code, and performance checks."}, "reason": {"statement": "Do not preserve unattributed cycle counts.", "urls": ["https://tridao.me/blog/2026/flash4/", "https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "- The `ldexpf` or exponent bit-manipulation step for 2^n must handle overflow/underflow (very large/small x). In attention, `x <= 0` always holds, so only underflow toward zero is possible."}, "after": {"statement": "At Dao-AILab/flash-attention revision `a369df707e1980fb328abcc1733e3457ec10155f`, [`flash_attn/cute/utils.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/utils.py) defines the default software path and [`flash_attn/cute/softmax.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/softmax.py) performs fragment-level hardware/software selection.\n\nFor each software-selected pair, the pinned implementation:\n\n1. Assumes each input is no greater than 127 and clamps values below `-127`.\n2. Uses a rounding-down addition with the float32 constant `2^23 + 2^22` to recover the integer floor and a fractional value in `[0,1)`.\n3. Evaluates a degree-3 polynomial in Horner form with packed float32 FMA operations.\n4. Combines the integer contribution with the polynomial's float32 representation by exponent-field integer operations; the software branch does not call `ex2.approx` for reconstruction.\n\nThe degree-3 float32 coefficients in that revision are:\n\n| `p0` | `1.0` |\n| `p1` | `0.695146143436431884765625` |\n| `p2` | `0.227564394474029541015625` |\n| `p3` | `0.077119089663028717041015625` |\n\nThe authors state that Sollya selected these coefficients to minimize relative error for `2^f` over `f in [0,1)`. For a natural exponential, the caller uses the identity `e^z = 2^(z * log2(e))`.\n\nThe polynomial is approximate. On a deterministic host grid of 1,000,002 evenly spaced points over `[0,1]`, evaluating the rounded degree-3 coefficients against `2^x` produced a maximum sampled relative error of approximately `8.763e-5`. This is a regression observation, not a proof of the continuous maximum and not an end-to-end attention tolerance."}, "reason": {"statement": "State the exact helper domain and require special-case handling at the caller.", "urls": ["https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/utils.py", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/techniques/software-exp.md", "before": {"statement": "- The input `x = (S[i,j] - max) * log2(e)` is always non-positive\n- The softmax output is normalized, so small absolute errors cancel out\n- BF16 output has only 7 mantissa bits anyway\n\nFor applications requiring higher accuracy, a degree-6 polynomial (6 FMAs) achieves near-ULP accuracy across the full float range."}, "after": {"statement": "The polynomial is approximate. On a deterministic host grid of 1,000,002 evenly spaced points over `[0,1]`, evaluating the rounded degree-3 coefficients against `2^x` produced a maximum sampled relative error of approximately `8.763e-5`. This is a regression observation, not a proof of the continuous maximum and not an end-to-end attention tolerance.\n\nBF16 conversion does not by itself prove that approximation errors are harmless. Per-entry error changes both the softmax numerator and row sum, and masking, all-`-inf` rows, conditional rescaling, underflow clamping, and output accumulation introduce separate boundary cases. Validate the scalar approximation and the complete attention output for the exact dtype and features.\n\nUse the pinned implementation as the starting point; do not reconstruct it from rounded blog coefficients. For each target configuration:\n\n1. Build an all-hardware control and one or more hybrid selections from the same source revision, compiler, target, and launch configuration.\n2. Inspect generated PTX/SASS to confirm which entries use hardware `MUFU.EX2`, which use the expected FMA/range-reduction sequence, and whether register use or spills changed.\n3. Test ordinary, masked, all-masked, causal, variable-length, large-gap, and underflow-heavy rows against a declared higher-precision reference. Record maximum absolute/relative output error and row-sum behavior, not only BF16 agreement on random inputs.\n4. Profile exponential-pipeline pressure, FMA/ALU issue, tensor-core overlap, registers, and spills. A high hardware-exp metric is a lead, not proof that moving more entries to FMA improves the schedule.\n5. Benchmark identical shapes, inputs, warmup, synchronization, clock policy, and repeated-trial statistics. Sweep the software fraction because both zero emulation and mixed settings appear in the pinned target/configuration table.\n\nKeep the hybrid only where both the numerical contract and declared end-to-end metric pass. Do not transfer the choice to another architecture or transcendental function without repeating the reduction, approximation, special-value, generated-code, and performance checks."}, "reason": {"statement": "Replace universal accuracy claims with an explicit validation protocol.", "urls": ["https://tridao.me/blog/2026/flash4/", "https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/utils.py", "https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute"]}} +{"path": "wiki/techniques/swizzling.md", "before": {"statement": "Shared memory swizzling remaps the linear address layout of a matrix tile in SMEM so that threads accessing consecutive columns (or rows) hit different 32-byte banks rather than the same bank. This eliminates bank conflicts that would otherwise serialize concurrent accesses. On Blackwell (SM100), 128-byte swizzling is mandatory for TMA loads and tcgen05.mma operands. Without it, performance drops to 46% of the achievable throughput for GEMM workloads.\n\nShared memory has 32 banks, each 4 bytes wide (128 bytes total per bank cycle). When a warp accesses a matrix stored in row-major layout, threads in the same warp reading elements from consecutive rows in the same column hit the same bank, causing a 32-way bank conflict.\n\nThe TMA unit on both Hopper and Blackwell encodes the swizzle pattern as part of the tensor descriptor. The tcgen05.mma instruction expects its SMEM operands to already be swizzled in the 128-byte pattern. Using unswizzled data produces incorrect MMA results."}, "after": {"statement": "Shared memory has 32 banks, and successive 32-bit words map to successive banks. For one warp memory request, accesses to different words in the same bank require serialized wavefronts; same-word reads can broadcast and do not create that conflict. The result therefore depends on the exact byte address requested by every participating lane.\n\nA swizzle permutes address chunks so a target access pattern may distribute its requests over banks more evenly. It can reduce conflicts for that pattern, but it does not make every access to the tile conflict-free. A layout favorable to an MMA operand can still be unfavorable to a CUDA-core row, column, transpose, or epilogue access.\n\nFor a TMA-to-tcgen05 path, keep these layers consistent:\n\n1. The tensor map describes how TMA places the global-memory box into shared memory, including interleave and swizzle.\n2. The shared-memory allocation and base address satisfy the alignment and span constraints of that mapping.\n3. The tcgen05 shared-memory descriptor describes the same physical-to-logical layout, leading/stride dimensions, base offset, and swizzle mode expected by the MMA operand.\n\nPTX ISA 9.0 permits ordinary tcgen05 shared-memory descriptor modes with no swizzle and 32B, 64B, or 128B spans, plus a 128B/base-32B mode. In the descriptor's three-bit layout field, ordinary no-swizzle is `0`, 128B/base-32B is `1`, ordinary 128B is `2`, 64B is `4`, and 32B is `6`; values `3`, `5`, and `7` are invalid. Legality also depends on MMA kind, element type, major mode, shape, CTA group, and target.\n\nThe CUDA 13.0.97 Driver API exposes TMA modes including:\n\n| `CU_TENSOR_MAP_SWIZZLE_NONE` | No bank swizzle |\n| `CU_TENSOR_MAP_SWIZZLE_32B` | 16B chunks within a 32B span |\n| `CU_TENSOR_MAP_SWIZZLE_64B` | 16B chunks within a 64B span |\n| `CU_TENSOR_MAP_SWIZZLE_128B` | 16B chunks within a 128B span |\n| `CU_TENSOR_MAP_SWIZZLE_128B_ATOM_32B` | 32B chunks within a 128B span |\n| `CU_TENSOR_MAP_SWIZZLE_128B_ATOM_64B` | 64B chunks within a 128B span; support is operation/type-specific |\n\nThese names define mappings, not universal datatype or tile-size recommendations. The tensor-map encoder imposes mode-, interleave-, datatype-, alignment-, and box-size constraints; for example, ordinary 128B modes require the inner bounding-box byte span not to exceed 128 bytes. Check the exact archived API for the selected type and operation."}, "reason": {"statement": "Define conflicts per access and mode legality per consumer combination.", "urls": ["https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/techniques/swizzling.md", "before": {"statement": "The tcgen05-tutorial benchmark progression shows the impact:\n\n```\nNaive (no swizzle): 255 TFLOPS (17% of cuBLAS)\n128B swizzle applied: 695 TFLOPS (46% of cuBLAS)\n ---- 2.7x improvement from swizzling alone ----\n```"}, "after": {"statement": "Gau Nernst's pinned B200 tutorial compares M=N=K=4096 kernels with PyTorch 2.9.1 and CUDA 13. Its 3D TMA version changes from a 16-byte inner tile with no swizzle to a 128-byte inner tile with 128B swizzling and matching tcgen05 descriptors:\n\n| v1b: 3D 16B TMA | 252.81 |\n| v2b: 3D 128B TMA plus 128B swizzle | 695.43 |\n\nThe combined change is approximately 2.75× and the v2b endpoint is about 46% of the tutorial's 1506.74 TFLOP/s cuBLAS result. It is not a bank-conflict or swizzle-only ablation. The author notes that the earlier contiguous `8×16B` tile might already span all 32 banks, lacked Nsight Compute access, and offers wider TMA transfers as an alternative explanation."}, "reason": {"statement": "Preserve endpoints and list the simultaneous changes and unresolved cause.", "urls": ["https://gau-nernst.github.io/tcgen05/"]}} +{"path": "wiki/techniques/swizzling.md", "before": {"statement": "The swizzle function XORs a portion of the column address with the row address to scatter accesses across banks:\n\n```cuda\n// 128-byte swizzle: XOR bits [4:6] of the byte offset with the row index\n// This ensures that consecutive rows accessing the same logical column\n// map to different physical SMEM banks.\n//\n// For a tile stored in SMEM with TILE_N columns of 2-byte elements:\n// byte_offset = row * (TILE_N * sizeof(half)) + col * sizeof(half)\n// swizzled_offset = byte_offset ^ ((row & 0x7) << 4)\n//\n// The mask 0x7 = 3 bits, shift 4 = bits [4:6], giving 8-row periodicity\n// across the 128-byte bank group.\n\n__device__ int swizzle_128B(int row, int col, int stride_bytes) {\n int byte_offset = row * stride_bytes + col * sizeof(half);\n // XOR bits [4:6] of byte offset with low 3 bits of row\n int swizzled = byte_offset ^ ((row & 0x7) << 4);\n return swizzled;\n}\n```\n\nVisually, for an 8-row x 64-column half-precision tile (128 bytes per row):\n\n```\nWithout swizzle (row-major):\n Row 0: bank 0,1,2,...,31 bank 0,1,2,...,31\n Row 1: bank 0,1,2,...,31 bank 0,1,2,...,31\n Row 2: bank 0,1,2,...,31 bank 0,1,2,...,31\n -> Column access = 8-way bank conflict\n\nWith 128B swizzle (XOR pattern):\n Row 0: bank 0,1,2,...,31 bank 0,1,2,...,31\n Row 1: bank 1,2,3,...,0 bank 1,2,3,...,0 (rotated by 1)\n Row 2: bank 2,3,4,...,1 bank 2,3,4,...,1 (rotated by 2)\n -> Column access = conflict-free\n```"}, "after": {"statement": "CUTLASS 4.5.0 defines [`Swizzle`](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/swizzle.hpp):\n\n- `BBits` is the number of mask bits;\n- `MBase` is the number of least-significant address bits kept invariant; and\n- `SShift` is the distance between the two bit fields.\n\nFor `Swizzle<3,4,3>`, three address bits beginning above the four invariant low bits are XORed with the three-bit field shifted by three positions. Equivalently, address bits 7:9 affect bits 4:6. This is an address transformation, not a general `row & 7` rule: equivalence to row-based indexing depends on stride, byte units, base alignment, and layout composition.\n\nCUTLASS also distinguishes a position-independent composed swizzle layout from a position-dependent swizzle pointer, because hardware swizzling depends on the shared-memory pointer address. Reuse a pinned complete layout/descriptor construction or prove the composition and required base alignment; a `Swizzle` type alone is not a complete TMA or MMA contract."}, "reason": {"statement": "Use exact address-bit semantics and library/descriptor mappings.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/swizzle.hpp", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/pointer_swizzle.hpp"]}} +{"path": "wiki/techniques/swizzling.md", "before": {"statement": "```cuda\n// Creating a TMA descriptor with 128-byte swizzle\n#include \n\nCUtensorMap tensor_map;\n\n// Swizzle mode: CU_TENSOR_MAP_SWIZZLE_128B\n// This tells TMA to apply the 128-byte XOR swizzle pattern\n// when writing data into shared memory\ncuTensorMapEncodeTiled(\n &tensor_map,\n CU_TENSOR_MAP_DATA_TYPE_FLOAT16,\n 2, // 2D tensor\n global_ptr, // global memory base\n global_dims, // {N, M} dimensions\n global_strides, // {N * sizeof(half), sizeof(half)}\n tile_dims, // {TILE_N, TILE_M}\n element_strides, // {1, 1}\n CU_TENSOR_MAP_INTERLEAVE_NONE,\n CU_TENSOR_MAP_SWIZZLE_128B, // 128-byte swizzle\n CU_TENSOR_MAP_L2_PROMOTION_NONE,\n CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE\n);\n```"}, "after": {"statement": "For a TMA-to-tcgen05 path, keep these layers consistent:\n\n1. The tensor map describes how TMA places the global-memory box into shared memory, including interleave and swizzle.\n2. The shared-memory allocation and base address satisfy the alignment and span constraints of that mapping.\n3. The tcgen05 shared-memory descriptor describes the same physical-to-logical layout, leading/stride dimensions, base offset, and swizzle mode expected by the MMA operand.\n\nPTX ISA 9.0 permits ordinary tcgen05 shared-memory descriptor modes with no swizzle and 32B, 64B, or 128B spans, plus a 128B/base-32B mode. In the descriptor's three-bit layout field, ordinary no-swizzle is `0`, 128B/base-32B is `1`, ordinary 128B is `2`, 64B is `4`, and 32B is `6`; values `3`, `5`, and `7` are invalid. Legality also depends on MMA kind, element type, major mode, shape, CTA group, and target.\n\nThe CUDA 13.0.97 Driver API exposes TMA modes including:\n\n| `CU_TENSOR_MAP_SWIZZLE_NONE` | No bank swizzle |\n| `CU_TENSOR_MAP_SWIZZLE_32B` | 16B chunks within a 32B span |\n| `CU_TENSOR_MAP_SWIZZLE_64B` | 16B chunks within a 64B span |\n| `CU_TENSOR_MAP_SWIZZLE_128B` | 16B chunks within a 128B span |\n| `CU_TENSOR_MAP_SWIZZLE_128B_ATOM_32B` | 32B chunks within a 128B span |\n| `CU_TENSOR_MAP_SWIZZLE_128B_ATOM_64B` | 64B chunks within a 128B span; support is operation/type-specific |\n\nThese names define mappings, not universal datatype or tile-size recommendations. The tensor-map encoder imposes mode-, interleave-, datatype-, alignment-, and box-size constraints; for example, ordinary 128B modes require the inner bounding-box byte span not to exceed 128 bytes. Check the exact archived API for the selected type and operation.\n\nFor `cuTensorMapEncodeTiled`, record and validate all inputs rather than copying only the swizzle enumerator:\n\n1. Use a correctly aligned `CUtensorMap` object and global base pointer.\n2. Supply rank-sized global dimensions, rank-minus-one byte strides (the fastest dimension is implicit), rank-sized box dimensions, and rank-sized element strides.\n3. Satisfy the global alignment, stride, box, interleave, datatype, and selected-swizzle constraints.\n4. Check the returned `CUresult`; do not launch with an output descriptor after encoding failed.\n5. Use a shared-memory base and tcgen05 descriptor that represent the same mapping as the tensor map.\n\nAn invalid encoder combination can fail explicitly. A successfully encoded tensor map paired with the wrong consumer layout may instead read the wrong logical elements, so a successful API return is not a correctness oracle."}, "reason": {"statement": "Replace incomplete code with an encoder validation checklist and pinned full example.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/techniques/swizzling.md", "before": {"statement": "The available swizzle modes and their use cases:\n\n| `SWIZZLE_NONE` | No remapping | Non-MMA data (flags, scales) |\n| `SWIZZLE_32B` | 32-byte groups | Narrow tiles, small data types |\n| `SWIZZLE_64B` | 64-byte groups | Medium tiles |\n| `SWIZZLE_128B` | 128-byte groups | Standard for BF16/FP16 MMA operands |"}, "after": {"statement": "For a TMA-to-tcgen05 path, keep these layers consistent:\n\n1. The tensor map describes how TMA places the global-memory box into shared memory, including interleave and swizzle.\n2. The shared-memory allocation and base address satisfy the alignment and span constraints of that mapping.\n3. The tcgen05 shared-memory descriptor describes the same physical-to-logical layout, leading/stride dimensions, base offset, and swizzle mode expected by the MMA operand.\n\nPTX ISA 9.0 permits ordinary tcgen05 shared-memory descriptor modes with no swizzle and 32B, 64B, or 128B spans, plus a 128B/base-32B mode. In the descriptor's three-bit layout field, ordinary no-swizzle is `0`, 128B/base-32B is `1`, ordinary 128B is `2`, 64B is `4`, and 32B is `6`; values `3`, `5`, and `7` are invalid. Legality also depends on MMA kind, element type, major mode, shape, CTA group, and target.\n\nThe CUDA 13.0.97 Driver API exposes TMA modes including:\n\n| `CU_TENSOR_MAP_SWIZZLE_NONE` | No bank swizzle |\n| `CU_TENSOR_MAP_SWIZZLE_32B` | 16B chunks within a 32B span |\n| `CU_TENSOR_MAP_SWIZZLE_64B` | 16B chunks within a 64B span |\n| `CU_TENSOR_MAP_SWIZZLE_128B` | 16B chunks within a 128B span |\n| `CU_TENSOR_MAP_SWIZZLE_128B_ATOM_32B` | 32B chunks within a 128B span |\n| `CU_TENSOR_MAP_SWIZZLE_128B_ATOM_64B` | 64B chunks within a 128B span; support is operation/type-specific |\n\nThese names define mappings, not universal datatype or tile-size recommendations. The tensor-map encoder imposes mode-, interleave-, datatype-, alignment-, and box-size constraints; for example, ordinary 128B modes require the inner bounding-box byte span not to exceed 128 bytes. Check the exact archived API for the selected type and operation."}, "reason": {"statement": "List exact mapping spans and defer legality to producer and consumer contracts.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/techniques/swizzling.md", "before": {"statement": "In CuTe/CUTLASS, swizzle is expressed as a layout composition:\n\n```cuda\n// CuTe swizzle layout for 128-byte swizzle pattern\n// Swizzle where:\n// B = number of bits in the base (non-swizzled) portion\n// M = number of bits in the mask\n// S = shift amount\n//\n// Swizzle<3, 4, 3> encodes the 128B swizzle:\n// 3 base bits (8-byte alignment)\n// 4 mask bits (16 rows)\n// 3 shift bits (8-column groups)\n\nusing SmemLayoutAtom = decltype(\n composition(\n Swizzle<3, 4, 3>{},\n Layout,\n Stride<_64, _1>>{}\n )\n);\n\n// Tile the atom across the full SMEM tile\nusing SmemLayoutA = decltype(\n tile_to_shape(SmemLayoutAtom{}, Shape, Int>{})\n);\n```"}, "after": {"statement": "CUTLASS 4.5.0 defines [`Swizzle`](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/swizzle.hpp):\n\n- `BBits` is the number of mask bits;\n- `MBase` is the number of least-significant address bits kept invariant; and\n- `SShift` is the distance between the two bit fields.\n\nFor `Swizzle<3,4,3>`, three address bits beginning above the four invariant low bits are XORed with the three-bit field shifted by three positions. Equivalently, address bits 7:9 affect bits 4:6. This is an address transformation, not a general `row & 7` rule: equivalence to row-based indexing depends on stride, byte units, base alignment, and layout composition.\n\nCUTLASS also distinguishes a position-independent composed swizzle layout from a position-dependent swizzle pointer, because hardware swizzling depends on the shared-memory pointer address. Reuse a pinned complete layout/descriptor construction or prove the composition and required base alignment; a `Swizzle` type alone is not a complete TMA or MMA contract."}, "reason": {"statement": "Define parameters exactly and cite a pinned full implementation rather than a generic atom.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/swizzle.hpp", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/pointer_swizzle.hpp"]}} +{"path": "wiki/techniques/swizzling.md", "before": {"statement": "Use `nvprof` or Nsight Compute to verify that swizzling eliminates conflicts:\n\n```python\n# Nsight Compute command to check shared memory bank conflicts\n# Look for \"Shared Memory Bank Conflicts\" metric\n# ncu --metrics l1tex__data_bank_conflicts_pipe_lsu_mem_shared_op_ld.sum \\\n# ./my_kernel\n\n# Expected results:\n# Without swizzle: bank_conflicts >> 0\n# With 128B swizzle: bank_conflicts == 0\n```"}, "after": {"statement": "For `cuTensorMapEncodeTiled`, record and validate all inputs rather than copying only the swizzle enumerator:\n\n1. Use a correctly aligned `CUtensorMap` object and global base pointer.\n2. Supply rank-sized global dimensions, rank-minus-one byte strides (the fastest dimension is implicit), rank-sized box dimensions, and rank-sized element strides.\n3. Satisfy the global alignment, stride, box, interleave, datatype, and selected-swizzle constraints.\n4. Check the returned `CUresult`; do not launch with an output descriptor after encoding failed.\n5. Use a shared-memory base and tcgen05 descriptor that represent the same mapping as the tensor map.\n\nAn invalid encoder combination can fail explicitly. A successfully encoded tensor map paired with the wrong consumer layout may instead read the wrong logical elements, so a successful API return is not a correctness oracle."}, "reason": {"statement": "Use ncu --query-metrics and compare correctness, wavefronts/conflicts, and timing between matched layouts.", "urls": ["https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html", "https://gau-nernst.github.io/tcgen05/", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/techniques/swizzling.md", "before": {"statement": "- **All Blackwell tensor core kernels**: 128-byte swizzling is not optional. Both TMA and tcgen05.mma require it for correct results and peak performance.\n- **Hopper wgmma kernels**: Same requirement applies; wgmma expects swizzled SMEM operands.\n- **Non-MMA shared memory access**: If multiple warps access the same SMEM tile in a column pattern (e.g., reduction), swizzling prevents serialization."}, "after": {"statement": "Shared memory has 32 banks, and successive 32-bit words map to successive banks. For one warp memory request, accesses to different words in the same bank require serialized wavefronts; same-word reads can broadcast and do not create that conflict. The result therefore depends on the exact byte address requested by every participating lane.\n\nA swizzle permutes address chunks so a target access pattern may distribute its requests over banks more evenly. It can reduce conflicts for that pattern, but it does not make every access to the tile conflict-free. A layout favorable to an MMA operand can still be unfavorable to a CUDA-core row, column, transpose, or epilogue access.\n\nFor `cuTensorMapEncodeTiled`, record and validate all inputs rather than copying only the swizzle enumerator:\n\n1. Use a correctly aligned `CUtensorMap` object and global base pointer.\n2. Supply rank-sized global dimensions, rank-minus-one byte strides (the fastest dimension is implicit), rank-sized box dimensions, and rank-sized element strides.\n3. Satisfy the global alignment, stride, box, interleave, datatype, and selected-swizzle constraints.\n4. Check the returned `CUresult`; do not launch with an output descriptor after encoding failed.\n5. Use a shared-memory base and tcgen05 descriptor that represent the same mapping as the tensor map.\n\nAn invalid encoder combination can fail explicitly. A successfully encoded tensor map paired with the wrong consumer layout may instead read the wrong logical elements, so a successful API return is not a correctness oracle."}, "reason": {"statement": "Replace architecture categories with a producer/consumer/access-pattern decision.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html"]}} +{"path": "wiki/techniques/swizzling.md", "before": {"statement": "- The swizzle mode in the TMA descriptor must exactly match the access pattern of the consumer. A mismatch produces silently incorrect results, not a runtime error.\n- Swizzled layouts make SMEM address computation non-trivial. Using CuTe's layout algebra avoids manual indexing errors.\n- For data types wider than 2 bytes (e.g., FP32 accumulators), the optimal swizzle mode may differ. TMEM accumulators avoid this issue since they use a separate address space."}, "after": {"statement": "For `cuTensorMapEncodeTiled`, record and validate all inputs rather than copying only the swizzle enumerator:\n\n1. Use a correctly aligned `CUtensorMap` object and global base pointer.\n2. Supply rank-sized global dimensions, rank-minus-one byte strides (the fastest dimension is implicit), rank-sized box dimensions, and rank-sized element strides.\n3. Satisfy the global alignment, stride, box, interleave, datatype, and selected-swizzle constraints.\n4. Check the returned `CUresult`; do not launch with an output descriptor after encoding failed.\n5. Use a shared-memory base and tcgen05 descriptor that represent the same mapping as the tensor map.\n\nAn invalid encoder combination can fail explicitly. A successfully encoded tensor map paired with the wrong consumer layout may instead read the wrong logical elements, so a successful API return is not a correctness oracle."}, "reason": {"statement": "State explicit encoder checks, layout equivalence and correctness/performance validation.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/swizzle.hpp", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "For memory-bound kernels (low arithmetic intensity), maximizing global memory throughput is critical. Three complementary techniques from the GPU Mode NVFP4 Hackathon achieve this: (1) wide vectorized loads (128-bit and 256-bit) to saturate memory bandwidth per thread, (2) differentiated L1 cache policies to keep reused data hot while bypassing the cache for streaming data, and (3) register budgeting via `-maxrregcount` to increase occupancy. These techniques reduced NVFP4 GEMV latency from 2000us to 22.4us (89x improvement)."}, "after": {"statement": "Amandeep Singh's attempts supply useful negative controls for the same task. Replacing two `uchar4` loads with one `uint2` load was reported 16–25% slower because extraction added instructions. Lowering `-maxrregcount` from 80 to 64 had no effect because natural allocation was already below the cap. The author later observed wider PTX forms and differentiated L1 policies in other solutions, but published no contestant code or controlled ablation for those observations.\n\nTogether, the reports justify testing vector width, decode organization, cache hints, and register limits. They do not establish that the widest load, a particular cache hint, or the lowest register cap is essential for GEMV, sub-byte arithmetic, or decode workloads."}, "reason": {"statement": "Retain the report as an author-reported multi-change case study without causal attribution.", "urls": ["https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "Standard 32-bit loads waste memory bus bandwidth. Wider loads amortize the instruction overhead and saturate the 8 TB/s HBM bandwidth of B200:\n\n```cuda\n// Vectorized load widths comparison for FP4 GEMV\n// Each thread loads more data per instruction\n\n// 32-bit load: 4 bytes per thread per instruction\nfloat val;\nasm volatile(\"ld.global.b32 %0, [%1];\" : \"=f\"(val) : \"l\"(ptr));\n\n// 64-bit load: 8 bytes per thread per instruction\nuint2 val64;\nasm volatile(\"ld.global.v2.u32 {%0,%1}, [%2];\"\n : \"=r\"(val64.x), \"=r\"(val64.y) : \"l\"(ptr));\n\n// 128-bit load: 16 bytes per thread per instruction (preferred)\nuint4 val128;\nasm volatile(\"ld.global.v4.u32 {%0,%1,%2,%3}, [%4];\"\n : \"=r\"(val128.x), \"=r\"(val128.y), \"=r\"(val128.z), \"=r\"(val128.w)\n : \"l\"(ptr));\n\n// 256-bit load: 32 bytes per thread per instruction\n// Requires v4.u64 (4 x 64-bit)\nuint64_t v256[4];\nasm volatile(\"ld.global.v4.u64 {%0,%1,%2,%3}, [%4];\"\n : \"=l\"(v256[0]), \"=l\"(v256[1]), \"=l\"(v256[2]), \"=l\"(v256[3])\n : \"l\"(ptr));\n```"}, "after": {"statement": "A PTX vector load moves several typed elements into several registers with one instruction. This can reduce the number of load instructions issued by a thread, but PTX only says that vector loads *may* improve memory performance. Source-level width alone does not prove fewer physical memory transactions, higher achieved bandwidth, or lower kernel latency.\n\nPTX ISA 9.0 permits the following global-memory forms on `sm_100`. The first accesses 16 bytes and the second accesses 32 bytes:\n\n```ptx\n.reg .b64 addr;\n.reg .u32 x<4>;\n.reg .u64 y<4>;\n\nld.global.v4.u32 {x0, x1, x2, x3}, [addr];\nld.global.v4.u64 {y0, y1, y2, y3}, [addr];\n```\n\nThe address must be naturally aligned to the total access size: 16 bytes for `v4.u32` and 32 bytes for `v4.u64`. A misaligned PTX address has undefined behavior; the ISA says it may have low address bits masked or fault. It does not specify a fallback to narrower loads. Guard tails or dispatch them to an access whose complete range and alignment are valid.\n\nThe 256-bit `v4.b64` family is an SM100-or-newer feature. A 32-byte load contains 64 values when the payload is densely packed E2M1 at two 4-bit values per byte. That arithmetic says nothing about whether the width is profitable: unpack cost, live registers, instruction selection, per-thread address patterns, and tail handling can outweigh a lower source-level load count.\n\nPTX distinguishes cache operators, eviction priorities, prefetch-size hints, and non-coherent read-only loads. Representative legal forms are:\n\n```ptx\nld.global.L1::no_allocate.v4.u32 {x0, x1, x2, x3}, [addr];\nld.global.L1::evict_last.v4.u32 {x0, x1, x2, x3}, [addr];\nld.global.L2::256B.b32 x0, [addr];\nld.global.nc.b32 x0, [addr];\n```\n\n| `L1::no_allocate` | L1 eviction-priority selection that may be applied | Does not guarantee an L1 bypass or a speedup for a streaming operand |\n| `L1::evict_last` | Requests the corresponding L1 eviction priority | Does not guarantee that a line remains resident |\n| `L2::256B` | Hints that additional data of the stated size be prefetched into L2 | Is not a 256-byte load or a promotion guarantee |\n| `ld.global.nc` | Loads through a non-coherent read-only cache | Has architecture- and parallelism-dependent latency/throughput; it is not a general coherence optimization |\n\nCache-policy operands and prefetch-size qualifiers are performance hints and do not change the program's memory-consistency behavior. A reuse argument can motivate `evict_last`, and a one-pass stream can motivate `no_allocate`, but only a matched comparison determines whether either helps the concrete working set and launch."}, "reason": {"statement": "Document legal widths, exact alignment, and the need to inspect/profile generated code.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld-global-nc"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "For the NVFP4 GEMV, 128-bit and 256-bit loads are essential because FP4 elements are only 0.5 bytes each. A 256-bit load fetches 64 FP4 values in a single instruction:\n\n```cuda\n// NVFP4 GEMV: each thread loads 64 FP4 values via 256-bit load\n// Then unpacks using PTX byte manipulation instead of bitwise ops\n__device__ void load_and_unpack_nvfp4_256bit(\n const uint8_t* fp4_data, // Packed FP4 data (2 values per byte)\n float* unpacked, // Output: 64 FP32 values\n int offset)\n{\n // 256-bit load: 32 bytes = 64 FP4 values\n uint64_t raw[4];\n const uint64_t* ptr = reinterpret_cast(fp4_data + offset);\n asm volatile(\n \"ld.global.v4.u64 {%0,%1,%2,%3}, [%4];\"\n : \"=l\"(raw[0]), \"=l\"(raw[1]), \"=l\"(raw[2]), \"=l\"(raw[3])\n : \"l\"(ptr)\n );\n\n // Unpack using PTX mov.b32 byte extraction\n // This avoids the bitwise shift-and-mask overhead\n for (int i = 0; i < 4; i++) {\n uint32_t lo = (uint32_t)(raw[i]);\n uint32_t hi = (uint32_t)(raw[i] >> 32);\n\n // PTX byte unpack: extract individual bytes from 32-bit word\n uint32_t b0, b1, b2, b3;\n asm volatile(\"mov.b32 {%0,%1,%2,%3}, %4;\"\n : \"=r\"(b0), \"=r\"(b1), \"=r\"(b2), \"=r\"(b3) : \"r\"(lo));\n\n // Each byte contains 2 FP4 values — decode low word (8 values)\n for (int b = 0; b < 4; b++) {\n uint32_t byte_val = (b == 0) ? b0 : (b == 1) ? b1 : (b == 2) ? b2 : b3;\n unpacked[i * 16 + b * 2] = decode_fp4(byte_val & 0xF);\n unpacked[i * 16 + b * 2 + 1] = decode_fp4((byte_val >> 4) & 0xF);\n }\n\n // Unpack high word (next 8 values from same 64-bit element)\n uint32_t hb0, hb1, hb2, hb3;\n asm volatile(\"mov.b32 {%0,%1,%2,%3}, %4;\"\n : \"=r\"(hb0), \"=r\"(hb1), \"=r\"(hb2), \"=r\"(hb3) : \"r\"(hi));\n for (int b = 0; b < 4; b++) {\n uint32_t byte_val = (b == 0) ? hb0 : (b == 1) ? hb1 : (b == 2) ? hb2 : hb3;\n unpacked[i * 16 + 8 + b * 2] = decode_fp4(byte_val & 0xF);\n unpacked[i * 16 + 8 + b * 2 + 1] = decode_fp4((byte_val >> 4) & 0xF);\n }\n }\n}\n```"}, "after": {"statement": "PTX distinguishes cache operators, eviction priorities, prefetch-size hints, and non-coherent read-only loads. Representative legal forms are:\n\n```ptx\nld.global.L1::no_allocate.v4.u32 {x0, x1, x2, x3}, [addr];\nld.global.L1::evict_last.v4.u32 {x0, x1, x2, x3}, [addr];\nld.global.L2::256B.b32 x0, [addr];\nld.global.nc.b32 x0, [addr];\n```\n\n| `L1::no_allocate` | L1 eviction-priority selection that may be applied | Does not guarantee an L1 bypass or a speedup for a streaming operand |\n| `L1::evict_last` | Requests the corresponding L1 eviction priority | Does not guarantee that a line remains resident |\n| `L2::256B` | Hints that additional data of the stated size be prefetched into L2 | Is not a 256-byte load or a promotion guarantee |\n| `ld.global.nc` | Loads through a non-coherent read-only cache | Has architecture- and parallelism-dependent latency/throughput; it is not a general coherence optimization |\n\nCache-policy operands and prefetch-size qualifiers are performance hints and do not change the program's memory-consistency behavior. A reuse argument can motivate `evict_last`, and a one-pass stream can motivate `no_allocate`, but only a matched comparison determines whether either helps the concrete working set and launch.\n\nYue Zhang reports the following CUDA progression for GPU Mode Problem 1. These are author-reported endpoints without raw repeated-trial data or released complete submission code:\n\n| Initial CUDA | Naive hand-written path | about 2000 µs |\n| CUDA optimization 1 | Coalescing, shared B, thread collaboration, warp reduction | about 443 µs |\n| CUDA optimization 2 | Remove shared B, per-thread tiles, `float4` loads, hardware intrinsics | about 39 µs |\n| CUDA optimization 3 | Vectorized PTX FP4 and scale decode | about 27 µs |\n| Parameter tuning | Threads per row and rows per block | about 26 µs |\n| ILP | Two tiles per loop iteration | about 22.9 µs |\n| Aggressive PTX fusion | Decode, scales, multiply, and accumulation in a larger PTX block | about 22.3 µs |\n\nThe submitted public-leaderboard score was 22.392 microseconds, the geometric mean over three benchmark shapes. The pinned task's theoretical model gives 8.622, 17.275, and 4.317 microseconds for those separate shapes; 8.622 microseconds is therefore not an aggregate “speed of light.” The 39-to-27 endpoints change the PTX load/decode path together and do not isolate cache policy, load width, or conversion choice."}, "reason": {"statement": "Replace the invented helper with exact PTX semantics and an empirical selection workflow.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld-global-nc", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv/task.yml"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "Different data streams have different reuse patterns. Applying the correct cache policy per stream avoids L1 pollution:\n\n```cuda\n// Cache policy selection based on data reuse pattern\n//\n// Matrix A (streamed, each row used once): bypass L1\n// Vector B (reused across all rows): keep in L1\n\n// L1::no_allocate -- data bypasses L1 cache (streaming access)\n// Used for matrix A which is read once per GEMV\nasm volatile(\n \"ld.global.L1::no_allocate.v4.u32 {%0,%1,%2,%3}, [%4];\"\n : \"=r\"(a.x), \"=r\"(a.y), \"=r\"(a.z), \"=r\"(a.w)\n : \"l\"(matrix_a_ptr)\n);\n\n// L1::evict_last -- data stays in L1 as long as possible\n// Used for vector B which is reused across all M rows\nasm volatile(\n \"ld.global.L1::evict_last.v4.u32 {%0,%1,%2,%3}, [%4];\"\n : \"=r\"(b.x), \"=r\"(b.y), \"=r\"(b.z), \"=r\"(b.w)\n : \"l\"(vector_b_ptr)\n);\n```"}, "after": {"statement": "For each candidate width and cache policy:\n\n1. Prove base and per-thread address alignment for every executed access. Use a separate scalar or narrower-vector path for tails; validate minimum, maximum, and awkward sizes.\n2. Hold the algorithm, mapping, decode, unrolling, launch shape, compiler, and inputs fixed while changing one load or cache choice. Compare identical correctness oracles before timing.\n3. Inspect generated PTX and SASS. Record actual load instructions, registers per thread, spill loads/stores, stack bytes, shared memory, and launch parameters. A source cast or inline-PTX block does not bypass compiler register allocation.\n4. Profile the matched variants. Check achieved bandwidth, requested versus transferred bytes, cache hit behavior, instruction issue/stalls, and active warps with metrics available on the installed Nsight Compute and GPU versions.\n5. Use warmups, synchronization, repeated trials, and the same statistic for every production shape. Keep the change only where the declared metric improves without a correctness or resource regression.\n\nRegister caps and launch bounds are a separate variable. A nominal cap may be inert when natural allocation is lower, or it may trade registers for spills and extra instructions. Follow the resource and occupancy workflow in [Register Budgeting](register-budgeting.md) rather than inferring residency from the cap value."}, "reason": {"statement": "State exact hint semantics and require a matched comparison.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#addresses-as-operands", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "The impact of cache policies from the GPU Mode Hackathon:\n\n```\nNo cache policy differentiation: 39 us\nA: L1::no_allocate, B: L1::evict_last: 27 us (1.44x faster)\n```"}, "after": {"statement": "Amandeep Singh's attempts supply useful negative controls for the same task. Replacing two `uchar4` loads with one `uint2` load was reported 16–25% slower because extraction added instructions. Lowering `-maxrregcount` from 80 to 64 had no effect because natural allocation was already below the cap. The author later observed wider PTX forms and differentiated L1 policies in other solutions, but published no contestant code or controlled ablation for those observations.\n\nTogether, the reports justify testing vector width, decode organization, cache hints, and register limits. They do not establish that the widest load, a particular cache hint, or the lowest register cap is essential for GEMV, sub-byte arithmetic, or decode workloads."}, "reason": {"statement": "Restore the complete stage descriptions and label the values author-reported.", "urls": ["https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "The full set of PTX load cache qualifiers:\n\n```ptx\n// PTX load qualifiers for cache control\n\n// Default: normal L1 and L2 caching\nld.global.b32 %r, [%addr];\n\n// L1 bypass: skip L1, still cached in L2\nld.global.L1::no_allocate.b32 %r, [%addr];\n\n// L1 keep: prioritize keeping in L1 (evict last)\nld.global.L1::evict_last.b32 %r, [%addr];\n\n// L2 promotion hint (256-byte sector)\n// Used by DeepEP for communication overlap\nld.global.nc.L1::no_allocate.L2::256B.b32 %r, [%addr];\n\n// Non-coherent read-only (nc): uses texture path\n// Avoids coherence traffic, useful for read-only data\nld.global.nc.b32 %r, [%addr];\n```"}, "after": {"statement": "For each candidate width and cache policy:\n\n1. Prove base and per-thread address alignment for every executed access. Use a separate scalar or narrower-vector path for tails; validate minimum, maximum, and awkward sizes.\n2. Hold the algorithm, mapping, decode, unrolling, launch shape, compiler, and inputs fixed while changing one load or cache choice. Compare identical correctness oracles before timing.\n3. Inspect generated PTX and SASS. Record actual load instructions, registers per thread, spill loads/stores, stack bytes, shared memory, and launch parameters. A source cast or inline-PTX block does not bypass compiler register allocation.\n4. Profile the matched variants. Check achieved bandwidth, requested versus transferred bytes, cache hit behavior, instruction issue/stalls, and active warps with metrics available on the installed Nsight Compute and GPU versions.\n5. Use warmups, synchronization, repeated trials, and the same statistic for every production shape. Keep the change only where the declared metric improves without a correctness or resource regression.\n\nRegister caps and launch bounds are a separate variable. A nominal cap may be inert when natural allocation is lower, or it may trade registers for spills and extra instructions. Follow the resource and occupancy workflow in [Register Budgeting](register-budgeting.md) rather than inferring residency from the cap value."}, "reason": {"statement": "Use the archived grammar and scope each semantic statement.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld-global-nc", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#addresses-as-operands", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "For memory-bound kernels, occupancy (number of concurrent warps) matters more than per-thread register count. Limiting registers per thread allows more warps to be resident:\n\n```cuda\n// Compile-time register budgeting\n// Lower register count -> higher occupancy -> better latency hiding\n\n// Problem 1 winner (rank 1): -maxrregcount=32\n// This allows 64 warps per SM (100% occupancy on SM100)\n// Sufficient for GEMV where each thread does minimal computation\n\n// Problem 1 rank 3: -maxrregcount=45\n// Allows 44 warps per SM (~69% occupancy)\n// More registers per thread for wider vectorized accumulation\n```\n\nThe tradeoff in a build system:\n\n```python\n# nvcc compilation with register budgeting\n# In CMakeLists.txt or build script:\n\n# For memory-bound GEMV kernel:\n# nvcc -maxrregcount=32 -arch=sm_100a gemv_kernel.cu -o gemv_kernel\n\n# For compute-bound GEMM kernel:\n# nvcc -arch=sm_100a gemm_kernel.cu -o gemm_kernel (no limit; needs ~128+ regs)\n\n# Per-kernel register limits in the same translation unit:\n# Use __launch_bounds__ to control per-kernel\n\n# Memory-bound: maximize occupancy\n__global__ void __launch_bounds__(256, 8) // 256 threads, min 8 blocks/SM\ngemv_kernel(/* ... */) { /* ... */ }\n\n# Compute-bound: maximize register availability\n__global__ void __launch_bounds__(512, 1) // 512 threads, min 1 block/SM\ngemm_kernel(/* ... */) { /* ... */ }\n```"}, "after": {"statement": "Yue Zhang reports the following CUDA progression for GPU Mode Problem 1. These are author-reported endpoints without raw repeated-trial data or released complete submission code:\n\n| Initial CUDA | Naive hand-written path | about 2000 µs |\n| CUDA optimization 1 | Coalescing, shared B, thread collaboration, warp reduction | about 443 µs |\n| CUDA optimization 2 | Remove shared B, per-thread tiles, `float4` loads, hardware intrinsics | about 39 µs |\n| CUDA optimization 3 | Vectorized PTX FP4 and scale decode | about 27 µs |\n| Parameter tuning | Threads per row and rows per block | about 26 µs |\n| ILP | Two tiles per loop iteration | about 22.9 µs |\n| Aggressive PTX fusion | Decode, scales, multiply, and accumulation in a larger PTX block | about 22.3 µs |\n\nThe submitted public-leaderboard score was 22.392 microseconds, the geometric mean over three benchmark shapes. The pinned task's theoretical model gives 8.622, 17.275, and 4.317 microseconds for those separate shapes; 8.622 microseconds is therefore not an aggregate “speed of light.” The 39-to-27 endpoints change the PTX load/decode path together and do not isolate cache policy, load width, or conversion choice."}, "reason": {"statement": "Route register-control details to the audited register-budgeting page and remove exact residency claims.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.0/cuda-c-programming-guide/index.html", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv/task.yml"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "Combining all three techniques for the GPU Mode Hackathon Problem 1:\n\n```cuda\n// Optimized NVFP4 Batched GEMV\n// A: [M, K] NVFP4, B: [1, K] NVFP4, C: [M, 1] FP16\n// Memory-bound: maximize bandwidth utilization\n\n// NVFP4 Batched GEMV: each row processed by THREADS_PER_ROW threads\n// Memory-bound: maximize bandwidth with wide loads and cache policies\n\n#define BLOCK_M 4 // Rows per thread block\n#define THREADS 256\n#define THREADS_PER_ROW (THREADS / BLOCK_M) // 64 threads per row\n\n__global__ void __launch_bounds__(THREADS, 4)\nnvfp4_gemv_optimized(\n const uint8_t* __restrict__ A, // [M, K/2] packed FP4\n const uint8_t* __restrict__ B, // [1, K/2] packed FP4\n const fp8_e4m3* __restrict__ sfa, // [M, K/16] block scales\n const fp8_e4m3* __restrict__ sfb, // [1, K/16] block scales\n half* __restrict__ C, // [M, 1] output\n float global_scale_a, float global_scale_b,\n int M, int K)\n{\n // Map threads to rows: 64 threads per row, 4 rows per block\n int local_row = threadIdx.x / THREADS_PER_ROW; // 0..3\n int thread_in_row = threadIdx.x % THREADS_PER_ROW; // 0..63\n int row = blockIdx.x * BLOCK_M + local_row;\n if (row >= M) return;\n\n float acc = 0.0f;\n\n // Each of the 64 threads handles a distinct K-chunk (no duplication)\n // 64 elements per load × 64 threads = 4096 K elements per iteration\n for (int k = thread_in_row * 64; k < K; k += THREADS_PER_ROW * 64) {\n // Load B (reused across rows): L1::evict_last, 256-bit\n uint64_t b_raw[4];\n asm volatile(\n \"ld.global.L1::evict_last.v4.u64 {%0,%1,%2,%3}, [%4];\"\n : \"=l\"(b_raw[0]), \"=l\"(b_raw[1]), \"=l\"(b_raw[2]), \"=l\"(b_raw[3])\n : \"l\"((const uint64_t*)(B + k / 2)));\n\n // Load A (streamed once): L1::no_allocate, 256-bit\n uint64_t a_raw[4];\n asm volatile(\n \"ld.global.L1::no_allocate.v4.u64 {%0,%1,%2,%3}, [%4];\"\n : \"=l\"(a_raw[0]), \"=l\"(a_raw[1]), \"=l\"(a_raw[2]), \"=l\"(a_raw[3])\n : \"l\"((const uint64_t*)(A + row * (K / 2) + k / 2)));\n\n // Unpack FP4, apply block scale, dot-product\n for (int i = 0; i < 64; i++) {\n float a_val = unpack_fp4(a_raw, i) * get_block_scale(sfa, row, k + i);\n float b_val = unpack_fp4(b_raw, i) * get_block_scale(sfb, 0, k + i);\n acc += a_val * b_val;\n }\n }\n\n // Two-phase reduction: first within each warp, then across the 2 warps per row\n // Phase 1: warp-level reduction (32 threads → 1 partial sum per warp)\n for (int offset = 16; offset > 0; offset >>= 1) {\n acc += __shfl_xor_sync(0xFFFFFFFF, acc, offset);\n }\n\n // Phase 2: shared memory reduction across the 2 warps assigned to this row\n __shared__ float smem_reduce[BLOCK_M * 2]; // 2 warp partials per row\n int warp_in_row = thread_in_row / 32; // 0 or 1\n int lane = thread_in_row % 32;\n if (lane == 0) {\n smem_reduce[local_row * 2 + warp_in_row] = acc;\n }\n __syncthreads();\n\n // Final sum and store (one thread per row)\n if (thread_in_row == 0) {\n float result = smem_reduce[local_row * 2] + smem_reduce[local_row * 2 + 1];\n C[row] = __float2half(result * global_scale_a * global_scale_b);\n }\n}\n```"}, "after": {"statement": null}, "reason": {"statement": "No direct published contestant implementation supports repairing this invented kernel in place.", "urls": ["https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv", "https://docs.nvidia.com/cuda/archive/13.0.0/cuda-c-programming-guide/index.html"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "| Baseline | Naive C++ | 2000 us | 1.0x |\n| Coalesced access | Memory layout fix | 443 us | 4.5x |\n| Hardware intrinsics | FP4 decode | 39 us | 51x |\n| PTX assembly | Vectorized loads + cache policy | 27 us | 74x |\n| ILP + register tuning | Unrolling + maxrregcount | 22.4 us | 89x |\n| Speed of light | | ~8.6 us | 233x |"}, "after": {"statement": "Amandeep Singh's attempts supply useful negative controls for the same task. Replacing two `uchar4` loads with one `uint2` load was reported 16–25% slower because extraction added instructions. Lowering `-maxrregcount` from 80 to 64 had no effect because natural allocation was already below the cap. The author later observed wider PTX forms and differentiated L1 policies in other solutions, but published no contestant code or controlled ablation for those observations.\n\nTogether, the reports justify testing vector width, decode organization, cache hints, and register limits. They do not establish that the widest load, a particular cache hint, or the lowest register cap is essential for GEMV, sub-byte arithmetic, or decode workloads."}, "reason": {"statement": "Use exact author-reported combined-stage descriptions and separate task-model rows.", "urls": ["https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv/task.yml", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "- **GEMV and memory-bound kernels**: Vectorized loads and cache policies are essential. These kernels are entirely limited by memory bandwidth.\n- **FP4/FP8 kernels**: Sub-byte data types make wide loads even more impactful since more elements fit in a single wide load.\n- **Decode-phase inference**: Single-token GEMV during autoregressive decoding is always memory-bound."}, "after": {"statement": "Yue Zhang reports the following CUDA progression for GPU Mode Problem 1. These are author-reported endpoints without raw repeated-trial data or released complete submission code:\n\n| Initial CUDA | Naive hand-written path | about 2000 µs |\n| CUDA optimization 1 | Coalescing, shared B, thread collaboration, warp reduction | about 443 µs |\n| CUDA optimization 2 | Remove shared B, per-thread tiles, `float4` loads, hardware intrinsics | about 39 µs |\n| CUDA optimization 3 | Vectorized PTX FP4 and scale decode | about 27 µs |\n| Parameter tuning | Threads per row and rows per block | about 26 µs |\n| ILP | Two tiles per loop iteration | about 22.9 µs |\n| Aggressive PTX fusion | Decode, scales, multiply, and accumulation in a larger PTX block | about 22.3 µs |\n\nThe submitted public-leaderboard score was 22.392 microseconds, the geometric mean over three benchmark shapes. The pinned task's theoretical model gives 8.622, 17.275, and 4.317 microseconds for those separate shapes; 8.622 microseconds is therefore not an aggregate “speed of light.” The 39-to-27 endpoints change the PTX load/decode path together and do not isolate cache policy, load width, or conversion choice."}, "reason": {"statement": "Replace category prescriptions with concrete selection criteria and measurement.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#roofline", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv/task.yml"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "- 256-bit loads require 32-byte aligned addresses. Misaligned access falls back to multiple narrower transactions.\n- `L1::no_allocate` is harmful for data that will be reused. Only apply it to truly streaming access patterns."}, "after": {"statement": "PTX distinguishes cache operators, eviction priorities, prefetch-size hints, and non-coherent read-only loads. Representative legal forms are:\n\n```ptx\nld.global.L1::no_allocate.v4.u32 {x0, x1, x2, x3}, [addr];\nld.global.L1::evict_last.v4.u32 {x0, x1, x2, x3}, [addr];\nld.global.L2::256B.b32 x0, [addr];\nld.global.nc.b32 x0, [addr];\n```\n\n| `L1::no_allocate` | L1 eviction-priority selection that may be applied | Does not guarantee an L1 bypass or a speedup for a streaming operand |\n| `L1::evict_last` | Requests the corresponding L1 eviction priority | Does not guarantee that a line remains resident |\n| `L2::256B` | Hints that additional data of the stated size be prefetched into L2 | Is not a 256-byte load or a promotion guarantee |\n| `ld.global.nc` | Loads through a non-coherent read-only cache | Has architecture- and parallelism-dependent latency/throughput; it is not a general coherence optimization |\n\nCache-policy operands and prefetch-size qualifiers are performance hints and do not change the program's memory-consistency behavior. A reuse argument can motivate `evict_last`, and a one-pass stream can motivate `no_allocate`, but only a matched comparison determines whether either helps the concrete working set and launch.\n\nFor each candidate width and cache policy:\n\n1. Prove base and per-thread address alignment for every executed access. Use a separate scalar or narrower-vector path for tails; validate minimum, maximum, and awkward sizes.\n2. Hold the algorithm, mapping, decode, unrolling, launch shape, compiler, and inputs fixed while changing one load or cache choice. Compare identical correctness oracles before timing.\n3. Inspect generated PTX and SASS. Record actual load instructions, registers per thread, spill loads/stores, stack bytes, shared memory, and launch parameters. A source cast or inline-PTX block does not bypass compiler register allocation.\n4. Profile the matched variants. Check achieved bandwidth, requested versus transferred bytes, cache hit behavior, instruction issue/stalls, and active warps with metrics available on the installed Nsight Compute and GPU versions.\n5. Use warmups, synchronization, repeated trials, and the same statistic for every production shape. Keep the change only where the declared metric improves without a correctness or resource regression.\n\nRegister caps and launch bounds are a separate variable. A nominal cap may be inert when natural allocation is lower, or it may trade registers for spills and extra instructions. Follow the resource and occupancy workflow in [Register Budgeting](register-budgeting.md) rather than inferring residency from the cap value."}, "reason": {"statement": "State the normative correctness condition and empirical status of hints.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#addresses-as-operands", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld-global-nc", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html"]}} +{"path": "wiki/techniques/vectorized-loads.md", "before": {"statement": "- `-maxrregcount` that is too low causes register spilling to local memory, which is slower than the occupancy gain. Profile with Nsight Compute to find the optimal point.\n- PTX inline assembly bypasses the compiler's register allocator. Excessive inline PTX can interfere with compiler optimizations for surrounding code."}, "after": {"statement": "Yue Zhang reports the following CUDA progression for GPU Mode Problem 1. These are author-reported endpoints without raw repeated-trial data or released complete submission code:\n\n| Initial CUDA | Naive hand-written path | about 2000 µs |\n| CUDA optimization 1 | Coalescing, shared B, thread collaboration, warp reduction | about 443 µs |\n| CUDA optimization 2 | Remove shared B, per-thread tiles, `float4` loads, hardware intrinsics | about 39 µs |\n| CUDA optimization 3 | Vectorized PTX FP4 and scale decode | about 27 µs |\n| Parameter tuning | Threads per row and rows per block | about 26 µs |\n| ILP | Two tiles per loop iteration | about 22.9 µs |\n| Aggressive PTX fusion | Decode, scales, multiply, and accumulation in a larger PTX block | about 22.3 µs |\n\nThe submitted public-leaderboard score was 22.392 microseconds, the geometric mean over three benchmark shapes. The pinned task's theoretical model gives 8.622, 17.275, and 4.317 microseconds for those separate shapes; 8.622 microseconds is therefore not an aggregate “speed of light.” The 39-to-27 endpoints change the PTX load/decode path together and do not isolate cache policy, load width, or conversion choice."}, "reason": {"statement": "Separate opaque instruction scheduling effects from register allocation and keep performance empirical.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/inline-ptx-assembly/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html", "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html", "https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv/task.yml"]}} +{"path": "wiki/techniques/cache-policy.md", "before": {"statement": "PTX cache qualifiers (`L1::no_allocate`, `L1::evict_last`, `L1::evict_first`) let kernels hint to hardware how to handle cache admission for specific loads. Critical for memory-bound kernels where the L1 working set matters more than the compute."}, "after": {"statement": "PTX global loads and stores can carry cache operators and eviction-priority qualifiers. Global loads can also carry L2 prefetch-size hints. These controls let a kernel express a preference for a particular access; they do not guarantee cache admission, residence, eviction time, hit rate, or performance.\n\n| `L1::no_allocate` | Selects an L1 eviction priority that may be applied | That the access bypasses L1 |\n| `L1::evict_first` | Requests first-eviction priority | Immediate eviction |\n| `L1::evict_last` | Requests last-eviction priority | Persistent residence |\n| `L2::64B`, `128B`, `256B` | Hints that additional data of that size be fetched into L2 | A wider memory instruction or a completed prefetch |\n| `L2::cache_hint` with a policy operand | Supplies a created L2 eviction policy | That the hint is respected or changes memory consistency |\n\nThe following are legal PTX 9.0 instruction fragments when their operands and addresses are declared with matching types. Each vector access shown is 16 bytes and therefore requires 16-byte natural alignment:\n\n```ptx\n.reg .b64 addr_a, addr_b, addr_c;\n.reg .u32 a<4>, b<4>, c<4>;\n\nld.global.L1::no_allocate.v4.u32 {a0, a1, a2, a3}, [addr_a];\nld.global.L1::evict_last.v4.u32 {b0, b1, b2, b3}, [addr_b];\nst.global.L1::evict_first.v4.u32 [addr_c], {c0, c1, c2, c3};\n```\n\nThe common “stream A, retain B” explanation is a hypothesis about reuse and interference, not the semantics of the code. Even with correct alignment, the hardware may apply the priorities differently than a literal bypass/keep model suggests."}, "reason": {"statement": "State the exact contract and empirical scope.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld"]}} +{"path": "wiki/techniques/cache-policy.md", "before": {"statement": "```asm\n; Matrix A (streamed once per row, never reused): bypass L1\n; Avoids polluting L1 with one-shot data\nld.global.L1::no_allocate.v4.u64 {a0,a1,a2,a3}, [addr_a];\n\n; Vector B (reused across BLOCK_M rows): keep in L1\nld.global.L1::evict_last.v4.u64 {b0,b1,b2,b3}, [addr_b];\n\n; Streaming output: evict immediately after write\nst.global.L1::evict_first.v2.u64 [addr_c], {c0, c1};\n```"}, "after": {"statement": "Start from the concrete access trace rather than a kernel label or tensor name:\n\n1. Identify which addresses each warp touches, the reuse distance for each line, the live working set, and competing traffic at the same launch shape.\n2. Establish a correct default-policy baseline. Hold mapping, vector width, decode, unrolling, register controls, compiler, inputs, and launch parameters constant.\n3. Change one qualifier at a time. Re-run the same correctness oracle, including sizes that exercise alignment and tail paths.\n4. Record generated instructions and resources, then profile cache hit behavior, requested/transferred bytes, stalls, achieved bandwidth, and active warps with metrics available on the installed tool and target.\n5. Benchmark every production shape with the same warmup, synchronization, repetitions, and statistic. Retain only scoped improvements; a policy may help one shape and regress another.\n\nAn input being larger than L2, a kernel being described as memory-bound, or a tensor being called streamed/reused does not by itself predict a useful qualifier. Concurrent blocks can reuse data, a nominally reused vector may exceed the effective working set, and a hint can alter other traffic. Those are measurements, not properties inferred from names."}, "reason": {"statement": "Keep legal fragments with accurate non-guarantee comments and alignment requirements.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"]}} +{"path": "wiki/techniques/cache-policy.md", "before": {"statement": "Rank 1 submission used **different qualifiers per K-dimension variant**:\n- K=16384 (large): aggressive `L1::no_allocate` on A (huge streaming matrix)\n- K=2048 (small): relaxed balance since B is smaller relative to cache"}, "after": {"statement": null}, "reason": {"statement": "No direct public source supports this contestant attribution.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv"]}} +{"path": "wiki/techniques/cache-policy.md", "before": {"statement": "- NVFP4 GEMV: 443μs → 27μs (16x improvement) came partly from cache policy + PTX byte unpacking\n- On memory-bound kernels, cache policy can be the dominant lever"}, "after": {"statement": "Yue Zhang reports approximately 39 microseconds for a stage combining removal of B shared-memory staging, per-thread tiles, `float4` loads, and hardware conversion, followed by approximately 27 microseconds for a vectorized PTX FP4/scale-decode stage. Those endpoints change the load and decode path together. They do not measure a cache-hint-only speedup or establish cache policy as the dominant lever for memory-bound kernels."}, "reason": {"statement": "Preserve only the complete combined-stage observation and causal limit.", "urls": ["https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"]}} +{"path": "wiki/techniques/cache-policy.md", "before": {"statement": "- Memory-bound kernels (profile with Nsight Compute first)\n- Tensor with clear \"streaming\" vs \"reused\" access patterns\n- Inputs > L2 cache size (B200: 126MB)\n- Separate M and N tile loading patterns in GEMM"}, "after": {"statement": "Amandeep Singh reports that three inspected B200 NVFP4 GEMV solutions used `L1::no_allocate` for A and `L1::evict_last` for B alongside raw PTX decode, wide loads, exact-K specialization, tighter register caps, and—in one solution—sharing B reads across M rows. The report does not release those contestant implementations or a cache-policy-only ablation, and it does not support the former page's rank-1 per-K policy attribution."}, "reason": {"statement": "Replace with a one-variable measurement procedure based on concrete address streams and reuse distances.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv"]}} +{"path": "wiki/techniques/chunk-parallelism.md", "before": {"statement": "Linear attention variants (GatedDeltaNet, RetNet, Mamba) have O(n) complexity but naive implementations are sequential. Chunk-based parallelism divides the sequence into chunks of size C, computes within each chunk in parallel (matmul-friendly), and propagates state between chunks sequentially."}, "after": {"statement": "Some linear recurrent models admit an algebraically equivalent chunkwise formulation. Work local to a chunk can then be expressed with parallel matrix operations, while the state passed across chunk boundaries preserves the recurrence's sequence order. The exact transform is model-specific: it must be derived from the recurrence, not replaced by a generic attention matrix and additive state update.\n\nA correct implementation separates at least these obligations:\n\n1. Compute the chunk-local quantities required by the model's exact recurrence.\n2. Resolve boundary states in sequence order, either with an associative scan supported by the formulation or with explicitly ordered stages or launches.\n3. Combine each chunk's local result with its incoming boundary state and emit outputs in the original token order.\n4. Validate outputs and final states against a token-by-token reference across variable sequence lengths, chunk tails, batches, heads, dtypes, and gate extremes.\n\nAn ordinary GPU grid does not imply increasing program-ID execution order or grid-wide synchronization. Programs for every chunk therefore cannot safely read and overwrite one shared state pointer in a single unordered launch. A staged algorithm must make the boundary-state dependency explicit."}, "reason": {"statement": "Scope chunking to concrete recurrence transformations and implementations.", "urls": ["https://arxiv.org/abs/2503.14376v3", "https://github.com/NVlabs/GatedDeltaNet/tree/b53d6d3a161267432a79c1c04af69fa52bddc921", "https://triton-lang.org/main/programming-guide/chapter-1/introduction.html"]}} +{"path": "wiki/techniques/chunk-parallelism.md", "before": {"statement": "```python\n@triton.jit\ndef chunk_parallel_linear_attn(Q, K, V, State, Output,\n chunk_size: tl.constexpr,\n d: tl.constexpr):\n # Grid: (num_chunks, num_heads, batch)\n chunk_id = tl.program_id(0)\n\n # Load chunk of Q, K, V\n q = tl.load(Q + chunk_id * chunk_size * d + offsets) # [C, d]\n k = tl.load(K + chunk_id * chunk_size * d + offsets)\n v = tl.load(V + chunk_id * chunk_size * d + offsets)\n\n # Intra-chunk: parallel O(C^2) attention-like compute\n scores = tl.dot(q, tl.trans(k))\n o_intra = tl.dot(scores, v)\n\n # Inter-chunk: sequential state propagation\n state = tl.load(State) # From previous chunk\n o_inter = tl.dot(q, state)\n\n # Combine and update state\n output = o_intra + o_inter\n state = update_state(state, k, v)\n\n tl.store(Output + offsets, output)\n tl.store(State, state)\n```"}, "after": {"statement": null}, "reason": {"statement": "The incomplete, racy pseudo-kernel cannot be repaired into a model-correct implementation without choosing a specific algorithm.", "urls": ["https://triton-lang.org/main/programming-guide/chapter-1/introduction.html", "https://github.com/NVlabs/GatedDeltaNet/tree/b53d6d3a161267432a79c1c04af69fa52bddc921"]}} +{"path": "wiki/techniques/chunk-parallelism.md", "before": {"statement": "- **Small chunks (C=32)**: low latency decode, fewer intermediate materializations\n- **Large chunks (C=256-512)**: better tensor core utilization, higher throughput for prefill\n- **TFLA (Tiled FLA)**: two-level tiling allows arbitrary chunk sizes via recursive tiling"}, "after": {"statement": "The pinned NVlabs GatedDeltaNet repository uses chunkwise Triton kernels for training and a WY representation of the gated delta rule. That implementation is direct evidence for GatedDeltaNet chunking, but it is not equivalent to a generic `scores = Q @ K.T; output = scores @ V` snippet and does not supply a universal chunk-size rule.\n\nTiled Flash Linear Attention (TFLA) starts from the chunkwise formulation of linear RNNs and adds another level of sequence parallelization within a chunk. The authors state that this permits arbitrarily large chunks, raises arithmetic intensity, and reduces intermediate-state materialization. The paper and pinned official code apply the method to mLSTM and report H100 results; they do not establish a GatedDeltaNet implementation, a Blackwell/TMEM implementation, or a recursive-tiling API."}, "reason": {"statement": "Retain TFLA's exact contribution and make chunk size an empirical backend/model choice.", "urls": ["https://arxiv.org/abs/2503.14376v3", "https://github.com/NVlabs/GatedDeltaNet/tree/b53d6d3a161267432a79c1c04af69fa52bddc921"]}} +{"path": "wiki/techniques/ping-pong-scheduling.md", "before": {"statement": "Ping-pong scheduling alternates two query tiles within a single CTA so the softmax warpgroup never stalls waiting for MMA. Introduced in FlashAttention-4 to exploit Blackwell's asymmetric hardware (2× tensor cores, same SFU count as Hopper)."}, "after": {"statement": "Ping-pong scheduling interleaves two output-tile states in one CTA. In the pinned FlashAttention-4 (FA4) SM100 forward implementation, `q_stage=2` makes the CTA cover two 128-row query tiles. One dedicated warp controls MMA, two four-warp groups perform softmax for the respective query stages, and a separate four-warp group performs correction work. While MMA advances one tile, the schedule tries to overlap softmax work for the other tile.\n\nThis is not merely ordinary double buffering of one producer-consumer stream. Each query stage owns a distinct output state, including its softmax and output TMEM regions, and the algorithm must preserve the dependencies among MMA accumulation, row statistics, rescaling/correction, and output consumption. “Ping-pong” describes this interleaving; it does not guarantee that either execution resource is stall-free."}, "reason": {"statement": "Describe the exact two-output-tile schedule and its bounded overlap objective.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py"]}} +{"path": "wiki/techniques/ping-pong-scheduling.md", "before": {"statement": "```cuda\n// Two 128-token query tiles per CTA, alternating through the mainloop\n// Warpgroup 0: softmax for tile A while MMA runs on tile B\n// Warpgroup 1: softmax for tile B while MMA runs on tile A\n\n__global__ void fa4_ping_pong_attn(...) {\n int wg = warp_group_id();\n\n // TMEM holds accumulators for BOTH tiles\n uint32_t tmem_A = tmem_alloc(256);\n uint32_t tmem_B = tmem_alloc(256);\n\n for (int k = 0; k < num_kv_tiles; k++) {\n if (wg == 0) {\n // Compute softmax for tile A (previous MMA output)\n softmax_normalize(tmem_A);\n // Issue MMA for tile B next\n tcgen05_mma(Q_B_smem, K_smem[k], tmem_B);\n } else {\n softmax_normalize(tmem_B);\n tcgen05_mma(Q_A_smem, K_smem[k], tmem_A);\n }\n mbarrier_arrive(&ping_pong_sync);\n mbarrier_wait(&ping_pong_sync);\n }\n}\n```"}, "after": {"statement": "The concrete reference is [`flash_fwd_sm100.py` at commit `a369df707e1980fb328abcc1733e3457ec10155f`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py). Its default two-stage layout has the following software roles:\n\n| 0–3 | softmax for query stage 0 |\n| 4–7 | softmax for query stage 1 |\n| 8–11 | correction |\n| 12 | MMA control |\n| 13 | epilogue |\n| 14 | load |\n| 15 | empty in this configuration |\n\nThese IDs are implementation choices, not SM100 architectural roles. The source changes assignments for other configurations, including `q_stage=1`.\n\nThe implementation performs one collective TMEM allocation sized for its required columns and gives the two query stages disjoint offsets within that allocation. It also constructs multiple producer/consumer pipelines for distinct handoffs. A single generic barrier after issuing `tcgen05.mma` is not an equivalent implementation: tcgen05 work is asynchronous, and completion, memory visibility, stage reuse, and TMEM lifetime must follow the corresponding pipeline and ISA contracts.\n\nBefore treating a two-tile schedule as valid, verify all of the following in the complete kernel:\n\n1. TMEM regions for simultaneous tile states are disjoint, allocated and deallocated collectively, and remain live until their final consumers finish.\n2. Every SMEM or TMEM stage has one unambiguous producer/consumer phase owner; a stage cannot be overwritten until all operations that read it have completed.\n3. Asynchronous MMA completion is connected to the barrier that guards accumulator consumption and operand-stage reuse. A CTA barrier or an unrelated mbarrier arrival is insufficient.\n4. Softmax groups obey the implementation's explicit synchronization. FA4 serializes their exponential critical sections rather than allowing both groups to contend there simultaneously.\n5. Correction and epilogue work wait for the row statistics and accumulators they consume, including the proper proxy and execution-order fences.\n6. Boundary query rows, final key tiles, causal/window masks, and the pipeline tail preserve the same mathematical result as the reference attention computation."}, "reason": {"statement": "Replace executable-looking unsafe code with a source-pinned structural contract and verification checklist.", "urls": ["https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions"]}} +{"path": "wiki/techniques/ping-pong-scheduling.md", "before": {"statement": "- Single-tile schedule would leave SFU idle while MMA runs, and vice versa\n- Ping-pong keeps both units 100% busy"}, "after": {"statement": "Ping-pong scheduling interleaves two output-tile states in one CTA. In the pinned FlashAttention-4 (FA4) SM100 forward implementation, `q_stage=2` makes the CTA cover two 128-row query tiles. One dedicated warp controls MMA, two four-warp groups perform softmax for the respective query stages, and a separate four-warp group performs correction work. While MMA advances one tile, the schedule tries to overlap softmax work for the other tile.\n\nThis is not merely ordinary double buffering of one producer-consumer stream. Each query stage owns a distinct output state, including its softmax and output TMEM regions, and the algorithm must preserve the dependencies among MMA accumulation, row statistics, rescaling/correction, and output consumption. “Ping-pong” describes this interleaving; it does not guarantee that either execution resource is stall-free.\n\nThe paper reports up to 1613 TFLOP/s and 71% utilization for complete FA4 forward kernels. The accompanying author blog reports up to 1605 TFLOP/s and 71%. Those endpoints include partial software exponentials, conditional rescaling, TMEM partitioning, register allocation choices, and the rest of the pipeline. Neither source supplies a ping-pong-only ablation, and neither establishes 100% tensor-core or exponential-unit utilization."}, "reason": {"statement": "Retain the overlap motivation without universal idle-state or utilization assertions.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/techniques/ping-pong-scheduling.md", "before": {"statement": "- FA4 achieves 1605 TFLOPS BF16 (71% utilization) with this pattern"}, "after": {"statement": "The paper reports up to 1613 TFLOP/s and 71% utilization for complete FA4 forward kernels. The accompanying author blog reports up to 1605 TFLOP/s and 71%. Those endpoints include partial software exponentials, conditional rescaling, TMEM partitioning, register allocation choices, and the rest of the pipeline. Neither source supplies a ping-pong-only ablation, and neither establishes 100% tensor-core or exponential-unit utilization."}, "reason": {"statement": "Report the result only at full-system scope and explicitly deny isolated attribution.", "urls": ["https://tridao.me/blog/2026/flash4/", "https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/techniques/ping-pong-scheduling.md", "before": {"statement": "- Compute-bound attention kernels on Blackwell\n- Kernels where softmax/epilogue is SFU-heavy\n- Not useful on Hopper (balance is different)"}, "after": {"statement": "Use the pinned SM100 kernel as the concrete reference when two independent query/output states can coexist within the register, shared-memory, and TMEM budgets. Compare `q_stage=2` with the source-supported `q_stage=1` configuration while holding the remaining build, input, tile, and launch choices fixed. Measure end-to-end time, MMA and exponential-pipeline activity, barrier stalls, per-role idle time, register spills, and occupancy across representative shapes.\n\nDo not select the technique from a generic “compute-bound” or “SFU-heavy” label alone. The FA4 paper says its schedule is similar to FlashAttention-3's Hopper ping-pong schedule, so the scheduling idea is not intrinsically Blackwell-only; this page's pinned implementation and hardware figures are specifically SM100. Keep the two-stage form only when the controlled comparison shows a relevant improvement and correctness tests cover boundaries and pipeline tails."}, "reason": {"statement": "Scope concrete code to SM100 and recommend controlled measurement instead of workload-label prescriptions.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py"]}} +{"path": "wiki/techniques/ping-pong-scheduling.md", "before": {"statement": "Verbatim upstream code lives in [`artifacts/kernels/ping-pong-scheduling/full/`](../../artifacts/kernels/ping-pong-scheduling/full/); labeled derived variants (each with the required `// provenance: derived from ...; not upstream code` header) live in [`artifacts/kernels/ping-pong-scheduling/variants/`](../../artifacts/kernels/ping-pong-scheduling/variants/). Every file's SHA-256 and upstream-pinning metadata is in `PROVENANCE.yaml` inside each bundle.\n\nQuery via:\n\n```bash\npython3 scripts/get_page.py technique-ping-pong-scheduling --include-code\n```"}, "after": {"statement": null}, "reason": {"statement": "Remove the misleading page linkage while preserving the separately provenance-labeled files for repository integrity.", "urls": []}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "Nsight Compute shows TMA or tcgen05 units idle despite nominally compute-bound workload. Tensor core utilization drops during specific phases of the kernel. Warp-level profiling reveals threads blocked on `mbarrier.try_wait` more than expected."}, "after": {"statement": "A pipeline stall is lost issue opportunity caused by a producer-consumer dependency on the critical path. Low TMA or tensor-core activity, a warp sampled at a barrier wait, or a phase-local utilization drop is only a lead. Expected dependency waits, memory latency, execution-pipeline contention, load imbalance, prologue/tail work, and synchronization defects can produce similar observations.\n\nNsight Compute's Warp State Statistics describes why sampled warps could not issue, while Scheduler Statistics shows whether schedulers had eligible warps and issued instructions. NVIDIA cautions that stalls are not necessarily performance-limiting and should be prioritized when schedulers fail to issue. Metric availability and names vary by tool and chip, so query the installed profiler and use its shipped sections rather than assuming a Blackwell metric name. PM sampling can add a timeline on supported systems, but warp sampling itself has no time resolution."}, "reason": {"statement": "Require scheduler issue evidence, source correlation, and a controlled causal perturbation.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "1. **Insufficient pipeline depth**: 2 stages cannot hide a 3-cycle latency chain"}, "after": {"statement": "1. Establish a synchronized end-to-end timing regression on fixed inputs and confirm outputs against a reference. Record GPU, clocks, toolkit, build flags, kernel name, launch shape, and resource use.\n2. Collect Speed-of-Light, Scheduler Statistics, Warp State Statistics, and source/SASS correlation with the sections available in the installed Nsight Compute. Account for replay and sampling effects.\n3. Map the dominant not-issued locations to concrete edges: TMA-full wait, MMA-completion wait, output-buffer reuse, CTA barrier, queue starvation, or pipeline prologue/tail.\n4. State a prediction. For example: if TMA readiness is the critical edge, a legal extra operand stage should reduce that wait and runtime; if only the tail is exposed, the steady-state wait distribution should remain largely unchanged.\n5. Change one variable and repeat identical correctness, warmup, timing, and profiler collection. Reject a cause when its predicted counter and time movement do not occur.\n\n| Vary legal SMEM stage count | Producer cannot stay far enough ahead of MMA | Same tile/math/roles; record SMEM, occupancy, short-loop behavior, and tail |\n| Separate long-lived warp roles | Role handoff or control work is on the issue path | Same stages and tile; record registers, active warps, and per-role idle/backpressure |\n| Add a second TMEM output region | Epilogue holds the only accumulator region | Prove disjoint lifetime; record TMEM columns and epilogue/MMA completion waits |\n| Interleave two query/output tiles | Softmax/correction and MMA have independent ready work | Prove separate state and dependencies; compare one versus two query stages |\n\nNone is a universal cure. More stages consume storage and can reduce occupancy; specialization adds warps and synchronization; TMEM buffering consumes columns; multi-tile schedules increase live state. A memory-bound roofline classification also does not prove pipelining is useless: test it only when the proposed change has a specific issue-gap, latency, or transaction-efficiency prediction."}, "reason": {"statement": "Make depth a resource-checked controlled variable.", "urls": ["https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://github.com/gau-nernst/learn-cuda/tree/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100", "https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "3. **Missing `tcgen05.fence::after_thread_sync`**: MMA reads SMEM before TMA transfer fully visible"}, "after": {"statement": "Do this before tuning around an mbarrier wait:\n\n1. Identify the exact barrier object, owner, initialized arrival count, initial phase, and storage stage for the wait.\n2. For a TMA global-to-shared load, account for the producer's software arrival and expected transaction bytes. `mbarrier.arrive.expect_tx` performs an arrival and adds transaction bytes; the TMA `.mbarrier::complete_tx::bytes` operation decrements transaction bytes, not a second arrival.\n3. Wait for the matching phase of that same object. Phase parity changes when that barrier completes a phase and is reused; “flip after every wait” is not a valid global rule when a thread waits on multiple objects or phases.\n4. A successful acquire wait supplies the documented visibility for associated prior `cp.async.bulk` work before the consumer reads SMEM.\n5. Before reusing SMEM operands read by asynchronous MMA, attach completion of the relevant tcgen05 work with `tcgen05.commit` and observe its mbarrier. Issue is not completion.\n6. When asynchronous tcgen05 operations cross a thread handoff, place `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` around the applicable execution-ordering operation. The after fence is not a generic replacement for the TMA acquire wait.\n7. Verify prologue, steady-state wraparound, short loops, and the producer/consumer tails. A correct steady-state loop can still hang or reuse live storage at a boundary.\n\nAn extra software arrival is erroneous only relative to the barrier's initialized and phase-specific accounting. Diagnose pending arrivals and transaction bytes separately instead of assuming that TMA hardware performs another arrival."}, "reason": {"statement": "Separate TMA completion/visibility from cross-thread tcgen05 ordering.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-try-wait", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier"]}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "4. **Single-tile scheduling**: All warps serialized on one tile's softmax/epilogue"}, "after": {"statement": "1. Establish a synchronized end-to-end timing regression on fixed inputs and confirm outputs against a reference. Record GPU, clocks, toolkit, build flags, kernel name, launch shape, and resource use.\n2. Collect Speed-of-Light, Scheduler Statistics, Warp State Statistics, and source/SASS correlation with the sections available in the installed Nsight Compute. Account for replay and sampling effects.\n3. Map the dominant not-issued locations to concrete edges: TMA-full wait, MMA-completion wait, output-buffer reuse, CTA barrier, queue starvation, or pipeline prologue/tail.\n4. State a prediction. For example: if TMA readiness is the critical edge, a legal extra operand stage should reduce that wait and runtime; if only the tail is exposed, the steady-state wait distribution should remain largely unchanged.\n5. Change one variable and repeat identical correctness, warmup, timing, and profiler collection. Reject a cause when its predicted counter and time movement do not occur.\n\n| Vary legal SMEM stage count | Producer cannot stay far enough ahead of MMA | Same tile/math/roles; record SMEM, occupancy, short-loop behavior, and tail |\n| Separate long-lived warp roles | Role handoff or control work is on the issue path | Same stages and tile; record registers, active warps, and per-role idle/backpressure |\n| Add a second TMEM output region | Epilogue holds the only accumulator region | Prove disjoint lifetime; record TMEM columns and epilogue/MMA completion waits |\n| Interleave two query/output tiles | Softmax/correction and MMA have independent ready work | Prove separate state and dependencies; compare one versus two query stages |\n\nNone is a universal cure. More stages consume storage and can reduce occupancy; specialization adds warps and synchronization; TMEM buffering consumes columns; multi-tile schedules increase live state. A memory-bound roofline classification also does not prove pipelining is useless: test it only when the proposed change has a specific issue-gap, latency, or transaction-efficiency prediction."}, "reason": {"statement": "Present multi-tile scheduling as a hypothesis only when independent state and work exist.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://github.com/gau-nernst/learn-cuda/tree/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100"]}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "5. **Producer over-arrives**: Manual `mbarrier_arrive` after async TMA — hardware + manual both arrive, next stage gets stale release"}, "after": {"statement": "Do this before tuning around an mbarrier wait:\n\n1. Identify the exact barrier object, owner, initialized arrival count, initial phase, and storage stage for the wait.\n2. For a TMA global-to-shared load, account for the producer's software arrival and expected transaction bytes. `mbarrier.arrive.expect_tx` performs an arrival and adds transaction bytes; the TMA `.mbarrier::complete_tx::bytes` operation decrements transaction bytes, not a second arrival.\n3. Wait for the matching phase of that same object. Phase parity changes when that barrier completes a phase and is reused; “flip after every wait” is not a valid global rule when a thread waits on multiple objects or phases.\n4. A successful acquire wait supplies the documented visibility for associated prior `cp.async.bulk` work before the consumer reads SMEM.\n5. Before reusing SMEM operands read by asynchronous MMA, attach completion of the relevant tcgen05 work with `tcgen05.commit` and observe its mbarrier. Issue is not completion.\n6. When asynchronous tcgen05 operations cross a thread handoff, place `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` around the applicable execution-ordering operation. The after fence is not a generic replacement for the TMA acquire wait.\n7. Verify prologue, steady-state wraparound, short loops, and the producer/consumer tails. A correct steady-state loop can still hang or reuse live storage at a boundary.\n\nAn extra software arrival is erroneous only relative to the barrier's initialized and phase-specific accounting. Diagnose pending arrivals and transaction bytes separately instead of assuming that TMA hardware performs another arrival."}, "reason": {"statement": "Teach the two independent counters exactly.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-arrive", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence"]}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "| [Pipeline stages](../techniques/pipeline-stages.md) | Increase NUM_STAGES (3-5 typical on Blackwell) |\n| [Warp specialization](../techniques/warp-specialization.md) | Dedicated warps for TMA/MMA/epilogue eliminate role-switching stalls |"}, "after": {"statement": "1. Establish a synchronized end-to-end timing regression on fixed inputs and confirm outputs against a reference. Record GPU, clocks, toolkit, build flags, kernel name, launch shape, and resource use.\n2. Collect Speed-of-Light, Scheduler Statistics, Warp State Statistics, and source/SASS correlation with the sections available in the installed Nsight Compute. Account for replay and sampling effects.\n3. Map the dominant not-issued locations to concrete edges: TMA-full wait, MMA-completion wait, output-buffer reuse, CTA barrier, queue starvation, or pipeline prologue/tail.\n4. State a prediction. For example: if TMA readiness is the critical edge, a legal extra operand stage should reduce that wait and runtime; if only the tail is exposed, the steady-state wait distribution should remain largely unchanged.\n5. Change one variable and repeat identical correctness, warmup, timing, and profiler collection. Reject a cause when its predicted counter and time movement do not occur.\n\n| Vary legal SMEM stage count | Producer cannot stay far enough ahead of MMA | Same tile/math/roles; record SMEM, occupancy, short-loop behavior, and tail |\n| Separate long-lived warp roles | Role handoff or control work is on the issue path | Same stages and tile; record registers, active warps, and per-role idle/backpressure |\n| Add a second TMEM output region | Epilogue holds the only accumulator region | Prove disjoint lifetime; record TMEM columns and epilogue/MMA completion waits |\n| Interleave two query/output tiles | Softmax/correction and MMA have independent ready work | Prove separate state and dependencies; compare one versus two query stages |\n\nNone is a universal cure. More stages consume storage and can reduce occupancy; specialization adds warps and synchronization; TMEM buffering consumes columns; multi-tile schedules increase live state. A memory-bound roofline classification also does not prove pipelining is useless: test it only when the proposed change has a specific issue-gap, latency, or transaction-efficiency prediction."}, "reason": {"statement": "Turn both into measured candidate changes with explicit costs.", "urls": ["https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu", "https://gau-nernst.github.io/tcgen05/", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://github.com/gau-nernst/learn-cuda/tree/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100", "https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "```\n1. Profile with Nsight Compute, check tensor core active cycles\n2. Inspect mbarrier wait stalls in warp state breakdown\n3. Verify phase tracking increments correctly (each wait should flip parity)\n4. Check that TMA uses arrive_expect_tx + mbarrier target (not manual arrive)\n5. Ensure tcgen05.fence::after_thread_sync between TMA wait and MMA issue\n6. Measure pipeline depth: can you add more NUM_STAGES?\n```"}, "after": {"statement": "A pipeline stall is lost issue opportunity caused by a producer-consumer dependency on the critical path. Low TMA or tensor-core activity, a warp sampled at a barrier wait, or a phase-local utilization drop is only a lead. Expected dependency waits, memory latency, execution-pipeline contention, load imbalance, prologue/tail work, and synchronization defects can produce similar observations.\n\nNsight Compute's Warp State Statistics describes why sampled warps could not issue, while Scheduler Statistics shows whether schedulers had eligible warps and issued instructions. NVIDIA cautions that stalls are not necessarily performance-limiting and should be prioritized when schedulers fail to issue. Metric availability and names vary by tool and chip, so query the installed profiler and use its shipped sections rather than assuming a Blackwell metric name. PM sampling can add a timeline on supported systems, but warp sampling itself has no time resolution.\n\nDo this before tuning around an mbarrier wait:\n\n1. Identify the exact barrier object, owner, initialized arrival count, initial phase, and storage stage for the wait.\n2. For a TMA global-to-shared load, account for the producer's software arrival and expected transaction bytes. `mbarrier.arrive.expect_tx` performs an arrival and adds transaction bytes; the TMA `.mbarrier::complete_tx::bytes` operation decrements transaction bytes, not a second arrival.\n3. Wait for the matching phase of that same object. Phase parity changes when that barrier completes a phase and is reused; “flip after every wait” is not a valid global rule when a thread waits on multiple objects or phases.\n4. A successful acquire wait supplies the documented visibility for associated prior `cp.async.bulk` work before the consumer reads SMEM.\n5. Before reusing SMEM operands read by asynchronous MMA, attach completion of the relevant tcgen05 work with `tcgen05.commit` and observe its mbarrier. Issue is not completion.\n6. When asynchronous tcgen05 operations cross a thread handoff, place `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` around the applicable execution-ordering operation. The after fence is not a generic replacement for the TMA acquire wait.\n7. Verify prologue, steady-state wraparound, short loops, and the producer/consumer tails. A correct steady-state loop can still hang or reuse live storage at a boundary.\n\nAn extra software arrival is erroneous only relative to the barrier's initialized and phase-specific accounting. Diagnose pending arrivals and transaction bytes separately instead of assuming that TMA hardware performs another arrival.\n\n1. Establish a synchronized end-to-end timing regression on fixed inputs and confirm outputs against a reference. Record GPU, clocks, toolkit, build flags, kernel name, launch shape, and resource use.\n2. Collect Speed-of-Light, Scheduler Statistics, Warp State Statistics, and source/SASS correlation with the sections available in the installed Nsight Compute. Account for replay and sampling effects.\n3. Map the dominant not-issued locations to concrete edges: TMA-full wait, MMA-completion wait, output-buffer reuse, CTA barrier, queue starvation, or pipeline prologue/tail.\n4. State a prediction. For example: if TMA readiness is the critical edge, a legal extra operand stage should reduce that wait and runtime; if only the tail is exposed, the steady-state wait distribution should remain largely unchanged.\n5. Change one variable and repeat identical correctness, warmup, timing, and profiler collection. Reject a cause when its predicted counter and time movement do not occur.\n\n| Vary legal SMEM stage count | Producer cannot stay far enough ahead of MMA | Same tile/math/roles; record SMEM, occupancy, short-loop behavior, and tail |\n| Separate long-lived warp roles | Role handoff or control work is on the issue path | Same stages and tile; record registers, active warps, and per-role idle/backpressure |\n| Add a second TMEM output region | Epilogue holds the only accumulator region | Prove disjoint lifetime; record TMEM columns and epilogue/MMA completion waits |\n| Interleave two query/output tiles | Softmax/correction and MMA have independent ready work | Prove separate state and dependencies; compare one versus two query stages |\n\nNone is a universal cure. More stages consume storage and can reduce occupancy; specialization adds warps and synchronization; TMEM buffering consumes columns; multi-tile schedules increase live state. A memory-bound roofline classification also does not prove pipelining is useless: test it only when the proposed change has a specific issue-gap, latency, or transaction-efficiency prediction."}, "reason": {"statement": "Replace with separate profiling, barrier-accounting, and controlled-experiment stages.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier", "https://github.com/gau-nernst/learn-cuda/tree/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100", "https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "- 1-stage: 62% of cuBLAS (TMA blocks MMA)\n- 3-stage pipelined: 70% (hide most TMA latency)\n- Warp specialized: 80% (no role switching)\n- Add 2-SM MMA: 86% (larger tile, more reuse)\n- Persistent + CLC: 98% (eliminate tail effect)"}, "after": {"statement": "Gau Nernst reports the following for one `M=N=K=4096` BF16 GEMM on a Modal B200 using PyTorch 2.9.1 and CUDA 13. Percentages below are computed from the reported 1506.74-TFLOP/s cuBLAS value.\n\n| v1a | basic tcgen05 + 2D 16-byte TMA | 254.62 | 16.90% |\n| v2b | 3D 128-byte TMA | 695.43 | 46.15% |\n| v3 | pipelining | 939.61 | 62.36% |\n| v4 | warp specialization | 1208.83 | 80.23% |\n| v5 | 2-SM MMA | 1302.29 | 86.43% |\n| v6 | persistent kernel with static scheduling | 1475.93 | 97.96% |\n\nThe pinned v3 source instantiates two stages, not three. Each row is a cumulative source version rather than an isolated microbenchmark of the named mechanism. The final version uses static scheduling; the author explicitly says Cluster Launch Control was not added. The result is evidence that these changes helped that implementation and shape, not a Blackwell progression template."}, "reason": {"statement": "Report the exact source table and combined-version scope.", "urls": ["https://gau-nernst.github.io/tcgen05/", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu"]}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "- Too many stages consume SMEM; exceeds 228KB budget"}, "after": {"statement": "1. Establish a synchronized end-to-end timing regression on fixed inputs and confirm outputs against a reference. Record GPU, clocks, toolkit, build flags, kernel name, launch shape, and resource use.\n2. Collect Speed-of-Light, Scheduler Statistics, Warp State Statistics, and source/SASS correlation with the sections available in the installed Nsight Compute. Account for replay and sampling effects.\n3. Map the dominant not-issued locations to concrete edges: TMA-full wait, MMA-completion wait, output-buffer reuse, CTA barrier, queue starvation, or pipeline prologue/tail.\n4. State a prediction. For example: if TMA readiness is the critical edge, a legal extra operand stage should reduce that wait and runtime; if only the tail is exposed, the steady-state wait distribution should remain largely unchanged.\n5. Change one variable and repeat identical correctness, warmup, timing, and profiler collection. Reject a cause when its predicted counter and time movement do not occur.\n\n| Vary legal SMEM stage count | Producer cannot stay far enough ahead of MMA | Same tile/math/roles; record SMEM, occupancy, short-loop behavior, and tail |\n| Separate long-lived warp roles | Role handoff or control work is on the issue path | Same stages and tile; record registers, active warps, and per-role idle/backpressure |\n| Add a second TMEM output region | Epilogue holds the only accumulator region | Prove disjoint lifetime; record TMEM columns and epilogue/MMA completion waits |\n| Interleave two query/output tiles | Softmax/correction and MMA have independent ready work | Prove separate state and dependencies; compare one versus two query stages |\n\nNone is a universal cure. More stages consume storage and can reduce occupancy; specialization adds warps and synchronization; TMEM buffering consumes columns; multi-tile schedules increase live state. A memory-bound roofline classification also does not prove pipelining is useless: test it only when the proposed change has a specific issue-gap, latency, or transaction-efficiency prediction."}, "reason": {"statement": "Require explicit storage arithmetic and compiled resource checks.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://github.com/gau-nernst/learn-cuda/tree/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100", "https://arxiv.org/html/2603.05451v1"]}} +{"path": "wiki/patterns/pipeline-stalls.md", "before": {"statement": "- Profile first — pipeline is a waste of effort on memory-bound kernels"}, "after": {"statement": "- [Nsight Compute 2025.3 Profiling Guide](https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html)\n- [PTX ISA 9.0 mbarrier waits and visibility](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-try-wait)\n- [PTX ISA 9.0 tcgen05 execution ordering](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-special-sync-operations-fence)\n- [Pinned tutorial v3 source](https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu)\n- [Tutorial progression](https://gau-nernst.github.io/tcgen05/)"}, "reason": {"statement": "Use causal measurements rather than excluding an entire category.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html#roofline", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu", "https://gau-nernst.github.io/tcgen05/"]}} +{"path": "wiki/patterns/compute-bound.md", "before": {"statement": "Tensor core utilization below 70%. Memory bandwidth is not saturated. Kernel is compute-bound but not reaching peak FLOPS."}, "after": {"statement": "“Below peak FLOPS” is not itself a bottleneck diagnosis. Select the peak for the executed datatype, instruction kind, sparsity/scaling mode, clocks, and number of participating SMs. Then use arithmetic intensity and achieved compute/memory ceilings to decide whether the measured kernel lies on the compute side of the relevant roofline. Unsaturated DRAM bandwidth and tensor-core utilization below an arbitrary threshold such as 70% do not prove compute boundedness.\n\nAlso distinguish whole-kernel throughput from tensor-core active time. A correct kernel can have efficient MMA intervals yet spend material time in TMA readiness, CUDA-core transforms, reductions, synchronization, epilogue work, or the grid tail. Scheduler under-issue plus source/SASS correlation identifies where issue opportunity is lost; a high stall sample count alone does not establish the cause."}, "reason": {"statement": "Replace the threshold with roofline and scheduler evidence.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html#roofline", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/compute-bound.md", "before": {"statement": "3. **Single-SM MMA tiles too small**: Not fully utilizing available compute"}, "after": {"statement": "Enumerate stage counts that compile and fit the complete shared-storage allocation. More stages can overlap TMA production with MMA consumption, but they also consume SMEM, change occupancy, and enlarge prologue/tail costs. There is no architecture-wide “three to five stages” range; the cited tutorial's beneficial v3 kernel uses two stages.\n\nDedicated producer, MMA, or epilogue warps can remove role switching from a loop and allow independent work to progress, but add live warps, registers, and synchronization. They do not eliminate stalls. If the epilogue owns the only output region, compare one versus multiple disjoint TMEM regions and prove MMA-completion and epilogue-load completion before each handoff.\n\n`cta_group::2` requires a valid cluster and exact kind-, shape-, layout-, descriptor-, and peer-resource constraints. It does not universally mean `m256n256`, require identical SMEM layouts, or promise twice the compute per cycle: one cooperative operation consumes resources from two CTAs. Compare total and per-SM throughput against a legal one-CTA mapping and measure whether peer operand reuse or a larger aggregate tile reduces traffic enough to repay coordination and occupancy costs.\n\nOptimize non-MMA work only after showing that it lies on the critical path. Fusion may remove intermediate traffic; tile interleaving may expose independent work; an approximation may exchange numerical error for throughput. Validate error against the application oracle rather than assuming a software transcendental is interchangeable with the hardware operation."}, "reason": {"statement": "Make CTA-group mode a controlled legal-shape and resource experiment.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu", "https://gau-nernst.github.io/tcgen05/"]}} +{"path": "wiki/patterns/compute-bound.md", "before": {"statement": "| [2-SM cooperative](../hardware/2sm-cooperative.md) | Double effective MMA tile (m256×n256), 2× compute per cycle |"}, "after": {"statement": "Enumerate stage counts that compile and fit the complete shared-storage allocation. More stages can overlap TMA production with MMA consumption, but they also consume SMEM, change occupancy, and enlarge prologue/tail costs. There is no architecture-wide “three to five stages” range; the cited tutorial's beneficial v3 kernel uses two stages.\n\nDedicated producer, MMA, or epilogue warps can remove role switching from a loop and allow independent work to progress, but add live warps, registers, and synchronization. They do not eliminate stalls. If the epilogue owns the only output region, compare one versus multiple disjoint TMEM regions and prove MMA-completion and epilogue-load completion before each handoff.\n\n`cta_group::2` requires a valid cluster and exact kind-, shape-, layout-, descriptor-, and peer-resource constraints. It does not universally mean `m256n256`, require identical SMEM layouts, or promise twice the compute per cycle: one cooperative operation consumes resources from two CTAs. Compare total and per-SM throughput against a legal one-CTA mapping and measure whether peer operand reuse or a larger aggregate tile reduces traffic enough to repay coordination and occupancy costs.\n\nOptimize non-MMA work only after showing that it lies on the critical path. Fusion may remove intermediate traffic; tile interleaving may expose independent work; an approximation may exchange numerical error for throughput. Validate error against the application oracle rather than assuming a software transcendental is interchangeable with the hardware operation."}, "reason": {"statement": "State exact compatibility scope and measure the paired-resource tradeoff.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu", "https://gau-nernst.github.io/tcgen05/"]}} +{"path": "wiki/patterns/compute-bound.md", "before": {"statement": "| [Warp specialization](../techniques/warp-specialization.md) | Dedicated warps for TMA/MMA/epilogue, no stalls |"}, "after": {"statement": "Enumerate stage counts that compile and fit the complete shared-storage allocation. More stages can overlap TMA production with MMA consumption, but they also consume SMEM, change occupancy, and enlarge prologue/tail costs. There is no architecture-wide “three to five stages” range; the cited tutorial's beneficial v3 kernel uses two stages.\n\nDedicated producer, MMA, or epilogue warps can remove role switching from a loop and allow independent work to progress, but add live warps, registers, and synchronization. They do not eliminate stalls. If the epilogue owns the only output region, compare one versus multiple disjoint TMEM regions and prove MMA-completion and epilogue-load completion before each handoff.\n\n`cta_group::2` requires a valid cluster and exact kind-, shape-, layout-, descriptor-, and peer-resource constraints. It does not universally mean `m256n256`, require identical SMEM layouts, or promise twice the compute per cycle: one cooperative operation consumes resources from two CTAs. Compare total and per-SM throughput against a legal one-CTA mapping and measure whether peer operand reuse or a larger aggregate tile reduces traffic enough to repay coordination and occupancy costs.\n\nOptimize non-MMA work only after showing that it lies on the critical path. Fusion may remove intermediate traffic; tile interleaving may expose independent work; an approximation may exchange numerical error for throughput. Validate error against the application oracle rather than assuming a software transcendental is interchangeable with the hardware operation."}, "reason": {"statement": "Treat role separation as a candidate with resource and synchronization costs.", "urls": ["https://gau-nernst.github.io/tcgen05/", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma"]}} +{"path": "wiki/patterns/compute-bound.md", "before": {"statement": "```\n// Problem: Blackwell doubles tensor core throughput but SFU count unchanged\n// SFU bottleneck: exp() for softmax\n//\n// Solution: Software 2^x via Cody-Waite + Horner polynomial\n// Distributes across FMA units, multiplying exponential throughput\n// Result: 1605 TFLOPS (71% utilization) on B200\n```"}, "after": {"statement": "FA4's B200 analysis reports 8192 BF16 MMA operations per clock per SM versus 4096 on Hopper, while exponential throughput is 16 operations per clock per SM on both. Its response is a coordinated design: two-output-tile scheduling, selected software exponentials, conditional rescaling, TMEM partitioning, and pipeline/register choices.\n\nThe software path uses base-2 range reduction with `n=floor(x)` and a cubic FMA polynomial for a selected fraction of exponential evaluations; other values still use hardware `ex2`. The paper evaluates approximation error and end-to-end accuracy. This is not a claim that every exponential uses Cody-Waite reduction or that polynomial evaluation universally multiplies exponential throughput.\n\nThe paper reports up to 1613 TFLOP/s and 71% for complete FA4 forward kernels; the author blog reports up to 1605 TFLOP/s and 71%. Neither number isolates software exponentiation or any other single technique. Use FA4 as evidence that non-MMA work can become material after tensor-core throughput increases, not as a recipe for an unrelated compute-bound kernel."}, "reason": {"statement": "Remove the misleading pseudo-code and present the exact scoped case in prose.", "urls": ["https://arxiv.org/html/2603.05451v1", "https://tridao.me/blog/2026/flash4/"]}} +{"path": "wiki/patterns/compute-bound.md", "before": {"statement": "- 2-SM cooperative requires cluster configuration and identical SMEM layouts"}, "after": {"statement": "Enumerate stage counts that compile and fit the complete shared-storage allocation. More stages can overlap TMA production with MMA consumption, but they also consume SMEM, change occupancy, and enlarge prologue/tail costs. There is no architecture-wide “three to five stages” range; the cited tutorial's beneficial v3 kernel uses two stages.\n\nDedicated producer, MMA, or epilogue warps can remove role switching from a loop and allow independent work to progress, but add live warps, registers, and synchronization. They do not eliminate stalls. If the epilogue owns the only output region, compare one versus multiple disjoint TMEM regions and prove MMA-completion and epilogue-load completion before each handoff.\n\n`cta_group::2` requires a valid cluster and exact kind-, shape-, layout-, descriptor-, and peer-resource constraints. It does not universally mean `m256n256`, require identical SMEM layouts, or promise twice the compute per cycle: one cooperative operation consumes resources from two CTAs. Compare total and per-SM throughput against a legal one-CTA mapping and measure whether peer operand reuse or a larger aggregate tile reduces traffic enough to repay coordination and occupancy costs.\n\nOptimize non-MMA work only after showing that it lies on the critical path. Fusion may remove intermediate traffic; tile interleaving may expose independent work; an approximation may exchange numerical error for throughput. Validate error against the application oracle rather than assuming a software transcendental is interchangeable with the hardware operation."}, "reason": {"statement": "Use the actual instruction/configuration contract.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu", "https://gau-nernst.github.io/tcgen05/"]}} +{"path": "wiki/patterns/compute-bound.md", "before": {"statement": "- Pipeline depth tuning is workload-dependent (3-5 stages typical)"}, "after": {"statement": "Enumerate stage counts that compile and fit the complete shared-storage allocation. More stages can overlap TMA production with MMA consumption, but they also consume SMEM, change occupancy, and enlarge prologue/tail costs. There is no architecture-wide “three to five stages” range; the cited tutorial's beneficial v3 kernel uses two stages.\n\nDedicated producer, MMA, or epilogue warps can remove role switching from a loop and allow independent work to progress, but add live warps, registers, and synchronization. They do not eliminate stalls. If the epilogue owns the only output region, compare one versus multiple disjoint TMEM regions and prove MMA-completion and epilogue-load completion before each handoff.\n\n`cta_group::2` requires a valid cluster and exact kind-, shape-, layout-, descriptor-, and peer-resource constraints. It does not universally mean `m256n256`, require identical SMEM layouts, or promise twice the compute per cycle: one cooperative operation consumes resources from two CTAs. Compare total and per-SM throughput against a legal one-CTA mapping and measure whether peer operand reuse or a larger aggregate tile reduces traffic enough to repay coordination and occupancy costs.\n\nOptimize non-MMA work only after showing that it lies on the critical path. Fusion may remove intermediate traffic; tile interleaving may expose independent work; an approximation may exchange numerical error for throughput. Validate error against the application oracle rather than assuming a software transcendental is interchangeable with the hardware operation."}, "reason": {"statement": "Retain only configuration dependence and controlled selection.", "urls": ["https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v3.cu", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma", "https://gau-nernst.github.io/tcgen05/"]}} +{"path": "wiki/patterns/low-sm-utilization.md", "before": {"statement": "SM utilization below 60% despite sufficient occupancy. Nsight Compute shows idle SMs during portions of kernel execution."}, "after": {"statement": "Low SM utilization means that fewer SMs perform useful work than the workload could profitably use during a material part of its measured time. It is not defined by a universal 60% threshold. Theoretical occupancy describes how many blocks or warps can reside from resource limits; it does not prove that the grid supplies those workers, that they are simultaneously active, or that their work is balanced.\n\nCollect a synchronized kernel time and a time-resolved view where supported. Record the physical and application-constrained SM count, grid and cluster dimensions, blocks resident per SM, logical work count, work duration distribution, and active/idle intervals. Aggregate SM activity alone cannot distinguish a small grid, a partial final wave, variable-duration work, resource-limited residency, or phase-local serial work."}, "reason": {"statement": "Define the symptom from insufficient useful active work relative to required parallelism and timing.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/low-sm-utilization.md", "before": {"statement": "| [CLC](../hardware/clc.md) | SM100 only | Dynamic tile assignment, eliminates load imbalance |"}, "after": {"statement": "Persistence, coordinate order, CLC reassignment, and K decomposition are separate controls:\n\n- A static persistent worker can process multiple logical tiles by grid stride. It can amortize setup and change wave behavior but cannot guarantee removal of the final tail.\n- A row/column raster or swizzle changes coordinate order and may change operand locality. It does not guarantee a better L2 hit rate or lower work variance.\n- Cluster Launch Control lets a running worker cancel an unspecified not-yet-started block or cluster from the launched grid and process the returned ID. It redistributes existing work; it cannot create independent tiles, discard required work, or guarantee equal worker times.\n- Stream-K or Split-K can create additional partitions when tile-level parallelism is insufficient, at the cost of partial-result reduction, workspace, synchronization, and possible determinism changes.\n\nFor CLC, compare static and dynamic scheduling with identical math, tile/cluster shapes, problem-sized grid, resource limits, and timing method. Record successful and failed requests plus per-worker work counts where instrumentation permits. Include ordinary and intentionally uneven SM availability as separate cases.\n\nPTX ISA 9.0 says `clusterlaunchcontrol.try_cancel` requires `sm_100` or higher; its cluster-wide multicast qualifier explicitly lists `sm_120a` and the SM120 family. Therefore CLC is not categorically excluded from SM120 by the ISA. The pinned CUTLASS 4.5.0 persistent scheduler discussed in this wiki is specifically an SM100 integration; do not generalize a library route into an architecture exclusion."}, "reason": {"statement": "State exact redistribution scope and failure/parallelism limits.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/low-sm-utilization.md", "before": {"statement": "| [Persistent kernels](../techniques/persistent-kernels.md) | SM90+ | Eliminates tail effect, one-time launch overhead |"}, "after": {"statement": "Persistence, coordinate order, CLC reassignment, and K decomposition are separate controls:\n\n- A static persistent worker can process multiple logical tiles by grid stride. It can amortize setup and change wave behavior but cannot guarantee removal of the final tail.\n- A row/column raster or swizzle changes coordinate order and may change operand locality. It does not guarantee a better L2 hit rate or lower work variance.\n- Cluster Launch Control lets a running worker cancel an unspecified not-yet-started block or cluster from the launched grid and process the returned ID. It redistributes existing work; it cannot create independent tiles, discard required work, or guarantee equal worker times.\n- Stream-K or Split-K can create additional partitions when tile-level parallelism is insufficient, at the cost of partial-result reduction, workspace, synchronization, and possible determinism changes.\n\nFor CLC, compare static and dynamic scheduling with identical math, tile/cluster shapes, problem-sized grid, resource limits, and timing method. Record successful and failed requests plus per-worker work counts where instrumentation permits. Include ordinary and intentionally uneven SM availability as separate cases.\n\nPTX ISA 9.0 says `clusterlaunchcontrol.try_cancel` requires `sm_100` or higher; its cluster-wide multicast qualifier explicitly lists `sm_120a` and the SM120 family. Therefore CLC is not categorically excluded from SM120 by the ISA. The pinned CUTLASS 4.5.0 persistent scheduler discussed in this wiki is specifically an SM100 integration; do not generalize a library route into an architecture exclusion."}, "reason": {"statement": "Separate persistence from dynamic assignment and measure tail distribution.", "urls": ["https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/low-sm-utilization.md", "before": {"statement": "| [Tile scheduling](../techniques/tile-scheduling.md) | SM90+ | Better L2 locality, reduce load variance |"}, "after": {"statement": "Persistence, coordinate order, CLC reassignment, and K decomposition are separate controls:\n\n- A static persistent worker can process multiple logical tiles by grid stride. It can amortize setup and change wave behavior but cannot guarantee removal of the final tail.\n- A row/column raster or swizzle changes coordinate order and may change operand locality. It does not guarantee a better L2 hit rate or lower work variance.\n- Cluster Launch Control lets a running worker cancel an unspecified not-yet-started block or cluster from the launched grid and process the returned ID. It redistributes existing work; it cannot create independent tiles, discard required work, or guarantee equal worker times.\n- Stream-K or Split-K can create additional partitions when tile-level parallelism is insufficient, at the cost of partial-result reduction, workspace, synchronization, and possible determinism changes.\n\nFor CLC, compare static and dynamic scheduling with identical math, tile/cluster shapes, problem-sized grid, resource limits, and timing method. Record successful and failed requests plus per-worker work counts where instrumentation permits. Include ordinary and intentionally uneven SM availability as separate cases.\n\nPTX ISA 9.0 says `clusterlaunchcontrol.try_cancel` requires `sm_100` or higher; its cluster-wide multicast qualifier explicitly lists `sm_120a` and the SM120 family. Therefore CLC is not categorically excluded from SM120 by the ISA. The pinned CUTLASS 4.5.0 persistent scheduler discussed in this wiki is specifically an SM100 integration; do not generalize a library route into an architecture exclusion."}, "reason": {"statement": "Map each scheduler choice to a specific measured hypothesis.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel"]}} +{"path": "wiki/patterns/low-sm-utilization.md", "before": {"statement": "```\n// tcgen05 tutorial progression:\n// Without persistent/CLC: 86% of cuBLAS (some SMs idle at wave boundaries)\n// With persistent + CLC: 98% of cuBLAS (all SMs stay busy)\n```"}, "after": {"statement": "In Gau Nernst's `M=N=K=4096` B200 experiment, v5 reports 1302.29 TFLOP/s (86.43% of its 1506.74-TFLOP/s cuBLAS value), while v6 reports 1475.93 TFLOP/s (97.96%). The v6 endpoint combines static persistence, a changed output pipeline, and epilogue-specialized warps on top of earlier changes. The author says CLC was not added and observes that overlap remains imperfect. This is not a CLC result, an all-SMs-busy measurement, or an isolated tail-effect ablation."}, "reason": {"statement": "Report exact cumulative version scope without all-SMs-busy causality.", "urls": ["https://gau-nernst.github.io/tcgen05/", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v6.cu"]}} +{"path": "wiki/patterns/low-sm-utilization.md", "before": {"statement": "- CLC only available on SM100 datacenter GPUs (not SM120 consumer)"}, "after": {"statement": "Persistence, coordinate order, CLC reassignment, and K decomposition are separate controls:\n\n- A static persistent worker can process multiple logical tiles by grid stride. It can amortize setup and change wave behavior but cannot guarantee removal of the final tail.\n- A row/column raster or swizzle changes coordinate order and may change operand locality. It does not guarantee a better L2 hit rate or lower work variance.\n- Cluster Launch Control lets a running worker cancel an unspecified not-yet-started block or cluster from the launched grid and process the returned ID. It redistributes existing work; it cannot create independent tiles, discard required work, or guarantee equal worker times.\n- Stream-K or Split-K can create additional partitions when tile-level parallelism is insufficient, at the cost of partial-result reduction, workspace, synchronization, and possible determinism changes.\n\nFor CLC, compare static and dynamic scheduling with identical math, tile/cluster shapes, problem-sized grid, resource limits, and timing method. Record successful and failed requests plus per-worker work counts where instrumentation permits. Include ordinary and intentionally uneven SM availability as separate cases.\n\nPTX ISA 9.0 says `clusterlaunchcontrol.try_cancel` requires `sm_100` or higher; its cluster-wide multicast qualifier explicitly lists `sm_120a` and the SM120 family. Therefore CLC is not categorically excluded from SM120 by the ISA. The pinned CUTLASS 4.5.0 persistent scheduler discussed in this wiki is specifically an SM100 integration; do not generalize a library route into an architecture exclusion."}, "reason": {"statement": "Separate PTX target support from pinned CUTLASS integration.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/low-sm-utilization.md", "before": {"statement": "- For non-persistent kernels, ensure grid size >> SM count"}, "after": {"statement": "| Too little independent work | Logical block/cluster count is below available one-wave worker capacity | Change problem decomposition, accounting for reduction and synchronization cost |\n| Wave quantization | Equal-duration data-parallel work has a small nonzero final-wave remainder | Compare tile shapes or a decomposition that changes tile count |\n| Variable work duration | Per-worker tile counts/times have a long tail despite enough pending work | Compare static and dynamic acquisition with identical tile/decomposition |\n| Residency or phase limitation | Grid is large, but resources or serial phases limit active blocks/warps | Change the limiting resource or phase; more grid blocks alone do not help |\n\nStatic assignment is nonadaptive, but it is not automatically imbalanced. A grid with fewer independent blocks than SMs cannot occupy every SM, while a grid much larger than the SM count can still show a tail or long-running stragglers. Do not prescribe `grid size >> SM count` without a decomposition that creates useful independent work."}, "reason": {"statement": "Use explicit worker-demand and tile arithmetic.", "urls": ["https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "Nsight Compute shows high DRAM throughput but low tensor core utilization. Arithmetic intensity below the roofline knee point."}, "after": {"statement": "A kernel is memory-bandwidth bound when its measured arithmetic intensity places it on the memory side of the relevant roofline and its useful throughput is limited by an attained memory ceiling. Compute intensity from the operations actually performed and bytes transferred at the memory level under study. Compare against a measured ceiling for the same device, clocks, memory level, datatype path, and environment; a nominal product bandwidth is only an upper-bound input.\n\nHigh DRAM throughput, low tensor-core activity, or a workload label such as GEMV is not sufficient alone. Record useful/requested bytes, transferred sectors or bytes, achieved bandwidth, cache behavior, scheduler issue/stalls, and end-to-end time. This separates four cases that can otherwise look similar:\n\n| Useful bytes and transferred bytes are close; attained bandwidth is near the measured roof | Plausible bandwidth-ceiling limit |\n| Transferred bytes substantially exceed useful bytes | Coalescing, overfetch, cache, or redundant-traffic problem |\n| Bandwidth is below the roof and warps lack ready work | Latency, dependency, insufficient concurrency, or issue problem |\n| Bandwidth is high only during one phase | Phase balance or fusion opportunity; whole-kernel boundedness remains unproven |\n\nSingle-use data can lower operations per transferred byte, but “poor reuse” is actionable only if additional legal reuse exists. Uncoalesced access and cache interference may increase traffic or latency; they are not synonyms for saturation of the DRAM bandwidth ceiling."}, "reason": {"statement": "Require a complete roofline and traffic/issue record.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html#roofline", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "1. **Low arithmetic intensity**: Operations like GEMV, small batch decode, or reduction kernels"}, "after": {"statement": "A kernel is memory-bandwidth bound when its measured arithmetic intensity places it on the memory side of the relevant roofline and its useful throughput is limited by an attained memory ceiling. Compute intensity from the operations actually performed and bytes transferred at the memory level under study. Compare against a measured ceiling for the same device, clocks, memory level, datatype path, and environment; a nominal product bandwidth is only an upper-bound input.\n\nHigh DRAM throughput, low tensor-core activity, or a workload label such as GEMV is not sufficient alone. Record useful/requested bytes, transferred sectors or bytes, achieved bandwidth, cache behavior, scheduler issue/stalls, and end-to-end time. This separates four cases that can otherwise look similar:\n\n| Useful bytes and transferred bytes are close; attained bandwidth is near the measured roof | Plausible bandwidth-ceiling limit |\n| Transferred bytes substantially exceed useful bytes | Coalescing, overfetch, cache, or redundant-traffic problem |\n| Bandwidth is below the roof and warps lack ready work | Latency, dependency, insufficient concurrency, or issue problem |\n| Bandwidth is high only during one phase | Phase balance or fusion opportunity; whole-kernel boundedness remains unproven |\n\nSingle-use data can lower operations per transferred byte, but “poor reuse” is actionable only if additional legal reuse exists. Uncoalesced access and cache interference may increase traffic or latency; they are not synonyms for saturation of the DRAM bandwidth ceiling."}, "reason": {"statement": "Use measured work and bytes for the actual implementation/input.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html#roofline", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "3. **Inefficient memory access**: Uncoalesced loads, L1 cache thrashing"}, "after": {"statement": "Choose only legal, naturally aligned vector forms and handle tails separately. Compare scalar/narrow and wider variants with identical mapping. Record instruction count, requested and transferred bytes, transactions, registers, spills, achieved bandwidth, and time. Wider instructions do not guarantee fewer hardware transactions or higher bandwidth.\n\nPTX L1 eviction priorities and L2 prefetch controls are hints. `no_allocate` does not guarantee bypass, and `evict_last` does not guarantee residence. Characterize address order, reuse distance, working set, and interfering streams, then vary one hint at a time against the default. Retain it only when a representative end-to-end comparison improves.\n\nInspect compiled registers, spills, SMEM, threads, and the actual occupancy-limiting resource before applying `-maxrregcount`. A cap may be clamped by ABI requirements, introduce spill traffic, or leave occupancy unchanged. Higher theoretical occupancy is useful only if it raises ready work or attained bandwidth enough to reduce runtime.\n\nTMA multicast can issue one global-to-shared tensor copy to selected CTAs' shared-memory destinations within a cluster. It is relevant when those CTAs consume the same operand and the cluster/lifetime/barrier costs are valid. It does not help a stream with no inter-CTA reuse.\n\nSwizzling changes a shared-memory address mapping and can reduce conflicts for a specified access pattern. It does not universally eliminate conflicts and is not by itself a DRAM optimization. Validate the legal tensor-map/layout constraints and compare bank-conflict, traffic, and time measurements."}, "reason": {"statement": "Separate bandwidth ceiling, transaction efficiency, cache behavior, and latency/issue limits.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "| [Vectorized loads](../techniques/vectorized-loads.md) | 128/256-bit loads maximize bandwidth utilization |"}, "after": {"statement": "The cited Amandeep NVFP4 GEMV report is useful precisely because plausible memory-oriented changes failed. A wider `uint2` load was 16–25% slower on the reported shapes, and reducing `maxrregcount` from 80 to 64 had no effect. These observations do not prove that wide loads or register caps are generally harmful; they refute a fixed optimization priority based only on the “memory-bound GEMV” label.\n\nUse the same discipline for compute work. If the kernel is genuinely at its attainable memory roof, compute-only instruction reductions may have little effect. But address calculation, decoding, and instruction-level parallelism can affect memory issue and latency hiding before that roof is reached. State a predicted counter change, alter one variable, and keep or reject the hypothesis from matched time and profiler evidence."}, "reason": {"statement": "Make width an aligned legal candidate with a scalar/narrow control.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "| [Cache policies](../techniques/vectorized-loads.md) | L1::no_allocate for streaming, L1::evict_last for reuse |"}, "after": {"statement": "The cited Amandeep NVFP4 GEMV report is useful precisely because plausible memory-oriented changes failed. A wider `uint2` load was 16–25% slower on the reported shapes, and reducing `maxrregcount` from 80 to 64 had no effect. These observations do not prove that wide loads or register caps are generally harmful; they refute a fixed optimization priority based only on the “memory-bound GEMV” label.\n\nUse the same discipline for compute work. If the kernel is genuinely at its attainable memory roof, compute-only instruction reductions may have little effect. But address calculation, decoding, and instruction-level parallelism can affect memory issue and latency hiding before that roof is reached. State a predicted counter change, alter one variable, and keep or reject the hypothesis from matched time and profiler evidence."}, "reason": {"statement": "Test hints one variable at a time from concrete reuse/interference evidence.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "| [Register budgeting](../techniques/vectorized-loads.md) | -maxrregcount increases occupancy |"}, "after": {"statement": "The cited Amandeep NVFP4 GEMV report is useful precisely because plausible memory-oriented changes failed. A wider `uint2` load was 16–25% slower on the reported shapes, and reducing `maxrregcount` from 80 to 64 had no effect. These observations do not prove that wide loads or register caps are generally harmful; they refute a fixed optimization priority based only on the “memory-bound GEMV” label.\n\nUse the same discipline for compute work. If the kernel is genuinely at its attainable memory roof, compute-only instruction reductions may have little effect. But address calculation, decoding, and instruction-level parallelism can affect memory issue and latency hiding before that roof is reached. State a predicted counter change, alter one variable, and keep or reject the hypothesis from matched time and profiler evidence."}, "reason": {"statement": "Use compiled-resource and occupancy evidence before timing caps.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "| [Swizzling](../techniques/swizzling.md) | Eliminate bank conflicts in shared memory |"}, "after": {"statement": "The cited Amandeep NVFP4 GEMV report is useful precisely because plausible memory-oriented changes failed. A wider `uint2` load was 16–25% slower on the reported shapes, and reducing `maxrregcount` from 80 to 64 had no effect. These observations do not prove that wide loads or register caps are generally harmful; they refute a fixed optimization priority based only on the “memory-bound GEMV” label.\n\nUse the same discipline for compute work. If the kernel is genuinely at its attainable memory roof, compute-only instruction reductions may have little effect. But address calculation, decoding, and instruction-level parallelism can affect memory issue and latency hiding before that roof is reached. State a predicted counter change, alter one variable, and keep or reject the hypothesis from matched time and profiler evidence."}, "reason": {"statement": "Treat swizzle as a shared-memory conflict hypothesis, not a DRAM-bandwidth cure.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-map-swizzle", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "```cuda\n// NVFP4 GEMV: memory-bound optimization\n// Key insight: profile FIRST to confirm memory-bound behavior\n// \"The single most important thing could have been running Nsight Compute\"\n// — Amandeep (12 Attempts at an FP4 Kernel)\n\n// Optimization priorities for memory-bound kernels:\n// 1. Maximize memory bandwidth (wide loads, coalescing)\n// 2. Reduce register count (higher occupancy)\n// 3. Differentiate cache policies per access pattern\n// 4. DON'T optimize compute (it's not the bottleneck)\n```"}, "after": {"statement": "Report input shapes/distributions, useful work and bytes, cache state, warmup/repetitions/statistic, GPU and clocks, software versions, generated instructions, resource usage, roofline assumptions, achieved memory-level bandwidth, requested/transferred efficiency, scheduler activity, and correctness tolerance. Include negative and regressing variants so a category heuristic is not mistaken for causal evidence."}, "reason": {"statement": "Replace the pseudo-code prescription with the exact negative-control lesson.", "urls": ["https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "- B200 has 8 TB/s bandwidth; speed-of-light calculation determines achievable performance"}, "after": {"statement": "A kernel is memory-bandwidth bound when its measured arithmetic intensity places it on the memory side of the relevant roofline and its useful throughput is limited by an attained memory ceiling. Compute intensity from the operations actually performed and bytes transferred at the memory level under study. Compare against a measured ceiling for the same device, clocks, memory level, datatype path, and environment; a nominal product bandwidth is only an upper-bound input.\n\nHigh DRAM throughput, low tensor-core activity, or a workload label such as GEMV is not sufficient alone. Record useful/requested bytes, transferred sectors or bytes, achieved bandwidth, cache behavior, scheduler issue/stalls, and end-to-end time. This separates four cases that can otherwise look similar:\n\n| Useful bytes and transferred bytes are close; attained bandwidth is near the measured roof | Plausible bandwidth-ceiling limit |\n| Transferred bytes substantially exceed useful bytes | Coalescing, overfetch, cache, or redundant-traffic problem |\n| Bandwidth is below the roof and warps lack ready work | Latency, dependency, insufficient concurrency, or issue problem |\n| Bandwidth is high only during one phase | Phase balance or fusion opportunity; whole-kernel boundedness remains unproven |\n\nSingle-use data can lower operations per transferred byte, but “poor reuse” is actionable only if additional legal reuse exists. Uncoalesced access and cache interference may increase traffic or latency; they are not synonyms for saturation of the DRAM bandwidth ceiling."}, "reason": {"statement": "Use measured ceiling and efficiency with complete environment scope.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html#roofline", "https://www.nvidia.com/en-us/data-center/blackwell/", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "- ILP and compute optimizations have diminishing returns for memory-bound kernels"}, "after": {"statement": "Choose only legal, naturally aligned vector forms and handle tails separately. Compare scalar/narrow and wider variants with identical mapping. Record instruction count, requested and transferred bytes, transactions, registers, spills, achieved bandwidth, and time. Wider instructions do not guarantee fewer hardware transactions or higher bandwidth.\n\nPTX L1 eviction priorities and L2 prefetch controls are hints. `no_allocate` does not guarantee bypass, and `evict_last` does not guarantee residence. Characterize address order, reuse distance, working set, and interfering streams, then vary one hint at a time against the default. Retain it only when a representative end-to-end comparison improves.\n\nInspect compiled registers, spills, SMEM, threads, and the actual occupancy-limiting resource before applying `-maxrregcount`. A cap may be clamped by ABI requirements, introduce spill traffic, or leave occupancy unchanged. Higher theoretical occupancy is useful only if it raises ready work or attained bandwidth enough to reduce runtime.\n\nTMA multicast can issue one global-to-shared tensor copy to selected CTAs' shared-memory destinations within a cluster. It is relevant when those CTAs consume the same operand and the cluster/lifetime/barrier costs are valid. It does not help a stream with no inter-CTA reuse.\n\nSwizzling changes a shared-memory address mapping and can reduce conflicts for a specified access pattern. It does not universally eliminate conflicts and is not by itself a DRAM optimization. Validate the legal tensor-map/layout constraints and compare bank-conflict, traffic, and time measurements.\n\nThe cited Amandeep NVFP4 GEMV report is useful precisely because plausible memory-oriented changes failed. A wider `uint2` load was 16–25% slower on the reported shapes, and reducing `maxrregcount` from 80 to 64 had no effect. These observations do not prove that wide loads or register caps are generally harmful; they refute a fixed optimization priority based only on the “memory-bound GEMV” label.\n\nUse the same discipline for compute work. If the kernel is genuinely at its attainable memory roof, compute-only instruction reductions may have little effect. But address calculation, decoding, and instruction-level parallelism can affect memory issue and latency hiding before that roof is reached. State a predicted counter change, alter one variable, and keep or reject the hypothesis from matched time and profiler evidence."}, "reason": {"statement": "Tie every candidate to a measured critical resource and predicted counter movement.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor", "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"]}} +{"path": "wiki/patterns/register-pressure.md", "before": {"statement": "Occupancy below target due to high register usage per thread. Nsight Compute shows register spilling to local memory."}, "after": {"statement": "Register pressure is performance-relevant only when compiled register allocation or spills constrain useful scheduling or add material local-memory traffic. “Occupancy below target” is not enough: theoretical occupancy is a residency limit, achieved occupancy is runtime behavior, and maximum occupancy is not a universal optimum.\n\nFor the exact binary and launch, record registers per thread, allocation granularity, spill stores/loads, local-memory traffic, threads and warps per CTA, SMEM, cluster shape, theoretical limiting resource, achieved active/eligible warps, scheduler stalls, and end-to-end time. Inspect generated SASS/source correlation to find the live ranges or spill sites. Then change one source or compiler factor and require the predicted resource/stall movement plus a runtime improvement.\n\nCommon contributors include a resident MMA fragment, an epilogue whose temporaries overlap the mainloop, descriptors/addresses and pipeline state, unrolled loops, and values live across branches. These are hypotheses about compiled liveness, not conclusions from source complexity alone."}, "reason": {"statement": "Require compiled resource and limiting-resource evidence plus a causal variant.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/register-pressure.md", "before": {"statement": "| [TMEM](../hardware/tmem.md) | SM100 only | Moves accumulators to dedicated 256KB memory |"}, "after": {"statement": "For Hopper `wgmma.mma_async.m64nNk16` with FP32 D, each warpgroup thread holds `N/2` accumulator registers. At `N=256`, that is 128 32-bit registers (512 bytes) per thread for D. This exact fragment arithmetic does not include other live state or guarantee a particular resident-block count.\n\nOn the SM100 tcgen05 path, resident D is in TMEM, organized as 128 lanes by 512 columns of 32-bit cells. That removes the long-lived per-thread WGMMA D fragment, but not all accumulator-related register work: addresses, descriptors, barriers, loop state, `tcgen05.ld` destinations, conversion, and epilogue temporaries still consume registers. Logical capacity and required columns depend on MMA kind, shape, and packing, so a largest-operation or always-double-bufferable rule cannot be inferred from raw cell count.\n\nThe migration must implement collective allocation/address publication, tcgen05 MMA completion, cross-thread ordering where applicable, collective TMEM loads and `tcgen05.wait::ld`, consumer completion, and collective deallocation before exit. The described TMEM/tcgen05 path targets SM100-class data-center architectures and is not the SM120 consumer MMA path."}, "reason": {"statement": "State organization and resident-D scope without promising exact register relief.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-instructions-wgmma-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld"]}} +{"path": "wiki/patterns/register-pressure.md", "before": {"statement": "| [Warp specialization](../techniques/warp-specialization.md) | SM100+ | Different warps handle different roles, reducing per-warp register needs |"}, "after": {"statement": "Move epilogue work after accumulator lifetime when dependencies allow, reduce unnecessary unrolling, or split a long-lived role. Warp specialization exists on Hopper as well as Blackwell; it can shorten one role's live set, but adds role state and synchronization and does not guarantee fewer registers. Compare compiled resources and time for matched role layouts.\n\nCompare an uncapped build with selected `-maxrregcount` values. Record whether the requested cap is effective, the occupancy-limiting resource, spill traffic, instructions, and runtime. ABI minima can constrain the cap, another resource can remain limiting, and spills can erase any benefit."}, "reason": {"statement": "Separate architecture availability from measured role-liveness/resource changes.", "urls": ["https://docs.nvidia.com/cutlass/4.5.0/media/docs/cpp/gemm_api_3x.html", "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-compiler-driver-nvcc/index.html"]}} +{"path": "wiki/patterns/register-pressure.md", "before": {"statement": "```\n// Hopper: 64×256 MMA tile accumulator = 64*256*4 bytes in registers per warp group\n// → ~128 registers per thread just for accumulators\n//\n// Blackwell: TMEM holds accumulators\n// → 0 registers for accumulators\n// → ~128 registers freed for other work or higher occupancy\n//\n// TMEM: 256 KB per SM, 128 rows × 512 columns × 32-bit\n// Largest 1-SM MMA uses half → double-buffering possible\n```"}, "after": {"statement": "For Hopper `wgmma.mma_async.m64nNk16` with FP32 D, each warpgroup thread holds `N/2` accumulator registers. At `N=256`, that is 128 32-bit registers (512 bytes) per thread for D. This exact fragment arithmetic does not include other live state or guarantee a particular resident-block count.\n\nOn the SM100 tcgen05 path, resident D is in TMEM, organized as 128 lanes by 512 columns of 32-bit cells. That removes the long-lived per-thread WGMMA D fragment, but not all accumulator-related register work: addresses, descriptors, barriers, loop state, `tcgen05.ld` destinations, conversion, and epilogue temporaries still consume registers. Logical capacity and required columns depend on MMA kind, shape, and packing, so a largest-operation or always-double-bufferable rule cannot be inferred from raw cell count.\n\nThe migration must implement collective allocation/address publication, tcgen05 MMA completion, cross-thread ordering where applicable, collective TMEM loads and `tcgen05.wait::ld`, consumer completion, and collective deallocation before exit. The described TMEM/tcgen05 path targets SM100-class data-center architectures and is not the SM120 consumer MMA path."}, "reason": {"statement": "Keep the exact comparison while naming residual registers and configuration-specific capacity.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-instructions-wgmma-mma", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld"]}} +{"path": "wiki/patterns/register-pressure.md", "before": {"statement": "- TMEM→register transfer adds latency (offset by freeing registers)"}, "after": {"statement": "TMEM loads are asynchronous operations with explicit completion waits. Whether their issue/wait and epilogue work are repaid by lower long-lived register use is an empirical whole-kernel question. Compare the Hopper and Blackwell designs only with equivalent math and precision; for same-architecture alternatives, compare TMEM region count/layout while holding tile and launch policy fixed.\n\nReport compiled registers and spills, TMEM columns, SMEM, barriers, occupancy limit, achieved warps, pipeline/scoreboard stalls, correctness, and time. Include shapes where register occupancy changes and shapes where it does not. A reduction in register count without a useful residency, issue, traffic, or time improvement is not sufficient."}, "reason": {"statement": "Make it a controlled whole-kernel tradeoff.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/tail-effect.md", "before": {"statement": "Performance drops for problem sizes where total_tiles % num_SMs != 0. The last wave of tiles runs with many SMs idle."}, "after": {"statement": "For `T` equal-duration independent tiles and `W` available one-tile workers, with no K decomposition, write:\n\n```text\nT = qW + r, 0 <= r < W\n```\n\nThere are `q` full waves. If `r>0`, a final partial wave uses `r` workers and has instantaneous worker utilization `r/W`; if `r=0` and `T>0`, the final wave is full. For example, `T=150` and `W=142` gives one full wave plus eight tiles: the partial wave has `8/142 = 5.63%` worker utilization under these assumptions.\n\nThis is an analytical model, not a statement that a B200 has 142 SMs or that physical SM count always equals `W`. Block resources can make multiple blocks resident per SM, cluster shape changes scheduling granularity, application policies may restrict available SMs, and tile durations can differ. Measure the actual worker capacity and timeline.\n\nUnder the equal-duration model, the time fraction attributable to at most one partial wave shrinks as the number of full waves grows. There is no universal “below four times the SM count” cutoff: the remainder, wave duration, other phases, and imbalance determine significance."}, "reason": {"statement": "Define and compute the simplified model, then require measurement for real kernels.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/tail-effect.md", "before": {"statement": "2. **Static assignment**: stride-by-gridDim leaves remainder tiles on few SMs\n3. **Non-persistent launch**: each kernel launch has fixed grid, no dynamic rebalancing"}, "after": {"statement": "1. Record logical tiles/clusters, grid and cluster dimensions, available worker capacity, residency limits, and per-work-item duration.\n2. Predict wave count and the final remainder from the simplified model.\n3. Use time-resolved activity or instrumented worker records to locate the underfilled interval at the end, rather than inferring it from aggregate utilization.\n4. Sweep nearby problem sizes or tile shapes. A wave-quantization hypothesis predicts a sawtooth response aligned with changes in the remainder, after controlling total work.\n5. Separate unequal tile durations: a long straggler is load imbalance even if the tile-count remainder is zero.\n\nCUDA schedules ordinary grid blocks onto available SMs; a static grid-stride loop fixes logical worker indices, not `blockIdx`-to-physical-SM placement. A fixed grid therefore does not mean CUDA lacks dynamic block scheduling."}, "reason": {"statement": "Separate logical worker assignment from hardware block placement and persistence.", "urls": ["https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/patterns/tail-effect.md", "before": {"statement": "| [CLC](../hardware/clc.md) | Hardware dynamic scheduling, SMs grab tiles on-demand |"}, "after": {"statement": "- A static persistent loop lets a resident CTA process multiple logical work items. Worker count is selected from problem decomposition, cluster/resource limits, and policy—not necessarily one CTA per physical SM. Finite work still has a final subset and may remain imbalanced.\n- Cluster Launch Control lets a selected thread request cancellation of an unspecified not-yet-started block or cluster and process the returned grid ID. CLC redistributes existing IDs; it cannot turn eight remaining independent tiles into 142 or 148 concurrent tiles.\n- Raster order and swizzle are coordinate transforms. Test them for locality while holding work acquisition fixed; they do not create work or guarantee balanced durations.\n- Stream-K or Split-K may create more independent partitions when tile-level work is insufficient. Evaluate reduction traffic, workspace, synchronization, determinism, and numerical effects separately.\n\nCompare static and CLC-backed persistence with identical math, decomposition, tile/cluster shapes, grid, resources, and timing. Record CLC request results and per-worker work/time distribution. PTX ISA 9.0 requires `sm_100` or higher for CLC and explicitly lists SM120-family support for the cluster-wide multicast qualifier; the pinned CUTLASS 4.5.0 route used here is specifically its SM100 scheduler."}, "reason": {"statement": "Describe exact work-reassignment lifecycle and limits.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/tail-effect.md", "before": {"statement": "| [Persistent kernels](../techniques/persistent-kernels.md) | SM-count grid, iterate over tiles, no wave boundary |"}, "after": {"statement": "- A static persistent loop lets a resident CTA process multiple logical work items. Worker count is selected from problem decomposition, cluster/resource limits, and policy—not necessarily one CTA per physical SM. Finite work still has a final subset and may remain imbalanced.\n- Cluster Launch Control lets a selected thread request cancellation of an unspecified not-yet-started block or cluster and process the returned grid ID. CLC redistributes existing IDs; it cannot turn eight remaining independent tiles into 142 or 148 concurrent tiles.\n- Raster order and swizzle are coordinate transforms. Test them for locality while holding work acquisition fixed; they do not create work or guarantee balanced durations.\n- Stream-K or Split-K may create more independent partitions when tile-level work is insufficient. Evaluate reduction traffic, workspace, synchronization, determinism, and numerical effects separately.\n\nCompare static and CLC-backed persistence with identical math, decomposition, tile/cluster shapes, grid, resources, and timing. Record CLC request results and per-worker work/time distribution. PTX ISA 9.0 requires `sm_100` or higher for CLC and explicitly lists SM120-family support for the cluster-wide multicast qualifier; the pinned CUTLASS 4.5.0 route used here is specifically its SM100 scheduler."}, "reason": {"statement": "Present static persistence as a baseline with its own final work distribution.", "urls": ["https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/tail-effect.md", "before": {"statement": "| [Tile scheduling](../techniques/tile-scheduling.md) | Raster order, swizzle patterns for better distribution |"}, "after": {"statement": "- A static persistent loop lets a resident CTA process multiple logical work items. Worker count is selected from problem decomposition, cluster/resource limits, and policy—not necessarily one CTA per physical SM. Finite work still has a final subset and may remain imbalanced.\n- Cluster Launch Control lets a selected thread request cancellation of an unspecified not-yet-started block or cluster and process the returned grid ID. CLC redistributes existing IDs; it cannot turn eight remaining independent tiles into 142 or 148 concurrent tiles.\n- Raster order and swizzle are coordinate transforms. Test them for locality while holding work acquisition fixed; they do not create work or guarantee balanced durations.\n- Stream-K or Split-K may create more independent partitions when tile-level work is insufficient. Evaluate reduction traffic, workspace, synchronization, determinism, and numerical effects separately.\n\nCompare static and CLC-backed persistence with identical math, decomposition, tile/cluster shapes, grid, resources, and timing. Record CLC request results and per-worker work/time distribution. PTX ISA 9.0 requires `sm_100` or higher for CLC and explicitly lists SM120-family support for the cluster-wide multicast qualifier; the pinned CUTLASS 4.5.0 route used here is specifically its SM100 scheduler."}, "reason": {"statement": "Separate locality ordering from acquisition and decomposition.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel"]}} +{"path": "wiki/patterns/tail-effect.md", "before": {"statement": "```\n// B200: 142 SMs\n// Problem: 150 tiles\n// Without CLC: 2 waves (142 + 8), last wave uses only 8 SMs (5.6%)\n// With CLC: single persistent wave, all 142 SMs stay busy\n//\n// Impact: 86% → 98% of cuBLAS (tcgen05 tutorial data)\n```"}, "after": {"statement": "For `T` equal-duration independent tiles and `W` available one-tile workers, with no K decomposition, write:\n\n```text\nT = qW + r, 0 <= r < W\n```\n\nThere are `q` full waves. If `r>0`, a final partial wave uses `r` workers and has instantaneous worker utilization `r/W`; if `r=0` and `T>0`, the final wave is full. For example, `T=150` and `W=142` gives one full wave plus eight tiles: the partial wave has `8/142 = 5.63%` worker utilization under these assumptions.\n\nThis is an analytical model, not a statement that a B200 has 142 SMs or that physical SM count always equals `W`. Block resources can make multiple blocks resident per SM, cluster shape changes scheduling granularity, application policies may restrict available SMs, and tile durations can differ. Measure the actual worker capacity and timeline.\n\nUnder the equal-duration model, the time fraction attributable to at most one partial wave shrinks as the number of full waves grows. There is no universal “below four times the SM count” cutoff: the remainder, wave duration, other phases, and imbalance determine significance.\n\nGau Nernst's Modal B200 has 148 SMs. In the author's `M=N=K=4096` experiment, v5 reports 1302.29 TFLOP/s (86.43% of cuBLAS) and v6 reports 1475.93 TFLOP/s (97.96%). The v6 change is static persistence plus output-pipeline/epilogue-role changes accumulated over earlier versions. The author explicitly did not add CLC and says overlap remains imperfect. Those results cannot be used as a CLC ablation or proof that all SMs stay busy."}, "reason": {"statement": "Use explicit hypothetical arithmetic separate from exact tutorial evidence.", "urls": ["https://gau-nernst.github.io/tcgen05/", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md", "https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v6.cu"]}} +{"path": "wiki/patterns/tail-effect.md", "before": {"statement": "- Only significant for moderate tile counts (< 4× SM count)"}, "after": {"statement": "For `T` equal-duration independent tiles and `W` available one-tile workers, with no K decomposition, write:\n\n```text\nT = qW + r, 0 <= r < W\n```\n\nThere are `q` full waves. If `r>0`, a final partial wave uses `r` workers and has instantaneous worker utilization `r/W`; if `r=0` and `T>0`, the final wave is full. For example, `T=150` and `W=142` gives one full wave plus eight tiles: the partial wave has `8/142 = 5.63%` worker utilization under these assumptions.\n\nThis is an analytical model, not a statement that a B200 has 142 SMs or that physical SM count always equals `W`. Block resources can make multiple blocks resident per SM, cluster shape changes scheduling granularity, application policies may restrict available SMs, and tile durations can differ. Measure the actual worker capacity and timeline.\n\nUnder the equal-duration model, the time fraction attributable to at most one partial wave shrinks as the number of full waves grows. There is no universal “below four times the SM count” cutoff: the remainder, wave duration, other phases, and imbalance determine significance."}, "reason": {"statement": "Give the analytical fractional bound under declared assumptions and measure real kernels.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/tail-effect.md", "before": {"statement": "- CLC only on SM100 datacenter"}, "after": {"statement": "- A static persistent loop lets a resident CTA process multiple logical work items. Worker count is selected from problem decomposition, cluster/resource limits, and policy—not necessarily one CTA per physical SM. Finite work still has a final subset and may remain imbalanced.\n- Cluster Launch Control lets a selected thread request cancellation of an unspecified not-yet-started block or cluster and process the returned grid ID. CLC redistributes existing IDs; it cannot turn eight remaining independent tiles into 142 or 148 concurrent tiles.\n- Raster order and swizzle are coordinate transforms. Test them for locality while holding work acquisition fixed; they do not create work or guarantee balanced durations.\n- Stream-K or Split-K may create more independent partitions when tile-level work is insufficient. Evaluate reduction traffic, workspace, synchronization, determinism, and numerical effects separately.\n\nCompare static and CLC-backed persistence with identical math, decomposition, tile/cluster shapes, grid, resources, and timing. Record CLC request results and per-worker work/time distribution. PTX ISA 9.0 requires `sm_100` or higher for CLC and explicitly lists SM120-family support for the cluster-wide multicast qualifier; the pinned CUTLASS 4.5.0 route used here is specifically its SM100 scheduler."}, "reason": {"statement": "Separate ISA compatibility from pinned library examples.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "MoE grouped GEMM shows uneven per-expert compute time. Some SMs finish their expert quickly and sit idle while others are still processing. Overall latency is dominated by the slowest expert."}, "after": {"statement": "Do not infer one expert per physical SM from a grouped-GEMM trace. CUDA assigns\nthread blocks to available SMs, while grouped kernels may split an expert into\nmultiple output tiles or let one resident worker process several logical tiles.\nMeasure at each relevant level:\n\n- routed tokens per expert for the exact batch and prefill/decode phase;\n- valid rows and output-tile counts per expert;\n- completed tiles and elapsed work per logical worker and, when instrumented,\n per SM;\n- dispatch, grouped-GEMM, combine, and end-to-end times per expert-parallel\n rank.\n\nSmall expert segments and partial output tiles can expose too little parallel\nwork or leave lanes predicated out. The effect depends on the kernel tile,\nother GEMM dimensions, resident-worker count, and competing implementation;\nthere is no universal `M < BLOCK_M` diagnosis or minimum viable size.\n\nUniform expected routing, a larger batch, or an auxiliary balancing loss may\nchange token-count skew, but none proves balanced tile counts, worker\ndurations, communication, or runtime. Treat imbalance as absent only when the\nmeasured distributions are narrow and a matched balancing variant does not\nmaterially improve the timed operation."}, "reason": {"statement": "Define imbalance across routing, logical work, worker time, and rank communication without assumed ownership.", "urls": ["https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/efficient_gemm.md", "https://www.lmsys.org/blog/2025-05-05-large-scale-ep/"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "1. **Skewed token distribution**: Router sends 80% of tokens to 20% of experts (common in trained MoE models)"}, "after": {"statement": "Do not infer one expert per physical SM from a grouped-GEMM trace. CUDA assigns\nthread blocks to available SMs, while grouped kernels may split an expert into\nmultiple output tiles or let one resident worker process several logical tiles.\nMeasure at each relevant level:\n\n- routed tokens per expert for the exact batch and prefill/decode phase;\n- valid rows and output-tile counts per expert;\n- completed tiles and elapsed work per logical worker and, when instrumented,\n per SM;\n- dispatch, grouped-GEMM, combine, and end-to-end times per expert-parallel\n rank.\n\nSmall expert segments and partial output tiles can expose too little parallel\nwork or leave lanes predicated out. The effect depends on the kernel tile,\nother GEMM dimensions, resident-worker count, and competing implementation;\nthere is no universal `M < BLOCK_M` diagnosis or minimum viable size.\n\nUniform expected routing, a larger batch, or an auxiliary balancing loss may\nchange token-count skew, but none proves balanced tile counts, worker\ndurations, communication, or runtime. Treat imbalance as absent only when the\nmeasured distributions are narrow and a matched balancing variant does not\nmaterially improve the timed operation."}, "reason": {"statement": "Require exact observed count distributions.", "urls": ["https://github.com/deepseek-ai/EPLB/blob/d52c72d5b2f2fb4c41afbf8eb21366820239913d/README.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/efficient_gemm.md", "https://www.lmsys.org/blog/2025-05-05-large-scale-ep/"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "2. **Static tile assignment**: Precomputed tile→SM mapping cannot rebalance at runtime"}, "after": {"statement": "Keep persistence, work acquisition, and decomposition as separate variables:\n\n1. A static persistent worker can advance through a deterministic logical-work\n sequence. CUDA still decides where its block runs; the rule is not a\n precomputed tile-to-physical-SM map.\n2. In a CLC-backed scheduler, a selected thread requests cancellation of an\n unspecified block or cluster that has not launched. A successful response\n returns that existing grid coordinate; a request can fail. CLC does not\n create tiles or make the fastest SM autonomously steal arbitrary work.\n3. The initial `blockIdx` in CUTLASS's pinned CLC scheduler is static and later\n requests are asynchronous, pipelined, and cluster-granular. There is no\n universal per-tile latency bound: compare request activity and end-to-end\n time against the matched static scheduler.\n4. Splitting a large expert or K range may expose more independent work, but it\n can add partial-result and reduction costs. Hold math, tile shape, cluster\n shape, launch resources, and output semantics constant in the comparison.\n\nPTX ISA 9.0 specifies CLC for `sm_100` or higher and explicitly includes\nSM120-family targets for the multicast form. CUTLASS 4.5.0's documented\n`PersistentTileSchedulerSm100` integration is a narrower library example, not\nthe complete ISA compatibility boundary."}, "reason": {"statement": "Separate logical assignment from physical placement.", "urls": ["https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "3. **Masked layout waste**: Fixed M_max per expert wastes compute on padding rows"}, "after": {"statement": "At pinned DeepGEMM commit\n[`891d57b4`](https://github.com/deepseek-ai/DeepGEMM/tree/891d57b4db1071624b5c8fa0d1e51cb317fa709f),\nthe three grouped interfaces have different axes and metadata:\n\n| M-grouped contiguous | Pack `A` and `D` along variable M with N/K fixed; identify groups by per-row expert IDs or per-group prefix-sum ends; segments are M-block aligned | Record valid rows, alignment padding, tile counts, and metadata form |\n| M-grouped masked | Allocate `[G, M_max, ...]`, pass one valid-M count per group, and compute valid portions; the fixed allocation is documented for a CUDA-graph decode case | Separate allocated rows from valid rows and inspect edge predication in generated code |\n| K-grouped contiguous | Pack variable K with M/N fixed for MoE weight backward | Do not use its K-axis contract to describe forward token imbalance |\n\nA fixed `M_max` allocation therefore does not establish that all padding rows\nare computed. Any residual edge-tile or predication cost needs generated-code\nand profile evidence for the selected kernel."}, "reason": {"statement": "Preserve graph-friendly allocation while removing false padding-compute attribution.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "| [CLC (Cluster Launch Control)](../hardware/clc.md) | Hardware dynamic tile assignment — fastest SMs grab more tiles |"}, "after": {"statement": "Keep persistence, work acquisition, and decomposition as separate variables:\n\n1. A static persistent worker can advance through a deterministic logical-work\n sequence. CUDA still decides where its block runs; the rule is not a\n precomputed tile-to-physical-SM map.\n2. In a CLC-backed scheduler, a selected thread requests cancellation of an\n unspecified block or cluster that has not launched. A successful response\n returns that existing grid coordinate; a request can fail. CLC does not\n create tiles or make the fastest SM autonomously steal arbitrary work.\n3. The initial `blockIdx` in CUTLASS's pinned CLC scheduler is static and later\n requests are asynchronous, pipelined, and cluster-granular. There is no\n universal per-tile latency bound: compare request activity and end-to-end\n time against the matched static scheduler.\n4. Splitting a large expert or K range may expose more independent work, but it\n can add partial-result and reduction costs. Hold math, tile shape, cluster\n shape, launch resources, and output semantics constant in the comparison.\n\nPTX ISA 9.0 specifies CLC for `sm_100` or higher and explicitly includes\nSM120-family targets for the multicast form. CUTLASS 4.5.0's documented\n`PersistentTileSchedulerSm100` integration is a narrower library example, not\nthe complete ISA compatibility boundary."}, "reason": {"statement": "State the exact reassignment protocol.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "| [Persistent kernels](../techniques/persistent-kernels.md) | Amortize launch overhead; loop over dynamic work queue |"}, "after": {"statement": "Keep persistence, work acquisition, and decomposition as separate variables:\n\n1. A static persistent worker can advance through a deterministic logical-work\n sequence. CUDA still decides where its block runs; the rule is not a\n precomputed tile-to-physical-SM map.\n2. In a CLC-backed scheduler, a selected thread requests cancellation of an\n unspecified block or cluster that has not launched. A successful response\n returns that existing grid coordinate; a request can fail. CLC does not\n create tiles or make the fastest SM autonomously steal arbitrary work.\n3. The initial `blockIdx` in CUTLASS's pinned CLC scheduler is static and later\n requests are asynchronous, pipelined, and cluster-granular. There is no\n universal per-tile latency bound: compare request activity and end-to-end\n time against the matched static scheduler.\n4. Splitting a large expert or K range may expose more independent work, but it\n can add partial-result and reduction costs. Hold math, tile shape, cluster\n shape, launch resources, and output semantics constant in the comparison.\n\nPTX ISA 9.0 specifies CLC for `sm_100` or higher and explicitly includes\nSM120-family targets for the multicast form. CUTLASS 4.5.0's documented\n`PersistentTileSchedulerSm100` integration is a narrower library example, not\nthe complete ISA compatibility boundary."}, "reason": {"statement": "Make persistence and acquisition policy independent choices.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "| [Contiguous layout](../kernels/grouped-gemm.md) | Pack variable-M experts sequentially; offsets array indexes expert boundaries |"}, "after": {"statement": "At pinned DeepGEMM commit\n[`891d57b4`](https://github.com/deepseek-ai/DeepGEMM/tree/891d57b4db1071624b5c8fa0d1e51cb317fa709f),\nthe three grouped interfaces have different axes and metadata:\n\n| M-grouped contiguous | Pack `A` and `D` along variable M with N/K fixed; identify groups by per-row expert IDs or per-group prefix-sum ends; segments are M-block aligned | Record valid rows, alignment padding, tile counts, and metadata form |\n| M-grouped masked | Allocate `[G, M_max, ...]`, pass one valid-M count per group, and compute valid portions; the fixed allocation is documented for a CUDA-graph decode case | Separate allocated rows from valid rows and inspect edge predication in generated code |\n| K-grouped contiguous | Pack variable K with M/N fixed for MoE weight backward | Do not use its K-axis contract to describe forward token imbalance |\n\nA fixed `M_max` allocation therefore does not establish that all padding rows\nare computed. Any residual edge-tile or predication cost needs generated-code\nand profile evidence for the selected kernel."}, "reason": {"statement": "Name both actual ABI forms.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "| [Masked layout](../kernels/grouped-gemm.md) | Good for CUDA graph capture; wastes compute on padding |"}, "after": {"statement": "At pinned DeepGEMM commit\n[`891d57b4`](https://github.com/deepseek-ai/DeepGEMM/tree/891d57b4db1071624b5c8fa0d1e51cb317fa709f),\nthe three grouped interfaces have different axes and metadata:\n\n| M-grouped contiguous | Pack `A` and `D` along variable M with N/K fixed; identify groups by per-row expert IDs or per-group prefix-sum ends; segments are M-block aligned | Record valid rows, alignment padding, tile counts, and metadata form |\n| M-grouped masked | Allocate `[G, M_max, ...]`, pass one valid-M count per group, and compute valid portions; the fixed allocation is documented for a CUDA-graph decode case | Separate allocated rows from valid rows and inspect edge predication in generated code |\n| K-grouped contiguous | Pack variable K with M/N fixed for MoE weight backward | Do not use its K-axis contract to describe forward token imbalance |\n\nA fixed `M_max` allocation therefore does not establish that all padding rows\nare computed. Any residual edge-tile or predication cost needs generated-code\nand profile evidence for the selected kernel."}, "reason": {"statement": "Retain graph scope and separate allocation from valid computation.", "urls": ["https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md", "https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "| [EPLB (Expert Parallel Load Balancer)](https://github.com/deepseek-ai/EPLB) | Replicate heavy experts across GPUs; 1.49x prefill speedup, 2.54x decode |"}, "after": {"statement": "[DeepSeek EPLB at commit\n`d52c72d`](https://github.com/deepseek-ai/EPLB/tree/d52c72d5b2f2fb4c41afbf8eb21366820239913d)\ntakes per-logical-expert load statistics, replicates heavily loaded logical\nexperts, and packs physical experts across configured GPUs and nodes. It is a\nhost-side expert-parallel placement planner, not a device-kernel tile\nscheduler; use it as a complement only when multi-GPU expert placement is in\nthe measured system scope.\n\nAn LMSYS/SGLang study on a 96-H100 deployment reported `1.49x` prefill and\n`2.54x` decode throughput speedups in its large-scale EPLB ablation. The same\nstudy says it used in-distribution data and that production distribution\nshifts require further testing. Those figures are scoped results, not generic\nEPLB speedups."}, "reason": {"statement": "Scope placement mechanism and measurement separately.", "urls": ["https://www.lmsys.org/blog/2025-05-05-large-scale-ep/", "https://github.com/deepseek-ai/EPLB/blob/d52c72d5b2f2fb4c41afbf8eb21366820239913d/eplb.py"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "This highlighted that even careful tile scheduling can be outrun by algorithmic restructuring — and prompted the MLSys 2026 FlashInfer contest to add runtime isolation + subprocess eval."}, "after": {"statement": "GPU Mode's official postmortem records a temporarily first-place submission\nthat combined a real grouped-GEMM kernel with a timing-harness exploit. The\ncorrectness path ran a padded eight-group computation on each of 15 cloned\nobjects. During timing, the first call merged them into one 120-group launch,\ncalls 2 through 15 returned cached output pointers, and the harness divided the\ncombined timing by 15.\n\nThis is evidence about evaluator state reuse, not a valid load-balancing\nperformance result. The postmortem identifies `gpu-mode/reference-kernels`\nPR 104 as the harness response; neither that record nor the pinned FlashInfer\nMLSys 2026 evaluation contract establishes a causal link between this incident\nand the later contest design."}, "reason": {"statement": "Preserve the verified incident mechanics without inventing historical causality.", "urls": ["https://www.gpumode.com/news/reward-hacking-nvfp4", "https://github.com/flashinfer-ai/flashinfer-bench-starter-kit/blob/75ccd05cafceb0fd1f86be4cd0f2117249463c66/EVALUATION.md"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "- CLC only available on SM100 datacenter (not SM120 consumer)"}, "after": {"statement": "Keep persistence, work acquisition, and decomposition as separate variables:\n\n1. A static persistent worker can advance through a deterministic logical-work\n sequence. CUDA still decides where its block runs; the rule is not a\n precomputed tile-to-physical-SM map.\n2. In a CLC-backed scheduler, a selected thread requests cancellation of an\n unspecified block or cluster that has not launched. A successful response\n returns that existing grid coordinate; a request can fail. CLC does not\n create tiles or make the fastest SM autonomously steal arbitrary work.\n3. The initial `blockIdx` in CUTLASS's pinned CLC scheduler is static and later\n requests are asynchronous, pipelined, and cluster-granular. There is no\n universal per-tile latency bound: compare request activity and end-to-end\n time against the matched static scheduler.\n4. Splitting a large expert or K range may expose more independent work, but it\n can add partial-result and reduction costs. Hold math, tile shape, cluster\n shape, launch resources, and output semantics constant in the comparison.\n\nPTX ISA 9.0 specifies CLC for `sm_100` or higher and explicitly includes\nSM120-family targets for the multicast form. CUTLASS 4.5.0's documented\n`PersistentTileSchedulerSm100` integration is a narrower library example, not\nthe complete ISA compatibility boundary."}, "reason": {"statement": "Separate PTX compatibility from a particular library integration.", "urls": ["https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel", "https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "- Dynamic scheduling has small per-tile overhead vs static precomputed"}, "after": {"statement": "Keep persistence, work acquisition, and decomposition as separate variables:\n\n1. A static persistent worker can advance through a deterministic logical-work\n sequence. CUDA still decides where its block runs; the rule is not a\n precomputed tile-to-physical-SM map.\n2. In a CLC-backed scheduler, a selected thread requests cancellation of an\n unspecified block or cluster that has not launched. A successful response\n returns that existing grid coordinate; a request can fail. CLC does not\n create tiles or make the fastest SM autonomously steal arbitrary work.\n3. The initial `blockIdx` in CUTLASS's pinned CLC scheduler is static and later\n requests are asynchronous, pipelined, and cluster-granular. There is no\n universal per-tile latency bound: compare request activity and end-to-end\n time against the matched static scheduler.\n4. Splitting a large expert or K range may expose more independent work, but it\n can add partial-result and reduction costs. Hold math, tile shape, cluster\n shape, launch resources, and output semantics constant in the comparison.\n\nPTX ISA 9.0 specifies CLC for `sm_100` or higher and explicitly includes\nSM120-family targets for the multicast form. CUTLASS 4.5.0's documented\n`PersistentTileSchedulerSm100` integration is a narrower library example, not\nthe complete ISA compatibility boundary."}, "reason": {"statement": "Require matched measurements of request activity and latency.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "- Small experts may not benefit — minimum viable tile size is a floor"}, "after": {"statement": "Do not infer one expert per physical SM from a grouped-GEMM trace. CUDA assigns\nthread blocks to available SMs, while grouped kernels may split an expert into\nmultiple output tiles or let one resident worker process several logical tiles.\nMeasure at each relevant level:\n\n- routed tokens per expert for the exact batch and prefill/decode phase;\n- valid rows and output-tile counts per expert;\n- completed tiles and elapsed work per logical worker and, when instrumented,\n per SM;\n- dispatch, grouped-GEMM, combine, and end-to-end times per expert-parallel\n rank.\n\nSmall expert segments and partial output tiles can expose too little parallel\nwork or leave lanes predicated out. The effect depends on the kernel tile,\nother GEMM dimensions, resident-worker count, and competing implementation;\nthere is no universal `M < BLOCK_M` diagnosis or minimum viable size.\n\nUniform expected routing, a larger batch, or an auxiliary balancing loss may\nchange token-count skew, but none proves balanced tile counts, worker\ndurations, communication, or runtime. Treat imbalance as absent only when the\nmeasured distributions are narrow and a matched balancing variant does not\nmaterially improve the timed operation."}, "reason": {"statement": "Make small-M a measured risk rather than a fixed cutoff.", "urls": ["https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/efficient_gemm.md", "https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://www.lmsys.org/blog/2025-05-05-large-scale-ep/"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "- EPLB works at cluster scale, not single-device"}, "after": {"statement": "[DeepSeek EPLB at commit\n`d52c72d`](https://github.com/deepseek-ai/EPLB/tree/d52c72d5b2f2fb4c41afbf8eb21366820239913d)\ntakes per-logical-expert load statistics, replicates heavily loaded logical\nexperts, and packs physical experts across configured GPUs and nodes. It is a\nhost-side expert-parallel placement planner, not a device-kernel tile\nscheduler; use it as a complement only when multi-GPU expert placement is in\nthe measured system scope.\n\nAn LMSYS/SGLang study on a 96-H100 deployment reported `1.49x` prefill and\n`2.54x` decode throughput speedups in its large-scale EPLB ablation. The same\nstudy says it used in-distribution data and that production distribution\nshifts require further testing. Those figures are scoped results, not generic\nEPLB speedups."}, "reason": {"statement": "State intended multi-GPU placement scope without a false scale dichotomy.", "urls": ["https://github.com/deepseek-ai/EPLB/blob/d52c72d5b2f2fb4c41afbf8eb21366820239913d/eplb.py", "https://www.lmsys.org/blog/2025-05-05-large-scale-ep/"]}} +{"path": "wiki/patterns/moe-load-imbalance.md", "before": {"statement": "- Uniform routing (rare in practice)\n- Very large batch sizes (statistics average out)\n- Training with auxiliary load balancing loss"}, "after": {"statement": "Do not infer one expert per physical SM from a grouped-GEMM trace. CUDA assigns\nthread blocks to available SMs, while grouped kernels may split an expert into\nmultiple output tiles or let one resident worker process several logical tiles.\nMeasure at each relevant level:\n\n- routed tokens per expert for the exact batch and prefill/decode phase;\n- valid rows and output-tile counts per expert;\n- completed tiles and elapsed work per logical worker and, when instrumented,\n per SM;\n- dispatch, grouped-GEMM, combine, and end-to-end times per expert-parallel\n rank.\n\nSmall expert segments and partial output tiles can expose too little parallel\nwork or leave lanes predicated out. The effect depends on the kernel tile,\nother GEMM dimensions, resident-worker count, and competing implementation;\nthere is no universal `M < BLOCK_M` diagnosis or minimum viable size.\n\nUniform expected routing, a larger batch, or an auxiliary balancing loss may\nchange token-count skew, but none proves balanced tile counts, worker\ndurations, communication, or runtime. Treat imbalance as absent only when the\nmeasured distributions are narrow and a matched balancing variant does not\nmaterially improve the timed operation."}, "reason": {"statement": "Replace proxies with an operational measurement criterion.", "urls": ["https://www.lmsys.org/blog/2025-05-05-large-scale-ep/", "https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html", "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/efficient_gemm.md"]}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "Sparse Multi-head Latent Attention introduced in DeepSeek V3.2. Two-stage pipeline: (1) Lightning Indexer selects top-K tokens per query via FP8 scorer, (2) MLA runs only over selected tokens. This reduces decode attention compute from O(seqlen) to O(topk=2048) tokens, critical for long-context serving."}, "after": {"statement": "DeepSeek-V3.2-Exp introduces **DeepSeek Sparse Attention (DSA)**. Its\nfirst-party report defines two components:\n\n1. The lightning indexer computes one score for every query/preceding-token\n pair. A score is a weighted sum across indexer heads of a ReLU-applied query\n and key dot product.\n2. Fine-grained token selection retains the KV entries at the top-k index\n scores and applies the main attention only to that selected set.\n\nThe released `config_671B_v3.2.json` uses 64 indexer heads of dimension 128 and\n`index_topk=2048`. DSA is instantiated under MLA's MQA mode: the selected MLA\nlatent entry is shared across the query heads. The model has 128 MLA query\nheads, a 512-dimensional latent KV component, and a 64-dimensional RoPE\ncomponent; a smaller local head count is a parallel-sharding choice rather than\nthe architecture-wide contract.\n\nFor a length-L sequence and fixed selected count k, the report reduces the\n**main/core attention** complexity from O(L squared) to O(Lk). The lightning\nindexer still scores the preceding context and remains O(L squared) over the\nsequence. For decode, measure both the O(L) selector scan for each new query and\nthe O(k) selected-attention work; do not describe the full pipeline as O(k)."}, "reason": {"statement": "Separate selector and selected-attention complexity.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "```\nQuery q_t (new token embedding)\n │\n ▼\n┌────────────────────────┐\n│ Lightning Indexer │ FP8 scorer, per-query top-K selection\n│ - FP8 KV cache │ h64, d128, topk=2048, page_size=64\n│ - Compute q·k_i scores │\n│ - Select top-2048 i │\n└────────────────────────┘\n │ selected_indices [2048]\n ▼\n┌────────────────────────┐\n│ Sparse MLA │ Standard MLA but only over selected\n│ - Gather selected K,V │ h16, ckv512, kpe64, topk=2048\n│ - Attention compute │\n│ - Output y_t │\n└────────────────────────┘\n```"}, "after": {"statement": "DeepSeek-V3.2-Exp introduces **DeepSeek Sparse Attention (DSA)**. Its\nfirst-party report defines two components:\n\n1. The lightning indexer computes one score for every query/preceding-token\n pair. A score is a weighted sum across indexer heads of a ReLU-applied query\n and key dot product.\n2. Fine-grained token selection retains the KV entries at the top-k index\n scores and applies the main attention only to that selected set.\n\nThe released `config_671B_v3.2.json` uses 64 indexer heads of dimension 128 and\n`index_topk=2048`. DSA is instantiated under MLA's MQA mode: the selected MLA\nlatent entry is shared across the query heads. The model has 128 MLA query\nheads, a 512-dimensional latent KV component, and a 64-dimensional RoPE\ncomponent; a smaller local head count is a parallel-sharding choice rather than\nthe architecture-wide contract.\n\nFor a length-L sequence and fixed selected count k, the report reduces the\n**main/core attention** complexity from O(L squared) to O(Lk). The lightning\nindexer still scores the preceding context and remains O(L squared) over the\nsequence. For decode, measure both the O(L) selector scan for each new query and\nthe O(k) selected-attention work; do not describe the full pipeline as O(k).\n\nThe released high-performance path is not one fused “indexer plus sparse MLA”\nkernel:\n\n- DeepGEMM provides non-paged and paged indexer-logit kernels. Its pinned SM100\n FP8 path computes token logits from FP8 query/key inputs, per-token key\n scales, and per-query head weights; top-k selection remains a separate\n operation.\n- FlashMLA sparse attention consumes caller-produced token indices. It does not\n run the lightning indexer or top-k selector.\n\nAt FlashMLA commit\n[`71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232),\nprefill and decode have different contracts:\n\n| Sparse decode | `q[batch,s_q,h_q,576]`; paged `k_cache`; `indices[batch,s_q,topk]`, where each nonnegative value encodes physical page times page size plus token offset; `-1` is invalid | V3-family sparse mode dequantizes its FP8 cache for BF16 attention and returns BF16 `out` plus FP32 `lse` |\n| Sparse prefill | Unbatched BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and INT32 `indices[s_q,h_kv,topk]`; the documented equivalence requires `h_kv=1`; negative or at-least-`s_kv` entries are invalid | Computes attention over gathered token rows and returns BF16 `out`, FP32 `max_logits`, and FP32 `lse` |\n\nThese are token indices, not one maximum or one selection per cache block.\nThe sparse-decode API accepts page size through the cache tensor; pinned\ncorrectness tests exercise multiple values including 2, 53, 61, 64, 69, 256,\nand 576. Page size 64 is therefore a deployment configuration, not a universal\nFlashMLA requirement."}, "reason": {"statement": "Replace invented deployment structure with paper equations and exact public API boundaries.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "Each KV cache entry is 656 bytes:\n- 512 bytes: FP8 compressed KV data\n- 16 bytes: FP32 per-block scale factors\n- 128 bytes: BF16 RoPE embeddings (for indexer positional encoding)\n\nBlock size fixed at 64 (FlashMLA requirement)."}, "after": {"statement": "Only the V3/V3.1/V3.2 **FP8 sparse-decode** mode has the documented 656-byte\nper-token layout:\n\n- 512 E4M3 NoPE values: 512 bytes;\n- four FP32 scales, one for each successive group of 128 NoPE values: 16 bytes;\n- 64 BF16 RoPE values used by the attention key: 128 bytes.\n\nThe indexer has a separate FP8 K cache and scale cache in the released model.\nThe 656-byte attention entry is not an indexer cache and is not the layout of\nevery dense, sparse-prefill, or non-V3 FlashMLA mode."}, "reason": {"statement": "Scope the byte layout and make page size an explicit interface dimension.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "```cuda\n// Score each KV block against query using FP8 block-scale MMA\n// Reduce to per-block max, then top-K selection across blocks\n\n__global__ void lightning_indexer_kernel(\n const fp8_t* q_fp8, // [h, d] query (FP8 quantized)\n const fp8_t* kv_cache_fp8, // [num_blocks, 64, d] paged\n const fp8_t* kv_scales,\n float* scores_out, // [num_blocks] per-block max score\n int num_blocks\n) {\n // Each threadblock handles one KV block's score\n uint32_t tmem = tmem_alloc(64);\n tcgen05_mma_f8(q_smem, k_block_smem, tmem);\n // Reduce inside block to max score\n // Write per-block score\n}\n\n// Separate top-K selection kernel across the num_blocks score array\n```"}, "after": {"statement": "DeepSeek-V3.2-Exp introduces **DeepSeek Sparse Attention (DSA)**. Its\nfirst-party report defines two components:\n\n1. The lightning indexer computes one score for every query/preceding-token\n pair. A score is a weighted sum across indexer heads of a ReLU-applied query\n and key dot product.\n2. Fine-grained token selection retains the KV entries at the top-k index\n scores and applies the main attention only to that selected set.\n\nThe released `config_671B_v3.2.json` uses 64 indexer heads of dimension 128 and\n`index_topk=2048`. DSA is instantiated under MLA's MQA mode: the selected MLA\nlatent entry is shared across the query heads. The model has 128 MLA query\nheads, a 512-dimensional latent KV component, and a 64-dimensional RoPE\ncomponent; a smaller local head count is a parallel-sharding choice rather than\nthe architecture-wide contract.\n\nFor a length-L sequence and fixed selected count k, the report reduces the\n**main/core attention** complexity from O(L squared) to O(Lk). The lightning\nindexer still scores the preceding context and remains O(L squared) over the\nsequence. For decode, measure both the O(L) selector scan for each new query and\nthe O(k) selected-attention work; do not describe the full pipeline as O(k).\n\nThe released high-performance path is not one fused “indexer plus sparse MLA”\nkernel:\n\n- DeepGEMM provides non-paged and paged indexer-logit kernels. Its pinned SM100\n FP8 path computes token logits from FP8 query/key inputs, per-token key\n scales, and per-query head weights; top-k selection remains a separate\n operation.\n- FlashMLA sparse attention consumes caller-produced token indices. It does not\n run the lightning indexer or top-k selector.\n\nAt FlashMLA commit\n[`71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232),\nprefill and decode have different contracts:\n\n| Sparse decode | `q[batch,s_q,h_q,576]`; paged `k_cache`; `indices[batch,s_q,topk]`, where each nonnegative value encodes physical page times page size plus token offset; `-1` is invalid | V3-family sparse mode dequantizes its FP8 cache for BF16 attention and returns BF16 `out` plus FP32 `lse` |\n| Sparse prefill | Unbatched BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and INT32 `indices[s_q,h_kv,topk]`; the documented equivalence requires `h_kv=1`; negative or at-least-`s_kv` entries are invalid | Computes attention over gathered token rows and returns BF16 `out`, FP32 `max_logits`, and FP32 `lse` |\n\nThese are token indices, not one maximum or one selection per cache block.\nThe sparse-decode API accepts page size through the cache tensor; pinned\ncorrectness tests exercise multiple values including 2, 53, 61, 64, 69, 256,\nand 576. Page size 64 is therefore a deployment configuration, not a universal\nFlashMLA requirement."}, "reason": {"statement": "The snippet is not upstream code and is semantically misleading.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "```cuda\n// After top-K selection gives indices, gather K,V from paged cache\n// Then run standard MLA on the gathered subset\n\n__global__ void sparse_mla_decode_kernel(\n const int* topk_indices, // [2048] selected block indices\n const fp8_t* kv_cache, // paged KV (656 bytes/token)\n const half* q, // [16, 576] MLA query\n half* output\n) {\n // Load q into registers/SMEM\n // For each selected block:\n // gather K,V block (FP8) → dequant to BF16 → MMA\n // Online softmax accumulation\n // Final weighted sum\n}\n```"}, "after": {"statement": "The released high-performance path is not one fused “indexer plus sparse MLA”\nkernel:\n\n- DeepGEMM provides non-paged and paged indexer-logit kernels. Its pinned SM100\n FP8 path computes token logits from FP8 query/key inputs, per-token key\n scales, and per-query head weights; top-k selection remains a separate\n operation.\n- FlashMLA sparse attention consumes caller-produced token indices. It does not\n run the lightning indexer or top-k selector.\n\nAt FlashMLA commit\n[`71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232),\nprefill and decode have different contracts:\n\n| Sparse decode | `q[batch,s_q,h_q,576]`; paged `k_cache`; `indices[batch,s_q,topk]`, where each nonnegative value encodes physical page times page size plus token offset; `-1` is invalid | V3-family sparse mode dequantizes its FP8 cache for BF16 attention and returns BF16 `out` plus FP32 `lse` |\n| Sparse prefill | Unbatched BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and INT32 `indices[s_q,h_kv,topk]`; the documented equivalence requires `h_kv=1`; negative or at-least-`s_kv` entries are invalid | Computes attention over gathered token rows and returns BF16 `out`, FP32 `max_logits`, and FP32 `lse` |\n\nThese are token indices, not one maximum or one selection per cache block.\nThe sparse-decode API accepts page size through the cache tensor; pinned\ncorrectness tests exercise multiple values including 2, 53, 61, 64, 69, 256,\nand 576. Page size 64 is therefore a deployment configuration, not a universal\nFlashMLA requirement."}, "reason": {"statement": "Use the exact public contract instead of invented CUDA.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "| Dense MLA decode | H800 | 660 (BF16) | 3000 GB/s, compute-bound |"}, "after": {"statement": "FlashMLA's pinned README reports the following maxima. They are useful source\nclaims, not reproducible benchmark tuples: the README does not provide complete\nshapes, timed regions, repetitions, samples, or variance.\n\n| Dense MLA decode, memory-bound configuration | H800 SXM5, CUDA 12.8 | Up to 3000 GB/s with BF16 cache |\n| Dense MLA decode, compute-bound configuration | H800 SXM5, CUDA 12.8 | Up to 660 TFLOPS with BF16 cache; separate from the 3000-GB/s case |\n| Sparse MLA decode | H800 SXM5, CUDA 12.8 | 410 TFLOPS; FP8 KV storage and BF16 matrix multiplication |\n| Sparse MLA decode | B200 | Up to 350 TFLOPS; the source says this path was not really optimized and gives no bandwidth-causality result |\n| Sparse MLA prefill | H800 SXM5, CUDA 12.8 | Up to 640 TFLOPS forward with BF16 Q/KV |\n| Sparse MLA prefill | B200, CUDA 12.9 | Up to 1450 TFLOPS forward with BF16 Q/KV |\n\nThe same README separately reports NVIDIA's dense **MHA** prefill maxima of\n1460 TFLOPS forward and 1000 TFLOPS backward on B200. Those values are not a\ndense-MLA baseline matched to the sparse-prefill result, so numerical proximity\nbetween 1450 and 1460 does not establish equivalent performance."}, "reason": {"statement": "Report the maxima as separate author-reported regimes.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "| Sparse MLA decode | H800 | 410 (FP8) | Token-level sparsity |"}, "after": {"statement": "FlashMLA's pinned README reports the following maxima. They are useful source\nclaims, not reproducible benchmark tuples: the README does not provide complete\nshapes, timed regions, repetitions, samples, or variance.\n\n| Dense MLA decode, memory-bound configuration | H800 SXM5, CUDA 12.8 | Up to 3000 GB/s with BF16 cache |\n| Dense MLA decode, compute-bound configuration | H800 SXM5, CUDA 12.8 | Up to 660 TFLOPS with BF16 cache; separate from the 3000-GB/s case |\n| Sparse MLA decode | H800 SXM5, CUDA 12.8 | 410 TFLOPS; FP8 KV storage and BF16 matrix multiplication |\n| Sparse MLA decode | B200 | Up to 350 TFLOPS; the source says this path was not really optimized and gives no bandwidth-causality result |\n| Sparse MLA prefill | H800 SXM5, CUDA 12.8 | Up to 640 TFLOPS forward with BF16 Q/KV |\n| Sparse MLA prefill | B200, CUDA 12.9 | Up to 1450 TFLOPS forward with BF16 Q/KV |\n\nThe same README separately reports NVIDIA's dense **MHA** prefill maxima of\n1460 TFLOPS forward and 1000 TFLOPS backward on B200. Those values are not a\ndense-MLA baseline matched to the sparse-prefill result, so numerical proximity\nbetween 1450 and 1460 does not establish equivalent performance."}, "reason": {"statement": "Separate storage and compute dtypes and retain source scope.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "| Sparse MLA decode | B200 | 350 (FP8) | Lower because bandwidth dominates decode |"}, "after": {"statement": "FlashMLA's pinned README reports the following maxima. They are useful source\nclaims, not reproducible benchmark tuples: the README does not provide complete\nshapes, timed regions, repetitions, samples, or variance.\n\n| Dense MLA decode, memory-bound configuration | H800 SXM5, CUDA 12.8 | Up to 3000 GB/s with BF16 cache |\n| Dense MLA decode, compute-bound configuration | H800 SXM5, CUDA 12.8 | Up to 660 TFLOPS with BF16 cache; separate from the 3000-GB/s case |\n| Sparse MLA decode | H800 SXM5, CUDA 12.8 | 410 TFLOPS; FP8 KV storage and BF16 matrix multiplication |\n| Sparse MLA decode | B200 | Up to 350 TFLOPS; the source says this path was not really optimized and gives no bandwidth-causality result |\n| Sparse MLA prefill | H800 SXM5, CUDA 12.8 | Up to 640 TFLOPS forward with BF16 Q/KV |\n| Sparse MLA prefill | B200, CUDA 12.9 | Up to 1450 TFLOPS forward with BF16 Q/KV |\n\nThe same README separately reports NVIDIA's dense **MHA** prefill maxima of\n1460 TFLOPS forward and 1000 TFLOPS backward on B200. Those values are not a\ndense-MLA baseline matched to the sparse-prefill result, so numerical proximity\nbetween 1450 and 1460 does not establish equivalent performance."}, "reason": {"statement": "Retain only the scoped author report and explicit unoptimized caveat.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "| Dense prefill | B200 | 1460 (BF16) | tcgen05 peak |"}, "after": {"statement": "FlashMLA's pinned README reports the following maxima. They are useful source\nclaims, not reproducible benchmark tuples: the README does not provide complete\nshapes, timed regions, repetitions, samples, or variance.\n\n| Dense MLA decode, memory-bound configuration | H800 SXM5, CUDA 12.8 | Up to 3000 GB/s with BF16 cache |\n| Dense MLA decode, compute-bound configuration | H800 SXM5, CUDA 12.8 | Up to 660 TFLOPS with BF16 cache; separate from the 3000-GB/s case |\n| Sparse MLA decode | H800 SXM5, CUDA 12.8 | 410 TFLOPS; FP8 KV storage and BF16 matrix multiplication |\n| Sparse MLA decode | B200 | Up to 350 TFLOPS; the source says this path was not really optimized and gives no bandwidth-causality result |\n| Sparse MLA prefill | H800 SXM5, CUDA 12.8 | Up to 640 TFLOPS forward with BF16 Q/KV |\n| Sparse MLA prefill | B200, CUDA 12.9 | Up to 1450 TFLOPS forward with BF16 Q/KV |\n\nThe same README separately reports NVIDIA's dense **MHA** prefill maxima of\n1460 TFLOPS forward and 1000 TFLOPS backward on B200. Those values are not a\ndense-MLA baseline matched to the sparse-prefill result, so numerical proximity\nbetween 1450 and 1460 does not establish equivalent performance."}, "reason": {"statement": "Name the correct operator and attribution.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "| Sparse prefill | B200 | 1450 (FP8) | FP8 sparse matches BF16 dense |"}, "after": {"statement": "FlashMLA's pinned README reports the following maxima. They are useful source\nclaims, not reproducible benchmark tuples: the README does not provide complete\nshapes, timed regions, repetitions, samples, or variance.\n\n| Dense MLA decode, memory-bound configuration | H800 SXM5, CUDA 12.8 | Up to 3000 GB/s with BF16 cache |\n| Dense MLA decode, compute-bound configuration | H800 SXM5, CUDA 12.8 | Up to 660 TFLOPS with BF16 cache; separate from the 3000-GB/s case |\n| Sparse MLA decode | H800 SXM5, CUDA 12.8 | 410 TFLOPS; FP8 KV storage and BF16 matrix multiplication |\n| Sparse MLA decode | B200 | Up to 350 TFLOPS; the source says this path was not really optimized and gives no bandwidth-causality result |\n| Sparse MLA prefill | H800 SXM5, CUDA 12.8 | Up to 640 TFLOPS forward with BF16 Q/KV |\n| Sparse MLA prefill | B200, CUDA 12.9 | Up to 1450 TFLOPS forward with BF16 Q/KV |\n\nThe same README separately reports NVIDIA's dense **MHA** prefill maxima of\n1460 TFLOPS forward and 1000 TFLOPS backward on B200. Those values are not a\ndense-MLA baseline matched to the sparse-prefill result, so numerical proximity\nbetween 1450 and 1460 does not establish equivalent performance."}, "reason": {"statement": "Report the value only with its dtype/environment/source limitations.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "- Long-context LLM serving (32K+)"}, "after": {"statement": "Use this path directly for DeepSeek-V3.2-Exp, or for another model only after\nits query dimensions, latent/RoPE layout, cache format, head relationships,\nindex encoding, invalid-entry rules, and output semantics match the chosen\nFlashMLA interface.\n\nFor a target deployment:\n\n1. Compare index scores and selected token sets against the released model\n equation and a dense reference, including causal masking and the indexer's\n non-interleaved RoPE layout.\n2. Compare sparse prefill/decode outputs and LSE values with the pinned\n FlashMLA reference for identical selected indices, including invalid and\n partially filled top-k cases.\n3. Time indexer logits, top-k selection, sparse attention, and the complete\n pipeline separately across context lengths, query batch sizes, page sizes,\n and selected counts. Use a matched dense-attention baseline and report\n synchronization, warmup, repeated trials, statistic, and variation.\n\nThere is no verified universal 32K crossover. The relevant threshold is where\nthe measured selector-plus-sparse-attention pipeline improves the target's\nend-to-end latency or cost without violating its accuracy criterion."}, "reason": {"statement": "Replace threshold advice with measured selector-plus-attention crossover.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "- DeepSeek V3.2 and similar MLA architectures"}, "after": {"statement": "Use this path directly for DeepSeek-V3.2-Exp, or for another model only after\nits query dimensions, latent/RoPE layout, cache format, head relationships,\nindex encoding, invalid-entry rules, and output semantics match the chosen\nFlashMLA interface.\n\nFor a target deployment:\n\n1. Compare index scores and selected token sets against the released model\n equation and a dense reference, including causal masking and the indexer's\n non-interleaved RoPE layout.\n2. Compare sparse prefill/decode outputs and LSE values with the pinned\n FlashMLA reference for identical selected indices, including invalid and\n partially filled top-k cases.\n3. Time indexer logits, top-k selection, sparse attention, and the complete\n pipeline separately across context lengths, query batch sizes, page sizes,\n and selected counts. Use a matched dense-attention baseline and report\n synchronization, warmup, repeated trials, statistic, and variation.\n\nThere is no verified universal 32K crossover. The relevant threshold is where\nthe measured selector-plus-sparse-attention pipeline improves the target's\nend-to-end latency or cost without violating its accuracy criterion."}, "reason": {"statement": "Make compatibility checklist-based.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "performance_claims:\n - gpu: B200\n dtype: fp8\n shape: \"sparse prefill, seqlen=32k, topk=2048\"\n metric: TFLOPS\n value: 1450\n utilization: \"FP8 sparse compute bound\"\n source_id: blog-flashmla"}, "after": {"statement": "performance_claims: []\n\nFlashMLA's pinned README reports the following maxima. They are useful source\nclaims, not reproducible benchmark tuples: the README does not provide complete\nshapes, timed regions, repetitions, samples, or variance.\n\n| Dense MLA decode, memory-bound configuration | H800 SXM5, CUDA 12.8 | Up to 3000 GB/s with BF16 cache |\n| Dense MLA decode, compute-bound configuration | H800 SXM5, CUDA 12.8 | Up to 660 TFLOPS with BF16 cache; separate from the 3000-GB/s case |\n| Sparse MLA decode | H800 SXM5, CUDA 12.8 | 410 TFLOPS; FP8 KV storage and BF16 matrix multiplication |\n| Sparse MLA decode | B200 | Up to 350 TFLOPS; the source says this path was not really optimized and gives no bandwidth-causality result |\n| Sparse MLA prefill | H800 SXM5, CUDA 12.8 | Up to 640 TFLOPS forward with BF16 Q/KV |\n| Sparse MLA prefill | B200, CUDA 12.9 | Up to 1450 TFLOPS forward with BF16 Q/KV |\n\nThe same README separately reports NVIDIA's dense **MHA** prefill maxima of\n1460 TFLOPS forward and 1000 TFLOPS backward on B200. Those values are not a\ndense-MLA baseline matched to the sparse-prefill result, so numerical proximity\nbetween 1450 and 1460 does not establish equivalent performance."}, "reason": {"statement": "Do not encode an incomplete author maximum as a structured benchmark claim.", "urls": []}} +{"path": "wiki/kernels/sparse-mla.md", "before": {"statement": "Sparse Multi-head Latent Attention introduced in DeepSeek V3.2. Two-stage pipeline: (1) Lightning Indexer selects top-K tokens per query via FP8 scorer, (2) MLA runs only over selected tokens. This reduces decode attention compute from O(seqlen) to O(topk=2048) tokens, critical for long-context serving."}, "after": {"statement": "The released high-performance path is not one fused “indexer plus sparse MLA”\nkernel:\n\n- DeepGEMM provides non-paged and paged indexer-logit kernels. Its pinned SM100\n FP8 path computes token logits from FP8 query/key inputs, per-token key\n scales, and per-query head weights; top-k selection remains a separate\n operation.\n- FlashMLA sparse attention consumes caller-produced token indices. It does not\n run the lightning indexer or top-k selector.\n\nAt FlashMLA commit\n[`71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232),\nprefill and decode have different contracts:\n\n| Sparse decode | `q[batch,s_q,h_q,576]`; paged `k_cache`; `indices[batch,s_q,topk]`, where each nonnegative value encodes physical page times page size plus token offset; `-1` is invalid | V3-family sparse mode dequantizes its FP8 cache for BF16 attention and returns BF16 `out` plus FP32 `lse` |\n| Sparse prefill | Unbatched BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and INT32 `indices[s_q,h_kv,topk]`; the documented equivalence requires `h_kv=1`; negative or at-least-`s_kv` entries are invalid | Computes attention over gathered token rows and returns BF16 `out`, FP32 `max_logits`, and FP32 `lse` |\n\nThese are token indices, not one maximum or one selection per cache block.\nThe sparse-decode API accepts page size through the cache tensor; pinned\ncorrectness tests exercise multiple values including 2, 53, 61, 64, 69, 256,\nand 576. Page size 64 is therefore a deployment configuration, not a universal\nFlashMLA requirement.\n\nOnly the V3/V3.1/V3.2 **FP8 sparse-decode** mode has the documented 656-byte\nper-token layout:\n\n- 512 E4M3 NoPE values: 512 bytes;\n- four FP32 scales, one for each successive group of 128 NoPE values: 16 bytes;\n- 64 BF16 RoPE values used by the attention key: 128 bytes.\n\nThe indexer has a separate FP8 K cache and scale cache in the released model.\nThe 656-byte attention entry is not an indexer cache and is not the layout of\nevery dense, sparse-prefill, or non-V3 FlashMLA mode."}, "reason": {"statement": "State separate SM100 indexer and attention implementations with their actual precisions.", "urls": []}} +{"path": "wiki/kernels/tensorrt-llm-blackwell-indexer.md", "before": {"statement": "```cuda\n// Evidence checklist before adapting the idea:\n// 1. Inspect indexerKCacheGather.cu and indexerKCacheScatter.cu.\n// 2. Check the scale and FP4 packing layout.\n// 3. Benchmark gather/scatter separately from top-k selection.\n__global__ void candidate_indexer_probe(const uint8_t* cache, int* indices) {\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n indices[tid] = static_cast(cache[tid]);\n}\n```"}, "after": {"statement": "For the fixed 128-value indexer head in this path, one row has:\n\n| Input | BF16 positional values followed by BF16 non-positional values | 256 before quantization |\n| Packed payload | Two FP4 E2M1 codes per byte | 64 |\n| Scale word | Four UE8M0 exponent bytes, one per successive group of 32 values, packed little-endian into one `int32` | 4 |\n| Cache footprint | Packed payload plus scale word | 68 |\n\nThe fused operator requires CUDA BF16 inputs on one device, at least two\ndimensions, a contiguous innermost dimension, eight-byte-aligned addresses,\nequal row counts, and positional width divisible by four. Positional and\nnon-positional widths must sum to 128. It returns packed `int8[M,64]` data and\n`int32[M,1]` scales.\n\nThe scale for each 32-value group is\n`2^ceil(log2(max(amax, 1e-12) / 6))`. Quantization uses the FP4 E2M1 magnitude\nset `{0, 0.5, 1, 1.5, 2, 3, 4, 6}` and packs the earlier value into the low\nnibble.\n\nThe cache is viewed as\n`[num_blocks, block_size, 1, per_token_size]` and may be non-contiguous. Each\ntoken launch copies four bytes per thread. The FP4 path uses 64 payload bytes\nand one four-byte scale word; the legacy FP8 path uses 128 payload bytes and\none four-byte FP32 scale.\n\nPayload and scale use separate contiguous `int64` slot-mapping arrays. If\neither mapping for a token is negative, gather and scatter skip that entire\ntoken. The gather wrapper allocates output with `empty`, so a directly gathered\nrow skipped this way has no kernel-written sentinel value; callers must avoid\nconsuming it or define initialization in their own reference.\n\nThe gather wrapper preserves a historical typed view: payload bytes are\nreturned as float8 and scale bytes as FP32. The FP4 call site reinterprets them\nas packed `int8` data and `int32` scale words before the DeepGEMM call. These\nviews are byte contracts, not evidence that the FP4 payload became FP8 or that\nits UE8M0 scale word became an FP32 numeric scale.\n\n1. Compare `fused_cat_fp4` byte-for-byte with a reference implementation for\n zeros, FP4 decision boundaries, saturation, non-contiguous row strides, and\n multiple positional/non-positional splits whose widths sum to 128.\n2. Round-trip valid tokens through scatter and gather using strided cache\n views. Check all 64 payload bytes and the four scale bytes independently;\n test negative payload and scale mappings without reading skipped empty rows.\n3. Compare FP4 non-paged and paged indexer logits, then selected indices,\n against an unquantized or higher-precision reference with identical masks,\n weights, and sequence boundaries.\n4. Profile fused preparation, scatter, gather, logit computation, top-k, and\n the complete indexer separately. Report shapes, cache layout, mapping mix,\n warmup, synchronization, repetitions, statistic, and variation.\n\nThe pinned PR contains no performance result, so use it to define candidate\nmechanisms and exact contracts rather than to claim a speedup."}, "reason": {"statement": "Remove invented CUDA that neither implements nor safely probes the pinned indexer contract.", "urls": []}} +{"path": "wiki/kernels/tensorrt-llm-blackwell-indexer.md", "before": {"statement": "TensorRT-LLM PR 13340 integrates an FP4 indexer path for DSA on Blackwell and\nlands CUDA kernels for K-cache gather/scatter and fused FP4 concatenation. Use it\nas implementation evidence for sparse indexer memory movement and quantized\ncache layout, not as a drop-in answer for FlashInfer-Bench."}, "after": {"statement": "TensorRT-LLM PR 13340 adds an FP4 option to its DeepSeek Sparse Attention\n(DSA) indexer path. This page describes the PR's pinned merge revision\n`897c4bff`; it is a TensorRT-LLM implementation reference, not a generic DSA\nABI or a drop-in FlashInfer-Bench kernel.\n\nThe implementation has four distinct stages:\n\n| Q/K preparation | `fused_cat_fp4` concatenates BF16 positional and non-positional components, then quantizes the 128-value row to FP4 E2M1 with per-32-value UE8M0 scales |\n| Cache update/read | Scatter and gather copy an already-quantized payload and its scale word between contiguous tensors and TensorRT-LLM's possibly non-contiguous paged indexer cache |\n| Indexer logits | The FP4 path reinterprets the packed bytes/scales and dispatches TensorRT-LLM's DeepGEMM FP4 MQA-logit implementation |\n| Selection | Prefill or decode top-k runs after logit computation in a separate operator |\n\nThe gather/scatter kernels do not quantize values, compute logits, or select\nindices. Calling them “fused quantized gather/scatter” conflates the first two\nstages.\n\n1. Compare `fused_cat_fp4` byte-for-byte with a reference implementation for\n zeros, FP4 decision boundaries, saturation, non-contiguous row strides, and\n multiple positional/non-positional splits whose widths sum to 128.\n2. Round-trip valid tokens through scatter and gather using strided cache\n views. Check all 64 payload bytes and the four scale bytes independently;\n test negative payload and scale mappings without reading skipped empty rows.\n3. Compare FP4 non-paged and paged indexer logits, then selected indices,\n against an unquantized or higher-precision reference with identical masks,\n weights, and sequence boundaries.\n4. Profile fused preparation, scatter, gather, logit computation, top-k, and\n the complete indexer separately. Report shapes, cache layout, mapping mix,\n warmup, synchronization, repetitions, statistic, and variation.\n\nThe pinned PR contains no performance result, so use it to define candidate\nmechanisms and exact contracts rather than to claim a speedup."}, "reason": {"statement": "Name concat-plus-quantization and byte-copy cache movement as separate operations.", "urls": []}} +{"path": "wiki/patterns/memory-bound.md", "before": {"statement": "- Always profile before optimizing — wrong assumption wastes effort"}, "after": {"statement": "Report input shapes/distributions, useful work and bytes, cache state, warmup/repetitions/statistic, GPU and clocks, software versions, generated instructions, resource usage, roofline assumptions, achieved memory-level bandwidth, requested/transferred efficiency, scheduler activity, and correctness tolerance. Include negative and regressing variants so a category heuristic is not mistaken for causal evidence."}, "reason": {"statement": "Replace an absolute workflow rule with an evidence-based diagnose, hypothesize, control, and measure loop.", "urls": ["https://docs.nvidia.com/nsight-compute/2025.3/ProfilingGuide/index.html"]}} +{"path": "wiki/techniques/chunk-parallelism.md", "before": {"statement": "- Linear attention (O(n) complexity)\n- Recurrent state models (Mamba, GatedDeltaNet, Delta Rule)"}, "after": {"statement": "Some linear recurrent models admit an algebraically equivalent chunkwise formulation. Work local to a chunk can then be expressed with parallel matrix operations, while the state passed across chunk boundaries preserves the recurrence's sequence order. The exact transform is model-specific: it must be derived from the recurrence, not replaced by a generic attention matrix and additive state update.\n\nA correct implementation separates at least these obligations:\n\n1. Compute the chunk-local quantities required by the model's exact recurrence.\n2. Resolve boundary states in sequence order, either with an associative scan supported by the formulation or with explicitly ordered stages or launches.\n3. Combine each chunk's local result with its incoming boundary state and emit outputs in the original token order.\n4. Validate outputs and final states against a token-by-token reference across variable sequence lengths, chunk tails, batches, heads, dtypes, and gate extremes.\n\nAn ordinary GPU grid does not imply increasing program-ID execution order or grid-wide synchronization. Programs for every chunk therefore cannot safely read and overwrite one shared state pointer in a single unordered launch. A staged algorithm must make the boundary-state dependency explicit.\n\nThe pinned NVlabs GatedDeltaNet repository uses chunkwise Triton kernels for training and a WY representation of the gated delta rule. That implementation is direct evidence for GatedDeltaNet chunking, but it is not equivalent to a generic `scores = Q @ K.T; output = scores @ V` snippet and does not supply a universal chunk-size rule.\n\nTiled Flash Linear Attention (TFLA) starts from the chunkwise formulation of linear RNNs and adds another level of sequence parallelization within a chunk. The authors state that this permits arbitrarily large chunks, raises arithmetic intensity, and reduces intermediate-state materialization. The paper and pinned official code apply the method to mLSTM and report H100 results; they do not establish a GatedDeltaNet implementation, a Blackwell/TMEM implementation, or a recursive-tiling API.\n\nThere is no source-backed universal rule that `C=32` is a decode choice or that `C=256-512` is the prefill optimum. Choose only among chunk sizes supported by the exact algorithm and backend, then measure the tradeoff:\n\n- arithmetic intensity and matrix-instruction utilization;\n- intermediate-state and workspace traffic;\n- registers, shared memory, and occupancy;\n- tail handling and variable-length metadata;\n- launch count and boundary-scan cost;\n- latency and throughput for the intended batch and sequence distribution.\n\nCompare candidates with identical compiler/software revisions, launch inputs, correctness oracles, warmups, synchronization, and repeated-trial statistics. Treat a selected size as scoped to the model dimensions, dtype, GPU, backend, and workload. TMEM availability on SM100 may change an implementation's resource design, but it does not by itself prove that a larger chunk is legal or faster."}, "reason": {"statement": "Require a proven model-specific chunkwise-equivalent transform and measured benefit before transfer.", "urls": ["https://arxiv.org/abs/2503.14376v3", "https://github.com/NVlabs/GatedDeltaNet/tree/b53d6d3a161267432a79c1c04af69fa52bddc921", "https://github.com/state-spaces/mamba", "https://triton-lang.org/main/programming-guide/chapter-1/introduction.html"]}} diff --git a/verification/current-queue.jsonl b/verification/current-queue.jsonl new file mode 100644 index 000000000..32dd7a45a --- /dev/null +++ b/verification/current-queue.jsonl @@ -0,0 +1,52 @@ +{"body_sha256": "3323bbd48edb46227476afa34e05f5c2552b2883b02b8a0e60d189dc5592ae97", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "PTX defines a CTA pair as two CTAs in the same cluster whose `%cluster_ctarank` values differ only in the low bit. With `cta_group::2`, one thread from either CTA can initiate a whole `tcgen05.mma`; the peer CTA must still be active. The op", "sha256": "b7afdc24eb589c39ba6e02afe005b308b174971a2755868869988a5789159e7e"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "Allocation management differs from MMA issue. A `tcgen05.alloc` or `tcgen05.dealloc` for `cta_group::2` is issued collectively by two warps, one in each CTA. All tcgen05 instructions in the kernel must use the same CTA-group value.", "sha256": "dbe9bd221edf8a902619236cdafd74941eaa79370ff87f5be263e86965cd6403"}, {"id": "u003", "kind": "prose", "locator": "body:L11-L11", "preview": "`cta_group::2` selects pair-level resources; it does not by itself select one fixed MxNxK shape. The instruction descriptor (`idesc`) encodes M, N, exact operand and accumulator types, sparsity, and related operation details. Legal values d", "sha256": "645ac1d3970d062f6bb9eae3ae3b25048285e45ef7a9f67d305f3d5850fe00e6"}, {"id": "u004", "kind": "prose", "locator": "body:L13-L13", "preview": "For example, m256xn256xk16 is a useful maximum F16/BF16 configuration, but PTX also defines group-2 layouts with other M/N values. Do not infer that every pair-level MMA is created by mechanically doubling a group-1 M dimension.", "sha256": "45f876da36a8addf0f5f581bfda573dd932287c7dc2df933d377bd5a562a1e27"}, {"id": "u005", "kind": "prose", "locator": "body:L15-L15", "preview": "The complete operand grammar, including the eight-register disable-output-lane vector used by `cta_group::2`, is documented on the related [tcgen05.mma page](tcgen05-mma.md).", "sha256": "936e6a2c0cc8ca27f6d457147b1e4da3d5cb75d9e7ebe81f0d7a427f0df6a20e"}, {"id": "u006", "kind": "prose", "locator": "body:L19-L19", "preview": "A pair-level kernel must account for all of these invariants:", "sha256": "e650fb835f8148efa001798dc386feb5cf624c517a63042b2bf85b81eb9ce3e7"}, {"id": "u007", "kind": "list-item", "locator": "body:L21-L21", "preview": "- The two CTAs form a valid CTA pair, and the peer remains active while a group-2 operation is issued.", "sha256": "8c9f5a7af50f1a7d7318498652a12b917fadff697d60bbacde9da59632ca1727"}, {"id": "u008", "kind": "list-item", "locator": "body:L22-L22", "preview": "- Pair-level TMEM allocation and deallocation follow their two-warp collective issue rule.", "sha256": "7fc30f24802c8c5f7ad184674a87dd8fae96c86c6fb7c60b5f65bddd03c46a83"}, {"id": "u009", "kind": "list-item", "locator": "body:L23-L23", "preview": "- SMEM and TMEM operands use legal layouts and descriptors for the selected instruction configuration.", "sha256": "1b832c3aec6846dd172301510f13cf19edd674601565aaca3167657749c9298e"}, {"id": "u010", "kind": "list-item", "locator": "body:L24-L24", "preview": "- Source storage is not overwritten while the asynchronous MMA may still consume it.", "sha256": "68db8f70b3b5c1f6ffa65d9ca6a1b5fde856003e9f6774e061d5768162bba2ed"}, {"id": "u011", "kind": "list-item", "locator": "body:L25-L25", "preview": "- `tcgen05.commit.cta_group::2` and an mbarrier wait provide completion tracking. Fences and execution-ordering operations are added where tcgen05-visible state crosses threads or CTAs.", "sha256": "81756fed0c3ff7d3024ce2f8d37cc4909fa6f8e020401bd81455b0b1a565d299"}, {"id": "u012", "kind": "prose", "locator": "body:L29-L29", "preview": "In Gau Nernst's M=N=K=4096 experiment on a Modal B200 with PyTorch 2.9.1 and CUDA 13, v4 warp specialization reports 1208.83 TFLOP/s and v5 2-SM MMA reports 1302.29 TFLOP/s. Relative to the same 1506.74-TFLOP/s cuBLAS result, those are appr", "sha256": "61e879b8bfa7a29e2e447c1ee711711fbe772da90995a3fe00d069595f991495"}, {"id": "u013", "kind": "prose", "locator": "body:L31-L31", "preview": "That result establishes a gain for one kernel and setup, not a universal threshold. Choose between group 1 and group 2 by benchmarking the target shapes and accounting for CTA pairing, data reuse, layout, occupancy, pipeline stages, and epi", "sha256": "7a1a54d6bfb919e3146075f7166fe3c39e80c43c275ae0409c1c81288eae52ec"}, {"id": "u014", "kind": "list-item", "locator": "body:L35-L35", "preview": "- [tcgen05.mma](tcgen05-mma.md) \u2014 instruction grammar, completion, and descriptors", "sha256": "59d6232600e3c79f97116d6414daad7399a0e29b469130cf23ce8ff9b7f124c0"}, {"id": "u015", "kind": "list-item", "locator": "body:L36-L36", "preview": "- [Tensor Memory](tmem.md) \u2014 TMEM allocation, addressing, and access", "sha256": "a401db8bea32d6d1e6be27e6bb3b9692341354f1689f50bb323de203b7a85c75"}], "confidence_claimed": "verified", "headings": ["Execution model", "Shape is independent of group size", "Correctness requirements", "Source-reported performance", "Related"], "id": "hw-2sm-cooperative", "path": "wiki/hardware/2sm-cooperative.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/prs/cutlass/PR-2139.md", "revision": "ca4fdbea", "url": "https://github.com/NVIDIA/cutlass/pull/2139"}], "risk_flags": ["ordering"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-ptx-isa-sm100", "blog-tcgen05-tutorial", "pr-cutlass-2139"], "title": "Two-SM Cooperative MMA", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "1f3e642012f3b80c6e5f67e510f41b1577c6bf9f6c669549349e1825285ea491", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L8", "preview": "Cluster Launch Control is a Blackwell compute-capability 10.0 mechanism for work stealing between running and not-yet-started thread blocks or thread block clusters. A CLC kernel still launches the problem-sized grid. Each grid coordinate, ", "sha256": "aed47d2a04a85e6e88c936e4f0305caff731581c87ae085491120f8fa1ae4e43"}, {"id": "u002", "kind": "list-item", "locator": "body:L10-L10", "preview": "1. The block or cluster launches normally and first processes its own", "sha256": "dfffcdb04d50ba6a0611612fbb6ff9f3a8689688b0dcd3728ba506a89ef66b38"}, {"id": "u003", "kind": "prose", "locator": "body:L11-L11", "preview": "`blockIdx`.", "sha256": "4c5c20de2592c1acafe9877ccbb8b570ecf16bbef8b6f7e393e80a08ad288c45"}, {"id": "u004", "kind": "list-item", "locator": "body:L12-L12", "preview": "2. An existing worker successfully cancels that not-yet-started ClcID and", "sha256": "ed46f5f3fe23df91f74b22f3f5038976844d96b772df7bc9f16241a82cc067a3"}, {"id": "u005", "kind": "prose", "locator": "body:L13-L13", "preview": "processes the returned coordinate itself.", "sha256": "6d361b359451a9c431b0548ae2c09aa46647cf39813bcb04e3b07d03f17f274f"}, {"id": "u006", "kind": "prose", "locator": "body:L15-L17", "preview": "This lets a persistent worker request subsequent work without maintaining a separate software work queue. It is especially useful when the set of SMs available to a kernel is uneven or changes while the grid is running.", "sha256": "5882b7a980f93728bc6dd0f50b3db643bb8841689dfd7f738ccdb0d8ed30eaf9"}, {"id": "u007", "kind": "prose", "locator": "body:L21-L23", "preview": "`clusterlaunchcontrol.try_cancel` is asynchronous. It writes an opaque 16-byte response to shared memory and completes a transaction on a shared-memory `mbarrier`. The request does not accept a tile coordinate to cancel.", "sha256": "07b338face1ef537bc6a6b1f149dd819322353bfa5868d3c7912e3dc818d2221"}, {"id": "u008", "kind": "prose", "locator": "body:L25-L25", "preview": "The normative PTX instruction forms are:", "sha256": "ed7ac6510f74ef3d579ebe7336066cd20a940b5608289455a2568d88e557f929"}, {"id": "u009", "kind": "code", "locator": "body:L27-L31", "preview": "```ptx clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [response], [mbar]; clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 p, response_b128; @p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4", "sha256": "67fa262449a500557e66306c5d57edcda130d2e7ad8b3b2353b998f1aacb1556"}, {"id": "u010", "kind": "prose", "locator": "body:L33-L33", "preview": "A complete loop must:", "sha256": "d24cc2e528fb2301c03829b15fab641a2eca64b281568e016244188a32f257f6"}, {"id": "u011", "kind": "list-item", "locator": "body:L35-L35", "preview": "1. Allocate and initialize a shared response and `mbarrier`.", "sha256": "0ba588d30c80542da4138743e2418709adee3172b8e1aabc0eb1399de0d04c1e"}, {"id": "u012", "kind": "list-item", "locator": "body:L36-L36", "preview": "2. Submit one asynchronous request from the selected thread and set the", "sha256": "262ae4de6893ed5ff99b6aefa72c4f46117de59cee3bc9fdea46db4d10ccab08"}, {"id": "u013", "kind": "prose", "locator": "body:L37-L37", "preview": "expected transaction size to 16 bytes.", "sha256": "c5b2c635a95f64a2b4978c6746fb9a09fb96d36de263e92d906c555c0c376272"}, {"id": "u014", "kind": "list-item", "locator": "body:L38-L38", "preview": "3. Wait for the corresponding barrier phase to complete.", "sha256": "30d41ba4441d9bf673d62236cb464dde1dad69478b780b3fdd7f13aaea5d1fff"}, {"id": "u015", "kind": "list-item", "locator": "body:L39-L39", "preview": "4. Decode `is_canceled`; decode `get_first_ctaid` only after success.", "sha256": "38e1bc22c329938b11e59946ee33bcab2ee641c7f44aabec8d12e11ba0ee4347"}, {"id": "u016", "kind": "list-item", "locator": "body:L40-L40", "preview": "5. Apply the async/generic proxy fences needed before reusing the response.", "sha256": "26a497bb386f06ad534f04253e05b08ae4f740df588cfb9b7464897480ef7feb"}, {"id": "u017", "kind": "prose", "locator": "body:L42-L45", "preview": "After a thread has observed a failed request, issuing another request from that thread is undefined. Decoding a CTA ID from a failed response is also undefined. A request can fail because no ClcIDs remain or for another scheduling reason, i", "sha256": "2579bb2d0dc3f63c5616d49e9cd07bdaf39852713cc130a7f10392d3fc7d4a85"}, {"id": "u018", "kind": "prose", "locator": "body:L49-L54", "preview": "CLC cancellation is cluster-granular when the kernel uses thread block clusters. One cluster thread submits the multicast request. Every CTA tracks completion with its local shared-memory barrier at cluster scope and receives the same encod", "sha256": "af8682d845156e2308926d1a0bf821b02be6e659e9b3ff363b58921f5558b16d"}, {"id": "u019", "kind": "prose", "locator": "body:L56-L57", "preview": "For example, a successful query by a 2x2 worker cluster consumes the matching 2x2 group of ClcIDs; it is not four unrelated CTA-level cancellations.", "sha256": "6e23b2f1a5cde36d9a61363e854bcc5530da8de592fcda721043478ce0b8c281"}, {"id": "u020", "kind": "prose", "locator": "body:L61-L65", "preview": "At CUTLASS 4.5.0, the `PersistentScheduler` tag for `arch::Sm100` maps to `PersistentTileSchedulerSm100`; newer code can select the intent explicitly with `DynamicPersistentScheduler`. The SM100 scheduler uses `PipelineCLCFetchAsync`: `adva", "sha256": "15bb650d78b4f58a6b6a89201a36b0df29565b4d9ef8768ae8ca5f3a2ae03437"}, {"id": "u021", "kind": "prose", "locator": "body:L67-L67", "preview": "A schematic of the relevant CUTLASS 3.x kernel composition is:", "sha256": "c30f20ad1c9bae9938a60381504d2be3fa4a3a3d3989ca677da0457e294ed4a6"}, {"id": "u022", "kind": "code", "locator": "body:L69-L77", "preview": "```cpp using TileScheduler = cutlass::gemm::DynamicPersistentScheduler; using GemmKernel = cutlass::gemm::kernel::GemmUniversal< cute::Shape, CollectiveMainloop, CollectiveEpilogue, TileScheduler>; ```", "sha256": "f2d33d4b2462ceef8aaac37046da1b30637a67e5d88e2e6402598e676bf5d53b"}, {"id": "u023", "kind": "prose", "locator": "body:L79-L82", "preview": "CUTLASS can apply a software coordinate transform to both the initial `blockIdx` and decoded CLC responses. `max_swizzle_size` and `raster_order` are scheduler arguments used by `swizzle_and_rasterize()`; they are not operands of the CLC PT", "sha256": "a4b2a143772be0706381b1a9813f26cd44da22fd53d5f82576c4b4dd053d10e7"}, {"id": "u024", "kind": "prose", "locator": "body:L86-L86", "preview": "CLC redistributes ClcIDs that already exist in the launched grid. It does not:", "sha256": "bf4dc5fc684e939ef4ea815ea1f55868b6255ce0620993cb595c0fd89df6aab7"}, {"id": "u025", "kind": "list-item", "locator": "body:L88-L88", "preview": "- discard an application-selected output tile;", "sha256": "0e4143cc1ba403906fbd9bb07350d6ac3d46a4ab482c833d5befca3696d1c77f"}, {"id": "u026", "kind": "list-item", "locator": "body:L89-L89", "preview": "- create more independent tiles than the problem grid contains;", "sha256": "cd5c58b2f2af74b71e1551b0cab1067a68a6385717c9f4ce6d0138711e7814db"}, {"id": "u027", "kind": "list-item", "locator": "body:L90-L90", "preview": "- guarantee that every SM remains occupied; or", "sha256": "ca82f9c8684574f060c65785314120d152a34c0efe8956d710f8250716b52bde"}, {"id": "u028", "kind": "list-item", "locator": "body:L91-L91", "preview": "- universally eliminate GEMM wave quantization.", "sha256": "4eaabf49ee1f6647506cc7cdb71f11a5ec2655ea5ca0bee1aabfb7661a071d8a"}, {"id": "u029", "kind": "prose", "locator": "body:L93-L96", "preview": "Consequently, a 32-tile grid exposes at most 32 independent ClcIDs even on a 148-SM B200. Any CLC performance result must state the GPU, available SMs, software versions, tile and cluster shapes, data types, timed region, and measurement me", "sha256": "0453affd2bd43d77232b7fa7a6bd19d9d54911593654fe9569df1a5693c05960"}, {"id": "u030", "kind": "list-item", "locator": "body:L100-L100", "preview": "- [Persistent kernels](../techniques/persistent-kernels.md)", "sha256": "ec9585a9787c7d4334a41d77c6ecbeee6575e90c64bb37f1f2e8c8b8d64b041d"}, {"id": "u031", "kind": "list-item", "locator": "body:L101-L101", "preview": "- [Tile scheduling](../techniques/tile-scheduling.md)", "sha256": "cf18db71a889f046a73a3782397405ed6582feabacaff30a3581db0e6ca9b909"}, {"id": "u032", "kind": "list-item", "locator": "body:L102-L102", "preview": "- [Two-SM cooperative MMA](2sm-cooperative.md)", "sha256": "72792611c19c45c9af380298f75c59a65e9192b3ca1891804c858ae32c448c19"}], "confidence_claimed": "source-reported", "headings": ["Overview", "Request and Decode Protocol", "Thread Block Cluster Rules", "CUTLASS 4.5.0 Integration", "Scope and Limits", "Related"], "id": "hw-clc", "path": "wiki/hardware/clc.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}, {"path": "sources/docs/cutlass-clc-documentation.md", "url": "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"}], "risk_flags": ["code", "ordering"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-ptx-isa-sm100", "doc-cutlass-clc"], "title": "Cluster Launch Control (CLC)", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "4215a80fde138535a1d096475ad4d1b76c905d6cd8c3ab2b6198eae4c78180e3", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "An mbarrier is an opaque, naturally aligned 64-bit object in shared memory. It synchronizes threads and can track asynchronous operations. The base instructions were introduced in PTX ISA 7.0 for `sm_80`; Hopper (`sm_90`) added transaction-", "sha256": "c4f5f8029fdece300451e77adb2415e3afc2669f9a0de1bfb7882ffc46fc741a"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "mbarriers are useful in warp-specialized pipelines, but they are a mechanism rather than a requirement for every such kernel.", "sha256": "c1a2ae1d13b327f646fba681f8179c799b52402580d94b42b7d37665834c5abf"}, {"id": "u003", "kind": "prose", "locator": "body:L11-L11", "preview": "For the current phase, an mbarrier tracks:", "sha256": "304bf0328887acfa9d619fae48be89bcb511e2e5dfdda8e39df146bdc226ccc4"}, {"id": "u004", "kind": "list-item", "locator": "body:L13-L13", "preview": "- pending arrivals;", "sha256": "34d9f60ef2b7432a837c1500cfba321064686c29d34d2ae29f3b2958006daa5f"}, {"id": "u005", "kind": "list-item", "locator": "body:L14-L14", "preview": "- the expected arrival count for the next phase; and", "sha256": "f58e7621149f63f5e686db346bcae1c67443ce37f6e6548ed08d0405e9e19c4f"}, {"id": "u006", "kind": "list-item", "locator": "body:L15-L15", "preview": "- a transaction count (`tx-count`) for outstanding asynchronous work.", "sha256": "79aac4088b7db28aec02c8ae5c432e55959337176f40cf20ee2c9dd974977dc0"}, {"id": "u007", "kind": "prose", "locator": "body:L17-L17", "preview": "The current phase completes only when **both** pending arrivals and tx-count reach zero. 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Before an arrival in the following phase, at le", "sha256": "3ef1cba778254c5a2d9eb1e0c765268be4505dbd47deab20ed5d96aa70b884f1"}, {"id": "u008", "kind": "prose", "locator": "body:L19-L19", "preview": "Initialization sets phase 0, initializes expected and pending arrivals to `count`, and sets tx-count to zero:", "sha256": "3dd244f469369ff5bb493acac9cf1c56fa19c974e059eee55b901afb1febbd78"}, {"id": "u009", "kind": "code", "locator": "body:L21-L23", "preview": "```ptx mbarrier.init.shared::cta.b64 [bar], arrival_count; ```", "sha256": "aa334cafb032b7c70d03d4e311e23e4026954ad8ea5831c5b48c3204ddb2e352"}, {"id": "u010", "kind": "prose", "locator": "body:L25-L25", "preview": "Invalidate the object with `mbarrier.inval` before reusing its storage for another purpose or reinitializing an already-valid object.", "sha256": "3e1ccc8d4cf7dcc62712f205c681c77ac6676d2a8976dbbb38da31e5ce84dd82"}, {"id": "u011", "kind": "prose", "locator": "body:L29-L29", "preview": "These operations affect different parts of the state:", "sha256": "db8771ec1644298d11488ccedea8133c2d8a332e784378167861fde24f6d0dac"}, {"id": "u012", "kind": "table-row", "locator": "body:L33-L33", "preview": "| Operation | Effect | | `mbarrier.arrive` | Decrements pending arrivals; returns a phase state token for a CTA-shared object. |", "sha256": "300828c39cb781b4776ad8085e58d35a449c60007fb58130022bd4d2df92ee87"}, {"id": "u013", "kind": "table-row", "locator": "body:L34-L34", "preview": "| Operation | Effect | | `mbarrier.arrive.expect_tx` | Performs an arrival and increments tx-count by `txCount`. |", "sha256": "772dbfd906bd8df1d1355530998b10a6527e37976ed1f530c1e6a2ddee681939"}, {"id": "u014", "kind": "table-row", "locator": "body:L35-L35", "preview": "| Operation | Effect | | `mbarrier.expect_tx` | Increments tx-count without an arrival. |", "sha256": "5bb2361feb6d63ec4abc789110d8fe7ae1e7755422f6d64271931f8408e346a1"}, {"id": "u015", "kind": "table-row", "locator": "body:L36-L36", "preview": "| Operation | Effect | | `mbarrier.complete_tx` | Decrements tx-count; it is not an arrival. |", "sha256": "4a62afc513ab2b8c7e543ac78ea5073ed6a6e2edbdac71c34a72fcfa814f5d44"}, {"id": "u016", "kind": "table-row", "locator": "body:L37-L37", "preview": "| Operation | Effect | | `mbarrier.test_wait` / `try_wait` | Tests completion of the phase identified by a state token or parity. |", "sha256": "1eba28206a3d00699d921ca747a0c9124fbece5c665904280441030dffc1c170"}, {"id": "u017", "kind": "prose", "locator": "body:L39-L39", "preview": "Representative CTA-shared forms from PTX ISA 9.0 are:", "sha256": "6438bbf3813fa047bdeeb75c65d22888dd99b788ba7abe2ee32fa891eed9dc5b"}, {"id": "u018", "kind": "code", "locator": "body:L41-L45", "preview": "```ptx mbarrier.arrive.shared::cta.b64 state, [bar]; mbarrier.arrive.expect_tx.shared::cta.b64 state, [bar], tx_count; mbarrier.try_wait.parity.acquire.cta.shared::cta.b64 ready, [bar], phase_parity; ```", "sha256": "0c512373f52c01377048c5a4fea08c09a3152100ab4a8ed297d6eda13d7df509"}, {"id": "u019", "kind": "prose", "locator": "body:L47-L47", "preview": "`try_wait` can suspend temporarily and must still be retried until its predicate is true. Use acquire/release semantics appropriate to the producer-consumer handoff; `.relaxed` does not provide memory-ordering or visibility guarantees.", "sha256": "d4d9f62f69e26f69151ea42f45ec273782c1731a952027788eba1155e66b9538"}, {"id": "u020", "kind": "prose", "locator": "body:L51-L51", "preview": "Parity is the low bit of an individual mbarrier object's phase: even phases use 0 and odd phases use 1. A parity wait can refer only to the current or immediately preceding phase, so software must track phase for the entire lifetime of that", "sha256": "e47ce58bc9df238ddefe1d32feb34f481553161f6041f3bdeafe9dae2c88b0ea"}, {"id": "u021", "kind": "prose", "locator": "body:L53-L53", "preview": "For an N-stage ring, track state per stage. When stage `s` is reused, pass the parity expected for `bar[s]`; toggle that stage's parity only after its phase completes. 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The producer executes `mbarrier.arrive.expect_tx` with the sum of bytes that all TMA operations in this phase will report.", "sha256": "e6e85131dd05b8acd13524ece1fbf82c07d1fb351d06ba6b9b97466177defb4d"}, {"id": "u025", "kind": "list-item", "locator": "body:L62-L62", "preview": "2. The producer issues the TMA operations with `.mbarrier::complete_tx::bytes` and the same barrier.", "sha256": "3b455d20ff2edf905c7c37c22b84bb4032d6e814ebf48c6ebc9f292e7b9c2a12"}, {"id": "u026", "kind": "list-item", "locator": "body:L63-L63", "preview": "3. Each TMA completion performs `complete-tx` for the bytes it copied.", "sha256": "58b5cf80e14bbd08da00abbf27a7f8a2da08ada34555b744fbf89d7700b0b686"}, {"id": "u027", "kind": "list-item", "locator": "body:L64-L64", "preview": "4. The consumer waits for the phase to complete before reading the destination.", "sha256": "9a51e79d4ad54417a7c9bc97a7b91a0d23fae064b7c858456d0904fc8586e507"}, {"id": "u028", "kind": "prose", "locator": "body:L66-L66", "preview": "The `arrive.expect_tx` operation accounts for the software arrival and establishes the expected byte total. TMA hardware does **not** perform a second arrival: it decrements tx-count through complete-tx. Therefore, do not add an unmatched `", "sha256": "c52470c2e44b4d5cf43c371c1c9b810cea078c50208fbb8aac48d0844940ac00"}, {"id": "u029", "kind": "prose", "locator": "body:L68-L68", "preview": "The expected byte total, barrier address, destination ownership, and exact `cp.async.bulk.tensor` form must match. Follow the complete instruction grammar in the PTX ISA rather than using placeholder helper calls.", "sha256": "37fcfdfc369b1e9a22b669962cfd1e4ae24637c9e9f768a9b2dcc0054bc2122d"}, {"id": "u030", "kind": "prose", "locator": "body:L72-L72", "preview": "`tcgen05.commit.cta_group::*.mbarrier::arrive::one` makes an mbarrier track prior asynchronous `tcgen05.mma`, `tcgen05.cp`, or `tcgen05.shift` operations issued by that thread. When those operations complete, the system performs one arrive-", "sha256": "20e0ed0e00ca9af1a215f7874e174566a789deba3bab63c34b5cb599d5e24b8e"}, {"id": "u031", "kind": "prose", "locator": "body:L74-L74", "preview": "A consumer in another thread waits for the mbarrier and then uses the applicable `tcgen05.fence::after_thread_sync` ordering sequence. The fence participates in the handoff but does not replace the completion wait.", "sha256": "ef5af611efeacf06e77ed80510a63fb91011e700d7c43b4e8ef02263a285fe2b"}, {"id": "u032", "kind": "prose", "locator": "body:L78-L78", "preview": "State space and synchronization scope are separate concepts:", "sha256": "cde5c333b489108b69110f7a534b3445c2a5bdba33ea8114b885c3b9ef0f15bf"}, {"id": "u033", "kind": "list-item", "locator": "body:L80-L80", "preview": "- `.shared::cta` identifies a barrier in the current CTA's shared memory.", "sha256": "cb736ed3b82018b4af9ff8a71c06b39150af84e6300cd74341b00374ce604cd7"}, {"id": "u034", "kind": "list-item", "locator": "body:L81-L81", "preview": "- `.shared::cluster` identifies a cluster-shared address, such as a mapped address for another CTA's shared memory.", "sha256": "090eeb2f11c80401d9b399e755d561f418360d9f38fa7a8327e255e58ee245fe"}, {"id": "u035", "kind": "list-item", "locator": "body:L82-L82", "preview": "- `.cta` or `.cluster` on an operation specifies its synchronization scope.", "sha256": "1865209300b9b76af9ab274882f77faf299eb648588d07c2d2d23ea10172511a"}, {"id": "u036", "kind": "prose", "locator": "body:L84-L84", "preview": "Only `arrive`, `expect_tx`, and `complete_tx` support an mbarrier address in `.shared::cluster`. Other mbarrier operations, including initialization and waits, target a CTA-shared object. A cluster can initialize an owner CTA's object, map ", "sha256": "979150fd2755438fb6b2960fbfc8b1b3a6008d8b833e6e9e2368d68f72f98663"}, {"id": "u037", "kind": "list-item", "locator": "body:L88-L88", "preview": "- Initialize the object before any other mbarrier operation.", "sha256": "5a0505577b6d44496231fcf69d503700ad594baa46ed4caca261a31e4ae6fff8"}, {"id": "u038", "kind": "list-item", "locator": "body:L89-L89", "preview": "- Match all arrivals and byte-valued complete-tx operations to the initialized counts.", "sha256": "215bf504fc87a3066decf20c5d7b854138df7c926508dd83e33184698daa0f0d"}, {"id": "u039", "kind": "list-item", "locator": "body:L90-L90", "preview": "- Keep phase or opaque state separately for each pipeline stage.", "sha256": "9e11f202036db2380e4c8b118a24287c1b99ecdb55d99b096401f940d36ab928"}, {"id": "u040", "kind": "list-item", "locator": "body:L91-L91", "preview": "- Retry `try_wait` until it reports completion.", "sha256": "6ed11f86197d07208c541ec7e852358105d81227c2d119a210c9faac8b158b05"}, {"id": "u041", "kind": "list-item", "locator": "body:L92-L92", "preview": "- Use the required acquire/release semantics for data visibility.", "sha256": "7ad077d086fcdf1658e08a255ac255fb1bcaa232c537a86f920dbdce1f42130a"}, {"id": "u042", "kind": "list-item", "locator": "body:L93-L93", "preview": "- Distinguish TMA complete-tx from tcgen05 arrive-on completion.", "sha256": "9a4c97d8692c9ed6e03314c310463412be4d5b55a180624c83e2c0c70eb1f8b6"}, {"id": "u043", "kind": "list-item", "locator": "body:L94-L94", "preview": "- Respect the supported combinations of object state space and operation scope.", "sha256": "dd65f3da0041c597a64d3f6dcf024b5636d8dc1c4dbf5fc06b0d07075eedca5b"}, {"id": "u044", "kind": "list-item", "locator": "body:L95-L95", "preview": "- Invalidate the object before repurposing its storage.", "sha256": "a90e4657917b4d85f0f24721c561d0f0372ae63de4b3772aa96a1ad70a5b3cff"}, {"id": "u045", "kind": "list-item", "locator": "body:L99-L99", "preview": "- [PTX ISA 9.0: mbarrier object and lifecycle](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier)", "sha256": "440c7134e3238c710417e1ec64af241a2957ba1cd0e9ac30ba99e5ea63262e6a"}, {"id": "u046", "kind": "list-item", "locator": "body:L100-L100", "preview": "- [PTX ISA 9.0: mbarrier waits](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-try-wait)", "sha256": "545e66c84f010d0d57ac169190a90198a16ed31f5e14c5b327907a3110cb04b8"}, {"id": "u047", "kind": "list-item", "locator": "body:L101-L101", "preview": "- [PTX ISA 9.0: TMA tensor copies](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor)", "sha256": "daf224131f7f98d73e758e640b317c7c441ec221b87331b1d98fcaebc71e1c40"}, {"id": "u048", "kind": "list-item", "locator": "body:L102-L102", "preview": "- [TMA](tma.md)", "sha256": "d31942a8af5df5dde77f7f955775cf0a1e7539926207438cd5560491f1574f5d"}, {"id": "u049", "kind": "list-item", "locator": "body:L103-L103", "preview": "- [Warp specialization](../techniques/warp-specialization.md)", "sha256": "94df377cf6d384f1a13d7bab49fd429a6059089d72d3ec45bc1306ee3bba3549"}], "confidence_claimed": "verified", "headings": ["Scope and history", "Object state and phase completion", "Arrival, transaction, and wait operations", "Phase and parity in a stage ring", "TMA completion accounting", "tcgen05 completion accounting", "CTA and cluster distinctions", "Correctness checklist", "References"], "id": "hw-mbarrier", "path": "wiki/hardware/mbarrier.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}, {"path": "sources/prs/cutlass/PR-2139.md", "revision": "ca4fdbea", "url": "https://github.com/NVIDIA/cutlass/pull/2139"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-ptx-isa-sm100", "pr-cutlass-2139"], "title": "mbarrier (Memory Barrier Primitives)", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "0b946b34a4845a0b6c3bb801db3b992a4e8b6a858cb8b98fb47ebfd4239ba65f", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "NVFP4 is a quantization recipe, not just another name for its 4-bit payload. It reconstructs a value as:", "sha256": "227c70eceb96556659b2b5f6cf54e400e6245360f15905a84705c09b89a48113"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "`x_hat_i = e2m1_i * s_block * s_global`", "sha256": "794f7462514befdb8ac4a28522080782143495f8fd3157b5bea8c46d09934c6d"}, {"id": "u003", "kind": "prose", "locator": "body:L9-L9", "preview": "The three components are:", "sha256": "890b0b87819a86372f7ddcee49a11fd621e9a3a29c35ac7b8d1d2c2ff00d5c3e"}, {"id": "u004", "kind": "list-item", "locator": "body:L11-L11", "preview": "- **E2M1 payload:** one sign bit, two exponent bits, and one mantissa bit. Its numeric values are 0, +/-0.5, +/-1, +/-1.5, +/-2, +/-3, +/-4, and +/-6. Two E2M1 encodings fit in one byte.", "sha256": "c7e17ce8c55c39e0403be620d6ad757c8fa414b998dddfbdae211367d3c095e8"}, {"id": "u005", "kind": "list-item", "locator": "body:L12-L12", "preview": "- **Local scale:** one E4M3 scale shared by 16 consecutive payload values. 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Use the complete block and scale-vector qualifiers and follow the type-combination tables. These forms target arch", "sha256": "c48d3a2f58dfe90849b6ee8abacd39ebf0f30cc5c6835517ffe7997d411dd227"}, {"id": "u019", "kind": "prose", "locator": "body:L42-L42", "preview": "PTX ISA 9.0 provides the packed conversion form:", "sha256": "0895c7933390c018b85b8fbb5f7a635b182476c0daf63b31053aa71a507bba62"}, {"id": "u020", "kind": "code", "locator": "body:L44-L46", "preview": "```ptx cvt.rn.f16x2.e2m1x2 d, a; ```", "sha256": "b23b367d52866372d72acbf6316fbedf194a07a40533912e462aa9f5d2989ef1"}, {"id": "u021", "kind": "prose", "locator": "body:L48-L48", "preview": "Here `a` is a byte-sized packed pair and `d` is a 32-bit `f16x2` result. PTX also permits `mov.b32` to unpack a 32-bit scalar into four byte-sized vector destinations when the declarations satisfy its type rules. Neither syntax establishes ", "sha256": "ebaaf257c26310449c24b83cf719888507d42b14702ca8571b844efa027b0539"}, {"id": "u022", "kind": "prose", "locator": "body:L52-L52", "preview": "There is no architecture-independent \"4x versus Hopper\" result for these instructions. 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It is available on compute capability 9.0 and later, including Hopper and Blackwell.", "sha256": "b2a6132457b1395799e2baeb71d8b78a2aefada9ebcdb45692fe7c25aaeb6823"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "PDL creates an **opportunity** for overlap; it does not guarantee that the grids execute concurrently. The useful overlap is normally the primary's work after its launch trigger and the secondary's independent preamble before its dependency", "sha256": "3fadb352705867bcecdab210311e7fef978fb6c4d548428135a83c2cc9a4a59e"}, {"id": "u003", "kind": "prose", "locator": "body:L9-L9", "preview": "The CUDA protocol has three required roles:", "sha256": "f06a64f5123e88dbd07114031cac5afabaeaa52abc8ecae0037804ec2d46ba9a"}, {"id": "u004", "kind": "list-item", "locator": "body:L11-L11", "preview": "1. Every primary CTA either executes `cudaTriggerProgrammaticLaunchCompletion()` or exits. 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Omitting the explicit trigger is correct but removes the intended primary-tail overlap.", "sha256": "bfc1bc44195a8cde7f45936b64ed7d6aa9339ddddfada2ad1b2116386640a488"}, {"id": "u008", "kind": "prose", "locator": "body:L19-L19", "preview": "This minimal skeleton shows where each operation belongs; real kernels put independent and dependent work at the indicated points and add normal error checking:", "sha256": "3370f3719697733fed41083390007ea5145cd8c1b8282d838bd01adfb718bf3b"}, {"id": "u009", "kind": "code", "locator": "body:L21-L53", "preview": "```cuda #include __global__ void primary() { // Produce everything needed before the secondary may be launched. if (threadIdx.x == 0) { cudaTriggerProgrammaticLaunchCompletion(); } // Primary tail that does not change data ", "sha256": "eead129a867adbd5fb1df86742d091900d3f862173e7beba21c3690a3860a7e3"}, {"id": "u010", "kind": "prose", "locator": "body:L55-L55", "preview": "Do not place `cudaGridDependencySynchronize()` in the primary: it is the secondary-side wait, not the launch trigger. Do not replace the wait with an ordinary memory fence. PDL's wait supplies both prerequisite-grid completion and visibilit", "sha256": "e79291426c2535ad3f17bf2a11bf664cbe62f5ccc989b134980cb4688c2d116f"}, {"id": "u011", "kind": "prose", "locator": "body:L59-L59", "preview": "CUDA lowers the two device roles to Grid Dependency Control instructions:", "sha256": "b250259e26671cdcac831c563720d242a666b0ed7a9b6afd3bc3d07a4a29075e"}, {"id": "u012", "kind": "code", "locator": "body:L61-L68", "preview": "```ptx // Primary CTA: makes designated dependent grids eligible after every CTA // has issued this instruction or completed. griddepcontrol.launch_dependents; // Secondary thread: waits for in-flight prerequisite grids and visibility. grid", "sha256": "9a67c56925d56525f39e506610fa57ffe5f3d4cb35db94ae4b010c90bc37cc98"}, {"id": "u013", "kind": "prose", "locator": "body:L70-L70", "preview": "`griddepcontrol` was introduced in PTX ISA 7.8 and requires `sm_90` or newer. Repeating `launch_dependents` within one CTA has no additional effect after that CTA's first invocation. If a prerequisite uses `launch_dependents`, its dependent", "sha256": "11123906a586c5505184a7cdc1d00fc51809ba90d7022a7722448cdeb72d9f02"}, {"id": "u014", "kind": "prose", "locator": "body:L74-L74", "preview": "Blackwell does not make arbitrary back-to-back launches overlap automatically. CUDA applications still opt the secondary launch into programmatic stream serialization and implement the device-side trigger/wait protocol.", "sha256": "ccfc3e2c2f99820ecb72aa491631c59b39d47de9f75b8a957e277d6a99d7fa86"}, {"id": "u015", "kind": "prose", "locator": "body:L76-L76", "preview": "CUTLASS has a separate build choice. In CUTLASS 4.5.0, the CMake option `CUTLASS_ENABLE_GDC_FOR_SM100` defaults to `ON`, while the SM90 option is opt-in. That default only enables eligible CUTLASS code to emit its GDC wrappers; it is not a ", "sha256": "8eb6cc4790bdeac39a848471ff2ce472fad33e190c16c073942ece6b3446f6d8"}, {"id": "u016", "kind": "prose", "locator": "body:L80-L80", "preview": "PDL can help only when all of these conditions hold:", "sha256": "b2f3b22d9295e43ef95becd759c3f639e71bc43ce4f72542271211cd62079f54"}, {"id": "u017", "kind": "list-item", "locator": "body:L82-L82", "preview": "- the secondary has enough independent preamble to overlap;", "sha256": "eba59af65aaa7d730d01e0cc16bbd138f86c11888c7eb6c6b3f24a3c18abb67e"}, {"id": "u018", "kind": "list-item", "locator": "body:L83-L83", "preview": "- the primary has useful tail work after every CTA reaches the trigger;", "sha256": "275a77efa3bd46865530e8b4d92dbdd17cadc14417e31d68a8f1164ce5f46db4"}, {"id": "u019", "kind": "list-item", "locator": "body:L84-L84", "preview": "- the two grids have enough simultaneous resource headroom; and", "sha256": "f7874709a96e779af80196a86caff96361b4b30864ef2d3989d1c0e3352a02b4"}, {"id": "u020", "kind": "list-item", "locator": "body:L85-L85", "preview": "- the saved launch/serialization time exceeds the protocol and occupancy costs.", "sha256": "8b99cc7e62635157ccc3a04c9e04da4db13139ca6e15882d68b73abe87cbf385"}, {"id": "u021", "kind": "prose", "locator": "body:L87-L87", "preview": "Small-kernel chains, GEMM/epilogue sequences, and pipeline-parallel stages are candidates, not guaranteed wins. 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Consequently, names such as m128n256k16 and m256n256k16 are useful maximum-shape examples for F16/BF16 configuratio", "sha256": "2c714ca4e2add6030e2ffd3a982d42e1928c97e656e998af2d554e29bb7c7052"}, {"id": "u015", "kind": "prose", "locator": "body:L35-L35", "preview": "The unscaled floating-point grammar includes a disable-output-lane vector before the accumulation predicate:", "sha256": "0c3d6d381d9ddfc6470a447bf5c7209a114dfe79cca59536d5329b306df0caeb"}, {"id": "u016", "kind": "code", "locator": "body:L37-L41", "preview": "```ptx tcgen05.mma.cta_group.kind [d-tmem], a-desc, b-desc, idesc, { disable-output-lane }, enable-input-d {, scale-input-d}; ```", "sha256": "2ed61a81ad137911dae0bc5b5d1f4cf410d79d32deb51059f1da36185bc35527"}, {"id": "u017", "kind": "prose", "locator": "body:L43-L43", "preview": "For `cta_group::1`, the lane-disable vector contains four 32-bit values; for `cta_group::2`, it contains eight. Setting `enable-input-d` false computes `D = A*B`; setting it true computes `D = A*B+D`. The optional `scale-input-d` is limited", "sha256": "b9fb63cf6d552bb548afef70443d9c4a0b4bcc76a419792cfffbcd851b60e038"}, {"id": "u018", "kind": "prose", "locator": "body:L45-L45", "preview": "The block-scaled grammar is structurally different:", "sha256": "c89976d470fdda264de2b4c13671d036c8da1bc84c424adf03ecfdb9ec956213"}, {"id": "u019", "kind": "code", "locator": "body:L47-L51", "preview": "```ptx tcgen05.mma.cta_group.kind.block_scale.scale_vectorsize [d-tmem], a-desc, b-desc, idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d; ```", "sha256": "8e585731217607fbd7145d665ac7790e9f8610c4630fec9b63f1e613bc675ae8"}, {"id": "u020", "kind": "prose", "locator": "body:L53-L53", "preview": "These are normative grammar excerpts, not complete inline-assembly functions: real code must also build valid descriptors, allocate TMEM, preserve operand lifetimes, and implement completion.", "sha256": "c026a8a36bf3c27d1e949b295720a13a93ac89b99bf0e5d297e1efa0f274677d"}, {"id": "u021", "kind": "prose", "locator": "body:L57-L57", "preview": "`tcgen05.mma` is asynchronous. Two mechanisms serve different purposes:", "sha256": "0eb63c199bd2648a1a838b2d3a47ac38561ae64dd5a5aa4a389176a4bba0a4b9"}, {"id": "u022", "kind": "list-item", "locator": "body:L59-L59", "preview": "1. `tcgen05.commit.cta_group::N.mbarrier::arrive::one.b64` makes an mbarrier track completion of prior asynchronous tcgen05 operations issued by the executing thread. Waiting on that mbarrier observes completion.", "sha256": "b94843121138c19fe4f9c6b5f2e4180325b4b07209b2b16d53801684eb26feab"}, {"id": "u023", "kind": "list-item", "locator": "body:L60-L60", "preview": "2. `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` order tcgen05 operations across an execution-ordering handoff and constrain code motion. A fence is not a completion wait.", "sha256": "c0f4ab169700e7114ac3cfaf535bfcc96235d55a67b70ab445eeae606728c5c2"}, {"id": "u024", "kind": "prose", "locator": "body:L62-L62", "preview": "A cross-thread result handoff therefore needs both the applicable completion protocol and the applicable fence/execution-ordering protocol. Likewise, a pipelined mainloop must not release or overwrite an SMEM stage until the asynchronous MM", "sha256": "adf70d7f3800a733444d846a2e3c015cbd24273cb2574a36d0f5998aff0d4b87"}, {"id": "u025", "kind": "prose", "locator": "body:L66-L66", "preview": "The tcgen05 shared-memory descriptor is a 64-bit runtime value. PTX ISA 9.0 assigns fields for the encoded base address, leading dimension, stride dimension, fixed bits, base offset, leading-dimension mode, and a three-bit swizzle mode.", "sha256": "cd4b8ef944a646278af6e6a6ed009a7641447384c06e392a47867c99b4214e9c"}, {"id": "u026", "kind": "prose", "locator": "body:L68-L68", "preview": "Valid swizzle encodings include no swizzle, 128-byte, 64-byte, and 32-byte layouts (plus a 128-byte/32-byte-atomic mode). Values 3, 5, and 7 are invalid; ordinary 128-byte swizzling uses value 2. A layout must satisfy the addressing and ali", "sha256": "ffd078c072d1f53a4004b9a5bfd9958461011d22405ec4ef1724cc5f8fa0a464"}, {"id": "u027", "kind": "prose", "locator": "body:L72-L72", "preview": "For comparison, CUTLASS's pinned Hopper wrapper for m64n256k16 with FP32 accumulation declares 128 accumulator registers per participating thread. tcgen05 keeps D in TMEM during the MMA sequence, which can free GPR capacity for data movemen", "sha256": "aea6db1f85746818e4767b9d406b4e771290c0e462d3cabf587264e302613aef"}, {"id": "u028", "kind": "prose", "locator": "body:L76-L76", "preview": "Gau Nernst reports the following results for M=N=K=4096 on a Modal B200, using PyTorch 2.9.1 with CUDA 13. Values are measurements for that setup, not architecture-wide guarantees.", "sha256": "13f1217bf7f22fcc79830356b02e702206bb4a00151c16924639cf6d2bb21a99"}, {"id": "u029", "kind": "table-row", "locator": "body:L80-L80", "preview": "| Tutorial version | Reported TFLOP/s | Approx. cuBLAS share | | cuBLAS | 1506.74 | 100% |", "sha256": "ac004f48b31dd6f7024996d3995ded82f823d87f3eff7413f55ff3e6acc116b4"}, {"id": "u030", "kind": "table-row", "locator": "body:L81-L81", "preview": "| Tutorial version | Reported TFLOP/s | Approx. cuBLAS share | | v1a: basic tcgen05 + 2D 16B TMA | 254.62 | 17% |", "sha256": "81e39acb68544a7b7f6402f743738b5e37e51cd2b474f9cbfdb331689fdfd3f4"}, {"id": "u031", "kind": "table-row", "locator": "body:L82-L82", "preview": "| Tutorial version | Reported TFLOP/s | Approx. cuBLAS share | | v1b: 3D 16B TMA | 252.81 | 17% |", "sha256": "26b2647c4773366a5f1d00f84486e9190c5ce010b5958463cc44d7d8335336b6"}, {"id": "u032", "kind": "table-row", "locator": "body:L83-L83", "preview": "| Tutorial version | Reported TFLOP/s | Approx. cuBLAS share | | v2a: 2D 128B TMA | 681.20 | 45% |", "sha256": "589a9a37b7cf4601f48e74eed00ff7f502e5754d3003b46ad18b82471359782c"}, {"id": "u033", "kind": "table-row", "locator": "body:L84-L84", "preview": "| Tutorial version | Reported TFLOP/s | Approx. cuBLAS share | | v2b: 3D 128B TMA | 695.43 | 46% |", "sha256": "e70b55975fd80df16e31a7ae4e4699c6dc4a32c1f1579136407c89a4385d9c75"}, {"id": "u034", "kind": "table-row", "locator": "body:L85-L85", "preview": "| Tutorial version | Reported TFLOP/s | Approx. cuBLAS share | | v3: pipelining | 939.61 | 62% |", "sha256": "cb276d4db269baa1b1d091ffd693f81215a14e11e87bca3bbb7b4e737d267150"}, {"id": "u035", "kind": "table-row", "locator": "body:L86-L86", "preview": "| Tutorial version | Reported TFLOP/s | Approx. cuBLAS share | | v4: warp specialization | 1208.83 | 80% |", "sha256": "85b80f84546f9b39fe250172f16144299c9d09f56364b578a12423b78e221f9f"}, {"id": "u036", "kind": "table-row", "locator": "body:L87-L87", "preview": "| Tutorial version | Reported TFLOP/s | Approx. cuBLAS share | | v5: 2-SM MMA | 1302.29 | 86% |", "sha256": "7b18e80a7aa94f919322812f64ce759b9517b58ca7efba7933732a0f9aa0f531"}, {"id": "u037", "kind": "table-row", "locator": "body:L88-L88", "preview": "| Tutorial version | Reported TFLOP/s | Approx. cuBLAS share | | v6: persistent, static scheduling | 1475.93 | 98% |", "sha256": "dc244caa4f60fc59b1d9e62d010731e5e119b04331695c37ec54a5d5660f60d2"}, {"id": "u038", "kind": "prose", "locator": "body:L90-L90", "preview": "The v6 result did not use Cluster Launch Control; the author lists CLC and threadblock swizzling as unimplemented follow-up ideas.", "sha256": "58b7618727532d91a2095babb6482b7a126310da1fbdfaf4bab8776a2cefabc9"}], "confidence_claimed": "verified", "headings": ["Overview", "Kinds and shapes", "Operand grammar", "Completion and inter-thread ordering", "Shared-memory descriptors", "Register pressure and specialization", "Source-reported performance progression"], "id": "hw-tcgen05-mma", "path": "wiki/hardware/tcgen05-mma.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}, {"path": "sources/prs/cutlass/PR-2139.md", "revision": "ca4fdbea", "url": "https://github.com/NVIDIA/cutlass/pull/2139"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-ptx-isa-sm100", "pr-cutlass-2139", "blog-tcgen05-tutorial"], "title": "tcgen05.mma \u2014 Blackwell MMA Instruction", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "1eb48a33cd77ce277ac4783d357f5784e487533159bbe155fc942f404f3655f1", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "TMA is the descriptor-driven `cp.async.bulk.tensor` facility introduced for Hopper (`sm_90`) and retained on Blackwell. One thread can issue a non-blocking rank-1 through rank-5 tensor copy while the hardware performs multidimensional addre", "sha256": "942ee8eaa2c8a1a7a630eb77b351844e980ef1e36f0e549a8f0fa35689f227df"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "The principal copy directions and completion mechanisms are:", "sha256": "cd258dbf1c80e8b3bf04db3d6601ed09723c72ff7ce612a7202994b8369b02d5"}, {"id": "u003", "kind": "table-row", "locator": "body:L11-L11", "preview": "| Direction | Destination | Optional cluster behavior | Completion | | Global to shared | Issuing CTA or a CTA in its cluster | One masked instruction can multicast to selected CTAs | mbarrier `complete_tx` in bytes |", "sha256": "0d062928bfbbdbd16737f4478e912c51a16020e856647600f0273112a61ce977"}, {"id": "u004", "kind": "table-row", "locator": "body:L12-L12", "preview": "| Direction | Destination | Optional cluster behavior | Completion | | Shared to global | Issuing CTA's shared memory to a tensor map | Scatter modes are available on supported Blackwell targets | Bulk async group: issue, commit, wait |", "sha256": "be8df0a0b92e6d46dc931918bc193cda48ba5a02cdbf7655cef986ad552fc1cb"}, {"id": "u005", "kind": "prose", "locator": "body:L14-L14", "preview": "TMA copies the datatype represented by the tensor map. It does not provide a general FP32-to/from-FP16 or BF16 conversion step. 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Always check the encoder's `CUresult`; never use the output after an encoding failure.", "sha256": "1dc42273ad70a1619c9b071188b6c21a33296af5ea280e944e372650c47d5e1f"}, {"id": "u021", "kind": "prose", "locator": "body:L38-L38", "preview": "Host encoding is common, but it is not the only Blackwell path. CUDA also documents device-side tensor-map construction and modification on Blackwell. A map modified through the generic proxy must be published to the tensor-map proxy with t", "sha256": "32c5584ca3441e4fc303d1aacb9ebde7f3bd75753c43adcac3cf8eda7bfd543e"}, {"id": "u022", "kind": "prose", "locator": "body:L42-L42", "preview": "PTX ISA 9.0 defines this representative 2D CTA-local form:", "sha256": "b0293941d4875c7b42475bd148a898910ccfba21295ea5e319fcd8483dfdf15a"}, {"id": "u023", "kind": "code", "locator": "body:L44-L47", "preview": "```ptx cp.async.bulk.tensor.2d.shared::cta.global.mbarrier::complete_tx::bytes [dst_smem], [tensor_map, {x, y}], [full_barrier]; ```", "sha256": "c63f1e52e13d7bed644ceffc9967df48dac5830d6c1c436b73250f38dd90fdb3"}, {"id": "u024", "kind": "prose", "locator": "body:L49-L49", "preview": "The instruction is non-blocking. A common one-producer phase with one or more loads uses this accounting:", "sha256": "33c59a474aaa779a2840508f993381a25aeaa81e88b896d3e729b91f4863ca8d"}, {"id": "u025", "kind": "list-item", "locator": "body:L51-L51", "preview": "1. Initialize and publish the stage's mbarrier with the intended pending-arrival count.", "sha256": "b97850eccf2dd9133f354210b468324757ccddd7363c04b11905826bd5231e19"}, {"id": "u026", "kind": "list-item", "locator": "body:L52-L52", "preview": "2. The producer performs one `mbarrier.arrive.expect_tx` for its software arrival and the sum of bytes that all loads in this phase will complete.", "sha256": "7536187d8435ca9f9d70ea4ba02e02a996a19a2b67a19e2524ae42383ccaeb3f"}, {"id": "u027", "kind": "list-item", "locator": "body:L53-L53", "preview": "3. Issue the TMA loads against that barrier.", "sha256": "387aec934b017aca25a3dde3f8509850f2406a8e8fb178ae11305df52df38430"}, {"id": "u028", "kind": "list-item", "locator": "body:L54-L54", "preview": "4. Each completed load performs `complete_tx` for its copied byte count; it does **not** perform another arrival.", "sha256": "41c113b3b786060e187ca94075b7e8b4fbf2bdd2a611cab9393d01671a812f20"}, {"id": "u029", "kind": "list-item", "locator": "body:L55-L55", "preview": "5. Consumers wait with the correct state token or per-stage parity and acquire semantics before reading the destination.", "sha256": "d844abea9463ba69fbba5103258780bd95d6b474e5bb6eb11991a6f48d940c29"}, {"id": "u030", "kind": "prose", "locator": "body:L57-L57", "preview": "The phase completes only after pending arrivals and tx-count are both zero. If a design performs multiple software arrivals instead, its initialized count must match them exactly. See [mbarrier](mbarrier.md) for lifecycle, phase, and memory", "sha256": "84689cde185105f289c1e125c553e90e62cf23b7efc0219e0dc269aec0b3cf30"}, {"id": "u031", "kind": "prose", "locator": "body:L61-L61", "preview": "A tensor store uses bulk-group completion rather than the load's mbarrier protocol:", "sha256": "7644e09174ad1ec06520bbb2067d83e2dd1964ae8a1b874ce3b0f3e6a5d9cb90"}, {"id": "u032", "kind": "code", "locator": "body:L63-L68", "preview": "```ptx cp.async.bulk.tensor.2d.global.shared::cta.bulk_group [tensor_map, {x, y}], [src_smem]; cp.async.bulk.commit_group; cp.async.bulk.wait_group 0; ```", "sha256": "9b7414acc80138f372a237ff15efd42d0f0f188d9931500d80b109804411152e"}, {"id": "u033", "kind": "prose", "locator": "body:L70-L70", "preview": "The wait may be delayed to overlap independent work. It must occur before the issuing thread reuses the source shared memory or before code that requires store completion. `commit_group` creates the group; it is not itself a completion wait", "sha256": "bfc107e49734a610b28fe2cde672a1a0645e272320b570dc8c44f3b9596dab3f"}, {"id": "u034", "kind": "prose", "locator": "body:L74-L74", "preview": "The cluster form copies a global tile to the same shared-memory offset in every CTA selected by a 16-bit mask:", "sha256": "94c03e8dfa1adfc21eee3339add8ff57b0febd458ea6dca96c153d7bf652b35c"}, {"id": "u035", "kind": "code", "locator": "body:L76-L79", "preview": "```ptx cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster [dst_smem], [tensor_map, {x, y}], [full_barrier], cta_mask; ```", "sha256": "13740ee71ef9eb029a8fd56b0cf01d83934433dff96a8f1fc6ab0f1869ebdbc7"}, {"id": "u036", "kind": "prose", "locator": "body:L81-L81", "preview": "For `cta_group::1` (the default), the completion signal is also multicast to the same barrier offset in every selected destination CTA. A correct design therefore:", "sha256": "bd2bc4bda81f3d523a915f9119c19a704ad18216bea214eb3116c3ca820ce4a6"}, {"id": "u037", "kind": "list-item", "locator": "body:L83-L83", "preview": "- launches an explicit cluster and keeps every destination CTA's shared memory alive;", "sha256": "99220fe82c4329fd5ff1a570bae96e8b1a304953a628a7ed13aaff2e932dc681"}, {"id": "u038", "kind": "list-item", "locator": "body:L84-L84", "preview": "- initializes corresponding destination barriers before the elected issuer can start;", "sha256": "aaa47a1f531b09283cee30555df707bd08f0c1271b4e15442f61a81f8a97df53"}, {"id": "u039", "kind": "list-item", "locator": "body:L85-L85", "preview": "- uses one cluster-wide elected issuer, not one `threadIdx.x == 0` issuer in every CTA;", "sha256": "002e972562c21a4dd64b4792b70d2d300e01fe73754728937a5e32b8a654441d"}, {"id": "u040", "kind": "list-item", "locator": "body:L86-L86", "preview": "- includes only valid destination CTA ranks in the mask; and", "sha256": "8dfb07761fafb9091a650ad2883aa5dd47b19a85a523291ef4aba5dc9e978dd7"}, {"id": "u041", "kind": "list-item", "locator": "body:L87-L87", "preview": "- has every destination wait on its own corresponding barrier phase before consuming the tile.", "sha256": "6032817a977cb65d2e38311dba90fce95f1ba507d414939a1be5383ac925cd88"}, {"id": "u042", "kind": "prose", "locator": "body:L89-L89", "preview": "For GEMM tiles with the same N range and different M ranges, the CTAs use different A tiles but the same B tile, so multicast can avoid duplicate logical B-load requests. It does not promise an exact `cluster_size` reduction in measured DRA", "sha256": "c6b1d2169446becddd2f513ea356236dd3a2dc964bd99d7b0c2582db59b2f24b"}, {"id": "u043", "kind": "prose", "locator": "body:L93-L93", "preview": "TMA supports no swizzle and multiple swizzled shared-memory layouts, including 32B, 64B, and 128B spans plus newer variants for selected types. Swizzling rearranges chunks across shared-memory banks. The consumer must address the matching l", "sha256": "853a7a8ba52912cbc1b920f6f71d0610c40733f923573857286b071994a68364"}, {"id": "u044", "kind": "prose", "locator": "body:L95-L95", "preview": "There is no universal rule that every Blackwell or `tcgen05.mma` input uses 128B swizzling. The TMA tensor-map swizzle, destination base alignment, leading dimension, and the tcgen05 shared-memory descriptor must describe the **same** legal", "sha256": "2b4b0d6d11682df0f0130a149296140f1a53aa39f3ec97618d9acc1302d4715a"}, {"id": "u045", "kind": "prose", "locator": "body:L97-L97", "preview": "A matched swizzle can reduce or remove bank conflicts for a particular access pattern. It does not make every possible consumer access conflict-free.", "sha256": "a0b6b60319b33d60b4c5d3fe6af97125681fcc47c3b23349ca8c394854345795"}, {"id": "u046", "kind": "prose", "locator": "body:L101-L101", "preview": "A common Blackwell GEMM data path is:", "sha256": "13268f43c424737e1cb3cec39868151eea4e3d9bdd671f7b87dafcb603717e4f"}, {"id": "u047", "kind": "prose", "locator": "body:L103-L103", "preview": "`GMEM -> TMA -> SMEM -> tcgen05.mma -> TMEM -> tcgen05.ld -> registers -> output store`", "sha256": "23afe141ca999584d588aa68850c067da012eed1030c92b9aef1b932e349a614"}, {"id": "u048", "kind": "prose", "locator": "body:L105-L105", "preview": "Each reusable pipeline stage needs two independent ownership transitions:", "sha256": "bfa1891a762540b1465d3767155e2928b8b026e0f40f012c7bcd41afd38b6392"}, {"id": "u049", "kind": "list-item", "locator": "body:L107-L107", "preview": "- **full:** TMA has finished producing the shared-memory operands, so the MMA consumer may read them; and", "sha256": "11d6052606c7b84bebee01e3c45bd2589c56b249d41d348edfd2aafd566d180b"}, {"id": "u050", "kind": "list-item", "locator": "body:L108-L108", "preview": "- **empty:** asynchronous MMA has stopped reading those operands, so the TMA producer may overwrite the stage.", "sha256": "eef3d18fd694d3e4b240e591ddccf87b99764dd71f1f72c9e14f2fc1fceab149"}, {"id": "u051", "kind": "prose", "locator": "body:L110-L110", "preview": "Track full and empty state per stage. Account transaction bytes once, track each barrier's own phase, and do not equate CTA synchronization or a tcgen05 fence with async completion. A complete CUTLASS pipeline is safer evidence than a short", "sha256": "248d9132d4467e85eeff75f7f120ab16a0679a718df2d20a806c822af36f2027"}, {"id": "u052", "kind": "prose", "locator": "body:L112-L112", "preview": "Choose tile rank, swizzle, multicast, issue cadence, and stage count from the actual access pattern and resource budget. More distinct stages consume more shared memory; there is no universal optimum of three to five stages. Profile the tar", "sha256": "8a0567c9674b127300435eb31acb41d3d1aead134c3bae110c17c6d5aec4d12f"}, {"id": "u053", "kind": "list-item", "locator": "body:L116-L116", "preview": "- [CUDA 13.0.2 Programming Guide: TMA](https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#asynchronous-data-copies-using-the-tensor-memory-accelerator-tma)", "sha256": "6e4dfa9b3ded302ca056bb6a498de0ab3aaafeef829d5103c81e632f5c1bf14a"}, {"id": "u054", "kind": "list-item", "locator": "body:L117-L117", "preview": "- [CUDA Driver API 13.0.97: tensor-map management](https://docs.nvidia.com/cuda/archive/13.0.2/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html)", "sha256": "4e29813dfddcaddb177f40e4fe9480deb10b9dbe097b724c947ccd91c3658c8f"}, {"id": "u055", "kind": "list-item", "locator": "body:L118-L118", "preview": "- [PTX ISA 9.0: `cp.async.bulk.tensor`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor)", "sha256": "ef3133ce097f33a254f3b19981e6d76ec88f33e964ee32edb03b3aecb627cc9f"}, {"id": "u056", "kind": "list-item", "locator": "body:L119-L119", "preview": "- [CUTLASS 4.5.0: complete CuTe DSL TMA tutorial](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/python/CuTeDSL/cute/blackwell/tutorial/tutorial_tma/tma_v0.py)", "sha256": "fffa82636381165a465946081584ded3dbcb39253ce114ed6ca90eec84090ffb"}, {"id": "u057", "kind": "list-item", "locator": "body:L120-L120", "preview": "- [mbarrier](mbarrier.md)", "sha256": "3cdff3a1605be2d98c176340b72d54b96f0575bb3dad4b249d5599d1bb94c369"}, {"id": "u058", "kind": "list-item", "locator": "body:L121-L121", "preview": "- [tcgen05 MMA](tcgen05-mma.md)", "sha256": "8fe04c67b24dcafdf0ff00c51238617219c223e45065aa447c5f56c2203a5e2c"}], "confidence_claimed": "verified", "headings": ["Scope", "Tensor maps", "Global-to-shared load", "Shared-to-global store", "Cluster multicast", "Swizzle and tcgen05", "Pipeline invariants", "References"], "id": "hw-tma", "path": "wiki/hardware/tma.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-cuda-13-0-2-tma.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#asynchronous-data-copies-using-the-tensor-memory-accelerator-tma"}, {"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}, {"path": "sources/prs/cutlass/PR-2139.md", "revision": "ca4fdbea", "url": "https://github.com/NVIDIA/cutlass/pull/2139"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-cuda-13-0-2-tma", "doc-ptx-isa-sm100", "pr-cutlass-2139"], "title": "Tensor Memory Accelerator (TMA)", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "e03fceba3cdacef11e31732fc23f086a61294f8dd66e33483845ab06046ff224", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Tensor Memory is an addressable, on-chip memory introduced for fifth-generation Tensor Core operations on Blackwell. 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Use the PTX shape-specific layout tables rather than treating a logical MxN accumulator as a universal row-major array owne", "sha256": "2ea3747ea0fa2ad571db92917836e6431266f2c4a6f150e3cf559d78cad6fa63"}, {"id": "u012", "kind": "prose", "locator": "body:L31-L31", "preview": "TMEM has an explicit software-managed lifetime:", "sha256": "619075113787e60845488a825201856ee59878b761427028e7103ca64764ccdf"}, {"id": "u013", "kind": "list-item", "locator": "body:L33-L33", "preview": "1. Reserve shared memory for the 32-bit allocation result.", "sha256": "347425a839a5fa6eac81d4797ca4de56bb02bbb2eda77b4c47ae23820a94a58c"}, {"id": "u014", "kind": "list-item", "locator": "body:L34-L34", "preview": "2. Execute `tcgen05.alloc` collectively from one warp for `cta_group::1`, or from two warps\u2014one per paired CTA\u2014for `cta_group::2`.", "sha256": "b8e4f5ea142d2258f24cb03b6fea0cce727beb4c7d601d6b5af1bbc2b3abb396"}, {"id": "u015", "kind": "list-item", "locator": "body:L35-L35", "preview": "3. Synchronize consumers as required, then read the returned base `taddr` from shared memory.", "sha256": "75df93469c3e8eb30d652d8f99f7f56af6674bf7704e0a36db7c6d7f92987a9e"}, {"id": "u016", "kind": "list-item", "locator": "body:L36-L36", "preview": "4. Use the allocation for MMA, copy, load, or store operations with the same CTA-group mode.", "sha256": "bb1d97a60d0710ea6e20c4bf6951496a283f5fbf8979b4c474b8e45df508f13c"}, {"id": "u017", "kind": "list-item", "locator": "body:L37-L37", "preview": "5. Execute `tcgen05.dealloc` with the corresponding collective issue pattern.", "sha256": "2dc6706ed0536b771b2cde4f4f7fa2fac7f90658f9b4da940bfe0d24161a4c5b"}, {"id": "u018", "kind": "list-item", "locator": "body:L38-L38", "preview": "6. Deallocate every TMEM allocation before kernel exit.", "sha256": "d1938b5098e7b266d47da39e56ea7dab3975b115b4fc0ba3424c3ddf451ac0cd"}, {"id": "u019", "kind": "prose", "locator": "body:L40-L40", "preview": "The allocation operand counts columns. Legal allocation sizes are powers of two from 32 through 512 columns. Allocation can block until the requested TMEM is available; the ISA does not define folklore outcomes such as silent corruption for", "sha256": "f91ee27bb11a3513503232c20e34d34d2a15adafe81323e309113b223563d26a"}, {"id": "u020", "kind": "prose", "locator": "body:L44-L44", "preview": "All allocations share the SM's 512-column capacity. Some useful whole-allocation budgets are:", "sha256": "b4ee5bf23171df60c790b148f9fd3cedc5a56e4433af63ad5d475858f984e163"}, {"id": "u021", "kind": "table-row", "locator": "body:L48-L48", "preview": "| Allocation per stage | Maximum stages if TMEM has no other use | Columns left | | 128 columns | 4 | 0 |", "sha256": "b072c857bef9e2ac11466c7551dd2f9becdd59b4f4673742468fcc36d7d11ebb"}, {"id": "u022", "kind": "table-row", "locator": "body:L49-L49", "preview": "| Allocation per stage | Maximum stages if TMEM has no other use | Columns left | | 256 columns | 2 | 0 |", "sha256": "05a58dad733419c4156a0f06f2154ef8615e852d12525633dfd35418f52a89f3"}, {"id": "u023", "kind": "table-row", "locator": "body:L50-L50", "preview": "| Allocation per stage | Maximum stages if TMEM has no other use | Columns left | | 512 columns | 1 | 0 |", "sha256": "a940200162e3b907c6f8faab934616f673d5f4a5aff941ec4376c3638fdc0f1d"}, {"id": "u024", "kind": "prose", "locator": "body:L52-L52", "preview": "A logical need of 192 columns cannot be requested directly: reserve 256 columns, or suballocate that logical region within another legal power-of-two reservation. Two 256-column accumulator stages consume the entire capacity, so scale-facto", "sha256": "0e50cd966770f36695b446d06e378b73e842ebf0b42c509fa17fea8336fed88c"}, {"id": "u025", "kind": "prose", "locator": "body:L56-L56", "preview": "The relevant mechanisms are distinct:", "sha256": "fc1c5304326b584de63c1c1519794b7e024c06d00ee87b0186768ab05a4c4a4c"}, {"id": "u026", "kind": "list-item", "locator": "body:L58-L58", "preview": "- `tcgen05.commit` attaches completion of prior asynchronous MMA operations to an mbarrier. Wait on that barrier before consuming their results.", "sha256": "1af1167372a70c2f450e4a843b993d8129391f12b1cc1919b4c294825e811e89"}, {"id": "u027", "kind": "list-item", "locator": "body:L59-L59", "preview": "- `tcgen05.wait::ld` and `tcgen05.wait::st` are the completion mechanisms for the corresponding asynchronous TMEM load/store operations.", "sha256": "386820efb8194c8b401e0b7a6a6743e16f245b9eaa180ec26a92080c99e8b34d"}, {"id": "u028", "kind": "list-item", "locator": "body:L60-L60", "preview": "- `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` order tcgen05 operations around a documented execution-ordering handoff. A fence is not an MMA completion wait.", "sha256": "0943cb17d0d11a25cf92c877aadb5c2a5ab386de0329b9466b6895733f0cfa65"}, {"id": "u029", "kind": "list-item", "locator": "body:L61-L61", "preview": "- Producer buffers must remain live until the asynchronous operation that reads them has completed according to its instruction contract.", "sha256": "feb718367dc639669dec4406eae2afadd79207dafd794557fa719986099b240d"}, {"id": "u030", "kind": "prose", "locator": "body:L63-L63", "preview": "CTA synchronization alone does not replace these completion operations.", "sha256": "c9f735b433318be62dcfdac6bd798094eddd61f8b412e8617e21d7ecdb82b89c"}, {"id": "u031", "kind": "prose", "locator": "body:L67-L67", "preview": "`tcgen05.ld` transfers TMEM into registers, and `tcgen05.st` transfers registers into TMEM. Their documented shapes include `.16x64b`, `.16x128b`, `.16x256b`, `.32x32b`, and `.16x32bx2`, with supported repetition qualifiers. There is no sca", "sha256": "00c8ef6aa00691fb742087960b4de34db91b6645935dd58d1869ccc2f1f05775"}, {"id": "u032", "kind": "prose", "locator": "body:L69-L69", "preview": "`tcgen05.cp` performs shaped shared-memory-to-TMEM copies. For example, PTX ISA 9.0 defines this exact form:", "sha256": "9ae8051754c858f6c0e847374738cfc3809f3de06adf5ad59088acdcd4389e5c"}, {"id": "u033", "kind": "code", "locator": "body:L71-L73", "preview": "```ptx tcgen05.cp.cta_group::1.128x256b [taddr], sdesc; ```", "sha256": "31c9dbcff5abb4891536fbccdba342e817b50f428cafdf35cebc02bf54bd30f1"}, {"id": "u034", "kind": "prose", "locator": "body:L75-L75", "preview": "Here `taddr` is the TMEM destination and `sdesc` is the 64-bit shared-memory matrix descriptor. Follow the instruction's asynchronous ordering and completion rules before reusing the source or consuming the destination.", "sha256": "e068f39c91ad4a5696b7fc43d22115ac304f1155eeede678c6d93adc1160eec4"}, {"id": "u035", "kind": "prose", "locator": "body:L79-L79", "preview": "Multiple accumulator stages can overlap MMA production with draining a different, completed TMEM stage. The design is valid only when:", "sha256": "991654cf4559d3b7da1d51e83dcda7db8c0ab1803d8d84734223be63483ea452"}, {"id": "u036", "kind": "list-item", "locator": "body:L81-L81", "preview": "- the combined allocations and suballocations fit the 512-column budget;", "sha256": "17fd8af5790cb5d70bdc34a7f45f8874f12f30b681bea0944af76bc4f3a33768"}, {"id": "u037", "kind": "list-item", "locator": "body:L82-L82", "preview": "- producer and consumer roles use explicit pipeline barriers;", "sha256": "33a31fcf7dce9d220bd55852b4c572cf63e5fa7e983b37d2da40fef011abccd5"}, {"id": "u038", "kind": "list-item", "locator": "body:L83-L83", "preview": "- MMA completion is observed before a consumer drains a stage;", "sha256": "e7c3b8ae852fb631c85ccd5f45b861b4388ae3bdf8d483489d44d8f62fa939be"}, {"id": "u039", "kind": "list-item", "locator": "body:L84-L84", "preview": "- TMEM load completion is observed before register results are used; and", "sha256": "f2ed672764ffffbedc6bd0dabc492b18674a4866746bf6d07551955baee25d50"}, {"id": "u040", "kind": "list-item", "locator": "body:L85-L85", "preview": "- no stage is recycled while an asynchronous operation can still access it.", "sha256": "7da7a6de9e5d7952da1a50d38417f3cc335d39e018c3a67e33e0fc3cf595c69a"}, {"id": "u041", "kind": "prose", "locator": "body:L87-L87", "preview": "This is a pipeline design, not an automatic consequence of alternating two addresses. CUTLASS's version-pinned SM100 tutorials show complete producer/consumer implementations.", "sha256": "d4011413497e52d0dcae86b5ffa75a65ffb125c97d706d62a54ae44b73511e4c"}, {"id": "u042", "kind": "prose", "locator": "body:L91-L91", "preview": "CUTLASS 4.5.0 exposes TMEM through `cutlass.utils.TmemAllocator` and layout-aware CuTe tensors. The official tutorial sequence is:", "sha256": "e18540de26c1c50ab8326e2ae286d0d965df1b58986f5c5eae9076c610e4bebb"}, {"id": "u043", "kind": "list-item", "locator": "body:L93-L93", "preview": "1. create a `TmemAllocator` over shared storage for the allocation result;", "sha256": "a3edc461fce5b5784083dacacd0f1c101b43ca2a85cf79745fece0939240b903"}, {"id": "u044", "kind": "list-item", "locator": "body:L94-L94", "preview": "2. call `allocate(num_columns)` from the configured allocator warp;", "sha256": "292ed99bc0f058be44017f232311ac5c48a4aa2d2d479d9e6e1d01fc3675398c"}, {"id": "u045", "kind": "list-item", "locator": "body:L95-L95", "preview": "3. use `wait_for_alloc()` before other warps retrieve the address;", "sha256": "ce966bcfd9c03d8d2d5ac2362e6a8493e4fa73e2008dea59f9b3b83c8fd2dc52"}, {"id": "u046", "kind": "list-item", "locator": "body:L96-L96", "preview": "4. obtain a typed pointer with `retrieve_ptr(dtype)`;", "sha256": "07e29aa2cd0afb608284d84518f2dd6ca9e0992bce434000e1e795ba8f54c97d"}, {"id": "u047", "kind": "list-item", "locator": "body:L97-L97", "preview": "5. bind that pointer to the MMA accumulator layout with `cute.make_tensor`;", "sha256": "cffb932874a3bf23919dc46c78e281039af766ddac29dcd431edd27a8e57f4db"}, {"id": "u048", "kind": "list-item", "locator": "body:L98-L98", "preview": "6. drain it with `tcgen05` copy atoms and the pipeline's completion protocol; and", "sha256": "2c1a41548f8cadb56da832323b1246a164a9b72881e751bdc28165d0e836fd4b"}, {"id": "u049", "kind": "list-item", "locator": "body:L99-L99", "preview": "7. call `free(tmem_ptr)` before exit.", "sha256": "43514435699f5adeeb0344be0c63200aa778fa36ddef2b0aed2e70ee5579cb83"}, {"id": "u050", "kind": "prose", "locator": "body:L101-L101", "preview": "See the pinned [CUTLASS 4.5.0 FP16 GEMM tutorial](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/python/CuTeDSL/cute/blackwell/tutorial/tutorial_gemm/fp16_gemm_0.py) and [TMEM allocator implementati", "sha256": "ed0773f61bf2f5159b5ba120c90bdf34465bfa942c6d6a4ea55d4fcbd90048ab"}, {"id": "u051", "kind": "list-item", "locator": "body:L105-L105", "preview": "- [PTX ISA 9.0: Tensor Memory](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory)", "sha256": "40744f485d8c843f17e8166199678d16332069d8bcd1fbd4f490d2703e20657a"}, {"id": "u052", "kind": "list-item", "locator": "body:L106-L106", "preview": "- [PTX ISA 9.0: `tcgen05.alloc`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit)", "sha256": "76fb28bfcdeee86b21c8f72d7dc1cb015f9d3ec4e10a6ade0aef7a2eed4df97c"}, {"id": "u053", "kind": "list-item", "locator": "body:L107-L107", "preview": "- [PTX ISA 9.0: `tcgen05.ld`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld)", "sha256": "239281ff0e000a65d4c317dadbe3d2e97a6e2e3a1cb7be5b4fbdabccfe02d633"}, {"id": "u054", "kind": "list-item", "locator": "body:L108-L108", "preview": "- [PTX ISA 9.0: `tcgen05.commit`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen-async-sync-operations-commit)", "sha256": "c69ca2bbb4309efad8d395fa08712c1df40146c6081c9fc7197d604b4a9fb4fa"}, {"id": "u055", "kind": "list-item", "locator": "body:L109-L109", "preview": "- [CUTLASS 4.5.0 SM100 Python tutorial](https://github.com/NVIDIA/cutlass/tree/e406c186f510a15091cce01f782020ceb7ba8eb5/examples/python/CuTeDSL/cute/blackwell/tutorial/tutorial_gemm)", "sha256": "42eee452d016fa75699f23e63de919826e07c0ff194b091beae8c3b06db6ffa9"}], "confidence_claimed": "verified", "headings": ["What TMEM is", "Addressing and warp access", "Allocation lifecycle", "Column budgeting", "Completion and ordering", "Data movement", "Staging accumulators", "CUTLASS 4.5.0 Python DSL", "Primary references"], "id": "hw-tmem", "path": "wiki/hardware/tmem.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}, {"path": "sources/prs/cutlass/PR-2139.md", "revision": "ca4fdbea", "url": "https://github.com/NVIDIA/cutlass/pull/2139"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-ptx-isa-sm100", "pr-cutlass-2139"], "title": "Tensor Memory (TMEM)", "type": "hardware", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "5e2f98b996033253da1252cec281af40f1f858fa39675a8296b17564863d76fe", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "DeepGEMM is DeepSeek's open-source tensor-core kernel library. This page describes the FP8 GEMM paths at commit [`891d57b4db1071624b5c8fa0d1e51cb317fa709f`](https://github.com/deepseek-ai/DeepGEMM/tree/891d57b4db1071624b5c8fa0d1e51cb317fa70", "sha256": "edc884f2b15966309a2f894d85f5e0cc5e7f6e8be752415ddc8b5c870d4fcc8f"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "DeepGEMM contains multiple kernels and APIs; the local SM90 and SM100 files below are representative FP8 1D1D implementations, not the whole library.", "sha256": "07ce76e8768d979abddde871720e0182365b4bdfa27b3ca467b4c1c4d823efb9"}, {"id": "u003", "kind": "prose", "locator": "body:L11-L11", "preview": "The [DeepSeek-V3 Technical Report v2](https://arxiv.org/abs/2412.19437v2) defines the training scheme that motivates this path:", "sha256": "d5d25beeba794a452ddfdbfb7f2711ddecc946602125840ec83ddc44a8a70211"}, {"id": "u004", "kind": "list-item", "locator": "body:L13-L13", "preview": "- activations are grouped per token and per 128 channels, forming `1 x 128` tiles;", "sha256": "d7523bee1428dc93fed5ab553055f979f4a735bf9765274f1071846fe85f6b7a"}, {"id": "u005", "kind": "list-item", "locator": "body:L14-L14", "preview": "- weights are grouped per 128 input channels and 128 output channels, forming `128 x 128` blocks; and", "sha256": "62bb926d275734b391c879539ab2d755a9e8816843dfb6307f76326ddab70563"}, {"id": "u006", "kind": "list-item", "locator": "body:L15-L15", "preview": "- smaller groups let scales adapt more locally, which the paper says better accommodates outliers. This is a scoped accuracy motivation, not a guarantee that quantization error disappears.", "sha256": "ff206a53bb27abcfe054b691bd34313268d95364b3b5358dacc0b02d1a3eb51a"}, {"id": "u007", "kind": "prose", "locator": "body:L17-L17", "preview": "Scale representation is architecture-specific in the pinned DeepGEMM interface. SM90 consumes FP32 scale factors. SM100 consumes packed UE8M0 factors, four UE8M0 values per `torch.int`. The pinned SM90 1D1D kernel fixes `BLOCK_K == 128`; th", "sha256": "e6026ff271a6b450b3b13f3d8add4c8296916a6e5f637c409363b33b5975c990"}, {"id": "u008", "kind": "prose", "locator": "body:L21-L21", "preview": "The DeepSeek-V3 report characterizes H800 FP8 Tensor Core accumulation as retaining about 14 bits. Its `Nc=128` strategy accumulates 128 elements of the GEMM inner dimension\u2014four WGMMAs in the described configuration\u2014before moving the parti", "sha256": "c24f17362025a8f052e005acfbb16c91b9ec59729dff0831ba4ec2b0ff77d245"}, {"id": "u009", "kind": "prose", "locator": "body:L23-L23", "preview": "The pinned [`sm90_fp8_gemm_1d1d.cuh`](../../artifacts/kernels/deepgemm/full/sm90_fp8_gemm_1d1d.cuh) implements that structure directly:", "sha256": "28c625a2df66c12415c1fdbca2c390ce628c03257471e82b88294d81adb12a6e"}, {"id": "u010", "kind": "list-item", "locator": "body:L25-L25", "preview": "1. A math warp-group owns `float accum[...]` for WGMMA output and zero-initialized `float final_accum[...]` for promoted results.", "sha256": "017785087339586990befb86eed10f456ab3fdea6e55f20099e25f7e3aca49af"}, {"id": "u011", "kind": "list-item", "locator": "body:L26-L26", "preview": "2. For each 128-element K block, it reads the A and B FP32 factors from shared memory, issues `BLOCK_K / WGMMA::K` WGMMA operations, commits the group, and waits for completion.", "sha256": "16af9fe856a77026821209080a4bb5d64b1b710abe0540ebb08e107d52a0234a"}, {"id": "u012", "kind": "list-item", "locator": "body:L27-L27", "preview": "3. The `Promote with scales` loop multiplies each partial result by its A and B factors and adds it to `final_accum`.", "sha256": "4c32846882c303ba304d47e97688ddab5d2ff00cf6391d834a2a91bbf4d48ff2"}, {"id": "u013", "kind": "list-item", "locator": "body:L28-L28", "preview": "4. After all K blocks, the kernel stages the final FP32 values for the epilogue/store path.", "sha256": "f7783a1c6fb5faf02bc3b5e1de09015b518d2f5e4cdf3e20f55cca904a2b495d"}, {"id": "u014", "kind": "prose", "locator": "body:L30-L30", "preview": "The exact upstream file is the reproducible reference. It should not be replaced by a sketch using half accumulators or by deriving the promotion interval from WGMMA's output-N tile.", "sha256": "925a0225db7cd7132a69208d817eb1af5a27db511f4f65a66e43b6c105290cd5"}, {"id": "u015", "kind": "prose", "locator": "body:L34-L34", "preview": "The pinned [`sm100_fp8_gemm_1d1d.cuh`](../../artifacts/kernels/deepgemm/full/sm100_fp8_gemm_1d1d.cuh) uses a different data path:", "sha256": "32baacf395d6dca95c445def85a6d35ecd549ba78a9d23a33a0ac511c5b3c116"}, {"id": "u016", "kind": "list-item", "locator": "body:L36-L36", "preview": "1. It creates a block-scaled UMMA instruction descriptor with a `float` accumulator type and `cutlass::float_ue8m0_t` scale type.", "sha256": "e4d0d03fdc026620956fc648d7b9b500f2c77ae9a96e8c85c028f1fa8fa08f86"}, {"id": "u017", "kind": "list-item", "locator": "body:L37-L37", "preview": "2. TMA loads packed scale-factor data into shared memory. UTCCP copies selected scale blocks from shared memory into dedicated SFA and SFB columns in TMEM.", "sha256": "ea3a550a3695844dd1292293e91418bd8514f42d2b2da9c09981584452bfea44"}, {"id": "u018", "kind": "list-item", "locator": "body:L38-L38", "preview": "3. The elected issuing thread calls the SM100 UMMA wrapper with shared-memory operand descriptors, the TMEM accumulator column, a runtime instruction descriptor containing scale IDs, and the two TMEM scale addresses.", "sha256": "e405f66e1b53d88218e2e20a61440d777fcbc83e5db36be347d089df597d0f66"}, {"id": "u019", "kind": "list-item", "locator": "body:L39-L39", "preview": "4. The epilogue drains the TMEM accumulator after the kernel's full/empty barrier protocol says it is ready.", "sha256": "255120ab2662ebea058a8ececcabcbb648e337d16a860d70134dc24994ae88fa"}, {"id": "u020", "kind": "prose", "locator": "body:L41-L41", "preview": "This path does not contain the SM90 `final_accum` CUDA-core promotion loop. That difference does not justify a blanket claim that every tcgen05 accumulator mode or datatype has \"full FP32\" behavior; the accumulator type and instruction form", "sha256": "032e89c865af65e49fd21968c9ccf8e1074c5932b40d2e28b7444d03ed3cb6b8"}, {"id": "u021", "kind": "prose", "locator": "body:L45-L45", "preview": "The pinned interface distinguishes three workload arrangements rather than treating all of them as M-varying layouts:", "sha256": "929dc28b5052e9d9082a478f9145da75cf574dbe40e0fe8ce42d9881ea6fa20d"}, {"id": "u022", "kind": "table-row", "locator": "body:L49-L49", "preview": "| Interface family | Varying group dimension | Fixed dimensions | Work metadata | | M-grouped contiguous | M | N and K | Either a group index for each packed M row or a prefix-sum M layout, depending on the selected option |", "sha256": "f7573a4ed8c1905b6389177ee297f27b173966c755b256e452c45cb74823ae95"}, {"id": "u023", "kind": "table-row", "locator": "body:L50-L50", "preview": "| Interface family | Varying group dimension | Fixed dimensions | Work metadata | | M-grouped masked | Valid M within each `[G, M, K]` allocation | Maximum M, N, and K tensor extents | An integer `masked_m[G]` vector holding each group's va", "sha256": "be7ea9aa4dce872c95db03488e96c249b3c54d4d251596470d9ad9425f682ced"}, {"id": "u024", "kind": "table-row", "locator": "body:L51-L51", "preview": "| Interface family | Varying group dimension | Fixed dimensions | Work metadata | | K-grouped contiguous | K | M and N | Per-group K lengths plus their device tensor; used for weight-gradient-style grouped GEMM |", "sha256": "7310a12d3f4e4e0fda19fded69bf1350f734d99d6e2604faa989f64702635f24"}, {"id": "u025", "kind": "prose", "locator": "body:L53-L53", "preview": "Contiguous M grouping is intended for variable per-expert token counts in training forward or inference prefill. Masked M grouping keeps fixed allocations suitable for CUDA-graph decode while limiting work to each group's valid M. The pinne", "sha256": "70a8f3bbeae80bf8c0c0aac86aa2c0c3660c948dc1df5e3bc0cb1ae46c2dfff2"}, {"id": "u026", "kind": "prose", "locator": "body:L57-L57", "preview": "DeepGEMM generates and compiles kernel source at runtime. At the pinned commit, the compiler defaults to NVCC. Setting `DG_JIT_USE_NVRTC=1` selects the optional NVRTC path; the project warns that this may reduce performance for some cases.", "sha256": "f913b537fa51d19b4b9fcbe96f968fb465d7a606e1e7ec5579ce26905c4995d6"}, {"id": "u027", "kind": "prose", "locator": "body:L59-L59", "preview": "The cache key includes the kernel name, compiler signature, compiler flags, and generated source. A cache hit reuses the existing kernel runtime; a miss compiles a CUBIN in a temporary directory and then publishes the completed cache entry.", "sha256": "b35a525c4472aae9970a77f0af0207eb0b614a25db706f4facec3b0bfcae106e"}, {"id": "u028", "kind": "prose", "locator": "body:L63-L63", "preview": "For the pinned FP8 interface, SM90 supports NT only: A is non-transposed and B is supplied in the representation used for `A @ B.T`. SM100 exposes dense `fp8_gemm_{nt, nn, tn, tt}` variants. Its implementation propagates the selected operan", "sha256": "45eee831267e7730526a83b7bb4f986d8ff85c414f93e0cd755c424951e96ab3"}, {"id": "u029", "kind": "prose", "locator": "body:L67-L67", "preview": "The pinned README reports that DeepGEMM reached **up to 1550 TFLOPS on H800** in an April 2025 news item. It does not bind that peak to `M=N=K=4096`, state approximately 90% utilization, or preserve enough benchmark conditions for reproduct", "sha256": "fc2a0fd111e796b31a0c7e0947d44cc55e0b67eb0dda053f25f0d4dff9835a38"}, {"id": "u030", "kind": "list-item", "locator": "body:L71-L71", "preview": "- Input transposition, FP8 casting, and scale-layout preparation are separate from the optimized GEMM kernels; the project supplies utilities but warns they may be slower than fusing the work into producers.", "sha256": "13b031a9e940905a676b7e3e9b18cbd3d783a31dc4a622a7231e0c33147cdd46"}, {"id": "u031", "kind": "list-item", "locator": "body:L72-L72", "preview": "- M-grouped contiguous segments must satisfy the configured M/K alignment. Masked mode uses valid-length integers, while K-grouped mode has different shapes and architecture-specific layout variants.", "sha256": "a98c5f037a06bb31517448c4705d346c2b1164baca656c828855dfa1b9c179f4"}, {"id": "u032", "kind": "list-item", "locator": "body:L73-L73", "preview": "- JIT cache misses add compilation latency, and NVRTC is optional rather than the default.", "sha256": "baf5e541e3f2c2af10edc3b9a7ea55312df051da85ac772dfced929f7d872e91"}, {"id": "u033", "kind": "list-item", "locator": "body:L74-L74", "preview": "- Fine-grained scaling's accuracy and cost tradeoffs depend on quantization recipe, target architecture, scale preparation, fusion, and workload. There is no universal per-tensor-scaling penalty or single \"use only for outliers\" rule.", "sha256": "f9ee05e0618cef4fc4736191e6043939ccd7187cf5bb95ffcfe425f7633e66ad"}, {"id": "u034", "kind": "list-item", "locator": "body:L78-L78", "preview": "- [DeepGEMM README at commit `891d57b`](https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md)", "sha256": "a8115b879e294785bbc27931facc99142bd71a23cf5bb9c6d0ff177a40b32e03"}, {"id": "u035", "kind": "list-item", "locator": "body:L79-L79", "preview": "- [DeepGEMM GEMM API at commit `891d57b`](https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/apis/gemm.hpp)", "sha256": "6344a99161ed183b81d6f0677ac4d26de38cc9974fed0d20c38bf7432a9ca253"}, {"id": "u036", "kind": "list-item", "locator": "body:L80-L80", "preview": "- [DeepGEMM JIT compiler at commit `891d57b`](https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/csrc/jit/compiler.hpp)", "sha256": "256e0bde5da762844f66e366cd65a297e4093cbaebe7b8369f2d20c4d87aa958"}, {"id": "u037", "kind": "list-item", "locator": "body:L81-L81", "preview": "- [DeepSeek-V3 Technical Report v2](https://arxiv.org/abs/2412.19437v2)", "sha256": "15d831659fae7c38fffb3b6766c08144ff0af11075d3445e73179f7691e7b4e5"}, {"id": "u038", "kind": "prose", "locator": "body:L85-L85", "preview": "Local verbatim upstream code lives in [`artifacts/kernels/deepgemm/full/`](../../artifacts/kernels/deepgemm/full/) and is pinned by [`PROVENANCE.yaml`](../../artifacts/kernels/deepgemm/full/PROVENANCE.yaml) to commit `891d57b4db1071624b5c8f", "sha256": "5fef9de55b64a522e42b6cfb7faad3d0a73df75e4c883e89431c4595916e569f"}, {"id": "u039", "kind": "prose", "locator": "body:L87-L87", "preview": "Query the page and its attached code with:", "sha256": "0da0b6e07247d8d8ebfa9751fbc20aba136debe8f0a07212223182e717bf84d1"}, {"id": "u040", "kind": "code", "locator": "body:L89-L91", "preview": "```bash python3 scripts/get_page.py kernel-deepgemm --include-code ```", "sha256": "a2051b59354d2536049b6650555806c0410635aa728921831a30c1e1855977b1"}, {"id": "u041", "kind": "prose", "locator": "body:L93-L93", "preview": "The following is a verbatim fragment of the SM90 promotion loop; the linked full file supplies its surrounding declarations and loop bounds:", "sha256": "806d5647140f861cdf5ae0117bbbf910630168e069a638198e6ff844f98594ed"}, {"id": "u042", "kind": "code", "locator": "body:L95-L102", "preview": "```cpp const float &scale_b_0 = scales_b[i].x; const float &scale_b_1 = scales_b[i].y; final_accum[i * 4 + 0] += scale_a_0 * scale_b_0 * accum[i * 4 + 0]; final_accum[i * 4 + 1] += scale_a_0 * scale_b_1 * accum[i * 4 + 1]; final_accum[i * 4", "sha256": "7d801ab9fe44c41c62fdf33ba40c8a04c0057328187ea3c19e0f056a5b0ecca0"}], "confidence_claimed": "source-reported", "headings": ["Verified Scope", "Fine-Grained Quantization", "SM90: WGMMA and CUDA-Core Promotion", "SM100: Native Block-Scaled UMMA", "Grouped GEMM Interfaces", "JIT Compilation", "Operand Layouts", "Performance Evidence", "Practical Boundaries", "Pinned Sources", "Full Reference Implementation"], "id": "kernel-deepgemm", "path": "wiki/kernels/deepgemm.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/deepgemm.md", "url": "https://github.com/deepseek-ai/DeepGEMM/tree/891d57b4db1071624b5c8fa0d1e51cb317fa709f"}, {"path": "sources/prs/DeepGEMM/PR-304.md", "revision": "7f2a703e", "url": "https://github.com/deepseek-ai/DeepGEMM/pull/304"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-deepgemm", "pr-deepgemm-304"], "title": "DeepGEMM \u2014 FP8 GEMM with Fine-Grained Scaling", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "eb0beda6d21999eb5a9af51fbb7869f46f78dcb0a29c7d5df1fbde5a0b49b875", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "FlashAttention-4 is an attention algorithm and CuTe DSL implementation designed around Blackwell's asymmetric throughput: B200 tensor-core throughput grows much more than its special-function and shared-memory resources. This page separates", "sha256": "1e410d8f43116d7362371c8f774303c9f6c1f9cf76d3978e901efadfdc47845d"}, {"id": "u002", "kind": "list-item", "locator": "body:L7-L7", "preview": "- the [FA4 paper v1](https://arxiv.org/abs/2603.05451v1), which studies the SM100/B200 algorithm and reports the authors' measurements; and", "sha256": "ff06a9c75bcd69176044dff5a2e64357af716d6fc527b4b5a918cdf9a5cd9a05"}, {"id": "u003", "kind": "list-item", "locator": "body:L8-L8", "preview": "- the public implementation at Dao-AILab/flash-attention commit [`a369df707e1980fb328abcc1733e3457ec10155f`](https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute), which is the source sn", "sha256": "582bae2812e5a0d1842e5dabcaa3a111d9723410fdcb5287165744e1b7b680f9"}, {"id": "u004", "kind": "prose", "locator": "body:L10-L10", "preview": "The paper implementation is written in CuTe DSL. Its compilation comparison is against corresponding FA3 CUTLASS kernels: forward compiles in 2.5 seconds instead of 55 seconds, and backward in 1.4 seconds instead of 45 seconds. Those are si", "sha256": "2266d20d5c09dbaa973f352ea1400662ca84a3b9038021272b1258c9deefc4e0"}, {"id": "u005", "kind": "prose", "locator": "body:L14-L14", "preview": "The forward kernel assigns two output tiles of 128 query rows to one CTA. One MMA warp issues the matrix products, two four-warp softmax groups serve the two output tiles, and a correction warpgroup handles accumulator corrections. The scor", "sha256": "f72a68c72ef30e73a848c40dcf32c36a953ba4f63d07dea896a729aaf5fad961"}, {"id": "u006", "kind": "prose", "locator": "body:L16-L16", "preview": "This is more than ordinary K/V double buffering: the two alternating objects are output tiles with separate softmax state. The exact synchronization and stage ownership are implementation details; the invented one-loop pseudocode formerly o", "sha256": "c191fae7db0b6d0f0e9f84bffa3a6831477e6cfdabf2886659511eed72e8c34a"}, {"id": "u007", "kind": "prose", "locator": "body:L20-L20", "preview": "FA4 does not replace every hardware exponential. The paper selects only about 10-25% of entries for software evaluation on FMA units and leaves the rest on the hardware MUFU `ex2` path, allowing both resources to contribute.", "sha256": "684eaf9635c6bb161d267b05e4f15ce13f54b79e00d86174511b80879bedc800"}, {"id": "u008", "kind": "prose", "locator": "body:L22-L22", "preview": "For a software-selected value, the published range reduction writes `x = n + f` with `n = floor(x)` and `f` in `[0, 1)`, evaluates a degree-3 polynomial for `2**f`, and reconstructs the scale from `n`. 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This is", "sha256": "8d23ff074a9499de040bca63da0fe4d30d194b537de181f4ca508d2bc79bc11a"}, {"id": "u014", "kind": "prose", "locator": "body:L46-L46", "preview": "For dQ, each CTA computes a half of dS and exchanges that half through distributed shared memory so both CTAs can form the required dQ product. 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It also has non-TMA Q and paged-K/V copy paths, so TMA use is not unconditional.", "sha256": "4c5c693b748161d30902f58dbd51ef0a42316b48ac01e7d28f12bcafddee5fea"}, {"id": "u018", "kind": "list-item", "locator": "body:L54-L54", "preview": "- [`flash_bwd_sm100.py`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_bwd_sm100.py) constructs the five backward MMA operations and the two-CTA exchange/reduction pipelines", "sha256": "815a65094e11852de9574447bc0d50adf1df3ad935e82caf224f979c7d21448c"}, {"id": "u019", "kind": "list-item", "locator": "body:L55-L55", "preview": "- The package README describes CuTe DSL attention for Hopper and Blackwell, and the tree contains SM90, SM100, and SM120 dispatch modules. The paper's FA4 result remains SM100/B200-specific; package architecture coverage should not be used ", "sha256": "2cc2823a1a7c188475de9f29140603b203621cbb842f595398a7083e604ffb08"}, {"id": "u020", "kind": "list-item", "locator": "body:L56-L56", "preview": "- The pinned [`pyproject.toml`](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/pyproject.toml) requires `nvidia-cutlass-dsl==4.6.0.dev0`. That is a property of this source snapshot", "sha256": "2560ae01ebeeaa288f2229ebb7f069cf4864ff5ec4988bf4eceb965be3630659"}, {"id": "u021", "kind": "list-item", "locator": "body:L57-L57", "preview": "- Forward and backward accept FP16/BF16. An FP8 benchmark/bring-up script is present, but at this revision it explicitly expects the FA4 FP8 call to fail until support is implemented.", "sha256": "feeb126d7d71e6c313ef6c9da1aab21d2d319602db6e2c3de1fd9437053222c4"}, {"id": "u022", "kind": "prose", "locator": "body:L61-L61", "preview": "The first-party sources contain two different source-reported peak values. Paper v1 reports **up to 1613 TFLOPS/s on B200 BF16, or 71% of the peak convention used by the authors**. Tri Dao's blog reports **up to 1605 TFLOPS/s, also labeled ", "sha256": "1c2e20a8e65ba15f72f872cf74d6a28352ebfb75c641d12fde648b98cf037bd7"}, {"id": "u023", "kind": "prose", "locator": "body:L63-L63", "preview": "The paper's benchmark suite spans sequence lengths from 1K through 32K and multiple query/value head-dimension pairs under a fixed total-token convention. Neither textual source establishes the former single row that attached 1605 TFLOPS, 7", "sha256": "ffecfa7f2cb14d406a31606a14172909bfbbe0db54c419239eb5ae2e8ecb70ed"}, {"id": "u024", "kind": "list-item", "locator": "body:L67-L67", "preview": "- Choose the package path only for a supported architecture, dtype, head-dimension pair, masking mode, and feature set at the exact revision in use.", "sha256": "762ad956d4509aee447615faf6b80f1a258782fafdec6dd079f3e3e3c6ac920d"}, {"id": "u025", "kind": "list-item", "locator": "body:L68-L68", "preview": "- Do not treat sequence length 1024 or head dimension 128 as universal crossover or optimum values. Compare against the relevant cuDNN, framework, or other kernel path on the actual workload.", "sha256": "8375983f1d4f7ce52c849304a3aad867c8c2b667afa82f6b1ebf061cf544f372"}, {"id": "u026", "kind": "list-item", "locator": "body:L69-L69", "preview": "- Compilation speed and runtime speed are separate measurements. The paper's compile comparison does not prove an equivalent runtime factor.", "sha256": "90d8676cddf785613147e85842b741464ae3ae1fb640fd08252120ddd68f6785"}, {"id": "u027", "kind": "list-item", "locator": "body:L70-L70", "preview": "- Treat source-reported B200 numbers as unreproduced unless the same software, clock/power settings, tensor shapes, timing region, warmup, and FLOP convention are available.", "sha256": "896b8ebc0778eb869845e20ff98d507909b34ea91491af6057824a37de4f85a0"}, {"id": "u028", "kind": "list-item", "locator": "body:L74-L74", "preview": "- [FlashAttention-4 paper, arXiv v1](https://arxiv.org/abs/2603.05451v1)", "sha256": "65c89a97ddf06d9514d19588fe1266a84f9ab8f7dc02d57f8732947385eabe66"}, {"id": "u029", "kind": "list-item", "locator": "body:L75-L75", "preview": "- [Tri Dao's FlashAttention-4 blog](https://tridao.me/blog/2026/flash4/)", "sha256": "0c88bc6176d024bb44f1ccb80556697f7868de9d35d59a10546d17b279974d99"}, {"id": "u030", "kind": "list-item", "locator": "body:L76-L76", "preview": "- [FA4 CuTe DSL package at commit `a369df7`](https://github.com/Dao-AILab/flash-attention/tree/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute)", "sha256": "98fa8065e41a96242bc726acab9d3101d53459cf3260434fc27bf76545ee39e5"}, {"id": "u031", "kind": "list-item", "locator": "body:L77-L77", "preview": "- [Pinned SM100 forward source](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_fwd_sm100.py)", "sha256": "4938cdf2c16b4de76f90e1e8a33103be66d267abb2adb5a030d8fc510818857b"}, {"id": "u032", "kind": "list-item", "locator": "body:L78-L78", "preview": "- [Pinned SM100 backward source](https://github.com/Dao-AILab/flash-attention/blob/a369df707e1980fb328abcc1733e3457ec10155f/flash_attn/cute/flash_bwd_sm100.py)", "sha256": "afee82a4bbcd20dd427756fd46204f17af4ce2985c49fe7e4aca940035bb47b6"}, {"id": "u033", "kind": "prose", "locator": "body:L82-L82", "preview": "The local [`full/`](../../artifacts/kernels/flash-attention-4/full/) bundle is a byte-verified, verbatim **adjacent NVIDIA CUTLASS SM100 FMHA backward MLA example**, pinned to CUTLASS commit `0e026982`. It is not the Dao-AILab FA4 implement", "sha256": "a85ac9e12fb38e14987c53ae33ffdfc5ca91b605e4368033767b3b1cecebc738"}, {"id": "u034", "kind": "prose", "locator": "body:L84-L84", "preview": "Query the page and its attached local references with:", "sha256": "38c4142a3241d438fee5d4ab59db0c7c243b0825b789d47c12e6f4d62b2a4092"}, {"id": "u035", "kind": "code", "locator": "body:L86-L88", "preview": "```bash python3 scripts/get_page.py kernel-flash-attention-4 --include-code ```", "sha256": "dbaa5f540bdab5755bcdb9295bc1637f3e10a533091792abfe6b693678d4bd54"}], "confidence_claimed": "source-reported", "headings": ["Verified Scope", "Ping-Pong Forward Schedule", "Partial Software Exponential", "Conditional Softmax Rescaling", "Two-CTA Backward", "Pinned Implementation Notes", "Performance Evidence", "Practical Boundaries", "Pinned Sources", "Local Code References"], "id": "kernel-flash-attention-4", "path": "wiki/kernels/flash-attention-4.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/flash-attention-4.md", "url": "https://arxiv.org/abs/2603.05451v1"}, {"path": "sources/blogs/flash-attention-4.md", "url": "https://tridao.me/blog/2026/flash4/"}], "risk_flags": ["code", "ordering"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-flash-attention-4", "blog-flash-attention-4"], "title": "FlashAttention-4", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "73e3ffa9038dafda7f4083be34a1dabae23531849cb738ba46e7914bfcff9857", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "[Dao-AILab/flash-attention PR 2441](https://github.com/Dao-AILab/flash-attention/pull/2441), merged as [`f219c89c886c6ccbf9d3dbd9fe41b11ac64e9df8`](https://github.com/Dao-AILab/flash-attention/commit/f219c89c886c6ccbf9d3dbd9fe41b11ac64e9df8", "sha256": "4f63a059a81265b7e1cc2d93083303f2ea9498f4b056d7f2855f19c4807dabbf"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "The top-k path is deliberately narrower than a generic paged sparse-attention API. It requires packed GQA/MQA, `qhead_per_kvhead == 128`, and the cp.async K/V gather path. Its constructor defaults to top-k length 2048 and requires the confi", "sha256": "da9c2fe6ef32dd275484f90f2353c35bb3d70a61c4879680f449bfcd5bb081d1"}, {"id": "u003", "kind": "prose", "locator": "body:L11-L11", "preview": "The pinned merge keeps three responsibilities distinguishable:", "sha256": "7c8e584dcb6ba3f5fec244c339c7c94b0aa5316af71a4de934df4270db9bb7f3"}, {"id": "u004", "kind": "list-item", "locator": "body:L13-L13", "preview": "- [`topk_gather_kv.py`](../../artifacts/prs/flash-attention/PR-2441/key-files/flash_attn/cute/topk_gather_kv.py) loads caller-provided top-k indices, forms indexed K/V addresses, issues cp.async copies, and optionally constructs validity bi", "sha256": "73efde420784dfeb2b7aa524d5aa4affeab8241ce307f37e1e5353236b1008f7"}, {"id": "u005", "kind": "list-item", "locator": "body:L14-L14", "preview": "- [`tile_scheduler.py`](../../artifacts/prs/flash-attention/PR-2441/key-files/flash_attn/cute/tile_scheduler.py) supplies the tile-scheduler implementations selected by the MLA kernel.", "sha256": "e609fba486c07cb0513067e5110f4a56712998c460ac1190ae764e870ea1df45"}, {"id": "u006", "kind": "list-item", "locator": "body:L15-L15", "preview": "- [`flash_fwd_mla_sm100.py`](../../artifacts/prs/flash-attention/PR-2441/key-files/flash_attn/cute/flash_fwd_mla_sm100.py) integrates gather, scheduling, two-CTA tcgen05 MMA, TMEM accumulators, softmax, and the output path.", "sha256": "82cb38d28021580714bc04318a4ef997cb376381d574b4edf67e7311c34059d2"}, {"id": "u007", "kind": "prose", "locator": "body:L17-L17", "preview": "This separation matters for evaluation. Arithmetic work follows the effective top-k length, whereas memory addresses follow the caller's index set and use an indexed gather/optional-bitmask path. Reduced attention FLOPs therefore do not pro", "sha256": "2daefc28898a6cce495bbd7fda384f2c0419b4e5882ed996444d0f964d074001"}, {"id": "u008", "kind": "prose", "locator": "body:L21-L21", "preview": "The PR author reports an initial saturating-decode comparison for batch 512, `seqlen_q=1`, `seqlen_k=16384`, 128 query heads, the 64/512 MLA shape, and top-k length 2048:", "sha256": "b3035685847df985b94a47aa4fa504d1371190e34396dde9ccd741363aa0a602"}, {"id": "u009", "kind": "table-row", "locator": "body:L25-L25", "preview": "| Variant | Author-reported latency | Author-reported throughput | | DSA, no bitmask; indices assumed in bounds | 0.31 ms | 955.47 TFLOPS |", "sha256": "a24fbe88c47cc40ebc98942a7df9423dbbbb468b341e1bb5aebed73761544c38"}, {"id": "u010", "kind": "table-row", "locator": "body:L26-L26", "preview": "| Variant | Author-reported latency | Author-reported throughput | | DSA, validity bitmask | 0.33 ms | 898.08 TFLOPS |", "sha256": "e7bf57c1383e05c0ff49169009cdc8f758023a7591f7c01c3ed64e68125b906f"}, {"id": "u011", "kind": "table-row", "locator": "body:L27-L27", "preview": "| Variant | Author-reported latency | Author-reported throughput | | Vanilla MLA baseline | 1.98 ms | 1180.70 TFLOPS |", "sha256": "8955e33c28ba6617ad774374f32687f50790bc825342c54af110832cf10f2fd8"}, {"id": "u012", "kind": "prose", "locator": "body:L29-L29", "preview": "These PR-description observations are not reproduced here. The PR body does not name the exact GPU model, dtype, clocks/power state, software environment, timing protocol, or run-to-run variation for the rows. They therefore remain prose wi", "sha256": "8f464ccdce13dd8c03fcdf509014a32437181e4d6a2d29317aa718b9aadb63fd"}, {"id": "u013", "kind": "list-item", "locator": "body:L33-L33", "preview": "- Confirm the exact MQA packing, 64/512 dimensions, top-k divisibility, index layout, and bounds contract used by the target revision.", "sha256": "0bd5d403083d1c9c0011d53972bb920f173d638cc6297d0fa560921a2d139f9b"}, {"id": "u014", "kind": "list-item", "locator": "body:L34-L34", "preview": "- Treat no-bitmask results as valid only when the caller guarantees every index is in bounds; otherwise preserve the validity path.", "sha256": "b76830a1691f4a2f7e8439909d3a544660928842234c0f5a41c0cb587eca8bdc"}, {"id": "u015", "kind": "list-item", "locator": "body:L35-L35", "preview": "- Do not infer paged-KV compatibility from the exposed parameter name: merge `f219c89c` rejects page tables in this MLA path.", "sha256": "0d852df017b6e52be08f9f98ecc3426541d04f254d3ece4a4dd788bc77df514e"}, {"id": "u016", "kind": "list-item", "locator": "body:L36-L36", "preview": "- Profile indexed-gather traffic and tensor arithmetic separately, then validate end-to-end accuracy and latency on the full workload.", "sha256": "9ab5962234ff3e14f16d030c48e8abf52d8283ce1b4b6c187393bc55d964aeed"}, {"id": "u017", "kind": "prose", "locator": "body:L40-L40", "preview": "The local PR record and byte-verified bundle identify the integration and its dedicated gather file:", "sha256": "47a761a14371c5670c19841d3279cbd73443fbd8a209713016e33d2693199cad"}, {"id": "u018", "kind": "code", "locator": "body:L42-L49", "preview": "```python from pathlib import Path pr_page = Path(\"sources/prs/flash-attention/PR-2441.md\").read_text() provenance = Path(\"artifacts/prs/flash-attention/PR-2441/PROVENANCE.yaml\").read_text() assert \"flash_fwd_mla_sm100.py\" in pr_page assert", "sha256": "cb588e655e6743eac16572e26541b164f2853fd9aa333125fff8febac7bb5298"}], "confidence_claimed": "source-reported", "headings": ["Verified Scope", "Gather and Scheduling Paths", "Source-Reported Performance", "Transfer Checklist", "Reproducible Source Lookup"], "id": "kernel-flash-attention-sm100-mla-topk", "path": "wiki/kernels/flash-attention-sm100-mla-topk.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/prs/flash-attention/PR-2441.md", "revision": "f219c89c", "url": "https://github.com/Dao-AILab/flash-attention/pull/2441"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["pr-flash-attention-2441"], "title": "FlashAttention SM100 MLA TopK Sparse Forward", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "3c4ba2ede0a25c46871912580475e2e71786d53c38b8dea8330b7b017e42d0ae", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "FlashMLA is DeepSeek's attention-kernel library for DeepSeek-V3 and DeepSeek-V3.2-Exp. At pinned commit [`71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232), the library contains MLA-mode decode", "sha256": "08238d87cfdb4314f85a910680b5840280b83bf0cc9e41bd80a02b4cfdb103c3"}, {"id": "u002", "kind": "prose", "locator": "body:L9-L9", "preview": "The DeepSeek-V2 paper describes the model-level reduction in elements cached per layer and token:", "sha256": "90f1ed73430b4cbde8c69c4af03544e62c75f78b7add683720adc84ef20b861f"}, {"id": "u003", "kind": "list-item", "locator": "body:L11-L11", "preview": "- MHA: `2 * n_h * d_h`", "sha256": "3065811e2bcaaead5d63598f5f54ddb3a2a8a65a0d5b1657ff8d27f5a7147e8c"}, {"id": "u004", "kind": "list-item", "locator": "body:L12-L12", "preview": "- MLA: `d_c + d_h^R`, approximately `4.5 * d_h` for its `d_c=4*d_h` and `d_h^R=d_h/2` configuration", "sha256": "075599e94f2e9cf9e3afd1a93903fc330f0193fede80ce16e1ad9c1768b2ece4"}, {"id": "u005", "kind": "prose", "locator": "body:L14-L14", "preview": "These formulas are independent of storage dtype and layer count. They should not be converted to whole-model KB/token figures without naming those additional assumptions.", "sha256": "5679a2621c2ce8aca3375f7bb6c190b8507bced12fa41d172eee9f063a08afda"}, {"id": "u006", "kind": "prose", "locator": "body:L16-L16", "preview": "FlashMLA's **656-byte** layout is narrower: it is the DeepSeek-V3-family FP8 sparse-decode cache ABI, not the definition of an MLA cache. One token contains:", "sha256": "8b83eac13e9ced1937c096c44920f26d7bb029cd81382cc390b1351c2c619b50"}, {"id": "u007", "kind": "table-row", "locator": "body:L20-L20", "preview": "| Region | Representation | Bytes | | NoPE latent data | 512 `float8_e4m3` values | 512 |", "sha256": "841cdc35d7e665175a013bf5bce137a96f0b1702d6a08dc47aa78095460aac24"}, {"id": "u008", "kind": "table-row", "locator": "body:L21-L21", "preview": "| Region | Representation | Bytes | | NoPE group scales | four `float32` values, one per 128 values | 16 |", "sha256": "71b3d01dd719dba8f1ff88f5f1f197a6693308676134668ce2fab9152fa59e46"}, {"id": "u009", "kind": "table-row", "locator": "body:L22-L22", "preview": "| Region | Representation | Bytes | | RoPE data | 64 unquantized `bfloat16` values | 128 |", "sha256": "acd39402aa7de9ad4eb981b9bd203369c56fda205897ab6fa61b2c7a625c0d5a"}, {"id": "u010", "kind": "table-row", "locator": "body:L23-L23", "preview": "| Region | Representation | Bytes | | **Total** | | **656** |", "sha256": "7b8371fda18c965ce82741c5d286f4e1076c5bb5722a40f803b4bde89ec2ce18"}, {"id": "u011", "kind": "prose", "locator": "body:L25-L25", "preview": "Dense decode uses a BF16 cache. The pinned quantization tests also contain a separate 512-dimensional sparse layout, so code must select the model/layout contract rather than assuming 656 bytes universally. `page_block_size` is taken from t", "sha256": "34fe059844fd809f6ef31b60cc8e093bb4c288d0de8db452a89fbe1ddda0c68c"}, {"id": "u012", "kind": "table-row", "locator": "body:L31-L31", "preview": "| Operator | Architecture | Attention mode | Documented cache/input format | | Dense decode | SM90 | MQA (`576/512`) | BF16 paged KV |", "sha256": "d293f5c14941162e3c80a4c205f6461abdb0acb7a357aba82b7bf19f2f2db22a"}, {"id": "u013", "kind": "table-row", "locator": "body:L32-L32", "preview": "| Operator | Architecture | Attention mode | Documented cache/input format | | Sparse decode | SM90, SM100 | MQA (`576/512`) | FP8 KV, dequantized for BF16 MMA; BF16 output |", "sha256": "65e23814a89de7ef621dd455097923d1f3f566b4b2f4051f65b33140950730b1"}, {"id": "u014", "kind": "table-row", "locator": "body:L33-L33", "preview": "| Operator | Architecture | Attention mode | Documented cache/input format | | Dense prefill | SM100 | MHA (`192/128` or `128/128`) | BF16 Q/K/V |", "sha256": "d2d522e04a6d5154570c895e700920708c7a57dd0a136996bbdde85b9cb691b9"}, {"id": "u015", "kind": "table-row", "locator": "body:L34-L34", "preview": "| Operator | Architecture | Attention mode | Documented cache/input format | | Sparse prefill | SM90, SM100 | MQA | BF16 Q and KV |", "sha256": "7d4c68d61d7d6124b0163996c5984745b43d81755a3dbffa98a6ed329f929770"}, {"id": "u016", "kind": "prose", "locator": "body:L36-L36", "preview": "CUDA 12.8 or newer and PyTorch 2.0 or newer are required; the pinned README requires CUDA 12.9 or newer for SM100.", "sha256": "f35e263d91113a6389ad903fab7fa42d70860898334fef8104eb0d3dc67d36c5"}, {"id": "u017", "kind": "prose", "locator": "body:L40-L40", "preview": "Sparse decode receives `indices[batch, s_q, topk]`. Each nonnegative value already encodes a physical page and offset:", "sha256": "5dfe1322da0b2dfe3df8fbe6ed0ece5d000cd1286a6beef0d863746051aa4f73"}, {"id": "u018", "kind": "code", "locator": "body:L42-L44", "preview": "```text encoded = physical_page * page_block_size + offset_in_page ```", "sha256": "5231e8b5e77d4fc668820c802694dfdb284139fc38a77fddae3aef8dc57c3bee"}, {"id": "u019", "kind": "prose", "locator": "body:L46-L46", "preview": "Because the physical page is already encoded, sparse decode does not use `block_table`; `-1` marks an invalid entry. The kernel consumes these indices but does not produce the top-k selection, so an indexing stage outside the attention call", "sha256": "04ac9da24c0828b044f4d7f4d8ca798014651239c97575e1852f78bd95cf7e10"}, {"id": "u020", "kind": "prose", "locator": "body:L48-L48", "preview": "Sparse prefill is a different interface. It receives BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and `indices[s_q,h_kv,topk]`; it has no batch dimension, requires `h_kv=1` in the documented equivalence, and accepts `-1` or values at ", "sha256": "09284ad50c2cab412438ff4567f4f3773d30676a42e6f882fc3e0de26bfdb1db"}, {"id": "u021", "kind": "prose", "locator": "body:L52-L52", "preview": "The following are maxima reported by the pinned first-party README. They were not reproduced here, and the README does not provide complete shape, timing, sample-count, or variance cells, so they are intentionally excluded from structured `", "sha256": "a0ee45c4809bef21a69de293f0ce17990d899829625c2c97508db34adc85e738"}, {"id": "u022", "kind": "table-row", "locator": "body:L56-L56", "preview": "| Operator | Environment stated by source | Precision scope | Author-reported observation | | Dense MLA decode | H800 SXM5, CUDA 12.8 | BF16 cache | Up to 3000 GB/s in a memory-bound configuration; up to 660 TFLOPS in a compute-bound config", "sha256": "29f91ffd6863b1a26ca514240351b3d944b37d1143ee38f4e83180a774a3fb09"}, {"id": "u023", "kind": "table-row", "locator": "body:L57-L57", "preview": "| Operator | Environment stated by source | Precision scope | Author-reported observation | | Sparse MLA decode | H800 SXM5, CUDA 12.8 | FP8 KV, BF16 MMA | 410 TFLOPS in a compute-bound configuration |", "sha256": "9764016bfae45c9128dd978cf206509cf6b2448ec5602b05a403d0642521afe0"}, {"id": "u024", "kind": "table-row", "locator": "body:L58-L58", "preview": "| Operator | Environment stated by source | Precision scope | Author-reported observation | | Sparse MLA decode | B200; software version not stated in the row | FP8 KV, BF16 MMA | Up to 350 TFLOPS; the author says it was not well optimized ", "sha256": "c818b558acbb7ed171090bb6661eaaf4400cd8a3666a57fc1b7761aad8436b48"}, {"id": "u025", "kind": "table-row", "locator": "body:L59-L59", "preview": "| Operator | Environment stated by source | Precision scope | Author-reported observation | | Dense MHA prefill | B200; NVIDIA-reported | BF16 inputs | Up to 1460 TFLOPS forward and 1000 TFLOPS backward |", "sha256": "9a9d5d7fc032bd9e83da289de902bbf1535e3c996a3f8ba5210f76906dec57f0"}, {"id": "u026", "kind": "table-row", "locator": "body:L60-L60", "preview": "| Operator | Environment stated by source | Precision scope | Author-reported observation | | Sparse MLA prefill | H800 SXM5, CUDA 12.8 | BF16 inputs | Up to 640 TFLOPS forward |", "sha256": "53d0b78b4866316334e4a20763250f5c5fab57171f7c843f7722b12794bda70f"}, {"id": "u027", "kind": "table-row", "locator": "body:L61-L61", "preview": "| Operator | Environment stated by source | Precision scope | Author-reported observation | | Sparse MLA prefill | B200, CUDA 12.9 | BF16 inputs | Up to 1450 TFLOPS forward |", "sha256": "6ff6f1fdd66ca72895d490f8c0607ddf8e1df1df56d7fd8f12aed022c8527a79"}, {"id": "u028", "kind": "prose", "locator": "body:L63-L63", "preview": "The numbers compare different operators, phases, shapes, precision scopes, and machines. In particular, `1460` is dense MHA prefill, not a replacement for the `660` dense-MLA-decode observation.", "sha256": "e5a0dbf189f061c878b4cae1b5a7048e458381ff9fc70b5229b92828896acc57"}, {"id": "u029", "kind": "prose", "locator": "body:L67-L67", "preview": "The pinned DeepSeek SM100 sources use TMA, `tcgen05` tensor-core operations, and TMEM in specialized sparse-decode/prefill and dense-MHA-prefill code. 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The [`variants/`](../../artifacts/kernels/flashmla/variants/) directory contains a small KernelWiki-derived layout/index helper, explicitly marked as non-upstream. For the", "sha256": "37b693efa9f5daa2cf92e3b9434f64d04bd1a1159c2c7f697461898614ff707e"}, {"id": "u034", "kind": "list-item", "locator": "body:L78-L78", "preview": "- Match the operator family, `d_qk/d_v`, architecture, CUDA version, cache dtype, and index shape exactly.", "sha256": "1f8f834f7ce3ce7eca28b0eb611071ec978c248ae82042c4f293e78b9710b8cc"}, {"id": "u035", "kind": "list-item", "locator": "body:L79-L79", "preview": "- Treat the 656-byte layout as a V3-family FP8 sparse-decode ABI, not a generic MLA property.", "sha256": "a6abb77196519f2420b0a762e095773a8b5c77f40b2ee203ec99fd16ce3abe25"}, {"id": "u036", "kind": "list-item", "locator": "body:L80-L80", "preview": "- Generate sparse indices before invoking FlashMLA and validate invalid-index/page encoding rules.", "sha256": "0ca8b8e69996a2e86619b01c4abc06f895da7e1a18d8bd095f31ffe0ad454823"}, {"id": "u037", "kind": "list-item", "locator": "body:L81-L81", "preview": "- Benchmark the target decode or prefill workload; do not transfer TFLOPS or bandwidth across the table's distinct regimes.", "sha256": "f75121f6f51ee2d76e0ec793123df0743909bccb3bbf06e7ff84fe69b2682390"}, {"id": "u038", "kind": "list-item", "locator": "body:L82-L82", "preview": "- Validate output and LSE against the repository reference before relying on throughput.", "sha256": "13d8121c830496708430c92fd8de8b4fc8517137efec46a16fdb5566da14a859"}, {"id": "u039", "kind": "list-item", "locator": "body:L86-L86", "preview": "- [DeepSeek FlashMLA at audited commit `71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232)", "sha256": "0de9535be0d6d149c00340e2638776319f26831cdee6a72ee9c9fe208d2761b9"}, {"id": "u040", "kind": "list-item", "locator": "body:L87-L87", "preview": "- [DeepSeek-V2 MLA paper, v5](https://arxiv.org/html/2405.04434v5)", "sha256": "67b77a2f9ec951fd7db140185b5eedc21e2c3d8c8fa615da68632b6ee1075c44"}, {"id": "u041", "kind": "list-item", "locator": "body:L88-L88", "preview": "- [CUTLASS PR 2466, SM100 MLA-shape backward](https://github.com/NVIDIA/cutlass/pull/2466)", "sha256": "0e7eede9e2ae4d56aae5f8797c6118fbbbe1859478a97294d44e70db06ec8ee1"}, {"id": "u042", "kind": "list-item", "locator": "body:L89-L89", "preview": "- [CUTLASS PR 2472, SM100 MLA-shape forward](https://github.com/NVIDIA/cutlass/pull/2472)", "sha256": "ea1ffa911f1b9bfd82df419873ec8deed230cbd340899b68a493ef7db213d13a"}, {"id": "u043", "kind": "prose", "locator": "body:L91-L91", "preview": "Query the page and its labeled artifacts with:", "sha256": "f5116cccd6a53f501df19ca2264a4ecc72b0e1cdbd130894bdf4cc89c362ef66"}, {"id": "u044", "kind": "code", "locator": "body:L93-L95", "preview": "```bash conda run -n base python scripts/get_page.py kernel-flashmla --include-code ```", "sha256": "7bc0deaa394726c6a68dd18d167067b318bd1716043acfa1e49b6793d677009c"}, {"id": "u045", "kind": "prose", "locator": "body:L97-L97", "preview": "The mode-specific byte arithmetic can be checked without a GPU:", "sha256": "3ad75e7b4793a8c3389c0175106203e303b590c71caf9e9c606fa07a6c4428b6"}, {"id": "u046", "kind": "code", "locator": "body:L99-L108", "preview": "```python # KernelWiki-derived contract check; not upstream FlashMLA code. def v3_fp8_sparse_bytes() -> int: nope_bytes = 512 scale_bytes = 4 * 4 rope_bytes = 64 * 2 return nope_bytes + scale_bytes + rope_bytes assert v3_fp8_sparse_bytes() ", "sha256": "a3c4914434151f616abf1963f00adbf0e98f53973f559a7d54967a7b0f7b2e3c"}], "confidence_claimed": "source-reported", "headings": ["Scope", "MLA Cache Reduction Versus a Concrete Cache ABI", "Supported Paths at `71c7379`", "Sparse Contracts", "Source-Reported Performance", "SM100 Implementation Notes", "Selection and Validation Checklist", "Sources and Local Query"], "id": "kernel-flashmla", "path": "wiki/kernels/flashmla.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/flashmla.md", "url": "https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232"}, {"path": "sources/docs/deepseek-v2-mla.md", "url": "https://arxiv.org/abs/2405.04434v5"}, {"path": "sources/prs/cutlass/PR-2466.md", "revision": "0e026982", "url": "https://github.com/NVIDIA/cutlass/pull/2466"}, {"path": "sources/prs/cutlass/PR-2472.md", "revision": "9baa06dd", "url": "https://github.com/NVIDIA/cutlass/pull/2472"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-flashmla", "doc-deepseek-v2-mla", "pr-cutlass-2466", "pr-cutlass-2472"], "title": "FlashMLA \u2014 Multi-head Latent Attention", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "5c0369ba45f1bfcc220967e83d4765f7e8b56908a310a1bf0356e9bb2c996e70", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "The DeepSeek-V3 training recipe quantizes forward activations per `1x128` tile and weights per `128x128` block. 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expert parallelism | 8 | `256 / 32` ranks in the published definition |", "sha256": "c8110af705992d3b500544c8283f2149d07f0b61bb0e7d2eb3b9a47b1c3006af"}, {"id": "u006", "kind": "table-row", "locator": "body:L15-L15", "preview": "| Field | Value | Meaning | | `top_k` | 8 | Selected global experts per token |", "sha256": "701a714491b6d44c4bdaf8ce3d4267a0be3dd9a838e889f963f29c96ba2da59b"}, {"id": "u007", "kind": "table-row", "locator": "body:L16-L16", "preview": "| Field | Value | Meaning | | `n_group` | 8 | Groups of 32 global experts |", "sha256": "5f46d8298cd7f3e8e9d21f875d1f5924b6cd1074db5eba13f0fdeb0c6d0d1817"}, {"id": "u008", "kind": "table-row", "locator": "body:L17-L17", "preview": "| Field | Value | Meaning | | `topk_group` | 4 | Groups retained before global top-k selection |", "sha256": "527a38b3ef12c6bde36175a483564ad6c5cafe7704a00b97ceaedef2c4c9cd3e"}, {"id": "u009", "kind": "table-row", "locator": "body:L18-L18", "preview": "| Field | Value | Meaning | | hidden size | 7168 | Input and output width |", "sha256": "54e08f4f881e5c89526ffbe3b836b2356c8f3d62502fac07571f4d119f3358ef"}, {"id": "u010", "kind": "table-row", "locator": "body:L19-L19", "preview": "| Field | Value | Meaning | | intermediate size | 2048 | Per-expert SwiGLU width |", "sha256": "0ce89dc7a715c664bb87be41e1d21dfb81be33c180bf130ca6016fdfeb3bb0ee"}, {"id": "u011", "kind": "table-row", "locator": "body:L20-L20", "preview": "| Field | Value | Meaning | | GEMM1 output | 4096 | Concatenated W13 output, `2 * 2048` |", "sha256": "5c686849f46d9f7b44e9e1ee43efe1ceaa4668e29bda28a0cc4f8842cfa33d39"}, {"id": "u012", "kind": "table-row", "locator": "body:L21-L21", "preview": "| Field | Value | Meaning | | scale block | 128 | Fixed granularity for this DeepSeek-FP8 trace |", "sha256": "d1e5a1c8c5c7c963f36ab5fc093ade0e8927e34ebe5f2f5ffa18a5862183b023"}, {"id": "u013", "kind": "prose", "locator": "body:L23-L23", "preview": "The `e32` suffix means **32 local experts**, not 32 total experts.", "sha256": "001cf0ce8a59e9e29df693e403576c4d03447c4f9682265f4b571f1828177834"}, {"id": "u014", "kind": "prose", "locator": "body:L27-L27", "preview": "For `T = seq_len`, the published benchmark signature is:", "sha256": "737ed711ebf0a7140acfc7a8cab6f37d5f0ea8a77c0085292675844f26e7e74c"}, {"id": "u015", "kind": "table-row", "locator": "body:L31-L31", "preview": "| Input | Dtype | Shape | | `routing_logits` | FP32 | `[T, 256]` |", "sha256": "ebc301e873d88834130b18c076ac974b142065b79907dfd1f98b160ef7f232d1"}, {"id": "u016", "kind": "table-row", "locator": "body:L32-L32", "preview": "| Input | Dtype | Shape | | `routing_bias` | BF16 | `[256]` |", "sha256": "bcad38d96f0c6feac0ec3bb267624a4bc1c16f57f261031a7f29e6eb8da880d0"}, {"id": "u017", "kind": "table-row", "locator": "body:L33-L33", "preview": "| Input | Dtype | Shape | | `hidden_states` | FP8 E4M3FN | `[T, 7168]` |", "sha256": "bfb153078bcae7b3e69fe5de92d4edb832a264671a102886e2d2a320c4f6ea99"}, {"id": "u018", "kind": "table-row", "locator": "body:L34-L34", "preview": "| Input | Dtype | Shape | | `hidden_states_scale` | FP32 | `[56, T]` |", "sha256": "ec4bec489db7f5fce3b61e3e1747ecbd18c30c063b557a5bfcb5c20d512722fc"}, {"id": "u019", "kind": "table-row", "locator": "body:L35-L35", "preview": "| Input | Dtype | Shape | | `gemm1_weights` | FP8 E4M3FN | `[32, 4096, 7168]` |", "sha256": "24269b2c4d8cfe693e764fd54dfd1eafdc57616ea155cc3b8502138b1c9d9ea4"}, {"id": "u020", "kind": "table-row", "locator": "body:L36-L36", "preview": "| Input | Dtype | Shape | | `gemm1_weights_scale` | FP32 | `[32, 32, 56]` |", "sha256": "f4e5562976a2cf05bb99c60098e7f9d596b5a3cd59d749a6ba082028da0a37b6"}, {"id": "u021", "kind": "table-row", "locator": "body:L37-L37", "preview": "| Input | Dtype | Shape | | `gemm2_weights` | FP8 E4M3FN | `[32, 7168, 2048]` |", "sha256": "3a489fb55046bcfe271ac63e38346248a7bd6ad7a116d4992738d0a853ef2ffc"}, {"id": "u022", "kind": "table-row", "locator": "body:L38-L38", "preview": "| Input | Dtype | Shape | | `gemm2_weights_scale` | FP32 | `[32, 56, 16]` |", "sha256": "2c1d01b228f14c9f210eed1f920111406117344ee9bd24cd14033623ae06e443"}, {"id": "u023", "kind": "table-row", "locator": "body:L39-L39", "preview": "| Input | Dtype | Shape | | `local_expert_offset` | INT32 | scalar |", "sha256": "9f61941d2f2c8b538b6e5943fae9de3253c2a8a16e803ef74fca6ea3f343f6a6"}, {"id": "u024", "kind": "table-row", "locator": "body:L40-L40", "preview": "| Input | Dtype | Shape | | `routed_scaling_factor` | FP32 | scalar |", "sha256": "45c2c5da5cafe1e777345bd9b5dddcb9507ed68d91079ab886f275c556cefc30"}, {"id": "u025", "kind": "prose", "locator": "body:L42-L42", "preview": "The output is BF16 `[T, 7168]`. These scale tensors are explicit storage inputs; this page does not infer their runtime cost from their existence.", "sha256": "29d8f9c0cd8e3cc789f0c79fe0466d03269314a7c1be853882d9ab25e3004baf"}, {"id": "u026", "kind": "prose", "locator": "body:L44-L44", "preview": "This derived helper makes the fixed shape arithmetic executable without pretending to encode FlashInfer's physical layouts:", "sha256": "f5cfd21000618d145880cf47d79989f120bce90aadb2093820bd177df828a846"}, {"id": "u027", "kind": "code", "locator": "body:L46-L61", "preview": "```python def track_a_shapes(tokens: int) -> dict[str, tuple[int, ...]]: assert tokens > 0 return { \"routing_logits\": (tokens, 256), \"hidden_states\": (tokens, 7168), \"hidden_states_scale\": (7168 // 128, tokens), \"gemm1_weights\": (32, 2 * 20", "sha256": "ecbb997f0664e8b26ef95d1baab5c4bdeaa20c737ccc6c532d90123fac4cd4be"}, {"id": "u028", "kind": "prose", "locator": "body:L63-L63", "preview": "At FlashInfer commit `7f614b86470180bab2d22e36fd1775791c6bf3e6`, the corresponding public entry point is `flashinfer.fused_moe.trtllm_fp8_block_scale_moe`. Its complete call includes the eight tensors above plus `num_experts=256`, `top_k=8`", "sha256": "9c3a9fd3260dc9da7f6ecf5ccc39d149dcb6a903af942158546e10489b32fd3e"}, {"id": "u029", "kind": "prose", "locator": "body:L67-L67", "preview": "The official reference performs these steps:", "sha256": "69ce47bf087e8ec43d4a017de654b2adcee5426fdc4873b0c0a0e2b44b78a2d7"}, {"id": "u030", "kind": "list-item", "locator": "body:L69-L69", "preview": "1. Convert routing logits to `s = sigmoid(logits)` and form selection scores `s + routing_bias`.", "sha256": "3a336cf3dad815c822d8e002d8dd323c7e07e17b50547f448e040bafd885de53"}, {"id": "u031", "kind": "list-item", "locator": "body:L70-L70", "preview": "2. Reshape 256 scores into eight groups of 32. Sum the top two selection scores in each group, then retain four groups.", "sha256": "6b360ceba71fa8a57766d24eaa3ca8d86046b6171c1d410ce3c19e4be76aee4a"}, {"id": "u032", "kind": "list-item", "locator": "body:L71-L71", "preview": "3. Select eight global experts from the retained groups using the biased selection scores.", "sha256": "11b6dce51cdc636939c8f51b1e46572fe134d200e051272c53c2c59bf13b4534"}, {"id": "u033", "kind": "list-item", "locator": "body:L72-L72", "preview": "4. Form combine weights from the **unbiased** sigmoid values for those eight experts, normalize per token, and multiply by `routed_scaling_factor`.", "sha256": "894f6b0f253fe79c3ec06beb426083fff0499b2824bf87bbda3e96a40c4692d3"}, {"id": "u034", "kind": "list-item", "locator": "body:L73-L73", "preview": "5. For global expert IDs in `[local_expert_offset, local_expert_offset + 32)`, dequantize the relevant activation and weight blocks, compute one W13 projection, split its 4096 columns into two 2048-column halves, apply SwiGLU, and compute W", "sha256": "11671de6844ef72df08d28569ecd72a6d4f81714708312cb527c2cfcbed5510c"}, {"id": "u035", "kind": "list-item", "locator": "body:L74-L74", "preview": "6. Accumulate each local expert result into the token output using that expert's combine weight. Experts outside the local interval contribute nothing on that rank.", "sha256": "94aff12c1b0fd4c8ffcce3f97b9d20436416bd6b958791ca29293066d3a8509c"}, {"id": "u036", "kind": "prose", "locator": "body:L76-L76", "preview": "The W13 representation permits one logical `A @ W13.T` followed by a split. It does not require two separately allocated TMEM accumulators, and the benchmark contract does not prescribe a tcgen05 instruction sequence.", "sha256": "3e1f2f7efc222f4fcd494a9c8f4c0c4cd901badb958318c4f8e60fcf6d6c8784"}, {"id": "u037", "kind": "prose", "locator": "body:L80-L80", "preview": "[`01-routing-plus-fusion-skeleton.py`](../../artifacts/kernels/fused-moe/variants/01-routing-plus-fusion-skeleton.py) is a CPU-checkable, parameterized reference for grouped selection and local W13/SwiGLU/W2 accumulation. It is derived Kern", "sha256": "5bba28addcad2283879b25fb8696bf9be4d51a9ee49b8133a9f12bec14bf1853"}, {"id": "u038", "kind": "prose", "locator": "body:L84-L84", "preview": "The starter-kit evaluation document at commit `75ccd05cafceb0fd1f86be4cd0f2117249463c66` records:", "sha256": "cde284ee48fbdd748f8d3600e66c7ed2497287762035e914798400ff58e76db6"}, {"id": "u039", "kind": "list-item", "locator": "body:L86-L86", "preview": "- bare-metal NVIDIA B200 (`sm_100a`) with clocks locked to `3996,1965`;", "sha256": "7a75f41e06a4d80bd5efe0b54130a8d0d51fea02a0a481c349034c605fec1995"}, {"id": "u040", "kind": "list-item", "locator": "body:L87-L87", "preview": "- container `flashinfer/flashinfer-ci-cu132:20260401-2c675fb`;", "sha256": "664e4bf418b4433598ddd3b63587c5a7fbd5032aa5d703f03fcbfd59e9b59d40"}, {"id": "u041", "kind": "list-item", "locator": "body:L88-L88", "preview": "- CUDA 13.2, Python 3.12, PyTorch 2.12.0+cu132, and Triton 3.6.0;", "sha256": "8f2cdf7f92d9320af77e430548deb1e4a0c44ecd153c72aec5af59d9b51bed06"}, {"id": "u042", "kind": "list-item", "locator": "body:L89-L89", "preview": "- correctness gates `atol=1`, `rtol=0.3`, and matched ratio `0.9` for the MoE command; and", "sha256": "3dd94426d3da0fbbcd98a12ab3f69353a043fbdeda9a53737c85fc6c8324a6ac"}, {"id": "u043", "kind": "list-item", "locator": "body:L90-L90", "preview": "- an arithmetic mean of per-workload `FlashInfer baseline latency / candidate latency` as the single-definition MoE score.", "sha256": "4de08486e0d7f77210459b4a263cd093943ef5d7facc52f44330e366a8fd83f1"}, {"id": "u044", "kind": "prose", "locator": "body:L92-L92", "preview": "The current primary sources do not support the former framework TFLOPS/latency table, its launch counts, or the structured 1262-TFLOPS record. No performance result is retained here. The official trace axis is `seq_len`; relabeling its endp", "sha256": "2a74e722e8395c0bd3a36f6db147654d36e575ab03bc89b76451f3193502d75d"}, {"id": "u045", "kind": "list-item", "locator": "body:L96-L96", "preview": "- Routing produces different token counts per expert, hence different grouped-GEMM M dimensions. A scheduler can mitigate that imbalance; no single bottleneck is universal across token counts and tactics.", "sha256": "4509252cba2ad79785ad002e88756ca7547dcded8949e062f02b0159cdeb7799"}, {"id": "u046", "kind": "list-item", "locator": "body:L97-L97", "preview": "- Small M or partially filled GEMM tiles can reduce utilization. This is a workload-dependent risk, not a retained performance result.", "sha256": "778b5bf014aeac4c0a4c0bbc62ec34555e7b986c03a88beab2e204ff4d198183"}, {"id": "u047", "kind": "list-item", "locator": "body:L98-L98", "preview": "- At the pinned FlashInfer revision, runtime autotuning enumerates valid tactics and selects GEMM1 and GEMM2 tactics over token buckets. Record the exact revision and tuning state in any measurement.", "sha256": "f81de9fa798fe72ce83f43a6c0161e4a6bee5347a381db18bfc7767aee91b202"}, {"id": "u048", "kind": "list-item", "locator": "body:L99-L99", "preview": "- The FP8 element type alone is insufficient for compatibility. Routing method, global/local expert mapping, scale dtype and granularity, tensor layout, activation, and output semantics must all match.", "sha256": "7fa8a79649e679c66099456a574a461b2d8a93822d78cc19407dc800cf27174c"}, {"id": "u049", "kind": "list-item", "locator": "body:L100-L100", "preview": "- CUDA-graph layout requirements are backend-specific. DeepGEMM's masked grouped layout is one documented decode case when the CPU does not know expert token counts; it is not a universal graph requirement.", "sha256": "1b726ae4f1e45208d34afba797a4104fc1687728707f7a82b976fcc90e9bcec1"}, {"id": "u050", "kind": "list-item", "locator": "body:L101-L101", "preview": "- TMA alignment depends on the tensor-map configuration. CUDA 13.2.1 requires a 64-byte-aligned tensor-map object and ordinarily a 16-byte-aligned global base, with additional requirements for selected interleave, dtype, and swizzle modes; ", "sha256": "c489192b4d16ba711c6b5070c6f199816b5ca1ca31d2eca0880d8b3700ba4f60"}, {"id": "u051", "kind": "prose", "locator": "body:L105-L105", "preview": "The files under [`full/`](../../artifacts/kernels/fused-moe/full/) are mixed **adjacent references**, not a full implementation of this benchmark:", "sha256": "91e526c7370778ef42f7ef4e5d413af9fc8ce67b7ba844c2d32247386429a4d8"}, {"id": "u052", "kind": "list-item", "locator": "body:L107-L107", "preview": "- `vllm-PR-23696-dual-gemm.patch` is the aggregate merged diff for vLLM's MXFP4-weight fused expert-compute integration (BF16 activations on Hopper and MXFP8 activations on Blackwell).", "sha256": "eb444460ff069d31acae33faebd1748acbca31b3314448454b206450136a7227"}, {"id": "u053", "kind": "list-item", "locator": "body:L108-L108", "preview": "- `flashinfer_cutedsl.py` is byte-identical to an SGLang FP4 CuteDSL runner at commit `c554dc5c64b661f2c53225b03a76359eaddc39e4`.", "sha256": "4637e22f808fa7be197ed05bf39999b3faef048bfcc7d170b174045f5f9285e7"}, {"id": "u054", "kind": "list-item", "locator": "body:L109-L109", "preview": "- `moe-grouped-gemm-launch.cpp` is local illustrative pseudocode for varying per-expert M segments.", "sha256": "ce5f3f3207b6fccc92cbbd767ab21e5019b9dd4875f37d8ccbeebb95df5387d2"}, {"id": "u055", "kind": "prose", "locator": "body:L111-L111", "preview": "None supplies the exact Track A FP8 implementation or substantiates performance/launch claims. Their hashes and exact scopes are recorded in the bundle provenance.", "sha256": "3185281cb5115e4e603b66baf2ef9a9182277ac604d0c1f3542a0654e29f064d"}, {"id": "u056", "kind": "list-item", "locator": "body:L115-L115", "preview": "- [MLSys 2026 FlashInfer contest](https://mlsys26.flashinfer.ai/)", "sha256": "ab9d2391f0df03c8f838cf0749ecc9726e2d2d3dcb8b884ea6b7375a47370484"}, {"id": "u057", "kind": "list-item", "locator": "body:L116-L116", "preview": "- [Exact FP8 MoE benchmark definition](https://bench.flashinfer.ai/kernels/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048)", "sha256": "419456d967a9985601dbcaf552faa63a40fd1b1d7b83c31d08a20aaaf87158c0"}, {"id": "u058", "kind": "list-item", "locator": "body:L117-L117", "preview": "- [Starter-kit evaluation contract at `75ccd05`](https://github.com/flashinfer-ai/flashinfer-bench-starter-kit/blob/75ccd05cafceb0fd1f86be4cd0f2117249463c66/EVALUATION.md)", "sha256": "52ca433ee6415278862ce222bb43c605d0c133517e6d0abce32e8221ad225165"}, {"id": "u059", "kind": "list-item", "locator": "body:L118-L118", "preview": "- [FlashInfer trace reference at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/trace/templates/moe.py)", "sha256": "8cb3c878949322786ae8d9707896d528775d5cd7441e618252145f01bc31265d"}, {"id": "u060", "kind": "list-item", "locator": "body:L119-L119", "preview": "- [FlashInfer API implementation at `7f614b8`](https://github.com/flashinfer-ai/flashinfer/blob/7f614b86470180bab2d22e36fd1775791c6bf3e6/flashinfer/fused_moe/core.py)", "sha256": "bd2e86c0528a00b0e278588ee1708fab986c461ffb0f5991e414b6b325d24bd1"}, {"id": "u061", "kind": "list-item", "locator": "body:L120-L120", "preview": "- [CUDA 13.2.1 tensor-map requirements](https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html)", "sha256": "9b0de5e25bc10f3d939d8e71de0c30e132b9e3d13375dea6dbe04499bbeccfa7"}, {"id": "u062", "kind": "list-item", "locator": "body:L121-L121", "preview": "- [CUTLASS efficient-GEMM small-dimension discussion](https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/efficient_gemm.md)", "sha256": "4b8edf9932c5821c5b961c770a55f0ce93b8a5ad8b5dbde632639d6ecb14be2b"}, {"id": "u063", "kind": "list-item", "locator": "body:L122-L122", "preview": "- [DeepGEMM grouped-layout documentation at `891d57b4`](https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/README.md)", "sha256": "52f8e92ca35c41e0413de525aa48ca4351f19d3d790f77ef8c0ac67f59ef158d"}, {"id": "u064", "kind": "prose", "locator": "body:L124-L124", "preview": "Query the page and its explicitly labeled artifacts with:", "sha256": "b0d28b74774c0b84d20fed48deff776c39a4c6fcda541d401cebc50ea98a12fd"}, {"id": "u065", "kind": "code", "locator": "body:L126-L128", "preview": "```bash python3 scripts/get_page.py kernel-fused-moe --include-code ```", "sha256": "56fc790420908106565f83ed31ab8a2fe1aa1e849fce411f2babc6c449629082"}], "confidence_claimed": "source-reported", "headings": ["Scope", "Fixed Benchmark Geometry", "Tensor Contract", "Reference Semantics", "Small Derived Reference", "Official Evaluation Boundary", "Implementation Risks That Must Be Measured", "Adjacent Local Artifacts", "Sources"], "id": "kernel-fused-moe", "path": "wiki/kernels/fused-moe.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/contests/flashinfer-mlsys26/track-a-fused-moe.md", "url": "https://mlsys26.flashinfer.ai/"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-flashinfer-track-a"], "title": "FlashInfer Track A FP8 Block-Scale MoE", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "2ed46cc12dc31743da8142c69d5a8c6b3d03b077d1ddd624e2e4351206734b68", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Gated DeltaNet is a recurrent linear-attention architecture published at ICLR 2025. For one head with state `S` shaped `[K,V]`, the FlashInfer reference at commit `7f614b8` implements the update in this equivalent form:", "sha256": "7f1a002328cc8b9c3b1f6c35a1deef36116d2a1d4096548aa30b3067c801835f"}, {"id": "u002", "kind": "code", "locator": "body:L7-L16", "preview": "```python def gdn_step(S, q, k, v, A_log, a, dt_bias, b, scale): g = exp(-exp(A_log) * softplus(a + dt_bias)) beta = sigmoid(b) decayed = g * S read = k @ decayed S_new = decayed + outer(k, beta * (v - read)) output = scale * (q @ S_new) re", "sha256": "238655628f5620f295796b5458731e1de971b0b1ccdfa2a0d61e2b06b3fa42e0"}, {"id": "u003", "kind": "prose", "locator": "body:L18-L18", "preview": "The subtraction is the delta-rule correction: the update moves the value retrieved at `k` toward `v`, while `g` independently decays the previous state. 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"claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "The official NVIDIA rules identify NVFP4 Gated Dual GEMM as Kernel Challenge 3 of the Blackwell NVFP4 Hackathon, open from December 20, 2025 through January 16, 2026. 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The task explicitly labels the final column a speed-of-light analysis based on the maximum of B200 FP4 Tensor Core math time and DRAM-memory time at a 1.5 GHz clock. These values ", "sha256": "dbd703852dc16a02bacb2b9359f855f7cc6bb5aedbbe12766b5359b12b4c3df3"}, {"id": "u017", "kind": "prose", "locator": "body:L45-L45", "preview": "The shared `a` and `sfa` inputs create an opportunity to reuse data across the two products, and a genuinely fused epilogue can avoid writing both full-precision products to global memory. Those are optimization possibilities, not task guar", "sha256": "b9506a581d543f3f3449095a2de708afaf0cc2d3a4074808d129cf966b6143d6"}, {"id": "u018", "kind": "prose", "locator": "body:L47-L47", "preview": "The public task/reference does not establish a final leaderboard, winning source, single-launch decomposition, physical load count, TMEM accumulator partition, TMA pipeline, CUTLASS schedule, or compute-/memory-bound classification. If an i", "sha256": "7eebde5afbe8c3125f5c62849cf9a347608afc921f13de479637aa8d16a48e84"}, {"id": "u019", "kind": "prose", "locator": "body:L49-L49", "preview": "Compatibility is correspondingly narrower than \u201cany dual-output operation\u201d: a model/backend must match the two same-shaped NVFP4 products, scale storage and layouts, first-branch SiLU, FP16 output, batching, and divisibility rules. Grouped ", "sha256": "de73a447abc831be11c8a20216e9aa9deb202edda82ffd8e4b5fc04f855730f1"}, {"id": "u020", "kind": "prose", "locator": "body:L53-L53", "preview": "The `full/` bundle contains the byte-pinned official `task.yml` from commit `c5b2f7c`; it is the problem specification, not an optimized submission. The unrelated third-party schedule extract and duplicate vLLM MXFP4 MoE patch formerly stor", "sha256": "a38ab1c3e4bbe45a644a36ccc7d310f1d64e15abe5098570c0957bb0d2796105"}, {"id": "u021", "kind": "prose", "locator": "body:L55-L55", "preview": "The `variants/` bundle contains a standard-library semantic reference for two small dense products followed by `SiLU(gate) * up`. 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It carries 40% of the four-problem grand-prize score. The corrected public task at", "sha256": "1639b7acf7b23b5b3321612131bdeb27e99062306a5f8603dfffeed74f69e18d"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "\u201cGrouped GEMM\u201d does not imply one universal shape contract. Two relevant interfaces differ materially:", "sha256": "5b62624db91dbdc4fd13581947cfda51890c1a7856fb2d73124be674dbe12784"}, {"id": "u003", "kind": "list-item", "locator": "body:L9-L9", "preview": "- The GPU Mode challenge accepts a list of independent problems; `M_i`, `N_i`, and `K_i` can all differ by group.", "sha256": "b9b8d88536cad39bc38b2372af39b03590aa774e4505cb406874ddcaa776f659"}, {"id": "u004", "kind": "list-item", "locator": "body:L10-L10", "preview": "- DeepGEMM's M-grouped MoE APIs vary M while holding N and K fixed. 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Each `b` is stored as `[N,K]`, so its rows are the columns of the mathematical right operand:", "sha256": "c320379f94fb28a61cb7701495a1d6932da8855cefe44c8cff6bbf150cb886ae"}, {"id": "u016", "kind": "code", "locator": "body:L33-L45", "preview": "```python def grouped_reference(groups): outputs = [] for a, b in groups: k = len(a[0]) if any(len(row) != k for row in a) or any(len(row) != k for row in b): raise ValueError(\"ragged or incompatible K\") outputs.append([ [sum(x * y for x, y", "sha256": "d4407b78235c5840c595cce75e98468022e0ca987e0d8fc61a22a961b679a537"}, {"id": "u017", "kind": "prose", "locator": "body:L47-L47", "preview": "It models neither NVFP4 packing nor block scales; those remain part of the challenge ABI above.", "sha256": "db4cf3e6019dbe5437fe573745b89e7c26bd66bf1eb1bde7f5476bee73e47323"}, {"id": "u018", "kind": "prose", "locator": "body:L51-L51", "preview": "The following shapes describe the pinned FP8/FP4 grouped APIs; scale tensors and layout conversions are additional required inputs.", "sha256": "b668b60f58e395720c62a89ca031cf80584385c6778c5de7785c935b7919a176"}, {"id": "u019", "kind": "table-row", "locator": "body:L55-L55", "preview": "| Mode | Main tensors | Group descriptor | Documented role | | M-grouped contiguous | A `[M,K]`, B `[G,N,K]`, D `[M,N]` | `grouped_layout` is either one expert ID per packed row (with `-1` padding) or one prefix-sum end per group | Training", "sha256": "3edecad8eeab41879305a4720468fe2b3a039c304de9a2f6ed4b2f7554929c39"}, {"id": "u020", "kind": "table-row", "locator": "body:L56-L56", "preview": "| Mode | Main tensors | Group descriptor | Documented role | | M-grouped masked | A `[G,Mmax,K]`, B `[G,N,K]`, D `[G,Mmax,N]` | `masked_m` is one int32 valid-row count per group | CUDA-graph decode; fixed allocation while computing valid po", "sha256": "afe0b21b4ba74a5b245f7b7473fa0a5db9141c4c404a861f5e32a9ee39ab9a09"}, {"id": "u021", "kind": "table-row", "locator": "body:L57-L57", "preview": "| Mode | Main tensors | Group descriptor | Documented role | | K-grouped contiguous | packed A `[sum(K_i),M]`, B `[sum(K_i),N]`, D `[G,M,N]` | host and device K-size lists; optional C has `[G,M,N]` | MoE weight backward; M/N fixed |", "sha256": "3e21ac0d9e7eca36eedbde09c1f5b847faa5edff155b273eb488f4168043f2ea"}, {"id": "u022", "kind": "prose", "locator": "body:L59-L59", "preview": "These are concrete library contracts, not generic C++ structs. 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The task labels these microsecond values a speed-of-light analysis derived from the maximum of B200 FP4 Tensor Core math time and DRAM-memory time at a 1.5 GHz clock. They are theoretical comparison values, ", "sha256": "6465beb0e7a292f48bf4e830c3442e6a8b1a8b71c37567dc903a1a346d91299a"}, {"id": "u028", "kind": "prose", "locator": "body:L74-L74", "preview": "GPU Mode's official postmortem records a submission that temporarily reached the number-one leaderboard position with a reported `11.191 \u00b5s`, roughly `2 \u00b5s` ahead of the next entry, and was scrubbed minutes after the competition.", "sha256": "b537c11c34b663ab971a605f55df3a11f215899dc99d34622e205983403d5c10"}, {"id": "u029", "kind": "prose", "locator": "body:L76-L76", "preview": "During correctness, it ran a real padded 8-group kernel on each of 15 cloned data objects. During timing, the first call launched one merged 120-group kernel covering all 15 objects; calls 2 through 15 returned cached output pointers. The h", "sha256": "fb7cc6e225efe9c103ee51aa0acf7fcb118fd3215154625920012cf1d6418a1c"}, {"id": "u030", "kind": "prose", "locator": "body:L78-L78", "preview": "The official post points to `gpu-mode/reference-kernels` PR #104 as the harness response. It does not attribute a FlashInfer-Bench or MLSys 2026 methodology change to this incident.", "sha256": "af363322f4bd273ed6d9542a802080bb526828195a6a0717566c17eb3054ab47"}, {"id": "u031", "kind": "prose", "locator": "body:L82-L82", "preview": "The public challenge constrains outputs, tolerances, workloads, and scoring. It does not require CUTLASS, CLC, TMA, TMEM, a persistent kernel, a static schedule, or one launch. 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Compare quality, sequence distribution, memory use, and measured latency or throughput on the target workload.", "sha256": "c9ee5b9ee579038f32902b7284d069a8b03a8a5513560bf99a3c9b4caddf92d9"}, {"id": "u026", "kind": "list-item", "locator": "body:L84-L84", "preview": "- CUDA Graphs can reduce repeated-launch CPU overhead, but they are not an NSA-specific default. Profile first: NVIDIA's guidance says the largest gains occur for CPU-bound workflows and that GPU-bound workloads may see little benefit or re", "sha256": "f9b6df5ef4f3f131f00c87890ba79a225234505a177ddf9f29eae775645f6938"}, {"id": "u027", "kind": "list-item", "locator": "body:L85-L85", "preview": "- The compression MLP adds learned parameters and computation. The paper does not isolate a standalone cost for that component.", "sha256": "9ccd7326bd68872d3e7c3e4f9753cb1a498f16f8e6fc032eac6fba3b8475a883"}, {"id": "u028", "kind": "list-item", "locator": "body:L86-L86", "preview": "- The paper notes that a Triton implementation can retain abstraction overhead relative to native CUDA; it does not publish an NSA-specific CPU-launch profile.", "sha256": "f6435058cc76f46ad9f41b109905a67f7e096f67dce91f53dc284c7fd4d1f671"}, {"id": "u029", "kind": "list-item", "locator": "body:L90-L90", "preview": "- [NSA in the ACL 2025 Anthology](https://aclanthology.org/2025.acl-long.1126/)", "sha256": "78ccf4813ea3076dc266e56c039c186998cec537ae12c990098355ca1dd0affc"}, {"id": "u030", "kind": "list-item", "locator": "body:L91-L91", "preview": "- [ACL proceedings PDF](https://aclanthology.org/2025.acl-long.1126.pdf)", "sha256": "13864f984b34a739b22354671bf40b7b132a4a92b1fe709c69c18516a3157473"}, {"id": "u031", "kind": "list-item", "locator": "body:L92-L92", "preview": "- [DeepSeek-V3.2-Exp at pinned commit 87e509a](https://github.com/deepseek-ai/DeepSeek-V3.2-Exp/tree/87e509a2e5a100d221c97df52c6e8be7835f0057)", "sha256": "495799eeb9bf66dfb26c143f0617fa51bb3eafc0b83db9a0ecbf52e94f45bd9f"}, {"id": "u032", "kind": "list-item", "locator": "body:L93-L93", "preview": "- [FlashMLA at pinned commit 71c7379](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232)", "sha256": "9a703d254eb11b0c82694980bf3ace79260d5a522fbbc81e75e1d5c838cc0273"}, {"id": "u033", "kind": "list-item", "locator": "body:L94-L94", "preview": "- [NVIDIA CUDA Graph performance troubleshooting](https://docs.nvidia.com/dl-cuda-graph/troubleshooting/performance-issues.html)", "sha256": "f07028fb31a610923a456920862ac95e7fe74dbbb90917e2ee033cc76d23f1d9"}, {"id": "u034", "kind": "list-item", "locator": "body:L95-L95", "preview": "- [Third-party lucidrains PyTorch implementation](https://github.com/lucidrains/native-sparse-attention-pytorch)", "sha256": "4ac2ee874ac52c888f894dbe154072fa140f783aefe6c722c45a6b7eaf2cfd00"}, {"id": "u035", "kind": "code", "locator": "body:L99-L101", "preview": "```bash conda run -n base python scripts/get_page.py kernel-nsa ```", "sha256": "1f78b6b3ff77dec53e1ab9848cec6dad73d5a38e2591afa12472b71b618f4c82"}], "confidence_claimed": "source-reported", "headings": ["Verified scope", "Exact three-branch mechanism", "Executable branch-combination reference", "Paper-described Triton design", "Source-reported efficiency", "NSA is not the later DSA deployment", "Applicability and boundaries", "Primary sources", "Query"], "id": "kernel-nsa", "path": "wiki/kernels/nsa.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nsa.md", "url": "https://aclanthology.org/2025.acl-long.1126/"}, {"path": "sources/blogs/flashmla.md", "url": "https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-nsa", "blog-flashmla"], "title": "Native Sparse Attention (NSA)", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "174e77c3133c6b67914db0e72ccf06349e86c0818a834cc8196e0965554d776c", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "The official NVIDIA rules identify NVFP4 GEMM as Kernel Challenge 2 of the Blackwell NVFP4 Hackathon. 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E2M1 represents zero and signed magnitudes 0.5, 1, 1.5, 2, 3,", "sha256": "2d3e513162b32573b229edb6791eca5c968c25d20a763fc0c6728bee7623a754"}, {"id": "u004", "kind": "prose", "locator": "body:L13-L13", "preview": "The contest ABI is narrower and does not expose the generic recipe's FP32 global scales. Its actual generated input has seven tensors:", "sha256": "3a871dd4a928094b50b5397043bcb0ed40b4ca720015ca6f28f00940abc8308f"}, {"id": "u005", "kind": "table-row", "locator": "body:L17-L17", "preview": "| Tensor | Published representation | Physical shape | | `a` | packed E2M1, two values per byte | `[M,K/2,L]` |", "sha256": "e0a7789d78d69b33651c32ed0b1322da6a51ce99701fb8c4f691c1d606ca1e27"}, {"id": "u006", "kind": "table-row", "locator": "body:L18-L18", "preview": "| Tensor | Published representation | Physical shape | | `b` | packed E2M1, two values per byte | `[N,K/2,L]` |", "sha256": "7d0102d70ed8d43681e30199436e1a4ca93f82176a713d1a4eb60f915d82a32b"}, {"id": "u007", "kind": "table-row", "locator": "body:L19-L19", "preview": "| Tensor | Published representation | Physical shape | | `sfa` | logical E4M3 scales | `[M,K/16,L]` |", "sha256": "8c6e7b8cc27b3f4659878a193b0d177ad42556861e9af3c56bf8dd190847c87d"}, {"id": "u008", "kind": "table-row", "locator": "body:L20-L20", "preview": "| Tensor | Published representation | Physical shape | | `sfb` | logical E4M3 scales | `[N,K/16,L]` |", "sha256": "53f0052f4f81c4ddb14c0a6d49f8abbe1ee49fffe56a0e6600ba2e4690d9a1fc"}, {"id": "u009", "kind": "table-row", "locator": "body:L21-L21", "preview": "| Tensor | Published representation | Physical shape | | `sfa_reordered` | MMA-oriented scale copy | `[32,4,ceil(M/128),4,K/64,L]` |", "sha256": "fdccc0a2063460171c6874f7b71b04aa81f8547a6adf6647394f30407ad2130f"}, {"id": "u010", "kind": "table-row", "locator": "body:L22-L22", "preview": "| Tensor | Published representation | Physical shape | | `sfb_reordered` | MMA-oriented scale copy | `[32,4,ceil(N/128),4,K/64,L]` |", "sha256": "dc780d607c17c5380f0d0cf88b406360fc63691f9131f5658c4666fe6a431427"}, {"id": "u011", "kind": "table-row", "locator": "body:L23-L23", "preview": "| Tensor | Published representation | Physical shape | | `c` | preallocated FP16 output | `[M,N,L]` |", "sha256": "5bb5aa5ac7ba2bf79f1a086d297ae8bf6ac71c70fd93ef7176c42f472b856b8b"}, {"id": "u012", "kind": "prose", "locator": "body:L25-L25", "preview": "For each `L` slice, the correctness reference computes the block-scaled equivalent of `A @ B.T` and stores FP16 output. It uses `rtol=1e-3` and `atol=1e-3`.", "sha256": "6f3e0ffc95c1f7cfbba0f5cce8d4ad5cf98e730c2518d3f862973484eb5cd357"}, {"id": "u013", "kind": "prose", "locator": "body:L27-L27", "preview": "The upstream files contain two interface inconsistencies that implementations must not conceal:", "sha256": "2ead2f5e8d44bc8c68f365c286a7d40895ac73ad636d88cfbbf74c8456754f89"}, {"id": "u014", "kind": "list-item", "locator": "body:L29-L29", "preview": "- `task.yml` describes a five-member `(a,b,sfa,sfb,c)` tuple, while `task.py`, `template.py`, and `reference.py` expose the seven tensors above.", "sha256": "b1ab36d41d8414867d0fd4b868add90d1552fb037fa289b4952ffc5335fe9025"}, {"id": "u015", "kind": "list-item", "locator": "body:L30-L30", "preview": "- Task and template prose label scale tensors E4M3FNUZ, while `reference.py` constructs `torch.float8_e4m3fn` values. A submission must follow the tensors supplied by the actual harness rather than treating those suffixes as interchangeable", "sha256": "60a30abca2b8e35e3e85f9529afad31c41f9e672f64a665c9cab4c93db10e6cb"}, {"id": "u016", "kind": "prose", "locator": "body:L34-L34", "preview": "The published task requires `K` divisible by 256. Divisibility of `M` and `N` depends on the submission's selected MMA tile. The following CPU-only helper reproduces the published storage shapes; it does not decode FP4, apply scales, or mod", "sha256": "b665b4c6d8030c332f28c4d3ee158ae219b6d15795bdaee05374861dbc13385b"}, {"id": "u017", "kind": "code", "locator": "body:L36-L58", "preview": "```python def task_storage_shapes(m, n, k, l=1): if min(m, n, k, l) <= 0: raise ValueError(\"dimensions must be positive\") if k % 256: raise ValueError(\"K must be divisible by 256\") return { \"a_packed\": (m, k // 2, l), \"b_packed\": (n, k // 2", "sha256": "7642131a89d5b771cbf27494b4cc0b80cd0cf33ee914733ba4332b41646dc052"}, {"id": "u018", "kind": "prose", "locator": "body:L60-L60", "preview": "Nine of the ten official correctness shapes fail the former `(K/16) % 128 == 0` assertion, including the smallest valid case with `K=256`.", "sha256": "05437858b45314ea93e0a0104ea46596c3ea7d49d2c24ae53df396395c1074ae"}, {"id": "u019", "kind": "prose", "locator": "body:L64-L64", "preview": "The native Blackwell instruction path supports block-of-16 NVFP4 through `tcgen05.mma...kind::mxf4nvf4.block_scale.block16`. It uses UE4M3 scale elements, which CUTLASS names `float_ue4m3_t`; UE8M0 is the MXFP4 scale type. Converting NVFP4 ", "sha256": "5c735c80238f43b67916629af854f0bc5ebe3cbdc2a5dd8c6884eb7c0e838112"}, {"id": "u020", "kind": "prose", "locator": "body:L66-L66", "preview": "CUTLASS defines `KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100`, but its direct official example is a grouped pointer-array kernel. The symbol's existence is not evidence that the contest entrants used it. CUTLASS's current official NVFP4 ex", "sha256": "ab4df04cd09ce423053e72e6743e8bd87ad2ec87bbac6cc6a67fcdf80f74f1bb"}, {"id": "u021", "kind": "prose", "locator": "body:L68-L68", "preview": "TMA likewise has no universal 128-byte alignment rule for every operand. CUDA 13.2.1 generally requires a 16-byte-aligned global base and 16-byte-multiple strides for a tiled tensor map, with additional datatype-, interleave-, swizzle-, and", "sha256": "3ccf1a1511937dc90f14ec1f46a7a6da76096f2e80ebf2b09b6040f7c8715278"}, {"id": "u022", "kind": "prose", "locator": "body:L70-L70", "preview": "TMEM's 128-lane by 512-column organization is a storage and addressing model, not a universal 128-by-512 logical output-tile limit. Official CUTLASS NVFP4 configurations include a cooperative two-SM MMA tile with logical shape 256 by 256 by", "sha256": "9146b8a20d4fa3e2d61f9fc78dbb921c708e685affa23cd507b61539ba3c289d"}, {"id": "u023", "kind": "prose", "locator": "body:L74-L74", "preview": "The task ranks the geometric mean across three benchmark cases. It labels the following values a speed-of-light analysis based on the maximum of B200 FP4 Tensor Core math time and DRAM-memory time at a 1.5 GHz clock:", "sha256": "1333ed27524466513afa4aa3d6b2aca56e71b8dd321380468992191a08483324"}, {"id": "u024", "kind": "table-row", "locator": "body:L78-L78", "preview": "| M | N | K | L | Theoretical time (\u00b5s) | | 128 | 7168 | 16384 | 1 | 8.994 |", "sha256": "ac29495b16a50fe1cfa2dcde5a85eb0fbc58049c674a2acd145386cdf9509a03"}, {"id": "u025", "kind": "table-row", "locator": "body:L79-L79", "preview": "| M | N | K | L | Theoretical time (\u00b5s) | | 128 | 4096 | 7168 | 1 | 2.354 |", "sha256": "5830e08d67630c0aa4612f11749d003bd0e8772b58d5696ff74cb0b2383e0fe2"}, {"id": "u026", "kind": "table-row", "locator": "body:L80-L80", "preview": "| M | N | K | L | Theoretical time (\u00b5s) | | 128 | 7168 | 2048 | 1 | 1.333 |", "sha256": "fa3e79cd0999f76fee4e1016298889112f86cae481bb308bf85adc53cba145e9"}, {"id": "u027", "kind": "prose", "locator": "body:L82-L82", "preview": "These are theoretical comparison rows, not measured contestant latencies and not cuBLAS results.", "sha256": "e7cccec1a9469a76f5310902e63e0ff426f9cdfb679295d05b973561c5a59ba8"}, {"id": "u028", "kind": "prose", "locator": "body:L84-L84", "preview": "The public Popcorn endpoint currently gives the following dated snapshot. To make its small floating-point `submission_score` values readable beside the task's microsecond presentation, the table shows `submission_score \u00d7 10^6`; it does not", "sha256": "ca5d81241e455f5afedd1cd83c9e5f33b6ce5ffd65e4fc6dbee310fe12e17238"}, {"id": "u029", "kind": "table-row", "locator": "body:L88-L88", "preview": "| Current rank | User | API score \u00d7 10^6 | Submission timestamp (UTC) | | 1 | `gau.nernst` | 9.981889 | 2025-12-21 00:43:03 |", "sha256": "fe02ccfff7ba7a01f611de399274d94df3fc34621f9c1f49f0b4661b1049fc8e"}, {"id": "u030", "kind": "table-row", "locator": "body:L89-L89", "preview": "| Current rank | User | API score \u00d7 10^6 | Submission timestamp (UTC) | | 2 | `s.am._` | 10.060110 | 2025-12-20 17:45:21 |", "sha256": "3b924272968baecf2642aff9df9a27f543bf3a3ec76b865ad5651e3dfc27ae46"}, {"id": "u031", "kind": "table-row", "locator": "body:L90-L90", "preview": "| Current rank | User | API score \u00d7 10^6 | Submission timestamp (UTC) | | 3 | `billcarson` | 10.137411 | 2025-12-21 03:05:32 |", "sha256": "682d0b4289aaf64c4a8dfce794ab877797b0f27e2dfbdb0558cd5b91020e7ea6"}, {"id": "u032", "kind": "table-row", "locator": "body:L91-L91", "preview": "| Current rank | User | API score \u00d7 10^6 | Submission timestamp (UTC) | | 8 | `Simon` | 10.806750 | 2025-12-16 20:18:42 |", "sha256": "532478b666f20292d73ffe2cf7b1d1e68503fdadedf372b6bc068566201ba1ca"}, {"id": "u033", "kind": "table-row", "locator": "body:L92-L92", "preview": "| Current rank | User | API score \u00d7 10^6 | Submission timestamp (UTC) | | 9 | `yue` | 10.914084 | 2025-12-11 04:36:45 |", "sha256": "390d4818810b01ab386a95f2b688d3b0e6b496b5c99251c2597eee2fffca1387"}, {"id": "u034", "kind": "table-row", "locator": "body:L93-L93", "preview": "| Current rank | User | API score \u00d7 10^6 | Submission timestamp (UTC) | | 10 | `currybab` | 10.930623 | 2025-12-19 08:10:18 |", "sha256": "b20e53b276da79e3e8db64ea4bc8792ffde6e7159c74d43fdd475df2f464a8d0"}, {"id": "u035", "kind": "prose", "locator": "body:L95-L95", "preview": "Snapshot fetched August 8, 2026. Because the current first three submissions postdate the official December 19 cutoff, this endpoint alone cannot establish winners or final prize rankings. It also publishes no contestant source, CUTLASS att", "sha256": "31d7de708031defe935bf9ec093e7e4e609515f457b21a57edaae459c012889a"}, {"id": "u036", "kind": "prose", "locator": "body:L99-L99", "preview": "Use this task contract only when the packed E2M1 payloads, logical and reordered scales, transpose convention, FP16 output, tolerances, and B200 target match the workload. \u201cFour-bit weights\u201d alone is insufficient: INT4, MXFP4, other scale g", "sha256": "73cdc11c5d684987ddca4b7d6b757fa05f35817fafcc4b69fab11eb85fdadbea"}, {"id": "u037", "kind": "prose", "locator": "body:L101-L101", "preview": "The documented native tensor-core path is Blackwell-specific; Hopper has no native FP4 tensor-core instruction. This does not exclude software conversion or emulation. Choose TMA, TMEM allocation, CUTLASS schedules, warp specialization, til", "sha256": "44a9079d9bde40b4b9d9f4314563b36497b2c4c3baf8f73d63b50ba622654431"}, {"id": "u038", "kind": "list-item", "locator": "body:L105-L105", "preview": "- [Official contest rules](https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf)", "sha256": "c945d69cc0933ee89c1418170925a1dac08b34aa49c449aff8fab2f67960ab55"}, {"id": "u039", "kind": "list-item", "locator": "body:L106-L106", "preview": "- [Pinned task definition](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.yml)", "sha256": "e65c352f0be491a3018d9832b9eb33f9a20999ed3c89f8073d9b51d7b05ab736"}, {"id": "u040", "kind": "list-item", "locator": "body:L107-L107", "preview": "- [Pinned task types](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/task.py)", "sha256": "3fd0cff1732ff2946231c340cdb3f1e603f51d9e30c1d38d02c5bdd5e97047cc"}, {"id": "u041", "kind": "list-item", "locator": "body:L108-L108", "preview": "- [Pinned starter template](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/template.py)", "sha256": "f0c85282243b89d3b5178d653b7368861f3c8179b8902ccb2d8cf362e007ba1f"}, {"id": "u042", "kind": "list-item", "locator": "body:L109-L109", "preview": "- [Pinned correctness reference](https://github.com/gpu-mode/reference-kernels/blob/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm/reference.py)", "sha256": "a9913b0ecd262bdf9fc1ed22d8ba73b0df684b9d60385ea92765cefada05884c"}, {"id": "u043", "kind": "list-item", "locator": "body:L110-L110", "preview": "- [Public Popcorn leaderboard API](https://site--bot--dxfjds728w5v.code.run/submissions/nvfp4_gemm/NVIDIA?limit=12)", "sha256": "05fc2df13c95fa5525c4bc583dfe7fbd3d792d5b56bd9701b72b2005410eba68"}, {"id": "u044", "kind": "list-item", "locator": "body:L111-L111", "preview": "- [Transformer Engine 2.13 NVFP4 recipe](https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html)", "sha256": "6a8a7f25f33afde1adc5eb40bedd91ec6b208700f493f6716ab59dda9d710f87"}, {"id": "u045", "kind": "list-item", "locator": "body:L112-L112", "preview": "- [cuBLAS block-scaling formats](https://docs.nvidia.com/cuda/cublas/index.html#element-1d-block-scaling-for-fp8-and-fp4-data-types)", "sha256": "835625f4c0a79e2e00ed840ffb666c21b6794ec80c63ba082abf75c3ac010c1f"}, {"id": "u046", "kind": "list-item", "locator": "body:L113-L113", "preview": "- [PTX ISA 9.0 block-scaled `tcgen05.mma`](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma)", "sha256": "0eae676c73ff2a26b0c7f4700430e3d5418c17442c24232d71e63edb3926281d"}, {"id": "u047", "kind": "list-item", "locator": "body:L114-L114", "preview": "- [Pinned CUTLASS NVFP4 example](https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu)", "sha256": "673b6e03246cef1e9406aab15f2e173b99d155e39e94f235480d949ea32a846e"}, {"id": "u048", "kind": "list-item", "locator": "body:L115-L115", "preview": "- [Pinned CUTLASS grouped NVFP4 example](https://github.com/NVIDIA/cutlass/blob/e05f953a5b3d38adc240df2ff928e0421c2abba3/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu)", "sha256": "072f9f025862aacd8fa196a463d4a6c65ad7f4c07ffc75f84a2e3230b331ecd9"}, {"id": "u049", "kind": "list-item", "locator": "body:L116-L116", "preview": "- [CUDA 13.2.1 tensor-map constraints](https://docs.nvidia.com/cuda/archive/13.2.1/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html)", "sha256": "2ce8fa29f655906e7c265b4f2dcf842b58186c862ebf8809d5b5e51ecc9f5225"}, {"id": "u050", "kind": "prose", "locator": "body:L118-L118", "preview": "Query via:", "sha256": "6abd63e508f9320fdd3b2b0cc5b5f6a000f4462abfd17f9ecc3c4818f4a0f875"}, {"id": "u051", "kind": "code", "locator": "body:L120-L122", "preview": "```bash conda run -n base python scripts/get_page.py kernel-nvfp4-gemm ```", "sha256": "48df91e99487c982432b8d227c4d314527b5a7a8f1814e19da626a790ab563a4"}], "confidence_claimed": "verified", "headings": ["Verified scope", "Format recipe versus task ABI", "Host-checkable shape contract", "Blackwell implementation boundary", "Published performance records", "Applicability", "Primary sources"], "id": "kernel-nvfp4-gemm", "path": "wiki/kernels/nvfp4-gemm.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/contests/gpu-mode-nvfp4/problem-2-gemm.md", "url": "https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemm"}, {"path": "sources/docs/nvidia-transformer-engine-2.13-nvfp4.md", "url": "https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html"}, {"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}, {"path": "sources/docs/nvidia-cuda-13-0-2-tma.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#asynchronous-data-copies-using-the-tensor-memory-accelerator-tma"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-gpumode-p2", "doc-transformer-engine-2.13-nvfp4", "doc-ptx-isa-sm100", "doc-cuda-13-0-2-tma"], "title": "NVFP4 GEMM \u2014 GPU Mode Problem 2 Contract", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "15a1de756e23c26b7938e4b0c5e12e918492d5f204e504a428fcb1573c5bbd26", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "GPU Mode's Problem 1 asks for a block-scaled NVFP4 batched matrix-vector product on NVIDIA B200. The official task models its three benchmark cases against the slower of FFMA math and DRAM transfer time and reports DRAM-limited theoretical ", "sha256": "14e1c04988eab77eb5fda24b66c9161c6b4819d6a72816cd82aa24e0a228b98e"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "The logical operation has one B row, reused by all M output rows. The reference harness pads B and its scales to 128 rows so it can call `torch._scaled_mm`, then retains only result column zero. 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The task prose labels scales `e4m3fnuz`, but the pinned generator constructs `torch.float8_e4m3fn`; implementations should follow the actual harne", "sha256": "9d23ed25965f166e208682143b1379b4a346ef123a4f513c3160a28f289fbe68"}, {"id": "u012", "kind": "prose", "locator": "body:L27-L27", "preview": "The official table assumes a 1.5 GHz B200 clock and ranks submissions by the geometric mean across all three rows:", "sha256": "181b1e55fb5b84d28814d49c47efc252c00f59b87529df6181d4be0f24168dcc"}, {"id": "u013", "kind": "table-row", "locator": "body:L31-L31", "preview": "| M | K | L | Theoretical time (\u00b5s) | | 7168 | 16384 | 1 | 8.622 |", "sha256": "9d7c65618fc8dc86bb3d2746a16f175fd4649ddfb006c68c807ce5e587b8fd0b"}, {"id": "u014", "kind": "table-row", "locator": "body:L32-L32", "preview": "| M | K | L | Theoretical time (\u00b5s) | | 4096 | 7168 | 8 | 17.275 |", "sha256": "6ef10de1e876f22ab461b936146b0788d1bf5d704d586c207ec965c2cfb38c65"}, {"id": "u015", "kind": "table-row", "locator": "body:L33-L33", "preview": "| M | K | L | Theoretical time (\u00b5s) | | 7168 | 2048 | 4 | 4.317 |", "sha256": "f615c82589dadc4edfe7b91cae3fca3ca39d09c582d799c3ea68d1cd3429a24c"}, {"id": "u016", "kind": "prose", "locator": "body:L35-L35", "preview": "NVIDIA's Blackwell technical brief specifies 8 TB/s of HBM3e bandwidth for one GB200 GPU. The task's theoretical numbers are model values, not measured kernel timings.", "sha256": "704c6601665fccbda264f611828f4318072acc029cf200d5edb39ac485314581"}, {"id": "u017", "kind": "prose", "locator": "body:L37-L37", "preview": "The public leaderboard is mutable and reports aggregate scores rather than per-shape latencies. In the snapshot fetched on 2026-08-08, the first three rows were `s.am._` at 18.549562452 \u00b5s, `gau.nernst` at 18.552844757 \u00b5s, and `shellsmile15", "sha256": "22240d05193ce717b94fafae8edaa23f1553f76a8c00a46d942aa92c4300367a"}, {"id": "u018", "kind": "prose", "locator": "body:L41-L41", "preview": "PTX ISA 9.0 defines the packed conversion and typed register decomposition used in Yue's author-reported decode path:", "sha256": "4affc9d80b04da71f0c299c5784d8efc15535361c1156364eff99e69729b354f"}, {"id": "u019", "kind": "code", "locator": "body:L43-L46", "preview": "```asm cvt.rn.f16x2.e2m1x2 %result, %packed_fp4_pair; mov.b32 {%b0, %b1, %b2, %b3}, %packed_word; ```", "sha256": "3e8b7ea84b83abad0b9ce987bd7810cd56904af6c822034b66dc22b09deced0a"}, {"id": "u020", "kind": "prose", "locator": "body:L48-L48", "preview": "It also defines vector loads such as `ld.global.v2.u64` and `ld.global.v4.u64`, which move 16 and 32 bytes and can carry 32 and 64 packed FP4 values. The ISA specifies behavior, not that one width or decomposition is universally faster.", "sha256": "9d0de1cc2b4db79424fedba1e2f5d3bc17dccb713cb173f3a8b41405ac5bf617"}, {"id": "u021", "kind": "prose", "locator": "body:L50-L50", "preview": "Amandeep reports that three solutions inspected after the event used `L1::no_allocate` for streamed A loads, `L1::evict_last` for reused B loads, wider PTX loads, and exact-K specializations. Those are author-reported observations; the publ", "sha256": "8d769e43685ea0b46eefdae1e86397cdbe7f97387c4fdb5be59a5305352d80cb"}, {"id": "u022", "kind": "prose", "locator": "body:L54-L54", "preview": "The following timings are from Yue's post, not an independent reproduction. Several stages combine multiple changes and cannot establish isolated causality:", "sha256": "a663193aef641ad8433597c548f5820e215e4556a1f06db8485c4075e1cbf6f9"}, {"id": "u023", "kind": "table-row", "locator": "body:L58-L58", "preview": "| Stage | Combined change | Reported latency | | Initial CuTe DSL | First working CuTe implementation | ~100 \u00b5s |", "sha256": "43eb908efd6940c3a7f0b3cb44880e4110b5b361042ab2ccf9cec68ad6d5009f"}, {"id": "u024", "kind": "table-row", "locator": "body:L59-L59", "preview": "| Stage | Combined change | Reported latency | | Optimized CuTe DSL | Scale-load and arithmetic changes plus thread collaboration | ~33 \u00b5s |", "sha256": "8ff27a458e08c63aa19c12f8680ccc4cb633d6b880364aec30bfce4b162c5aa7"}, {"id": "u025", "kind": "table-row", "locator": "body:L60-L60", "preview": "| Stage | Combined change | Reported latency | | Initial CUDA | Naive hand-written path | ~2000 \u00b5s |", "sha256": "ca54d2e0867aaacac8ef7cb2d50ce50784f5192560a97826eabca1c17f14eaba"}, {"id": "u026", "kind": "table-row", "locator": "body:L61-L61", "preview": "| Stage | Combined change | Reported latency | | CUDA step 1 | Coalescing, shared B, thread collaboration, warp reduction | ~443 \u00b5s |", "sha256": "45a99e5c48954c46d64d8216a104e7f192c5d36eae133d72ead8f09d1b957a37"}, {"id": "u027", "kind": "table-row", "locator": "body:L62-L62", "preview": "| Stage | Combined change | Reported latency | | CUDA step 2 | Remove shared B, per-thread tiles, `float4` loads, hardware intrinsics | ~39 \u00b5s |", "sha256": "c7347c699aff3a09cbd3e861889c16bd4cab72d2239ec315fc23068cdff5cf2b"}, {"id": "u028", "kind": "table-row", "locator": "body:L63-L63", "preview": "| Stage | Combined change | Reported latency | | CUDA step 3 | Vectorized PTX FP4/scale decode | ~27 \u00b5s |", "sha256": "6219356ab8e9caca95b5f5bf5e4a40b08c5b6eaef70784ebcafa9b4bc9966a55"}, {"id": "u029", "kind": "table-row", "locator": "body:L64-L64", "preview": "| Stage | Combined change | Reported latency | | Parameter tuning | Threads per row and rows per block | ~26 \u00b5s |", "sha256": "5d2fda1525d1d93874e8cdcc642024d47fe2139e768806cdfa35ab38b4826a4c"}, {"id": "u030", "kind": "table-row", "locator": "body:L65-L65", "preview": "| Stage | Combined change | Reported latency | | Two-tile ILP | Interleave two tiles per loop | ~22.9 \u00b5s |", "sha256": "55bc6ef2fdac8923e7f8d89df31dd74418182cd3741c71c983b0b942c8165841"}, {"id": "u031", "kind": "table-row", "locator": "body:L66-L66", "preview": "| Stage | Combined change | Reported latency | | Aggressive PTX fusion | Fuse decode, scale, multiply, and accumulation | ~22.3 \u00b5s |", "sha256": "3e9d7de1f63be9029aa4ff29559822da7ac982629cde96e956e04ec4c3330b31"}, {"id": "u032", "kind": "table-row", "locator": "body:L67-L67", "preview": "| Stage | Combined change | Reported latency | | Submitted score | Geometric mean shown by the leaderboard | 22.392 \u00b5s |", "sha256": "088f1750e1a2800452b3e097abdcb2af7099608a24ecb7bf909f53c3406f2917"}, {"id": "u033", "kind": "prose", "locator": "body:L69-L69", "preview": "Yue also reports that loading the entire B vector into shared memory did not improve the CuTe attempt. This is a useful counterexample to treating shared-memory B staging or an exact `BLOCK_M` traffic reduction as automatic.", "sha256": "19ee8de8d318e9c5ada566f02126040608afa1d3e39dbc64e014946f41585387"}, {"id": "u034", "kind": "list-item", "locator": "body:L73-L73", "preview": "- Use this case study for an N=1 decode-style matrix-vector operation only when payloads, scales, layouts, output type, and target match the chosen NVFP4 implementation contract.", "sha256": "a8248df41bbce5cc45f98412659fa2f2d8f3ad504d6e7dbf6611009207c697f4"}, {"id": "u035", "kind": "list-item", "locator": "body:L74-L74", "preview": "- Profile bytes moved, instruction count, decode and reduction work, cache behavior, spills, and occupancy before deciding which resource is limiting performance.", "sha256": "c725284ade431a9257a1b4a7cf2ae3f84f565ddd6b5a45c645adbba3458b3580"}, {"id": "u036", "kind": "list-item", "locator": "body:L75-L75", "preview": "- Exact-K dispatch can enable full unrolling and size-specific tuning, but retaining multiple specializations adds compiled kernel entries.", "sha256": "2f807d582f25851529b1c82489b1ba304fdc4b91510a1bfaf6f8b259db03ec6f"}, {"id": "u037", "kind": "list-item", "locator": "body:L76-L76", "preview": "- Inline PTX must be revalidated against the selected PTX ISA, toolkit, and target. The contest ran on B200; that does not imply packed FP4 conversion is restricted to SM100/SM100a forever. Transformer Engine 2.13 lists NVFP4 inference supp", "sha256": "9f975c4e2c336fdd731e7222126701eac54c48fbacbccd74f4fc7230a54c0ca7"}, {"id": "u038", "kind": "list-item", "locator": "body:L77-L77", "preview": "- The official task accepts any implementation that satisfies its checker. It does not require the cache policies, load widths, register limits, or code structures described in participant posts.", "sha256": "86286884a901e356f8c977190835d2ab47157b7f2fa23ef0bbb05aa129da29f2"}, {"id": "u039", "kind": "list-item", "locator": "body:L81-L81", "preview": "- [Pinned Problem 1 task](https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv)", "sha256": "253eac43081be0b1c0f587a706185b6b8f30e7b2cebb381630c17652de95898d"}, {"id": "u040", "kind": "list-item", "locator": "body:L82-L82", "preview": "- [Official contest rules](https://developer.download.nvidia.com/licenses/Blackwell-NVFP4-Hackathon-Terms-and-Conditions.pdf)", "sha256": "c945d69cc0933ee89c1418170925a1dac08b34aa49c449aff8fab2f67960ab55"}, {"id": "u041", "kind": "list-item", "locator": "body:L83-L83", "preview": "- [NVIDIA Blackwell Architecture Technical Brief](https://resources.nvidia.com/en-us-blackwell-architecture/blackwell-architecture-technical-brief)", "sha256": "c330012ad06dc51b1eccaade34a7425fc7b7a8aaefd177c220b19f75aacfc633"}, {"id": "u042", "kind": "list-item", "locator": "body:L84-L84", "preview": "- [PTX ISA 9.0](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html)", "sha256": "f287fbe5a77017bc028e72cfac864b6bb16272498a46b45f643b430593555c9b"}, {"id": "u043", "kind": "list-item", "locator": "body:L85-L85", "preview": "- [Transformer Engine 2.13 NVFP4](https://docs.nvidia.com/deeplearning/transformer-engine-releases/release-2.13/user-guide/features/low_precision_training/nvfp4/nvfp4.html)", "sha256": "fd66d9aaa128a191225657e888e4d0692eac5623d5d11ade7dfc67793dad73e0"}, {"id": "u044", "kind": "list-item", "locator": "body:L86-L86", "preview": "- [Yue Zhang's hackathon journey](https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html)", "sha256": "c92a8a46203210ed1e85fb159f8abb7ee9402f2560f9d4f9c3bba8b71a5a2467"}, {"id": "u045", "kind": "list-item", "locator": "body:L87-L87", "preview": "- [Amandeep Singh's twelve attempts](https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/)", "sha256": "32b13b998fa855e2f28acc4e3385e172306944a5676385b43b3a1d65c0fffbe7"}, {"id": "u046", "kind": "list-item", "locator": "body:L88-L88", "preview": "- [Simon Veitner's reference](https://veitner.bearblog.dev/nvfp4-gemv/) and [improved variants](https://veitner.bearblog.dev/nvfp4-gemv-improved/)", "sha256": "1de91575cdf7f4cd9043e4939095ac18a892ba8e120f1b5343db9ef35082a8e0"}], "confidence_claimed": "source-reported", "headings": ["Verified Scope", "Official Callable Contract", "Official Benchmark Model", "PTX Semantics and Reported Techniques", "Yue's Author-Reported Progression", "Practical Use and Caveats", "Primary Sources"], "id": "kernel-nvfp4-gemv", "path": "wiki/kernels/nvfp4-gemv.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/contests/gpu-mode-nvfp4/problem-1-gemv.md", "url": "https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv"}, {"path": "sources/blogs/yue-nvfp4-hackathon.md", "url": "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"}, {"path": "sources/blogs/amandeep-nvfp4-attempts.md", "url": "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"}], "risk_flags": ["code", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["contest-gpumode-p1", "blog-yue-nvfp4", "blog-amandeep-nvfp4"], "title": "NVFP4 Batched GEMV", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "948b326db003b5db4472a9222cbd12a7ea8b28c706bb3c67abfc29cdc7846cca", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L6", "preview": "DeepSeek-V3.2-Exp introduces **DeepSeek Sparse Attention (DSA)**. Its first-party report defines two components:", "sha256": "bb3c5529691e366dd6efa2a880b744e11851437076378b06b60557eed9f130e4"}, {"id": "u002", "kind": "list-item", "locator": "body:L8-L8", "preview": "1. The lightning indexer computes one score for every query/preceding-token", "sha256": "800571c72e22c76c4f46f84b358de8ed823f7e7daa1d5a0a1aada431dff73396"}, {"id": "u003", "kind": "prose", "locator": "body:L9-L10", "preview": "pair. A score is a weighted sum across indexer heads of a ReLU-applied query and key dot product.", "sha256": "b0c28b86e74cff53ff735a2fccf865af8a26d42271a8e1f9e5ba566ac3c6bc24"}, {"id": "u004", "kind": "list-item", "locator": "body:L11-L11", "preview": "2. Fine-grained token selection retains the KV entries at the top-k index", "sha256": "27bba385baa0f30644e808286cf4cd7f206ac7b835de6e843d5877b66605f308"}, {"id": "u005", "kind": "prose", "locator": "body:L12-L12", "preview": "scores and applies the main attention only to that selected set.", "sha256": "799ed51e15b7fac5411d28e251d11824024993140b9ef0591e8307e92855c99b"}, {"id": "u006", "kind": "prose", "locator": "body:L14-L19", "preview": "The released `config_671B_v3.2.json` uses 64 indexer heads of dimension 128 and `index_topk=2048`. DSA is instantiated under MLA's MQA mode: the selected MLA latent entry is shared across the query heads. The model has 128 MLA query heads, ", "sha256": "7999f09cb62ad0774fc6162c7eeb34be31d20d0047d0dae05d29f9edc76f3774"}, {"id": "u007", "kind": "prose", "locator": "body:L21-L25", "preview": "For a length-L sequence and fixed selected count k, the report reduces the **main/core attention** complexity from O(L squared) to O(Lk). The lightning indexer still scores the preceding context and remains O(L squared) over the sequence. F", "sha256": "2c7a6f110419179e164e3a5294219756ca737c3fcc8e666080d7b2dbdaa83df2"}, {"id": "u008", "kind": "prose", "locator": "body:L29-L30", "preview": "The released high-performance path is not one fused \u201cindexer plus sparse MLA\u201d kernel:", "sha256": "55f8654222c7c4ed6f9915195f9062b25ad60c76e2b1fdb603290b284fdd718a"}, {"id": "u009", "kind": "list-item", "locator": "body:L32-L32", "preview": "- DeepGEMM provides non-paged and paged indexer-logit kernels. Its pinned SM100", "sha256": "49ef39eedf0417732d260892fbf391b96e42f8be6fcfc25f65df6a95b5a976d8"}, {"id": "u010", "kind": "prose", "locator": "body:L33-L35", "preview": "FP8 path computes token logits from FP8 query/key inputs, per-token key scales, and per-query head weights; top-k selection remains a separate operation.", "sha256": "37f4d58acab34fe50c0f8f7112e6ca0b4bfea2750e936edd7287731209210208"}, {"id": "u011", "kind": "list-item", "locator": "body:L36-L36", "preview": "- FlashMLA sparse attention consumes caller-produced token indices. It does not", "sha256": "cc6129e45570619d4939c753c50aa7f48f97d6bd16ddccbef36dafe6d6a91980"}, {"id": "u012", "kind": "prose", "locator": "body:L37-L37", "preview": "run the lightning indexer or top-k selector.", "sha256": "ae05e1bbfe66ece445518ed31b0a0d666c384437f79b7d468584eec2274a5262"}, {"id": "u013", "kind": "prose", "locator": "body:L39-L41", "preview": "At FlashMLA commit [`71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232), prefill and decode have different contracts:", "sha256": "eb389ddbba522174d4e4bfeeae557782e265db6d785ad1db1e6534dae97f1dd5"}, {"id": "u014", "kind": "table-row", "locator": "body:L45-L45", "preview": "| Stage | Inputs and selected-token encoding | Precision and outputs | | Sparse decode | `q[batch,s_q,h_q,576]`; paged `k_cache`; `indices[batch,s_q,topk]`, where each nonnegative value encodes physical page times page size plus token offse", "sha256": "26a36dfe709a48b77979096047f08d9c163ac61519ddf4cdf0418f3ac8e5e996"}, {"id": "u015", "kind": "table-row", "locator": "body:L46-L46", "preview": "| Stage | Inputs and selected-token encoding | Precision and outputs | | Sparse prefill | Unbatched BF16 `q[s_q,h_q,d_qk]`, BF16 `kv[s_kv,h_kv,d_qk]`, and INT32 `indices[s_q,h_kv,topk]`; the documented equivalence requires `h_kv=1`; negativ", "sha256": "1e44a7ce28c3d88a202ffd6faf77f7cedd7ca507f7ce76c55601542bc3357387"}, {"id": "u016", "kind": "prose", "locator": "body:L48-L52", "preview": "These are token indices, not one maximum or one selection per cache block. The sparse-decode API accepts page size through the cache tensor; pinned correctness tests exercise multiple values including 2, 53, 61, 64, 69, 256, and 576. Page s", "sha256": "708e5ca34ceab27f48e8fe7b2f704d457087a65dd4385e2131a535dc0871273d"}, {"id": "u017", "kind": "prose", "locator": "body:L56-L57", "preview": "Only the V3/V3.1/V3.2 **FP8 sparse-decode** mode has the documented 656-byte per-token layout:", "sha256": "953e4b660a1d8b065676b80e7b7bfe06fbcc32914d3a83085d33182a259edc3c"}, {"id": "u018", "kind": "list-item", "locator": "body:L59-L59", "preview": "- 512 E4M3 NoPE values: 512 bytes;", "sha256": "cab31744fcfa6f82078271f60cd43b820f43334dfc55e6a23d6b4eff5d85eeab"}, {"id": "u019", "kind": "list-item", "locator": "body:L60-L60", "preview": "- four FP32 scales, one for each successive group of 128 NoPE values: 16 bytes;", "sha256": "e9793ded4f667e1592dd6b993dd390b5016a1cf8154c4041a50971a687d58d57"}, {"id": "u020", "kind": "list-item", "locator": "body:L61-L61", "preview": "- 64 BF16 RoPE values used by the attention key: 128 bytes.", "sha256": "42502eff2ec7dd17fd0437ce18e46942556ee145ee15b2f566f78fc7f1f35cf6"}, {"id": "u021", "kind": "prose", "locator": "body:L63-L65", "preview": "The indexer has a separate FP8 K cache and scale cache in the released model. The 656-byte attention entry is not an indexer cache and is not the layout of every dense, sparse-prefill, or non-V3 FlashMLA mode.", "sha256": "004ef4c9a6d5f3ed82854f9a9c23912785829fab4c14b88f3209e130e2804f32"}, {"id": "u022", "kind": "prose", "locator": "body:L69-L71", "preview": "FlashMLA's pinned README reports the following maxima. They are useful source claims, not reproducible benchmark tuples: the README does not provide complete shapes, timed regions, repetitions, samples, or variance.", "sha256": "53fac485447961fd25735e0a07f1bc42805fa1e081bfc85f7e358c428dfce49f"}, {"id": "u023", "kind": "table-row", "locator": "body:L75-L75", "preview": "| Operator and regime | Reported environment | Author-reported maximum and precision scope | | Dense MLA decode, memory-bound configuration | H800 SXM5, CUDA 12.8 | Up to 3000 GB/s with BF16 cache |", "sha256": "330ca8a2334ecb87ab1bbb24ffd109a884a2205e87bf06eb13a6a23f7971d01c"}, {"id": "u024", "kind": "table-row", "locator": "body:L76-L76", "preview": "| Operator and regime | Reported environment | Author-reported maximum and precision scope | | Dense MLA decode, compute-bound configuration | H800 SXM5, CUDA 12.8 | Up to 660 TFLOPS with BF16 cache; separate from the 3000-GB/s case |", "sha256": "498754f9010440f53a448bb30c012279c0b07afbed50d3948e10936a375fe13b"}, {"id": "u025", "kind": "table-row", "locator": "body:L77-L77", "preview": "| Operator and regime | Reported environment | Author-reported maximum and precision scope | | Sparse MLA decode | H800 SXM5, CUDA 12.8 | 410 TFLOPS; FP8 KV storage and BF16 matrix multiplication |", "sha256": "619c3ef250d56d62746909cd8385a09d21c42b91cbb78ca19ff12ee196e011d7"}, {"id": "u026", "kind": "table-row", "locator": "body:L78-L78", "preview": "| Operator and regime | Reported environment | Author-reported maximum and precision scope | | Sparse MLA decode | B200 | Up to 350 TFLOPS; the source says this path was not really optimized and gives no bandwidth-causality result |", "sha256": "8c29c94ec9620c62ce3dc2dca6c5caf9fc593e6e655ed3083238714f063298c1"}, {"id": "u027", "kind": "table-row", "locator": "body:L79-L79", "preview": "| Operator and regime | Reported environment | Author-reported maximum and precision scope | | Sparse MLA prefill | H800 SXM5, CUDA 12.8 | Up to 640 TFLOPS forward with BF16 Q/KV |", "sha256": "65b792e1dcb4c09b1df29d269f6b31e97e9759eb45d1dbfb50461bdfc30a2b78"}, {"id": "u028", "kind": "table-row", "locator": "body:L80-L80", "preview": "| Operator and regime | Reported environment | Author-reported maximum and precision scope | | Sparse MLA prefill | B200, CUDA 12.9 | Up to 1450 TFLOPS forward with BF16 Q/KV |", "sha256": "95c25ad0d981b3686a61775f7965640cc532bb9f6b636a35fd27c6a294572fe7"}, {"id": "u029", "kind": "prose", "locator": "body:L82-L85", "preview": "The same README separately reports NVIDIA's dense **MHA** prefill maxima of 1460 TFLOPS forward and 1000 TFLOPS backward on B200. Those values are not a dense-MLA baseline matched to the sparse-prefill result, so numerical proximity between", "sha256": "7ac9b3f51be9a7774fa020507229c154b698af2de5f5294b218fdc3135466a57"}, {"id": "u030", "kind": "prose", "locator": "body:L89-L92", "preview": "Use this path directly for DeepSeek-V3.2-Exp, or for another model only after its query dimensions, latent/RoPE layout, cache format, head relationships, index encoding, invalid-entry rules, and output semantics match the chosen FlashMLA in", "sha256": "8f4750da95e3b1406c6de34977adb16629218d8cbf8633e93a0e2d1402c11c69"}, {"id": "u031", "kind": "prose", "locator": "body:L94-L94", "preview": "For a target deployment:", "sha256": "fbb956c923fa1fd09806a78a27d293e0f8ebba82fb051ec936245cfbab5aa6bf"}, {"id": "u032", "kind": "list-item", "locator": "body:L96-L96", "preview": "1. Compare index scores and selected token sets against the released model", "sha256": "a242b13ee51da5cc6cb541c02ee0c6daec6fdfc1984d6ec275554957be416c4a"}, {"id": "u033", "kind": "prose", "locator": "body:L97-L98", "preview": "equation and a dense reference, including causal masking and the indexer's non-interleaved RoPE layout.", "sha256": "2e2cead28d1d22caa0e2eb0a926978703e3dac81cef6c1ca51ca073875034c13"}, {"id": "u034", "kind": "list-item", "locator": "body:L99-L99", "preview": "2. Compare sparse prefill/decode outputs and LSE values with the pinned", "sha256": "da0d88573313119d302c4d5be8a002a02d2e95ed3cfdf92b11d9eb6d471ee920"}, {"id": "u035", "kind": "prose", "locator": "body:L100-L101", "preview": "FlashMLA reference for identical selected indices, including invalid and partially filled top-k cases.", "sha256": "7dfcefbf9f9a818d7f9216ec620e421da6a17ef61a85dc8a12903765a3d3a748"}, {"id": "u036", "kind": "list-item", "locator": "body:L102-L102", "preview": "3. Time indexer logits, top-k selection, sparse attention, and the complete", "sha256": "94eb29b4206955c162be3c506b690b8704ac47a014a9065ffb96b40829d3a68e"}, {"id": "u037", "kind": "prose", "locator": "body:L103-L105", "preview": "pipeline separately across context lengths, query batch sizes, page sizes, and selected counts. Use a matched dense-attention baseline and report synchronization, warmup, repeated trials, statistic, and variation.", "sha256": "f02576926515f6346b13cb20938a90d9add5d59c67836537a247f53a7ed3964e"}, {"id": "u038", "kind": "prose", "locator": "body:L107-L109", "preview": "There is no verified universal 32K crossover. The relevant threshold is where the measured selector-plus-sparse-attention pipeline improves the target's end-to-end latency or cost without violating its accuracy criterion.", "sha256": "dbcd039e000ca1384e83656c5550b990540d5f937a2165464a53be0b3a47373b"}, {"id": "u039", "kind": "prose", "locator": "body:L113-L117", "preview": "DeepSeek-V3.2-Exp DSA selects individual token positions with a learned indexer. The ACL Native Sparse Attention architecture instead combines compressed-block, selected-block, and sliding-window branches with learned gates. Do not transfer", "sha256": "0acee81708a88fb6dadac0671ca900e0781e9ea10c0f915e18641f375c096b84"}, {"id": "u040", "kind": "list-item", "locator": "body:L121-L121", "preview": "- [DeepSeek-V3.2-Exp report and released model](https://github.com/deepseek-ai/DeepSeek-V3.2-Exp/tree/87e509a2e5a100d221c97df52c6e8be7835f0057)", "sha256": "7e2d20a04ee83d9a3bf13f14c6776ff4b781d09b3be1430590dc1ecf4a0c74bc"}, {"id": "u041", "kind": "list-item", "locator": "body:L122-L122", "preview": "- [FlashMLA at audited commit `71c7379`](https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232)", "sha256": "1f1e839b0c6d66154bae95cc00ff4970eabb13c2b7f9c1fbf2c2adbc49cbff46"}, {"id": "u042", "kind": "list-item", "locator": "body:L123-L123", "preview": "- [FlashMLA sparse interface at `71c7379`](https://github.com/deepseek-ai/FlashMLA/blob/71c737929f2567bd0a094ae140f8f60f390b1232/flash_mla/flash_mla_interface.py)", "sha256": "e814ec84eaefe35612a2df8db9295b511349797f6c84c94ee4a8c5dd1fa447ae"}, {"id": "u043", "kind": "list-item", "locator": "body:L124-L124", "preview": "- [DeepGEMM indexer-logit implementation at `891d57b4`](https://github.com/deepseek-ai/DeepGEMM/blob/891d57b4db1071624b5c8fa0d1e51cb317fa709f/deep_gemm/include/deep_gemm/impls/sm100_fp8_mqa_logits.cuh)", "sha256": "719f548e64d48d007a4167184782be4a682c07ce1fc80ce249f2422d75dd59cf"}, {"id": "u044", "kind": "list-item", "locator": "body:L125-L125", "preview": "- [ACL 2025 Native Sparse Attention paper](https://aclanthology.org/2025.acl-long.1126/)", "sha256": "0d5536512e7b6f36724ec0738c6ae2905c69b13a296ce9b447941d99d1ba1f39"}], "confidence_claimed": "source-reported", "headings": ["Model mechanism", "Separate implementation boundaries", "V3-family sparse-decode cache", "Source-reported performance boundary", "Evaluation procedure", "DSA is not Native Sparse Attention", "Primary references"], "id": "kernel-sparse-mla", "path": "wiki/kernels/sparse-mla.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/flashmla.md", "url": "https://github.com/deepseek-ai/FlashMLA/tree/71c737929f2567bd0a094ae140f8f60f390b1232"}, {"path": "sources/blogs/vllm-deepseek-v3-sparse-attention.md", "url": "https://blog.vllm.ai/2025/09/29/deepseek-v3-2.html"}, {"path": "sources/docs/nsa.md", "url": "https://aclanthology.org/2025.acl-long.1126/"}], "risk_flags": ["ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-flashmla", "blog-vllm-deepseek-v3-sparse", "blog-nsa"], "title": "DeepSeek Sparse Attention / Sparse MLA", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "64b746e36ef7866e93cb1c9aca98703acc5008d485a0d9c96ab31f7a1504a964", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L6", "preview": "TensorRT-LLM PR 13340 adds an FP4 option to its DeepSeek Sparse Attention (DSA) indexer path. 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Calling them \u201cfused quantized gather/scatter\u201d conflates the first two stages.", "sha256": "807375e96e742adf3dcf843c6629b966585ade9ccf3c8eeb2203385bc47f166c"}, {"id": "u008", "kind": "prose", "locator": "body:L23-L23", "preview": "For the fixed 128-value indexer head in this path, one row has:", "sha256": "ebb2a6213e4bff8f699eae8109c1f172ba7e674d0b9b63b222df48f57b18e727"}, {"id": "u009", "kind": "table-row", "locator": "body:L27-L27", "preview": "| Component | Representation | Bytes per row | | Input | BF16 positional values followed by BF16 non-positional values | 256 before quantization |", "sha256": "baec963beab3b990ec4394a2317a757e16a2ae7eed59ba449f4b13f0c8d41276"}, {"id": "u010", "kind": "table-row", "locator": "body:L28-L28", "preview": "| Component | Representation | Bytes per row | | Packed payload | Two FP4 E2M1 codes per byte | 64 |", "sha256": "733a12c767a0e5c2b16891c439d9afb7f02967486419f72c19ab6be2f8899338"}, {"id": "u011", "kind": "table-row", "locator": "body:L29-L29", "preview": "| Component | Representation | Bytes per row | | Scale word | Four UE8M0 exponent bytes, one per successive group of 32 values, packed little-endian into one `int32` | 4 |", "sha256": "4f5e47e73b176f3b9410f26081aa80b35d5dc6f60655aab518f2b403c93c8d03"}, {"id": "u012", "kind": "table-row", "locator": "body:L30-L30", "preview": "| Component | Representation | Bytes per row | | Cache footprint | Packed payload plus scale word | 68 |", "sha256": "eb8484b32ee5c8dbb43eac0b6a213e540b06d702b5a0c10b8af1388ef129c7f5"}, {"id": "u013", "kind": "prose", "locator": "body:L32-L36", "preview": "The fused operator requires CUDA BF16 inputs on one device, at least two dimensions, a contiguous innermost dimension, eight-byte-aligned addresses, equal row counts, and positional width divisible by four. Positional and non-positional wid", "sha256": "a5cc71924358ceb6ead6a2ecda37330218b28290f4b2d41b6adaeb5ac031bebd"}, {"id": "u014", "kind": "prose", "locator": "body:L38-L41", "preview": "The scale for each 32-value group is `2^ceil(log2(max(amax, 1e-12) / 6))`. Quantization uses the FP4 E2M1 magnitude set `{0, 0.5, 1, 1.5, 2, 3, 4, 6}` and packs the earlier value into the low nibble.", "sha256": "f7c210916986dea9cc641e69e78cc98f6ecd2e4cf7699853f0ff2c8ccc511256"}, {"id": "u015", "kind": "prose", "locator": "body:L45-L49", "preview": "The cache is viewed as `[num_blocks, block_size, 1, per_token_size]` and may be non-contiguous. Each token launch copies four bytes per thread. The FP4 path uses 64 payload bytes and one four-byte scale word; the legacy FP8 path uses 128 pa", "sha256": "987ce4347f8506f5eea5a3d223d7a93fb36282a6a0fde62ad4a46290c6f401ba"}, {"id": "u016", "kind": "prose", "locator": "body:L51-L55", "preview": "Payload and scale use separate contiguous `int64` slot-mapping arrays. If either mapping for a token is negative, gather and scatter skip that entire token. The gather wrapper allocates output with `empty`, so a directly gathered row skippe", "sha256": "9368aff166cf872488d1f74571c046b6ce8644b1e602bf3a20e68ce7b65d9bec"}, {"id": "u017", "kind": "prose", "locator": "body:L57-L61", "preview": "The gather wrapper preserves a historical typed view: payload bytes are returned as float8 and scale bytes as FP32. The FP4 call site reinterprets them as packed `int8` data and `int32` scale words before the DeepGEMM call. These views are ", "sha256": "3d313476860278e4ba8137a9d7cdeab1f70baca9b13c2e21fb85e25506deb8a4"}, {"id": "u018", "kind": "list-item", "locator": "body:L65-L65", "preview": "1. Compare `fused_cat_fp4` byte-for-byte with a reference implementation for", "sha256": "154a706e5febec7291f37c016f2c410dda069d1093b5277e758ecc7df33d51d8"}, {"id": "u019", "kind": "prose", "locator": "body:L66-L67", "preview": "zeros, FP4 decision boundaries, saturation, non-contiguous row strides, and multiple positional/non-positional splits whose widths sum to 128.", "sha256": "73c51aeb33326d6cb9aa5f4b0051dbd1226634ef3d17ad7ac5542abf75368a5b"}, {"id": "u020", "kind": "list-item", "locator": "body:L68-L68", "preview": "2. Round-trip valid tokens through scatter and gather using strided cache", "sha256": "dd3e85e021b2f37adc460ca62eb0dd4572d922c801da9f356f462c7edd762b3f"}, {"id": "u021", "kind": "prose", "locator": "body:L69-L70", "preview": "views. Check all 64 payload bytes and the four scale bytes independently; test negative payload and scale mappings without reading skipped empty rows.", "sha256": "5c513ab9c82962738d09cd52fa8abbe2157d34276c0d623a35c76c705daf72bb"}, {"id": "u022", "kind": "list-item", "locator": "body:L71-L71", "preview": "3. Compare FP4 non-paged and paged indexer logits, then selected indices,", "sha256": "f2a52d0cdaea7c448fda6a9ec9891ff1715df56ef0cf0f062f7a4f8e5d951d60"}, {"id": "u023", "kind": "prose", "locator": "body:L72-L73", "preview": "against an unquantized or higher-precision reference with identical masks, weights, and sequence boundaries.", "sha256": "ec15cbb04e5738b69458f6dd903cb1034e1125baeb8eb7fe8ee1db97b5311e8f"}, {"id": "u024", "kind": "list-item", "locator": "body:L74-L74", "preview": "4. Profile fused preparation, scatter, gather, logit computation, top-k, and", "sha256": "21d1fd695924b33d8c8316a89cad074218542e8d28d1311eb48f082429e42713"}, {"id": "u025", "kind": "prose", "locator": "body:L75-L76", "preview": "the complete indexer separately. Report shapes, cache layout, mapping mix, warmup, synchronization, repetitions, statistic, and variation.", "sha256": "b76f11b1782d4489ce3834019cbd0aa1e7079900dc54bde8f66498aa7519c781"}, {"id": "u026", "kind": "prose", "locator": "body:L78-L79", "preview": "The pinned PR contains no performance result, so use it to define candidate mechanisms and exact contracts rather than to claim a speedup.", "sha256": "62b72a9c0d5493138efc92602fe3a9b570342ca3e3a1afd37d89359535faae33"}, {"id": "u027", "kind": "list-item", "locator": "body:L83-L83", "preview": "- [TensorRT-LLM PR 13340](https://github.com/NVIDIA/TensorRT-LLM/pull/13340)", "sha256": "b5192a1e772c7397854ba03a1cf3a79cadfd904f45437b099332dda59be08ce4"}, {"id": "u028", "kind": "list-item", "locator": "body:L84-L84", "preview": "- [Pinned `fusedCatFp4.cu` artifact](../../artifacts/prs/tensorrt-llm/PR-13340/key-files/cpp/tensorrt_llm/kernels/fusedCatFp4.cu)", "sha256": "5c2e1274b194d2974112ca102087a93493f94e7c6c0166d5e928aaaf4423415f"}, {"id": "u029", "kind": "list-item", "locator": "body:L85-L85", "preview": "- [Pinned gather kernel artifact](../../artifacts/prs/tensorrt-llm/PR-13340/key-files/cpp/tensorrt_llm/kernels/indexerKCacheGather.cu)", "sha256": "e4cb68f24b2d80c4b670273abebab689b0effa32829ffbd7ba41922a51f517c3"}, {"id": "u030", "kind": "list-item", "locator": "body:L86-L86", "preview": "- [Pinned scatter kernel artifact](../../artifacts/prs/tensorrt-llm/PR-13340/key-files/cpp/tensorrt_llm/kernels/indexerKCacheScatter.cu)", "sha256": "0811f065211145ad22d7ea66d97a233992db16c6c2a1559f862a6399de29cef5"}, {"id": "u031", "kind": "list-item", "locator": "body:L87-L87", "preview": "- [Pinned DSA integration artifact](../../artifacts/prs/tensorrt-llm/PR-13340/key-files/tensorrt_llm/_torch/attention_backend/sparse/dsa.py)", "sha256": "6ab0e3cc566c51a18ede438c4e7b208034aae703a7d915c4a0ae46c997b62226"}], "confidence_claimed": "source-reported", "headings": ["Audited scope", "FP4 row and scale contract", "Gather and scatter semantics", "Validation and profiling procedure", "Primary references"], "id": "kernel-tensorrt-llm-blackwell-indexer", "path": "wiki/kernels/tensorrt-llm-blackwell-indexer.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/prs/TensorRT-LLM/PR-13340.md", "revision": "897c4bff", "url": "https://github.com/NVIDIA/TensorRT-LLM/pull/13340"}], "risk_flags": ["ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["pr-TensorRT-LLM-13340"], "title": "TensorRT-LLM Blackwell FP4 DSA Indexer", "type": "kernel", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "280b0450a7c8a8d900672fd9664f15c0dfdc7f7464b794a771ca6275e0b23ead", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "CUDA C++ can host PTX instructions that do not yet have a convenient CUDA intrinsic. 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The producer reserves a reusable stage, issues TMA against that stage's full barrier, and accounts for the expected transaction bytes.", "sha256": "8cd760e642ac8dd2a6c515be010fe9a44a7bb62f7ef15c8f70e6c6ebc9c401f1"}, {"id": "u011", "kind": "list-item", "locator": "body:L51-L51", "preview": "3. The consumer waits with acquire semantics on the matching phase before reading the shared-memory stage.", "sha256": "312a192456b9daef18da5ad8e2f779541b10225463031894dd7f857871ec475f"}, {"id": "u012", "kind": "list-item", "locator": "body:L52-L52", "preview": "4. After issuing tcgen05 MMA, it commits completion to a separate barrier; the epilogue waits before loading TMEM.", "sha256": "86b997ef2bea7fd774b96fcee44abe925d6bd6a210f9b95bb6d8af8236cb7286"}, {"id": "u013", "kind": "list-item", "locator": "body:L53-L53", "preview": "5. The last stage user signals a separate empty/reuse barrier. A stage cannot be overwritten until its owner observes that handoff.", "sha256": "37f0a635354de7c909cf892d271fe017f1e61f286f30fcad30e0489653a63125"}, {"id": "u014", "kind": "list-item", "locator": "body:L54-L54", "preview": "6. Each barrier's parity flips only when its circular stage is revisited. Inline assembly that reads or writes memory invisibly to C++ uses a `\"memory\"` clobber.", "sha256": "b0b450e2673b3629ee08ba79029114501314c74fe24b7f02b919b5cbe5173472"}, {"id": "u015", "kind": "prose", "locator": "body:L56-L56", "preview": "Arrival counts, transaction bytes, scope, and which CTA owns each barrier depend on whether the kernel uses one-CTA or two-CTA MMA. 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It is not the introduction boundary. |", "sha256": "ae8dd494d86b9bdf4335d086a7fc67293ccb647ee15a43e83ae74a51c7583926"}, {"id": "u006", "kind": "table-row", "locator": "body:L11-L11", "preview": "| Release | Evidence-scoped milestone | | v3.7.0 / v3.7.1 | v3.7.0 continues 2-CTA, multicast, and TMA work; v3.7.1 is a two-regression patch with no advertised new API or feature. |", "sha256": "4635dc9d8b11b6614cb89888178e84327676f99fed5e0b67f2e5f75e64e46829"}, {"id": "u007", "kind": "prose", "locator": "body:L13-L13", "preview": "The compiler evidence proves that native paths exist. It does not prove that every plain `tl.dot` shape selects TCGen5: instruction selection can depend on architecture, dtype, shape, layout, and compiler configuration. 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They must not be combined with the separate compiler-version evidence to infer an unobserved lowering.", "sha256": "e25568d8c8d675f229103457b89bfe14c70bb60ea3c384f8aec4ee49263bde73"}, {"id": "u017", "kind": "prose", "locator": "body:L35-L35", "preview": "SGLang [`pr-sglang-5390`](../../sources/prs/sglang/PR-5390.md) reports 10,447.34 total tok/s for its CUTLASS MLA run and 8,227.35 total tok/s for its Triton run, 26.98% higher under the PR's recorded DeepSeek-R1, 3,000-prompt, TP8/DP8, floa", "sha256": "e18be1d70f68c7e9f57e4ce6512515fba305011c95d9c3fb4f4aa91cee317942"}, {"id": "u018", "kind": "prose", "locator": "body:L37-L37", "preview": "SGLang [`pr-sglang-21595`](../../sources/prs/sglang/PR-21595.md) changes the SM100 datacenter multimodal-attention default from `triton_attn` to FA4. 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this page does not duplicate that changing count.", "sha256": "b82bbb549f1e4dfa484c36d1134005bb13fd50ddc1a6db308b67a2dab96b78c1"}, {"id": "u033", "kind": "prose", "locator": "body:L68-L68", "preview": "This verbatim excerpt from the pinned vLLM decode kernel demonstrates the page's deliberately limited downstream claim\u2014FP8 rescaling followed by `tl.dot`, without proving a particular emitted MMA instruction:", "sha256": "161635e13b202066602eecd585ccef97bc289ce7efd17d6eda51155b8cbce11b"}, {"id": "u034", "kind": "code", "locator": "body:L70-L76", "preview": "```python if k.dtype.is_fp8(): k = (k.to(tl.float32) * ks).to(q.dtype) qk = tl.dot(q, k.to(q.dtype)) if BLOCK_DPE > 0: offs_buf_kpe = kv_loc[None, :] * stride_buf_kbs ```", "sha256": "98ec2d0651858cbb3b5795bc15f9064e1167c1f0800a61b764ad5906cb6bcca9"}, {"id": "u035", "kind": "metadata-version", "locator": "frontmatter:version_sensitive", "preview": "{\"id\": \"vs-triton-3.3-blackwell-tcgen05\"}", "sha256": "2c0977b31b1a2e307ef3fca06c52165f985ad1366e7255b1e8c869baca5a2669"}], "confidence_claimed": "verified", "headings": ["Verified release boundary", "User-visible surfaces", "What downstream code establishes", "Scoped ecosystem results", "Launch overhead and CUDA Graphs", "Provenance-pinned examples"], "id": "lang-triton", "path": "wiki/languages/triton-blackwell.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/triton-3.3-blackwell.md", "url": "https://github.com/triton-lang/triton/compare/v3.2.0...v3.3.0"}, {"path": "sources/docs/triton-3.6-blackwell.md", "url": "https://github.com/triton-lang/triton/releases/tag/v3.6.0"}, {"path": "sources/prs/vllm/PR-34597.md", "revision": "a1257fd1", "url": "https://github.com/vllm-project/vllm/pull/34597"}, {"path": "sources/prs/vllm/PR-29339.md", "revision": "c17610e2", "url": "https://github.com/vllm-project/vllm/pull/29339"}, {"path": "sources/prs/sglang/PR-22079.md", "revision": "5638d40f", "url": "https://github.com/sgl-project/sglang/pull/22079"}, {"path": "sources/prs/sglang/PR-21019.md", "revision": "5bdc07d9", "url": "https://github.com/sgl-project/sglang/pull/21019"}, {"path": "sources/prs/sglang/PR-5390.md", "revision": "84810da4", "url": "https://github.com/sgl-project/sglang/pull/5390"}, {"path": "sources/prs/sglang/PR-21595.md", "revision": "87a27682", "url": "https://github.com/sgl-project/sglang/pull/21595"}], "risk_flags": ["code", "table", "version"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-triton-3.3-blackwell", "doc-triton-3.6-blackwell", "pr-vllm-34597", "pr-vllm-29339", "pr-sglang-22079", "pr-sglang-21019", "pr-sglang-5390", "pr-sglang-21595"], "title": "Triton on Blackwell", "type": "language", "unresolved_source_ids": [], "version_sensitive": {"id": "vs-triton-3.3-blackwell-tcgen05"}} +{"body_sha256": "1780b4d4aa8b9c8bc2757dd6d8601d0ed39055ea4e641003be7d16db8b598931", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "For Hopper `wgmma.mma_async.m64nNk16` with an FP32 accumulator, each warpgroup thread holds `N/2` FP32 D registers. At `N=256`, that is 128 registers per thread for D. WGMMA updates that register vector asynchronously; the program uses the ", "sha256": "81c50814350c832517909572561c4f72593f90fdf9fd14235d07601b29cc502b"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "For `sm_100a`, tcgen05 D is addressed in Tensor Memory rather than supplied as a per-thread register vector. The CTA-visible TMEM structure has 128 lanes by 512 columns of 32-bit cells, or 256 KiB when fully allocated. Allocation is dynamic", "sha256": "90915abc172e7b8a5e9fdec98cdb99a4f905d1e52e66f7b4a939c546ed740ab2"}, {"id": "u003", "kind": "prose", "locator": "body:L9-L9", "preview": "This removes the resident D vector from the ordinary register file. It does not remove all register pressure: descriptors, addresses, loop state, pipeline state, and each TMEM-to-register epilogue batch still need registers. Both Hopper and", "sha256": "3065c8674899961c948b2920ce5998033450f02b782f496619e938425f12bb2c"}, {"id": "u004", "kind": "table-row", "locator": "body:L15-L15", "preview": "| Concern | Hopper WGMMA | Blackwell tcgen05 | | Resident D | Per-thread register fragment | TMEM region addressed by `taddr` |", "sha256": "caf62cc51664762ce0014371563bd85fb173f40058af73033877c114fb4e957d"}, {"id": "u005", "kind": "table-row", "locator": "body:L16-L16", "preview": "| Concern | Hopper WGMMA | Blackwell tcgen05 | | Example FP32 D cost | `N/2` registers/thread; 128 at `N=256` | No resident per-thread D vector |", "sha256": "6e4cf747f49122769816e81e7f7200b5e7c2dbef080de92600e88c94f0a6a67e"}, {"id": "u006", "kind": "table-row", "locator": "body:L17-L17", "preview": "| Concern | Hopper WGMMA | Blackwell tcgen05 | | First accumulation | Set WGMMA `scale-d` false to compute `D=A*B`, or initialize/use D when accumulation is intended | Set `enable-input-d` false to compute `D=A*B`, or explicitly initialize ", "sha256": "3eef8e2f3c1f793204f9ac25cd12a7ca2646443ef0aac8c4c12cf7b7d68a4482"}, {"id": "u007", "kind": "table-row", "locator": "body:L18-L18", "preview": "| Concern | Hopper WGMMA | Blackwell tcgen05 | | Compute completion | WGMMA commit/wait group | `tcgen05.commit` to an mbarrier, then wait before a consumer reads/reuses D |", "sha256": "0b73d94f0d547ca8fde7bfcbd32bb2051564e76bfacb9631eb78add6646bf88c"}, {"id": "u008", "kind": "table-row", "locator": "body:L19-L19", "preview": "| Concern | Hopper WGMMA | Blackwell tcgen05 | | Epilogue access | Use the thread's D registers | Collective `tcgen05.ld`, then `tcgen05.wait::ld` before consuming result registers |", "sha256": "61e6795055d9b77d891ca6222fd9697889c19e800e9403c14867010befb557d6"}, {"id": "u009", "kind": "table-row", "locator": "body:L20-L20", "preview": "| Concern | Hopper WGMMA | Blackwell tcgen05 | | Cleanup | Register lifetime ends with the thread | Matching collective `tcgen05.dealloc` before kernel exit |", "sha256": "735266abf367eab94461e883b716688a8976f3847bed7a112cba79534d11f5d7"}, {"id": "u010", "kind": "table-row", "locator": "body:L21-L21", "preview": "| Concern | Hopper WGMMA | Blackwell tcgen05 | | Double buffering | Two simultaneously live D fragments consume two register fragments | Two live outputs consume disjoint TMEM columns inside the allocation |", "sha256": "b04813198ede3f9af7088d4f1b95aa578b1195e6e41e388421499ab2487372ba"}, {"id": "u011", "kind": "prose", "locator": "body:L23-L23", "preview": "The table describes storage contracts, not an occupancy prediction. Instruction shape is also not necessarily the same as a composed CTA tile.", "sha256": "195c5b3cd276fffc69431065c21852ab5d89c54e26805dfbc82eeadd098432ab"}, {"id": "u012", "kind": "list-item", "locator": "body:L27-L27", "preview": "1. Choose one CTA-group mode for the kernel. For allocation, `nCols` is a power of two in `[32, 512]`; allocations are column-granular and cover all 128 lanes.", "sha256": "663ec5e2ecd0084580d22cb5e1a1fdb601f34042656316eb82971db2810e2220"}, {"id": "u013", "kind": "list-item", "locator": "body:L28-L28", "preview": "2. Have every lane of one designated warp execute the same `.cta_group::1` allocation. Synchronize before other threads read the 32-bit `taddr` written to shared memory. Two-CTA mode requires one warp in each live peer CTA.", "sha256": "442f844d571108d531ca6c4f1c2fcb34a128af006b51feb868efa7ca66f6945f"}, {"id": "u014", "kind": "list-item", "locator": "body:L29-L29", "preview": "3. Initialize and publish the barriers used by TMA and tcgen05. If the first MMA should compute only `A*B`, supply a false `enable-input-d` predicate instead of assuming a mandatory TMEM zero-store pass.", "sha256": "688cacfc78db32ef2dbc1b5748ab430829d8949fa6ec1e7f1737048cbcfa2858"}, {"id": "u015", "kind": "list-item", "locator": "body:L30-L30", "preview": "4. Issue MMA from the permitted elected thread with valid A/B descriptors, instruction descriptor, predicate, and lifetimes.", "sha256": "c81894a6edec76da9df885f000827bc66cd3820796598af4d484b7a69c4643e9"}, {"id": "u016", "kind": "list-item", "locator": "body:L31-L31", "preview": "5. Attach completion of the relevant tcgen05 work to an mbarrier with `tcgen05.commit`. A fence controls execution ordering but is not a completion wait.", "sha256": "3f66638c0aa59578daef93b5cd3375015890606f7dbaa0f9f2b07f9e33caa19c"}, {"id": "u017", "kind": "list-item", "locator": "body:L32-L32", "preview": "6. After the completion handoff, participating epilogue lanes execute a legal `tcgen05.ld` shape and `tcgen05.wait::ld` before using the loaded registers.", "sha256": "add86c6758160d1ee6436e9bbb4a42118fa75ad68987d8da15053e12fcddcc68"}, {"id": "u018", "kind": "list-item", "locator": "body:L33-L33", "preview": "7. After all readers finish, every lane of the designated warp executes the matching deallocation on every kernel exit path. Allocation/deallocation address, column count, and CTA-group mode must agree.", "sha256": "f07d98a96b90ae28744b10a65fee6446286122ccfd1e24b3f6df56759d8d3b9a"}, {"id": "u019", "kind": "prose", "locator": "body:L35-L35", "preview": "Representative PTX ISA 9.0 forms are shown below. They omit declarations, descriptor construction, collective control flow, barriers, and inline-assembly constraints, so they are not a standalone kernel.", "sha256": "ba8a0bbd80024f2e78f378a5524beb0317003225da5d484380df0020489d90f3"}, {"id": "u020", "kind": "code", "locator": "body:L37-L44", "preview": "```ptx tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [saddr], nCols; tcgen05.mma.cta_group::1.kind::f16 [taddr], a_desc, b_desc, idesc, p; tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cta.b64 [mbar]; tcgen05.ld.sync.a", "sha256": "a5d9f9e0f8f9643e18992569407c06dd52f1583195162b4b41c9bdfa172c67d7"}, {"id": "u021", "kind": "prose", "locator": "body:L48-L48", "preview": "TMEM makes it practical to keep multiple output regions independently addressable while different warp roles issue MMA and drain a completed region. Safe overlap needs three distinct proofs:", "sha256": "472061f2ee2a0acce107d45fd26f201f4bd143c15aeb1efeaef163973f894aa0"}, {"id": "u022", "kind": "list-item", "locator": "body:L50-L50", "preview": "- compute completion occurs before an epilogue loads a region;", "sha256": "797834acb4631fde043533de9ef5d1938c604993e27069015705834e832921ab"}, {"id": "u023", "kind": "list-item", "locator": "body:L51-L51", "preview": "- all epilogue loads complete before that region is overwritten or deallocated;", "sha256": "f76c38cde4d90d1036b53206db7b3fa9eb7c698a8ec70a94f914970e27393b41"}, {"id": "u024", "kind": "list-item", "locator": "body:L52-L52", "preview": "- producer/consumer state and phase cannot alias a different pipeline stage.", "sha256": "53171494a69370538165b9a5233bde906d81d1a6117a916676ef9f91f33fa533"}, {"id": "u025", "kind": "prose", "locator": "body:L54-L54", "preview": "TMEM is not the only way to overlap tensor-core and non-matmul work. FlashAttention-3 already uses warp specialization and matmul/softmax interleaving on Hopper with register accumulators. The migration benefit is the different storage and ", "sha256": "c0d0df2e7890cb2071ca656369ce0ebacde9548a7e8d52684018dc1f460f15bf"}, {"id": "u026", "kind": "prose", "locator": "body:L58-L58", "preview": "FlashAttention-4's first-party paper places score/output accumulators in TMEM and assigns MMA, softmax, and correction work to specialized warp roles. The accompanying author post describes software-selected polynomial `exp2` work on CUDA c", "sha256": "3b5cea1d7c442196306c53f5222f1b29458f1a4a7f94880145e94721679140e9"}, {"id": "u027", "kind": "prose", "locator": "body:L62-L62", "preview": "Do not translate an instruction shape directly into a required CTA tile or assume that moving D guarantees no spills. For each concrete kernel:", "sha256": "458b810cc30dfa258823ec0f43d812cd1b0d189139c427c79b07cf5bcf6d2d8b"}, {"id": "u028", "kind": "list-item", "locator": "body:L64-L64", "preview": "1. Record the compiler's registers/thread, spill loads/stores, static/dynamic shared memory, barriers, threads/CTA, and cluster shape.", "sha256": "d16c6acd3215b8f25c44c532f8c911211631184ea4f19611507b0865dcbf5215"}, {"id": "u029", "kind": "list-item", "locator": "body:L65-L65", "preview": "2. Compute occupancy with the CUDA occupancy APIs for the actual launch; do not equate one warpgroup with one CTA.", "sha256": "61f8007df8291d17b10b5d98fa24b9e5270e9671577f6d2185f80148fcd9a1d0"}, {"id": "u030", "kind": "list-item", "locator": "body:L66-L66", "preview": "3. Sweep legal instruction descriptors, CTA tiles, pipeline depth, TMEM column partitioning, and epilogue batch width.", "sha256": "c38ba2f0bc7de4c81597e253f093a2e181a747fa3c44afa31f9fc7ca8fe9edcc"}, {"id": "u031", "kind": "list-item", "locator": "body:L67-L67", "preview": "4. Benchmark identical shapes, datatypes, outputs, synchronization, warmup, and trial statistics. A fixed latency such as \u201c420 cycles per TMEM load\u201d is not an ISA guarantee.", "sha256": "254ff0f6b010a5a5da0857102c7f77d31d8d19ebeb3a17d4d96f5fb73b3da8e2"}, {"id": "u032", "kind": "list-item", "locator": "body:L68-L68", "preview": "5. Inspect generated PTX/SASS to confirm that the intended tcgen05 shapes, waits, and no unexpected spills are present.", "sha256": "a0dc065f5f6cd024c8097f8d5c531813014b8bcd3af6638ce958f8f15187547f"}, {"id": "u033", "kind": "list-item", "locator": "body:L72-L72", "preview": "- TMEM is not an ordinary CUDA pointer space. Load through a legal collective tcgen05 copy operation before scalar arithmetic.", "sha256": "5a0dc36e41360a05b9484ba2c76a8a40f4c50cd91d824efc8390bd263d26569e"}, {"id": "u034", "kind": "list-item", "locator": "body:L73-L73", "preview": "- Do not issue collective allocation, load/store, or deallocation from lane 0 alone.", "sha256": "7a08a8655056273dbd66d60daed365c7599fec8e52caf56e1ba389cdb33f2a41"}, {"id": "u035", "kind": "list-item", "locator": "body:L74-L74", "preview": "- Do not substitute `tcgen05.fence` or `__syncthreads()` for asynchronous MMA completion.", "sha256": "39b83c942611535ed32d220db39984aaaa353937f00d2407e2638f6864583fa9"}, {"id": "u036", "kind": "list-item", "locator": "body:L75-L75", "preview": "- Do not zero TMEM unconditionally when a false `enable-input-d` predicate provides the intended first-write semantics.", "sha256": "b99c99b2e0c4cd1c80b2fe08796a0916cc6f0b10aa816e84fc12cc3a76507733"}, {"id": "u037", "kind": "list-item", "locator": "body:L76-L76", "preview": "- Do not treat TMEM-resident D as the entire kernel's register allocation; the epilogue can still spill.", "sha256": "34b5e7d2ea4620b8b6eac38d7fd6247040e0caa5401bfee293902cc71ebd84c9"}, {"id": "u038", "kind": "list-item", "locator": "body:L77-L77", "preview": "- Do not describe missing deallocation as a defined recoverable \u201cleak.\u201d The normative rule is explicit matching deallocation before exit.", "sha256": "7459f5d2fab8c6fe59eeef14ce208773a6ea79f29893b81890e9546f5334030d"}, {"id": "u039", "kind": "list-item", "locator": "body:L81-L81", "preview": "- [PTX ISA 9.0 WGMMA register fragments](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#asynchronous-warpgroup-level-matrix-register-fragment-wgmma-64n16)", "sha256": "56a14ee2db1f1b79e0e525648d0d966aaa69571dfe36c87de7168f26881ef269"}, {"id": "u040", "kind": "list-item", "locator": "body:L82-L82", "preview": "- [PTX ISA 9.0 Tensor Memory](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory)", "sha256": "aed47f18c514497e50694f89415704f98533229e52ed733c1898d3c9bb3e2747"}, {"id": "u041", "kind": "list-item", "locator": "body:L83-L83", "preview": "- [PTX ISA 9.0 tcgen05 allocation](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit)", "sha256": "d42d0c01cb062292369af97827421a3a287ec970b4bc869b80edaefb263b177c"}, {"id": "u042", "kind": "list-item", "locator": "body:L84-L84", "preview": "- [PTX ISA 9.0 tcgen05 MMA](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-mma-instructions-mma)", "sha256": "732ea76b4a51fe3c2ffcae7ea22d70813776ee650170d529574101600b2a1686"}, {"id": "u043", "kind": "list-item", "locator": "body:L85-L85", "preview": "- [CUDA 13.0.2 Hopper Tuning Guide](https://docs.nvidia.com/cuda/archive/13.0.2/hopper-tuning-guide/index.html#occupancy)", "sha256": "acaee20e11d45fd20a8d0c6e29f05aec3d89d17a203eae0a47e821c7f1c2946c"}, {"id": "u044", "kind": "list-item", "locator": "body:L86-L86", "preview": "- [CUDA 13.0.2 Blackwell Tuning Guide](https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy)", "sha256": "8d963db7f76eb6508d3be3b8853709f57f9a8b2f98e623d121cff16c31de6585"}, {"id": "u045", "kind": "list-item", "locator": "body:L87-L87", "preview": "- [FlashAttention-3 paper](https://arxiv.org/abs/2407.08608)", "sha256": "5a5ef1b6d90749138db83d063d75df914e64702b3d88af097f7ab1b7918bd60c"}, {"id": "u046", "kind": "list-item", "locator": "body:L88-L88", "preview": "- [FlashAttention-4 paper v1](https://arxiv.org/abs/2603.05451v1)", "sha256": "0fb60e121910c6e3db40016b49479cf32b63868bf4c07d1765c52f09c5adad70"}, {"id": "u047", "kind": "list-item", "locator": "body:L92-L92", "preview": "- [Tensor Memory](../hardware/tmem.md) \u2014 allocation, addressing, and access constraints", "sha256": "b3c60111974bb86dc60da7215cbb37b18f5ed884f7afc8f2ba9e888704ee4c81"}, {"id": "u048", "kind": "list-item", "locator": "body:L93-L93", "preview": "- [tcgen05 MMA](../hardware/tcgen05-mma.md) \u2014 exact operation and completion semantics", "sha256": "8eaf7f0f1fcdebbab2fb0edc10f2597a39ea62bb5d5350106b42fccbf9e6260c"}, {"id": "u049", "kind": "list-item", "locator": "body:L94-L94", "preview": "- [register pressure](../patterns/register-pressure.md) \u2014 diagnosis and compiler-resource evidence", "sha256": "63798ee2070c890c2bee614823e025d90ee4f0841197c7da548cb5327b8c297d"}], "confidence_claimed": "verified", "headings": ["What actually changes", "Storage and lifecycle contrast", "Migration lifecycle", "Overlap without invented guarantees", "FlashAttention-4 case study", "Evidence-driven retuning", "Common migration errors", "Primary references", "Related"], "id": "migration-register-to-tmem", "path": "wiki/migration/register-to-tmem.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/prs/vllm/PR-22738.md", "revision": "b1361c72", "url": "https://github.com/vllm-project/vllm/pull/22738"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "pr-vllm-22738"], "title": "Register Accumulators to TMEM", "type": "migration", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "138004faa6219749f4d0e9072b9bca0649a4a7ad20e9616caa52e18ea33b5b17", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Port the programming model, not just the opcode:", "sha256": "9be3861214d8d1c37479c20bd21f2a3e7c33c7460656c78dc9992c6bbbe1999a"}, {"id": "u002", "kind": "table-row", "locator": "body:L9-L9", "preview": "| Concern | SM90 WGMMA | SM100 tcgen05.mma | | MMA issue | Warpgroup collective | One thread for group-1 or group-2 MMA |", "sha256": "aa5e3304df841c5d5e3ac5c52d103b8fcf0d8e0bb2a39c54a026f790dd7a4b9a"}, {"id": "u003", "kind": "table-row", "locator": "body:L10-L10", "preview": "| Concern | SM90 WGMMA | SM100 tcgen05.mma | | D accumulator | Per-thread registers | TMEM |", "sha256": "599eed1c6192c3cdba2fd7c04288ba5f919d0307d513ea12d52ed5533800a1f3"}, {"id": "u004", "kind": "table-row", "locator": "body:L11-L11", "preview": "| Concern | SM90 WGMMA | SM100 tcgen05.mma | | A operand | SMEM-descriptor or register forms, depending on instruction | SMEM-descriptor or TMEM-address forms |", "sha256": "c8e2f6685d308cb41e7788d727dab8bf0129426bad70f0138f73a6c64cb636c6"}, {"id": "u005", "kind": "table-row", "locator": "body:L12-L12", "preview": "| Concern | SM90 WGMMA | SM100 tcgen05.mma | | B operand | SMEM descriptor | SMEM descriptor |", "sha256": "0966cfea21760a831d495ee1346a258dd33095cff8f2e23e5d7148f1280f1c8d"}, {"id": "u006", "kind": "table-row", "locator": "body:L13-L13", "preview": "| Concern | SM90 WGMMA | SM100 tcgen05.mma | | MMA completion | Commit/wait groups | `tcgen05.commit` plus mbarrier wait |", "sha256": "129b864fde6ae8e8e58264f223c3ab52804dcb50c282146b2a153673afe572eb"}, {"id": "u007", "kind": "table-row", "locator": "body:L14-L14", "preview": "| Concern | SM90 WGMMA | SM100 tcgen05.mma | | Cross-thread ordering | WGMMA-specific rules | tcgen05 fences composed with an execution-ordering operation |", "sha256": "2ba345a4115e7a6e1f81acbd1416a0f89dc2ee2033027406b83461798bb45007"}, {"id": "u008", "kind": "table-row", "locator": "body:L15-L15", "preview": "| Concern | SM90 WGMMA | SM100 tcgen05.mma | | Narrow floating formats | FP8 WGMMA forms | FP8/FP6/FP4 plus block-scaled MX/NVFP4 kinds |", "sha256": "5947c0ca6e715328562acf6c43de21c60e196b9155df29bf170d6e250ea8b9e2"}, {"id": "u009", "kind": "prose", "locator": "body:L17-L17", "preview": "The exact old WGMMA form matters. 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Group-1 allocation/deallocation is warp-collective; group 2 requires one warp in each CTA of the pair.", "sha256": "94550e33d2e5fc9492d28f341ecdc5ca0655fb2f1c88303fdb7165407f78fcd9"}, {"id": "u013", "kind": "list-item", "locator": "body:L24-L24", "preview": "4. Keep A/B backing storage unchanged until all asynchronous MMA consumers have completed.", "sha256": "e1465bb385f2612cdc483569cb82b1fcee5fb9aaebcb9eeb65667686e7e33848"}, {"id": "u014", "kind": "list-item", "locator": "body:L25-L25", "preview": "5. Replace WGMMA group completion with `tcgen05.commit` and an mbarrier wait. Add tcgen05 fences only where an execution-ordering handoff must order tcgen05-visible state across threads or CTAs.", "sha256": "4362a63d2b1bd22a3096480f6c9a35d00538f93e94821b33c705086971b544ad"}, {"id": "u015", "kind": "list-item", "locator": "body:L26-L26", "preview": "6. Transfer completed accumulator values from TMEM to registers with `tcgen05.ld`, observe its completion/access rules, then run the epilogue.", "sha256": "cc2fdea219e29be1d20d93e0ba014159d0e34b2c8e0de0d4b01083b03c8a177d"}, {"id": "u016", "kind": "list-item", "locator": "body:L27-L27", "preview": "7. Deallocate every dynamic TMEM allocation before kernel exit. Use the same `cta_group` value for all tcgen05 instructions in the kernel.", "sha256": "93a1c4bb169b8c6c02b3b85f458290d7346ff8af1ea4b70ae3f779db14d83181"}, {"id": "u017", "kind": "list-item", "locator": "body:L28-L28", "preview": "8. Retune CTA/cluster shapes, pipeline stages, thread roles, descriptors, and epilogue scheduling on the target workload.", "sha256": "7f11e9b39fa11e8d8ebfaa1313cf7dd006346a8458830b0170a888d8b75eb94d"}, {"id": "u018", "kind": "prose", "locator": "body:L32-L32", "preview": "`tcgen05.alloc` writes a 32-bit TMEM address to shared memory. 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A `tcgen05.fence` is an ordering and co", "sha256": "2c0f765385f99c91fd6bba2fce4d7f86c037b58d0a20e7f6ebd86695c01aa76c"}, {"id": "u021", "kind": "prose", "locator": "body:L40-L40", "preview": "After completion and any necessary thread handoff, epilogue warps use `tcgen05.ld` to bring their accessible TMEM lanes into registers. Ordinary bias, activation, conversion, and global-store code then operates on those register values. Pre", "sha256": "9a0355a075bf524abfe540283b025bfdd995ccf1fff1a336741a4c22859c7514"}, {"id": "u022", "kind": "prose", "locator": "body:L44-L44", "preview": "Do not mechanically convert every 64-byte swizzle to 128-byte swizzling. The tcgen05 shared-memory descriptor defines valid no-swizzle, 128B, 64B, and 32B modes, subject to mode-specific alignment and layout constraints. The 128B choice can", "sha256": "a5608028d7dfad8506b7b6106284085462c52175cc29c7fd2293ab77560f02b3"}, {"id": "u023", "kind": "prose", "locator": "body:L46-L46", "preview": "Similarly, there is no universal Hopper-to-Blackwell rule that doubles M. WGMMA and tcgen05 each expose multiple shapes; tcgen05 M/N are encoded in `idesc` and constrained by kind, layout, CTA group, and target ISA. Treat m128xn256xk16 and ", "sha256": "a8234afdf8accc4e7f9754a352400271f4c0da85834278656ef70b903510bf4e"}, {"id": "u024", "kind": "prose", "locator": "body:L50-L50", "preview": "Single-thread MMA issue can free instruction-issue capacity for TMA, descriptor preparation, epilogue, reductions, or scheduling. It does not determine the kernel's total thread count: TMEM allocation, TMEM loads, TMA, epilogue, and barrier", "sha256": "9c73fd720d7cee08f667430e653f338b5de11c015ad161b38c7e22150ac74a05"}, {"id": "u025", "kind": "prose", "locator": "body:L52-L52", "preview": "Moving D out of the GPR file also changes the register budget. Revisit tile size, pipeline depth, and launch bounds, but do not assume that lower accumulator pressure automatically increases occupancy; SMEM, TMEM, barriers, threads, and reg", "sha256": "a9ec2eb6b76b5bbe2308d3a68e5b60337addc6a971601f555cb98fb058f78f48"}, {"id": "u026", "kind": "prose", "locator": "body:L56-L56", "preview": "CUTLASS does not reduce this port to replacing an architecture tag and one schedule token. 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Instrument work count and time per worker to separate shortage from variable-duration imbalance.", "sha256": "85d7667eb183b65674cf5bd1b4a61e1b431faf63459925677d7428c012beb7db"}, {"id": "u019", "kind": "list-item", "locator": "body:L40-L40", "preview": "4. Hold decomposition constant when testing static versus dynamic acquisition; test decomposition separately.", "sha256": "52d3102612d922f1fc85038af5c4ab2562f4ebabc9055143ddff583eafbdc805"}, {"id": "u020", "kind": "list-item", "locator": "body:L41-L41", "preview": "5. Report end-to-end time along with active-SM distribution, scheduler overhead, cache traffic, occupancy, and regressions.", "sha256": "baade11400a3d956b8272f80cca633553e8e4a8b7937e365aec1771558f87edb"}, {"id": "u021", "kind": "list-item", "locator": "body:L45-L45", "preview": "- [CUDA Programming Guide: Cluster Launch Control](https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/cluster-launch-control.html)", "sha256": "434985b84456959e4f53d2ca8c885026c1e84c1718e8d70d3a58f21c7cfff6cd"}, {"id": "u022", "kind": "list-item", "locator": "body:L46-L46", "preview": "- [PTX ISA 9.0 CLC target and request semantics](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel)", "sha256": "055e35e565a291ec0e9bbe519173d1aec130896cce80b1a65209730c3f346eb5"}, {"id": "u023", "kind": "list-item", "locator": "body:L47-L47", "preview": "- [CUTLASS 4.5.0 CLC scheduling](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md)", "sha256": "f82b94cccb8b9883e584fa5ec6b7e602e2b7c3247932e262a7a61b54773d925d"}, {"id": "u024", "kind": "list-item", "locator": "body:L48-L48", "preview": "- [Pinned tutorial v6](https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v6.cu)", "sha256": "5b526dd64c330d7d736082b7324135601597bb08ed0687532ebef171bf9798d1"}, {"id": "u025", "kind": "list-item", "locator": "body:L49-L49", "preview": "- [Tutorial result progression](https://gau-nernst.github.io/tcgen05/)", "sha256": "797b16f54ff8d25ba34fefe90153d0a2e58a3efa7414f3594476c0b133a26bad"}], "confidence_claimed": "verified", "headings": ["Define the Missing Parallelism", "Distinguish Four Cases", "Scheduler Choices", "Source-Reported Tutorial Result", "Verification Checklist", "Primary References"], "id": "pattern-low-sm-utilization", "path": "wiki/patterns/low-sm-utilization.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/docs/cutlass-clc-documentation.md", "url": "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"}, {"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}], "risk_flags": ["ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "doc-cutlass-clc", "doc-ptx-isa-sm100"], "title": "Low SM Utilization", "type": "pattern", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "df62414848150544dd22c908b1f015e7c3925bad2512fe91186cfc9edffc8e8b", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "A kernel is memory-bandwidth bound when its measured arithmetic intensity places it on the memory side of the relevant roofline and its useful throughput is limited by an attained memory ceiling. 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Any residual edge-tile or predication cost needs generated-code and profile evidence for the selected kernel.", "sha256": "e1ad215b1834aea24c4c71f10f9dd49adb76027b5707f91aa558f23fed0775eb"}, {"id": "u015", "kind": "prose", "locator": "body:L46-L46", "preview": "Keep persistence, work acquisition, and decomposition as separate variables:", "sha256": "72b5c8bd73eb8523601df6dc917588754a8f96308e1b63a0634cf317643b4636"}, {"id": "u016", "kind": "list-item", "locator": "body:L48-L48", "preview": "1. A static persistent worker can advance through a deterministic logical-work", "sha256": "2ebeac42de4c86f459f32944d820f960af294bb7e3e90652bce81f1750d37a47"}, {"id": "u017", "kind": "prose", "locator": "body:L49-L50", "preview": "sequence. CUDA still decides where its block runs; the rule is not a precomputed tile-to-physical-SM map.", "sha256": "2141d38662b0abc377581ebce726e1b0f19cb22664d04f848c469c8824eb4a2d"}, {"id": "u018", "kind": "list-item", "locator": "body:L51-L51", "preview": "2. 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Low TMA or tensor-core activity, a warp sampled at a barrier wait, or a phase-local utilization drop is only a lead. Expected dependen", "sha256": "da7a72a788c774770d5fdbfdf3a011e6425280d30b33bc03a25a0f39f5c83564"}, {"id": "u002", "kind": "prose", "locator": "body:L5-L5", "preview": "Nsight Compute's Warp State Statistics describes why sampled warps could not issue, while Scheduler Statistics shows whether schedulers had eligible warps and issued instructions. NVIDIA cautions that stalls are not necessarily performance-", "sha256": "7e0728caba67afc2a3981a4c5be636334cc90fa93bf4fc0ee6782c0c878e3126"}, {"id": "u003", "kind": "prose", "locator": "body:L9-L9", "preview": "Do this before tuning around an mbarrier wait:", "sha256": "14ed4da2dccf88e9f5096dc225ad0185ddffa3f32922f4eba71d0c4949f3c428"}, {"id": "u004", "kind": "list-item", "locator": "body:L11-L11", "preview": "1. Identify the exact barrier object, owner, initialized arrival count, initial phase, and storage stage for the wait.", "sha256": "214f90bfaac4e1a67bc424fb4679a4d4914d5f861188655234c0caaa267b4043"}, {"id": "u005", "kind": "list-item", "locator": "body:L12-L12", "preview": "2. For a TMA global-to-shared load, account for the producer's software arrival and expected transaction bytes. `mbarrier.arrive.expect_tx` performs an arrival and adds transaction bytes; the TMA `.mbarrier::complete_tx::bytes` operation de", "sha256": "3e96182dbe690a820cbf9b5e9fdb6b3cc25b08f91eca7cef16719bd9922e117c"}, {"id": "u006", "kind": "list-item", "locator": "body:L13-L13", "preview": "3. Wait for the matching phase of that same object. Phase parity changes when that barrier completes a phase and is reused; \u201cflip after every wait\u201d is not a valid global rule when a thread waits on multiple objects or phases.", "sha256": "fc67e43b74ef2c49970cdfcfcdfbc17e669fe14236db9b9cbb80a129f16f059e"}, {"id": "u007", "kind": "list-item", "locator": "body:L14-L14", "preview": "4. A successful acquire wait supplies the documented visibility for associated prior `cp.async.bulk` work before the consumer reads SMEM.", "sha256": "cad75bba1a6209991e889aebed6a0e54d9a993ac199a3b785434c82630900b3e"}, {"id": "u008", "kind": "list-item", "locator": "body:L15-L15", "preview": "5. Before reusing SMEM operands read by asynchronous MMA, attach completion of the relevant tcgen05 work with `tcgen05.commit` and observe its mbarrier. Issue is not completion.", "sha256": "0471e26fc7edd3ac9914e4d364ca725d6935473ed772fc429bdde5c130e8f362"}, {"id": "u009", "kind": "list-item", "locator": "body:L16-L16", "preview": "6. When asynchronous tcgen05 operations cross a thread handoff, place `tcgen05.fence::before_thread_sync` and `tcgen05.fence::after_thread_sync` around the applicable execution-ordering operation. The after fence is not a generic replacemen", "sha256": "a5a5678d754c4afc5251f822e93233a03ffb7e18a06d9f8a9157f3a0686476c6"}, {"id": "u010", "kind": "list-item", "locator": "body:L17-L17", "preview": "7. Verify prologue, steady-state wraparound, short loops, and the producer/consumer tails. A correct steady-state loop can still hang or reuse live storage at a boundary.", "sha256": "44d732e3dec9b913fb7e525f92cb9f90686aa569ff6b9dac92ebae4e0e8b19e2"}, {"id": "u011", "kind": "prose", "locator": "body:L19-L19", "preview": "An extra software arrival is erroneous only relative to the barrier's initialized and phase-specific accounting. Diagnose pending arrivals and transaction bytes separately instead of assuming that TMA hardware performs another arrival.", "sha256": "b0db1b4e9bcf02bdb609d55928eb002804bcdc285274448f73a2424b521cc581"}, {"id": "u012", "kind": "list-item", "locator": "body:L23-L23", "preview": "1. Establish a synchronized end-to-end timing regression on fixed inputs and confirm outputs against a reference. Record GPU, clocks, toolkit, build flags, kernel name, launch shape, and resource use.", "sha256": "c93c68e7cb1a483a6a1d4d21cf5f26631ffbbb1a2a8ab85db6bec467a9cb4798"}, {"id": "u013", "kind": "list-item", "locator": "body:L24-L24", "preview": "2. Collect Speed-of-Light, Scheduler Statistics, Warp State Statistics, and source/SASS correlation with the sections available in the installed Nsight Compute. Account for replay and sampling effects.", "sha256": "a67f70665ee157c5e1909e56a42f789904f46a2629e9a837c8b9573a46cb1eb5"}, {"id": "u014", "kind": "list-item", "locator": "body:L25-L25", "preview": "3. Map the dominant not-issued locations to concrete edges: TMA-full wait, MMA-completion wait, output-buffer reuse, CTA barrier, queue starvation, or pipeline prologue/tail.", "sha256": "9110e18720b271d8f64c2dd21aeb2b3f56a93dac9966380f70d9299ba74a4a67"}, {"id": "u015", "kind": "list-item", "locator": "body:L26-L26", "preview": "4. State a prediction. For example: if TMA readiness is the critical edge, a legal extra operand stage should reduce that wait and runtime; if only the tail is exposed, the steady-state wait distribution should remain largely unchanged.", "sha256": "36934631ace735be26b95ac853c3673c22dce4b1f4969d98234b65b90350f632"}, {"id": "u016", "kind": "list-item", "locator": "body:L27-L27", "preview": "5. Change one variable and repeat identical correctness, warmup, timing, and profiler collection. Reject a cause when its predicted counter and time movement do not occur.", "sha256": "2cd9d472de4c08e8283c6bd52fcbd6704e0be919b520fe671cb542c07a6841e4"}, {"id": "u017", "kind": "table-row", "locator": "body:L31-L31", "preview": "| Controlled change | Plausible target | Required controls and costs | | Vary legal SMEM stage count | Producer cannot stay far enough ahead of MMA | Same tile/math/roles; record SMEM, occupancy, short-loop behavior, and tail |", "sha256": "04c436dbcb263690831932e9dc3de9489d78d1aff38a257a533eb521cdf51549"}, {"id": "u018", "kind": "table-row", "locator": "body:L32-L32", "preview": "| Controlled change | Plausible target | Required controls and costs | | Separate long-lived warp roles | Role handoff or control work is on the issue path | Same stages and tile; record registers, active warps, and per-role idle/backpressu", "sha256": "b5b7ebcf0548afdbddcb877c7fcc70d3352750d277941928b752f71dcd59231e"}, {"id": "u019", "kind": "table-row", "locator": "body:L33-L33", "preview": "| Controlled change | Plausible target | Required controls and costs | | Add a second TMEM output region | Epilogue holds the only accumulator region | Prove disjoint lifetime; record TMEM columns and epilogue/MMA completion waits |", "sha256": "ab79f66f2d1b762e0d24d903673ac799dce4d639794e042dceeaa12daa1f3b07"}, {"id": "u020", "kind": "table-row", "locator": "body:L34-L34", "preview": "| Controlled change | Plausible target | Required controls and costs | | Interleave two query/output tiles | Softmax/correction and MMA have independent ready work | Prove separate state and dependencies; compare one versus two query stages", "sha256": "995291335dcbcf4e24bb3a145bedf98f4fa72eb4f49add2fca9612b80d272803"}, {"id": "u021", "kind": "prose", "locator": "body:L36-L36", "preview": "None is a universal cure. More stages consume storage and can reduce occupancy; specialization adds warps and synchronization; TMEM buffering consumes columns; multi-tile schedules increase live state. A memory-bound roofline classification", "sha256": "214e9852ed70ec2446680cf91d4def45cd5a23b65b1c8c942241a501ce9405b5"}, {"id": "u022", "kind": "prose", "locator": "body:L40-L40", "preview": "Gau Nernst reports the following for one `M=N=K=4096` BF16 GEMM on a Modal B200 using PyTorch 2.9.1 and CUDA 13. Percentages below are computed from the reported 1506.74-TFLOP/s cuBLAS value.", "sha256": "b5438bc9ed3152dfc868c28a134f08b5fad7f494f7c6b85998f51619284bdd40"}, {"id": "u023", "kind": "table-row", "locator": "body:L44-L44", "preview": "| Version | Author's cumulative version label | TFLOP/s | cuBLAS ratio | | v1a | basic tcgen05 + 2D 16-byte TMA | 254.62 | 16.90% |", "sha256": "2ec8ddf8e324506fc9632dec2e2b8bc384ea8deefdb9267c6cdcdc2c2732566d"}, {"id": "u024", "kind": "table-row", "locator": "body:L45-L45", "preview": "| Version | Author's cumulative version label | TFLOP/s | cuBLAS ratio | | v2b | 3D 128-byte TMA | 695.43 | 46.15% |", "sha256": "dbba2419e3054de28eff2b7f1fd83d83d98f18bea3fbea121804656bd24e694c"}, {"id": "u025", "kind": "table-row", "locator": "body:L46-L46", "preview": "| Version | Author's cumulative version label | TFLOP/s | cuBLAS ratio | | v3 | pipelining | 939.61 | 62.36% |", "sha256": "8b5c05c6b3e8641c5d14409e7371999aef50591dc7ded0fb18dd77e6bb1138f1"}, {"id": "u026", "kind": "table-row", "locator": "body:L47-L47", "preview": "| Version | Author's cumulative version label | TFLOP/s | cuBLAS ratio | | v4 | warp specialization | 1208.83 | 80.23% |", "sha256": "12da1a7a1107856224c31730db16b1b6d72ccb37605926b17cd3f1a7d9ec851f"}, {"id": "u027", "kind": "table-row", "locator": "body:L48-L48", "preview": "| Version | Author's cumulative version label | TFLOP/s | cuBLAS ratio | | v5 | 2-SM MMA | 1302.29 | 86.43% |", "sha256": "f849944c51b336479e60eefa90208c5313995e912594c9861c162dfbec203411"}, {"id": "u028", "kind": "table-row", "locator": "body:L49-L49", "preview": "| Version | Author's cumulative version label | TFLOP/s | cuBLAS ratio | | v6 | persistent kernel with static scheduling | 1475.93 | 97.96% |", "sha256": "37b786019302d87416e187fb57c9b75385ecb50a1b91484b1afc0437adc2fac5"}, {"id": "u029", "kind": "prose", "locator": "body:L51-L51", "preview": "The pinned v3 source instantiates two stages, not three. Each row is a cumulative source version rather than an isolated microbenchmark of the named mechanism. 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There is no universal \u201cbelow four times the SM count\u201d cutoff: the remainder, wave duration, other phases, ", "sha256": "f324cd0832cae3c8f0339ca28879361e2a3ea07764d3318bfdc48a357f3fec53"}, {"id": "u006", "kind": "list-item", "locator": "body:L17-L17", "preview": "1. Record logical tiles/clusters, grid and cluster dimensions, available worker capacity, residency limits, and per-work-item duration.", "sha256": "e795d774faa4fd3b84027ef69d3dbb0f4ac2f61de31b0ad0ae7c902891d22e3f"}, {"id": "u007", "kind": "list-item", "locator": "body:L18-L18", "preview": "2. Predict wave count and the final remainder from the simplified model.", "sha256": "1d8d9be6330b539daf5cecf3a3e9ca5bdc43c8d66dc6dafc1626dcc58ab23c80"}, {"id": "u008", "kind": "list-item", "locator": "body:L19-L19", "preview": "3. Use time-resolved activity or instrumented worker records to locate the underfilled interval at the end, rather than inferring it from aggregate utilization.", "sha256": "171e09c6edcc03571aba5731487e7092cbfe98166edaacb3f751eca20419d90d"}, {"id": "u009", "kind": "list-item", "locator": "body:L20-L20", "preview": "4. Sweep nearby problem sizes or tile shapes. A wave-quantization hypothesis predicts a sawtooth response aligned with changes in the remainder, after controlling total work.", "sha256": "23112755735c4dfdfb4280e3bb343028ef65ce6126d88127f7553182529809e6"}, {"id": "u010", "kind": "list-item", "locator": "body:L21-L21", "preview": "5. Separate unequal tile durations: a long straggler is load imbalance even if the tile-count remainder is zero.", "sha256": "12e6a06a0cf28b05b3c3a675a4db26089ec744d706d3001cb0bd2b7b1e7342a7"}, {"id": "u011", "kind": "prose", "locator": "body:L23-L23", "preview": "CUDA schedules ordinary grid blocks onto available SMs; a static grid-stride loop fixes logical worker indices, not `blockIdx`-to-physical-SM placement. A fixed grid therefore does not mean CUDA lacks dynamic block scheduling.", "sha256": "6452a882b8c5416203c08e6041cef08ba04ccf0849deafc93a15afae865c9512"}, {"id": "u012", "kind": "list-item", "locator": "body:L27-L27", "preview": "- A static persistent loop lets a resident CTA process multiple logical work items. Worker count is selected from problem decomposition, cluster/resource limits, and policy\u2014not necessarily one CTA per physical SM. Finite work still has a fi", "sha256": "9db529aa6ae9bd030c3c8089509d63d8584dd95219b31f6d18be3cdf57767e73"}, {"id": "u013", "kind": "list-item", "locator": "body:L28-L28", "preview": "- Cluster Launch Control lets a selected thread request cancellation of an unspecified not-yet-started block or cluster and process the returned grid ID. CLC redistributes existing IDs; it cannot turn eight remaining independent tiles into ", "sha256": "0a5afba4961508157c3c0154f138d89d14c968938adcce7244fc0c81efbacd1c"}, {"id": "u014", "kind": "list-item", "locator": "body:L29-L29", "preview": "- Raster order and swizzle are coordinate transforms. Test them for locality while holding work acquisition fixed; they do not create work or guarantee balanced durations.", "sha256": "7fd94e42d1d2576ed4e87b200e19e9776b4d787a553e5e40fcef1a118dd2e23a"}, {"id": "u015", "kind": "list-item", "locator": "body:L30-L30", "preview": "- Stream-K or Split-K may create more independent partitions when tile-level work is insufficient. Evaluate reduction traffic, workspace, synchronization, determinism, and numerical effects separately.", "sha256": "dd0d2eea0bfed3c0fd23a77f78dc563c2da37c925225e0718d43ab29b94f49d4"}, {"id": "u016", "kind": "prose", "locator": "body:L32-L32", "preview": "Compare static and CLC-backed persistence with identical math, decomposition, tile/cluster shapes, grid, resources, and timing. Record CLC request results and per-worker work/time distribution. PTX ISA 9.0 requires `sm_100` or higher for CL", "sha256": "fcb099d00bab658c03147f5a9ec638a5500d4389439fad74c26eef326c17a5e8"}, {"id": "u017", "kind": "prose", "locator": "body:L36-L36", "preview": "Gau Nernst's Modal B200 has 148 SMs. In the author's `M=N=K=4096` experiment, v5 reports 1302.29 TFLOP/s (86.43% of cuBLAS) and v6 reports 1475.93 TFLOP/s (97.96%). The v6 change is static persistence plus output-pipeline/epilogue-role chan", "sha256": "6f9b202e053f7d5da7cb68d6ce3e62c4533da60caaa7c16fa6b728a202a33c95"}, {"id": "u018", "kind": "list-item", "locator": "body:L40-L40", "preview": "- [CUDA Programming Guide: block and cluster scheduling](https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html)", "sha256": "502cb7460a63cee49afa6d82044dcbfe0b1a257319a5ceb0c2543173f8b71844"}, {"id": "u019", "kind": "list-item", "locator": "body:L41-L41", "preview": "- [PTX ISA 9.0 CLC](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel)", "sha256": "8c89668f826fa705d199d168dcff6bea3195792e01de2698f854bb90db46ce5f"}, {"id": "u020", "kind": "list-item", "locator": "body:L42-L42", "preview": "- [CUTLASS 4.5.0 CLC scheduling](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md)", "sha256": "f82b94cccb8b9883e584fa5ec6b7e602e2b7c3247932e262a7a61b54773d925d"}, {"id": "u021", "kind": "list-item", "locator": "body:L43-L43", "preview": "- [Pinned tutorial v6 source](https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v6.cu)", "sha256": "d47967878d57c59a54264abe233d783fe466469b45b79870f89f24ba6c73531a"}, {"id": "u022", "kind": "list-item", "locator": "body:L44-L44", "preview": "- [Tutorial result progression](https://gau-nernst.github.io/tcgen05/)", "sha256": "797b16f54ff8d25ba34fefe90153d0a2e58a3efa7414f3594476c0b133a26bad"}], "confidence_claimed": "verified", "headings": ["Exact Simplified Model", "Confirm a Last-Wave Cause", "Scheduler and Decomposition Choices", "Tutorial Scope", "Primary References"], "id": "pattern-tail-effect", "path": "wiki/patterns/tail-effect.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/docs/cutlass-clc-documentation.md", "url": "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"}, {"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}], "risk_flags": ["code", "ordering"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-nvidia-tuning-guide", "blog-tcgen05-tutorial", "doc-cutlass-clc", "doc-ptx-isa-sm100"], "title": "Tail Effect \u2014 Last-Wave Underutilization", "type": "pattern", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "3af5831a5b82c05926f7c6ecb8301f7e0c4d3d03774f809a36f86ef5e95df07b", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "PTX global loads and stores can carry cache operators and eviction-priority qualifiers. Global loads can also carry L2 prefetch-size hints. These controls let a kernel express a preference for a particular access; they do not guarantee cach", "sha256": "58fc3708b4bf0b06839ff597548bd0d45b4f269cf14a89d70ed6547be08989a6"}, {"id": "u002", "kind": "table-row", "locator": "body:L9-L9", "preview": "| Form | PTX meaning | Not guaranteed | | `L1::no_allocate` | Selects an L1 eviction priority that may be applied | That the access bypasses L1 |", "sha256": "8225a6a519ce7e32ce882a77aa1056b9169be6e42a5f22560b898481579b8eef"}, {"id": "u003", "kind": "table-row", "locator": "body:L10-L10", "preview": "| Form | PTX meaning | Not guaranteed | | `L1::evict_first` | Requests first-eviction priority | Immediate eviction |", "sha256": "bc512e53bc172d71d0cb8d1ccfa67a7842621adcf4c72daf4c4016c906262a26"}, {"id": "u004", "kind": "table-row", "locator": "body:L11-L11", "preview": "| Form | PTX meaning | Not guaranteed | | `L1::evict_last` | Requests last-eviction priority | Persistent residence |", "sha256": "54e7c9299b1db1db2546f3ad6f51fd38f3f1ea1c67355720fe46d456320adaa4"}, {"id": "u005", "kind": "table-row", "locator": "body:L12-L12", "preview": "| Form | PTX meaning | Not guaranteed | | `L2::64B`, `128B`, `256B` | Hints that additional data of that size be fetched into L2 | A wider memory instruction or a completed prefetch |", "sha256": "23a0133f060ed5d78700c80e13b705675ace800df529b843bb4417b4894b9035"}, {"id": "u006", "kind": "table-row", "locator": "body:L13-L13", "preview": "| Form | PTX meaning | Not guaranteed | | `L2::cache_hint` with a policy operand | Supplies a created L2 eviction policy | That the hint is respected or changes memory consistency |", "sha256": "92165e23d514905a7089b6f790e98bc0b81b229b23cd9f6eb1a558c76feb682e"}, {"id": "u007", "kind": "prose", "locator": "body:L15-L15", "preview": "The following are legal PTX 9.0 instruction fragments when their operands and addresses are declared with matching types. Each vector access shown is 16 bytes and therefore requires 16-byte natural alignment:", "sha256": "e6875d2adb5ad541e5579d45da0f70247686265f3f187debecb3662cfe1c686d"}, {"id": "u008", "kind": "code", "locator": "body:L17-L24", "preview": "```ptx .reg .b64 addr_a, addr_b, addr_c; .reg .u32 a<4>, b<4>, c<4>; ld.global.L1::no_allocate.v4.u32 {a0, a1, a2, a3}, [addr_a]; ld.global.L1::evict_last.v4.u32 {b0, b1, b2, b3}, [addr_b]; st.global.L1::evict_first.v4.u32 [addr_c], {c0, c1", "sha256": "dff1576a0ce3b45407dcdc9dddaf973b2f0df90f5c9dc8eedbab93b06b805315"}, {"id": "u009", "kind": "prose", "locator": "body:L26-L26", "preview": "The common \u201cstream A, retain B\u201d explanation is a hypothesis about reuse and interference, not the semantics of the code. Even with correct alignment, the hardware may apply the priorities differently than a literal bypass/keep model suggest", "sha256": "0f8b19c545e0751d4f2f9962b9b26f4586f822f95847e2b4ab0fbb405ea44515"}, {"id": "u010", "kind": "prose", "locator": "body:L30-L30", "preview": "Start from the concrete access trace rather than a kernel label or tensor name:", "sha256": "eeb262f9767e73e0d30f6587d5465e23ddb312d3367caff656125c14d8a1e9b1"}, {"id": "u011", "kind": "list-item", "locator": "body:L32-L32", "preview": "1. Identify which addresses each warp touches, the reuse distance for each line, the live working set, and competing traffic at the same launch shape.", "sha256": "db5d6449fa0ee136e4483eec513b11e760a840112559819e672a1d3c568586fb"}, {"id": "u012", "kind": "list-item", "locator": "body:L33-L33", "preview": "2. Establish a correct default-policy baseline. Hold mapping, vector width, decode, unrolling, register controls, compiler, inputs, and launch parameters constant.", "sha256": "0aaf1ed9f480045eafdcc9a795490fea975fb9496b7da080a6f7dc21a2fcdceb"}, {"id": "u013", "kind": "list-item", "locator": "body:L34-L34", "preview": "3. Change one qualifier at a time. Re-run the same correctness oracle, including sizes that exercise alignment and tail paths.", "sha256": "6f4744fe0b055ceede7d49f44cbe6268747460836c80a678ad1457b7c21208ed"}, {"id": "u014", "kind": "list-item", "locator": "body:L35-L35", "preview": "4. Record generated instructions and resources, then profile cache hit behavior, requested/transferred bytes, stalls, achieved bandwidth, and active warps with metrics available on the installed tool and target.", "sha256": "4bfc53a191440ff619777b08cc32f2adb819edb032cee818fd8539d4679668de"}, {"id": "u015", "kind": "list-item", "locator": "body:L36-L36", "preview": "5. Benchmark every production shape with the same warmup, synchronization, repetitions, and statistic. Retain only scoped improvements; a policy may help one shape and regress another.", "sha256": "ae112842d641a2c358bbe90a6d930cfd3f10160668b7dadbea95eec4259b234f"}, {"id": "u016", "kind": "prose", "locator": "body:L38-L38", "preview": "An input being larger than L2, a kernel being described as memory-bound, or a tensor being called streamed/reused does not by itself predict a useful qualifier. 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Its captured key file exposes surrounding TopK implementation for inspection, but the PR's semantic delta is the small debug-only patch.", "sha256": "c6caf045a6b9260f06d822235725a7371ef237eb9773c2804f1e8bf3dfb8dc89"}, {"id": "u005", "kind": "prose", "locator": "body:L14-L14", "preview": "The new `sm100_tuning` specializations select a tuple rather than a single \u201cvectorized\u201d bit:", "sha256": "ef1ba6a5ffaf5c3db38f4137420cffbd6f9b3147a650d9c0bce7ab83dc894da3"}, {"id": "u006", "kind": "table-row", "locator": "body:L18-L18", "preview": "| Policy dimension | Examples in the captured source | | Classification | input value size, accumulator type/size, offset size, and recognized `plus` operator |", "sha256": "a9e0c1a68c8e41698173559e124463741f1f39a94e516597aef7ad189b74d4d5"}, {"id": "u007", "kind": "table-row", "locator": "body:L19-L19", "preview": "| Policy dimension | Examples in the captured source | | Work partition | `threads` and `items` per thread |", "sha256": "0815c33204b77ed25cca9827b2ab51e07004ebad4b5f9f78e9093d09f3a45c15"}, {"id": "u008", "kind": "table-row", "locator": "body:L20-L20", "preview": "| Policy dimension | Examples in the captured source | | Memory policy | `BLOCK_LOAD_*`, `BLOCK_STORE_*`, and `LOAD_DEFAULT` or `LOAD_CA` |", "sha256": "affc3f2082c6b33e588efad21bb73e3ae75573b1ba705d2cadbef18c285fc8cb"}, {"id": "u009", "kind": "table-row", "locator": "body:L21-L21", "preview": "| Policy dimension | Examples in the captured source | | Look-back behavior | an exponential backoff/delay constructor and its parameters |", "sha256": "d476c9630872da451c8547fe530ade5fa22ca4e2f4e0773635a7b5c3c3731dcb"}, {"id": "u010", "kind": "table-row", "locator": "body:L22-L22", "preview": "| Policy dimension | Examples in the captured source | | Fallback | `Policy1000` selects a matching SM100 specialization; otherwise it falls back to `Policy900`; the double specialization explicitly inherits an SM90 tuning |", "sha256": "612ef7a8a3d8257ec2557bc3eddb18089b41ad5c6f0249bcb1e0eed5db932d78"}, {"id": "u011", "kind": "prose", "locator": "body:L24-L24", "preview": "`items >= 4` does not establish vectorized access. Vector width also depends on iterator contiguity, element type, alignment, load/store algorithm, compiler lowering, and the executed policy. Treat items-per-thread, block size, load/store a", "sha256": "05b467376da229569223be7afe7af2a5044c10fabb1983ccbb1aed8b5a096f2c"}, {"id": "u012", "kind": "list-item", "locator": "body:L28-L28", "preview": "1. Identify the exact primitive and semantic contract: inclusive/exclusive scan, operator, input/output/accumulator types, offset width, aliasing, and empty/large-size behavior.", "sha256": "22bee881668fd269c29db6987e756c55090a7bdd5b4037f8d671563d07193f25"}, {"id": "u013", "kind": "list-item", "locator": "body:L29-L29", "preview": "2. Follow runtime architecture dispatch to the active policy. Confirm whether SM100 has a matching specialization or inherits the SM90/default route.", "sha256": "133fa8b4c60fbf759bbe9b2666428bd7250701273d08f0525df21dea718ff00b"}, {"id": "u014", "kind": "list-item", "locator": "body:L30-L30", "preview": "3. Reproduce the upstream baseline and changed policy over the size/type/operator matrix relevant to the application. A policy comment containing benchmark ratios is source context, not a portable speedup guarantee.", "sha256": "e1e61e646347efc9bc0b0608ba22f5dff8e61a40790c4fcb6b0f56bff39ca816"}, {"id": "u015", "kind": "list-item", "locator": "body:L31-L31", "preview": "4. Change one policy dimension at a time where practical and record time, bandwidth, occupancy, register/spill data, and correctness.", "sha256": "7566f62910d39f9e0363c194e49c8b25cc0cc4b9df73f45a5ef292116bfe7d77"}, {"id": "u016", "kind": "list-item", "locator": "body:L32-L32", "preview": "5. For selection, separately verify membership, output count, ordering, ties, NaNs, signed zero, key/value association, and repeatability. Those properties are not established by PR 6152.", "sha256": "c695167e5abc2c932b57c83095361a7e4713d338d1da7cf9e6ee588d4054dfa0"}, {"id": "u017", "kind": "prose", "locator": "body:L34-L34", "preview": "The linked evidence does not support claims about fill, histogram, reduce, block-load/store vectorization, or application-level DSA score computation. Add a directly relevant CCCL source before transferring policy conclusions to those primi", "sha256": "64c0b1fa7d7a20f4942ddeaae956cb7837d4285ade8e50e71db3e773e162e840"}], "confidence_claimed": "source-reported", "headings": ["Exact Source Scope", "What PR 3559 Actually Tunes", "Transfer Workflow"], "id": "technique-cccl-memory-primitives", "path": "wiki/techniques/cccl-memory-primitives.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/prs/cccl/PR-3559.md", "revision": "25523da2", "url": "https://github.com/NVIDIA/cccl/pull/3559"}, {"path": "sources/prs/cccl/PR-6152.md", "revision": "3fb05826", "url": "https://github.com/NVIDIA/cccl/pull/6152"}], "risk_flags": ["ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["pr-cccl-3559", "pr-cccl-6152"], "title": "CCCL CUB Memory Primitives For Selection And Scan", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "dc1f127417087638a33a432f9defd1b6e66efce189bd004f9e699f1bbbee4372", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Some linear recurrent models admit an algebraically equivalent chunkwise formulation. Work local to a chunk can then be expressed with parallel matrix operations, while the state passed across chunk boundaries preserves the recurrence's seq", "sha256": "48a92e68a2fe0a23f551664777d23c15d691c5921abf8b854b06caa7ef5106b9"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "A correct implementation separates at least these obligations:", "sha256": "8c48104a851aa54aa0a45bc389fd93b6f9409ea226bc2d7c0ed56b1f8d6b352d"}, {"id": "u003", "kind": "list-item", "locator": "body:L9-L9", "preview": "1. Compute the chunk-local quantities required by the model's exact recurrence.", "sha256": "7fd75a382a40ba603fb0f8a9810aebf341cd1a888ddc21d67b892970f1d1c1ef"}, {"id": "u004", "kind": "list-item", "locator": "body:L10-L10", "preview": "2. Resolve boundary states in sequence order, either with an associative scan supported by the formulation or with explicitly ordered stages or launches.", "sha256": "32e5983ffa33337e71cec6880f42fd8b53325b7039069f4940df823e46c9485b"}, {"id": "u005", "kind": "list-item", "locator": "body:L11-L11", "preview": "3. Combine each chunk's local result with its incoming boundary state and emit outputs in the original token order.", "sha256": "4185354ea9059f98c36f3e955471e7a5fe4d33df82d607b931c250a87e364f94"}, {"id": "u006", "kind": "list-item", "locator": "body:L12-L12", "preview": "4. Validate outputs and final states against a token-by-token reference across variable sequence lengths, chunk tails, batches, heads, dtypes, and gate extremes.", "sha256": "a3cba5f1e5eb6aa7623dc2822355cf7b802b9d57465d667703f3c10ba06f35e1"}, {"id": "u007", "kind": "prose", "locator": "body:L14-L14", "preview": "An ordinary GPU grid does not imply increasing program-ID execution order or grid-wide synchronization. Programs for every chunk therefore cannot safely read and overwrite one shared state pointer in a single unordered launch. A staged algo", "sha256": "9fc013326b6878c87eff2b13eecd2a1d2a3cf9e14d2f23ccd000b58042d8c0c4"}, {"id": "u008", "kind": "prose", "locator": "body:L18-L18", "preview": "The pinned NVlabs GatedDeltaNet repository uses chunkwise Triton kernels for training and a WY representation of the gated delta rule. That implementation is direct evidence for GatedDeltaNet chunking, but it is not equivalent to a generic ", "sha256": "e7c843e29ca3efe700861205d29f457d86bd1ba013279d32be1a0f2c46aa779b"}, {"id": "u009", "kind": "prose", "locator": "body:L20-L20", "preview": "Tiled Flash Linear Attention (TFLA) starts from the chunkwise formulation of linear RNNs and adds another level of sequence parallelization within a chunk. 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Treat a selected size as scoped to the model dimensions, dtype, GPU, backend, and wo", "sha256": "d0698561089a9d858f6770ce429c967f63c781117e5ec3e658af91b908ef14d4"}], "confidence_claimed": "verified", "headings": ["Mechanism", "Verified implementations and scope", "Choosing a chunk configuration"], "id": "technique-chunk-parallelism", "path": "wiki/techniques/chunk-parallelism.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/gated-delta-net.md", "url": "https://github.com/NVlabs/GatedDeltaNet/tree/b53d6d3a161267432a79c1c04af69fa52bddc921"}, {"path": "sources/docs/tfla.md", "url": "https://arxiv.org/abs/2503.14376v3"}, {"path": "sources/blogs/qwen3-next-architecture.md", "url": "https://developer.nvidia.com/blog/new-open-source-qwen3-next-models-preview-hybrid-moe-architecture-delivering-improved-accuracy-and-accelerated-parallel-processing-across-nvidia-platform/"}], "risk_flags": ["ordering"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-gated-delta-net", "doc-tfla", "blog-qwen3-next-architecture"], "title": "Chunkwise Parallelism for Linear Recurrences", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "4315ebf7a923e2304d59133d865cac6d17a177dde8141b6956e3fb6f93de2abc", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Double- or multi-buffering reserves disjoint storage regions and transfers ownership between producers and consumers. While a consumer reads stage `s`, a producer may fill another stage. The storage alone does not establish overlap: the pro", "sha256": "353970ee76fddcefdd8634bdce84efaf522019d1c67aadbc7734485b35739dec"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "On SM100 these ideas can be applied independently:", "sha256": "7a9f970eba37f57c06d3e4c1053f758644480ec9c1bfd6e13000b66fa7e2fd52"}, {"id": "u003", "kind": "list-item", "locator": "body:L9-L9", "preview": "- SMEM stages can hold operand tiles while TMA production overlaps MMA consumption.", "sha256": "bceca9323f3eeda738243bf77003183e73292e753517a3d9c5e0a58bf486072e"}, {"id": "u004", "kind": "list-item", "locator": "body:L10-L10", "preview": "- Separate TMEM regions can hold output accumulators while an epilogue drains a completed region and MMA writes a different region.", "sha256": "c08e7056d2703d9010ebb72f542b30e222b600fba13f3990bf373404cd5ec57f"}, {"id": "u005", "kind": "prose", "locator": "body:L12-L12", "preview": "The pinned `matmul_v6.cu` from Gau Nernst's tutorial uses both mechanisms. That is a concrete design, not a rule that every optimized Blackwell GEMM needs both.", "sha256": "7143ee6782943e2cf11478db5d26219b0b9ed56dbb20c7df822457fa19405753"}, {"id": "u006", "kind": "prose", "locator": "body:L16-L16", "preview": "The CTA-visible TMEM address structure has 128 lanes and 512 columns of 32-bit cells. Allocation is column-granular across all 128 lanes. A kernel that allocates 512 columns may choose two 256-column regions:", "sha256": "28df4d63890310783d60527b96ed4c07c057cfe045b622775dbf7d3029cffe26"}, {"id": "u007", "kind": "code", "locator": "body:L18-L21", "preview": "```text region[0] = columns [0, 256) region[1] = columns [256, 512) ```", "sha256": "ed69a2b1fa0220c87f2e0b386d916c2e13666c8f97966b1b23e1551f5656de80"}, {"id": "u008", "kind": "prose", "locator": "body:L23-L23", "preview": "This equal split is one implementation choice. The actual invariant is that every simultaneously live region is inside the allocation and does not alias another region whose MMA or epilogue access is still outstanding. Region sizes can diff", "sha256": "47dc0422eca78419d023b265f59cbad85c48bb108bf29c8b6982f069ad1e6564"}, {"id": "u009", "kind": "prose", "locator": "body:L25-L25", "preview": "For each region, prove this lifecycle:", "sha256": "77958ca2b2300609b14a11248488adc9a6078379d31d5df83720e798035ab4a9"}, {"id": "u010", "kind": "table-row", "locator": "body:L29-L29", "preview": "| Transition | Required edge | | free \u2192 MMA-owned | every prior epilogue load from the region has completed |", "sha256": "b36ebc214cce51253c6d828b95dc22426a8ab01b4128d0a6e49484d51e3735db"}, {"id": "u011", "kind": "table-row", "locator": "body:L30-L30", "preview": "| Transition | Required edge | | MMA-owned \u2192 ready | relevant tcgen05 work is committed to an mbarrier and completion is observed |", "sha256": "8af311d47b977e2484a14ff52be09086cc85443f38fed3ec42c5cc1d87cf531d"}, {"id": "u012", "kind": "table-row", "locator": "body:L31-L31", "preview": "| Transition | Required edge | | ready \u2192 epilogue-owned | readers observe the matching barrier phase before `tcgen05.ld` |", "sha256": "086da55067d42eea98da03787c03f386f30b566554fe854779777bfb6a1909b7"}, {"id": "u013", "kind": "table-row", "locator": "body:L32-L32", "preview": "| Transition | Required edge | | epilogue-owned \u2192 free | all collective loads complete with `tcgen05.wait::ld`, then every reader reports completion |", "sha256": "04c3311dcc82b7cc6680a8b4e7e23e43fc32e4f21b96dc5d35631d0e0ad3e828"}, {"id": "u014", "kind": "prose", "locator": "body:L34-L34", "preview": "TMEM must first be allocated by the required participating warp and its address safely published. Matching collective deallocation is required before every kernel exit. Reused mbarriers need the correct arrival count and phase/parity state;", "sha256": "0190655232d79908e1b5184a1aba9c8b97f9ce1895c72ef9b24d30b25b54600e"}, {"id": "u015", "kind": "prose", "locator": "body:L38-L38", "preview": "An SMEM operand stage normally has its own full/empty state:", "sha256": "70c65950ab321f20237632a725827aae81634feef5c60cb54887ca343647416d"}, {"id": "u016", "kind": "list-item", "locator": "body:L40-L40", "preview": "1. The producer waits until stage `s` is empty.", "sha256": "a79eddecdf545db8d1cf874c1f8d4281c05ee71fbe6cbec7e01fe3c0c5162046"}, {"id": "u017", "kind": "list-item", "locator": "body:L41-L41", "preview": "2. It issues the stage's TMA copies and accounts for expected transaction bytes.", "sha256": "4bff5a30df81531732eda4d3b5c80ed4c98124eb1f1f620d593322f52494ae75"}, {"id": "u018", "kind": "list-item", "locator": "body:L42-L42", "preview": "3. The consumer observes the full barrier's matching phase before using the stage.", "sha256": "e61f4af11998b70bd86556f287f45075f6b2ec06632bb6af1d0977cf7c9f3624"}, {"id": "u019", "kind": "list-item", "locator": "body:L43-L43", "preview": "4. After the final dependent read, the consumer releases the empty barrier for reuse.", "sha256": "763037b61e4bfbaae65d104e217069396c21b86838e86a0a3cf76a821234b0fa"}, {"id": "u020", "kind": "prose", "locator": "body:L45-L45", "preview": "For binary16 `A[128,64]` and `B[64,256]`, the unpadded payload arithmetic is:", "sha256": "720c85da0975a0f1d2896dc5160c1ddb319b5ab4e5f9e77a1f863b5571298ee7"}, {"id": "u021", "kind": "code", "locator": "body:L47-L51", "preview": "```text A = 128 \u00d7 64 \u00d7 2 bytes = 16 KiB B = 64 \u00d7 256 \u00d7 2 bytes = 32 KiB one stage = 48 KiB; three stages = 144 KiB ```", "sha256": "b092d8e540dcc0b91039c62edcef86c1328d4c9d837144ae54279532c788868b"}, {"id": "u022", "kind": "prose", "locator": "body:L53-L53", "preview": "That is not a complete C++ shared-storage layout. Barriers, descriptors, epilogue scratch, padding, alignment, and swizzled physical layouts also consume or constrain shared memory. Compute capability 10.0 supports up to 228 KiB of shared m", "sha256": "7571140fcd587dd0d7dbfd830e6b0aa9af7f30e57c7f6c49c46017c55c048e65"}, {"id": "u023", "kind": "prose", "locator": "body:L55-L55", "preview": "FlashInfer PR 2387 is a second pinned example. Its merged `selective_state_update.cuh` has `state[numStages][...]` plus `bar_full` and `bar_empty` arrays and uses stage-specific producer/consumer handoffs. One path selects three stages and ", "sha256": "b3e9b66c8f8cc9b7e41acfa835cc972955d57829756334c98c944cf8b6d7aa7e"}, {"id": "u024", "kind": "prose", "locator": "body:L59-L59", "preview": "For Hopper `wgmma.mma_async.m64nNk16` with FP32 D, each warpgroup thread holds `N/2` accumulator registers. At `N=256`, one D fragment is 128 registers per thread; two simultaneously live fragments are 256 registers, or 1024 bytes, per thre", "sha256": "f6e642682b459f63b368dd28720e7321715e6f3f095f5708a72b505a14d6e214"}, {"id": "u025", "kind": "prose", "locator": "body:L61-L61", "preview": "On SM100, tcgen05 keeps resident D in TMEM. This avoids a long-lived per-thread D vector, but the kernel still uses registers for addresses, descriptors, loop and barrier state, `tcgen05.ld` destinations, and epilogue temporaries. TMEM buff", "sha256": "bfb0ec4702c7e38a89db5564c2c0bc9038b25f7fb2da4fe7e93dfb6d6fc53189"}, {"id": "u026", "kind": "table-row", "locator": "body:L65-L65", "preview": "| Concern | Hopper WGMMA D | Blackwell tcgen05 D | | Resident storage | per-thread register fragment | allocated TMEM region |", "sha256": "c6d2a5bb97def6cf558e27a9beaf1ef9ddecc90fe5db35e212ebb270b9829736"}, {"id": "u027", "kind": "table-row", "locator": "body:L66-L66", "preview": "| Concern | Hopper WGMMA D | Blackwell tcgen05 D | | Two live outputs | two disjoint register fragments | two disjoint TMEM regions |", "sha256": "0713b8c5efd58eb69a0c9afbb6b8fdfabbfdad4b38831bbf0fba248d83b392c5"}, {"id": "u028", "kind": "table-row", "locator": "body:L67-L67", "preview": "| Concern | Hopper WGMMA D | Blackwell tcgen05 D | | Epilogue access | dependent use after WGMMA completion | collective `tcgen05.ld` and `tcgen05.wait::ld` after MMA completion |", "sha256": "1a1b26e2df7829f360c6b0d265010b85cdb71600218bc36dc143cbdb080c9368"}, {"id": "u029", "kind": "table-row", "locator": "body:L68-L68", "preview": "| Concern | Hopper WGMMA D | Blackwell tcgen05 D | | Main resource question | compiled registers, SMEM, block shape, and other limits | TMEM columns plus compiled registers, SMEM, block/cluster shape, and other limits |", "sha256": "45f5f676075588236b666c4a523ad20b4b6719508a6f5749f640ee3fbd88902f"}, {"id": "u030", "kind": "prose", "locator": "body:L72-L72", "preview": "Buffering is useful only when useful producer/consumer work overlaps enough to repay extra storage and coordination. For each concrete variant:", "sha256": "793da3bb85dc9c0487c967d2d3786db983a421feb6842d70691e85f9b3dd0189"}, {"id": "u031", "kind": "list-item", "locator": "body:L74-L74", "preview": "1. Keep shape, datatype, outputs, launch policy, warmup, and timing statistics identical.", "sha256": "c811a391248f2e1296904f15657e53b1e655a693b0c2f20cdf700f28553830e9"}, {"id": "u032", "kind": "list-item", "locator": "body:L75-L75", "preview": "2. Compare one versus multiple TMEM regions and the legal SMEM stage counts.", "sha256": "deb1c0cee7d6eaf7e50b64e7c05f585d2a755e855afdd7d697211d5fcfb3c6a2"}, {"id": "u033", "kind": "list-item", "locator": "body:L76-L76", "preview": "3. Record compiled registers/thread, spill traffic, static/dynamic SMEM, TMEM columns, barriers, threads/CTA, and cluster shape.", "sha256": "ae0395488ac0efa61f5fd2d5ac4a9b1daf9550fd06c04f868ae9f0183e291406"}, {"id": "u034", "kind": "list-item", "locator": "body:L77-L77", "preview": "4. Use the CUDA occupancy APIs for the actual resource record; do not infer a universal CTA/SM count from an instruction tile.", "sha256": "2a10693b0198014d1dc04730355f7a036237d5182f1bd7761e564c5141a60c79"}, {"id": "u035", "kind": "list-item", "locator": "body:L78-L78", "preview": "5. Inspect profiler pipeline and barrier stalls. PTX specifies mbarrier semantics, not a fixed \u201cfew cycles\u201d latency.", "sha256": "cf8f03e1c706642c110aae5d3923247b587728b29b7cd75a9abadb186bb84dbe"}, {"id": "u036", "kind": "list-item", "locator": "body:L79-L79", "preview": "6. Inspect generated PTX/SASS and execute correctness tests that force region wraparound and pipeline-tail paths.", "sha256": "65a8a0abcb1daa2ba41ef79bcbcc029319411ffd7cd2758984f0c96c15b9f169"}, {"id": "u037", "kind": "prose", "locator": "body:L81-L81", "preview": "Useful negative tests deliberately delay the epilogue, swap a barrier phase, omit the final drain, or reuse a region early. A correct test should detect stale/overwritten output or time out under a watchdog rather than silently accepting th", "sha256": "679336a50791d2df8ee87709263ae3c87ca8e1ff4b42560ec26d159a2e390266"}, {"id": "u038", "kind": "list-item", "locator": "body:L85-L85", "preview": "- [PTX ISA 9.0 Tensor Memory](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tensor-memory)", "sha256": "aed47f18c514497e50694f89415704f98533229e52ed733c1898d3c9bb3e2747"}, {"id": "u039", "kind": "list-item", "locator": "body:L86-L86", "preview": "- [PTX ISA 9.0 tcgen05 allocation](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit)", "sha256": "d42d0c01cb062292369af97827421a3a287ec970b4bc869b80edaefb263b177c"}, {"id": "u040", "kind": "list-item", "locator": "body:L87-L87", "preview": "- [PTX ISA 9.0 tcgen05 load and wait](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-ld)", "sha256": "f40af7d65df1e61acadc0ecdeabe2a8e73048e397d9aadccedda0847a031c532"}, {"id": "u041", "kind": "list-item", "locator": "body:L88-L88", "preview": "- [PTX ISA 9.0 mbarrier](https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier)", "sha256": "57f21ef2db856a7d997dff531533e549ea54d4a49becca4e57e4fa0f44f2cc99"}, {"id": "u042", "kind": "list-item", "locator": "body:L89-L89", "preview": "- [CUDA 13.0.2 Blackwell Tuning Guide](https://docs.nvidia.com/cuda/archive/13.0.2/blackwell-tuning-guide/index.html#occupancy)", "sha256": "8d963db7f76eb6508d3be3b8853709f57f9a8b2f98e623d121cff16c31de6585"}, {"id": "u043", "kind": "list-item", "locator": "body:L90-L90", "preview": "- [Pinned combined SMEM/TMEM example](https://github.com/gau-nernst/learn-cuda/blob/3b90ac9b3f624bdf1f6f78d02dcd533675d36573/02e_matmul_sm100/matmul_v6.cu)", "sha256": "862d7ef0e5fe7e4485454b7d0fbf52b79f47212d96d6c3d2d61e2f99a12c0966"}, {"id": "u044", "kind": "list-item", "locator": "body:L91-L91", "preview": "- [FlashInfer PR 2387 merged source](https://github.com/flashinfer-ai/flashinfer/blob/18804cd51734cccf807356d017733bc757677f15/include/flashinfer/mamba/selective_state_update.cuh)", "sha256": "21e58f5ba0dd7a07429d9e9e15e0cb6abd0137cefbff017bad4ae6654b1df059"}, {"id": "u045", "kind": "list-item", "locator": "body:L95-L95", "preview": "- [Tensor Memory](../hardware/tmem.md) \u2014 allocation, addressing, and lifetime rules", "sha256": "7afb4cc4a4c10faf8414ea0adcf8dbca658326f9d2b530cdba04f46f89c8a510"}, {"id": "u046", "kind": "list-item", "locator": "body:L96-L96", "preview": "- [pipeline stages](pipeline-stages.md) \u2014 SMEM pipeline construction and tail handling", "sha256": "a926fba806fc32d5e84f37e9775faa981aee434d3e360678aee986e6bc627802"}, {"id": "u047", "kind": "list-item", "locator": "body:L97-L97", "preview": "- [epilogue fusion](epilogue-fusion.md) \u2014 work performed while draining an output tile", "sha256": "613bbcc5ee62a62bc83b7c29a8227e6b57497c4f7f38939f1ca80134084b718c"}], "confidence_claimed": "verified", "headings": ["What the pattern guarantees", "TMEM regions", "SMEM stages", "Hopper and Blackwell storage tradeoff", "Decide with a controlled comparison", "Primary references", "Related"], "id": "technique-double-buffering", "path": "wiki/techniques/double-buffering.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}, {"path": "sources/docs/nvidia-blackwell-tuning-guide.md", "url": "https://docs.nvidia.com/cuda/blackwell-tuning-guide/"}, {"path": "sources/prs/flashinfer/PR-2387.md", "revision": "18804cd51734cccf807356d017733bc757677f15", "url": "https://github.com/flashinfer-ai/flashinfer/pull/2387"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["blog-tcgen05-tutorial", "doc-nvidia-tuning-guide", "pr-flashinfer-2387"], "title": "Double/Multi-Buffering Patterns", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "7696e2fa8a45334a92f6735216304fabf7d86fa7322b32d3d194f5d695927258", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "Epilogue fusion computes output transformations\u2014such as `alpha*acc + beta*C`, bias, activation, output conversion, or auxiliary values\u2014inside the producer kernel before final output materialization. It can remove an intermediate tensor or l", "sha256": "f9107441dd920540c0d1ac9e5090773a75dfa9fa7d1443b994ffe3d7f94d465d"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "Fusion does not by itself imply overlap with the next MMA tile. A schedule may drain one completed accumulator after the mainloop, or it may use disjoint storage and specialized roles to overlap a completed region's epilogue with independen", "sha256": "4f47d7d2b8553488318d46030c512f990423ca91ad8d800925811d2b7e8bb075"}, {"id": "u003", "kind": "prose", "locator": "body:L11-L11", "preview": "For tcgen05, D resides in TMEM. An ordinary arithmetic epilogue first uses a legal collective `tcgen05.ld` mapping, or a library wrapper around it, to transfer a partition into per-thread registers. The load is asynchronous with respect to ", "sha256": "5877a199df06e039e1d768c0f9a71bba45e88384bc7e3ff057d758f72ec8ce82"}, {"id": "u004", "kind": "prose", "locator": "body:L13-L13", "preview": "CUTLASS 4.5.0's `fp16_gemm_2.py` demonstrates the typed route:", "sha256": "adc38d40084211a2785289cdae32b37c45f48b6c540acd24ab586a3a8994814b"}, {"id": "u005", "kind": "code", "locator": "body:L15-L24", "preview": "```python copy_atom_t2r = cute.make_copy_atom( tcgen05.Ld32x32bOp(tcgen05.Repetition.x32), cutlass.Float32 ) tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tCtAcc_epi) thr_copy_t2r = tiled_copy_t2r.get_slice(tidx) tTR_tAcc = thr_cop", "sha256": "98fb794337ea2463c1d0e401026810e136bcde4790746a21365872ce92d466a6"}, {"id": "u006", "kind": "prose", "locator": "body:L26-L26", "preview": "This is an API-routing fragment, not standalone code: the official file supplies the exact tensor layouts, selected load shape, participant group, edge predicates, accumulator-completion handoff, register-to-SMEM conversion, TMA-store pipel", "sha256": "a8dc66e0523115acbd50a98fb09e529ba902911c6c8ccd4b24c2afc24fec85eb"}, {"id": "u007", "kind": "table-row", "locator": "body:L32-L32", "preview": "| Boundary | Proof required before crossing it | | tcgen05 MMA \u2192 TMEM reader | the relevant asynchronous MMA is committed and its completion observed |", "sha256": "9985d4cd976b715fdc76865925a3aa8489cadc7a359e285805c6174ead01f6a4"}, {"id": "u008", "kind": "table-row", "locator": "body:L33-L33", "preview": "| Boundary | Proof required before crossing it | | TMEM \u2192 result registers | the legal collective load completes before dependent arithmetic |", "sha256": "6b6d528df317b00dd9c026068a171d0397fece81c64efdee7e8451c739811c78"}, {"id": "u009", "kind": "table-row", "locator": "body:L34-L34", "preview": "| Boundary | Proof required before crossing it | | registers \u2192 output | element/layout mapping and output-edge predicates cover exactly the valid coordinates |", "sha256": "efc6c04d14475fe8461a37c816dadacb9dfe78df871eba2e26350ad5e59bbc3e"}, {"id": "u010", "kind": "table-row", "locator": "body:L35-L35", "preview": "| Boundary | Proof required before crossing it | | TMEM reader \u2192 region reuse | every reader's load has completed and the matching reusable barrier phase is released |", "sha256": "624abc6a869187539c7ac548bb053a85c391b041419a4f52f82cd2390fe000da"}, {"id": "u011", "kind": "table-row", "locator": "body:L36-L36", "preview": "| Boundary | Proof required before crossing it | | kernel tail | all output stores complete as required and every TMEM allocation is collectively freed |", "sha256": "394bf4e44474bc37252b13e6680b64dce13cdd39a349c33da579f6af120afb85"}, {"id": "u012", "kind": "prose", "locator": "body:L38-L38", "preview": "For a multi-region overlap schedule, simultaneously live TMEM regions must also be disjoint. Equal 256-column halves are one possible policy for a 512-column allocation, not an epilogue-fusion requirement. Reusable mbarriers need correct ex", "sha256": "632d24557c88b222486de12166a2781d2e53a39ed69410cfa66d6ec170d85f1a"}, {"id": "u013", "kind": "prose", "locator": "body:L42-L42", "preview": "`cutlass::epilogue::fusion::LinCombEltAct` has this parameter order:", "sha256": "91ce48572731a856757d222bfb3aa65e8350a69cd68d1b04eff3e953be42239a"}, {"id": "u014", "kind": "code", "locator": "body:L44-L53", "preview": "```cpp template < template class ActivationFn, class ElementOutput, class ElementCompute, class ElementSource = ElementOutput, class ElementScalar = ElementCompute, cutlass::FloatRoundStyle Round = cutlass::FloatRoundStyle::round_to", "sha256": "2c17e7f24711c91e72d68d975cae0b68a3c2482f8b386e3a64ab96d14482efa0"}, {"id": "u015", "kind": "prose", "locator": "body:L55-L55", "preview": "For SM100 construction, `cutlass::epilogue::collective::CollectiveBuilder` receives architecture, operator class, tile/cluster shapes, `EpilogueTileAuto` or an explicit epilogue tile, accumulator/compute/C/D types and layouts, alignment, `E", "sha256": "5ba02c063f7bbb12184dbe6ba70d2875fca82c9b9bb28392add306148e470825"}, {"id": "u016", "kind": "prose", "locator": "body:L57-L57", "preview": "There is no CUTLASS 4.5.0 type named `Sm100EpilogueTmaWarpSpecialized`. Support is constrained by the exact architecture, operator class, schedule, tile, layout, alignment, datatype, and fusion callback combination. Use `Gemm::can_implement", "sha256": "d111f3431cc1550474efe0835affdc6255eb3133f4ab79c1adeab8d7bb1385ce"}, {"id": "u017", "kind": "prose", "locator": "body:L59-L59", "preview": "The vLLM PR 16032 NVFP4 wrapper is one pinned C++ construction example: it uses `CollectiveBuilder<... EpilogueTileAuto, ... EpilogueScheduleAuto>` and derives mainloop shared-memory stages with `StageCountAutoCarveout`](https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/include/cute/swizzle.hpp):", "sha256": "e2de909b5c3702e90f3adc61d96f2aa80f06ace5b81ecfbbc16554b50cd26daa"}, {"id": "u017", "kind": "list-item", "locator": "body:L36-L36", "preview": "- `BBits` is the number of mask bits;", "sha256": "5af4a067d6c7da7415684db6889c71471be01324eefd2b56cba5ab0605b9048b"}, {"id": "u018", "kind": "list-item", "locator": "body:L37-L37", "preview": "- `MBase` is the number of least-significant address bits kept invariant; and", "sha256": "4baa3200cd5285f7c28a299e5577b8cdb19ad27e8d093c6208a6d0b33aad32b5"}, {"id": "u019", "kind": "list-item", "locator": "body:L38-L38", "preview": "- `SShift` is the distance between the two bit fields.", "sha256": "f28019ed4ea31c3b1d699597255eec3b2cb5bca744ea8d505802e5142e328689"}, {"id": "u020", "kind": "prose", "locator": "body:L40-L40", "preview": "For `Swizzle<3,4,3>`, three address bits beginning above the four invariant low bits are XORed with the three-bit field shifted by three positions. Equivalently, address bits 7:9 affect bits 4:6. This is an address transformation, not a gen", "sha256": "ffaae440bfd21e9f23db7977e6f25a0843206a5ebcccceb60b0f43b287fb38b6"}, {"id": "u021", "kind": "prose", "locator": "body:L42-L42", "preview": "CUTLASS also distinguishes a position-independent composed swizzle layout from a position-dependent swizzle pointer, because hardware swizzling depends on the shared-memory pointer address. Reuse a pinned complete layout/descriptor construc", "sha256": "7b7c33d7d8af0396265809e977fa799bb5bc22896a34d87bb0341b7036cd6fdf"}, {"id": "u022", "kind": "prose", "locator": "body:L46-L46", "preview": "For `cuTensorMapEncodeTiled`, record and validate all inputs rather than copying only the swizzle enumerator:", "sha256": "52e9d72146342e12fd2b1490c3761b731df5f3257a9203f475f988e31c7143c9"}, {"id": "u023", "kind": "list-item", "locator": "body:L48-L48", "preview": "1. Use a correctly aligned `CUtensorMap` object and global base pointer.", "sha256": "80e4aa5c2d38c0d179760ddbd62c54902ad761ce25c126a2a276d27c250232a0"}, {"id": "u024", "kind": "list-item", "locator": "body:L49-L49", "preview": "2. Supply rank-sized global dimensions, rank-minus-one byte strides (the fastest dimension is implicit), rank-sized box dimensions, and rank-sized element strides.", "sha256": "7a0cabb5ab90c8ad9fcb90c4a3b1abec710ea10e42d49e4b1ae7f089df312640"}, {"id": "u025", "kind": "list-item", "locator": "body:L50-L50", "preview": "3. Satisfy the global alignment, stride, box, interleave, datatype, and selected-swizzle constraints.", "sha256": "44c861550453d7469cfe6ab5f3f95ff727c04f68a1728ad416f78b1f7d2b1b7c"}, {"id": "u026", "kind": "list-item", "locator": "body:L51-L51", "preview": "4. Check the returned `CUresult`; do not launch with an output descriptor after encoding failed.", "sha256": "e35e8c5abe5a043f7a59a02a53ec58fbe4d9c5630736504600a4fdf081ea801d"}, {"id": "u027", "kind": "list-item", "locator": "body:L52-L52", "preview": "5. Use a shared-memory base and tcgen05 descriptor that represent the same mapping as the tensor map.", "sha256": "bcf3491b71148b2582b92aa3a39be1f27b68b24860545007d7c3fceec0df92d3"}, {"id": "u028", "kind": "prose", "locator": "body:L54-L54", "preview": "An invalid encoder combination can fail explicitly. A successfully encoded tensor map paired with the wrong consumer layout may instead read the wrong logical elements, so a successful API return is not a correctness oracle.", "sha256": "5bb6b35556ce52d1c4949afd7353eea6ed6e47d18072506fc1477c4c5e422a86"}, {"id": "u029", "kind": "prose", "locator": "body:L58-L58", "preview": "Gau Nernst's pinned B200 tutorial compares M=N=K=4096 kernels with PyTorch 2.9.1 and CUDA 13. Its 3D TMA version changes from a 16-byte inner tile with no swizzle to a 128-byte inner tile with 128B swizzling and matching tcgen05 descriptors", "sha256": "1442557fe3203a558928700307223fea48556a1423bb751823fe7a3ded0daec6"}, {"id": "u030", "kind": "table-row", "locator": "body:L62-L62", "preview": "| Tutorial version | Author-reported TFLOP/s | | v1b: 3D 16B TMA | 252.81 |", "sha256": "5ec52bb84daca8d9c4f9c330d7e0f75780b21a3674ec4e8c94329488f3030c29"}, {"id": "u031", "kind": "table-row", "locator": "body:L63-L63", "preview": "| Tutorial version | Author-reported TFLOP/s | | v2b: 3D 128B TMA plus 128B swizzle | 695.43 |", "sha256": "98a08ba0c20d778d67556cee3756e894c83682172bf48209e67517fa770e44e4"}, {"id": "u032", "kind": "prose", "locator": "body:L65-L65", "preview": "The combined change is approximately 2.75\u00d7 and the v2b endpoint is about 46% of the tutorial's 1506.74 TFLOP/s cuBLAS result. It is not a bank-conflict or swizzle-only ablation. The author notes that the earlier contiguous `8\u00d716B` tile migh", "sha256": "5c904bdadd0bdbec537b8da0a58b9e0eae1846a8130911c2933fdae421f9771c"}, {"id": "u033", "kind": "prose", "locator": "body:L69-L69", "preview": "For each candidate mapping:", "sha256": "7efda7c57692314fbd1a9fcdd587176241012dc24de5eecd9b854d1b2545ead1"}, {"id": "u034", "kind": "list-item", "locator": "body:L71-L71", "preview": "1. Keep global tensor, box, consumer instruction, tile shape, synchronization, and output oracle fixed. Change only the producer/consumer layout pair when an isolated comparison is possible.", "sha256": "85fa3e9198db89eed9cb12480937658783d70f38dd929725f0b8cf71e59328c7"}, {"id": "u035", "kind": "list-item", "locator": "body:L72-L72", "preview": "2. Check every tensor-map encoder result and run correctness tests that distinguish rows, columns, tiles, boundaries, and out-of-bounds fill. Do not rely on random uniform values that can hide permutations.", "sha256": "7c059219f0a0bef45641d0ee887c2f16f188c681fa01a4258e0aac06772ee9ef"}, {"id": "u036", "kind": "list-item", "locator": "body:L73-L73", "preview": "3. Use the installed Nsight Compute's `--query-metrics` or Memory Workload Analysis rather than assuming one metric name exists on every chip/tool version. Current documentation includes `l1tex__data_bank_conflicts_pipe_lsu.sum` and request", "sha256": "7081d7ec194ad85836cd0a830d113b7edfbf9547a09a3d54ef52e60a1a4dbf2e"}, {"id": "u037", "kind": "list-item", "locator": "body:L74-L74", "preview": "4. Compare executed shared-memory requests, ideal versus excessive wavefronts, bank conflicts, TMA behavior, total time, and occupancy. Zero observed CUDA-core bank conflicts neither proves the MMA descriptor matches nor explains a performa", "sha256": "16afbfd8bff05f99eb2faf2c5860e7a0786f1e850a6c43efa566f887bdcc24dd"}, {"id": "u038", "kind": "list-item", "locator": "body:L75-L75", "preview": "5. Record GPU, clocks, toolkit, profiler, compiler, exact addresses/alignment, layout types, descriptor fields, warmup, repetitions, and trial statistic.", "sha256": "09ceac52c96b6ed2ee30601a3682d58e7e976256b12796df1a192f98531b105e"}, {"id": "u039", "kind": "prose", "locator": "body:L77-L77", "preview": "Select the mapping that is legal and correct for both producer and every consumer, then retain it only where the controlled target workload improves. Do not infer the choice from architecture name, element width, or \u201cMMA versus non-MMA\u201d alo", "sha256": "d9fe95880e83d8c77d23da16c2196e5649905b51170a21816dd3bca04ba4e1a5"}], "confidence_claimed": "verified", "headings": ["Bank-conflict model", "Three mappings must agree", "CuTe address-bit form", "Tensor-map construction checklist", "Source-reported tutorial result", "Verification procedure"], "id": "technique-swizzling", "path": "wiki/techniques/swizzling.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-cuda-13-0-2-tma.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/cuda-c-programming-guide/index.html#asynchronous-data-copies-using-the-tensor-memory-accelerator-tma"}, {"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}, {"path": "sources/blogs/tcgen05-tutorial.md", "url": "https://gau-nernst.github.io/tcgen05/"}], "risk_flags": ["ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-cuda-13-0-2-tma", "doc-ptx-isa-sm100", "blog-tcgen05-tutorial"], "title": "Shared Memory Swizzling", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "ddee79f7472a6c3a775767f5f72596fd42a2d47df2856c53f96609d5e55ce71c", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "\u201cTile scheduling\u201d can refer to four different choices:", "sha256": "7b32fb0a937d7562fe4d500af4d3ac5ec152f9dc500779bc152c44b07f745659"}, {"id": "u002", "kind": "list-item", "locator": "body:L5-L5", "preview": "1. **Coordinate order:** a software mapping from a logical work index to `(tile_m, tile_n, ...)`, such as row-major, column-major, or a blocked/swizzled raster.", "sha256": "01bc0ff0de2d8faaa3f3ecc471ffde0939b45942f3e3b0e91c98312a9e644340"}, {"id": "u003", "kind": "list-item", "locator": "body:L6-L6", "preview": "2. **Resident-worker iteration:** whether a CTA handles one logical tile or repeatedly advances through work, for example by a static grid stride.", "sha256": "dfce2ca5b0bf2328975bc0b6e37cb7aa76a25fe5d9e46ec5b83b958e1df2ca8e"}, {"id": "u004", "kind": "list-item", "locator": "body:L7-L7", "preview": "3. **Work reassignment:** on SM100, Cluster Launch Control (CLC) lets a running worker cancel another grid entity that has not started and process the returned ClcID.", "sha256": "ad294691c329b879334b36f7addb42f5a735d07f182fa05a1568622e393ddf42"}, {"id": "u005", "kind": "list-item", "locator": "body:L8-L8", "preview": "4. **Problem decomposition:** Stream-K or Split-K can partition a tile's K work and then reduce partial results.", "sha256": "d68060e493898620463da03ac5643b456b664ef8a1a347e6ab695b45be712287"}, {"id": "u006", "kind": "prose", "locator": "body:L10-L10", "preview": "CLC does not accept a raster-order or swizzle-policy operand. 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It does not by itself prove a hit rate or speedup. A valid transform must first be shown to be in-bounds and bijective for edge groups; then its locali", "sha256": "6f6772443125529b78281c3269007c9d850c5072b7942599dbb6f86413914f7e"}, {"id": "u012", "kind": "prose", "locator": "body:L40-L40", "preview": "CUTLASS 4.5.0 documents this lifecycle for a CLC-backed persistent scheduler:", "sha256": "b9c7e8b605d64aac51b86256ed00d2cacf354e8b60280f9b4a025abfb2d71e25"}, {"id": "u013", "kind": "list-item", "locator": "body:L42-L42", "preview": "1. Launch the full problem grid and process the worker's initial `blockIdx` coordinate.", "sha256": "20d20b6a4cf0cb97dd6ffbb93b309b13a3241d6fcdaade9558afc3a1d4ac05c2"}, {"id": "u014", "kind": "list-item", "locator": "body:L43-L43", "preview": "2. Submit `clusterlaunchcontrol.try_cancel` against another not-yet-started grid entity. The asynchronous 16-byte response completes a transaction on an mbarrier.", "sha256": "a06961216d88c13174e5484e203558f45cf98ac572f6a213677701fbf730bf7d"}, {"id": "u015", "kind": "list-item", "locator": "body:L44-L44", "preview": "3. After the transaction completes, query whether cancellation succeeded. On success, decode and process the returned ClcID; for clusters, combine the returned first coordinate with the local cluster rank.", "sha256": "c7ab67729620e19fb98c56bbd8970ce7a7b024dd1e993362701587079589ba6d"}, {"id": "u016", "kind": "list-item", "locator": "body:L45-L45", "preview": "4. Treat an observed failed request as terminal for requests by that thread. Retrying from the same thread after failure is undefined.", "sha256": "c881c94cd5d38a82f418a9dd3cb9fd072897c3e38cf5208b7f2616ef9db28130"}, {"id": "u017", "kind": "prose", "locator": "body:L47-L47", "preview": "This can redistribute existing work when SM availability is uneven. It changes which resident worker handles an unlaunched ID, not the number of independent IDs in the grid. Software raster/swizzle may be applied consistently to both initia", "sha256": "1438dba392c4a82e98af96e55adc1a396e15067319beaa2511761701eca3fe2c"}, {"id": "u018", "kind": "prose", "locator": "body:L51-L51", "preview": "The public scheduler tags select implementation classes; users should prefer those tags over spelling detail types directly.", "sha256": "c9194ef2ae3478c668ebd794c2ebda157dd3b3fd60d8dff4d17922264e0e1c40"}, {"id": "u019", "kind": "table-row", "locator": "body:L55-L55", "preview": "| Public tag for `arch::Sm100` | Selected implementation | Scope | | `PersistentScheduler` (also the default `void` tag) | `PersistentTileSchedulerSm100` | CLC-backed persistent data-parallel scheduling |", "sha256": "436f3f1bdc780f0bcbba5b14d827591dbd44f9d903da5772fa655b3ac7a478c6"}, {"id": "u020", "kind": "table-row", "locator": "body:L56-L56", "preview": "| Public tag for `arch::Sm100` | Selected implementation | Scope | | `DynamicPersistentScheduler` | `PersistentTileSchedulerSm100` | Explicit dynamic route to the same SM100 implementation |", "sha256": "ce0c2c6ed629edf9fded3c6cfe63c01b6790dc62bc3d52c0b6858ae77a6c97b0"}, {"id": "u021", "kind": "table-row", "locator": "body:L57-L57", "preview": "| Public tag for `arch::Sm100` | Selected implementation | Scope | | `StaticPersistentScheduler` | `StaticPersistentTileScheduler100` | Static persistent scheduling |", "sha256": "59209b09fb5932bb87b80c3e1579fb729d01134b2ad07175e6e3765b61a7531a"}, {"id": "u022", "kind": "table-row", "locator": "body:L58-L58", "preview": "| Public tag for `arch::Sm100` | Selected implementation | Scope | | `StreamKScheduler` | `PersistentTileSchedulerSm100StreamK` | Parameterized data-parallel, Stream-K, or Split-K decomposition |", "sha256": "9dbd3bb085575ad9584218613f353eac0dcb7893ce1c68d03863b8011786992e"}, {"id": "u023", "kind": "table-row", "locator": "body:L59-L59", "preview": "| Public tag for `arch::Sm100` | Selected implementation | Scope | | `GroupScheduler` | `PersistentTileSchedulerSm100Group` | Grouped-problem route; in this tag it wraps the SM90-style static group scheduler |", "sha256": "0ecf5b3ad36b38af94e66745a93247520268644a8550382e195bb62071a6bf95"}, {"id": "u024", "kind": "prose", "locator": "body:L61-L61", "preview": "The SM100 Stream-K route accepts decomposition, split, raster, swizzle, and reduction settings. CUTLASS 4.5.0 has a deterministic lock/turnstile reduction and a nondeterministic atomic-workspace reduction; atomic accumulation is therefore n", "sha256": "1ff1f5194c712ba9bb2dae5da5ffaa2ba7c9fc8351523869f82bed91b7567175"}, {"id": "u025", "kind": "prose", "locator": "body:L65-L65", "preview": "For a deliberately simplified model with `T` equal-duration independent tiles, `W` available one-tile workers, and no K decomposition, write:", "sha256": "3184df242365781fc5c684291037f9127188eed995576762d2924ebb7cebccab"}, {"id": "u026", "kind": "code", "locator": "body:L67-L69", "preview": "```text T = qW + r, 0 <= r < W ```", "sha256": "9055386055d6219a3731bea281e8962958fea9a3ccddd596354c89e898f6cd16"}, {"id": "u027", "kind": "prose", "locator": "body:L71-L71", "preview": "If `r > 0`, the final partial wave has `r` active workers and occupancy `r / W`. If `r == 0` and `T > 0`, the final wave is full; reporting zero occupancy from the remainder alone is an error.", "sha256": "26ad025dfeb8dbf255a8583d4cc6332064e9c8889825eea498c1e7f0b3f5e5db"}, {"id": "u028", "kind": "prose", "locator": "body:L73-L73", "preview": "For `T = 150` and `W = 142`, the second wave contains 8 tiles, so 8 workers are active, 134 are idle, and wave occupancy is `8 / 142 = 5.63%` under those assumptions. CLC may change which workers receive those eight IDs and reduce delays ca", "sha256": "ea61406965d276427719ff49baf8c6394acc0d66f5e297ec2fe702333b6d0412"}, {"id": "u029", "kind": "list-item", "locator": "body:L77-L77", "preview": "1. Establish a correct unswizzled data-parallel mapping and verify exact tile coverage, including nondivisible edge groups.", "sha256": "e0aab377952cc5e5d1d899541ec67d739c272ed4e36f6ec16e835f1ce75277f5"}, {"id": "u030", "kind": "list-item", "locator": "body:L78-L78", "preview": "2. Sweep legal raster orders and swizzle sizes. Record kernel time plus L2 hit/sector traffic; do not infer eviction from coordinate order alone.", "sha256": "c06c06c02554411d3f9b47429f84f9a8e5441e79fc4dbdb332d4e538106ece78"}, {"id": "u031", "kind": "list-item", "locator": "body:L79-L79", "preview": "3. Compare static and CLC-backed persistence at identical tile, cluster, grid, and occupancy settings. Record successful/failed CLC requests and per-worker tile counts where instrumentation permits.", "sha256": "9b223b0ad22011e157f170461269e99ab6faeb845709c550a38ce039b5bb616d"}, {"id": "u032", "kind": "list-item", "locator": "body:L80-L80", "preview": "4. Test Stream-K separately with explicit decomposition, split, and reduction modes. Include workspace traffic, synchronization, determinism, and numerical tolerance.", "sha256": "636232c0d996791186f2d18f4d6911d3189712cd4ca86a0da1cd78474119981a"}, {"id": "u033", "kind": "list-item", "locator": "body:L81-L81", "preview": "5. Repeat across representative shapes and grouped-size distributions. Report regressions as well as wins; there is no universal best scheduler for all GEMMs, attention kernels, or MoE workloads.", "sha256": "ffb9c866fb101d1393c4c852ec2fb45c0f61356743566ff7791cda405e4c31ce"}, {"id": "u034", "kind": "prose", "locator": "body:L83-L83", "preview": "Without target-GPU measurements, this page makes no fixed claim for CLC acquisition latency, L2-miss reduction, or scheduler speedup.", "sha256": "2925a13ea32074b79278f44f396331abbada0e420d39689800102052fdcf8625"}], "confidence_claimed": "source-reported", "headings": ["Keep the Scheduling Layers Separate", "Exact Static Mappings", "SM100 CLC Work Acquisition", "CUTLASS 4.5.0 Scheduler Routes", "Tail Arithmetic", "Selection and Verification Workflow"], "id": "technique-tile-scheduling", "path": "wiki/techniques/tile-scheduling.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/cutlass-clc-documentation.md", "url": "https://github.com/NVIDIA/cutlass/blob/e406c186f510a15091cce01f782020ceb7ba8eb5/media/docs/cpp/blackwell_cluster_launch_control.md"}, {"path": "sources/docs/nvidia-cutlass-blackwell.md", "url": "https://github.com/NVIDIA/cutlass/tree/v4.5.0"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-cutlass-clc", "doc-cutlass-blackwell"], "title": "Tile Scheduling Strategies", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "06ac3ebdfd34c7e7e4d4572a79c562a6b8733c0609fbdfe47db0573ad33e2290", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L5-L5", "preview": "A PTX vector load moves several typed elements into several registers with one instruction. This can reduce the number of load instructions issued by a thread, but PTX only says that vector loads *may* improve memory performance. Source-lev", "sha256": "3d99821d64a7e0fcf66a49561f2925641a983fbfdf7a6bdc83d77beacdcaa737"}, {"id": "u002", "kind": "prose", "locator": "body:L7-L7", "preview": "PTX ISA 9.0 permits the following global-memory forms on `sm_100`. The first accesses 16 bytes and the second accesses 32 bytes:", "sha256": "9f567d25863717dbe10d6a0c35951f195f02e73b69f3216826746dd1b16b7492"}, {"id": "u003", "kind": "code", "locator": "body:L9-L16", "preview": "```ptx .reg .b64 addr; .reg .u32 x<4>; .reg .u64 y<4>; ld.global.v4.u32 {x0, x1, x2, x3}, [addr]; ld.global.v4.u64 {y0, y1, y2, y3}, [addr]; ```", "sha256": "761519ce1a2f10c73aea258740cca70aac5fdf07bf0ff7a8a9d5b4984de5eace"}, {"id": "u004", "kind": "prose", "locator": "body:L18-L18", "preview": "The address must be naturally aligned to the total access size: 16 bytes for `v4.u32` and 32 bytes for `v4.u64`. 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Representative legal forms are:", "sha256": "0b9faa0d058fdadf045f326ea5dfcbab2f53d282615162309f99230b62e0cd20"}, {"id": "u007", "kind": "code", "locator": "body:L26-L31", "preview": "```ptx ld.global.L1::no_allocate.v4.u32 {x0, x1, x2, x3}, [addr]; ld.global.L1::evict_last.v4.u32 {x0, x1, x2, x3}, [addr]; ld.global.L2::256B.b32 x0, [addr]; ld.global.nc.b32 x0, [addr]; ```", "sha256": "ec4167ea0ba7152cb2179a67671479d0a2f4f407a28687bf87af2d87540b6f29"}, {"id": "u008", "kind": "table-row", "locator": "body:L35-L35", "preview": "| Form | Documented meaning | Limit on inference | | `L1::no_allocate` | L1 eviction-priority selection that may be applied | Does not guarantee an L1 bypass or a speedup for a streaming operand |", "sha256": "2780be407bbe96d5b106e3a0f5a703536fbb5465cf3d0d723517517d9918dcea"}, {"id": "u009", "kind": "table-row", "locator": "body:L36-L36", "preview": "| Form | Documented meaning | Limit on inference | | `L1::evict_last` | Requests the corresponding L1 eviction priority | Does not guarantee that a line remains resident |", "sha256": "1840c23696a0f16e1089d8d0649d755433db335252c3256c41f938763dc645d2"}, {"id": "u010", "kind": "table-row", "locator": "body:L37-L37", "preview": "| Form | Documented meaning | Limit on inference | | `L2::256B` | Hints that additional data of the stated size be prefetched into L2 | Is not a 256-byte load or a promotion guarantee |", "sha256": "06b2d39edee55c63dc2701519fcfeb993a3d00a45c4922a7b7b2e8dc80220e9b"}, {"id": "u011", "kind": "table-row", "locator": "body:L38-L38", "preview": "| Form | Documented meaning | Limit on inference | | `ld.global.nc` | Loads through a non-coherent read-only cache | Has architecture- and parallelism-dependent latency/throughput; it is not a general coherence optimization |", "sha256": "494ed829c67676d6c3b42e0d71f7c5924d0ae9f55c3a3caaf41be0d2bc6e093e"}, {"id": "u012", "kind": "prose", "locator": "body:L40-L40", "preview": "Cache-policy operands and prefetch-size qualifiers are performance hints and do not change the program's memory-consistency behavior. A reuse argument can motivate `evict_last`, and a one-pass stream can motivate `no_allocate`, but only a m", "sha256": "ad91b927be30bcfcfa70030224edc683a2b9de8c4f6af8a4d75c1c7d147b9724"}, {"id": "u013", "kind": "prose", "locator": "body:L44-L44", "preview": "For each candidate width and cache policy:", "sha256": "5e99de4759e9a94d2fa025e1ecf3ba20b1ee617b70fb262ad9d3cfde7d0408f5"}, {"id": "u014", "kind": "list-item", "locator": "body:L46-L46", "preview": "1. Prove base and per-thread address alignment for every executed access. Use a separate scalar or narrower-vector path for tails; validate minimum, maximum, and awkward sizes.", "sha256": "e6034cb185b56b2aa0b6088595b59f10d947cedfc609d0a6b028860c3041cbbf"}, {"id": "u015", "kind": "list-item", "locator": "body:L47-L47", "preview": "2. Hold the algorithm, mapping, decode, unrolling, launch shape, compiler, and inputs fixed while changing one load or cache choice. Compare identical correctness oracles before timing.", "sha256": "280cf574c975c962cfa7fb90943e03e73b2c5c96a11093dcab42ecce65d1bbb6"}, {"id": "u016", "kind": "list-item", "locator": "body:L48-L48", "preview": "3. Inspect generated PTX and SASS. Record actual load instructions, registers per thread, spill loads/stores, stack bytes, shared memory, and launch parameters. A source cast or inline-PTX block does not bypass compiler register allocation.", "sha256": "2fd170479b42be4da847ddabe8e7582f942debfed14c3050e1b31f7ad4941bdc"}, {"id": "u017", "kind": "list-item", "locator": "body:L49-L49", "preview": "4. Profile the matched variants. Check achieved bandwidth, requested versus transferred bytes, cache hit behavior, instruction issue/stalls, and active warps with metrics available on the installed Nsight Compute and GPU versions.", "sha256": "b7cee53be2ebd70f15f015073066cec635dbf6649f523057f03d1f5ac2e26ea9"}, {"id": "u018", "kind": "list-item", "locator": "body:L50-L50", "preview": "5. Use warmups, synchronization, repeated trials, and the same statistic for every production shape. Keep the change only where the declared metric improves without a correctness or resource regression.", "sha256": "36924cb17b1ccb46e32d0ddea78c1db22526b9871e47971d6fb917b03381c23f"}, {"id": "u019", "kind": "prose", "locator": "body:L52-L52", "preview": "Register caps and launch bounds are a separate variable. A nominal cap may be inert when natural allocation is lower, or it may trade registers for spills and extra instructions. Follow the resource and occupancy workflow in [Register Budge", "sha256": "cb3704e62d7d4725397d5fe9b2a2bcecbb903980445d842b50eb237c778bd327"}, {"id": "u020", "kind": "prose", "locator": "body:L56-L56", "preview": "Yue Zhang reports the following CUDA progression for GPU Mode Problem 1. These are author-reported endpoints without raw repeated-trial data or released complete submission code:", "sha256": "7b332e96d30f401078015efa8d7c6b2790a822f625eebb2f9b0a386d4e64a262"}, {"id": "u021", "kind": "table-row", "locator": "body:L60-L60", "preview": "| Stage | Combined change | Reported latency | | Initial CUDA | Naive hand-written path | about 2000 \u00b5s |", "sha256": "7c11921183bdbcbdb88258eff9a6b1d38d68d52b03ad0de2a6ddd30a6c5dbae1"}, {"id": "u022", "kind": "table-row", "locator": "body:L61-L61", "preview": "| Stage | Combined change | Reported latency | | CUDA optimization 1 | Coalescing, shared B, thread collaboration, warp reduction | about 443 \u00b5s |", "sha256": "98bdc14cff910536e6b2902f8e77cea8a8cf5401513c2fb653c934478cfaaf4b"}, {"id": "u023", "kind": "table-row", "locator": "body:L62-L62", "preview": "| Stage | Combined change | Reported latency | | CUDA optimization 2 | Remove shared B, per-thread tiles, `float4` loads, hardware intrinsics | about 39 \u00b5s |", "sha256": "3ccddb9db69afdec4a4b5e80e9279ce9e056ea7e8650ec0fc13b76260a91c8a3"}, {"id": "u024", "kind": "table-row", "locator": "body:L63-L63", "preview": "| Stage | Combined change | Reported latency | | CUDA optimization 3 | Vectorized PTX FP4 and scale decode | about 27 \u00b5s |", "sha256": "56cbb91dc0717675c0b075e8dc705e187892f107bb0bdbd355c5f7523fa1fb50"}, {"id": "u025", "kind": "table-row", "locator": "body:L64-L64", "preview": "| Stage | Combined change | Reported latency | | Parameter tuning | Threads per row and rows per block | about 26 \u00b5s |", "sha256": "20ec181854506636133e200346d437e30e574a0b0c4cf11fe5b13a2b148e2dde"}, {"id": "u026", "kind": "table-row", "locator": "body:L65-L65", "preview": "| Stage | Combined change | Reported latency | | ILP | Two tiles per loop iteration | about 22.9 \u00b5s |", "sha256": "65bd979b07f3eb7e869fa06be77e1a2ca90c448ece9242fb34e69473313aa428"}, {"id": "u027", "kind": "table-row", "locator": "body:L66-L66", "preview": "| Stage | Combined change | Reported latency | | Aggressive PTX fusion | Decode, scales, multiply, and accumulation in a larger PTX block | about 22.3 \u00b5s |", "sha256": "b88905c939fdf1e9c68c504abe3f1270ee932c5ff8c8adc0a20f9b4be6559dec"}, {"id": "u028", "kind": "prose", "locator": "body:L68-L68", "preview": "The submitted public-leaderboard score was 22.392 microseconds, the geometric mean over three benchmark shapes. The pinned task's theoretical model gives 8.622, 17.275, and 4.317 microseconds for those separate shapes; 8.622 microseconds is", "sha256": "59f3301f0b00e666daa6bccf8f7b771f1e6c77e3c16f6af8d5c0fb429fecef87"}, {"id": "u029", "kind": "prose", "locator": "body:L70-L70", "preview": "Amandeep Singh's attempts supply useful negative controls for the same task. Replacing two `uchar4` loads with one `uint2` load was reported 16\u201325% slower because extraction added instructions. Lowering `-maxrregcount` from 80 to 64 had no ", "sha256": "4f5cf4a108e0b33babb146932c0781c5c7e48b7b71672d1aee225a6f5226c9c6"}, {"id": "u030", "kind": "prose", "locator": "body:L72-L72", "preview": "Together, the reports justify testing vector width, decode organization, cache hints, and register limits. They do not establish that the widest load, a particular cache hint, or the lowest register cap is essential for GEMV, sub-byte arith", "sha256": "ef8f3594f82b50827d6fbc4ad359d74a683c0fee16b9c701e09124fd010fb6a4"}], "confidence_claimed": "verified", "headings": ["What a wider load establishes", "Cache controls are hints", "Reproducible selection procedure", "NVFP4 GEMV case study"], "id": "technique-vectorized-loads", "path": "wiki/techniques/vectorized-loads.md", "performance_claim_count": 0, "resolved_sources": [{"path": "sources/docs/nvidia-ptx-isa-sm100.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.2/parallel-thread-execution/index.html"}, {"path": "sources/docs/nvidia-cuda-register-controls.md", "url": "https://docs.nvidia.com/cuda/archive/13.0.0/cuda-c-programming-guide/index.html"}, {"path": "sources/blogs/yue-nvfp4-hackathon.md", "url": "https://yue-zhang-2025.github.io/2025/12/02/blackwell-nvfp4-kernel-hackathon-journey.html"}, {"path": "sources/blogs/amandeep-nvfp4-attempts.md", "url": "https://amandeepsp.github.io/blog/nvfp4-blackwell-gemv/"}, {"path": "sources/contests/gpu-mode-nvfp4/problem-1-gemv.md", "url": "https://github.com/gpu-mode/reference-kernels/tree/ae67948685dfccf54ae8374dc9402addb7aae4f6/problems/nvidia/nvfp4_gemv"}], "risk_flags": ["code", "ordering", "table"], "schema_version": "kernel-wiki-verifier-queue/v2", "source_ids": ["doc-ptx-isa-sm100", "doc-cuda-register-controls", "blog-yue-nvfp4", "blog-amandeep-nvfp4", "contest-gpumode-p1"], "title": "Vectorized Loads and Cache Hints", "type": "technique", "unresolved_source_ids": [], "version_sensitive": null} +{"body_sha256": "9cff7bf68b39a3b6cef5c930d99bd525e7e3f232e933f44bee877722f8ecaa6c", "claim_units": [{"id": "u001", "kind": "prose", "locator": "body:L3-L3", "preview": "Warp specialization assigns different long-lived functions to disjoint warps in a CTA\u2014for example scheduler, TMA load, MMA control, softmax/correction, or epilogue work. It is a software organization for overlapping pipeline stages, not a f", "sha256": "3ba8e2f12c87ebb0e5dcc7c4505180f38dc8ff8beac7d1d793ab842d17117595"}, {"id": "u002", "kind": "prose", "locator": "body:L5-L5", "preview": "The architecture-level comparison is narrower:", "sha256": "f5fce66b629d64368a8ad2f3262804a0414fb44cf8e2cad0753ec4c379769a0d"}, {"id": "u003", "kind": "table-row", "locator": "body:L9-L9", "preview": "| Property | Hopper `wgmma.mma_async` | Blackwell `tcgen05.mma` | | Issue granularity | Warpgroup collective | One thread for `cta_group::1` or `cta_group::2` |", "sha256": "78012326dd8c87c08b14223c51cb0caca44f22f93153cad66a4f9db57ff7f46c"}, {"id": "u004", "kind": "table-row", "locator": "body:L10-L10", "preview": "| Property | Hopper `wgmma.mma_async` | Blackwell `tcgen05.mma` | | D accumulator | Per-thread registers | TMEM |", "sha256": "9d8f6c6479d0022158169c0c47e8d10179521df1707c1a368c754cc5a2a3a884"}, {"id": "u005", "kind": "table-row", "locator": "body:L11-L11", "preview": "| Property | Hopper `wgmma.mma_async` | Blackwell `tcgen05.mma` | | A/B movement | Explicit register/SMEM operands and producer work | Explicit SMEM descriptors or TMEM addresses and producer work |", "sha256": "562e8662604420b24685b52bbc320c26ac8d2af69a511ce0e6e24f94d573f776"}, {"id": "u006", "kind": "table-row", "locator": "body:L12-L12", "preview": "| Property | Hopper `wgmma.mma_async` | Blackwell `tcgen05.mma` | | Completion | WGMMA commit/wait groups | `tcgen05.commit` tied to an mbarrier, followed by a wait |", "sha256": "9adf92e37d53097b532873a08e3c9c1fb6d611b608108674deb1ff1e73395fe6"}, {"id": "u007", "kind": "prose", "locator": "body:L14-L14", "preview": "Single-thread issue reduces the number of threads needed to submit MMA instructions. It does not make operands move automatically, turn an entire warp into an ISA-level role, complete MMA synchronously, or choose how many epilogue warps a k", "sha256": "04a758f12de17c65173d342cb8f24e546f345fb1e1d1e7807da8597afc4c9033"}, {"id": "u008", "kind": "prose", "locator": "body:L18-L18", "preview": "There is no universal \u201cwarp 0 load, warp 1 MMA, warps 2\u201315 epilogue\u201d rule. Three primary implementations illustrate the range:", "sha256": "85be6e7da4f7a119a0268d227c104475692b8b379b0e80a19e54c5ecadf8d6d0"}, {"id": "u009", "kind": "table-row", "locator": "body:L22-L22", "preview": "| Implementation | Total warps and roles | | Gau Nernst tutorial v4, commit `3b90ac9b...` | 4 warps. An elected lane in warp 0 runs the TMA loop; an elected lane in warp 1 runs the MMA loop; after completion, all four warps participate in T", "sha256": "04f9a434f6d86ab29394b02159dd40778cf936ab3da64f4c13afea393bf664ee"}, {"id": "u010", "kind": "table-row", "locator": "body:L23-L23", "preview": "| Implementation | Total warps and roles | | CUTLASS 4.5.0 generic SM100 GEMM | One warp each for `MMA`, `Sched`, `MainloopLoad`, and `EpilogueLoad`, followed by `CollectiveEpilogue::ThreadCount / 32` epilogue warps. Optional work can make ", "sha256": "cdd3cb833878e188948d9fa2d121d4b3ac4deb77d7309f891e965cff438b590c"}, {"id": "u011", "kind": "table-row", "locator": "body:L24-L24", "preview": "| Implementation | Total warps and roles | | FlashInfer PR 1039 context FMHA | 16 warps: 0\u20133 `Softmax0`, 4\u20137 `Softmax1`, 8\u201311 correction, 12 MMA, 13 load, 14 epilogue, and 15 empty. The kernel has explicit pipelines between these roles. |", "sha256": "a1adbbd5ec3b0d9716988bb7715ca8f100d59539d41bb5bfa1bb704f18062ac2"}, {"id": "u012", "kind": "prose", "locator": "body:L26-L26", "preview": "FlashAttention-4's pinned SM100 forward source likewise starts from a 16-warp layout with two four-warp softmax groups, four correction warps, and dedicated MMA/load/epilogue IDs, then adjusts roles for configuration choices such as one Q s", "sha256": "85453f8d16b28425bdf3fabef09e21c9aa6f172224da9679fd66630af21a45ae"}, {"id": "u013", "kind": "prose", "locator": "body:L30-L30", "preview": "A warp-specialized implementation must prove each ownership handoff. For a reusable TMA-to-MMA stage:", "sha256": "901977eb7283ec2dcce8362743f2200d3162ca12f2f28ca013243cee361015f0"}, {"id": "u014", "kind": "list-item", "locator": "body:L32-L32", "preview": "1. Initialize the mbarrier objects with correct participant/transaction counts and publish them to the required threads and async proxies before use.", "sha256": "9b61910e09ca8df51a88598997a7a9ccf36c7e3a690f01531a4933e884dcbe37"}, {"id": "u015", "kind": "list-item", "locator": "body:L33-L33", "preview": "2. The producer acquires an empty stage, sets expected transaction bytes, and submits the TMA copies. The full/data-ready phase completes only after the expected async transactions complete.", "sha256": "6480a07f2fe51b271cadf66a732a388767b3bc00f4b7b5d69ae5081150fc2337"}, {"id": "u016", "kind": "list-item", "locator": "body:L34-L34", "preview": "3. The MMA controller waits for the full phase and applies the required cross-thread/proxy fence before issuing `tcgen05.mma` against that SMEM stage.", "sha256": "8c289184a687c5b6dc0a191ff7f7c890df85100e6e37b09bb7251409b2af34df"}, {"id": "u017", "kind": "list-item", "locator": "body:L35-L35", "preview": "4. Because MMA is asynchronous, `__syncwarp()` or an ordinary `mbarrier.arrive` after issue does not make the operands reusable. Commit prior tcgen05 work to an mbarrier and wait for completion before releasing or overwriting the stage.", "sha256": "e95047726737de8cacee65eccb16e9c33b29eb85a3f60bd462536178e6ccf539"}, {"id": "u018", "kind": "list-item", "locator": "body:L36-L36", "preview": "5. Before another role reads D from TMEM, complete the MMA sequence and apply the required `tcgen05.fence::before_thread_sync` / execution-ordering handoff / `tcgen05.fence::after_thread_sync` protocol. A fence orders operations; it is not ", "sha256": "c144a17005a0a78e9914bbf04f8e669ae34d5edc880fd085e95eb70a070df51c"}, {"id": "u019", "kind": "list-item", "locator": "body:L37-L37", "preview": "6. Keep TMEM allocated until every consumer finishes its `tcgen05.ld` sequence and associated waits, then deallocate with the required collective participation.", "sha256": "0c51e8e3c826e6843d2f29ea4dadff3c0aec26d0e2e3f62b60976ff405bc3857"}, {"id": "u020", "kind": "prose", "locator": "body:L39-L39", "preview": "Pipeline wrappers in CUTLASS/CuTe encode parts of these rules, but participant counts, initial phases, tails, and producer/consumer states remain configuration-specific. A short role-dispatch sketch is not a substitute for the complete pipe", "sha256": "89b2f283a5df3d8a1f56bf6af22a431d104476439e941498a2c99702463b4198"}, {"id": "u021", "kind": "prose", "locator": "body:L43-L43", "preview": "For the author's exact `M=N=K=4096` Modal B200 setup with PyTorch 2.9.1 and CUDA 13, tutorial v3 reports 939.61 TFLOP/s and v4 reports 1208.83 TFLOP/s after introducing warp specialization. That is a 269.22-TFLOP/s, approximately 28.65% ste", "sha256": "6621d3a76f8c031fec1925cda99d56cfdf593b282737d84897dd3277eeb93451"}, {"id": "u022", "kind": "prose", "locator": "body:L47-L47", "preview": "Use it as a candidate when independent pipeline roles have enough steady-state work to overlap and their register needs differ materially. Compare it with a temporally pipelined version at the same tile shape, stage count, CTA-group mode, a", "sha256": "1627600031e403cc9fddb951b81bf297d7caa64fb89255c37db446929c69e78b"}, {"id": "u023", "kind": "list-item", "locator": "body:L49-L49", "preview": "- time and achieved throughput across representative shapes;", "sha256": "8932c9b5bb7697e947fe26437053390822855b8d9afe20b6084fb4aa9ab88b26"}, {"id": "u024", "kind": "list-item", "locator": "body:L50-L50", "preview": "- per-role active/stall time and pipeline backpressure;", "sha256": "366a32c28b89526070b467e74080a4bf9f037e0f770c23f0a439da3094e25b40"}, {"id": "u025", "kind": "list-item", "locator": "body:L51-L51", "preview": "- register allocation, spills, shared memory, and occupancy;", "sha256": "e6d4d8f371f22ff49a3f1b804e0e88ce3d32209249dc5d9b04d60e0793d7cc8e"}, {"id": "u026", "kind": "list-item", "locator": "body:L52-L52", "preview": "- TMA/MMA/epilogue balance, including prologue and tail cost;", "sha256": "a94aa0efb4d9bedf92e4e7496eaef4e479680d6899227cdd262b800f28a4a47e"}, {"id": "u027", "kind": "list-item", "locator": "body:L53-L53", "preview": "- 1-SM versus 2-SM mode as an independent legal-shape/resource choice.", "sha256": "eecde6ff7378da0ec52ac7970d16eca0580901fa5268e91d4e8dac14c05f5c0f"}, {"id": "u028", "kind": "prose", "locator": "body:L55-L55", "preview": "More role warps are not automatically useful for a more complex epilogue, and one MMA-control warp does not limit the issuer to one outstanding asynchronous MMA operation. Choose participant counts from the concrete collective and measureme", "sha256": "1f5622ad117b53bfcf321b00eccfc035da8b2468ad897d4b62c3e0c2ffd988a7"}, {"id": "u029", "kind": "prose", "locator": "body:L59-L59", "preview": "[`artifacts/kernels/warp-specialization/full/`](../../artifacts/kernels/warp-specialization/full/) contains the captured FlashInfer PR 1039 mainloop file; its bytes match the SHA-256 recorded in `PROVENANCE.yaml` and the duplicate captured ", "sha256": "2f40dc82464551aafd8efd85eb3d27958f6b2220bb352611772e73c0998ec3c0"}, {"id": "u030", "kind": "prose", "locator": "body:L61-L61", "preview": "[`artifacts/kernels/warp-specialization/variants/`](../../artifacts/kernels/warp-specialization/variants/) is explicitly `derived` teaching material and must not be cited as upstream code or as a complete safe kernel.", "sha256": "9b8752deff98b9437a0ad5787db5b0941b2c657c3ca2c5ca0a4a02cab448e48e"}, {"id": "u031", "kind": "prose", "locator": "body:L63-L63", "preview": "Retrieve the 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b/verification/evidence/README.md @@ -0,0 +1,30 @@ +# Repository-local verification evidence + +`local-snapshots/` contains the exact files and named source subtrees used by +the verifier reports. Nested Git metadata is intentionally excluded. + +`MANIFEST.json` records the stable repository-relative path, revision labels, +file count, byte count, and SHA-256 digest for every copied evidence target. +Two complete CUTLASS checkout roots that were used only for repository-wide +searches are represented by the immutable upstream commit tree recorded in the +manifest; copying both full worktrees would have added roughly 200 MiB. + +`historical-artifacts/` preserves six small files that remediation later +deleted or replaced but that original-review receipts still cite. Its separate +manifest records the source Git revision and SHA-256 for every restored file. + +Exact host checks cited by receipts live in +`verification/tools/check_verification_evidence.py`. The aggregate audit checks structured +paths and commands, and can also fetch every current evidence URL and validate +NVIDIA fragments: + +```bash +python3 verification/tools/audit_verification_evidence.py --network +``` + +Do not edit copied source files in place. Re-run the migration from the pinned +source checkouts when evidence must be refreshed, then validate the result: + +```bash +python3 verification/tools/migrate_verification_evidence.py --check +``` diff --git a/verification/evidence/historical-artifacts/MANIFEST.json b/verification/evidence/historical-artifacts/MANIFEST.json new file mode 100644 index 000000000..3bba55fab --- /dev/null +++ b/verification/evidence/historical-artifacts/MANIFEST.json @@ -0,0 +1,48 @@ +{ + "files": [ + { + "bytes": 1453, + "path": "verification/evidence/historical-artifacts/artifacts/kernels/flashmla/variants/01-mla-decode-inner-loop.cu", + "revision": "2777d18", + "sha256": "4f494dc2d282468966a1e2028bc50d0ef0c364b34d24f75ee881608ddef2df69", + "source_path": "artifacts/kernels/flashmla/variants/01-mla-decode-inner-loop.cu" + }, + { + "bytes": 1451, + "path": "verification/evidence/historical-artifacts/artifacts/kernels/gated-delta-net/variants/01-chunk-parallel-prefill-reference-pytorch.py", + "revision": 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rename from artifacts/kernels/flashmla/variants/01-mla-decode-inner-loop.cu rename to verification/evidence/historical-artifacts/artifacts/kernels/flashmla/variants/01-mla-decode-inner-loop.cu diff --git a/artifacts/kernels/gated-delta-net/variants/01-chunk-parallel-prefill-reference-pytorch.py b/verification/evidence/historical-artifacts/artifacts/kernels/gated-delta-net/variants/01-chunk-parallel-prefill-reference-pytorch.py similarity index 100% rename from artifacts/kernels/gated-delta-net/variants/01-chunk-parallel-prefill-reference-pytorch.py rename to verification/evidence/historical-artifacts/artifacts/kernels/gated-delta-net/variants/01-chunk-parallel-prefill-reference-pytorch.py diff --git a/artifacts/kernels/gated-delta-net/variants/02-triton-decode-step-kernel-streaming.py b/verification/evidence/historical-artifacts/artifacts/kernels/gated-delta-net/variants/02-triton-decode-step-kernel-streaming.py similarity index 100% rename from artifacts/kernels/gated-delta-net/variants/02-triton-decode-step-kernel-streaming.py rename to verification/evidence/historical-artifacts/artifacts/kernels/gated-delta-net/variants/02-triton-decode-step-kernel-streaming.py diff --git a/artifacts/kernels/gated-dual-gemm/full/blackwell-cutlass-schedules-and-tma.cu b/verification/evidence/historical-artifacts/artifacts/kernels/gated-dual-gemm/full/blackwell-cutlass-schedules-and-tma.cu similarity index 100% rename from artifacts/kernels/gated-dual-gemm/full/blackwell-cutlass-schedules-and-tma.cu rename to verification/evidence/historical-artifacts/artifacts/kernels/gated-dual-gemm/full/blackwell-cutlass-schedules-and-tma.cu diff --git a/artifacts/kernels/gated-dual-gemm/full/vllm-PR-23696-gated-dual-gemm.patch b/verification/evidence/historical-artifacts/artifacts/kernels/gated-dual-gemm/full/vllm-PR-23696-gated-dual-gemm.patch similarity index 100% rename from artifacts/kernels/gated-dual-gemm/full/vllm-PR-23696-gated-dual-gemm.patch rename to verification/evidence/historical-artifacts/artifacts/kernels/gated-dual-gemm/full/vllm-PR-23696-gated-dual-gemm.patch diff --git a/artifacts/kernels/gated-dual-gemm/variants/01-fused-epilogue-swiglu-skeleton.cu b/verification/evidence/historical-artifacts/artifacts/kernels/gated-dual-gemm/variants/01-fused-epilogue-swiglu-skeleton.cu similarity index 100% rename from artifacts/kernels/gated-dual-gemm/variants/01-fused-epilogue-swiglu-skeleton.cu rename to verification/evidence/historical-artifacts/artifacts/kernels/gated-dual-gemm/variants/01-fused-epilogue-swiglu-skeleton.cu diff --git a/verification/evidence/local-snapshots/cutlass-audit.8aj07j/repo/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu b/verification/evidence/local-snapshots/cutlass-audit.8aj07j/repo/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu new file mode 100644 index 000000000..0a5d6c314 --- /dev/null +++ b/verification/evidence/local-snapshots/cutlass-audit.8aj07j/repo/examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm.cu @@ -0,0 +1,597 @@ +/*************************************************************************************************** + * Copyright (c) 2025 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*! \file + \brief A GEMM example using CUTLASS for the NVIDIA Blackwell SM100 architecture. + + This example demonstrate a simple way to instantiate and run a blockscaled NVFP4 GEMM on the NVIDIA Blackwell SM100 architecture + on NVIDIA Blackwell SM100 architecture. The kernel outputs quantized fp4 values with scale factors that be the input of another GEMM. + + Similar to 72a_blackwell_nvfp4_bf16_gemm, this kernel leverages: + 1. Blockscaled tcgen05.mma instructions. + + 2. Per-SM memory called Tensor Memory (TMEM) + + 3. The extended warp-specialized kernel design introduced in Hopper enabled by use of TMEM + which allows us to decouple the execution of MMA and epilogue into separate warps. + + 4. A new SW controlled dynamic scheduler based on cluster launch control (See https://docs.nvidia.com/cuda/parallel-thread-execution). + + Usage: + + $ ./examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm --m=2048 --n=2048 --k=2048 +*/ + +#include + +#include "cutlass/cutlass.h" + +#include "cute/tensor.hpp" +#include "cutlass/tensor_ref.h" +#include "cutlass/epilogue/thread/linear_combination.h" +#include "cutlass/gemm/dispatch_policy.hpp" +#include "cutlass/gemm/collective/collective_builder.hpp" +#include "cutlass/epilogue/collective/collective_builder.hpp" +#include "cutlass/detail/sm100_blockscaled_layout.hpp" +#include "cutlass/gemm/device/gemm_universal_adapter.h" +#include "cutlass/gemm/kernel/gemm_universal.hpp" +#include "cutlass/gemm/kernel/tile_scheduler_params.h" + +#include "cutlass/util/command_line.h" +#include "cutlass/util/distribution.h" +#include "cutlass/util/host_tensor.h" +#include "cutlass/util/packed_stride.hpp" +#include "cutlass/util/tensor_view_io.h" +#include "cutlass/util/reference/device/gemm.h" +#include "cutlass/util/reference/device/tensor_compare.h" +#include "cutlass/util/reference/host/tensor_fill.h" +#include "cutlass/util/reference/host/gett.hpp" +#include "cutlass/util/reference/host/tensor_norm.h" +#include "cutlass/util/reference/host/tensor_compare.h" + + +#include + +#include "helper.h" + +using namespace cute; + +#if defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + + +///////////////////////////////////////////////////////////////////////////////////////////////// +/// GEMM kernel configurations +///////////////////////////////////////////////////////////////////////////////////////////////// + +// A matrix configuration +using ElementA = cutlass::nv_float4_t; // Element type for A matrix operand +using LayoutATag = cutlass::layout::RowMajor; // Layout type for A matrix operand +constexpr int AlignmentA = 32; // Memory access granularity/alignment of A matrix in units of elements (up to 16 bytes) + +// B matrix configuration +using ElementB = cutlass::nv_float4_t; // Element type for A matrix operand +using LayoutBTag = cutlass::layout::ColumnMajor; // Layout type for B matrix operand +constexpr int AlignmentB = 32; // Memory access granularity/alignment of B matrix in units of elements (up to 16 bytes) + +// C/D matrix configuration +using ElementD = cutlass::float_e2m1_t; // Element type for D matrix operand +using ElementSFD = cutlass::float_ue8m0_t; // Element type for SFB matrix operand +using ElementC = float; // Element type for C matrix operand +using LayoutCTag = cutlass::layout::RowMajor; // Layout type for C matrix operand +using LayoutDTag = cutlass::layout::RowMajor; // Layout type for D matrix operand +using LayoutSFDTag = LayoutDTag; // Layout type for SFD should be same as D matrix operand + +constexpr int AlignmentD = 128 / cutlass::sizeof_bits::value; // Memory access granularity/alignment of C matrix in units of elements (up to 16 bytes) +constexpr int AlignmentC = 128 / cutlass::sizeof_bits::value; // Memory access granularity/alignment of C matrix in units of elements (up to 16 bytes) + +// Kernel functional config +using ElementAccumulator = float; // Element type for internal accumulation +using ElementCompute = float; // Element type for internal accumulation +using ArchTag = cutlass::arch::Sm100; // Tag indicating the minimum SM that supports the intended feature +using OperatorClass = cutlass::arch::OpClassBlockScaledTensorOp; // Operator class tag + +// Kernel Perf config +using MmaTileShape = Shape<_128,_128,_256>; // MMA's tile size +using ClusterShape = Shape<_1,_1,_1>; // Shape of the threadblocks in a cluster + +constexpr int InputSFVectorSize = 16; +constexpr int OutputSFVectorSize = InputSFVectorSize; + +// D = alpha * acc + beta * C +// With BlockScaleFactor generation. +using FusionOperation = cutlass::epilogue::fusion::LinCombBlockScaleFactor< + OutputSFVectorSize, + ElementD, + ElementCompute, + ElementSFD, LayoutSFDTag, + ElementC>; + +using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder< + ArchTag, OperatorClass, + MmaTileShape, ClusterShape, + cutlass::epilogue::collective::EpilogueTileAuto, + ElementAccumulator, ElementAccumulator, + ElementC, LayoutCTag, AlignmentC, + ElementD, LayoutDTag, AlignmentD, + cutlass::epilogue::collective::EpilogueScheduleAuto, // Epilogue schedule policy + FusionOperation + >::CollectiveOp; + +using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder< + ArchTag, OperatorClass, + ElementA, LayoutATag, AlignmentA, + ElementB, LayoutBTag, AlignmentB, + ElementAccumulator, + MmaTileShape, ClusterShape, + cutlass::gemm::collective::StageCountAutoCarveout(sizeof(typename CollectiveEpilogue::SharedStorage))>, + cutlass::gemm::collective::KernelScheduleAuto // Kernel schedule policy. Auto or using targeted scheduling policy + >::CollectiveOp; + +using GemmKernel = cutlass::gemm::kernel::GemmUniversal< + Shape, // Indicates ProblemShape + CollectiveMainloop, + CollectiveEpilogue, + void>; + +using Gemm = cutlass::gemm::device::GemmUniversalAdapter; + +// Reference device GEMM implementation type +using StrideA = typename Gemm::GemmKernel::StrideA; +using LayoutA = decltype(cute::make_layout(make_shape(0,0,0), StrideA{})); +using LayoutSFA = typename Gemm::GemmKernel::CollectiveMainloop::LayoutSFA; // Scale Factor tensors have an interleaved layout. Bring Layout instead of stride. +using StrideB = typename Gemm::GemmKernel::StrideB; +using LayoutB = decltype(cute::make_layout(make_shape(0,0,0), StrideB{})); +using LayoutSFB = typename Gemm::GemmKernel::CollectiveMainloop::LayoutSFB; // Scale Factor tensors have an interleaved layout. Bring Layout instead of stride. +using StrideC = typename Gemm::GemmKernel::StrideC; +using LayoutC = decltype(cute::make_layout(make_shape(0,0,0), StrideC{})); +using StrideD = typename Gemm::GemmKernel::StrideD; +using LayoutD = decltype(cute::make_layout(make_shape(0,0,0), StrideD{})); + +using FusionOp = typename Gemm::EpilogueOutputOp; +constexpr bool IsBlockScaleSupported = FusionOp::IsBlockScaleSupported; +using SfdOutputCfg = cutlass::detail::Sm1xxBlockScaledOutputConfig; +using LayoutSFD = typename SfdOutputCfg::LayoutSF; + +// +// Data members +// + +/// Initialization +StrideA stride_A; +LayoutA layout_A; +LayoutSFA layout_SFA; +StrideB stride_B; +LayoutB layout_B; +LayoutSFB layout_SFB; +StrideC stride_C; +LayoutC layout_C; +StrideD stride_D; +LayoutD layout_D; +LayoutSFD layout_SFD; + +uint64_t seed; + +// The HostTensors are only used for allocating memory on host and device, and transferring data between host and device +// Use cute::Tensor and cute::Layout for iterating thru the matrix elements +cutlass::HostTensor block_A; +cutlass::HostTensor block_SFA; +cutlass::HostTensor block_B; +cutlass::HostTensor block_SFB; +cutlass::HostTensor block_C; +// Output Tensors +cutlass::HostTensor block_D; +cutlass::HostTensor block_SFD; +// Reference Output Tensors +cutlass::HostTensor block_reference_D; +cutlass::HostTensor block_reference_SFD; +// Matrix-wide normalization constant +cutlass::HostTensor block_Normconst; + +#endif // defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + +template +auto make_iterator(T* ptr) { + return cute::recast_ptr(ptr); +} + +///////////////////////////////////////////////////////////////////////////////////////////////// +/// Testbed utility types +///////////////////////////////////////////////////////////////////////////////////////////////// + +// Command line options parsing +struct Options { + + bool help; + + float alpha, beta; + int iterations; + int m, n, k; + int swizzle = 0; + + Options(): + help(false), + m(1024), n(1024), k(1024), + alpha(1.f), beta(0.f), + iterations(10), + swizzle(0) + { } + + // Parses the command line + void parse(int argc, char const **args) { + cutlass::CommandLine cmd(argc, args); + + if (cmd.check_cmd_line_flag("help")) { + help = true; + return; + } + + cmd.get_cmd_line_argument("m", m); + cmd.get_cmd_line_argument("n", n); + cmd.get_cmd_line_argument("k", k); + cmd.get_cmd_line_argument("alpha", alpha, 1.f); + cmd.get_cmd_line_argument("beta", beta, 0.f); + cmd.get_cmd_line_argument("iterations", iterations); + cmd.get_cmd_line_argument("swizzle", swizzle); + } + + /// Prints the usage statement. + std::ostream & print_usage(std::ostream &out) const { + + out << "72b_blackwell_nvfp4_nvfp4_gemm\n\n" + << " Blackwell NVFP4 GEMM using a Warp Specialized kernel.\n\n" + << "Options:\n\n" + << " --help If specified, displays this usage statement\n\n" + << " --m= Sets the M extent of the GEMM\n" + << " --n= Sets the N extent of the GEMM\n" + << " --k= Sets the K extent of the GEMM\n" + << " --alpha= Epilogue scalar alpha\n" + << " --beta= Epilogue scalar beta\n" + << " --swizzle= Cluster rasterization swizzle\n" + << " --iterations= Number of profiling iterations to perform.\n\n"; + + out << "\n\nExamples:\n\n" + << "$ " << "./examples/72_blackwell_narrow_precision_gemm/72b_blackwell_nvfp4_nvfp4_gemm" << " --m=1024 --n=512 --k=1024 --alpha=2 --beta=0.707 \n\n"; + + return out; + } + + /// Compute performance in GFLOP/s + double gflops(double runtime_s) const + { + // Two flops per multiply-add + uint64_t flop = uint64_t(2) * m * n * k; + double gflop = double(flop) / double(1.0e9); + return gflop / runtime_s; + } +}; + +/// Result structure +struct Result +{ + double avg_runtime_ms; + double gflops; + cutlass::Status status; + cudaError_t error; + bool passed; + + Result( + double avg_runtime_ms = 0, + double gflops = 0, + cutlass::Status status = cutlass::Status::kSuccess, + cudaError_t error = cudaSuccess) + : + avg_runtime_ms(avg_runtime_ms), gflops(gflops), status(status), error(error), passed(false) + {} + +}; + +#if defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + +///////////////////////////////////////////////////////////////////////////////////////////////// +/// GEMM setup and evaluation +///////////////////////////////////////////////////////////////////////////////////////////////// + +/// Helper to initialize a block of device data +template +bool initialize_block( + cutlass::TensorView view, + uint64_t seed) { + + double scope_max, scope_min; + constexpr int bits_input = cutlass::sizeof_bits::value; + + if constexpr (bits_input == 1) { + scope_max = 2; + scope_min = 0; + } + else if constexpr (bits_input <= 6) { + scope_max = 2; + scope_min = -2; + } + else if constexpr (bits_input <= 8) { + if constexpr (cute::is_same_v) { + scope_max = 4; + scope_min = 1; + } + else { + scope_max = 1; + scope_min = -1; + } + } + else{ + scope_max = 4; + scope_min = -4; + } + cutlass::reference::host::TensorFillRandomUniform( + view, seed, scope_max, scope_min, 0); + + return true; +} + +/// Initialize operands to be used in the GEMM and reference GEMM +void initialize(const Options &options) { + using namespace cute; + // For SFA and SFB tensors layouts + using Sm1xxBlkScaledConfig = typename Gemm::GemmKernel::CollectiveMainloop::Sm1xxBlkScaledConfig; + // For SFD tensor layout + using Sm1xxBlockScaledOutputConfig= typename Gemm::GemmKernel::CollectiveMainloop::Sm1xxBlkScaledConfig; + + stride_A = cutlass::make_cute_packed_stride(StrideA{}, {options.m, options.k, 1}); + stride_B = cutlass::make_cute_packed_stride(StrideB{}, {options.n, options.k, 1}); + stride_C = cutlass::make_cute_packed_stride(StrideC{}, {options.m, options.n, 1}); + stride_D = cutlass::make_cute_packed_stride(StrideD{}, {options.m, options.n, 1}); + + layout_A = make_layout(make_shape(options.m, options.k, 1), stride_A); + layout_B = make_layout(make_shape(options.n, options.k, 1), stride_B); + layout_C = make_layout(make_shape(options.m, options.n, 1), stride_C); + layout_D = make_layout(make_shape(options.m, options.n, 1), stride_D); + layout_SFA = Sm1xxBlkScaledConfig::tile_atom_to_shape_SFA(cute::make_shape(options.m, options.n, options.k, 1)); + layout_SFB = Sm1xxBlkScaledConfig::tile_atom_to_shape_SFB(cute::make_shape(options.m, options.n, options.k, 1)); + layout_SFD = SfdOutputCfg::tile_atom_to_shape_SFD(cute::make_shape(options.m, options.n, options.k, 1)); + + block_A.reset(cutlass::make_Coord(size(layout_A))); + block_B.reset(cutlass::make_Coord(size(layout_B))); + block_C.reset(cutlass::make_Coord(size(layout_C))); + block_D.reset(cutlass::make_Coord(size(layout_D))); + block_reference_D.reset(cutlass::make_Coord(size(layout_D))); + block_reference_SFD.reset(cutlass::make_Coord(size(filter_zeros(layout_SFD)))); + block_Normconst.reset(cutlass::make_Coord(1)); + + block_SFA.reset(cutlass::make_Coord(size(filter_zeros(layout_SFA)))); + block_SFB.reset(cutlass::make_Coord(size(filter_zeros(layout_SFB)))); + block_SFD.reset(cutlass::make_Coord(size(filter_zeros(layout_SFD)))); + + initialize_block(block_A.host_view(), seed + 2021); + initialize_block(block_B.host_view(), seed + 2022); + initialize_block(block_C.host_view(), seed + 2023); + initialize_block(block_SFA.host_view(), seed + 2024); + initialize_block(block_SFB.host_view(), seed + 2025); + block_Normconst.at(cutlass::make_Coord(0)) = 2; + + block_A.sync_device(); + block_B.sync_device(); + block_C.sync_device(); + block_D.sync_device(); + block_SFA.sync_device(); + block_SFB.sync_device(); + block_SFD.sync_device(); + block_Normconst.sync_device(); + +} + +// Populates a Gemm::Arguments structure from the given commandline options +typename Gemm::Arguments args_from_options(const Options &options) +{ + typename Gemm::Arguments arguments { + cutlass::gemm::GemmUniversalMode::kGemm, + {options.m, options.n, options.k, 1}, + { // Mainloop arguments + block_A.device_data(), stride_A, + block_B.device_data(), stride_B, + block_SFA.device_data(), layout_SFA, + block_SFB.device_data(), layout_SFB + }, + { // Epilogue arguments + { options.alpha, options.beta }, + block_C.device_data(), stride_C, + block_D.device_data(), stride_D} + }; + + if constexpr (IsBlockScaleSupported) { + arguments.epilogue.thread.block_scale_factor_ptr = block_SFD.device_data(); + arguments.epilogue.thread.norm_constant_ptr = block_Normconst.device_data(); + } + + arguments.scheduler.max_swizzle_size = options.swizzle; + return arguments; +} + +bool verify(const Options &options) { + using namespace cute; + // Create the arguments for host reference implementation + Tensor tensor_A = make_tensor(make_iterator(block_A.host_data()), layout_A); + Tensor tensor_SFA = make_tensor(block_SFA.host_data(), layout_SFA); + Tensor tensor_B = make_tensor(make_iterator(block_B.host_data()), layout_B); + Tensor tensor_SFB = make_tensor(block_SFB.host_data(), layout_SFB); + + // think about how to simplify the gemm3x interface. + cutlass::reference::host::GettBlockScalingMainloopParams< + ElementAccumulator, // ElementAccumulator + decltype(tensor_A), // TensorA + decltype(tensor_SFA), // TensorSfA + decltype(tensor_B), // TensorB + decltype(tensor_SFB) // TensorSfB + > mainloop_params{tensor_A, tensor_SFA, tensor_B, tensor_SFB}; + + Tensor tensor_C = cute::make_tensor(make_iterator(block_C.host_data()), layout_C); + Tensor tensor_D = cute::make_tensor(make_iterator(block_reference_D.host_data()), layout_D); + Tensor tensor_SFD = make_tensor(block_reference_SFD.host_data(), layout_SFD); + + cutlass::reference::host::GettBlockScalingEpilogueParams< + ElementCompute, // ElementScalar + ElementAccumulator, // ElementAccumulator + ElementCompute, // ElementCompute + decltype(tensor_C), // TensorC + decltype(tensor_D), // TensorD + decltype(tensor_SFD), // TensorSfD + cute::Int, + cutlass::reference::host::SfStrategy::SfDGen + > epilogue_params {options.alpha, options.beta, tensor_C, tensor_D, tensor_SFD, block_Normconst.at(cutlass::make_Coord(0))}; + + cutlass::reference::host::Gemm3x(mainloop_params, epilogue_params); + + // Comparison + block_D.sync_host(); + bool passed = cutlass::reference::host::TensorEquals(block_reference_D.host_view(), block_D.host_view()); + passed &= (cutlass::reference::host::TensorNorm(block_reference_D.host_view()) > 0); + passed &= (cutlass::reference::host::TensorNorm(block_D.host_view()) > 0); + + block_SFD.sync_host(); + bool passed_sfd = cutlass::reference::host::TensorEquals(block_reference_SFD.host_view(), block_SFD.host_view()); + passed_sfd &= (cutlass::reference::host::TensorNorm(block_reference_SFD.host_view()) > 0); + passed_sfd &= (cutlass::reference::host::TensorNorm(block_SFD.host_view()) > 0); + + return passed && passed_sfd; +} + +/// Execute a given example GEMM computation +template +int run(Options &options) +{ + initialize(options); + + // Instantiate CUTLASS kernel depending on templates + Gemm gemm; + + // Create a structure of gemm kernel arguments suitable for invoking an instance of Gemm + auto arguments = args_from_options(options); + + // Using the arguments, query for extra workspace required for matrix multiplication computation + size_t workspace_size = Gemm::get_workspace_size(arguments); + + // Allocate workspace memory + cutlass::device_memory::allocation workspace(workspace_size); + + // Check if the problem size is supported or not + CUTLASS_CHECK(gemm.can_implement(arguments)); + + // Initialize CUTLASS kernel with arguments and workspace pointer + CUTLASS_CHECK(gemm.initialize(arguments, workspace.get())); + + // Correctness / Warmup iteration + CUTLASS_CHECK(gemm.run()); + + cudaDeviceSynchronize(); + + // Check if output from CUTLASS kernel and reference kernel are equal or not + Result result; + result.passed = verify(options); + + std::cout << " Disposition: " << (result.passed ? "Passed" : "Failed") << std::endl; + + if (!result.passed) { + exit(-1); + } + + // Run profiling loop + if (options.iterations > 0) + { + GpuTimer timer; + timer.start(); + for (int iter = 0; iter < options.iterations; ++iter) { + CUTLASS_CHECK(gemm.initialize(arguments, workspace.get())); + CUTLASS_CHECK(gemm.run()); + } + timer.stop(); + + // Compute average runtime and GFLOPs. + float elapsed_ms = timer.elapsed_millis(); + result.avg_runtime_ms = double(elapsed_ms) / double(options.iterations); + result.gflops = options.gflops(result.avg_runtime_ms / 1000.0); + + + std::cout << " Problem Size: " << options.m << 'x' << options.n << 'x' << options.k << std::endl; + std::cout << " Avg runtime: " << result.avg_runtime_ms << " ms" << std::endl; + std::cout << " GFLOPS: " << result.gflops << std::endl; + } + + return 0; +} + +#endif // defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +int main(int argc, char const **args) { + + // CUTLASS must be compiled with CUDA 12.8 or higher Toolkit to run this example + // and must have compute capability at least 100. + if (__CUDACC_VER_MAJOR__ < 12 || (__CUDACC_VER_MAJOR__ == 12 && __CUDACC_VER_MINOR__ < 8)) { + std::cerr << "This example requires CUDA 12.8 or newer." << std::endl; + // Returning zero so this test passes on older Toolkits. Its actions are no-op. + return 0; + } + + cudaDeviceProp props; + int current_device_id; + CUDA_CHECK(cudaGetDevice(¤t_device_id)); + + CUDA_CHECK(cudaGetDeviceProperties(&props, current_device_id)); + + if (props.major != 10 || (props.minor != 0 && props.minor != 1 && props.minor != 3)) { + std::cerr << "This example requires a GPU with compute capability 100a|f, 101a|f, or 103a|f)." << std::endl; + return 0; + } + + // + // Parse options + // + + Options options; + + options.parse(argc, args); + + if (options.help) { + options.print_usage(std::cout) << std::endl; + return 0; + } + + // + // Evaluate CUTLASS kernels + // +#if defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + run(options); +#endif // defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + + return 0; +} + +///////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/verification/evidence/local-snapshots/cutlass-audit.8aj07j/repo/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu b/verification/evidence/local-snapshots/cutlass-audit.8aj07j/repo/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu new file mode 100644 index 000000000..1ff8f2152 --- /dev/null +++ b/verification/evidence/local-snapshots/cutlass-audit.8aj07j/repo/examples/75_blackwell_grouped_gemm/75_blackwell_grouped_gemm_block_scaled.cu @@ -0,0 +1,944 @@ +/*************************************************************************************************** + * Copyright (c) 2024 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + + + +/*! \file + \brief Grouped GEMM example using CUTLASS 3 APIs for the NVIDIA Blackwell SM100 architecture. + + This example demonstrates an implementation of Grouped GEMM using a TMA + Blackwell SM100 TensorOp-based warp-specialized kernel + for narrow precisions (FP4) with Scale Factors (In and Out). + For this example all scheduling work is performed on the device. + The new feature showcased in this example is device-side modification of TMA descriptors + to move between groups/problem_count (represented by groups). + https://docs.nvidia.com/cuda/cuda-c-programming-guide/#encoding-a-tensor-map-on-device + + To run this example: + + $ ./examples/75_blackwell_grouped_gemm_block_scaled/75_blackwell_grouped_gemm_block_scaled --m=2048 --n=2048 --k=2048 --groups=10 + + The above example command makes all 10 groups to be sized at the given m, n, k sizes. + Skipping any of the problem dimensions randomizes it across the different groups. + Same applies for alpha and beta values that are randomized across the different groups. + + To run this example for a set of problems using the benchmark option: + + $ ./examples/75_blackwell_grouped_gemm_block_scaled/75_blackwell_grouped_gemm_block_scaled --benchmark=./test_benchmark.txt + + Where the test_benchmark.txt may look as such: + 0 256x512x128 + 1 256x512x512 + 2 512x256x128 + 3 256x256x128 + 4 256x512x1024 + 5 1024x512x128 and so on +*/ + +#include +#include +#include +#include +#include +#include + +#include "cutlass/cutlass.h" + +#include "cute/tensor.hpp" +#include "cutlass/tensor_ref.h" +#include "cutlass/epilogue/collective/default_epilogue.hpp" +#include "cutlass/epilogue/thread/linear_combination.h" +#include "cutlass/gemm/dispatch_policy.hpp" +#include "cutlass/gemm/group_array_problem_shape.hpp" +#include "cutlass/gemm/collective/collective_builder.hpp" +#include "cutlass/epilogue/collective/collective_builder.hpp" +#include "cutlass/gemm/device/gemm_universal_adapter.h" +#include "cutlass/gemm/kernel/gemm_universal.hpp" + +#include "cutlass/util/command_line.h" +#include "cutlass/util/distribution.h" +#include "cutlass/util/host_tensor.h" +#include "cutlass/util/packed_stride.hpp" +#include "cutlass/util/tensor_view_io.h" +#include "cutlass/util/reference/device/gemm.h" +#include "cutlass/util/reference/device/tensor_compare.h" +#include "cutlass/util/reference/host/tensor_fill.h" +#include "cutlass/util/reference/host/gett.hpp" +#include "cutlass/util/reference/host/tensor_norm.h" +#include "cutlass/util/reference/host/tensor_compare.h" + +#include "helper.h" +using namespace cute; + +using ProblemShape = cutlass::gemm::GroupProblemShape>; // per group +using ElementInput = cutlass::float_e2m1_t; // Element type for Input matrix operands +using ElementSF = cutlass::float_ue4m3_t; // Element type for SF matrix operands +using ElementC = cutlass::half_t; // Element type for C matrix operands + +#if defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) +///////////////////////////////////////////////////////////////////////////////////////////////// +/// GEMM kernel configurations +///////////////////////////////////////////////////////////////////////////////////////////////// +// A matrix configuration +using ElementA = cutlass::nv_float4_t; // Element type for A matrix operand +using LayoutA = cutlass::layout::RowMajor; // Layout type for A matrix operand +constexpr int AlignmentA = 32; // Alignment of A matrix in units of elements (up to 16 bytes) + +// B matrix configuration +using ElementB = cutlass::nv_float4_t; // Element type for B matrix operand +using LayoutB = cutlass::layout::ColumnMajor; // Layout type for B matrix operand +constexpr int AlignmentB = 32; // Alignment of A matrix in units of elements (up to 16 bytes) + +// C/D matrix configuration +using ElementD = ElementC; // Element type for D matrix operands +using LayoutC = cutlass::layout::RowMajor; // Layout type for C and D matrix operands +constexpr int AlignmentC = 128 / cutlass::sizeof_bits::value; // Alignment of C matrix in units of elements (up to 16 bytes) +constexpr int AlignmentD = 128 / cutlass::sizeof_bits::value; // Alignment of D matrix in units of elements (up to 16 bytes) +using ElementAccumulator = float; // Element type for internal accumulation + +// using ElementD = cutlass::float_e2m1_t; // Enable for SF Output // Element type for D matrix operands + +using ElementSFD = cutlass::float_ue4m3_t; // Element type for SF Output operands +constexpr int OutputSFVectorSize = 16; +using FusionOperation = cutlass::epilogue::fusion::LinCombEltActBlockScaleFactor< + cutlass::epilogue::thread::SiLu, + OutputSFVectorSize, + ElementD, + ElementAccumulator, + ElementSFD, + LayoutC, + ElementC>; + +// Core kernel configurations +using ArchTag = cutlass::arch::Sm100; // Tag indicating the minimum SM that supports the intended feature +using OperatorClass = cutlass::arch::OpClassBlockScaledTensorOp; // Operator class tag +using StageCountType = cutlass::gemm::collective::StageCountAuto; // Stage count maximized based on the tile size + +// Runtime Cluster Shape +using ClusterShape = Shape; + +// Different configs for 1SM and 2SM MMA kernel +struct MMA1SMConfig { + using MmaTileShape = Shape<_128,_256,_256>; + using KernelSchedule = cutlass::gemm::KernelPtrArrayTmaWarpSpecialized1SmNvf4Sm100; // Kernel to launch + using EpilogueSchedule = cutlass::epilogue::PtrArrayTmaWarpSpecialized1Sm; // Epilogue to launch +}; + +struct MMA2SMConfig { + using MmaTileShape = Shape<_256,_256,_256>; + using KernelSchedule = cutlass::gemm::KernelPtrArrayTmaWarpSpecialized2SmNvf4Sm100; // Kernel to launch + using EpilogueSchedule = cutlass::epilogue::PtrArrayTmaWarpSpecialized2Sm; // Epilogue to launch +}; + +using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder< + ArchTag, OperatorClass, + typename MMA1SMConfig::MmaTileShape, ClusterShape, + Shape<_128,_64>, + ElementAccumulator, ElementAccumulator, + ElementC, LayoutC *, AlignmentC, + ElementD, LayoutC *, AlignmentD, + typename MMA1SMConfig::EpilogueSchedule + // , FusionOperation // Enable for SF Output +>::CollectiveOp; +using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder< + ArchTag, OperatorClass, + ElementA, LayoutA *, AlignmentA, + ElementB, LayoutB *, AlignmentB, + ElementAccumulator, + typename MMA1SMConfig::MmaTileShape, ClusterShape, + cutlass::gemm::collective::StageCountAutoCarveout< + static_cast(sizeof(typename CollectiveEpilogue::SharedStorage))>, + typename MMA1SMConfig::KernelSchedule +>::CollectiveOp; +using GemmKernel = cutlass::gemm::kernel::GemmUniversal< + ProblemShape, + CollectiveMainloop, + CollectiveEpilogue +>; +using Gemm1SM = cutlass::gemm::device::GemmUniversalAdapter; +using Gemm = Gemm1SM; + +using CollectiveEpilogue2SM = typename cutlass::epilogue::collective::CollectiveBuilder< + ArchTag, OperatorClass, + typename MMA2SMConfig::MmaTileShape, ClusterShape, + Shape<_128,_64>, + ElementAccumulator, ElementAccumulator, + ElementC, LayoutC *, AlignmentC, + ElementD, LayoutC *, AlignmentD, + typename MMA2SMConfig::EpilogueSchedule + // , FusionOperation // Enable for SF Output +>::CollectiveOp; +using CollectiveMainloop2SM = typename cutlass::gemm::collective::CollectiveBuilder< + ArchTag, OperatorClass, + ElementA, LayoutA *, AlignmentA, + ElementB, LayoutB *, AlignmentB, + ElementAccumulator, + typename MMA2SMConfig::MmaTileShape, ClusterShape, + cutlass::gemm::collective::StageCountAutoCarveout< + static_cast(sizeof(typename CollectiveEpilogue2SM::SharedStorage))>, + typename MMA2SMConfig::KernelSchedule +>::CollectiveOp; +using GemmKernel2SM = cutlass::gemm::kernel::GemmUniversal< + ProblemShape, + CollectiveMainloop2SM, + CollectiveEpilogue2SM +>; +using Gemm2SM = cutlass::gemm::device::GemmUniversalAdapter; + +using StrideA = typename Gemm::GemmKernel::InternalStrideA; +using StrideB = typename Gemm::GemmKernel::InternalStrideB; +using StrideC = typename Gemm::GemmKernel::InternalStrideC; +using StrideD = typename Gemm::GemmKernel::InternalStrideD; + +using LayoutSFA = typename Gemm::GemmKernel::CollectiveMainloop::InternalLayoutSFA; +using LayoutSFB = typename Gemm::GemmKernel::CollectiveMainloop::InternalLayoutSFB; +using Sm1xxBlkScaledConfig = typename Gemm::GemmKernel::CollectiveMainloop::Sm1xxBlkScaledConfig; +using Sm1xxBlockScaledOutputConfig= cutlass::detail::Sm1xxBlockScaledOutputConfig< + OutputSFVectorSize, + cute::is_same_v ? cute::UMMA::Major::K : cute::UMMA::Major::MN + >; +using OutputSFAtom = typename Sm1xxBlockScaledOutputConfig::SfAtom; +using LayoutSFD = typename Sm1xxBlockScaledOutputConfig::LayoutSF; + +// Host-side allocations +std::vector stride_A_host; +std::vector stride_B_host; +std::vector layout_SFA_host; +std::vector layout_SFB_host; +std::vector stride_C_host; +std::vector stride_D_host; + +std::vector alpha_host; +std::vector beta_host; + +using HostTensorA = cutlass::HostTensor; +using HostTensorB = cutlass::HostTensor; +using HostTensorSF = cutlass::HostTensor; +using HostTensorC = cutlass::HostTensor; +using HostTensorD = cutlass::HostTensor; +std::vector block_A; +std::vector block_B; +std::vector block_SFA; +std::vector block_SFB; +std::vector block_C; +std::vector block_D; +std::vector block_SFD; +std::vector block_ref_D; + +// Device-side allocations +cutlass::DeviceAllocation problem_sizes; + +cutlass::DeviceAllocation ptr_A; +cutlass::DeviceAllocation ptr_B; +cutlass::DeviceAllocation ptr_SFA; +cutlass::DeviceAllocation ptr_SFB; +cutlass::DeviceAllocation ptr_C; +cutlass::DeviceAllocation ptr_D; +cutlass::DeviceAllocation ptr_SFD; +cutlass::DeviceAllocation ptr_ref_D; + +cutlass::DeviceAllocation stride_A; +cutlass::DeviceAllocation stride_B; +cutlass::DeviceAllocation layout_SFA; +cutlass::DeviceAllocation layout_SFB; +cutlass::DeviceAllocation stride_C; +cutlass::DeviceAllocation stride_D; + +// Note, this is an array of pointers to alpha and beta scaling values per group +cutlass::DeviceAllocation alpha_device; +cutlass::DeviceAllocation beta_device; +cutlass::DeviceAllocation block_alpha; +cutlass::DeviceAllocation block_beta; +// A matrix wide constant value to scale the output matrix +// Avoids generating small FP4 values. +// NormConst is a single device-side constant value, its not per-batch or per-group +cutlass::DeviceAllocation norm_constant_device; + +#endif // defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + +template +auto make_iterator(T* ptr) { + return cute::recast_ptr(ptr); +} + +///////////////////////////////////////////////////////////////////////////////////////////////// +/// Testbed utility types +///////////////////////////////////////////////////////////////////////////////////////////////// + +using RasterOrderOptions = cutlass::gemm::kernel::detail::RasterOrderOptions; +// Command line options parsing +struct Options { + + bool help = false; + bool verification = true; + bool use_pdl = false; + + float alpha = FLT_MAX; + float beta = FLT_MAX; + float norm_constant = 1.0; + int iterations = 10; + int m = 1024, n = 2048, k = 512, groups = 10; + dim3 cluster_shape = dim3(2,1,1); + dim3 cluster_shape_fallback = dim3(2,1,1); + RasterOrderOptions raster_order = RasterOrderOptions::AlongN; + char raster_char = 'N'; + int swizzle = 1; + int max_sm_count = INT_MAX; + std::string benchmark_path; + std::vector problem_sizes_host; + int const tma_alignment_bits = 128; + int const alignment = tma_alignment_bits / cutlass::sizeof_bits::value; + + // Parses the command line + void parse(int argc, char const **args) { + cutlass::CommandLine cmd(argc, args); + + if (cmd.check_cmd_line_flag("help")) { + help = true; + return; + } + if (cmd.check_cmd_line_flag("no_verif")) { + verification = false; + } + if (cmd.check_cmd_line_flag("use_pdl")) { + use_pdl = true; + } + + cmd.get_cmd_line_argument("m", m); + cmd.get_cmd_line_argument("n", n); + cmd.get_cmd_line_argument("k", k); + cmd.get_cmd_line_argument("groups", groups); + cmd.get_cmd_line_argument("alpha", alpha, FLT_MAX); + cmd.get_cmd_line_argument("beta", beta, FLT_MAX); + cmd.get_cmd_line_argument("norm_constant", norm_constant, float(1.0)); + cmd.get_cmd_line_argument("iterations", iterations); + cmd.get_cmd_line_argument("benchmark", benchmark_path); + cmd.get_cmd_line_argument("cluster_m", cluster_shape.x); + cmd.get_cmd_line_argument("cluster_n", cluster_shape.y); + cmd.get_cmd_line_argument("cluster_fallback_m", cluster_shape_fallback.x); + cmd.get_cmd_line_argument("cluster_fallback_n", cluster_shape_fallback.y); + cmd.get_cmd_line_argument("max_sm_count", max_sm_count, INT_MAX); + + // Decide how to initialize the problems + if (!benchmark_path.empty()) { + if (!benchmark_problems()) { + problem_sizes_host.clear(); + return; + } + } + else { + randomize_problems(cmd); + } + + cmd.get_cmd_line_argument("raster", raster_char); + + if (raster_char == 'N' || raster_char == 'n') { + raster_order = RasterOrderOptions::AlongN; + } + else if (raster_char == 'M' || raster_char == 'm') { + raster_order = RasterOrderOptions::AlongM; + } + cmd.get_cmd_line_argument("swizzle", swizzle, 1); + } + + void randomize_problems(cutlass::CommandLine &cmd) { + int cmd_line_m = -1, cmd_line_n = -1, cmd_line_k = -1; + cmd.get_cmd_line_argument("m", cmd_line_m); + cmd.get_cmd_line_argument("n", cmd_line_n); + cmd.get_cmd_line_argument("k", cmd_line_k); + + problem_sizes_host.reserve(groups); + + for (int i = groups; i > 0; i--) { + int m = cmd_line_m; + int n = cmd_line_n; + int k = cmd_line_k; + if (m < 0) { + m = alignment * ((rand() % 64)); + } + if (n < 0) { + n = alignment * ((rand() % 64)); + } + if (k < 0) { + k = alignment * ((rand() % 64)); + } + problem_sizes_host.push_back({m, n, k}); + } + } + + /// Load a benchmark + bool benchmark_problems() { + std::ifstream file(benchmark_path); + if (!file.good()) { + return false; + } + + while (file.good()) { + + int idx = -1; + std::string extent_str; + + file >> idx >> extent_str; + + if (idx < 0 || extent_str.empty()) { + break; + } + + cutlass::gemm::GemmCoord extent; + std::vector tokens; + + cutlass::CommandLine::tokenize(tokens, extent_str, 'x'); + + for (int i = 0; i < int(tokens.size()); ++i) { + extent.at(i) = std::atoi(tokens.at(i).c_str()); + } + problem_sizes_host.push_back({extent.m(), extent.n(), extent.k()}); + } + groups = static_cast(problem_sizes_host.size()); + + return true; + } + + /// Prints the usage statement. + std::ostream & print_usage(std::ostream &out) const { + + out << "75_blackwell_grouped_gemm_block_scaled\n\n" + << " Blackwell Block Scaled Narrow Precision Grouped GEMM using a Warp Specialized kernel.\n\n" + << "Options:\n\n" + << " --help If specified, displays this usage statement\n\n" + << " --m= Sets the M extent of the GEMM for all groups\n" + << " --n= Sets the N extent of the GEMM for all groups\n" + << " --k= Sets the K extent of the GEMM for all groups\n" + << " --groups= Sets the number of individual GEMM problems for Grouped GEMM\n" + << " --alpha= Epilogue scalar alpha\n" + << " --beta= Epilogue scalar beta\n" + << " --norm_constant= Epilogue scalar normalization constant for the output matrix\n\n" + << " --cluster_m= and --cluster_n= Sets the X,Y dims of the preferred cluster shape\n" + << " --cluster_fallback_m= and --cluster_fallback_n= Sets the X,Y dims of the fallback cluster shape\n\n" + << " --raster= Cluster rasterization direction (N for along N, M for along M)\n" + << " --swizzle= Cluster swizzle (swizzle up to 8 and with the nearest multiple of 2)\n\n" + << " --iterations= Number of profiling iterations to perform\n\n" + << " --benchmark= Executes a benchmark problem size\n" + << " --max_sm_count= Run kernels using only these number of SMs\n" + << " --no_verif Do not run (host-side) verification kernels\n" + << " --use_pdl Launch kernel with PDL (Programmatic Dependent Launch) enabled\n"; + + out + << "\n\nExamples:\n\n" + << "$ " << "75_blackwell_grouped_gemm_block_scaled" << " --m=1024 --n=512 --k=1024 --groups=10 --alpha=2 --beta=0.707 \n\n"; + + return out; + } + + /// Compute performance in GFLOP/s + double gflops(double runtime_s, std::vector problem_sizes_host) const + { + // Number of real-valued multiply-adds + uint64_t fmas = uint64_t(); + + for (auto const & problem : problem_sizes_host) { + fmas += static_cast(get<0>(problem)) * + static_cast(get<1>(problem)) * + static_cast(get<2>(problem)); + } + // Two flops per multiply-add + uint64_t flop = uint64_t(2) * uint64_t(fmas); + double gflop = double(flop) / double(1.0e9); + return gflop / runtime_s; + } +}; + +/// Result structure +struct Result +{ + double avg_runtime_ms = 0.0; + double gflops = 0.0; + cutlass::Status status = cutlass::Status::kSuccess; + cudaError_t error = cudaSuccess; + bool passed = false; +}; + +#if defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + +///////////////////////////////////////////////////////////////////////////////////////////////// +/// GEMM setup and evaluation +///////////////////////////////////////////////////////////////////////////////////////////////// + +/// Helper to initialize a block of device data +template +bool initialize_block( + cutlass::TensorView view, + uint64_t seed) { + + double scope_max, scope_min; + constexpr int bits_input = cutlass::sizeof_bits::value; + + if constexpr (bits_input == 1) { + scope_max = 2; + scope_min = 0; + } + else if constexpr (bits_input <= 6) { + scope_max = 2; + scope_min = -2; + } + else if constexpr (bits_input <= 8) { + if constexpr (cute::is_same_v) { + scope_max = 4; + scope_min = 1; + } + else { + scope_max = 1; + scope_min = -1; + } + } + else{ + scope_max = 4; + scope_min = -4; + } + cutlass::reference::host::TensorFillRandomUniform( + view, seed, scope_max, scope_min, 0); + + return true; +} + +/// Allocates device-side data +void allocate(const Options &options) { + for (int32_t i = 0; i < options.groups; ++i) { + auto problem = options.problem_sizes_host.at(i); + auto M = get<0>(problem); + auto N = get<1>(problem); + auto K = get<2>(problem); + + auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, {M, K, 1}); + auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, {N, K, 1}); + auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, {M, N, 1}); + auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, {M, N, 1}); + + auto layout_A = make_layout(make_shape(M, K, 1), stride_A); + auto layout_B = make_layout(make_shape(N, K, 1), stride_B); + auto layout_C = make_layout(make_shape(M, N, 1), stride_C); + auto layout_D = make_layout(make_shape(M, N, 1), stride_D); + auto layout_SFA = Sm1xxBlkScaledConfig::tile_atom_to_shape_SFA(cute::make_shape(M, N, K, 1)); + auto layout_SFB = Sm1xxBlkScaledConfig::tile_atom_to_shape_SFB(cute::make_shape(M, N, K, 1)); + auto layout_SFD = Sm1xxBlockScaledOutputConfig::tile_atom_to_shape_SFD(cute::make_shape(M, N, K, 1)); + + stride_A_host.push_back(stride_A); + stride_B_host.push_back(stride_B); + layout_SFA_host.push_back(layout_SFA); + layout_SFB_host.push_back(layout_SFB); + stride_C_host.push_back(stride_C); + stride_D_host.push_back(stride_D); + + block_A.push_back(HostTensorA(cutlass::make_Coord(size(layout_A)))); + block_B.push_back(HostTensorB(cutlass::make_Coord(size(layout_B)))); + block_SFA.push_back(HostTensorSF(cutlass::make_Coord(size(filter_zeros(layout_SFA))))); + block_SFB.push_back(HostTensorSF(cutlass::make_Coord(size(filter_zeros(layout_SFB))))); + block_C.push_back(HostTensorC(cutlass::make_Coord(size(layout_C)))); + block_D.push_back(HostTensorD(cutlass::make_Coord(size(layout_D)))); + block_SFD.push_back(HostTensorSF(cutlass::make_Coord(size(filter_zeros(layout_SFD))))); + block_ref_D.push_back(HostTensorD(cutlass::make_Coord(size(layout_D)))); + } + block_alpha.reset(options.groups); + block_beta.reset(options.groups); +} + +/// Initialize operands to be used in the GEMM and reference GEMM +void initialize(const Options &options) { + uint64_t seed = 2020; + problem_sizes.reset(options.groups); + problem_sizes.copy_from_host(options.problem_sizes_host.data()); + + // + // Assign pointers + // + + std::vector ptr_A_host(options.groups); + std::vector ptr_B_host(options.groups); + std::vector ptr_SFA_host(options.groups); + std::vector ptr_SFB_host(options.groups); + std::vector ptr_C_host(options.groups); + std::vector ptr_D_host(options.groups); + std::vector ptr_SFD_host(options.groups); + std::vector ptr_alpha_host(options.groups); + std::vector ptr_beta_host(options.groups); + + for (int32_t i = 0; i < options.groups; ++i) { + + initialize_block(block_A.at(i).host_view(), seed + 2021); + initialize_block(block_B.at(i).host_view(), seed + 2022); + initialize_block(block_C.at(i).host_view(), seed + 2023); + initialize_block(block_SFA.at(i).host_view(), seed + 2024); + initialize_block(block_SFB.at(i).host_view(), seed + 2025); + + block_A.at(i).sync_device(); + block_B.at(i).sync_device(); + block_C.at(i).sync_device(); + block_SFA.at(i).sync_device(); + block_SFB.at(i).sync_device(); + + ptr_A_host.at(i) = block_A.at(i).device_data(); + ptr_B_host.at(i) = block_B.at(i).device_data(); + ptr_SFA_host.at(i) = block_SFA.at(i).device_data(); + ptr_SFB_host.at(i) = block_SFB.at(i).device_data(); + ptr_C_host.at(i) = block_C.at(i).device_data(); + ptr_D_host.at(i) = block_D.at(i).device_data(); + ptr_SFD_host.at(i) = block_SFD.at(i).device_data(); + + alpha_host.push_back((options.alpha == FLT_MAX) ? static_cast((rand() % 5) + 1) : options.alpha); + beta_host.push_back((options.beta == FLT_MAX) ? static_cast(rand() % 5) : options.beta); + ptr_alpha_host.at(i) = block_alpha.get() + i; + ptr_beta_host.at(i) = block_beta.get() + i; + } + + ptr_A.reset(options.groups); + ptr_A.copy_from_host(ptr_A_host.data()); + + ptr_B.reset(options.groups); + ptr_B.copy_from_host(ptr_B_host.data()); + + ptr_SFA.reset(options.groups); + ptr_SFA.copy_from_host(ptr_SFA_host.data()); + + ptr_SFB.reset(options.groups); + ptr_SFB.copy_from_host(ptr_SFB_host.data()); + + ptr_C.reset(options.groups); + ptr_C.copy_from_host(ptr_C_host.data()); + + ptr_D.reset(options.groups); + ptr_D.copy_from_host(ptr_D_host.data()); + + ptr_SFD.reset(options.groups); + ptr_SFD.copy_from_host(ptr_SFD_host.data()); + + stride_A.reset(options.groups); + stride_A.copy_from_host(stride_A_host.data()); + + stride_B.reset(options.groups); + stride_B.copy_from_host(stride_B_host.data()); + + layout_SFA.reset(options.groups); + layout_SFA.copy_from_host(layout_SFA_host.data()); + + layout_SFB.reset(options.groups); + layout_SFB.copy_from_host(layout_SFB_host.data()); + + stride_C.reset(options.groups); + stride_C.copy_from_host(stride_C_host.data()); + + stride_D.reset(options.groups); + stride_D.copy_from_host(stride_D_host.data()); + + alpha_device.reset(options.groups); + alpha_device.copy_from_host(ptr_alpha_host.data()); + beta_device.reset(options.groups); + beta_device.copy_from_host(ptr_beta_host.data()); + + block_alpha.copy_from_host(alpha_host.data()); + block_beta.copy_from_host(beta_host.data()); + + norm_constant_device.reset(1); + norm_constant_device.copy_from_host(&options.norm_constant); +} + +/// Populates a Gemm::Arguments structure from the given commandline options +template +typename Gemm::Arguments args_from_options(Options &options, bool host_problem_shapes_available = true) +{ + cutlass::KernelHardwareInfo hw_info; + // Change device_id to another value if you are running on a machine with multiple GPUs and wish + // to use a GPU other than that with device ID 0. + hw_info.device_id = 0; + hw_info.sm_count = min(cutlass::KernelHardwareInfo::query_device_multiprocessor_count(hw_info.device_id), options.max_sm_count); + + if (!is_static_v) { + if (size<0>(typename Gemm::GemmKernel::CollectiveMainloop::AtomThrShapeMNK{}) == 2 && + (options.cluster_shape.x < 2 || options.cluster_shape_fallback.x < 2)) { + std::cout << "Error: MMA2SMConfig kernel config needs cluster_dim.x >= 2" << std::endl; + } + hw_info.cluster_shape = options.cluster_shape; + hw_info.cluster_shape_fallback = options.cluster_shape_fallback; + } + + typename Gemm::Arguments arguments; + decltype(arguments.epilogue.thread) fusion_args; + fusion_args.alpha_ptr = nullptr; + fusion_args.beta_ptr = nullptr; + + // If alpha/beta are provided (via cmd line args) and are scalar, i.e., same alpha/beta applies to all batches. + // If pointers to alpha/beta are provided, i.e., alpha/beta can differ between batches/groups. + if (options.alpha != FLT_MAX){ + // Single alpha for all groups + fusion_args.alpha = options.alpha; + fusion_args.alpha_ptr_array = nullptr; + fusion_args.dAlpha = {_0{}, _0{}, 0}; + } + else { + fusion_args.alpha = 0; + fusion_args.alpha_ptr_array = alpha_device.get(); + // Only one alpha per each group + fusion_args.dAlpha = {_0{}, _0{}, 1}; + } + if (options.beta != FLT_MAX) { + // Single beta for all groups + fusion_args.beta = options.beta; + fusion_args.beta_ptr_array = nullptr; + fusion_args.dBeta = {_0{}, _0{}, 0}; + } + else { + fusion_args.beta = 0; + fusion_args.beta_ptr_array = beta_device.get(); + // Only one beta per each group + fusion_args.dBeta = {_0{}, _0{}, 1}; + } + // Output Block SF + // fusion_args.block_scale_factor_ptr = ptr_SFD.get(); // Enable for SF Output + // fusion_args.norm_constant_ptr = norm_constant_device.get(); // Enable for SF Output + + typename Gemm::GemmKernel::TileSchedulerArguments scheduler; + scheduler.raster_order = options.raster_order; + scheduler.max_swizzle_size = options.swizzle; + + if (host_problem_shapes_available) { + arguments = typename Gemm::Arguments { + cutlass::gemm::GemmUniversalMode::kGrouped, + {options.groups, problem_sizes.get(), options.problem_sizes_host.data()}, + {ptr_A.get(), stride_A.get(), ptr_B.get(), stride_B.get(), + ptr_SFA.get(), layout_SFA.get(), ptr_SFB.get(), layout_SFB.get()}, + {fusion_args, ptr_C.get(), stride_C.get(), ptr_D.get(), stride_D.get()}, + hw_info, scheduler + }; + } + else { + arguments = typename Gemm::Arguments { + cutlass::gemm::GemmUniversalMode::kGrouped, + {options.groups, problem_sizes.get(), nullptr}, + {ptr_A.get(), stride_A.get(), ptr_B.get(), stride_B.get(), + ptr_SFA.get(), layout_SFA.get(), ptr_SFB.get(), layout_SFB.get()}, + {fusion_args, ptr_C.get(), stride_C.get(), ptr_D.get(), stride_D.get()}, + hw_info, scheduler + }; + } + + return arguments; +} + +bool verify(const Options &options) { + using namespace cute; + bool passed = true; + for (int32_t i = 0; i < options.groups; ++i) { + auto problem = options.problem_sizes_host.at(i); + auto M = get<0>(problem); + auto N = get<1>(problem); + auto K = get<2>(problem); + + auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, {M, K, 1}); + auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, {N, K, 1}); + auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, {M, N, 1}); + auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, {M, N, 1}); + auto layout_A = make_layout(make_shape(M, K, 1), stride_A); + auto layout_B = make_layout(make_shape(N, K, 1), stride_B); + auto layout_C = make_layout(make_shape(M, N, 1), stride_C); + auto layout_D = make_layout(make_shape(M, N, 1), stride_D); + auto layout_SFA = Sm1xxBlkScaledConfig::tile_atom_to_shape_SFA(cute::make_shape(M, N, K, 1)); + auto layout_SFB = Sm1xxBlkScaledConfig::tile_atom_to_shape_SFB(cute::make_shape(M, N, K, 1)); + auto layout_SFD = Sm1xxBlockScaledOutputConfig::tile_atom_to_shape_SFD(cute::make_shape(M, N, K, 1)); + + // Create the arguments for host reference implementation + Tensor tensor_A = make_tensor(make_iterator(block_A.at(i).host_data()), layout_A); + Tensor tensor_SFA = make_tensor(block_SFA.at(i).host_data(), layout_SFA); + Tensor tensor_B = make_tensor(make_iterator(block_B.at(i).host_data()), layout_B); + Tensor tensor_SFB = make_tensor(block_SFB.at(i).host_data(), layout_SFB); + cutlass::reference::host::GettBlockScalingMainloopParams + mainloop_params{tensor_A, tensor_SFA, tensor_B, tensor_SFB}; + + auto tensor_C = cute::make_tensor(make_iterator(block_C.at(i).host_data()), layout_C); + auto tensor_ref_D = cute::make_tensor(make_iterator(block_ref_D.at(i).host_data()), layout_D); + + cutlass::reference::host::GettEpilogueParams< + float, float, + ElementAccumulator, ElementAccumulator, + decltype(tensor_C), decltype(tensor_ref_D) + > epilogue_params{}; + + epilogue_params.C = tensor_C; + epilogue_params.D = tensor_ref_D; + epilogue_params.alpha = alpha_host.at(i); + epilogue_params.beta = beta_host.at(i); + + cutlass::reference::host::Gemm3x(mainloop_params, epilogue_params); + + block_D.at(i).sync_host(); + // Check if output from CUTLASS kernel and reference kernel are equal or not + passed &= cutlass::reference::host::TensorEquals(block_ref_D.at(i).host_view(), block_D.at(i).host_view()); + } + return passed; +} + +/// Execute a given example GEMM computation +template +int run(Options &options, bool host_problem_shapes_available = true) +{ + std::cout << " Problem Sizes, Alpha, Beta " << std::endl; + for (int32_t i = 0; i < options.groups; ++i) { + std::cout << " " << options.problem_sizes_host.at(i); + std::cout << ", " << alpha_host.at(i) << ", " << beta_host.at(i) << std::endl; + } + std::cout << " Groups : " << options.groups << std::endl; + + std::cout << " Cluster Shape : " << options.cluster_shape.x << "x" << options.cluster_shape.y << std::endl; + std::cout << " Cluster Fallback Shape : " << options.cluster_shape_fallback.x << "x" << options.cluster_shape_fallback.y << std::endl; + + std::cout << " Raster Order : Along-" << options.raster_char << std::endl; + std::cout << " Max Swizzle Size : " << options.swizzle << std::endl; + + // Instantiate CUTLASS kernel depending on templates + Gemm gemm; + + // Create a structure of gemm kernel arguments suitable for invoking an instance of Gemm + auto arguments = args_from_options(options, host_problem_shapes_available); + + // Using the arguments, query for extra workspace required for matrix multiplication computation + size_t workspace_size = Gemm::get_workspace_size(arguments); + + // Allocate workspace memory + cutlass::device_memory::allocation workspace(workspace_size); + + // Check if the problem size is supported or not + CUTLASS_CHECK(gemm.can_implement(arguments)); + + // Initialize CUTLASS kernel with arguments and workspace pointer + CUTLASS_CHECK(gemm.initialize(arguments, workspace.get())); + + // Correctness / Warmup iteration + CUTLASS_CHECK(gemm.run(/* stream = */ nullptr, /* cuda_adapter = */ nullptr, /* launch_with_pdl = */ options.use_pdl)); + + cudaDeviceSynchronize(); + + // Check if output from CUTLASS kernel and reference kernel are equal or not + Result result; + if (options.verification) { + std::cout << " Host-side verification is now running - may be very slow for large cases." << std::endl; + result.passed = verify(options); + std::cout << " Disposition: " << (result.passed ? "Passed" : "Failed") << std::endl; + if (!result.passed) { + exit(-1); + } + } + else { + std::cout << " Verification is turned off for this run." << std::endl; + } + + // Run profiling loop + if (options.iterations > 0) + { + GpuTimer timer; + timer.start(); + for (int iter = 0; iter < options.iterations; ++iter) { + CUTLASS_CHECK(gemm.initialize(arguments, workspace.get())); + CUTLASS_CHECK(gemm.run(/* stream = */ nullptr, /* cuda_adapter = */ nullptr, /* launch_with_pdl = */ options.use_pdl)); + } + timer.stop(); + + // Compute average setup and runtime and GFLOPs. + float elapsed_ms = timer.elapsed_millis(); + result.avg_runtime_ms = double(elapsed_ms) / double(options.iterations); + result.gflops = options.gflops(result.avg_runtime_ms / 1000.0, options.problem_sizes_host); + + std::cout << " Avg runtime : " << result.avg_runtime_ms << " ms" << std::endl; + std::cout << " TFLOPS : " << result.gflops / 1000.0 << std::endl; + } + + return 0; +} + +#endif // defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +int main(int argc, char const **args) { + + // CUTLASS must be compiled with CUDA 12.8 Toolkit to run this example + if (__CUDACC_VER_MAJOR__ < 12 || + ((__CUDACC_VER_MAJOR__ == 12 && __CUDACC_VER_MINOR__ < 8) + ) + ) { + std::cerr << "This example requires CUDA 12.8 or newer.\n"; + // Returning zero so this test passes on older Toolkits. Its actions are no-op. + return 0; + } + + cudaDeviceProp props; + int current_device_id; + CUDA_CHECK(cudaGetDevice(¤t_device_id)); + CUDA_CHECK(cudaGetDeviceProperties(&props, current_device_id)); + cudaError_t error = cudaGetDeviceProperties(&props, 0); + if (props.major != 10 || (props.minor != 0 && props.minor != 1 && props.minor != 3)) { + std::cerr << "This example requires a GPU with compute capability 100a|f, 101a|f, or 103a|f)." << std::endl; + return 0; + } + + // + // Parse options + // + + Options options; + + options.parse(argc, args); + + if (options.help) { + options.print_usage(std::cout) << std::endl; + return 0; + } + +#if defined(CUTLASS_ARCH_MMA_SM100_SUPPORTED) + allocate(options); + initialize(options); + + // + // Evaluate CUTLASS kernels + // + + std::cout << "Running kernel with 1SM MMA config:" << std::endl; + run(options, false /*host_problem_shapes_available*/); + std::cout << "Running kernel with 2SM MMA config:" << std::endl; + run(options, false /*host_problem_shapes_available*/); +#endif + + return 0; +} + +///////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/verification/evidence/local-snapshots/cutlass-audit.8aj07j/repo/include/cutlass/gemm/dispatch_policy.hpp b/verification/evidence/local-snapshots/cutlass-audit.8aj07j/repo/include/cutlass/gemm/dispatch_policy.hpp new file mode 100644 index 000000000..9cd9d2569 --- /dev/null +++ b/verification/evidence/local-snapshots/cutlass-audit.8aj07j/repo/include/cutlass/gemm/dispatch_policy.hpp @@ -0,0 +1,1590 @@ +/*************************************************************************************************** + * Copyright (c) 2023 - 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ +#pragma once + +#include "cutlass/arch/arch.h" +#include "cutlass/gemm/gemm.h" + +#include "cute/layout.hpp" +#include "cute/numeric/integral_constant.hpp" // cute::false_type +#include "cute/atom/copy_traits_sm100.hpp" +#include "cutlass/detail/collective/sm103_kernel_type.hpp" +////////////////////////////////////////////////////////////////////////////// + +namespace cutlass::detail { + +template class U> +struct is_kernel_tag_of : cute::false_type {}; + +template