Hello,
I was trying to get the xmg circuit from the verilog file, I noticed that the number of inverters are more than the number I got from the xmgcost command, I tried this with the EPFL benchmarks. I also tried to use xmginv to optimize the number of inverters, but I got the same verilog file in the output as before the inverter optimization.
without the xmginv
read_aiger $i; ps -a;
lut_mapping;
convert --aig_to_mig; ps -m;
convert --mig_to_xmg; ps -x;
write_verilog -x $destination_path/${strarr[5]}.v;
with the xmginv
read_aiger $i; ps -a;
lut_mapping;
convert --aig_to_mig; ps -m;
convert --mig_to_xmg; ps -x;
xmginv
write_verilog -x $destination_path/${strarr[5]}.v;
Hello,
I was trying to get the xmg circuit from the verilog file, I noticed that the number of inverters are more than the number I got from the xmgcost command, I tried this with the EPFL benchmarks. I also tried to use xmginv to optimize the number of inverters, but I got the same verilog file in the output as before the inverter optimization.
without the xmginv
with the xmginv