diff --git a/corescore.core b/corescore.core index 0b0a4b6..a6310da 100644 --- a/corescore.core +++ b/corescore.core @@ -8,7 +8,7 @@ filesets: - rtl/wb2axis.v - rtl/base.v file_type: verilogSource - depend: ["=::serv:1.0.2", "=::serving:1.0.2", verilog-axis] + depend: [serv, serving, verilog-axis] emitter_serv: files: @@ -17,7 +17,7 @@ filesets: - rtl/emitter_mux.v - rtl/emitter.v file_type: verilogSource - depend: ["=::servant:1.0.2-r1"] + depend: [servant] emitter_uart: files: [rtl/emitter_uart.v : {file_type: verilogSource}] @@ -156,6 +156,11 @@ filesets: - data/vivado_waive.tcl: { file_type: tclSource } - data/genesys2.xdc: { file_type: xdc } + gmm7550: + files: + - rtl/corescore_gmm7550.v: { file_type: verilogSource } + - data/gmm7550.ccf: { file_type: CCF } + go_board: files: - rtl/corescore_go_board.v: { file_type: verilogSource } @@ -605,6 +610,20 @@ targets: vivado: { part: xc7k325tffg900-2 } toplevel: corescore_genesys2 + gmm7550: + description: CologneChip GateMate FPGA Module + default_tool: gatemate + filesets: [base, emitter_serv, gmm7550] + toplevel: corescore_gmm7550 + generate: [corescorecore: {count: 57}] + flow: gatemate + flow_options: + device: CCGM1A1 + nextpnr_options: + - --placer-heap-cell-placement-timeout 0 + - --placer-heap-alpha 0.05 + - --placer-heap-beta 0.4 + go_board: default_tool: icestorm description: Nandland Go Board + Verilog emitter diff --git a/data/gmm7550.ccf b/data/gmm7550.ccf new file mode 100644 index 0000000..8dcdfa9 --- /dev/null +++ b/data/gmm7550.ccf @@ -0,0 +1,65 @@ +## GMM-7550 pins + +# This file is a part of the GMM-7550 VHDL Examples +# +# +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2023 Anton Kuzmin + +# Master clock input (100 MHz) +Pin_in "ser_clk" Loc = "SER_CLK"; + +### SPI + +Pin_inout "CFG_SPI_nCS" Loc = "IO_WA_A8"; +Pin_inout "CFG_SPI_CLK" Loc = "IO_WA_B8"; +Pin_inout "CFG_SPI_IO0" Loc = "IO_WA_B7"; # MOSI +Pin_inout "CFG_SPI_IO1" Loc = "IO_WA_A7"; # MISO +# Pin_inout "CFG_SPI_IO2" Loc = "IO_WA_B6"; # May be reused on the HAT for UART +# Pin_inout "CFG_SPI_IO3" Loc = "IO_WA_A6"; # May be reused on the HAT for UART +## HAT Adapter board + +# This file is a part of the GMM-7550 VHDL Examples +# +# +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2023 Anton Kuzmin + +# D4 CFG_FAILED (Red) +Pin_out "led_red_n" Loc = "IO_WA_A2"; + +# D2 CFG_DONE (Green) +Pin_out "led_green" Loc = "IO_WA_B2"; + +### UART + +Pin_out "uart_tx" Loc = "IO_WA_A6"; # SPI D3, GPIO pin 10 +Pin_in "uart_rx" Loc = "IO_WA_B6"; # SPI D2, GPIO pin 8 + +### Pmod J10 + +Pin_out "J10_EN" Loc = "IO_SA_A7"; + +Pin_inout "J10_IO[0]" Loc = "IO_SA_A0"; +Pin_inout "J10_IO[1]" Loc = "IO_SA_A1"; +Pin_inout "J10_IO[2]" Loc = "IO_SA_A2"; +Pin_inout "J10_IO[3]" Loc = "IO_SA_A3"; +Pin_inout "J10_IO[4]" Loc = "IO_SA_B0"; +Pin_inout "J10_IO[5]" Loc = "IO_SA_B1"; +Pin_inout "J10_IO[6]" Loc = "IO_SA_B2"; +Pin_inout "J10_IO[7]" Loc = "IO_SA_B3"; + +### Pmod J9 + +Pin_out "J9_EN" Loc = "IO_SB_B3"; + +Pin_inout "J9_IO[0]" Loc = "IO_SB_A6"; # CLK_2 +Pin_inout "J9_IO[1]" Loc = "IO_SB_A7"; # CLK_1 +Pin_inout "J9_IO[2]" Loc = "IO_SB_A8"; # CLK_0 +Pin_inout "J9_IO[3]" Loc = "IO_SB_A5"; # CLK_3 +Pin_inout "J9_IO[4]" Loc = "IO_SB_B6"; +Pin_inout "J9_IO[5]" Loc = "IO_SB_B7"; +Pin_inout "J9_IO[6]" Loc = "IO_SB_B8"; +Pin_inout "J9_IO[7]" Loc = "IO_SB_B5"; diff --git a/rtl/corescore_gmm7550.v b/rtl/corescore_gmm7550.v new file mode 100644 index 0000000..47bd9cd --- /dev/null +++ b/rtl/corescore_gmm7550.v @@ -0,0 +1,87 @@ +`timescale 1ns / 1ps + +module corescore_gmm7550( + input wire ser_clk, + output wire led_green, + output wire led_red_n, + output wire uart_tx); + + parameter memfile_emitter = "emitter.hex"; + + wire [7:0] tdata; + wire tlast; + wire tvalid; + wire tready; + + wire clk270, clk180, clk90, clk0, usr_ref_out; + wire usr_pll_lock_stdy, usr_pll_lock; + + wire usr_rstn; + reg [4:0] rst; + + wire sys_clk; + wire sys_rst; + wire sys_rst_n; + wire q; + + assign led_red_n = 1'b1; + assign led_green = q; + assign uart_tx = q; + + CC_PLL #( + .REF_CLK("100.0"), // reference input in MHz + .OUT_CLK("16.0"), // pll output frequency in MHz + .PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED + .LOCK_REQ(1), // Lock status required before PLL output enable + .LOW_JITTER(1), // 0: disable, 1: enable low jitter mode + .CI_FILTER_CONST(2), // optional CI filter constant + .CP_FILTER_CONST(4) // optional CP filter constant + ) pll_inst ( + .CLK_REF(ser_clk), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0), + .USR_LOCKED_STDY_RST(1'b0), .USR_PLL_LOCKED_STDY(usr_pll_lock_stdy), .USR_PLL_LOCKED(usr_pll_lock), + .CLK270(clk270), .CLK180(clk180), .CLK90(clk90), .CLK0(clk0), .CLK_REF_OUT(usr_ref_out) + ); + + assign sys_clk = clk0; + + CC_USR_RSTN usr_rst_inst + (.USR_RSTN(usr_rstn)); + + always @(posedge sys_clk or negedge usr_rstn) + begin + if (!usr_rstn) begin + rst <= 5'b01111; + end else begin + if (usr_pll_lock) begin + if (!rst[4]) begin + rst <= rst - 1; + end else begin + rst <= rst; + end + end else begin + rst <= 5'b01111; + end + end + end + + assign sys_rst = !rst[4]; + assign sys_rst_n = rst[4]; + + corescorecore corescorecore + (.i_clk (sys_clk), + .i_rst (sys_rst), + .o_tdata (tdata), + .o_tlast (tlast), + .o_tvalid (tvalid), + .i_tready (tready)); + + emitter #(.memfile (memfile_emitter)) emitter + (.i_clk (sys_clk), + .i_rst (sys_rst), + .i_tdata (tdata), + .i_tlast (tlast), + .i_tvalid (tvalid), + .o_tready (tready), + .o_uart_tx (q)); + +endmodule