Vivado Implementation Issues

[ANILATHOMAS519]

Hi @michaelgmcintyre ,
While trying to implement this project in Vivado, we found some syntax errors and some ports which were wrongly declared, like in file:

• https://github.com/opencomputeproject/Project-Zipline/blob/master/rtl/cr_prefix/cr_prefix_fe_ctlr.v

Can you please clarify whether these are bugs or any mistakes that we are overlooking from our side?

[michaelgmcintyre]

Hi ANILATHOMAS519,

Please provide specific details on both syntax errors and wrongly declared ports. Project was developed using synopsys tool flow. See zipline.setup for specific version.

Thanks,
Michael

[ANILATHOMAS519]

1. Project-Zipline/rtl/cr_prefix_attach/cr_prefix_fe _ctlr.v

   • Line 32 : "usr_ib_rd","fe_ctlr_cmd_tlv","fe_ctlr_cmd_tlv_valid"=> These ports are declared in Module Declaration, but has not been mentioned whether they are input or output.

   • Line 36 : "usr_ib_empty", "usr_ib_aempty", "usr_ib_tlv" => Have these three variables used in this file?

   • Line 53-55 : " input logic [63:0] ibc_char_in; }
     input logic [63:0] ibc_char_in_valid; }
     input logic [7:0] ibc_char_vbytes; }
     output fe_ready; }
     output fe_eodb; } => Are these five variables input ,output or just logic ? (since they have not mentioned inside module declaration as ports).

   • Line 281 : Is there an "end" missing in DATA_BLK corresponding to the "begin"?

2. Project-Zipline/rtl/cr_prefix_attach/cr_prefix_attach_ctlr.v

   • Line 107 : assign pfd_mem_addr = {pac_prefix_num,pac_pfcounter};
     => Is it "pac_pfcounter" or "pac_pfdcounter"?(Because in Line 97 "pac_pfdcounter" is declared.)

   • Line 108 : assign phd_mem_addr = {pac_prefix_num,pac_hfcounter};
     => Is it "pac_hfcounter" or "pac_phdcounter"?(Because in Line 98 "pac_phdcounter" is declared.)

   • Line 110 : assign pac_phdcounter_max = (pac_phdcounter == N_PHD_WORDS); => Is it "N_PHD_WORDS" or "CR_PREFIX_N_PHD_WORDS"? (Since N_PHD_WORDS are not declared anywhere. In the file "Project-Zipline/rtl/common/include/cr_global_params.vh" CR_PREFIX_N_PHD_WORDS has been declared in line 118)

   • Line 111 : assign pac_pfdcounter_max = (pac_pfdcounter == N_PFD_WORDS); => Is it "N_PFD_WORDS" or "CR_PREFIX_N_PFD_WORDS"? (Since N_PFD_WORDS are not declared anywhere.In the file "Project-Zipline/rtl/common/include/cr_global_params.vh" CR_PREFIX_N_PFD_WORDS has been declared in line 119.)

3. Project-Zipline/rtl/common/cr_mux_32.v

  *Line 14        :       wire   0  = t0 | t1;
                                                                  =>Is it "0" or "o"?

[ANILATHOMAS519]

Hi @michaelgmcintyre ,

   As you mentioned above , I have given the details of syntax errors and their respective location in the files . Can you please check it whether these are errors or not?   We are using Vivado 18.3 tool for this project.

Syntax errors noticed and it's file location:

1. Project-Zipline/rtl/cr_prefix_attach/cr_prefix_fe _ctlr.v

   • Line 32 : "usr_ib_rd","fe_ctlr_cmd_tlv","fe_ctlr_cmd_tlv_valid"=> These ports are declared in Module Declaration,but has not been mentioned whether they are input or output.

   • Line 36 : "usr_ib_empty", "usr_ib_aempty", "usr_ib_tlv" => Have these three variables used in this file?

   • Line 53-55 : " input logic [63:0] ibc_char_in; }
     input logic [63:0] ibc_char_in_valid; }
     input logic [7:0] ibc_char_vbytes; }
     output fe_ready; }
     output fe_eodb; } => Are these five variables input ,output or just logic ? (since they have not mentioned inside module declaration as ports).

   • Line 281 : Is there an "end" missing in DATA_BLK corresponding to the "begin"?

2. Project-Zipline/rtl/cr_prefix_attach/cr_prefix_attach_ctlr.v

   • Line 107 : assign pfd_mem_addr = {pac_prefix_num,pac_pfcounter};
     => Is it "pac_pfcounter" or "pac_pfdcounter"?(Because in Line 97 "pac_pfdcounter" is declared.)

   • Line 108 : assign phd_mem_addr = {pac_prefix_num,pac_hfcounter};
     => Is it "pac_hfcounter" or "pac_phdcounter"?(Because in Line 98 "pac_phdcounter" is declared.)

   • Line 110 : assign pac_phdcounter_max = (pac_phdcounter == N_PHD_WORDS); => Is it "N_PHD_WORDS" or "CR_PREFIX_N_PHD_WORDS" ? (Since N_PHD_WORDS are not declared anywhere. In the file "Project-Zipline/rtl/common/include/cr_global_params.vh" CR_PREFIX_N_PHD_WORDS has been declared in line 118)

   • Line 111 : assign pac_pfdcounter_max = (pac_pfdcounter == N_PFD_WORDS); => Is it "N_PFD_WORDS" or "CR_PREFIX_N_PFD_WORDS"? (Since N_PFD_WORDS are not declared anywhere.In the file "Project-Zipline/rtl/common/include/cr_global_params.vh" CR_PREFIX_N_PFD_WORDS has been declared in line 119.)

3. Project-Zipline/rtl/common/cr_mux_32.v

  *Line 14        :       wire   0  = t0 | t1;
                                                                  =>Is it "0" or "o"?

[michaelgmcintyre]

Thanks ANILATHOMAS519.

Please provide the error and warning messages coming from Vivado when you attempt to elaborate.

[ANILATHOMAS519]

Thanks for your response.

                                                                          This is the screenshot of the error and critical warning shown when we compile only CCEIP_64 part of the project.

 We tried after removing the syntax errors, after that we were able to do away with the critical warnings. But the errors remain the same. The screenshot given below shows the synthesis error what we got after removing syntax errors.

[michaelgmcintyre]

Hi ANILATHOMAS519,

I looked through the modules that generated the errors and failures. Nothing stands out specifically to me. May well be implementation of Verilog parsing syntax between Synopsis and Xilinx toolchains.

For example, the error "conditional expression could not be resolved to a constant [cr_huf_comp_lut.v:335]"

  for (genvar i=0; i<N_SYMBOLS_ENTRY; i++)
  . . .

Most likely can be resolved by rearranging the code to:

  genvar i;
  for (i=0; i<N_SYMBOLS_ENTRY; i++)
  . . .

You may need to modify files for your toolchain.

Thanks,
Michael

[ANILATHOMAS519]

Thanks for your sincere support .
As per your suggestion, we are doing on that error in project . I have given declaration of "i" outside for loop , but the synthesis error didn't gone . We are looking into the issue related to that "for" loop and will revert back to you(since for loop is not seem to be synthesizable in vivado).

Thank you
Anila

[michaelgmcintyre]

I'm a little surprised the declaration of "i" outside the for loop didn't resolve the issue. That Verilog block is pretty straight forward. The only other thing I can see there would be how the "generate" statement works in vivado. You may try to move the "genvar" statement outside the "generate" block:

genvar i;
generate
    for (i=0; i<N_SYMBOLS_ENTRY; i++)
        begin : hw_mem
             . . . 
        end
endgenerate	

Please consult the vivado doumentation concerning variable declaration, especially for the use of the "generate" block.

It would be useful for this project to add a file describing what needs to be changed or how to get the vivado toolchain to work if you are able to resolve the issues.

Thanks,
Michael

[ANILATHOMAS519]

We are looking on that error as per your suggestion. We failed again when genvar is given outside of the loop. We will try to provide the document if we succeed .
Thanks
Anila

[ANILATHOMAS519]

Hi @michaelgmcintyre ,

We tried implementing "for" loops in an independent project and that was synthesized successfully.So only error which we can doubt to create the problem is as given below.
Can you please take a look at the below mentioned error :

[Synth 8-3391] Unable to infer a block/distributed RAM for 'g.mem_reg' because the memory
pattern used is not supported. Failed to dissolve the memory into bits because the number of bits
(73728) is too large. Use 'set_param synth.elaboration.rodinMoreOptions {rt::set_parameter
dissolveMemorySizeLimit 73728}' to allow the memory to be dissolved into individual bits

Our doubt is that this above mentioned error can be the reason for the generation of the remaining errors which can be seen in the screenshot which was posted in this thread itself.

Can this error be related to over utilization of resources ?

We tried setting the parameter given in the error but again it throw the same error with this time the number of bits being even bigger(155360).

Regards
Anila

[michaelgmcintyre]

Hi Anila,

Please make sure you understand the Verilog code based on the keywords. It is good that you can synthesis "for" loops, but in the example above you need to use the "generate" block for the code to produce the correct results.

As to the block/distributed RAM issue, I don't think I can help since this issue does not occur with the Synopsis toolchain. However, I did find the links below for Vivado which may help.

https://forums.xilinx.com/t5/Vivado-TCL-Community/Why-is-the-Vivado-HD-unable-to-infer-a-block-distributed-RAM/td-p/304489

Also, please review the Vivado documentation on the application of distributed RAM and block RAM. You may need to contact your Xilinx FAE for additional support.

Thanks,
Michael

[ANILATHOMAS519]

Hi @michaelgmcintyre ,

   We read the link which you have given. The solution which we can see is that   "set parameter" which we have implemented. But the error remained same. We are continuing to take a look based on Vivado documentation of the "application of distributed RAM and block RAM". 

On the log file of synthesis, the warning corresponding to the error is

**
WARNING: [Synth 8-4767] Trying to implement RAM 'g.mem_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
2: Unable to determine number of words or word size in RAM.
3: No valid read/write found for RAM.

Since warning is not mentioning the correct location of the warning, we are having a hard time locating which module/file would be responsible for this. Can you please suggest whether any of the mentioned cases can be a problem?

Thanks for your support
Anila

[michaelgmcintyre]

Anila,

How does the error change when you apply the following as suggested in the elaboration error:

set_param synth.elaboration.rodinMoreOptions {rt::set_parameter dissolveMemorySizeLimit 73728}

Thanks,
Michael

[ANILATHOMAS519]

Hi @michaelgmcintyre ,
After applying :
"set_param synth.elaboration.rodinMoreOptions {rt::set_parameter dissolveMemorySizeLimit 73728}", we encountered the same error with the "Sizelimit" being 1563000 and the error corresponding to "for"(error of for loop:"conditional expression could not be resolved to a constant") loop was solved.

Then we again gave "set_param synth.elaboration.rodinMoreOptions {rt::set_parameter dissolveMemorySizeLimit 1563000}"

Attached the screenshot of the synthesis error at this point for your reference

Now the error files have changed from "huf_comp files" to "xp10 files".
We are now looking into these errors and will let you know the results.

[Meradanis]

@ANILATHOMAS519 Did you ever manage to solve your problems?
I'm trying to simulate the zipline_tb.v and had no success with vivado simulator or questa advances. I ran into the same syntax problems you've decribed (I suspect some lines were accidently deleted when part of this project has been made open source).
If you managed to get is working with the vivado toolchain, sharing your fork of the repo would be much appreceated.