verilogCPU/dm_ctrl.v at main · outofshade/verilogCPU · GitHub

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`define dm_word 3'b000
`define dm_halfword 3'b001
`define dm_halfword_unsigned 3'b010
`define dm_byte 3'b011
`define dm_byte_unsigned 3'b100

module dm_control(
    input  wire        mem_w,
    input  wire [31:0] Addr_in,
    input  wire [31:0] Data_write,
    input  wire [2:0]  dm_ctrl,
    input  wire [31:0] Data_read_from_dm,

    output reg  [31:0] Data_read,
    output reg  [31:0] Data_write_to_dm,
    output reg  [3:0]  wea_mem
);

    always @(*) begin
        Data_read        = 32'b0;
        Data_write_to_dm = 32'b0;
        wea_mem          = 4'b0000;


        if (dm_ctrl == `dm_word) begin
            Data_read = Data_read_from_dm;
        end
        else if (dm_ctrl == `dm_halfword) begin
            if (Addr_in[1] == 1'b1)
                Data_read = {{16{Data_read_from_dm[31]}}, Data_read_from_dm[31:16]};
            else
                Data_read = {{16{Data_read_from_dm[15]}}, Data_read_from_dm[15:0]};
        end
        else if (dm_ctrl == `dm_halfword_unsigned) begin
            if (Addr_in[1] == 1'b1)
                Data_read = {16'b0, Data_read_from_dm[31:16]};
            else
                Data_read = {16'b0, Data_read_from_dm[15:0]};
        end
        else if (dm_ctrl == `dm_byte) begin
            case (Addr_in[1:0])
                2'b00: Data_read = {{24{Data_read_from_dm[7]}},  Data_read_from_dm[7:0]};
                2'b01: Data_read = {{24{Data_read_from_dm[15]}}, Data_read_from_dm[15:8]};
                2'b10: Data_read = {{24{Data_read_from_dm[23]}}, Data_read_from_dm[23:16]};
                2'b11: Data_read = {{24{Data_read_from_dm[31]}}, Data_read_from_dm[31:24]};
                default: Data_read = 32'b0;
            endcase
        end
        else if (dm_ctrl == `dm_byte_unsigned) begin
            case (Addr_in[1:0])
                2'b00: Data_read = {24'b0, Data_read_from_dm[7:0]};
                2'b01: Data_read = {24'b0, Data_read_from_dm[15:8]};
                2'b10: Data_read = {24'b0, Data_read_from_dm[23:16]};
                2'b11: Data_read = {24'b0, Data_read_from_dm[31:24]};
                default: Data_read = 32'b0;
            endcase
        end

        if (mem_w == 1'b1) begin
            if (dm_ctrl == `dm_word) begin
                Data_write_to_dm = Data_write;
            end
            else if (dm_ctrl == `dm_halfword || dm_ctrl == `dm_halfword_unsigned) begin
                if (Addr_in[1] == 1'b1)
                    Data_write_to_dm = {Data_write[15:0], 16'b0};              // 对应 wea_mem = 1100
                else
                    Data_write_to_dm = {16'b0, Data_write[15:0]};              // 对应 wea_mem = 0011
            end
            else if (dm_ctrl == `dm_byte || dm_ctrl == `dm_byte_unsigned) begin
                case (Addr_in[1:0])
                    2'b00: Data_write_to_dm = {24'b0, Data_write[7:0]};        // 对应 wea_mem = 0001
                    2'b01: Data_write_to_dm = {16'b0, Data_write[7:0], 8'b0};  // 对应 wea_mem = 0010
                    2'b10: Data_write_to_dm = {8'b0, Data_write[7:0], 16'b0};  // 对应 wea_mem = 0100
                    2'b11: Data_write_to_dm = {Data_write[7:0], 24'b0};        // 对应 wea_mem = 1000
                    default: Data_write_to_dm = 32'b0;
                endcase
            end
        end

        if (mem_w == 1'b1) begin
            if (dm_ctrl == `dm_word) begin
                wea_mem = 4'b1111;
            end
            else if (dm_ctrl == `dm_halfword || dm_ctrl == `dm_halfword_unsigned) begin
                if (Addr_in[1] == 1'b1)
                    wea_mem = 4'b1100;
                else
                    wea_mem = 4'b0011;
            end
            else if (dm_ctrl == `dm_byte || dm_ctrl == `dm_byte_unsigned) begin
                case (Addr_in[1:0])
                    2'b00: wea_mem = 4'b0001;
                    2'b01: wea_mem = 4'b0010;
                    2'b10: wea_mem = 4'b0100;
                    2'b11: wea_mem = 4'b1000;
                    default: wea_mem = 4'b0000;
                endcase
            end
        end
        else begin
            wea_mem = 4'b0000;
        end
    end

endmodule