Here's an example using the new @m.circuit.combinational syntax to implement an FSM similar to the Verilog case statement style. We should add a notebook for this that discusses this in more detail.
https://github.com/phanrahan/mantle/tree/master/examples/example/fsm
Here's an example using the new
@m.circuit.combinationalsyntax to implement an FSM similar to the Verilog case statement style. We should add a notebook for this that discusses this in more detail.https://github.com/phanrahan/mantle/tree/master/examples/example/fsm