Related to vector lanes in Gem5 for RISC-V Vector

[soniab]

How many vector lanes does this Gem5 for RISC-V Vector support? Is it possible to change vector lanes at this point?

[huxuan0307]

Our implementation uses register renaming instead of vector lanes. If you want to limit the number of vector execution units, you can modify the code of the O3CPU.

[soniab]

Thank you for clarifying this. I am using RISC-V MinorCPU, so it will be the same for in-order CPUs too. I have checked "BaseMinorCPU.py" and have observed that only one vector unit (MinorDefaultVecFU) is being used here. If I want to change the number of vector execution units then will it be enough to add the vector units here? Do I need to change some other files too?