diff --git a/Bender.yml b/Bender.yml
index ccf4897b..6629bcd1 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -34,13 +34,11 @@ sources:
   - hardware/src/snitch_addr_demux.sv
   - hardware/src/tcdm_adapter.sv
   - hardware/src/tcdm_shim.sv
-  - hardware/src/tcdm_wide_narrow_mux.sv
-  - hardware/src/address_scrambler.sv
+  - hardware/src/mempool_addr_scrambler.sv
+  - hardware/src/mempool_tcdm_bank_interco.sv
   - hardware/src/axi_L2_interleaver.sv
   - hardware/src/bootrom.sv
   - hardware/src/selector.sv
-  - hardware/src/mempool_bank_id_remapper.sv
-  - hardware/src/mempool_dma_tile_id_remapper.sv
   - hardware/src/mempool_tile_rw_demux.sv
   - hardware/src/control_registers/control_registers_reg_pkg.sv
   - hardware/src/control_registers/control_registers_reg_top.sv
diff --git a/Makefile b/Makefile
index 1727ea19..4d2cdc40 100644
--- a/Makefile
+++ b/Makefile
@@ -192,6 +192,29 @@ $(VERILATOR_INSTALL_DIR)/bin/verilator: toolchain/verilator Makefile
 	cp toolchain/verilator/bin/verilator_bin $(VERILATOR_INSTALL_DIR)/share/verilator/bin/verilator_bin
 	cp toolchain/verilator/bin/verilator_bin $(VERILATOR_INSTALL_DIR)/bin/verilator_bin
 
+# Perfetto trace_processor (native, large-trace acceleration). The prebuilt
+# shell needs a newer GLIBC than older hosts ship, so run it in an Ubuntu
+# singularity container; shell + image install under install/perfetto.
+PERFETTO_INSTALL_DIR ?= $(INSTALL_DIR)/perfetto
+PERFETTO_IMAGE       ?= docker://ubuntu:24.04
+PERFETTO_SHELL       := $(PERFETTO_INSTALL_DIR)/trace_processor_shell
+PERFETTO_SIF         := $(PERFETTO_INSTALL_DIR)/ubuntu2404.sif
+
+.PHONY: perfetto
+perfetto: $(PERFETTO_SHELL) $(PERFETTO_SIF)
+$(PERFETTO_SHELL):
+	mkdir -p $(PERFETTO_INSTALL_DIR)
+	@url=$$(curl -sSL --fail https://get.perfetto.dev/trace_processor | \
+		grep -oE 'https://\S+linux-amd64/trace_processor_shell' | head -1); \
+	test -n "$$url" || { echo "ERROR: cannot resolve latest trace_processor URL"; exit 1; }; \
+	echo ">> latest trace_processor: $$url"; \
+	curl -L --fail -o $@ "$$url"
+	chmod +x $@
+$(PERFETTO_SIF):
+	mkdir -p $(PERFETTO_INSTALL_DIR)
+	SINGULARITY_CACHEDIR=$(PERFETTO_INSTALL_DIR)/.cache singularity build --force $@ $(PERFETTO_IMAGE)
+	rm -rf $(PERFETTO_INSTALL_DIR)/.cache
+
 # Update and patch hardware dependencies for MemPool
 # Previous changes will be stashed. Clear all the stashes with `git stash clear`
 .PHONY: update-deps
diff --git a/hardware/Makefile b/hardware/Makefile
index 055670f9..16dd8ea0 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -35,6 +35,7 @@ questa_config    ?=
 vcs_version      ?= 2024.09-zr
 vcs_cmd          ?= vcs-$(vcs_version)
 vcs_config       ?=
+vcs_gui          ?= -verdi
 # Path to the application binaries
 app_path         ?= $(abspath $(ROOT_DIR)/../software/bin)
 # Bender
@@ -96,6 +97,8 @@ vlogan_args += -assert svaext +v2k -override_timescale=1ns/1ps -kdb
 ifdef preload
   vcs_args += +PRELOAD=$(preload)
 endif
+vcs_assert_args ?= -assert nopostproc
+vcs_args        += $(vcs_assert_args)
 
 # ============================================================================
 # DPI and Trace Configuration
@@ -365,13 +368,20 @@ $(buildpath)/mempool_simvopt: $(buildpath)/compilevcs.sh $(buildpath)/$(dpi_libr
 	$(vcs_cmd) vcs -full64 $(top_level) -cc $(CC) -cpp $(CXX) -ld $(CXX) $(dpi_library)/mempool_vcs_dpi.so $(vcs_config) -assert disable_cover -o mempool_simvopt
 
 # Simulation
-simvcs: compile_vcs_simv
+simvcs: clean-dasm compile_vcs_simv
 	cd $(buildpath) && \
-	./mempool_simv $(vcs_args) -ucli -l transcript -do ../scripts/vcs/run.tcl -gui
+	./mempool_simv $(vcs_args) $(vcs_gui) -ucli -do ../scripts/vcs/run.tcl -l transcript
+	./scripts/return_status.sh $(buildpath)/transcript
 
-simcvcs: compile_vcs_simvopt
+simcvcs: clean-dasm compile_vcs_simvopt
 	cd $(buildpath) && \
 	./mempool_simvopt $(vcs_args) -l transcript
+	./scripts/return_status.sh $(buildpath)/transcript
+
+simcvcs_fsdb: clean-dasm compile_vcs_simv
+	cd $(buildpath) && \
+	./mempool_simv $(vcs_args) -ucli -do ../scripts/vcs/dump_all.tcl -l transcript
+	./scripts/return_status.sh $(buildpath)/transcript
 
 # DPIs
 .PHONY: dpivcs
@@ -509,6 +519,56 @@ $(buildpath)/%.trace: $(buildpath)/%.dasm
 tracevis:
 	$(MEMPOOL_DIR)/scripts/tracevis.py $(preload) $(buildpath)/*.trace -o $(buildpath)/tracevis.json
 
+# Perfetto protobuf export. Knobs:
+#   slices=function|instruction|none   core slice granularity (instruction needs spike-dasm)
+#   noc_slices=state|packet            NoC port slice granularity
+#   free_range=1                       auto-scale counter y-axes (default: pinned to [0,1])
+#   flows=1                            correlate packets to core requests via (requester, meta_id); forces noc_slices=packet
+#   freq=<MHz>                         clock freq for the real-ns axis (default 500 MHz)
+slices ?= function
+freq ?= 500
+noc_slices ?= state
+ifeq ($(flows),1)
+override noc_slices := packet
+endif
+# Optional cycle window: window=START:END exports only that cycle range (smaller/faster trace).
+ifdef window
+  win_start := $(word 1,$(subst :, ,$(window)))
+  win_end   := $(word 2,$(subst :, ,$(window)))
+endif
+.PHONY: perfetto-gen
+perfetto-gen:
+	$(python) $(ROOT_DIR)/scripts/perfetto_gen.py $(buildpath)/trace_hart_*.dasm \
+		--cores-per-tile $(num_cores_per_tile) \
+		--tiles-per-group $(shell echo $$(( $(num_cores) / $(num_cores_per_tile) / $(num_groups) ))) \
+		--mesh-y $(shell echo $$(( $(num_groups) / $(num_x) ))) \
+		--clk-freq $(freq) \
+		--slices $(slices) $(if $(preload),--elf $(preload),) \
+		$(if $(wildcard $(buildpath)/noc_profiling),--noc $(buildpath)/noc_profiling,) \
+		$(if $(wildcard $(buildpath)/spm_profiling),--spm $(buildpath)/spm_profiling,) \
+		--noc-slices $(noc_slices) $(if $(filter 1,$(free_range)),--free-range,) \
+		$(if $(filter 1,$(flows)),--flows,) \
+		$(if $(win_start),--cycle-start $(win_start),) $(if $(win_end),--cycle-end $(win_end),) \
+		-o $(buildpath)/perf.perfetto-trace
+
+# Native Perfetto trace_processor lives under $(INSTALL_DIR)/perfetto, installed
+# by the root `make perfetto`. perfetto-gen exports the trace; perfetto-view
+# serves it through the installed shell + container.
+perfetto_dir := $(INSTALL_DIR)/perfetto
+tp_shell     := $(perfetto_dir)/trace_processor_shell
+perfetto_sif := $(perfetto_dir)/ubuntu2404.sif
+
+.PHONY: perfetto-view
+perfetto-view:
+	@test -f $(tp_shell) -a -f $(perfetto_sif) || \
+		{ echo "ERROR: trace_processor not installed -- run 'make perfetto' in the repo root"; exit 1; }
+	@test -f $(buildpath)/perf.perfetto-trace || \
+		{ echo "ERROR: $(buildpath)/perf.perfetto-trace not found -- run 'make perfetto-gen' first"; exit 1; }
+	@echo ">> Serving $(abspath $(buildpath))/perf.perfetto-trace on 127.0.0.1:9001"
+	@echo ">> Reload https://ui.perfetto.dev and click YES on 'Trace Processor native acceleration'"
+	singularity exec -B $(abspath $(buildpath)) -B $(perfetto_dir) $(perfetto_sif) \
+		$(tp_shell) --httpd $(abspath $(buildpath))/perf.perfetto-trace
+
 ############################
 # Unit tests simulation    #
 ############################
diff --git a/hardware/scripts/perfetto_gen.py b/hardware/scripts/perfetto_gen.py
new file mode 100644
index 00000000..3644a652
--- /dev/null
+++ b/hardware/scripts/perfetto_gen.py
@@ -0,0 +1,1716 @@
+#!/usr/bin/env python3
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# perfetto_gen.py -- Phase 1 of the performance-visualization plan.
+#
+# Reads the per-hart Snitch traces (trace_hart_*.dasm) and emits a Perfetto
+# *protobuf* trace (https://ui.perfetto.dev). Scale-ready successor to and
+# SUPERSET of `make tracevis`: group>tile>core nested track tree, per-core
+# function/instruction slices, and per-core IPC + stall-breakdown COUNTER
+# tracks (windowed over --window-ns), which tracevis never had.
+#
+# Counter semantics (matters for correctness): the .dasm emits a line only when
+# an instruction RETIRES, and its stall_* count the cycles of the gap that
+# PRECEDED that retirement, so each instruction's stalls are spread across the
+# windows the retirement gap spans; every active window is emitted so an idle
+# window reads a true 0 (no sample-and-hold).
+#
+# Everything comes from the raw .dasm (no `make trace`): stalls + pc in the
+# line, function/source via addr2line on the elf, disasm via spike-dasm.
+#
+# Usage:
+#   scripts/perfetto_gen.py build_vcs/trace_hart_*.dasm -o out.perfetto-trace
+# scripts/perfetto_gen.py ... --slices instruction # full per-insn timeline
+#   scripts/perfetto_gen.py ... --slices none             # counters only
+#   (geometry defaults match tensorpool64: 4 cores/tile, 4 tiles/group)
+
+import argparse
+import bisect
+import collections
+import glob
+import os
+import re
+import subprocess
+import sys
+
+from perfetto.trace_builder.proto_builder import TraceProtoBuilder
+from perfetto.protos.perfetto.trace.perfetto_trace_pb2 import TrackEvent
+
+SEQ = 1  # trusted_packet_sequence_id (single producer; absolute timestamps)
+
+# One .dasm line:  <time> <cyc> <pc> <instr-or-DASM(hex)> #; {'k': 0x.., ...}
+# spike-dasm replaces DASM(hex) with disasm but preserves the `#;` extras dict,
+# so this matches both forms.
+LINE_RE = re.compile(
+    r"^\s*(\d+)\s+(\d+)\s+(0x[0-9a-fA-F]+)\s+(.*?)\s+#;\s*(.*)$")
+FIELD_RE = re.compile(r"'(\w+)':\s*(0x[0-9a-fA-F]+)")
+HART_RE = re.compile(r"trace_hart_0x([0-9a-fA-F]+)\.dasm")
+
+# Per-core counter metrics. IPC from the retirement count; stalls from the
+# .dasm extras dict.
+STALLS = ["stall_tot", "stall_raw", "stall_lsu", "stall_acc", "stall_ins"]
+STALL_COMPONENTS = [s for s in STALLS if s != "stall_tot"]  # raw/lsu/acc/ins
+METRICS = ["IPC"] + STALLS
+
+# Functions that bracket the region of interest (tracevis -cb semantics).
+BENCH_START = "mempool_start_benchmark"
+BENCH_STOP = "mempool_stop_benchmark"
+
+
+class Uuids:
+    """Deterministic, collision-free uuid allocator keyed by a name."""
+
+    def __init__(self):
+        self._n = 0
+        self._m = {}
+        self._seen = set()
+
+    def get(self, key):
+        if key not in self._m:
+            self._n += 1
+            self._m[key] = self._n
+        return self._m[key]
+
+
+class Addr2Line:
+    """Batched, globally-cached PC -> (function, source, inlined-frames)."""
+
+    def __init__(self, tool, elf):
+        self.tool = tool
+        self.elf = elf
+        self.cache = {}
+
+    def resolve(self, pcs):
+        need = sorted({p for p in pcs if p not in self.cache})
+        if need and self.tool and self.elf:
+            for i in range(0, len(need), 4000):  # stay under arg-length limits
+                chunk = need[i:i + 4000]
+                out = subprocess.run(
+                    [self.tool, "-e", self.elf, "-f", "-a", "-i"]
+                    + [f"0x{p:x}" for p in chunk],
+                    capture_output=True, text=True).stdout
+                self._parse(out)
+        for p in need:  # anything addr2line didn't echo
+            self.cache.setdefault(p, ("??", "??:0", ""))
+
+    def _parse(self, out):
+        # Block: 0x<addr>\n<func>\n<file>:<line>\n[<inl func>\n<inl file>\n]...
+        # `-a` echoes the address; `-i` lists inlined-by frames after the
+        # first.
+        lines = out.split("\n")
+        i, n = 0, len(lines)
+        while i < n:
+            if not lines[i].startswith("0x"):
+                i += 1
+                continue
+            addr = int(lines[i], 16)
+            func = lines[i + 1] if i + 1 < n else "??"
+            src = lines[i + 2] if i + 2 < n else "??:0"
+            i += 3
+            inl = []
+            while i < n and not lines[i].startswith("0x"):
+                inl.append(lines[i])
+                i += 1
+            # remaining lines are (func, file) pairs for each inlined-by frame
+            inline_str = " ".join("(inlined by) " + x for x in inl if x)
+            self.cache[addr] = (func, src, inline_str)
+
+    def get(self, pc):
+        return self.cache.get(pc, ("??", "??:0", ""))
+
+
+# TrackDescriptor.ChildTracksOrdering.EXPLICIT: order children by
+# sibling_order_rank
+CHILD_ORDER_EXPLICIT = 3
+
+
+def add_track(
+        builder,
+        uuid,
+        name,
+        parent=None,
+        counter=False,
+        child_order=None,
+        order_rank=None):
+    pkt = builder.add_packet()
+    td = pkt.track_descriptor
+    td.uuid = uuid
+    td.name = name
+    if parent is not None:
+        td.parent_uuid = parent
+    if counter:
+        td.counter.SetInParent()
+    # how THIS track's children are ordered in the UI
+    if child_order is not None:
+        td.child_ordering = child_order
+    # this track's rank among its siblings (EXPLICIT parent)
+    if order_rank is not None:
+        td.sibling_order_rank = order_rank
+    return uuid
+
+
+# Flow-slice ordering. Several hops of one transaction can land on the SAME
+# cycle (combinational wires across pipeline stages). Perfetto chains
+# same-timestamp flow slices by TRACE-INSERTION order, but the passes below
+# emit per NODE TYPE (cores, tiles, routers, banks), NOT per transaction. So we
+# BUFFER every event and flush it (flush_events) stable-sorted by (ts, phase,
+# rank): the pipeline `rank` puts same-cycle hops in causal order. The rank
+# lives ONLY in the sort key -- timestamps stay the TRUE cycle*clk_ns, so a
+# 1-cycle handshake is exactly clk_ns wide (honest ns axis).
+#
+# Canonical transaction order (= strictly increasing (cycle, rank) along the
+# chain):
+# core req -> tile req out -> (router in -> router out)* -> tile req in -> bank
+#   -> tile resp out -> (router in -> router out)* -> tile resp in -> core resp
+# `rank` (pipeline stage, used by the flush sort key, NOT the timestamp):
+#   0 = origin (core req)    1 = send (tile/router out)
+#   2 = recv  (router/tile in)  3 = sink (bank, core resp terminator)
+# ns per cycle: the timeline axis is REAL ns = cycle * clk_ns. Set in main()
+# from
+TICK = 2.0
+# --clk-freq (default 500 MHz -> 2.0 ns/cycle) or --clk-period.
+
+# The Perfetto UI orders sibling tracks LEXICOGRAPHICALLY by name, so numeric
+# ids must be zero-padded (else Tile 10 sorts before Tile 2) and the top-level
+# roots are numbered so the flow reads top-to-bottom. Widths set in main();
+# MESH_NY (= --mesh-y) maps a linear group id to its mesh (x,y).
+PAD_G = PAD_T = PAD_H = 2
+MESH_NY = 1
+
+
+def _gname(g):
+    """Group track label: zero-padded linear id + its mesh (x,y) coordinate."""
+    return f"Group {g:0{PAD_G}d} ({g // MESH_NY},{g % MESH_NY})"
+
+
+def _tname(t):
+    return f"Tile {t:0{PAD_T}d}"
+
+
+# Export window in CYCLE NUMBERS (frequency-independent). Out-of-window data is
+# DROPPED at load so the trace/DB actually shrinks. Defaults cover the whole
+# run; set in main() from --cycle-start/end.
+WIN_CYC_LO = 0
+WIN_CYC_HI = 1 << 62
+
+
+def _winclip(s, e):
+    """Clip a [start,end] cycle run to the export window; None if it doesn't
+    overlap."""
+    s = s if s > WIN_CYC_LO else WIN_CYC_LO
+    e = e if e < WIN_CYC_HI else WIN_CYC_HI
+    return (s, e) if e > s else None
+
+
+# Buffered track events, flushed by flush_events in a final stable sort by (ts,
+# phase, rank). phase orders END(0) < COUNTER(1) < BEGIN(2) so a slice closes
+# before the next opens at a shared timestamp; among same-cycle BEGINs the
+# pipeline `rank` gives causal order so flows chain correctly.
+_EVENTS = []
+_PH_END, _PH_CTR, _PH_BEGIN = 0, 1, 2
+
+
+def emit_counter(builder, ts_ns, track_uuid, value):
+    t = int(ts_ns)
+    _EVENTS.append(((t, _PH_CTR, 0), ("C", t, track_uuid, float(value))))
+
+
+def pin_counter_range(builder, ctr_uuids, end_ns, clk_ns, lo=0.0, hi=1.0):
+    """Pin each counter's y-axis to [lo, hi] (the protobuf has NO counter range
+    field -- only data-driven auto-scaling). Emit a 1-cycle `hi` blip then `lo`
+    at the very END of the track, past all real samples so it draws no visible
+    bar yet forces the auto-range to span [lo, hi]; `lo` last so the track ends
+    at 0."""
+    for u in ctr_uuids:
+        emit_counter(builder, end_ns - clk_ns, u, hi)
+        emit_counter(builder, end_ns, u, lo)
+
+
+def emit_slice_begin(
+        builder,
+        ts_ns,
+        track_uuid,
+        name,
+        annos=None,
+        flow_id=None,
+        terminating=False,
+        rank=0):
+    # `rank` is the pipeline stage (0 origin .. 3 sink); it orders same-cycle
+    # flow slices in the flush sort key, NEVER the timestamp.
+    t = int(ts_ns)
+    _EVENTS.append(((t, _PH_BEGIN, rank), ("B", t, track_uuid,
+                   name, annos, flow_id, terminating)))
+
+
+def emit_slice_end(builder, ts_ns, track_uuid):
+    t = int(ts_ns)
+    _EVENTS.append(((t, _PH_END, 0), ("E", t, track_uuid)))
+
+
+def flush_events(builder):
+    """Write every buffered track event, stable-sorted by (ts, phase, rank) so
+    same-cycle flow begins land in pipeline order (see _EVENTS)."""
+    for _, p in sorted(_EVENTS, key=lambda x: x[0]):
+        pkt = builder.add_packet()
+        pkt.timestamp = p[1]
+        pkt.trusted_packet_sequence_id = SEQ
+        ev = pkt.track_event
+        ev.track_uuid = p[2]
+        kind = p[0]
+        if kind == "C":
+            ev.type = TrackEvent.TYPE_COUNTER
+            ev.double_counter_value = p[3]
+        elif kind == "E":
+            ev.type = TrackEvent.TYPE_SLICE_END
+        # "B": slice begin (may carry a flow)
+        else:
+            ev.type = TrackEvent.TYPE_SLICE_BEGIN
+            ev.name = p[3]
+            annos, flow_id, terminating = p[4], p[5], p[6]
+            # Flow: every slice of one transaction shares the flow_id, so a
+            # click follows the arrows to the originating request and back. The
+            # LAST hop lists the id in terminating_flow_ids ONLY -- not
+            # flow_ids: Perfetto's FlowTracker inserts an edge on both
+            # Begin(flow_ids) and End(terminating_flow_ids), so putting it in
+            # both would self-loop the terminator (a bogus extra arrow).
+            if flow_id is not None:
+                if terminating:
+                    ev.terminating_flow_ids.append(flow_id)
+                else:
+                    ev.flow_ids.append(flow_id)
+            for k, v in (annos or []):
+                if not v:
+                    continue
+                da = ev.debug_annotations.add()
+                da.name = k
+                da.string_value = v
+    _EVENTS.clear()
+
+
+class WindowAcc:
+    """Per-window IPC + stall accumulator with gap-aware stall spreading.
+
+    add(prev_t, t, stalls): the instruction retired at `t`; its stall cycles
+    occurred during (prev_t, t], so they are distributed across the windows
+    that interval overlaps. The retirement (for IPC) is counted in window(t).
+    emit() then writes every window in [first_active, last_active] -- idle
+    windows in between get a real 0.
+    """
+
+    def __init__(self, window_ns, clk_ns):
+        self.W = window_ns
+        self.clk = clk_ns
+        self.count = {}
+        self.stall = {}
+        self.first = None
+        self.last = None
+        self.last_t = None
+
+    def _touch(self, w):
+        if self.first is None or w < self.first:
+            self.first = w
+        if self.last is None or w > self.last:
+            self.last = w
+
+    def _add_stall(self, w, stalls, frac):
+        d = self.stall.setdefault(w, {s: 0.0 for s in STALLS})
+        for s in STALLS:
+            d[s] += stalls[s] * frac
+        self._touch(w)
+
+    def add(self, prev_t, t, stalls):
+        w = int(t // self.W)
+        self.count[w] = self.count.get(w, 0) + 1
+        self._touch(w)
+        self.last_t = t
+        a = prev_t if (prev_t is not None and prev_t < t) else t
+        if a >= t:                       # no preceding gap -> all in window(t)
+            self._add_stall(w, stalls, 1.0)
+            return
+        span = t - a
+        for ww in range(int(a // self.W), int((t - 1) // self.W) + 1):
+            lo = max(a, ww * self.W)
+            hi = min(t, (ww + 1) * self.W)
+            if hi > lo:
+                self._add_stall(ww, stalls, (hi - lo) / span)
+
+    def emit(self, builder, ctr_uuid, pin=True):
+        # Perfetto counters are sample-and-hold, so emit a value only when it
+        # CHANGES (idle stretches collapse to a single 0 point). The first and
+        # last active windows are always emitted to bound the track.
+        if self.first is None:
+            return
+        cyc_per_win = self.W / self.clk
+        zero = {s: 0.0 for s in STALLS}
+        last_val = {m: None for m in METRICS}
+        for w in range(self.first, self.last + 1):
+            ts = w * self.W
+            # IPC = retirements / active cycles; the trailing window is
+            # partial.
+            if w == self.last and self.last_t is not None:
+                cyc = max(1.0, (self.last_t - ts) / self.clk)
+            else:
+                cyc = cyc_per_win
+            st = self.stall.get(w, zero)
+            # CPI-stack as PER-CYCLE fractions so IPC + stalls == 1 while busy.
+            # The raw .dasm stall_* OVERLAP (one stall is charged to several
+            # bursting instructions), so summed they can exceed the
+            # non-retiring budget (1 - IPC); we cap the components into that
+            # budget (preserving their ratio) and stall_tot is their sum.
+            # IPC + stall_tot == 1 when busy, < 1 only when genuinely idle.
+            ipc = self.count.get(w, 0) / cyc
+            nonretire = max(0.0, 1.0 - ipc)
+            raw = sum(st[s] for s in STALL_COMPONENTS) / \
+                cyc     # measured stall frac (may overlap)
+            scale = (nonretire / raw) if raw > nonretire else 1.0
+            vals = {"IPC": ipc}
+            tot = 0.0
+            for s in STALL_COMPONENTS:
+                f = (st[s] / cyc) * scale
+                vals[s] = f
+                tot += f
+            vals["stall_tot"] = tot
+            force = (w == self.first or w == self.last)
+            for m in METRICS:
+                if force or vals[m] != last_val[m]:
+                    emit_counter(builder, ts, ctr_uuid[m], vals[m])
+                    last_val[m] = vals[m]
+        # Drop to 0 one window past the last active window so a finished core's
+        # final value doesn't sample-and-hold across the idle tail.
+        ts_end = (self.last + 1) * self.W
+        for m in METRICS:
+            if last_val[m]:
+                emit_counter(builder, ts_end, ctr_uuid[m], 0.0)
+        # Pin every metric's y-axis to [0,1] (1.0 blip past the data).
+        if pin:
+            pin_counter_range(
+                builder,
+                ctr_uuid.values(),
+                ts_end + 2 * self.clk,
+                self.clk)
+
+
+def hart_to_gtc(hart, cores_per_tile, tiles_per_group):
+    cores_per_group = cores_per_tile * tiles_per_group
+    g = hart // cores_per_group
+    within = hart % cores_per_group
+    return g, within // cores_per_tile, within % cores_per_tile
+
+
+def collect_pcs(path):
+    """Cheap first pass over the RAW .dasm: just the PC column (for
+    addr2line)."""
+    pcs = set()
+    with open(path, "r", errors="replace") as f:
+        for line in f:
+            m = LINE_RE.match(line)
+            if m:
+                pcs.add(int(m.group(3), 16))
+    return pcs
+
+
+def line_iter(path, spike_dasm, want_disasm):
+    """Stream lines (O(1) memory): raw, or piped through spike-dasm for
+    disasm."""
+    if want_disasm and spike_dasm:
+        proc = subprocess.Popen([spike_dasm], stdin=open(path, "r"),
+                                stdout=subprocess.PIPE, text=True,
+                                errors="replace")
+        try:
+            for line in proc.stdout:
+                yield line
+        finally:
+            proc.stdout.close()
+            proc.wait()
+    else:
+        with open(path, "r", errors="replace") as f:
+            for line in f:
+                yield line
+
+
+def process_dasm(path, hart, builder, uu, args, a2l, pe_data=None, flows=None):
+    g, t, c = hart_to_gtc(hart, args.cores_per_tile, args.tiles_per_group)
+    want_disasm = (args.slices == "instruction")
+    want_slices = (args.slices != "none")
+    # marker names are needed even in counters-only mode when filtering
+    need_names = want_slices or args.filter_benchmark
+
+    # --- Core › group / tile / core track tree (deduped by Uuids._seen) ---
+    # "Core" is a top-level root mirroring the "NoC routers"/"NoC tiles" roots.
+    core_root = uu.get(("core_root",))
+    if ("core_root",) not in uu._seen:
+        add_track(builder, core_root, "1 Core")
+        uu._seen.add(("core_root",))
+    g_uuid = uu.get(("g", g))
+    if ("g", g) not in uu._seen:
+        add_track(builder, g_uuid, _gname(g), parent=core_root)
+        uu._seen.add(("g", g))
+    t_uuid = uu.get(("t", g, t))
+    if ("t", g, t) not in uu._seen:
+        add_track(builder, t_uuid, _tname(t), parent=g_uuid)
+        uu._seen.add(("t", g, t))
+    # EXPLICIT child ordering so the stat counters and the PE port-traffic
+    # tracks don't interleave (default lexicographic sort would slot req/resp
+    # between IPC and stall_*). Counters first (rank 0..), traffic last.
+    core_uuid = uu.get(("c", hart))
+    add_track(
+        builder,
+        core_uuid,
+        f"Core {hart:0{PAD_H}d} (G{g}T{t}C{c})",
+        parent=t_uuid,
+        child_order=CHILD_ORDER_EXPLICIT)
+    ctr_uuid = {
+        name: add_track(
+            builder,
+            uu.get(
+                ("ctr",
+                 hart,
+                 name)),
+            name,
+            parent=core_uuid,
+            counter=True,
+            order_rank=i) for i,
+        name in enumerate(METRICS)}
+
+    # PE (Snitch core) data-port traffic as expandable child tracks of the Core
+    # node, beside IPC/stalls. No bw/util for PE ports (traffic); req shows
+    # read/write/stall, resp shows hsk/stall, idle = grey gaps. --noc-slices
+    # packet shows one slice per load/store with its address.
+    pe = pe_data.get((g, t, c)) if pe_data else None
+    if pe:
+        pe_runs, pe_pkts = pe
+        for j, (rr, io, port) in enumerate(sorted(pe_runs)):
+            label = ("req" if rr == 0 else "resp") + \
+                (f" {port}" if port else "")
+            leaf = add_track(
+                builder,
+                uu.get(
+                    ("pe",
+                     hart,
+                     rr,
+                     io,
+                     port)),
+                label,
+                parent=core_uuid,
+                order_rank=len(METRICS) +
+                j)
+            if args.noc_slices == "packet" and rr == 0 and (
+                    io, port) in pe_pkts:
+                _emit_req_packet_slices(
+                    pe_runs[(rr, io, port)], pe_pkts[(io, port)],
+                    leaf, rr, builder, args, pe=True, flows=flows,
+                    req_ctx=(g, t, c), flow_rank=0)
+            elif (flows and args.noc_slices == "packet" and rr == 1
+                  and (io, port) in pe_pkts):
+                _emit_pe_resp_packets(pe_runs[(rr, io, port)], pe_pkts[(
+                    io, port)], leaf, builder, args, flows, (g, t, c))
+            else:
+                _emit_state_slices(
+                    pe_runs[(rr, io, port)], leaf, rr, builder, args)
+
+    if need_names:
+        a2l.resolve(collect_pcs(path))
+
+    # counter bucket (cycles)
+    win_cyc = max(1, int(round(args.window_ns / args.clk_ns)))
+    acc = WindowAcc(win_cyc * TICK, TICK)
+    cur_func = None          # name of the open function slice (None = closed)
+    instr_open = False
+    in_bench = not args.filter_benchmark
+    prev_t = None
+    last_t = None
+
+    def close_instr(ts):
+        nonlocal instr_open
+        if instr_open:
+            emit_slice_end(builder, ts, core_uuid)
+            instr_open = False
+
+    def close_func(ts):
+        nonlocal cur_func
+        close_instr(ts)
+        if cur_func is not None:
+            emit_slice_end(builder, ts, core_uuid)
+            cur_func = None
+
+    for line in line_iter(path, args.spike_dasm, want_disasm):
+        m = LINE_RE.match(line)
+        if not m:
+            continue
+        cyc = m.group(2)
+        cyc_n = int(cyc)
+        # core lane on the same cycle axis as traffic lanes
+        time_ns = cyc_n * TICK
+        if cyc_n < WIN_CYC_LO:           # before the export window -> skip
+            prev_t = None  # don't bridge stalls across the window start
+            continue
+        # past it (dasm is time-ordered) -> close + stop
+        if cyc_n >= WIN_CYC_HI:
+            close_func(time_ns)
+            break
+        pc = int(m.group(3), 16)
+        func, src, inl = a2l.get(pc) if need_names else ("", "", "")
+
+        if args.filter_benchmark:
+            if func == BENCH_START:
+                in_bench = True
+                prev_t = None        # don't bridge stalls across the boundary
+                continue
+            if func == BENCH_STOP:
+                in_bench = False
+                close_func(time_ns)
+                continue
+        if not in_bench:
+            continue
+
+        ex = dict(FIELD_RE.findall(m.group(5)))
+        stalls = {s: int(ex.get(s, "0x0"), 16) for s in STALLS}
+        acc.add(prev_t, time_ns, stalls)
+        prev_t = last_t = time_ns
+
+        if want_slices:
+            if func != cur_func:
+                close_func(time_ns)
+                label = func if func and func != "??" else os.path.basename(
+                    src)
+                emit_slice_begin(builder, time_ns, core_uuid, label or "??",
+                                 annos=[("source", src), ("cyc", cyc)])
+                cur_func = func
+            if want_disasm:
+                close_instr(time_ns)
+                instr = m.group(4).strip()
+                emit_slice_begin(builder, time_ns, core_uuid, instr or "?",
+                                 annos=[("pc", f"0x{pc:08x}"), ("source", src),
+                                        ("cyc", cyc), ("inline", inl)])
+                instr_open = True
+
+    acc.emit(builder, ctr_uuid, pin=not args.free_range)
+    close_func((last_t + TICK) if last_t is not None else 0)
+    return g, t, c
+
+
+def detect_elf(files):
+    """Look for PRELOAD=<elf> in the build dir's transcript (next to
+    traces)."""
+    seen = set()
+    for f in files:
+        d = os.path.dirname(os.path.abspath(f))
+        if d in seen:
+            continue
+        seen.add(d)
+        tr = os.path.join(d, "transcript")
+        if os.path.isfile(tr):
+            with open(tr, "r", errors="replace") as fh:
+                m = re.search(r"PRELOAD=(\S+)", fh.read())
+                if m and os.path.isfile(m.group(1)):
+                    return m.group(1)
+    return None
+
+
+def find_tool(explicit, names):
+    if explicit:
+        return explicit
+    from shutil import which
+    here = os.path.dirname(os.path.abspath(__file__))
+    roots = [os.path.join(here, "..", "..", "install", "riscv-gcc", "bin"),
+             os.path.join(here, "..", "..", "install", "riscv-isa-sim", "bin")]
+    for r in roots:
+        for nm in names:
+            cand = os.path.join(r, nm)
+            if os.path.isfile(cand):
+                return cand
+    for nm in names:  # fall back to PATH
+        if which(nm):
+            return which(nm)
+    return None
+
+
+# ---------------------------------------------------------------------------
+# NoC interconnect: derived ENTIRELY from the per-router / per-tile full logs
+# (router_g*_<req|resp>.log, tile_g*_t*.log -- one file per router and per
+# tile). Each file carries BOTH the state runs (S lines) and the per-request
+# packet detail (P lines); --noc-slices picks the granularity at export, like
+# the core --slices function|instruction. Two trees ("NoC routers", "NoC
+# tiles"): each per-port node carries its util/throughput/stall counters SIDE
+# BY SIDE with that port's traffic slices. state 0=idle 1=stall 2=hsk/read
+# 3=hsk-write. Idle is DROPPED so the gap renders as Perfetto's neutral grey
+# (the protobuf has no per-slice color field).
+# ---------------------------------------------------------------------------
+NOC_NET = {0: "REQ", 1: "RESP"}
+NOC_PORTIDX = {0: "N", 1: "E", 2: "S", 3: "W", 4: "local"}
+NOC_IO = {0: "in", 1: "out"}
+# Per-port-side stats, per-cycle fractions of the window:
+#   bw [flit/cyc] = handshakes/win ; stall [cyc/cyc] = stalled/win ;
+#   util = (handshakes+stalled)/win = bw+stall (idle = 1-util).
+NOC_PORT_METRICS = ["util", "bw [flit/cyc]", "stall [cyc/cyc]"]
+
+
+def noc_state_name(rr, st):
+    """Slice name (Perfetto colors by name)."""
+    if st == 0:
+        return "idle"
+    if st == 1:
+        return "stall"
+    if rr == 1:                              # resp ports: no read/write split
+        return "hsk"
+    return "read" if st == 2 else "write"    # req ports
+
+
+# merged: one file per group
+ROUTER_LOG_RE = re.compile(r"router_g(\d+)_(req|resp)\.log$")
+TILE_LOG_RE = re.compile(r"tile_g(\d+)_t(\d+)\.log$")
+# merged: one file per tile (core in line)
+PE_LOG_RE = re.compile(r"pe_g(\d+)_t(\d+)\.log$")
+SPM_BANK_LOG_RE = re.compile(r"bank_g(\d+)_t(\d+)\.log$")
+
+
+def load_spm_bank_logs(spm_dir):
+    """Glob per-tile SPM bank logs (bank_g<g>_t<t>.log; one per tile, all its
+    banks). Returns {(g,t): (runs, packets)}: S line = bank start end state
+    (0=idle 1=stall 2=read 3=write); P line =
+    bank cyc wen addr loc wide port sg it core meta_id (each granted access).
+    loc=1 if a local input port won, wide=1 for a DMA access, port=winning
+    arbiter input-port index, sg/it/core=remote NoC origin."""
+    out = {}
+    for path in glob.glob(os.path.join(spm_dir, "bank_g*_t*.log")):
+        m = SPM_BANK_LOG_RE.search(os.path.basename(path))
+        if not m:
+            continue
+        key = (int(m.group(1)), int(m.group(2)))
+        runs, packets = out.setdefault(key, ({}, {}))
+        with open(path, "r", errors="replace") as f:
+            for line in f:
+                x = line.split()
+                if len(
+                        x) == 5 and x[0] == "S":  # S bank start end state
+                    try:
+                        bank, s, e, st = int(
+                            x[1]), int(
+                            x[2]), int(
+                            x[3]), int(
+                            x[4])
+                    except ValueError:
+                        continue
+                    w = _winclip(s, e)
+                    if w:
+                        runs.setdefault(bank, []).append((w[0], w[1], st))
+                # P bank cyc wen addr loc wide port sg it core meta_id
+                elif len(x) == 12 and x[0] == "P":
+                    try:
+                        bank = int(x[1])
+                        rec = [
+                            int(
+                                x[2]), int(
+                                x[3]), int(
+                                x[4], 16), int(
+                                x[5]), int(
+                                x[6]), int(
+                                x[7]), int(
+                                x[8]), int(
+                                    x[9]), int(
+                                        x[10]), int(
+                                            x[11])]
+                    except ValueError:
+                        continue
+                    if not (WIN_CYC_LO <= rec[0] < WIN_CYC_HI):
+                        continue
+                    packets.setdefault(bank, []).append(rec)
+    return out
+
+
+def load_pe_logs(noc_dir):
+    """Glob the MERGED per-tile core-port logs -> {(g,t,c): (runs, packets)}.
+    pe_g<g>_t<t>.log is one file PER TILE with every line PREFIXED by its core
+    index (idx), so idx is read from the line, not the filename.
+      runs[(rr,io,port)] = [(s,e,st)]                                 (S lines)
+      packets[(io,port)] : req (io=1) [[cyc,wen,addr,meta_id]]
+                           resp (io=0) [[cyc,meta_id]]                (P lines)
+    The trailing meta_id ties each packet to its originating request."""
+    out = {}
+    for path in glob.glob(os.path.join(noc_dir, "pe_g*_t*.log")):
+        m = PE_LOG_RE.search(os.path.basename(path))
+        if not m:
+            continue
+        g, t = int(m.group(1)), int(m.group(2))
+        with open(path, "r", errors="replace") as f:
+            for line in f:
+                x = line.split()
+                if len(x) < 2:
+                    continue
+                try:
+                    # leading demux index = core / port
+                    idx = int(x[0])
+                except ValueError:
+                    continue
+                # the rest is the original S/P line
+                x = x[1:]
+                runs, packets = out.setdefault((g, t, idx), ({}, {}))
+                # S rr io port start end state
+                if len(x) == 7 and x[0] == "S":
+                    try:
+                        rr, io, port, s, e, st = (int(z) for z in x[1:])
+                    except ValueError:
+                        continue
+                    w = _winclip(s, e)
+                    if w:
+                        runs.setdefault(
+                            (rr, io, port), []).append(
+                            (w[0], w[1], st))
+                # REQ: P io port cyc wen addr meta_id
+                elif len(x) == 7 and x[0] == "P":
+                    try:
+                        io, port, cyc, wen = int(
+                            x[1]), int(
+                            x[2]), int(
+                            x[3]), int(
+                            x[4])
+                        if not (WIN_CYC_LO <= cyc < WIN_CYC_HI):
+                            continue
+                        packets.setdefault((io, port), []).append(
+                            [cyc, wen, int(x[5], 16), int(x[6])])
+                    except ValueError:
+                        continue
+                # RESP: P io port cyc meta_id
+                elif len(x) == 5 and x[0] == "P":
+                    try:
+                        io, port, cyc, mid = int(
+                            x[1]), int(
+                            x[2]), int(
+                            x[3]), int(
+                            x[4])
+                        if not (WIN_CYC_LO <= cyc < WIN_CYC_HI):
+                            continue
+                        packets.setdefault((io, port), []).append([cyc, mid])
+                    except ValueError:
+                        continue
+    return out
+
+
+def load_noc_router_logs(noc_dir):
+    """Glob the per-router full logs. `rid` is a flat router id within the
+    group (NOT tile/port -- the remapper shuffles the tile<->router
+    assignment), read from the line prefix. Returns:
+      runs[(g,rid,rr,pi,io)] = [(start,end,state)]   (from S lines)
+      packets[(g,rid,rr,pi,io)] (P lines):
+        req:  [[cyc,wen,addr,dstx,dsty,srcx,srcy,src_tile,core,meta_id]]
+        resp: [[cyc,dstx,dsty,srcx,srcy,req_tile,req_core,meta_id]]
+    Resp flits have no tgt_addr; dst_id is the requester they return to, src_id
+    the responder. The trailing meta_id is the per-request correlation id."""
+    runs, packets = {}, {}
+    for path in glob.glob(os.path.join(noc_dir, "router_g*_*.log")):
+        m = ROUTER_LOG_RE.search(os.path.basename(path))
+        if not m:  # skip tile_/pe_/... that also match the glob
+            continue
+        g = int(m.group(1))
+        rr = 0 if m.group(2) == "req" else 1
+        with open(path, "r", errors="replace") as f:
+            for line in f:
+                x = line.split()
+                if len(x) < 2:
+                    continue
+                try:
+                    # leading demux index = in-group router id
+                    rid = int(x[0])
+                except ValueError:
+                    continue
+                # the rest is the original S/P line
+                x = x[1:]
+                # S portidx io start end state
+                if len(x) == 6 and x[0] == "S":
+                    try:
+                        pi, io, s, e, st = (int(z) for z in x[1:])
+                    except ValueError:
+                        continue
+                    w = _winclip(s, e)
+                    if w:
+                        runs.setdefault(
+                            (g, rid, rr, pi, io), []).append(
+                            (w[0], w[1], st))
+                # REQ: pi io cyc wen addr dstx dsty srcx srcy stile core mid
+                elif len(x) == 13 and x[0] == "P":
+                    try:
+                        pi, io, cyc, wen = int(
+                            x[1]), int(
+                            x[2]), int(
+                            x[3]), int(
+                            x[4])
+                        if not (WIN_CYC_LO <= cyc < WIN_CYC_HI):
+                            continue
+                        rec = [
+                            cyc, wen, int(
+                                x[5], 16), int(
+                                x[6]), int(
+                                x[7]), int(
+                                x[8]), int(
+                                x[9]), int(
+                                x[10]), int(
+                                x[11]), int(
+                                    x[12])]
+                    except ValueError:
+                        continue
+                    packets.setdefault((g, rid, rr, pi, io), []).append(rec)
+                # RESP: pi io cyc dstx dsty srcx srcy rtile rcore mid
+                elif len(x) == 11 and x[0] == "P":
+                    try:
+                        pi, io, cyc = int(x[1]), int(x[2]), int(x[3])
+                        if not (WIN_CYC_LO <= cyc < WIN_CYC_HI):
+                            continue
+                        rec = [
+                            cyc, int(
+                                x[4]), int(
+                                x[5]), int(
+                                x[6]), int(
+                                x[7]), int(
+                                x[8]), int(
+                                x[9]), int(
+                                x[10])]
+                    except ValueError:
+                        continue
+                    packets.setdefault((g, rid, rr, pi, io), []).append(rec)
+    return runs, packets
+
+
+def load_noc_tile_logs(noc_dir):
+    """Glob the per-tile full logs (tile_g<g>_t<t>.log). Returns (runs,
+    packets):
+      runs[(g,t,rr,io,p)] = [(start,end,state)]   (S lines)
+      req  (P): [[cyc,wen,addr,src_grp,dst_grp,req_tile,req_core,meta_id]]
+      resp (Q): [[cyc,srcvalid,src_grp,dst_grp,req_tile,req_core,meta_id]]
+    Resp Q lines have no addr/wen; srcvalid=0 (master_resp, in) = responder
+    group unknown so only dst (x,y); srcvalid=1 (slave_resp, out) has both
+    src and dst (x,y) (linear groups)."""
+    runs, packets = {}, {}
+    for path in glob.glob(os.path.join(noc_dir, "tile_g*_t*.log")):
+        m = TILE_LOG_RE.search(os.path.basename(path))
+        if not m:
+            continue
+        g, t = int(m.group(1)), int(m.group(2))
+        with open(path, "r", errors="replace") as f:
+            for line in f:
+                x = line.split()
+                # S rr io port start end state
+                if len(x) == 7 and x[0] == "S":
+                    try:
+                        rr, io, p, s, e, st = (int(z) for z in x[1:])
+                    except ValueError:
+                        continue
+                    w = _winclip(s, e)
+                    if w:
+                        runs.setdefault(
+                            (g, t, rr, io, p), []).append(
+                            (w[0], w[1], st))
+                # REQ: io port cyc wen addr sgrp dgrp rtile rcore mid
+                elif len(x) == 11 and x[0] == "P":
+                    try:
+                        io, p, cyc, wen = int(
+                            x[1]), int(
+                            x[2]), int(
+                            x[3]), int(
+                            x[4])
+                        if not (WIN_CYC_LO <= cyc < WIN_CYC_HI):
+                            continue
+                        rec = [
+                            cyc, wen, int(
+                                x[5], 16), int(
+                                x[6]), int(
+                                x[7]), int(
+                                x[8]), int(
+                                x[9]), int(
+                                x[10])]
+                    except ValueError:
+                        continue
+                    packets.setdefault((g, t, 0, io, p), []).append(rec)
+                # RESP: io port cyc srcvalid sgrp dgrp rtile rcore mid
+                elif len(x) == 10 and x[0] == "Q":
+                    try:
+                        io, p, cyc = int(x[1]), int(x[2]), int(x[3])
+                        if not (WIN_CYC_LO <= cyc < WIN_CYC_HI):
+                            continue
+                        rec = [
+                            cyc, int(
+                                x[4]), int(
+                                x[5]), int(
+                                x[6]), int(
+                                x[7]), int(
+                                x[8]), int(
+                                x[9])]
+                    except ValueError:
+                        continue
+                    packets.setdefault((g, t, 1, io, p), []).append(rec)
+    return runs, packets
+
+
+class Flows:
+    """Transaction correlation across every packet trace, via (requester,
+    meta_id).
+
+    For a reorder-buffered requester (the Snitch load/store port) meta_id is
+    unique among that requester's OUTSTANDING requests and carried unchanged
+    end-to-end, so per (requester, meta_id) the req/resp pairs are strictly
+    ordered (a meta_id cannot be reused until its response returns), even
+    though responses across DIFFERENT meta_ids may return out of order (NUMA).
+    So we segment each (group, tile, core idx, meta_id) timeline into
+    non-overlapping [req_cyc, resp_cyc] intervals (k-th req pairs with k-th
+    resp), each given a unique Perfetto flow_id. Any packet carrying that
+    requester+meta_id inside the interval binds to the flow.
+
+    NOT every requester reorders: an in-order requester may reuse one meta_id
+    for many concurrently-outstanding requests (a stream tag, not a unique id),
+    and the interconnect re-derives the address at each hop, so no key spans
+    the path. We auto-detect such buckets (overlapping outstanding) and leave
+    them UNFLOWED -- their packets keep annotations, just no arrows.
+
+    The local-port idx is the core_id space ([0,cpt) Snitch cores)."""
+
+    INF = float("inf")
+
+    def __init__(self, pe_data):
+        # (g,t,idx) -> {meta_id: (req_cyc list, resp_cyc list, [(rc,sc,fid)])}
+        self.ix = {}
+        # (g,t,idx,meta_id) buckets that are in-order streams (no flows)
+        self.streams = set()
+        # flow ids start at 1 (0 is "no flow" for Perfetto)
+        self._next = 1
+        self.n_txn = self.n_inflight = self.n_orphan_resp = self.n_stream = 0
+        self.bound = self.unbound = self.stream_pkts = 0
+        self._build(pe_data or {}, 0)
+
+    def _build(self, data, base):
+        for (g, t, sub), (_runs, pkts) in data.items():
+            idx = base + sub
+            req_by_m = collections.defaultdict(list)
+            resp_by_m = collections.defaultdict(list)
+            for rec in pkts.get((1, 0), []):     # req  [cyc,wen,addr,meta_id]
+                req_by_m[rec[3]].append(rec[0])
+            for rec in pkts.get((0, 0), []):     # resp [cyc,meta_id]
+                resp_by_m[rec[1]].append(rec[0])
+            d = {}
+            for m, rc in req_by_m.items():
+                rcs = sorted(rc)
+                resp = sorted(resp_by_m.get(m, []))
+                scs = [
+                    resp[k] if k < len(resp) else self.INF for k in range(
+                        len(rcs))]
+                # In-order STREAM detection: a request issued before the
+                # previous response of the same (requester, meta_id) returned
+                # => >1 concurrent outstanding => meta_id is reused as a stream
+                # tag, not a unique reorder id. Such a bucket has no
+                # per-request identity to follow (and the address is re-derived
+                # per hop), so we do NOT fabricate flows -- its packets keep
+                # annotations, no arrows. Loads keep a unique meta_id per
+                # outstanding, so they never trip this.
+                if any(rcs[k + 1] < scs[k] for k in range(len(rcs) - 1)):
+                    self.streams.add((g, t, idx, m))
+                    self.n_stream += len(rcs)
+                    continue
+                ivs = []
+                for k, rcyc in enumerate(rcs):
+                    ivs.append((rcyc, scs[k], self._next))
+                    self._next += 1
+                    if scs[k] is self.INF:
+                        self.n_inflight += 1
+                self.n_txn += len(rcs)
+                if len(resp) > len(
+                        rcs):         # resp with no preceding req (trace edge)
+                    self.n_orphan_resp += len(resp) - len(rcs)
+                # intervals are non-overlapping and ordered, so the resp-cyc
+                # list can be bisected directly; inf (in-flight) sorts last.
+                d[m] = (rcs, [iv[1] for iv in ivs], ivs)
+            self.ix[(g, t, idx)] = d
+
+    def fid(self, g, t, idx, meta_id, cyc, is_resp=False):
+        """Resolve the flow_id for a packet at `cyc` carrying (requester,
+        meta_id). Intervals share boundaries when a meta_id is reused
+        immediately, so disambiguate by direction: a request-side packet binds
+        to the latest interval whose req has started (req_cyc <= cyc); a
+        response-side packet to the earliest interval whose resp ends at/after
+        cyc. Bounds are EXACT and no slack is allowed, else a 1-cycle gap
+        between back-to-back transactions would pull a packet into the wrong
+        flow. Returns None (counted unbound) if cyc lands in no interval;
+        in-order stream buckets are deliberately not flowed."""
+        # in-order stream: keep annotations, no arrows
+        if (g, t, idx, meta_id) in self.streams:
+            self.stream_pkts += 1
+            return None
+        ent = self.ix.get((g, t, idx), _EMPTY).get(meta_id)
+        if ent:
+            rcs, scs, ivs = ent
+            i = bisect.bisect_left(
+                scs, cyc) if is_resp else bisect.bisect_right(
+                rcs, cyc) - 1
+            if 0 <= i < len(ivs):
+                rcyc, scyc, fid = ivs[i]
+                if rcyc <= cyc <= scyc:
+                    self.bound += 1
+                    return fid
+        self.unbound += 1
+        return None
+
+    def report(self):
+        return (f"  flows: {self.n_txn} transactions / "
+                f"{self._next - 1} flow ids; "
+                f"{self.bound} packet-hops bound, {self.unbound} unbound "
+                f"(DMA/uncorrelated), "
+                f"{self.stream_pkts} in in-order streams (annotated, not "
+                f"flowed: "
+                f"{len(self.streams)} streams / {self.n_stream} txns); "
+                f"{self.n_inflight} in-flight at EOS, {self.n_orphan_resp} "
+                f"orphan resp")
+
+
+_EMPTY = {}
+
+
+def _ensure(builder, uu, key, name, parent_key=None):
+    """Idempotent container track (deduped via uu._seen). Returns its uuid."""
+    if key not in uu._seen:
+        parent = uu.get(parent_key) if parent_key is not None else None
+        add_track(builder, uu.get(key), name, parent=parent)
+        uu._seen.add(key)
+    return uu.get(key)
+
+
+def _emit_state_slices(rl, leaf, rr, builder, args, only=None):
+    """One colored slice per non-idle run. Idle (st==0) is DROPPED so the gap
+    renders as Perfetto's neutral grey (the protobuf has no per-slice color
+    field). `only` (a set of state codes) restricts which states are drawn --
+    packet mode passes {1} to keep the stall runs. Returns #emitted."""
+    n = 0
+    for s, e, st in sorted(rl):
+        if st == 0:                              # idle -> leave a grey gap
+            continue
+        if only is not None and st not in only:
+            continue
+        emit_slice_begin(builder, s * TICK, leaf, noc_state_name(rr, st))
+        emit_slice_end(builder, e * TICK, leaf)
+        n += 1
+    return n
+
+
+def _req_eng(core, cpt):
+    """Render an originating local-port id as a core (C{core})."""
+    return f"C{core}"
+
+
+def _emit_req_packet_slices(
+        rl,
+        recs,
+        leaf,
+        rr,
+        builder,
+        args,
+        is_router=True,
+        pe=False,
+        show_xy=True,
+        is_resp=False,
+        flows=None,
+        req_ctx=None,
+        flow_rank=0):
+    """Packet granularity for a REQUEST port: per-request read/write slices
+    (address + routing on hover) MERGED with the stall runs and emitted in
+    start-time order. Merging is REQUIRED: stall and packet slices share
+    boundary timestamps, and two separate passes make Perfetto's timestamp sort
+    nest the stall INSIDE the just-closed packet (a malformed marker arrow).
+    Every NoC packet is annotated with src (x,y), dst (x,y), and the
+    originating requester as a LINEAR G<group> T<tile> C<port>. Layout:
+      router req =[cyc,wen,addr,dstx,dsty,srcx,srcy,src_tile,core,meta_id]
+      router resp=[cyc,dstx,dsty,srcx,srcy,req_tile,req_core,meta_id] (is_resp)
+      tile req =[cyc,wen,addr,src_grp,dst_grp,req_tile,req_core,meta_id]
+      tile resp  =[cyc,srcvalid,src_grp,dst_grp,req_tile,req_core,meta_id]
+      pe    =[cyc,wen,addr,meta_id]  (meta_id is rec[-1] in every layout)
+    A RESPONSE flit carries no address; src=responder, dst=the requester it
+    returns to."""
+    ny = args.mesh_y
+    cpt = args.cores_per_tile
+    # items carry a 5th field = flow_id (None for stall runs and when --flows
+    # is off). The requester key (group,tile,idx) is read straight from the
+    # packet's own fields, so every hop binds independently.
+    items = [(s, e, "stall", None, None) for s, e, st in rl if st == 1]
+    for rec in recs:
+        mid = rec[-1]
+        # ROUTER resp flit: no addr; src=responder, dst=requester
+        if is_resp and is_router:
+            cyc, dstx, dsty, srcx, srcy, tile, core = rec[:7]
+            annos = [("src (x,y)", f"({srcx},{srcy})"),
+                     ("dst (x,y)", f"({dstx},{dsty})"),
+                     ("requester",
+                      f"G{dstx * ny + dsty} T{tile} {_req_eng(core, cpt)}"),
+                     ("meta_id", str(mid)), ("op", "resp")]
+            fid = flows.fid(dstx * ny + dsty, tile, core, mid,
+                            cyc, is_resp=True) if flows else None
+            items.append((cyc, cyc + 1, "resp", annos, fid))
+            continue
+        # TILE resp: src/dst are linear groups (src only if srcvalid)
+        if is_resp:
+            cyc, srcvalid, src_grp, dst_grp, req_tile, core = rec[:6]
+            annos = []
+            # local port (show_xy=False) hides both
+            if show_xy:
+                # master_resp (srcvalid=0): responder group unknown
+                if srcvalid:
+                    annos.append(
+                        ("src (x,y)", f"({src_grp // ny},{src_grp % ny})"))
+                annos.append(
+                    ("dst (x,y)", f"({dst_grp // ny},{dst_grp % ny})"))
+            annos += [("requester",
+                       f"G{dst_grp} T{req_tile} {_req_eng(core, cpt)}"),
+                      ("meta_id",
+                       str(mid)),
+                      ("op",
+                       "resp")]
+            fid = flows.fid(dst_grp, req_tile, core, mid, cyc,
+                            is_resp=True) if flows else None
+            items.append((cyc, cyc + 1, "resp", annos, fid))
+            continue
+        cyc, wen, addr = rec[0], rec[1], rec[2]
+        op = "write" if wen else "read"
+        # requester is the port itself (req_ctx)
+        if pe:
+            annos = [("addr", f"0x{addr:x}"), ("op", op)]
+            rg, rt, ridx = req_ctx
+        # src/dst already mesh (x,y)
+        elif is_router:
+            dstx, dsty, srcx, srcy, src_tile, core = rec[3:9]
+            annos = [("addr", f"0x{addr:x}"),
+                     ("src (x,y)", f"({srcx},{srcy})"),
+                     ("dst (x,y)", f"({dstx},{dsty})"),
+                     ("requester",
+                     f"G{srcx * ny + srcy} T{src_tile} {_req_eng(core, cpt)}"),
+                     ("op", op)]
+            rg, rt, ridx = srcx * ny + srcy, src_tile, core
+        # tile: src/dst groups linear -> mesh (x,y)
+        else:
+            src_grp, dst_grp, req_tile, core = rec[3:7]
+            annos = [("addr", f"0x{addr:x}")]
+            # local port stays in-group: src/dst (x,y) is redundant
+            if show_xy:
+                annos += [("src (x,y)", f"({src_grp // ny},{src_grp % ny})"),
+                          ("dst (x,y)", f"({dst_grp // ny},{dst_grp % ny})")]
+            annos += [("requester",
+                       f"G{src_grp} T{req_tile} {_req_eng(core, cpt)}"),
+                      ("op", op)]
+            rg, rt, ridx = src_grp, req_tile, core
+        annos.append(("meta_id", str(mid)))
+        fid = flows.fid(rg, rt, ridx, mid, cyc) if flows else None
+        items.append((cyc, cyc + 1, op, annos, fid))
+    for s, e, name, annos, fid in sorted(
+            items, key=lambda x: x[0]):  # start-time order (starts unique)
+        emit_slice_begin(
+            builder,
+            s * TICK,
+            leaf,
+            name,
+            annos,
+            flow_id=fid,
+            rank=flow_rank)
+        emit_slice_end(builder, e * TICK, leaf)
+    return len(items)
+
+
+def _emit_port(
+        builder,
+        uu,
+        leaf_key,
+        leaf_name,
+        parent_key,
+        rl,
+        rr,
+        win,
+        args,
+        pkts=None,
+        is_router=True,
+        show_xy=True,
+        is_resp=False,
+        flows=None,
+        flow_rank=0):
+    """One NoC port-side, laid out like a Core: the traffic state slices are
+    drawn ON the port's own line, and its statistics hang under it as
+    expandable counter children, computed INDIVIDUALLY for this port-side,
+    windowed, as PER-CYCLE fractions (bw = handshake/win, stall = stalled/win,
+    util = (handshake+stalled)/win = bw+stall). Returns #traffic slices."""
+    import collections
+    leaf = add_track(
+        builder,
+        uu.get(leaf_key),
+        leaf_name,
+        parent=uu.get(parent_key))
+    ctr = {m: add_track(builder, uu.get(leaf_key + (m,)), m,
+                        parent=leaf, counter=True) for m in NOC_PORT_METRICS}
+    # state granularity (default)
+    if pkts is None:
+        nsl = _emit_state_slices(rl, leaf, rr, builder, args)
+    # packet granularity (request port):
+    else:
+        nsl = _emit_req_packet_slices(
+            rl,
+            pkts,
+            leaf,
+            rr,
+            builder,
+            args,
+            is_router=is_router,
+            show_xy=show_xy,
+            is_resp=is_resp,
+            flows=flows,
+            flow_rank=flow_rank)
+    # NOTE: stats below are ALWAYS derived from the state runs (rl),
+    # independent of slice granularity.
+    # window -> [handshake_cyc, stall_cyc]
+    acc = collections.defaultdict(lambda: [0, 0])
+    maxw = -1
+    for s, e, st in rl:
+        if st == 0:                                  # idle adds nothing
+            continue
+        w = s // win
+        while w * win < e:
+            d = min(e, (w + 1) * win) - max(s, w * win)
+            # st>=2 handshake (read/write/hsk), st==1 stall
+            acc[w][0 if st >= 2 else 1] += d
+            if w > maxw:
+                maxw = w
+            w += 1
+    # change-detected emit (sample-and-hold)
+    last = {}
+    for w in range(maxw + 1):
+        ts = w * win * TICK
+        hsk, stall = acc.get(w, (0, 0))
+        for m, val in (("bw [flit/cyc]", hsk / win),
+                       ("stall [cyc/cyc]", stall / win),
+                       ("util", (hsk + stall) / win)):
+            if last.get(m) != val:
+                emit_counter(builder, ts, ctr[m], val)
+                last[m] = val
+    # Drop to 0 one window past the last active window, else sample-and-hold
+    # smears the last value across the idle tail.
+    if maxw >= 0:
+        ts_close = (maxw + 1) * win * TICK
+        for m in NOC_PORT_METRICS:
+            if last.get(m):
+                emit_counter(builder, ts_close, ctr[m], 0.0)
+    else:  # fully-idle port: one 0 baseline at t0
+        for m in NOC_PORT_METRICS:
+            emit_counter(builder, 0, ctr[m], 0.0)
+    # Pin every counter's y-axis to [0,1] with a blip at the end of the
+    # timeline (all ports share the flush cycle, so it sits at the far right).
+    if not args.free_range:
+        pin_counter_range(
+            builder, ctr.values(), max(
+                e for _, e, _ in rl) * TICK, TICK)
+    return nsl
+
+
+def _emit_pe_resp_packets(rl, recs, leaf, builder, args, flows, req_ctx):
+    """The originating port's RESPONSE side as per-packet slices
+    (rec=[cyc,meta_id]), merged with stall runs. Each response is the LAST hop
+    of its transaction, so it carries the flow's terminating arrow (no dangling
+    outgoing flow). It is emitted in pipeline order AFTER the same-cycle
+    router-resp-out and tile-resp-in (rank 3), so insertion-order tie-break
+    makes it uniquely the LAST slice of its flow."""
+    g, t, idx = req_ctx
+    items = [(s, e, "stall", None, None, False) for s, e, st in rl if st == 1]
+    for cyc, mid in recs:
+        fid = flows.fid(g, t, idx, mid, cyc, is_resp=True) if flows else None
+        items.append((cyc, cyc + 1, "resp",
+                     [("meta_id", str(mid)), ("op", "resp")],
+                     fid, fid is not None))
+    for s, e, name, annos, fid, term in sorted(items, key=lambda x: x[0]):
+        emit_slice_begin(
+            builder,
+            s * TICK,
+            leaf,
+            name,
+            annos,
+            flow_id=fid,
+            terminating=term,
+            rank=3)  # terminator = sink, last in the cycle
+        emit_slice_end(builder, e * TICK, leaf)
+    return len(items)
+
+
+def process_noc_routers(noc_dir, builder, uu, args, flows=None):
+    """NoC routers laid out like the core view: one LINE per router port-side
+    ({N/E/S/W/local} {in|out}) carrying its traffic slices, with util/bw/stall
+    as expandable counter children. Hierarchy: NoC routers > Group > Router >
+    port-side line. Routers carry a flat group router id from the file name
+    (NOT tile/port -- remapping makes the tile<->router association
+    meaningless). Leaves are local-first so the stall-heavy ejection port
+    surfaces above the mesh links."""
+    runs, packets = load_noc_router_logs(
+        noc_dir)        # runs:(g,rid,rr,pi,io)  packets:(g,rid,pi,io)
+    if not runs:
+        print(
+            f"  NoC routers: no router_g*_r*_*.log in {noc_dir}; skipping",
+            file=sys.stderr)
+        return 0
+    win = max(1, int(round(args.window_ns / args.clk_ns)))
+    groups = sorted({k[0] for k in runs})
+    # zero-pad router id for lexicographic order
+    rpad = len(str(max((k[1] for k in runs), default=0)))
+
+    # local (pi=4) first within a router
+    def leaf_order(item):
+        (g, rid, rr, pi, io), _ = item
+        return (g, rid, rr, 0 if pi == 4 else 1, pi, io)
+
+    # packet granularity (chosen at export): per-flit slices on REQUEST
+    # (read/write + addr) AND RESPONSE (src/dst + requester) ports.
+    packet_mode = args.noc_slices == "packet"
+
+    nsl = nports = 0
+    for (g, rid, rr, pi, io), rl in sorted(runs.items(), key=leaf_order):
+        _ensure(builder, uu, ("nr",), "3 NoC routers")
+        _ensure(builder, uu, ("nr_g", g), _gname(g), ("nr",))
+        _ensure(
+            builder, uu, ("nr_p", g, rid, rr),
+            f"Router {rid:0{rpad}d} {NOC_NET[rr]}", ("nr_g", g))
+        pk = packets.get((g, rid, rr, pi, io), []) if packet_mode else None
+        nsl += _emit_port(
+            builder, uu, ("nr_l", g, rid, rr, pi, io),
+            f"{NOC_PORTIDX[pi]} {NOC_IO[io]}", ("nr_p", g, rid, rr),
+            rl, rr, win, args, pkts=pk, is_router=True, is_resp=(rr == 1),
+            flows=flows,
+            flow_rank=(1 if io == 1 else 2))  # out=send(1), in=recv(2)
+        nports += 1
+    gran = "packet" if packet_mode else "state"
+    print(f"  NoC routers: {len(groups)} groups, "
+          f"{nports} port-side lines, {nsl} slices "
+          f"({gran} granularity; util/bw/stall expandable)")
+    return nports
+
+
+def process_noc_tiles(noc_dir, builder, uu, args, flows=None):
+    """NoC tiles laid out like the core view: one LINE per tile port-side
+    ({in|out} {local|remoteN}) carrying its traffic slices, with util/bw/stall
+    as expandable counter children. Hierarchy: NoC tiles > Group > Tile >
+    {REQ|RESP} > port-side line."""
+    runs, packets = load_noc_tile_logs(
+        noc_dir)          # runs:(g,t,rr,io,p)  packets:(g,t,io,p)
+    if not runs:
+        print(
+            f"  NoC tiles: no tile_g*_t*.log in {noc_dir}; skipping",
+            file=sys.stderr)
+        return 0
+    win = max(1, int(round(args.window_ns / args.clk_ns)))
+    groups = sorted({k[0] for k in runs})
+    # per-request slices on req ports
+    packet_mode = args.noc_slices == "packet"
+    nsl = nports = 0
+    for (g, t, rr, io, p), rl in sorted(runs.items()):
+        _ensure(builder, uu, ("nt",), "2 NoC tiles")
+        _ensure(builder, uu, ("nt_g", g), _gname(g), ("nt",))
+        _ensure(builder, uu, ("nt_t", g, t), _tname(t), ("nt_g", g))
+        _ensure(builder, uu, ("nt_n", g, t, rr), NOC_NET[rr], ("nt_t", g, t))
+        leaf_name = f"{NOC_IO[io]} " + ("local" if p == 0 else f"remote{p}")
+        pk = packets.get((g, t, rr, io, p), []) if packet_mode else None
+        nsl += _emit_port(
+            builder, uu, ("nt_l", g, t, rr, io, p), leaf_name,
+            ("nt_n", g, t, rr), rl, rr, win, args, pkts=pk,
+            is_router=False,
+            # tile local port (p==0): in-group, hide src/dst (x,y)
+            show_xy=(p != 0),
+            # resp ports use the Q-line recs (src/dst + requester + op)
+            is_resp=(rr == 1),
+            # out=send(1), in=recv(2)
+            flows=flows, flow_rank=(1 if io == 1 else 2))
+        nports += 1
+    gran = "packet" if packet_mode else "state"
+    print(f"  NoC tiles: {len(groups)} groups, "
+          f"{nports} port-side lines, {nsl} slices "
+          f"({gran} granularity; util/bw/stall expandable)")
+    return nports
+
+
+def _emit_bank_packets(rl, recs, leaf, bg, bt, builder, args, flows=None):
+    """SPM bank accesses (packet granularity): per-access read/write slice
+    (address + the requester that won the bank on hover) merged with the bank's
+    stall runs, start-sorted (same anti-nesting reason as
+    _emit_req_packet_slices). The requester uses the SAME uniform
+    "G<grp> T<tile> C<idx>" format as NoC packets (no local/remote/DMA words):
+    a true local input is named by the bank's own (bg,bt) + the winning port
+    index, since local requests zero their payload src fields; remote NoC and
+    wide DMA carry the origin in sg/it/core. DMA/wide accesses have no core
+    flow -> they stay unbound."""
+    cpt = args.cores_per_tile
+
+    # (group, tile, local-port idx) + label
+    def _req(loc, wide, port, sg, it, core):
+        if loc and not wide:                     # this tile's own core port
+            return (bg, bt, port), f"G{bg} T{bt} {_req_eng(port, cpt)}"
+        return (sg, it, core), f"G{sg} T{it} {_req_eng(core, cpt)}"
+
+    items = [(s, e, "stall", None, None) for s, e, st in rl if st == 1]
+    for cyc, wen, addr, loc, wide, port, sg, it, core, meta_id in recs:
+        op = "write" if wen else "read"
+        (rg, rt, ridx), who = _req(loc, wide, port, sg, it, core)
+        # wide = a 512-bit DMA burst (separate initiator, no core flow); don't
+        # even probe, to keep the unbound count clean.
+        fid = flows.fid(
+            rg, rt, ridx, meta_id, cyc) if (
+            flows and not wide) else None
+        items.append((cyc,
+                      cyc + 1,
+                      op,
+                      [("addr",
+                        f"0x{addr:x}"),
+                          ("requester",
+                           who),
+                          ("meta_id",
+                           str(meta_id)),
+                          ("op",
+                           op)],
+                      fid))
+    for s, e, name, annos, fid in sorted(items, key=lambda x: x[0]):
+        emit_slice_begin(
+            builder,
+            s * TICK,
+            leaf,
+            name,
+            annos,
+            flow_id=fid,
+            rank=3)  # bank = sink
+        emit_slice_end(builder, e * TICK, leaf)
+    return len(items)
+
+
+def process_spm_banks(spm_dir, builder, uu, args, flows=None):
+    """Per-SPM-bank access trace under each Tile node (NoC tiles › Group › Tile
+    › SPM banks › bank N). Explains slave_req-in stalls: who won each contended
+    bank. Follows --noc-slices (state = read/write/stall runs; packet =
+    per-access slice with address + requester). No bw/util counters."""
+    banks = load_spm_bank_logs(spm_dir)
+    if not banks:
+        print(
+            f"  SPM banks: no bank_g*_t*.log in {spm_dir}; skipping",
+            file=sys.stderr)
+        return 0
+    packet_mode = args.noc_slices == "packet"
+    bpad = len(str(max((b for runs, _ in banks.values()
+               for b in runs), default=0)))
+    nb = ntile = 0
+    for (g, t), (runs, packets) in sorted(banks.items()):
+        _ensure(builder, uu, ("nt",), "2 NoC tiles")
+        _ensure(builder, uu, ("nt_g", g), _gname(g), ("nt",))
+        _ensure(builder, uu, ("nt_t", g, t), _tname(t), ("nt_g", g))
+        _ensure(builder, uu, ("nt_spm", g, t), "SPM banks", ("nt_t", g, t))
+        for bank in sorted(runs):
+            leaf = add_track(
+                builder,
+                uu.get(("nt_bank", g, t, bank)),
+                f"bank {bank:0{bpad}d}",
+                parent=uu.get(("nt_spm", g, t)))
+            if packet_mode and bank in packets:
+                _emit_bank_packets(
+                    runs[bank],
+                    packets[bank],
+                    leaf,
+                    g,
+                    t,
+                    builder,
+                    args,
+                    flows=flows)
+            else:  # rr=0 -> read/write/stall naming
+                _emit_state_slices(runs[bank], leaf, 0, builder, args)
+            nb += 1
+        ntile += 1
+    print(f"  SPM banks: {nb} bank tracks across {ntile} tiles "
+          f"({'packet' if packet_mode else 'state'} granularity)")
+    return nb
+
+
+def main():
+    ap = argparse.ArgumentParser("perfetto_gen")
+    ap.add_argument("traces", nargs="+", help="trace_hart_*.dasm files")
+    ap.add_argument("-o", "--output", default="perf.perfetto-trace")
+    ap.add_argument("--cores-per-tile", type=int, default=4)
+    ap.add_argument("--tiles-per-group", type=int, default=4)
+    ap.add_argument(
+        "--mesh-y",
+        type=int,
+        default=1,
+        help="NoC mesh Y dimension (NumY = NumGroups / NumX). "
+        "A linear group g maps "
+        "to mesh (g // mesh_y, g %% mesh_y); used to render src/dst (x,y) on "
+        "NoC "
+        "packets. Pass from config (Makefile does) or src/dst (x,y) will be "
+        "wrong.")
+    ap.add_argument("--window-ns", type=int, default=1000,
+                    help="counter window in ns (default 1000 = 500 cycles)")
+    ap.add_argument(
+        "--clk-freq",
+        type=float,
+        default=500.0,
+        help="clock frequency in MHz (default 500 -> 2.0 ns/cycle). "
+        "The timeline "
+        "axis is REAL ns = cycle * (1000 / clk_freq); 1 cycle therefore spans "
+        "the true clock period, not a misleading 1 ns.")
+    ap.add_argument(
+        "--clk-period",
+        "--clk-ns",
+        type=float,
+        default=None,
+        dest="clk_ns",
+        help="clock period in ns -- overrides --clk-freq if given "
+        "(e.g. --clk-period 1.25 for 800 MHz).")
+    ap.add_argument("--slices", choices=["none", "function", "instruction"],
+                    default="function",
+                    help="timeline slices: none, function (default), or "
+                         "instruction (per-insn disasm; heavy at scale)")
+    ap.add_argument("--filter-benchmark", action="store_true",
+                    help="only emit between mempool_start/stop_benchmark")
+    ap.add_argument(
+        "--elf",
+        help="elf for addr2line (default: from transcript)")
+    ap.add_argument(
+        "--addr2line",
+        help="addr2line path (default: auto-detect)")
+    ap.add_argument(
+        "--spike-dasm",
+        help="spike-dasm path (default: auto-detect)")
+    ap.add_argument(
+        "--noc", help="noc_profiling/ dir (router_g*/tile_g* full logs); "
+        "overlays NoC state-runs + derived counters on the timeline")
+    ap.add_argument(
+        "--spm", help="spm_profiling/ dir (bank_g*_t*.log); adds per-SPM-bank "
+        "access tracks under each Tile node (needs --noc for the tiles)")
+    ap.add_argument(
+        "--cycle-start",
+        type=int,
+        default=0,
+        help="export only cycles >= this (frequency-independent; default 0)")
+    ap.add_argument(
+        "--cycle-end",
+        type=int,
+        default=None,
+        help="export only cycles < this (default: end of run). "
+        "Windowing DROPS "
+        "out-of-range data, shrinking the trace/DB for fast load + click")
+    ap.add_argument(
+        "--free-range",
+        action="store_true",
+        help="let counter y-axes auto-scale to their data range "
+        "(default: every fraction counter is pinned to [0,1])")
+    ap.add_argument(
+        "--noc-slices",
+        choices=[
+            "state",
+            "packet"],
+        default="state",
+        help="NoC request-port traffic granularity (chosen here, like "
+        "--slices function|instruction -- the per-router/tile logs "
+        "always carry both): 'state' (default) = idle/stall/read/write "
+        "runs; 'packet' = one slice per request flit w/ address + target XY")
+    ap.add_argument(
+        "--flows",
+        action="store_true",
+        help="correlate packets into Perfetto flows via (requester, meta_id): "
+        "click any NoC/bank packet to follow arrows to the originating "
+        "core request and back. Requires --noc-slices packet.")
+    args = ap.parse_args()
+
+    # ns per cycle (honest real-ns axis)
+    global TICK
+    if args.clk_ns is None:  # derive period from frequency
+        args.clk_ns = 1000.0 / args.clk_freq
+    TICK = float(args.clk_ns)
+    print(f"  clock: {args.clk_freq:g} MHz -> {args.clk_ns:g} ns/cycle "
+          f"(timeline axis in real ns; flow order via rank, not time)")
+
+    files = []
+    for pat in args.traces:
+        files.extend(sorted(glob.glob(pat)) if any(ch in pat for ch in "*?[")
+                     else [pat])
+
+    # export window (cycles); drops the rest
+    global WIN_CYC_LO, WIN_CYC_HI
+    WIN_CYC_LO = max(0, args.cycle_start)
+    WIN_CYC_HI = args.cycle_end if args.cycle_end is not None else (1 << 62)
+    if WIN_CYC_LO or args.cycle_end is not None:
+        print(f"  window: cycles [{WIN_CYC_LO}, "
+              f"{WIN_CYC_HI if args.cycle_end is not None else 'end'})")
+
+    # Zero-pad widths so the lexicographic UI order matches numeric order
+    # (Tile 00..15).
+    global PAD_G, PAD_T, PAD_H, MESH_NY
+    MESH_NY = max(1, args.mesh_y)
+    harts = [int(m.group(1), 16)
+             for m in (HART_RE.search(p) for p in files) if m]
+    cpg = max(1, args.cores_per_tile * args.tiles_per_group)
+    PAD_H = len(str(max(harts))) if harts else 2
+    PAD_G = len(str(max(harts) // cpg)) if harts else 2
+    PAD_T = len(str(max(1, args.tiles_per_group - 1)))
+
+    if args.slices != "none" or args.filter_benchmark:
+        args.elf = args.elf or detect_elf(files)
+        args.addr2line = find_tool(
+            args.addr2line, [
+                "riscv32-unknown-elf-addr2line", "addr2line"])
+        if not args.elf or not args.addr2line:
+            print(f"  WARNING: function/source names need elf+addr2line "
+                  f"(elf={args.elf}, addr2line={args.addr2line}); "
+                  f"slices unnamed, --filter-benchmark may drop everything",
+                  file=sys.stderr)
+    if args.slices == "instruction":
+        args.spike_dasm = find_tool(args.spike_dasm, ["spike-dasm"])
+        if not args.spike_dasm:
+            print("  WARNING: spike-dasm not found; instruction slices will "
+                  "show raw DASM(hex)", file=sys.stderr)
+
+    builder = TraceProtoBuilder()
+    uu = Uuids()
+    a2l = Addr2Line(args.addr2line, args.elf)
+
+    pe_data = load_pe_logs(args.noc) if args.noc else {
+    }    # per-core PE port traffic
+    flows = None
+    if args.flows:  # flows only in packet mode
+        if args.noc_slices != "packet":
+            print(
+                "  WARNING: --flows needs --noc-slices packet; flows disabled",
+                file=sys.stderr)
+        else:
+            flows = Flows(pe_data)
+    n = 0
+    for path in files:
+        m = HART_RE.search(path)
+        if not m:
+            print(f"skip (no hart id): {path}", file=sys.stderr)
+            continue
+        process_dasm(path, int(m.group(1), 16), builder,
+                     uu, args, a2l, pe_data, flows=flows)
+        n += 1
+    if pe_data:
+        print(
+            f"  PE ports: attached {len(pe_data)} core port "
+            "traces under Core nodes")
+    if args.noc:
+        # Tiles BEFORE routers so the root order is Core / NoC tiles / NoC
+        # routers: a memory access enters/exits the mesh at the tile, so
+        # keeping tiles adjacent to the cores makes the
+        # req->tile->router->tile->bank flow read top-to-bottom.
+        process_noc_tiles(args.noc, builder, uu, args, flows=flows)
+        process_noc_routers(args.noc, builder, uu, args, flows=flows)
+    if args.spm:  # per-SPM-bank tracks under the tiles
+        process_spm_banks(args.spm, builder, uu, args, flows=flows)
+    if flows:
+        print(flows.report())
+
+    # write buffered events in (ts, phase, rank) order
+    flush_events(builder)
+    with open(args.output, "wb") as f:
+        f.write(builder.serialize())
+    per_group = args.cores_per_tile * args.tiles_per_group
+    groups = (n + per_group - 1) // per_group
+    print(f"wrote {args.output}: {n} cores -> {groups} groups x "
+          f"{args.tiles_per_group} tiles/group x {args.cores_per_tile} "
+          f"cores/tile, slices={args.slices}, "
+          f"{len(builder.trace.packet)} packets")
+    if n % per_group:
+        print(f"  WARNING: {n} cores not divisible by {per_group} cores/group "
+              f"-- check --cores-per-tile/--tiles-per-group (or pass "
+              f"config=<flavor> to make)", file=sys.stderr)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/hardware/scripts/vcs/dump_all.tcl b/hardware/scripts/vcs/dump_all.tcl
new file mode 100644
index 00000000..4feb2aca
--- /dev/null
+++ b/hardware/scripts/vcs/dump_all.tcl
@@ -0,0 +1,9 @@
+# Copyright 2021 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Headless full-signal FSDB dump (no GUI). Like run.tcl but skips the nWave
+# window population (the wv* commands need the Verdi GUI).
+dump -file mempool.fsdb -type FSDB
+dump -add /mempool_tb -depth 0 -aggregates -fsdb_opt +mda+packedmda+struct
+run
\ No newline at end of file
diff --git a/hardware/scripts/vcs/run.tcl b/hardware/scripts/vcs/run.tcl
index e60f4829..cb29716b 100644
--- a/hardware/scripts/vcs/run.tcl
+++ b/hardware/scripts/vcs/run.tcl
@@ -2,5 +2,17 @@
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 
-do ./wave.tcl
+# VCS + Verdi run script. Under `-verdi` the simv `-do` file is played by Verdi's
+# TclPlay console, which runs both simulator (dump/run) and Verdi/nWave commands.
+#
+#   1. Full-signal FSDB dump (= QuestaSim `log -r *`): -depth 0 = all levels,
+#      -aggregates keeps structs/arrays, -fsdb_opt also captures memories.
+dump -file mempool.fsdb -type FSDB
+dump -add /mempool_tb -depth 0 -aggregates -fsdb_opt +mda+packedmda+struct
+
+#   2. Populate nWave. wave.tcl uses Verdi-only console commands, so source it
+#      here (under -verdi), not via -ucli.
+source ../scripts/vcs/wave.tcl
+
+#   3. Run until the testbench's $finish.
 run
diff --git a/hardware/scripts/vcs/wave.tcl b/hardware/scripts/vcs/wave.tcl
index 97fb29d3..5c1fa6fe 100644
--- a/hardware/scripts/vcs/wave.tcl
+++ b/hardware/scripts/vcs/wave.tcl
@@ -2,117 +2,34 @@
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 
-# Create an nWave window
-wvCreateWindow
-
-# Add a vector of the core's wfi signal to quickly see which cores are active
-wvAddGroup wfi
-wvAddSignal -group {wfi {mempool_tb/wfi}}
-
-# Add min function (DVE does not support TCL8.5)
-proc min args {
-    set minval [lindex args 0]
-    foreach arg $args {
-        if { $arg < $minval } {
-            set minval $arg
-        }
-    }
-    return $minval
-}
-
-# Add all cores from group 0 tile 0
-set group 0
-set tile 0
-for {set core 0}  {$core < [min 4 [get -radix dec mempool_pkg::NumCoresPerTile]]} {incr core} {
-    source ../scripts/vcs/wave_core.tcl
-}
-
-# Add specific cores from different tiles
-set group 1
-set tile 0
-set core 0
-source ../scripts/vcs/wave_core.tcl
-
-# Add groups
-for {set group 0} {$group < [get -radix dec mempool_pkg::NumGroups]} {incr group} {
-    # Create the group
-    wvAddGroup group\[$group\]
-
-    # Add tiles
-    for {set tile 0} {$tile < [min 2 [get -radix dec mempool_pkg::NumTilesPerGroup]]} {incr tile} {
-        source ../scripts/vcs/wave_tile.tcl
-    }
-
-    # Interconnects
-    for {set tgtgroup 0} {$tgtgroup < [get -radix dec mempool_pkg::NumGroups]} {incr tgtgroup} {
-        if {$tgtgroup != $group} {
-            set interco_idx [expr $group ^ $tgtgroup]
-            wvSelectGroup group\[$group\]
-            wvAddSubGroup interconnect_to_group\[$tgtgroup\]
-            wvSetPosition [subst {(group\[$group\]/interconnect_to_group\[$tgtgroup\] last)}]
-
-            wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/clk_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/rst_ni \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_valid_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_ready_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_tgt_addr_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_wen_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_wdata_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_be_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/resp_valid_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/resp_ready_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/resp_rdata_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_valid_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_ready_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_ini_addr_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_tgt_addr_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_wen_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_wdata_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/req_be_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/resp_valid_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/resp_ready_o \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/resp_ini_addr_i \
-                        mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_remote_interco\[$interco_idx\]/i_remote_interco/resp_rdata_i
-        }
-    }
-
-    wvSelectGroup group\[$group\]
-    wvAddSubGroup local_interconnect
-    wvSetPosition [subst {(group\[$group\]/local_interconnect last)}]
-
-    wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/clk_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/rst_ni \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_valid_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_ready_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_tgt_addr_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_wen_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_wdata_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_be_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/resp_valid_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/resp_ready_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/resp_rdata_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_valid_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_ready_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_ini_addr_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_tgt_addr_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_wen_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_wdata_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/req_be_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/resp_valid_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/resp_ready_o \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/resp_ini_addr_i \
-                mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/i_local_interco/resp_rdata_i
-}
-
-wvAddGroup Control_Registers
-wvSetPosition {(Control_Registers last)}
-wvAddSignal mempool_tb/dut/i_ctrl_registers/clk_i \
-            mempool_tb/dut/i_ctrl_registers/rst_ni \
-            mempool_tb/dut/i_ctrl_registers/axi_lite_slave_req_i \
-            mempool_tb/dut/i_ctrl_registers/axi_lite_slave_resp_o \
-            mempool_tb/dut/i_ctrl_registers/eoc_o \
-            mempool_tb/dut/i_ctrl_registers/eoc_valid_o \
-            mempool_tb/dut/i_ctrl_registers/wake_up_o \
-            mempool_tb/dut/i_ctrl_registers/tcdm_start_address_o \
-            mempool_tb/dut/i_ctrl_registers/tcdm_end_address_o \
-            mempool_tb/dut/i_ctrl_registers/num_cores_o
+# VCS + Verdi (nWave) curated overview for the 2D-mesh FlooNoC topology.
+# `make simvcs` auto-sources this from run.tcl; re-source any time from Verdi's
+# Tcl console: source ../scripts/vcs/wave.tcl. run.tcl dumps EVERY signal to the
+# FSDB, so anything not listed here can still be dragged into nWave (no re-run).
+#
+# GOTCHA: interpreted by VERDI (nWave), NOT the UCLI shell -- use only `wv*`
+# commands (no `dump`/`run`/`get`) and hard-code loop bounds (no
+# `get mempool_pkg::...`). Wrap `[0]`/`[3]` indices in {braces} so Tcl does not
+# treat them as command substitution.
+
+# GOTCHA: capture wvCreateWindow's return -- it does NOT auto-set $_nWave2 from
+# the -do/TclPlay console, so `wvAddSignal -win $_nWave2` would otherwise fail.
+set _nWave2 [wvCreateWindow]
+
+# --- System overview (testbench level) ---
+wvAddSignal -win $_nWave2 {/mempool_tb/wfi}
+wvAddSignal -win $_nWave2 {/mempool_tb/eoc_valid}
+wvAddSignal -win $_nWave2 {/mempool_tb/snitch_utilization}
+wvAddSignal -win $_nWave2 {/mempool_tb/lsu_utilization}
+
+# --- Control registers (end-of-computation / wake-up) ---
+wvAddSignal -win $_nWave2 {/mempool_tb/dut/i_ctrl_registers/eoc_o}
+wvAddSignal -win $_nWave2 {/mempool_tb/dut/i_ctrl_registers/eoc_valid_o}
+wvAddSignal -win $_nWave2 {/mempool_tb/dut/i_ctrl_registers/wake_up_o}
+
+# --- Group 0 / Tile 0, core 0 (snitch front-end) ---
+wvAddSignal -win $_nWave2 {/mempool_tb/dut/i_mempool_cluster/gen_groups_x[0]/gen_groups_y[0]/gen_rtl_group/i_group/i_mempool_group/gen_tiles[0]/i_tile/gen_cores[0]/gen_mempool_cc/riscv_core/i_snitch/pc_q}
+wvAddSignal -win $_nWave2 {/mempool_tb/dut/i_mempool_cluster/gen_groups_x[0]/gen_groups_y[0]/gen_rtl_group/i_group/i_mempool_group/gen_tiles[0]/i_tile/gen_cores[0]/gen_mempool_cc/riscv_core/i_snitch/wfi_q}
+
+
+wvZoomAll -win $_nWave2
diff --git a/hardware/scripts/vcs/wave_cache.tcl b/hardware/scripts/vcs/wave_cache.tcl
deleted file mode 100644
index bc198935..00000000
--- a/hardware/scripts/vcs/wave_cache.tcl
+++ /dev/null
@@ -1,28 +0,0 @@
-# Copyright 2021 ETH Zurich and University of Bologna.
-# Solderpad Hardware License, Version 0.51, see LICENSE for details.
-# SPDX-License-Identifier: SHL-0.51
-
-# Create cache for core $3 from group $1 tile $2 (core_id=NUM_CORES_PER_group*$1+NUM_CORES_PER_TILE*$2+$3)
-
-add_wave -group core\[$1\]\[$2\]\[$3\] -divider Parameters
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/NR_FETCH_PORTS
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/L0_LINE_COUNT
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/LINE_WIDTH
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/LINE_COUNT
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/SET_COUNT
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/FETCH_DW
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/FILL_AW
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/FILL_DW
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/EARLY_LATCH
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/L0_EARLY_TAG_WIDTH
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/ISO_CROSSING
-add_wave -group core\[$1\]\[$2\]\[$3\] -divider Signals
-add_wave -group cache\[$1\]\[$2\]\[$3\] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/*
-
-for {set i 0} {$i < [get -radix dec /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/NR_FETCH_PORTS]} {incr i} {
-  add_wave -group cache\[$1\]\[$2\]\[$3\]|refill[$i] /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/gen_prefetcher[$i]/i_snitch_icache_l0/*
-}
-
-add_wave -group cache\[$1\]\[$2\]\[$3\]|lookup  /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/gen_serial_lookup/i_lookup/*
-add_wave -group cache\[$1\]\[$2\]\[$3\]|handler /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/i_handler/*
-add_wave -group cache\[$1\]\[$2\]\[$3\]|refill  /mempool_tb/dut/i_mempool_cluster/gen_groups\[$1\]/i_group/gen_tiles\[$2\]/i_tile/gen_caches\[$3\]/i_snitch_icache/i_refill/*
diff --git a/hardware/scripts/vcs/wave_core.tcl b/hardware/scripts/vcs/wave_core.tcl
deleted file mode 100644
index 2f4ef0be..00000000
--- a/hardware/scripts/vcs/wave_core.tcl
+++ /dev/null
@@ -1,141 +0,0 @@
-# Copyright 2021 ETH Zurich and University of Bologna.
-# Solderpad Hardware License, Version 0.51, see LICENSE for details.
-# SPDX-License-Identifier: SHL-0.51
-
-# Create group for core $core from group $group tile $tile (core_id=NUM_CORES_PER_group*$group+NUM_CORES_PER_TILE*$tile+$core)
-
-wvAddGroup core\[$group\]\[$tile\]\[$core\]
-wvSetPosition [subst {(core\[$group\]\[$tile\]\[$core\] last)}]
-
-add_wave -divider Clock
-wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/clk_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/rst_ni \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/hart_id_i
-
-add_wave -divider Instructions
-wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/inst_addr_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/inst_data_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/inst_valid_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/inst_ready_i
-
-add_wave -divider "Load and Store"
-wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_qaddr_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_qwrite_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_qamo_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_qdata_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_qstrb_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_qvalid_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_qready_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_pdata_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_perror_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_pvalid_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/data_pready_o
-
-add_wave -divider Accelerator
-wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_qaddr_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_qid_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_op_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_arga_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argb_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argc_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_qvalid_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_qready_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_pdata_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_pid_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_perror_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_pvalid_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_pready_o \
-
-wvSelectGroup core\[$group\]\[$tile\]\[$core\]
-wvAddSubGroup Internal
-wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/clk_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/rst_ni \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/illegal_inst \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/stall \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/lsu_stall \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_stall \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/zero_lsb \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/pc_d \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/pc_q \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/wfi_d \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/wfi_q \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/wake_up_sync_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/wake_up_d \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/wake_up_q
-add_wave -divider LSU
-wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/ls_size \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/ls_amo \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/ld_result \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/lsu_qready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/lsu_qvalid \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/lsu_pvalid \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/lsu_pready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/lsu_rd \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/retire_load \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/retire_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/retire_acc
-add_wave -divider ALU
-wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/opa \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/opb \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/iimm \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/uimm \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/jimm \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/bimm \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/simm \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/adder_result \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/alu_result \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/rd \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/rs1 \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/rs2 \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/gpr_raddr \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/gpr_rdata \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/gpr_waddr \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/gpr_wdata \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/gpr_we \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/consec_pc \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/sb_d \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/sb_q \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/is_load \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/is_store \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/is_signed \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/is_fp_load \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/is_fp_store \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/ls_misaligned \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/ld_addr_misaligned \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/st_addr_misaligned \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/valid_instr \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/exception \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/alu_op \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/opa_select \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/opb_select \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/write_rd \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/uses_rd \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/next_pc \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/rd_select \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/rd_bypass \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/is_branch \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/csr_rvalue \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/csr_en \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/cycle_q \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/instret_q \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/acc_register_rd \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/operands_ready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/dst_ready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/opa_ready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/opb_ready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/shift_opa \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_reversed \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/shift_left_result \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_ext \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result_ext \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/shift_left \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/shift_arithmetic \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/alu_opa \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/alu_opb \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/alu_writeback \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_q \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_en \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/gen_cores\[$core\]/gen_mempool_cc/riscv_core/i_snitch/core_events_o
-
-wvCollapseAllGroups
diff --git a/hardware/scripts/vcs/wave_tile.tcl b/hardware/scripts/vcs/wave_tile.tcl
deleted file mode 100644
index 20f06693..00000000
--- a/hardware/scripts/vcs/wave_tile.tcl
+++ /dev/null
@@ -1,57 +0,0 @@
-# Copyright 2021 ETH Zurich and University of Bologna.
-# Solderpad Hardware License, Version 0.51, see LICENSE for details.
-# SPDX-License-Identifier: SHL-0.51
-
-# Create group for group $group tile $tile
-
-wvSelectGroup group\[$group\]
-wvAddSubGroup tile\[$tile\]
-
-wvSetPosition [subst {(group\[$group\]/tile\[$tile\] last)}]
-
-add_wave -divider Clock
-wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/clk_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/rst_ni \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tile_id_i \
-
-add_wave -divider TCDM
-wvAddSignal mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_master_req_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_master_req_valid_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_master_req_ready_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_master_resp_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_master_resp_valid_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_master_resp_ready_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_slave_req_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_slave_req_valid_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_slave_req_ready_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_slave_resp_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_slave_resp_valid_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/tcdm_slave_resp_ready_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/axi_mst_req_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/axi_mst_resp_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_inst_addr \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_inst_data \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_inst_valid \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_inst_ready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_qaddr \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_qwrite \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_qamo \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_qdata \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_qstrb \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_qid \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_qvalid \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_qready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_pdata \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_perror \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_pid \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_pvalid \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/snitch_data_pready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/mask_map \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/soc_req_o \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/soc_resp_i \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/soc_qvalid \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/soc_qready \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/soc_pvalid \
-            mempool_tb/dut/i_mempool_cluster/gen_groups\[$group\]/i_group/gen_tiles\[$tile\]/i_tile/soc_pready
-
-wvCollapseAllGroups
diff --git a/hardware/src/address_scrambler.sv b/hardware/src/address_scrambler.sv
deleted file mode 100644
index 78377a48..00000000
--- a/hardware/src/address_scrambler.sv
+++ /dev/null
@@ -1,89 +0,0 @@
-// Copyright 2021 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-
-// Description: Scrambles the address in such a way, that part of the memory is accessed
-// sequentially and part is interleaved.
-// Current constraints:
-
-// Author: Samuel Riedel <sriedel@iis.ee.ethz.ch>
-
-module address_scrambler
-#(
-  parameter int unsigned          AddrWidth         = 32,
-  parameter int unsigned          ByteOffset        = 2,
-  parameter int unsigned          NumTiles          = 2,
-  parameter int unsigned          NumTilesPerDma    = 16,
-  parameter int unsigned          NumBanksPerTile   = 2,
-  parameter bit                   Bypass            = 0,
-  parameter int unsigned          SeqMemSizePerTile = 4*1024,
-  parameter logic [AddrWidth-1:0] TCDMBaseAddr      = 32'b0,
-  parameter logic [31:0]          TCDMMask          = '1 << 28
-) (
-  input  logic [AddrWidth-1:0] address_i,
-  output logic [AddrWidth-1:0] address_o
-);
-  localparam int unsigned BankOffsetBits    = $clog2(NumBanksPerTile);
-  localparam int unsigned TileIdBits        = $clog2(NumTiles);
-  localparam int unsigned TileIdBitsPerDma  = $clog2(NumTilesPerDma);
-  localparam int unsigned SeqPerTileBits    = $clog2(SeqMemSizePerTile);
-  localparam int unsigned SeqTotalBits      = SeqPerTileBits+TileIdBits;
-  localparam int unsigned ConstantBitsLSB   = ByteOffset + BankOffsetBits;
-  localparam int unsigned ScrambleBits      = SeqPerTileBits-ConstantBitsLSB;
-
-  logic not_io_address;
-  assign not_io_address = (address_i & TCDMMask) == TCDMBaseAddr;
-
-  function automatic logic [TileIdBitsPerDma-1:0] spm_tile_id_remap (
-      logic [TileIdBitsPerDma-1:0] data_in,
-      logic [TileIdBitsPerDma-1:0] idx_i
-  );
-    if (mempool_pkg::TileIdRemap == 1) begin
-      spm_tile_id_remap = data_in + idx_i;
-    end else begin
-      spm_tile_id_remap = data_in;
-    end
-  endfunction
-
-  if (Bypass || NumTiles < 2) begin
-    assign address_o = address_i;
-  end else begin
-    logic [ScrambleBits-1:0]    scramble;    // Address bits that have to be shuffled around
-    logic [TileIdBits-1:0]      tile_id;     // Which tile does  this address region belong to
-
-    // Leave this part of the address unchanged
-    // The LSBs that correspond to the offset inside a tile. These are the byte offset (bank width)
-    // and the Bank offset (Number of Banks in tile)
-    assign address_o[ConstantBitsLSB-1:0] = address_i[ConstantBitsLSB-1:0];
-    // The MSBs that are outside of the sequential memory size. Currently the sequential memory size
-    // always starts at 0. These are all the MSBs up to SeqMemSizePerTile*NumTiles
-    assign address_o[AddrWidth-1:SeqTotalBits] = address_i[AddrWidth-1:SeqTotalBits];
-
-    // Scramble the middle part
-    // Bits that would have gone to different tiles but now go to increasing lines in the same tile
-    assign scramble = address_i[SeqPerTileBits-1:ConstantBitsLSB]; // Bits that would
-    // Bits that would have gone to increasing lines in the same tile but now go to different tiles
-    assign tile_id  = address_i[SeqTotalBits-1:SeqPerTileBits];
-
-    always_comb begin
-      // Default: Unscrambled
-      address_o[SeqTotalBits-1:ConstantBitsLSB] = {tile_id, scramble};
-      // If not in bypass mode and address is in sequential region and more than one tile
-      if (address_i < (NumTiles * SeqMemSizePerTile)) begin
-        address_o[SeqTotalBits-1:ConstantBitsLSB] = {scramble, tile_id};
-      end else if(not_io_address) begin
-        address_o[ConstantBitsLSB +: TileIdBitsPerDma] =
-          spm_tile_id_remap(
-            address_i[ConstantBitsLSB +: TileIdBitsPerDma],
-            address_i[(ConstantBitsLSB + TileIdBits) +: TileIdBitsPerDma]
-          );
-      end
-    end
-  end
-
-  // Check for unsupported configurations
-  if (NumBanksPerTile < 2)
-    $fatal(1, "NumBanksPerTile must be greater than 2. The special case '1' is currently not supported!");
-  if (SeqMemSizePerTile % (2**ByteOffset*NumBanksPerTile) != 0)
-    $fatal(1, "SeqMemSizePerTile must be a multiple of BankWidth*NumBanksPerTile!");
-endmodule : address_scrambler
diff --git a/hardware/src/mempool_addr_scrambler.sv b/hardware/src/mempool_addr_scrambler.sv
new file mode 100644
index 00000000..0f8ef2c4
--- /dev/null
+++ b/hardware/src/mempool_addr_scrambler.sv
@@ -0,0 +1,95 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+// SPM address scrambler. Single combinational module applying up to two
+// independently-gated address transforms:
+//   Stage 1 (EnableSeqInterleaveSwap, sequential region): swap the
+//     {tile_id, scramble} fields so HW sees an interleaved-bank layout.
+//   Stage 2 (EnableTileIdRemap, non-sequential TCDM): spread accesses
+//     across the NumTilesPerDma tiles of a DMA group.
+//
+// Used by snitch cores pre-tcdm_shim (both stages on) and by the DMA
+// tile-id path in mempool_group.sv (Stage 1 off, Stage 2 on; caller then
+// slices tile_id_remap out of address_o for the reqrsp_demux select).
+// Replaces address_scrambler.sv and mempool_dma_tile_id_remapper.sv.
+//
+// NOTE: bank-id remap is intentionally NOT here — it lives in the tile's
+// bank-side network (mempool_bank_id_remapper).
+
+module mempool_addr_scrambler
+#(
+  parameter int unsigned          AddrWidth                = 32,
+  parameter int unsigned          ByteOffset               = 2,
+  parameter int unsigned          NumTiles                 = 2,
+  parameter int unsigned          NumTilesPerDma           = 16,
+  parameter int unsigned          NumBanksPerTile          = 2,
+  parameter bit                   Bypass                   = 1'b0,
+  parameter int unsigned          SeqMemSizePerTile        = 4*1024,
+  parameter logic [AddrWidth-1:0] TCDMBaseAddr             = 32'b0,
+  parameter logic [31:0]          TCDMMask                 = '1 << 28,
+  parameter bit                   EnableSeqInterleaveSwap  = 1'b1,
+  parameter bit                   EnableTileIdRemap        = 1'b0
+) (
+  input  logic [AddrWidth-1:0] address_i,
+  output logic [AddrWidth-1:0] address_o
+);
+
+  `define max(a,b) (((a) > (b))? (a) : (b))
+
+  localparam int unsigned BankOffsetBits    = $clog2(NumBanksPerTile);
+  localparam int unsigned TileIdBits        = $clog2(NumTiles);
+  localparam int unsigned TileIdBitsPerDma  = `max(1, $clog2(NumTilesPerDma));
+  localparam int unsigned SeqPerTileBits    = $clog2(SeqMemSizePerTile);
+  localparam int unsigned SeqTotalBits      = SeqPerTileBits + TileIdBits;
+  localparam int unsigned ConstantBitsLSB   = ByteOffset + BankOffsetBits;
+  localparam int unsigned ScrambleBits      = SeqPerTileBits - ConstantBitsLSB;
+
+  logic not_io_address;
+  assign not_io_address = (address_i & TCDMMask) == TCDMBaseAddr;
+
+  function automatic logic [TileIdBitsPerDma-1:0] spm_tile_id_remap (
+      logic [TileIdBitsPerDma-1:0] data_in,
+      logic [TileIdBitsPerDma-1:0] idx_i
+  );
+    if (EnableTileIdRemap) begin
+      spm_tile_id_remap = data_in + idx_i;
+    end else begin
+      spm_tile_id_remap = data_in;
+    end
+  endfunction
+
+  if (Bypass || NumTiles < 2) begin : gen_bypass
+    assign address_o = address_i;
+  end else begin : gen_active
+    logic [ScrambleBits-1:0] scramble;
+    logic [TileIdBits-1:0]   tile_id;
+
+    assign scramble = address_i[SeqPerTileBits-1:ConstantBitsLSB];
+    assign tile_id  = address_i[SeqTotalBits-1:SeqPerTileBits];
+
+    always_comb begin
+      address_o = address_i;
+
+      // Stage 1: sequential→interleaved field swap (sequential region only).
+      if (EnableSeqInterleaveSwap && (address_i < (NumTiles * SeqMemSizePerTile))) begin
+        address_o[SeqTotalBits-1:ConstantBitsLSB] = {scramble, tile_id};
+      end
+      // Stage 2: tile-id remap. Stages 1/2 are mutually exclusive by range.
+      else if (EnableTileIdRemap && not_io_address) begin
+        address_o[ConstantBitsLSB +: TileIdBitsPerDma] =
+          spm_tile_id_remap(
+            address_i[ConstantBitsLSB +: TileIdBitsPerDma],
+            address_i[(ConstantBitsLSB + TileIdBits) +: TileIdBitsPerDma]
+          );
+      end
+    end
+  end : gen_active
+
+  // Check for unsupported configurations
+  if (NumBanksPerTile < 2)
+    $fatal(1, "NumBanksPerTile must be greater than 2. The special case '1' is currently not supported!");
+  if (SeqMemSizePerTile % (2**ByteOffset*NumBanksPerTile) != 0)
+    $fatal(1, "SeqMemSizePerTile must be a multiple of BankWidth*NumBanksPerTile!");
+
+endmodule : mempool_addr_scrambler
diff --git a/hardware/src/mempool_bank_id_remapper.sv b/hardware/src/mempool_bank_id_remapper.sv
deleted file mode 100644
index ef012b58..00000000
--- a/hardware/src/mempool_bank_id_remapper.sv
+++ /dev/null
@@ -1,89 +0,0 @@
-// Copyright 2021 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-
-`include "mempool/mempool.svh"
-
-module mempool_bank_id_remapper
-  import mempool_pkg::*;
-  import cf_math_pkg::idx_width;
-#(
-  parameter int unsigned NumCoresPerTile              = 4,
-  parameter int unsigned NumRemoteReqPortsPerTile     = 4,
-  parameter int unsigned NumBanksPerTile              = 16,
-  parameter int unsigned TCDMAddrMemWidth             = 8,
-  parameter bit          SpmBankIdRemap               = 0
-) (
-  input  tcdm_dma_req_t                                      tcdm_dma_req_i,
-  input  tcdm_slave_req_t     [NumRemoteReqPortsPerTile-1:0] tcdm_slave_req_i,
-  input  tcdm_slave_req_t     [NumCoresPerTile-1:0]          local_req_interco_payload_i,
-  output tcdm_dma_req_t                                      tcdm_dma_req_remapped_o,
-  output tcdm_slave_req_t     [NumRemoteReqPortsPerTile-1:0] tcdm_slave_req_remapped_o,
-  output tcdm_slave_req_t     [NumCoresPerTile-1:0]          local_req_interco_payload_remapped_o
-);
-
-  /*****************
-   *  Definitions  *
-   *****************/
-
-  // Compute shift amount: use lower of address width and bank index bits
-  `define min(a,b) (((a) < (b))? (a) : (b))
-  `define max(a,b) (((a) > (b))? (a) : (b))
-
-  typedef logic [idx_width(NumRemoteReqPortsPerTile)-1:0] remote_ports_index_t;
-  localparam SHIFT_AMOUNT = `min(TCDMAddrMemWidth, idx_width(NumBanksPerTile)); // or 4
-  localparam RemoteReqBits = `max(1, $clog2(NumRemoteReqPortsPerTile-1));
-
-  // Rotate bank ID by index bits for spreading
-  function automatic logic [idx_width(NumBanksPerTile)-1:0] spm_bank_id_remap (
-    logic [idx_width(NumBanksPerTile)-1:0] data_in,
-    logic [SHIFT_AMOUNT-1:0] idx_i
-  );
-  if (SpmBankIdRemap == 1) begin
-    spm_bank_id_remap = data_in + idx_i;
-  end else begin
-    spm_bank_id_remap = data_in;
-  end
-  endfunction
-
-  /************************
-   *  Bank Address Remap  *
-   ************************/
-  // Apply to DMA, remote, and local requests
-  tcdm_dma_req_t                                  tcdm_dma_req_remapped;
-  tcdm_slave_req_t [NumRemoteReqPortsPerTile-1:0] tcdm_slave_req_remapped;
-  tcdm_slave_req_t [NumCoresPerTile-1:0]          local_req_interco_payload_remapped;
-
-  always_comb begin
-    // DMA request: remap low bits of tgt_addr
-    tcdm_dma_req_remapped = tcdm_dma_req_i;
-    tcdm_dma_req_remapped.tgt_addr[idx_width(NumBanksPerTile)-1:0] =
-    spm_bank_id_remap(
-      tcdm_dma_req_i.tgt_addr[idx_width(NumBanksPerTile)-1:0],
-      tcdm_dma_req_i.tgt_addr[idx_width(NumBanksPerTile) +: SHIFT_AMOUNT]
-    );
-    // Remote requests: remap low bits of tgt_addr
-    for(int rp = 0; rp < NumRemoteReqPortsPerTile; rp++) begin
-      tcdm_slave_req_remapped[rp] = tcdm_slave_req_i[rp];
-      tcdm_slave_req_remapped[rp].tgt_addr[idx_width(NumBanksPerTile)-1:0] =
-      spm_bank_id_remap(
-        tcdm_slave_req_i[rp].tgt_addr[idx_width(NumBanksPerTile)-1:0],
-        tcdm_slave_req_i[rp].tgt_addr[idx_width(NumBanksPerTile) +: SHIFT_AMOUNT]
-      );
-    end
-    // Local requests: remap low bits of tgt_addr
-    for(int c = 0; c < NumCoresPerTile; c++) begin
-      local_req_interco_payload_remapped[c] = local_req_interco_payload_i[c];
-      local_req_interco_payload_remapped[c].tgt_addr[idx_width(NumBanksPerTile)-1:0] =
-      spm_bank_id_remap(
-        local_req_interco_payload_i[c].tgt_addr[idx_width(NumBanksPerTile)-1:0],
-        local_req_interco_payload_i[c].tgt_addr[idx_width(NumBanksPerTile) +: SHIFT_AMOUNT]
-      );
-    end
-  end
-
-  // Drive outputs
-  assign tcdm_dma_req_remapped_o              = tcdm_dma_req_remapped;
-  assign tcdm_slave_req_remapped_o            = tcdm_slave_req_remapped;
-  assign local_req_interco_payload_remapped_o = local_req_interco_payload_remapped;
-endmodule
diff --git a/hardware/src/mempool_dma_tile_id_remapper.sv b/hardware/src/mempool_dma_tile_id_remapper.sv
deleted file mode 100644
index 751fc6c7..00000000
--- a/hardware/src/mempool_dma_tile_id_remapper.sv
+++ /dev/null
@@ -1,43 +0,0 @@
-// Copyright 2025 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-
-module mempool_dma_tile_id_remapper
-  import mempool_pkg::*;
-  import cf_math_pkg::idx_width;
-(
-  input  reqrsp_req_t                               dma_reqrsp_req_i,
-  output logic [idx_width(NumTilesPerDma)-1:0]      tile_id_remap_o
-);
-
-  // Address slice offsets
-  localparam int TILE_ID_LOW_OFFSET      = ByteOffset
-                                         + idx_width(NumBanksPerTile);
-  localparam int TILE_ID_REMAPPED_OFFSET = TILE_ID_LOW_OFFSET
-                                         + idx_width(NumTilesPerGroup)
-                                         + idx_width(NumGroups);
-  localparam int TILE_ID_WIDTH           = idx_width(NumTilesPerDma);
-
-  // Extract fields from address
-  logic [TILE_ID_WIDTH-1:0] tile_id_remap_before;
-  logic [TILE_ID_WIDTH-1:0] tile_id_remap;
-
-  assign tile_id_remap_before = dma_reqrsp_req_i.q.addr[TILE_ID_LOW_OFFSET +: TILE_ID_WIDTH];
-  assign tile_id_remap        = tile_id_remap_before +
-                                dma_reqrsp_req_i.q.addr[TILE_ID_REMAPPED_OFFSET +: TILE_ID_WIDTH];
-
-  generate
-    if (TileIdRemap == 1) begin : gen_remap_enabled
-      always_comb begin
-        if (dma_reqrsp_req_i.q.addr < (NumTiles * SeqMemSizePerTile)) begin
-          tile_id_remap_o = tile_id_remap_before;
-        end else begin
-          tile_id_remap_o = tile_id_remap;
-        end
-      end
-    end else begin : gen_remap_disabled
-      assign tile_id_remap_o = tile_id_remap_before;
-    end
-  endgenerate
-
-endmodule
diff --git a/hardware/src/mempool_group.sv b/hardware/src/mempool_group.sv
index 9c8bd039..0cf66c21 100644
--- a/hardware/src/mempool_group.sv
+++ b/hardware/src/mempool_group.sv
@@ -536,11 +536,32 @@ module mempool_group
       .reqrsp_rsp_i(dma_reqrsp_rsp)
     );
 
-    mempool_dma_tile_id_remapper i_mempool_group_tile_id_remapper (
-      .dma_reqrsp_req_i (dma_reqrsp_req),
-      .tile_id_remap_o  (tile_id_remap[d])
+    // SPM address pipeline for the DMA request: tile-id remap selects the dest tile.
+    // The seq↔interleave swap is SKIPPED (DMA addresses are already interleaved).
+    addr_t dma_scrambled_addr;
+
+    mempool_addr_scrambler #(
+      .AddrWidth               (AddrWidth        ),
+      .ByteOffset              (ByteOffset       ),
+      .NumTiles                (NumTiles         ),
+      .NumTilesPerDma          (NumTilesPerDma   ),
+      .NumBanksPerTile         (NumBanksPerTile  ),
+      .Bypass                  (0                ),
+      .SeqMemSizePerTile       (SeqMemSizePerTile),
+      .TCDMBaseAddr            (TCDMBaseAddr     ),
+      .TCDMMask                (TCDMMask         ),
+      .EnableSeqInterleaveSwap (1'b0             ),
+      .EnableTileIdRemap       (TileIdRemap      )
+    ) i_dma_addr_scrambler (
+      .address_i (dma_reqrsp_req.q.addr ),
+      .address_o (dma_scrambled_addr    )
     );
 
+    // Extract the (post-remap) tile-id slice for the reqrsp_demux select.
+    assign tile_id_remap[d] =
+        dma_scrambled_addr[ByteOffset + idx_width(NumBanksPerTile)
+                           +: idx_width(NumTilesPerDma)];
+
     if (NumTilesPerDma > 1) begin: gen_dma_reqrsp_demux
       reqrsp_demux #(
         .NrPorts  (NumTilesPerDma        ),
diff --git a/hardware/src/mempool_pkg.sv b/hardware/src/mempool_pkg.sv
index 1771b6d9..92b372a0 100644
--- a/hardware/src/mempool_pkg.sv
+++ b/hardware/src/mempool_pkg.sv
@@ -505,50 +505,6 @@ package mempool_pkg;
     int unsigned write_cycles[$];      // dynamic array to store cycles of write accesses
   } profile_t;
 
-  // tile level profiling
-  typedef struct {
-    // tile remote ports profile
-    int unsigned req_vld_cyc_num[NumRemoteReqPortsPerTile-1];
-    int unsigned req_hsk_cyc_num[NumRemoteReqPortsPerTile-1];
-  } tile_level_profile_t;
-
-  // group level profiling
-  typedef struct {
-    // group xbar ports profile
-    int unsigned req_vld_cyc_num                            [NumRemoteReqPortsPerTile-1];
-    int unsigned req_hsk_cyc_num                            [NumRemoteReqPortsPerTile-1];
-    int unsigned req_vld_cyc_more_than_one_hit_same_bank_num;
-  } group_level_profile_t;
-
-  // router level profile
-  typedef struct {
-    // noc router ports profile
-    int unsigned in_vld_cyc_num [4]; // 4: 4 directions
-    int unsigned in_hsk_cyc_num [4]; // 4: 4 directions
-    int unsigned out_vld_cyc_num[4]; // 4: 4 directions
-    int unsigned out_hsk_cyc_num[4]; // 4: 4 directions
-  } router_level_profile_t;
-
-  // router local ports profile
-    // noc router local req ports profile
-  typedef struct {
-    int unsigned read_req_num;
-    int unsigned write_req_num;
-  } router_local_req_port_profile_t;
-    // noc router local resp ports profile
-  typedef struct {
-    int unsigned req_num;
-  } router_local_resp_port_profile_t;
-
-  typedef struct {
-    // noc router ports profile
-    int unsigned in_vld_cyc_num [5];
-    int unsigned in_hsk_cyc_num [5];
-    int unsigned hol_stall_cyc_num [5];
-    int unsigned out_congst_cyc_num [5][5];
-    int unsigned cur_stall_cyc_num [5];
-    int unsigned max_stall_cyc_num [5];
-  } router_input_profile_t;
   `endif
 `endif
 
diff --git a/hardware/src/mempool_tcdm_bank_interco.sv b/hardware/src/mempool_tcdm_bank_interco.sv
new file mode 100644
index 00000000..68aeddd9
--- /dev/null
+++ b/hardware/src/mempool_tcdm_bank_interco.sv
@@ -0,0 +1,415 @@
+// Copyright 2026 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+`include "mempool/mempool.svh"
+
+// Tile-internal TCDM bank-side interconnect: narrow req/resp crossbars, the
+// wide DMA superbank demux/mux, per-bank wide-over-narrow priority, and the
+// within-superbank bank-id remap. Replaces the legacy i_local_req_interco /
+// i_local_resp_interco / i_dma_req_interco / i_dma_resp_interco stream_xbars,
+// the per-superbank tcdm_wide_narrow_mux, and mempool_bank_id_remapper.sv.
+//
+// Bank-id remap is within-superbank only: only the low log2(NumBanksPerSB)
+// bits of bank_id are rewritten (add the row-id slice). bank_id_hi (selects
+// superbank for wide DMA) passes through unchanged so the wide chunk lands in
+// the same superbank a narrow access of its base address would pick; the wide
+// fork then rotates within that superbank to stay coherent with the narrow path.
+//
+// gen_superbank_resp_ini_addr (NumRemoteReqPortsPerTile vs
+// NumRemoteRespPortsPerTile asymmetry) stays OUTSIDE this module: the caller
+// passes the post-conditioning resp idx via mst_resp_ini_addr_i.
+
+module mempool_tcdm_bank_interco
+  import mempool_pkg::*;
+  import cf_math_pkg::idx_width;
+#(
+  parameter int unsigned NumNarrowReq      = 8,
+  parameter int unsigned NumNarrowResp     = 8,
+  parameter int unsigned NumBanksPerTile   = 16,
+  parameter int unsigned NumSuperbanks     = 1,
+  parameter int unsigned NarrowDataWidth   = 32,
+  parameter int unsigned WideDataWidth     = 512,
+  parameter int unsigned ByteOffset        = 2,
+  parameter bit          SpmBankIdRemap    = 0,
+  parameter type narrow_req_t  = tcdm_slave_req_t,
+  parameter type narrow_resp_t = tcdm_slave_resp_t,
+  parameter type wide_req_t    = tcdm_dma_req_t,
+  parameter type wide_resp_t   = tcdm_dma_resp_t,
+  parameter type group_id_t    = mempool_pkg::group_id_t,
+  // Must be wide enough to address NumNarrowResp ports (logic [idx_width(NumNarrowResp)-1:0]).
+  parameter type resp_idx_t    = logic [3:0],
+  // derived
+  localparam int unsigned NumBanksPerSB    = NumBanksPerTile / NumSuperbanks,
+  localparam int unsigned BankOffsetBits   = $clog2(NumBanksPerTile),
+  localparam int unsigned BankIdLoBits     = $clog2(NumBanksPerSB),
+  localparam int unsigned SBSelBits        = (NumSuperbanks > 1) ? $clog2(NumSuperbanks) : 1,
+  localparam int unsigned NarrowBeWidth    = NarrowDataWidth / 8,
+  localparam int unsigned RotBits          = (NumBanksPerSB > 1) ? $clog2(NumBanksPerSB) : 1,
+  // Bank-id remap offset width, clamped by the row-id slice above bank_id.
+  localparam int unsigned BankRemapShiftAmt =
+      (BankIdLoBits <= (NumBanksPerSB == 1 ? 0 : BankIdLoBits)) ? BankIdLoBits : BankIdLoBits
+) (
+  input  logic                                          clk_i,
+  input  logic                                          rst_ni,
+  input  group_id_t                                     group_id_i,
+
+  // ----- Narrow request inputs -----
+  input  narrow_req_t  [NumNarrowReq-1:0]               slv_narrow_req_i,
+  input  logic         [NumNarrowReq-1:0]               slv_narrow_req_valid_i,
+  output logic         [NumNarrowReq-1:0]               slv_narrow_req_ready_o,
+
+  // ----- Narrow response outputs -----
+  output narrow_resp_t [NumNarrowResp-1:0]              slv_narrow_resp_o,
+  output logic         [NumNarrowResp-1:0]              slv_narrow_resp_valid_o,
+  input  logic         [NumNarrowResp-1:0]              slv_narrow_resp_ready_i,
+
+  // ----- Wide DMA request input (single, demuxed internally) -----
+  input  wide_req_t                                     slv_wide_req_i,
+  input  logic                                          slv_wide_req_valid_i,
+  output logic                                          slv_wide_req_ready_o,
+
+  // ----- Wide DMA response output (single, muxed internally) -----
+  output wide_resp_t                                    slv_wide_resp_o,
+  output logic                                          slv_wide_resp_valid_o,
+  input  logic                                          slv_wide_resp_ready_i,
+
+  // ----- Bank-side request ports (per bank) -----
+  output narrow_req_t  [NumBanksPerTile-1:0]            mst_req_o,
+  output logic         [NumBanksPerTile-1:0]            mst_req_valid_o,
+  input  logic         [NumBanksPerTile-1:0]            mst_req_ready_i,
+  output logic         [NumBanksPerTile-1:0]            mst_req_wide_o,
+  output resp_idx_t    [NumBanksPerTile-1:0]            mst_req_ini_addr_o,
+
+  // ----- Bank-side response ports (per bank) -----
+  input  narrow_resp_t [NumBanksPerTile-1:0]            mst_resp_i,
+  input  logic         [NumBanksPerTile-1:0]            mst_resp_valid_i,
+  output logic         [NumBanksPerTile-1:0]            mst_resp_ready_o,
+  input  logic         [NumBanksPerTile-1:0]            mst_resp_wide_i,
+  input  resp_idx_t    [NumBanksPerTile-1:0]            mst_resp_ini_addr_i
+);
+
+  // Depth to absorb the bank pipeline plus slack (a couple of wide reqs
+  // outstanding per superbank; 8 leaves comfortable slack).
+  localparam int unsigned RotFifoDepth = 8;
+
+  // ============================================================
+  // Narrow-request: bank-id-lo remap + xbar
+  // ============================================================
+  // Within-superbank constraint: only the low BankIdLoBits of bank_id are rewritten.
+  logic [NumNarrowReq-1:0][BankOffsetBits-1:0] narrow_sel;
+  for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_sel
+    logic [BankIdLoBits-1:0] raw_lo, new_lo;
+    assign raw_lo = slv_narrow_req_i[i].tgt_addr[0 +: BankIdLoBits];
+    if (SpmBankIdRemap) begin : gen_remap_active
+      // Offset comes from the row-id slice just above bank_id.
+      logic [BankRemapShiftAmt-1:0] offset_lo;
+      assign offset_lo = slv_narrow_req_i[i].tgt_addr[BankOffsetBits +: BankRemapShiftAmt];
+      assign new_lo = raw_lo + offset_lo;
+    end else begin : gen_remap_passthrough
+      assign new_lo = raw_lo;
+    end
+    if (NumSuperbanks > 1) begin : gen_hi_passthrough
+      // bank_id_hi passes through untouched
+      assign narrow_sel[i] =
+          {slv_narrow_req_i[i].tgt_addr[BankIdLoBits +: (BankOffsetBits - BankIdLoBits)],
+           new_lo};
+    end else begin : gen_no_hi
+      assign narrow_sel[i] = new_lo;
+    end
+  end
+
+  narrow_req_t [NumBanksPerTile-1:0] narrow_to_bank;
+  logic        [NumBanksPerTile-1:0] narrow_to_bank_valid;
+  logic        [NumBanksPerTile-1:0] narrow_to_bank_ready;
+  resp_idx_t   [NumBanksPerTile-1:0] narrow_to_bank_idx;
+
+  stream_xbar #(
+    .NumInp   (NumNarrowReq    ),
+    .NumOut   (NumBanksPerTile ),
+    .payload_t(narrow_req_t    )
+  ) i_narrow_req_xbar (
+    .clk_i  (clk_i                  ),
+    .rst_ni (rst_ni                 ),
+    .flush_i(1'b0                   ),
+    .rr_i   ('0                     ),
+    .data_i (slv_narrow_req_i       ),
+    .valid_i(slv_narrow_req_valid_i ),
+    .ready_o(slv_narrow_req_ready_o ),
+    .sel_i  (narrow_sel             ),
+    .data_o (narrow_to_bank         ),
+    .valid_o(narrow_to_bank_valid   ),
+    .ready_i(narrow_to_bank_ready   ),
+    .idx_o  (narrow_to_bank_idx     )
+  );
+
+  // ============================================================
+  // Wide DMA: demux single wide req to per-superbank streams.
+  // ============================================================
+  wide_req_t [NumSuperbanks-1:0] wide_to_sb;
+  logic      [NumSuperbanks-1:0] wide_to_sb_valid;
+  logic      [NumSuperbanks-1:0] wide_to_sb_ready;
+
+  if (NumSuperbanks > 1) begin : gen_wide_req_demux
+    stream_xbar #(
+      .NumInp   (1            ),
+      .NumOut   (NumSuperbanks),
+      .payload_t(wide_req_t   )
+    ) i_wide_req_demux (
+      .clk_i  (clk_i               ),
+      .rst_ni (rst_ni              ),
+      .flush_i(1'b0                ),
+      .rr_i   ('0                  ),
+      .data_i (slv_wide_req_i      ),
+      .valid_i(slv_wide_req_valid_i),
+      .ready_o(slv_wide_req_ready_o),
+      // Superbank select uses the upper bits of bank_id (unchanged by remap).
+      .sel_i  (slv_wide_req_i.tgt_addr[BankIdLoBits +: SBSelBits]),
+      .data_o (wide_to_sb          ),
+      .valid_o(wide_to_sb_valid    ),
+      .ready_i(wide_to_sb_ready    ),
+      .idx_o  (/* unused */        )
+    );
+  end else begin : gen_wide_req_bypass
+    assign wide_to_sb[0]        = slv_wide_req_i;
+    assign wide_to_sb_valid[0]  = slv_wide_req_valid_i;
+    assign slv_wide_req_ready_o = wide_to_sb_ready[0];
+  end
+
+  // ============================================================
+  // Per-superbank wide handling: fork-with-rotation on the req side,
+  // join-with-inverse-rotation on the resp side. Rotation amount per wide
+  // req is queued in a per-superbank FIFO so outstanding reqs reassemble.
+  // ============================================================
+  wide_resp_t [NumSuperbanks-1:0] sb_wide_resp;
+  logic       [NumSuperbanks-1:0] sb_wide_resp_valid;
+  logic       [NumSuperbanks-1:0] sb_wide_resp_ready;
+
+  // Per-bank wide req/resp signals coming out of the fork / into the join.
+  logic        [NumBanksPerTile-1:0] wide_fork_valid;
+  logic        [NumBanksPerTile-1:0] wide_fork_ready;
+  narrow_req_t [NumBanksPerTile-1:0] wide_req_for_bank;
+  logic        [NumBanksPerTile-1:0] wide_join_in_valid;
+  logic        [NumBanksPerTile-1:0] wide_join_in_ready;
+
+  for (genvar d = 0; d < NumSuperbanks; d++) begin : gen_sb
+    // Rotation amount = (remapped) bank_id_lo of the wide req's tgt_addr.
+    logic [RotBits-1:0] req_rot;
+    if (NumBanksPerSB > 1) begin : gen_rot
+      // Same bank-id-lo remap arithmetic as the narrow xbar sel, so rotations match.
+      logic [BankIdLoBits-1:0] raw_lo, post_lo;
+      assign raw_lo = wide_to_sb[d].tgt_addr[0 +: BankIdLoBits];
+      if (SpmBankIdRemap) begin : gen_remap_on
+        logic [BankRemapShiftAmt-1:0] off_lo;
+        assign off_lo = wide_to_sb[d].tgt_addr[BankOffsetBits +: BankRemapShiftAmt];
+        assign post_lo = raw_lo + off_lo;
+      end else begin : gen_remap_off
+        assign post_lo = raw_lo;
+      end
+      assign req_rot = post_lo;
+    end else begin : gen_no_rot
+      assign req_rot = '0;
+    end
+
+    // Rotation FIFO: push at fork accept, pop at wide resp out.
+    logic [RotBits-1:0] resp_rot;
+    logic               rot_fifo_push, rot_fifo_pop;
+    logic               rot_fifo_full;
+
+    fifo_v3 #(
+      .DEPTH      (RotFifoDepth),
+      .DATA_WIDTH (RotBits     )
+    ) i_rot_fifo (
+      .clk_i      (clk_i        ),
+      .rst_ni     (rst_ni       ),
+      .flush_i    (1'b0         ),
+      .testmode_i (1'b0         ),
+      .data_i     (req_rot      ),
+      .push_i     (rot_fifo_push),
+      .full_o     (rot_fifo_full),
+      .data_o     (resp_rot     ),
+      .pop_i      (rot_fifo_pop ),
+      .empty_o    (/* unused */ ),
+      .usage_o    (/* unused */ )
+    );
+
+    // Fork the wide req across the superbank's banks.
+    logic [NumBanksPerSB-1:0] sb_fork_valid;
+    logic [NumBanksPerSB-1:0] sb_fork_ready;
+    stream_fork #(.N_OUP(NumBanksPerSB)) i_wide_fork (
+      .clk_i  (clk_i                ),
+      .rst_ni (rst_ni               ),
+      .valid_i(wide_to_sb_valid[d]  ),
+      .ready_o(wide_to_sb_ready[d]  ),
+      .valid_o(sb_fork_valid        ),
+      .ready_i(sb_fork_ready        )
+    );
+    assign rot_fifo_push = wide_to_sb_valid[d] & wide_to_sb_ready[d];
+
+    // Compose each bank's wide req: rotated word slice + shared address.
+    for (genvar b = 0; b < NumBanksPerSB; b++) begin : gen_sb_bank_req
+      localparam int unsigned global_bank = d*NumBanksPerSB + b;
+      always_comb begin
+        // word j = (b - req_rot) mod NumBanksPerSB feeds bank port b.
+        automatic int unsigned j = (b + NumBanksPerSB - req_rot) % NumBanksPerSB;
+        wide_req_for_bank[global_bank] = '{
+          wdata: '{
+            meta_id: wide_to_sb[d].wdata.meta_id,
+            core_id: wide_to_sb[d].wdata.core_id,
+            amo:     wide_to_sb[d].wdata.amo,
+            data:    wide_to_sb[d].wdata.data[j*NarrowDataWidth +: NarrowDataWidth]
+          },
+          wen:           wide_to_sb[d].wen,
+          be:            wide_to_sb[d].be[j*NarrowBeWidth +: NarrowBeWidth],
+          tgt_addr:      wide_to_sb[d].tgt_addr,
+          ini_addr:      '0,
+          src_group_id:  group_id_i
+        };
+      end
+      assign wide_fork_valid[global_bank] = sb_fork_valid[b];
+      assign sb_fork_ready[b]             = wide_fork_ready[global_bank];
+    end
+
+    // Wide resp join across the superbank's banks; inverse rotation uses
+    // resp_rot from the FIFO head.
+    logic [NumBanksPerSB-1:0] sb_join_valid;
+    logic [NumBanksPerSB-1:0] sb_join_ready;
+    stream_join #(.N_INP(NumBanksPerSB)) i_wide_join (
+      .inp_valid_i(sb_join_valid          ),
+      .inp_ready_o(sb_join_ready          ),
+      .oup_valid_o(sb_wide_resp_valid[d]  ),
+      .oup_ready_i(sb_wide_resp_ready[d]  )
+    );
+    assign rot_fifo_pop = sb_wide_resp_valid[d] & sb_wide_resp_ready[d];
+
+    // Wire the per-bank wide-side response handshake into the join.
+    for (genvar b = 0; b < NumBanksPerSB; b++) begin : gen_sb_bank_resp
+      localparam int unsigned global_bank = d*NumBanksPerSB + b;
+      assign sb_join_valid[b]                  = wide_join_in_valid[global_bank];
+      assign wide_join_in_ready[global_bank]   = sb_join_ready[b];
+    end
+
+    // Reassemble wide rdata with inverse rotation, then carry metadata.
+    always_comb begin
+      sb_wide_resp[d] = '{rdata: '{default: '0}};
+      for (int b = 0; b < NumBanksPerSB; b++) begin
+        // Bank port b carries word j = (b - resp_rot) mod NumBanksPerSB.
+        automatic int unsigned j = (b + NumBanksPerSB - resp_rot) % NumBanksPerSB;
+        sb_wide_resp[d].rdata.data[j*NarrowDataWidth +: NarrowDataWidth]
+            = mst_resp_i[d*NumBanksPerSB + b].rdata.data;
+      end
+      // Metadata from the lowest bank — all banks of a wide chunk share it.
+      sb_wide_resp[d].rdata.meta_id = mst_resp_i[d*NumBanksPerSB].rdata.meta_id;
+      sb_wide_resp[d].rdata.core_id = mst_resp_i[d*NumBanksPerSB].rdata.core_id;
+      sb_wide_resp[d].rdata.amo     = mst_resp_i[d*NumBanksPerSB].rdata.amo;
+    end
+
+    // synopsys translate_off
+`ifndef SYNTHESIS
+    always_ff @(posedge clk_i) begin
+      if (rst_ni && rot_fifo_push && rot_fifo_full) begin
+        $fatal(1, "[mempool_tcdm_bank_interco] sb=%0d rot FIFO overflow (depth=%0d)", d, RotFifoDepth);
+      end
+    end
+`endif
+    // synopsys translate_on
+  end
+
+  // ============================================================
+  // Per-bank priority: wide overrides narrow at the request port.
+  // ============================================================
+  for (genvar b = 0; b < NumBanksPerTile; b++) begin : gen_bank_mux
+    always_comb begin
+      if (wide_fork_valid[b]) begin
+        mst_req_o[b]              = wide_req_for_bank[b];
+        mst_req_valid_o[b]        = wide_fork_valid[b];
+        mst_req_wide_o[b]         = 1'b1;
+        wide_fork_ready[b]        = mst_req_ready_i[b];
+        narrow_to_bank_ready[b]   = 1'b0;
+        mst_req_ini_addr_o[b]     = '0;
+      end else begin
+        mst_req_o[b]              = narrow_to_bank[b];
+        mst_req_valid_o[b]        = narrow_to_bank_valid[b];
+        mst_req_wide_o[b]         = 1'b0;
+        wide_fork_ready[b]        = 1'b0;
+        narrow_to_bank_ready[b]   = mst_req_ready_i[b];
+        mst_req_ini_addr_o[b]     = narrow_to_bank_idx[b];
+      end
+    end
+  end
+
+  // ============================================================
+  // Per-bank response split: wide → join, narrow → resp xbar.
+  // ============================================================
+  narrow_resp_t [NumBanksPerTile-1:0] narrow_resp_to_xbar;
+  logic         [NumBanksPerTile-1:0] narrow_resp_to_xbar_valid;
+  logic         [NumBanksPerTile-1:0] narrow_resp_to_xbar_ready;
+
+  for (genvar b = 0; b < NumBanksPerTile; b++) begin : gen_resp_split
+    assign narrow_resp_to_xbar[b] = mst_resp_i[b];
+    always_comb begin
+      if (mst_resp_wide_i[b]) begin
+        wide_join_in_valid[b]        = mst_resp_valid_i[b];
+        mst_resp_ready_o[b]          = wide_join_in_ready[b];
+        narrow_resp_to_xbar_valid[b] = 1'b0;
+      end else begin
+        wide_join_in_valid[b]        = 1'b0;
+        mst_resp_ready_o[b]          = narrow_resp_to_xbar_ready[b];
+        narrow_resp_to_xbar_valid[b] = mst_resp_valid_i[b];
+      end
+    end
+  end
+
+  // ============================================================
+  // Narrow response xbar (NumBanksPerTile → NumNarrowResp).
+  // sel = caller-supplied resp idx (already conditioned for any
+  // NumRemoteReqPortsPerTile vs NumRemoteRespPortsPerTile asymmetry).
+  // ============================================================
+  stream_xbar #(
+    .NumInp   (NumBanksPerTile ),
+    .NumOut   (NumNarrowResp   ),
+    .payload_t(narrow_resp_t   )
+  ) i_narrow_resp_xbar (
+    .clk_i  (clk_i                      ),
+    .rst_ni (rst_ni                     ),
+    .flush_i(1'b0                       ),
+    .rr_i   ('0                         ),
+    .data_i (narrow_resp_to_xbar        ),
+    .valid_i(narrow_resp_to_xbar_valid  ),
+    .ready_o(narrow_resp_to_xbar_ready  ),
+    .sel_i  (mst_resp_ini_addr_i        ),
+    .data_o (slv_narrow_resp_o          ),
+    .valid_o(slv_narrow_resp_valid_o    ),
+    .ready_i(slv_narrow_resp_ready_i    ),
+    .idx_o  (/* unused */               )
+  );
+
+  // ============================================================
+  // Wide response mux (NumSuperbanks → 1).
+  // ============================================================
+  if (NumSuperbanks > 1) begin : gen_wide_resp_mux
+    stream_xbar #(
+      .NumInp   (NumSuperbanks ),
+      .NumOut   (1             ),
+      .payload_t(wide_resp_t   )
+    ) i_wide_resp_mux (
+      .clk_i  (clk_i                 ),
+      .rst_ni (rst_ni                ),
+      .flush_i(1'b0                  ),
+      .rr_i   ('0                    ),
+      .data_i (sb_wide_resp          ),
+      .valid_i(sb_wide_resp_valid    ),
+      .ready_o(sb_wide_resp_ready    ),
+      .sel_i  ('0                    ),
+      .data_o (slv_wide_resp_o       ),
+      .valid_o(slv_wide_resp_valid_o ),
+      .ready_i(slv_wide_resp_ready_i ),
+      .idx_o  (/* unused */          )
+    );
+  end else begin : gen_wide_resp_bypass
+    assign slv_wide_resp_o        = sb_wide_resp[0];
+    assign slv_wide_resp_valid_o  = sb_wide_resp_valid[0];
+    assign sb_wide_resp_ready[0]  = slv_wide_resp_ready_i;
+  end
+
+endmodule
diff --git a/hardware/src/mempool_tile.sv b/hardware/src/mempool_tile.sv
index 1ed11816..a660e673 100644
--- a/hardware/src/mempool_tile.sv
+++ b/hardware/src/mempool_tile.sv
@@ -88,13 +88,6 @@ module mempool_tile
     assign group_id = '0;
   end: gen_group_id
 
-  /************************
-   *  Bank Address Remap  *
-   ************************/
-  tcdm_dma_req_t                                  tcdm_dma_req_remapped;
-  tcdm_slave_req_t [NumRemoteReqPortsPerTile-1:0] tcdm_slave_req_remapped;
-  tcdm_slave_req_t [NumCoresPerTile-1:0]          local_req_interco_payload_remapped;
-
   /***********
    *  Cores  *
    ***********/
@@ -367,20 +360,6 @@ module mempool_tile
   } bank_metadata_t;
 
   // Memory interfaces
-  tcdm_dma_req_t           [NumSuperbanks-1:0]   tcdm_dma_req;
-  logic                    [NumSuperbanks-1:0]   tcdm_dma_req_valid;
-  logic                    [NumSuperbanks-1:0]   tcdm_dma_req_ready;
-  tcdm_dma_resp_t          [NumSuperbanks-1:0]   tcdm_dma_resp;
-  logic                    [NumSuperbanks-1:0]   tcdm_dma_resp_valid;
-  logic                    [NumSuperbanks-1:0]   tcdm_dma_resp_ready;
-
-  logic                    [NumBanksPerTile-1:0] superbank_req_valid;
-  logic                    [NumBanksPerTile-1:0] superbank_req_ready;
-  local_req_interco_addr_t [NumBanksPerTile-1:0] superbank_req_ini_addr;
-  tcdm_slave_req_t         [NumBanksPerTile-1:0] superbank_req_payload;
-  logic                    [NumBanksPerTile-1:0] superbank_resp_valid;
-  logic                    [NumBanksPerTile-1:0] superbank_resp_ready;
-  tcdm_slave_resp_t        [NumBanksPerTile-1:0] superbank_resp_payload;
   local_resp_interco_addr_t[NumBanksPerTile-1:0] superbank_resp_ini_addr;
 
   logic                    [NumBanksPerTile-1:0] bank_req_valid;
@@ -394,63 +373,8 @@ module mempool_tile
   logic                    [NumBanksPerTile-1:0] bank_resp_wide;
   local_resp_interco_addr_t[NumBanksPerTile-1:0] bank_resp_ini_addr;
 
-  tcdm_dma_req_t tcdm_dma_req_i_struct;
-  assign tcdm_dma_req_i_struct = tcdm_dma_req_remapped;
-
-  if (NumSuperbanks == 1) begin : gen_dma_interco_bypass
-    assign tcdm_dma_req = tcdm_dma_req_i_struct;
-    assign tcdm_dma_req_valid = tcdm_dma_req_valid_i;
-    assign tcdm_dma_req_ready_o = tcdm_dma_req_ready;
-    assign tcdm_dma_resp_o = tcdm_dma_resp;
-    assign tcdm_dma_resp_valid_o = tcdm_dma_resp_valid;
-    assign tcdm_dma_resp_ready = tcdm_dma_resp_ready_i;
-  end else begin : gen_dma_interco
-    stream_xbar #(
-      .NumInp   (1             ),
-      .NumOut   (NumSuperbanks ),
-      .payload_t(tcdm_dma_req_t)
-    ) i_dma_req_interco (
-      .clk_i  (clk_i                                                  ),
-      .rst_ni (rst_ni                                                 ),
-      .flush_i(1'b0                                                   ),
-      // External priority flag
-      .rr_i   ('0                                                     ),
-      // Master
-      .data_i (tcdm_dma_req_i_struct                                  ),
-      .valid_i(tcdm_dma_req_valid_i                                   ),
-      .ready_o(tcdm_dma_req_ready_o                                   ),
-      .sel_i  (tcdm_dma_req_i_struct.tgt_addr[idx_width(NumBanksPerTile)-1:$clog2(DmaNumWords)]),
-      // Slave
-      .data_o (tcdm_dma_req                                           ),
-      .valid_o(tcdm_dma_req_valid                                     ),
-      .ready_i(tcdm_dma_req_ready                                     ),
-      .idx_o  (/* Unused */                                           )
-    );
-
-    stream_xbar #(
-      .NumInp   (NumSuperbanks  ),
-      .NumOut   (1              ),
-      .payload_t(tcdm_dma_resp_t)
-    ) i_dma_resp_interco (
-      .clk_i  (clk_i                           ),
-      .rst_ni (rst_ni                          ),
-      .flush_i(1'b0                            ),
-      // External priority flag
-      .rr_i   ('0                              ),
-      // Master
-      .data_i (tcdm_dma_resp                   ),
-      .valid_i(tcdm_dma_resp_valid             ),
-      .ready_o(tcdm_dma_resp_ready             ),
-      .sel_i  ('0                              ),
-      // Slave
-      .data_o (tcdm_dma_resp_o                 ),
-      .valid_o(tcdm_dma_resp_valid_o           ),
-      .ready_i(tcdm_dma_resp_ready_i           ),
-      .idx_o  (/* Unused */                    )
-    );
-  end
-
-  assign bank_req_ini_addr = superbank_req_ini_addr;
+  // Condition bank_resp_ini_addr into the resp xbar's sel, handling
+  // req/resp port-count asymmetry; feeds i_tcdm_bank_interco.mst_resp_ini_addr_i.
   for (genvar b = 0; unsigned'(b) < NumBanksPerTile; b++) begin: gen_superbank_resp_ini_addr
     if(NumRemoteReqPortsPerTile > NumRemoteRespPortsPerTile ) begin: gen_superbank_resp_ini_addr_req_gt_resp
       always_comb begin
@@ -507,45 +431,16 @@ module mempool_tile
     end
   end
 
-  for (genvar d = 0; unsigned'(d) < NumSuperbanks; d++) begin: gen_dma_mux
-    tcdm_wide_narrow_mux #(
-      .NarrowDataWidth(DataWidth        ),
-      .WideDataWidth  (DmaDataWidth     ),
-      .narrow_req_t   (tcdm_slave_req_t ),
-      .narrow_rsp_t   (tcdm_slave_resp_t),
-      .wide_req_t     (tcdm_dma_req_t   ),
-      .wide_rsp_t     (tcdm_dma_resp_t  ),
-      .group_id_t     (group_id_t       )
-    ) i_tcdm_wide_narrow_mux (
-      .clk_i                 (clk_i                                             ),
-      .rst_ni                (rst_ni                                            ),
-      .group_id_i            (group_id                                          ), // FlooNoC Added
-      .slv_narrow_req_i      (superbank_req_payload[d*DmaNumWords+:DmaNumWords] ),
-      .slv_narrow_req_valid_i(superbank_req_valid[d*DmaNumWords+:DmaNumWords]   ),
-      .slv_narrow_req_ready_o(superbank_req_ready[d*DmaNumWords+:DmaNumWords]   ),
-      .slv_narrow_rsp_o      (superbank_resp_payload[d*DmaNumWords+:DmaNumWords]),
-      .slv_narrow_rsp_valid_o(superbank_resp_valid[d*DmaNumWords+:DmaNumWords]  ),
-      .slv_narrow_rsp_ready_i(superbank_resp_ready[d*DmaNumWords+:DmaNumWords]  ),
-      .slv_wide_req_i        (tcdm_dma_req[d]                                   ),
-      .slv_wide_req_valid_i  (tcdm_dma_req_valid[d]                             ),
-      .slv_wide_req_ready_o  (tcdm_dma_req_ready[d]                             ),
-      .slv_wide_rsp_o        (tcdm_dma_resp[d]                                  ),
-      .slv_wide_rsp_valid_o  (tcdm_dma_resp_valid[d]                            ),
-      .slv_wide_rsp_ready_i  (tcdm_dma_resp_ready[d]                            ),
-      .mst_req_o             (bank_req_payload[d*DmaNumWords+:DmaNumWords]      ),
-      .mst_req_wide_o        (bank_req_wide[d*DmaNumWords+:DmaNumWords]         ),
-      .mst_req_valid_o       (bank_req_valid[d*DmaNumWords+:DmaNumWords]        ),
-      .mst_req_ready_i       (bank_req_ready[d*DmaNumWords+:DmaNumWords]        ),
-      .mst_rsp_i             (bank_resp_payload[d*DmaNumWords+:DmaNumWords]     ),
-      .mst_rsp_wide_i        (bank_resp_wide[d*DmaNumWords+:DmaNumWords]        ),
-      .mst_rsp_valid_i       (bank_resp_valid[d*DmaNumWords+:DmaNumWords]       ),
-      .mst_rsp_ready_o       (bank_resp_ready[d*DmaNumWords+:DmaNumWords]       )
-    );
-  end
+  // mempool_tcdm_bank_interco is instantiated further below, after its
+  // connected signal declarations.
 
   `ifndef TARGET_SYNTHESIS
   `ifndef TARGET_VERILATOR
+  // DISABLED (commented out): heavy per-word SPM profiler (profile_d) — its
+  // unbounded [bank][2^addr] cycle lists balloon VCS memory; superseded by the
+  // lightweight per-bank trace in tb/tb_spm_profiling.svh.
   `ifdef SPM_PROFILING
+    /*
     logic [63:0] cycle_q;
     profile_t profile_d [NumBanksPerTile-1:0][2**TCDMAddrMemWidth-1:0];
     // profile_t profile_q [NumBanksPerTile-1:0][2**TCDMAddrMemWidth-1:0];
@@ -558,6 +453,7 @@ module mempool_tile
         // profile_q <= profile_d;
       end
     end
+    */
   `endif
   `endif
   `endif
@@ -640,6 +536,8 @@ module mempool_tile
   `ifndef TARGET_SYNTHESIS
   `ifndef TARGET_VERILATOR
   `ifdef SPM_PROFILING
+    // DISABLED (commented out) with the profile_d decl above.
+    /*
     always_ff @(posedge clk_i or negedge rst_ni) begin
       // profile_d[b] = profile_q[b];
       if(~rst_ni) begin
@@ -673,6 +571,7 @@ module mempool_tile
         end
       end
     end
+    */
   `endif
   `endif
   `endif
@@ -720,7 +619,7 @@ module mempool_tile
       .rst_ni    (rst_ni                         ),
       .clr_i     (1'b0                           ),
       .testmode_i(1'b0                           ),
-      .data_i    (tcdm_slave_req_remapped[h]     ),
+      .data_i    (tcdm_slave_req_i[h]            ),
       .valid_i   (tcdm_slave_req_valid_i[h]      ),
       .ready_o   (tcdm_slave_req_ready_o[h]      ),
       .data_o    (postreg_tcdm_slave_req[h]      ),
@@ -849,75 +748,57 @@ module mempool_tile
   tcdm_slave_resp_t [NumCoresPerTile-1:0] local_resp_interco_payload;
   addr_t            [NumCoresPerTile-1:0] local_req_interco_addr_int;
 
-  logic [NumCoresPerTile+NumRemoteReqPortsPerTile-1:0][idx_width(NumBanksPerTile)-1:0] local_req_interco_tgt_sel;
-  for (genvar j = 0; unsigned'(j) < NumCoresPerTile; j++) begin: gen_local_req_interco_tgt_sel_local
-    assign local_req_interco_tgt_sel[j]  = local_req_interco_payload_remapped[j].tgt_addr[idx_width(NumBanksPerTile)-1:0];
-  end: gen_local_req_interco_tgt_sel_local
-  for (genvar j = 0; unsigned'(j) < NumRemoteReqPortsPerTile; j++) begin: gen_local_req_interco_tgt_sel_remote
-    assign local_req_interco_tgt_sel[j + NumCoresPerTile]  = postreg_tcdm_slave_req[j].tgt_addr[idx_width(NumBanksPerTile)-1:0];
-  end: gen_local_req_interco_tgt_sel_remote
-
-  stream_xbar #(
-    .NumInp   (NumCoresPerTile + NumRemoteReqPortsPerTile                ),
-    .NumOut   (NumBanksPerTile                                           ),
-    .payload_t(tcdm_slave_req_t                                          )
-  ) i_local_req_interco (
-    .clk_i  (clk_i                                                       ),
-    .rst_ni (rst_ni                                                      ),
-    .flush_i(1'b0                                                        ),
-    // External priority flag
-    .rr_i   ('0                                                          ),
-    // Master
-    .data_i ({postreg_tcdm_slave_req, local_req_interco_payload_remapped}),
-    .valid_i({postreg_tcdm_slave_req_valid, local_req_interco_valid}     ),
-    .ready_o({postreg_tcdm_slave_req_ready, local_req_interco_ready}     ),
-    .sel_i  (local_req_interco_tgt_sel                                   ),
-    // Slave
-    .data_o (superbank_req_payload                                       ),
-    .valid_o(superbank_req_valid                                         ),
-    .ready_i(superbank_req_ready                                         ),
-    .idx_o  (superbank_req_ini_addr                                      )
+  // Bank-side TCDM interconnect: narrow req/resp routing, wide-DMA superbank
+  // demux/mux, per-bank wide-narrow arbitration, and within-superbank bank-id remap.
+  mempool_tcdm_bank_interco #(
+    .NumNarrowReq   (NumCoresPerTile + NumRemoteReqPortsPerTile),
+    .NumNarrowResp  (NumCoresPerTile + NumRemoteRespPortsPerTile),
+    .NumBanksPerTile(NumBanksPerTile  ),
+    .NumSuperbanks  (NumSuperbanks    ),
+    .NarrowDataWidth(DataWidth        ),
+    .WideDataWidth  (DmaDataWidth     ),
+    .ByteOffset     (ByteOffset       ),
+    .SpmBankIdRemap (SpmBankIdRemap   ),
+    .narrow_req_t   (tcdm_slave_req_t ),
+    .narrow_resp_t  (tcdm_slave_resp_t),
+    .wide_req_t     (tcdm_dma_req_t   ),
+    .wide_resp_t    (tcdm_dma_resp_t  ),
+    .group_id_t     (group_id_t       ),
+    .resp_idx_t     (local_resp_interco_addr_t)
+  ) i_tcdm_bank_interco (
+    .clk_i                  (clk_i),
+    .rst_ni                 (rst_ni),
+    .group_id_i             (group_id),
+    // Narrow req inputs: cores at low indices, remote slaves above; concat
+    // order must match the legacy i_local_req_interco order.
+    .slv_narrow_req_i       ({postreg_tcdm_slave_req,       local_req_interco_payload}),
+    .slv_narrow_req_valid_i ({postreg_tcdm_slave_req_valid, local_req_interco_valid  }),
+    .slv_narrow_req_ready_o ({postreg_tcdm_slave_req_ready, local_req_interco_ready  }),
+    // Narrow resp outputs: cores at low indices, remote resp ports above.
+    .slv_narrow_resp_o      ({prereg_tcdm_slave_resp,       local_resp_interco_payload}),
+    .slv_narrow_resp_valid_o({prereg_tcdm_slave_resp_valid, local_resp_interco_valid  }),
+    .slv_narrow_resp_ready_i({prereg_tcdm_slave_resp_ready, local_resp_interco_ready  }),
+    // Wide DMA (single, demuxed/muxed across superbanks inside the module)
+    .slv_wide_req_i         (tcdm_dma_req_i      ),
+    .slv_wide_req_valid_i   (tcdm_dma_req_valid_i),
+    .slv_wide_req_ready_o   (tcdm_dma_req_ready_o),
+    .slv_wide_resp_o        (tcdm_dma_resp_o      ),
+    .slv_wide_resp_valid_o  (tcdm_dma_resp_valid_o),
+    .slv_wide_resp_ready_i  (tcdm_dma_resp_ready_i),
+    // Bank-side request / response.
+    .mst_req_o              (bank_req_payload    ),
+    .mst_req_valid_o        (bank_req_valid      ),
+    .mst_req_ready_i        (bank_req_ready      ),
+    .mst_req_wide_o         (bank_req_wide       ),
+    .mst_req_ini_addr_o     (bank_req_ini_addr   ),
+    .mst_resp_i             (bank_resp_payload   ),
+    .mst_resp_valid_i       (bank_resp_valid     ),
+    .mst_resp_ready_o       (bank_resp_ready     ),
+    .mst_resp_wide_i        (bank_resp_wide      ),
+    // Conditioned resp xbar sel (see gen_superbank_resp_ini_addr above).
+    .mst_resp_ini_addr_i    (superbank_resp_ini_addr)
   );
 
-  stream_xbar #(
-    .NumInp   (NumBanksPerTile                                       ),
-    .NumOut   (NumCoresPerTile + NumRemoteRespPortsPerTile           ),
-    .payload_t(tcdm_slave_resp_t                                     )
-  ) i_local_resp_interco (
-    .clk_i  (clk_i                                                   ),
-    .rst_ni (rst_ni                                                  ),
-    .flush_i(1'b0                                                    ),
-    // External priority flag
-    .rr_i   ('0                                                      ),
-    // Master
-    .data_i (superbank_resp_payload                                  ),
-    .valid_i(superbank_resp_valid                                    ),
-    .ready_o(superbank_resp_ready                                    ),
-    .sel_i  (superbank_resp_ini_addr                                 ),
-    // Slave
-    .data_o ({prereg_tcdm_slave_resp, local_resp_interco_payload}    ),
-    .valid_o({prereg_tcdm_slave_resp_valid, local_resp_interco_valid}),
-    .ready_i({prereg_tcdm_slave_resp_ready, local_resp_interco_ready}),
-    .idx_o  (/* Unused */                                            )
-  );
-
-  /********************
-   *   ID Remapping   *
-   ********************/
-  mempool_bank_id_remapper #(
-    .NumCoresPerTile                      (NumCoresPerTile                     ),
-    .NumRemoteReqPortsPerTile             (NumRemoteReqPortsPerTile            ),
-    .NumBanksPerTile                      (NumBanksPerTile                     ),
-    .TCDMAddrMemWidth                     (TCDMAddrMemWidth                    ),
-    .SpmBankIdRemap                       (SpmBankIdRemap                      )
-  ) i_mempool_tile_id_remapper (
-    .tcdm_dma_req_i                       (tcdm_dma_req_i                      ),
-    .tcdm_slave_req_i                     (tcdm_slave_req_i                    ),
-    .local_req_interco_payload_i          (local_req_interco_payload           ),
-    .tcdm_dma_req_remapped_o              (tcdm_dma_req_remapped               ),
-    .tcdm_slave_req_remapped_o            (tcdm_slave_req_remapped             ),
-    .local_req_interco_payload_remapped_o (local_req_interco_payload_remapped  )
-  );
 
   /*******************
    *   Core De/mux   *
@@ -1022,17 +903,21 @@ module mempool_tile
     assign remote_req_interco_wen   [c] = remote_req_interco[c].wen;
     assign remote_req_interco_amoen [c] = |remote_req_interco[c].wdata.amo;
 
-    // Scramble address before entering TCDM shim for sequential+interleaved memory map
-    address_scrambler #(
-      .AddrWidth         (AddrWidth        ),
-      .ByteOffset        (ByteOffset       ),
-      .NumTiles          (NumTiles         ),
-      .NumBanksPerTile   (NumBanksPerTile  ),
-      .Bypass            (0                ),
-      .SeqMemSizePerTile (SeqMemSizePerTile),
-      .TCDMBaseAddr      (TCDMBaseAddr     ),
-      .TCDMMask          (TCDMMask         )
-    ) i_address_scrambler (
+    // Scramble + remap address before the TCDM shim: stage 1 seq->interleave
+    // swap always on; stage 2 tile-id remap gated by TileIdRemap.
+    mempool_addr_scrambler #(
+      .AddrWidth               (AddrWidth        ),
+      .ByteOffset              (ByteOffset       ),
+      .NumTiles                (NumTiles         ),
+      .NumTilesPerDma          (NumTilesPerDma   ),
+      .NumBanksPerTile         (NumBanksPerTile  ),
+      .Bypass                  (0                ),
+      .SeqMemSizePerTile       (SeqMemSizePerTile),
+      .TCDMBaseAddr            (TCDMBaseAddr     ),
+      .TCDMMask                (TCDMMask         ),
+      .EnableSeqInterleaveSwap (1'b1             ),
+      .EnableTileIdRemap       (TileIdRemap      )
+    ) i_addr_scrambler (
       .address_i (snitch_data_qaddr[c]          ),
       .address_o (snitch_data_qaddr_scrambled[c])
     );
@@ -1044,12 +929,7 @@ module mempool_tile
         .MaxOutStandingTrans (snitch_pkg::NumIntOutstandingLoads),
         .NrTCDM              (2                                 ),
         .NrSoC               (1                                 ),
-        .NumRules            (3                                 ),
-        .ByteOffset          (ByteOffset                        ),
-        .NumTiles            (NumTiles                          ),
-        .NumTilesPerDma      (NumTilesPerDma                    ),
-        .NumBanksPerTile     (NumBanksPerTile                   ),
-        .SeqMemSizePerTile   (SeqMemSizePerTile                 )
+        .NumRules            (3                                 )
       ) i_tcdm_shim (
         .clk_i              (clk_i                                                                              ),
         .rst_ni             (rst_ni                                                                             ),
diff --git a/hardware/src/tcdm_shim.sv b/hardware/src/tcdm_shim.sv
index d1ca964f..5da72f99 100644
--- a/hardware/src/tcdm_shim.sv
+++ b/hardware/src/tcdm_shim.sv
@@ -17,13 +17,6 @@ module tcdm_shim
   parameter int unsigned NrTCDM              = 2             ,
   parameter int unsigned NrSoC               = 1             ,
   parameter int unsigned NumRules            = 1             , // Routing rules
-
-  parameter int unsigned ByteOffset          = 2             ,
-  parameter int unsigned NumTiles            = 256           ,
-  parameter int unsigned NumTilesPerDma      = 16            ,
-  parameter int unsigned NumBanksPerTile     = 16            ,
-  parameter int unsigned SeqMemSizePerTile   = 4*1024        ,
-
   localparam int unsigned StrbWidth          = DataWidth/8   ,
   localparam int unsigned NumOutput          = NrTCDM + NrSoC,
   localparam int unsigned MetaIdWidth        = idx_width(MaxOutStandingTrans)
@@ -80,28 +73,10 @@ module tcdm_shim
 
   // Includes
   `include "common_cells/registers.svh"
-  `define max(a,b) (((a) > (b))? (a) : (b))
-
-  localparam int unsigned BankOffsetBits    = $clog2(NumBanksPerTile);
-  localparam int unsigned TileIdBits        = $clog2(NumTiles);
-  localparam int unsigned TileIdBitsPerDma  = `max(1, $clog2(NumTilesPerDma));
-  localparam int unsigned ConstantBitsLSB   = ByteOffset + BankOffsetBits;
-
-  function automatic logic [TileIdBitsPerDma-1:0] spm_tile_id_remap (
-      logic [TileIdBitsPerDma-1:0] data_in,
-      logic [TileIdBitsPerDma-1:0] idx_i
-  );
-    // if (mempool_pkg::TileIdRemap == 1) begin
-    // spm_tile_id_remap = data_in + idx_i;
-    // end else begin
-    spm_tile_id_remap = data_in;
-    // end
-  endfunction
 
   dreq_t              data_qpayload ;
   dreq_t [NrSoC-1:0]  soc_qpayload ;
   dreq_t [NrTCDM-1:0] tcdm_qpayload;
-  logic  [NrTCDM-1:0][AddrWidth-1:0] tcdm_qpayload_addr_remapped;
 
   dresp_t              data_ppayload ;
   dresp_t [NrSoC-1:0]  soc_ppayload ;
@@ -184,21 +159,8 @@ module tcdm_shim
   );
 
   // Connect TCDM output ports
-  always_comb begin
-    for (int i = 0; i < NrTCDM; i++) begin
-      tcdm_qpayload_addr_remapped[i] = tcdm_qpayload[i].addr;
-      if (tcdm_qpayload[i].addr >= (NumTiles * SeqMemSizePerTile)) begin
-        tcdm_qpayload_addr_remapped[i][ConstantBitsLSB +: TileIdBitsPerDma] =
-          spm_tile_id_remap(
-            tcdm_qpayload[i].addr[ConstantBitsLSB +: TileIdBitsPerDma],
-            tcdm_qpayload[i].addr[(ConstantBitsLSB + TileIdBits) +: TileIdBitsPerDma]
-          );
-      end
-    end
-  end
-
   for (genvar i = 0; i < NrTCDM; i++) begin : gen_tcdm_con
-    assign tcdm_req_tgt_addr_o[i] = tcdm_qpayload_addr_remapped[i] ;
+    assign tcdm_req_tgt_addr_o[i] = tcdm_qpayload[i].addr ;
     assign tcdm_req_wdata_o[i]    = tcdm_qpayload[i].data ;
     assign tcdm_req_amo_o[i]      = tcdm_qpayload[i].amo  ;
     assign tcdm_req_id_o[i]       = tcdm_qpayload[i].id   ;
diff --git a/hardware/src/tcdm_wide_narrow_mux.sv b/hardware/src/tcdm_wide_narrow_mux.sv
deleted file mode 100644
index 33382130..00000000
--- a/hardware/src/tcdm_wide_narrow_mux.sv
+++ /dev/null
@@ -1,143 +0,0 @@
-// Copyright 2020 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-
-// Author: Samuel Riedel <sriedel@iis.ee.ethz.ch>
-
-// This module multiplexes many narrow ports and one wide port onto many narrow
-// ports. The wide port is prioritized.
-module tcdm_wide_narrow_mux #(
-  // Width of narrow data.
-  parameter int unsigned NarrowDataWidth = 0,
-  // Width of wide data.
-  parameter int unsigned WideDataWidth   = 0,
-  // Request type of narrow inputs.
-  parameter type narrow_req_t        = logic,
-  // Response type of narrow inputs.
-  parameter type narrow_rsp_t        = logic,
-  // Request type of wide inputs.
-  parameter type wide_req_t          = logic,
-  // Response type of wide inputs.
-  parameter type wide_rsp_t          = logic,
-  // Group ID type, FlooNoC Added
-  parameter type group_id_t          = logic,
-  // Derived. *Do not override*
-  // Number of narrow inputs.
-  parameter int unsigned NrPorts = WideDataWidth / NarrowDataWidth
-) (
-  input  logic                          clk_i,
-  input  logic                          rst_ni,
-  // Group ID, FlooNoC Added
-  input  group_id_t                     group_id_i,
-  // Narrow inputs
-  input  narrow_req_t [NrPorts-1:0] slv_narrow_req_i,
-  input  logic        [NrPorts-1:0] slv_narrow_req_valid_i,
-  output logic        [NrPorts-1:0] slv_narrow_req_ready_o,
-  output narrow_rsp_t [NrPorts-1:0] slv_narrow_rsp_o,
-  output logic        [NrPorts-1:0] slv_narrow_rsp_valid_o,
-  input  logic        [NrPorts-1:0] slv_narrow_rsp_ready_i,
-  // Wide input
-  input  wide_req_t                 slv_wide_req_i,
-  input  logic                      slv_wide_req_valid_i,
-  output logic                      slv_wide_req_ready_o,
-  output wide_rsp_t                 slv_wide_rsp_o,
-  output logic                      slv_wide_rsp_valid_o,
-  input  logic                      slv_wide_rsp_ready_i,
-  // Multiplexed outputs
-  output narrow_req_t [NrPorts-1:0] mst_req_o,
-  output logic        [NrPorts-1:0] mst_req_wide_o,
-  output logic        [NrPorts-1:0] mst_req_valid_o,
-  input  logic        [NrPorts-1:0] mst_req_ready_i,
-  input  narrow_rsp_t [NrPorts-1:0] mst_rsp_i,
-  input  logic        [NrPorts-1:0] mst_rsp_wide_i,
-  input  logic        [NrPorts-1:0] mst_rsp_valid_i,
-  output logic        [NrPorts-1:0] mst_rsp_ready_o
-);
-
-  localparam int unsigned NarrowBeWidth = NarrowDataWidth/8;
-
-  // Request path
-  logic [NrPorts-1:0] forked_wide_req_valid;
-  logic [NrPorts-1:0] forked_wide_req_ready;
-
-  // Fork the wide request into multiple narrow ones
-  stream_fork #(
-    .N_OUP (NrPorts)
-  ) i_wide_stream_fork (
-    .clk_i  (clk_i                ),
-    .rst_ni (rst_ni               ),
-    .valid_i(slv_wide_req_valid_i ),
-    .ready_o(slv_wide_req_ready_o ),
-    .valid_o(forked_wide_req_valid),
-    .ready_i(forked_wide_req_ready)
-  );
-
-  always_comb begin
-    // Feed-through narrow ports by default
-    mst_req_valid_o = slv_narrow_req_valid_i;
-    slv_narrow_req_ready_o = mst_req_ready_i;
-    mst_req_wide_o = '0;
-    mst_req_o = slv_narrow_req_i;
-    // Block wide by default
-    forked_wide_req_ready = '0;
-
-    for (int i = 0; i < NrPorts; i++) begin
-      if (forked_wide_req_valid[i]) begin
-        // Select the wide port
-        mst_req_valid_o[i] = forked_wide_req_valid[i];
-        forked_wide_req_ready[i] = mst_req_ready_i[i];
-        mst_req_wide_o[i] = 1'b1;
-        mst_req_o[i] = '{
-          wdata: slv_wide_req_i.wdata[i*NarrowDataWidth+:NarrowDataWidth],
-          wen: slv_wide_req_i.wen,
-          be: slv_wide_req_i.be[i*NarrowBeWidth+:NarrowBeWidth],
-          tgt_addr: slv_wide_req_i.tgt_addr,
-          ini_addr: '0,
-          src_group_id: group_id_i // FlooNoC Added
-        };
-        // Block access from narrow ports.
-        slv_narrow_req_ready_o[i] = 1'b0;
-      end
-    end
-  end
-
-  // Response path
-  logic [NrPorts-1:0] forked_wide_rsp_valid;
-  logic [NrPorts-1:0] forked_wide_rsp_ready;
-
-  // Join the multiple narrow requests into one wide one
-  stream_join #(
-    .N_INP (NrPorts)
-  ) i_wide_stream_join (
-    .inp_valid_i(forked_wide_rsp_valid),
-    .inp_ready_o(forked_wide_rsp_ready),
-    .oup_valid_o(slv_wide_rsp_valid_o ),
-    .oup_ready_i(slv_wide_rsp_ready_i )
-  );
-
-  always_comb begin
-    // Broadcast data
-    slv_narrow_rsp_o = mst_rsp_i;
-    // Tie off both interfaces by default
-    slv_narrow_rsp_valid_o = '0;
-    forked_wide_rsp_valid = '0;
-    mst_rsp_ready_o = '0;
-    for (int i = 0; i < NrPorts; i++) begin
-      // Broadcast data from all banks.
-      slv_wide_rsp_o.rdata[i*NarrowDataWidth+:NarrowDataWidth] = mst_rsp_i[i].rdata;
-      // Connect handshake based on selection
-      if (mst_rsp_wide_i[i]) begin
-        forked_wide_rsp_valid[i] = mst_rsp_valid_i[i];
-        mst_rsp_ready_o[i] = forked_wide_rsp_ready[i];
-      end else begin
-        slv_narrow_rsp_valid_o[i] = mst_rsp_valid_i[i];
-        mst_rsp_ready_o[i] = slv_narrow_rsp_ready_i[i];
-      end
-    end
-  end
-
-  // Check parameters
-  if (NrPorts*NarrowDataWidth != WideDataWidth) begin
-    $error("[tcdm_wide_narrow_mux] WideDataWidth must be divisible by NarrowDataWidth.");
-  end
-endmodule
diff --git a/hardware/tb/mempool_tb.sv b/hardware/tb/mempool_tb.sv
index 4ce4fc14..d389276f 100644
--- a/hardware/tb/mempool_tb.sv
+++ b/hardware/tb/mempool_tb.sv
@@ -457,5 +457,6 @@ module mempool_tb;
  * NoC Profiling *
  ****************/
 `include "tb_noc_profiling.svh"
+`include "tb_spm_profiling.svh"
 
 endmodule : mempool_tb
diff --git a/hardware/tb/tb_noc_profiling.svh b/hardware/tb/tb_noc_profiling.svh
index 73622ae0..2fe24a93 100644
--- a/hardware/tb/tb_noc_profiling.svh
+++ b/hardware/tb/tb_noc_profiling.svh
@@ -17,1116 +17,224 @@
   end
 
 `ifdef NOC_PROFILING
-  string  app, log_path, dump_time;
+  // Hierarchical path to group g's FlooNoC wrapper (i_group).
+  `define NOC_GRP(grp) dut.i_mempool_cluster.gen_groups_x[(grp) / NumY].gen_groups_y[(grp) % NumY].gen_rtl_group.i_group
+
+  // ONE FULL per-router / per-tile NoC trace; the export-time --noc-slices flag
+  // chooses the granularity. Each line is one of:
+  //   S <portidx> <io> <start> <end> <state>   run-length: idle(0)/stall(1)/read(2)/write(3)
+  //   P ... one accepted REQUEST flit (addr + XY routing), emitted every handshake cycle
+  //   portidx 0..3 = N/E/S/W mesh ports, 4 = local; io 0=input, 1=output.
+  // To stay under VCS's open-file limit, files are MERGED and lines PREFIXED with a demux idx:
+  //   routers -> router_g<g>_{req,resp}.log  (one per group; <idx> = in-group router id
+  //              <rid>, a flat slot t*ports+p -- routers are remapped so NOT tile/port)
+  //   cores   -> pe_g<g>_t<t>.log            (one per tile; <idx> = core)
+  //   tiles   -> tile_g<g>_t<t>.log          (already one per tile; NO prefix)
+  string  app, log_path;
   integer retval;
-  // File handles and filenames for various profiling logs
-  int     f_2, f_3, f_4, f_5;
-  int     f_final_2, f_final_3, f_final_4, f_final_5;
-  string  fn_2, fn_3, fn_4, fn_5;
-  string  fn_final_2, fn_final_3, fn_final_4, fn_final_5;
-  // Input/output log file descriptors
-  int     req_floo_input_log_fd, resp_floo_input_log_fd;
+  // MERGED file handles: routers -> ONE req + ONE resp file per group (line tagged with
+  // router id); Snitch cores -> ONE file per tile (line tagged with core idx). PE = the
+  // Snitch core's data memory port.
+  int f_rreq  [NumGroups];
+  int f_rresp [NumGroups];
+  int f_tile  [NumGroups][NumTilesPerGroup];
+  int f_pe    [NumGroups][NumTilesPerGroup];
 
   initial begin
-    // Read APP name from command line argument
     void'($value$plusargs("APP=%s", app));
-    // Set profiling output path
-    $sformat(log_path, "noc_profiling");
-    // Create log directory
-    retval = $system({"mkdir -p ", log_path});
-    // Open input/output log files
-    req_floo_input_log_fd  = $fopen($sformatf("%s/req_floo_input.log",  log_path), "w");
-    resp_floo_input_log_fd = $fopen($sformatf("%s/resp_floo_input.log", log_path), "w");
-  end
-
-  // ------------------------------------------------------------
-  // Profiling structures
-  // ------------------------------------------------------------
-
-  tile_level_profile_t            tile_level_profile_q              [NumGroups-1:0][NumTilesPerGroup-1:0];
-  group_level_profile_t           group_level_profile_q             [NumGroups-1:0];
-
-  router_level_profile_t          router_level_profile_req_q        [NumGroups-1:0][NumTilesPerGroup-1:0][NumWideRemoteReqPortsPerTile-1:0];
-  router_local_req_port_profile_t router_local_req_port_profile_q   [NumGroups-1:0][NumTilesPerGroup-1:0][NumWideRemoteReqPortsPerTile-1:0];
-
-  router_level_profile_t          router_level_profile_resp_q       [NumGroups-1:0][NumTilesPerGroup-1:0][NumRemoteRespPortsPerTile-2:0];
-  router_local_resp_port_profile_t router_local_resp_port_profile_q [NumGroups-1:0][NumTilesPerGroup-1:0][NumRemoteRespPortsPerTile-2:0];
-
-  // ------------------------------------------------------------
-  // Tile-level profiling: counts valid and handshake cycles
-  // ------------------------------------------------------------
-
-  generate
-    for (genvar g = 0; g < NumGroups; g++) begin : gen_group
-      for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_tile
-        always_ff @(posedge clk or negedge rst_n) begin
-          if (!rst_n) begin
-            for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-              tile_level_profile_q[g][t].req_vld_cyc_num[p] <= '0;
-              tile_level_profile_q[g][t].req_hsk_cyc_num[p] <= '0;
-            end
-          end else begin
-            for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-              tile_level_profile_q[g][t].req_vld_cyc_num[p] <=
-                  tile_level_profile_q[g][t].req_vld_cyc_num[p] +
-                  $countones(
-                    dut.i_mempool_cluster
-                      .gen_groups_x[g / NumY]
-                      .gen_groups_y[g % NumY]
-                      .i_group
-                      .i_mempool_group
-                      .gen_tiles[t]
-                      .i_tile
-                      .tcdm_master_req_valid_o[p + 1]
-                  );
-
-              tile_level_profile_q[g][t].req_hsk_cyc_num[p] <=
-                  tile_level_profile_q[g][t].req_hsk_cyc_num[p] +
-                  $countones(
-                    dut.i_mempool_cluster
-                      .gen_groups_x[g / NumY]
-                      .gen_groups_y[g % NumY]
-                      .i_group
-                      .i_mempool_group
-                      .gen_tiles[t]
-                      .i_tile
-                      .tcdm_master_req_valid_o[p + 1] &
-                    dut.i_mempool_cluster
-                      .gen_groups_x[g / NumY]
-                      .gen_groups_y[g % NumY]
-                      .i_group
-                      .i_mempool_group
-                      .gen_tiles[t]
-                      .i_tile
-                      .tcdm_master_req_ready_i[p + 1]
-                  );
-            end
-          end
-        end
-      end
-    end
-  endgenerate
-
-  // ------------------------------------------------------------
-  // Group-level profiling signals
-  // ------------------------------------------------------------
-
-  // Count of requests targeting the same bank from multiple tiles
-  logic [NumGroups-1:0]
-        [NumTilesPerGroup * NumBanksPerTile - 1:0]
-        [$clog2(NumTilesPerGroup * (NumRemoteReqPortsPerTile - 1)) : 0]
-        group_xbar_req_to_same_bank_count;
-
-  // Count of bank access conflicts from multiple requesters
-  logic [NumGroups-1:0]
-        [NumTilesPerGroup * NumBanksPerTile - 1:0]
-        [$clog2(NumTilesPerGroup * (NumRemoteReqPortsPerTile - 1)) : 0]
-        group_xbar_req_to_same_bank_conflict_count;
-
-  // Sum of conflict counts across all banks in a group
-  logic [NumGroups-1:0]
-        [$clog2(NumTilesPerGroup * (NumRemoteReqPortsPerTile - 1)) : 0]
-        group_xbar_req_to_same_bank_conflict_count_sum;
-
-  // Per-port valid signal for incoming requests to TCDM crossbar
-  logic [NumX-1:0]
-        [NumY-1:0]
-        [NumRemoteReqPortsPerTile - 2:0]
-        [NumTilesPerGroup-1:0]
-        tcdm_slave_req_valid;
-
-  // Per-port target address for incoming requests to TCDM crossbar
-  logic [NumX-1:0]
-        [NumY-1:0]
-        [NumRemoteReqPortsPerTile - 2:0]
-        [NumTilesPerGroup-1:0]
-        [idx_width(NumTilesPerGroup) + idx_width(NumBanksPerTile) - 1 : 0]
-        tcdm_slave_req_tgt_addr;
-
-  // ------------------------------------------------------------
-  // Capture TCDM slave port request valid & address per tile/port
-  // ------------------------------------------------------------
-  generate
-    for (genvar x_dim = 0; x_dim < NumX; x_dim++) begin : gen_x
-      for (genvar y_dim = 0; y_dim < NumY; y_dim++) begin : gen_y
-        for (genvar p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin : gen_port
-          for (genvar t_i = 0; t_i < NumTilesPerGroup; t_i++) begin : gen_tile
-            assign tcdm_slave_req_valid[x_dim][y_dim][p][t_i] =
-                dut.i_mempool_cluster
-                  .gen_groups_x[x_dim]
-                  .gen_groups_y[y_dim]
-                  .i_group
-                  .floo_req_from_router_before_xbar_valid_per_port[p + 1][t_i];
-
-            assign tcdm_slave_req_tgt_addr[x_dim][y_dim][p][t_i] =
-                dut.i_mempool_cluster
-                  .gen_groups_x[x_dim]
-                  .gen_groups_y[y_dim]
-                  .i_group
-                  .floo_req_from_router[t_i][p + 1]
-                  .hdr.tgt_addr[
-                    idx_width(NumTilesPerGroup) + idx_width(NumBanksPerTile) - 1 : 0
-                  ];
-          end
-        end
-      end
-    end
-  endgenerate
-
-  always_comb begin
-    group_xbar_req_to_same_bank_count = '0;
-
+    log_path = "noc_profiling";
+    retval   = $system({"mkdir -p ", log_path});
+    // Tiles keep their id. Routers use a FLAT in-group router id (r = t*NumPortsPerTile + p):
+    // the req/resp remappers shuffle logical traffic across physical routers, so [tile][port]
+    // is just a physical slot, not a tile/port assignment.
     for (int g = 0; g < NumGroups; g++) begin
-      for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-        for (int t_i = 0; t_i < NumTilesPerGroup; t_i++) begin
-          // If source port from router is valid
-          if (tcdm_slave_req_valid[g / NumY][g % NumY][p][t_i]) begin
-            // Then destination port count +1
-            group_xbar_req_to_same_bank_count[g][
-              tcdm_slave_req_tgt_addr[g / NumY][g % NumY][p][t_i]
-            ] += 1;
-          end
-        end
+      f_rreq[g]  = $fopen($sformatf("%s/router_g%0d_req.log",  log_path, g), "w");
+      f_rresp[g] = $fopen($sformatf("%s/router_g%0d_resp.log", log_path, g), "w");
+      for (int t = 0; t < NumTilesPerGroup; t++) begin
+        f_tile[g][t] = $fopen($sformatf("%s/tile_g%0d_t%0d.log", log_path, g, t), "w");
+        f_pe[g][t]   = $fopen($sformatf("%s/pe_g%0d_t%0d.log",   log_path, g, t), "w");
       end
     end
   end
 
-  always_comb begin
-    group_xbar_req_to_same_bank_conflict_count     = '0;
-    group_xbar_req_to_same_bank_conflict_count_sum = '0;
-
-    for (int g = 0; g < NumGroups; g++) begin
-      for (int b = 0; b < NumTilesPerGroup * NumBanksPerTile; b++) begin
-        if (group_xbar_req_to_same_bank_count[g][b] > 0) begin
-          // Minus the one that is not a conflict
-          group_xbar_req_to_same_bank_conflict_count[g][b] =
-              group_xbar_req_to_same_bank_count[g][b] - 1;
-        end
-
-        group_xbar_req_to_same_bank_conflict_count_sum[g] +=
-            group_xbar_req_to_same_bank_conflict_count[g][b];
-      end
-    end
-  end
+  // Module-scope state registers so the end-of-sim `final` below can flush them.
+  // router: [group][tile][port][portidx 0..4][io 0..1]
+  logic [1:0]  rsq_st    [NumGroups][NumTilesPerGroup][NumWideRemoteReqPortsPerTile][5][2];
+  logic [63:0] rsq_start [NumGroups][NumTilesPerGroup][NumWideRemoteReqPortsPerTile][5][2];
+  logic [1:0]  rsp_st    [NumGroups][NumTilesPerGroup][NumRemoteRespPortsPerTile-1][5][2];
+  logic [63:0] rsp_start [NumGroups][NumTilesPerGroup][NumRemoteRespPortsPerTile-1][5][2];
+  // tile: [group][tile][port]
+  logic [1:0]  ts_mreq_st [NumGroups][NumTilesPerGroup][NumRemoteReqPortsPerTile];  logic [63:0] ts_mreq_s [NumGroups][NumTilesPerGroup][NumRemoteReqPortsPerTile];
+  logic [1:0]  ts_sreq_st [NumGroups][NumTilesPerGroup][NumRemoteReqPortsPerTile];  logic [63:0] ts_sreq_s [NumGroups][NumTilesPerGroup][NumRemoteReqPortsPerTile];
+  logic [1:0]  ts_mrsp_st [NumGroups][NumTilesPerGroup][NumRemoteRespPortsPerTile]; logic [63:0] ts_mrsp_s [NumGroups][NumTilesPerGroup][NumRemoteRespPortsPerTile];
+  logic [1:0]  ts_srsp_st [NumGroups][NumTilesPerGroup][NumRemoteRespPortsPerTile]; logic [63:0] ts_srsp_s [NumGroups][NumTilesPerGroup][NumRemoteRespPortsPerTile];
+  // PE (Snitch core data port): req = data_q* (out, read/write by qwrite), resp = data_p* (in).
+  logic [1:0]  pe_req_st [NumGroups][NumTilesPerGroup][NumCoresPerTile]; logic [63:0] pe_req_s [NumGroups][NumTilesPerGroup][NumCoresPerTile];
+  logic [1:0]  pe_rsp_st [NumGroups][NumTilesPerGroup][NumCoresPerTile]; logic [63:0] pe_rsp_s [NumGroups][NumTilesPerGroup][NumCoresPerTile];
 
+  // ------------------------------------------------------------
+  // Router port capture (4 mesh dirs + local, input + output) -> per-router file.
+  // S lines RLE idle/stall/read/write; P lines log every accepted request flit
+  // (req routers only). read/write split via payload.wen.
+  // ------------------------------------------------------------
   generate
-    for (genvar g = 0; g < NumGroups; g++) begin : gen_group_level_profile
+    for (genvar g = 0; g < NumGroups; g++) begin : gen_rstate_g
       always_ff @(posedge clk or negedge rst_n) begin
         if (!rst_n) begin
-          for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-            group_level_profile_q[g].req_vld_cyc_num[p] = '0;
-            group_level_profile_q[g].req_hsk_cyc_num[p] = '0;
-          end
-          group_level_profile_q[g].req_vld_cyc_more_than_one_hit_same_bank_num = '0;
+          rsq_st[g] <= '{default: '0}; rsq_start[g] <= '{default: '0};
+          rsp_st[g] <= '{default: '0}; rsp_start[g] <= '{default: '0};
         end else begin
-          for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-            group_level_profile_q[g].req_vld_cyc_num[p] +=
-                $countones(
-                  dut.i_mempool_cluster
-                    .gen_groups_x[g / NumY]
-                    .gen_groups_y[g % NumY]
-                    .i_group
-                    .floo_req_from_router_before_xbar_valid_per_port[p + 1]
-                    [NumTilesPerGroup - 1 : 0]
-                );
-
-            group_level_profile_q[g].req_hsk_cyc_num[p] +=
-                $countones(
-                  dut.i_mempool_cluster
-                    .gen_groups_x[g / NumY]
-                    .gen_groups_y[g % NumY]
-                    .i_group
-                    .floo_req_from_router_before_xbar_valid_per_port[p + 1]
-                    [NumTilesPerGroup - 1 : 0] &
-
-                  dut.i_mempool_cluster
-                    .gen_groups_x[g / NumY]
-                    .gen_groups_y[g % NumY]
-                    .i_group
-                    .floo_req_from_router_before_xbar_ready_per_port[p + 1]
-                    [NumTilesPerGroup - 1 : 0]
-                );
-          end
-
-          group_level_profile_q[g].req_vld_cyc_more_than_one_hit_same_bank_num +=
-              group_xbar_req_to_same_bank_conflict_count_sum[g];
-        end
-      end
-    end
-  endgenerate
-
-  // router level profiling
-  generate
-    for (genvar g = 0; g < NumGroups; g++) begin : gen_router_profile_per_group
-      for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_router_profile_per_tile
-        for (genvar p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin : gen_req_router_profile_per_remote_port
-          if (p < NumNarrowRemoteReqPortsPerTile) begin
-            always_ff @(posedge clk or negedge rst_n) begin
-              if (!rst_n) begin
-                router_local_req_port_profile_q[g][t][p].read_req_num  = '0;
-                router_local_req_port_profile_q[g][t][p].write_req_num = '0;
-
-                for (int router_p = 0; router_p < 4; router_p++) begin
-                  router_level_profile_req_q[g][t][p].in_vld_cyc_num[router_p]  = '0;
-                  router_level_profile_req_q[g][t][p].in_hsk_cyc_num[router_p]  = '0;
-                  router_level_profile_req_q[g][t][p].out_vld_cyc_num[router_p] = '0;
-                  router_level_profile_req_q[g][t][p].out_hsk_cyc_num[router_p] = '0;
+          for (int t = 0; t < NumTilesPerGroup; t++) begin
+            // ---- wide-req routers ----
+            for (int p = 0; p < NumWideRemoteReqPortsPerTile; p++) begin
+              automatic int rid = t*NumWideRemoteReqPortsPerTile + p;  // merged-file router tag
+              for (int d = 0; d < 4; d++) begin
+                automatic logic [1:0] si = `NOC_GRP(g).floo_tcdm_wide_req_valid_in_trans[t][p][d]
+                  ? (`NOC_GRP(g).floo_tcdm_wide_req_ready_out_trans[t][p][d]
+                     ? (`NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].payload.wen ? 2'd3 : 2'd2) : 2'd1) : 2'd0;
+                automatic logic [1:0] so = `NOC_GRP(g).floo_tcdm_wide_req_valid_out_trans[t][p][d]
+                  ? (`NOC_GRP(g).floo_tcdm_wide_req_ready_in_trans[t][p][d]
+                     ? (`NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].payload.wen ? 2'd3 : 2'd2) : 2'd1) : 2'd0;
+                if (si != rsq_st[g][t][p][d][0]) begin
+                  $fwrite(f_rreq[g], "%0d S %0d 0 %0d %0d %0d\n", rid, d, rsq_start[g][t][p][d][0], cycle_q, rsq_st[g][t][p][d][0]);
+                  rsq_st[g][t][p][d][0] <= si; rsq_start[g][t][p][d][0] <= cycle_q;
                 end
-              end else begin
-                router_local_req_port_profile_q[g][t][p].read_req_num +=
-                    $countones(
-                      (|(
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_narrow_req_router_j[p]
-                          .i_floo_narrow_req_router.valid_i[0] &
-
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_narrow_req_router_j[p]
-                          .i_floo_narrow_req_router.ready_i[0]
-                      )) & ~dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_narrow_req_router_j[p]
-                            .i_floo_narrow_req_router.data_i[0][0].payload.wen
-                    );
-
-                for (int router_p = 0; router_p < 4; router_p++) begin
-                  // narrow req router
-
-                  router_level_profile_req_q[g][t][p].in_vld_cyc_num[router_p] +=
-                      $countones(
-                        |dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_narrow_req_router_j[p]
-                          .i_floo_narrow_req_router.valid_i[router_p + 1]
-                      );
-
-                  router_level_profile_req_q[g][t][p].in_hsk_cyc_num[router_p] +=
-                      $countones(
-                        |(
-                          dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_narrow_req_router_j[p]
-                            .i_floo_narrow_req_router.valid_i[router_p + 1] &
-
-                          dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_narrow_req_router_j[p]
-                            .i_floo_narrow_req_router.ready_o[router_p + 1]
-                        )
-                      );
-
-                  router_level_profile_req_q[g][t][p].out_vld_cyc_num[router_p] +=
-                      $countones(
-                        |dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_narrow_req_router_j[p]
-                          .i_floo_narrow_req_router.valid_o[router_p + 1]
-                      );
-
-                  router_level_profile_req_q[g][t][p].out_hsk_cyc_num[router_p] +=
-                      $countones(
-                        |(
-                          dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_narrow_req_router_j[p]
-                            .i_floo_narrow_req_router.valid_o[router_p + 1] &
-
-                          dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_narrow_req_router_j[p]
-                            .i_floo_narrow_req_router.ready_i[router_p + 1]
-                        )
-                      );
+                if (so != rsq_st[g][t][p][d][1]) begin
+                  $fwrite(f_rreq[g], "%0d S %0d 1 %0d %0d %0d\n", rid, d, rsq_start[g][t][p][d][1], cycle_q, rsq_st[g][t][p][d][1]);
+                  rsq_st[g][t][p][d][1] <= so; rsq_start[g][t][p][d][1] <= cycle_q;
                 end
+                // P: portidx io cycle wen tgt_addr dst_x dst_y src_x src_y src_tile core meta_id
+                if (si >= 2)  // input handshake -> one request flit accepted
+                  $fwrite(f_rreq[g], "%0d P %0d 0 %0d %0d %0h %0d %0d %0d %0d %0d %0d %0d\n", rid, d, cycle_q,
+                    `NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].payload.wen,
+                    `NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].hdr.tgt_addr,
+                    `NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].hdr.dst_id.x,
+                    `NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].hdr.dst_id.y,
+                    `NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].hdr.src_id.x,
+                    `NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].hdr.src_id.y,
+                    `NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].hdr.src_tile_id,
+                    `NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].hdr.core_id,
+                    `NOC_GRP(g).floo_tcdm_wide_req_in_trans[t][p][d].hdr.meta_id);
+                if (so >= 2)  // output handshake
+                  $fwrite(f_rreq[g], "%0d P %0d 1 %0d %0d %0h %0d %0d %0d %0d %0d %0d %0d\n", rid, d, cycle_q,
+                    `NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].payload.wen,
+                    `NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].hdr.tgt_addr,
+                    `NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].hdr.dst_id.x,
+                    `NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].hdr.dst_id.y,
+                    `NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].hdr.src_id.x,
+                    `NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].hdr.src_id.y,
+                    `NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].hdr.src_tile_id,
+                    `NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].hdr.core_id,
+                    `NOC_GRP(g).floo_tcdm_wide_req_out_trans[t][p][d].hdr.meta_id);
               end
-            end
-          end
-          else begin
-            always_ff @(posedge clk or negedge rst_n) begin
-              if (!rst_n) begin
-                router_local_req_port_profile_q[g][t][p].read_req_num  = '0;
-                router_local_req_port_profile_q[g][t][p].write_req_num = '0;
-
-                for (int router_p = 0; router_p < 4; router_p++) begin
-                  router_level_profile_req_q[g][t][p].in_vld_cyc_num[router_p]  = '0;
-                  router_level_profile_req_q[g][t][p].in_hsk_cyc_num[router_p]  = '0;
-                  router_level_profile_req_q[g][t][p].out_vld_cyc_num[router_p] = '0;
-                  router_level_profile_req_q[g][t][p].out_hsk_cyc_num[router_p] = '0;
+              begin : req_local
+                automatic logic [1:0] sli = `NOC_GRP(g).floo_tcdm_rdwr_req_to_router_vc_valid[t][p]
+                  ? (`NOC_GRP(g).floo_tcdm_rdwr_req_to_router_vc_ready[t][p]
+                     ? (`NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].payload.wen ? 2'd3 : 2'd2) : 2'd1) : 2'd0;
+                automatic logic [1:0] slo = `NOC_GRP(g).floo_tcdm_rdwr_req_from_router_vc_valid[t][p]
+                  ? (`NOC_GRP(g).floo_tcdm_rdwr_req_from_router_vc_ready[t][p]
+                     ? (`NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].payload.wen ? 2'd3 : 2'd2) : 2'd1) : 2'd0;
+                if (sli != rsq_st[g][t][p][4][0]) begin
+                  $fwrite(f_rreq[g], "%0d S 4 0 %0d %0d %0d\n", rid, rsq_start[g][t][p][4][0], cycle_q, rsq_st[g][t][p][4][0]);
+                  rsq_st[g][t][p][4][0] <= sli; rsq_start[g][t][p][4][0] <= cycle_q;
                 end
-              end else begin
-                router_local_req_port_profile_q[g][t][p].read_req_num +=
-                    $countones(
-                      (|(
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                          .i_floo_wide_req_router.valid_i[0] &
-
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                          .i_floo_wide_req_router.ready_i[0]
-                      )) & ~dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                            .i_floo_wide_req_router.data_i[0][0].payload.wen
-                    );
-
-                router_local_req_port_profile_q[g][t][p].write_req_num +=
-                    $countones(
-                      (|(
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                          .i_floo_wide_req_router.valid_i[0] &
-
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                          .i_floo_wide_req_router.ready_i[0]
-                      )) & dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                            .i_floo_wide_req_router.data_i[0][0].payload.wen
-                    );
-
-                for (int router_p = 0; router_p < 4; router_p++) begin
-                  // wide req router
-
-                  router_level_profile_req_q[g][t][p].in_vld_cyc_num[router_p] +=
-                      $countones(
-                        |dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                          .i_floo_wide_req_router.valid_i[router_p + 1]
-                      );
-
-                  router_level_profile_req_q[g][t][p].in_hsk_cyc_num[router_p] +=
-                      $countones(
-                        |(
-                          dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                            .i_floo_wide_req_router.valid_i[router_p + 1] &
-
-                          dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                            .i_floo_wide_req_router.ready_o[router_p + 1]
-                        )
-                      );
-
-                  router_level_profile_req_q[g][t][p].out_vld_cyc_num[router_p] +=
-                      $countones(
-                        |dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                          .i_floo_wide_req_router.valid_o[router_p + 1]
-                      );
-
-                  router_level_profile_req_q[g][t][p].out_hsk_cyc_num[router_p] +=
-                      $countones(
-                        |(
-                          dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                            .i_floo_wide_req_router.valid_o[router_p + 1] &
-
-                          dut.i_mempool_cluster
-                            .gen_groups_x[g / NumY]
-                            .gen_groups_y[g % NumY]
-                            .i_group
-                            .gen_router_router_i[t]
-                            .gen_router_wide_req_router_j[p - NumNarrowRemoteReqPortsPerTile]
-                            .i_floo_wide_req_router.ready_i[router_p + 1]
-                        )
-                      );
+                if (slo != rsq_st[g][t][p][4][1]) begin
+                  $fwrite(f_rreq[g], "%0d S 4 1 %0d %0d %0d\n", rid, rsq_start[g][t][p][4][1], cycle_q, rsq_st[g][t][p][4][1]);
+                  rsq_st[g][t][p][4][1] <= slo; rsq_start[g][t][p][4][1] <= cycle_q;
                 end
+                if (sli >= 2)  // local input (injection from tile) handshake
+                  $fwrite(f_rreq[g], "%0d P 4 0 %0d %0d %0h %0d %0d %0d %0d %0d %0d %0d\n", rid, cycle_q,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].payload.wen,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].hdr.tgt_addr,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].hdr.dst_id.x,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].hdr.dst_id.y,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].hdr.src_id.x,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].hdr.src_id.y,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].hdr.src_tile_id,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].hdr.core_id,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_to_router[t][p].hdr.meta_id);
+                if (slo >= 2)  // local output (ejection to tile) handshake
+                  $fwrite(f_rreq[g], "%0d P 4 1 %0d %0d %0h %0d %0d %0d %0d %0d %0d %0d\n", rid, cycle_q,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].payload.wen,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].hdr.tgt_addr,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].hdr.dst_id.x,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].hdr.dst_id.y,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].hdr.src_id.x,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].hdr.src_id.y,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].hdr.src_tile_id,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].hdr.core_id,
+                    `NOC_GRP(g).floo_tcdm_rdwr_req_from_router[t][p].hdr.meta_id);
               end
             end
-          end
-        end
-        for (genvar p = 0; p < (NumRemoteRespPortsPerTile - 1); p++) begin : gen_resp_router_profile_per_remote_port
-          always_ff @(posedge clk or negedge rst_n) begin
-            if (!rst_n) begin
-              router_local_resp_port_profile_q[g][t][p].req_num = '0;
-
-              for (int router_p = 0; router_p < 4; router_p++) begin
-                router_level_profile_resp_q[g][t][p].in_vld_cyc_num[router_p]  = '0;
-                router_level_profile_resp_q[g][t][p].in_hsk_cyc_num[router_p]  = '0;
-                router_level_profile_resp_q[g][t][p].out_vld_cyc_num[router_p] = '0;
-                router_level_profile_resp_q[g][t][p].out_hsk_cyc_num[router_p] = '0;
-              end
-            end else begin
-              router_local_resp_port_profile_q[g][t][p].req_num +=
-                  $countones(
-                    |(
-                      dut.i_mempool_cluster
-                        .gen_groups_x[g / NumY]
-                        .gen_groups_y[g % NumY]
-                        .i_group
-                        .gen_router_router_i[t]
-                        .gen_router_wide_resp_router_j[p + 1]
-                        .i_floo_wide_resp_router.valid_i[0] &
-
-                      dut.i_mempool_cluster
-                        .gen_groups_x[g / NumY]
-                        .gen_groups_y[g % NumY]
-                        .i_group
-                        .gen_router_router_i[t]
-                        .gen_router_wide_resp_router_j[p + 1]
-                        .i_floo_wide_resp_router.ready_i[0]
-                    )
-                  );
-
-              for (int router_p = 0; router_p < 4; router_p++) begin
-                // resp router
-
-                router_level_profile_resp_q[g][t][p].in_vld_cyc_num[router_p] +=
-                    $countones(
-                      |dut.i_mempool_cluster
-                        .gen_groups_x[g / NumY]
-                        .gen_groups_y[g % NumY]
-                        .i_group
-                        .gen_router_router_i[t]
-                        .gen_router_wide_resp_router_j[p + 1]
-                        .i_floo_wide_resp_router.valid_i[router_p + 1]
-                    );
-
-                router_level_profile_resp_q[g][t][p].in_hsk_cyc_num[router_p] +=
-                    $countones(
-                      |(
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_resp_router_j[p + 1]
-                          .i_floo_wide_resp_router.valid_i[router_p + 1] &
-
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_resp_router_j[p + 1]
-                          .i_floo_wide_resp_router.ready_o[router_p + 1]
-                      )
-                    );
-
-                router_level_profile_resp_q[g][t][p].out_vld_cyc_num[router_p] +=
-                    $countones(
-                      |dut.i_mempool_cluster
-                        .gen_groups_x[g / NumY]
-                        .gen_groups_y[g % NumY]
-                        .i_group
-                        .gen_router_router_i[t]
-                        .gen_router_wide_resp_router_j[p + 1]
-                        .i_floo_wide_resp_router.valid_o[router_p + 1]
-                    );
-
-                router_level_profile_resp_q[g][t][p].out_hsk_cyc_num[router_p] +=
-                    $countones(
-                      |(
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_resp_router_j[p + 1]
-                          .i_floo_wide_resp_router.valid_o[router_p + 1] &
-
-                        dut.i_mempool_cluster
-                          .gen_groups_x[g / NumY]
-                          .gen_groups_y[g % NumY]
-                          .i_group
-                          .gen_router_router_i[t]
-                          .gen_router_wide_resp_router_j[p + 1]
-                          .i_floo_wide_resp_router.ready_i[router_p + 1]
-                      )
-                    );
-              end
-            end
-          end
-        end
-      end
-    end
-  endgenerate
-
-  always_ff @(posedge clk) begin
-    if (rst_n) begin
-      // if (cycle_q[19:0] == 'h80000) begin
-      if (
-          ((cycle_q[63:0] < 'h8000) &&
-           ((cycle_q[10:0] == 11'h400) || (cycle_q[10:0] == 11'h000))) ||
-          (cycle_q[15:0] == 'h8000)
-         ) begin
-
-        $sformat(fn_2, "%s/tile_level_profile_q_%8x.log", log_path, cycle_q);
-        f_2 = $fopen(fn_2, "w");
-        $display("[Tracer] Logging tile_level_profile_q to %s", fn_2);
-
-        $sformat(fn_3, "%s/group_level_profile_q_%8x.log", log_path, cycle_q);
-        f_3 = $fopen(fn_3, "w");
-        $display("[Tracer] Logging group_level_profile_q to %s", fn_3);
-
-        $sformat(fn_4, "%s/router_level_profile_q_%8x.log", log_path, cycle_q);
-        f_4 = $fopen(fn_4, "w");
-        $display("[Tracer] Logging router_level_profile_q to %s", fn_4);
-
-        $sformat(fn_5, "%s/router_local_input_profile_q_%8x.log", log_path, cycle_q);
-        f_5 = $fopen(fn_5, "w");
-        $display("[Tracer] Logging router_local_input_profile_q to %s", fn_5);
-
-        $timeformat(-9, 0, "", 10);
-        $sformat(dump_time, "dump time %t, cycle %8d #;\n", $time, cycle_q);
-        $fwrite(f_2, dump_time);
-        $fwrite(f_3, dump_time);
-        $fwrite(f_4, dump_time);
-        $fwrite(f_5, dump_time);
-
-        // tile level
-        for (int g = 0; g < NumGroups; g++) begin
-          for (int t_i = 0; t_i < NumTilesPerGroup; t_i++) begin
-            for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-              automatic string extras_str_2;
-              extras_str_2 = $sformatf(
-                "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'req_vld_cyc_num': %03d, 'req_hsk_cyc_num': %03d, 'util': %.2f\n",
-                g, t_i, p,
-                tile_level_profile_q[g][t_i].req_vld_cyc_num[p],
-                tile_level_profile_q[g][t_i].req_hsk_cyc_num[p],
-                (tile_level_profile_q[g][t_i].req_vld_cyc_num[p] == 0) ? 0.0 :
-                ((tile_level_profile_q[g][t_i].req_hsk_cyc_num[p] * 1.0) /
-                 (tile_level_profile_q[g][t_i].req_vld_cyc_num[p] * 1.0))
-              );
-              $fwrite(f_2, extras_str_2);
-            end
-          end
-        end
-        $fclose(f_2);
-
-        // group level
-        for (int g = 0; g < NumGroups; g++) begin
-          int unsigned req_vld_cyc_num_sum;
-          int unsigned req_hsk_cyc_num_sum;
-          automatic string extras_str_3;
-
-          req_vld_cyc_num_sum = 0;
-          req_hsk_cyc_num_sum = 0;
-
-          for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-            req_vld_cyc_num_sum += group_level_profile_q[g].req_vld_cyc_num[p];
-            req_hsk_cyc_num_sum += group_level_profile_q[g].req_hsk_cyc_num[p];
-          end
-
-          extras_str_3 = $sformatf(
-            "{'GROUP': %03d, 'req_vld_cyc_num': %03d, 'req_hsk_cyc_num': %03d, "
-            "'req_vld_cyc_more_than_one_hit_same_bank_num': %03d, 'util': %.2f\n",
-            g,
-            req_vld_cyc_num_sum,
-            req_hsk_cyc_num_sum,
-            group_level_profile_q[g].req_vld_cyc_more_than_one_hit_same_bank_num,
-            ((req_vld_cyc_num_sum - group_level_profile_q[g].req_vld_cyc_more_than_one_hit_same_bank_num) == 0) ?
-              0.0 :
-              ((req_hsk_cyc_num_sum * 1.0) /
-               ((req_vld_cyc_num_sum - group_level_profile_q[g].req_vld_cyc_more_than_one_hit_same_bank_num) * 1.0))
-          );
-
-          $fwrite(f_3, extras_str_3);
-        end
-        $fclose(f_3);
-
-        // router level
-        for (int g = 0; g < NumGroups; g++) begin
-          for (int t = 0; t < NumTilesPerGroup; t++) begin
-            for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-              if (p < NumNarrowRemoteReqPortsPerTile) begin
-                // narrow req
-                for (int dir = 0; dir < 4; dir++) begin
-                  automatic string extras_str_4;
-                  extras_str_4 = $sformatf(
-                    "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'REQ_RSP': 0, "
-                    "'TYPE': 0, 'DIR': %03d, 'in_vld_cyc_num': %03d, 'in_hsk_cyc_num': %03d, "
-                    "'out_vld_cyc_num': %03d, 'out_hsk_cyc_num': %03d, "
-                    "'in_util': %.2f, 'out_util': %.2f\n",
-                    g, t, p, dir,
-                    router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir],
-                    router_level_profile_req_q[g][t][p].in_hsk_cyc_num[dir],
-                    router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir],
-                    router_level_profile_req_q[g][t][p].out_hsk_cyc_num[dir],
-                    (router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir] > 0) ?
-                      (router_level_profile_req_q[g][t][p].in_hsk_cyc_num[dir] * 1.0) /
-                      (router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir] * 1.0) :
-                      0,
-                    (router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir] > 0) ?
-                      (router_level_profile_req_q[g][t][p].out_hsk_cyc_num[dir] * 1.0) /
-                      (router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir] * 1.0) :
-                      0
-                  );
-                  $fwrite(f_4, extras_str_4);
+            // ---- resp routers (router slot p+1; no read/write split). P lines log every
+            //      accepted RESPONSE flit; a resp flit has no tgt_addr. hdr carries dst_id
+            //      (requester it returns to), src_id (responder), tile_id/core_id (requester).
+            //   P <portidx> <io> <cycle> <dst_x> <dst_y> <src_x> <src_y> <req_tile> <req_core> <meta_id> ----
+            for (int p = 0; p < NumRemoteRespPortsPerTile-1; p++) begin
+              automatic int rid = t*(NumRemoteRespPortsPerTile-1) + p;  // merged-file router tag
+              for (int d = 0; d < 4; d++) begin
+                automatic logic [1:0] si = `NOC_GRP(g).floo_tcdm_resp_valid_in_trans[t][p+1][d]
+                  ? (`NOC_GRP(g).floo_tcdm_resp_ready_out_trans[t][p+1][d] ? 2'd2 : 2'd1) : 2'd0;
+                automatic logic [1:0] so = `NOC_GRP(g).floo_tcdm_resp_valid_out_trans[t][p+1][d]
+                  ? (`NOC_GRP(g).floo_tcdm_resp_ready_in_trans[t][p+1][d] ? 2'd2 : 2'd1) : 2'd0;
+                if (si != rsp_st[g][t][p][d][0]) begin
+                  $fwrite(f_rresp[g], "%0d S %0d 0 %0d %0d %0d\n", rid, d, rsp_start[g][t][p][d][0], cycle_q, rsp_st[g][t][p][d][0]);
+                  rsp_st[g][t][p][d][0] <= si; rsp_start[g][t][p][d][0] <= cycle_q;
                 end
-              end else begin
-                // wide req
-                for (int dir = 0; dir < 4; dir++) begin
-                  automatic string extras_str_4;
-                  extras_str_4 = $sformatf(
-                    "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'REQ_RSP': 0, "
-                    "'TYPE': 1, 'DIR': %03d, 'in_vld_cyc_num': %03d, 'in_hsk_cyc_num': %03d, "
-                    "'out_vld_cyc_num': %03d, 'out_hsk_cyc_num': %03d, "
-                    "'in_util': %.2f, 'out_util': %.2f\n",
-                    g, t, p, dir,
-                    router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir],
-                    router_level_profile_req_q[g][t][p].in_hsk_cyc_num[dir],
-                    router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir],
-                    router_level_profile_req_q[g][t][p].out_hsk_cyc_num[dir],
-                    (router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir] > 0) ?
-                      (router_level_profile_req_q[g][t][p].in_hsk_cyc_num[dir] * 1.0) /
-                      (router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir] * 1.0) :
-                      0,
-                    (router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir] > 0) ?
-                      (router_level_profile_req_q[g][t][p].out_hsk_cyc_num[dir] * 1.0) /
-                      (router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir] * 1.0) :
-                      0
-                  );
-                  $fwrite(f_4, extras_str_4);
+                if (so != rsp_st[g][t][p][d][1]) begin
+                  $fwrite(f_rresp[g], "%0d S %0d 1 %0d %0d %0d\n", rid, d, rsp_start[g][t][p][d][1], cycle_q, rsp_st[g][t][p][d][1]);
+                  rsp_st[g][t][p][d][1] <= so; rsp_start[g][t][p][d][1] <= cycle_q;
                 end
+                if (si >= 2)  // mesh input handshake -> one response flit accepted
+                  $fwrite(f_rresp[g], "%0d P %0d 0 %0d %0d %0d %0d %0d %0d %0d %0d\n", rid, d, cycle_q,
+                    `NOC_GRP(g).floo_tcdm_resp_in_trans[t][p+1][d].hdr.dst_id.x,
+                    `NOC_GRP(g).floo_tcdm_resp_in_trans[t][p+1][d].hdr.dst_id.y,
+                    `NOC_GRP(g).floo_tcdm_resp_in_trans[t][p+1][d].hdr.src_id.x,
+                    `NOC_GRP(g).floo_tcdm_resp_in_trans[t][p+1][d].hdr.src_id.y,
+                    `NOC_GRP(g).floo_tcdm_resp_in_trans[t][p+1][d].hdr.tile_id,
+                    `NOC_GRP(g).floo_tcdm_resp_in_trans[t][p+1][d].hdr.core_id,
+                    `NOC_GRP(g).floo_tcdm_resp_in_trans[t][p+1][d].hdr.meta_id);
+                if (so >= 2)  // mesh output handshake
+                  $fwrite(f_rresp[g], "%0d P %0d 1 %0d %0d %0d %0d %0d %0d %0d %0d\n", rid, d, cycle_q,
+                    `NOC_GRP(g).floo_tcdm_resp_out_trans[t][p+1][d].hdr.dst_id.x,
+                    `NOC_GRP(g).floo_tcdm_resp_out_trans[t][p+1][d].hdr.dst_id.y,
+                    `NOC_GRP(g).floo_tcdm_resp_out_trans[t][p+1][d].hdr.src_id.x,
+                    `NOC_GRP(g).floo_tcdm_resp_out_trans[t][p+1][d].hdr.src_id.y,
+                    `NOC_GRP(g).floo_tcdm_resp_out_trans[t][p+1][d].hdr.tile_id,
+                    `NOC_GRP(g).floo_tcdm_resp_out_trans[t][p+1][d].hdr.core_id,
+                    `NOC_GRP(g).floo_tcdm_resp_out_trans[t][p+1][d].hdr.meta_id);
               end
-            end
-
-            // resp
-            for (int p = 0; p < (NumRemoteRespPortsPerTile - 1); p++) begin
-              for (int dir = 0; dir < 4; dir++) begin
-                automatic string extras_str_4;
-
-                extras_str_4 = $sformatf(
-                  "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'REQ_RSP': 1, "
-                  "'TYPE': 1, 'DIR': %03d, 'in_vld_cyc_num': %03d, 'in_hsk_cyc_num': %03d, "
-                  "'out_vld_cyc_num': %03d, 'out_hsk_cyc_num': %03d, "
-                  "'in_util': %.2f, 'out_util': %.2f\n",
-                  g, t, p, dir,
-                  router_level_profile_resp_q[g][t][p].in_vld_cyc_num[dir],
-                  router_level_profile_resp_q[g][t][p].in_hsk_cyc_num[dir],
-                  router_level_profile_resp_q[g][t][p].out_vld_cyc_num[dir],
-                  router_level_profile_resp_q[g][t][p].out_hsk_cyc_num[dir],
-                  (router_level_profile_resp_q[g][t][p].in_vld_cyc_num[dir] > 0) ?
-                    (router_level_profile_resp_q[g][t][p].in_hsk_cyc_num[dir] * 1.0) /
-                    (router_level_profile_resp_q[g][t][p].in_vld_cyc_num[dir] * 1.0) :
-                    0,
-                  (router_level_profile_resp_q[g][t][p].out_vld_cyc_num[dir] > 0) ?
-                    (router_level_profile_resp_q[g][t][p].out_hsk_cyc_num[dir] * 1.0) /
-                    (router_level_profile_resp_q[g][t][p].out_vld_cyc_num[dir] * 1.0) :
-                    0
-                );
-
-                $fwrite(f_4, extras_str_4);
-              end
-            end
-          end
-        end
-        $fclose(f_4);
-
-        // router local port
-        for (int g = 0; g < NumGroups; g++) begin
-          for (int t = 0; t < NumTilesPerGroup; t++) begin
-            for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-              if (p < NumNarrowRemoteReqPortsPerTile) begin
-                // narrow req
-                automatic string extras_str_5;
-                extras_str_5 = $sformatf(
-                  "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'REQ_RSP': 0, 'TYPE': 0, "
-                  "'req_read_in_num': %03d, 'req_write_in_num': %03d\n",
-                  g, t, p,
-                  router_local_req_port_profile_q[g][t][p].read_req_num,
-                  router_local_req_port_profile_q[g][t][p].write_req_num
-                );
-                $fwrite(f_5, extras_str_5);
-              end else begin
-                // wide req
-                automatic string extras_str_5;
-                extras_str_5 = $sformatf(
-                  "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'REQ_RSP': 0, 'TYPE': 1, "
-                  "'req_read_in_num': %03d, 'req_write_in_num': %03d\n",
-                  g, t, p,
-                  router_local_req_port_profile_q[g][t][p].read_req_num,
-                  router_local_req_port_profile_q[g][t][p].write_req_num
-                );
-                $fwrite(f_5, extras_str_5);
-              end
-            end
-
-            // resp
-            for (int p = 0; p < (NumRemoteRespPortsPerTile - 1); p++) begin
-              automatic string extras_str_5;
-              extras_str_5 = $sformatf(
-                "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'REQ_RSP': 1, "
-                "'TYPE': 1, 'resp_in_num': %03d\n",
-                g, t, p,
-                router_local_resp_port_profile_q[g][t][p].req_num
-              );
-              $fwrite(f_5, extras_str_5);
-            end
-          end
-        end
-
-        $fclose(f_5);
-      end
-    end
-  end
-
-  final begin
-    $sformat(fn_final_2, "%s/tile_level_profile_q.log", log_path);
-    f_final_2 = $fopen(fn_final_2, "w");
-    $display("[Tracer] Final Logging Banks to %s", fn_final_2);
-
-    $sformat(fn_final_3, "%s/group_level_profile_q.log", log_path);
-    f_final_3 = $fopen(fn_final_3, "w");
-    $display("[Tracer] Final Logging Banks to %s", fn_final_3);
-
-    $sformat(fn_final_4, "%s/router_level_profile_q.log", log_path);
-    f_final_4 = $fopen(fn_final_4, "w");
-    $display("[Tracer] Final Logging Banks to %s", fn_final_4);
-
-    $timeformat(-9, 0, "", 10);
-    $sformat(dump_time, "dump time %t, cycle %8d #;\n", $time, cycle_q);
-    $fwrite(f_final_2, dump_time);
-    $fwrite(f_final_3, dump_time);
-    $fwrite(f_final_4, dump_time);
-
-    // tile level
-    for (int g = 0; g < NumGroups; g++) begin
-      for (int t_i = 0; t_i < NumTilesPerGroup; t_i++) begin
-        for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-          automatic string extras_str_final_2;
-
-          extras_str_final_2 = $sformatf(
-            "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, "
-            "'req_vld_cyc_num': %03d, 'req_hsk_cyc_num': %03d, 'util': %.2f\n",
-            g, t_i, p,
-            tile_level_profile_q[g][t_i].req_vld_cyc_num[p],
-            tile_level_profile_q[g][t_i].req_hsk_cyc_num[p],
-            (tile_level_profile_q[g][t_i].req_vld_cyc_num[p] == 0) ?
-              0.0 :
-              (tile_level_profile_q[g][t_i].req_hsk_cyc_num[p] * 1.0) /
-              (tile_level_profile_q[g][t_i].req_vld_cyc_num[p] * 1.0)
-          );
-
-          $fwrite(f_final_2, extras_str_final_2);
-        end
-      end
-    end
-    $fclose(f_final_2);
-
-    // group level
-    for (int g = 0; g < NumGroups; g++) begin
-      int unsigned req_vld_cyc_num_sum;
-      int unsigned req_hsk_cyc_num_sum;
-      automatic string extras_str_final_3;
-
-      req_vld_cyc_num_sum = 0;
-      req_hsk_cyc_num_sum = 0;
-
-      for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-        req_vld_cyc_num_sum += group_level_profile_q[g].req_vld_cyc_num[p];
-        req_hsk_cyc_num_sum += group_level_profile_q[g].req_hsk_cyc_num[p];
-      end
-
-      extras_str_final_3 = $sformatf(
-        "{'GROUP': %03d, 'req_vld_cyc_num': %03d, 'req_hsk_cyc_num': %03d, "
-        "'req_vld_cyc_more_than_one_hit_same_bank_num': %03d, 'util': %.2f\n",
-        g,
-        req_vld_cyc_num_sum,
-        req_hsk_cyc_num_sum,
-        group_level_profile_q[g].req_vld_cyc_more_than_one_hit_same_bank_num,
-        ((req_vld_cyc_num_sum - group_level_profile_q[g].req_vld_cyc_more_than_one_hit_same_bank_num) == 0) ?
-          0.0 :
-          (req_hsk_cyc_num_sum * 1.0) /
-          ((req_vld_cyc_num_sum - group_level_profile_q[g].req_vld_cyc_more_than_one_hit_same_bank_num) * 1.0)
-      );
-
-      $fwrite(f_final_3, extras_str_final_3);
-    end
-    $fclose(f_final_3);
-
-    // router level
-    for (int g = 0; g < NumGroups; g++) begin
-      for (int t = 0; t < NumTilesPerGroup; t++) begin
-        for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin
-          if (p < NumNarrowRemoteReqPortsPerTile) begin
-            // narrow req
-            for (int dir = 0; dir < 4; dir++) begin
-              automatic string extras_str_final_4;
-              extras_str_final_4 = $sformatf(
-                "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'REQ_RSP': 0, 'TYPE': 0, "
-                "'DIR': %03d, 'in_vld_cyc_num': %03d, 'in_hsk_cyc_num': %03d, "
-                "'out_vld_cyc_num': %03d, 'out_hsk_cyc_num': %03d, "
-                "'in_util': %.2f, 'out_util': %.2f\n",
-                g, t, p, dir,
-                router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir],
-                router_level_profile_req_q[g][t][p].in_hsk_cyc_num[dir],
-                router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir],
-                router_level_profile_req_q[g][t][p].out_hsk_cyc_num[dir],
-                (router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir] > 0) ?
-                  (router_level_profile_req_q[g][t][p].in_hsk_cyc_num[dir] * 1.0) /
-                  (router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir] * 1.0) : 0,
-                (router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir] > 0) ?
-                  (router_level_profile_req_q[g][t][p].out_hsk_cyc_num[dir] * 1.0) /
-                  (router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir] * 1.0) : 0
-              );
-              $fwrite(f_final_4, extras_str_final_4);
-            end
-          end else begin
-            // wide req
-            for (int dir = 0; dir < 4; dir++) begin
-              automatic string extras_str_final_4;
-              extras_str_final_4 = $sformatf(
-                "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'REQ_RSP': 0, 'TYPE': 1, "
-                "'DIR': %03d, 'in_vld_cyc_num': %03d, 'in_hsk_cyc_num': %03d, "
-                "'out_vld_cyc_num': %03d, 'out_hsk_cyc_num': %03d, "
-                "'in_util': %.2f, 'out_util': %.2f\n",
-                g, t, p, dir,
-                router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir],
-                router_level_profile_req_q[g][t][p].in_hsk_cyc_num[dir],
-                router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir],
-                router_level_profile_req_q[g][t][p].out_hsk_cyc_num[dir],
-                (router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir] > 0) ?
-                  (router_level_profile_req_q[g][t][p].in_hsk_cyc_num[dir] * 1.0) /
-                  (router_level_profile_req_q[g][t][p].in_vld_cyc_num[dir] * 1.0) : 0,
-                (router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir] > 0) ?
-                  (router_level_profile_req_q[g][t][p].out_hsk_cyc_num[dir] * 1.0) /
-                  (router_level_profile_req_q[g][t][p].out_vld_cyc_num[dir] * 1.0) : 0
-              );
-              $fwrite(f_final_4, extras_str_final_4);
-            end
-          end
-        end
-
-        // resp
-        for (int p = 0; p < NumRemoteRespPortsPerTile; p++) begin
-          for (int dir = 0; dir < 4; dir++) begin
-            automatic string extras_str_final_4;
-            extras_str_final_4 = $sformatf(
-              "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'REQ_RSP': 1, 'TYPE': 1, "
-              "'DIR': %03d, 'in_vld_cyc_num': %03d, 'in_hsk_cyc_num': %03d, "
-              "'out_vld_cyc_num': %03d, 'out_hsk_cyc_num': %03d, "
-              "'in_util': %.2f, 'out_util': %.2f\n",
-              g, t, p, dir,
-              router_level_profile_resp_q[g][t][p].in_vld_cyc_num[dir],
-              router_level_profile_resp_q[g][t][p].in_hsk_cyc_num[dir],
-              router_level_profile_resp_q[g][t][p].out_vld_cyc_num[dir],
-              router_level_profile_resp_q[g][t][p].out_hsk_cyc_num[dir],
-              (router_level_profile_resp_q[g][t][p].in_vld_cyc_num[dir] > 0) ?
-                (router_level_profile_resp_q[g][t][p].in_hsk_cyc_num[dir] * 1.0) /
-                (router_level_profile_resp_q[g][t][p].in_vld_cyc_num[dir] * 1.0) : 0,
-              (router_level_profile_resp_q[g][t][p].out_vld_cyc_num[dir] > 0) ?
-                (router_level_profile_resp_q[g][t][p].out_hsk_cyc_num[dir] * 1.0) /
-                (router_level_profile_resp_q[g][t][p].out_vld_cyc_num[dir] * 1.0) : 0
-            );
-            $fwrite(f_final_4, extras_str_final_4);
-          end
-        end
-      end
-    end
-    $fclose(f_final_4);
-  end
-
-  router_input_profile_t req_router_input_profile_q[NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0];
-  floo_rdwr_req_t floo_req_input_queue[NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0][$];
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_req_input_fifo_ready_o;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_req_input_fifo_valid_i;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_req_input_fifo_ready_i;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_req_input_fifo_valid_o;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_req_output_fifo_ready_o;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_req_output_fifo_valid_i;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_req_output_fifo_ready_i;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteReqPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_req_output_fifo_valid_o;
-
-  generate
-    for (genvar g = 0; g < NumGroups; g++) begin : gen_req_router_input_queue_per_group
-      for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_req_router_input_queue_per_tile
-        for (genvar r = 0; r < (NumRemoteReqPortsPerTile - 1); r++) begin : gen_req_router_input_queue_per_remote_port
-          for (genvar router_p = 0; router_p < 5; router_p++) begin : gen_req_router_input_queue_per_dir
-            if (r < NumNarrowRemoteReqPortsPerTile) begin
-              assign floo_req_input_fifo_ready_o[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_narrow_req_router_j[r]
-                  .i_floo_narrow_req_router.ready_o[router_p];
-
-              assign floo_req_input_fifo_valid_i[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_narrow_req_router_j[r]
-                  .i_floo_narrow_req_router.valid_i[router_p];
-
-              assign floo_req_input_fifo_ready_i[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_narrow_req_router_j[r]
-                  .i_floo_narrow_req_router.in_ready[router_p];
-
-              assign floo_req_input_fifo_valid_o[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_narrow_req_router_j[r]
-                  .i_floo_narrow_req_router.in_valid[router_p];
-
-              assign floo_req_output_fifo_ready_o[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_narrow_req_router_j[r]
-                  .i_floo_narrow_req_router.out_ready[router_p];
-
-              assign floo_req_output_fifo_valid_i[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_narrow_req_router_j[r]
-                  .i_floo_narrow_req_router.out_valid[router_p];
-
-              assign floo_req_output_fifo_ready_i[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_narrow_req_router_j[r]
-                  .i_floo_narrow_req_router.out_buffered_ready[router_p];
-
-              assign floo_req_output_fifo_valid_o[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_narrow_req_router_j[r]
-                  .i_floo_narrow_req_router.out_buffered_valid[router_p];
-
-              for (genvar v = 0; v < NumVirtualChannel; v++) begin : gen_req_router_input_queue_per_vc
-                always_ff @(posedge clk) begin
-                  if (rst_n) begin
-                    if (floo_req_input_fifo_valid_i[g][t][r][router_p][v] &
-                        floo_req_input_fifo_ready_o[g][t][r][router_p][v]) begin
-                      floo_req_input_queue[g][t][r][router_p][v].push_back(
-                        floo_rdwr_req_t'{
-                          hdr: dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                                 .i_group.gen_router_router_i[t].gen_router_narrow_req_router_j[r]
-                                 .i_floo_narrow_req_router.data_i[router_p].hdr,
-                          payload: '0
-                        });
-                    end
-
-                    if (floo_req_input_fifo_valid_o[g][t][r][router_p][v] &
-                        floo_req_input_fifo_ready_i[g][t][r][router_p][v]) begin
-                      floo_req_input_queue[g][t][r][router_p][v].delete(0);
-                    end
-                  end
+              begin : rsp_local
+                automatic logic [1:0] sli = `NOC_GRP(g).floo_tcdm_resp_to_router_vc_valid[t][p+1]
+                  ? (`NOC_GRP(g).floo_tcdm_resp_to_router_vc_ready[t][p+1] ? 2'd2 : 2'd1) : 2'd0;
+                automatic logic [1:0] slo = `NOC_GRP(g).floo_tcdm_resp_from_router_vc_valid[t][p+1]
+                  ? (`NOC_GRP(g).floo_tcdm_resp_from_router_vc_ready[t][p+1] ? 2'd2 : 2'd1) : 2'd0;
+                if (sli != rsp_st[g][t][p][4][0]) begin
+                  $fwrite(f_rresp[g], "%0d S 4 0 %0d %0d %0d\n", rid, rsp_start[g][t][p][4][0], cycle_q, rsp_st[g][t][p][4][0]);
+                  rsp_st[g][t][p][4][0] <= sli; rsp_start[g][t][p][4][0] <= cycle_q;
                 end
-              end
-            end else begin
-              assign floo_req_input_fifo_ready_o[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_wide_req_router_j[r - NumNarrowRemoteReqPortsPerTile]
-                  .i_floo_wide_req_router.ready_o[router_p];
-
-              assign floo_req_input_fifo_valid_i[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_wide_req_router_j[r - NumNarrowRemoteReqPortsPerTile]
-                  .i_floo_wide_req_router.valid_i[router_p];
-
-              assign floo_req_input_fifo_ready_i[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_wide_req_router_j[r - NumNarrowRemoteReqPortsPerTile]
-                  .i_floo_wide_req_router.in_ready[router_p];
-
-              assign floo_req_input_fifo_valid_o[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_wide_req_router_j[r - NumNarrowRemoteReqPortsPerTile]
-                  .i_floo_wide_req_router.in_valid[router_p];
-
-              assign floo_req_output_fifo_ready_o[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_wide_req_router_j[r - NumNarrowRemoteReqPortsPerTile]
-                  .i_floo_wide_req_router.out_ready[router_p];
-
-              assign floo_req_output_fifo_valid_i[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_wide_req_router_j[r - NumNarrowRemoteReqPortsPerTile]
-                  .i_floo_wide_req_router.out_valid[router_p];
-
-              assign floo_req_output_fifo_ready_i[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_wide_req_router_j[r - NumNarrowRemoteReqPortsPerTile]
-                  .i_floo_wide_req_router.out_buffered_ready[router_p];
-
-              assign floo_req_output_fifo_valid_o[g][t][r][router_p] =
-                dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                  .i_group.gen_router_router_i[t].gen_router_wide_req_router_j[r - NumNarrowRemoteReqPortsPerTile]
-                  .i_floo_wide_req_router.out_buffered_valid[router_p];
-
-              for (genvar v = 0; v < NumVirtualChannel; v++) begin : gen_req_router_input_queue_per_vc
-                always_ff @(posedge clk) begin
-                  if (rst_n) begin
-                    if (floo_req_input_fifo_valid_i[g][t][r][router_p][v] &
-                        floo_req_input_fifo_ready_o[g][t][r][router_p][v]) begin
-                      floo_req_input_queue[g][t][r][router_p][v].push_back(
-                        dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                          .i_group.gen_router_router_i[t].gen_router_wide_req_router_j[r - NumNarrowRemoteReqPortsPerTile]
-                          .i_floo_wide_req_router.data_i[router_p]);
-                    end
-
-                    if (floo_req_input_fifo_valid_o[g][t][r][router_p][v] &
-                        floo_req_input_fifo_ready_i[g][t][r][router_p][v]) begin
-                      floo_req_input_queue[g][t][r][router_p][v].delete(0);
-                    end
-                  end
+                if (slo != rsp_st[g][t][p][4][1]) begin
+                  $fwrite(f_rresp[g], "%0d S 4 1 %0d %0d %0d\n", rid, rsp_start[g][t][p][4][1], cycle_q, rsp_st[g][t][p][4][1]);
+                  rsp_st[g][t][p][4][1] <= slo; rsp_start[g][t][p][4][1] <= cycle_q;
                 end
+                if (sli >= 2)  // local input (injection from tile = slave_resp) handshake
+                  $fwrite(f_rresp[g], "%0d P 4 0 %0d %0d %0d %0d %0d %0d %0d %0d\n", rid, cycle_q,
+                    `NOC_GRP(g).floo_tcdm_resp_to_router[t][p+1].hdr.dst_id.x,
+                    `NOC_GRP(g).floo_tcdm_resp_to_router[t][p+1].hdr.dst_id.y,
+                    `NOC_GRP(g).floo_tcdm_resp_to_router[t][p+1].hdr.src_id.x,
+                    `NOC_GRP(g).floo_tcdm_resp_to_router[t][p+1].hdr.src_id.y,
+                    `NOC_GRP(g).floo_tcdm_resp_to_router[t][p+1].hdr.tile_id,
+                    `NOC_GRP(g).floo_tcdm_resp_to_router[t][p+1].hdr.core_id,
+                    `NOC_GRP(g).floo_tcdm_resp_to_router[t][p+1].hdr.meta_id);
+                if (slo >= 2)  // local output (ejection to tile = master_resp) handshake
+                  $fwrite(f_rresp[g], "%0d P 4 1 %0d %0d %0d %0d %0d %0d %0d %0d\n", rid, cycle_q,
+                    `NOC_GRP(g).floo_tcdm_resp_from_router[t][p+1].hdr.dst_id.x,
+                    `NOC_GRP(g).floo_tcdm_resp_from_router[t][p+1].hdr.dst_id.y,
+                    `NOC_GRP(g).floo_tcdm_resp_from_router[t][p+1].hdr.src_id.x,
+                    `NOC_GRP(g).floo_tcdm_resp_from_router[t][p+1].hdr.src_id.y,
+                    `NOC_GRP(g).floo_tcdm_resp_from_router[t][p+1].hdr.tile_id,
+                    `NOC_GRP(g).floo_tcdm_resp_from_router[t][p+1].hdr.core_id,
+                    `NOC_GRP(g).floo_tcdm_resp_from_router[t][p+1].hdr.meta_id);
               end
             end
           end
@@ -1135,389 +243,87 @@
     end
   endgenerate
 
-  function route_direction_e xy_routing (group_xy_id_t group_id, floo_rdwr_req_t floo_req);
-    automatic group_xy_id_t dest_id = group_xy_id_t'(floo_req.hdr.dst_id);
-    if (dest_id == group_id) begin
-      xy_routing = Eject;
-    end else if (dest_id.x == group_id.x) begin
-      if (dest_id.y < group_id.y) begin
-        xy_routing = South;
-      end else begin
-        xy_routing = North;
-      end
-    end else begin
-      if (dest_id.x < group_id.x) begin
-        xy_routing = West;
-      end else begin
-        xy_routing = East;
-      end
-    end
-  endfunction
-
-  function group_xy_id_t get_next_hop (group_xy_id_t group_id, route_direction_e out_dir);
-    if (out_dir == Eject) begin
-      get_next_hop = group_id;
-    end else if (out_dir == South) begin
-      get_next_hop = '{x:group_id.x, y:group_id.y-1};
-    end else if (out_dir == North) begin
-      get_next_hop = '{x:group_id.x, y:group_id.y+1};
-    end else if (out_dir == East) begin
-      get_next_hop = '{x:group_id.x+1, y:group_id.y};
-    end else if (out_dir == West) begin
-      get_next_hop = '{x:group_id.x-1, y:group_id.y};
-    end
-  endfunction
-
-  function int onehot_to_bin (logic [NumVirtualChannel-1:0] onehot);
-    for (int i = 0; i < NumVirtualChannel; i++) begin
-        if (onehot[i]) begin
-            onehot_to_bin = i;
-            break;
-        end
-    end
-  endfunction
-
+  // ------------------------------------------------------------
+  // Tile port capture -> per-tile file. req=master_req(out)/slave_req(in) split
+  // read/write by .wen + P packet lines; resp=master_resp(in)/slave_resp(out)
+  // single handshake state (no address). genvar t: gen_tiles[t].i_tile constant.
+  // ------------------------------------------------------------
   generate
-    for (genvar g = 0; g < NumGroups; g++) begin : gen_req_router_input_profile_per_group
-      for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_req_router_input_profile_per_tile
-        for (genvar r = 0; r < (NumRemoteReqPortsPerTile - 1); r++) begin : gen_req_router_input_profile_per_remote_port
-          for (genvar router_p = 0; router_p < 5; router_p++) begin : gen_req_router_input_profile_per_dir
-            always_ff @(posedge clk or negedge rst_n) begin
-              if (!rst_n) begin
-                req_router_input_profile_q[g][t][r].in_vld_cyc_num[router_p]       = '0;
-                req_router_input_profile_q[g][t][r].in_hsk_cyc_num[router_p]       = '0;
-                req_router_input_profile_q[g][t][r].hol_stall_cyc_num[router_p]    = '0;
-                req_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p]   = {'0, '0, '0, '0, '0};
-                req_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p]    = '0;
-                req_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p]    = '0;
-              end else begin
-                if ((cycle_q % 200) == 0) begin
-                  req_router_input_profile_q[g][t][r].in_vld_cyc_num[router_p]     = '0;
-                  req_router_input_profile_q[g][t][r].in_hsk_cyc_num[router_p]     = '0;
-                  req_router_input_profile_q[g][t][r].hol_stall_cyc_num[router_p]  = '0;
-                  req_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p] = {'0, '0, '0, '0, '0};
-                  req_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p]  = '0;
-                end
-
-                if (|floo_req_input_fifo_valid_i[g][t][r][router_p]) begin
-                  req_router_input_profile_q[g][t][r].in_vld_cyc_num[router_p] += 1;
-
-                  if (|(floo_req_input_fifo_ready_o[g][t][r][router_p] &
-                         floo_req_input_fifo_valid_i[g][t][r][router_p])) begin
-                    req_router_input_profile_q[g][t][r].in_hsk_cyc_num[router_p] += 1;
-
-                    if (req_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p] > 0) begin
-                      if (req_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p] >
-                          req_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p]) begin
-                        req_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p] =
-                            req_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p];
-                      end
-                      req_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p] = 0;
-                    end
-                  end else begin
-                    automatic int vc_idx = onehot_to_bin(floo_req_input_fifo_valid_i[g][t][r][router_p]);
-                    assert(|floo_req_input_fifo_valid_o[g][t][r][router_p]);
-
-                    req_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p] += 1;
-
-                    `ifdef XY_ROUTING
-                      if (~floo_req_input_fifo_ready_i[g][t][r][router_p][vc_idx]) begin
-                        automatic route_direction_e in_dir  = route_direction_e'(router_p);
-                        automatic route_direction_e out_dir = xy_routing(g, floo_req_input_queue[g][t][r][router_p][vc_idx][0]);
-                        automatic group_xy_id_t cur_hop     = g;
-                        automatic logic cont                = '1;
-
-                        req_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][out_dir] += 1;
-
-                        assert(floo_req_output_fifo_valid_i[g][t][r][out_dir][vc_idx]);
-
-                        while ('1) begin
-                          for (int i = 1; i < floo_req_input_queue[cur_hop][t][r][in_dir][vc_idx].size(); i++) begin
-                            out_dir = xy_routing(cur_hop, floo_req_input_queue[cur_hop][t][r][in_dir][vc_idx][i]);
-
-                            if (~floo_req_output_fifo_valid_i[cur_hop][t][r][out_dir][vc_idx] &
-                                 floo_req_output_fifo_ready_o[cur_hop][t][r][out_dir][vc_idx]) begin
-                              req_router_input_profile_q[g][t][r].hol_stall_cyc_num[router_p] += 1;
-                              cont = '0;
-                              break;
-                            end
-                          end
-
-                          if (~cont) break;
-
-                          out_dir = xy_routing(cur_hop, floo_req_input_queue[cur_hop][t][r][in_dir][vc_idx][0]);
-                          assert(floo_req_output_fifo_valid_i[cur_hop][t][r][out_dir][vc_idx]);
-
-                          if (floo_req_output_fifo_ready_o[cur_hop][t][r][out_dir][vc_idx] |
-                              floo_req_output_fifo_ready_i[cur_hop][t][r][out_dir][vc_idx]) begin
-                            break;
-                          end
-
-                          if (out_dir == Eject) break;
-
-                          cur_hop = get_next_hop(cur_hop, out_dir);
-
-                          if (out_dir == North) begin
-                            in_dir = South;
-                          end else if (out_dir == South) begin
-                            in_dir = North;
-                          end else if (out_dir == East) begin
-                            in_dir = West;
-                          end else if (out_dir == West) begin
-                            in_dir = East;
-                          end
-
-                          if (floo_req_input_fifo_ready_i[cur_hop][t][r][in_dir][vc_idx]) begin
-                            break;
-                          end
-                        end
-                      end
-                    `endif
-                  end
-                end
+    for (genvar g = 0; g < NumGroups; g++) begin : gen_tstate_g
+      for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_tstate_t
+        always_ff @(posedge clk or negedge rst_n) begin
+          if (!rst_n) begin
+            ts_mreq_st[g][t] <= '{default: '0}; ts_mreq_s[g][t] <= '{default: '0};
+            ts_sreq_st[g][t] <= '{default: '0}; ts_sreq_s[g][t] <= '{default: '0};
+            ts_mrsp_st[g][t] <= '{default: '0}; ts_mrsp_s[g][t] <= '{default: '0};
+            ts_srsp_st[g][t] <= '{default: '0}; ts_srsp_s[g][t] <= '{default: '0};
+          end else begin
+            for (int p = 0; p < NumRemoteReqPortsPerTile; p++) begin
+              automatic logic [1:0] smo = `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_req_valid_o[p]
+                ? (`NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_req_ready_i[p]
+                   ? (`NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_req_o[p].wen ? 2'd3 : 2'd2) : 2'd1) : 2'd0;
+              automatic logic [1:0] ssi = `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_req_valid_i[p]
+                ? (`NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_req_ready_o[p]
+                   ? (`NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_req_i[p].wen ? 2'd3 : 2'd2) : 2'd1) : 2'd0;
+              if (smo != ts_mreq_st[g][t][p]) begin
+                $fwrite(f_tile[g][t], "S 0 1 %0d %0d %0d %0d\n", p, ts_mreq_s[g][t][p], cycle_q, ts_mreq_st[g][t][p]);
+                ts_mreq_st[g][t][p] <= smo; ts_mreq_s[g][t][p] <= cycle_q;
               end
-            end
-          end
-        end
-      end
-    end
-  endgenerate
-
-  always_ff @(negedge clk) begin : log_req_router_input_profile
-    if (rst_n) begin
-      for (int g = 0; g < NumGroups; g++) begin
-        for (int t = 0; t < NumTilesPerGroup; t++) begin
-          for (int r = 0; r < (NumRemoteReqPortsPerTile - 1); r++) begin
-            for (int router_p = 0; router_p < 5; router_p++) begin
-              if ((cycle_q % 200) == 199) begin
-                automatic string log_str;
-
-                log_str = $sformatf(
-                  "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'DIR': %03d, "
-                  "'start_cycle': %03d, 'end_cycle': %03d, "
-                  "'in_vld_cyc_num': %03d, 'in_hsk_cyc_num': %03d, "
-                  "'hol_stall_cyc_num': %03d, 'max_stall_cyc_num': %03d, "
-                  "'out_dir0_cong_cyc_num': %03d, 'out_dir1_cong_cyc_num': %03d, "
-                  "'out_dir2_cong_cyc_num': %03d, 'out_dir3_cong_cyc_num': %03d, "
-                  "'out_dir4_cong_cyc_num': %03d}\n",
-                  g, t, r, router_p, cycle_q - 199, cycle_q,
-                  req_router_input_profile_q[g][t][r].in_vld_cyc_num[router_p],
-                  req_router_input_profile_q[g][t][r].in_hsk_cyc_num[router_p],
-                  req_router_input_profile_q[g][t][r].hol_stall_cyc_num[router_p],
-                  req_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p],
-                  req_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][0],
-                  req_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][1],
-                  req_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][2],
-                  req_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][3],
-                  req_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][4]
-                );
-
-                $fwrite(req_floo_input_log_fd, log_str);
+              if (ssi != ts_sreq_st[g][t][p]) begin
+                $fwrite(f_tile[g][t], "S 0 0 %0d %0d %0d %0d\n", p, ts_sreq_s[g][t][p], cycle_q, ts_sreq_st[g][t][p]);
+                ts_sreq_st[g][t][p] <= ssi; ts_sreq_s[g][t][p] <= cycle_q;
               end
+              // P: io port cycle wen tgt_addr src_group dst_group req_tile req_core meta_id.
+              //   src/dst groups are LINEAR ids (exporter renders as mesh (x,y));
+              //   requester group == src group, so not emitted separately.
+              if (smo >= 2)  // master_req out (this tile issues a request)
+                $fwrite(f_tile[g][t], "P 1 %0d %0d %0d %0h %0d %0d %0d %0d %0d\n", p, cycle_q,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_req_o[p].wen,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_req_o[p].tgt_addr,
+                  g,                                                                                  // src group
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_req_o[p].tgt_group_id, // dst group
+                  t,                                                                                  // requester tile
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_req_o[p].wdata.core_id, // requester core
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_req_o[p].wdata.meta_id);// meta_id
+              if (ssi >= 2)  // slave_req in (a request arrives at this tile's SPM)
+                $fwrite(f_tile[g][t], "P 0 %0d %0d %0d %0h %0d %0d %0d %0d %0d\n", p, cycle_q,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_req_i[p].wen,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_req_i[p].tgt_addr,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_req_i[p].src_group_id,   // src group
+                  g,                                                                                  // dst group
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_req_i[p].ini_addr,       // requester tile
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_req_i[p].wdata.core_id,  // requester core
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_req_i[p].wdata.meta_id); // meta_id
             end
-          end
-        end
-      end
-    end
-  end
-
-  router_input_profile_t resp_router_input_profile_q[NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0];
-  floo_resp_t floo_resp_input_queue[NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0][$];
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_resp_input_fifo_ready_o;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_resp_input_fifo_valid_i;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_resp_input_fifo_ready_i;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_resp_input_fifo_valid_o;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_resp_output_fifo_ready_o;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_resp_output_fifo_valid_i;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_resp_output_fifo_ready_i;
-  logic [NumGroups-1:0][NumTilesPerGroup-1:0][(NumRemoteRespPortsPerTile-1)-1:0][4:0][NumVirtualChannel-1:0] floo_resp_output_fifo_valid_o;
-
-  generate
-    for (genvar g = 0; g < NumGroups; g++) begin : gen_resp_router_input_queue_per_group
-      for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_resp_router_input_queue_per_tile
-        for (genvar r = 0; r < (NumRemoteRespPortsPerTile - 1); r++) begin : gen_resp_router_input_queue_per_remote_port
-          for (genvar router_p = 0; router_p < 5; router_p++) begin : gen_resp_router_input_queue_per_dir
-            assign floo_resp_input_fifo_ready_o[g][t][r][router_p] =
-              dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                .i_group.gen_router_router_i[t].gen_router_wide_resp_router_j[r + 1]
-                .i_floo_wide_resp_router.ready_o[router_p];
-
-            assign floo_resp_input_fifo_valid_i[g][t][r][router_p] =
-              dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                .i_group.gen_router_router_i[t].gen_router_wide_resp_router_j[r + 1]
-                .i_floo_wide_resp_router.valid_i[router_p];
-
-            assign floo_resp_input_fifo_ready_i[g][t][r][router_p] =
-              dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                .i_group.gen_router_router_i[t].gen_router_wide_resp_router_j[r + 1]
-                .i_floo_wide_resp_router.in_ready[router_p];
-
-            assign floo_resp_input_fifo_valid_o[g][t][r][router_p] =
-              dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                .i_group.gen_router_router_i[t].gen_router_wide_resp_router_j[r + 1]
-                .i_floo_wide_resp_router.in_valid[router_p];
-
-            assign floo_resp_output_fifo_ready_o[g][t][r][router_p] =
-              dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                .i_group.gen_router_router_i[t].gen_router_wide_resp_router_j[r + 1]
-                .i_floo_wide_resp_router.out_ready[router_p];
-
-            assign floo_resp_output_fifo_valid_i[g][t][r][router_p] =
-              dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                .i_group.gen_router_router_i[t].gen_router_wide_resp_router_j[r + 1]
-                .i_floo_wide_resp_router.out_valid[router_p];
-
-            assign floo_resp_output_fifo_ready_i[g][t][r][router_p] =
-              dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                .i_group.gen_router_router_i[t].gen_router_wide_resp_router_j[r + 1]
-                .i_floo_wide_resp_router.out_buffered_ready[router_p];
-
-            assign floo_resp_output_fifo_valid_o[g][t][r][router_p] =
-              dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                .i_group.gen_router_router_i[t].gen_router_wide_resp_router_j[r + 1]
-                .i_floo_wide_resp_router.out_buffered_valid[router_p];
-
-            for (genvar v = 0; v < NumVirtualChannel; v++) begin : gen_resp_router_input_queue_per_vc
-              always_ff @(posedge clk) begin
-                if (rst_n) begin
-                  if (floo_resp_input_fifo_valid_i[g][t][r][router_p][v] &
-                      floo_resp_input_fifo_ready_o[g][t][r][router_p][v]) begin
-                    floo_resp_input_queue[g][t][r][router_p][v].push_back(
-                      dut.i_mempool_cluster.gen_groups_x[g / NumY].gen_groups_y[g % NumY]
-                        .i_group.gen_router_router_i[t].gen_router_wide_resp_router_j[r + 1]
-                        .i_floo_wide_resp_router.data_i[router_p]);
-                  end
-
-                  if (floo_resp_input_fifo_valid_o[g][t][r][router_p][v] &
-                      floo_resp_input_fifo_ready_i[g][t][r][router_p][v]) begin
-                    floo_resp_input_queue[g][t][r][router_p][v].delete(0);
-                  end
-                end
+            for (int p = 0; p < NumRemoteRespPortsPerTile; p++) begin
+              automatic logic [1:0] smi = `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_resp_valid_i[p]
+                ? (`NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_resp_ready_o[p] ? 2'd2 : 2'd1) : 2'd0;
+              automatic logic [1:0] sso = `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_resp_valid_o[p]
+                ? (`NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_resp_ready_i[p] ? 2'd2 : 2'd1) : 2'd0;
+              // Tile RESP packets use Q lines (kept apart from P req lines):
+              //   Q <io> <port> <cycle> <srcvalid> <src_grp> <dst_grp> <req_tile> <req_core> <meta_id>
+              //   master_resp(in,io0): responder not on tcdm boundary -> srcvalid=0, dst=this group.
+              //   slave_resp(out,io1): src=this group, dst=src_group_id (requester it returns to).
+              if (smi != ts_mrsp_st[g][t][p]) begin
+                $fwrite(f_tile[g][t], "S 1 0 %0d %0d %0d %0d\n", p, ts_mrsp_s[g][t][p], cycle_q, ts_mrsp_st[g][t][p]);
+                ts_mrsp_st[g][t][p] <= smi; ts_mrsp_s[g][t][p] <= cycle_q;
               end
-            end
-          end
-        end
-      end
-    end
-  endgenerate
-
-  function route_direction_e resp_xy_routing (group_xy_id_t group_id, floo_resp_t floo_resp);
-    automatic group_xy_id_t dest_id = group_xy_id_t'(floo_resp.hdr.dst_id);
-    if (dest_id == group_id) begin
-      resp_xy_routing = Eject;
-    end else if (dest_id.x == group_id.x) begin
-      if (dest_id.y < group_id.y) begin
-        resp_xy_routing = South;
-      end else begin
-        resp_xy_routing = North;
-      end
-    end else begin
-      if (dest_id.x < group_id.x) begin
-        resp_xy_routing = West;
-      end else begin
-        resp_xy_routing = East;
-      end
-    end
-  endfunction
-
-  generate
-    for (genvar g = 0; g < NumGroups; g++) begin : gen_resp_router_input_profile_per_group
-      for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_resp_router_input_profile_per_tile
-        for (genvar r = 0; r < (NumRemoteRespPortsPerTile - 1); r++) begin : gen_resp_router_input_profile_per_remote_port
-          for (genvar router_p = 0; router_p < 5; router_p++) begin : gen_resp_router_input_profile_per_dir
-            always_ff @(posedge clk or negedge rst_n) begin
-              if (!rst_n) begin
-                resp_router_input_profile_q[g][t][r].in_vld_cyc_num[router_p]      = '0;
-                resp_router_input_profile_q[g][t][r].in_hsk_cyc_num[router_p]      = '0;
-                resp_router_input_profile_q[g][t][r].hol_stall_cyc_num[router_p]   = '0;
-                resp_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p]  = {'0, '0, '0, '0, '0};
-                resp_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p]   = '0;
-                resp_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p]   = '0;
-              end else begin
-                if ((cycle_q % 200) == 0) begin
-                  resp_router_input_profile_q[g][t][r].in_vld_cyc_num[router_p]     = '0;
-                  resp_router_input_profile_q[g][t][r].in_hsk_cyc_num[router_p]     = '0;
-                  resp_router_input_profile_q[g][t][r].hol_stall_cyc_num[router_p]  = '0;
-                  resp_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p] = {'0, '0, '0, '0, '0};
-                  resp_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p]  = '0;
-                end
-
-                if (|floo_resp_input_fifo_valid_i[g][t][r][router_p]) begin
-                  resp_router_input_profile_q[g][t][r].in_vld_cyc_num[router_p] += 1;
-
-                  if (|(floo_resp_input_fifo_ready_o[g][t][r][router_p] &
-                         floo_resp_input_fifo_valid_i[g][t][r][router_p])) begin
-                    resp_router_input_profile_q[g][t][r].in_hsk_cyc_num[router_p] += 1;
-
-                    if (resp_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p] > 0) begin
-                      if (resp_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p] >
-                          resp_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p]) begin
-                        resp_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p] =
-                            resp_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p];
-                      end
-                      resp_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p] = 0;
-                    end
-                  end else begin
-                    automatic int vc_idx = onehot_to_bin(floo_resp_input_fifo_valid_i[g][t][r][router_p]);
-                    assert(|floo_resp_input_fifo_valid_o[g][t][r][router_p]);
-
-                    resp_router_input_profile_q[g][t][r].cur_stall_cyc_num[router_p] += 1;
-
-                    `ifdef XY_ROUTING
-                      if (~floo_resp_input_fifo_ready_i[g][t][r][router_p][vc_idx]) begin
-                        automatic route_direction_e in_dir  = route_direction_e'(router_p);
-                        automatic route_direction_e out_dir = resp_xy_routing(g, floo_resp_input_queue[g][t][r][router_p][vc_idx][0]);
-                        automatic group_xy_id_t cur_hop     = g;
-                        automatic logic cont                = '1;
-
-                        resp_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][out_dir] += 1;
-                        assert(floo_resp_output_fifo_valid_i[g][t][r][out_dir][vc_idx]);
-
-                        while ('1) begin
-                          for (int i = 1; i < floo_resp_input_queue[cur_hop][t][r][in_dir][vc_idx].size(); i++) begin
-                            out_dir = resp_xy_routing(cur_hop, floo_resp_input_queue[cur_hop][t][r][in_dir][vc_idx][i]);
-
-                            if (~floo_resp_output_fifo_valid_i[cur_hop][t][r][out_dir][vc_idx] &
-                                 floo_resp_output_fifo_ready_o[cur_hop][t][r][out_dir][vc_idx]) begin
-                              resp_router_input_profile_q[g][t][r].hol_stall_cyc_num[router_p] += 1;
-                              cont = '0;
-                              break;
-                            end
-                          end
-
-                          if (~cont) break;
-
-                          out_dir = resp_xy_routing(cur_hop, floo_resp_input_queue[cur_hop][t][r][in_dir][vc_idx][0]);
-                          assert(floo_resp_output_fifo_valid_i[cur_hop][t][r][out_dir][vc_idx]);
-
-                          if (floo_resp_output_fifo_ready_o[cur_hop][t][r][out_dir][vc_idx] |
-                              floo_resp_output_fifo_ready_i[cur_hop][t][r][out_dir][vc_idx]) begin
-                            break;
-                          end
-
-                          if (out_dir == Eject) break;
-
-                          cur_hop = get_next_hop(cur_hop, out_dir);
-
-                          if (out_dir == North) begin
-                            in_dir = South;
-                          end else if (out_dir == South) begin
-                            in_dir = North;
-                          end else if (out_dir == East) begin
-                            in_dir = West;
-                          end else if (out_dir == West) begin
-                            in_dir = East;
-                          end
-
-                          if (floo_resp_input_fifo_ready_i[cur_hop][t][r][in_dir][vc_idx]) begin
-                            break;
-                          end
-                        end
-                      end
-                    `endif
-                  end
-                end
+              if (smi >= 2)  // master_resp in: response arrives for this tile's core
+                $fwrite(f_tile[g][t], "Q 0 %0d %0d 0 %0d %0d %0d %0d %0d\n", p, cycle_q,
+                  g, g, t,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_resp_i[p].rdata.core_id,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_master_resp_i[p].rdata.meta_id);
+              if (sso != ts_srsp_st[g][t][p]) begin
+                $fwrite(f_tile[g][t], "S 1 1 %0d %0d %0d %0d\n", p, ts_srsp_s[g][t][p], cycle_q, ts_srsp_st[g][t][p]);
+                ts_srsp_st[g][t][p] <= sso; ts_srsp_s[g][t][p] <= cycle_q;
               end
+              if (sso >= 2)  // slave_resp out: this tile's SPM responds to a requester
+                $fwrite(f_tile[g][t], "Q 1 %0d %0d 1 %0d %0d %0d %0d %0d\n", p, cycle_q,
+                  g,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_resp_o[p].src_group_id,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_resp_o[p].ini_addr,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_resp_o[p].rdata.core_id,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.tcdm_slave_resp_o[p].rdata.meta_id);
             end
           end
         end
@@ -1525,222 +331,97 @@
     end
   endgenerate
 
-  always_ff @(negedge clk) begin : log_resp_router_input_profile
-    if (rst_n) begin
-      for (int g = 0; g < NumGroups; g++) begin
-        for (int t = 0; t < NumTilesPerGroup; t++) begin
-          for (int r = 0; r < (NumRemoteRespPortsPerTile - 1); r++) begin
-            for (int router_p = 0; router_p < 5; router_p++) begin
-              if ((cycle_q % 200) == 199) begin
-                automatic string log_str;
-
-                log_str = $sformatf(
-                  "{'GROUP': %03d, 'TILE': %03d, 'PORT': %03d, 'DIR': %03d, "
-                  "'start_cycle': %03d, 'end_cycle': %03d, "
-                  "'in_vld_cyc_num': %03d, 'in_hsk_cyc_num': %03d, "
-                  "'hol_stall_cyc_num': %03d, 'max_stall_cyc_num': %03d, "
-                  "'out_dir0_cong_cyc_num': %03d, 'out_dir1_cong_cyc_num': %03d, "
-                  "'out_dir2_cong_cyc_num': %03d, 'out_dir3_cong_cyc_num': %03d, "
-                  "'out_dir4_cong_cyc_num': %03d}\n",
-                  g, t, r, router_p, cycle_q - 199, cycle_q,
-                  resp_router_input_profile_q[g][t][r].in_vld_cyc_num[router_p],
-                  resp_router_input_profile_q[g][t][r].in_hsk_cyc_num[router_p],
-                  resp_router_input_profile_q[g][t][r].hol_stall_cyc_num[router_p],
-                  resp_router_input_profile_q[g][t][r].max_stall_cyc_num[router_p],
-                  resp_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][0],
-                  resp_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][1],
-                  resp_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][2],
-                  resp_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][3],
-                  resp_router_input_profile_q[g][t][r].out_congst_cyc_num[router_p][4]
-                );
-
-                $fwrite(resp_floo_input_log_fd, log_str);
-              end
-            end
-          end
-        end
-      end
-    end
-  end
-`endif // NOC_PROFILING
-
-`ifdef SPM_PROFILING
-  int    f_0,   f_1,    f_final_0,  f_final_1;
-  string fn_0,  fn_1,   fn_final_0, fn_final_1;
-  string app,   log_path;
-
-  initial begin
-    void'($value$plusargs("APP=%s", app));
-    $sformat(log_path, "../scripts/spm_profiling/run_logs/%s", app);
-  end
-
-  profile_t dbg_profile_q[NumGroups-1:0][NumTilesPerGroup-1:0][NumBanksPerTile-1:0][2**TCDMAddrMemWidth-1:0];
-
+  // ------------------------------------------------------------
+  // PE (Snitch core) data-port capture -> per-tile file (one line per core). Same
+  // format as a tile port; req = snitch_data_q* (out, read/write by qwrite, addr=qaddr),
+  // resp = snitch_data_p* (in). No bw/util derived for PE ports.
+  //   S <rr> <io> <port> <start> <end> <state> ; P <io> <port> <cycle> <wen> <addr(hex)>
+  // ------------------------------------------------------------
   generate
-    for (genvar g = 0; g < NumGroups; g++) begin
-      for (genvar t = 0; t < NumTilesPerGroup; t++) begin
-        for (genvar b = 0; b < NumBanksPerTile; b++) begin
-          for(genvar i = 0; i < 2**TCDMAddrMemWidth; i++) begin
-            always_ff @(posedge clk or posedge rst_n) begin
-              if(cycle_q[7:0] == 'h80) begin
-                dbg_profile_q[g][t][b][i].initiated            = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].initiated;
-                dbg_profile_q[g][t][b][i].initial_cycle        = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].initial_cycle;
-                dbg_profile_q[g][t][b][i].last_read_cycle      = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].last_read_cycle;
-                dbg_profile_q[g][t][b][i].last_write_cycle     = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].last_write_cycle;
-                dbg_profile_q[g][t][b][i].last_access_cycle    = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].last_access_cycle;
-                dbg_profile_q[g][t][b][i].access_read_number   = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].access_read_number;
-                dbg_profile_q[g][t][b][i].access_write_number  = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].access_write_number;
-                dbg_profile_q[g][t][b][i].access_number        = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].access_number;
-                dbg_profile_q[g][t][b][i].read_cycles          = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].read_cycles;
-                dbg_profile_q[g][t][b][i].write_cycles         = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].write_cycles;
+    for (genvar g = 0; g < NumGroups; g++) begin : gen_pe_g
+      for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_pe_t
+        always_ff @(posedge clk or negedge rst_n) begin
+          if (!rst_n) begin
+            pe_req_st[g][t] <= '{default: '0}; pe_req_s[g][t] <= '{default: '0};
+            pe_rsp_st[g][t] <= '{default: '0}; pe_rsp_s[g][t] <= '{default: '0};
+          end else begin
+            for (int c = 0; c < NumCoresPerTile; c++) begin
+              automatic logic [1:0] rq = `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.snitch_data_qvalid[c]
+                ? (`NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.snitch_data_qready[c]
+                   ? (`NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.snitch_data_qwrite[c] ? 2'd3 : 2'd2) : 2'd1) : 2'd0;
+              automatic logic [1:0] rp = `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.snitch_data_pvalid[c]
+                ? (`NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.snitch_data_pready[c] ? 2'd2 : 2'd1) : 2'd0;
+              if (rq != pe_req_st[g][t][c]) begin
+                $fwrite(f_pe[g][t], "%0d S 0 1 0 %0d %0d %0d\n", c, pe_req_s[g][t][c], cycle_q, pe_req_st[g][t][c]);
+                pe_req_st[g][t][c] <= rq; pe_req_s[g][t][c] <= cycle_q;
               end
-            end
-          end
-        end
-      end
-    end
-  endgenerate
-
-  always_ff @(posedge clk or posedge rst_n) begin
-    if (rst_n) begin
-      if ((cycle_q[63:0] == 'h100)  ||
-          (cycle_q[63:0] == 'h200)  ||
-          (cycle_q[63:0] == 'h400)  ||
-          (cycle_q[63:0] == 'h800)  ||
-          (cycle_q[63:0] == 'h1000) ||
-          (cycle_q[15:0] == 'h8000)) begin
-
-        $sformat(fn_0, "%s/trace_banks_cyc_%8x.dasm",        log_path, cycle_q);
-        $sformat(fn_1, "%s/trace_banks_cyc_%8x_inited.dasm", log_path, cycle_q);
-        f_1 = $fopen(fn_1, "w");
-        $display("[Tracer] Logging Banks to %s, %s", fn_0, fn_1);
-
-        for (int g = 0; g < NumGroups; g++) begin
-          for (int t = 0; t < NumTilesPerGroup; t++) begin
-            for (int b = 0; b < NumBanksPerTile; b++) begin
-              for (int i = 0; i < 2 ** TCDMAddrMemWidth; i++) begin
-                automatic string trace_entry;
-                automatic string extras_str;
-
-                extras_str = $sformatf(
-                  "{'GROUP': %03d, 'TILE': %03d, 'BANK': %03d, 'IDX': 0x%x, "
-                  "'inited': %03d, 'ini_cyc': %03d, 'last_rd_cyc': %03d, "
-                  "'last_wr_cyc': %03d, 'last_acc_cyc': %03d, "
-                  "'acc_rd_num': %03d, 'acc_wr_num': %03d, 'acc_num': %03d, ",
-                  g, t, b, i,
-                  dbg_profile_q[g][t][b][i].initiated,
-                  dbg_profile_q[g][t][b][i].initial_cycle,
-                  dbg_profile_q[g][t][b][i].last_read_cycle,
-                  dbg_profile_q[g][t][b][i].last_write_cycle,
-                  dbg_profile_q[g][t][b][i].last_access_cycle,
-                  dbg_profile_q[g][t][b][i].access_read_number,
-                  dbg_profile_q[g][t][b][i].access_write_number,
-                  dbg_profile_q[g][t][b][i].access_number
-                );
-
-                // Append read cycles
-                extras_str = $sformatf("%s'rd_cyc': ", extras_str);
-                foreach (dbg_profile_q[g][t][b][i].read_cycles[cycle_idx]) begin
-                  extras_str = $sformatf(
-                    "%s%03d ", extras_str,
-                    dbg_profile_q[g][t][b][i].read_cycles[cycle_idx]
-                  );
-                end
-                extras_str = $sformatf("%s, ", extras_str);
-
-                // Append write cycles
-                extras_str = $sformatf("%s'wr_cyc': ", extras_str);
-                foreach (dbg_profile_q[g][t][b][i].write_cycles[cycle_idx]) begin
-                  extras_str = $sformatf(
-                    "%s%03d ", extras_str,
-                    dbg_profile_q[g][t][b][i].write_cycles[cycle_idx]
-                  );
-                end
-                extras_str = $sformatf("%s}", extras_str);
-
-                // Conditionally log only initialized banks
-                if (dbg_profile_q[g][t][b][i].initiated) begin
-                  $sformat(trace_entry, "%8d #; %s\n", cycle_q, extras_str);
-                  $fwrite(f_1, trace_entry);
-                end
+              if (rp != pe_rsp_st[g][t][c]) begin
+                $fwrite(f_pe[g][t], "%0d S 1 0 0 %0d %0d %0d\n", c, pe_rsp_s[g][t][c], cycle_q, pe_rsp_st[g][t][c]);
+                pe_rsp_st[g][t][c] <= rp; pe_rsp_s[g][t][c] <= cycle_q;
               end
+              if (rq >= 2)  // req handshake -> one core load/store accepted (qid = meta_id)
+                // mask qid to the low snitch_pkg::MetaIdWidth bits (upper bits are X) so the
+                // printed id matches the NoC's zero-extended meta_id for this request.
+                $fwrite(f_pe[g][t], "%0d P 1 0 %0d %0d %0h %0d\n", c, cycle_q,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.snitch_data_qwrite[c],
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.snitch_data_qaddr[c],
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.snitch_data_qid[c][snitch_pkg::MetaIdWidth-1:0]);
+              if (rp >= 2)  // resp handshake -> a response returns to this core (pid = meta_id)
+                $fwrite(f_pe[g][t], "%0d P 0 0 %0d %0d\n", c, cycle_q,
+                  `NOC_GRP(g).i_mempool_group.gen_tiles[t].i_tile.snitch_data_pid[c]);
             end
           end
         end
-        $fclose(f_1);
       end
     end
-  end
+  endgenerate
 
+  // ------------------------------------------------------------
+  // End-of-sim flush: write every port's still-open S run, then close every file.
+  // P lines are written as they happen, so they need no flush.
+  // ------------------------------------------------------------
   final begin
-    $sformat(fn_final_0, "%s/trace_banks_cyc_%8x_final.dasm",        log_path, cycle_q);
-    $sformat(fn_final_1, "%s/trace_banks_cyc_%8x_inited_final.dasm", log_path, cycle_q);
-    f_final_0 = $fopen(fn_final_0, "w");
-    f_final_1 = $fopen(fn_final_1, "w");
-
-    $display("[Tracer] Final Logging Banks to %s, %s", fn_final_0, fn_final_1);
-
     for (int g = 0; g < NumGroups; g++) begin
       for (int t = 0; t < NumTilesPerGroup; t++) begin
-        for (int b = 0; b < NumBanksPerTile; b++) begin
-          for (int i = 0; i < 2 ** TCDMAddrMemWidth; i++) begin
-            automatic string trace_entry_final;
-            automatic string extras_str_final;
-
-            extras_str_final = $sformatf(
-              "{'GROUP': %03d, 'TILE': %03d, 'BANK': %03d, 'IDX': 0x%x, "
-              "'inited': %03d, 'ini_cyc': %03d, 'last_rd_cyc': %03d, "
-              "'last_wr_cyc': %03d, 'last_acc_cyc': %03d, "
-              "'acc_rd_num': %03d, 'acc_wr_num': %03d, 'acc_num': %03d, ",
-              g, t, b, i,
-              dbg_profile_q[g][t][b][i].initiated,
-              dbg_profile_q[g][t][b][i].initial_cycle,
-              dbg_profile_q[g][t][b][i].last_read_cycle,
-              dbg_profile_q[g][t][b][i].last_write_cycle,
-              dbg_profile_q[g][t][b][i].last_access_cycle,
-              dbg_profile_q[g][t][b][i].access_read_number,
-              dbg_profile_q[g][t][b][i].access_write_number,
-              dbg_profile_q[g][t][b][i].access_number
-            );
-
-            // Append read cycles
-            extras_str_final = $sformatf("%s'rd_cyc': ", extras_str_final);
-            foreach (dbg_profile_q[g][t][b][i].read_cycles[cycle_idx]) begin
-              extras_str_final = $sformatf(
-                "%s%03d ", extras_str_final,
-                dbg_profile_q[g][t][b][i].read_cycles[cycle_idx]
-              );
-            end
-            extras_str_final = $sformatf("%s, ", extras_str_final);
-
-            // Append write cycles
-            extras_str_final = $sformatf("%s'wr_cyc': ", extras_str_final);
-            foreach (dbg_profile_q[g][t][b][i].write_cycles[cycle_idx]) begin
-              extras_str_final = $sformatf(
-                "%s%03d ", extras_str_final,
-                dbg_profile_q[g][t][b][i].write_cycles[cycle_idx]
-              );
-            end
-            extras_str_final = $sformatf("%s}", extras_str_final);
-
-            // Log to inited trace file if applicable
-            if (dbg_profile_q[g][t][b][i].initiated) begin
-              $sformat(trace_entry_final, "%8d #; %s\n", cycle_q, extras_str_final);
-              $fwrite(f_final_1, trace_entry_final);
-            end
-
-            // Log to full trace file
-            $sformat(trace_entry_final, "%8d #; %s\n", cycle_q, extras_str_final);
-            $fwrite(f_final_0, trace_entry_final);
+        for (int p = 0; p < NumWideRemoteReqPortsPerTile; p++) begin
+          automatic int rid = t*NumWideRemoteReqPortsPerTile + p;
+          for (int d = 0; d < 4; d++) begin
+            $fwrite(f_rreq[g], "%0d S %0d 0 %0d %0d %0d\n", rid, d, rsq_start[g][t][p][d][0], cycle_q, rsq_st[g][t][p][d][0]);
+            $fwrite(f_rreq[g], "%0d S %0d 1 %0d %0d %0d\n", rid, d, rsq_start[g][t][p][d][1], cycle_q, rsq_st[g][t][p][d][1]);
+          end
+          $fwrite(f_rreq[g], "%0d S 4 0 %0d %0d %0d\n", rid, rsq_start[g][t][p][4][0], cycle_q, rsq_st[g][t][p][4][0]);
+          $fwrite(f_rreq[g], "%0d S 4 1 %0d %0d %0d\n", rid, rsq_start[g][t][p][4][1], cycle_q, rsq_st[g][t][p][4][1]);
+        end
+        for (int p = 0; p < NumRemoteRespPortsPerTile-1; p++) begin
+          automatic int rid = t*(NumRemoteRespPortsPerTile-1) + p;
+          for (int d = 0; d < 4; d++) begin
+            $fwrite(f_rresp[g], "%0d S %0d 0 %0d %0d %0d\n", rid, d, rsp_start[g][t][p][d][0], cycle_q, rsp_st[g][t][p][d][0]);
+            $fwrite(f_rresp[g], "%0d S %0d 1 %0d %0d %0d\n", rid, d, rsp_start[g][t][p][d][1], cycle_q, rsp_st[g][t][p][d][1]);
           end
+          $fwrite(f_rresp[g], "%0d S 4 0 %0d %0d %0d\n", rid, rsp_start[g][t][p][4][0], cycle_q, rsp_st[g][t][p][4][0]);
+          $fwrite(f_rresp[g], "%0d S 4 1 %0d %0d %0d\n", rid, rsp_start[g][t][p][4][1], cycle_q, rsp_st[g][t][p][4][1]);
+        end
+        for (int p = 0; p < NumRemoteReqPortsPerTile; p++) begin
+          $fwrite(f_tile[g][t], "S 0 1 %0d %0d %0d %0d\n", p, ts_mreq_s[g][t][p], cycle_q, ts_mreq_st[g][t][p]);
+          $fwrite(f_tile[g][t], "S 0 0 %0d %0d %0d %0d\n", p, ts_sreq_s[g][t][p], cycle_q, ts_sreq_st[g][t][p]);
         end
+        for (int p = 0; p < NumRemoteRespPortsPerTile; p++) begin
+          $fwrite(f_tile[g][t], "S 1 0 %0d %0d %0d %0d\n", p, ts_mrsp_s[g][t][p], cycle_q, ts_mrsp_st[g][t][p]);
+          $fwrite(f_tile[g][t], "S 1 1 %0d %0d %0d %0d\n", p, ts_srsp_s[g][t][p], cycle_q, ts_srsp_st[g][t][p]);
+        end
+        $fclose(f_tile[g][t]);
+        for (int c = 0; c < NumCoresPerTile; c++) begin
+          $fwrite(f_pe[g][t], "%0d S 0 1 0 %0d %0d %0d\n", c, pe_req_s[g][t][c], cycle_q, pe_req_st[g][t][c]);
+          $fwrite(f_pe[g][t], "%0d S 1 0 0 %0d %0d %0d\n", c, pe_rsp_s[g][t][c], cycle_q, pe_rsp_st[g][t][c]);
+        end
+        $fclose(f_pe[g][t]);
       end
+      $fclose(f_rreq[g]);
+      $fclose(f_rresp[g]);
     end
-
-    $fclose(f_final_0);
-    $fclose(f_final_1);
   end
-`endif // SPM_PROFILING
+
+`endif // NOC_PROFILING
 
 `endif // TARGET_VERILATOR
 `endif // TARGET_SYNTHESIS
diff --git a/hardware/tb/tb_spm_profiling.svh b/hardware/tb/tb_spm_profiling.svh
new file mode 100644
index 00000000..0416bf6b
--- /dev/null
+++ b/hardware/tb/tb_spm_profiling.svh
@@ -0,0 +1,349 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+// SPM bank-activity time-series trace (enabled by SPM_PROFILING).
+//
+// One lightweight log per tile (spm_profiling/bank_g<g>_t<t>.log) covering all
+// its banks. Taps the post-arbitration bank grant + winning request payload, so
+// it shows per-bank idle/stall/read/write over time AND which core won each bank
+// cycle (explains tile slave_req-in stalls from bank contention).
+//   S <bank> <start> <end> <state>   state 0=idle 1=stall 2=read 3=write
+//   P <bank> <cycle> <wen> <tgt_addr(hex)> <loc> <wide> <port> <src_grp> <src_tile> <src_core> <meta_id>
+//       loc=1 iff winning input port is local; wide=1 = DMA. Local requests zero
+//       their src_{grp,tile,core} payload fields, so use port for local accesses;
+//       remote accesses carry the true NoC origin in src_{grp,tile,core}.
+//
+// The old per-cycle bank-conflict counters and heavy per-word profiler
+// (dbg_profile_q, mirroring mempool_tile.profile_d) are commented out at the
+// bottom -- their unbounded dynamic cycle lists balloon VCS memory. mempool_tile's
+// matching profile_d is likewise commented out (under its SPM_PROFILING gate).
+// Relies on cycle_q (declared in tb_noc_profiling.svh, included first).
+
+`ifndef TB_SPM_PROFILING_SVH_
+`define TB_SPM_PROFILING_SVH_
+
+`ifndef TARGET_SYNTHESIS
+`ifndef TARGET_VERILATOR
+`ifdef SPM_PROFILING
+
+  // Hierarchical path to group g, tile t's i_tile. Defined locally because
+  // NOC_GRP (tb_noc_profiling.svh) only exists under NOC_PROFILING, whereas this
+  // trace must work whenever SPM_PROFILING is set.
+  `define SPM_TILE(gg,tt) dut.i_mempool_cluster.gen_groups_x[(gg)/NumY].gen_groups_y[(gg)%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[tt].i_tile
+
+  string  spm_bank_log_path;
+  integer spm_bank_retval;
+  int     f_bank  [NumGroups][NumTilesPerGroup];
+  // Per-bank run state (0=idle 1=stall 2=read 3=write) and start cycle of the
+  // currently-open run.
+  logic [1:0]  bank_st [NumGroups][NumTilesPerGroup][NumBanksPerTile];
+  logic [63:0] bank_s  [NumGroups][NumTilesPerGroup][NumBanksPerTile];
+
+  initial begin
+    spm_bank_log_path = "spm_profiling";
+    spm_bank_retval   = $system({"mkdir -p ", spm_bank_log_path});
+    for (int g = 0; g < NumGroups; g++)
+      for (int t = 0; t < NumTilesPerGroup; t++)
+        f_bank[g][t] = $fopen($sformatf("%s/bank_g%0d_t%0d.log",
+                              spm_bank_log_path, g, t), "w");
+  end
+
+  // Per-bank access capture. bank_req_valid/ready[b] is the post-arbitration
+  // grant; bank_req_ini_addr[b] (winning input port) + bank_req_wide[b] identify
+  // the requester (payload src fields valid only for remote inputs).
+  generate
+    for (genvar g = 0; g < NumGroups; g++) begin : gen_spm_bank_g
+      for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_spm_bank_t
+        // local/remote boundary = NumCoresPerTile core ports on the local side.
+        localparam int unsigned NLP = NumCoresPerTile;
+        always_ff @(posedge clk or negedge rst_n) begin
+          if (!rst_n) begin
+            bank_st[g][t] <= '{default: '0}; bank_s[g][t] <= '{default: '0};
+          end else begin
+            for (int b = 0; b < NumBanksPerTile; b++) begin
+              automatic logic [1:0] rb = `SPM_TILE(g,t).bank_req_valid[b]
+                ? (`SPM_TILE(g,t).bank_req_ready[b]
+                   ? (`SPM_TILE(g,t).bank_req_payload[b].wen ? 2'd3 : 2'd2) : 2'd1) : 2'd0;
+              if (rb != bank_st[g][t][b]) begin
+                $fwrite(f_bank[g][t], "S %0d %0d %0d %0d\n", b, bank_s[g][t][b], cycle_q, bank_st[g][t][b]);
+                bank_st[g][t][b] <= rb; bank_s[g][t][b] <= cycle_q;
+              end
+              if (rb >= 2) begin
+                // Who won the bank: bank_req_ini_addr[b] = winning input-port index
+                // (< NLP = local), bank_req_wide[b]=1 = DMA. Local inputs zero their
+                // src fields, so port identifies them; remote inputs carry origin.
+                automatic int unsigned winp = `SPM_TILE(g,t).bank_req_ini_addr[b];
+                $fwrite(f_bank[g][t], "P %0d %0d %0d %0h %0d %0d %0d %0d %0d %0d %0d\n",
+                  b, cycle_q,
+                  `SPM_TILE(g,t).bank_req_payload[b].wen,
+                  `SPM_TILE(g,t).bank_req_payload[b].tgt_addr,
+                  (winp < NLP) ? 1 : 0,                              // loc: local port
+                  `SPM_TILE(g,t).bank_req_wide[b],                   // wide: DMA access
+                  winp,                                              // winning input port
+                  `SPM_TILE(g,t).bank_req_payload[b].src_group_id,   // remote origin grp
+                  `SPM_TILE(g,t).bank_req_payload[b].ini_addr,       // remote origin tile
+                  `SPM_TILE(g,t).bank_req_payload[b].wdata.core_id,  // remote origin core
+                  `SPM_TILE(g,t).bank_req_payload[b].wdata.meta_id); // meta_id
+              end
+            end
+          end
+        end
+      end
+    end
+  endgenerate
+
+  // End-of-sim flush: emit each bank's still-open run, then close every file.
+  final begin
+    for (int g = 0; g < NumGroups; g++)
+      for (int t = 0; t < NumTilesPerGroup; t++) begin
+        for (int b = 0; b < NumBanksPerTile; b++)
+          $fwrite(f_bank[g][t], "S %0d %0d %0d %0d\n", b, bank_s[g][t][b], cycle_q, bank_st[g][t][b]);
+        $fclose(f_bank[g][t]);
+      end
+  end
+
+  /* ===================== DISABLED previous profiler =====================
+   * Old per-cycle bank-conflict counters and per-word dbg_profile_q profiler.
+   * The per-word profiler mirrors mempool_tile.profile_d, whose unbounded dynamic
+   * cycle lists balloon VCS. Kept commented for reference.
+   * ======================================================================
+  string  spm_app, spm_log_path;
+  integer spm_retval;
+  int     f_0, f_1, f_final_0, f_final_1;
+  string  fn_0, fn_1, fn_final_0, fn_final_1;
+  int     f_bc;
+
+  initial begin
+    void'($value$plusargs("APP=%s", spm_app));
+    $sformat(spm_log_path, "../scripts/spm_profiling/run_logs/%s", spm_app);
+    spm_retval = $system({"mkdir -p ", spm_log_path});
+    f_bc = $fopen({spm_log_path, "/bank_conflict.log"}, "w");
+  end
+
+  // ------------------------------------------------------------
+  // Bank-conflict profiling (same-bank contention from multiple tiles)
+  // ------------------------------------------------------------
+  // Count of requests targeting the same bank from multiple tiles
+  logic [NumGroups-1:0]
+        [NumTilesPerGroup * NumBanksPerTile - 1:0]
+        [$clog2(NumTilesPerGroup * (NumRemoteReqPortsPerTile - 1)) : 0]
+        group_xbar_req_to_same_bank_count;
+  logic [NumGroups-1:0]
+        [NumTilesPerGroup * NumBanksPerTile - 1:0]
+        [$clog2(NumTilesPerGroup * (NumRemoteReqPortsPerTile - 1)) : 0]
+        group_xbar_req_to_same_bank_conflict_count;
+  logic [NumGroups-1:0]
+        [$clog2(NumTilesPerGroup * (NumRemoteReqPortsPerTile - 1)) : 0]
+        group_xbar_req_to_same_bank_conflict_count_sum;
+  logic [NumX-1:0][NumY-1:0][NumRemoteReqPortsPerTile - 2:0][NumTilesPerGroup-1:0]
+        tcdm_slave_req_valid;
+  logic [NumX-1:0][NumY-1:0][NumRemoteReqPortsPerTile - 2:0][NumTilesPerGroup-1:0]
+        [idx_width(NumTilesPerGroup) + idx_width(NumBanksPerTile) - 1 : 0]
+        tcdm_slave_req_tgt_addr;
+
+  generate
+    for (genvar x_dim = 0; x_dim < NumX; x_dim++) begin : gen_x
+      for (genvar y_dim = 0; y_dim < NumY; y_dim++) begin : gen_y
+        for (genvar p = 0; p < (NumRemoteReqPortsPerTile - 1); p++) begin : gen_port
+          for (genvar t = 0; t < NumTilesPerGroup; t++) begin : gen_tile
+            assign tcdm_slave_req_valid[x_dim][y_dim][p][t] =
+                dut.i_mempool_cluster.gen_groups_x[x_dim].gen_groups_y[y_dim]
+                  .gen_rtl_group.i_group
+                  .floo_tcdm_req_from_router_before_xbar_valid_per_port[p + 1][t];
+            assign tcdm_slave_req_tgt_addr[x_dim][y_dim][p][t] =
+                dut.i_mempool_cluster.gen_groups_x[x_dim].gen_groups_y[y_dim]
+                  .gen_rtl_group.i_group.floo_tcdm_req_from_router[t][p + 1]
+                  .hdr.tgt_addr[idx_width(NumTilesPerGroup) + idx_width(NumBanksPerTile) - 1 : 0];
+          end
+        end
+      end
+    end
+  endgenerate
+
+  always_comb begin
+    group_xbar_req_to_same_bank_count = '0;
+    for (int g = 0; g < NumGroups; g++)
+      for (int p = 0; p < (NumRemoteReqPortsPerTile - 1); p++)
+        for (int t = 0; t < NumTilesPerGroup; t++)
+          if (tcdm_slave_req_valid[g / NumY][g % NumY][p][t])
+            group_xbar_req_to_same_bank_count[g][
+              tcdm_slave_req_tgt_addr[g / NumY][g % NumY][p][t]] += 1;
+  end
+
+  always_comb begin
+    group_xbar_req_to_same_bank_conflict_count     = '0;
+    group_xbar_req_to_same_bank_conflict_count_sum = '0;
+    for (int g = 0; g < NumGroups; g++)
+      for (int b = 0; b < NumTilesPerGroup * NumBanksPerTile; b++) begin
+        if (group_xbar_req_to_same_bank_count[g][b] > 0)
+          group_xbar_req_to_same_bank_conflict_count[g][b] =
+              group_xbar_req_to_same_bank_count[g][b] - 1;  // minus the winner
+        group_xbar_req_to_same_bank_conflict_count_sum[g] +=
+            group_xbar_req_to_same_bank_conflict_count[g][b];
+      end
+  end
+
+  // Cumulative per-group bank-conflict cycles, dumped as a time series.
+  int unsigned bank_conflict_q [NumGroups];
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n)
+      for (int g = 0; g < NumGroups; g++) bank_conflict_q[g] = '0;
+    else
+      for (int g = 0; g < NumGroups; g++)
+        bank_conflict_q[g] += group_xbar_req_to_same_bank_conflict_count_sum[g];
+  end
+
+  always_ff @(posedge clk) begin
+    if (rst_n && ((cycle_q % 1024) == 0)) begin
+      $timeformat(-9, 0, "", 10);
+      $fwrite(f_bc, "dump time %t, cycle %8d #;\n", $time, cycle_q);
+      for (int g = 0; g < NumGroups; g++)
+        $fwrite(f_bc, "{'GROUP': %03d, 'bank_conflict_cyc_num': %0d}\n", g, bank_conflict_q[g]);
+    end
+  end
+
+  // ------------------------------------------------------------
+  // SPM bank-activity profiling (per-bank-word access trace)
+  // ------------------------------------------------------------
+  profile_t dbg_profile_q[NumGroups-1:0][NumTilesPerGroup-1:0][NumBanksPerTile-1:0][2**TCDMAddrMemWidth-1:0];
+
+  generate
+    for (genvar g = 0; g < NumGroups; g++) begin
+      for (genvar t = 0; t < NumTilesPerGroup; t++) begin
+        for (genvar b = 0; b < NumBanksPerTile; b++) begin
+          for(genvar i = 0; i < 2**TCDMAddrMemWidth; i++) begin
+            always_ff @(posedge clk or posedge rst_n) begin
+              if(cycle_q[7:0] == 'h80) begin
+                dbg_profile_q[g][t][b][i].initiated            = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].initiated;
+                dbg_profile_q[g][t][b][i].initial_cycle        = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].initial_cycle;
+                dbg_profile_q[g][t][b][i].last_read_cycle      = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].last_read_cycle;
+                dbg_profile_q[g][t][b][i].last_write_cycle     = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].last_write_cycle;
+                dbg_profile_q[g][t][b][i].last_access_cycle    = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].last_access_cycle;
+                dbg_profile_q[g][t][b][i].access_read_number   = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].access_read_number;
+                dbg_profile_q[g][t][b][i].access_write_number  = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].access_write_number;
+                dbg_profile_q[g][t][b][i].access_number        = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].access_number;
+                dbg_profile_q[g][t][b][i].read_cycles          = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].read_cycles;
+                dbg_profile_q[g][t][b][i].write_cycles         = dut.i_mempool_cluster.gen_groups_x[g/NumY].gen_groups_y[g%NumY].gen_rtl_group.i_group.i_mempool_group.gen_tiles[t].i_tile.profile_d[b][i].write_cycles;
+              end
+            end
+          end
+        end
+      end
+    end
+  endgenerate
+
+  always_ff @(posedge clk or posedge rst_n) begin
+    if (rst_n) begin
+      if ((cycle_q[63:0] == 'h100)  ||
+          (cycle_q[63:0] == 'h200)  ||
+          (cycle_q[63:0] == 'h400)  ||
+          (cycle_q[63:0] == 'h800)  ||
+          (cycle_q[63:0] == 'h1000) ||
+          (cycle_q[15:0] == 'h8000)) begin
+
+        $sformat(fn_0, "%s/trace_banks_cyc_%8x.dasm",        spm_log_path, cycle_q);
+        $sformat(fn_1, "%s/trace_banks_cyc_%8x_inited.dasm", spm_log_path, cycle_q);
+        f_1 = $fopen(fn_1, "w");
+        $display("[Tracer] Logging Banks to %s, %s", fn_0, fn_1);
+
+        for (int g = 0; g < NumGroups; g++) begin
+          for (int t = 0; t < NumTilesPerGroup; t++) begin
+            for (int b = 0; b < NumBanksPerTile; b++) begin
+              for (int i = 0; i < 2 ** TCDMAddrMemWidth; i++) begin
+                automatic string trace_entry;
+                automatic string extras_str;
+
+                extras_str = $sformatf(
+                  "{'GROUP': %03d, 'TILE': %03d, 'BANK': %03d, 'IDX': 0x%x, 'inited': %03d, 'ini_cyc': %03d, 'last_rd_cyc': %03d, 'last_wr_cyc': %03d, 'last_acc_cyc': %03d, 'acc_rd_num': %03d, 'acc_wr_num': %03d, 'acc_num': %03d, ",
+                  g, t, b, i,
+                  dbg_profile_q[g][t][b][i].initiated,
+                  dbg_profile_q[g][t][b][i].initial_cycle,
+                  dbg_profile_q[g][t][b][i].last_read_cycle,
+                  dbg_profile_q[g][t][b][i].last_write_cycle,
+                  dbg_profile_q[g][t][b][i].last_access_cycle,
+                  dbg_profile_q[g][t][b][i].access_read_number,
+                  dbg_profile_q[g][t][b][i].access_write_number,
+                  dbg_profile_q[g][t][b][i].access_number
+                );
+
+                extras_str = $sformatf("%s'rd_cyc': ", extras_str);
+                foreach (dbg_profile_q[g][t][b][i].read_cycles[cycle_idx])
+                  extras_str = $sformatf("%s%03d ", extras_str, dbg_profile_q[g][t][b][i].read_cycles[cycle_idx]);
+                extras_str = $sformatf("%s, ", extras_str);
+
+                extras_str = $sformatf("%s'wr_cyc': ", extras_str);
+                foreach (dbg_profile_q[g][t][b][i].write_cycles[cycle_idx])
+                  extras_str = $sformatf("%s%03d ", extras_str, dbg_profile_q[g][t][b][i].write_cycles[cycle_idx]);
+                extras_str = $sformatf("%s}", extras_str);
+
+                if (dbg_profile_q[g][t][b][i].initiated) begin
+                  $sformat(trace_entry, "%8d #; %s\n", cycle_q, extras_str);
+                  $fwrite(f_1, trace_entry);
+                end
+              end
+            end
+          end
+        end
+        $fclose(f_1);
+      end
+    end
+  end
+
+  final begin
+    $sformat(fn_final_0, "%s/trace_banks_cyc_%8x_final.dasm",        spm_log_path, cycle_q);
+    $sformat(fn_final_1, "%s/trace_banks_cyc_%8x_inited_final.dasm", spm_log_path, cycle_q);
+    f_final_0 = $fopen(fn_final_0, "w");
+    f_final_1 = $fopen(fn_final_1, "w");
+    $display("[Tracer] Final Logging Banks to %s, %s", fn_final_0, fn_final_1);
+
+    for (int g = 0; g < NumGroups; g++) begin
+      for (int t = 0; t < NumTilesPerGroup; t++) begin
+        for (int b = 0; b < NumBanksPerTile; b++) begin
+          for (int i = 0; i < 2 ** TCDMAddrMemWidth; i++) begin
+            automatic string trace_entry_final;
+            automatic string extras_str_final;
+
+            extras_str_final = $sformatf(
+              "{'GROUP': %03d, 'TILE': %03d, 'BANK': %03d, 'IDX': 0x%x, 'inited': %03d, 'ini_cyc': %03d, 'last_rd_cyc': %03d, 'last_wr_cyc': %03d, 'last_acc_cyc': %03d, 'acc_rd_num': %03d, 'acc_wr_num': %03d, 'acc_num': %03d, ",
+              g, t, b, i,
+              dbg_profile_q[g][t][b][i].initiated,
+              dbg_profile_q[g][t][b][i].initial_cycle,
+              dbg_profile_q[g][t][b][i].last_read_cycle,
+              dbg_profile_q[g][t][b][i].last_write_cycle,
+              dbg_profile_q[g][t][b][i].last_access_cycle,
+              dbg_profile_q[g][t][b][i].access_read_number,
+              dbg_profile_q[g][t][b][i].access_write_number,
+              dbg_profile_q[g][t][b][i].access_number
+            );
+
+            extras_str_final = $sformatf("%s'rd_cyc': ", extras_str_final);
+            foreach (dbg_profile_q[g][t][b][i].read_cycles[cycle_idx])
+              extras_str_final = $sformatf("%s%03d ", extras_str_final, dbg_profile_q[g][t][b][i].read_cycles[cycle_idx]);
+            extras_str_final = $sformatf("%s, ", extras_str_final);
+
+            extras_str_final = $sformatf("%s'wr_cyc': ", extras_str_final);
+            foreach (dbg_profile_q[g][t][b][i].write_cycles[cycle_idx])
+              extras_str_final = $sformatf("%s%03d ", extras_str_final, dbg_profile_q[g][t][b][i].write_cycles[cycle_idx]);
+            extras_str_final = $sformatf("%s}", extras_str_final);
+
+            if (dbg_profile_q[g][t][b][i].initiated) begin
+              $sformat(trace_entry_final, "%8d #; %s\n", cycle_q, extras_str_final);
+              $fwrite(f_final_1, trace_entry_final);
+            end
+            $sformat(trace_entry_final, "%8d #; %s\n", cycle_q, extras_str_final);
+            $fwrite(f_final_0, trace_entry_final);
+          end
+        end
+      end
+    end
+    $fclose(f_final_0);
+    $fclose(f_final_1);
+    $fclose(f_bc);
+  end
+  ===================== end DISABLED previous profiler ===================== */
+
+`endif // SPM_PROFILING
+`endif // TARGET_VERILATOR
+`endif // TARGET_SYNTHESIS
+`endif // TB_SPM_PROFILING_SVH_