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[tb] Introduced MISALIGNED_ACCESSES parameter, switched copy mode order (d0/d1)
1 parent 35fcddf commit bedb480

9 files changed

Lines changed: 72 additions & 75 deletions

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Makefile

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ TESTBENCH_DEFINES += -DSTIM_TRANSP_LEN=${STIM_TRANSP_LEN}
5757
TESTBENCH_DEFINES += -DBANDWIDTH=${BANDWIDTH}
5858
TESTBENCH_DEFINES += -DNUM_ELEM_WORD=${NUM_ELEM_WORD}
5959
TESTBENCH_DEFINES += -DELEM_WIDTH=${ELEM_WIDTH}
60+
TESTBENCH_DEFINES += -DMISALIGNED_ACCESSES=${MISALIGNED_ACCESSES}
6061

6162

6263
# .PHONY: clean-sim sim-script sim synopsys-script
@@ -125,7 +126,7 @@ test-transpose-modes:
125126
@failed_tests=""; \
126127
for mode in 1 2 4; do \
127128
echo "=== Testing TRANSP_MODE=$$mode ==="; \
128-
if $(MAKE) sim CONFIG_PRESET=transpose-test TRANSP_MODE=$$mode; then \
129+
if $(MAKE) sim CONFIG_PRESET=transpose-test DATAMOVER_MODE=1 TRANSP_MODE=$$mode; then \
129130
echo "✓ TRANSP_MODE=$$mode: PASSED"; \
130131
else \
131132
echo "✗ TRANSP_MODE=$$mode: FAILED"; \
@@ -153,7 +154,7 @@ test-transpose-grid:
153154
total_tests=$$((total_tests + 1)); \
154155
echo "=== Testing BANDWIDTH=$$bandwidth TRANSP_MODE=$$transp_mode WORD_WIDTH=$$word_width ==="; \
155156
if $(MAKE) sim CONFIG_PRESET=medium-matrix BANDWIDTH=$$bandwidth TRANSP_MODE=$$transp_mode WORD_WIDTH=$$word_width; then \
156-
echo "✓ BANDWIDTH=$$bandwidth TRANSP_MODE=$$transp_mode WORD_WIDTH=$$word_width: PASSED"; \
157+
echo "✓ BANDWIDTH=$$bandwidth DATAMOVER_MODE=1 TRANSP_MODE=$$transp_mode WORD_WIDTH=$$word_width: PASSED"; \
157158
passed_tests=$$((passed_tests + 1)); \
158159
else \
159160
echo "✗ BANDWIDTH=$$bandwidth TRANSP_MODE=$$transp_mode WORD_WIDTH=$$word_width: FAILED"; \
@@ -240,6 +241,7 @@ validate-config:
240241
--word_width $(WORD_WIDTH) \
241242
--elem_width $(ELEM_WIDTH) \
242243
--memory_size $(MEMORY_SIZE) \
244+
--misaligned_accesses $(MISALIGNED_ACCESSES) \
243245
--datamover_mode $(DATAMOVER_MODE) \
244246
--transp_mode $(TRANSP_MODE) \
245247
--cim_mode $(CIM_MODE) \
@@ -286,6 +288,7 @@ stimuli: clean-stimuli
286288
--bandwidth_bits $(BANDWIDTH) \
287289
--num_elem_word $(NUM_ELEM_WORD) \
288290
--elem_width $(ELEM_WIDTH) \
291+
--misaligned_accesses $(MISALIGNED_ACCESSES) \
289292
--datamover_mode $(DATAMOVER_MODE) \
290293
--transp_mode $(STIM_TRANSP_MODE) \
291294
--transp_len $(STIM_TRANSP_LEN) \

README.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,8 @@ PASSED!!!!
109109
## Contributors
110110
- Francesco Conti, University of Bologna (*f.conti@unibo.it*)
111111
- Arpan Suravi Prasad, ETH Zurich (*prasadar@iis.ee.ethz.ch*)
112+
- Sergio Mazzola, ETH Zurich (*smazzola@iis.ee.ethz.ch*)
113+
- Cyrill Durrer, ETH Zurich (*cdurrer@iis.ee.ethz.ch*)
112114

113115
## License
114116
This repository makes use of two licenses:

ReadMe.md

Lines changed: 0 additions & 46 deletions
This file was deleted.

config.mk

Lines changed: 19 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -13,25 +13,28 @@
1313
#######################
1414

1515
# Hardware configuration (can be overridden by presets or command line)
16-
BANDWIDTH ?= 512 # in bits, multiple of WORD_WIDTH
17-
WORD_WIDTH ?= 64 # in bits, multiple of ELEM_WIDTH
16+
BANDWIDTH ?= 64 # in bits, multiple of WORD_WIDTH
17+
WORD_WIDTH ?= 32 # in bits, multiple of ELEM_WIDTH
1818
ELEM_WIDTH ?= 8 # in bits
19-
MEMORY_SIZE ?= 131072 # in words
19+
MEMORY_SIZE ?= 512 # in words
20+
MISALIGNED_ACCESSES ?= 1
2021

21-
DATAMOVER_MODE ?= 2 # 0 = copy, 1 = transpose, 2 = CIM data layout conversion
22-
TRANSP_MODE ?= 0 # 1 = 1 elem, 2 = 2 elem, 4 = 4 elem, other values: not accepted
22+
DATAMOVER_MODE ?= 0 # 0 = copy, 1 = transpose, 2 = CIM data layout conversion
23+
TRANSP_MODE ?= 4 # 1 = 1 elem, 2 = 2 elem, 4 = 4 elem, other values: not accepted
2324
CIM_MODE ?= 0 # Data layout conversion mode: 0: row-major -> A-Layout, 1: row-major -> B-Layout
24-
CIM_INNER_DIM ?= 64 # Inner dimension of the CIM accelerator (in elements): 64 for 64x8 CIM macro
25-
CIM_OUTER_DIM ?= 64 # Outer dimension of the CIM accelerator (in elements): 8x #CIM macros
25+
CIM_INNER_DIM ?= 32 # Inner dimension of the CIM accelerator (in elements): 64 for 64x8 CIM macro
26+
CIM_OUTER_DIM ?= 32 # Outer dimension of the CIM accelerator (in elements): 8x #CIM macros
2627

2728
# Input matrix dimensions (in elements)
28-
MATRIX_SIZE_M ?= 448 # Matrix height in elements
29-
MATRIX_SIZE_N ?= 512 # Matrix width in elements
29+
MATRIX_SIZE_M ?= 8 # Matrix height in elements
30+
MATRIX_SIZE_N ?= 8 # Matrix width in elements
3031

3132
WRITE_BASE_ADDR = $(shell echo $$(($(MATRIX_SIZE_M) * $(MATRIX_SIZE_N)))) # Element-addressed
3233

3334
# Derived constants from basic parameters
34-
BANDWIDTH_ELEMS := $(shell echo $$(($(BANDWIDTH) / $(ELEM_WIDTH)))) # Number of elements per bandwidth
35+
BANDWIDTH_REDUCTION := $(shell echo $$(($(MISALIGNED_ACCESSES) * $(WORD_WIDTH)))) # in bits
36+
BANDWIDTH_ALIGNED := $(shell echo $$(($(BANDWIDTH) - $(BANDWIDTH_REDUCTION)))) # in bytes
37+
BANDWIDTH_ELEMS := $(shell echo $$(($(BANDWIDTH_ALIGNED) / $(ELEM_WIDTH)))) # Number of elements per bandwidth
3538
NUM_ELEM_WORD := $(shell echo $$(($(WORD_WIDTH) / $(ELEM_WIDTH)))) # Number of elements per word
3639

3740
# ADDR and STRIDE are in bytes, LENGTH is in number of memory accesses (4*32b)
@@ -40,10 +43,10 @@ NUM_ELEM_WORD := $(shell echo $$(($(WORD_WIDTH) / $(ELEM_WIDTH)))) # Number of
4043
ifeq "$(strip $(DATAMOVER_MODE))" "0" # Copy mode
4144
$(info Copy mode enabled)
4245
STIM_READ_BASE_ADDR ?= 0 # Element-addressed
43-
STIM_READ_D0_LENGTH ?= $(MATRIX_SIZE_M) # [Nof accesses with bandwidth BW per D0-transfer ("row")]
44-
STIM_READ_D0_STRIDE ?= $(MATRIX_SIZE_N) # [Elements]
45-
STIM_READ_D1_LENGTH ?= $(shell echo $$(($(MATRIX_SIZE_N) / $(BANDWIDTH_ELEMS)))) # [Number of full D0-transfers ("rows")]
46-
STIM_READ_D1_STRIDE ?= $(BANDWIDTH_ELEMS) # [Elements] -> manually compute "next row" stride
46+
STIM_READ_D0_LENGTH ?= $(shell echo $$(($(MATRIX_SIZE_N) / $(BANDWIDTH_ELEMS)))) # [Nof accesses with bandwidth BW per D0-transfer ("row")]
47+
STIM_READ_D0_STRIDE ?= $(BANDWIDTH_ELEMS) # [Elements]
48+
STIM_READ_D1_LENGTH ?= $(MATRIX_SIZE_M) # [Number of full D0-transfers ("rows")]
49+
STIM_READ_D1_STRIDE ?= $(MATRIX_SIZE_N) # [Elements] -> manually compute "next row" stride
4750
STIM_READ_D2_LENGTH ?= 0 # Not used for copy mode
4851
STIM_READ_D2_STRIDE ?= 0 # Not used for copy mode
4952
STIM_READ_TOT_LENGTH ?= $(shell echo $$(($(STIM_READ_D0_LENGTH) * $(STIM_READ_D1_LENGTH)))) # [Total memory accesses]
@@ -122,6 +125,8 @@ endif
122125
$(info ========================================)
123126
$(info Hardware Configuration:)
124127
$(info BANDWIDTH: $(BANDWIDTH) bits)
128+
$(info MISALIGNED_ACCESSES: $(MISALIGNED_ACCESSES))
129+
$(info BANDWIDTH_ALIGNED: $(BANDWIDTH_ALIGNED) bits)
125130
$(info WORD_WIDTH: $(WORD_WIDTH) bits)
126131
$(info ELEM_WIDTH: $(ELEM_WIDTH) bits)
127132
$(info BANDWIDTH_ELEMS: $(BANDWIDTH_ELEMS))

config_presets.mk

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ ifeq ($(CONFIG_PRESET),small-matrix)
3434
WORD_WIDTH = 32
3535
ELEM_WIDTH = 8
3636
MEMORY_SIZE = 512
37+
MISALIGNED_ACCESSES = 0
3738
DATAMOVER_MODE = 1
3839
TRANSP_MODE = 1
3940
CIM_MODE = 0
@@ -49,6 +50,7 @@ ifeq ($(CONFIG_PRESET),medium-matrix)
4950
WORD_WIDTH = 32
5051
ELEM_WIDTH = 8
5152
MEMORY_SIZE = 4096
53+
MISALIGNED_ACCESSES = 0
5254
DATAMOVER_MODE = 1
5355
TRANSP_MODE = 1
5456
CIM_MODE = 0
@@ -64,6 +66,7 @@ ifeq ($(CONFIG_PRESET),large-matrix)
6466
WORD_WIDTH = 32
6567
ELEM_WIDTH = 8
6668
MEMORY_SIZE = 131072
69+
MISALIGNED_ACCESSES = 0
6770
DATAMOVER_MODE = 1
6871
TRANSP_MODE = 1
6972
CIM_MODE = 0
@@ -79,6 +82,7 @@ ifeq ($(CONFIG_PRESET),transpose-test)
7982
WORD_WIDTH = 32
8083
ELEM_WIDTH = 8
8184
MEMORY_SIZE = 16384
85+
MISALIGNED_ACCESSES = 0
8286
DATAMOVER_MODE = 1
8387
TRANSP_MODE = 2
8488
CIM_MODE = 0
@@ -94,6 +98,7 @@ ifeq ($(CONFIG_PRESET),rect-wide)
9498
WORD_WIDTH = 16
9599
ELEM_WIDTH = 8
96100
MEMORY_SIZE = 32768
101+
MISALIGNED_ACCESSES = 0
97102
DATAMOVER_MODE = 1
98103
TRANSP_MODE = 4
99104
CIM_MODE = 0
@@ -109,6 +114,7 @@ ifeq ($(CONFIG_PRESET),rect-tall)
109114
WORD_WIDTH = 32
110115
ELEM_WIDTH = 8
111116
MEMORY_SIZE = 32768
117+
MISALIGNED_ACCESSES = 0
112118
DATAMOVER_MODE = 1
113119
TRANSP_MODE = 2
114120
CIM_MODE = 0
@@ -124,6 +130,7 @@ ifeq ($(CONFIG_PRESET),rect-narrow)
124130
WORD_WIDTH = 32
125131
ELEM_WIDTH = 8
126132
MEMORY_SIZE = 8192
133+
MISALIGNED_ACCESSES = 0
127134
DATAMOVER_MODE = 1
128135
TRANSP_MODE = 1
129136
CIM_MODE = 0
@@ -139,6 +146,7 @@ ifeq ($(CONFIG_PRESET),rect-elongated)
139146
WORD_WIDTH = 32
140147
ELEM_WIDTH = 8
141148
MEMORY_SIZE = 16384
149+
MISALIGNED_ACCESSES = 0
142150
DATAMOVER_MODE = 1
143151
TRANSP_MODE = 2
144152
CIM_MODE = 0
@@ -154,6 +162,7 @@ ifeq ($(CONFIG_PRESET),copy-small)
154162
WORD_WIDTH = 32
155163
ELEM_WIDTH = 8
156164
MEMORY_SIZE = 512
165+
MISALIGNED_ACCESSES = 0
157166
DATAMOVER_MODE = 0
158167
TRANSP_MODE = 0
159168
CIM_MODE = 0
@@ -169,6 +178,7 @@ ifeq ($(CONFIG_PRESET),copy-medium)
169178
WORD_WIDTH = 32
170179
ELEM_WIDTH = 8
171180
MEMORY_SIZE = 4096
181+
MISALIGNED_ACCESSES = 0
172182
DATAMOVER_MODE = 0
173183
TRANSP_MODE = 0
174184
CIM_MODE = 0
@@ -184,6 +194,7 @@ ifeq ($(CONFIG_PRESET),cim-small)
184194
WORD_WIDTH = 32
185195
ELEM_WIDTH = 8
186196
MEMORY_SIZE = 8192
197+
MISALIGNED_ACCESSES = 0
187198
DATAMOVER_MODE = 2
188199
TRANSP_MODE = 0
189200
CIM_MODE = 0
@@ -199,6 +210,7 @@ ifeq ($(CONFIG_PRESET),cim-medium)
199210
WORD_WIDTH = 64
200211
ELEM_WIDTH = 8
201212
MEMORY_SIZE = 16384
213+
MISALIGNED_ACCESSES = 0
202214
DATAMOVER_MODE = 2
203215
TRANSP_MODE = 0
204216
CIM_MODE = 0
@@ -214,6 +226,7 @@ ifeq ($(CONFIG_PRESET),cim-large)
214226
WORD_WIDTH = 64
215227
ELEM_WIDTH = 8
216228
MEMORY_SIZE = 65536
229+
MISALIGNED_ACCESSES = 0
217230
DATAMOVER_MODE = 2
218231
TRANSP_MODE = 0
219232
CIM_MODE = 0

verif/python/generate_stimuli_test.py

Lines changed: 30 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,13 @@
44
import math
55

66
RANDOM_STIMULI = False # If False, counting stimuli are generated in a counting fashion
7+
WORD_ALIGNED = False # If True, matrices are aligned to word boundaries by zero-padding
78

89
# ToDo(cdurrer): small matrices (N < BW) not working
910

1011
def extract_elements_from_word(word, word_width, elem_width):
1112
"""Extract elements from a word based on the specified widths."""
1213
word_int = int(word, 16) # Convert hex string to integer
13-
1414
elements = []
1515
for i in range(word_width // elem_width):
1616
# Extract each element using shift and mask
@@ -44,29 +44,42 @@ def generate_counting_hex(size, elem_width, word_width):
4444
elem_val = (i * elems_per_word + j) & ((1 << elem_width) - 1)
4545
word_val |= (elem_val << (j * elem_width))
4646
result.append(f"{word_val:0{word_width // 4}X}") # Format as hex string
47-
4847
return result
4948

5049
def pack_elements_to_word(elements, elem_width, word_width):
5150
"""Pack multiple elements into a single word."""
5251
elems_per_word = word_width // elem_width
5352
word_val = 0
54-
5553
for i, elem in enumerate(elements[:elems_per_word]): # Take only what fits in a word
5654
word_val |= (elem << (i * elem_width))
57-
5855
return f"{word_val:0{word_width // 4}X}"
5956

6057
def matrix_to_hex_words(matrix, elem_width, word_width):
6158
"""Convert a matrix of elements to a list of hex words."""
6259
elems_per_word = word_width // elem_width
6360
hex_words = []
6461
matrix_flat = sum(matrix, [])
65-
6662
for i in range(math.ceil(len(matrix_flat) / elems_per_word)):
6763
hex_word = pack_elements_to_word(matrix_flat[i*elems_per_word:i*elems_per_word+elems_per_word], elem_width, word_width)
6864
hex_words.append(hex_word)
65+
return hex_words
6966

67+
def matrix_to_hex_words_word_aligned(matrix, elem_width, word_width):
68+
"""Convert a matrix of elements to a list of hex words - aligned to word boundaries by zero-padding."""
69+
elems_per_word = word_width // elem_width
70+
hex_words = []
71+
for row in matrix:
72+
# Process each row, grouping elements into words
73+
for i in range(0, len(row), elems_per_word):
74+
elements_for_word = row[i:i + elems_per_word]
75+
76+
# Pad with zeros if the row doesn't fill a complete word
77+
while len(elements_for_word) < elems_per_word:
78+
elements_for_word.append(0)
79+
80+
# Pack elements into a word
81+
hex_word = pack_elements_to_word(elements_for_word, elem_width, word_width)
82+
hex_words.append(hex_word)
7083
return hex_words
7184

7285
def write_file(output_dir, filename, content):
@@ -114,6 +127,7 @@ def main():
114127
parser.add_argument("--bandwidth_bits", type=int, default=4, help="Number of bits per transaction")
115128
parser.add_argument("--num_elem_word", type=int, default=4, help="Number of elements in a memory bank word")
116129
parser.add_argument("--elem_width", type=int, default=8, help="Width of each element (in bits)")
130+
parser.add_argument("--misaligned_accesses", type=int, default=0, help="Enable misaligned accesses (0=disabled, 1=enabled)")
117131
parser.add_argument("--datamover_mode", type=int, default=0, help="Datamover mode (0=normal, 1=CIM)")
118132
parser.add_argument("--transp_mode", type=int, default=0, help="Transposition mode (3'b000 = none, 3'b001 = 1 elem, 3'b010 = 2 elem, 3'b100 = 4 elem)")
119133
parser.add_argument("--transp_len", type=int, default=0, help="Transposition length")
@@ -126,8 +140,9 @@ def main():
126140

127141
args = parser.parse_args()
128142

143+
BANDWIDTH_ALIGNED = args.bandwidth_bits - (args.misaligned_accesses * (args.elem_width * args.num_elem_word))
129144
MEMORY_SIZE = args.mem_size # Set global memory size
130-
BANDWIDTH_ELEMS = args.bandwidth_bits // args.elem_width
145+
BANDWIDTH_ELEMS = BANDWIDTH_ALIGNED // args.elem_width
131146
BANDWIDTH_WORDS = BANDWIDTH_ELEMS // args.num_elem_word
132147
WORD_SIZE_BITS = args.num_elem_word * args.elem_width # Set global word size in bits
133148

@@ -151,11 +166,11 @@ def main():
151166
if args.num_elem_word & (args.num_elem_word - 1) != 0 or args.num_elem_word <= 0:
152167
raise ValueError("[GM] num_elem_word must be a power of two and greater than zero.")
153168
# bandwidth width must be a multiple of word size
154-
if args.bandwidth_bits % WORD_SIZE_BITS != 0:
155-
raise ValueError("[GM] bandwidth_bits must be a multiple of the word size (num_elem_word * elem_width).")
169+
if BANDWIDTH_ALIGNED % WORD_SIZE_BITS != 0:
170+
raise ValueError("[GM] BANDWIDTH_ALIGNED must be a multiple of the word size (num_elem_word * elem_width).")
156171
# # bandwidth width must be a multiple of word size
157-
# if ((MATRIX_SIZE_N * ELEM_WIDTH) < args.bandwidth_bits):
158-
# raise ValueError("[GM] Matrix width (N) in bits must be at least as large as bandwidth_bits.")
172+
# if ((MATRIX_SIZE_N * ELEM_WIDTH) < BANDWIDTH_ALIGNED):
173+
# raise ValueError("[GM] Matrix width (N) in bits must be at least as large as BANDWIDTH_ALIGNED.")
159174
# read_tot_length must not exceed 12-bit register capacity (4096)
160175
if ((args.read_tot_length >= 4096) & (args.datamover_mode != 0)):
161176
raise ValueError("[GM] read_tot_length (MxN / BW_ELEM) must be less than 4096 in transpose and CIM modes (12-bit register limit).")
@@ -180,7 +195,6 @@ def main():
180195

181196
# Convert memory to flat vector
182197
memory_flat = convert_memory_to_vector(memory, ELEM_WIDTH, WORD_WIDTH)
183-
print(memory_flat)
184198

185199
# Extract matrix (read dimensions) from memory
186200
input_matrix = [[0 for _ in range(MATRIX_SIZE_N)] for _ in range(MATRIX_SIZE_M)]
@@ -213,7 +227,11 @@ def main():
213227
print("\n")
214228

215229
# # Convert output matrix back to words
216-
output_hex_words = matrix_to_hex_words(output_matrix, ELEM_WIDTH, WORD_WIDTH)
230+
if (WORD_ALIGNED):
231+
output_hex_words = matrix_to_hex_words_word_aligned(output_matrix, ELEM_WIDTH, WORD_WIDTH)
232+
else:
233+
output_hex_words = matrix_to_hex_words(output_matrix, ELEM_WIDTH, WORD_WIDTH)
234+
217235
print(f"\nOutput Matrix as Hex Words:")
218236
for i, word in enumerate(output_hex_words):
219237
print(f"Word {i}: {word}")

verif/python/validate_config.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,7 @@ def main():
8888
parser.add_argument("--word_width", type=int, required=True)
8989
parser.add_argument("--elem_width", type=int, required=True)
9090
parser.add_argument("--memory_size", type=int, required=True)
91+
parser.add_argument("--misaligned_accesses", type=int, required=True)
9192
parser.add_argument("--datamover_mode", type=int, required=True)
9293
parser.add_argument("--transp_mode", type=int, required=True)
9394
parser.add_argument("--cim_mode", type=int, required=True)

verif/tb/tb_datamover_top_wrap.sv

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ import tb_package::*;
138138
.ELEM_WIDTH ( ELEM_WIDTH ),
139139
.N_CORES ( N_CORES ),
140140
.N_CONTEXT ( 2 ),
141-
.MISALIGNED_ACCESSES ( 0 )
141+
.MISALIGNED_ACCESSES ( MISALIGNED_ACCESSES )
142142
) i_hwpe_top_wrap (
143143
.clk_i ( clk_i ),
144144
.rst_ni ( rst_ni ),

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