Vivado synthesis error in soc_interconnect.sv when building open-platform for ZCU102

[balditommaso]

Hello,

I am trying to deploy the open-platform on a ZCU102 by following the steps in the README, but I encounter a Vivado synthesis error related to a SystemVerilog enum assignment in soc_interconnect.sv.

ERROR: [Synth 8-9123] an enum variable may only be assigned the same enum typed variable or one of its values [/home/tom/***/pulp/.bender/git/checkouts/pulp_soc-16c884c1d0dd5bfc/rtl/pulp_soc/soc_interconnect.sv:279]
INFO: [Synth 8-10285] module 'soc_interconnect' is ignored due to previous errors [/home/tom/***/pulp/.bender/git/checkouts/pulp_soc-16c884c1d0dd5bfc/rtl/pulp_soc/soc_interconnect.sv:324]

Environment:

• Board: ZCU102

• Vivado versions tested: 2025.1 and 2022.2

• OS: Ubuntu (VM)

• Repository setup via Bender (no local modifications)

Steps to reproduce:

1. Clone and set up open-platform as described in the README

2. Select the ZCU102 target

Notes / observations:

The issue appears to be related to an assignment involving an enum type in soc_interconnect.sv

The same error occurs across multiple Vivado versions

No manual changes were made to the RTL

Could this be related to:

• a SystemVerilog enum compatibility issue with Vivado?

• a missing cast or a stricter synthesis rule in recent Vivado versions?

• a known incompatibility with ZCU102 builds?

Please let me know if additional information (logs, exact commit hashes, or a minimal reproduction) would be helpful.

Thank you for your help.