From c87f34a0aecc0029e5ebaa660f889e18f3f692da Mon Sep 17 00:00:00 2001 From: Ralf Anton Beier Date: Tue, 28 Jul 2026 20:49:57 +0200 Subject: [PATCH 1/2] =?UTF-8?q?release-watch:=20synth=20v0.51.0=20tested?= =?UTF-8?q?=20on=20real=20fused=20falcon=20v1.128=20=E2=80=94=20float=20ga?= =?UTF-8?q?te=20UNCHANGED=20(aarch64=20release,=20ARM=20path=20untouched)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit STEP-1 release-watch: synth v0.51.0 shipped. Tested against the REAL fused falcon v1.128 (sha 54020c5e) on the full DD-018 chain (meld 0.39 -> loom 1.2 -> synth --relocatable -t cortex-m7dp), controlled 0.50.0-vs-0.51.0 on identical input: BYTE-IDENTICAL 9-skip set (F32ConvertI64S x3, spill-exhaust x2, no-free-callee, arm-compile-fail x3). v0.51 is an aarch64 backend release (#851) + oracle hardening (#850) - it does not touch the ARM/cortex-m float lowering path, so the unchanged gate is the correct, expected result (no regression, no progress on offer). AFD-035 progression log updated; no upstream issue (v0.51 didn't target the gate). rivet validate PASS. Co-Authored-By: Claude Opus 4.8 --- artifacts/findings.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/artifacts/findings.yaml b/artifacts/findings.yaml index 962eaee..746082b 100644 --- a/artifacts/findings.yaml +++ b/artifacts/findings.yaml @@ -1233,6 +1233,18 @@ artifacts: run-stabilization still lowers. #345 (my minimal repro) NOT yet actioned (3x #345 remain); no new pole. Remaining 13 = 3x #345 literal-pool + 2x #503 + #518 + VFP-f32-exhaustion + VCR-RA-003 + no-free-callee + i64-spill + #331. Progression 26->16->14->13. Gate STILL OPEN (13>0). + UPDATE 2026-07-28 (synth v0.51.0, real fused falcon-v1.128 sha 54020c5e): float gate UNCHANGED - as + EXPECTED. v0.51 is an AARCH64 backend release (#851 aarch64 non-param locals + linmem load/store, "runs + real WASM modules"; #850/#853 differential-oracle hardening) - it does NOT touch the ARM/cortex-m float + lowering path that holds the falcon skips. CONTROLLED re-measure on the FULL DD-018 chain (meld v0.39 -> + loom v1.2 optimize -> synth --relocatable -t cortex-m7dp): synth v0.50.0 and v0.51.0 emit the + BYTE-IDENTICAL skip set - same 9 functions (func_29/31/42 F32ConvertI64S i64->f32 conv; func_36/78 + spill-slot-pool exhausted; func_88 no-free-callee; func_69/75/172 arm-backend compilation-failed). So + v0.51 makes zero falcon-lane progress (none was on offer - aarch64 is orthogonal to the RT1176 cortex-m + cores). NOTE the count here (9) is the loom-optimized full chain; the "13" above was pre-loom-optimize - + loom clears ~4 skippable funcs. The dominant residual blocker family = F32ConvertI64S + RA-exhaustion. + Gate STILL OPEN. No regression, no upstream issue (v0.51 did not target the gate). aarch64 maturation is + noted but not a Pixhawk target (RT1176 = M7/M4/M3, all cortex-m). tags: [release-watch, synth, arm, hard-float, gi-fpu, trunc-sat, on-target, falcon, blocking] fields: detected-by: jess release-watch chain-measure on synth v0.45.1 (meld v0.41.1, falcon-flight-v1.123); real-fused-core 26/156 skips vs the "#369 closed" claim; confirmed trunc_sat minimal repro; filed synth#782 From 0bb07fab3b1a9acaf15d878fe8606ea3e42eb2a1 Mon Sep 17 00:00:00 2001 From: Ralf Anton Beier Date: Tue, 28 Jul 2026 20:51:48 +0200 Subject: [PATCH 2/2] release-watch: add per-target-ISA skip matrix (north-star per-core build-matrix rung) synth v0.51.0 on the same fused+loom falcon v1.128, swept per target ISA: m7dp=9, m7=9, m4f(estimator)=9, m4=30, m3(F100-class)=30. Three reads: (1) F32ConvertI64S=3 on every target = target-independent irreducible float-gate core; (2) M7 + M4-estimator share the same 9-skip VFP floor (no separate estimator pole); (3) soft-float explodes RA pressure 6->27 -> independently confirms F100 runs the small gale VER-OS-HM-001 failsafe FSM, NOT a lowered full falcon (validates DD-025 partitioning + DD-026 decision 4). rivet validate PASS. Co-Authored-By: Claude Opus 4.8 --- artifacts/findings.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/artifacts/findings.yaml b/artifacts/findings.yaml index 746082b..25bb5e0 100644 --- a/artifacts/findings.yaml +++ b/artifacts/findings.yaml @@ -1245,6 +1245,16 @@ artifacts: loom clears ~4 skippable funcs. The dominant residual blocker family = F32ConvertI64S + RA-exhaustion. Gate STILL OPEN. No regression, no upstream issue (v0.51 did not target the gate). aarch64 maturation is noted but not a Pixhawk target (RT1176 = M7/M4/M3, all cortex-m). + PER-TARGET-ISA SKIP MATRIX (north-star per-core build-matrix rung, synth v0.51.0 on the same fused+loom'd + falcon-v1.128): cortex-m7dp[M7,fpv5-d16]=9, cortex-m7=9, cortex-m4f[M4-estimator,fpv4-sp]=9, cortex-m4=30, + cortex-m3[F100-class,soft-float]=30. THREE load-bearing reads: (1) F32ConvertI64S=3 on EVERY target - + target-INDEPENDENT, the irreducible float-gate core (i64->f32 conv the arm backend can't lower on any ISA); + (2) the VFP targets (M7 + M4-estimator) share the SAME 9-skip floor - the estimator partition lowers to the + same gate as the M7 falcon, no separate estimator pole; (3) soft-float (m3/m4) EXPLODES register-allocator + pressure 6->27 (30 total) because there is no VFP register file - which INDEPENDENTLY CONFIRMS the F100 must + run the SMALL gale-verified failsafe FSM (VER-OS-HM-001), NOT a lowered full falcon (validates DD-025 core + partitioning + DD-026 decision 4 - you would never soft-float-lower the full cascade onto the F100). So the + float gate's true blocker set is the VFP-path 9 (shared M7/M4), F32ConvertI64S being its irreducible 3. tags: [release-watch, synth, arm, hard-float, gi-fpu, trunc-sat, on-target, falcon, blocking] fields: detected-by: jess release-watch chain-measure on synth v0.45.1 (meld v0.41.1, falcon-flight-v1.123); real-fused-core 26/156 skips vs the "#369 closed" claim; confirmed trunc_sat minimal repro; filed synth#782