Skip to content

Add fault tolerant logical state preparation circuits #327

Description

@perlinm

It would be very useful to have circuits that fault tolerantly prepare, say, a logical all-|0> or all-|+> state.

In addition to being practically useful for simulations and experiments, this would enable Steane and Knill QEC (#304)

Related work:

Metadata

Metadata

Assignees

No one assigned

    Labels

    circuitshigh desirabilitySome features are highly desirable, but may require a formidable effort to implement.

    Type

    No type

    Fields

    No fields configured for issues without a type.

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions