Investigating ADS7924 software reset timing

[ryan-summers]

Currently, the ADS7924 uses a hard-coded 500uS wait cycle to determine when the software reset is done, however issues like #67 indicate this may be a problematic bug.

The exact timing is not specified in the datasheet. A support request has been made to TI here: https://e2e.ti.com/support/data-converters/f/73/t/945550

Wait until we get feedback and then update the code as appropriate.

[hartytp]

@ryan-summers are the supplies valid through the reset (cf sinara-hw/Booster#366)?

[ryan-summers]

That's a really good investigative avenue, especially given that the comment on the e2e ticket seems to indicate the reset should occur within 2uS.

I'll probe the supply pin next time I get a chance.

[ryan-summers]

AVDD supply looks normal through the reset:

Channel 3 is connected to the capacitors at the AVDD input - I don't see any deviation from the nominal voltage of 3.4V during the software reset

[ryan-summers]

Just as a quick update: TI's representatives indicate that the hardware issue we have may cause longer-than-specified reset conditions due to abnormal current draw through ESD protection diodes. Nominally, the reset should complete within 5uS, so we should investigate if it's our hardware configuration that's causing the issue.

From the TI thread:

This may be affecting the digital functions of the device. The ESD structure of the device may be turning on when DVDD surpasses AVDD, and this may be causing current consumption issues that are slowing down the device.

I would suggest addressing the power supply regulation to make sure DVDD does not surpass AVDD. Then we can move forward with the debugging if still not fixed

[jordens]

Yes. Also noted in sinara-hw/Booster#366 (comment)
I am seeing two other issues related to the ADS7924: #66 (comment) (not solved by the delay) and #61