I have a suggestion for updating the RP2040 (and perhaps RP2350) datasheet regarding the input synchronizers. Section 3.5.6.3 refers to the flip flops adding "two cycles of latency". I assumed that the cycle referred to the PIO state cycle time. I now understand that the flip flops are clocked by the CLK_SYS instead. The WARNING box in that section makes an indirect reference to CLK_SYS but I would have appreciated a more clear statement of which signal is clocking the flip flops and the magnitude of the resulting latency.
Thank you.
I have a suggestion for updating the RP2040 (and perhaps RP2350) datasheet regarding the input synchronizers. Section 3.5.6.3 refers to the flip flops adding "two cycles of latency". I assumed that the cycle referred to the PIO state cycle time. I now understand that the flip flops are clocked by the CLK_SYS instead. The WARNING box in that section makes an indirect reference to CLK_SYS but I would have appreciated a more clear statement of which signal is clocking the flip flops and the magnitude of the resulting latency.
Thank you.