From c6d9ef6e06109c2215290c13a27586ce96a213e5 Mon Sep 17 00:00:00 2001 From: JamesKenneyImperas Date: Tue, 14 Feb 2023 09:46:27 +0000 Subject: [PATCH] define asynchronous interrupt priorities --- Sdtrig.tex | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Sdtrig.tex b/Sdtrig.tex index 064687b5..4513c7dc 100644 --- a/Sdtrig.tex +++ b/Sdtrig.tex @@ -115,8 +115,9 @@ \section{Priority} & 3 & & icount \\ & 3 & & itrigger \\ & 3 & & mcontrol/mcontrol6 after \\ - & & & \hspace{2em}(on previous instruction) \\ - \hline + & & & \hspace{2em}(on previous instruction) \\ \hline + & & Asynchronous interrupt enabled by & \\ + & & \hspace{2em}xRET or explicit CSR write & \\ \hline & 3 & Instruction address breakpoint & mcontrol/mcontrol6 execute address before \\ \hline & 12 & Instruction page fault & \\ \hline & 1 & Instruction access fault & \\ \hline @@ -156,6 +157,12 @@ \section{Priority} trace actions when triggers with different actions are also firing is left to the trace specification. +\begin{commentary} +Note that asynchronous interrupts are included in the priority table because, when +enabled by xRET or explicit CSR write instructions, these interrupts must be treated +as high priority events on the next instruction. +\end{commentary} + \section{Native Triggers} \label{sec:nativetrigger}