YESS/y86_machine.7 at master · sbennett1990/YESS · GitHub

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.\"
.\" Copyright (c) 2020 Scott Bennett <scottb@fastmail.com>
.\"
.\" Permission to use, copy, modify, and distribute this software for any
.\" purpose with or without fee is hereby granted, provided that the above
.\" copyright notice and this permission notice appear in all copies.
.\"
.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
.\"
.Dd July 21, 2020
.Dt Y86_MACHINE 7
.Os
.Sh NAME
.Nm y86_machine
.Nd Y86 processor reference
.Sh DESCRIPTION
The Y86
.Pq Dq YES
machine is a theoretical processor based on a subset of x86 concepts.
Being a teaching processor, Y86 embodies elements of both RISC and CISC
architectures.
The Y86 machine is a 32-bit little endian machine consisting of three main
components:
memory, program registers, and processor registers.
.Ss Memory
Y86 memory consists of 1024, 32-bit words.
Addresses generated during program execution are
.Sy byte
addresses
.Pq e.g. the address in the PC .
However, memory can only be accessed with
.Sy word
addresses.
If a byte of data is needed from memory, it is obtaining by first loading the
word it's contained within.
Thus, this simulates a memory system where the
.Em word
is the smallest accessible unit.
.Pp
The relationship between word addresses and byte addresses can be seen below.
.\" Table of memory addresses
.TS
allbox;
cw14 cz s s s
r    c  c c c.
Word Address	Byte Address
0	3	2	1	0
1	7	6	5	4
2	11	10	9	8
3	15	14	13	12
4	19	18	17	16
\&.	\&.	\&.	\&.	\&.
1023	4095	4094	4093	4092
.TE
.Ss Program Registers
The Y86 has 8 32-bit program registers.
The names of those registers and their encodings can be seen in the table below.
.\" Table of program registers
.TS
allbox;
cw15 c
r c.
Register Name	Number
%eax	0
%ecx	1
%edx	2
%ebx	3
%esp	4
%ebp	5
%esi	6
%edi	7
.TE
.Ss Processor Registers
The simulated processor consists of 5 pipeline registers:
freg, dreg, ereg, mreg, and wreg.
These registers hold the output of one stage of the pipeline that then becomes the input to
the next stage of the pipeline.
.Bl -tag -width "xreg" -offset indent
.It freg
Holds the input to the
.Sy fetch
stage.
This stage fetches instructions from memory to feed to the
.Dq processor .
.Bd -literal
struct fregister {
        unsigned int predPC;
};
.Ed
.Pp
The fields have the following meanings:
.Bl -tag -width "predPC" -compact
.It predPC
The byte address for the predicted PC.
.El
.It dreg
Holds the input to the
.Sy decode
stage.
.Bd -literal
struct dregister {
        unsigned int stat;
        unsigned int icode;
        unsigned int ifun;
        unsigned int rA;
        unsigned int rB;
        unsigned int valC;
        unsigned int valP;
};
.Ed
.Pp
The fields have the following meanings:
.Bl -tag -width "icode" -compact
.It stat
The "stat"?
.It icode
Instruction code.
.El
.It ereg
Holds the input to the
.Sy execute
stage.
.Bd -literal
struct eregister {
        unsigned int stat;
        unsigned int icode;
        unsigned int ifun;
        unsigned int valC;
        unsigned int valA;
        unsigned int valB;
        unsigned int dstE;
        unsigned int dstM;
        unsigned int srcA;
        unsigned int srcB;
};
.Ed
.It mreg
Holds the input to the
.Sy memory
stage.
.Bd -literal
struct mregister {
        unsigned int stat;
        unsigned int icode;
        unsigned int Cnd;
        unsigned int valE;
        unsigned int valA;
        unsigned int dstE;
        unsigned int dstM;
};
.Ed
.It wreg
Holds the input to the
.Sy writeback
stage.
.Bd -literal
struct wregister {
        unsigned int stat;
        unsigned int icode;
        unsigned int valE;
        unsigned int valM;
        unsigned int dstE;
        unsigned int dstM;
};
.Ed
.El
.Sh SEE ALSO
.Xr yess 1 ,
.Xr y86_obj_code 7