From 912e6b7ac4c436fdf251d73028c4d007e0633655 Mon Sep 17 00:00:00 2001 From: petergrossmann21 Date: Fri, 17 Oct 2025 20:43:32 -0400 Subject: [PATCH] Remove demo architectures --- logiklib/demo/K4_N8_6x6/K4_N8_6x6.py | 45 ------------- logiklib/demo/K4_N8_6x6/README.md | 35 ---------- .../demo/K6_N8_12x12_BD/K6_N8_12x12_BD.py | 64 ------------------- logiklib/demo/K6_N8_12x12_BD/README.md | 45 ------------- .../demo/K6_N8_28x28_BD/K6_N8_28x28_BD.py | 64 ------------------- logiklib/demo/K6_N8_28x28_BD/README.md | 45 ------------- logiklib/demo/K6_N8_3x3/K6_N8_3x3.py | 45 ------------- logiklib/demo/K6_N8_3x3/README.md | 35 ---------- logiklib/demo/README.md | 2 - logiklib/demo/__init__.py | 0 10 files changed, 380 deletions(-) delete mode 100644 logiklib/demo/K4_N8_6x6/K4_N8_6x6.py delete mode 100644 logiklib/demo/K4_N8_6x6/README.md delete mode 100644 logiklib/demo/K6_N8_12x12_BD/K6_N8_12x12_BD.py delete mode 100644 logiklib/demo/K6_N8_12x12_BD/README.md delete mode 100644 logiklib/demo/K6_N8_28x28_BD/K6_N8_28x28_BD.py delete mode 100644 logiklib/demo/K6_N8_28x28_BD/README.md delete mode 100644 logiklib/demo/K6_N8_3x3/K6_N8_3x3.py delete mode 100644 logiklib/demo/K6_N8_3x3/README.md delete mode 100644 logiklib/demo/README.md delete mode 100644 logiklib/demo/__init__.py diff --git a/logiklib/demo/K4_N8_6x6/K4_N8_6x6.py b/logiklib/demo/K4_N8_6x6/K4_N8_6x6.py deleted file mode 100644 index 696917f..0000000 --- a/logiklib/demo/K4_N8_6x6/K4_N8_6x6.py +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright 2024 Zero ASIC Corporation - -from logiklib import register_part_data - -from siliconcompiler import FPGA - - -#################################################### -# Setup for K4_N8_6x6 FPGA -#################################################### -def setup(): - part_name = 'K4_N8_6x6' - - fpga = FPGA(part_name, package=f"logik-fpga-{part_name}") - - register_part_data(fpga, part_name, f"logik-fpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'zeroasic') - - fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'K4_N8_6x6') - - fpga.set('fpga', part_name, 'lutsize', 4) - - fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'ideal') - - fpga.set('fpga', part_name, 'file', 'archfile', 'cad/K4_N8_6x6.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/K4_N8_6x6_rr_graph.xml') - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', 'dff') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/K4_N8_6x6_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/K4_N8_6x6_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 50) - - return fpga - - -######################### -if __name__ == "__main__": - fpga = setup() - assert fpga.check_filepaths() - fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/demo/K4_N8_6x6/README.md b/logiklib/demo/K4_N8_6x6/README.md deleted file mode 100644 index 7f171d4..0000000 --- a/logiklib/demo/K4_N8_6x6/README.md +++ /dev/null @@ -1,35 +0,0 @@ -# K4_N8_6x6 FPGA Virtual Architecture - -The K4_N8_6x6 FPGA is a fixed-size virtual FPGA architecture consisting of configurable logic blocks (CLBs) and I/O blocks (IOBs). - -A summary of K4_N8_6x6 resources is shown in the table below - -Resource Type | Count ----------------------|------ -Lookup Tables (LUTs) | 288 -Registers | 288 -GPIOs | 192 -Max Clock Domains | 1 - -K4_N8_6x6 logic resources are organized into an 8x8 array of components. A 6x6 array of CLBs is surrounded on the perimeter by four banks of IOBs, one per side of the array. Corner array locations are unused. - -## Logic Resources - -A brief description for K4_N8_6x6 logic resources is shown below - -### Configurable Logic Block (CLB) - -Each configurable logic block (CLB) consists of 8 4-input lookup-tables (LUTs). The LUTs in a CLB share common inputs through local routing called a crossbar. All LUT outputs are fed back to the crossbar so that they may be used as inputs within the CLB. Each LUT output can be paired with a flip-flop (register) to synchronize the LUT output to a common clock. Flip-flops not paired with a LUT can accept crossbar inputs directly. All flip-flop usage is automatically determined as part of the RTL-to-bitstream flow and is thus transparent to the user. - -### I/O Block (IOB) - -General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the FPGA and reconfigurable logic. Each IOB contains eight iopad primitives. Each iopad primitive can operate either in input mode or output mode. The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs. - -### Clocking - -This architecture uses an ideal clock model; clocks are modeled as globally distributed to all logic resources with zero delay. - -## K4_N8_6x6 Configuration - -K4_N8_6x6 bitstreams are generated using Logik. An 8-bit wide interface is used to load a generated bitstream. - diff --git a/logiklib/demo/K6_N8_12x12_BD/K6_N8_12x12_BD.py b/logiklib/demo/K6_N8_12x12_BD/K6_N8_12x12_BD.py deleted file mode 100644 index 9b854c8..0000000 --- a/logiklib/demo/K6_N8_12x12_BD/K6_N8_12x12_BD.py +++ /dev/null @@ -1,64 +0,0 @@ -# Copyright 2025 Zero ASIC Corporation - -from logiklib import register_part_data - -from siliconcompiler import FPGA - - -#################################################### -# Setup for K6_N8_12x12_BD FPGA -#################################################### -def setup(): - part_name = 'K6_N8_12x12_BD' - - fpga = FPGA(part_name, package=f"logik-fpga-{part_name}") - - register_part_data(fpga, part_name, f"logik-fpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'zeroasic') - - fpga.set('fpga', part_name, 'var', 'vpr_device_code', part_name) - - fpga.set('fpga', part_name, 'lutsize', 6) - fpga.set('fpga', part_name, 'var', 'feature_set', [ - 'async_reset', 'async_set', 'enable']) - - fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'ideal') - - fpga.set('fpga', part_name, 'file', 'archfile', 'cad/K6_N8_12x12_BD.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/K6_N8_12x12_BD_rr_graph.xml') - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', [ - 'dff', 'dffe', 'dffer', 'dffers', 'dffes', 'dffr', 'dffrs', 'dffs', - 'dsp_mult', 'bram_sp' - ]) - - fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'techlib/tech_flops.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'techlib/tech_bram.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'techlib/bram_memory_map.txt') - fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'techlib/tech_dsp.v') - - # Set the dsp options for the yosys built-in DSP correctly for this - # architecture - fpga.set('fpga', part_name, 'var', 'yosys_dsp_options', [ - 'DSP_A_MAXWIDTH=18', 'DSP_A_MINWIDTH=2', - 'DSP_B_MAXWIDTH=18', 'DSP_B_MINWIDTH=2', - 'DSP_NAME=_dsp_block_']) - - fpga.set('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/K6_N8_12x12_BD_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/K6_N8_12x12_BD_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 80) - - return fpga - - -######################### -if __name__ == "__main__": - fpga = setup() - assert fpga.check_filepaths() - fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/demo/K6_N8_12x12_BD/README.md b/logiklib/demo/K6_N8_12x12_BD/README.md deleted file mode 100644 index 36963c8..0000000 --- a/logiklib/demo/K6_N8_12x12_BD/README.md +++ /dev/null @@ -1,45 +0,0 @@ -# K6_N8_12x12_BD FPGA Virtual Architecture - -The K6_N8_12x12_BD FPGA is a fixed-size virtual FPGA architecture consisting of configurable logic blocks (CLBs), multipliers (DSP blocks), single-port SRAM blocks (BRAMs), and I/O blocks (IOBs). - -A summary of K6_N8_12x12_BD resources is shown in the table below - -Resource Type | Count ----------------------|------ -Lookup Tables (LUTs) | 736 -Registers | 736 -18x18 Multipliers | 1 -4KB SRAM Blocks | 1 -GPIOs | 352 -Max Clock Domains | 1 - -K6_N8_12x12_BD logic resources are organized into an 14x14 array of components. A 12x12 array of logic blocks is surrounded on the perimeter by four banks of IOBs, one per side of the array. Corner array locations are unused. - -## Logic Resources - -A brief description for K6_N8_12x12_BD logic resources is shown below - -### Configurable Logic Block (CLB) - -Each configurable logic block (CLB) consists of 8 6-input lookup-tables (LUTs). The LUTs in a CLB share common inputs through local routing called a crossbar. All LUT outputs are fed back to the crossbar so that they may be used as inputs within the CLB. Each LUT output can be paired with a flip-flop (register) to synchronize the LUT output to a common clock. Flip-flops not paired with a LUT can accept crossbar inputs directly. All flip-flop usage is automatically determined as part of the RTL-to-bitstream flow and is thus transparent to the user. - -### I/O Block (IOB) - -General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the FPGA and reconfigurable logic. Each IOB contains eight iopad primitives. Each iopad primitive can operate either in input mode or output mode. The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs. - -### 18x18 Multiplier Block (DSP) - -To demonstrate hard arithmetic technology mapping, hard multipliers are offered. The multipliers take two 18-bit inputs and produce a 36-bit output. The block is fully combinational to keep the model as simple as possible. The multipliers are modeled as occupying a 2x2 footprint within the 12x12 array of logic blocks. This sizing is chosen for demonstration purposes and does not reflect the relative sizing of the multiplier to the CLB in any process technology. - -### SRAM Block (BRAM) - -A fixed size single port SRAM is provided to demonstrate memory technology mapping. The memory macro is 4096x8 bits. Each macro is modeled as occupying a 2x2 footprint within the 12x12 array of logic blocks. This sizing is chosen for demonstration purposes and does not reflect the relative sizing of the SRAM to the CLB in any process technology. - -### Clocking - -This architecture uses an ideal clock model; clocks are modeled as globally distributed to all logic resources with zero delay. - -## K6_N8_12x12_BD Configuration - -K6_N8_12x12_BD bitstreams are generated using Logik. An 8-bit wide interface is used to load a generated bitstream. - diff --git a/logiklib/demo/K6_N8_28x28_BD/K6_N8_28x28_BD.py b/logiklib/demo/K6_N8_28x28_BD/K6_N8_28x28_BD.py deleted file mode 100644 index 7b8395a..0000000 --- a/logiklib/demo/K6_N8_28x28_BD/K6_N8_28x28_BD.py +++ /dev/null @@ -1,64 +0,0 @@ -# Copyright 2025 Zero ASIC Corporation - -from logiklib import register_part_data - -from siliconcompiler import FPGA - - -#################################################### -# Setup for K6_N8_28x28_BD FPGA -#################################################### -def setup(): - part_name = 'K6_N8_28x28_BD' - - fpga = FPGA(part_name, package=f"logik-fpga-{part_name}") - - register_part_data(fpga, part_name, f"logik-fpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'zeroasic') - - fpga.set('fpga', part_name, 'var', 'vpr_device_code', part_name) - - fpga.set('fpga', part_name, 'lutsize', 6) - fpga.set('fpga', part_name, 'var', 'feature_set', [ - 'async_reset', 'async_set', 'enable']) - - fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'ideal') - - fpga.set('fpga', part_name, 'file', 'archfile', 'cad/K6_N8_28x28_BD.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/K6_N8_28x28_BD_rr_graph.xml') - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', [ - 'dff', 'dffe', 'dffer', 'dffers', 'dffes', 'dffr', 'dffrs', 'dffs', - 'dsp_mult', 'bram_sp' - ]) - - fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'techlib/tech_flops.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'techlib/tech_bram.v') - fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'techlib/bram_memory_map.txt') - fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'techlib/tech_dsp.v') - - # Set the dsp options for the yosys built-in DSP correctly for this - # architecture - fpga.set('fpga', part_name, 'var', 'yosys_dsp_options', [ - 'DSP_A_MAXWIDTH=18', 'DSP_A_MINWIDTH=2', - 'DSP_B_MAXWIDTH=18', 'DSP_B_MINWIDTH=2', - 'DSP_NAME=_dsp_block_']) - - fpga.set('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/K6_N8_28x28_BD_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/K6_N8_28x28_BD_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 120) - - return fpga - - -######################### -if __name__ == "__main__": - fpga = setup() - assert fpga.check_filepaths() - fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/demo/K6_N8_28x28_BD/README.md b/logiklib/demo/K6_N8_28x28_BD/README.md deleted file mode 100644 index ff224bc..0000000 --- a/logiklib/demo/K6_N8_28x28_BD/README.md +++ /dev/null @@ -1,45 +0,0 @@ -# K6_N8_28x28_BD FPGA Virtual Architecture - -The K6_N8_28x28_BD FPGA is a fixed-size virtual FPGA architecture consisting of configurable logic blocks (CLBs), multipliers (DSP blocks), single-port SRAM blocks (BRAMs), and I/O blocks (IOBs). - -A summary of K6_N8_28x28_BD resources is shown in the table below - -Resource Type | Count ----------------------|------ -Lookup Tables (LUTs) | 4832 -Registers | 4832 -18x18 Multipliers | 9 -4KB SRAM Blocks | 9 -GPIOs | 864 -Max Clock Domains | 1 - -K6_N8_28x28_BD logic resources are organized into an 30x30 array of components. A 28x28 array of logic blocks is surrounded on the perimeter by four banks of IOBs, one per side of the array. Corner array locations are unused. - -## Logic Resources - -A brief description for K6_N8_28x28_BD logic resources is shown below - -### Configurable Logic Block (CLB) - -Each configurable logic block (CLB) consists of 8 6-input lookup-tables (LUTs). The LUTs in a CLB share common inputs through local routing called a crossbar. All LUT outputs are fed back to the crossbar so that they may be used as inputs within the CLB. Each LUT output can be paired with a flip-flop (register) to synchronize the LUT output to a common clock. Flip-flops not paired with a LUT can accept crossbar inputs directly. All flip-flop usage is automatically determined as part of the RTL-to-bitstream flow and is thus transparent to the user. - -### 18x18 Multiplier Block (DSP) - -To demonstrate hard arithmetic technology mapping, hard multipliers are offered. The multipliers take two 18-bit inputs and produce a 36-bit output. The block is fully combinational to keep the model as simple as possible. The multipliers are modeled as occupying a 2x2 footprint within the 28x28 array of logic blocks. This sizing is chosen for demonstration purposes and does not reflect the relative sizing of the multiplier to the CLB in any process technology. - -### SRAM Block (BRAM) - -A fixed size single port SRAM is provided to demonstrate memory technology mapping. The memory macro is 4096x8 bits. Each macro is modeled as occupying a 2x2 footprint within the 28x28 array of logic blocks. This sizing is chosen for demonstration purposes and does not reflect the relative sizing of the SRAM to the CLB in any process technology. - -### I/O Block (IOB) - -General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the FPGA and reconfigurable logic. Each IOB contains eight iopad primitives. Each iopad primitive can operate either in input mode or output mode. The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs. - -### Clocking - -This architecture uses an ideal clock model; clocks are modeled as globally distributed to all logic resources with zero delay. - -## K6_N8_28x28_BD Configuration - -K6_N8_28x28_BD bitstreams are generated using Logik. An 8-bit wide interface is used to load a generated bitstream. - diff --git a/logiklib/demo/K6_N8_3x3/K6_N8_3x3.py b/logiklib/demo/K6_N8_3x3/K6_N8_3x3.py deleted file mode 100644 index 23ef4ba..0000000 --- a/logiklib/demo/K6_N8_3x3/K6_N8_3x3.py +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright 2024 Zero ASIC Corporation - -from logiklib import register_part_data - -from siliconcompiler import FPGA - - -#################################################### -# Setup for K6_N8_3x3 FPGA -#################################################### -def setup(): - part_name = 'K6_N8_3x3' - - fpga = FPGA(part_name, package=f"logik-fpga-{part_name}") - - register_part_data(fpga, part_name, f"logik-fpga-{part_name}") - - fpga.set('fpga', part_name, 'vendor', 'zeroasic') - - fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'K6_N8_3x3') - - fpga.set('fpga', part_name, 'lutsize', 6) - - fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'ideal') - - fpga.set('fpga', part_name, 'file', 'archfile', 'cad/K6_N8_3x3.xml') - fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/K6_N8_3x3_rr_graph.xml') - - for tool in ('vpr', 'yosys'): - fpga.set('fpga', part_name, 'var', f'{tool}_registers', 'dff') - - fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/K6_N8_3x3_bitstream_map.json') - - fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/K6_N8_3x3_constraint_map.json') - - fpga.set('fpga', part_name, 'var', 'channelwidth', 40) - - return fpga - - -######################### -if __name__ == "__main__": - fpga = setup() - assert fpga.check_filepaths() - fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/demo/K6_N8_3x3/README.md b/logiklib/demo/K6_N8_3x3/README.md deleted file mode 100644 index 6ef8c3d..0000000 --- a/logiklib/demo/K6_N8_3x3/README.md +++ /dev/null @@ -1,35 +0,0 @@ -# K6_N8_3x3 FPGA Virtual Architecture - -The K6_N8_3x3 FPGA is a fixed-size virtual FPGA architecture consisting of configurable logic blocks (CLBs) and I/O blocks (IOBs). - -A summary of K6_N8_3x3 resources is shown in the table below - -Resource Type | Count ----------------------|------ -Lookup Tables (LUTs) | 72 -Registers | 72 -GPIOs | 96 -Max Clock Domains | 1 - -K6_N8_3x3 logic resources are organized into an 5x5 array of components. A 3x3 array of CLBs is surrounded on the perimeter by four banks of IOBs, one per side of the array. Corner array locations are unused. - -## Logic Resources - -A brief description for K6_N8_3x3 logic resources is shown below - -### Configurable Logic Block (CLB) - -Each configurable logic block (CLB) consists of 8 6-input lookup-tables (LUTs). The LUTs in a CLB share common inputs through local routing called a crossbar. All LUT outputs are fed back to the crossbar so that they may be used as inputs within the CLB. Each LUT output can be paired with a flip-flop (register) to synchronize the LUT output to a common clock. Flip-flops not paired with a LUT can accept crossbar inputs directly. All flip-flop usage is automatically determined as part of the RTL-to-bitstream flow and is thus transparent to the user. - -### I/O Block (IOB) - -General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the FPGA and reconfigurable logic. Each IOB contains eight iopad primitives. Each iopad primitive can operate either in input mode or output mode. The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs. - -### Clocking - -This architecture uses an ideal clock model; clocks are modeled as globally distributed to all logic resources with zero delay. - -## K6_N8_3x3 Configuration - -K6_N8_3x3 bitstreams are generated using Logik. An 8-bit wide interface is used to load a generated bitstream. - diff --git a/logiklib/demo/README.md b/logiklib/demo/README.md deleted file mode 100644 index c9f75fe..0000000 --- a/logiklib/demo/README.md +++ /dev/null @@ -1,2 +0,0 @@ - -# PLACE-HOLDER \ No newline at end of file diff --git a/logiklib/demo/__init__.py b/logiklib/demo/__init__.py deleted file mode 100644 index e69de29..0000000