diff --git a/logiklib/__init__.py b/logiklib/__init__.py index f39bbd0..8143db1 100644 --- a/logiklib/__init__.py +++ b/logiklib/__init__.py @@ -1,7 +1,7 @@ -__version__ = "0.1.0" +__version__ = "0.1.2" def register_part_data(fpga, package_name, part_name): fpga.set_dataroot( package_name, - f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz") + f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz", f"v{__version__}") diff --git a/logiklib/zeroasic/z1000/z1000.py b/logiklib/zeroasic/z1000/z1000.py index dc9eb5a..24c7cfd 100644 --- a/logiklib/zeroasic/z1000/z1000.py +++ b/logiklib/zeroasic/z1000/z1000.py @@ -37,10 +37,10 @@ def __init__(self): self.set_vpr_clockmodel("route") with self.active_dataroot("logik-fpga-z1000"): - self.set_vpr_archfile('cad/z1000.xml') - self.set_vpr_graphfile('cad/z1000_rr_graph.xml') - self.set_yosys_config('cad/z1000_yosys_config.json') - self.set_yosys_flipfloptechmap('cad/tech_flops.v') + self.set_vpr_archfile('z1000/cad/z1000.xml') + self.set_vpr_graphfile('z1000/cad/z1000_rr_graph.xml') + self.set_yosys_config('z1000/cad/z1000_yosys_config.json') + self.set_yosys_flipfloptechmap('z1000/cad/tech_flops.v') # Define the macros that can be techmapped to based on the modes # that exist in the design @@ -122,15 +122,15 @@ def __init__(self): # TODO: blackbox_options with self.active_dataroot("logik-fpga-z1000"): - self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1000_bitstream_map.json') - self.set_vpr_constraintsmap('cad/z1000_constraint_map.json') + self.set("tool", "convert_bitstream", "bitstream_map", 'z1000/cad/z1000_bitstream_map.json') + self.set_vpr_constraintsmap('z1000/cad/z1000_constraint_map.json') self.set_vpr_channelwidth(100) with self.active_dataroot("logik-fpga-z1000"): with self.active_fileset("z1000_opensta_liberty_files"): - self.add_file('cad/vtr_primitives.lib') - self.add_file(['cad/tech_flops.lib']) + self.add_file('z1000/cad/vtr_primitives.lib') + self.add_file(['z1000/cad/tech_flops.lib']) self.add_opensta_liberty_fileset() self.set_vpr_router_lookahead('classic') diff --git a/logiklib/zeroasic/z1002/z1002.py b/logiklib/zeroasic/z1002/z1002.py index 2f39684..c83efcf 100644 --- a/logiklib/zeroasic/z1002/z1002.py +++ b/logiklib/zeroasic/z1002/z1002.py @@ -37,10 +37,10 @@ def __init__(self): self.set_vpr_clockmodel("route") with self.active_dataroot("logik-fpga-z1002"): - self.set_vpr_archfile('cad/z1002.xml') - self.set_vpr_graphfile('cad/z1002_rr_graph.xml') - self.set_yosys_config('cad/z1002_yosys_config.json') - self.set_yosys_flipfloptechmap('cad/tech_flops.v') + self.set_vpr_archfile('z1002/cad/z1002.xml') + self.set_vpr_graphfile('z1002/cad/z1002_rr_graph.xml') + self.set_yosys_config('z1002/cad/z1002_yosys_config.json') + self.set_yosys_flipfloptechmap('z1002/cad/tech_flops.v') # Define the macros that can be techmapped to based on the modes # that exist in the design @@ -122,15 +122,15 @@ def __init__(self): # TODO: blackbox_options with self.active_dataroot("logik-fpga-z1002"): - self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1002_bitstream_map.json') - self.set_vpr_constraintsmap('cad/z1002_constraint_map.json') + self.set("tool", "convert_bitstream", "bitstream_map", 'z1002/cad/z1002_bitstream_map.json') + self.set_vpr_constraintsmap('z1002/cad/z1002_constraint_map.json') self.set_vpr_channelwidth(150) with self.active_dataroot("logik-fpga-z1002"): with self.active_fileset("z1002_opensta_liberty_files"): - self.add_file('cad/vtr_primitives.lib') - self.add_file(['cad/tech_flops.lib']) + self.add_file('z1002/cad/vtr_primitives.lib') + self.add_file(['z1002/cad/tech_flops.lib']) self.add_opensta_liberty_fileset() self.set_vpr_router_lookahead('classic') diff --git a/logiklib/zeroasic/z1010/z1010.py b/logiklib/zeroasic/z1010/z1010.py index 43c00c1..200b248 100644 --- a/logiklib/zeroasic/z1010/z1010.py +++ b/logiklib/zeroasic/z1010/z1010.py @@ -37,13 +37,13 @@ def __init__(self): self.set_vpr_clockmodel("route") with self.active_dataroot("logik-fpga-z1010"): - self.set_vpr_archfile('cad/z1010.xml') - self.set_vpr_graphfile('cad/z1010_rr_graph.xml') - self.set_yosys_config('cad/z1010_yosys_config.json') - self.set_yosys_flipfloptechmap('cad/tech_flops.v') - self.set_yosys_memorymap(techmap='cad/tech_bram.v') - self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt') - self.set_yosys_dsptechmap('cad/tech_dsp.v', + self.set_vpr_archfile('z1010/cad/z1010.xml') + self.set_vpr_graphfile('z1010/cad/z1010_rr_graph.xml') + self.set_yosys_config('z1010/cad/z1010_yosys_config.json') + self.set_yosys_flipfloptechmap('z1010/cad/tech_flops.v') + self.set_yosys_memorymap(techmap='z1010/cad/tech_bram.v') + self.set_yosys_memorymap(libmap='z1010/cad/bram_memory_map.txt') + self.set_yosys_dsptechmap('z1010/cad/tech_dsp.v', options={'DSP_SIGNEDONLY': '1', 'DSP_A_MAXWIDTH': '18', 'DSP_B_MAXWIDTH': '18', @@ -51,7 +51,7 @@ def __init__(self): 'DSP_B_MINWIDTH': '2', 'DSP_Y_MINWIDTH': '2', 'DSP_NAME': '_dsp_block_'}) - self.add_yosys_macrolib('cad/tech_dsp_blackbox.v') + self.add_yosys_macrolib('z1010/cad/tech_dsp_blackbox.v') # Define the macros that can be techmapped to based on the modes # that exist in the design @@ -169,15 +169,15 @@ def __init__(self): # TODO: blackbox_options with self.active_dataroot("logik-fpga-z1010"): - self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1010_bitstream_map.json') - self.set_vpr_constraintsmap('cad/z1010_constraint_map.json') + self.set("tool", "convert_bitstream", "bitstream_map", 'z1010/cad/z1010_bitstream_map.json') + self.set_vpr_constraintsmap('z1010/cad/z1010_constraint_map.json') self.set_vpr_channelwidth(100) with self.active_dataroot("logik-fpga-z1010"): with self.active_fileset("z1010_opensta_liberty_files"): - self.add_file('cad/vtr_primitives.lib') - self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib']) + self.add_file('z1010/cad/vtr_primitives.lib') + self.add_file(['z1010/cad/tech_flops.lib', 'z1010/cad/tech_dsp.lib', 'z1010/cad/tech_bram.lib']) self.add_opensta_liberty_fileset() self.set_vpr_router_lookahead('classic') diff --git a/logiklib/zeroasic/z1012/z1012.py b/logiklib/zeroasic/z1012/z1012.py index ea1a4e2..db35bba 100644 --- a/logiklib/zeroasic/z1012/z1012.py +++ b/logiklib/zeroasic/z1012/z1012.py @@ -37,13 +37,13 @@ def __init__(self): self.set_vpr_clockmodel("route") with self.active_dataroot("logik-fpga-z1012"): - self.set_vpr_archfile('cad/z1012.xml') - self.set_vpr_graphfile('cad/z1012_rr_graph.xml') - self.set_yosys_config('cad/z1012_yosys_config.json') - self.set_yosys_flipfloptechmap('cad/tech_flops.v') - self.set_yosys_memorymap(techmap='cad/tech_bram.v') - self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt') - self.set_yosys_dsptechmap('cad/tech_dsp.v', + self.set_vpr_archfile('z1012/cad/z1012.xml') + self.set_vpr_graphfile('z1012/cad/z1012_rr_graph.xml') + self.set_yosys_config('z1012/cad/z1012_yosys_config.json') + self.set_yosys_flipfloptechmap('z1012/cad/tech_flops.v') + self.set_yosys_memorymap(techmap='z1012/cad/tech_bram.v') + self.set_yosys_memorymap(libmap='z1012/cad/bram_memory_map.txt') + self.set_yosys_dsptechmap('z1012/cad/tech_dsp.v', options={'DSP_SIGNEDONLY': '1', 'DSP_A_MAXWIDTH': '18', 'DSP_B_MAXWIDTH': '18', @@ -51,7 +51,7 @@ def __init__(self): 'DSP_B_MINWIDTH': '2', 'DSP_Y_MINWIDTH': '2', 'DSP_NAME': '_dsp_block_'}) - self.add_yosys_macrolib('cad/tech_dsp_blackbox.v') + self.add_yosys_macrolib('z1012/cad/tech_dsp_blackbox.v') # Define the macros that can be techmapped to based on the modes # that exist in the design @@ -169,15 +169,15 @@ def __init__(self): # TODO: blackbox_options with self.active_dataroot("logik-fpga-z1012"): - self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1012_bitstream_map.json') - self.set_vpr_constraintsmap('cad/z1012_constraint_map.json') + self.set("tool", "convert_bitstream", "bitstream_map", 'z1012/cad/z1012_bitstream_map.json') + self.set_vpr_constraintsmap('z1012/cad/z1012_constraint_map.json') self.set_vpr_channelwidth(150) with self.active_dataroot("logik-fpga-z1012"): with self.active_fileset("z1012_opensta_liberty_files"): - self.add_file('cad/vtr_primitives.lib') - self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib']) + self.add_file('z1012/cad/vtr_primitives.lib') + self.add_file(['z1012/cad/tech_flops.lib', 'z1012/cad/tech_dsp.lib', 'z1012/cad/tech_bram.lib']) self.add_opensta_liberty_fileset() self.set_vpr_router_lookahead('classic') diff --git a/logiklib/zeroasic/z1060/z1060.py b/logiklib/zeroasic/z1060/z1060.py index b5732d6..db8db27 100644 --- a/logiklib/zeroasic/z1060/z1060.py +++ b/logiklib/zeroasic/z1060/z1060.py @@ -37,13 +37,13 @@ def __init__(self): self.set_vpr_clockmodel("route") with self.active_dataroot("logik-fpga-z1060"): - self.set_vpr_archfile('cad/z1060.xml') - self.set_vpr_graphfile('cad/z1060_rr_graph.xml') - self.set_yosys_config('cad/z1060_yosys_config.json') - self.set_yosys_flipfloptechmap('cad/tech_flops.v') - self.set_yosys_memorymap(techmap='cad/tech_bram.v') - self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt') - self.set_yosys_dsptechmap('cad/tech_dsp.v', + self.set_vpr_archfile('z1060/cad/z1060.xml') + self.set_vpr_graphfile('z1060/cad/z1060_rr_graph.xml') + self.set_yosys_config('z1060/cad/z1060_yosys_config.json') + self.set_yosys_flipfloptechmap('z1060/cad/tech_flops.v') + self.set_yosys_memorymap(techmap='z1060/cad/tech_bram.v') + self.set_yosys_memorymap(libmap='z1060/cad/bram_memory_map.txt') + self.set_yosys_dsptechmap('z1060/cad/tech_dsp.v', options={'DSP_SIGNEDONLY': '1', 'DSP_A_MAXWIDTH': '18', 'DSP_B_MAXWIDTH': '18', @@ -51,7 +51,7 @@ def __init__(self): 'DSP_B_MINWIDTH': '2', 'DSP_Y_MINWIDTH': '2', 'DSP_NAME': '_dsp_block_'}) - self.add_yosys_macrolib('cad/tech_dsp_blackbox.v') + self.add_yosys_macrolib('z1060/cad/tech_dsp_blackbox.v') # Define the macros that can be techmapped to based on the modes # that exist in the design @@ -169,15 +169,15 @@ def __init__(self): # TODO: blackbox_options with self.active_dataroot("logik-fpga-z1060"): - self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1060_bitstream_map.json') - self.set_vpr_constraintsmap('cad/z1060_constraint_map.json') + self.set("tool", "convert_bitstream", "bitstream_map", 'z1060/cad/z1060_bitstream_map.json') + self.set_vpr_constraintsmap('z1060/cad/z1060_constraint_map.json') self.set_vpr_channelwidth(100) with self.active_dataroot("logik-fpga-z1060"): with self.active_fileset("z1060_opensta_liberty_files"): - self.add_file('cad/vtr_primitives.lib') - self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib']) + self.add_file('z1060/cad/vtr_primitives.lib') + self.add_file(['z1060/cad/tech_flops.lib', 'z1060/cad/tech_dsp.lib', 'z1060/cad/tech_bram.lib']) self.add_opensta_liberty_fileset() self.set_vpr_router_lookahead('classic') diff --git a/logiklib/zeroasic/z1062/z1062.py b/logiklib/zeroasic/z1062/z1062.py index 275c4a7..b8c932f 100644 --- a/logiklib/zeroasic/z1062/z1062.py +++ b/logiklib/zeroasic/z1062/z1062.py @@ -37,13 +37,13 @@ def __init__(self): self.set_vpr_clockmodel("route") with self.active_dataroot("logik-fpga-z1062"): - self.set_vpr_archfile('cad/z1062.xml') - self.set_vpr_graphfile('cad/z1062_rr_graph.xml') - self.set_yosys_config('cad/z1062_yosys_config.json') - self.set_yosys_flipfloptechmap('cad/tech_flops.v') - self.set_yosys_memorymap(techmap='cad/tech_bram.v') - self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt') - self.set_yosys_dsptechmap('cad/tech_dsp.v', + self.set_vpr_archfile('z1062/cad/z1062.xml') + self.set_vpr_graphfile('z1062/cad/z1062_rr_graph.xml') + self.set_yosys_config('z1062/cad/z1062_yosys_config.json') + self.set_yosys_flipfloptechmap('z1062/cad/tech_flops.v') + self.set_yosys_memorymap(techmap='z1062/cad/tech_bram.v') + self.set_yosys_memorymap(libmap='z1062/cad/bram_memory_map.txt') + self.set_yosys_dsptechmap('z1062/cad/tech_dsp.v', options={'DSP_SIGNEDONLY': '1', 'DSP_A_MAXWIDTH': '18', 'DSP_B_MAXWIDTH': '18', @@ -51,7 +51,7 @@ def __init__(self): 'DSP_B_MINWIDTH': '2', 'DSP_Y_MINWIDTH': '2', 'DSP_NAME': '_dsp_block_'}) - self.add_yosys_macrolib('cad/tech_dsp_blackbox.v') + self.add_yosys_macrolib('z1062/cad/tech_dsp_blackbox.v') # Define the macros that can be techmapped to based on the modes # that exist in the design @@ -169,15 +169,15 @@ def __init__(self): # TODO: blackbox_options with self.active_dataroot("logik-fpga-z1062"): - self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1062_bitstream_map.json') - self.set_vpr_constraintsmap('cad/z1062_constraint_map.json') + self.set("tool", "convert_bitstream", "bitstream_map", 'z1062/cad/z1062_bitstream_map.json') + self.set_vpr_constraintsmap('z1062/cad/z1062_constraint_map.json') self.set_vpr_channelwidth(150) with self.active_dataroot("logik-fpga-z1062"): with self.active_fileset("z1062_opensta_liberty_files"): - self.add_file('cad/vtr_primitives.lib') - self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib']) + self.add_file('z1062/cad/vtr_primitives.lib') + self.add_file(['z1062/cad/tech_flops.lib', 'z1062/cad/tech_dsp.lib', 'z1062/cad/tech_bram.lib']) self.add_opensta_liberty_fileset() self.set_vpr_router_lookahead('classic')