diff --git a/logiklib/zeroasic/z1002/README.md b/logiklib/zeroasic/z1002/README.md new file mode 100644 index 0000000..bbd42dd --- /dev/null +++ b/logiklib/zeroasic/z1002/README.md @@ -0,0 +1,96 @@ +# Z1002 eFPGA + +The Z1002 eFPGA is a fixed-size eFPGA architecture consisting of configurable logic blocks (CLBs), I/O blocks (IOBs), and a clock I/O block for clock distribution. + +## Z1002 Architecture + +A summary of Z1002 resources is shown in the table below + +Resource Type | Count +---------------------|------ +Lookup Tables (LUTs) | 8192 +Registers | 8192 +GPIOs | 2048 +Max Clock Domains | 4 + +The Z1002 architecture XML file provides a complete specification of how logic resources are arranged in this grid, the port lists of all logic resources, and how logic resources are organized and connected. Hierarchical representations of logic blocks are provided where needed to enable correct, efficient packing and placement of a user's netlist. The architecture XML also provides a delay model for the eFPGA and FASM feature metadata to enable logic block bitstream generation. The Z1002 routing graph XML file encapsulates a complete model of the eFPGA interconnect architecture and contains the FASM feature metadata for interconnect bitstream generation. + +The following sections summarize the architecture features of Z1002. + +### Array and Grid Model + +Z1002 logic resources are organized into an 34x34 array of components, depicted in the figure below. A 32x32 array of CLBs is surrounded on the perimeter by four banks of IOBs, one per side of the array. Corner array locations are used for programmable interconnect only with the exception of the lower left corner, where the clock IOB is placed. + +![z1002_array_diagram](./docs/z1002_Block_Diagram.png ) + +For modeling in VPR, this array of components is arranged on a 36x36 (X,Y) grid. The lower left corner of Z1002 (the clock IOB) is located at (1,1) on this grid. All locations at X=0, X=19, Y=0, and Y=19 are modeled as empty. This perimeter of empty locations is required to model the architecture in VPR correctly. + +### Logic Resource Types + +Brief descriptions and block diagrams for Z1002 logic resources are shown below. + +#### Configurable Logic Block (CLB) + +Each configurable logic block (CLB) consists of 8 4-input basic logic elements (BLEs). A block diagram of the BLE is shown below. The BLE contains a 4-input lookup table (LUT) a configurable flip-flop, and a multiplexer that selects whether the primary output of the BLE comes from the flip-flop or directly from the LUT. The flip-flop output is also routed out of the BLE as a secondary output; this secondary output is connected only to local interconnect in the CLB. + +![ble_block_diagram](../z1000/docs/BLE4_Block_Diagram.png ) + +The BLEs in a CLB share 18 common inputs through the CLB local interconnect, an array of multiplexers referred to as the CLB crossbar. Each BLE input is driven by a dedicated crossbar multiplexer that selects from a subset of the CLB inputs, BLE primary outputs, and BLE secondary outputs. The CLB inputs are subdivided between north, south, east, and west sides of the CLB to improve their interface to the eFPGA global interconnect. The BLE primary outputs are also outputs of the CLB and route directly to eFPGA global interconnect. The overall CLB block diagram is shown below. The BLE output feedback paths to the crossbar are not shown in the diagram to preserve diagram clarity. + +![clb_block_diagram](../z1000/docs/CLB4_Block_Diagram.png) + +#### I/O Block (IOB) + +General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the eFPGA and reconfigurable logic. Each IOB contains eight iopad primitives. Each iopad primitive can operate either in input mode or output mode. The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs. During RTL-to-bitstream generation, each top level RTL port directly maps to an iopad primitives via pin constraints. + +The figure below shows a block diagram of the iopad primitive. Each iopad enables a single signal to be connected . The data direction is determined during bitstream generation and stored in a configuration bit that is directly wired to an output enable signal pad_oe that is accessible as a top level signal of the eFPGA. When in input mode, the pad_in signal is received from external logic and passed to eFPGA logic via the inpad signal. Similarly, in output mode the outpad signal is received from eFPGA logic and passed to pad_out. + +![iob_block_diagram](../z1000/docs/IOB_Block_Diagram.png) + +#### Clock I/O Block (Clock IOB) + +A dedicated I/O block is provided that is only used for delivering clocks to the programmable logic. This I/O block is referred to as the clock IOB. It is constructed from the same iopad primitive as the general purpose I/O blocks, but internally connected to the eFPGA clock network rather than to programmable interconnect. + +## Z1002 Pin Constraints + +Z1002 implements the signals in the table below as valid pin names for specifying pin constraints in a JSON pin constraints file (PCF). Standard bus notatation using square brackets is required for all pins in the PCF. For example, to constrain a user input signal `foo` to bit 17 of `gpio_in_east`, the following content should be included in the PCF file + +``` + "foo": { + "direction": "input", + "pin": "gpio_in_east[17]" + }, +``` + +> **_NOTE:_** User clock signals must be mapped to the gpio_in_clk bus + +Pin Name | Direction | MSB | LSB | Purpose +--------------------------|-----------|-----|-----|--------- +gpio_in_clk | input | 3 | 0 | User clocks +gpio_in_south | input | 511 | 0 | South side GPIO inputs +gpio_in_north | input | 511 | 0 | North side GPIO inputs +gpio_in_west | input | 511 | 0 | West side GPIO inputs +gpio_in_east | input | 511 | 0 | East side GPIO inputs +gpio_out_south | output | 511 | 0 | South side GPIO outputs +gpio_oe_south | output | 511 | 0 | South side GPIO output enables +gpio_out_north | output | 511 | 0 | North side GPIO outputs +gpio_oe_north | output | 511 | 0 | North side GPIO output enables +gpio_out_west | output | 511 | 0 | West side GPIO outputs +gpio_oe_west | output | 511 | 0 | West side GPIO output enables +gpio_out_east | output | 511 | 0 | East side GPIO outputs +gpio_oe_east | output | 511 | 0 | East side GPIO output enables + +## Z1002 Bitstream Mapping + +The Z1002 bitstream format is organized into a four-dimensional array of configuration bits. The four dimensions are the VPR grid X coordinate, VPR grid Y coordinate, word address, and bit index. + +The table below shows the minimum and maximum array values for this array. Note that not all positions in the array contain valid configuration bits. + +Index | Min | Max | +------------|------|-----| +X | 0 | 35 | +Y | 0 | 35 | +Address | 0 | 142 | +Bit Index | 0 | 7 | + +The Z1002 bitstream map file specifies a mapping from these array indices to each FASM feature defined in the Z1002 VPR architecture file and routing graph XML file. diff --git a/logiklib/zeroasic/z1002/docs/z1002_Block_Diagram.png b/logiklib/zeroasic/z1002/docs/z1002_Block_Diagram.png new file mode 100644 index 0000000..3f3a3ec Binary files /dev/null and b/logiklib/zeroasic/z1002/docs/z1002_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1002/z1002.json b/logiklib/zeroasic/z1002/z1002.json new file mode 100644 index 0000000..61fcd7b --- /dev/null +++ b/logiklib/zeroasic/z1002/z1002.json @@ -0,0 +1,15 @@ +{ + "name": "z1002", + "fpga_x_size": 32, + "fpga_y_size": 32, + "num_routing_channels": 150, + "num_clb_inputs": 18, + "lut_size": 4, + "bles_per_clb": 8, + "outputs_per_ble": 1, + "crossbar_size": 15, + "sb_fraction": 0.15, + "logic_fraction": 0.15, + "ios_per_iob": 16, + "num_fracturable_elements": 1 +} diff --git a/logiklib/zeroasic/z1002/z1002.py b/logiklib/zeroasic/z1002/z1002.py new file mode 100644 index 0000000..c7b4b52 --- /dev/null +++ b/logiklib/zeroasic/z1002/z1002.py @@ -0,0 +1,107 @@ +# Copyright 2025 Zero ASIC Corporation +# Licensed under the Apache 2.0 License (see LICENSE for details) +# Auto-generated by FPGA Architect + +from logiklib import register_part_data + +from siliconcompiler import FPGA + + +#################################################### +# Setup for z1002 FPGA +#################################################### +def setup(): + + part_name = 'z1002' + + fpga = FPGA(part_name, package='logik-fpga-z1002') + + register_part_data(fpga, part_name, f"logik-fpga-{part_name}") + + fpga.set('fpga', part_name, 'vendor', 'fpga_architect') + + fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1002') + + fpga.set('fpga', part_name, 'lutsize', 4) + fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') + fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') + fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') + fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1002.xml') + fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1002_rr_graph.xml') + fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1002_yosys_config.json') + fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_registers', ['dffe', 'dffr', 'dffer', 'dff']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_dsps', + ['efpga_mult_addc', + 'efpga_acc_regi', + 'efpga_mult_addc_regi', + 'efpga_adder_regio', + 'dsp_mult', + 'efpga_acc', + 'efpga_adder_rego', + 'efpga_macc_pipe_regi', + 'efpga_mult_addc_rego', + 'efpga_mult_addc_regio', + 'efpga_mult', + 'efpga_macc_regi', + 'efpga_mult_regi', + 'efpga_mult_rego', + 'efpga_adder_regi', + 'efpga_macc', + 'efpga_macc_pipe', + 'efpga_mult_regio', + 'efpga_adder']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_brams', + ['sram_sdp', + 'tdpram_256x4', + 'sdpram_1024x1', + 'sdpram_512x2', + 'sram_sp', + 'spram_64x16', + 'tdpram_128x8', + 'tdpram_512x2', + 'spram_512x2', + 'spram_128x8', + 'sdpram_128x8', + 'spram_256x4', + 'sram_tdp', + 'sdpram_256x4', + 'tdpram_1024x1', + 'spram_1024x1']) + + # Set the dsp options for the yosys built-in DSP correctly for this + # architecture + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') + + fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') + + fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1002_bitstream_map.json') + + fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1002_constraint_map.json') + + fpga.set('fpga', part_name, 'var', 'channelwidth', 150) + + # Add the liberty files to the fpga part. + fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') + fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib']) + + return fpga + + +######################### +if __name__ == "__main__": + fpga = setup() + assert fpga.check_filepaths() + fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/zeroasic/z1010/README.md b/logiklib/zeroasic/z1010/README.md new file mode 100644 index 0000000..78b4918 --- /dev/null +++ b/logiklib/zeroasic/z1010/README.md @@ -0,0 +1,127 @@ +# Z1010 eFPGA + +The Z1010 eFPGA is a fixed-size eFPGA architecture consisting of configurable logic blocks (CLBs), I/O blocks (IOBs), and a clock I/O block for clock distribution. + +## Z1010 Architecture + +A summary of Z1010 resources is shown in the table below + +Resource Type | Count +---------------------|------ +Lookup Tables (LUTs) | 1664 +Registers | 1664 +GPIOs | 1024 +DSPs | 4 +BRAMs (16Kbit) | 4 +Max Clock Domains | 4 + +The Z1010 architecture XML file provides a complete specification of how logic resources are arranged in this grid, the port lists of all logic resources, and how logic resources are organized and connected. Hierarchical representations of logic blocks are provided where needed to enable correct, efficient packing and placement of a user's netlist. The architecture XML also provides a delay model for the eFPGA and FASM feature metadata to enable logic block bitstream generation. The Z1010 routing graph XML file encapsulates a complete model of the eFPGA interconnect architecture and contains the FASM feature metadata for interconnect bitstream generation. + +The following sections summarize the architecture features of Z1010. + +### Array and Grid Model + +Z1010 logic resources are organized into an 18x18 array of components, depicted in the figure below. A 16x16 array of logic blocks is surrounded on the perimeter by four banks of IOBs, one per side of the array. One column of logic blocks is consumed by four DSP blocks. Four block RAMs (BRAMs) consume an additional two columns. Corner array locations are used for programmable interconnect only with the exception of the lower left corner, where a special IOB for delivering clocks is placed. + +![z1010_array_diagram](./docs/z1010_Block_Diagram.png ) + +For modeling in VPR, this array of components is arranged on a 20x20 (X,Y) grid. The lower left corner of Z1010 (the clock IOB) is located at (1,1) on this grid. All locations at X=0, X=19, Y=0, and Y=19 are modeled as empty. This perimeter of empty locations is required to model the architecture in VPR correctly. + +### Logic Resource Types + +Brief descriptions and block diagrams for Z1010 logic resources are shown below. + +#### Configurable Logic Block (CLB) + +Each configurable logic block (CLB) consists of 8 4-input basic logic elements (BLEs). A block diagram of the BLE is shown below. The BLE contains a 4-input lookup table (LUT) a configurable flip-flop, and a multiplexer that selects whether the primary output of the BLE comes from the flip-flop or directly from the LUT. The flip-flop output is also routed out of the BLE as a secondary output; this secondary output is connected only to local interconnect in the CLB. + +![ble_block_diagram](../z1000/docs/BLE4_Block_Diagram.png ) + +The BLEs in a CLB share 18 common inputs through the CLB local interconnect, an array of multiplexers referred to as the CLB crossbar. Each BLE input is driven by a dedicated crossbar multiplexer that selects from a subset of the CLB inputs, BLE primary outputs, and BLE secondary outputs. The CLB inputs are subdivided between north, south, east, and west sides of the CLB to improve their interface to the eFPGA global interconnect. The BLE primary outputs are also outputs of the CLB and route directly to eFPGA global interconnect. The overall CLB block diagram is shown below. The BLE output feedback paths to the crossbar are not shown in the diagram to preserve diagram clarity. + +![clb_block_diagram](../z1000/docs/CLB4_Block_Diagram.png) + +#### DSP Block + +Each DSP block consists of one configurable arithmetic circuit whose operating modes are suitable for various types of digital signal processing. DSP block modes are selected via bitstream configuration. Users write HDL code that models their desired arithmetic operations and synthesis software infers the correct operating mode of the DSP block. + +A block diagram of the DSP block is shown below. Three data inputs, a clock, and an asynchronous reset signal are provided. All inputs may optionally be re-registered; synthesis software infers when these registers should be used. Two of the three inputs serve primarily as inputs to an 18x18 multiplier; however, they may also be routed to an adder circuit to use the block only for wide addition operations. These two inputs are 18 bits wide. A third 40-bit input is provided to enable fused multiply-add operations. Additional operating modes enable the block to function as an accumulator or a multiply-accumulator. For high-performance DSP, the multiply-accumulator mode may optionally be pipelined; users must model this pipelining in their HDL code to ensure correct inference. + +![dsp_block_diagram](./docs/DSP_Block_Diagram.png ) + +#### BRAM + +Each block BRAM (BRAM) consists of one configurable SRAM circuit. The underlying memory primitive is a 1K x 16 bit true dual port memory macro. Control circuitry surrounding this macro enables emulation of single port RAM and dual port RAM. Emulation of other memory dimensions with the same number of bits is also supported; a complete table of supported memory sizes is shown below. For memory widths wider than 8 bits, byte enables are supported to individually write specific bytes at a given address. + +Word Width | Data Width +---------------------|----------- +512 | 32* +1024 | 16 +2048 | 8 +4096 | 4 +8192 | 2 +16384 | 1 + +*supported in single port mode only + +BRAM modes are selected via bitstream configuration. Users write HDL code that models their desired arithmetic operations and synthesis software infers the correct operating mode of the BRAM. To ensure that the desired BRAM mode is selected, consult synthesis software documentation for HDL style guidelines. + +A block diagram of the BRAM is shown below. The BRAM has dedicated I/O interfaces for two complete SRAM ports. Note that not all signals may be used in all modes. Dedicated signals are provided for clock enable, read enable, write enable, and byte enables in addition to the signaling for clock, address, and data. Depending on HDL coding styles chosen, users may include or exclude clock enable, read enable, and/or byte enables signals from their designs and rely on synthesis software to connect them to constant values that ensure user functionality is preserved. + +![bram_block_diagram](./docs/BRAM_Block_Diagram.png ) + +#### I/O Block (IOB) + +General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the eFPGA and reconfigurable logic. Each IOB contains eight iopad primitives. Each iopad primitive can operate either in input mode or output mode. The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs. During RTL-to-bitstream generation, each top level RTL port directly maps to an iopad primitives via pin constraints. + +The figure below shows a block diagram of the iopad primitive. Each iopad enables a single signal to be connected . The data direction is determined during bitstream generation and stored in a configuration bit that is directly wired to an output enable signal pad_oe that is accessible as a top level signal of the eFPGA. When in input mode, the pad_in signal is received from external logic and passed to eFPGA logic via the inpad signal. Similarly, in output mode the outpad signal is received from eFPGA logic and passed to pad_out. + +![iob_block_diagram](../z1000/docs/IOB_Block_Diagram.png) + +#### Clock I/O Block (Clock IOB) + +A dedicated I/O block is provided that is only used for delivering clocks to the programmable logic. This I/O block is referred to as the clock IOB. It is constructed from the same iopad primitive as the general purpose I/O blocks, but internally connected to the eFPGA clock network rather than to programmable interconnect. + +## Z1010 Pin Constraints + +Z1010 implements the signals in the table below as valid pin names for specifying pin constraints in a JSON pin constraints file (PCF). Standard bus notatation using square brackets is required for all pins in the PCF. For example, to constrain a user input signal `foo` to bit 17 of `gpio_in_east`, the following content should be included in the PCF file + +``` + "foo": { + "direction": "input", + "pin": "gpio_in_east[17]" + }, +``` + +> **_NOTE:_** User clock signals must be mapped to the gpio_in_clk bus + +Pin Name | Direction | MSB | LSB | Purpose +--------------------------|-----------|-----|-----|--------- +gpio_in_clk | input | 3 | 0 | User clocks +gpio_in_south | input | 255 | 0 | South side GPIO inputs +gpio_in_north | input | 255 | 0 | North side GPIO inputs +gpio_in_west | input | 255 | 0 | West side GPIO inputs +gpio_in_east | input | 255 | 0 | East side GPIO inputs +gpio_out_south | output | 255 | 0 | South side GPIO outputs +gpio_oe_south | output | 255 | 0 | South side GPIO output enables +gpio_out_north | output | 255 | 0 | North side GPIO outputs +gpio_oe_north | output | 255 | 0 | North side GPIO output enables +gpio_out_west | output | 255 | 0 | West side GPIO outputs +gpio_oe_west | output | 255 | 0 | West side GPIO output enables +gpio_out_east | output | 255 | 0 | East side GPIO outputs +gpio_oe_east | output | 255 | 0 | East side GPIO output enables + +## Z1010 Bitstream Mapping + +The Z1010 bitstream format is organized into a four-dimensional array of configuration bits. The four dimensions are the VPR grid X coordinate, VPR grid Y coordinate, word address, and bit index. + +The table below shows the minimum and maximum array values for this array. Note that not all positions in the array contain valid configuration bits. + +Index | Min | Max | +------------|------|-----| +X | 0 | 19 | +Y | 0 | 19 | +Address | 0 | 115 | +Bit Index | 0 | 7 | + +The Z1010 bitstream map file specifies a mapping from these array indices to each FASM feature defined in the Z1010 VPR architecture file and routing graph XML file. \ No newline at end of file diff --git a/logiklib/zeroasic/z1010/docs/BRAM_Block_Diagram.png b/logiklib/zeroasic/z1010/docs/BRAM_Block_Diagram.png new file mode 100644 index 0000000..d2bc17e Binary files /dev/null and b/logiklib/zeroasic/z1010/docs/BRAM_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1010/docs/DSP_Block_Diagram.png b/logiklib/zeroasic/z1010/docs/DSP_Block_Diagram.png new file mode 100644 index 0000000..d92389a Binary files /dev/null and b/logiklib/zeroasic/z1010/docs/DSP_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1010/docs/z1010_Block_Diagram.png b/logiklib/zeroasic/z1010/docs/z1010_Block_Diagram.png new file mode 100644 index 0000000..e347b86 Binary files /dev/null and b/logiklib/zeroasic/z1010/docs/z1010_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1010/z1010.json b/logiklib/zeroasic/z1010/z1010.json new file mode 100644 index 0000000..acc950a --- /dev/null +++ b/logiklib/zeroasic/z1010/z1010.json @@ -0,0 +1,32 @@ +{ + "name": "z1010", + "fpga_x_size": 16, + "fpga_y_size": 16, + "num_routing_channels": 100, + "num_clb_inputs": 18, + "lut_size": 4, + "bles_per_clb": 8, + "outputs_per_ble": 1, + "crossbar_size": 15, + "sb_fraction": 0.15, + "logic_fraction": 0.15, + "ios_per_iob": 16, + "num_fracturable_elements": 1, + "ram_address_width": 14, + "ram_data_width": 16, + "ram_byte_size": 8, + "ram_block_width": 2, + "ram_block_height": 4, + "ram_x_spacing": 16, + "ram_y_spacing": 4, + "ram_x_offset": 8, + "ram_y_offset": 2, + "mult_block_width": 1, + "mult_block_height": 4, + "mult_input_width": 18, + "mult_output_width": 40, + "mult_x_spacing": 16, + "mult_y_spacing": 4, + "mult_x_offset": 5, + "mult_y_offset": 2 +} diff --git a/logiklib/zeroasic/z1010/z1010.py b/logiklib/zeroasic/z1010/z1010.py new file mode 100644 index 0000000..231e4ea --- /dev/null +++ b/logiklib/zeroasic/z1010/z1010.py @@ -0,0 +1,131 @@ +# Copyright 2025 Zero ASIC Corporation +# Licensed under the Apache 2.0 License (see LICENSE for details) +# Auto-generated by FPGA Architect + +from logiklib import register_part_data + +from siliconcompiler import FPGA + + +#################################################### +# Setup for z1010 FPGA +#################################################### +def setup(): + + part_name = 'z1010' + + fpga = FPGA(part_name, package='logik-fpga-z1010') + + register_part_data(fpga, part_name, f"logik-fpga-{part_name}") + + fpga.set('fpga', part_name, 'vendor', 'fpga_architect') + + fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1010') + + fpga.set('fpga', part_name, 'lutsize', 4) + fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') + fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') + fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') + fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1010.xml') + fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1010_rr_graph.xml') + fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1010_yosys_config.json') + fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') + fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'cad/tech_bram.v') + fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'cad/bram_memory_map.txt') + fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'cad/tech_dsp.v') + fpga.set('fpga', part_name, 'file', 'yosys_extractlib', 'cad/tech_dsp_extract.v') + fpga.set('fpga', part_name, 'file', 'yosys_macrolib', 'cad/tech_dsp_blackbox.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_registers', + ['dffelr', + 'dffhlr', + 'dffl', + 'dffe', + 'dffhr', + 'dffehlr', + 'dffer', + 'dfflr', + 'dffehl', + 'dff', + 'dffeh', + 'dffel', + 'dffhl', + 'dffr', + 'dffh', + 'dffehr']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_dsps', + ['efpga_acc', + 'efpga_mult_rego', + 'efpga_mult_regio', + 'efpga_mult_addc_regi', + 'efpga_mult_addc_rego', + 'efpga_mult', + 'efpga_adder_rego', + 'efpga_adder', + 'efpga_mult_regi', + 'efpga_acc_regi', + 'efpga_macc_regi', + 'efpga_mult_addc_regio', + 'efpga_adder_regi', + 'efpga_mult_addc', + 'efpga_adder_regio', + 'efpga_macc_pipe_regi', + 'dsp_mult', + 'efpga_macc', + 'efpga_macc_pipe']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_brams', + ['sram_sp', + 'spram_8192x2', + 'spram_2048x8', + 'tdpram_1024x16', + 'sdpram_8192x2', + 'sdpram_2048x8', + 'sdpram_1024x16', + 'spram_1024x16', + 'sdpram_4096x4', + 'spram_16384x1', + 'tdpram_16384x1', + 'sram_tdp', + 'spram_4096x4', + 'sdpram_16384x1', + 'sram_sdp', + 'spram_512x32', + 'tdpram_4096x4', + 'tdpram_2048x8', + 'tdpram_8192x2']) + + # Set the dsp options for the yosys built-in DSP correctly for this + # architecture + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') + + fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') + + fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1010_bitstream_map.json') + + fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1010_constraint_map.json') + + fpga.set('fpga', part_name, 'var', 'channelwidth', 100) + + # Add the liberty files to the fpga part. + fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') + fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib', 'tech_dsp.lib', 'tech_bram.lib']) + + return fpga + + +######################### +if __name__ == "__main__": + fpga = setup() + assert fpga.check_filepaths() + fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/zeroasic/z1012/README.md b/logiklib/zeroasic/z1012/README.md new file mode 100644 index 0000000..6d079cb --- /dev/null +++ b/logiklib/zeroasic/z1012/README.md @@ -0,0 +1,127 @@ +# Z1012 eFPGA + +The Z1012 eFPGA is a fixed-size eFPGA architecture consisting of configurable logic blocks (CLBs), I/O blocks (IOBs), and a clock I/O block for clock distribution. + +## Z1012 Architecture + +A summary of Z1012 resources is shown in the table below + +Resource Type | Count +---------------------|------ +Lookup Tables (LUTs) | 6656 +Registers | 6656 +GPIOs | 2048 +DSPs | 16 +BRAMs (16Kbit) | 16 +Max Clock Domains | 4 + +The Z1012 architecture XML file provides a complete specification of how logic resources are arranged in this grid, the port lists of all logic resources, and how logic resources are organized and connected. Hierarchical representations of logic blocks are provided where needed to enable correct, efficient packing and placement of a user's netlist. The architecture XML also provides a delay model for the eFPGA and FASM feature metadata to enable logic block bitstream generation. The Z1012 routing graph XML file encapsulates a complete model of the eFPGA interconnect architecture and contains the FASM feature metadata for interconnect bitstream generation. + +The following sections summarize the architecture features of Z1012. + +### Array and Grid Model + +Z1012 logic resources are organized into an 34x34 array of components, depicted in the figure below. A 32x32 array of logic blocks is surrounded on the perimeter by four banks of IOBs, one per side of the array. One column of logic blocks is consumed by four DSP blocks. Four block RAMs (BRAMs) consume an additional two columns. Corner array locations are used for programmable interconnect only with the exception of the lower left corner, where a special IOB for delivering clocks is placed. + +![z1012_array_diagram](./docs/z1012_Block_Diagram.png ) + +For modeling in VPR, this array of components is arranged on a 36x36 (X,Y) grid. The lower left corner of Z1012 (the clock IOB) is located at (1,1) on this grid. All locations at X=0, X=19, Y=0, and Y=19 are modeled as empty. This perimeter of empty locations is required to model the architecture in VPR correctly. + +### Logic Resource Types + +Brief descriptions and block diagrams for Z1012 logic resources are shown below. + +#### Configurable Logic Block (CLB) + +Each configurable logic block (CLB) consists of 8 4-input basic logic elements (BLEs). A block diagram of the BLE is shown below. The BLE contains a 4-input lookup table (LUT) a configurable flip-flop, and a multiplexer that selects whether the primary output of the BLE comes from the flip-flop or directly from the LUT. The flip-flop output is also routed out of the BLE as a secondary output; this secondary output is connected only to local interconnect in the CLB. + +![ble_block_diagram](../z1000/docs/BLE4_Block_Diagram.png ) + +The BLEs in a CLB share 18 common inputs through the CLB local interconnect, an array of multiplexers referred to as the CLB crossbar. Each BLE input is driven by a dedicated crossbar multiplexer that selects from a subset of the CLB inputs, BLE primary outputs, and BLE secondary outputs. The CLB inputs are subdivided between north, south, east, and west sides of the CLB to improve their interface to the eFPGA global interconnect. The BLE primary outputs are also outputs of the CLB and route directly to eFPGA global interconnect. The overall CLB block diagram is shown below. The BLE output feedback paths to the crossbar are not shown in the diagram to preserve diagram clarity. + +![clb_block_diagram](../z1000/docs/CLB4_Block_Diagram.png) + +#### DSP Block + +Each DSP block consists of one configurable arithmetic circuit whose operating modes are suitable for various types of digital signal processing. DSP block modes are selected via bitstream configuration. Users write HDL code that models their desired arithmetic operations and synthesis software infers the correct operating mode of the DSP block. + +A block diagram of the DSP block is shown below. Three data inputs, a clock, and an asynchronous reset signal are provided. All inputs may optionally be re-registered; synthesis software infers when these registers should be used. Two of the three inputs serve primarily as inputs to an 18x18 multiplier; however, they may also be routed to an adder circuit to use the block only for wide addition operations. These two inputs are 18 bits wide. A third 40-bit input is provided to enable fused multiply-add operations. Additional operating modes enable the block to function as an accumulator or a multiply-accumulator. For high-performance DSP, the multiply-accumulator mode may optionally be pipelined; users must model this pipelining in their HDL code to ensure correct inference. + +![dsp_block_diagram](../z1010/docs/DSP_Block_Diagram.png ) + +#### BRAM + +Each block BRAM (BRAM) consists of one configurable SRAM circuit. The underlying memory primitive is a 1K x 16 bit true dual port memory macro. Control circuitry surrounding this macro enables emulation of single port RAM and dual port RAM. Emulation of other memory dimensions with the same number of bits is also supported; a complete table of supported memory sizes is shown below. For memory widths wider than 8 bits, byte enables are supported to individually write specific bytes at a given address. + +Word Width | Data Width +---------------------|----------- +512 | 32* +1024 | 16 +2048 | 8 +4096 | 4 +8192 | 2 +16384 | 1 + +*supported in single port mode only + +BRAM modes are selected via bitstream configuration. Users write HDL code that models their desired arithmetic operations and synthesis software infers the correct operating mode of the BRAM. To ensure that the desired BRAM mode is selected, consult synthesis software documentation for HDL style guidelines. + +A block diagram of the BRAM is shown below. The BRAM has dedicated I/O interfaces for two complete SRAM ports. Note that not all signals may be used in all modes. Dedicated signals are provided for clock enable, read enable, write enable, and byte enables in addition to the signaling for clock, address, and data. Depending on HDL coding styles chosen, users may include or exclude clock enable, read enable, and/or byte enables signals from their designs and rely on synthesis software to connect them to constant values that ensure user functionality is preserved. + +![bram_block_diagram](../z1010/docs/BRAM_Block_Diagram.png ) + +#### I/O Block (IOB) + +General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the eFPGA and reconfigurable logic. Each IOB contains eight iopad primitives. Each iopad primitive can operate either in input mode or output mode. The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs. During RTL-to-bitstream generation, each top level RTL port directly maps to an iopad primitives via pin constraints. + +The figure below shows a block diagram of the iopad primitive. Each iopad enables a single signal to be connected . The data direction is determined during bitstream generation and stored in a configuration bit that is directly wired to an output enable signal pad_oe that is accessible as a top level signal of the eFPGA. When in input mode, the pad_in signal is received from external logic and passed to eFPGA logic via the inpad signal. Similarly, in output mode the outpad signal is received from eFPGA logic and passed to pad_out. + +![iob_block_diagram](../z1000/docs/IOB_Block_Diagram.png) + +#### Clock I/O Block (Clock IOB) + +A dedicated I/O block is provided that is only used for delivering clocks to the programmable logic. This I/O block is referred to as the clock IOB. It is constructed from the same iopad primitive as the general purpose I/O blocks, but internally connected to the eFPGA clock network rather than to programmable interconnect. + +## Z1012 Pin Constraints + +Z1012 implements the signals in the table below as valid pin names for specifying pin constraints in a JSON pin constraints file (PCF). Standard bus notatation using square brackets is required for all pins in the PCF. For example, to constrain a user input signal `foo` to bit 17 of `gpio_in_east`, the following content should be included in the PCF file + +``` + "foo": { + "direction": "input", + "pin": "gpio_in_east[17]" + }, +``` + +> **_NOTE:_** User clock signals must be mapped to the gpio_in_clk bus + +Pin Name | Direction | MSB | LSB | Purpose +--------------------------|-----------|-----|-----|--------- +gpio_in_clk | input | 3 | 0 | User clocks +gpio_in_south | input | 511 | 0 | South side GPIO inputs +gpio_in_north | input | 511 | 0 | North side GPIO inputs +gpio_in_west | input | 511 | 0 | West side GPIO inputs +gpio_in_east | input | 511 | 0 | East side GPIO inputs +gpio_out_south | output | 511 | 0 | South side GPIO outputs +gpio_oe_south | output | 511 | 0 | South side GPIO output enables +gpio_out_north | output | 511 | 0 | North side GPIO outputs +gpio_oe_north | output | 511 | 0 | North side GPIO output enables +gpio_out_west | output | 511 | 0 | West side GPIO outputs +gpio_oe_west | output | 511 | 0 | West side GPIO output enables +gpio_out_east | output | 511 | 0 | East side GPIO outputs +gpio_oe_east | output | 511 | 0 | East side GPIO output enables + +## Z1012 Bitstream Mapping + +The Z1012 bitstream format is organized into a four-dimensional array of configuration bits. The four dimensions are the VPR grid X coordinate, VPR grid Y coordinate, word address, and bit index. + +The table below shows the minimum and maximum array values for this array. Note that not all positions in the array contain valid configuration bits. + +Index | Min | Max | +------------|------|-----| +X | 0 | 19 | +Y | 0 | 19 | +Address | 0 | 115 | +Bit Index | 0 | 7 | + +The Z1012 bitstream map file specifies a mapping from these array indices to each FASM feature defined in the Z1012 VPR architecture file and routing graph XML file. \ No newline at end of file diff --git a/logiklib/zeroasic/z1012/docs/z1012_Block_Diagram.png b/logiklib/zeroasic/z1012/docs/z1012_Block_Diagram.png new file mode 100644 index 0000000..71dcfd7 Binary files /dev/null and b/logiklib/zeroasic/z1012/docs/z1012_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1012/z1012.json b/logiklib/zeroasic/z1012/z1012.json new file mode 100644 index 0000000..43125ac --- /dev/null +++ b/logiklib/zeroasic/z1012/z1012.json @@ -0,0 +1,32 @@ +{ + "name": "z1012", + "fpga_x_size": 32, + "fpga_y_size": 32, + "num_routing_channels": 150, + "num_clb_inputs": 18, + "lut_size": 4, + "bles_per_clb": 8, + "outputs_per_ble": 1, + "crossbar_size": 15, + "sb_fraction": 0.15, + "logic_fraction": 0.15, + "ios_per_iob": 16, + "num_fracturable_elements": 1, + "ram_address_width": 14, + "ram_data_width": 16, + "ram_byte_size": 8, + "ram_block_width": 2, + "ram_block_height": 4, + "ram_x_spacing": 16, + "ram_y_spacing": 4, + "ram_x_offset": 8, + "ram_y_offset": 2, + "mult_block_width": 1, + "mult_block_height": 4, + "mult_input_width": 18, + "mult_output_width": 40, + "mult_x_spacing": 16, + "mult_y_spacing": 4, + "mult_x_offset": 5, + "mult_y_offset": 2 +} diff --git a/logiklib/zeroasic/z1012/z1012.py b/logiklib/zeroasic/z1012/z1012.py new file mode 100644 index 0000000..353cacb --- /dev/null +++ b/logiklib/zeroasic/z1012/z1012.py @@ -0,0 +1,131 @@ +# Copyright 2025 Zero ASIC Corporation +# Licensed under the Apache 2.0 License (see LICENSE for details) +# Auto-generated by FPGA Architect + +from logiklib import register_part_data + +from siliconcompiler import FPGA + + +#################################################### +# Setup for z1012 FPGA +#################################################### +def setup(): + + part_name = 'z1012' + + fpga = FPGA(part_name, package='logik-fpga-z1012') + + register_part_data(fpga, part_name, f"logik-fpga-{part_name}") + + fpga.set('fpga', part_name, 'vendor', 'fpga_architect') + + fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1012') + + fpga.set('fpga', part_name, 'lutsize', 4) + fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') + fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') + fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') + fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1012.xml') + fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1012_rr_graph.xml') + fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1012_yosys_config.json') + fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') + fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'cad/tech_bram.v') + fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'cad/bram_memory_map.txt') + fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'cad/tech_dsp.v') + fpga.set('fpga', part_name, 'file', 'yosys_extractlib', 'cad/tech_dsp_extract.v') + fpga.set('fpga', part_name, 'file', 'yosys_macrolib', 'cad/tech_dsp_blackbox.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_registers', + ['dffhl', + 'dffer', + 'dffhr', + 'dfflr', + 'dffeh', + 'dffh', + 'dffhlr', + 'dffehlr', + 'dffl', + 'dffel', + 'dffe', + 'dff', + 'dffehl', + 'dffehr', + 'dffr', + 'dffelr']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_dsps', + ['efpga_adder_regio', + 'efpga_adder_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_adder', + 'efpga_mult_addc_regio', + 'efpga_macc_pipe_regi', + 'efpga_acc', + 'efpga_acc_regi', + 'efpga_macc_pipe', + 'efpga_macc', + 'efpga_mult_addc_rego', + 'dsp_mult', + 'efpga_mult_addc_regi', + 'efpga_mult_regio', + 'efpga_mult_regi', + 'efpga_adder_rego', + 'efpga_mult_rego', + 'efpga_mult_addc']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_brams', + ['spram_16384x1', + 'sram_sp', + 'tdpram_16384x1', + 'tdpram_2048x8', + 'spram_8192x2', + 'spram_512x32', + 'sdpram_8192x2', + 'sdpram_4096x4', + 'spram_4096x4', + 'tdpram_8192x2', + 'tdpram_1024x16', + 'sdpram_1024x16', + 'sdpram_16384x1', + 'tdpram_4096x4', + 'spram_1024x16', + 'sram_tdp', + 'sdpram_2048x8', + 'spram_2048x8', + 'sram_sdp']) + + # Set the dsp options for the yosys built-in DSP correctly for this + # architecture + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') + + fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') + + fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1012_bitstream_map.json') + + fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1012_constraint_map.json') + + fpga.set('fpga', part_name, 'var', 'channelwidth', 100) + + # Add the liberty files to the fpga part. + fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') + fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib', 'tech_dsp.lib', 'tech_bram.lib']) + + return fpga + + +######################### +if __name__ == "__main__": + fpga = setup() + assert fpga.check_filepaths() + fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/zeroasic/z1060/README.md b/logiklib/zeroasic/z1060/README.md new file mode 100644 index 0000000..4611232 --- /dev/null +++ b/logiklib/zeroasic/z1060/README.md @@ -0,0 +1,127 @@ +# Z1060 eFPGA + +The Z1060 eFPGA is a fixed-size eFPGA architecture consisting of configurable logic blocks (CLBs), I/O blocks (IOBs), and a clock I/O block for clock distribution. + +## Z1060 Architecture + +A summary of Z1060 resources is shown in the table below + +Resource Type | Count +---------------------|------ +Lookup Tables (LUTs) | 1664 +Registers | 1664 +GPIOs | 1024 +DSPs | 4 +BRAMs (16Kbit) | 4 +Max Clock Domains | 4 + +The Z1060 architecture XML file provides a complete specification of how logic resources are arranged in this grid, the port lists of all logic resources, and how logic resources are organized and connected. Hierarchical representations of logic blocks are provided where needed to enable correct, efficient packing and placement of a user's netlist. The architecture XML also provides a delay model for the eFPGA and FASM feature metadata to enable logic block bitstream generation. The Z1060 routing graph XML file encapsulates a complete model of the eFPGA interconnect architecture and contains the FASM feature metadata for interconnect bitstream generation. + +The following sections summarize the architecture features of Z1060. + +### Array and Grid Model + +Z1060 logic resources are organized into an 18x18 array of components, depicted in the figure below. A 16x16 array of logic blocks is surrounded on the perimeter by four banks of IOBs, one per side of the array. One column of logic blocks is consumed by four DSP blocks. Four block RAMs (BRAMs) consume an additional two columns. Corner array locations are used for programmable interconnect only with the exception of the lower left corner, where a special IOB for delivering clocks is placed. + +![z1060_array_diagram](./docs/z1060_Block_Diagram.png ) + +For modeling in VPR, this array of components is arranged on a 20x20 (X,Y) grid. The lower left corner of Z1060 (the clock IOB) is located at (1,1) on this grid. All locations at X=0, X=19, Y=0, and Y=19 are modeled as empty. This perimeter of empty locations is required to model the architecture in VPR correctly. + +### Logic Resource Types + +Brief descriptions and block diagrams for Z1060 logic resources are shown below. + +#### Configurable Logic Block (CLB) + +Each configurable logic block (CLB) consists of 8 6-input basic logic elements (BLEs). A block diagram of the BLE is shown below. The BLE contains a 6-input lookup table (LUT) a configurable flip-flop, and a multiplexer that selects whether the primary output of the BLE comes from the flip-flop or directly from the LUT. The flip-flop output is also routed out of the BLE as a secondary output; this secondary output is connected only to local interconnect in the CLB. + +![ble_block_diagram](../z1060/docs/BLE6_Block_Diagram.png ) + +The BLEs in a CLB share 24 common inputs through the CLB local interconnect, an array of multiplexers referred to as the CLB crossbar. Each BLE input is driven by a dedicated crossbar multiplexer that selects from a subset of the CLB inputs, BLE primary outputs, and BLE secondary outputs. The CLB inputs are subdivided between north, south, east, and west sides of the CLB to improve their interface to the eFPGA global interconnect. The BLE primary outputs are also outputs of the CLB and route directly to eFPGA global interconnect. The overall CLB block diagram is shown below. The BLE output feedback paths to the crossbar are not shown in the diagram to preserve diagram clarity. + +![clb_block_diagram](./docs/CLB6_Block_Diagram.png) + +#### DSP Block + +Each DSP block consists of one configurable arithmetic circuit whose operating modes are suitable for various types of digital signal processing. DSP block modes are selected via bitstream configuration. Users write HDL code that models their desired arithmetic operations and synthesis software infers the correct operating mode of the DSP block. + +A block diagram of the DSP block is shown below. Three data inputs, a clock, and an asynchronous reset signal are provided. All inputs may optionally be re-registered; synthesis software infers when these registers should be used. Two of the three inputs serve primarily as inputs to an 18x18 multiplier; however, they may also be routed to an adder circuit to use the block only for wide addition operations. These two inputs are 18 bits wide. A third 40-bit input is provided to enable fused multiply-add operations. Additional operating modes enable the block to function as an accumulator or a multiply-accumulator. For high-performance DSP, the multiply-accumulator mode may optionally be pipelined; users must model this pipelining in their HDL code to ensure correct inference. + +![dsp_block_diagram](../z1010/docs/DSP_Block_Diagram.png ) + +#### BRAM + +Each block BRAM (BRAM) consists of one configurable SRAM circuit. The underlying memory primitive is a 1K x 16 bit true dual port memory macro. Control circuitry surrounding this macro enables emulation of single port RAM and dual port RAM. Emulation of other memory dimensions with the same number of bits is also supported; a complete table of supported memory sizes is shown below. For memory widths wider than 8 bits, byte enables are supported to individually write specific bytes at a given address. + +Word Width | Data Width +---------------------|----------- +512 | 32* +1024 | 16 +2048 | 8 +4096 | 4 +8192 | 2 +16384 | 1 + +*supported in single port mode only + +BRAM modes are selected via bitstream configuration. Users write HDL code that models their desired arithmetic operations and synthesis software infers the correct operating mode of the BRAM. To ensure that the desired BRAM mode is selected, consult synthesis software documentation for HDL style guidelines. + +A block diagram of the BRAM is shown below. The BRAM has dedicated I/O interfaces for two complete SRAM ports. Note that not all signals may be used in all modes. Dedicated signals are provided for clock enable, read enable, write enable, and byte enables in addition to the signaling for clock, address, and data. Depending on HDL coding styles chosen, users may include or exclude clock enable, read enable, and/or byte enables signals from their designs and rely on synthesis software to connect them to constant values that ensure user functionality is preserved. + +![bram_block_diagram](../z1010/docs/BRAM_Block_Diagram.png ) + +#### I/O Block (IOB) + +General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the eFPGA and reconfigurable logic. Each IOB contains eight iopad primitives. Each iopad primitive can operate either in input mode or output mode. The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs. During RTL-to-bitstream generation, each top level RTL port directly maps to an iopad primitives via pin constraints. + +The figure below shows a block diagram of the iopad primitive. Each iopad enables a single signal to be connected . The data direction is determined during bitstream generation and stored in a configuration bit that is directly wired to an output enable signal pad_oe that is accessible as a top level signal of the eFPGA. When in input mode, the pad_in signal is received from external logic and passed to eFPGA logic via the inpad signal. Similarly, in output mode the outpad signal is received from eFPGA logic and passed to pad_out. + +![iob_block_diagram](../z1000/docs/IOB_Block_Diagram.png) + +#### Clock I/O Block (Clock IOB) + +A dedicated I/O block is provided that is only used for delivering clocks to the programmable logic. This I/O block is referred to as the clock IOB. It is constructed from the same iopad primitive as the general purpose I/O blocks, but internally connected to the eFPGA clock network rather than to programmable interconnect. + +## Z1060 Pin Constraints + +Z1060 implements the signals in the table below as valid pin names for specifying pin constraints in a JSON pin constraints file (PCF). Standard bus notatation using square brackets is required for all pins in the PCF. For example, to constrain a user input signal `foo` to bit 17 of `gpio_in_east`, the following content should be included in the PCF file + +``` + "foo": { + "direction": "input", + "pin": "gpio_in_east[17]" + }, +``` + +> **_NOTE:_** User clock signals must be mapped to the gpio_in_clk bus + +Pin Name | Direction | MSB | LSB | Purpose +--------------------------|-----------|-----|-----|--------- +gpio_in_clk | input | 3 | 0 | User clocks +gpio_in_south | input | 255 | 0 | South side GPIO inputs +gpio_in_north | input | 255 | 0 | North side GPIO inputs +gpio_in_west | input | 255 | 0 | West side GPIO inputs +gpio_in_east | input | 255 | 0 | East side GPIO inputs +gpio_out_south | output | 255 | 0 | South side GPIO outputs +gpio_oe_south | output | 255 | 0 | South side GPIO output enables +gpio_out_north | output | 255 | 0 | North side GPIO outputs +gpio_oe_north | output | 255 | 0 | North side GPIO output enables +gpio_out_west | output | 255 | 0 | West side GPIO outputs +gpio_oe_west | output | 255 | 0 | West side GPIO output enables +gpio_out_east | output | 255 | 0 | East side GPIO outputs +gpio_oe_east | output | 255 | 0 | East side GPIO output enables + +## Z1060 Bitstream Mapping + +The Z1060 bitstream format is organized into a four-dimensional array of configuration bits. The four dimensions are the VPR grid X coordinate, VPR grid Y coordinate, word address, and bit index. + +The table below shows the minimum and maximum array values for this array. Note that not all positions in the array contain valid configuration bits. + +Index | Min | Max | +------------|------|-----| +X | 0 | 19 | +Y | 0 | 19 | +Address | 0 | 176 | +Bit Index | 0 | 7 | + +The Z1060 bitstream map file specifies a mapping from these array indices to each FASM feature defined in the Z1060 VPR architecture file and routing graph XML file. diff --git a/logiklib/zeroasic/z1060/docs/BLE6_Block_Diagram.png b/logiklib/zeroasic/z1060/docs/BLE6_Block_Diagram.png new file mode 100644 index 0000000..179a57e Binary files /dev/null and b/logiklib/zeroasic/z1060/docs/BLE6_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1060/docs/BRAM_Block_Diagram.png b/logiklib/zeroasic/z1060/docs/BRAM_Block_Diagram.png new file mode 100644 index 0000000..b58adab Binary files /dev/null and b/logiklib/zeroasic/z1060/docs/BRAM_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1060/docs/CLB6_Block_Diagram.png b/logiklib/zeroasic/z1060/docs/CLB6_Block_Diagram.png new file mode 100644 index 0000000..23d634b Binary files /dev/null and b/logiklib/zeroasic/z1060/docs/CLB6_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1060/docs/DSP_Block_Diagram.png b/logiklib/zeroasic/z1060/docs/DSP_Block_Diagram.png new file mode 100644 index 0000000..d92389a Binary files /dev/null and b/logiklib/zeroasic/z1060/docs/DSP_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1060/docs/z1060_Block_Diagram.png b/logiklib/zeroasic/z1060/docs/z1060_Block_Diagram.png new file mode 100644 index 0000000..58bf1a6 Binary files /dev/null and b/logiklib/zeroasic/z1060/docs/z1060_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1060/z1060.json b/logiklib/zeroasic/z1060/z1060.json new file mode 100644 index 0000000..47df7a7 --- /dev/null +++ b/logiklib/zeroasic/z1060/z1060.json @@ -0,0 +1,32 @@ +{ + "name": "z1060", + "fpga_x_size": 16, + "fpga_y_size": 16, + "num_routing_channels": 100, + "num_clb_inputs": 24, + "lut_size": 6, + "bles_per_clb": 8, + "outputs_per_ble": 1, + "crossbar_size": 23, + "sb_fraction": 0.15, + "logic_fraction": 0.15, + "ios_per_iob": 16, + "num_fracturable_elements": 1, + "ram_address_width": 14, + "ram_data_width": 16, + "ram_byte_size": 8, + "ram_block_width": 2, + "ram_block_height": 4, + "ram_x_spacing": 16, + "ram_y_spacing": 4, + "ram_x_offset": 8, + "ram_y_offset": 2, + "mult_block_width": 1, + "mult_block_height": 4, + "mult_input_width": 18, + "mult_output_width": 40, + "mult_x_spacing": 16, + "mult_y_spacing": 4, + "mult_x_offset": 5, + "mult_y_offset": 2 +} diff --git a/logiklib/zeroasic/z1060/z1060.py b/logiklib/zeroasic/z1060/z1060.py new file mode 100644 index 0000000..0972e2b --- /dev/null +++ b/logiklib/zeroasic/z1060/z1060.py @@ -0,0 +1,131 @@ +# Copyright 2025 Zero ASIC Corporation +# Licensed under the Apache 2.0 License (see LICENSE for details) +# Auto-generated by FPGA Architect + +from logiklib import register_part_data + +from siliconcompiler import FPGA + + +#################################################### +# Setup for z1060 FPGA +#################################################### +def setup(): + + part_name = 'z1060' + + fpga = FPGA(part_name, package='logik-fpga-z1060') + + register_part_data(fpga, part_name, f"logik-fpga-{part_name}") + + fpga.set('fpga', part_name, 'vendor', 'fpga_architect') + + fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1060') + + fpga.set('fpga', part_name, 'lutsize', 6) + fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') + fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') + fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') + fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1060.xml') + fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1060_rr_graph.xml') + fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1060_yosys_config.json') + fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') + fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'cad/tech_bram.v') + fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'cad/bram_memory_map.txt') + fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'cad/tech_dsp.v') + fpga.set('fpga', part_name, 'file', 'yosys_extractlib', 'cad/tech_dsp_extract.v') + fpga.set('fpga', part_name, 'file', 'yosys_macrolib', 'cad/tech_dsp_blackbox.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_registers', + ['dffe', + 'dffeh', + 'dffr', + 'dffelr', + 'dffh', + 'dffehr', + 'dfflr', + 'dffer', + 'dffhr', + 'dffhlr', + 'dffel', + 'dff', + 'dffhl', + 'dffl', + 'dffehlr', + 'dffehl']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_dsps', + ['dsp_mult', + 'efpga_mult_regi', + 'efpga_mult_rego', + 'efpga_adder_regio', + 'efpga_macc_regi', + 'efpga_macc_pipe_regi', + 'efpga_adder_rego', + 'efpga_mult_addc_regi', + 'efpga_adder_regi', + 'efpga_macc', + 'efpga_acc_regi', + 'efpga_acc', + 'efpga_mult_addc_rego', + 'efpga_mult_addc_regio', + 'efpga_macc_pipe', + 'efpga_mult', + 'efpga_adder', + 'efpga_mult_regio', + 'efpga_mult_addc']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_brams', + ['sdpram_2048x8', + 'sram_tdp', + 'spram_512x32', + 'tdpram_8192x2', + 'tdpram_2048x8', + 'tdpram_16384x1', + 'tdpram_1024x16', + 'sdpram_8192x2', + 'spram_1024x16', + 'tdpram_4096x4', + 'spram_8192x2', + 'sdpram_16384x1', + 'sdpram_1024x16', + 'spram_4096x4', + 'spram_16384x1', + 'sram_sp', + 'spram_2048x8', + 'sdpram_4096x4', + 'sram_sdp']) + + # Set the dsp options for the yosys built-in DSP correctly for this + # architecture + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') + + fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') + + fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1060_bitstream_map.json') + + fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1060_constraint_map.json') + + fpga.set('fpga', part_name, 'var', 'channelwidth', 100) + + # Add the liberty files to the fpga part. + fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') + fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib', 'tech_dsp.lib', 'tech_bram.lib']) + + return fpga + + +######################### +if __name__ == "__main__": + fpga = setup() + assert fpga.check_filepaths() + fpga.write_manifest(f'{fpga.design}.json') diff --git a/logiklib/zeroasic/z1062/README.md b/logiklib/zeroasic/z1062/README.md new file mode 100644 index 0000000..c742b44 --- /dev/null +++ b/logiklib/zeroasic/z1062/README.md @@ -0,0 +1,127 @@ +# Z1062 eFPGA + +The Z1062 eFPGA is a fixed-size eFPGA architecture consisting of configurable logic blocks (CLBs), I/O blocks (IOBs), and a clock I/O block for clock distribution. + +## Z1062 Architecture + +A summary of Z1062 resources is shown in the table below + +Resource Type | Count +---------------------|------ +Lookup Tables (LUTs) | 6656 +Registers | 6656 +GPIOs | 2048 +DSPs | 16 +BRAMs (16Kbit) | 16 +Max Clock Domains | 4 + +The Z1062 architecture XML file provides a complete specification of how logic resources are arranged in this grid, the port lists of all logic resources, and how logic resources are organized and connected. Hierarchical representations of logic blocks are provided where needed to enable correct, efficient packing and placement of a user's netlist. The architecture XML also provides a delay model for the eFPGA and FASM feature metadata to enable logic block bitstream generation. The Z1062 routing graph XML file encapsulates a complete model of the eFPGA interconnect architecture and contains the FASM feature metadata for interconnect bitstream generation. + +The following sections summarize the architecture features of Z1062. + +### Array and Grid Model + +Z1062 logic resources are organized into an 34x34 array of components, depicted in the figure below. A 32x32 array of logic blocks is surrounded on the perimeter by four banks of IOBs, one per side of the array. One column of logic blocks is consumed by four DSP blocks. Four block RAMs (BRAMs) consume an additional two columns. Corner array locations are used for programmable interconnect only with the exception of the lower left corner, where a special IOB for delivering clocks is placed. + +![z1062_array_diagram](./docs/z1062_Block_Diagram.png ) + +For modeling in VPR, this array of components is arranged on a 36x36 (X,Y) grid. The lower left corner of Z1062 (the clock IOB) is located at (1,1) on this grid. All locations at X=0, X=19, Y=0, and Y=19 are modeled as empty. This perimeter of empty locations is required to model the architecture in VPR correctly. + +### Logic Resource Types + +Brief descriptions and block diagrams for Z1062 logic resources are shown below. + +#### Configurable Logic Block (CLB) + +Each configurable logic block (CLB) consists of 8 6-input basic logic elements (BLEs). A block diagram of the BLE is shown below. The BLE contains a 6-input lookup table (LUT) a configurable flip-flop, and a multiplexer that selects whether the primary output of the BLE comes from the flip-flop or directly from the LUT. The flip-flop output is also routed out of the BLE as a secondary output; this secondary output is connected only to local interconnect in the CLB. + +![ble_block_diagram](../z1060/docs/BLE6_Block_Diagram.png ) + +The BLEs in a CLB share 24 common inputs through the CLB local interconnect, an array of multiplexers referred to as the CLB crossbar. Each BLE input is driven by a dedicated crossbar multiplexer that selects from a subset of the CLB inputs, BLE primary outputs, and BLE secondary outputs. The CLB inputs are subdivided between north, south, east, and west sides of the CLB to improve their interface to the eFPGA global interconnect. The BLE primary outputs are also outputs of the CLB and route directly to eFPGA global interconnect. The overall CLB block diagram is shown below. The BLE output feedback paths to the crossbar are not shown in the diagram to preserve diagram clarity. + +![clb_block_diagram](../z1060/docs/CLB6_Block_Diagram.png) + +#### DSP Block + +Each DSP block consists of one configurable arithmetic circuit whose operating modes are suitable for various types of digital signal processing. DSP block modes are selected via bitstream configuration. Users write HDL code that models their desired arithmetic operations and synthesis software infers the correct operating mode of the DSP block. + +A block diagram of the DSP block is shown below. Three data inputs, a clock, and an asynchronous reset signal are provided. All inputs may optionally be re-registered; synthesis software infers when these registers should be used. Two of the three inputs serve primarily as inputs to an 18x18 multiplier; however, they may also be routed to an adder circuit to use the block only for wide addition operations. These two inputs are 18 bits wide. A third 40-bit input is provided to enable fused multiply-add operations. Additional operating modes enable the block to function as an accumulator or a multiply-accumulator. For high-performance DSP, the multiply-accumulator mode may optionally be pipelined; users must model this pipelining in their HDL code to ensure correct inference. + +![dsp_block_diagram](../z1010/docs/DSP_Block_Diagram.png ) + +#### BRAM + +Each block BRAM (BRAM) consists of one configurable SRAM circuit. The underlying memory primitive is a 1K x 16 bit true dual port memory macro. Control circuitry surrounding this macro enables emulation of single port RAM and dual port RAM. Emulation of other memory dimensions with the same number of bits is also supported; a complete table of supported memory sizes is shown below. For memory widths wider than 8 bits, byte enables are supported to individually write specific bytes at a given address. + +Word Width | Data Width +---------------------|----------- +512 | 32* +1024 | 16 +2048 | 8 +4096 | 4 +8192 | 2 +16384 | 1 + +*supported in single port mode only + +BRAM modes are selected via bitstream configuration. Users write HDL code that models their desired arithmetic operations and synthesis software infers the correct operating mode of the BRAM. To ensure that the desired BRAM mode is selected, consult synthesis software documentation for HDL style guidelines. + +A block diagram of the BRAM is shown below. The BRAM has dedicated I/O interfaces for two complete SRAM ports. Note that not all signals may be used in all modes. Dedicated signals are provided for clock enable, read enable, write enable, and byte enables in addition to the signaling for clock, address, and data. Depending on HDL coding styles chosen, users may include or exclude clock enable, read enable, and/or byte enables signals from their designs and rely on synthesis software to connect them to constant values that ensure user functionality is preserved. + +![bram_block_diagram](../z1010/docs/BRAM_Block_Diagram.png ) + +#### I/O Block (IOB) + +General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the eFPGA and reconfigurable logic. Each IOB contains eight iopad primitives. Each iopad primitive can operate either in input mode or output mode. The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs. During RTL-to-bitstream generation, each top level RTL port directly maps to an iopad primitives via pin constraints. + +The figure below shows a block diagram of the iopad primitive. Each iopad enables a single signal to be connected . The data direction is determined during bitstream generation and stored in a configuration bit that is directly wired to an output enable signal pad_oe that is accessible as a top level signal of the eFPGA. When in input mode, the pad_in signal is received from external logic and passed to eFPGA logic via the inpad signal. Similarly, in output mode the outpad signal is received from eFPGA logic and passed to pad_out. + +![iob_block_diagram](../z1000/docs/IOB_Block_Diagram.png) + +#### Clock I/O Block (Clock IOB) + +A dedicated I/O block is provided that is only used for delivering clocks to the programmable logic. This I/O block is referred to as the clock IOB. It is constructed from the same iopad primitive as the general purpose I/O blocks, but internally connected to the eFPGA clock network rather than to programmable interconnect. + +## Z1062 Pin Constraints + +Z1062 implements the signals in the table below as valid pin names for specifying pin constraints in a JSON pin constraints file (PCF). Standard bus notatation using square brackets is required for all pins in the PCF. For example, to constrain a user input signal `foo` to bit 17 of `gpio_in_east`, the following content should be included in the PCF file + +``` + "foo": { + "direction": "input", + "pin": "gpio_in_east[17]" + }, +``` + +> **_NOTE:_** User clock signals must be mapped to the gpio_in_clk bus + +Pin Name | Direction | MSB | LSB | Purpose +--------------------------|-----------|-----|-----|--------- +gpio_in_clk | input | 3 | 0 | User clocks +gpio_in_south | input | 511 | 0 | South side GPIO inputs +gpio_in_north | input | 511 | 0 | North side GPIO inputs +gpio_in_west | input | 511 | 0 | West side GPIO inputs +gpio_in_east | input | 511 | 0 | East side GPIO inputs +gpio_out_south | output | 511 | 0 | South side GPIO outputs +gpio_oe_south | output | 511 | 0 | South side GPIO output enables +gpio_out_north | output | 511 | 0 | North side GPIO outputs +gpio_oe_north | output | 511 | 0 | North side GPIO output enables +gpio_out_west | output | 511 | 0 | West side GPIO outputs +gpio_oe_west | output | 511 | 0 | West side GPIO output enables +gpio_out_east | output | 511 | 0 | East side GPIO outputs +gpio_oe_east | output | 511 | 0 | East side GPIO output enables + +## Z1062 Bitstream Mapping + +The Z1062 bitstream format is organized into a four-dimensional array of configuration bits. The four dimensions are the VPR grid X coordinate, VPR grid Y coordinate, word address, and bit index. + +The table below shows the minimum and maximum array values for this array. Note that not all positions in the array contain valid configuration bits. + +Index | Min | Max | +------------|------|-----| +X | 0 | 19 | +Y | 0 | 19 | +Address | 0 | 207 | +Bit Index | 0 | 7 | + +The Z1062 bitstream map file specifies a mapping from these array indices to each FASM feature defined in the Z1062 VPR architecture file and routing graph XML file. \ No newline at end of file diff --git a/logiklib/zeroasic/z1062/docs/z1062_Block_Diagram.png b/logiklib/zeroasic/z1062/docs/z1062_Block_Diagram.png new file mode 100644 index 0000000..8183122 Binary files /dev/null and b/logiklib/zeroasic/z1062/docs/z1062_Block_Diagram.png differ diff --git a/logiklib/zeroasic/z1062/z1062.json b/logiklib/zeroasic/z1062/z1062.json new file mode 100644 index 0000000..11cbd2b --- /dev/null +++ b/logiklib/zeroasic/z1062/z1062.json @@ -0,0 +1,32 @@ +{ + "name": "z1062", + "fpga_x_size": 32, + "fpga_y_size": 32, + "num_routing_channels": 150, + "num_clb_inputs": 24, + "lut_size": 6, + "bles_per_clb": 8, + "outputs_per_ble": 1, + "crossbar_size": 23, + "sb_fraction": 0.15, + "logic_fraction": 0.15, + "ios_per_iob": 16, + "num_fracturable_elements": 1, + "ram_address_width": 14, + "ram_data_width": 16, + "ram_byte_size": 8, + "ram_block_width": 2, + "ram_block_height": 4, + "ram_x_spacing": 16, + "ram_y_spacing": 4, + "ram_x_offset": 8, + "ram_y_offset": 2, + "mult_block_width": 1, + "mult_block_height": 4, + "mult_input_width": 18, + "mult_output_width": 40, + "mult_x_spacing": 16, + "mult_y_spacing": 4, + "mult_x_offset": 5, + "mult_y_offset": 2 +} diff --git a/logiklib/zeroasic/z1062/z1062.py b/logiklib/zeroasic/z1062/z1062.py new file mode 100644 index 0000000..d471fc8 --- /dev/null +++ b/logiklib/zeroasic/z1062/z1062.py @@ -0,0 +1,131 @@ +# Copyright 2025 Zero ASIC Corporation +# Licensed under the Apache 2.0 License (see LICENSE for details) +# Auto-generated by FPGA Architect + +from logiklib import register_part_data + +from siliconcompiler import FPGA + + +#################################################### +# Setup for z1062 FPGA +#################################################### +def setup(): + + part_name = 'z1062' + + fpga = FPGA(part_name, package='logik-fpga-z1062') + + register_part_data(fpga, part_name, f"logik-fpga-{part_name}") + + fpga.set('fpga', part_name, 'vendor', 'fpga_architect') + + fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'z1062') + + fpga.set('fpga', part_name, 'lutsize', 6) + fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset') + fpga.add('fpga', part_name, 'var', 'feature_set', 'enable') + fpga.add('fpga', part_name, 'var', 'vpr_clock_model', 'route') + fpga.set('fpga', part_name, 'file', 'archfile', 'cad/z1062.xml') + fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/z1062_rr_graph.xml') + fpga.set('fpga', part_name, 'file', 'yosys_fpga_config', 'cad/z1062_yosys_config.json') + fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'cad/tech_flops.v') + fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'cad/tech_bram.v') + fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'cad/bram_memory_map.txt') + fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'cad/tech_dsp.v') + fpga.set('fpga', part_name, 'file', 'yosys_extractlib', 'cad/tech_dsp_extract.v') + fpga.set('fpga', part_name, 'file', 'yosys_macrolib', 'cad/tech_dsp_blackbox.v') + + # Define the macros that can be techmapped to based on the modes + # that exist in the design + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_registers', + ['dffehlr', + 'dffer', + 'dffhlr', + 'dffel', + 'dffhl', + 'dffl', + 'dff', + 'dffeh', + 'dffr', + 'dffh', + 'dffhr', + 'dfflr', + 'dffehr', + 'dffelr', + 'dffe', + 'dffehl']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_dsps', + ['efpga_mult_regi', + 'efpga_adder_regi', + 'efpga_macc_pipe_regi', + 'efpga_macc_pipe', + 'efpga_adder', + 'efpga_macc', + 'efpga_mult_regio', + 'efpga_mult_addc', + 'efpga_mult_addc_regio', + 'efpga_adder_regio', + 'efpga_mult_addc_regi', + 'efpga_macc_regi', + 'efpga_mult', + 'efpga_acc_regi', + 'efpga_mult_rego', + 'dsp_mult', + 'efpga_adder_rego', + 'efpga_mult_addc_rego', + 'efpga_acc']) + + for tool in ('vpr', 'yosys'): + fpga.set('fpga', part_name, 'var', f'{tool}_brams', + ['tdpram_2048x8', + 'spram_1024x16', + 'spram_4096x4', + 'spram_16384x1', + 'tdpram_4096x4', + 'spram_2048x8', + 'sdpram_2048x8', + 'sram_sp', + 'tdpram_1024x16', + 'tdpram_8192x2', + 'sdpram_8192x2', + 'sdpram_16384x1', + 'spram_512x32', + 'spram_8192x2', + 'sram_tdp', + 'tdpram_16384x1', + 'sdpram_1024x16', + 'sram_sdp', + 'sdpram_4096x4']) + + # Set the dsp options for the yosys built-in DSP correctly for this + # architecture + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2') + fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_') + + fpga.add('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS') + + fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/z1062_bitstream_map.json') + + fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/z1062_constraint_map.json') + + fpga.set('fpga', part_name, 'var', 'channelwidth', 150) + + # Add the liberty files to the fpga part. + fpga.set('fpga', part_name, 'file', 'vtr_primitives_lib', 'vtr_primitives.lib') + fpga.set('fpga', part_name, 'file', 'fpga_macros_libs', ['tech_flops.lib', 'tech_dsp.lib', 'tech_bram.lib']) + + return fpga + + +######################### +if __name__ == "__main__": + fpga = setup() + assert fpga.check_filepaths() + fpga.write_manifest(f'{fpga.design}.json') diff --git a/tests/test_fpga_modules.py b/tests/test_fpga_modules.py index 0a07280..e3c5a78 100644 --- a/tests/test_fpga_modules.py +++ b/tests/test_fpga_modules.py @@ -9,13 +9,23 @@ from logiklib.demo.K6_N8_12x12_BD import K6_N8_12x12_BD from logiklib.demo.K6_N8_28x28_BD import K6_N8_28x28_BD from logiklib.zeroasic.z1000 import z1000 +from logiklib.zeroasic.z1002 import z1002 +from logiklib.zeroasic.z1010 import z1010 +from logiklib.zeroasic.z1012 import z1012 +from logiklib.zeroasic.z1060 import z1060 +from logiklib.zeroasic.z1062 import z1062 all_modules = (K6_N8_3x3, K4_N8_6x6, K6_N8_12x12_BD, K6_N8_28x28_BD, - z1000) + z1000, + z1002, + z1010, + z1012, + z1060, + z1062) def test_all_modules():