From 3af54e69bb08320ab9f1e9e3d8cdc9070f3c437b Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Thu, 27 Mar 2025 22:03:17 +0000 Subject: [PATCH] Renamed erroneous variable name --- .../graph/transforms/verilog/test_synthesize_mxint_vivado.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/passes/graph/transforms/verilog/test_synthesize_mxint_vivado.py b/test/passes/graph/transforms/verilog/test_synthesize_mxint_vivado.py index c6e200b55..33fd8700b 100644 --- a/test/passes/graph/transforms/verilog/test_synthesize_mxint_vivado.py +++ b/test/passes/graph/transforms/verilog/test_synthesize_mxint_vivado.py @@ -79,7 +79,7 @@ def get_params(trial): f"{block_size=}, {batch_parallelism=}, {params['e_width']=}, {params['m_width']=}, {params['batches']=}" ) - mg, mlp = shared_emit_verilog_mxint(mlp, input_shape, params, simulate=False) + mg, mlp = shared_emit_verilog_mxint(mlp, input_shape, params, sim=False) return params, mg, mlp