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<!DOCTYPE html>
<html lang="en">
<head>
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    <title>Suyash Vardhan Singh</title>
    <link rel="stylesheet" href="styles.css">
</head>
<body>

<header>
    <img class="profile-img" src="IMG-0702.JPG" alt="Portrait of Suyash Vardhan Singh">
    <h1>Suyash Vardhan Singh</h1>
    <p>
        Columbia, SC 29210 |
        <a href="mailto:ss121@email.sc.edu">ss121@email.sc.edu</a> |
        <a href="https://www.linkedin.com/in/svsingh11/" target="_blank">LinkedIn</a> |
        <a href="tel:+17142130102">+1-714-213-0102</a>
    </p>
</header>

<nav>
    <a href="#intro">Introduction</a>
    <a href="#skills">Technical Skills</a>
    <a href="#education">Education</a>
    <a href="#experience">Experience</a>
    <a href="#publications">Publications</a>
     <div class="dropdown">
        <a href="javascript:void(0)" class="dropbtn">Posters ▼</a>
        <div class="dropdown-content">
            <a href="posters/FPGA_poster_feb.pdf" target="_blank">FPGA '25 Poster</a>
        </div>
    </div>
</nav>

<main>

    <section id="intro">
        <h2>Introduction</h2>
        <p>
            I am a Ph.D. student in Computer Engineering at the University of South Carolina. My research focuses on FPGA-based machine learning acceleration and digital system design.
            I hold a Master's in Computer Engineering from California State University, Fullerton, and a Bachelor's in Electronics and Communications from IET Lucknow.
            My research interests include hardware architectures for Real-Time Machine Learning.
        </p>
    </section>

    <section id="skills">
        <h2>Technical Skills</h2>
        <ul>
            <li><strong>Programming:</strong> Verilog, SystemVerilog, C, Python, MATLAB, HSpice</li>
            <li><strong>Concepts:</strong> Digital Design, SoC Design, FPGA, HLS, Computer Architecture, Static Timing Analysis</li>
            <li><strong>Tools:</strong> Synopsys VCS, Mentor Graphics ModelSim, Xilinx Vivado, Vitis, Synopsys Design Compiler, QuestaSim, LTSpice</li>
        </ul>
    </section>

    <section id="education">
        <h2>Education</h2>
        <ul>
            <li><strong>Ph.D. in Computer Engineering</strong>, University of South Carolina, Columbia, SC (Jan 2022 – Present)</li>
            <li><strong>M.S. in Computer Engineering</strong>, California State University, Fullerton, CA (May 2019)</li>
            <li><strong>B.Tech. in Electronics and Communications</strong>, IET Lucknow, India (June 2017)</li>
        </ul>
    </section>

    <section id="experience">
        <h2>Experience</h2>
        <ul>
            <li><strong>Research Assistant/Teaching Assistant, University of South Carolina</strong> (Jan 2022 – Present)</li>
            <li>Developed an ILP-based optimizer for efficient resource scheduling in deploying machine learning models onto FPGA.
                <a href="https://github.com/HeRCLab/N-TORC" target="_blank">GitHub: N-TORC</a></li>
            <li>Designed and implemented an LSTM accelerator in HLS on Xilinx ZCU104 for real-time machine learning applications.</li>
            <li>Assisted in CSCE 611 (Advanced Digital Design) labs, guiding students in designing a 3-stage pipelined RISC-V processor and writing assembly programs.</li>

            <li><strong>Design Engineer Intern, Pacific Microchip Corp</strong> (Mar 2020 – Apr 2020)</li>
            <li>Worked with Simulink models for fixed-point processing, including FFT.</li>
            <li>Developed custom RTL from Simulink models and created scripts to automate RTL generation.</li>
            <li>Implemented and tested RTL components on FPGA for verification.</li>

            <li><strong>RTL Design Intern, HDLexpress</strong> (Jul 2019 – Jan 2020)</li>
            <li>Designed RTL for a read-only instruction cache controller in SystemVerilog.</li>
            <li>Debugged and optimized cache controller design; provided weekly reports to the supervisor.</li>
        </ul>
    </section>

    <section id="publications">
        <h2>Publications</h2>
        <div class="card">
    <strong>Resource Scheduling for Real-Time Machine Learning</strong><br/>
    <em>Suyash V. Singh, Iftakhar Ahmad, David Andrews, Miaoqing Huang, Austin Downey, Jason D. Bakos</em><br/>
    <em>ACM/SIGDA International Symposium on FPGA (FPGA 2025), Monterey, CA, USA, Feb. 2025</em><br/>
    <a href="https://doi.org/10.1145/3706628.3708848" target="_blank">DOI: 10.1145/3706628.3708848</a>
</div>

<div class="card">
    <strong>N-TORC: Native Tensor Optimizer for Real-time Constraints</strong><br/>
    <em>Suyash V. Singh, Iftakhar Ahmad, David Andrews, Miaoqing Huang, Austin Downey, Jason D. Bakos</em><br/>
    <em>IEEE 33rd FCCM, May 2025</em><br/>
    <a href="https://doi.org/10.1109/FCCM62733.2025.00061" target="_blank">DOI: 10.1109/FCCM62733.2025.00061</a>
</div>

<div class="card">
    <strong>A Decomposition-Based Memristive Crossbar Solver and FPGA-Accelerated Hardware Implementation</strong><br/>
    <em>Suyash V. Singh, A. Kolinko, MH. Amin, R. Zand, J. Bakos</em><br/>
    <em>Great Lakes Symposium on VLSI (GLSVLSI 2025)</em><br/>
    <a href="https://doi.org/10.1145/3716368.3735282" target="_blank">DOI: 10.1145/3716368.3735282</a>
</div>

<div class="card">
    <strong>Switchable Single/Dual Edge Registers for Pipeline Architecture</strong><br/>
    <em>Suyash V. Singh, R. Mahto</em><br/>
    <em>ITNG, Apr. 2019</em><br/>
    <a href="https://doi.org/10.1007/978-3-030-14070-0_79" target="_blank">DOI: 10.1007/978-3-030-14070-0_79</a>
</div>

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