diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_dma.c b/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_dma.c
deleted file mode 100644
index ac2a89c..0000000
--- a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_dma.c
+++ /dev/null
@@ -1,412 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_ll_dma.c
- * @author MCD Application Team
- * @brief DMA LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_ll_dma.h"
-#include "stm32f0xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F0xx_LL_Driver
- * @{
- */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup DMA_LL_Private_Macros
- * @{
- */
-#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
-
-#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
- ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
-
-#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
- ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
-
-#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
- ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
-
-#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
-
-#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
-
-#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-
-#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
-#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \
- ((__VALUE__) == LL_DMA_REQUEST_1) || \
- ((__VALUE__) == LL_DMA_REQUEST_2) || \
- ((__VALUE__) == LL_DMA_REQUEST_3) || \
- ((__VALUE__) == LL_DMA_REQUEST_4) || \
- ((__VALUE__) == LL_DMA_REQUEST_5) || \
- ((__VALUE__) == LL_DMA_REQUEST_6) || \
- ((__VALUE__) == LL_DMA_REQUEST_7) || \
- ((__VALUE__) == LL_DMA_REQUEST_8) || \
- ((__VALUE__) == LL_DMA_REQUEST_9) || \
- ((__VALUE__) == LL_DMA_REQUEST_10) || \
- ((__VALUE__) == LL_DMA_REQUEST_11) || \
- ((__VALUE__) == LL_DMA_REQUEST_12) || \
- ((__VALUE__) == LL_DMA_REQUEST_13) || \
- ((__VALUE__) == LL_DMA_REQUEST_14) || \
- ((__VALUE__) == LL_DMA_REQUEST_15))
-#endif
-
-#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
- ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
- ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
- ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
-
-#if defined (DMA2)
-#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
- (((INSTANCE) == DMA2) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
- (((INSTANCE) == DMA2) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5))))
-#endif
-#else
-#if defined(DMA1_Channel6) && defined(DMA1_Channel7)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#elif defined (DMA1_Channel6)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6))))
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5))))
-#endif /* DMA1_Channel6 && DMA1_Channel7 */
-#endif
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the DMA registers to their default reset values.
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6 (*)
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- *
- * (*) value not defined in all devices
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DMA registers are de-initialized
- * - ERROR: DMA registers are not de-initialized
- */
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
- ErrorStatus status = SUCCESS;
-
- /* Check the DMA Instance DMAx and Channel parameters*/
- assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
- tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
-
- /* Disable the selected DMAx_Channely */
- CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
-
- /* Reset DMAx_Channely control register */
- LL_DMA_WriteReg(tmp, CCR, 0U);
-
- /* Reset DMAx_Channely remaining bytes register */
- LL_DMA_WriteReg(tmp, CNDTR, 0U);
-
- /* Reset DMAx_Channely peripheral address register */
- LL_DMA_WriteReg(tmp, CPAR, 0U);
-
- /* Reset DMAx_Channely memory address register */
- LL_DMA_WriteReg(tmp, CMAR, 0U);
-
-#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
- /* Reset Request register field for DMAx Channel */
- LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
-#endif
-
- if (Channel == LL_DMA_CHANNEL_1)
- {
- /* Reset interrupt pending bits for DMAx Channel1 */
- LL_DMA_ClearFlag_GI1(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_2)
- {
- /* Reset interrupt pending bits for DMAx Channel2 */
- LL_DMA_ClearFlag_GI2(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_3)
- {
- /* Reset interrupt pending bits for DMAx Channel3 */
- LL_DMA_ClearFlag_GI3(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_4)
- {
- /* Reset interrupt pending bits for DMAx Channel4 */
- LL_DMA_ClearFlag_GI4(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_5)
- {
- /* Reset interrupt pending bits for DMAx Channel5 */
- LL_DMA_ClearFlag_GI5(DMAx);
- }
-
-#if defined(DMA1_Channel6)
- else if (Channel == LL_DMA_CHANNEL_6)
- {
- /* Reset interrupt pending bits for DMAx Channel6 */
- LL_DMA_ClearFlag_GI6(DMAx);
- }
-#endif
-#if defined(DMA1_Channel7)
- else if (Channel == LL_DMA_CHANNEL_7)
- {
- /* Reset interrupt pending bits for DMAx Channel7 */
- LL_DMA_ClearFlag_GI7(DMAx);
- }
-#endif
- else
- {
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
- * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
- * @arg @ref __LL_DMA_GET_INSTANCE
- * @arg @ref __LL_DMA_GET_CHANNEL
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6 (*)
- * @arg @ref LL_DMA_CHANNEL_7 (*)
- *
- * (*) value not defined in all devices
- * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DMA registers are initialized
- * - ERROR: Not applicable
- */
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
-{
- /* Check the DMA Instance DMAx and Channel parameters*/
- assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
- /* Check the DMA parameters from DMA_InitStruct */
- assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
- assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
- assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
- assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
- assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
- assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
- assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
-#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
- assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
-#endif
- assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
-
- /*---------------------------- DMAx CCR Configuration ------------------------
- * Configure DMAx_Channely: data transfer direction, data transfer mode,
- * peripheral and memory increment mode,
- * data size alignment and priority level with parameters :
- * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
- * - Mode: DMA_CCR_CIRC bit
- * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
- * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
- * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
- * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
- * - Priority: DMA_CCR_PL[1:0] bits
- */
- LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
- DMA_InitStruct->Mode | \
- DMA_InitStruct->PeriphOrM2MSrcIncMode | \
- DMA_InitStruct->MemoryOrM2MDstIncMode | \
- DMA_InitStruct->PeriphOrM2MSrcDataSize | \
- DMA_InitStruct->MemoryOrM2MDstDataSize | \
- DMA_InitStruct->Priority);
-
- /*-------------------------- DMAx CMAR Configuration -------------------------
- * Configure the memory or destination base address with parameter :
- * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
- */
- LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
-
- /*-------------------------- DMAx CPAR Configuration -------------------------
- * Configure the peripheral or source base address with parameter :
- * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
- */
- LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
-
- /*--------------------------- DMAx CNDTR Configuration -----------------------
- * Configure the peripheral base address with parameter :
- * - NbData: DMA_CNDTR_NDT[15:0] bits
- */
- LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
-
-#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
- /*--------------------------- DMAx CSELR Configuration -----------------------
- * Configure the DMA request for DMA instance on Channel x with parameter :
- * - PeriphRequest: DMA_CSELR[31:0] bits
- */
- LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
-#endif
-
- return SUCCESS;
-}
-
-/**
- * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
- * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
- * @retval None
- */
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
-{
- /* Set DMA_InitStruct fields to default values */
- DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
- DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
- DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
- DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
- DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
- DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
- DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
- DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
- DMA_InitStruct->NbData = 0x00000000U;
-#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
- DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
-#endif
- DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMA1 || DMA2 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_exti.c b/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_exti.c
deleted file mode 100644
index d9e4253..0000000
--- a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_exti.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_ll_exti.c
- * @author MCD Application Team
- * @brief EXTI LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_ll_exti.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F0xx_LL_Driver
- * @{
- */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
-
-#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
- || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
- || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
-
-
-#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup EXTI_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the EXTI registers to their default reset values.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: EXTI registers are de-initialized
- * - ERROR: not applicable
- */
-uint32_t LL_EXTI_DeInit(void)
-{
- /* Interrupt mask register set to default reset values */
-#if defined(STM32F030x6) || defined(STM32F031x6) ||defined(STM32F038xx)
- LL_EXTI_WriteReg(IMR, 0x0FF40000U);
-#elif defined(STM32F070x6) || defined(STM32F042x6) || defined(STM32F048xx)
- LL_EXTI_WriteReg(IMR, 0x7FF40000U);
-#elif defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
- LL_EXTI_WriteReg(IMR, 0x0F940000U);
-#else
- LL_EXTI_WriteReg(IMR, 0x7F840000U);
-#endif
- /* Event mask register set to default reset values */
- LL_EXTI_WriteReg(EMR, 0x00000000U);
- /* Rising Trigger selection register set to default reset values */
- LL_EXTI_WriteReg(RTSR, 0x00000000U);
- /* Falling Trigger selection register set to default reset values */
- LL_EXTI_WriteReg(FTSR, 0x00000000U);
- /* Software interrupt event register set to default reset values */
- LL_EXTI_WriteReg(SWIER, 0x00000000U);
- /* Pending register clear */
- LL_EXTI_WriteReg(PR, 0x007BFFFFU);
-
- return SUCCESS;
-}
-
-/**
- * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
- * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: EXTI registers are initialized
- * - ERROR: not applicable
- */
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
- ErrorStatus status = SUCCESS;
- /* Check the parameters */
- assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
- assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
-
- /* ENABLE LineCommand */
- if (EXTI_InitStruct->LineCommand != DISABLE)
- {
- assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
-
- /* Configure EXTI Lines in range from 0 to 31 */
- if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
- {
- switch (EXTI_InitStruct->Mode)
- {
- case LL_EXTI_MODE_IT:
- /* First Disable Event on provided Lines */
- LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable IT on provided Lines */
- LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_MODE_EVENT:
- /* First Disable IT on provided Lines */
- LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Event on provided Lines */
- LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_MODE_IT_EVENT:
- /* Directly Enable IT & Event on provided Lines */
- LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
- break;
- default:
- status = ERROR;
- break;
- }
- if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
- {
- switch (EXTI_InitStruct->Trigger)
- {
- case LL_EXTI_TRIGGER_RISING:
- /* First Disable Falling Trigger on provided Lines */
- LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Rising Trigger on provided Lines */
- LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_TRIGGER_FALLING:
- /* First Disable Rising Trigger on provided Lines */
- LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Falling Trigger on provided Lines */
- LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_TRIGGER_RISING_FALLING:
- LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- default:
- status = ERROR;
- break;
- }
- }
- }
- }
- /* DISABLE LineCommand */
- else
- {
- /* De-configure EXTI Lines in range from 0 to 31 */
- LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
- * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
- * @retval None
- */
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
- EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
- EXTI_InitStruct->LineCommand = DISABLE;
- EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
- EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (EXTI) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_gpio.c b/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_gpio.c
deleted file mode 100644
index 3fae50c..0000000
--- a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_gpio.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_ll_gpio.c
- * @author MCD Application Team
- * @brief GPIO LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_ll_gpio.h"
-#include "stm32f0xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F0xx_LL_Driver
- * @{
- */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
-
-/** @addtogroup GPIO_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Private_Macros
- * @{
- */
-#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
-
-#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
- ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
- ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
- ((__VALUE__) == LL_GPIO_MODE_ANALOG))
-
-#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
- ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
-
-#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
- ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
- ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
-
-#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
- ((__VALUE__) == LL_GPIO_PULL_UP) ||\
- ((__VALUE__) == LL_GPIO_PULL_DOWN))
-
-#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
- ((__VALUE__) == LL_GPIO_AF_1 ) ||\
- ((__VALUE__) == LL_GPIO_AF_2 ) ||\
- ((__VALUE__) == LL_GPIO_AF_3 ) ||\
- ((__VALUE__) == LL_GPIO_AF_4 ) ||\
- ((__VALUE__) == LL_GPIO_AF_5 ) ||\
- ((__VALUE__) == LL_GPIO_AF_6 ) ||\
- ((__VALUE__) == LL_GPIO_AF_7 ))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIO_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize GPIO registers (Registers restored to their default values).
- * @param GPIOx GPIO Port
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: GPIO registers are de-initialized
- * - ERROR: Wrong GPIO Port
- */
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
- /* Force and Release reset on clock of GPIOx Port */
- if (GPIOx == GPIOA)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
- }
- else if (GPIOx == GPIOB)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
- }
- else if (GPIOx == GPIOC)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
- }
-#if defined(GPIOD)
- else if (GPIOx == GPIOD)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
- }
-#endif /* GPIOD */
-#if defined(GPIOE)
- else if (GPIOx == GPIOE)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
- }
-#endif /* GPIOE */
-#if defined(GPIOF)
- else if (GPIOx == GPIOF)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
- }
-#endif /* GPIOF */
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
- * @param GPIOx GPIO Port
- * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
- * that contains the configuration information for the specified GPIO peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
- * - ERROR: Not applicable
- */
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00000000U;
- uint32_t currentpin = 0x00000000U;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
- assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
- assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
-
- /* ------------------------- Configure the port pins ---------------- */
- /* Initialize pinpos on first pin set */
- /* pinpos = 0; useless as already done in default initialization */
-
- /* Configure the port pins */
- while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
- {
- /* Get current io position */
- currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
-
- if (currentpin)
- {
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Speed mode parameters */
- assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
-
- /* Speed mode configuration */
- LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
- }
-
- /* Pull-up Pull down resistor configuration*/
- LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
-
- if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
- {
- /* Check Alternate parameter */
- assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
-
- /* Speed mode configuration */
- if (currentpin < LL_GPIO_PIN_8)
- {
- LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
- }
- else
- {
- LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
- }
- }
- }
- pinpos++;
- }
-
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Output mode parameters */
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
-
- }
- return (SUCCESS);
-}
-
-/**
- * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
- * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
- GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
- GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
- GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
- GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_pwr.c b/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_pwr.c
deleted file mode 100644
index b4bf665..0000000
--- a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_pwr.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_ll_pwr.c
- * @author MCD Application Team
- * @brief PWR LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_ll_pwr.h"
-#include "stm32f0xx_ll_bus.h"
-
-/** @addtogroup STM32F0xx_LL_Driver
- * @{
- */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup PWR_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the PWR registers to their default reset values.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: PWR registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_PWR_DeInit(void)
-{
- /* Force reset of PWR clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
-
- /* Release reset of PWR clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
-
- return SUCCESS;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined(PWR) */
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_rcc.c b/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_rcc.c
deleted file mode 100644
index 6a244fd..0000000
--- a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_rcc.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_ll_rcc.c
- * @author MCD Application Team
- * @brief RCC LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_ll_rcc.h"
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-/** @addtogroup STM32F0xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_LL_Private_Macros
- * @{
- */
-#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
-#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
-#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
-#else
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
-#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
-
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
-
-#if defined(USB)
-#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
-#endif /* USB */
-
-#if defined(CEC)
-#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
-#endif /* CEC */
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_LL_Private_Functions RCC Private functions
- * @{
- */
-uint32_t RCC_GetSystemClockFreq(void);
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief Reset the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE and PLL OFF
- * - AHB and APB1 prescaler set to 1.
- * - CSS, MCO OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RCC registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_RCC_DeInit(void)
-{
- uint32_t vl_mask = 0U;
-
- /* Set HSION bit */
- LL_RCC_HSI_Enable();
-
- /* Set HSITRIM bits to the reset value*/
- LL_RCC_HSI_SetCalibTrimming(0x10U);
-
- /* Reset SW, HPRE, PPRE and MCOSEL bits */
- vl_mask = 0xFFFFFFFFU;
- CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL));
- LL_RCC_WriteReg(CFGR, vl_mask);
-
- /* Reset HSEON, CSSON, PLLON bits */
- vl_mask = 0xFFFFFFFFU;
- CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
- LL_RCC_WriteReg(CR, vl_mask);
-
- /* Reset HSEBYP bit */
- LL_RCC_HSE_DisableBypass();
-
- /* Reset CFGR register */
- LL_RCC_WriteReg(CFGR, 0x00000000U);
-
-#if defined(RCC_HSI48_SUPPORT)
- /* Reset CR2 register */
- LL_RCC_WriteReg(CR2, 0x00000000U);
-
- /* Disable HSI48 */
- LL_RCC_HSI48_Disable();
-
-#endif /*RCC_HSI48_SUPPORT*/
- /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/
- LL_RCC_HSI14_SetCalibTrimming(0x10U);
- LL_RCC_HSI14_Disable();
- LL_RCC_HSI14_EnableADCControl();
-
- /* Reset CFGR2 register */
- LL_RCC_WriteReg(CFGR2, 0x00000000U);
-
- /* Reset CFGR3 register */
- LL_RCC_WriteReg(CFGR3, 0x00000000U);
-
- /* Clear pending flags */
-#if defined(RCC_HSI48_SUPPORT)
- vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC);
-#else
- vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC);
-#endif /* RCC_HSI48_SUPPORT */
- SET_BIT(RCC->CIR, vl_mask);
-
- /* Disable all interrupts */
- LL_RCC_WriteReg(CIR, 0x00000000U);
-
- return SUCCESS;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_LL_EF_Get_Freq
- * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
- * and different peripheral clocks available on the device.
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
- * @note If SYSCLK source is PLL, function returns values based on
- * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
- * @note (**) HSI_VALUE is a defined constant but the real value may vary
- * depending on the variations in voltage and temperature.
- * @note (***) HSE_VALUE is a defined constant, user has to ensure that
- * HSE_VALUE is same as the real frequency of the crystal used.
- * Otherwise, this function may have wrong result.
- * @note The result of this function could be incorrect when using fractional
- * value for HSE crystal.
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- * @{
- */
-
-/**
- * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
- * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function
- * must be called to update structure fields. Otherwise, any
- * configuration based on this function will be incorrect.
- * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
- * @retval None
- */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
-{
- /* Get SYSCLK frequency */
- RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
-
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
-
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
-}
-
-/**
- * @brief Return USARTx clock frequency
- * @param USARTxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USART1_CLKSOURCE
- * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
- *
- * (*) value not defined in all devices.
- * @retval USART clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
- */
-uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
-{
- uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
-#if defined(RCC_CFGR3_USART1SW)
- if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
- {
- /* USART1CLK clock frequency */
- switch (LL_RCC_GetUSARTClockSource(USARTxSource))
- {
- case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
- usart_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady())
- {
- usart_frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady())
- {
- usart_frequency = LSE_VALUE;
- }
- break;
-
- case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
- default:
- usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- break;
- }
- }
-#endif /* RCC_CFGR3_USART1SW */
-
-#if defined(RCC_CFGR3_USART2SW)
- if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
- {
- /* USART2CLK clock frequency */
- switch (LL_RCC_GetUSARTClockSource(USARTxSource))
- {
- case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
- usart_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady())
- {
- usart_frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady())
- {
- usart_frequency = LSE_VALUE;
- }
- break;
-
- case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
- default:
- usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- break;
- }
- }
-#endif /* RCC_CFGR3_USART2SW */
-
-#if defined(RCC_CFGR3_USART3SW)
- if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
- {
- /* USART3CLK clock frequency */
- switch (LL_RCC_GetUSARTClockSource(USARTxSource))
- {
- case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
- usart_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady())
- {
- usart_frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady())
- {
- usart_frequency = LSE_VALUE;
- }
- break;
-
- case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
- default:
- usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- break;
- }
- }
-
-#endif /* RCC_CFGR3_USART3SW */
- return usart_frequency;
-}
-
-/**
- * @brief Return I2Cx clock frequency
- * @param I2CxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2C1_CLKSOURCE
- * @retval I2C clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
- */
-uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
-{
- uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
-
- /* I2C1 CLK clock frequency */
- if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
- {
- switch (LL_RCC_GetI2CClockSource(I2CxSource))
- {
- case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
- i2c_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
- default:
- if (LL_RCC_HSI_IsReady())
- {
- i2c_frequency = HSI_VALUE;
- }
- break;
- }
- }
-
- return i2c_frequency;
-}
-
-#if defined(USB)
-/**
- * @brief Return USBx clock frequency
- * @param USBxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE
- * @retval USB clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
- */
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
-{
- uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
-
- /* USBCLK clock frequency */
- switch (LL_RCC_GetUSBClockSource(USBxSource))
- {
- case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- break;
-
-#if defined(RCC_CFGR3_USBSW_HSI48)
- case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
- default:
- if (LL_RCC_HSI48_IsReady())
- {
- usb_frequency = HSI48_VALUE;
- }
- break;
-#else
- case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
- default:
- usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
- break;
-#endif /* RCC_CFGR3_USBSW_HSI48 */
- }
-
- return usb_frequency;
-}
-#endif /* USB */
-
-#if defined(CEC)
-/**
- * @brief Return CECx clock frequency
- * @param CECxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_CEC_CLKSOURCE
- * @retval CEC clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
- */
-uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
-{
- uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
-
- /* CECCLK clock frequency */
- switch (LL_RCC_GetCECClockSource(CECxSource))
- {
- case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
- if (LL_RCC_HSI_IsReady())
- {
- cec_frequency = HSI_VALUE / 244U;
- }
- break;
-
- case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
- default:
- if (LL_RCC_LSE_IsReady())
- {
- cec_frequency = LSE_VALUE;
- }
- break;
- }
-
- return cec_frequency;
-}
-#endif /* CEC */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_LL_Private_Functions
- * @{
- */
-
-/**
- * @brief Return SYSTEM clock frequency
- * @retval SYSTEM clock frequency (in Hz)
- */
-uint32_t RCC_GetSystemClockFreq(void)
-{
- uint32_t frequency = 0U;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (LL_RCC_GetSysClkSource())
- {
- case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- frequency = HSI_VALUE;
- break;
-
- case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- frequency = HSE_VALUE;
- break;
-
- case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
- frequency = RCC_PLL_GetFreqDomain_SYS();
- break;
-
-#if defined(RCC_HSI48_SUPPORT)
- case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */
- frequency = HSI48_VALUE;
- break;
-#endif /* RCC_HSI48_SUPPORT */
-
- default:
- frequency = HSI_VALUE;
- break;
- }
-
- return frequency;
-}
-
-/**
- * @brief Return HCLK clock frequency
- * @param SYSCLK_Frequency SYSCLK clock frequency
- * @retval HCLK clock frequency (in Hz)
- */
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
-{
- /* HCLK clock frequency */
- return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
-}
-
-/**
- * @brief Return PCLK1 clock frequency
- * @param HCLK_Frequency HCLK clock frequency
- * @retval PCLK1 clock frequency (in Hz)
- */
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
-{
- /* PCLK1 clock frequency */
- return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
-}
-/**
- * @brief Return PLL clock frequency used for system domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLL_GetFreqDomain_SYS(void)
-{
- uint32_t pllinputfreq = 0U, pllsource = 0U;
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
-
- /* Get PLL source */
- pllsource = LL_RCC_PLL_GetMainSource();
-
- switch (pllsource)
- {
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- pllinputfreq = HSI_VALUE;
-#else
- case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
- pllinputfreq = HSI_VALUE / 2U;
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
- break;
-
-#if defined(RCC_HSI48_SUPPORT)
- case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */
- pllinputfreq = HSI48_VALUE;
- break;
-#endif /* RCC_HSI48_SUPPORT */
-
- case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllinputfreq = HSE_VALUE;
- break;
-
- default:
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- pllinputfreq = HSI_VALUE;
-#else
- pllinputfreq = HSI_VALUE / 2U;
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
- break;
- }
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
-#else
- return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_spi.c b/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_spi.c
deleted file mode 100644
index 3005490..0000000
--- a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_spi.c
+++ /dev/null
@@ -1,545 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_ll_spi.c
- * @author MCD Application Team
- * @brief SPI LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_ll_spi.h"
-#include "stm32f0xx_ll_bus.h"
-#include "stm32f0xx_ll_rcc.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F0xx_LL_Driver
- * @{
- */
-
-#if defined (SPI1) || defined (SPI2)
-
-/** @addtogroup SPI_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Constants SPI Private Constants
- * @{
- */
-/* SPI registers Masks */
-#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
- SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
- SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
- SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
- SPI_CR1_BIDIMODE)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Macros SPI Private Macros
- * @{
- */
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
- || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
-
-#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
- || ((__VALUE__) == LL_SPI_MODE_SLAVE))
-
-#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
-
-#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
- || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
-
-#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
- || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-
-#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
-
-#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
- || ((__VALUE__) == LL_SPI_MSB_FIRST))
-
-#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
- || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
-
-#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the SPI registers to their default reset values.
- * @param SPIx SPI Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are de-initialized
- * - ERROR: SPI registers are not de-initialized
- */
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-#if defined(SPI1)
- if (SPIx == SPI1)
- {
- /* Force reset of SPI clock */
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SPI1);
-
- /* Release reset of SPI clock */
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SPI1);
-
- status = SUCCESS;
- }
-#endif /* SPI1 */
-#if defined(SPI2)
- if (SPIx == SPI2)
- {
- /* Force reset of SPI clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
-
- /* Release reset of SPI clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
-
- status = SUCCESS;
- }
-#endif /* SPI2 */
-
- return status;
-}
-
-/**
- * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param SPIx SPI Instance
- * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
- * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
- */
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the SPI Instance SPIx*/
- assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
- /* Check the SPI parameters from SPI_InitStruct*/
- assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
- assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
- assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
- assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
- assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
- assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
- assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
- assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
- assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
-
- if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
- {
- /*---------------------------- SPIx CR1 Configuration ------------------------
- * Configure SPIx CR1 with parameters:
- * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
- * - Master/Slave Mode: SPI_CR1_MSTR bit
- * - ClockPolarity: SPI_CR1_CPOL bit
- * - ClockPhase: SPI_CR1_CPHA bit
- * - NSS management: SPI_CR1_SSM bit
- * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
- * - BitOrder: SPI_CR1_LSBFIRST bit
- * - CRCCalculation: SPI_CR1_CRCEN bit
- */
- MODIFY_REG(SPIx->CR1,
- SPI_CR1_CLEAR_MASK,
- SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
- SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
- SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
- SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
-
- /*---------------------------- SPIx CR2 Configuration ------------------------
- * Configure SPIx CR2 with parameters:
- * - DataWidth: DS[3:0] bits
- * - NSS management: SSOE bit
- */
- MODIFY_REG(SPIx->CR2,
- SPI_CR2_DS | SPI_CR2_SSOE,
- SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
-
- /*---------------------------- SPIx CRCPR Configuration ----------------------
- * Configure SPIx CRCPR with parameters:
- * - CRCPoly: CRCPOLY[15:0] bits
- */
- if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
- {
- assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
- LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
- }
- status = SUCCESS;
- }
-
-#if defined (SPI_I2S_SUPPORT)
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2S_SUPPORT */
- return status;
-}
-
-/**
- * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
- * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
-{
- /* Set SPI_InitStruct fields to default values */
- SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
- SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
- SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
- SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
- SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
- SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
- SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
- SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
- SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
- SPI_InitStruct->CRCPoly = 7U;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup I2S_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Constants I2S Private Constants
- * @{
- */
-/* I2S registers Masks */
-#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
- SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
- SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
-
-#define I2S_I2SPR_CLEAR_MASK 0x0002U
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Macros I2S Private Macros
- * @{
- */
-
-#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
-
-#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
- || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-
-#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
- || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-
-#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
- || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
-
-#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
- || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
- && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
- || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
-
-#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
- || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2S_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the SPI/I2S registers to their default reset values.
- * @param SPIx SPI Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are de-initialized
- * - ERROR: SPI registers are not de-initialized
- */
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
-{
- return LL_SPI_DeInit(SPIx);
-}
-
-/**
- * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param SPIx SPI Instance
- * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are Initialized
- * - ERROR: SPI registers are not Initialized
- */
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
-{
- uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U;
- LL_RCC_ClocksTypeDef rcc_clocks;
- uint32_t sourceclock = 0U;
- ErrorStatus status = ERROR;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(SPIx));
- assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
- assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
- assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
- assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
- assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
- assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
-
- if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
- {
- /*---------------------------- SPIx I2SCFGR Configuration --------------------
- * Configure SPIx I2SCFGR with parameters:
- * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
- * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
- * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
- * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
- */
-
- /* Write to SPIx I2SCFGR */
- MODIFY_REG(SPIx->I2SCFGR,
- I2S_I2SCFGR_CLEAR_MASK,
- I2S_InitStruct->Mode | I2S_InitStruct->Standard |
- I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
- SPI_I2SCFGR_I2SMOD);
-
- /*---------------------------- SPIx I2SPR Configuration ----------------------
- * Configure SPIx I2SPR with parameters:
- * - MCLKOutput: SPI_I2SPR_MCKOE bit
- * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
- */
-
- /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
- * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
- */
- if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
- {
- /* Check the frame length (For the Prescaler computing)
- * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
- */
- if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
- {
- /* Packet length is 32 bits */
- packetlength = 2U;
- }
-
- /* I2S Clock source is System clock: Get System Clock frequency */
- LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-
- /* Get the source clock value: based on System Clock value */
- sourceclock = rcc_clocks.SYSCLK_Frequency;
-
- /* Compute the Real divider depending on the MCLK output state with a floating point */
- if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
- }
-
- /* Remove the floating point */
- tmp = tmp / 10U;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t)(i2sodd << 8U);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
- {
- /* Set the default values */
- i2sdiv = 2U;
- i2sodd = 0U;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
-
- status = SUCCESS;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
- * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
-{
- /*--------------- Reset I2S init structure parameters values -----------------*/
- I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
- I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
- I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
- I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
- I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
- I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
-}
-
-/**
- * @brief Set linear and parity prescaler.
- * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
- * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
- * @param SPIx SPI Instance
- * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
- * @param PrescalerParity This parameter can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- * @retval None
- */
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
-{
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(SPIx));
- assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
- assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
-
- /* Write to SPIx I2SPR */
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_tim.c b/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_tim.c
deleted file mode 100644
index fa745e1..0000000
--- a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_tim.c
+++ /dev/null
@@ -1,1175 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_ll_tim.c
- * @author MCD Application Team
- * @brief TIM LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_ll_tim.h"
-#include "stm32f0xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F0xx_LL_Driver
- * @{
- */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
-
-/** @addtogroup TIM_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup TIM_LL_Private_Macros
- * @{
- */
-#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
-
-#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
-
-#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
- || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
-
-#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
- || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
-
-#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
- || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
-
-#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
- || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
-
-#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
-
-#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
-
-#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
-
-#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
-
-#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
-
-#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
-
-#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
-
-#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
-
-#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
-
-#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
- || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
-
-#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
-
-#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
- || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup TIM_LL_Private_Functions TIM Private Functions
- * @{
- */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup TIM_LL_EF_Init
- * @{
- */
-
-/**
- * @brief Set TIMx registers to their reset values.
- * @param TIMx Timer instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: invalid TIMx instance
- */
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
-{
- ErrorStatus result = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(TIMx));
-
- if (TIMx == TIM1)
- {
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM1);
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM1);
- }
-#if defined (TIM2)
- else if (TIMx == TIM2)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
- }
-#endif
-#if defined(TIM3)
- else if (TIMx == TIM3)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
- }
-#endif
-#if defined(TIM5)
- else if (TIMx == TIM5)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
- }
-#endif
-#if defined (TIM6)
- else if (TIMx == TIM6)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
- }
-#endif
-#if defined (TIM7)
- else if (TIMx == TIM7)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
- }
-#endif
-#if defined(TIM8)
- else if (TIMx == TIM8)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
- }
-#endif
-#if defined (TIM14)
- else if (TIMx == TIM14)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
- }
-#endif
-#if defined (TIM15)
- else if (TIMx == TIM15)
- {
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15);
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15);
- }
-#endif
-#if defined (TIM16)
- else if (TIMx == TIM16)
- {
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM16);
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM16);
- }
-#endif
-#if defined(TIM17)
- else if (TIMx == TIM17)
- {
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM17);
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM17);
- }
-#endif
- else
- {
- result = ERROR;
- }
-
- return result;
-}
-
-/**
- * @brief Set the fields of the time base unit configuration data structure
- * to their default values.
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
- * @retval None
- */
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
-{
- /* Set the default configuration */
- TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
- TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
- TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
- TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
-}
-
-/**
- * @brief Configure the TIMx time base unit.
- * @param TIMx Timer Instance
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
-{
- uint32_t tmpcr1 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
- assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
-
- tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
-
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- {
- /* Select the Counter Mode */
- MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- {
- /* Set the clock division */
- MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
- }
-
- /* Write to TIMx CR1 */
- LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
-
- /* Set the Autoreload value */
- LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
-
- /* Set the Prescaler value */
- LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- {
- /* Set the Repetition Counter value */
- LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter value (if applicable) immediately */
- LL_TIM_GenerateEvent_UPDATE(TIMx);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the TIMx output channel configuration data
- * structure to their default values.
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
- * @retval None
- */
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
- /* Set the default configuration */
- TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
- TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct->CompareValue = 0x00000000U;
- TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
- TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
- TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
- TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
-}
-
-/**
- * @brief Configure the TIMx output channel.
- * @param TIMx Timer Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx output channel is initialized
- * - ERROR: TIMx output channel is not initialized
- */
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
- ErrorStatus result = ERROR;
-
- switch (Channel)
- {
- case LL_TIM_CHANNEL_CH1:
- result = OC1Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH2:
- result = OC2Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH3:
- result = OC3Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH4:
- result = OC4Config(TIMx, TIM_OC_InitStruct);
- break;
- default:
- break;
- }
-
- return result;
-}
-
-/**
- * @brief Set the fields of the TIMx input channel configuration data
- * structure to their default values.
- * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
- * @retval None
- */
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
- TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
- TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
- * @brief Configure the TIMx input channel.
- * @param TIMx Timer Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx output channel is initialized
- * - ERROR: TIMx output channel is not initialized
- */
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
-{
- ErrorStatus result = ERROR;
-
- switch (Channel)
- {
- case LL_TIM_CHANNEL_CH1:
- result = IC1Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH2:
- result = IC2Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH3:
- result = IC3Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH4:
- result = IC4Config(TIMx, TIM_IC_InitStruct);
- break;
- default:
- break;
- }
-
- return result;
-}
-
-/**
- * @brief Fills each TIM_EncoderInitStruct field with its default value
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
- * @retval None
- */
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
- /* Set the default configuration */
- TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
- TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
- TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
- * @brief Configure the encoder interface of the timer instance.
- * @param TIMx Timer Instance
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
-
- /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
- TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Configure TI1 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
-
- /* Configure TI2 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
-
- /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
- tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
- tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
- tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Set encoder mode */
- LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the TIMx Hall sensor interface configuration data
- * structure to their default values.
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
- * @retval None
- */
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
- /* Set the default configuration */
- TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
- TIM_HallSensorInitStruct->CommutationDelay = 0U;
-}
-
-/**
- * @brief Configure the Hall sensor interface of the timer instance.
- * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
- * to the TI1 input channel
- * @note TIMx slave mode controller is configured in reset mode.
- Selected internal trigger is TI1F_ED.
- * @note Channel 1 is configured as input, IC1 is mapped on TRC.
- * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
- * between 2 changes on the inputs. It gives information about motor speed.
- * @note Channel 2 is configured in output PWM 2 mode.
- * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
- * @note OC2REF is selected as trigger output on TRGO.
- * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
- * when TIMx operates in Hall sensor interface mode.
- * @param TIMx Timer Instance
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
- uint32_t tmpcr2 = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpsmcr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
- assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
-
- /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
- TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
-
- /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
- tmpcr2 |= TIM_CR2_TI1S;
-
- /* OC2REF signal is used as trigger output (TRGO) */
- tmpcr2 |= LL_TIM_TRGO_OC2REF;
-
- /* Configure the slave mode controller */
- tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
- tmpsmcr |= LL_TIM_TS_TI1F_ED;
- tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
-
- /* Configure input channel 1 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
- tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
-
- /* Configure input channel 2 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
- tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
-
- /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
- tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
- tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx SMCR */
- LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- /* Write to TIMx CCR2 */
- LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the Break and Dead Time configuration data structure
- * to their default values.
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
- * @retval None
- */
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
- TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
- TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
- TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
- TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
- TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
- TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
-}
-
-/**
- * @brief Configure the Break and Dead Time feature of the timer instance.
- * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
- * depending on the LOCK configuration, it can be necessary to configure all of
- * them during the first write access to the TIMx_BDTR register.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @param TIMx Timer Instance
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Break and Dead Time is initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
- uint32_t tmpbdtr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
- assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
- assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
- assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
- assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
- assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
-
- /* Set TIMx_BDTR */
- LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
-
- return SUCCESS;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
- * @brief Private functions
- * @{
- */
-/**
- * @brief Configure the TIMx output channel 1.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
-
- /* Set the Output Compare Mode */
- MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 2.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 3.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR2 */
- LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 4.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR2 */
- LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-
-/**
- * @brief Configure the TIMx input channel 1.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR1,
- (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
- /* Select the Polarity and set the CC1E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC1P | TIM_CCER_CC1NP),
- (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 2.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR1,
- (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
- /* Select the Polarity and set the CC2E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC2P | TIM_CCER_CC2NP),
- ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 3.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR2,
- (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
- /* Select the Polarity and set the CC3E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC3P | TIM_CCER_CC3NP),
- ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 4.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR2,
- (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
- /* Select the Polarity and set the CC2E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC4P | TIM_CCER_CC4NP),
- ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
-
- return SUCCESS;
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_usart.c b/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_usart.c
deleted file mode 100644
index d671b29..0000000
--- a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_usart.c
+++ /dev/null
@@ -1,529 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_ll_usart.c
- * @author MCD Application Team
- * @brief USART LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_ll_usart.h"
-#include "stm32f0xx_ll_rcc.h"
-#include "stm32f0xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F0xx_LL_Driver
- * @{
- */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6) || defined (USART7) || defined (USART8)
-
-/** @addtogroup USART_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Macros
- * @{
- */
-
-/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
- * divided by the smallest oversampling used on the USART (i.e. 8) */
-#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U)
-
-/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
-#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
-
-/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
-#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-
-#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
- || ((__VALUE__) == LL_USART_DIRECTION_RX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
-
-#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
- || ((__VALUE__) == LL_USART_PARITY_EVEN) \
- || ((__VALUE__) == LL_USART_PARITY_ODD))
-
-#if defined(USART_7BITS_SUPPORT)
-#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
-#else
-#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
-#endif
-
-#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
- || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
-
-#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
- || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
-
-#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
- || ((__VALUE__) == LL_USART_PHASE_2EDGE))
-
-#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
- || ((__VALUE__) == LL_USART_POLARITY_HIGH))
-
-#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
- || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
-
-#if defined(USART_SMARTCARD_SUPPORT)
-#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_1) \
- || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_2))
-#else
-#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \
- || ((__VALUE__) == LL_USART_STOPBITS_2))
-#endif
-
-#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup USART_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize USART registers (Registers restored to their default values).
- * @param USARTx USART Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers are de-initialized
- * - ERROR: USART registers are not de-initialized
- */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(USARTx));
-
- if (USARTx == USART1)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1);
-
- /* Release reset of USART clock */
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1);
- }
-#if defined(USART2)
- else if (USARTx == USART2)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
-
- /* Release reset of USART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
- }
-#endif /* USART2 */
-#if defined(USART3)
- else if (USARTx == USART3)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
-
- /* Release reset of USART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
- }
-#endif /* USART3 */
-#if defined(USART4)
- else if (USARTx == USART4)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
-
- /* Release reset of USART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
- }
-#endif /* USART4 */
-#if defined(USART5)
- else if (USARTx == USART5)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
-
- /* Release reset of USART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
- }
-#endif /* USART5 */
-#if defined(USART6)
- else if (USARTx == USART6)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART6);
-
- /* Release reset of USART clock */
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART6);
- }
-#endif /* USART6 */
-#if defined(USART7)
- else if (USARTx == USART7)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART7);
-
- /* Release reset of USART clock */
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART7);
- }
-#endif /* USART7 */
-#if defined(USART8)
- else if (USARTx == USART8)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART8);
-
- /* Release reset of USART clock */
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART8);
- }
-#endif /* USART8 */
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Initialize USART registers according to the specified
- * parameters in USART_InitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
- * @param USARTx USART Instance
- * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
- * that contains the configuration information for the specified USART peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers are initialized according to USART_InitStruct content
- * - ERROR: Problem occurred during USART Registers initialization
- */
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
-{
- ErrorStatus status = ERROR;
- uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
-#if defined(STM32F030x8) || defined(STM32F030xC) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
- LL_RCC_ClocksTypeDef RCC_Clocks;
-#endif
-
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(USARTx));
- assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
- assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
- assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
- assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
- assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
- assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
- assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
-
- /* USART needs to be in disabled state, in order to be able to configure some bits in
- CRx registers */
- if (LL_USART_IsEnabled(USARTx) == 0U)
- {
- /*---------------------------- USART CR1 Configuration ---------------------
- * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
- * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
- * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
- * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
- * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
- */
- MODIFY_REG(USARTx->CR1,
- (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
- (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
- USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
-
- /*---------------------------- USART CR2 Configuration ---------------------
- * Configure USARTx CR2 (Stop bits) with parameters:
- * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
- * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
- */
- LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
-
- /*---------------------------- USART CR3 Configuration ---------------------
- * Configure USARTx CR3 (Hardware Flow Control) with parameters:
- * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
- */
- LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
-
- /*---------------------------- USART BRR Configuration ---------------------
- * Retrieve Clock frequency used for USART Peripheral
- */
- if (USARTx == USART1)
- {
- periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
- }
-#if defined(USART2)
- else if (USARTx == USART2)
- {
-#if defined (RCC_CFGR3_USART2SW)
- periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
-#else
- /* USART2 clock is PCLK */
- LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
- periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
- }
-#endif /* USART2 */
-#if defined(USART3)
- else if (USARTx == USART3)
- {
-#if defined (RCC_CFGR3_USART3SW)
- periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
-#else
- /* USART3 clock is PCLK */
- LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
- periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
- }
-#endif /* USART3 */
-#if defined(USART4)
- else if (USARTx == USART4)
- {
- /* USART4 clock is PCLK */
- LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
- periphclk = RCC_Clocks.PCLK1_Frequency;
- }
-#endif /* USART4 */
-#if defined(USART5)
- else if (USARTx == USART5)
- {
- /* USART5 clock is PCLK */
- LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
- periphclk = RCC_Clocks.PCLK1_Frequency;
- }
-#endif /* USART5 */
-#if defined(USART6)
- else if (USARTx == USART6)
- {
- /* USART6 clock is PCLK */
- LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
- periphclk = RCC_Clocks.PCLK1_Frequency;
- }
-#endif /* USART6 */
-#if defined(USART7)
- else if (USARTx == USART7)
- {
- /* USART7 clock is PCLK */
- LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
- periphclk = RCC_Clocks.PCLK1_Frequency;
- }
-#endif /* USART7 */
-#if defined(USART8)
- else if (USARTx == USART8)
- {
- /* USART8 clock is PCLK */
- LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
- periphclk = RCC_Clocks.PCLK1_Frequency;
- }
-#endif /* USART8 */
- else
- {
- /* Nothing to do, as error code is already assigned to ERROR value */
- }
-
- /* Configure the USART Baud Rate :
- - valid baud rate value (different from 0) is required
- - Peripheral clock as returned by RCC service, should be valid (different from 0).
- */
- if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
- && (USART_InitStruct->BaudRate != 0U))
- {
- status = SUCCESS;
- LL_USART_SetBaudRate(USARTx,
- periphclk,
- USART_InitStruct->OverSampling,
- USART_InitStruct->BaudRate);
-
- /* Check BRR is greater than or equal to 16d */
- assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
-
- /* Check BRR is greater than or equal to 16d */
- assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
- }
- }
- /* Endif (=> USART not in Disabled state => return ERROR) */
-
- return (status);
-}
-
-/**
- * @brief Set each @ref LL_USART_InitTypeDef field to default value.
- * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
-{
- /* Set USART_InitStruct fields to default values */
- USART_InitStruct->BaudRate = 9600U;
- USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
- USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
- USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
- USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
- USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
- USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
-}
-
-/**
- * @brief Initialize USART Clock related settings according to the
- * specified parameters in the USART_ClockInitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param USARTx USART Instance
- * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
- * that contains the Clock configuration information for the specified USART peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
- * - ERROR: Problem occurred during USART Registers initialization
- */
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check USART Instance and Clock signal output parameters */
- assert_param(IS_UART_INSTANCE(USARTx));
- assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
-
- /* USART needs to be in disabled state, in order to be able to configure some bits in
- CRx registers */
- if (LL_USART_IsEnabled(USARTx) == 0U)
- {
- /*---------------------------- USART CR2 Configuration -----------------------*/
- /* If Clock signal has to be output */
- if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
- {
- /* Deactivate Clock signal delivery :
- * - Disable Clock Output: USART_CR2_CLKEN cleared
- */
- LL_USART_DisableSCLKOutput(USARTx);
- }
- else
- {
- /* Ensure USART instance is USART capable */
- assert_param(IS_USART_INSTANCE(USARTx));
-
- /* Check clock related parameters */
- assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
- assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
- assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
-
- /*---------------------------- USART CR2 Configuration -----------------------
- * Configure USARTx CR2 (Clock signal related bits) with parameters:
- * - Enable Clock Output: USART_CR2_CLKEN set
- * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
- * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
- * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
- */
- MODIFY_REG(USARTx->CR2,
- USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
- USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
- USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
- }
- }
- /* Else (USART not in Disabled state => return ERROR */
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
- * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
- /* Set LL_USART_ClockInitStruct fields with default values */
- USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
- USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* USART1 || USART2|| USART3 || USART4 || USART5 || USART6 || USART7 || USART8 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_utils.c b/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_utils.c
deleted file mode 100644
index 836204a..0000000
--- a/firmware/S42BV1.0/Close_loop/src/Libraries/Stm32F0_lib/Src/stm32f0xx_ll_utils.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_ll_utils.c
- * @author MCD Application Team
- * @brief UTILS LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_ll_rcc.h"
-#include "stm32f0xx_ll_utils.h"
-#include "stm32f0xx_ll_system.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F0xx_LL_Driver
- * @{
- */
-
-/** @addtogroup UTILS_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Constants
- * @{
- */
-
-/* Defines used for PLL range */
-#define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */
-#define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */
-
-/* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
-#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */
-
-/* Defines used for FLASH latency according to SYSCLK Frequency */
-#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Macros
- * @{
- */
-#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
-
-#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_16))
-
-#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_16))
-
-#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
-
-#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((UTILS_PLL_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX))
-
-
-#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
- || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
-
-#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
- * @{
- */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-#if defined(FLASH_ACR_LATENCY)
-static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
-#endif /* FLASH_ACR_LATENCY */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-static ErrorStatus UTILS_PLL_IsBusy(void);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup UTILS_LL_EF_DELAY
- * @{
- */
-
-/**
- * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
- * @note When a RTOS is used, it is recommended to avoid changing the Systick
- * configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param HCLKFrequency HCLK frequency in Hz
- * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
- * @retval None
- */
-void LL_Init1msTick(uint32_t HCLKFrequency)
-{
- /* Use frequency provided in argument */
- LL_InitTick(HCLKFrequency, 1000U);
-}
-
-/**
- * @brief This function provides accurate delay (in milliseconds) based
- * on SysTick counter flag
- * @note When a RTOS is used, it is recommended to avoid using blocking delay
- * and use rather osDelay service.
- * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
- * will configure Systick to 1ms
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-void LL_mDelay(uint32_t Delay)
-{
- __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
- /* Add this code to indicate that local variable is not used */
- ((void)tmp);
-
- /* Add a period to guaranty minimum wait */
- if (Delay < LL_MAX_DELAY)
- {
- Delay++;
- }
-
- while (Delay)
- {
- if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
- {
- Delay--;
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @addtogroup UTILS_EF_SYSTEM
- * @brief System Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### System Configuration functions #####
- ===============================================================================
- [..]
- System, AHB and APB buses clocks configuration
-
- (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 48000000 Hz.
- @endverbatim
- @internal
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
- (++) +-----------------------------------------------+
- (++) | Latency | SYSCLK clock frequency (MHz) |
- (++) |---------------|-------------------------------|
- (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
- (++) |---------------|-------------------------------|
- (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
- (++) +-----------------------------------------------+
- @endinternal
- * @{
- */
-
-/**
- * @brief This function sets directly SystemCoreClock CMSIS variable.
- * @note Variable can be calculated also through SystemCoreClockUpdate function.
- * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
- * @retval None
- */
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
-{
- /* HCLK clock frequency */
- SystemCoreClock = HCLKFrequency;
-}
-
-/**
- * @brief This function configures system clock with HSI as clock source of the PLL
- * @note The application need to ensure that PLL is disabled.
- * @note Function is based on the following formula:
- * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
- * - PREDIV: Set to 2 for few devices
- * - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * be in the range 16-48MHz
- * @note FLASH latency can be modified through this function.
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Max frequency configuration done
- * - ERROR: Max frequency configuration not done
- */
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t pllfreq = 0U;
-
- /* Check if one of the PLL is enabled */
- if (UTILS_PLL_IsBusy() == SUCCESS)
- {
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- /* Check PREDIV value */
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
-#else
- /* Force PREDIV value to 2 */
- UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
- /* Calculate the new PLL output frequency */
- pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
-
- /* Enable HSI if not enabled */
- if (LL_RCC_HSI_IsReady() != 1U)
- {
- LL_RCC_HSI_Enable();
- while (LL_RCC_HSI_IsReady() != 1U)
- {
- /* Wait for HSI ready */
- }
- }
-
- /* Configure PLL */
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-#else
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
-
- /* Enable PLL and switch system clock to PLL */
- status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- }
- else
- {
- /* Current PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-#if defined(RCC_CFGR_SW_HSI48)
-/**
- * @brief This function configures system clock with HSI48 as clock source of the PLL
- * @note The application need to ensure that PLL is disabled.
- * @note Function is based on the following formula:
- * - PLL output frequency = ((HSI48 frequency / PREDIV) * PLLMUL)
- * - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * be in the range 16-48MHz
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Max frequency configuration done
- * - ERROR: Max frequency configuration not done
- */
-ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t pllfreq = 0U;
-
- /* Check if one of the PLL is enabled */
- if (UTILS_PLL_IsBusy() == SUCCESS)
- {
- /* Check PREDIV value */
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
-
- /* Calculate the new PLL output frequency */
- pllfreq = UTILS_GetPLLOutputFrequency(HSI48_VALUE, UTILS_PLLInitStruct);
-
- /* Enable HSI48 if not enabled */
- if (LL_RCC_HSI48_IsReady() != 1U)
- {
- LL_RCC_HSI48_Enable();
- while (LL_RCC_HSI48_IsReady() != 1U)
- {
- /* Wait for HSI48 ready */
- }
- }
-
- /* Configure PLL */
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-
- /* Enable PLL and switch system clock to PLL */
- status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- }
- else
- {
- /* Current PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-#endif /*RCC_CFGR_SW_HSI48*/
-/**
- * @brief This function configures system clock with HSE as clock source of the PLL
- * @note The application need to ensure that PLL is disabled.
- * @note Function is based on the following formula:
- * - PLL output frequency = ((HSE frequency / PREDIV) * PLLMUL)
- * - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * be in the range 16-48MHz
- * @note FLASH latency can be modified through this function.
- * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000
- * @param HSEBypass This parameter can be one of the following values:
- * @arg @ref LL_UTILS_HSEBYPASS_ON
- * @arg @ref LL_UTILS_HSEBYPASS_OFF
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Max frequency configuration done
- * - ERROR: Max frequency configuration not done
- */
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t pllfreq = 0U;
-
- /* Check the parameters */
- assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
- assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
-
- /* Check if one of the PLL is enabled */
- if (UTILS_PLL_IsBusy() == SUCCESS)
- {
- /* Check PREDIV value */
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
-#else
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
-
- /* Calculate the new PLL output frequency */
- pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
-
- /* Enable HSE if not enabled */
- if (LL_RCC_HSE_IsReady() != 1U)
- {
- /* Check if need to enable HSE bypass feature or not */
- if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
- {
- LL_RCC_HSE_EnableBypass();
- }
- else
- {
- LL_RCC_HSE_DisableBypass();
- }
-
- /* Enable HSE */
- LL_RCC_HSE_Enable();
- while (LL_RCC_HSE_IsReady() != 1U)
- {
- /* Wait for HSE ready */
- }
- }
-
- /* Configure PLL */
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-#else
- LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
-
- /* Enable PLL and switch system clock to PLL */
- status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- }
- else
- {
- /* Current PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup UTILS_LL_Private_Functions
- * @{
- */
-/**
- * @brief Update number of Flash wait states in line with new frequency and current
- voltage range.
- * @param Frequency SYSCLK frequency
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Latency has been modified
- * - ERROR: Latency cannot be modified
- */
-#if defined(FLASH_ACR_LATENCY)
-static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
-{
- ErrorStatus status = SUCCESS;
-
- uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
-
- /* Frequency cannot be equal to 0 */
- if (Frequency == 0U)
- {
- status = ERROR;
- }
- else
- {
- if (Frequency > UTILS_LATENCY1_FREQ)
- {
- /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
-
- LL_FLASH_SetLatency(latency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if (LL_FLASH_GetLatency() != latency)
- {
- status = ERROR;
- }
- }
- return status;
-}
-#endif /* FLASH_ACR_LATENCY */
-
-/**
- * @brief Function to check that PLL can be modified
- * @param PLL_InputFrequency PLL input frequency (in Hz)
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @retval PLL output frequency (in Hz)
- */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
-{
- uint32_t pllfreq = 0U;
-
- /* Check the parameters */
- assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
-
- /* Check different PLL parameters according to RM */
- /* The application software must set correctly the PLL multiplication factor to
- be in the range 16-48MHz */
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-#else
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
- assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
-
- return pllfreq;
-}
-
-/**
- * @brief Function to check that PLL can be modified
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: PLL modification can be done
- * - ERROR: PLL is busy
- */
-static ErrorStatus UTILS_PLL_IsBusy(void)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check if PLL is busy*/
- if (LL_RCC_PLL_IsReady() != 0U)
- {
- /* PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Function to enable PLL and switch system clock to PLL
- * @param SYSCLK_Frequency SYSCLK frequency
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: No problem to switch system to PLL
- * - ERROR: Problem to switch system to PLL
- */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t sysclk_frequency_current = 0U;
-
- assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
- assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
-
- /* Calculate current SYSCLK frequency */
- sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]);
-
- /* Increasing the number of wait states because of higher CPU frequency */
- if (sysclk_frequency_current < SYSCLK_Frequency)
- {
- /* Set FLASH latency to highest latency */
- status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- }
-
- /* Update system clock configuration */
- if (status == SUCCESS)
- {
- /* Enable PLL */
- LL_RCC_PLL_Enable();
- while (LL_RCC_PLL_IsReady() != 1U)
- {
- /* Wait for PLL ready */
- }
-
- /* Sysclk activation on the main PLL */
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
- LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- {
- /* Wait for system clock switch to PLL */
- }
-
- /* Set APB1 & APB2 prescaler*/
- LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if (sysclk_frequency_current > SYSCLK_Frequency)
- {
- /* Set FLASH latency to lowest latency */
- status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- }
-
- /* Update SystemCoreClock variable */
- if (status == SUCCESS)
- {
- LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/cmsis/core_cmFunc.h b/firmware/S42BV1.0/Close_loop/src/Libraries/cmsis/core_cmFunc.h
new file mode 100644
index 0000000..652a48a
--- /dev/null
+++ b/firmware/S42BV1.0/Close_loop/src/Libraries/cmsis/core_cmFunc.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/firmware/S42BV1.0/Close_loop/src/Libraries/cmsis/core_cmInstr.h b/firmware/S42BV1.0/Close_loop/src/Libraries/cmsis/core_cmInstr.h
new file mode 100644
index 0000000..f474b0e
--- /dev/null
+++ b/firmware/S42BV1.0/Close_loop/src/Libraries/cmsis/core_cmInstr.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/firmware/S42BV1.0/buildroot/boards/STM32F030C8.json b/firmware/S42BV1.0/buildroot/boards/STM32F030C8.json
index ae4fd63..43ec2a9 100644
--- a/firmware/S42BV1.0/buildroot/boards/STM32F030C8.json
+++ b/firmware/S42BV1.0/buildroot/boards/STM32F030C8.json
@@ -14,8 +14,9 @@
"0x0004"
]
],
- "ldscript": "STM32F030C8_FLASH.ld",
+ "ldscript": "buildroot/ldscripts/STM32F030C8_FLASH.ld",
"mcu": "stm32f030c8t6",
+ "product_line": "STM32F030X8",
"variant": "stm32f0"
},
"debug": {
diff --git a/firmware/S42BV1.0/platformio.ini b/firmware/S42BV1.0/platformio.ini
index 354842e..7832c8a 100644
--- a/firmware/S42BV1.0/platformio.ini
+++ b/firmware/S42BV1.0/platformio.ini
@@ -10,12 +10,12 @@
[platformio]
-src_dir = close_loop
-build_dir = .pioenvs
-lib_dir = .piolib
-libdeps_dir = .piolibdeps
-boards_dir = buildroot/boards
-env_default = BIGTREE_S42B_V1_0
+src_dir = close_loop
+build_dir = .pioenvs
+lib_dir = .piolib
+libdeps_dir = .piolibdeps
+boards_dir = buildroot/boards
+default_envs = BIGTREE_S42B_V1_0
[common]
#extra_scripts = pre:buildroot/scripts/custom_filename.py
@@ -27,7 +27,6 @@ build_flags = -fmax-errors=5
-D USE_FULL_LL_DRIVER
#-D __STATIC_INLINE=
-I close_loop/src/Libraries/cmsis
- -I close_loop/src/Libraries/Stm32f0_lib/inc
-I close_loop/src/User
-I close_loop/src/Hardware
@@ -42,6 +41,7 @@ platform = ststm32
framework = stm32cube
board = STM32F030C8
upload_protocol = stlink
+; upload_port = /dev/ttyACM0
#extra_scripts = ${common.extra_scripts}
build_flags = ${common.build_flags}