Invalid bitstream when using OSS CAD Suite Yosys with GHDL synthesis

[swittlich]

Title

Invalid bitstream when using OSS CAD Suite Yosys with GHDL synthesis

Description

When using the OSS CAD Suite Yosys (with GHDL plugin) for the synthesis flow, the following issue occurs:

• Synthesis from VHDL to Verilog via GHDL works.
• Subsequent synthesis via Yosys runs without errors.
• A bitstream is generated, but this bitstream cannot be flashed onto the FPGA.

In contrast, when using the Cologne Chip provided Yosys binaries, the same flow works correctly and the bitstream can be flashed.

Expected Behavior

The generated bitstream should be valid and flashable onto the FPGA device when using OSS CAD Suite Yosys with GHDL synthesis.

Current Behavior

• Flow executes without errors.
• Bitstream is generated.
• Flashing fails due to an invalid bitstream.

Additional Information

• Wrapping around the tools itself works as expected.
• The problem seems specific to the OSS CAD Suite version of Yosys.
• A follow-up issue will address possible root causes.

Steps to Reproduce

1. Use OSS CAD Suite Yosys with the OneWare-GHDL plugin.
2. Run synthesis from VHDL to Verilog using GHDL.
3. Run synthesis via Yosys.
4. Generate the bitstream.
5. Attempt to flash the bitstream onto the FPGA → flashing fails.

Environment

• Yosys binaries: OSS CAD Suite (failing)
• Yosys binaries: Cologne Chip release (working)
• Flow: ghdl → yosys → bitstream generation → flash