cannot instantiate CC_PLL primitive from gatemate fpga with yosys source: OSSCAD Suite

[isoeth]

OneWare version: 0.21.11.0
Extension version: git pull devel Date: Mon Sep 1 17:33:31 2025 +0200
Project: clock_pmod.zip

Output:
[clock_pmod]: ghdl -i --workdir=/home/ismail/OneWareStudio/Projects/clock_pmod/build -P/home/ismail/OneWareStudio/Projects/clock_pmod/build clock_pmod.vhd clock_pmod_tb.vhd
[clock_pmod]: ghdl -m --workdir=/home/ismail/OneWareStudio/Projects/clock_pmod/build -P/home/ismail/OneWareStudio/Projects/clock_pmod/build clock_pmod
clock_pmod.vhd:38:11:error: no declaration for "cc_pll"
pll : CC_PLL
^
[clock_pmod]: ghdl -e --workdir=/home/ismail/OneWareStudio/Projects/clock_pmod/build -P/home/ismail/OneWareStudio/Projects/clock_pmod/build clock_pmod
command line:1:1:error: unit entity "clock_pmod" has not been analyzed
[clock_pmod]: ghdl --synth --std=93c --workdir=/home/ismail/OneWareStudio/Projects/clock_pmod/build -P/home/ismail/OneWareStudio/Projects/clock_pmod/build --out=verilog -o=build/clock_pmod.v clock_pmod
command line:1:1:error: unit entity "clock_pmod" has not been analyzed
VHDL Synthesis (external GHDL → Verilog)...