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Driver infrastructure: typed register-bank abstraction for memory-mapped devices #248

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Most hardware drivers in the tree expose a fixed layout of memory-mapped registers grouped into one or more "banks" (MAC / MTL / DMA / PHY for Ethernet, control / queue / interrupt for storage, etc.). Today every driver invents its own way of expressing that layout, ranging from free-standing const NAME: usize = 0xNNN; offsets that are mixed by hand with a base pointer, to ad-hoc uses of mmio_struct!. The result:

  • Offsets from different banks can be combined with the wrong base pointer without any compile-time complaint.
  • Register layouts are not self-documenting; reviewers have to correlate constants with vendor datasheets manually.
  • Each new driver re-derives the same boilerplate.

We want a shared abstraction — a "device type" wrapper that bundles a base address with typed accessors for each register bank, similar in spirit to MMIO<T> (now in arch/src/mmio.rs) and the existing mmio_struct! macro (kernel/src/klibc/mmio.rs:4), but expressed at the bank / device level rather than per-field. The exact shape is open: it could be an extension to mmio_struct!, a new macro, or a generic struct.

Known first consumer: the DWMAC Ethernet driver (kernel/src/drivers/dwmac/mod.rs) currently declares ~30+ register offsets as bare usize constants at the top of the file. Once the abstraction lands, DWMAC should be the first driver migrated to it as a worked example.

Other likely consumers down the line: PLIC, UART variants, future VirtIO additions, NVMe / xHCI when they appear.


Created by Claude Code

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