Any driver that hands a memory region to a DMA engine has to keep that region coherent with the CPU cache: flush dirty cache lines before the device reads the buffer, invalidate before the CPU reads it back. Today every such driver has to reach for arch::cache::flush_range / equivalent by hand, with all the ordering and "did I forget a flush" footguns that implies.
Introduce a shared NonCachable<T> wrapper analogous to MMIO<T> (now in arch/src/mmio.rs) that encapsulates cache-coherency handling for memory shared with a DMA engine: flush on write, invalidate on read, prevent accidental cached access to the inner value, and document the ownership model so DMA descriptor rings, packet buffers, and similar structures can be expressed without per-driver bookkeeping.
Known first consumer: the DWMAC Ethernet driver (kernel/src/drivers/dwmac/mod.rs:556-567) currently calls arch::cache::flush_range directly on its RX and TX descriptor rings during init. Once NonCachable<T> exists, DWMAC should be the first driver ported to it.
Other likely consumers: any future VirtIO ring on a non-coherent SoC, NVMe / SD / xHCI drivers, framebuffers shared with GPU/DMA.
Created by Claude Code
Any driver that hands a memory region to a DMA engine has to keep that region coherent with the CPU cache: flush dirty cache lines before the device reads the buffer, invalidate before the CPU reads it back. Today every such driver has to reach for
arch::cache::flush_range/ equivalent by hand, with all the ordering and "did I forget a flush" footguns that implies.Introduce a shared
NonCachable<T>wrapper analogous toMMIO<T>(now inarch/src/mmio.rs) that encapsulates cache-coherency handling for memory shared with a DMA engine: flush on write, invalidate on read, prevent accidental cached access to the inner value, and document the ownership model so DMA descriptor rings, packet buffers, and similar structures can be expressed without per-driver bookkeeping.Known first consumer: the DWMAC Ethernet driver (
kernel/src/drivers/dwmac/mod.rs:556-567) currently callsarch::cache::flush_rangedirectly on its RX and TX descriptor rings during init. OnceNonCachable<T>exists, DWMAC should be the first driver ported to it.Other likely consumers: any future VirtIO ring on a non-coherent SoC, NVMe / SD / xHCI drivers, framebuffers shared with GPU/DMA.
Created by Claude Code