HDL backend binary models have unnecessary inputs

[thesps]

Binary classifier and regression models synthesized with the HLS backend get an extra input associated with the second class that is unused. For example, running the examples/sklearn_to_hls.py example project, the top level VHDL has ports:

entity my_prj is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    x_0 : IN STD_LOGIC_VECTOR (17 downto 0);
    x_1 : IN STD_LOGIC_VECTOR (17 downto 0);
    x_2 : IN STD_LOGIC_VECTOR (17 downto 0);
    x_3 : IN STD_LOGIC_VECTOR (17 downto 0);
    x_4 : IN STD_LOGIC_VECTOR (17 downto 0);
    x_5 : IN STD_LOGIC_VECTOR (17 downto 0);
    x_6 : IN STD_LOGIC_VECTOR (17 downto 0);
    x_7 : IN STD_LOGIC_VECTOR (17 downto 0);
    x_8 : IN STD_LOGIC_VECTOR (17 downto 0);
    x_9 : IN STD_LOGIC_VECTOR (17 downto 0);
    score_0 : OUT STD_LOGIC_VECTOR (17 downto 0);
    score_0_ap_vld : OUT STD_LOGIC;
    score_1 : IN STD_LOGIC_VECTOR (17 downto 0) );
end;

score_1 is an input, but it's not used in the rest of the VHDL. This is probably because parameters.h has:

static const int n_classes = 2;
typedef score_t score_arr_t[n_classes];

so the array on the interface has two elements, one of which is never written. This could probably be replaced with

typedef score_t score_arr_t[fn_classes(n_classes)];