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enhancementNew feature or requestNew feature or request
Description
Problem
Long compilations and simulations are completely silent. Users can't tell if the tool is hung or making progress, especially for large UVM designs where initialization alone takes 4+ seconds.
Proposed Solution
Add a --verbose or --progress flag that prints pipeline stage transitions:
[crun] parsing sources... (3 files)
[crun] lowering to MLIR... done (1.2s)
[crun] running MooreToCore passes... done (0.8s)
[crun] initializing simulation... done (4.3s)
[crun] simulating...
Implementation
The infrastructure already exists:
circt-sim.cpphasreportStage()(lines 3130-3144) which usesstd::chrono::steady_clockand prints[circt-sim] [stageName] X.XXXs (total: Y.YYYs)crun.cpphas the pipeline stages clearly separated: parse → MooreToCore → simulation init → run
Changes needed:
- Add
--verbosecl::opt to crun - Wire
reportStage()calls around each pipeline stage in crun'smain() - Print to stderr so it doesn't interfere with simulation output
- Consider a compact single-line progress mode for TTY (overwrite with
\r)
Nice-to-have
- Show signal/process counts after init:
[crun] initialized: 1,234 signals, 56 processes - Show simulation progress:
[crun] simulated 100ns (wall: 2.3s, 43 ns/s) - Quiet mode (default): no progress, only errors
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enhancementNew feature or requestNew feature or request